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IB/mlx5: Enable ECN capable bits for UD RoCE v2 QPs
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
37e92a9d 150 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 204 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
205 MLX5_CMD_OP_QUERY_RQ = 0x90b,
206 MLX5_CMD_OP_CREATE_RMP = 0x90c,
207 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
208 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
209 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 210 MLX5_CMD_OP_CREATE_TIS = 0x912,
211 MLX5_CMD_OP_MODIFY_TIS = 0x913,
212 MLX5_CMD_OP_DESTROY_TIS = 0x914,
213 MLX5_CMD_OP_QUERY_TIS = 0x915,
214 MLX5_CMD_OP_CREATE_RQT = 0x916,
215 MLX5_CMD_OP_MODIFY_RQT = 0x917,
216 MLX5_CMD_OP_DESTROY_RQT = 0x918,
217 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 241 MLX5_CMD_OP_MAX
e281682b
SM		 242};
243
244struct mlx5_ifc_flow_table_fields_supported_bits {
245 u8 outer_dmac[0x1];
246 u8 outer_smac[0x1];
247 u8 outer_ether_type[0x1];
19cc7524 248 u8 outer_ip_version[0x1];
e281682b
SM		 249 u8 outer_first_prio[0x1];
250 u8 outer_first_cfi[0x1];
251 u8 outer_first_vid[0x1];
a8ade55f 252 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 253 u8 outer_second_prio[0x1];
254 u8 outer_second_cfi[0x1];
255 u8 outer_second_vid[0x1];
b4ff3a36 256 u8 reserved_at_b[0x1];
e281682b
SM		 257 u8 outer_sip[0x1];
258 u8 outer_dip[0x1];
259 u8 outer_frag[0x1];
260 u8 outer_ip_protocol[0x1];
261 u8 outer_ip_ecn[0x1];
262 u8 outer_ip_dscp[0x1];
263 u8 outer_udp_sport[0x1];
264 u8 outer_udp_dport[0x1];
265 u8 outer_tcp_sport[0x1];
266 u8 outer_tcp_dport[0x1];
267 u8 outer_tcp_flags[0x1];
268 u8 outer_gre_protocol[0x1];
269 u8 outer_gre_key[0x1];
270 u8 outer_vxlan_vni[0x1];
b4ff3a36 271 u8 reserved_at_1a[0x5];
e281682b
SM		 272 u8 source_eswitch_port[0x1];
273
274 u8 inner_dmac[0x1];
275 u8 inner_smac[0x1];
276 u8 inner_ether_type[0x1];
19cc7524 277 u8 inner_ip_version[0x1];
e281682b
SM		 278 u8 inner_first_prio[0x1];
279 u8 inner_first_cfi[0x1];
280 u8 inner_first_vid[0x1];
b4ff3a36 281 u8 reserved_at_27[0x1];
e281682b
SM		 282 u8 inner_second_prio[0x1];
283 u8 inner_second_cfi[0x1];
284 u8 inner_second_vid[0x1];
b4ff3a36 285 u8 reserved_at_2b[0x1];
e281682b
SM		 286 u8 inner_sip[0x1];
287 u8 inner_dip[0x1];
288 u8 inner_frag[0x1];
289 u8 inner_ip_protocol[0x1];
290 u8 inner_ip_ecn[0x1];
291 u8 inner_ip_dscp[0x1];
292 u8 inner_udp_sport[0x1];
293 u8 inner_udp_dport[0x1];
294 u8 inner_tcp_sport[0x1];
295 u8 inner_tcp_dport[0x1];
296 u8 inner_tcp_flags[0x1];
b4ff3a36 297 u8 reserved_at_37[0x9];
3346c487
BP		 298 u8 reserved_at_40[0x17];
299 u8 outer_esp_spi[0x1];
300 u8 reserved_at_58[0x2];
a550ddfc 301 u8 bth_dst_qp[0x1];
e281682b 302
a550ddfc 303 u8 reserved_at_5b[0x25];
e281682b
SM		 304};
305
306struct mlx5_ifc_flow_table_prop_layout_bits {
307 u8 ft_support[0x1];
9dc0b289
AV		 308 u8 reserved_at_1[0x1];
309 u8 flow_counter[0x1];
26a81453 310 u8 flow_modify_en[0x1];
2cc43b49 311 u8 modify_root[0x1];
34a40e68
MG		 312 u8 identified_miss_table_mode[0x1];
313 u8 flow_table_modify[0x1];
7adbde20
HHZ		 314 u8 encap[0x1];
315 u8 decap[0x1];
316 u8 reserved_at_9[0x17];
e281682b 317
b4ff3a36 318 u8 reserved_at_20[0x2];
e281682b 319 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 320 u8 log_max_modify_header_context[0x8];
321 u8 max_modify_header_actions[0x8];
e281682b
SM		 322 u8 max_ft_level[0x8];
323
b4ff3a36 324 u8 reserved_at_40[0x20];
e281682b 325
b4ff3a36 326 u8 reserved_at_60[0x18];
e281682b
SM		 327 u8 log_max_ft_num[0x8];
328
b4ff3a36 329 u8 reserved_at_80[0x18];
e281682b
SM		 330 u8 log_max_destination[0x8];
331
16f1c5bb
RS		 332 u8 log_max_flow_counter[0x8];
333 u8 reserved_at_a8[0x10];
e281682b
SM		 334 u8 log_max_flow[0x8];
335
b4ff3a36 336 u8 reserved_at_c0[0x40];
e281682b
SM		 337
338 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
339
340 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
341};
342
343struct mlx5_ifc_odp_per_transport_service_cap_bits {
344 u8 send[0x1];
345 u8 receive[0x1];
346 u8 write[0x1];
347 u8 read[0x1];
17d2f88f 348 u8 atomic[0x1];
e281682b 349 u8 srq_receive[0x1];
b4ff3a36 350 u8 reserved_at_6[0x1a];
e281682b
SM		 351};
352
b4d1f032 353struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 354 u8 reserved_at_0[0x60];
b4d1f032
MG		 355
356 u8 ipv4[0x20];
357};
358
359struct mlx5_ifc_ipv6_layout_bits {
360 u8 ipv6[16][0x8];
361};
362
363union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
364 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
365 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 366 u8 reserved_at_0[0x80];
b4d1f032
MG		 367};
368
e281682b
SM		 369struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
370 u8 smac_47_16[0x20];
371
372 u8 smac_15_0[0x10];
373 u8 ethertype[0x10];
374
375 u8 dmac_47_16[0x20];
376
377 u8 dmac_15_0[0x10];
378 u8 first_prio[0x3];
379 u8 first_cfi[0x1];
380 u8 first_vid[0xc];
381
382 u8 ip_protocol[0x8];
383 u8 ip_dscp[0x6];
384 u8 ip_ecn[0x2];
10543365
MHY		 385 u8 cvlan_tag[0x1];
386 u8 svlan_tag[0x1];
e281682b 387 u8 frag[0x1];
19cc7524 388 u8 ip_version[0x4];
e281682b
SM		 389 u8 tcp_flags[0x9];
390
391 u8 tcp_sport[0x10];
392 u8 tcp_dport[0x10];
393
a8ade55f
OG		 394 u8 reserved_at_c0[0x18];
395 u8 ttl_hoplimit[0x8];
e281682b
SM		 396
397 u8 udp_sport[0x10];
398 u8 udp_dport[0x10];
399
b4d1f032 400 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 401
b4d1f032 402 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 403};
404
405struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 406 u8 reserved_at_0[0x8];
407 u8 source_sqn[0x18];
e281682b 408
b4ff3a36 409 u8 reserved_at_20[0x10];
e281682b
SM		 410 u8 source_port[0x10];
411
412 u8 outer_second_prio[0x3];
413 u8 outer_second_cfi[0x1];
414 u8 outer_second_vid[0xc];
415 u8 inner_second_prio[0x3];
416 u8 inner_second_cfi[0x1];
417 u8 inner_second_vid[0xc];
418
10543365
MHY		 419 u8 outer_second_cvlan_tag[0x1];
420 u8 inner_second_cvlan_tag[0x1];
421 u8 outer_second_svlan_tag[0x1];
422 u8 inner_second_svlan_tag[0x1];
423 u8 reserved_at_64[0xc];
e281682b
SM		 424 u8 gre_protocol[0x10];
425
426 u8 gre_key_h[0x18];
427 u8 gre_key_l[0x8];
428
429 u8 vxlan_vni[0x18];
b4ff3a36 430 u8 reserved_at_b8[0x8];
e281682b 431
b4ff3a36 432 u8 reserved_at_c0[0x20];
e281682b 433
b4ff3a36 434 u8 reserved_at_e0[0xc];
e281682b
SM		 435 u8 outer_ipv6_flow_label[0x14];
436
b4ff3a36 437 u8 reserved_at_100[0xc];
e281682b
SM		 438 u8 inner_ipv6_flow_label[0x14];
439
a550ddfc
YH		 440 u8 reserved_at_120[0x28];
441 u8 bth_dst_qp[0x18];
3346c487
BP		 442 u8 reserved_at_160[0x20];
443 u8 outer_esp_spi[0x20];
444 u8 reserved_at_1a0[0x60];
e281682b
SM		 445};
446
447struct mlx5_ifc_cmd_pas_bits {
448 u8 pa_h[0x20];
449
450 u8 pa_l[0x14];
b4ff3a36 451 u8 reserved_at_34[0xc];
e281682b
SM		 452};
453
454struct mlx5_ifc_uint64_bits {
455 u8 hi[0x20];
456
457 u8 lo[0x20];
458};
459
460enum {
461 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
462 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
463 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
464 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
465 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
466 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
467 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
468 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
469 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
470 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
471};
472
473struct mlx5_ifc_ads_bits {
474 u8 fl[0x1];
475 u8 free_ar[0x1];
b4ff3a36 476 u8 reserved_at_2[0xe];
e281682b
SM		 477 u8 pkey_index[0x10];
478
b4ff3a36 479 u8 reserved_at_20[0x8];
e281682b
SM		 480 u8 grh[0x1];
481 u8 mlid[0x7];
482 u8 rlid[0x10];
483
484 u8 ack_timeout[0x5];
b4ff3a36 485 u8 reserved_at_45[0x3];
e281682b 486 u8 src_addr_index[0x8];
b4ff3a36 487 u8 reserved_at_50[0x4];
e281682b
SM		 488 u8 stat_rate[0x4];
489 u8 hop_limit[0x8];
490
b4ff3a36 491 u8 reserved_at_60[0x4];
e281682b
SM		 492 u8 tclass[0x8];
493 u8 flow_label[0x14];
494
495 u8 rgid_rip[16][0x8];
496
b4ff3a36 497 u8 reserved_at_100[0x4];
e281682b
SM		 498 u8 f_dscp[0x1];
499 u8 f_ecn[0x1];
b4ff3a36 500 u8 reserved_at_106[0x1];
e281682b
SM		 501 u8 f_eth_prio[0x1];
502 u8 ecn[0x2];
503 u8 dscp[0x6];
504 u8 udp_sport[0x10];
505
506 u8 dei_cfi[0x1];
507 u8 eth_prio[0x3];
508 u8 sl[0x4];
32f69e4b 509 u8 vhca_port_num[0x8];
e281682b
SM		 510 u8 rmac_47_32[0x10];
511
512 u8 rmac_31_0[0x20];
513};
514
515struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 516 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 517 u8 nic_rx_multi_path_tirs_fts[0x1];
518 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
519 u8 reserved_at_3[0x1fd];
e281682b
SM		 520
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
522
b4ff3a36 523 u8 reserved_at_400[0x200];
e281682b
SM		 524
525 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
528
b4ff3a36 529 u8 reserved_at_a00[0x200];
e281682b
SM		 530
531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
532
b4ff3a36 533 u8 reserved_at_e00[0x7200];
e281682b
SM		 534};
535
495716b1 536struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 537 u8 reserved_at_0[0x200];
495716b1
SM		 538
539 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
540
541 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
542
543 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
544
b4ff3a36 545 u8 reserved_at_800[0x7800];
495716b1
SM		 546};
547
d6666753
SM		 548struct mlx5_ifc_e_switch_cap_bits {
549 u8 vport_svlan_strip[0x1];
550 u8 vport_cvlan_strip[0x1];
551 u8 vport_svlan_insert[0x1];
552 u8 vport_cvlan_insert_if_not_exist[0x1];
553 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 554 u8 reserved_at_5[0x19];
555 u8 nic_vport_node_guid_modify[0x1];
556 u8 nic_vport_port_guid_modify[0x1];
d6666753 557
7adbde20
HHZ		 558 u8 vxlan_encap_decap[0x1];
559 u8 nvgre_encap_decap[0x1];
560 u8 reserved_at_22[0x9];
561 u8 log_max_encap_headers[0x5];
562 u8 reserved_2b[0x6];
563 u8 max_encap_header_size[0xa];
564
565 u8 reserved_40[0x7c0];
566
d6666753
SM		 567};
568
7486216b
SM		 569struct mlx5_ifc_qos_cap_bits {
570 u8 packet_pacing[0x1];
813f8540 571 u8 esw_scheduling[0x1];
c9497c98
MHY		 572 u8 esw_bw_share[0x1];
573 u8 esw_rate_limit[0x1];
05d3ac97
BW		 574 u8 reserved_at_4[0x1];
575 u8 packet_pacing_burst_bound[0x1];
576 u8 packet_pacing_typical_size[0x1];
577 u8 reserved_at_7[0x19];
813f8540
MHY		 578
579 u8 reserved_at_20[0x20];
580
7486216b 581 u8 packet_pacing_max_rate[0x20];
813f8540 582
7486216b 583 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 584
585 u8 reserved_at_80[0x10];
7486216b 586 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 587
588 u8 esw_element_type[0x10];
589 u8 esw_tsar_type[0x10];
590
591 u8 reserved_at_c0[0x10];
592 u8 max_qos_para_vport[0x10];
593
594 u8 max_tsar_bw_share[0x20];
595
596 u8 reserved_at_100[0x700];
7486216b
SM		 597};
598
e281682b
SM		 599struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
600 u8 csum_cap[0x1];
601 u8 vlan_cap[0x1];
602 u8 lro_cap[0x1];
603 u8 lro_psh_flag[0x1];
604 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 605 u8 reserved_at_5[0x2];
606 u8 wqe_vlan_insert[0x1];
66189961 607 u8 self_lb_en_modifiable[0x1];
b4ff3a36 608 u8 reserved_at_9[0x2];
e281682b 609 u8 max_lso_cap[0x5];
c226dc22 610 u8 multi_pkt_send_wqe[0x2];
cff92d7c 611 u8 wqe_inline_mode[0x2];
e281682b 612 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 613 u8 reg_umr_sq[0x1];
614 u8 scatter_fcs[0x1];
050da902 615 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 616 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 617 u8 reserved_at_1c[0x2];
27299841 618 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 619 u8 tunnel_stateless_vxlan[0x1];
620
547eede0
IT		 621 u8 swp[0x1];
622 u8 swp_csum[0x1];
623 u8 swp_lso[0x1];
4d350f1f
MG		 624 u8 reserved_at_23[0x1b];
625 u8 max_geneve_opt_len[0x1];
626 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 627
b4ff3a36 628 u8 reserved_at_40[0x10];
e281682b
SM		 629 u8 lro_min_mss_size[0x10];
630
b4ff3a36 631 u8 reserved_at_60[0x120];
e281682b
SM		 632
633 u8 lro_timer_supported_periods[4][0x20];
634
b4ff3a36 635 u8 reserved_at_200[0x600];
e281682b
SM		 636};
637
638struct mlx5_ifc_roce_cap_bits {
639 u8 roce_apm[0x1];
b4ff3a36 640 u8 reserved_at_1[0x1f];
e281682b 641
b4ff3a36 642 u8 reserved_at_20[0x60];
e281682b 643
b4ff3a36 644 u8 reserved_at_80[0xc];
e281682b 645 u8 l3_type[0x4];
b4ff3a36 646 u8 reserved_at_90[0x8];
e281682b
SM		 647 u8 roce_version[0x8];
648
b4ff3a36 649 u8 reserved_at_a0[0x10];
e281682b
SM		 650 u8 r_roce_dest_udp_port[0x10];
651
652 u8 r_roce_max_src_udp_port[0x10];
653 u8 r_roce_min_src_udp_port[0x10];
654
b4ff3a36 655 u8 reserved_at_e0[0x10];
e281682b
SM		 656 u8 roce_address_table_size[0x10];
657
b4ff3a36 658 u8 reserved_at_100[0x700];
e281682b
SM		 659};
660
661enum {
662 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
663 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
664 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
665 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
666 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
671};
672
673enum {
674 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
675 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
676 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
677 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
678 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
679 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
680 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
681 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
682 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
683};
684
685struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 686 u8 reserved_at_0[0x40];
e281682b 687
bd10838a 688 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 689 u8 reserved_at_42[0x4];
bd10838a 690 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 691
b4ff3a36 692 u8 reserved_at_47[0x19];
e281682b 693
b4ff3a36 694 u8 reserved_at_60[0x20];
e281682b 695
b4ff3a36 696 u8 reserved_at_80[0x10];
f91e6d89 697 u8 atomic_operations[0x10];
e281682b 698
b4ff3a36 699 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 700 u8 atomic_size_qp[0x10];
701
b4ff3a36 702 u8 reserved_at_c0[0x10];
e281682b
SM		 703 u8 atomic_size_dc[0x10];
704
b4ff3a36 705 u8 reserved_at_e0[0x720];
e281682b
SM		 706};
707
708struct mlx5_ifc_odp_cap_bits {
b4ff3a36 709 u8 reserved_at_0[0x40];
e281682b
SM		 710
711 u8 sig[0x1];
b4ff3a36 712 u8 reserved_at_41[0x1f];
e281682b 713
b4ff3a36 714 u8 reserved_at_60[0x20];
e281682b
SM		 715
716 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
717
718 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
719
720 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
721
b4ff3a36 722 u8 reserved_at_e0[0x720];
e281682b
SM		 723};
724
3f0393a5
SG		 725struct mlx5_ifc_calc_op {
726 u8 reserved_at_0[0x10];
727 u8 reserved_at_10[0x9];
728 u8 op_swap_endianness[0x1];
729 u8 op_min[0x1];
730 u8 op_xor[0x1];
731 u8 op_or[0x1];
732 u8 op_and[0x1];
733 u8 op_max[0x1];
734 u8 op_add[0x1];
735};
736
737struct mlx5_ifc_vector_calc_cap_bits {
738 u8 calc_matrix[0x1];
739 u8 reserved_at_1[0x1f];
740 u8 reserved_at_20[0x8];
741 u8 max_vec_count[0x8];
742 u8 reserved_at_30[0xd];
743 u8 max_chunk_size[0x3];
744 struct mlx5_ifc_calc_op calc0;
745 struct mlx5_ifc_calc_op calc1;
746 struct mlx5_ifc_calc_op calc2;
747 struct mlx5_ifc_calc_op calc3;
748
749 u8 reserved_at_e0[0x720];
750};
751
e281682b
SM		 752enum {
753 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
754 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 755 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 756 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 757};
758
759enum {
760 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
761 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
762};
763
764enum {
765 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
766 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
767 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
768 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
769 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
770};
771
772enum {
773 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
774 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
775 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
776 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
777 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
778 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
779};
780
781enum {
782 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
783 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
784};
785
786enum {
787 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
788 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
789 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
790};
791
792enum {
793 MLX5_CAP_PORT_TYPE_IB = 0x0,
794 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 795};
796
1410a90a
MG		 797enum {
798 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
799 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
800 MLX5_CAP_UMR_FENCE_NONE = 0x2,
801};
802
b775516b 803struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 804 u8 reserved_at_0[0x30];
805 u8 vhca_id[0x10];
806
807 u8 reserved_at_40[0x40];
b775516b
EC		 808
809 u8 log_max_srq_sz[0x8];
810 u8 log_max_qp_sz[0x8];
b4ff3a36 811 u8 reserved_at_90[0xb];
b775516b
EC		 812 u8 log_max_qp[0x5];
813
b4ff3a36 814 u8 reserved_at_a0[0xb];
e281682b 815 u8 log_max_srq[0x5];
b4ff3a36 816 u8 reserved_at_b0[0x10];
b775516b 817
b4ff3a36 818 u8 reserved_at_c0[0x8];
b775516b 819 u8 log_max_cq_sz[0x8];
b4ff3a36 820 u8 reserved_at_d0[0xb];
b775516b
EC		 821 u8 log_max_cq[0x5];
822
823 u8 log_max_eq_sz[0x8];
b4ff3a36 824 u8 reserved_at_e8[0x2];
b775516b 825 u8 log_max_mkey[0x6];
b4ff3a36 826 u8 reserved_at_f0[0xc];
b775516b
EC		 827 u8 log_max_eq[0x4];
828
829 u8 max_indirection[0x8];
bcda1aca 830 u8 fixed_buffer_size[0x1];
b775516b 831 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 832 u8 force_teardown[0x1];
833 u8 reserved_at_111[0x1];
b775516b 834 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 835 u8 umr_extended_translation_offset[0x1];
836 u8 null_mkey[0x1];
b775516b
EC		 837 u8 log_max_klm_list_size[0x6];
838
b4ff3a36 839 u8 reserved_at_120[0xa];
b775516b 840 u8 log_max_ra_req_dc[0x6];
b4ff3a36 841 u8 reserved_at_130[0xa];
b775516b
EC		 842 u8 log_max_ra_res_dc[0x6];
843
b4ff3a36 844 u8 reserved_at_140[0xa];
b775516b 845 u8 log_max_ra_req_qp[0x6];
b4ff3a36 846 u8 reserved_at_150[0xa];
b775516b
EC		 847 u8 log_max_ra_res_qp[0x6];
848
f32f5bd2 849 u8 end_pad[0x1];
b775516b
EC		 850 u8 cc_query_allowed[0x1];
851 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 852 u8 start_pad[0x1];
853 u8 cache_line_128byte[0x1];
c02762eb
HN		 854 u8 reserved_at_165[0xa];
855 u8 qcam_reg[0x1];
e281682b 856 u8 gid_table_size[0x10];
b775516b 857
e281682b
SM		 858 u8 out_of_seq_cnt[0x1];
859 u8 vport_counters[0x1];
7486216b 860 u8 retransmission_q_counters[0x1];
83b502a1
AV		 861 u8 reserved_at_183[0x1];
862 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 863 u8 rq_delay_drop[0x1];
b775516b
EC		 864 u8 max_qp_cnt[0xa];
865 u8 pkey_table_size[0x10];
866
e281682b
SM		 867 u8 vport_group_manager[0x1];
868 u8 vhca_group_manager[0x1];
869 u8 ib_virt[0x1];
870 u8 eth_virt[0x1];
b4ff3a36 871 u8 reserved_at_1a4[0x1];
e281682b
SM		 872 u8 ets[0x1];
873 u8 nic_flow_table[0x1];
54f0a411 874 u8 eswitch_flow_table[0x1];
e1c9c62b 875 u8 early_vf_enable[0x1];
cfdcbcea
GP		 876 u8 mcam_reg[0x1];
877 u8 pcam_reg[0x1];
b775516b 878 u8 local_ca_ack_delay[0x5];
4ce3bf2f 879 u8 port_module_event[0x1];
58dcb60a 880 u8 enhanced_error_q_counters[0x1];
7d5e1423 881 u8 ports_check[0x1];
7b13558f 882 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 883 u8 disable_link_up[0x1];
884 u8 beacon_led[0x1];
e281682b 885 u8 port_type[0x2];
b775516b
EC		 886 u8 num_ports[0x8];
887
f9a1ef72
EE		 888 u8 reserved_at_1c0[0x1];
889 u8 pps[0x1];
890 u8 pps_modify[0x1];
b775516b 891 u8 log_max_msg[0x5];
e1c9c62b 892 u8 reserved_at_1c8[0x4];
4f3961ee 893 u8 max_tc[0x4];
7486216b
SM		 894 u8 reserved_at_1d0[0x1];
895 u8 dcbx[0x1];
246ac981
MG		 896 u8 general_notification_event[0x1];
897 u8 reserved_at_1d3[0x2];
e29341fb 898 u8 fpga[0x1];
928cfe87
TT		 899 u8 rol_s[0x1];
900 u8 rol_g[0x1];
e1c9c62b 901 u8 reserved_at_1d8[0x1];
928cfe87
TT		 902 u8 wol_s[0x1];
903 u8 wol_g[0x1];
904 u8 wol_a[0x1];
905 u8 wol_b[0x1];
906 u8 wol_m[0x1];
907 u8 wol_u[0x1];
908 u8 wol_p[0x1];
b775516b
EC		 909
910 u8 stat_rate_support[0x10];
e1c9c62b 911 u8 reserved_at_1f0[0xc];
e281682b 912 u8 cqe_version[0x4];
b775516b 913
e281682b 914 u8 compact_address_vector[0x1];
7d5e1423 915 u8 striding_rq[0x1];
500a3d0d
ES		 916 u8 reserved_at_202[0x1];
917 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 918 u8 ipoib_basic_offloads[0x1];
1410a90a
MG		 919 u8 reserved_at_205[0x5];
920 u8 umr_fence[0x2];
921 u8 reserved_at_20c[0x3];
e281682b 922 u8 drain_sigerr[0x1];
b775516b
EC		 923 u8 cmdif_checksum[0x2];
924 u8 sigerr_cqe[0x1];
e1c9c62b 925 u8 reserved_at_213[0x1];
b775516b
EC		 926 u8 wq_signature[0x1];
927 u8 sctr_data_cqe[0x1];
e1c9c62b 928 u8 reserved_at_216[0x1];
b775516b
EC		 929 u8 sho[0x1];
930 u8 tph[0x1];
931 u8 rf[0x1];
e281682b 932 u8 dct[0x1];
7486216b 933 u8 qos[0x1];
e281682b 934 u8 eth_net_offloads[0x1];
b775516b
EC		 935 u8 roce[0x1];
936 u8 atomic[0x1];
e1c9c62b 937 u8 reserved_at_21f[0x1];
b775516b
EC		 938
939 u8 cq_oi[0x1];
940 u8 cq_resize[0x1];
941 u8 cq_moderation[0x1];
e1c9c62b 942 u8 reserved_at_223[0x3];
e281682b 943 u8 cq_eq_remap[0x1];
b775516b
EC		 944 u8 pg[0x1];
945 u8 block_lb_mc[0x1];
e1c9c62b 946 u8 reserved_at_229[0x1];
e281682b 947 u8 scqe_break_moderation[0x1];
7d5e1423 948 u8 cq_period_start_from_cqe[0x1];
b775516b 949 u8 cd[0x1];
e1c9c62b 950 u8 reserved_at_22d[0x1];
b775516b 951 u8 apm[0x1];
3f0393a5 952 u8 vector_calc[0x1];
7d5e1423 953 u8 umr_ptr_rlky[0x1];
d2370e0a 954 u8 imaicl[0x1];
e1c9c62b 955 u8 reserved_at_232[0x4];
b775516b
EC		 956 u8 qkv[0x1];
957 u8 pkv[0x1];
b11a4f9c
HE		 958 u8 set_deth_sqpn[0x1];
959 u8 reserved_at_239[0x3];
b775516b
EC		 960 u8 xrc[0x1];
961 u8 ud[0x1];
962 u8 uc[0x1];
963 u8 rc[0x1];
964
a6d51b68
EC		 965 u8 uar_4k[0x1];
966 u8 reserved_at_241[0x9];
b775516b 967 u8 uar_sz[0x6];
e1c9c62b 968 u8 reserved_at_250[0x8];
b775516b
EC		 969 u8 log_pg_sz[0x8];
970
971 u8 bf[0x1];
0dbc6fe0 972 u8 driver_version[0x1];
e281682b 973 u8 pad_tx_eth_packet[0x1];
e1c9c62b 974 u8 reserved_at_263[0x8];
b775516b 975 u8 log_bf_reg_size[0x5];
84df61eb
AH		 976
977 u8 reserved_at_270[0xb];
978 u8 lag_master[0x1];
979 u8 num_lag_ports[0x4];
b775516b 980
e1c9c62b 981 u8 reserved_at_280[0x10];
b775516b
EC		 982 u8 max_wqe_sz_sq[0x10];
983
e1c9c62b 984 u8 reserved_at_2a0[0x10];
b775516b
EC		 985 u8 max_wqe_sz_rq[0x10];
986
a8ffcc74 987 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 988 u8 max_wqe_sz_sq_dc[0x10];
989
e1c9c62b 990 u8 reserved_at_2e0[0x7];
b775516b
EC		 991 u8 max_qp_mcg[0x19];
992
e1c9c62b 993 u8 reserved_at_300[0x18];
b775516b
EC		 994 u8 log_max_mcg[0x8];
995
e1c9c62b 996 u8 reserved_at_320[0x3];
e281682b 997 u8 log_max_transport_domain[0x5];
e1c9c62b 998 u8 reserved_at_328[0x3];
b775516b 999 u8 log_max_pd[0x5];
e1c9c62b 1000 u8 reserved_at_330[0xb];
b775516b
EC		 1001 u8 log_max_xrcd[0x5];
1002
a351a1b0
AV		 1003 u8 reserved_at_340[0x8];
1004 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1005 u8 max_flow_counter_15_0[0x10];
a351a1b0 1006
b775516b 1007
e1c9c62b 1008 u8 reserved_at_360[0x3];
b775516b 1009 u8 log_max_rq[0x5];
e1c9c62b 1010 u8 reserved_at_368[0x3];
b775516b 1011 u8 log_max_sq[0x5];
e1c9c62b 1012 u8 reserved_at_370[0x3];
b775516b 1013 u8 log_max_tir[0x5];
e1c9c62b 1014 u8 reserved_at_378[0x3];
b775516b
EC		 1015 u8 log_max_tis[0x5];
1016
e281682b 1017 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1018 u8 reserved_at_381[0x2];
e281682b 1019 u8 log_max_rmp[0x5];
e1c9c62b 1020 u8 reserved_at_388[0x3];
e281682b 1021 u8 log_max_rqt[0x5];
e1c9c62b 1022 u8 reserved_at_390[0x3];
e281682b 1023 u8 log_max_rqt_size[0x5];
e1c9c62b 1024 u8 reserved_at_398[0x3];
b775516b
EC		 1025 u8 log_max_tis_per_sq[0x5];
1026
e1c9c62b 1027 u8 reserved_at_3a0[0x3];
e281682b 1028 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1029 u8 reserved_at_3a8[0x3];
e281682b 1030 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1031 u8 reserved_at_3b0[0x3];
e281682b 1032 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1033 u8 reserved_at_3b8[0x3];
e281682b
SM		 1034 u8 log_min_stride_sz_sq[0x5];
1035
40817cdb
OG		 1036 u8 hairpin[0x1];
1037 u8 reserved_at_3c1[0x2];
1038 u8 log_max_hairpin_queues[0x5];
1039 u8 reserved_at_3c8[0x3];
1040 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1041 u8 reserved_at_3d0[0x3];
1042 u8 log_max_hairpin_num_packets[0x5];
1043 u8 reserved_at_3d8[0x3];
e281682b
SM		 1044 u8 log_max_wq_sz[0x5];
1045
54f0a411 1046 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1047 u8 disable_local_lb_uc[0x1];
1048 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1049 u8 log_min_hairpin_wq_data_sz[0x5];
1050 u8 reserved_at_3e8[0x3];
54f0a411 1051 u8 log_max_vlan_list[0x5];
e1c9c62b 1052 u8 reserved_at_3f0[0x3];
54f0a411 1053 u8 log_max_current_mc_list[0x5];
e1c9c62b 1054 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1055 u8 log_max_current_uc_list[0x5];
1056
e1c9c62b 1057 u8 reserved_at_400[0x80];
54f0a411 1058
e1c9c62b 1059 u8 reserved_at_480[0x3];
e281682b 1060 u8 log_max_l2_table[0x5];
e1c9c62b 1061 u8 reserved_at_488[0x8];
b775516b
EC		 1062 u8 log_uar_page_sz[0x10];
1063
e1c9c62b 1064 u8 reserved_at_4a0[0x20];
048ccca8 1065 u8 device_frequency_mhz[0x20];
b0844444 1066 u8 device_frequency_khz[0x20];
e1c9c62b 1067
a6d51b68
EC		 1068 u8 reserved_at_500[0x20];
1069 u8 num_of_uars_per_page[0x20];
1070 u8 reserved_at_540[0x40];
e1c9c62b 1071
0ff8e79c
GL		 1072 u8 reserved_at_580[0x3d];
1073 u8 cqe_128_always[0x1];
1074 u8 cqe_compression_128[0x1];
7d5e1423 1075 u8 cqe_compression[0x1];
b775516b 1076
7d5e1423
SM		 1077 u8 cqe_compression_timeout[0x10];
1078 u8 cqe_compression_max_num[0x10];
b775516b 1079
7486216b
SM		 1080 u8 reserved_at_5e0[0x10];
1081 u8 tag_matching[0x1];
1082 u8 rndv_offload_rc[0x1];
1083 u8 rndv_offload_dc[0x1];
1084 u8 log_tag_matching_list_sz[0x5];
7b13558f 1085 u8 reserved_at_5f8[0x3];
7486216b
SM		 1086 u8 log_max_xrq[0x5];
1087
32f69e4b
DJ		 1088 u8 affiliate_nic_vport_criteria[0x8];
1089 u8 native_port_num[0x8];
1090 u8 num_vhca_ports[0x8];
1091 u8 reserved_at_618[0x6];
1092 u8 sw_owner_id[0x1];
8737f818 1093 u8 reserved_at_61f[0x1e1];
b775516b
EC		 1094};
1095
81848731
SM		 1096enum mlx5_flow_destination_type {
1097 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1098 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1099 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1100
5f418378 1101 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1102 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1103};
b775516b 1104
e281682b
SM		 1105struct mlx5_ifc_dest_format_struct_bits {
1106 u8 destination_type[0x8];
1107 u8 destination_id[0x18];
b775516b 1108
b4ff3a36 1109 u8 reserved_at_20[0x20];
e281682b
SM		 1110};
1111
9dc0b289 1112struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1113 u8 flow_counter_id[0x20];
9dc0b289
AV		 1114
1115 u8 reserved_at_20[0x20];
1116};
1117
1118union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1119 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1120 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1121 u8 reserved_at_0[0x40];
1122};
1123
e281682b
SM		 1124struct mlx5_ifc_fte_match_param_bits {
1125 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1126
1127 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1128
1129 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1130
b4ff3a36 1131 u8 reserved_at_600[0xa00];
b775516b
EC		 1132};
1133
e281682b
SM		 1134enum {
1135 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1136 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1137 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1138 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1139 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1140};
b775516b 1141
e281682b
SM		 1142struct mlx5_ifc_rx_hash_field_select_bits {
1143 u8 l3_prot_type[0x1];
1144 u8 l4_prot_type[0x1];
1145 u8 selected_fields[0x1e];
1146};
b775516b 1147
e281682b
SM		 1148enum {
1149 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1150 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1151};
1152
e281682b
SM		 1153enum {
1154 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1155 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1156};
1157
1158struct mlx5_ifc_wq_bits {
1159 u8 wq_type[0x4];
1160 u8 wq_signature[0x1];
1161 u8 end_padding_mode[0x2];
1162 u8 cd_slave[0x1];
b4ff3a36 1163 u8 reserved_at_8[0x18];
b775516b 1164
e281682b
SM		 1165 u8 hds_skip_first_sge[0x1];
1166 u8 log2_hds_buf_size[0x3];
b4ff3a36 1167 u8 reserved_at_24[0x7];
e281682b
SM		 1168 u8 page_offset[0x5];
1169 u8 lwm[0x10];
b775516b 1170
b4ff3a36 1171 u8 reserved_at_40[0x8];
e281682b
SM		 1172 u8 pd[0x18];
1173
b4ff3a36 1174 u8 reserved_at_60[0x8];
e281682b
SM		 1175 u8 uar_page[0x18];
1176
1177 u8 dbr_addr[0x40];
1178
1179 u8 hw_counter[0x20];
1180
1181 u8 sw_counter[0x20];
1182
b4ff3a36 1183 u8 reserved_at_100[0xc];
e281682b 1184 u8 log_wq_stride[0x4];
b4ff3a36 1185 u8 reserved_at_110[0x3];
e281682b 1186 u8 log_wq_pg_sz[0x5];
b4ff3a36 1187 u8 reserved_at_118[0x3];
e281682b
SM		 1188 u8 log_wq_sz[0x5];
1189
4d533e0f
OG		 1190 u8 reserved_at_120[0x3];
1191 u8 log_hairpin_num_packets[0x5];
1192 u8 reserved_at_128[0x3];
40817cdb
OG		 1193 u8 log_hairpin_data_sz[0x5];
1194 u8 reserved_at_130[0x5];
1195
7d5e1423
SM		 1196 u8 log_wqe_num_of_strides[0x3];
1197 u8 two_byte_shift_en[0x1];
1198 u8 reserved_at_139[0x4];
1199 u8 log_wqe_stride_size[0x3];
1200
1201 u8 reserved_at_140[0x4c0];
b775516b 1202
e281682b 1203 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1204};
1205
e281682b 1206struct mlx5_ifc_rq_num_bits {
b4ff3a36 1207 u8 reserved_at_0[0x8];
e281682b
SM		 1208 u8 rq_num[0x18];
1209};
b775516b 1210
e281682b 1211struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1212 u8 reserved_at_0[0x10];
e281682b 1213 u8 mac_addr_47_32[0x10];
b775516b 1214
e281682b
SM		 1215 u8 mac_addr_31_0[0x20];
1216};
1217
c0046cf7 1218struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1219 u8 reserved_at_0[0x14];
c0046cf7
SM		 1220 u8 vlan[0x0c];
1221
b4ff3a36 1222 u8 reserved_at_20[0x20];
c0046cf7
SM		 1223};
1224
e281682b 1225struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1226 u8 reserved_at_0[0xa0];
e281682b
SM		 1227
1228 u8 min_time_between_cnps[0x20];
1229
b4ff3a36 1230 u8 reserved_at_c0[0x12];
e281682b 1231 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1232 u8 reserved_at_d8[0x4];
1233 u8 cnp_prio_mode[0x1];
e281682b
SM		 1234 u8 cnp_802p_prio[0x3];
1235
b4ff3a36 1236 u8 reserved_at_e0[0x720];
e281682b
SM		 1237};
1238
1239struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1240 u8 reserved_at_0[0x60];
e281682b 1241
b4ff3a36 1242 u8 reserved_at_60[0x4];
e281682b 1243 u8 clamp_tgt_rate[0x1];
b4ff3a36 1244 u8 reserved_at_65[0x3];
e281682b 1245 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1246 u8 reserved_at_69[0x17];
e281682b 1247
b4ff3a36 1248 u8 reserved_at_80[0x20];
e281682b
SM		 1249
1250 u8 rpg_time_reset[0x20];
1251
1252 u8 rpg_byte_reset[0x20];
1253
1254 u8 rpg_threshold[0x20];
1255
1256 u8 rpg_max_rate[0x20];
1257
1258 u8 rpg_ai_rate[0x20];
1259
1260 u8 rpg_hai_rate[0x20];
1261
1262 u8 rpg_gd[0x20];
1263
1264 u8 rpg_min_dec_fac[0x20];
1265
1266 u8 rpg_min_rate[0x20];
1267
b4ff3a36 1268 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1269
1270 u8 rate_to_set_on_first_cnp[0x20];
1271
1272 u8 dce_tcp_g[0x20];
1273
1274 u8 dce_tcp_rtt[0x20];
1275
1276 u8 rate_reduce_monitor_period[0x20];
1277
b4ff3a36 1278 u8 reserved_at_320[0x20];
e281682b
SM		 1279
1280 u8 initial_alpha_value[0x20];
1281
b4ff3a36 1282 u8 reserved_at_360[0x4a0];
e281682b
SM		 1283};
1284
1285struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1286 u8 reserved_at_0[0x80];
e281682b
SM		 1287
1288 u8 rppp_max_rps[0x20];
1289
1290 u8 rpg_time_reset[0x20];
1291
1292 u8 rpg_byte_reset[0x20];
1293
1294 u8 rpg_threshold[0x20];
1295
1296 u8 rpg_max_rate[0x20];
1297
1298 u8 rpg_ai_rate[0x20];
1299
1300 u8 rpg_hai_rate[0x20];
1301
1302 u8 rpg_gd[0x20];
1303
1304 u8 rpg_min_dec_fac[0x20];
1305
1306 u8 rpg_min_rate[0x20];
1307
b4ff3a36 1308 u8 reserved_at_1c0[0x640];
e281682b
SM		 1309};
1310
1311enum {
1312 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1313 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1314 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1315};
1316
1317struct mlx5_ifc_resize_field_select_bits {
1318 u8 resize_field_select[0x20];
1319};
1320
1321enum {
1322 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1323 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1324 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1325 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1326};
1327
1328struct mlx5_ifc_modify_field_select_bits {
1329 u8 modify_field_select[0x20];
1330};
1331
1332struct mlx5_ifc_field_select_r_roce_np_bits {
1333 u8 field_select_r_roce_np[0x20];
1334};
1335
1336struct mlx5_ifc_field_select_r_roce_rp_bits {
1337 u8 field_select_r_roce_rp[0x20];
1338};
1339
1340enum {
1341 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1342 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1343 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1344 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1345 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1346 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1347 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1348 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1349 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1350 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1351};
1352
1353struct mlx5_ifc_field_select_802_1qau_rp_bits {
1354 u8 field_select_8021qaurp[0x20];
1355};
1356
1357struct mlx5_ifc_phys_layer_cntrs_bits {
1358 u8 time_since_last_clear_high[0x20];
1359
1360 u8 time_since_last_clear_low[0x20];
1361
1362 u8 symbol_errors_high[0x20];
1363
1364 u8 symbol_errors_low[0x20];
1365
1366 u8 sync_headers_errors_high[0x20];
1367
1368 u8 sync_headers_errors_low[0x20];
1369
1370 u8 edpl_bip_errors_lane0_high[0x20];
1371
1372 u8 edpl_bip_errors_lane0_low[0x20];
1373
1374 u8 edpl_bip_errors_lane1_high[0x20];
1375
1376 u8 edpl_bip_errors_lane1_low[0x20];
1377
1378 u8 edpl_bip_errors_lane2_high[0x20];
1379
1380 u8 edpl_bip_errors_lane2_low[0x20];
1381
1382 u8 edpl_bip_errors_lane3_high[0x20];
1383
1384 u8 edpl_bip_errors_lane3_low[0x20];
1385
1386 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1387
1388 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1389
1390 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1391
1392 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1393
1394 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1395
1396 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1397
1398 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1399
1400 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1401
1402 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1403
1404 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1405
1406 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1407
1408 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1409
1410 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1411
1412 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1413
1414 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1415
1416 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1417
1418 u8 rs_fec_corrected_blocks_high[0x20];
1419
1420 u8 rs_fec_corrected_blocks_low[0x20];
1421
1422 u8 rs_fec_uncorrectable_blocks_high[0x20];
1423
1424 u8 rs_fec_uncorrectable_blocks_low[0x20];
1425
1426 u8 rs_fec_no_errors_blocks_high[0x20];
1427
1428 u8 rs_fec_no_errors_blocks_low[0x20];
1429
1430 u8 rs_fec_single_error_blocks_high[0x20];
1431
1432 u8 rs_fec_single_error_blocks_low[0x20];
1433
1434 u8 rs_fec_corrected_symbols_total_high[0x20];
1435
1436 u8 rs_fec_corrected_symbols_total_low[0x20];
1437
1438 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1439
1440 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1441
1442 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1443
1444 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1445
1446 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1447
1448 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1449
1450 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1451
1452 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1453
1454 u8 link_down_events[0x20];
1455
1456 u8 successful_recovery_events[0x20];
1457
b4ff3a36 1458 u8 reserved_at_640[0x180];
e281682b
SM		 1459};
1460
d8dc0508
GP		 1461struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1462 u8 time_since_last_clear_high[0x20];
1463
1464 u8 time_since_last_clear_low[0x20];
1465
1466 u8 phy_received_bits_high[0x20];
1467
1468 u8 phy_received_bits_low[0x20];
1469
1470 u8 phy_symbol_errors_high[0x20];
1471
1472 u8 phy_symbol_errors_low[0x20];
1473
1474 u8 phy_corrected_bits_high[0x20];
1475
1476 u8 phy_corrected_bits_low[0x20];
1477
1478 u8 phy_corrected_bits_lane0_high[0x20];
1479
1480 u8 phy_corrected_bits_lane0_low[0x20];
1481
1482 u8 phy_corrected_bits_lane1_high[0x20];
1483
1484 u8 phy_corrected_bits_lane1_low[0x20];
1485
1486 u8 phy_corrected_bits_lane2_high[0x20];
1487
1488 u8 phy_corrected_bits_lane2_low[0x20];
1489
1490 u8 phy_corrected_bits_lane3_high[0x20];
1491
1492 u8 phy_corrected_bits_lane3_low[0x20];
1493
1494 u8 reserved_at_200[0x5c0];
1495};
1496
1c64bf6f
MY		 1497struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1498 u8 symbol_error_counter[0x10];
1499
1500 u8 link_error_recovery_counter[0x8];
1501
1502 u8 link_downed_counter[0x8];
1503
1504 u8 port_rcv_errors[0x10];
1505
1506 u8 port_rcv_remote_physical_errors[0x10];
1507
1508 u8 port_rcv_switch_relay_errors[0x10];
1509
1510 u8 port_xmit_discards[0x10];
1511
1512 u8 port_xmit_constraint_errors[0x8];
1513
1514 u8 port_rcv_constraint_errors[0x8];
1515
1516 u8 reserved_at_70[0x8];
1517
1518 u8 link_overrun_errors[0x8];
1519
1520 u8 reserved_at_80[0x10];
1521
1522 u8 vl_15_dropped[0x10];
1523
133bea04
TW		 1524 u8 reserved_at_a0[0x80];
1525
1526 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1527};
1528
e281682b
SM		 1529struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1530 u8 transmit_queue_high[0x20];
1531
1532 u8 transmit_queue_low[0x20];
1533
b4ff3a36 1534 u8 reserved_at_40[0x780];
e281682b
SM		 1535};
1536
1537struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1538 u8 rx_octets_high[0x20];
1539
1540 u8 rx_octets_low[0x20];
1541
b4ff3a36 1542 u8 reserved_at_40[0xc0];
e281682b
SM		 1543
1544 u8 rx_frames_high[0x20];
1545
1546 u8 rx_frames_low[0x20];
1547
1548 u8 tx_octets_high[0x20];
1549
1550 u8 tx_octets_low[0x20];
1551
b4ff3a36 1552 u8 reserved_at_180[0xc0];
e281682b
SM		 1553
1554 u8 tx_frames_high[0x20];
1555
1556 u8 tx_frames_low[0x20];
1557
1558 u8 rx_pause_high[0x20];
1559
1560 u8 rx_pause_low[0x20];
1561
1562 u8 rx_pause_duration_high[0x20];
1563
1564 u8 rx_pause_duration_low[0x20];
1565
1566 u8 tx_pause_high[0x20];
1567
1568 u8 tx_pause_low[0x20];
1569
1570 u8 tx_pause_duration_high[0x20];
1571
1572 u8 tx_pause_duration_low[0x20];
1573
1574 u8 rx_pause_transition_high[0x20];
1575
1576 u8 rx_pause_transition_low[0x20];
1577
b4ff3a36 1578 u8 reserved_at_3c0[0x400];
e281682b
SM		 1579};
1580
1581struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1582 u8 port_transmit_wait_high[0x20];
1583
1584 u8 port_transmit_wait_low[0x20];
1585
2dba0797
GP		 1586 u8 reserved_at_40[0x100];
1587
1588 u8 rx_buffer_almost_full_high[0x20];
1589
1590 u8 rx_buffer_almost_full_low[0x20];
1591
1592 u8 rx_buffer_full_high[0x20];
1593
1594 u8 rx_buffer_full_low[0x20];
1595
1596 u8 reserved_at_1c0[0x600];
e281682b
SM		 1597};
1598
1599struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1600 u8 dot3stats_alignment_errors_high[0x20];
1601
1602 u8 dot3stats_alignment_errors_low[0x20];
1603
1604 u8 dot3stats_fcs_errors_high[0x20];
1605
1606 u8 dot3stats_fcs_errors_low[0x20];
1607
1608 u8 dot3stats_single_collision_frames_high[0x20];
1609
1610 u8 dot3stats_single_collision_frames_low[0x20];
1611
1612 u8 dot3stats_multiple_collision_frames_high[0x20];
1613
1614 u8 dot3stats_multiple_collision_frames_low[0x20];
1615
1616 u8 dot3stats_sqe_test_errors_high[0x20];
1617
1618 u8 dot3stats_sqe_test_errors_low[0x20];
1619
1620 u8 dot3stats_deferred_transmissions_high[0x20];
1621
1622 u8 dot3stats_deferred_transmissions_low[0x20];
1623
1624 u8 dot3stats_late_collisions_high[0x20];
1625
1626 u8 dot3stats_late_collisions_low[0x20];
1627
1628 u8 dot3stats_excessive_collisions_high[0x20];
1629
1630 u8 dot3stats_excessive_collisions_low[0x20];
1631
1632 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1633
1634 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1635
1636 u8 dot3stats_carrier_sense_errors_high[0x20];
1637
1638 u8 dot3stats_carrier_sense_errors_low[0x20];
1639
1640 u8 dot3stats_frame_too_longs_high[0x20];
1641
1642 u8 dot3stats_frame_too_longs_low[0x20];
1643
1644 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1645
1646 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1647
1648 u8 dot3stats_symbol_errors_high[0x20];
1649
1650 u8 dot3stats_symbol_errors_low[0x20];
1651
1652 u8 dot3control_in_unknown_opcodes_high[0x20];
1653
1654 u8 dot3control_in_unknown_opcodes_low[0x20];
1655
1656 u8 dot3in_pause_frames_high[0x20];
1657
1658 u8 dot3in_pause_frames_low[0x20];
1659
1660 u8 dot3out_pause_frames_high[0x20];
1661
1662 u8 dot3out_pause_frames_low[0x20];
1663
b4ff3a36 1664 u8 reserved_at_400[0x3c0];
e281682b
SM		 1665};
1666
1667struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1668 u8 ether_stats_drop_events_high[0x20];
1669
1670 u8 ether_stats_drop_events_low[0x20];
1671
1672 u8 ether_stats_octets_high[0x20];
1673
1674 u8 ether_stats_octets_low[0x20];
1675
1676 u8 ether_stats_pkts_high[0x20];
1677
1678 u8 ether_stats_pkts_low[0x20];
1679
1680 u8 ether_stats_broadcast_pkts_high[0x20];
1681
1682 u8 ether_stats_broadcast_pkts_low[0x20];
1683
1684 u8 ether_stats_multicast_pkts_high[0x20];
1685
1686 u8 ether_stats_multicast_pkts_low[0x20];
1687
1688 u8 ether_stats_crc_align_errors_high[0x20];
1689
1690 u8 ether_stats_crc_align_errors_low[0x20];
1691
1692 u8 ether_stats_undersize_pkts_high[0x20];
1693
1694 u8 ether_stats_undersize_pkts_low[0x20];
1695
1696 u8 ether_stats_oversize_pkts_high[0x20];
1697
1698 u8 ether_stats_oversize_pkts_low[0x20];
1699
1700 u8 ether_stats_fragments_high[0x20];
1701
1702 u8 ether_stats_fragments_low[0x20];
1703
1704 u8 ether_stats_jabbers_high[0x20];
1705
1706 u8 ether_stats_jabbers_low[0x20];
1707
1708 u8 ether_stats_collisions_high[0x20];
1709
1710 u8 ether_stats_collisions_low[0x20];
1711
1712 u8 ether_stats_pkts64octets_high[0x20];
1713
1714 u8 ether_stats_pkts64octets_low[0x20];
1715
1716 u8 ether_stats_pkts65to127octets_high[0x20];
1717
1718 u8 ether_stats_pkts65to127octets_low[0x20];
1719
1720 u8 ether_stats_pkts128to255octets_high[0x20];
1721
1722 u8 ether_stats_pkts128to255octets_low[0x20];
1723
1724 u8 ether_stats_pkts256to511octets_high[0x20];
1725
1726 u8 ether_stats_pkts256to511octets_low[0x20];
1727
1728 u8 ether_stats_pkts512to1023octets_high[0x20];
1729
1730 u8 ether_stats_pkts512to1023octets_low[0x20];
1731
1732 u8 ether_stats_pkts1024to1518octets_high[0x20];
1733
1734 u8 ether_stats_pkts1024to1518octets_low[0x20];
1735
1736 u8 ether_stats_pkts1519to2047octets_high[0x20];
1737
1738 u8 ether_stats_pkts1519to2047octets_low[0x20];
1739
1740 u8 ether_stats_pkts2048to4095octets_high[0x20];
1741
1742 u8 ether_stats_pkts2048to4095octets_low[0x20];
1743
1744 u8 ether_stats_pkts4096to8191octets_high[0x20];
1745
1746 u8 ether_stats_pkts4096to8191octets_low[0x20];
1747
1748 u8 ether_stats_pkts8192to10239octets_high[0x20];
1749
1750 u8 ether_stats_pkts8192to10239octets_low[0x20];
1751
b4ff3a36 1752 u8 reserved_at_540[0x280];
e281682b
SM		 1753};
1754
1755struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1756 u8 if_in_octets_high[0x20];
1757
1758 u8 if_in_octets_low[0x20];
1759
1760 u8 if_in_ucast_pkts_high[0x20];
1761
1762 u8 if_in_ucast_pkts_low[0x20];
1763
1764 u8 if_in_discards_high[0x20];
1765
1766 u8 if_in_discards_low[0x20];
1767
1768 u8 if_in_errors_high[0x20];
1769
1770 u8 if_in_errors_low[0x20];
1771
1772 u8 if_in_unknown_protos_high[0x20];
1773
1774 u8 if_in_unknown_protos_low[0x20];
1775
1776 u8 if_out_octets_high[0x20];
1777
1778 u8 if_out_octets_low[0x20];
1779
1780 u8 if_out_ucast_pkts_high[0x20];
1781
1782 u8 if_out_ucast_pkts_low[0x20];
1783
1784 u8 if_out_discards_high[0x20];
1785
1786 u8 if_out_discards_low[0x20];
1787
1788 u8 if_out_errors_high[0x20];
1789
1790 u8 if_out_errors_low[0x20];
1791
1792 u8 if_in_multicast_pkts_high[0x20];
1793
1794 u8 if_in_multicast_pkts_low[0x20];
1795
1796 u8 if_in_broadcast_pkts_high[0x20];
1797
1798 u8 if_in_broadcast_pkts_low[0x20];
1799
1800 u8 if_out_multicast_pkts_high[0x20];
1801
1802 u8 if_out_multicast_pkts_low[0x20];
1803
1804 u8 if_out_broadcast_pkts_high[0x20];
1805
1806 u8 if_out_broadcast_pkts_low[0x20];
1807
b4ff3a36 1808 u8 reserved_at_340[0x480];
e281682b
SM		 1809};
1810
1811struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1812 u8 a_frames_transmitted_ok_high[0x20];
1813
1814 u8 a_frames_transmitted_ok_low[0x20];
1815
1816 u8 a_frames_received_ok_high[0x20];
1817
1818 u8 a_frames_received_ok_low[0x20];
1819
1820 u8 a_frame_check_sequence_errors_high[0x20];
1821
1822 u8 a_frame_check_sequence_errors_low[0x20];
1823
1824 u8 a_alignment_errors_high[0x20];
1825
1826 u8 a_alignment_errors_low[0x20];
1827
1828 u8 a_octets_transmitted_ok_high[0x20];
1829
1830 u8 a_octets_transmitted_ok_low[0x20];
1831
1832 u8 a_octets_received_ok_high[0x20];
1833
1834 u8 a_octets_received_ok_low[0x20];
1835
1836 u8 a_multicast_frames_xmitted_ok_high[0x20];
1837
1838 u8 a_multicast_frames_xmitted_ok_low[0x20];
1839
1840 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1841
1842 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1843
1844 u8 a_multicast_frames_received_ok_high[0x20];
1845
1846 u8 a_multicast_frames_received_ok_low[0x20];
1847
1848 u8 a_broadcast_frames_received_ok_high[0x20];
1849
1850 u8 a_broadcast_frames_received_ok_low[0x20];
1851
1852 u8 a_in_range_length_errors_high[0x20];
1853
1854 u8 a_in_range_length_errors_low[0x20];
1855
1856 u8 a_out_of_range_length_field_high[0x20];
1857
1858 u8 a_out_of_range_length_field_low[0x20];
1859
1860 u8 a_frame_too_long_errors_high[0x20];
1861
1862 u8 a_frame_too_long_errors_low[0x20];
1863
1864 u8 a_symbol_error_during_carrier_high[0x20];
1865
1866 u8 a_symbol_error_during_carrier_low[0x20];
1867
1868 u8 a_mac_control_frames_transmitted_high[0x20];
1869
1870 u8 a_mac_control_frames_transmitted_low[0x20];
1871
1872 u8 a_mac_control_frames_received_high[0x20];
1873
1874 u8 a_mac_control_frames_received_low[0x20];
1875
1876 u8 a_unsupported_opcodes_received_high[0x20];
1877
1878 u8 a_unsupported_opcodes_received_low[0x20];
1879
1880 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1881
1882 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1883
1884 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1885
1886 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1887
b4ff3a36 1888 u8 reserved_at_4c0[0x300];
e281682b
SM		 1889};
1890
8ed1a630
GP		 1891struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1892 u8 life_time_counter_high[0x20];
1893
1894 u8 life_time_counter_low[0x20];
1895
1896 u8 rx_errors[0x20];
1897
1898 u8 tx_errors[0x20];
1899
1900 u8 l0_to_recovery_eieos[0x20];
1901
1902 u8 l0_to_recovery_ts[0x20];
1903
1904 u8 l0_to_recovery_framing[0x20];
1905
1906 u8 l0_to_recovery_retrain[0x20];
1907
1908 u8 crc_error_dllp[0x20];
1909
1910 u8 crc_error_tlp[0x20];
1911
efae7f78
EBE		 1912 u8 tx_overflow_buffer_pkt_high[0x20];
1913
1914 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 1915
1916 u8 outbound_stalled_reads[0x20];
1917
1918 u8 outbound_stalled_writes[0x20];
1919
1920 u8 outbound_stalled_reads_events[0x20];
1921
1922 u8 outbound_stalled_writes_events[0x20];
1923
1924 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 1925};
1926
e281682b
SM		 1927struct mlx5_ifc_cmd_inter_comp_event_bits {
1928 u8 command_completion_vector[0x20];
1929
b4ff3a36 1930 u8 reserved_at_20[0xc0];
e281682b
SM		 1931};
1932
1933struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1934 u8 reserved_at_0[0x18];
e281682b 1935 u8 port_num[0x1];
b4ff3a36 1936 u8 reserved_at_19[0x3];
e281682b
SM		 1937 u8 vl[0x4];
1938
b4ff3a36 1939 u8 reserved_at_20[0xa0];
e281682b
SM		 1940};
1941
1942struct mlx5_ifc_db_bf_congestion_event_bits {
1943 u8 event_subtype[0x8];
b4ff3a36 1944 u8 reserved_at_8[0x8];
e281682b 1945 u8 congestion_level[0x8];
b4ff3a36 1946 u8 reserved_at_18[0x8];
e281682b 1947
b4ff3a36 1948 u8 reserved_at_20[0xa0];
e281682b
SM		 1949};
1950
1951struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1952 u8 reserved_at_0[0x60];
e281682b
SM		 1953
1954 u8 gpio_event_hi[0x20];
1955
1956 u8 gpio_event_lo[0x20];
1957
b4ff3a36 1958 u8 reserved_at_a0[0x40];
e281682b
SM		 1959};
1960
1961struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1962 u8 reserved_at_0[0x40];
e281682b
SM		 1963
1964 u8 port_num[0x4];
b4ff3a36 1965 u8 reserved_at_44[0x1c];
e281682b 1966
b4ff3a36 1967 u8 reserved_at_60[0x80];
e281682b
SM		 1968};
1969
1970struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1971 u8 reserved_at_0[0xe0];
e281682b
SM		 1972};
1973
1974enum {
1975 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1976 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1977};
1978
1979struct mlx5_ifc_cq_error_bits {
b4ff3a36 1980 u8 reserved_at_0[0x8];
e281682b
SM		 1981 u8 cqn[0x18];
1982
b4ff3a36 1983 u8 reserved_at_20[0x20];
e281682b 1984
b4ff3a36 1985 u8 reserved_at_40[0x18];
e281682b
SM		 1986 u8 syndrome[0x8];
1987
b4ff3a36 1988 u8 reserved_at_60[0x80];
e281682b
SM		 1989};
1990
1991struct mlx5_ifc_rdma_page_fault_event_bits {
1992 u8 bytes_committed[0x20];
1993
1994 u8 r_key[0x20];
1995
b4ff3a36 1996 u8 reserved_at_40[0x10];
e281682b
SM		 1997 u8 packet_len[0x10];
1998
1999 u8 rdma_op_len[0x20];
2000
2001 u8 rdma_va[0x40];
2002
b4ff3a36 2003 u8 reserved_at_c0[0x5];
e281682b
SM		 2004 u8 rdma[0x1];
2005 u8 write[0x1];
2006 u8 requestor[0x1];
2007 u8 qp_number[0x18];
2008};
2009
2010struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2011 u8 bytes_committed[0x20];
2012
b4ff3a36 2013 u8 reserved_at_20[0x10];
e281682b
SM		 2014 u8 wqe_index[0x10];
2015
b4ff3a36 2016 u8 reserved_at_40[0x10];
e281682b
SM		 2017 u8 len[0x10];
2018
b4ff3a36 2019 u8 reserved_at_60[0x60];
e281682b 2020
b4ff3a36 2021 u8 reserved_at_c0[0x5];
e281682b
SM		 2022 u8 rdma[0x1];
2023 u8 write_read[0x1];
2024 u8 requestor[0x1];
2025 u8 qpn[0x18];
2026};
2027
2028struct mlx5_ifc_qp_events_bits {
b4ff3a36 2029 u8 reserved_at_0[0xa0];
e281682b
SM		 2030
2031 u8 type[0x8];
b4ff3a36 2032 u8 reserved_at_a8[0x18];
e281682b 2033
b4ff3a36 2034 u8 reserved_at_c0[0x8];
e281682b
SM		 2035 u8 qpn_rqn_sqn[0x18];
2036};
2037
2038struct mlx5_ifc_dct_events_bits {
b4ff3a36 2039 u8 reserved_at_0[0xc0];
e281682b 2040
b4ff3a36 2041 u8 reserved_at_c0[0x8];
e281682b
SM		 2042 u8 dct_number[0x18];
2043};
2044
2045struct mlx5_ifc_comp_event_bits {
b4ff3a36 2046 u8 reserved_at_0[0xc0];
e281682b 2047
b4ff3a36 2048 u8 reserved_at_c0[0x8];
e281682b
SM		 2049 u8 cq_number[0x18];
2050};
2051
2052enum {
2053 MLX5_QPC_STATE_RST = 0x0,
2054 MLX5_QPC_STATE_INIT = 0x1,
2055 MLX5_QPC_STATE_RTR = 0x2,
2056 MLX5_QPC_STATE_RTS = 0x3,
2057 MLX5_QPC_STATE_SQER = 0x4,
2058 MLX5_QPC_STATE_ERR = 0x6,
2059 MLX5_QPC_STATE_SQD = 0x7,
2060 MLX5_QPC_STATE_SUSPENDED = 0x9,
2061};
2062
2063enum {
2064 MLX5_QPC_ST_RC = 0x0,
2065 MLX5_QPC_ST_UC = 0x1,
2066 MLX5_QPC_ST_UD = 0x2,
2067 MLX5_QPC_ST_XRC = 0x3,
2068 MLX5_QPC_ST_DCI = 0x5,
2069 MLX5_QPC_ST_QP0 = 0x7,
2070 MLX5_QPC_ST_QP1 = 0x8,
2071 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2072 MLX5_QPC_ST_REG_UMR = 0xc,
2073};
2074
2075enum {
2076 MLX5_QPC_PM_STATE_ARMED = 0x0,
2077 MLX5_QPC_PM_STATE_REARM = 0x1,
2078 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2079 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2080};
2081
6e44636a
AK		 2082enum {
2083 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2084};
2085
e281682b
SM		 2086enum {
2087 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2088 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2089};
2090
2091enum {
2092 MLX5_QPC_MTU_256_BYTES = 0x1,
2093 MLX5_QPC_MTU_512_BYTES = 0x2,
2094 MLX5_QPC_MTU_1K_BYTES = 0x3,
2095 MLX5_QPC_MTU_2K_BYTES = 0x4,
2096 MLX5_QPC_MTU_4K_BYTES = 0x5,
2097 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2098};
2099
2100enum {
2101 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2102 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2103 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2104 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2105 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2106 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2107 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2108 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2109};
2110
2111enum {
2112 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2113 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2114 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2115};
2116
2117enum {
2118 MLX5_QPC_CS_RES_DISABLE = 0x0,
2119 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2120 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2121};
2122
2123struct mlx5_ifc_qpc_bits {
2124 u8 state[0x4];
84df61eb 2125 u8 lag_tx_port_affinity[0x4];
e281682b 2126 u8 st[0x8];
b4ff3a36 2127 u8 reserved_at_10[0x3];
e281682b 2128 u8 pm_state[0x2];
6e44636a
AK		 2129 u8 reserved_at_15[0x3];
2130 u8 offload_type[0x4];
e281682b 2131 u8 end_padding_mode[0x2];
b4ff3a36 2132 u8 reserved_at_1e[0x2];
e281682b
SM		 2133
2134 u8 wq_signature[0x1];
2135 u8 block_lb_mc[0x1];
2136 u8 atomic_like_write_en[0x1];
2137 u8 latency_sensitive[0x1];
b4ff3a36 2138 u8 reserved_at_24[0x1];
e281682b 2139 u8 drain_sigerr[0x1];
b4ff3a36 2140 u8 reserved_at_26[0x2];
e281682b
SM		 2141 u8 pd[0x18];
2142
2143 u8 mtu[0x3];
2144 u8 log_msg_max[0x5];
b4ff3a36 2145 u8 reserved_at_48[0x1];
e281682b
SM		 2146 u8 log_rq_size[0x4];
2147 u8 log_rq_stride[0x3];
2148 u8 no_sq[0x1];
2149 u8 log_sq_size[0x4];
b4ff3a36 2150 u8 reserved_at_55[0x6];
e281682b 2151 u8 rlky[0x1];
1015c2e8 2152 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2153
2154 u8 counter_set_id[0x8];
2155 u8 uar_page[0x18];
2156
b4ff3a36 2157 u8 reserved_at_80[0x8];
e281682b
SM		 2158 u8 user_index[0x18];
2159
b4ff3a36 2160 u8 reserved_at_a0[0x3];
e281682b
SM		 2161 u8 log_page_size[0x5];
2162 u8 remote_qpn[0x18];
2163
2164 struct mlx5_ifc_ads_bits primary_address_path;
2165
2166 struct mlx5_ifc_ads_bits secondary_address_path;
2167
2168 u8 log_ack_req_freq[0x4];
b4ff3a36 2169 u8 reserved_at_384[0x4];
e281682b 2170 u8 log_sra_max[0x3];
b4ff3a36 2171 u8 reserved_at_38b[0x2];
e281682b
SM		 2172 u8 retry_count[0x3];
2173 u8 rnr_retry[0x3];
b4ff3a36 2174 u8 reserved_at_393[0x1];
e281682b
SM		 2175 u8 fre[0x1];
2176 u8 cur_rnr_retry[0x3];
2177 u8 cur_retry_count[0x3];
b4ff3a36 2178 u8 reserved_at_39b[0x5];
e281682b 2179
b4ff3a36 2180 u8 reserved_at_3a0[0x20];
e281682b 2181
b4ff3a36 2182 u8 reserved_at_3c0[0x8];
e281682b
SM		 2183 u8 next_send_psn[0x18];
2184
b4ff3a36 2185 u8 reserved_at_3e0[0x8];
e281682b
SM		 2186 u8 cqn_snd[0x18];
2187
09a7d9ec
SM		 2188 u8 reserved_at_400[0x8];
2189 u8 deth_sqpn[0x18];
2190
2191 u8 reserved_at_420[0x20];
e281682b 2192
b4ff3a36 2193 u8 reserved_at_440[0x8];
e281682b
SM		 2194 u8 last_acked_psn[0x18];
2195
b4ff3a36 2196 u8 reserved_at_460[0x8];
e281682b
SM		 2197 u8 ssn[0x18];
2198
b4ff3a36 2199 u8 reserved_at_480[0x8];
e281682b 2200 u8 log_rra_max[0x3];
b4ff3a36 2201 u8 reserved_at_48b[0x1];
e281682b
SM		 2202 u8 atomic_mode[0x4];
2203 u8 rre[0x1];
2204 u8 rwe[0x1];
2205 u8 rae[0x1];
b4ff3a36 2206 u8 reserved_at_493[0x1];
e281682b 2207 u8 page_offset[0x6];
b4ff3a36 2208 u8 reserved_at_49a[0x3];
e281682b
SM		 2209 u8 cd_slave_receive[0x1];
2210 u8 cd_slave_send[0x1];
2211 u8 cd_master[0x1];
2212
b4ff3a36 2213 u8 reserved_at_4a0[0x3];
e281682b
SM		 2214 u8 min_rnr_nak[0x5];
2215 u8 next_rcv_psn[0x18];
2216
b4ff3a36 2217 u8 reserved_at_4c0[0x8];
e281682b
SM		 2218 u8 xrcd[0x18];
2219
b4ff3a36 2220 u8 reserved_at_4e0[0x8];
e281682b
SM		 2221 u8 cqn_rcv[0x18];
2222
2223 u8 dbr_addr[0x40];
2224
2225 u8 q_key[0x20];
2226
b4ff3a36 2227 u8 reserved_at_560[0x5];
e281682b 2228 u8 rq_type[0x3];
7486216b 2229 u8 srqn_rmpn_xrqn[0x18];
e281682b 2230
b4ff3a36 2231 u8 reserved_at_580[0x8];
e281682b
SM		 2232 u8 rmsn[0x18];
2233
2234 u8 hw_sq_wqebb_counter[0x10];
2235 u8 sw_sq_wqebb_counter[0x10];
2236
2237 u8 hw_rq_counter[0x20];
2238
2239 u8 sw_rq_counter[0x20];
2240
b4ff3a36 2241 u8 reserved_at_600[0x20];
e281682b 2242
b4ff3a36 2243 u8 reserved_at_620[0xf];
e281682b
SM		 2244 u8 cgs[0x1];
2245 u8 cs_req[0x8];
2246 u8 cs_res[0x8];
2247
2248 u8 dc_access_key[0x40];
2249
b4ff3a36 2250 u8 reserved_at_680[0xc0];
e281682b
SM		 2251};
2252
2253struct mlx5_ifc_roce_addr_layout_bits {
2254 u8 source_l3_address[16][0x8];
2255
b4ff3a36 2256 u8 reserved_at_80[0x3];
e281682b
SM		 2257 u8 vlan_valid[0x1];
2258 u8 vlan_id[0xc];
2259 u8 source_mac_47_32[0x10];
2260
2261 u8 source_mac_31_0[0x20];
2262
b4ff3a36 2263 u8 reserved_at_c0[0x14];
e281682b
SM		 2264 u8 roce_l3_type[0x4];
2265 u8 roce_version[0x8];
2266
b4ff3a36 2267 u8 reserved_at_e0[0x20];
e281682b
SM		 2268};
2269
2270union mlx5_ifc_hca_cap_union_bits {
2271 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2272 struct mlx5_ifc_odp_cap_bits odp_cap;
2273 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2274 struct mlx5_ifc_roce_cap_bits roce_cap;
2275 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2276 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2277 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2278 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2279 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2280 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2281 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2282 u8 reserved_at_0[0x8000];
e281682b
SM		 2283};
2284
2285enum {
2286 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2287 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2288 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2289 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2290 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2291 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2292 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
e281682b
SM		 2293};
2294
2295struct mlx5_ifc_flow_context_bits {
b4ff3a36 2296 u8 reserved_at_0[0x20];
e281682b
SM		 2297
2298 u8 group_id[0x20];
2299
b4ff3a36 2300 u8 reserved_at_40[0x8];
e281682b
SM		 2301 u8 flow_tag[0x18];
2302
b4ff3a36 2303 u8 reserved_at_60[0x10];
e281682b
SM		 2304 u8 action[0x10];
2305
b4ff3a36 2306 u8 reserved_at_80[0x8];
e281682b
SM		 2307 u8 destination_list_size[0x18];
2308
9dc0b289
AV		 2309 u8 reserved_at_a0[0x8];
2310 u8 flow_counter_list_size[0x18];
2311
7adbde20
HHZ		 2312 u8 encap_id[0x20];
2313
2a69cb9f
OG		 2314 u8 modify_header_id[0x20];
2315
2316 u8 reserved_at_100[0x100];
e281682b
SM		 2317
2318 struct mlx5_ifc_fte_match_param_bits match_value;
2319
b4ff3a36 2320 u8 reserved_at_1200[0x600];
e281682b 2321
9dc0b289 2322 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2323};
2324
2325enum {
2326 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2327 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2328};
2329
2330struct mlx5_ifc_xrc_srqc_bits {
2331 u8 state[0x4];
2332 u8 log_xrc_srq_size[0x4];
b4ff3a36 2333 u8 reserved_at_8[0x18];
e281682b
SM		 2334
2335 u8 wq_signature[0x1];
2336 u8 cont_srq[0x1];
b4ff3a36 2337 u8 reserved_at_22[0x1];
e281682b
SM		 2338 u8 rlky[0x1];
2339 u8 basic_cyclic_rcv_wqe[0x1];
2340 u8 log_rq_stride[0x3];
2341 u8 xrcd[0x18];
2342
2343 u8 page_offset[0x6];
b4ff3a36 2344 u8 reserved_at_46[0x2];
e281682b
SM		 2345 u8 cqn[0x18];
2346
b4ff3a36 2347 u8 reserved_at_60[0x20];
e281682b
SM		 2348
2349 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2350 u8 reserved_at_81[0x1];
e281682b
SM		 2351 u8 log_page_size[0x6];
2352 u8 user_index[0x18];
2353
b4ff3a36 2354 u8 reserved_at_a0[0x20];
e281682b 2355
b4ff3a36 2356 u8 reserved_at_c0[0x8];
e281682b
SM		 2357 u8 pd[0x18];
2358
2359 u8 lwm[0x10];
2360 u8 wqe_cnt[0x10];
2361
b4ff3a36 2362 u8 reserved_at_100[0x40];
e281682b
SM		 2363
2364 u8 db_record_addr_h[0x20];
2365
2366 u8 db_record_addr_l[0x1e];
b4ff3a36 2367 u8 reserved_at_17e[0x2];
e281682b 2368
b4ff3a36 2369 u8 reserved_at_180[0x80];
e281682b
SM		 2370};
2371
2372struct mlx5_ifc_traffic_counter_bits {
2373 u8 packets[0x40];
2374
2375 u8 octets[0x40];
2376};
2377
2378struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2379 u8 strict_lag_tx_port_affinity[0x1];
2380 u8 reserved_at_1[0x3];
2381 u8 lag_tx_port_affinity[0x04];
2382
2383 u8 reserved_at_8[0x4];
e281682b 2384 u8 prio[0x4];
b4ff3a36 2385 u8 reserved_at_10[0x10];
e281682b 2386
b4ff3a36 2387 u8 reserved_at_20[0x100];
e281682b 2388
b4ff3a36 2389 u8 reserved_at_120[0x8];
e281682b
SM		 2390 u8 transport_domain[0x18];
2391
500a3d0d
ES		 2392 u8 reserved_at_140[0x8];
2393 u8 underlay_qpn[0x18];
2394 u8 reserved_at_160[0x3a0];
e281682b
SM		 2395};
2396
2397enum {
2398 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2399 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2400};
2401
2402enum {
2403 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2404 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2405};
2406
2407enum {
2be6967c
SM		 2408 MLX5_RX_HASH_FN_NONE = 0x0,
2409 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2410 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2411};
2412
2413enum {
2414 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2415 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2416};
2417
2418struct mlx5_ifc_tirc_bits {
b4ff3a36 2419 u8 reserved_at_0[0x20];
e281682b
SM		 2420
2421 u8 disp_type[0x4];
b4ff3a36 2422 u8 reserved_at_24[0x1c];
e281682b 2423
b4ff3a36 2424 u8 reserved_at_40[0x40];
e281682b 2425
b4ff3a36 2426 u8 reserved_at_80[0x4];
e281682b
SM		 2427 u8 lro_timeout_period_usecs[0x10];
2428 u8 lro_enable_mask[0x4];
2429 u8 lro_max_ip_payload_size[0x8];
2430
b4ff3a36 2431 u8 reserved_at_a0[0x40];
e281682b 2432
b4ff3a36 2433 u8 reserved_at_e0[0x8];
e281682b
SM		 2434 u8 inline_rqn[0x18];
2435
2436 u8 rx_hash_symmetric[0x1];
b4ff3a36 2437 u8 reserved_at_101[0x1];
e281682b 2438 u8 tunneled_offload_en[0x1];
b4ff3a36 2439 u8 reserved_at_103[0x5];
e281682b
SM		 2440 u8 indirect_table[0x18];
2441
2442 u8 rx_hash_fn[0x4];
b4ff3a36 2443 u8 reserved_at_124[0x2];
e281682b
SM		 2444 u8 self_lb_block[0x2];
2445 u8 transport_domain[0x18];
2446
2447 u8 rx_hash_toeplitz_key[10][0x20];
2448
2449 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2450
2451 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2452
b4ff3a36 2453 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2454};
2455
2456enum {
2457 MLX5_SRQC_STATE_GOOD = 0x0,
2458 MLX5_SRQC_STATE_ERROR = 0x1,
2459};
2460
2461struct mlx5_ifc_srqc_bits {
2462 u8 state[0x4];
2463 u8 log_srq_size[0x4];
b4ff3a36 2464 u8 reserved_at_8[0x18];
e281682b
SM		 2465
2466 u8 wq_signature[0x1];
2467 u8 cont_srq[0x1];
b4ff3a36 2468 u8 reserved_at_22[0x1];
e281682b 2469 u8 rlky[0x1];
b4ff3a36 2470 u8 reserved_at_24[0x1];
e281682b
SM		 2471 u8 log_rq_stride[0x3];
2472 u8 xrcd[0x18];
2473
2474 u8 page_offset[0x6];
b4ff3a36 2475 u8 reserved_at_46[0x2];
e281682b
SM		 2476 u8 cqn[0x18];
2477
b4ff3a36 2478 u8 reserved_at_60[0x20];
e281682b 2479
b4ff3a36 2480 u8 reserved_at_80[0x2];
e281682b 2481 u8 log_page_size[0x6];
b4ff3a36 2482 u8 reserved_at_88[0x18];
e281682b 2483
b4ff3a36 2484 u8 reserved_at_a0[0x20];
e281682b 2485
b4ff3a36 2486 u8 reserved_at_c0[0x8];
e281682b
SM		 2487 u8 pd[0x18];
2488
2489 u8 lwm[0x10];
2490 u8 wqe_cnt[0x10];
2491
b4ff3a36 2492 u8 reserved_at_100[0x40];
e281682b 2493
01949d01 2494 u8 dbr_addr[0x40];
e281682b 2495
b4ff3a36 2496 u8 reserved_at_180[0x80];
e281682b
SM		 2497};
2498
2499enum {
2500 MLX5_SQC_STATE_RST = 0x0,
2501 MLX5_SQC_STATE_RDY = 0x1,
2502 MLX5_SQC_STATE_ERR = 0x3,
2503};
2504
2505struct mlx5_ifc_sqc_bits {
2506 u8 rlky[0x1];
2507 u8 cd_master[0x1];
2508 u8 fre[0x1];
2509 u8 flush_in_error_en[0x1];
795b609c 2510 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2511 u8 min_wqe_inline_mode[0x3];
e281682b 2512 u8 state[0x4];
7d5e1423 2513 u8 reg_umr[0x1];
547eede0 2514 u8 allow_swp[0x1];
40817cdb
OG		 2515 u8 hairpin[0x1];
2516 u8 reserved_at_f[0x11];
e281682b 2517
b4ff3a36 2518 u8 reserved_at_20[0x8];
e281682b
SM		 2519 u8 user_index[0x18];
2520
b4ff3a36 2521 u8 reserved_at_40[0x8];
e281682b
SM		 2522 u8 cqn[0x18];
2523
40817cdb
OG		 2524 u8 reserved_at_60[0x8];
2525 u8 hairpin_peer_rq[0x18];
2526
2527 u8 reserved_at_80[0x10];
2528 u8 hairpin_peer_vhca[0x10];
2529
2530 u8 reserved_at_a0[0x50];
e281682b 2531
7486216b 2532 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2533 u8 tis_lst_sz[0x10];
b4ff3a36 2534 u8 reserved_at_110[0x10];
e281682b 2535
b4ff3a36 2536 u8 reserved_at_120[0x40];
e281682b 2537
b4ff3a36 2538 u8 reserved_at_160[0x8];
e281682b
SM		 2539 u8 tis_num_0[0x18];
2540
2541 struct mlx5_ifc_wq_bits wq;
2542};
2543
813f8540
MHY		 2544enum {
2545 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2546 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2547 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2548 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2549};
2550
2551struct mlx5_ifc_scheduling_context_bits {
2552 u8 element_type[0x8];
2553 u8 reserved_at_8[0x18];
2554
2555 u8 element_attributes[0x20];
2556
2557 u8 parent_element_id[0x20];
2558
2559 u8 reserved_at_60[0x40];
2560
2561 u8 bw_share[0x20];
2562
2563 u8 max_average_bw[0x20];
2564
2565 u8 reserved_at_e0[0x120];
2566};
2567
e281682b 2568struct mlx5_ifc_rqtc_bits {
b4ff3a36 2569 u8 reserved_at_0[0xa0];
e281682b 2570
b4ff3a36 2571 u8 reserved_at_a0[0x10];
e281682b
SM		 2572 u8 rqt_max_size[0x10];
2573
b4ff3a36 2574 u8 reserved_at_c0[0x10];
e281682b
SM		 2575 u8 rqt_actual_size[0x10];
2576
b4ff3a36 2577 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2578
2579 struct mlx5_ifc_rq_num_bits rq_num[0];
2580};
2581
2582enum {
2583 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2584 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2585};
2586
2587enum {
2588 MLX5_RQC_STATE_RST = 0x0,
2589 MLX5_RQC_STATE_RDY = 0x1,
2590 MLX5_RQC_STATE_ERR = 0x3,
2591};
2592
2593struct mlx5_ifc_rqc_bits {
2594 u8 rlky[0x1];
03404e8a 2595 u8 delay_drop_en[0x1];
7d5e1423 2596 u8 scatter_fcs[0x1];
e281682b
SM		 2597 u8 vsd[0x1];
2598 u8 mem_rq_type[0x4];
2599 u8 state[0x4];
b4ff3a36 2600 u8 reserved_at_c[0x1];
e281682b 2601 u8 flush_in_error_en[0x1];
40817cdb
OG		 2602 u8 hairpin[0x1];
2603 u8 reserved_at_f[0x11];
e281682b 2604
b4ff3a36 2605 u8 reserved_at_20[0x8];
e281682b
SM		 2606 u8 user_index[0x18];
2607
b4ff3a36 2608 u8 reserved_at_40[0x8];
e281682b
SM		 2609 u8 cqn[0x18];
2610
2611 u8 counter_set_id[0x8];
b4ff3a36 2612 u8 reserved_at_68[0x18];
e281682b 2613
b4ff3a36 2614 u8 reserved_at_80[0x8];
e281682b
SM		 2615 u8 rmpn[0x18];
2616
40817cdb
OG		 2617 u8 reserved_at_a0[0x8];
2618 u8 hairpin_peer_sq[0x18];
2619
2620 u8 reserved_at_c0[0x10];
2621 u8 hairpin_peer_vhca[0x10];
2622
2623 u8 reserved_at_e0[0xa0];
e281682b
SM		 2624
2625 struct mlx5_ifc_wq_bits wq;
2626};
2627
2628enum {
2629 MLX5_RMPC_STATE_RDY = 0x1,
2630 MLX5_RMPC_STATE_ERR = 0x3,
2631};
2632
2633struct mlx5_ifc_rmpc_bits {
b4ff3a36 2634 u8 reserved_at_0[0x8];
e281682b 2635 u8 state[0x4];
b4ff3a36 2636 u8 reserved_at_c[0x14];
e281682b
SM		 2637
2638 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2639 u8 reserved_at_21[0x1f];
e281682b 2640
b4ff3a36 2641 u8 reserved_at_40[0x140];
e281682b
SM		 2642
2643 struct mlx5_ifc_wq_bits wq;
2644};
2645
e281682b 2646struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2647 u8 reserved_at_0[0x5];
2648 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2649 u8 reserved_at_8[0x15];
2650 u8 disable_mc_local_lb[0x1];
2651 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2652 u8 roce_en[0x1];
2653
d82b7318 2654 u8 arm_change_event[0x1];
b4ff3a36 2655 u8 reserved_at_21[0x1a];
d82b7318
SM		 2656 u8 event_on_mtu[0x1];
2657 u8 event_on_promisc_change[0x1];
2658 u8 event_on_vlan_change[0x1];
2659 u8 event_on_mc_address_change[0x1];
2660 u8 event_on_uc_address_change[0x1];
e281682b 2661
32f69e4b
DJ		 2662 u8 reserved_at_40[0xc];
2663
2664 u8 affiliation_criteria[0x4];
2665 u8 affiliated_vhca_id[0x10];
2666
2667 u8 reserved_at_60[0xd0];
d82b7318
SM		 2668
2669 u8 mtu[0x10];
2670
9efa7525
AS		 2671 u8 system_image_guid[0x40];
2672 u8 port_guid[0x40];
2673 u8 node_guid[0x40];
2674
b4ff3a36 2675 u8 reserved_at_200[0x140];
9efa7525 2676 u8 qkey_violation_counter[0x10];
b4ff3a36 2677 u8 reserved_at_350[0x430];
d82b7318
SM		 2678
2679 u8 promisc_uc[0x1];
2680 u8 promisc_mc[0x1];
2681 u8 promisc_all[0x1];
b4ff3a36 2682 u8 reserved_at_783[0x2];
e281682b 2683 u8 allowed_list_type[0x3];
b4ff3a36 2684 u8 reserved_at_788[0xc];
e281682b
SM		 2685 u8 allowed_list_size[0xc];
2686
2687 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2688
b4ff3a36 2689 u8 reserved_at_7e0[0x20];
e281682b
SM		 2690
2691 u8 current_uc_mac_address[0][0x40];
2692};
2693
2694enum {
2695 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2696 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2697 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2698 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2699};
2700
2701struct mlx5_ifc_mkc_bits {
b4ff3a36 2702 u8 reserved_at_0[0x1];
e281682b 2703 u8 free[0x1];
b4ff3a36 2704 u8 reserved_at_2[0xd];
e281682b
SM		 2705 u8 small_fence_on_rdma_read_response[0x1];
2706 u8 umr_en[0x1];
2707 u8 a[0x1];
2708 u8 rw[0x1];
2709 u8 rr[0x1];
2710 u8 lw[0x1];
2711 u8 lr[0x1];
2712 u8 access_mode[0x2];
b4ff3a36 2713 u8 reserved_at_18[0x8];
e281682b
SM		 2714
2715 u8 qpn[0x18];
2716 u8 mkey_7_0[0x8];
2717
b4ff3a36 2718 u8 reserved_at_40[0x20];
e281682b
SM		 2719
2720 u8 length64[0x1];
2721 u8 bsf_en[0x1];
2722 u8 sync_umr[0x1];
b4ff3a36 2723 u8 reserved_at_63[0x2];
e281682b 2724 u8 expected_sigerr_count[0x1];
b4ff3a36 2725 u8 reserved_at_66[0x1];
e281682b
SM		 2726 u8 en_rinval[0x1];
2727 u8 pd[0x18];
2728
2729 u8 start_addr[0x40];
2730
2731 u8 len[0x40];
2732
2733 u8 bsf_octword_size[0x20];
2734
b4ff3a36 2735 u8 reserved_at_120[0x80];
e281682b
SM		 2736
2737 u8 translations_octword_size[0x20];
2738
b4ff3a36 2739 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2740 u8 log_page_size[0x5];
2741
b4ff3a36 2742 u8 reserved_at_1e0[0x20];
e281682b
SM		 2743};
2744
2745struct mlx5_ifc_pkey_bits {
b4ff3a36 2746 u8 reserved_at_0[0x10];
e281682b
SM		 2747 u8 pkey[0x10];
2748};
2749
2750struct mlx5_ifc_array128_auto_bits {
2751 u8 array128_auto[16][0x8];
2752};
2753
2754struct mlx5_ifc_hca_vport_context_bits {
2755 u8 field_select[0x20];
2756
b4ff3a36 2757 u8 reserved_at_20[0xe0];
e281682b
SM		 2758
2759 u8 sm_virt_aware[0x1];
2760 u8 has_smi[0x1];
2761 u8 has_raw[0x1];
2762 u8 grh_required[0x1];
b4ff3a36 2763 u8 reserved_at_104[0xc];
707c4602
MD		 2764 u8 port_physical_state[0x4];
2765 u8 vport_state_policy[0x4];
2766 u8 port_state[0x4];
e281682b
SM		 2767 u8 vport_state[0x4];
2768
b4ff3a36 2769 u8 reserved_at_120[0x20];
707c4602
MD		 2770
2771 u8 system_image_guid[0x40];
e281682b
SM		 2772
2773 u8 port_guid[0x40];
2774
2775 u8 node_guid[0x40];
2776
2777 u8 cap_mask1[0x20];
2778
2779 u8 cap_mask1_field_select[0x20];
2780
2781 u8 cap_mask2[0x20];
2782
2783 u8 cap_mask2_field_select[0x20];
2784
b4ff3a36 2785 u8 reserved_at_280[0x80];
e281682b
SM		 2786
2787 u8 lid[0x10];
b4ff3a36 2788 u8 reserved_at_310[0x4];
e281682b
SM		 2789 u8 init_type_reply[0x4];
2790 u8 lmc[0x3];
2791 u8 subnet_timeout[0x5];
2792
2793 u8 sm_lid[0x10];
2794 u8 sm_sl[0x4];
b4ff3a36 2795 u8 reserved_at_334[0xc];
e281682b
SM		 2796
2797 u8 qkey_violation_counter[0x10];
2798 u8 pkey_violation_counter[0x10];
2799
b4ff3a36 2800 u8 reserved_at_360[0xca0];
e281682b
SM		 2801};
2802
d6666753 2803struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2804 u8 reserved_at_0[0x3];
d6666753
SM		 2805 u8 vport_svlan_strip[0x1];
2806 u8 vport_cvlan_strip[0x1];
2807 u8 vport_svlan_insert[0x1];
2808 u8 vport_cvlan_insert[0x2];
b4ff3a36 2809 u8 reserved_at_8[0x18];
d6666753 2810
b4ff3a36 2811 u8 reserved_at_20[0x20];
d6666753
SM		 2812
2813 u8 svlan_cfi[0x1];
2814 u8 svlan_pcp[0x3];
2815 u8 svlan_id[0xc];
2816 u8 cvlan_cfi[0x1];
2817 u8 cvlan_pcp[0x3];
2818 u8 cvlan_id[0xc];
2819
b4ff3a36 2820 u8 reserved_at_60[0x7a0];
d6666753
SM		 2821};
2822
e281682b
SM		 2823enum {
2824 MLX5_EQC_STATUS_OK = 0x0,
2825 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2826};
2827
2828enum {
2829 MLX5_EQC_ST_ARMED = 0x9,
2830 MLX5_EQC_ST_FIRED = 0xa,
2831};
2832
2833struct mlx5_ifc_eqc_bits {
2834 u8 status[0x4];
b4ff3a36 2835 u8 reserved_at_4[0x9];
e281682b
SM		 2836 u8 ec[0x1];
2837 u8 oi[0x1];
b4ff3a36 2838 u8 reserved_at_f[0x5];
e281682b 2839 u8 st[0x4];
b4ff3a36 2840 u8 reserved_at_18[0x8];
e281682b 2841
b4ff3a36 2842 u8 reserved_at_20[0x20];
e281682b 2843
b4ff3a36 2844 u8 reserved_at_40[0x14];
e281682b 2845 u8 page_offset[0x6];
b4ff3a36 2846 u8 reserved_at_5a[0x6];
e281682b 2847
b4ff3a36 2848 u8 reserved_at_60[0x3];
e281682b
SM		 2849 u8 log_eq_size[0x5];
2850 u8 uar_page[0x18];
2851
b4ff3a36 2852 u8 reserved_at_80[0x20];
e281682b 2853
b4ff3a36 2854 u8 reserved_at_a0[0x18];
e281682b
SM		 2855 u8 intr[0x8];
2856
b4ff3a36 2857 u8 reserved_at_c0[0x3];
e281682b 2858 u8 log_page_size[0x5];
b4ff3a36 2859 u8 reserved_at_c8[0x18];
e281682b 2860
b4ff3a36 2861 u8 reserved_at_e0[0x60];
e281682b 2862
b4ff3a36 2863 u8 reserved_at_140[0x8];
e281682b
SM		 2864 u8 consumer_counter[0x18];
2865
b4ff3a36 2866 u8 reserved_at_160[0x8];
e281682b
SM		 2867 u8 producer_counter[0x18];
2868
b4ff3a36 2869 u8 reserved_at_180[0x80];
e281682b
SM		 2870};
2871
2872enum {
2873 MLX5_DCTC_STATE_ACTIVE = 0x0,
2874 MLX5_DCTC_STATE_DRAINING = 0x1,
2875 MLX5_DCTC_STATE_DRAINED = 0x2,
2876};
2877
2878enum {
2879 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2880 MLX5_DCTC_CS_RES_NA = 0x1,
2881 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2882};
2883
2884enum {
2885 MLX5_DCTC_MTU_256_BYTES = 0x1,
2886 MLX5_DCTC_MTU_512_BYTES = 0x2,
2887 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2888 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2889 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2890};
2891
2892struct mlx5_ifc_dctc_bits {
b4ff3a36 2893 u8 reserved_at_0[0x4];
e281682b 2894 u8 state[0x4];
b4ff3a36 2895 u8 reserved_at_8[0x18];
e281682b 2896
b4ff3a36 2897 u8 reserved_at_20[0x8];
e281682b
SM		 2898 u8 user_index[0x18];
2899
b4ff3a36 2900 u8 reserved_at_40[0x8];
e281682b
SM		 2901 u8 cqn[0x18];
2902
2903 u8 counter_set_id[0x8];
2904 u8 atomic_mode[0x4];
2905 u8 rre[0x1];
2906 u8 rwe[0x1];
2907 u8 rae[0x1];
2908 u8 atomic_like_write_en[0x1];
2909 u8 latency_sensitive[0x1];
2910 u8 rlky[0x1];
2911 u8 free_ar[0x1];
b4ff3a36 2912 u8 reserved_at_73[0xd];
e281682b 2913
b4ff3a36 2914 u8 reserved_at_80[0x8];
e281682b 2915 u8 cs_res[0x8];
b4ff3a36 2916 u8 reserved_at_90[0x3];
e281682b 2917 u8 min_rnr_nak[0x5];
b4ff3a36 2918 u8 reserved_at_98[0x8];
e281682b 2919
b4ff3a36 2920 u8 reserved_at_a0[0x8];
7486216b 2921 u8 srqn_xrqn[0x18];
e281682b 2922
b4ff3a36 2923 u8 reserved_at_c0[0x8];
e281682b
SM		 2924 u8 pd[0x18];
2925
2926 u8 tclass[0x8];
b4ff3a36 2927 u8 reserved_at_e8[0x4];
e281682b
SM		 2928 u8 flow_label[0x14];
2929
2930 u8 dc_access_key[0x40];
2931
b4ff3a36 2932 u8 reserved_at_140[0x5];
e281682b
SM		 2933 u8 mtu[0x3];
2934 u8 port[0x8];
2935 u8 pkey_index[0x10];
2936
b4ff3a36 2937 u8 reserved_at_160[0x8];
e281682b 2938 u8 my_addr_index[0x8];
b4ff3a36 2939 u8 reserved_at_170[0x8];
e281682b
SM		 2940 u8 hop_limit[0x8];
2941
2942 u8 dc_access_key_violation_count[0x20];
2943
b4ff3a36 2944 u8 reserved_at_1a0[0x14];
e281682b
SM		 2945 u8 dei_cfi[0x1];
2946 u8 eth_prio[0x3];
2947 u8 ecn[0x2];
2948 u8 dscp[0x6];
2949
b4ff3a36 2950 u8 reserved_at_1c0[0x40];
e281682b
SM		 2951};
2952
2953enum {
2954 MLX5_CQC_STATUS_OK = 0x0,
2955 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2956 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2957};
2958
2959enum {
2960 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2961 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2962};
2963
2964enum {
2965 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2966 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2967 MLX5_CQC_ST_FIRED = 0xa,
2968};
2969
7d5e1423
SM		 2970enum {
2971 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2972 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2973 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2974};
2975
e281682b
SM		 2976struct mlx5_ifc_cqc_bits {
2977 u8 status[0x4];
b4ff3a36 2978 u8 reserved_at_4[0x4];
e281682b
SM		 2979 u8 cqe_sz[0x3];
2980 u8 cc[0x1];
b4ff3a36 2981 u8 reserved_at_c[0x1];
e281682b
SM		 2982 u8 scqe_break_moderation_en[0x1];
2983 u8 oi[0x1];
7d5e1423
SM		 2984 u8 cq_period_mode[0x2];
2985 u8 cqe_comp_en[0x1];
e281682b
SM		 2986 u8 mini_cqe_res_format[0x2];
2987 u8 st[0x4];
b4ff3a36 2988 u8 reserved_at_18[0x8];
e281682b 2989
b4ff3a36 2990 u8 reserved_at_20[0x20];
e281682b 2991
b4ff3a36 2992 u8 reserved_at_40[0x14];
e281682b 2993 u8 page_offset[0x6];
b4ff3a36 2994 u8 reserved_at_5a[0x6];
e281682b 2995
b4ff3a36 2996 u8 reserved_at_60[0x3];
e281682b
SM		 2997 u8 log_cq_size[0x5];
2998 u8 uar_page[0x18];
2999
b4ff3a36 3000 u8 reserved_at_80[0x4];
e281682b
SM		 3001 u8 cq_period[0xc];
3002 u8 cq_max_count[0x10];
3003
b4ff3a36 3004 u8 reserved_at_a0[0x18];
e281682b
SM		 3005 u8 c_eqn[0x8];
3006
b4ff3a36 3007 u8 reserved_at_c0[0x3];
e281682b 3008 u8 log_page_size[0x5];
b4ff3a36 3009 u8 reserved_at_c8[0x18];
e281682b 3010
b4ff3a36 3011 u8 reserved_at_e0[0x20];
e281682b 3012
b4ff3a36 3013 u8 reserved_at_100[0x8];
e281682b
SM		 3014 u8 last_notified_index[0x18];
3015
b4ff3a36 3016 u8 reserved_at_120[0x8];
e281682b
SM		 3017 u8 last_solicit_index[0x18];
3018
b4ff3a36 3019 u8 reserved_at_140[0x8];
e281682b
SM		 3020 u8 consumer_counter[0x18];
3021
b4ff3a36 3022 u8 reserved_at_160[0x8];
e281682b
SM		 3023 u8 producer_counter[0x18];
3024
b4ff3a36 3025 u8 reserved_at_180[0x40];
e281682b
SM		 3026
3027 u8 dbr_addr[0x40];
3028};
3029
3030union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3031 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3032 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3033 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3034 u8 reserved_at_0[0x800];
e281682b
SM		 3035};
3036
3037struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3038 u8 reserved_at_0[0xc0];
e281682b 3039
b4ff3a36 3040 u8 reserved_at_c0[0x8];
211e6c80
MD		 3041 u8 ieee_vendor_id[0x18];
3042
b4ff3a36 3043 u8 reserved_at_e0[0x10];
e281682b
SM		 3044 u8 vsd_vendor_id[0x10];
3045
3046 u8 vsd[208][0x8];
3047
3048 u8 vsd_contd_psid[16][0x8];
3049};
3050
7486216b
SM		 3051enum {
3052 MLX5_XRQC_STATE_GOOD = 0x0,
3053 MLX5_XRQC_STATE_ERROR = 0x1,
3054};
3055
3056enum {
3057 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3058 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3059};
3060
3061enum {
3062 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3063};
3064
3065struct mlx5_ifc_tag_matching_topology_context_bits {
3066 u8 log_matching_list_sz[0x4];
3067 u8 reserved_at_4[0xc];
3068 u8 append_next_index[0x10];
3069
3070 u8 sw_phase_cnt[0x10];
3071 u8 hw_phase_cnt[0x10];
3072
3073 u8 reserved_at_40[0x40];
3074};
3075
3076struct mlx5_ifc_xrqc_bits {
3077 u8 state[0x4];
3078 u8 rlkey[0x1];
3079 u8 reserved_at_5[0xf];
3080 u8 topology[0x4];
3081 u8 reserved_at_18[0x4];
3082 u8 offload[0x4];
3083
3084 u8 reserved_at_20[0x8];
3085 u8 user_index[0x18];
3086
3087 u8 reserved_at_40[0x8];
3088 u8 cqn[0x18];
3089
3090 u8 reserved_at_60[0xa0];
3091
3092 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3093
6e44636a 3094 u8 reserved_at_180[0x280];
7486216b
SM		 3095
3096 struct mlx5_ifc_wq_bits wq;
3097};
3098
e281682b
SM		 3099union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3100 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3101 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3102 u8 reserved_at_0[0x20];
e281682b
SM		 3103};
3104
3105union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3106 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3107 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3108 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3109 u8 reserved_at_0[0x20];
e281682b
SM		 3110};
3111
3112union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3113 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3114 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3115 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3116 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3117 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3118 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3119 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3120 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3121 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3122 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3123 u8 reserved_at_0[0x7c0];
e281682b
SM		 3124};
3125
8ed1a630
GP		 3126union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3127 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3128 u8 reserved_at_0[0x7c0];
3129};
3130
e281682b
SM		 3131union mlx5_ifc_event_auto_bits {
3132 struct mlx5_ifc_comp_event_bits comp_event;
3133 struct mlx5_ifc_dct_events_bits dct_events;
3134 struct mlx5_ifc_qp_events_bits qp_events;
3135 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3136 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3137 struct mlx5_ifc_cq_error_bits cq_error;
3138 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3139 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3140 struct mlx5_ifc_gpio_event_bits gpio_event;
3141 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3142 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3143 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3144 u8 reserved_at_0[0xe0];
e281682b
SM		 3145};
3146
3147struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3148 u8 reserved_at_0[0x100];
e281682b
SM		 3149
3150 u8 assert_existptr[0x20];
3151
3152 u8 assert_callra[0x20];
3153
b4ff3a36 3154 u8 reserved_at_140[0x40];
e281682b
SM		 3155
3156 u8 fw_version[0x20];
3157
3158 u8 hw_id[0x20];
3159
b4ff3a36 3160 u8 reserved_at_1c0[0x20];
e281682b
SM		 3161
3162 u8 irisc_index[0x8];
3163 u8 synd[0x8];
3164 u8 ext_synd[0x10];
3165};
3166
3167struct mlx5_ifc_register_loopback_control_bits {
3168 u8 no_lb[0x1];
b4ff3a36 3169 u8 reserved_at_1[0x7];
e281682b 3170 u8 port[0x8];
b4ff3a36 3171 u8 reserved_at_10[0x10];
e281682b 3172
b4ff3a36 3173 u8 reserved_at_20[0x60];
e281682b
SM		 3174};
3175
813f8540
MHY		 3176struct mlx5_ifc_vport_tc_element_bits {
3177 u8 traffic_class[0x4];
3178 u8 reserved_at_4[0xc];
3179 u8 vport_number[0x10];
3180};
3181
3182struct mlx5_ifc_vport_element_bits {
3183 u8 reserved_at_0[0x10];
3184 u8 vport_number[0x10];
3185};
3186
3187enum {
3188 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3189 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3190 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3191};
3192
3193struct mlx5_ifc_tsar_element_bits {
3194 u8 reserved_at_0[0x8];
3195 u8 tsar_type[0x8];
3196 u8 reserved_at_10[0x10];
3197};
3198
8812c24d
MD		 3199enum {
3200 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3201 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3202};
3203
e281682b
SM		 3204struct mlx5_ifc_teardown_hca_out_bits {
3205 u8 status[0x8];
b4ff3a36 3206 u8 reserved_at_8[0x18];
e281682b
SM		 3207
3208 u8 syndrome[0x20];
3209
8812c24d
MD		 3210 u8 reserved_at_40[0x3f];
3211
3212 u8 force_state[0x1];
e281682b
SM		 3213};
3214
3215enum {
3216 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3217 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3218};
3219
3220struct mlx5_ifc_teardown_hca_in_bits {
3221 u8 opcode[0x10];
b4ff3a36 3222 u8 reserved_at_10[0x10];
e281682b 3223
b4ff3a36 3224 u8 reserved_at_20[0x10];
e281682b
SM		 3225 u8 op_mod[0x10];
3226
b4ff3a36 3227 u8 reserved_at_40[0x10];
e281682b
SM		 3228 u8 profile[0x10];
3229
b4ff3a36 3230 u8 reserved_at_60[0x20];
e281682b
SM		 3231};
3232
3233struct mlx5_ifc_sqerr2rts_qp_out_bits {
3234 u8 status[0x8];
b4ff3a36 3235 u8 reserved_at_8[0x18];
e281682b
SM		 3236
3237 u8 syndrome[0x20];
3238
b4ff3a36 3239 u8 reserved_at_40[0x40];
e281682b
SM		 3240};
3241
3242struct mlx5_ifc_sqerr2rts_qp_in_bits {
3243 u8 opcode[0x10];
b4ff3a36 3244 u8 reserved_at_10[0x10];
e281682b 3245
b4ff3a36 3246 u8 reserved_at_20[0x10];
e281682b
SM		 3247 u8 op_mod[0x10];
3248
b4ff3a36 3249 u8 reserved_at_40[0x8];
e281682b
SM		 3250 u8 qpn[0x18];
3251
b4ff3a36 3252 u8 reserved_at_60[0x20];
e281682b
SM		 3253
3254 u8 opt_param_mask[0x20];
3255
b4ff3a36 3256 u8 reserved_at_a0[0x20];
e281682b
SM		 3257
3258 struct mlx5_ifc_qpc_bits qpc;
3259
b4ff3a36 3260 u8 reserved_at_800[0x80];
e281682b
SM		 3261};
3262
3263struct mlx5_ifc_sqd2rts_qp_out_bits {
3264 u8 status[0x8];
b4ff3a36 3265 u8 reserved_at_8[0x18];
e281682b
SM		 3266
3267 u8 syndrome[0x20];
3268
b4ff3a36 3269 u8 reserved_at_40[0x40];
e281682b
SM		 3270};
3271
3272struct mlx5_ifc_sqd2rts_qp_in_bits {
3273 u8 opcode[0x10];
b4ff3a36 3274 u8 reserved_at_10[0x10];
e281682b 3275
b4ff3a36 3276 u8 reserved_at_20[0x10];
e281682b
SM		 3277 u8 op_mod[0x10];
3278
b4ff3a36 3279 u8 reserved_at_40[0x8];
e281682b
SM		 3280 u8 qpn[0x18];
3281
b4ff3a36 3282 u8 reserved_at_60[0x20];
e281682b
SM		 3283
3284 u8 opt_param_mask[0x20];
3285
b4ff3a36 3286 u8 reserved_at_a0[0x20];
e281682b
SM		 3287
3288 struct mlx5_ifc_qpc_bits qpc;
3289
b4ff3a36 3290 u8 reserved_at_800[0x80];
e281682b
SM		 3291};
3292
3293struct mlx5_ifc_set_roce_address_out_bits {
3294 u8 status[0x8];
b4ff3a36 3295 u8 reserved_at_8[0x18];
e281682b
SM		 3296
3297 u8 syndrome[0x20];
3298
b4ff3a36 3299 u8 reserved_at_40[0x40];
e281682b
SM		 3300};
3301
3302struct mlx5_ifc_set_roce_address_in_bits {
3303 u8 opcode[0x10];
b4ff3a36 3304 u8 reserved_at_10[0x10];
e281682b 3305
b4ff3a36 3306 u8 reserved_at_20[0x10];
e281682b
SM		 3307 u8 op_mod[0x10];
3308
3309 u8 roce_address_index[0x10];
32f69e4b
DJ		 3310 u8 reserved_at_50[0xc];
3311 u8 vhca_port_num[0x4];
e281682b 3312
b4ff3a36 3313 u8 reserved_at_60[0x20];
e281682b
SM		 3314
3315 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3316};
3317
3318struct mlx5_ifc_set_mad_demux_out_bits {
3319 u8 status[0x8];
b4ff3a36 3320 u8 reserved_at_8[0x18];
e281682b
SM		 3321
3322 u8 syndrome[0x20];
3323
b4ff3a36 3324 u8 reserved_at_40[0x40];
e281682b
SM		 3325};
3326
3327enum {
3328 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3329 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3330};
3331
3332struct mlx5_ifc_set_mad_demux_in_bits {
3333 u8 opcode[0x10];
b4ff3a36 3334 u8 reserved_at_10[0x10];
e281682b 3335
b4ff3a36 3336 u8 reserved_at_20[0x10];
e281682b
SM		 3337 u8 op_mod[0x10];
3338
b4ff3a36 3339 u8 reserved_at_40[0x20];
e281682b 3340
b4ff3a36 3341 u8 reserved_at_60[0x6];
e281682b 3342 u8 demux_mode[0x2];
b4ff3a36 3343 u8 reserved_at_68[0x18];
e281682b
SM		 3344};
3345
3346struct mlx5_ifc_set_l2_table_entry_out_bits {
3347 u8 status[0x8];
b4ff3a36 3348 u8 reserved_at_8[0x18];
e281682b
SM		 3349
3350 u8 syndrome[0x20];
3351
b4ff3a36 3352 u8 reserved_at_40[0x40];
e281682b
SM		 3353};
3354
3355struct mlx5_ifc_set_l2_table_entry_in_bits {
3356 u8 opcode[0x10];
b4ff3a36 3357 u8 reserved_at_10[0x10];
e281682b 3358
b4ff3a36 3359 u8 reserved_at_20[0x10];
e281682b
SM		 3360 u8 op_mod[0x10];
3361
b4ff3a36 3362 u8 reserved_at_40[0x60];
e281682b 3363
b4ff3a36 3364 u8 reserved_at_a0[0x8];
e281682b
SM		 3365 u8 table_index[0x18];
3366
b4ff3a36 3367 u8 reserved_at_c0[0x20];
e281682b 3368
b4ff3a36 3369 u8 reserved_at_e0[0x13];
e281682b
SM		 3370 u8 vlan_valid[0x1];
3371 u8 vlan[0xc];
3372
3373 struct mlx5_ifc_mac_address_layout_bits mac_address;
3374
b4ff3a36 3375 u8 reserved_at_140[0xc0];
e281682b
SM		 3376};
3377
3378struct mlx5_ifc_set_issi_out_bits {
3379 u8 status[0x8];
b4ff3a36 3380 u8 reserved_at_8[0x18];
e281682b
SM		 3381
3382 u8 syndrome[0x20];
3383
b4ff3a36 3384 u8 reserved_at_40[0x40];
e281682b
SM		 3385};
3386
3387struct mlx5_ifc_set_issi_in_bits {
3388 u8 opcode[0x10];
b4ff3a36 3389 u8 reserved_at_10[0x10];
e281682b 3390
b4ff3a36 3391 u8 reserved_at_20[0x10];
e281682b
SM		 3392 u8 op_mod[0x10];
3393
b4ff3a36 3394 u8 reserved_at_40[0x10];
e281682b
SM		 3395 u8 current_issi[0x10];
3396
b4ff3a36 3397 u8 reserved_at_60[0x20];
e281682b
SM		 3398};
3399
3400struct mlx5_ifc_set_hca_cap_out_bits {
3401 u8 status[0x8];
b4ff3a36 3402 u8 reserved_at_8[0x18];
e281682b
SM		 3403
3404 u8 syndrome[0x20];
3405
b4ff3a36 3406 u8 reserved_at_40[0x40];
e281682b
SM		 3407};
3408
3409struct mlx5_ifc_set_hca_cap_in_bits {
3410 u8 opcode[0x10];
b4ff3a36 3411 u8 reserved_at_10[0x10];
e281682b 3412
b4ff3a36 3413 u8 reserved_at_20[0x10];
e281682b
SM		 3414 u8 op_mod[0x10];
3415
b4ff3a36 3416 u8 reserved_at_40[0x40];
e281682b
SM		 3417
3418 union mlx5_ifc_hca_cap_union_bits capability;
3419};
3420
26a81453
MG		 3421enum {
3422 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3423 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3424 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3425 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3426};
3427
e281682b
SM		 3428struct mlx5_ifc_set_fte_out_bits {
3429 u8 status[0x8];
b4ff3a36 3430 u8 reserved_at_8[0x18];
e281682b
SM		 3431
3432 u8 syndrome[0x20];
3433
b4ff3a36 3434 u8 reserved_at_40[0x40];
e281682b
SM		 3435};
3436
3437struct mlx5_ifc_set_fte_in_bits {
3438 u8 opcode[0x10];
b4ff3a36 3439 u8 reserved_at_10[0x10];
e281682b 3440
b4ff3a36 3441 u8 reserved_at_20[0x10];
e281682b
SM		 3442 u8 op_mod[0x10];
3443
7d5e1423
SM		 3444 u8 other_vport[0x1];
3445 u8 reserved_at_41[0xf];
3446 u8 vport_number[0x10];
3447
3448 u8 reserved_at_60[0x20];
e281682b
SM		 3449
3450 u8 table_type[0x8];
b4ff3a36 3451 u8 reserved_at_88[0x18];
e281682b 3452
b4ff3a36 3453 u8 reserved_at_a0[0x8];
e281682b
SM		 3454 u8 table_id[0x18];
3455
b4ff3a36 3456 u8 reserved_at_c0[0x18];
26a81453
MG		 3457 u8 modify_enable_mask[0x8];
3458
b4ff3a36 3459 u8 reserved_at_e0[0x20];
e281682b
SM		 3460
3461 u8 flow_index[0x20];
3462
b4ff3a36 3463 u8 reserved_at_120[0xe0];
e281682b
SM		 3464
3465 struct mlx5_ifc_flow_context_bits flow_context;
3466};
3467
3468struct mlx5_ifc_rts2rts_qp_out_bits {
3469 u8 status[0x8];
b4ff3a36 3470 u8 reserved_at_8[0x18];
e281682b
SM		 3471
3472 u8 syndrome[0x20];
3473
b4ff3a36 3474 u8 reserved_at_40[0x40];
e281682b
SM		 3475};
3476
3477struct mlx5_ifc_rts2rts_qp_in_bits {
3478 u8 opcode[0x10];
b4ff3a36 3479 u8 reserved_at_10[0x10];
e281682b 3480
b4ff3a36 3481 u8 reserved_at_20[0x10];
e281682b
SM		 3482 u8 op_mod[0x10];
3483
b4ff3a36 3484 u8 reserved_at_40[0x8];
e281682b
SM		 3485 u8 qpn[0x18];
3486
b4ff3a36 3487 u8 reserved_at_60[0x20];
e281682b
SM		 3488
3489 u8 opt_param_mask[0x20];
3490
b4ff3a36 3491 u8 reserved_at_a0[0x20];
e281682b
SM		 3492
3493 struct mlx5_ifc_qpc_bits qpc;
3494
b4ff3a36 3495 u8 reserved_at_800[0x80];
e281682b
SM		 3496};
3497
3498struct mlx5_ifc_rtr2rts_qp_out_bits {
3499 u8 status[0x8];
b4ff3a36 3500 u8 reserved_at_8[0x18];
e281682b
SM		 3501
3502 u8 syndrome[0x20];
3503
b4ff3a36 3504 u8 reserved_at_40[0x40];
e281682b
SM		 3505};
3506
3507struct mlx5_ifc_rtr2rts_qp_in_bits {
3508 u8 opcode[0x10];
b4ff3a36 3509 u8 reserved_at_10[0x10];
e281682b 3510
b4ff3a36 3511 u8 reserved_at_20[0x10];
e281682b
SM		 3512 u8 op_mod[0x10];
3513
b4ff3a36 3514 u8 reserved_at_40[0x8];
e281682b
SM		 3515 u8 qpn[0x18];
3516
b4ff3a36 3517 u8 reserved_at_60[0x20];
e281682b
SM		 3518
3519 u8 opt_param_mask[0x20];
3520
b4ff3a36 3521 u8 reserved_at_a0[0x20];
e281682b
SM		 3522
3523 struct mlx5_ifc_qpc_bits qpc;
3524
b4ff3a36 3525 u8 reserved_at_800[0x80];
e281682b
SM		 3526};
3527
3528struct mlx5_ifc_rst2init_qp_out_bits {
3529 u8 status[0x8];
b4ff3a36 3530 u8 reserved_at_8[0x18];
e281682b
SM		 3531
3532 u8 syndrome[0x20];
3533
b4ff3a36 3534 u8 reserved_at_40[0x40];
e281682b
SM		 3535};
3536
3537struct mlx5_ifc_rst2init_qp_in_bits {
3538 u8 opcode[0x10];
b4ff3a36 3539 u8 reserved_at_10[0x10];
e281682b 3540
b4ff3a36 3541 u8 reserved_at_20[0x10];
e281682b
SM		 3542 u8 op_mod[0x10];
3543
b4ff3a36 3544 u8 reserved_at_40[0x8];
e281682b
SM		 3545 u8 qpn[0x18];
3546
b4ff3a36 3547 u8 reserved_at_60[0x20];
e281682b
SM		 3548
3549 u8 opt_param_mask[0x20];
3550
b4ff3a36 3551 u8 reserved_at_a0[0x20];
e281682b
SM		 3552
3553 struct mlx5_ifc_qpc_bits qpc;
3554
b4ff3a36 3555 u8 reserved_at_800[0x80];
e281682b
SM		 3556};
3557
7486216b
SM		 3558struct mlx5_ifc_query_xrq_out_bits {
3559 u8 status[0x8];
3560 u8 reserved_at_8[0x18];
3561
3562 u8 syndrome[0x20];
3563
3564 u8 reserved_at_40[0x40];
3565
3566 struct mlx5_ifc_xrqc_bits xrq_context;
3567};
3568
3569struct mlx5_ifc_query_xrq_in_bits {
3570 u8 opcode[0x10];
3571 u8 reserved_at_10[0x10];
3572
3573 u8 reserved_at_20[0x10];
3574 u8 op_mod[0x10];
3575
3576 u8 reserved_at_40[0x8];
3577 u8 xrqn[0x18];
3578
3579 u8 reserved_at_60[0x20];
3580};
3581
e281682b
SM		 3582struct mlx5_ifc_query_xrc_srq_out_bits {
3583 u8 status[0x8];
b4ff3a36 3584 u8 reserved_at_8[0x18];
e281682b
SM		 3585
3586 u8 syndrome[0x20];
3587
b4ff3a36 3588 u8 reserved_at_40[0x40];
e281682b
SM		 3589
3590 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3591
b4ff3a36 3592 u8 reserved_at_280[0x600];
e281682b
SM		 3593
3594 u8 pas[0][0x40];
3595};
3596
3597struct mlx5_ifc_query_xrc_srq_in_bits {
3598 u8 opcode[0x10];
b4ff3a36 3599 u8 reserved_at_10[0x10];
e281682b 3600
b4ff3a36 3601 u8 reserved_at_20[0x10];
e281682b
SM		 3602 u8 op_mod[0x10];
3603
b4ff3a36 3604 u8 reserved_at_40[0x8];
e281682b
SM		 3605 u8 xrc_srqn[0x18];
3606
b4ff3a36 3607 u8 reserved_at_60[0x20];
e281682b
SM		 3608};
3609
3610enum {
3611 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3612 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3613};
3614
3615struct mlx5_ifc_query_vport_state_out_bits {
3616 u8 status[0x8];
b4ff3a36 3617 u8 reserved_at_8[0x18];
e281682b
SM		 3618
3619 u8 syndrome[0x20];
3620
b4ff3a36 3621 u8 reserved_at_40[0x20];
e281682b 3622
b4ff3a36 3623 u8 reserved_at_60[0x18];
e281682b
SM		 3624 u8 admin_state[0x4];
3625 u8 state[0x4];
3626};
3627
3628enum {
3629 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3630 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3631};
3632
3633struct mlx5_ifc_query_vport_state_in_bits {
3634 u8 opcode[0x10];
b4ff3a36 3635 u8 reserved_at_10[0x10];
e281682b 3636
b4ff3a36 3637 u8 reserved_at_20[0x10];
e281682b
SM		 3638 u8 op_mod[0x10];
3639
3640 u8 other_vport[0x1];
b4ff3a36 3641 u8 reserved_at_41[0xf];
e281682b
SM		 3642 u8 vport_number[0x10];
3643
b4ff3a36 3644 u8 reserved_at_60[0x20];
e281682b
SM		 3645};
3646
3647struct mlx5_ifc_query_vport_counter_out_bits {
3648 u8 status[0x8];
b4ff3a36 3649 u8 reserved_at_8[0x18];
e281682b
SM		 3650
3651 u8 syndrome[0x20];
3652
b4ff3a36 3653 u8 reserved_at_40[0x40];
e281682b
SM		 3654
3655 struct mlx5_ifc_traffic_counter_bits received_errors;
3656
3657 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3658
3659 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3660
3661 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3662
3663 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3664
3665 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3666
3667 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3668
3669 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3670
3671 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3672
3673 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3674
3675 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3676
3677 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3678
b4ff3a36 3679 u8 reserved_at_680[0xa00];
e281682b
SM		 3680};
3681
3682enum {
3683 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3684};
3685
3686struct mlx5_ifc_query_vport_counter_in_bits {
3687 u8 opcode[0x10];
b4ff3a36 3688 u8 reserved_at_10[0x10];
e281682b 3689
b4ff3a36 3690 u8 reserved_at_20[0x10];
e281682b
SM		 3691 u8 op_mod[0x10];
3692
3693 u8 other_vport[0x1];
b54ba277
MY		 3694 u8 reserved_at_41[0xb];
3695 u8 port_num[0x4];
e281682b
SM		 3696 u8 vport_number[0x10];
3697
b4ff3a36 3698 u8 reserved_at_60[0x60];
e281682b
SM		 3699
3700 u8 clear[0x1];
b4ff3a36 3701 u8 reserved_at_c1[0x1f];
e281682b 3702
b4ff3a36 3703 u8 reserved_at_e0[0x20];
e281682b
SM		 3704};
3705
3706struct mlx5_ifc_query_tis_out_bits {
3707 u8 status[0x8];
b4ff3a36 3708 u8 reserved_at_8[0x18];
e281682b
SM		 3709
3710 u8 syndrome[0x20];
3711
b4ff3a36 3712 u8 reserved_at_40[0x40];
e281682b
SM		 3713
3714 struct mlx5_ifc_tisc_bits tis_context;
3715};
3716
3717struct mlx5_ifc_query_tis_in_bits {
3718 u8 opcode[0x10];
b4ff3a36 3719 u8 reserved_at_10[0x10];
e281682b 3720
b4ff3a36 3721 u8 reserved_at_20[0x10];
e281682b
SM		 3722 u8 op_mod[0x10];
3723
b4ff3a36 3724 u8 reserved_at_40[0x8];
e281682b
SM		 3725 u8 tisn[0x18];
3726
b4ff3a36 3727 u8 reserved_at_60[0x20];
e281682b
SM		 3728};
3729
3730struct mlx5_ifc_query_tir_out_bits {
3731 u8 status[0x8];
b4ff3a36 3732 u8 reserved_at_8[0x18];
e281682b
SM		 3733
3734 u8 syndrome[0x20];
3735
b4ff3a36 3736 u8 reserved_at_40[0xc0];
e281682b
SM		 3737
3738 struct mlx5_ifc_tirc_bits tir_context;
3739};
3740
3741struct mlx5_ifc_query_tir_in_bits {
3742 u8 opcode[0x10];
b4ff3a36 3743 u8 reserved_at_10[0x10];
e281682b 3744
b4ff3a36 3745 u8 reserved_at_20[0x10];
e281682b
SM		 3746 u8 op_mod[0x10];
3747
b4ff3a36 3748 u8 reserved_at_40[0x8];
e281682b
SM		 3749 u8 tirn[0x18];
3750
b4ff3a36 3751 u8 reserved_at_60[0x20];
e281682b
SM		 3752};
3753
3754struct mlx5_ifc_query_srq_out_bits {
3755 u8 status[0x8];
b4ff3a36 3756 u8 reserved_at_8[0x18];
e281682b
SM		 3757
3758 u8 syndrome[0x20];
3759
b4ff3a36 3760 u8 reserved_at_40[0x40];
e281682b
SM		 3761
3762 struct mlx5_ifc_srqc_bits srq_context_entry;
3763
b4ff3a36 3764 u8 reserved_at_280[0x600];
e281682b
SM		 3765
3766 u8 pas[0][0x40];
3767};
3768
3769struct mlx5_ifc_query_srq_in_bits {
3770 u8 opcode[0x10];
b4ff3a36 3771 u8 reserved_at_10[0x10];
e281682b 3772
b4ff3a36 3773 u8 reserved_at_20[0x10];
e281682b
SM		 3774 u8 op_mod[0x10];
3775
b4ff3a36 3776 u8 reserved_at_40[0x8];
e281682b
SM		 3777 u8 srqn[0x18];
3778
b4ff3a36 3779 u8 reserved_at_60[0x20];
e281682b
SM		 3780};
3781
3782struct mlx5_ifc_query_sq_out_bits {
3783 u8 status[0x8];
b4ff3a36 3784 u8 reserved_at_8[0x18];
e281682b
SM		 3785
3786 u8 syndrome[0x20];
3787
b4ff3a36 3788 u8 reserved_at_40[0xc0];
e281682b
SM		 3789
3790 struct mlx5_ifc_sqc_bits sq_context;
3791};
3792
3793struct mlx5_ifc_query_sq_in_bits {
3794 u8 opcode[0x10];
b4ff3a36 3795 u8 reserved_at_10[0x10];
e281682b 3796
b4ff3a36 3797 u8 reserved_at_20[0x10];
e281682b
SM		 3798 u8 op_mod[0x10];
3799
b4ff3a36 3800 u8 reserved_at_40[0x8];
e281682b
SM		 3801 u8 sqn[0x18];
3802
b4ff3a36 3803 u8 reserved_at_60[0x20];
e281682b
SM		 3804};
3805
3806struct mlx5_ifc_query_special_contexts_out_bits {
3807 u8 status[0x8];
b4ff3a36 3808 u8 reserved_at_8[0x18];
e281682b
SM		 3809
3810 u8 syndrome[0x20];
3811
ec22eb53 3812 u8 dump_fill_mkey[0x20];
e281682b
SM		 3813
3814 u8 resd_lkey[0x20];
bcda1aca
AK		 3815
3816 u8 null_mkey[0x20];
3817
3818 u8 reserved_at_a0[0x60];
e281682b
SM		 3819};
3820
3821struct mlx5_ifc_query_special_contexts_in_bits {
3822 u8 opcode[0x10];
b4ff3a36 3823 u8 reserved_at_10[0x10];
e281682b 3824
b4ff3a36 3825 u8 reserved_at_20[0x10];
e281682b
SM		 3826 u8 op_mod[0x10];
3827
b4ff3a36 3828 u8 reserved_at_40[0x40];
e281682b
SM		 3829};
3830
813f8540
MHY		 3831struct mlx5_ifc_query_scheduling_element_out_bits {
3832 u8 opcode[0x10];
3833 u8 reserved_at_10[0x10];
3834
3835 u8 reserved_at_20[0x10];
3836 u8 op_mod[0x10];
3837
3838 u8 reserved_at_40[0xc0];
3839
3840 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3841
3842 u8 reserved_at_300[0x100];
3843};
3844
3845enum {
3846 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3847};
3848
3849struct mlx5_ifc_query_scheduling_element_in_bits {
3850 u8 opcode[0x10];
3851 u8 reserved_at_10[0x10];
3852
3853 u8 reserved_at_20[0x10];
3854 u8 op_mod[0x10];
3855
3856 u8 scheduling_hierarchy[0x8];
3857 u8 reserved_at_48[0x18];
3858
3859 u8 scheduling_element_id[0x20];
3860
3861 u8 reserved_at_80[0x180];
3862};
3863
e281682b
SM		 3864struct mlx5_ifc_query_rqt_out_bits {
3865 u8 status[0x8];
b4ff3a36 3866 u8 reserved_at_8[0x18];
e281682b
SM		 3867
3868 u8 syndrome[0x20];
3869
b4ff3a36 3870 u8 reserved_at_40[0xc0];
e281682b
SM		 3871
3872 struct mlx5_ifc_rqtc_bits rqt_context;
3873};
3874
3875struct mlx5_ifc_query_rqt_in_bits {
3876 u8 opcode[0x10];
b4ff3a36 3877 u8 reserved_at_10[0x10];
e281682b 3878
b4ff3a36 3879 u8 reserved_at_20[0x10];
e281682b
SM		 3880 u8 op_mod[0x10];
3881
b4ff3a36 3882 u8 reserved_at_40[0x8];
e281682b
SM		 3883 u8 rqtn[0x18];
3884
b4ff3a36 3885 u8 reserved_at_60[0x20];
e281682b
SM		 3886};
3887
3888struct mlx5_ifc_query_rq_out_bits {
3889 u8 status[0x8];
b4ff3a36 3890 u8 reserved_at_8[0x18];
e281682b
SM		 3891
3892 u8 syndrome[0x20];
3893
b4ff3a36 3894 u8 reserved_at_40[0xc0];
e281682b
SM		 3895
3896 struct mlx5_ifc_rqc_bits rq_context;
3897};
3898
3899struct mlx5_ifc_query_rq_in_bits {
3900 u8 opcode[0x10];
b4ff3a36 3901 u8 reserved_at_10[0x10];
e281682b 3902
b4ff3a36 3903 u8 reserved_at_20[0x10];
e281682b
SM		 3904 u8 op_mod[0x10];
3905
b4ff3a36 3906 u8 reserved_at_40[0x8];
e281682b
SM		 3907 u8 rqn[0x18];
3908
b4ff3a36 3909 u8 reserved_at_60[0x20];
e281682b
SM		 3910};
3911
3912struct mlx5_ifc_query_roce_address_out_bits {
3913 u8 status[0x8];
b4ff3a36 3914 u8 reserved_at_8[0x18];
e281682b
SM		 3915
3916 u8 syndrome[0x20];
3917
b4ff3a36 3918 u8 reserved_at_40[0x40];
e281682b
SM		 3919
3920 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3921};
3922
3923struct mlx5_ifc_query_roce_address_in_bits {
3924 u8 opcode[0x10];
b4ff3a36 3925 u8 reserved_at_10[0x10];
e281682b 3926
b4ff3a36 3927 u8 reserved_at_20[0x10];
e281682b
SM		 3928 u8 op_mod[0x10];
3929
3930 u8 roce_address_index[0x10];
32f69e4b
DJ		 3931 u8 reserved_at_50[0xc];
3932 u8 vhca_port_num[0x4];
e281682b 3933
b4ff3a36 3934 u8 reserved_at_60[0x20];
e281682b
SM		 3935};
3936
3937struct mlx5_ifc_query_rmp_out_bits {
3938 u8 status[0x8];
b4ff3a36 3939 u8 reserved_at_8[0x18];
e281682b
SM		 3940
3941 u8 syndrome[0x20];
3942
b4ff3a36 3943 u8 reserved_at_40[0xc0];
e281682b
SM		 3944
3945 struct mlx5_ifc_rmpc_bits rmp_context;
3946};
3947
3948struct mlx5_ifc_query_rmp_in_bits {
3949 u8 opcode[0x10];
b4ff3a36 3950 u8 reserved_at_10[0x10];
e281682b 3951
b4ff3a36 3952 u8 reserved_at_20[0x10];
e281682b
SM		 3953 u8 op_mod[0x10];
3954
b4ff3a36 3955 u8 reserved_at_40[0x8];
e281682b
SM		 3956 u8 rmpn[0x18];
3957
b4ff3a36 3958 u8 reserved_at_60[0x20];
e281682b
SM		 3959};
3960
3961struct mlx5_ifc_query_qp_out_bits {
3962 u8 status[0x8];
b4ff3a36 3963 u8 reserved_at_8[0x18];
e281682b
SM		 3964
3965 u8 syndrome[0x20];
3966
b4ff3a36 3967 u8 reserved_at_40[0x40];
e281682b
SM		 3968
3969 u8 opt_param_mask[0x20];
3970
b4ff3a36 3971 u8 reserved_at_a0[0x20];
e281682b
SM		 3972
3973 struct mlx5_ifc_qpc_bits qpc;
3974
b4ff3a36 3975 u8 reserved_at_800[0x80];
e281682b
SM		 3976
3977 u8 pas[0][0x40];
3978};
3979
3980struct mlx5_ifc_query_qp_in_bits {
3981 u8 opcode[0x10];
b4ff3a36 3982 u8 reserved_at_10[0x10];
e281682b 3983
b4ff3a36 3984 u8 reserved_at_20[0x10];
e281682b
SM		 3985 u8 op_mod[0x10];
3986
b4ff3a36 3987 u8 reserved_at_40[0x8];
e281682b
SM		 3988 u8 qpn[0x18];
3989
b4ff3a36 3990 u8 reserved_at_60[0x20];
e281682b
SM		 3991};
3992
3993struct mlx5_ifc_query_q_counter_out_bits {
3994 u8 status[0x8];
b4ff3a36 3995 u8 reserved_at_8[0x18];
e281682b
SM		 3996
3997 u8 syndrome[0x20];
3998
b4ff3a36 3999 u8 reserved_at_40[0x40];
e281682b
SM		 4000
4001 u8 rx_write_requests[0x20];
4002
b4ff3a36 4003 u8 reserved_at_a0[0x20];
e281682b
SM		 4004
4005 u8 rx_read_requests[0x20];
4006
b4ff3a36 4007 u8 reserved_at_e0[0x20];
e281682b
SM		 4008
4009 u8 rx_atomic_requests[0x20];
4010
b4ff3a36 4011 u8 reserved_at_120[0x20];
e281682b
SM		 4012
4013 u8 rx_dct_connect[0x20];
4014
b4ff3a36 4015 u8 reserved_at_160[0x20];
e281682b
SM		 4016
4017 u8 out_of_buffer[0x20];
4018
b4ff3a36 4019 u8 reserved_at_1a0[0x20];
e281682b
SM		 4020
4021 u8 out_of_sequence[0x20];
4022
7486216b
SM		 4023 u8 reserved_at_1e0[0x20];
4024
4025 u8 duplicate_request[0x20];
4026
4027 u8 reserved_at_220[0x20];
4028
4029 u8 rnr_nak_retry_err[0x20];
4030
4031 u8 reserved_at_260[0x20];
4032
4033 u8 packet_seq_err[0x20];
4034
4035 u8 reserved_at_2a0[0x20];
4036
4037 u8 implied_nak_seq_err[0x20];
4038
4039 u8 reserved_at_2e0[0x20];
4040
4041 u8 local_ack_timeout_err[0x20];
4042
58dcb60a
PP		 4043 u8 reserved_at_320[0xa0];
4044
4045 u8 resp_local_length_error[0x20];
4046
4047 u8 req_local_length_error[0x20];
4048
4049 u8 resp_local_qp_error[0x20];
4050
4051 u8 local_operation_error[0x20];
4052
4053 u8 resp_local_protection[0x20];
4054
4055 u8 req_local_protection[0x20];
4056
4057 u8 resp_cqe_error[0x20];
4058
4059 u8 req_cqe_error[0x20];
4060
4061 u8 req_mw_binding[0x20];
4062
4063 u8 req_bad_response[0x20];
4064
4065 u8 req_remote_invalid_request[0x20];
4066
4067 u8 resp_remote_invalid_request[0x20];
4068
4069 u8 req_remote_access_errors[0x20];
4070
4071 u8 resp_remote_access_errors[0x20];
4072
4073 u8 req_remote_operation_errors[0x20];
4074
4075 u8 req_transport_retries_exceeded[0x20];
4076
4077 u8 cq_overflow[0x20];
4078
4079 u8 resp_cqe_flush_error[0x20];
4080
4081 u8 req_cqe_flush_error[0x20];
4082
4083 u8 reserved_at_620[0x1e0];
e281682b
SM		 4084};
4085
4086struct mlx5_ifc_query_q_counter_in_bits {
4087 u8 opcode[0x10];
b4ff3a36 4088 u8 reserved_at_10[0x10];
e281682b 4089
b4ff3a36 4090 u8 reserved_at_20[0x10];
e281682b
SM		 4091 u8 op_mod[0x10];
4092
b4ff3a36 4093 u8 reserved_at_40[0x80];
e281682b
SM		 4094
4095 u8 clear[0x1];
b4ff3a36 4096 u8 reserved_at_c1[0x1f];
e281682b 4097
b4ff3a36 4098 u8 reserved_at_e0[0x18];
e281682b
SM		 4099 u8 counter_set_id[0x8];
4100};
4101
4102struct mlx5_ifc_query_pages_out_bits {
4103 u8 status[0x8];
b4ff3a36 4104 u8 reserved_at_8[0x18];
e281682b
SM		 4105
4106 u8 syndrome[0x20];
4107
b4ff3a36 4108 u8 reserved_at_40[0x10];
e281682b
SM		 4109 u8 function_id[0x10];
4110
4111 u8 num_pages[0x20];
4112};
4113
4114enum {
4115 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4116 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4117 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4118};
4119
4120struct mlx5_ifc_query_pages_in_bits {
4121 u8 opcode[0x10];
b4ff3a36 4122 u8 reserved_at_10[0x10];
e281682b 4123
b4ff3a36 4124 u8 reserved_at_20[0x10];
e281682b
SM		 4125 u8 op_mod[0x10];
4126
b4ff3a36 4127 u8 reserved_at_40[0x10];
e281682b
SM		 4128 u8 function_id[0x10];
4129
b4ff3a36 4130 u8 reserved_at_60[0x20];
e281682b
SM		 4131};
4132
4133struct mlx5_ifc_query_nic_vport_context_out_bits {
4134 u8 status[0x8];
b4ff3a36 4135 u8 reserved_at_8[0x18];
e281682b
SM		 4136
4137 u8 syndrome[0x20];
4138
b4ff3a36 4139 u8 reserved_at_40[0x40];
e281682b
SM		 4140
4141 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4142};
4143
4144struct mlx5_ifc_query_nic_vport_context_in_bits {
4145 u8 opcode[0x10];
b4ff3a36 4146 u8 reserved_at_10[0x10];
e281682b 4147
b4ff3a36 4148 u8 reserved_at_20[0x10];
e281682b
SM		 4149 u8 op_mod[0x10];
4150
4151 u8 other_vport[0x1];
b4ff3a36 4152 u8 reserved_at_41[0xf];
e281682b
SM		 4153 u8 vport_number[0x10];
4154
b4ff3a36 4155 u8 reserved_at_60[0x5];
e281682b 4156 u8 allowed_list_type[0x3];
b4ff3a36 4157 u8 reserved_at_68[0x18];
e281682b
SM		 4158};
4159
4160struct mlx5_ifc_query_mkey_out_bits {
4161 u8 status[0x8];
b4ff3a36 4162 u8 reserved_at_8[0x18];
e281682b
SM		 4163
4164 u8 syndrome[0x20];
4165
b4ff3a36 4166 u8 reserved_at_40[0x40];
e281682b
SM		 4167
4168 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4169
b4ff3a36 4170 u8 reserved_at_280[0x600];
e281682b
SM		 4171
4172 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4173
4174 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4175};
4176
4177struct mlx5_ifc_query_mkey_in_bits {
4178 u8 opcode[0x10];
b4ff3a36 4179 u8 reserved_at_10[0x10];
e281682b 4180
b4ff3a36 4181 u8 reserved_at_20[0x10];
e281682b
SM		 4182 u8 op_mod[0x10];
4183
b4ff3a36 4184 u8 reserved_at_40[0x8];
e281682b
SM		 4185 u8 mkey_index[0x18];
4186
4187 u8 pg_access[0x1];
b4ff3a36 4188 u8 reserved_at_61[0x1f];
e281682b
SM		 4189};
4190
4191struct mlx5_ifc_query_mad_demux_out_bits {
4192 u8 status[0x8];
b4ff3a36 4193 u8 reserved_at_8[0x18];
e281682b
SM		 4194
4195 u8 syndrome[0x20];
4196
b4ff3a36 4197 u8 reserved_at_40[0x40];
e281682b
SM		 4198
4199 u8 mad_dumux_parameters_block[0x20];
4200};
4201
4202struct mlx5_ifc_query_mad_demux_in_bits {
4203 u8 opcode[0x10];
b4ff3a36 4204 u8 reserved_at_10[0x10];
e281682b 4205
b4ff3a36 4206 u8 reserved_at_20[0x10];
e281682b
SM		 4207 u8 op_mod[0x10];
4208
b4ff3a36 4209 u8 reserved_at_40[0x40];
e281682b
SM		 4210};
4211
4212struct mlx5_ifc_query_l2_table_entry_out_bits {
4213 u8 status[0x8];
b4ff3a36 4214 u8 reserved_at_8[0x18];
e281682b
SM		 4215
4216 u8 syndrome[0x20];
4217
b4ff3a36 4218 u8 reserved_at_40[0xa0];
e281682b 4219
b4ff3a36 4220 u8 reserved_at_e0[0x13];
e281682b
SM		 4221 u8 vlan_valid[0x1];
4222 u8 vlan[0xc];
4223
4224 struct mlx5_ifc_mac_address_layout_bits mac_address;
4225
b4ff3a36 4226 u8 reserved_at_140[0xc0];
e281682b
SM		 4227};
4228
4229struct mlx5_ifc_query_l2_table_entry_in_bits {
4230 u8 opcode[0x10];
b4ff3a36 4231 u8 reserved_at_10[0x10];
e281682b 4232
b4ff3a36 4233 u8 reserved_at_20[0x10];
e281682b
SM		 4234 u8 op_mod[0x10];
4235
b4ff3a36 4236 u8 reserved_at_40[0x60];
e281682b 4237
b4ff3a36 4238 u8 reserved_at_a0[0x8];
e281682b
SM		 4239 u8 table_index[0x18];
4240
b4ff3a36 4241 u8 reserved_at_c0[0x140];
e281682b
SM		 4242};
4243
4244struct mlx5_ifc_query_issi_out_bits {
4245 u8 status[0x8];
b4ff3a36 4246 u8 reserved_at_8[0x18];
e281682b
SM		 4247
4248 u8 syndrome[0x20];
4249
b4ff3a36 4250 u8 reserved_at_40[0x10];
e281682b
SM		 4251 u8 current_issi[0x10];
4252
b4ff3a36 4253 u8 reserved_at_60[0xa0];
e281682b 4254
b4ff3a36 4255 u8 reserved_at_100[76][0x8];
e281682b
SM		 4256 u8 supported_issi_dw0[0x20];
4257};
4258
4259struct mlx5_ifc_query_issi_in_bits {
4260 u8 opcode[0x10];
b4ff3a36 4261 u8 reserved_at_10[0x10];
e281682b 4262
b4ff3a36 4263 u8 reserved_at_20[0x10];
e281682b
SM		 4264 u8 op_mod[0x10];
4265
b4ff3a36 4266 u8 reserved_at_40[0x40];
e281682b
SM		 4267};
4268
0dbc6fe0
SM		 4269struct mlx5_ifc_set_driver_version_out_bits {
4270 u8 status[0x8];
4271 u8 reserved_0[0x18];
4272
4273 u8 syndrome[0x20];
4274 u8 reserved_1[0x40];
4275};
4276
4277struct mlx5_ifc_set_driver_version_in_bits {
4278 u8 opcode[0x10];
4279 u8 reserved_0[0x10];
4280
4281 u8 reserved_1[0x10];
4282 u8 op_mod[0x10];
4283
4284 u8 reserved_2[0x40];
4285 u8 driver_version[64][0x8];
4286};
4287
e281682b
SM		 4288struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4289 u8 status[0x8];
b4ff3a36 4290 u8 reserved_at_8[0x18];
e281682b
SM		 4291
4292 u8 syndrome[0x20];
4293
b4ff3a36 4294 u8 reserved_at_40[0x40];
e281682b
SM		 4295
4296 struct mlx5_ifc_pkey_bits pkey[0];
4297};
4298
4299struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4300 u8 opcode[0x10];
b4ff3a36 4301 u8 reserved_at_10[0x10];
e281682b 4302
b4ff3a36 4303 u8 reserved_at_20[0x10];
e281682b
SM		 4304 u8 op_mod[0x10];
4305
4306 u8 other_vport[0x1];
b4ff3a36 4307 u8 reserved_at_41[0xb];
707c4602 4308 u8 port_num[0x4];
e281682b
SM		 4309 u8 vport_number[0x10];
4310
b4ff3a36 4311 u8 reserved_at_60[0x10];
e281682b
SM		 4312 u8 pkey_index[0x10];
4313};
4314
eff901d3
EC		 4315enum {
4316 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4317 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4318 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4319};
4320
e281682b
SM		 4321struct mlx5_ifc_query_hca_vport_gid_out_bits {
4322 u8 status[0x8];
b4ff3a36 4323 u8 reserved_at_8[0x18];
e281682b
SM		 4324
4325 u8 syndrome[0x20];
4326
b4ff3a36 4327 u8 reserved_at_40[0x20];
e281682b
SM		 4328
4329 u8 gids_num[0x10];
b4ff3a36 4330 u8 reserved_at_70[0x10];
e281682b
SM		 4331
4332 struct mlx5_ifc_array128_auto_bits gid[0];
4333};
4334
4335struct mlx5_ifc_query_hca_vport_gid_in_bits {
4336 u8 opcode[0x10];
b4ff3a36 4337 u8 reserved_at_10[0x10];
e281682b 4338
b4ff3a36 4339 u8 reserved_at_20[0x10];
e281682b
SM		 4340 u8 op_mod[0x10];
4341
4342 u8 other_vport[0x1];
b4ff3a36 4343 u8 reserved_at_41[0xb];
707c4602 4344 u8 port_num[0x4];
e281682b
SM		 4345 u8 vport_number[0x10];
4346
b4ff3a36 4347 u8 reserved_at_60[0x10];
e281682b
SM		 4348 u8 gid_index[0x10];
4349};
4350
4351struct mlx5_ifc_query_hca_vport_context_out_bits {
4352 u8 status[0x8];
b4ff3a36 4353 u8 reserved_at_8[0x18];
e281682b
SM		 4354
4355 u8 syndrome[0x20];
4356
b4ff3a36 4357 u8 reserved_at_40[0x40];
e281682b
SM		 4358
4359 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4360};
4361
4362struct mlx5_ifc_query_hca_vport_context_in_bits {
4363 u8 opcode[0x10];
b4ff3a36 4364 u8 reserved_at_10[0x10];
e281682b 4365
b4ff3a36 4366 u8 reserved_at_20[0x10];
e281682b
SM		 4367 u8 op_mod[0x10];
4368
4369 u8 other_vport[0x1];
b4ff3a36 4370 u8 reserved_at_41[0xb];
707c4602 4371 u8 port_num[0x4];
e281682b
SM		 4372 u8 vport_number[0x10];
4373
b4ff3a36 4374 u8 reserved_at_60[0x20];
e281682b
SM		 4375};
4376
4377struct mlx5_ifc_query_hca_cap_out_bits {
4378 u8 status[0x8];
b4ff3a36 4379 u8 reserved_at_8[0x18];
e281682b
SM		 4380
4381 u8 syndrome[0x20];
4382
b4ff3a36 4383 u8 reserved_at_40[0x40];
e281682b
SM		 4384
4385 union mlx5_ifc_hca_cap_union_bits capability;
4386};
4387
4388struct mlx5_ifc_query_hca_cap_in_bits {
4389 u8 opcode[0x10];
b4ff3a36 4390 u8 reserved_at_10[0x10];
e281682b 4391
b4ff3a36 4392 u8 reserved_at_20[0x10];
e281682b
SM		 4393 u8 op_mod[0x10];
4394
b4ff3a36 4395 u8 reserved_at_40[0x40];
e281682b
SM		 4396};
4397
4398struct mlx5_ifc_query_flow_table_out_bits {
4399 u8 status[0x8];
b4ff3a36 4400 u8 reserved_at_8[0x18];
e281682b
SM		 4401
4402 u8 syndrome[0x20];
4403
b4ff3a36 4404 u8 reserved_at_40[0x80];
e281682b 4405
b4ff3a36 4406 u8 reserved_at_c0[0x8];
e281682b 4407 u8 level[0x8];
b4ff3a36 4408 u8 reserved_at_d0[0x8];
e281682b
SM		 4409 u8 log_size[0x8];
4410
b4ff3a36 4411 u8 reserved_at_e0[0x120];
e281682b
SM		 4412};
4413
4414struct mlx5_ifc_query_flow_table_in_bits {
4415 u8 opcode[0x10];
b4ff3a36 4416 u8 reserved_at_10[0x10];
e281682b 4417
b4ff3a36 4418 u8 reserved_at_20[0x10];
e281682b
SM		 4419 u8 op_mod[0x10];
4420
b4ff3a36 4421 u8 reserved_at_40[0x40];
e281682b
SM		 4422
4423 u8 table_type[0x8];
b4ff3a36 4424 u8 reserved_at_88[0x18];
e281682b 4425
b4ff3a36 4426 u8 reserved_at_a0[0x8];
e281682b
SM		 4427 u8 table_id[0x18];
4428
b4ff3a36 4429 u8 reserved_at_c0[0x140];
e281682b
SM		 4430};
4431
4432struct mlx5_ifc_query_fte_out_bits {
4433 u8 status[0x8];
b4ff3a36 4434 u8 reserved_at_8[0x18];
e281682b
SM		 4435
4436 u8 syndrome[0x20];
4437
b4ff3a36 4438 u8 reserved_at_40[0x1c0];
e281682b
SM		 4439
4440 struct mlx5_ifc_flow_context_bits flow_context;
4441};
4442
4443struct mlx5_ifc_query_fte_in_bits {
4444 u8 opcode[0x10];
b4ff3a36 4445 u8 reserved_at_10[0x10];
e281682b 4446
b4ff3a36 4447 u8 reserved_at_20[0x10];
e281682b
SM		 4448 u8 op_mod[0x10];
4449
b4ff3a36 4450 u8 reserved_at_40[0x40];
e281682b
SM		 4451
4452 u8 table_type[0x8];
b4ff3a36 4453 u8 reserved_at_88[0x18];
e281682b 4454
b4ff3a36 4455 u8 reserved_at_a0[0x8];
e281682b
SM		 4456 u8 table_id[0x18];
4457
b4ff3a36 4458 u8 reserved_at_c0[0x40];
e281682b
SM		 4459
4460 u8 flow_index[0x20];
4461
b4ff3a36 4462 u8 reserved_at_120[0xe0];
e281682b
SM		 4463};
4464
4465enum {
4466 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4467 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4468 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4469};
4470
4471struct mlx5_ifc_query_flow_group_out_bits {
4472 u8 status[0x8];
b4ff3a36 4473 u8 reserved_at_8[0x18];
e281682b
SM		 4474
4475 u8 syndrome[0x20];
4476
b4ff3a36 4477 u8 reserved_at_40[0xa0];
e281682b
SM		 4478
4479 u8 start_flow_index[0x20];
4480
b4ff3a36 4481 u8 reserved_at_100[0x20];
e281682b
SM		 4482
4483 u8 end_flow_index[0x20];
4484
b4ff3a36 4485 u8 reserved_at_140[0xa0];
e281682b 4486
b4ff3a36 4487 u8 reserved_at_1e0[0x18];
e281682b
SM		 4488 u8 match_criteria_enable[0x8];
4489
4490 struct mlx5_ifc_fte_match_param_bits match_criteria;
4491
b4ff3a36 4492 u8 reserved_at_1200[0xe00];
e281682b
SM		 4493};
4494
4495struct mlx5_ifc_query_flow_group_in_bits {
4496 u8 opcode[0x10];
b4ff3a36 4497 u8 reserved_at_10[0x10];
e281682b 4498
b4ff3a36 4499 u8 reserved_at_20[0x10];
e281682b
SM		 4500 u8 op_mod[0x10];
4501
b4ff3a36 4502 u8 reserved_at_40[0x40];
e281682b
SM		 4503
4504 u8 table_type[0x8];
b4ff3a36 4505 u8 reserved_at_88[0x18];
e281682b 4506
b4ff3a36 4507 u8 reserved_at_a0[0x8];
e281682b
SM		 4508 u8 table_id[0x18];
4509
4510 u8 group_id[0x20];
4511
b4ff3a36 4512 u8 reserved_at_e0[0x120];
e281682b
SM		 4513};
4514
9dc0b289
AV		 4515struct mlx5_ifc_query_flow_counter_out_bits {
4516 u8 status[0x8];
4517 u8 reserved_at_8[0x18];
4518
4519 u8 syndrome[0x20];
4520
4521 u8 reserved_at_40[0x40];
4522
4523 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4524};
4525
4526struct mlx5_ifc_query_flow_counter_in_bits {
4527 u8 opcode[0x10];
4528 u8 reserved_at_10[0x10];
4529
4530 u8 reserved_at_20[0x10];
4531 u8 op_mod[0x10];
4532
4533 u8 reserved_at_40[0x80];
4534
4535 u8 clear[0x1];
4536 u8 reserved_at_c1[0xf];
4537 u8 num_of_counters[0x10];
4538
a8ffcc74 4539 u8 flow_counter_id[0x20];
9dc0b289
AV		 4540};
4541
d6666753
SM		 4542struct mlx5_ifc_query_esw_vport_context_out_bits {
4543 u8 status[0x8];
b4ff3a36 4544 u8 reserved_at_8[0x18];
d6666753
SM		 4545
4546 u8 syndrome[0x20];
4547
b4ff3a36 4548 u8 reserved_at_40[0x40];
d6666753
SM		 4549
4550 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4551};
4552
4553struct mlx5_ifc_query_esw_vport_context_in_bits {
4554 u8 opcode[0x10];
b4ff3a36 4555 u8 reserved_at_10[0x10];
d6666753 4556
b4ff3a36 4557 u8 reserved_at_20[0x10];
d6666753
SM		 4558 u8 op_mod[0x10];
4559
4560 u8 other_vport[0x1];
b4ff3a36 4561 u8 reserved_at_41[0xf];
d6666753
SM		 4562 u8 vport_number[0x10];
4563
b4ff3a36 4564 u8 reserved_at_60[0x20];
d6666753
SM		 4565};
4566
4567struct mlx5_ifc_modify_esw_vport_context_out_bits {
4568 u8 status[0x8];
b4ff3a36 4569 u8 reserved_at_8[0x18];
d6666753
SM		 4570
4571 u8 syndrome[0x20];
4572
b4ff3a36 4573 u8 reserved_at_40[0x40];
d6666753
SM		 4574};
4575
4576struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4577 u8 reserved_at_0[0x1c];
d6666753
SM		 4578 u8 vport_cvlan_insert[0x1];
4579 u8 vport_svlan_insert[0x1];
4580 u8 vport_cvlan_strip[0x1];
4581 u8 vport_svlan_strip[0x1];
4582};
4583
4584struct mlx5_ifc_modify_esw_vport_context_in_bits {
4585 u8 opcode[0x10];
b4ff3a36 4586 u8 reserved_at_10[0x10];
d6666753 4587
b4ff3a36 4588 u8 reserved_at_20[0x10];
d6666753
SM		 4589 u8 op_mod[0x10];
4590
4591 u8 other_vport[0x1];
b4ff3a36 4592 u8 reserved_at_41[0xf];
d6666753
SM		 4593 u8 vport_number[0x10];
4594
4595 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4596
4597 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4598};
4599
e281682b
SM		 4600struct mlx5_ifc_query_eq_out_bits {
4601 u8 status[0x8];
b4ff3a36 4602 u8 reserved_at_8[0x18];
e281682b
SM		 4603
4604 u8 syndrome[0x20];
4605
b4ff3a36 4606 u8 reserved_at_40[0x40];
e281682b
SM		 4607
4608 struct mlx5_ifc_eqc_bits eq_context_entry;
4609
b4ff3a36 4610 u8 reserved_at_280[0x40];
e281682b
SM		 4611
4612 u8 event_bitmask[0x40];
4613
b4ff3a36 4614 u8 reserved_at_300[0x580];
e281682b
SM		 4615
4616 u8 pas[0][0x40];
4617};
4618
4619struct mlx5_ifc_query_eq_in_bits {
4620 u8 opcode[0x10];
b4ff3a36 4621 u8 reserved_at_10[0x10];
e281682b 4622
b4ff3a36 4623 u8 reserved_at_20[0x10];
e281682b
SM		 4624 u8 op_mod[0x10];
4625
b4ff3a36 4626 u8 reserved_at_40[0x18];
e281682b
SM		 4627 u8 eq_number[0x8];
4628
b4ff3a36 4629 u8 reserved_at_60[0x20];
e281682b
SM		 4630};
4631
7adbde20
HHZ		 4632struct mlx5_ifc_encap_header_in_bits {
4633 u8 reserved_at_0[0x5];
4634 u8 header_type[0x3];
4635 u8 reserved_at_8[0xe];
4636 u8 encap_header_size[0xa];
4637
4638 u8 reserved_at_20[0x10];
4639 u8 encap_header[2][0x8];
4640
4641 u8 more_encap_header[0][0x8];
4642};
4643
4644struct mlx5_ifc_query_encap_header_out_bits {
4645 u8 status[0x8];
4646 u8 reserved_at_8[0x18];
4647
4648 u8 syndrome[0x20];
4649
4650 u8 reserved_at_40[0xa0];
4651
4652 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4653};
4654
4655struct mlx5_ifc_query_encap_header_in_bits {
4656 u8 opcode[0x10];
4657 u8 reserved_at_10[0x10];
4658
4659 u8 reserved_at_20[0x10];
4660 u8 op_mod[0x10];
4661
4662 u8 encap_id[0x20];
4663
4664 u8 reserved_at_60[0xa0];
4665};
4666
4667struct mlx5_ifc_alloc_encap_header_out_bits {
4668 u8 status[0x8];
4669 u8 reserved_at_8[0x18];
4670
4671 u8 syndrome[0x20];
4672
4673 u8 encap_id[0x20];
4674
4675 u8 reserved_at_60[0x20];
4676};
4677
4678struct mlx5_ifc_alloc_encap_header_in_bits {
4679 u8 opcode[0x10];
4680 u8 reserved_at_10[0x10];
4681
4682 u8 reserved_at_20[0x10];
4683 u8 op_mod[0x10];
4684
4685 u8 reserved_at_40[0xa0];
4686
4687 struct mlx5_ifc_encap_header_in_bits encap_header;
4688};
4689
4690struct mlx5_ifc_dealloc_encap_header_out_bits {
4691 u8 status[0x8];
4692 u8 reserved_at_8[0x18];
4693
4694 u8 syndrome[0x20];
4695
4696 u8 reserved_at_40[0x40];
4697};
4698
4699struct mlx5_ifc_dealloc_encap_header_in_bits {
4700 u8 opcode[0x10];
4701 u8 reserved_at_10[0x10];
4702
4703 u8 reserved_20[0x10];
4704 u8 op_mod[0x10];
4705
4706 u8 encap_id[0x20];
4707
4708 u8 reserved_60[0x20];
4709};
4710
2a69cb9f
OG		 4711struct mlx5_ifc_set_action_in_bits {
4712 u8 action_type[0x4];
4713 u8 field[0xc];
4714 u8 reserved_at_10[0x3];
4715 u8 offset[0x5];
4716 u8 reserved_at_18[0x3];
4717 u8 length[0x5];
4718
4719 u8 data[0x20];
4720};
4721
4722struct mlx5_ifc_add_action_in_bits {
4723 u8 action_type[0x4];
4724 u8 field[0xc];
4725 u8 reserved_at_10[0x10];
4726
4727 u8 data[0x20];
4728};
4729
4730union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4731 struct mlx5_ifc_set_action_in_bits set_action_in;
4732 struct mlx5_ifc_add_action_in_bits add_action_in;
4733 u8 reserved_at_0[0x40];
4734};
4735
4736enum {
4737 MLX5_ACTION_TYPE_SET = 0x1,
4738 MLX5_ACTION_TYPE_ADD = 0x2,
4739};
4740
4741enum {
4742 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4743 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4744 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4745 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4746 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4747 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4748 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4749 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4750 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4751 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4752 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4753 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4754 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4755 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4756 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4757 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4758 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4759 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4760 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4761 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4762 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4763 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4764 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4765};
4766
4767struct mlx5_ifc_alloc_modify_header_context_out_bits {
4768 u8 status[0x8];
4769 u8 reserved_at_8[0x18];
4770
4771 u8 syndrome[0x20];
4772
4773 u8 modify_header_id[0x20];
4774
4775 u8 reserved_at_60[0x20];
4776};
4777
4778struct mlx5_ifc_alloc_modify_header_context_in_bits {
4779 u8 opcode[0x10];
4780 u8 reserved_at_10[0x10];
4781
4782 u8 reserved_at_20[0x10];
4783 u8 op_mod[0x10];
4784
4785 u8 reserved_at_40[0x20];
4786
4787 u8 table_type[0x8];
4788 u8 reserved_at_68[0x10];
4789 u8 num_of_actions[0x8];
4790
4791 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4792};
4793
4794struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4795 u8 status[0x8];
4796 u8 reserved_at_8[0x18];
4797
4798 u8 syndrome[0x20];
4799
4800 u8 reserved_at_40[0x40];
4801};
4802
4803struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4804 u8 opcode[0x10];
4805 u8 reserved_at_10[0x10];
4806
4807 u8 reserved_at_20[0x10];
4808 u8 op_mod[0x10];
4809
4810 u8 modify_header_id[0x20];
4811
4812 u8 reserved_at_60[0x20];
4813};
4814
e281682b
SM		 4815struct mlx5_ifc_query_dct_out_bits {
4816 u8 status[0x8];
b4ff3a36 4817 u8 reserved_at_8[0x18];
e281682b
SM		 4818
4819 u8 syndrome[0x20];
4820
b4ff3a36 4821 u8 reserved_at_40[0x40];
e281682b
SM		 4822
4823 struct mlx5_ifc_dctc_bits dct_context_entry;
4824
b4ff3a36 4825 u8 reserved_at_280[0x180];
e281682b
SM		 4826};
4827
4828struct mlx5_ifc_query_dct_in_bits {
4829 u8 opcode[0x10];
b4ff3a36 4830 u8 reserved_at_10[0x10];
e281682b 4831
b4ff3a36 4832 u8 reserved_at_20[0x10];
e281682b
SM		 4833 u8 op_mod[0x10];
4834
b4ff3a36 4835 u8 reserved_at_40[0x8];
e281682b
SM		 4836 u8 dctn[0x18];
4837
b4ff3a36 4838 u8 reserved_at_60[0x20];
e281682b
SM		 4839};
4840
4841struct mlx5_ifc_query_cq_out_bits {
4842 u8 status[0x8];
b4ff3a36 4843 u8 reserved_at_8[0x18];
e281682b
SM		 4844
4845 u8 syndrome[0x20];
4846
b4ff3a36 4847 u8 reserved_at_40[0x40];
e281682b
SM		 4848
4849 struct mlx5_ifc_cqc_bits cq_context;
4850
b4ff3a36 4851 u8 reserved_at_280[0x600];
e281682b
SM		 4852
4853 u8 pas[0][0x40];
4854};
4855
4856struct mlx5_ifc_query_cq_in_bits {
4857 u8 opcode[0x10];
b4ff3a36 4858 u8 reserved_at_10[0x10];
e281682b 4859
b4ff3a36 4860 u8 reserved_at_20[0x10];
e281682b
SM		 4861 u8 op_mod[0x10];
4862
b4ff3a36 4863 u8 reserved_at_40[0x8];
e281682b
SM		 4864 u8 cqn[0x18];
4865
b4ff3a36 4866 u8 reserved_at_60[0x20];
e281682b
SM		 4867};
4868
4869struct mlx5_ifc_query_cong_status_out_bits {
4870 u8 status[0x8];
b4ff3a36 4871 u8 reserved_at_8[0x18];
e281682b
SM		 4872
4873 u8 syndrome[0x20];
4874
b4ff3a36 4875 u8 reserved_at_40[0x20];
e281682b
SM		 4876
4877 u8 enable[0x1];
4878 u8 tag_enable[0x1];
b4ff3a36 4879 u8 reserved_at_62[0x1e];
e281682b
SM		 4880};
4881
4882struct mlx5_ifc_query_cong_status_in_bits {
4883 u8 opcode[0x10];
b4ff3a36 4884 u8 reserved_at_10[0x10];
e281682b 4885
b4ff3a36 4886 u8 reserved_at_20[0x10];
e281682b
SM		 4887 u8 op_mod[0x10];
4888
b4ff3a36 4889 u8 reserved_at_40[0x18];
e281682b
SM		 4890 u8 priority[0x4];
4891 u8 cong_protocol[0x4];
4892
b4ff3a36 4893 u8 reserved_at_60[0x20];
e281682b
SM		 4894};
4895
4896struct mlx5_ifc_query_cong_statistics_out_bits {
4897 u8 status[0x8];
b4ff3a36 4898 u8 reserved_at_8[0x18];
e281682b
SM		 4899
4900 u8 syndrome[0x20];
4901
b4ff3a36 4902 u8 reserved_at_40[0x40];
e281682b 4903
e1f24a79 4904 u8 rp_cur_flows[0x20];
e281682b
SM		 4905
4906 u8 sum_flows[0x20];
4907
e1f24a79 4908 u8 rp_cnp_ignored_high[0x20];
e281682b 4909
e1f24a79 4910 u8 rp_cnp_ignored_low[0x20];
e281682b 4911
e1f24a79 4912 u8 rp_cnp_handled_high[0x20];
e281682b 4913
e1f24a79 4914 u8 rp_cnp_handled_low[0x20];
e281682b 4915
b4ff3a36 4916 u8 reserved_at_140[0x100];
e281682b
SM		 4917
4918 u8 time_stamp_high[0x20];
4919
4920 u8 time_stamp_low[0x20];
4921
4922 u8 accumulators_period[0x20];
4923
e1f24a79 4924 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 4925
e1f24a79 4926 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 4927
e1f24a79 4928 u8 np_cnp_sent_high[0x20];
e281682b 4929
e1f24a79 4930 u8 np_cnp_sent_low[0x20];
e281682b 4931
b4ff3a36 4932 u8 reserved_at_320[0x560];
e281682b
SM		 4933};
4934
4935struct mlx5_ifc_query_cong_statistics_in_bits {
4936 u8 opcode[0x10];
b4ff3a36 4937 u8 reserved_at_10[0x10];
e281682b 4938
b4ff3a36 4939 u8 reserved_at_20[0x10];
e281682b
SM		 4940 u8 op_mod[0x10];
4941
4942 u8 clear[0x1];
b4ff3a36 4943 u8 reserved_at_41[0x1f];
e281682b 4944
b4ff3a36 4945 u8 reserved_at_60[0x20];
e281682b
SM		 4946};
4947
4948struct mlx5_ifc_query_cong_params_out_bits {
4949 u8 status[0x8];
b4ff3a36 4950 u8 reserved_at_8[0x18];
e281682b
SM		 4951
4952 u8 syndrome[0x20];
4953
b4ff3a36 4954 u8 reserved_at_40[0x40];
e281682b
SM		 4955
4956 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4957};
4958
4959struct mlx5_ifc_query_cong_params_in_bits {
4960 u8 opcode[0x10];
b4ff3a36 4961 u8 reserved_at_10[0x10];
e281682b 4962
b4ff3a36 4963 u8 reserved_at_20[0x10];
e281682b
SM		 4964 u8 op_mod[0x10];
4965
b4ff3a36 4966 u8 reserved_at_40[0x1c];
e281682b
SM		 4967 u8 cong_protocol[0x4];
4968
b4ff3a36 4969 u8 reserved_at_60[0x20];
e281682b
SM		 4970};
4971
4972struct mlx5_ifc_query_adapter_out_bits {
4973 u8 status[0x8];
b4ff3a36 4974 u8 reserved_at_8[0x18];
e281682b
SM		 4975
4976 u8 syndrome[0x20];
4977
b4ff3a36 4978 u8 reserved_at_40[0x40];
e281682b
SM		 4979
4980 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4981};
4982
4983struct mlx5_ifc_query_adapter_in_bits {
4984 u8 opcode[0x10];
b4ff3a36 4985 u8 reserved_at_10[0x10];
e281682b 4986
b4ff3a36 4987 u8 reserved_at_20[0x10];
e281682b
SM		 4988 u8 op_mod[0x10];
4989
b4ff3a36 4990 u8 reserved_at_40[0x40];
e281682b
SM		 4991};
4992
4993struct mlx5_ifc_qp_2rst_out_bits {
4994 u8 status[0x8];
b4ff3a36 4995 u8 reserved_at_8[0x18];
e281682b
SM		 4996
4997 u8 syndrome[0x20];
4998
b4ff3a36 4999 u8 reserved_at_40[0x40];
e281682b
SM		 5000};
5001
5002struct mlx5_ifc_qp_2rst_in_bits {
5003 u8 opcode[0x10];
b4ff3a36 5004 u8 reserved_at_10[0x10];
e281682b 5005
b4ff3a36 5006 u8 reserved_at_20[0x10];
e281682b
SM		 5007 u8 op_mod[0x10];
5008
b4ff3a36 5009 u8 reserved_at_40[0x8];
e281682b
SM		 5010 u8 qpn[0x18];
5011
b4ff3a36 5012 u8 reserved_at_60[0x20];
e281682b
SM		 5013};
5014
5015struct mlx5_ifc_qp_2err_out_bits {
5016 u8 status[0x8];
b4ff3a36 5017 u8 reserved_at_8[0x18];
e281682b
SM		 5018
5019 u8 syndrome[0x20];
5020
b4ff3a36 5021 u8 reserved_at_40[0x40];
e281682b
SM		 5022};
5023
5024struct mlx5_ifc_qp_2err_in_bits {
5025 u8 opcode[0x10];
b4ff3a36 5026 u8 reserved_at_10[0x10];
e281682b 5027
b4ff3a36 5028 u8 reserved_at_20[0x10];
e281682b
SM		 5029 u8 op_mod[0x10];
5030
b4ff3a36 5031 u8 reserved_at_40[0x8];
e281682b
SM		 5032 u8 qpn[0x18];
5033
b4ff3a36 5034 u8 reserved_at_60[0x20];
e281682b
SM		 5035};
5036
5037struct mlx5_ifc_page_fault_resume_out_bits {
5038 u8 status[0x8];
b4ff3a36 5039 u8 reserved_at_8[0x18];
e281682b
SM		 5040
5041 u8 syndrome[0x20];
5042
b4ff3a36 5043 u8 reserved_at_40[0x40];
e281682b
SM		 5044};
5045
5046struct mlx5_ifc_page_fault_resume_in_bits {
5047 u8 opcode[0x10];
b4ff3a36 5048 u8 reserved_at_10[0x10];
e281682b 5049
b4ff3a36 5050 u8 reserved_at_20[0x10];
e281682b
SM		 5051 u8 op_mod[0x10];
5052
5053 u8 error[0x1];
b4ff3a36 5054 u8 reserved_at_41[0x4];
223cdc72
AK		 5055 u8 page_fault_type[0x3];
5056 u8 wq_number[0x18];
e281682b 5057
223cdc72
AK		 5058 u8 reserved_at_60[0x8];
5059 u8 token[0x18];
e281682b
SM		 5060};
5061
5062struct mlx5_ifc_nop_out_bits {
5063 u8 status[0x8];
b4ff3a36 5064 u8 reserved_at_8[0x18];
e281682b
SM		 5065
5066 u8 syndrome[0x20];
5067
b4ff3a36 5068 u8 reserved_at_40[0x40];
e281682b
SM		 5069};
5070
5071struct mlx5_ifc_nop_in_bits {
5072 u8 opcode[0x10];
b4ff3a36 5073 u8 reserved_at_10[0x10];
e281682b 5074
b4ff3a36 5075 u8 reserved_at_20[0x10];
e281682b
SM		 5076 u8 op_mod[0x10];
5077
b4ff3a36 5078 u8 reserved_at_40[0x40];
e281682b
SM		 5079};
5080
5081struct mlx5_ifc_modify_vport_state_out_bits {
5082 u8 status[0x8];
b4ff3a36 5083 u8 reserved_at_8[0x18];
e281682b
SM		 5084
5085 u8 syndrome[0x20];
5086
b4ff3a36 5087 u8 reserved_at_40[0x40];
e281682b
SM		 5088};
5089
5090struct mlx5_ifc_modify_vport_state_in_bits {
5091 u8 opcode[0x10];
b4ff3a36 5092 u8 reserved_at_10[0x10];
e281682b 5093
b4ff3a36 5094 u8 reserved_at_20[0x10];
e281682b
SM		 5095 u8 op_mod[0x10];
5096
5097 u8 other_vport[0x1];
b4ff3a36 5098 u8 reserved_at_41[0xf];
e281682b
SM		 5099 u8 vport_number[0x10];
5100
b4ff3a36 5101 u8 reserved_at_60[0x18];
e281682b 5102 u8 admin_state[0x4];
b4ff3a36 5103 u8 reserved_at_7c[0x4];
e281682b
SM		 5104};
5105
5106struct mlx5_ifc_modify_tis_out_bits {
5107 u8 status[0x8];
b4ff3a36 5108 u8 reserved_at_8[0x18];
e281682b
SM		 5109
5110 u8 syndrome[0x20];
5111
b4ff3a36 5112 u8 reserved_at_40[0x40];
e281682b
SM		 5113};
5114
75850d0b 5115struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5116 u8 reserved_at_0[0x20];
75850d0b 5117
84df61eb
AH		 5118 u8 reserved_at_20[0x1d];
5119 u8 lag_tx_port_affinity[0x1];
5120 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5121 u8 prio[0x1];
5122};
5123
e281682b
SM		 5124struct mlx5_ifc_modify_tis_in_bits {
5125 u8 opcode[0x10];
b4ff3a36 5126 u8 reserved_at_10[0x10];
e281682b 5127
b4ff3a36 5128 u8 reserved_at_20[0x10];
e281682b
SM		 5129 u8 op_mod[0x10];
5130
b4ff3a36 5131 u8 reserved_at_40[0x8];
e281682b
SM		 5132 u8 tisn[0x18];
5133
b4ff3a36 5134 u8 reserved_at_60[0x20];
e281682b 5135
75850d0b 5136 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5137
b4ff3a36 5138 u8 reserved_at_c0[0x40];
e281682b
SM		 5139
5140 struct mlx5_ifc_tisc_bits ctx;
5141};
5142
d9eea403 5143struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5144 u8 reserved_at_0[0x20];
d9eea403 5145
b4ff3a36 5146 u8 reserved_at_20[0x1b];
66189961 5147 u8 self_lb_en[0x1];
bdfc028d
TT		 5148 u8 reserved_at_3c[0x1];
5149 u8 hash[0x1];
5150 u8 reserved_at_3e[0x1];
d9eea403
AS		 5151 u8 lro[0x1];
5152};
5153
e281682b
SM		 5154struct mlx5_ifc_modify_tir_out_bits {
5155 u8 status[0x8];
b4ff3a36 5156 u8 reserved_at_8[0x18];
e281682b
SM		 5157
5158 u8 syndrome[0x20];
5159
b4ff3a36 5160 u8 reserved_at_40[0x40];
e281682b
SM		 5161};
5162
5163struct mlx5_ifc_modify_tir_in_bits {
5164 u8 opcode[0x10];
b4ff3a36 5165 u8 reserved_at_10[0x10];
e281682b 5166
b4ff3a36 5167 u8 reserved_at_20[0x10];
e281682b
SM		 5168 u8 op_mod[0x10];
5169
b4ff3a36 5170 u8 reserved_at_40[0x8];
e281682b
SM		 5171 u8 tirn[0x18];
5172
b4ff3a36 5173 u8 reserved_at_60[0x20];
e281682b 5174
d9eea403 5175 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5176
b4ff3a36 5177 u8 reserved_at_c0[0x40];
e281682b
SM		 5178
5179 struct mlx5_ifc_tirc_bits ctx;
5180};
5181
5182struct mlx5_ifc_modify_sq_out_bits {
5183 u8 status[0x8];
b4ff3a36 5184 u8 reserved_at_8[0x18];
e281682b
SM		 5185
5186 u8 syndrome[0x20];
5187
b4ff3a36 5188 u8 reserved_at_40[0x40];
e281682b
SM		 5189};
5190
5191struct mlx5_ifc_modify_sq_in_bits {
5192 u8 opcode[0x10];
b4ff3a36 5193 u8 reserved_at_10[0x10];
e281682b 5194
b4ff3a36 5195 u8 reserved_at_20[0x10];
e281682b
SM		 5196 u8 op_mod[0x10];
5197
5198 u8 sq_state[0x4];
b4ff3a36 5199 u8 reserved_at_44[0x4];
e281682b
SM		 5200 u8 sqn[0x18];
5201
b4ff3a36 5202 u8 reserved_at_60[0x20];
e281682b
SM		 5203
5204 u8 modify_bitmask[0x40];
5205
b4ff3a36 5206 u8 reserved_at_c0[0x40];
e281682b
SM		 5207
5208 struct mlx5_ifc_sqc_bits ctx;
5209};
5210
813f8540
MHY		 5211struct mlx5_ifc_modify_scheduling_element_out_bits {
5212 u8 status[0x8];
5213 u8 reserved_at_8[0x18];
5214
5215 u8 syndrome[0x20];
5216
5217 u8 reserved_at_40[0x1c0];
5218};
5219
5220enum {
5221 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5222 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5223};
5224
5225struct mlx5_ifc_modify_scheduling_element_in_bits {
5226 u8 opcode[0x10];
5227 u8 reserved_at_10[0x10];
5228
5229 u8 reserved_at_20[0x10];
5230 u8 op_mod[0x10];
5231
5232 u8 scheduling_hierarchy[0x8];
5233 u8 reserved_at_48[0x18];
5234
5235 u8 scheduling_element_id[0x20];
5236
5237 u8 reserved_at_80[0x20];
5238
5239 u8 modify_bitmask[0x20];
5240
5241 u8 reserved_at_c0[0x40];
5242
5243 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5244
5245 u8 reserved_at_300[0x100];
5246};
5247
e281682b
SM		 5248struct mlx5_ifc_modify_rqt_out_bits {
5249 u8 status[0x8];
b4ff3a36 5250 u8 reserved_at_8[0x18];
e281682b
SM		 5251
5252 u8 syndrome[0x20];
5253
b4ff3a36 5254 u8 reserved_at_40[0x40];
e281682b
SM		 5255};
5256
5c50368f 5257struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5258 u8 reserved_at_0[0x20];
5c50368f 5259
b4ff3a36 5260 u8 reserved_at_20[0x1f];
5c50368f
AS		 5261 u8 rqn_list[0x1];
5262};
5263
e281682b
SM		 5264struct mlx5_ifc_modify_rqt_in_bits {
5265 u8 opcode[0x10];
b4ff3a36 5266 u8 reserved_at_10[0x10];
e281682b 5267
b4ff3a36 5268 u8 reserved_at_20[0x10];
e281682b
SM		 5269 u8 op_mod[0x10];
5270
b4ff3a36 5271 u8 reserved_at_40[0x8];
e281682b
SM		 5272 u8 rqtn[0x18];
5273
b4ff3a36 5274 u8 reserved_at_60[0x20];
e281682b 5275
5c50368f 5276 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5277
b4ff3a36 5278 u8 reserved_at_c0[0x40];
e281682b
SM		 5279
5280 struct mlx5_ifc_rqtc_bits ctx;
5281};
5282
5283struct mlx5_ifc_modify_rq_out_bits {
5284 u8 status[0x8];
b4ff3a36 5285 u8 reserved_at_8[0x18];
e281682b
SM		 5286
5287 u8 syndrome[0x20];
5288
b4ff3a36 5289 u8 reserved_at_40[0x40];
e281682b
SM		 5290};
5291
83b502a1
AV		 5292enum {
5293 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5294 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5295 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5296};
5297
e281682b
SM		 5298struct mlx5_ifc_modify_rq_in_bits {
5299 u8 opcode[0x10];
b4ff3a36 5300 u8 reserved_at_10[0x10];
e281682b 5301
b4ff3a36 5302 u8 reserved_at_20[0x10];
e281682b
SM		 5303 u8 op_mod[0x10];
5304
5305 u8 rq_state[0x4];
b4ff3a36 5306 u8 reserved_at_44[0x4];
e281682b
SM		 5307 u8 rqn[0x18];
5308
b4ff3a36 5309 u8 reserved_at_60[0x20];
e281682b
SM		 5310
5311 u8 modify_bitmask[0x40];
5312
b4ff3a36 5313 u8 reserved_at_c0[0x40];
e281682b
SM		 5314
5315 struct mlx5_ifc_rqc_bits ctx;
5316};
5317
5318struct mlx5_ifc_modify_rmp_out_bits {
5319 u8 status[0x8];
b4ff3a36 5320 u8 reserved_at_8[0x18];
e281682b
SM		 5321
5322 u8 syndrome[0x20];
5323
b4ff3a36 5324 u8 reserved_at_40[0x40];
e281682b
SM		 5325};
5326
01949d01 5327struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5328 u8 reserved_at_0[0x20];
01949d01 5329
b4ff3a36 5330 u8 reserved_at_20[0x1f];
01949d01
HA		 5331 u8 lwm[0x1];
5332};
5333
e281682b
SM		 5334struct mlx5_ifc_modify_rmp_in_bits {
5335 u8 opcode[0x10];
b4ff3a36 5336 u8 reserved_at_10[0x10];
e281682b 5337
b4ff3a36 5338 u8 reserved_at_20[0x10];
e281682b
SM		 5339 u8 op_mod[0x10];
5340
5341 u8 rmp_state[0x4];
b4ff3a36 5342 u8 reserved_at_44[0x4];
e281682b
SM		 5343 u8 rmpn[0x18];
5344
b4ff3a36 5345 u8 reserved_at_60[0x20];
e281682b 5346
01949d01 5347 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5348
b4ff3a36 5349 u8 reserved_at_c0[0x40];
e281682b
SM		 5350
5351 struct mlx5_ifc_rmpc_bits ctx;
5352};
5353
5354struct mlx5_ifc_modify_nic_vport_context_out_bits {
5355 u8 status[0x8];
b4ff3a36 5356 u8 reserved_at_8[0x18];
e281682b
SM		 5357
5358 u8 syndrome[0x20];
5359
b4ff3a36 5360 u8 reserved_at_40[0x40];
e281682b
SM		 5361};
5362
5363struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5364 u8 reserved_at_0[0x12];
5365 u8 affiliation[0x1];
5366 u8 reserved_at_e[0x1];
bded747b
HN		 5367 u8 disable_uc_local_lb[0x1];
5368 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5369 u8 node_guid[0x1];
5370 u8 port_guid[0x1];
9def7121 5371 u8 min_inline[0x1];
d82b7318
SM		 5372 u8 mtu[0x1];
5373 u8 change_event[0x1];
5374 u8 promisc[0x1];
e281682b
SM		 5375 u8 permanent_address[0x1];
5376 u8 addresses_list[0x1];
5377 u8 roce_en[0x1];
b4ff3a36 5378 u8 reserved_at_1f[0x1];
e281682b
SM		 5379};
5380
5381struct mlx5_ifc_modify_nic_vport_context_in_bits {
5382 u8 opcode[0x10];
b4ff3a36 5383 u8 reserved_at_10[0x10];
e281682b 5384
b4ff3a36 5385 u8 reserved_at_20[0x10];
e281682b
SM		 5386 u8 op_mod[0x10];
5387
5388 u8 other_vport[0x1];
b4ff3a36 5389 u8 reserved_at_41[0xf];
e281682b
SM		 5390 u8 vport_number[0x10];
5391
5392 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5393
b4ff3a36 5394 u8 reserved_at_80[0x780];
e281682b
SM		 5395
5396 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5397};
5398
5399struct mlx5_ifc_modify_hca_vport_context_out_bits {
5400 u8 status[0x8];
b4ff3a36 5401 u8 reserved_at_8[0x18];
e281682b
SM		 5402
5403 u8 syndrome[0x20];
5404
b4ff3a36 5405 u8 reserved_at_40[0x40];
e281682b
SM		 5406};
5407
5408struct mlx5_ifc_modify_hca_vport_context_in_bits {
5409 u8 opcode[0x10];
b4ff3a36 5410 u8 reserved_at_10[0x10];
e281682b 5411
b4ff3a36 5412 u8 reserved_at_20[0x10];
e281682b
SM		 5413 u8 op_mod[0x10];
5414
5415 u8 other_vport[0x1];
b4ff3a36 5416 u8 reserved_at_41[0xb];
707c4602 5417 u8 port_num[0x4];
e281682b
SM		 5418 u8 vport_number[0x10];
5419
b4ff3a36 5420 u8 reserved_at_60[0x20];
e281682b
SM		 5421
5422 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5423};
5424
5425struct mlx5_ifc_modify_cq_out_bits {
5426 u8 status[0x8];
b4ff3a36 5427 u8 reserved_at_8[0x18];
e281682b
SM		 5428
5429 u8 syndrome[0x20];
5430
b4ff3a36 5431 u8 reserved_at_40[0x40];
e281682b
SM		 5432};
5433
5434enum {
5435 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5436 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5437};
5438
5439struct mlx5_ifc_modify_cq_in_bits {
5440 u8 opcode[0x10];
b4ff3a36 5441 u8 reserved_at_10[0x10];
e281682b 5442
b4ff3a36 5443 u8 reserved_at_20[0x10];
e281682b
SM		 5444 u8 op_mod[0x10];
5445
b4ff3a36 5446 u8 reserved_at_40[0x8];
e281682b
SM		 5447 u8 cqn[0x18];
5448
5449 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5450
5451 struct mlx5_ifc_cqc_bits cq_context;
5452
b4ff3a36 5453 u8 reserved_at_280[0x600];
e281682b
SM		 5454
5455 u8 pas[0][0x40];
5456};
5457
5458struct mlx5_ifc_modify_cong_status_out_bits {
5459 u8 status[0x8];
b4ff3a36 5460 u8 reserved_at_8[0x18];
e281682b
SM		 5461
5462 u8 syndrome[0x20];
5463
b4ff3a36 5464 u8 reserved_at_40[0x40];
e281682b
SM		 5465};
5466
5467struct mlx5_ifc_modify_cong_status_in_bits {
5468 u8 opcode[0x10];
b4ff3a36 5469 u8 reserved_at_10[0x10];
e281682b 5470
b4ff3a36 5471 u8 reserved_at_20[0x10];
e281682b
SM		 5472 u8 op_mod[0x10];
5473
b4ff3a36 5474 u8 reserved_at_40[0x18];
e281682b
SM		 5475 u8 priority[0x4];
5476 u8 cong_protocol[0x4];
5477
5478 u8 enable[0x1];
5479 u8 tag_enable[0x1];
b4ff3a36 5480 u8 reserved_at_62[0x1e];
e281682b
SM		 5481};
5482
5483struct mlx5_ifc_modify_cong_params_out_bits {
5484 u8 status[0x8];
b4ff3a36 5485 u8 reserved_at_8[0x18];
e281682b
SM		 5486
5487 u8 syndrome[0x20];
5488
b4ff3a36 5489 u8 reserved_at_40[0x40];
e281682b
SM		 5490};
5491
5492struct mlx5_ifc_modify_cong_params_in_bits {
5493 u8 opcode[0x10];
b4ff3a36 5494 u8 reserved_at_10[0x10];
e281682b 5495
b4ff3a36 5496 u8 reserved_at_20[0x10];
e281682b
SM		 5497 u8 op_mod[0x10];
5498
b4ff3a36 5499 u8 reserved_at_40[0x1c];
e281682b
SM		 5500 u8 cong_protocol[0x4];
5501
5502 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5503
b4ff3a36 5504 u8 reserved_at_80[0x80];
e281682b
SM		 5505
5506 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5507};
5508
5509struct mlx5_ifc_manage_pages_out_bits {
5510 u8 status[0x8];
b4ff3a36 5511 u8 reserved_at_8[0x18];
e281682b
SM		 5512
5513 u8 syndrome[0x20];
5514
5515 u8 output_num_entries[0x20];
5516
b4ff3a36 5517 u8 reserved_at_60[0x20];
e281682b
SM		 5518
5519 u8 pas[0][0x40];
5520};
5521
5522enum {
5523 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5524 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5525 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5526};
5527
5528struct mlx5_ifc_manage_pages_in_bits {
5529 u8 opcode[0x10];
b4ff3a36 5530 u8 reserved_at_10[0x10];
e281682b 5531
b4ff3a36 5532 u8 reserved_at_20[0x10];
e281682b
SM		 5533 u8 op_mod[0x10];
5534
b4ff3a36 5535 u8 reserved_at_40[0x10];
e281682b
SM		 5536 u8 function_id[0x10];
5537
5538 u8 input_num_entries[0x20];
5539
5540 u8 pas[0][0x40];
5541};
5542
5543struct mlx5_ifc_mad_ifc_out_bits {
5544 u8 status[0x8];
b4ff3a36 5545 u8 reserved_at_8[0x18];
e281682b
SM		 5546
5547 u8 syndrome[0x20];
5548
b4ff3a36 5549 u8 reserved_at_40[0x40];
e281682b
SM		 5550
5551 u8 response_mad_packet[256][0x8];
5552};
5553
5554struct mlx5_ifc_mad_ifc_in_bits {
5555 u8 opcode[0x10];
b4ff3a36 5556 u8 reserved_at_10[0x10];
e281682b 5557
b4ff3a36 5558 u8 reserved_at_20[0x10];
e281682b
SM		 5559 u8 op_mod[0x10];
5560
5561 u8 remote_lid[0x10];
b4ff3a36 5562 u8 reserved_at_50[0x8];
e281682b
SM		 5563 u8 port[0x8];
5564
b4ff3a36 5565 u8 reserved_at_60[0x20];
e281682b
SM		 5566
5567 u8 mad[256][0x8];
5568};
5569
5570struct mlx5_ifc_init_hca_out_bits {
5571 u8 status[0x8];
b4ff3a36 5572 u8 reserved_at_8[0x18];
e281682b
SM		 5573
5574 u8 syndrome[0x20];
5575
b4ff3a36 5576 u8 reserved_at_40[0x40];
e281682b
SM		 5577};
5578
5579struct mlx5_ifc_init_hca_in_bits {
5580 u8 opcode[0x10];
b4ff3a36 5581 u8 reserved_at_10[0x10];
e281682b 5582
b4ff3a36 5583 u8 reserved_at_20[0x10];
e281682b
SM		 5584 u8 op_mod[0x10];
5585
b4ff3a36 5586 u8 reserved_at_40[0x40];
8737f818 5587 u8 sw_owner_id[4][0x20];
e281682b
SM		 5588};
5589
5590struct mlx5_ifc_init2rtr_qp_out_bits {
5591 u8 status[0x8];
b4ff3a36 5592 u8 reserved_at_8[0x18];
e281682b
SM		 5593
5594 u8 syndrome[0x20];
5595
b4ff3a36 5596 u8 reserved_at_40[0x40];
e281682b
SM		 5597};
5598
5599struct mlx5_ifc_init2rtr_qp_in_bits {
5600 u8 opcode[0x10];
b4ff3a36 5601 u8 reserved_at_10[0x10];
e281682b 5602
b4ff3a36 5603 u8 reserved_at_20[0x10];
e281682b
SM		 5604 u8 op_mod[0x10];
5605
b4ff3a36 5606 u8 reserved_at_40[0x8];
e281682b
SM		 5607 u8 qpn[0x18];
5608
b4ff3a36 5609 u8 reserved_at_60[0x20];
e281682b
SM		 5610
5611 u8 opt_param_mask[0x20];
5612
b4ff3a36 5613 u8 reserved_at_a0[0x20];
e281682b
SM		 5614
5615 struct mlx5_ifc_qpc_bits qpc;
5616
b4ff3a36 5617 u8 reserved_at_800[0x80];
e281682b
SM		 5618};
5619
5620struct mlx5_ifc_init2init_qp_out_bits {
5621 u8 status[0x8];
b4ff3a36 5622 u8 reserved_at_8[0x18];
e281682b
SM		 5623
5624 u8 syndrome[0x20];
5625
b4ff3a36 5626 u8 reserved_at_40[0x40];
e281682b
SM		 5627};
5628
5629struct mlx5_ifc_init2init_qp_in_bits {
5630 u8 opcode[0x10];
b4ff3a36 5631 u8 reserved_at_10[0x10];
e281682b 5632
b4ff3a36 5633 u8 reserved_at_20[0x10];
e281682b
SM		 5634 u8 op_mod[0x10];
5635
b4ff3a36 5636 u8 reserved_at_40[0x8];
e281682b
SM		 5637 u8 qpn[0x18];
5638
b4ff3a36 5639 u8 reserved_at_60[0x20];
e281682b
SM		 5640
5641 u8 opt_param_mask[0x20];
5642
b4ff3a36 5643 u8 reserved_at_a0[0x20];
e281682b
SM		 5644
5645 struct mlx5_ifc_qpc_bits qpc;
5646
b4ff3a36 5647 u8 reserved_at_800[0x80];
e281682b
SM		 5648};
5649
5650struct mlx5_ifc_get_dropped_packet_log_out_bits {
5651 u8 status[0x8];
b4ff3a36 5652 u8 reserved_at_8[0x18];
e281682b
SM		 5653
5654 u8 syndrome[0x20];
5655
b4ff3a36 5656 u8 reserved_at_40[0x40];
e281682b
SM		 5657
5658 u8 packet_headers_log[128][0x8];
5659
5660 u8 packet_syndrome[64][0x8];
5661};
5662
5663struct mlx5_ifc_get_dropped_packet_log_in_bits {
5664 u8 opcode[0x10];
b4ff3a36 5665 u8 reserved_at_10[0x10];
e281682b 5666
b4ff3a36 5667 u8 reserved_at_20[0x10];
e281682b
SM		 5668 u8 op_mod[0x10];
5669
b4ff3a36 5670 u8 reserved_at_40[0x40];
e281682b
SM		 5671};
5672
5673struct mlx5_ifc_gen_eqe_in_bits {
5674 u8 opcode[0x10];
b4ff3a36 5675 u8 reserved_at_10[0x10];
e281682b 5676
b4ff3a36 5677 u8 reserved_at_20[0x10];
e281682b
SM		 5678 u8 op_mod[0x10];
5679
b4ff3a36 5680 u8 reserved_at_40[0x18];
e281682b
SM		 5681 u8 eq_number[0x8];
5682
b4ff3a36 5683 u8 reserved_at_60[0x20];
e281682b
SM		 5684
5685 u8 eqe[64][0x8];
5686};
5687
5688struct mlx5_ifc_gen_eq_out_bits {
5689 u8 status[0x8];
b4ff3a36 5690 u8 reserved_at_8[0x18];
e281682b
SM		 5691
5692 u8 syndrome[0x20];
5693
b4ff3a36 5694 u8 reserved_at_40[0x40];
e281682b
SM		 5695};
5696
5697struct mlx5_ifc_enable_hca_out_bits {
5698 u8 status[0x8];
b4ff3a36 5699 u8 reserved_at_8[0x18];
e281682b
SM		 5700
5701 u8 syndrome[0x20];
5702
b4ff3a36 5703 u8 reserved_at_40[0x20];
e281682b
SM		 5704};
5705
5706struct mlx5_ifc_enable_hca_in_bits {
5707 u8 opcode[0x10];
b4ff3a36 5708 u8 reserved_at_10[0x10];
e281682b 5709
b4ff3a36 5710 u8 reserved_at_20[0x10];
e281682b
SM		 5711 u8 op_mod[0x10];
5712
b4ff3a36 5713 u8 reserved_at_40[0x10];
e281682b
SM		 5714 u8 function_id[0x10];
5715
b4ff3a36 5716 u8 reserved_at_60[0x20];
e281682b
SM		 5717};
5718
5719struct mlx5_ifc_drain_dct_out_bits {
5720 u8 status[0x8];
b4ff3a36 5721 u8 reserved_at_8[0x18];
e281682b
SM		 5722
5723 u8 syndrome[0x20];
5724
b4ff3a36 5725 u8 reserved_at_40[0x40];
e281682b
SM		 5726};
5727
5728struct mlx5_ifc_drain_dct_in_bits {
5729 u8 opcode[0x10];
b4ff3a36 5730 u8 reserved_at_10[0x10];
e281682b 5731
b4ff3a36 5732 u8 reserved_at_20[0x10];
e281682b
SM		 5733 u8 op_mod[0x10];
5734
b4ff3a36 5735 u8 reserved_at_40[0x8];
e281682b
SM		 5736 u8 dctn[0x18];
5737
b4ff3a36 5738 u8 reserved_at_60[0x20];
e281682b
SM		 5739};
5740
5741struct mlx5_ifc_disable_hca_out_bits {
5742 u8 status[0x8];
b4ff3a36 5743 u8 reserved_at_8[0x18];
e281682b
SM		 5744
5745 u8 syndrome[0x20];
5746
b4ff3a36 5747 u8 reserved_at_40[0x20];
e281682b
SM		 5748};
5749
5750struct mlx5_ifc_disable_hca_in_bits {
5751 u8 opcode[0x10];
b4ff3a36 5752 u8 reserved_at_10[0x10];
e281682b 5753
b4ff3a36 5754 u8 reserved_at_20[0x10];
e281682b
SM		 5755 u8 op_mod[0x10];
5756
b4ff3a36 5757 u8 reserved_at_40[0x10];
e281682b
SM		 5758 u8 function_id[0x10];
5759
b4ff3a36 5760 u8 reserved_at_60[0x20];
e281682b
SM		 5761};
5762
5763struct mlx5_ifc_detach_from_mcg_out_bits {
5764 u8 status[0x8];
b4ff3a36 5765 u8 reserved_at_8[0x18];
e281682b
SM		 5766
5767 u8 syndrome[0x20];
5768
b4ff3a36 5769 u8 reserved_at_40[0x40];
e281682b
SM		 5770};
5771
5772struct mlx5_ifc_detach_from_mcg_in_bits {
5773 u8 opcode[0x10];
b4ff3a36 5774 u8 reserved_at_10[0x10];
e281682b 5775
b4ff3a36 5776 u8 reserved_at_20[0x10];
e281682b
SM		 5777 u8 op_mod[0x10];
5778
b4ff3a36 5779 u8 reserved_at_40[0x8];
e281682b
SM		 5780 u8 qpn[0x18];
5781
b4ff3a36 5782 u8 reserved_at_60[0x20];
e281682b
SM		 5783
5784 u8 multicast_gid[16][0x8];
5785};
5786
7486216b
SM		 5787struct mlx5_ifc_destroy_xrq_out_bits {
5788 u8 status[0x8];
5789 u8 reserved_at_8[0x18];
5790
5791 u8 syndrome[0x20];
5792
5793 u8 reserved_at_40[0x40];
5794};
5795
5796struct mlx5_ifc_destroy_xrq_in_bits {
5797 u8 opcode[0x10];
5798 u8 reserved_at_10[0x10];
5799
5800 u8 reserved_at_20[0x10];
5801 u8 op_mod[0x10];
5802
5803 u8 reserved_at_40[0x8];
5804 u8 xrqn[0x18];
5805
5806 u8 reserved_at_60[0x20];
5807};
5808
e281682b
SM		 5809struct mlx5_ifc_destroy_xrc_srq_out_bits {
5810 u8 status[0x8];
b4ff3a36 5811 u8 reserved_at_8[0x18];
e281682b
SM		 5812
5813 u8 syndrome[0x20];
5814
b4ff3a36 5815 u8 reserved_at_40[0x40];
e281682b
SM		 5816};
5817
5818struct mlx5_ifc_destroy_xrc_srq_in_bits {
5819 u8 opcode[0x10];
b4ff3a36 5820 u8 reserved_at_10[0x10];
e281682b 5821
b4ff3a36 5822 u8 reserved_at_20[0x10];
e281682b
SM		 5823 u8 op_mod[0x10];
5824
b4ff3a36 5825 u8 reserved_at_40[0x8];
e281682b
SM		 5826 u8 xrc_srqn[0x18];
5827
b4ff3a36 5828 u8 reserved_at_60[0x20];
e281682b
SM		 5829};
5830
5831struct mlx5_ifc_destroy_tis_out_bits {
5832 u8 status[0x8];
b4ff3a36 5833 u8 reserved_at_8[0x18];
e281682b
SM		 5834
5835 u8 syndrome[0x20];
5836
b4ff3a36 5837 u8 reserved_at_40[0x40];
e281682b
SM		 5838};
5839
5840struct mlx5_ifc_destroy_tis_in_bits {
5841 u8 opcode[0x10];
b4ff3a36 5842 u8 reserved_at_10[0x10];
e281682b 5843
b4ff3a36 5844 u8 reserved_at_20[0x10];
e281682b
SM		 5845 u8 op_mod[0x10];
5846
b4ff3a36 5847 u8 reserved_at_40[0x8];
e281682b
SM		 5848 u8 tisn[0x18];
5849
b4ff3a36 5850 u8 reserved_at_60[0x20];
e281682b
SM		 5851};
5852
5853struct mlx5_ifc_destroy_tir_out_bits {
5854 u8 status[0x8];
b4ff3a36 5855 u8 reserved_at_8[0x18];
e281682b
SM		 5856
5857 u8 syndrome[0x20];
5858
b4ff3a36 5859 u8 reserved_at_40[0x40];
e281682b
SM		 5860};
5861
5862struct mlx5_ifc_destroy_tir_in_bits {
5863 u8 opcode[0x10];
b4ff3a36 5864 u8 reserved_at_10[0x10];
e281682b 5865
b4ff3a36 5866 u8 reserved_at_20[0x10];
e281682b
SM		 5867 u8 op_mod[0x10];
5868
b4ff3a36 5869 u8 reserved_at_40[0x8];
e281682b
SM		 5870 u8 tirn[0x18];
5871
b4ff3a36 5872 u8 reserved_at_60[0x20];
e281682b
SM		 5873};
5874
5875struct mlx5_ifc_destroy_srq_out_bits {
5876 u8 status[0x8];
b4ff3a36 5877 u8 reserved_at_8[0x18];
e281682b
SM		 5878
5879 u8 syndrome[0x20];
5880
b4ff3a36 5881 u8 reserved_at_40[0x40];
e281682b
SM		 5882};
5883
5884struct mlx5_ifc_destroy_srq_in_bits {
5885 u8 opcode[0x10];
b4ff3a36 5886 u8 reserved_at_10[0x10];
e281682b 5887
b4ff3a36 5888 u8 reserved_at_20[0x10];
e281682b
SM		 5889 u8 op_mod[0x10];
5890
b4ff3a36 5891 u8 reserved_at_40[0x8];
e281682b
SM		 5892 u8 srqn[0x18];
5893
b4ff3a36 5894 u8 reserved_at_60[0x20];
e281682b
SM		 5895};
5896
5897struct mlx5_ifc_destroy_sq_out_bits {
5898 u8 status[0x8];
b4ff3a36 5899 u8 reserved_at_8[0x18];
e281682b
SM		 5900
5901 u8 syndrome[0x20];
5902
b4ff3a36 5903 u8 reserved_at_40[0x40];
e281682b
SM		 5904};
5905
5906struct mlx5_ifc_destroy_sq_in_bits {
5907 u8 opcode[0x10];
b4ff3a36 5908 u8 reserved_at_10[0x10];
e281682b 5909
b4ff3a36 5910 u8 reserved_at_20[0x10];
e281682b
SM		 5911 u8 op_mod[0x10];
5912
b4ff3a36 5913 u8 reserved_at_40[0x8];
e281682b
SM		 5914 u8 sqn[0x18];
5915
b4ff3a36 5916 u8 reserved_at_60[0x20];
e281682b
SM		 5917};
5918
813f8540
MHY		 5919struct mlx5_ifc_destroy_scheduling_element_out_bits {
5920 u8 status[0x8];
5921 u8 reserved_at_8[0x18];
5922
5923 u8 syndrome[0x20];
5924
5925 u8 reserved_at_40[0x1c0];
5926};
5927
5928struct mlx5_ifc_destroy_scheduling_element_in_bits {
5929 u8 opcode[0x10];
5930 u8 reserved_at_10[0x10];
5931
5932 u8 reserved_at_20[0x10];
5933 u8 op_mod[0x10];
5934
5935 u8 scheduling_hierarchy[0x8];
5936 u8 reserved_at_48[0x18];
5937
5938 u8 scheduling_element_id[0x20];
5939
5940 u8 reserved_at_80[0x180];
5941};
5942
e281682b
SM		 5943struct mlx5_ifc_destroy_rqt_out_bits {
5944 u8 status[0x8];
b4ff3a36 5945 u8 reserved_at_8[0x18];
e281682b
SM		 5946
5947 u8 syndrome[0x20];
5948
b4ff3a36 5949 u8 reserved_at_40[0x40];
e281682b
SM		 5950};
5951
5952struct mlx5_ifc_destroy_rqt_in_bits {
5953 u8 opcode[0x10];
b4ff3a36 5954 u8 reserved_at_10[0x10];
e281682b 5955
b4ff3a36 5956 u8 reserved_at_20[0x10];
e281682b
SM		 5957 u8 op_mod[0x10];
5958
b4ff3a36 5959 u8 reserved_at_40[0x8];
e281682b
SM		 5960 u8 rqtn[0x18];
5961
b4ff3a36 5962 u8 reserved_at_60[0x20];
e281682b
SM		 5963};
5964
5965struct mlx5_ifc_destroy_rq_out_bits {
5966 u8 status[0x8];
b4ff3a36 5967 u8 reserved_at_8[0x18];
e281682b
SM		 5968
5969 u8 syndrome[0x20];
5970
b4ff3a36 5971 u8 reserved_at_40[0x40];
e281682b
SM		 5972};
5973
5974struct mlx5_ifc_destroy_rq_in_bits {
5975 u8 opcode[0x10];
b4ff3a36 5976 u8 reserved_at_10[0x10];
e281682b 5977
b4ff3a36 5978 u8 reserved_at_20[0x10];
e281682b
SM		 5979 u8 op_mod[0x10];
5980
b4ff3a36 5981 u8 reserved_at_40[0x8];
e281682b
SM		 5982 u8 rqn[0x18];
5983
b4ff3a36 5984 u8 reserved_at_60[0x20];
e281682b
SM		 5985};
5986
c1e0bfc1
MG		 5987struct mlx5_ifc_set_delay_drop_params_in_bits {
5988 u8 opcode[0x10];
5989 u8 reserved_at_10[0x10];
5990
5991 u8 reserved_at_20[0x10];
5992 u8 op_mod[0x10];
5993
5994 u8 reserved_at_40[0x20];
5995
5996 u8 reserved_at_60[0x10];
5997 u8 delay_drop_timeout[0x10];
5998};
5999
6000struct mlx5_ifc_set_delay_drop_params_out_bits {
6001 u8 status[0x8];
6002 u8 reserved_at_8[0x18];
6003
6004 u8 syndrome[0x20];
6005
6006 u8 reserved_at_40[0x40];
6007};
6008
e281682b
SM		 6009struct mlx5_ifc_destroy_rmp_out_bits {
6010 u8 status[0x8];
b4ff3a36 6011 u8 reserved_at_8[0x18];
e281682b
SM		 6012
6013 u8 syndrome[0x20];
6014
b4ff3a36 6015 u8 reserved_at_40[0x40];
e281682b
SM		 6016};
6017
6018struct mlx5_ifc_destroy_rmp_in_bits {
6019 u8 opcode[0x10];
b4ff3a36 6020 u8 reserved_at_10[0x10];
e281682b 6021
b4ff3a36 6022 u8 reserved_at_20[0x10];
e281682b
SM		 6023 u8 op_mod[0x10];
6024
b4ff3a36 6025 u8 reserved_at_40[0x8];
e281682b
SM		 6026 u8 rmpn[0x18];
6027
b4ff3a36 6028 u8 reserved_at_60[0x20];
e281682b
SM		 6029};
6030
6031struct mlx5_ifc_destroy_qp_out_bits {
6032 u8 status[0x8];
b4ff3a36 6033 u8 reserved_at_8[0x18];
e281682b
SM		 6034
6035 u8 syndrome[0x20];
6036
b4ff3a36 6037 u8 reserved_at_40[0x40];
e281682b
SM		 6038};
6039
6040struct mlx5_ifc_destroy_qp_in_bits {
6041 u8 opcode[0x10];
b4ff3a36 6042 u8 reserved_at_10[0x10];
e281682b 6043
b4ff3a36 6044 u8 reserved_at_20[0x10];
e281682b
SM		 6045 u8 op_mod[0x10];
6046
b4ff3a36 6047 u8 reserved_at_40[0x8];
e281682b
SM		 6048 u8 qpn[0x18];
6049
b4ff3a36 6050 u8 reserved_at_60[0x20];
e281682b
SM		 6051};
6052
6053struct mlx5_ifc_destroy_psv_out_bits {
6054 u8 status[0x8];
b4ff3a36 6055 u8 reserved_at_8[0x18];
e281682b
SM		 6056
6057 u8 syndrome[0x20];
6058
b4ff3a36 6059 u8 reserved_at_40[0x40];
e281682b
SM		 6060};
6061
6062struct mlx5_ifc_destroy_psv_in_bits {
6063 u8 opcode[0x10];
b4ff3a36 6064 u8 reserved_at_10[0x10];
e281682b 6065
b4ff3a36 6066 u8 reserved_at_20[0x10];
e281682b
SM		 6067 u8 op_mod[0x10];
6068
b4ff3a36 6069 u8 reserved_at_40[0x8];
e281682b
SM		 6070 u8 psvn[0x18];
6071
b4ff3a36 6072 u8 reserved_at_60[0x20];
e281682b
SM		 6073};
6074
6075struct mlx5_ifc_destroy_mkey_out_bits {
6076 u8 status[0x8];
b4ff3a36 6077 u8 reserved_at_8[0x18];
e281682b
SM		 6078
6079 u8 syndrome[0x20];
6080
b4ff3a36 6081 u8 reserved_at_40[0x40];
e281682b
SM		 6082};
6083
6084struct mlx5_ifc_destroy_mkey_in_bits {
6085 u8 opcode[0x10];
b4ff3a36 6086 u8 reserved_at_10[0x10];
e281682b 6087
b4ff3a36 6088 u8 reserved_at_20[0x10];
e281682b
SM		 6089 u8 op_mod[0x10];
6090
b4ff3a36 6091 u8 reserved_at_40[0x8];
e281682b
SM		 6092 u8 mkey_index[0x18];
6093
b4ff3a36 6094 u8 reserved_at_60[0x20];
e281682b
SM		 6095};
6096
6097struct mlx5_ifc_destroy_flow_table_out_bits {
6098 u8 status[0x8];
b4ff3a36 6099 u8 reserved_at_8[0x18];
e281682b
SM		 6100
6101 u8 syndrome[0x20];
6102
b4ff3a36 6103 u8 reserved_at_40[0x40];
e281682b
SM		 6104};
6105
6106struct mlx5_ifc_destroy_flow_table_in_bits {
6107 u8 opcode[0x10];
b4ff3a36 6108 u8 reserved_at_10[0x10];
e281682b 6109
b4ff3a36 6110 u8 reserved_at_20[0x10];
e281682b
SM		 6111 u8 op_mod[0x10];
6112
7d5e1423
SM		 6113 u8 other_vport[0x1];
6114 u8 reserved_at_41[0xf];
6115 u8 vport_number[0x10];
6116
6117 u8 reserved_at_60[0x20];
e281682b
SM		 6118
6119 u8 table_type[0x8];
b4ff3a36 6120 u8 reserved_at_88[0x18];
e281682b 6121
b4ff3a36 6122 u8 reserved_at_a0[0x8];
e281682b
SM		 6123 u8 table_id[0x18];
6124
b4ff3a36 6125 u8 reserved_at_c0[0x140];
e281682b
SM		 6126};
6127
6128struct mlx5_ifc_destroy_flow_group_out_bits {
6129 u8 status[0x8];
b4ff3a36 6130 u8 reserved_at_8[0x18];
e281682b
SM		 6131
6132 u8 syndrome[0x20];
6133
b4ff3a36 6134 u8 reserved_at_40[0x40];
e281682b
SM		 6135};
6136
6137struct mlx5_ifc_destroy_flow_group_in_bits {
6138 u8 opcode[0x10];
b4ff3a36 6139 u8 reserved_at_10[0x10];
e281682b 6140
b4ff3a36 6141 u8 reserved_at_20[0x10];
e281682b
SM		 6142 u8 op_mod[0x10];
6143
7d5e1423
SM		 6144 u8 other_vport[0x1];
6145 u8 reserved_at_41[0xf];
6146 u8 vport_number[0x10];
6147
6148 u8 reserved_at_60[0x20];
e281682b
SM		 6149
6150 u8 table_type[0x8];
b4ff3a36 6151 u8 reserved_at_88[0x18];
e281682b 6152
b4ff3a36 6153 u8 reserved_at_a0[0x8];
e281682b
SM		 6154 u8 table_id[0x18];
6155
6156 u8 group_id[0x20];
6157
b4ff3a36 6158 u8 reserved_at_e0[0x120];
e281682b
SM		 6159};
6160
6161struct mlx5_ifc_destroy_eq_out_bits {
6162 u8 status[0x8];
b4ff3a36 6163 u8 reserved_at_8[0x18];
e281682b
SM		 6164
6165 u8 syndrome[0x20];
6166
b4ff3a36 6167 u8 reserved_at_40[0x40];
e281682b
SM		 6168};
6169
6170struct mlx5_ifc_destroy_eq_in_bits {
6171 u8 opcode[0x10];
b4ff3a36 6172 u8 reserved_at_10[0x10];
e281682b 6173
b4ff3a36 6174 u8 reserved_at_20[0x10];
e281682b
SM		 6175 u8 op_mod[0x10];
6176
b4ff3a36 6177 u8 reserved_at_40[0x18];
e281682b
SM		 6178 u8 eq_number[0x8];
6179
b4ff3a36 6180 u8 reserved_at_60[0x20];
e281682b
SM		 6181};
6182
6183struct mlx5_ifc_destroy_dct_out_bits {
6184 u8 status[0x8];
b4ff3a36 6185 u8 reserved_at_8[0x18];
e281682b
SM		 6186
6187 u8 syndrome[0x20];
6188
b4ff3a36 6189 u8 reserved_at_40[0x40];
e281682b
SM		 6190};
6191
6192struct mlx5_ifc_destroy_dct_in_bits {
6193 u8 opcode[0x10];
b4ff3a36 6194 u8 reserved_at_10[0x10];
e281682b 6195
b4ff3a36 6196 u8 reserved_at_20[0x10];
e281682b
SM		 6197 u8 op_mod[0x10];
6198
b4ff3a36 6199 u8 reserved_at_40[0x8];
e281682b
SM		 6200 u8 dctn[0x18];
6201
b4ff3a36 6202 u8 reserved_at_60[0x20];
e281682b
SM		 6203};
6204
6205struct mlx5_ifc_destroy_cq_out_bits {
6206 u8 status[0x8];
b4ff3a36 6207 u8 reserved_at_8[0x18];
e281682b
SM		 6208
6209 u8 syndrome[0x20];
6210
b4ff3a36 6211 u8 reserved_at_40[0x40];
e281682b
SM		 6212};
6213
6214struct mlx5_ifc_destroy_cq_in_bits {
6215 u8 opcode[0x10];
b4ff3a36 6216 u8 reserved_at_10[0x10];
e281682b 6217
b4ff3a36 6218 u8 reserved_at_20[0x10];
e281682b
SM		 6219 u8 op_mod[0x10];
6220
b4ff3a36 6221 u8 reserved_at_40[0x8];
e281682b
SM		 6222 u8 cqn[0x18];
6223
b4ff3a36 6224 u8 reserved_at_60[0x20];
e281682b
SM		 6225};
6226
6227struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6228 u8 status[0x8];
b4ff3a36 6229 u8 reserved_at_8[0x18];
e281682b
SM		 6230
6231 u8 syndrome[0x20];
6232
b4ff3a36 6233 u8 reserved_at_40[0x40];
e281682b
SM		 6234};
6235
6236struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6237 u8 opcode[0x10];
b4ff3a36 6238 u8 reserved_at_10[0x10];
e281682b 6239
b4ff3a36 6240 u8 reserved_at_20[0x10];
e281682b
SM		 6241 u8 op_mod[0x10];
6242
b4ff3a36 6243 u8 reserved_at_40[0x20];
e281682b 6244
b4ff3a36 6245 u8 reserved_at_60[0x10];
e281682b
SM		 6246 u8 vxlan_udp_port[0x10];
6247};
6248
6249struct mlx5_ifc_delete_l2_table_entry_out_bits {
6250 u8 status[0x8];
b4ff3a36 6251 u8 reserved_at_8[0x18];
e281682b
SM		 6252
6253 u8 syndrome[0x20];
6254
b4ff3a36 6255 u8 reserved_at_40[0x40];
e281682b
SM		 6256};
6257
6258struct mlx5_ifc_delete_l2_table_entry_in_bits {
6259 u8 opcode[0x10];
b4ff3a36 6260 u8 reserved_at_10[0x10];
e281682b 6261
b4ff3a36 6262 u8 reserved_at_20[0x10];
e281682b
SM		 6263 u8 op_mod[0x10];
6264
b4ff3a36 6265 u8 reserved_at_40[0x60];
e281682b 6266
b4ff3a36 6267 u8 reserved_at_a0[0x8];
e281682b
SM		 6268 u8 table_index[0x18];
6269
b4ff3a36 6270 u8 reserved_at_c0[0x140];
e281682b
SM		 6271};
6272
6273struct mlx5_ifc_delete_fte_out_bits {
6274 u8 status[0x8];
b4ff3a36 6275 u8 reserved_at_8[0x18];
e281682b
SM		 6276
6277 u8 syndrome[0x20];
6278
b4ff3a36 6279 u8 reserved_at_40[0x40];
e281682b
SM		 6280};
6281
6282struct mlx5_ifc_delete_fte_in_bits {
6283 u8 opcode[0x10];
b4ff3a36 6284 u8 reserved_at_10[0x10];
e281682b 6285
b4ff3a36 6286 u8 reserved_at_20[0x10];
e281682b
SM		 6287 u8 op_mod[0x10];
6288
7d5e1423
SM		 6289 u8 other_vport[0x1];
6290 u8 reserved_at_41[0xf];
6291 u8 vport_number[0x10];
6292
6293 u8 reserved_at_60[0x20];
e281682b
SM		 6294
6295 u8 table_type[0x8];
b4ff3a36 6296 u8 reserved_at_88[0x18];
e281682b 6297
b4ff3a36 6298 u8 reserved_at_a0[0x8];
e281682b
SM		 6299 u8 table_id[0x18];
6300
b4ff3a36 6301 u8 reserved_at_c0[0x40];
e281682b
SM		 6302
6303 u8 flow_index[0x20];
6304
b4ff3a36 6305 u8 reserved_at_120[0xe0];
e281682b
SM		 6306};
6307
6308struct mlx5_ifc_dealloc_xrcd_out_bits {
6309 u8 status[0x8];
b4ff3a36 6310 u8 reserved_at_8[0x18];
e281682b
SM		 6311
6312 u8 syndrome[0x20];
6313
b4ff3a36 6314 u8 reserved_at_40[0x40];
e281682b
SM		 6315};
6316
6317struct mlx5_ifc_dealloc_xrcd_in_bits {
6318 u8 opcode[0x10];
b4ff3a36 6319 u8 reserved_at_10[0x10];
e281682b 6320
b4ff3a36 6321 u8 reserved_at_20[0x10];
e281682b
SM		 6322 u8 op_mod[0x10];
6323
b4ff3a36 6324 u8 reserved_at_40[0x8];
e281682b
SM		 6325 u8 xrcd[0x18];
6326
b4ff3a36 6327 u8 reserved_at_60[0x20];
e281682b
SM		 6328};
6329
6330struct mlx5_ifc_dealloc_uar_out_bits {
6331 u8 status[0x8];
b4ff3a36 6332 u8 reserved_at_8[0x18];
e281682b
SM		 6333
6334 u8 syndrome[0x20];
6335
b4ff3a36 6336 u8 reserved_at_40[0x40];
e281682b
SM		 6337};
6338
6339struct mlx5_ifc_dealloc_uar_in_bits {
6340 u8 opcode[0x10];
b4ff3a36 6341 u8 reserved_at_10[0x10];
e281682b 6342
b4ff3a36 6343 u8 reserved_at_20[0x10];
e281682b
SM		 6344 u8 op_mod[0x10];
6345
b4ff3a36 6346 u8 reserved_at_40[0x8];
e281682b
SM		 6347 u8 uar[0x18];
6348
b4ff3a36 6349 u8 reserved_at_60[0x20];
e281682b
SM		 6350};
6351
6352struct mlx5_ifc_dealloc_transport_domain_out_bits {
6353 u8 status[0x8];
b4ff3a36 6354 u8 reserved_at_8[0x18];
e281682b
SM		 6355
6356 u8 syndrome[0x20];
6357
b4ff3a36 6358 u8 reserved_at_40[0x40];
e281682b
SM		 6359};
6360
6361struct mlx5_ifc_dealloc_transport_domain_in_bits {
6362 u8 opcode[0x10];
b4ff3a36 6363 u8 reserved_at_10[0x10];
e281682b 6364
b4ff3a36 6365 u8 reserved_at_20[0x10];
e281682b
SM		 6366 u8 op_mod[0x10];
6367
b4ff3a36 6368 u8 reserved_at_40[0x8];
e281682b
SM		 6369 u8 transport_domain[0x18];
6370
b4ff3a36 6371 u8 reserved_at_60[0x20];
e281682b
SM		 6372};
6373
6374struct mlx5_ifc_dealloc_q_counter_out_bits {
6375 u8 status[0x8];
b4ff3a36 6376 u8 reserved_at_8[0x18];
e281682b
SM		 6377
6378 u8 syndrome[0x20];
6379
b4ff3a36 6380 u8 reserved_at_40[0x40];
e281682b
SM		 6381};
6382
6383struct mlx5_ifc_dealloc_q_counter_in_bits {
6384 u8 opcode[0x10];
b4ff3a36 6385 u8 reserved_at_10[0x10];
e281682b 6386
b4ff3a36 6387 u8 reserved_at_20[0x10];
e281682b
SM		 6388 u8 op_mod[0x10];
6389
b4ff3a36 6390 u8 reserved_at_40[0x18];
e281682b
SM		 6391 u8 counter_set_id[0x8];
6392
b4ff3a36 6393 u8 reserved_at_60[0x20];
e281682b
SM		 6394};
6395
6396struct mlx5_ifc_dealloc_pd_out_bits {
6397 u8 status[0x8];
b4ff3a36 6398 u8 reserved_at_8[0x18];
e281682b
SM		 6399
6400 u8 syndrome[0x20];
6401
b4ff3a36 6402 u8 reserved_at_40[0x40];
e281682b
SM		 6403};
6404
6405struct mlx5_ifc_dealloc_pd_in_bits {
6406 u8 opcode[0x10];
b4ff3a36 6407 u8 reserved_at_10[0x10];
e281682b 6408
b4ff3a36 6409 u8 reserved_at_20[0x10];
e281682b
SM		 6410 u8 op_mod[0x10];
6411
b4ff3a36 6412 u8 reserved_at_40[0x8];
e281682b
SM		 6413 u8 pd[0x18];
6414
b4ff3a36 6415 u8 reserved_at_60[0x20];
e281682b
SM		 6416};
6417
9dc0b289
AV		 6418struct mlx5_ifc_dealloc_flow_counter_out_bits {
6419 u8 status[0x8];
6420 u8 reserved_at_8[0x18];
6421
6422 u8 syndrome[0x20];
6423
6424 u8 reserved_at_40[0x40];
6425};
6426
6427struct mlx5_ifc_dealloc_flow_counter_in_bits {
6428 u8 opcode[0x10];
6429 u8 reserved_at_10[0x10];
6430
6431 u8 reserved_at_20[0x10];
6432 u8 op_mod[0x10];
6433
a8ffcc74 6434 u8 flow_counter_id[0x20];
9dc0b289
AV		 6435
6436 u8 reserved_at_60[0x20];
6437};
6438
7486216b
SM		 6439struct mlx5_ifc_create_xrq_out_bits {
6440 u8 status[0x8];
6441 u8 reserved_at_8[0x18];
6442
6443 u8 syndrome[0x20];
6444
6445 u8 reserved_at_40[0x8];
6446 u8 xrqn[0x18];
6447
6448 u8 reserved_at_60[0x20];
6449};
6450
6451struct mlx5_ifc_create_xrq_in_bits {
6452 u8 opcode[0x10];
6453 u8 reserved_at_10[0x10];
6454
6455 u8 reserved_at_20[0x10];
6456 u8 op_mod[0x10];
6457
6458 u8 reserved_at_40[0x40];
6459
6460 struct mlx5_ifc_xrqc_bits xrq_context;
6461};
6462
e281682b
SM		 6463struct mlx5_ifc_create_xrc_srq_out_bits {
6464 u8 status[0x8];
b4ff3a36 6465 u8 reserved_at_8[0x18];
e281682b
SM		 6466
6467 u8 syndrome[0x20];
6468
b4ff3a36 6469 u8 reserved_at_40[0x8];
e281682b
SM		 6470 u8 xrc_srqn[0x18];
6471
b4ff3a36 6472 u8 reserved_at_60[0x20];
e281682b
SM		 6473};
6474
6475struct mlx5_ifc_create_xrc_srq_in_bits {
6476 u8 opcode[0x10];
b4ff3a36 6477 u8 reserved_at_10[0x10];
e281682b 6478
b4ff3a36 6479 u8 reserved_at_20[0x10];
e281682b
SM		 6480 u8 op_mod[0x10];
6481
b4ff3a36 6482 u8 reserved_at_40[0x40];
e281682b
SM		 6483
6484 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6485
b4ff3a36 6486 u8 reserved_at_280[0x600];
e281682b
SM		 6487
6488 u8 pas[0][0x40];
6489};
6490
6491struct mlx5_ifc_create_tis_out_bits {
6492 u8 status[0x8];
b4ff3a36 6493 u8 reserved_at_8[0x18];
e281682b
SM		 6494
6495 u8 syndrome[0x20];
6496
b4ff3a36 6497 u8 reserved_at_40[0x8];
e281682b
SM		 6498 u8 tisn[0x18];
6499
b4ff3a36 6500 u8 reserved_at_60[0x20];
e281682b
SM		 6501};
6502
6503struct mlx5_ifc_create_tis_in_bits {
6504 u8 opcode[0x10];
b4ff3a36 6505 u8 reserved_at_10[0x10];
e281682b 6506
b4ff3a36 6507 u8 reserved_at_20[0x10];
e281682b
SM		 6508 u8 op_mod[0x10];
6509
b4ff3a36 6510 u8 reserved_at_40[0xc0];
e281682b
SM		 6511
6512 struct mlx5_ifc_tisc_bits ctx;
6513};
6514
6515struct mlx5_ifc_create_tir_out_bits {
6516 u8 status[0x8];
b4ff3a36 6517 u8 reserved_at_8[0x18];
e281682b
SM		 6518
6519 u8 syndrome[0x20];
6520
b4ff3a36 6521 u8 reserved_at_40[0x8];
e281682b
SM		 6522 u8 tirn[0x18];
6523
b4ff3a36 6524 u8 reserved_at_60[0x20];
e281682b
SM		 6525};
6526
6527struct mlx5_ifc_create_tir_in_bits {
6528 u8 opcode[0x10];
b4ff3a36 6529 u8 reserved_at_10[0x10];
e281682b 6530
b4ff3a36 6531 u8 reserved_at_20[0x10];
e281682b
SM		 6532 u8 op_mod[0x10];
6533
b4ff3a36 6534 u8 reserved_at_40[0xc0];
e281682b
SM		 6535
6536 struct mlx5_ifc_tirc_bits ctx;
6537};
6538
6539struct mlx5_ifc_create_srq_out_bits {
6540 u8 status[0x8];
b4ff3a36 6541 u8 reserved_at_8[0x18];
e281682b
SM		 6542
6543 u8 syndrome[0x20];
6544
b4ff3a36 6545 u8 reserved_at_40[0x8];
e281682b
SM		 6546 u8 srqn[0x18];
6547
b4ff3a36 6548 u8 reserved_at_60[0x20];
e281682b
SM		 6549};
6550
6551struct mlx5_ifc_create_srq_in_bits {
6552 u8 opcode[0x10];
b4ff3a36 6553 u8 reserved_at_10[0x10];
e281682b 6554
b4ff3a36 6555 u8 reserved_at_20[0x10];
e281682b
SM		 6556 u8 op_mod[0x10];
6557
b4ff3a36 6558 u8 reserved_at_40[0x40];
e281682b
SM		 6559
6560 struct mlx5_ifc_srqc_bits srq_context_entry;
6561
b4ff3a36 6562 u8 reserved_at_280[0x600];
e281682b
SM		 6563
6564 u8 pas[0][0x40];
6565};
6566
6567struct mlx5_ifc_create_sq_out_bits {
6568 u8 status[0x8];
b4ff3a36 6569 u8 reserved_at_8[0x18];
e281682b
SM		 6570
6571 u8 syndrome[0x20];
6572
b4ff3a36 6573 u8 reserved_at_40[0x8];
e281682b
SM		 6574 u8 sqn[0x18];
6575
b4ff3a36 6576 u8 reserved_at_60[0x20];
e281682b
SM		 6577};
6578
6579struct mlx5_ifc_create_sq_in_bits {
6580 u8 opcode[0x10];
b4ff3a36 6581 u8 reserved_at_10[0x10];
e281682b 6582
b4ff3a36 6583 u8 reserved_at_20[0x10];
e281682b
SM		 6584 u8 op_mod[0x10];
6585
b4ff3a36 6586 u8 reserved_at_40[0xc0];
e281682b
SM		 6587
6588 struct mlx5_ifc_sqc_bits ctx;
6589};
6590
813f8540
MHY		 6591struct mlx5_ifc_create_scheduling_element_out_bits {
6592 u8 status[0x8];
6593 u8 reserved_at_8[0x18];
6594
6595 u8 syndrome[0x20];
6596
6597 u8 reserved_at_40[0x40];
6598
6599 u8 scheduling_element_id[0x20];
6600
6601 u8 reserved_at_a0[0x160];
6602};
6603
6604struct mlx5_ifc_create_scheduling_element_in_bits {
6605 u8 opcode[0x10];
6606 u8 reserved_at_10[0x10];
6607
6608 u8 reserved_at_20[0x10];
6609 u8 op_mod[0x10];
6610
6611 u8 scheduling_hierarchy[0x8];
6612 u8 reserved_at_48[0x18];
6613
6614 u8 reserved_at_60[0xa0];
6615
6616 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6617
6618 u8 reserved_at_300[0x100];
6619};
6620
e281682b
SM		 6621struct mlx5_ifc_create_rqt_out_bits {
6622 u8 status[0x8];
b4ff3a36 6623 u8 reserved_at_8[0x18];
e281682b
SM		 6624
6625 u8 syndrome[0x20];
6626
b4ff3a36 6627 u8 reserved_at_40[0x8];
e281682b
SM		 6628 u8 rqtn[0x18];
6629
b4ff3a36 6630 u8 reserved_at_60[0x20];
e281682b
SM		 6631};
6632
6633struct mlx5_ifc_create_rqt_in_bits {
6634 u8 opcode[0x10];
b4ff3a36 6635 u8 reserved_at_10[0x10];
e281682b 6636
b4ff3a36 6637 u8 reserved_at_20[0x10];
e281682b
SM		 6638 u8 op_mod[0x10];
6639
b4ff3a36 6640 u8 reserved_at_40[0xc0];
e281682b
SM		 6641
6642 struct mlx5_ifc_rqtc_bits rqt_context;
6643};
6644
6645struct mlx5_ifc_create_rq_out_bits {
6646 u8 status[0x8];
b4ff3a36 6647 u8 reserved_at_8[0x18];
e281682b
SM		 6648
6649 u8 syndrome[0x20];
6650
b4ff3a36 6651 u8 reserved_at_40[0x8];
e281682b
SM		 6652 u8 rqn[0x18];
6653
b4ff3a36 6654 u8 reserved_at_60[0x20];
e281682b
SM		 6655};
6656
6657struct mlx5_ifc_create_rq_in_bits {
6658 u8 opcode[0x10];
b4ff3a36 6659 u8 reserved_at_10[0x10];
e281682b 6660
b4ff3a36 6661 u8 reserved_at_20[0x10];
e281682b
SM		 6662 u8 op_mod[0x10];
6663
b4ff3a36 6664 u8 reserved_at_40[0xc0];
e281682b
SM		 6665
6666 struct mlx5_ifc_rqc_bits ctx;
6667};
6668
6669struct mlx5_ifc_create_rmp_out_bits {
6670 u8 status[0x8];
b4ff3a36 6671 u8 reserved_at_8[0x18];
e281682b
SM		 6672
6673 u8 syndrome[0x20];
6674
b4ff3a36 6675 u8 reserved_at_40[0x8];
e281682b
SM		 6676 u8 rmpn[0x18];
6677
b4ff3a36 6678 u8 reserved_at_60[0x20];
e281682b
SM		 6679};
6680
6681struct mlx5_ifc_create_rmp_in_bits {
6682 u8 opcode[0x10];
b4ff3a36 6683 u8 reserved_at_10[0x10];
e281682b 6684
b4ff3a36 6685 u8 reserved_at_20[0x10];
e281682b
SM		 6686 u8 op_mod[0x10];
6687
b4ff3a36 6688 u8 reserved_at_40[0xc0];
e281682b
SM		 6689
6690 struct mlx5_ifc_rmpc_bits ctx;
6691};
6692
6693struct mlx5_ifc_create_qp_out_bits {
6694 u8 status[0x8];
b4ff3a36 6695 u8 reserved_at_8[0x18];
e281682b
SM		 6696
6697 u8 syndrome[0x20];
6698
b4ff3a36 6699 u8 reserved_at_40[0x8];
e281682b
SM		 6700 u8 qpn[0x18];
6701
b4ff3a36 6702 u8 reserved_at_60[0x20];
e281682b
SM		 6703};
6704
6705struct mlx5_ifc_create_qp_in_bits {
6706 u8 opcode[0x10];
b4ff3a36 6707 u8 reserved_at_10[0x10];
e281682b 6708
b4ff3a36 6709 u8 reserved_at_20[0x10];
e281682b
SM		 6710 u8 op_mod[0x10];
6711
b4ff3a36 6712 u8 reserved_at_40[0x40];
e281682b
SM		 6713
6714 u8 opt_param_mask[0x20];
6715
b4ff3a36 6716 u8 reserved_at_a0[0x20];
e281682b
SM		 6717
6718 struct mlx5_ifc_qpc_bits qpc;
6719
b4ff3a36 6720 u8 reserved_at_800[0x80];
e281682b
SM		 6721
6722 u8 pas[0][0x40];
6723};
6724
6725struct mlx5_ifc_create_psv_out_bits {
6726 u8 status[0x8];
b4ff3a36 6727 u8 reserved_at_8[0x18];
e281682b
SM		 6728
6729 u8 syndrome[0x20];
6730
b4ff3a36 6731 u8 reserved_at_40[0x40];
e281682b 6732
b4ff3a36 6733 u8 reserved_at_80[0x8];
e281682b
SM		 6734 u8 psv0_index[0x18];
6735
b4ff3a36 6736 u8 reserved_at_a0[0x8];
e281682b
SM		 6737 u8 psv1_index[0x18];
6738
b4ff3a36 6739 u8 reserved_at_c0[0x8];
e281682b
SM		 6740 u8 psv2_index[0x18];
6741
b4ff3a36 6742 u8 reserved_at_e0[0x8];
e281682b
SM		 6743 u8 psv3_index[0x18];
6744};
6745
6746struct mlx5_ifc_create_psv_in_bits {
6747 u8 opcode[0x10];
b4ff3a36 6748 u8 reserved_at_10[0x10];
e281682b 6749
b4ff3a36 6750 u8 reserved_at_20[0x10];
e281682b
SM		 6751 u8 op_mod[0x10];
6752
6753 u8 num_psv[0x4];
b4ff3a36 6754 u8 reserved_at_44[0x4];
e281682b
SM		 6755 u8 pd[0x18];
6756
b4ff3a36 6757 u8 reserved_at_60[0x20];
e281682b
SM		 6758};
6759
6760struct mlx5_ifc_create_mkey_out_bits {
6761 u8 status[0x8];
b4ff3a36 6762 u8 reserved_at_8[0x18];
e281682b
SM		 6763
6764 u8 syndrome[0x20];
6765
b4ff3a36 6766 u8 reserved_at_40[0x8];
e281682b
SM		 6767 u8 mkey_index[0x18];
6768
b4ff3a36 6769 u8 reserved_at_60[0x20];
e281682b
SM		 6770};
6771
6772struct mlx5_ifc_create_mkey_in_bits {
6773 u8 opcode[0x10];
b4ff3a36 6774 u8 reserved_at_10[0x10];
e281682b 6775
b4ff3a36 6776 u8 reserved_at_20[0x10];
e281682b
SM		 6777 u8 op_mod[0x10];
6778
b4ff3a36 6779 u8 reserved_at_40[0x20];
e281682b
SM		 6780
6781 u8 pg_access[0x1];
b4ff3a36 6782 u8 reserved_at_61[0x1f];
e281682b
SM		 6783
6784 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6785
b4ff3a36 6786 u8 reserved_at_280[0x80];
e281682b
SM		 6787
6788 u8 translations_octword_actual_size[0x20];
6789
b4ff3a36 6790 u8 reserved_at_320[0x560];
e281682b
SM		 6791
6792 u8 klm_pas_mtt[0][0x20];
6793};
6794
6795struct mlx5_ifc_create_flow_table_out_bits {
6796 u8 status[0x8];
b4ff3a36 6797 u8 reserved_at_8[0x18];
e281682b
SM		 6798
6799 u8 syndrome[0x20];
6800
b4ff3a36 6801 u8 reserved_at_40[0x8];
e281682b
SM		 6802 u8 table_id[0x18];
6803
b4ff3a36 6804 u8 reserved_at_60[0x20];
e281682b
SM		 6805};
6806
0c90e9c6
MG		 6807struct mlx5_ifc_flow_table_context_bits {
6808 u8 encap_en[0x1];
6809 u8 decap_en[0x1];
6810 u8 reserved_at_2[0x2];
6811 u8 table_miss_action[0x4];
6812 u8 level[0x8];
6813 u8 reserved_at_10[0x8];
6814 u8 log_size[0x8];
6815
6816 u8 reserved_at_20[0x8];
6817 u8 table_miss_id[0x18];
6818
6819 u8 reserved_at_40[0x8];
6820 u8 lag_master_next_table_id[0x18];
6821
6822 u8 reserved_at_60[0xe0];
6823};
6824
e281682b
SM		 6825struct mlx5_ifc_create_flow_table_in_bits {
6826 u8 opcode[0x10];
b4ff3a36 6827 u8 reserved_at_10[0x10];
e281682b 6828
b4ff3a36 6829 u8 reserved_at_20[0x10];
e281682b
SM		 6830 u8 op_mod[0x10];
6831
7d5e1423
SM		 6832 u8 other_vport[0x1];
6833 u8 reserved_at_41[0xf];
6834 u8 vport_number[0x10];
6835
6836 u8 reserved_at_60[0x20];
e281682b
SM		 6837
6838 u8 table_type[0x8];
b4ff3a36 6839 u8 reserved_at_88[0x18];
e281682b 6840
b4ff3a36 6841 u8 reserved_at_a0[0x20];
e281682b 6842
0c90e9c6 6843 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6844};
6845
6846struct mlx5_ifc_create_flow_group_out_bits {
6847 u8 status[0x8];
b4ff3a36 6848 u8 reserved_at_8[0x18];
e281682b
SM		 6849
6850 u8 syndrome[0x20];
6851
b4ff3a36 6852 u8 reserved_at_40[0x8];
e281682b
SM		 6853 u8 group_id[0x18];
6854
b4ff3a36 6855 u8 reserved_at_60[0x20];
e281682b
SM		 6856};
6857
6858enum {
6859 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6860 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6861 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6862};
6863
6864struct mlx5_ifc_create_flow_group_in_bits {
6865 u8 opcode[0x10];
b4ff3a36 6866 u8 reserved_at_10[0x10];
e281682b 6867
b4ff3a36 6868 u8 reserved_at_20[0x10];
e281682b
SM		 6869 u8 op_mod[0x10];
6870
7d5e1423
SM		 6871 u8 other_vport[0x1];
6872 u8 reserved_at_41[0xf];
6873 u8 vport_number[0x10];
6874
6875 u8 reserved_at_60[0x20];
e281682b
SM		 6876
6877 u8 table_type[0x8];
b4ff3a36 6878 u8 reserved_at_88[0x18];
e281682b 6879
b4ff3a36 6880 u8 reserved_at_a0[0x8];
e281682b
SM		 6881 u8 table_id[0x18];
6882
b4ff3a36 6883 u8 reserved_at_c0[0x20];
e281682b
SM		 6884
6885 u8 start_flow_index[0x20];
6886
b4ff3a36 6887 u8 reserved_at_100[0x20];
e281682b
SM		 6888
6889 u8 end_flow_index[0x20];
6890
b4ff3a36 6891 u8 reserved_at_140[0xa0];
e281682b 6892
b4ff3a36 6893 u8 reserved_at_1e0[0x18];
e281682b
SM		 6894 u8 match_criteria_enable[0x8];
6895
6896 struct mlx5_ifc_fte_match_param_bits match_criteria;
6897
b4ff3a36 6898 u8 reserved_at_1200[0xe00];
e281682b
SM		 6899};
6900
6901struct mlx5_ifc_create_eq_out_bits {
6902 u8 status[0x8];
b4ff3a36 6903 u8 reserved_at_8[0x18];
e281682b
SM		 6904
6905 u8 syndrome[0x20];
6906
b4ff3a36 6907 u8 reserved_at_40[0x18];
e281682b
SM		 6908 u8 eq_number[0x8];
6909
b4ff3a36 6910 u8 reserved_at_60[0x20];
e281682b
SM		 6911};
6912
6913struct mlx5_ifc_create_eq_in_bits {
6914 u8 opcode[0x10];
b4ff3a36 6915 u8 reserved_at_10[0x10];
e281682b 6916
b4ff3a36 6917 u8 reserved_at_20[0x10];
e281682b
SM		 6918 u8 op_mod[0x10];
6919
b4ff3a36 6920 u8 reserved_at_40[0x40];
e281682b
SM		 6921
6922 struct mlx5_ifc_eqc_bits eq_context_entry;
6923
b4ff3a36 6924 u8 reserved_at_280[0x40];
e281682b
SM		 6925
6926 u8 event_bitmask[0x40];
6927
b4ff3a36 6928 u8 reserved_at_300[0x580];
e281682b
SM		 6929
6930 u8 pas[0][0x40];
6931};
6932
6933struct mlx5_ifc_create_dct_out_bits {
6934 u8 status[0x8];
b4ff3a36 6935 u8 reserved_at_8[0x18];
e281682b
SM		 6936
6937 u8 syndrome[0x20];
6938
b4ff3a36 6939 u8 reserved_at_40[0x8];
e281682b
SM		 6940 u8 dctn[0x18];
6941
b4ff3a36 6942 u8 reserved_at_60[0x20];
e281682b
SM		 6943};
6944
6945struct mlx5_ifc_create_dct_in_bits {
6946 u8 opcode[0x10];
b4ff3a36 6947 u8 reserved_at_10[0x10];
e281682b 6948
b4ff3a36 6949 u8 reserved_at_20[0x10];
e281682b
SM		 6950 u8 op_mod[0x10];
6951
b4ff3a36 6952 u8 reserved_at_40[0x40];
e281682b
SM		 6953
6954 struct mlx5_ifc_dctc_bits dct_context_entry;
6955
b4ff3a36 6956 u8 reserved_at_280[0x180];
e281682b
SM		 6957};
6958
6959struct mlx5_ifc_create_cq_out_bits {
6960 u8 status[0x8];
b4ff3a36 6961 u8 reserved_at_8[0x18];
e281682b
SM		 6962
6963 u8 syndrome[0x20];
6964
b4ff3a36 6965 u8 reserved_at_40[0x8];
e281682b
SM		 6966 u8 cqn[0x18];
6967
b4ff3a36 6968 u8 reserved_at_60[0x20];
e281682b
SM		 6969};
6970
6971struct mlx5_ifc_create_cq_in_bits {
6972 u8 opcode[0x10];
b4ff3a36 6973 u8 reserved_at_10[0x10];
e281682b 6974
b4ff3a36 6975 u8 reserved_at_20[0x10];
e281682b
SM		 6976 u8 op_mod[0x10];
6977
b4ff3a36 6978 u8 reserved_at_40[0x40];
e281682b
SM		 6979
6980 struct mlx5_ifc_cqc_bits cq_context;
6981
b4ff3a36 6982 u8 reserved_at_280[0x600];
e281682b
SM		 6983
6984 u8 pas[0][0x40];
6985};
6986
6987struct mlx5_ifc_config_int_moderation_out_bits {
6988 u8 status[0x8];
b4ff3a36 6989 u8 reserved_at_8[0x18];
e281682b
SM		 6990
6991 u8 syndrome[0x20];
6992
b4ff3a36 6993 u8 reserved_at_40[0x4];
e281682b
SM		 6994 u8 min_delay[0xc];
6995 u8 int_vector[0x10];
6996
b4ff3a36 6997 u8 reserved_at_60[0x20];
e281682b
SM		 6998};
6999
7000enum {
7001 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7002 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7003};
7004
7005struct mlx5_ifc_config_int_moderation_in_bits {
7006 u8 opcode[0x10];
b4ff3a36 7007 u8 reserved_at_10[0x10];
e281682b 7008
b4ff3a36 7009 u8 reserved_at_20[0x10];
e281682b
SM		 7010 u8 op_mod[0x10];
7011
b4ff3a36 7012 u8 reserved_at_40[0x4];
e281682b
SM		 7013 u8 min_delay[0xc];
7014 u8 int_vector[0x10];
7015
b4ff3a36 7016 u8 reserved_at_60[0x20];
e281682b
SM		 7017};
7018
7019struct mlx5_ifc_attach_to_mcg_out_bits {
7020 u8 status[0x8];
b4ff3a36 7021 u8 reserved_at_8[0x18];
e281682b
SM		 7022
7023 u8 syndrome[0x20];
7024
b4ff3a36 7025 u8 reserved_at_40[0x40];
e281682b
SM		 7026};
7027
7028struct mlx5_ifc_attach_to_mcg_in_bits {
7029 u8 opcode[0x10];
b4ff3a36 7030 u8 reserved_at_10[0x10];
e281682b 7031
b4ff3a36 7032 u8 reserved_at_20[0x10];
e281682b
SM		 7033 u8 op_mod[0x10];
7034
b4ff3a36 7035 u8 reserved_at_40[0x8];
e281682b
SM		 7036 u8 qpn[0x18];
7037
b4ff3a36 7038 u8 reserved_at_60[0x20];
e281682b
SM		 7039
7040 u8 multicast_gid[16][0x8];
7041};
7042
7486216b
SM		 7043struct mlx5_ifc_arm_xrq_out_bits {
7044 u8 status[0x8];
7045 u8 reserved_at_8[0x18];
7046
7047 u8 syndrome[0x20];
7048
7049 u8 reserved_at_40[0x40];
7050};
7051
7052struct mlx5_ifc_arm_xrq_in_bits {
7053 u8 opcode[0x10];
7054 u8 reserved_at_10[0x10];
7055
7056 u8 reserved_at_20[0x10];
7057 u8 op_mod[0x10];
7058
7059 u8 reserved_at_40[0x8];
7060 u8 xrqn[0x18];
7061
7062 u8 reserved_at_60[0x10];
7063 u8 lwm[0x10];
7064};
7065
e281682b
SM		 7066struct mlx5_ifc_arm_xrc_srq_out_bits {
7067 u8 status[0x8];
b4ff3a36 7068 u8 reserved_at_8[0x18];
e281682b
SM		 7069
7070 u8 syndrome[0x20];
7071
b4ff3a36 7072 u8 reserved_at_40[0x40];
e281682b
SM		 7073};
7074
7075enum {
7076 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7077};
7078
7079struct mlx5_ifc_arm_xrc_srq_in_bits {
7080 u8 opcode[0x10];
b4ff3a36 7081 u8 reserved_at_10[0x10];
e281682b 7082
b4ff3a36 7083 u8 reserved_at_20[0x10];
e281682b
SM		 7084 u8 op_mod[0x10];
7085
b4ff3a36 7086 u8 reserved_at_40[0x8];
e281682b
SM		 7087 u8 xrc_srqn[0x18];
7088
b4ff3a36 7089 u8 reserved_at_60[0x10];
e281682b
SM		 7090 u8 lwm[0x10];
7091};
7092
7093struct mlx5_ifc_arm_rq_out_bits {
7094 u8 status[0x8];
b4ff3a36 7095 u8 reserved_at_8[0x18];
e281682b
SM		 7096
7097 u8 syndrome[0x20];
7098
b4ff3a36 7099 u8 reserved_at_40[0x40];
e281682b
SM		 7100};
7101
7102enum {
7486216b
SM		 7103 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7104 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7105};
7106
7107struct mlx5_ifc_arm_rq_in_bits {
7108 u8 opcode[0x10];
b4ff3a36 7109 u8 reserved_at_10[0x10];
e281682b 7110
b4ff3a36 7111 u8 reserved_at_20[0x10];
e281682b
SM		 7112 u8 op_mod[0x10];
7113
b4ff3a36 7114 u8 reserved_at_40[0x8];
e281682b
SM		 7115 u8 srq_number[0x18];
7116
b4ff3a36 7117 u8 reserved_at_60[0x10];
e281682b
SM		 7118 u8 lwm[0x10];
7119};
7120
7121struct mlx5_ifc_arm_dct_out_bits {
7122 u8 status[0x8];
b4ff3a36 7123 u8 reserved_at_8[0x18];
e281682b
SM		 7124
7125 u8 syndrome[0x20];
7126
b4ff3a36 7127 u8 reserved_at_40[0x40];
e281682b
SM		 7128};
7129
7130struct mlx5_ifc_arm_dct_in_bits {
7131 u8 opcode[0x10];
b4ff3a36 7132 u8 reserved_at_10[0x10];
e281682b 7133
b4ff3a36 7134 u8 reserved_at_20[0x10];
e281682b
SM		 7135 u8 op_mod[0x10];
7136
b4ff3a36 7137 u8 reserved_at_40[0x8];
e281682b
SM		 7138 u8 dct_number[0x18];
7139
b4ff3a36 7140 u8 reserved_at_60[0x20];
e281682b
SM		 7141};
7142
7143struct mlx5_ifc_alloc_xrcd_out_bits {
7144 u8 status[0x8];
b4ff3a36 7145 u8 reserved_at_8[0x18];
e281682b
SM		 7146
7147 u8 syndrome[0x20];
7148
b4ff3a36 7149 u8 reserved_at_40[0x8];
e281682b
SM		 7150 u8 xrcd[0x18];
7151
b4ff3a36 7152 u8 reserved_at_60[0x20];
e281682b
SM		 7153};
7154
7155struct mlx5_ifc_alloc_xrcd_in_bits {
7156 u8 opcode[0x10];
b4ff3a36 7157 u8 reserved_at_10[0x10];
e281682b 7158
b4ff3a36 7159 u8 reserved_at_20[0x10];
e281682b
SM		 7160 u8 op_mod[0x10];
7161
b4ff3a36 7162 u8 reserved_at_40[0x40];
e281682b
SM		 7163};
7164
7165struct mlx5_ifc_alloc_uar_out_bits {
7166 u8 status[0x8];
b4ff3a36 7167 u8 reserved_at_8[0x18];
e281682b
SM		 7168
7169 u8 syndrome[0x20];
7170
b4ff3a36 7171 u8 reserved_at_40[0x8];
e281682b
SM		 7172 u8 uar[0x18];
7173
b4ff3a36 7174 u8 reserved_at_60[0x20];
e281682b
SM		 7175};
7176
7177struct mlx5_ifc_alloc_uar_in_bits {
7178 u8 opcode[0x10];
b4ff3a36 7179 u8 reserved_at_10[0x10];
e281682b 7180
b4ff3a36 7181 u8 reserved_at_20[0x10];
e281682b
SM		 7182 u8 op_mod[0x10];
7183
b4ff3a36 7184 u8 reserved_at_40[0x40];
e281682b
SM		 7185};
7186
7187struct mlx5_ifc_alloc_transport_domain_out_bits {
7188 u8 status[0x8];
b4ff3a36 7189 u8 reserved_at_8[0x18];
e281682b
SM		 7190
7191 u8 syndrome[0x20];
7192
b4ff3a36 7193 u8 reserved_at_40[0x8];
e281682b
SM		 7194 u8 transport_domain[0x18];
7195
b4ff3a36 7196 u8 reserved_at_60[0x20];
e281682b
SM		 7197};
7198
7199struct mlx5_ifc_alloc_transport_domain_in_bits {
7200 u8 opcode[0x10];
b4ff3a36 7201 u8 reserved_at_10[0x10];
e281682b 7202
b4ff3a36 7203 u8 reserved_at_20[0x10];
e281682b
SM		 7204 u8 op_mod[0x10];
7205
b4ff3a36 7206 u8 reserved_at_40[0x40];
e281682b
SM		 7207};
7208
7209struct mlx5_ifc_alloc_q_counter_out_bits {
7210 u8 status[0x8];
b4ff3a36 7211 u8 reserved_at_8[0x18];
e281682b
SM		 7212
7213 u8 syndrome[0x20];
7214
b4ff3a36 7215 u8 reserved_at_40[0x18];
e281682b
SM		 7216 u8 counter_set_id[0x8];
7217
b4ff3a36 7218 u8 reserved_at_60[0x20];
e281682b
SM		 7219};
7220
7221struct mlx5_ifc_alloc_q_counter_in_bits {
7222 u8 opcode[0x10];
b4ff3a36 7223 u8 reserved_at_10[0x10];
e281682b 7224
b4ff3a36 7225 u8 reserved_at_20[0x10];
e281682b
SM		 7226 u8 op_mod[0x10];
7227
b4ff3a36 7228 u8 reserved_at_40[0x40];
e281682b
SM		 7229};
7230
7231struct mlx5_ifc_alloc_pd_out_bits {
7232 u8 status[0x8];
b4ff3a36 7233 u8 reserved_at_8[0x18];
e281682b
SM		 7234
7235 u8 syndrome[0x20];
7236
b4ff3a36 7237 u8 reserved_at_40[0x8];
e281682b
SM		 7238 u8 pd[0x18];
7239
b4ff3a36 7240 u8 reserved_at_60[0x20];
e281682b
SM		 7241};
7242
7243struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7244 u8 opcode[0x10];
7245 u8 reserved_at_10[0x10];
7246
7247 u8 reserved_at_20[0x10];
7248 u8 op_mod[0x10];
7249
7250 u8 reserved_at_40[0x40];
7251};
7252
7253struct mlx5_ifc_alloc_flow_counter_out_bits {
7254 u8 status[0x8];
7255 u8 reserved_at_8[0x18];
7256
7257 u8 syndrome[0x20];
7258
a8ffcc74 7259 u8 flow_counter_id[0x20];
9dc0b289
AV		 7260
7261 u8 reserved_at_60[0x20];
7262};
7263
7264struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7265 u8 opcode[0x10];
b4ff3a36 7266 u8 reserved_at_10[0x10];
e281682b 7267
b4ff3a36 7268 u8 reserved_at_20[0x10];
e281682b
SM		 7269 u8 op_mod[0x10];
7270
b4ff3a36 7271 u8 reserved_at_40[0x40];
e281682b
SM		 7272};
7273
7274struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7275 u8 status[0x8];
b4ff3a36 7276 u8 reserved_at_8[0x18];
e281682b
SM		 7277
7278 u8 syndrome[0x20];
7279
b4ff3a36 7280 u8 reserved_at_40[0x40];
e281682b
SM		 7281};
7282
7283struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7284 u8 opcode[0x10];
b4ff3a36 7285 u8 reserved_at_10[0x10];
e281682b 7286
b4ff3a36 7287 u8 reserved_at_20[0x10];
e281682b
SM		 7288 u8 op_mod[0x10];
7289
b4ff3a36 7290 u8 reserved_at_40[0x20];
e281682b 7291
b4ff3a36 7292 u8 reserved_at_60[0x10];
e281682b
SM		 7293 u8 vxlan_udp_port[0x10];
7294};
7295
37e92a9d 7296struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7297 u8 status[0x8];
7298 u8 reserved_at_8[0x18];
7299
7300 u8 syndrome[0x20];
7301
7302 u8 reserved_at_40[0x40];
7303};
7304
37e92a9d 7305struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7306 u8 opcode[0x10];
7307 u8 reserved_at_10[0x10];
7308
7309 u8 reserved_at_20[0x10];
7310 u8 op_mod[0x10];
7311
7312 u8 reserved_at_40[0x10];
7313 u8 rate_limit_index[0x10];
7314
7315 u8 reserved_at_60[0x20];
7316
7317 u8 rate_limit[0x20];
37e92a9d 7318
05d3ac97
BW		 7319 u8 burst_upper_bound[0x20];
7320
7321 u8 reserved_at_c0[0x10];
7322 u8 typical_packet_size[0x10];
7323
7324 u8 reserved_at_e0[0x120];
7486216b
SM		 7325};
7326
e281682b
SM		 7327struct mlx5_ifc_access_register_out_bits {
7328 u8 status[0x8];
b4ff3a36 7329 u8 reserved_at_8[0x18];
e281682b
SM		 7330
7331 u8 syndrome[0x20];
7332
b4ff3a36 7333 u8 reserved_at_40[0x40];
e281682b
SM		 7334
7335 u8 register_data[0][0x20];
7336};
7337
7338enum {
7339 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7340 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7341};
7342
7343struct mlx5_ifc_access_register_in_bits {
7344 u8 opcode[0x10];
b4ff3a36 7345 u8 reserved_at_10[0x10];
e281682b 7346
b4ff3a36 7347 u8 reserved_at_20[0x10];
e281682b
SM		 7348 u8 op_mod[0x10];
7349
b4ff3a36 7350 u8 reserved_at_40[0x10];
e281682b
SM		 7351 u8 register_id[0x10];
7352
7353 u8 argument[0x20];
7354
7355 u8 register_data[0][0x20];
7356};
7357
7358struct mlx5_ifc_sltp_reg_bits {
7359 u8 status[0x4];
7360 u8 version[0x4];
7361 u8 local_port[0x8];
7362 u8 pnat[0x2];
b4ff3a36 7363 u8 reserved_at_12[0x2];
e281682b 7364 u8 lane[0x4];
b4ff3a36 7365 u8 reserved_at_18[0x8];
e281682b 7366
b4ff3a36 7367 u8 reserved_at_20[0x20];
e281682b 7368
b4ff3a36 7369 u8 reserved_at_40[0x7];
e281682b
SM		 7370 u8 polarity[0x1];
7371 u8 ob_tap0[0x8];
7372 u8 ob_tap1[0x8];
7373 u8 ob_tap2[0x8];
7374
b4ff3a36 7375 u8 reserved_at_60[0xc];
e281682b
SM		 7376 u8 ob_preemp_mode[0x4];
7377 u8 ob_reg[0x8];
7378 u8 ob_bias[0x8];
7379
b4ff3a36 7380 u8 reserved_at_80[0x20];
e281682b
SM		 7381};
7382
7383struct mlx5_ifc_slrg_reg_bits {
7384 u8 status[0x4];
7385 u8 version[0x4];
7386 u8 local_port[0x8];
7387 u8 pnat[0x2];
b4ff3a36 7388 u8 reserved_at_12[0x2];
e281682b 7389 u8 lane[0x4];
b4ff3a36 7390 u8 reserved_at_18[0x8];
e281682b
SM		 7391
7392 u8 time_to_link_up[0x10];
b4ff3a36 7393 u8 reserved_at_30[0xc];
e281682b
SM		 7394 u8 grade_lane_speed[0x4];
7395
7396 u8 grade_version[0x8];
7397 u8 grade[0x18];
7398
b4ff3a36 7399 u8 reserved_at_60[0x4];
e281682b
SM		 7400 u8 height_grade_type[0x4];
7401 u8 height_grade[0x18];
7402
7403 u8 height_dz[0x10];
7404 u8 height_dv[0x10];
7405
b4ff3a36 7406 u8 reserved_at_a0[0x10];
e281682b
SM		 7407 u8 height_sigma[0x10];
7408
b4ff3a36 7409 u8 reserved_at_c0[0x20];
e281682b 7410
b4ff3a36 7411 u8 reserved_at_e0[0x4];
e281682b
SM		 7412 u8 phase_grade_type[0x4];
7413 u8 phase_grade[0x18];
7414
b4ff3a36 7415 u8 reserved_at_100[0x8];
e281682b 7416 u8 phase_eo_pos[0x8];
b4ff3a36 7417 u8 reserved_at_110[0x8];
e281682b
SM		 7418 u8 phase_eo_neg[0x8];
7419
7420 u8 ffe_set_tested[0x10];
7421 u8 test_errors_per_lane[0x10];
7422};
7423
7424struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7425 u8 reserved_at_0[0x8];
e281682b 7426 u8 local_port[0x8];
b4ff3a36 7427 u8 reserved_at_10[0x10];
e281682b 7428
b4ff3a36 7429 u8 reserved_at_20[0x1c];
e281682b
SM		 7430 u8 vl_hw_cap[0x4];
7431
b4ff3a36 7432 u8 reserved_at_40[0x1c];
e281682b
SM		 7433 u8 vl_admin[0x4];
7434
b4ff3a36 7435 u8 reserved_at_60[0x1c];
e281682b
SM		 7436 u8 vl_operational[0x4];
7437};
7438
7439struct mlx5_ifc_pude_reg_bits {
7440 u8 swid[0x8];
7441 u8 local_port[0x8];
b4ff3a36 7442 u8 reserved_at_10[0x4];
e281682b 7443 u8 admin_status[0x4];
b4ff3a36 7444 u8 reserved_at_18[0x4];
e281682b
SM		 7445 u8 oper_status[0x4];
7446
b4ff3a36 7447 u8 reserved_at_20[0x60];
e281682b
SM		 7448};
7449
7450struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7451 u8 reserved_at_0[0x1];
7486216b 7452 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7453 u8 an_disable_cap[0x1];
7454 u8 reserved_at_3[0x5];
e281682b 7455 u8 local_port[0x8];
b4ff3a36 7456 u8 reserved_at_10[0xd];
e281682b
SM		 7457 u8 proto_mask[0x3];
7458
7486216b
SM		 7459 u8 an_status[0x4];
7460 u8 reserved_at_24[0x3c];
e281682b
SM		 7461
7462 u8 eth_proto_capability[0x20];
7463
7464 u8 ib_link_width_capability[0x10];
7465 u8 ib_proto_capability[0x10];
7466
b4ff3a36 7467 u8 reserved_at_a0[0x20];
e281682b
SM		 7468
7469 u8 eth_proto_admin[0x20];
7470
7471 u8 ib_link_width_admin[0x10];
7472 u8 ib_proto_admin[0x10];
7473
b4ff3a36 7474 u8 reserved_at_100[0x20];
e281682b
SM		 7475
7476 u8 eth_proto_oper[0x20];
7477
7478 u8 ib_link_width_oper[0x10];
7479 u8 ib_proto_oper[0x10];
7480
5b4793f8
EBE		 7481 u8 reserved_at_160[0x1c];
7482 u8 connector_type[0x4];
e281682b
SM		 7483
7484 u8 eth_proto_lp_advertise[0x20];
7485
b4ff3a36 7486 u8 reserved_at_1a0[0x60];
e281682b
SM		 7487};
7488
7d5e1423
SM		 7489struct mlx5_ifc_mlcr_reg_bits {
7490 u8 reserved_at_0[0x8];
7491 u8 local_port[0x8];
7492 u8 reserved_at_10[0x20];
7493
7494 u8 beacon_duration[0x10];
7495 u8 reserved_at_40[0x10];
7496
7497 u8 beacon_remain[0x10];
7498};
7499
e281682b 7500struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7501 u8 reserved_at_0[0x20];
e281682b
SM		 7502
7503 u8 algorithm_options[0x10];
b4ff3a36 7504 u8 reserved_at_30[0x4];
e281682b
SM		 7505 u8 repetitions_mode[0x4];
7506 u8 num_of_repetitions[0x8];
7507
7508 u8 grade_version[0x8];
7509 u8 height_grade_type[0x4];
7510 u8 phase_grade_type[0x4];
7511 u8 height_grade_weight[0x8];
7512 u8 phase_grade_weight[0x8];
7513
7514 u8 gisim_measure_bits[0x10];
7515 u8 adaptive_tap_measure_bits[0x10];
7516
7517 u8 ber_bath_high_error_threshold[0x10];
7518 u8 ber_bath_mid_error_threshold[0x10];
7519
7520 u8 ber_bath_low_error_threshold[0x10];
7521 u8 one_ratio_high_threshold[0x10];
7522
7523 u8 one_ratio_high_mid_threshold[0x10];
7524 u8 one_ratio_low_mid_threshold[0x10];
7525
7526 u8 one_ratio_low_threshold[0x10];
7527 u8 ndeo_error_threshold[0x10];
7528
7529 u8 mixer_offset_step_size[0x10];
b4ff3a36 7530 u8 reserved_at_110[0x8];
e281682b
SM		 7531 u8 mix90_phase_for_voltage_bath[0x8];
7532
7533 u8 mixer_offset_start[0x10];
7534 u8 mixer_offset_end[0x10];
7535
b4ff3a36 7536 u8 reserved_at_140[0x15];
e281682b
SM		 7537 u8 ber_test_time[0xb];
7538};
7539
7540struct mlx5_ifc_pspa_reg_bits {
7541 u8 swid[0x8];
7542 u8 local_port[0x8];
7543 u8 sub_port[0x8];
b4ff3a36 7544 u8 reserved_at_18[0x8];
e281682b 7545
b4ff3a36 7546 u8 reserved_at_20[0x20];
e281682b
SM		 7547};
7548
7549struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7550 u8 reserved_at_0[0x8];
e281682b 7551 u8 local_port[0x8];
b4ff3a36 7552 u8 reserved_at_10[0x5];
e281682b 7553 u8 prio[0x3];
b4ff3a36 7554 u8 reserved_at_18[0x6];
e281682b
SM		 7555 u8 mode[0x2];
7556
b4ff3a36 7557 u8 reserved_at_20[0x20];
e281682b 7558
b4ff3a36 7559 u8 reserved_at_40[0x10];
e281682b
SM		 7560 u8 min_threshold[0x10];
7561
b4ff3a36 7562 u8 reserved_at_60[0x10];
e281682b
SM		 7563 u8 max_threshold[0x10];
7564
b4ff3a36 7565 u8 reserved_at_80[0x10];
e281682b
SM		 7566 u8 mark_probability_denominator[0x10];
7567
b4ff3a36 7568 u8 reserved_at_a0[0x60];
e281682b
SM		 7569};
7570
7571struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7572 u8 reserved_at_0[0x8];
e281682b 7573 u8 local_port[0x8];
b4ff3a36 7574 u8 reserved_at_10[0x10];
e281682b 7575
b4ff3a36 7576 u8 reserved_at_20[0x60];
e281682b 7577
b4ff3a36 7578 u8 reserved_at_80[0x1c];
e281682b
SM		 7579 u8 wrps_admin[0x4];
7580
b4ff3a36 7581 u8 reserved_at_a0[0x1c];
e281682b
SM		 7582 u8 wrps_status[0x4];
7583
b4ff3a36 7584 u8 reserved_at_c0[0x8];
e281682b 7585 u8 up_threshold[0x8];
b4ff3a36 7586 u8 reserved_at_d0[0x8];
e281682b
SM		 7587 u8 down_threshold[0x8];
7588
b4ff3a36 7589 u8 reserved_at_e0[0x20];
e281682b 7590
b4ff3a36 7591 u8 reserved_at_100[0x1c];
e281682b
SM		 7592 u8 srps_admin[0x4];
7593
b4ff3a36 7594 u8 reserved_at_120[0x1c];
e281682b
SM		 7595 u8 srps_status[0x4];
7596
b4ff3a36 7597 u8 reserved_at_140[0x40];
e281682b
SM		 7598};
7599
7600struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7601 u8 reserved_at_0[0x8];
e281682b 7602 u8 local_port[0x8];
b4ff3a36 7603 u8 reserved_at_10[0x10];
e281682b 7604
b4ff3a36 7605 u8 reserved_at_20[0x8];
e281682b 7606 u8 lb_cap[0x8];
b4ff3a36 7607 u8 reserved_at_30[0x8];
e281682b
SM		 7608 u8 lb_en[0x8];
7609};
7610
7611struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7612 u8 reserved_at_0[0x8];
e281682b 7613 u8 local_port[0x8];
b4ff3a36 7614 u8 reserved_at_10[0x10];
e281682b 7615
b4ff3a36 7616 u8 reserved_at_20[0x20];
e281682b
SM		 7617
7618 u8 port_profile_mode[0x8];
7619 u8 static_port_profile[0x8];
7620 u8 active_port_profile[0x8];
b4ff3a36 7621 u8 reserved_at_58[0x8];
e281682b
SM		 7622
7623 u8 retransmission_active[0x8];
7624 u8 fec_mode_active[0x18];
7625
b4ff3a36 7626 u8 reserved_at_80[0x20];
e281682b
SM		 7627};
7628
7629struct mlx5_ifc_ppcnt_reg_bits {
7630 u8 swid[0x8];
7631 u8 local_port[0x8];
7632 u8 pnat[0x2];
b4ff3a36 7633 u8 reserved_at_12[0x8];
e281682b
SM		 7634 u8 grp[0x6];
7635
7636 u8 clr[0x1];
b4ff3a36 7637 u8 reserved_at_21[0x1c];
e281682b
SM		 7638 u8 prio_tc[0x3];
7639
7640 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7641};
7642
8ed1a630
GP		 7643struct mlx5_ifc_mpcnt_reg_bits {
7644 u8 reserved_at_0[0x8];
7645 u8 pcie_index[0x8];
7646 u8 reserved_at_10[0xa];
7647 u8 grp[0x6];
7648
7649 u8 clr[0x1];
7650 u8 reserved_at_21[0x1f];
7651
7652 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7653};
7654
e281682b 7655struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7656 u8 reserved_at_0[0x3];
e281682b 7657 u8 single_mac[0x1];
b4ff3a36 7658 u8 reserved_at_4[0x4];
e281682b
SM		 7659 u8 local_port[0x8];
7660 u8 mac_47_32[0x10];
7661
7662 u8 mac_31_0[0x20];
7663
b4ff3a36 7664 u8 reserved_at_40[0x40];
e281682b
SM		 7665};
7666
7667struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7668 u8 reserved_at_0[0x8];
e281682b 7669 u8 local_port[0x8];
b4ff3a36 7670 u8 reserved_at_10[0x10];
e281682b
SM		 7671
7672 u8 max_mtu[0x10];
b4ff3a36 7673 u8 reserved_at_30[0x10];
e281682b
SM		 7674
7675 u8 admin_mtu[0x10];
b4ff3a36 7676 u8 reserved_at_50[0x10];
e281682b
SM		 7677
7678 u8 oper_mtu[0x10];
b4ff3a36 7679 u8 reserved_at_70[0x10];
e281682b
SM		 7680};
7681
7682struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7683 u8 reserved_at_0[0x8];
e281682b 7684 u8 module[0x8];
b4ff3a36 7685 u8 reserved_at_10[0x10];
e281682b 7686
b4ff3a36 7687 u8 reserved_at_20[0x18];
e281682b
SM		 7688 u8 attenuation_5g[0x8];
7689
b4ff3a36 7690 u8 reserved_at_40[0x18];
e281682b
SM		 7691 u8 attenuation_7g[0x8];
7692
b4ff3a36 7693 u8 reserved_at_60[0x18];
e281682b
SM		 7694 u8 attenuation_12g[0x8];
7695};
7696
7697struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7698 u8 reserved_at_0[0x8];
e281682b 7699 u8 module[0x8];
b4ff3a36 7700 u8 reserved_at_10[0xc];
e281682b
SM		 7701 u8 module_status[0x4];
7702
b4ff3a36 7703 u8 reserved_at_20[0x60];
e281682b
SM		 7704};
7705
7706struct mlx5_ifc_pmpc_reg_bits {
7707 u8 module_state_updated[32][0x8];
7708};
7709
7710struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7711 u8 reserved_at_0[0x4];
e281682b
SM		 7712 u8 mlpn_status[0x4];
7713 u8 local_port[0x8];
b4ff3a36 7714 u8 reserved_at_10[0x10];
e281682b
SM		 7715
7716 u8 e[0x1];
b4ff3a36 7717 u8 reserved_at_21[0x1f];
e281682b
SM		 7718};
7719
7720struct mlx5_ifc_pmlp_reg_bits {
7721 u8 rxtx[0x1];
b4ff3a36 7722 u8 reserved_at_1[0x7];
e281682b 7723 u8 local_port[0x8];
b4ff3a36 7724 u8 reserved_at_10[0x8];
e281682b
SM		 7725 u8 width[0x8];
7726
7727 u8 lane0_module_mapping[0x20];
7728
7729 u8 lane1_module_mapping[0x20];
7730
7731 u8 lane2_module_mapping[0x20];
7732
7733 u8 lane3_module_mapping[0x20];
7734
b4ff3a36 7735 u8 reserved_at_a0[0x160];
e281682b
SM		 7736};
7737
7738struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7739 u8 reserved_at_0[0x8];
e281682b 7740 u8 module[0x8];
b4ff3a36 7741 u8 reserved_at_10[0x4];
e281682b 7742 u8 admin_status[0x4];
b4ff3a36 7743 u8 reserved_at_18[0x4];
e281682b
SM		 7744 u8 oper_status[0x4];
7745
7746 u8 ase[0x1];
7747 u8 ee[0x1];
b4ff3a36 7748 u8 reserved_at_22[0x1c];
e281682b
SM		 7749 u8 e[0x2];
7750
b4ff3a36 7751 u8 reserved_at_40[0x40];
e281682b
SM		 7752};
7753
7754struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7755 u8 reserved_at_0[0x4];
e281682b 7756 u8 profile_id[0xc];
b4ff3a36 7757 u8 reserved_at_10[0x4];
e281682b 7758 u8 proto_mask[0x4];
b4ff3a36 7759 u8 reserved_at_18[0x8];
e281682b 7760
b4ff3a36 7761 u8 reserved_at_20[0x10];
e281682b
SM		 7762 u8 lane_speed[0x10];
7763
b4ff3a36 7764 u8 reserved_at_40[0x17];
e281682b
SM		 7765 u8 lpbf[0x1];
7766 u8 fec_mode_policy[0x8];
7767
7768 u8 retransmission_capability[0x8];
7769 u8 fec_mode_capability[0x18];
7770
7771 u8 retransmission_support_admin[0x8];
7772 u8 fec_mode_support_admin[0x18];
7773
7774 u8 retransmission_request_admin[0x8];
7775 u8 fec_mode_request_admin[0x18];
7776
b4ff3a36 7777 u8 reserved_at_c0[0x80];
e281682b
SM		 7778};
7779
7780struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7781 u8 reserved_at_0[0x8];
e281682b 7782 u8 local_port[0x8];
b4ff3a36 7783 u8 reserved_at_10[0x8];
e281682b
SM		 7784 u8 ib_port[0x8];
7785
b4ff3a36 7786 u8 reserved_at_20[0x60];
e281682b
SM		 7787};
7788
7789struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7790 u8 reserved_at_0[0x8];
e281682b 7791 u8 local_port[0x8];
b4ff3a36 7792 u8 reserved_at_10[0xd];
e281682b
SM		 7793 u8 lbf_mode[0x3];
7794
b4ff3a36 7795 u8 reserved_at_20[0x20];
e281682b
SM		 7796};
7797
7798struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7799 u8 reserved_at_0[0x8];
e281682b 7800 u8 local_port[0x8];
b4ff3a36 7801 u8 reserved_at_10[0x10];
e281682b
SM		 7802
7803 u8 dic[0x1];
b4ff3a36 7804 u8 reserved_at_21[0x19];
e281682b 7805 u8 ipg[0x4];
b4ff3a36 7806 u8 reserved_at_3e[0x2];
e281682b
SM		 7807};
7808
7809struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7810 u8 reserved_at_0[0x8];
e281682b 7811 u8 local_port[0x8];
b4ff3a36 7812 u8 reserved_at_10[0x10];
e281682b 7813
b4ff3a36 7814 u8 reserved_at_20[0xe0];
e281682b
SM		 7815
7816 u8 port_filter[8][0x20];
7817
7818 u8 port_filter_update_en[8][0x20];
7819};
7820
7821struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7822 u8 reserved_at_0[0x8];
e281682b 7823 u8 local_port[0x8];
b4ff3a36 7824 u8 reserved_at_10[0x10];
e281682b
SM		 7825
7826 u8 ppan[0x4];
b4ff3a36 7827 u8 reserved_at_24[0x4];
e281682b 7828 u8 prio_mask_tx[0x8];
b4ff3a36 7829 u8 reserved_at_30[0x8];
e281682b
SM		 7830 u8 prio_mask_rx[0x8];
7831
7832 u8 pptx[0x1];
7833 u8 aptx[0x1];
b4ff3a36 7834 u8 reserved_at_42[0x6];
e281682b 7835 u8 pfctx[0x8];
b4ff3a36 7836 u8 reserved_at_50[0x10];
e281682b
SM		 7837
7838 u8 pprx[0x1];
7839 u8 aprx[0x1];
b4ff3a36 7840 u8 reserved_at_62[0x6];
e281682b 7841 u8 pfcrx[0x8];
b4ff3a36 7842 u8 reserved_at_70[0x10];
e281682b 7843
b4ff3a36 7844 u8 reserved_at_80[0x80];
e281682b
SM		 7845};
7846
7847struct mlx5_ifc_pelc_reg_bits {
7848 u8 op[0x4];
b4ff3a36 7849 u8 reserved_at_4[0x4];
e281682b 7850 u8 local_port[0x8];
b4ff3a36 7851 u8 reserved_at_10[0x10];
e281682b
SM		 7852
7853 u8 op_admin[0x8];
7854 u8 op_capability[0x8];
7855 u8 op_request[0x8];
7856 u8 op_active[0x8];
7857
7858 u8 admin[0x40];
7859
7860 u8 capability[0x40];
7861
7862 u8 request[0x40];
7863
7864 u8 active[0x40];
7865
b4ff3a36 7866 u8 reserved_at_140[0x80];
e281682b
SM		 7867};
7868
7869struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7870 u8 reserved_at_0[0x8];
e281682b 7871 u8 local_port[0x8];
b4ff3a36 7872 u8 reserved_at_10[0x10];
e281682b 7873
b4ff3a36 7874 u8 reserved_at_20[0xc];
e281682b 7875 u8 error_count[0x4];
b4ff3a36 7876 u8 reserved_at_30[0x10];
e281682b 7877
b4ff3a36 7878 u8 reserved_at_40[0xc];
e281682b 7879 u8 lane[0x4];
b4ff3a36 7880 u8 reserved_at_50[0x8];
e281682b
SM		 7881 u8 error_type[0x8];
7882};
7883
cfdcbcea 7884struct mlx5_ifc_pcam_enhanced_features_bits {
2dba0797 7885 u8 reserved_at_0[0x7b];
cfdcbcea 7886
2dba0797 7887 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 7888 u8 ptys_connector_type[0x1];
7889 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 7890 u8 ppcnt_discard_group[0x1];
7891 u8 ppcnt_statistical_group[0x1];
7892};
7893
7894struct mlx5_ifc_pcam_reg_bits {
7895 u8 reserved_at_0[0x8];
7896 u8 feature_group[0x8];
7897 u8 reserved_at_10[0x8];
7898 u8 access_reg_group[0x8];
7899
7900 u8 reserved_at_20[0x20];
7901
7902 union {
7903 u8 reserved_at_0[0x80];
7904 } port_access_reg_cap_mask;
7905
7906 u8 reserved_at_c0[0x80];
7907
7908 union {
7909 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7910 u8 reserved_at_0[0x80];
7911 } feature_cap_mask;
7912
7913 u8 reserved_at_1c0[0xc0];
7914};
7915
7916struct mlx5_ifc_mcam_enhanced_features_bits {
5405fa26
GP		 7917 u8 reserved_at_0[0x7b];
7918 u8 pcie_outbound_stalled[0x1];
efae7f78 7919 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 7920 u8 mtpps_enh_out_per_adj[0x1];
7921 u8 mtpps_fs[0x1];
cfdcbcea
GP		 7922 u8 pcie_performance_group[0x1];
7923};
7924
0ab87743
OG		 7925struct mlx5_ifc_mcam_access_reg_bits {
7926 u8 reserved_at_0[0x1c];
7927 u8 mcda[0x1];
7928 u8 mcc[0x1];
7929 u8 mcqi[0x1];
7930 u8 reserved_at_1f[0x1];
7931
7932 u8 regs_95_to_64[0x20];
7933 u8 regs_63_to_32[0x20];
7934 u8 regs_31_to_0[0x20];
7935};
7936
cfdcbcea
GP		 7937struct mlx5_ifc_mcam_reg_bits {
7938 u8 reserved_at_0[0x8];
7939 u8 feature_group[0x8];
7940 u8 reserved_at_10[0x8];
7941 u8 access_reg_group[0x8];
7942
7943 u8 reserved_at_20[0x20];
7944
7945 union {
0ab87743 7946 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 7947 u8 reserved_at_0[0x80];
7948 } mng_access_reg_cap_mask;
7949
7950 u8 reserved_at_c0[0x80];
7951
7952 union {
7953 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7954 u8 reserved_at_0[0x80];
7955 } mng_feature_cap_mask;
7956
7957 u8 reserved_at_1c0[0x80];
7958};
7959
c02762eb
HN		 7960struct mlx5_ifc_qcam_access_reg_cap_mask {
7961 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
7962 u8 qpdpm[0x1];
7963 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
7964 u8 qdpm[0x1];
7965 u8 qpts[0x1];
7966 u8 qcap[0x1];
7967 u8 qcam_access_reg_cap_mask_0[0x1];
7968};
7969
7970struct mlx5_ifc_qcam_qos_feature_cap_mask {
7971 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
7972 u8 qpts_trust_both[0x1];
7973};
7974
7975struct mlx5_ifc_qcam_reg_bits {
7976 u8 reserved_at_0[0x8];
7977 u8 feature_group[0x8];
7978 u8 reserved_at_10[0x8];
7979 u8 access_reg_group[0x8];
7980 u8 reserved_at_20[0x20];
7981
7982 union {
7983 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7984 u8 reserved_at_0[0x80];
7985 } qos_access_reg_cap_mask;
7986
7987 u8 reserved_at_c0[0x80];
7988
7989 union {
7990 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7991 u8 reserved_at_0[0x80];
7992 } qos_feature_cap_mask;
7993
7994 u8 reserved_at_1c0[0x80];
7995};
7996
e281682b 7997struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7998 u8 reserved_at_0[0x8];
e281682b 7999 u8 local_port[0x8];
b4ff3a36 8000 u8 reserved_at_10[0x10];
e281682b
SM		 8001
8002 u8 port_capability_mask[4][0x20];
8003};
8004
8005struct mlx5_ifc_paos_reg_bits {
8006 u8 swid[0x8];
8007 u8 local_port[0x8];
b4ff3a36 8008 u8 reserved_at_10[0x4];
e281682b 8009 u8 admin_status[0x4];
b4ff3a36 8010 u8 reserved_at_18[0x4];
e281682b
SM		 8011 u8 oper_status[0x4];
8012
8013 u8 ase[0x1];
8014 u8 ee[0x1];
b4ff3a36 8015 u8 reserved_at_22[0x1c];
e281682b
SM		 8016 u8 e[0x2];
8017
b4ff3a36 8018 u8 reserved_at_40[0x40];
e281682b
SM		 8019};
8020
8021struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8022 u8 reserved_at_0[0x8];
e281682b 8023 u8 opamp_group[0x8];
b4ff3a36 8024 u8 reserved_at_10[0xc];
e281682b
SM		 8025 u8 opamp_group_type[0x4];
8026
8027 u8 start_index[0x10];
b4ff3a36 8028 u8 reserved_at_30[0x4];
e281682b
SM		 8029 u8 num_of_indices[0xc];
8030
8031 u8 index_data[18][0x10];
8032};
8033
7d5e1423
SM		 8034struct mlx5_ifc_pcmr_reg_bits {
8035 u8 reserved_at_0[0x8];
8036 u8 local_port[0x8];
8037 u8 reserved_at_10[0x2e];
8038 u8 fcs_cap[0x1];
8039 u8 reserved_at_3f[0x1f];
8040 u8 fcs_chk[0x1];
8041 u8 reserved_at_5f[0x1];
8042};
8043
e281682b 8044struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8045 u8 reserved_at_0[0x6];
e281682b 8046 u8 rx_lane[0x2];
b4ff3a36 8047 u8 reserved_at_8[0x6];
e281682b 8048 u8 tx_lane[0x2];
b4ff3a36 8049 u8 reserved_at_10[0x8];
e281682b
SM		 8050 u8 module[0x8];
8051};
8052
8053struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8054 u8 reserved_at_0[0x6];
e281682b
SM		 8055 u8 lossy[0x1];
8056 u8 epsb[0x1];
b4ff3a36 8057 u8 reserved_at_8[0xc];
e281682b
SM		 8058 u8 size[0xc];
8059
8060 u8 xoff_threshold[0x10];
8061 u8 xon_threshold[0x10];
8062};
8063
8064struct mlx5_ifc_set_node_in_bits {
8065 u8 node_description[64][0x8];
8066};
8067
8068struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8069 u8 reserved_at_0[0x18];
e281682b
SM		 8070 u8 power_settings_level[0x8];
8071
b4ff3a36 8072 u8 reserved_at_20[0x60];
e281682b
SM		 8073};
8074
8075struct mlx5_ifc_register_host_endianness_bits {
8076 u8 he[0x1];
b4ff3a36 8077 u8 reserved_at_1[0x1f];
e281682b 8078
b4ff3a36 8079 u8 reserved_at_20[0x60];
e281682b
SM		 8080};
8081
8082struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8083 u8 reserved_at_0[0x20];
e281682b
SM		 8084
8085 u8 mkey[0x20];
8086
8087 u8 addressh_63_32[0x20];
8088
8089 u8 addressl_31_0[0x20];
8090};
8091
8092struct mlx5_ifc_ud_adrs_vector_bits {
8093 u8 dc_key[0x40];
8094
8095 u8 ext[0x1];
b4ff3a36 8096 u8 reserved_at_41[0x7];
e281682b
SM		 8097 u8 destination_qp_dct[0x18];
8098
8099 u8 static_rate[0x4];
8100 u8 sl_eth_prio[0x4];
8101 u8 fl[0x1];
8102 u8 mlid[0x7];
8103 u8 rlid_udp_sport[0x10];
8104
b4ff3a36 8105 u8 reserved_at_80[0x20];
e281682b
SM		 8106
8107 u8 rmac_47_16[0x20];
8108
8109 u8 rmac_15_0[0x10];
8110 u8 tclass[0x8];
8111 u8 hop_limit[0x8];
8112
b4ff3a36 8113 u8 reserved_at_e0[0x1];
e281682b 8114 u8 grh[0x1];
b4ff3a36 8115 u8 reserved_at_e2[0x2];
e281682b
SM		 8116 u8 src_addr_index[0x8];
8117 u8 flow_label[0x14];
8118
8119 u8 rgid_rip[16][0x8];
8120};
8121
8122struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8123 u8 reserved_at_0[0x10];
e281682b
SM		 8124 u8 function_id[0x10];
8125
8126 u8 num_pages[0x20];
8127
b4ff3a36 8128 u8 reserved_at_40[0xa0];
e281682b
SM		 8129};
8130
8131struct mlx5_ifc_eqe_bits {
b4ff3a36 8132 u8 reserved_at_0[0x8];
e281682b 8133 u8 event_type[0x8];
b4ff3a36 8134 u8 reserved_at_10[0x8];
e281682b
SM		 8135 u8 event_sub_type[0x8];
8136
b4ff3a36 8137 u8 reserved_at_20[0xe0];
e281682b
SM		 8138
8139 union mlx5_ifc_event_auto_bits event_data;
8140
b4ff3a36 8141 u8 reserved_at_1e0[0x10];
e281682b 8142 u8 signature[0x8];
b4ff3a36 8143 u8 reserved_at_1f8[0x7];
e281682b
SM		 8144 u8 owner[0x1];
8145};
8146
8147enum {
8148 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8149};
8150
8151struct mlx5_ifc_cmd_queue_entry_bits {
8152 u8 type[0x8];
b4ff3a36 8153 u8 reserved_at_8[0x18];
e281682b
SM		 8154
8155 u8 input_length[0x20];
8156
8157 u8 input_mailbox_pointer_63_32[0x20];
8158
8159 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8160 u8 reserved_at_77[0x9];
e281682b
SM		 8161
8162 u8 command_input_inline_data[16][0x8];
8163
8164 u8 command_output_inline_data[16][0x8];
8165
8166 u8 output_mailbox_pointer_63_32[0x20];
8167
8168 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8169 u8 reserved_at_1b7[0x9];
e281682b
SM		 8170
8171 u8 output_length[0x20];
8172
8173 u8 token[0x8];
8174 u8 signature[0x8];
b4ff3a36 8175 u8 reserved_at_1f0[0x8];
e281682b
SM		 8176 u8 status[0x7];
8177 u8 ownership[0x1];
8178};
8179
8180struct mlx5_ifc_cmd_out_bits {
8181 u8 status[0x8];
b4ff3a36 8182 u8 reserved_at_8[0x18];
e281682b
SM		 8183
8184 u8 syndrome[0x20];
8185
8186 u8 command_output[0x20];
8187};
8188
8189struct mlx5_ifc_cmd_in_bits {
8190 u8 opcode[0x10];
b4ff3a36 8191 u8 reserved_at_10[0x10];
e281682b 8192
b4ff3a36 8193 u8 reserved_at_20[0x10];
e281682b
SM		 8194 u8 op_mod[0x10];
8195
8196 u8 command[0][0x20];
8197};
8198
8199struct mlx5_ifc_cmd_if_box_bits {
8200 u8 mailbox_data[512][0x8];
8201
b4ff3a36 8202 u8 reserved_at_1000[0x180];
e281682b
SM		 8203
8204 u8 next_pointer_63_32[0x20];
8205
8206 u8 next_pointer_31_10[0x16];
b4ff3a36 8207 u8 reserved_at_11b6[0xa];
e281682b
SM		 8208
8209 u8 block_number[0x20];
8210
b4ff3a36 8211 u8 reserved_at_11e0[0x8];
e281682b
SM		 8212 u8 token[0x8];
8213 u8 ctrl_signature[0x8];
8214 u8 signature[0x8];
8215};
8216
8217struct mlx5_ifc_mtt_bits {
8218 u8 ptag_63_32[0x20];
8219
8220 u8 ptag_31_8[0x18];
b4ff3a36 8221 u8 reserved_at_38[0x6];
e281682b
SM		 8222 u8 wr_en[0x1];
8223 u8 rd_en[0x1];
8224};
8225
928cfe87
TT		 8226struct mlx5_ifc_query_wol_rol_out_bits {
8227 u8 status[0x8];
8228 u8 reserved_at_8[0x18];
8229
8230 u8 syndrome[0x20];
8231
8232 u8 reserved_at_40[0x10];
8233 u8 rol_mode[0x8];
8234 u8 wol_mode[0x8];
8235
8236 u8 reserved_at_60[0x20];
8237};
8238
8239struct mlx5_ifc_query_wol_rol_in_bits {
8240 u8 opcode[0x10];
8241 u8 reserved_at_10[0x10];
8242
8243 u8 reserved_at_20[0x10];
8244 u8 op_mod[0x10];
8245
8246 u8 reserved_at_40[0x40];
8247};
8248
8249struct mlx5_ifc_set_wol_rol_out_bits {
8250 u8 status[0x8];
8251 u8 reserved_at_8[0x18];
8252
8253 u8 syndrome[0x20];
8254
8255 u8 reserved_at_40[0x40];
8256};
8257
8258struct mlx5_ifc_set_wol_rol_in_bits {
8259 u8 opcode[0x10];
8260 u8 reserved_at_10[0x10];
8261
8262 u8 reserved_at_20[0x10];
8263 u8 op_mod[0x10];
8264
8265 u8 rol_mode_valid[0x1];
8266 u8 wol_mode_valid[0x1];
8267 u8 reserved_at_42[0xe];
8268 u8 rol_mode[0x8];
8269 u8 wol_mode[0x8];
8270
8271 u8 reserved_at_60[0x20];
8272};
8273
e281682b
SM		 8274enum {
8275 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8276 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8277 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8278};
8279
8280enum {
8281 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8282 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8283 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8284};
8285
8286enum {
8287 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8288 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8289 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8290 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8291 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8292 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8293 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8294 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8295 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8296 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8297 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8298};
8299
8300struct mlx5_ifc_initial_seg_bits {
8301 u8 fw_rev_minor[0x10];
8302 u8 fw_rev_major[0x10];
8303
8304 u8 cmd_interface_rev[0x10];
8305 u8 fw_rev_subminor[0x10];
8306
b4ff3a36 8307 u8 reserved_at_40[0x40];
e281682b
SM		 8308
8309 u8 cmdq_phy_addr_63_32[0x20];
8310
8311 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8312 u8 reserved_at_b4[0x2];
e281682b
SM		 8313 u8 nic_interface[0x2];
8314 u8 log_cmdq_size[0x4];
8315 u8 log_cmdq_stride[0x4];
8316
8317 u8 command_doorbell_vector[0x20];
8318
b4ff3a36 8319 u8 reserved_at_e0[0xf00];
e281682b
SM		 8320
8321 u8 initializing[0x1];
b4ff3a36 8322 u8 reserved_at_fe1[0x4];
e281682b 8323 u8 nic_interface_supported[0x3];
b4ff3a36 8324 u8 reserved_at_fe8[0x18];
e281682b
SM		 8325
8326 struct mlx5_ifc_health_buffer_bits health_buffer;
8327
8328 u8 no_dram_nic_offset[0x20];
8329
b4ff3a36 8330 u8 reserved_at_1220[0x6e40];
e281682b 8331
b4ff3a36 8332 u8 reserved_at_8060[0x1f];
e281682b
SM		 8333 u8 clear_int[0x1];
8334
8335 u8 health_syndrome[0x8];
8336 u8 health_counter[0x18];
8337
b4ff3a36 8338 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8339};
8340
f9a1ef72
EE		 8341struct mlx5_ifc_mtpps_reg_bits {
8342 u8 reserved_at_0[0xc];
8343 u8 cap_number_of_pps_pins[0x4];
8344 u8 reserved_at_10[0x4];
8345 u8 cap_max_num_of_pps_in_pins[0x4];
8346 u8 reserved_at_18[0x4];
8347 u8 cap_max_num_of_pps_out_pins[0x4];
8348
8349 u8 reserved_at_20[0x24];
8350 u8 cap_pin_3_mode[0x4];
8351 u8 reserved_at_48[0x4];
8352 u8 cap_pin_2_mode[0x4];
8353 u8 reserved_at_50[0x4];
8354 u8 cap_pin_1_mode[0x4];
8355 u8 reserved_at_58[0x4];
8356 u8 cap_pin_0_mode[0x4];
8357
8358 u8 reserved_at_60[0x4];
8359 u8 cap_pin_7_mode[0x4];
8360 u8 reserved_at_68[0x4];
8361 u8 cap_pin_6_mode[0x4];
8362 u8 reserved_at_70[0x4];
8363 u8 cap_pin_5_mode[0x4];
8364 u8 reserved_at_78[0x4];
8365 u8 cap_pin_4_mode[0x4];
8366
fa367688
EE		 8367 u8 field_select[0x20];
8368 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8369
8370 u8 enable[0x1];
8371 u8 reserved_at_101[0xb];
8372 u8 pattern[0x4];
8373 u8 reserved_at_110[0x4];
8374 u8 pin_mode[0x4];
8375 u8 pin[0x8];
8376
8377 u8 reserved_at_120[0x20];
8378
8379 u8 time_stamp[0x40];
8380
8381 u8 out_pulse_duration[0x10];
8382 u8 out_periodic_adjustment[0x10];
fa367688 8383 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8384
fa367688 8385 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8386};
8387
8388struct mlx5_ifc_mtppse_reg_bits {
8389 u8 reserved_at_0[0x18];
8390 u8 pin[0x8];
8391 u8 event_arm[0x1];
8392 u8 reserved_at_21[0x1b];
8393 u8 event_generation_mode[0x4];
8394 u8 reserved_at_40[0x40];
8395};
8396
47176289
OG		 8397struct mlx5_ifc_mcqi_cap_bits {
8398 u8 supported_info_bitmask[0x20];
8399
8400 u8 component_size[0x20];
8401
8402 u8 max_component_size[0x20];
8403
8404 u8 log_mcda_word_size[0x4];
8405 u8 reserved_at_64[0xc];
8406 u8 mcda_max_write_size[0x10];
8407
8408 u8 rd_en[0x1];
8409 u8 reserved_at_81[0x1];
8410 u8 match_chip_id[0x1];
8411 u8 match_psid[0x1];
8412 u8 check_user_timestamp[0x1];
8413 u8 match_base_guid_mac[0x1];
8414 u8 reserved_at_86[0x1a];
8415};
8416
8417struct mlx5_ifc_mcqi_reg_bits {
8418 u8 read_pending_component[0x1];
8419 u8 reserved_at_1[0xf];
8420 u8 component_index[0x10];
8421
8422 u8 reserved_at_20[0x20];
8423
8424 u8 reserved_at_40[0x1b];
8425 u8 info_type[0x5];
8426
8427 u8 info_size[0x20];
8428
8429 u8 offset[0x20];
8430
8431 u8 reserved_at_a0[0x10];
8432 u8 data_size[0x10];
8433
8434 u8 data[0][0x20];
8435};
8436
8437struct mlx5_ifc_mcc_reg_bits {
8438 u8 reserved_at_0[0x4];
8439 u8 time_elapsed_since_last_cmd[0xc];
8440 u8 reserved_at_10[0x8];
8441 u8 instruction[0x8];
8442
8443 u8 reserved_at_20[0x10];
8444 u8 component_index[0x10];
8445
8446 u8 reserved_at_40[0x8];
8447 u8 update_handle[0x18];
8448
8449 u8 handle_owner_type[0x4];
8450 u8 handle_owner_host_id[0x4];
8451 u8 reserved_at_68[0x1];
8452 u8 control_progress[0x7];
8453 u8 error_code[0x8];
8454 u8 reserved_at_78[0x4];
8455 u8 control_state[0x4];
8456
8457 u8 component_size[0x20];
8458
8459 u8 reserved_at_a0[0x60];
8460};
8461
8462struct mlx5_ifc_mcda_reg_bits {
8463 u8 reserved_at_0[0x8];
8464 u8 update_handle[0x18];
8465
8466 u8 offset[0x20];
8467
8468 u8 reserved_at_40[0x10];
8469 u8 size[0x10];
8470
8471 u8 reserved_at_60[0x20];
8472
8473 u8 data[0][0x20];
8474};
8475
e281682b
SM		 8476union mlx5_ifc_ports_control_registers_document_bits {
8477 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8478 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8479 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8480 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8481 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8482 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8483 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8484 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8485 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8486 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8487 struct mlx5_ifc_paos_reg_bits paos_reg;
8488 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8489 struct mlx5_ifc_peir_reg_bits peir_reg;
8490 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8491 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8492 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8493 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8494 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8495 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8496 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8497 struct mlx5_ifc_plib_reg_bits plib_reg;
8498 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8499 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8500 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8501 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8502 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8503 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8504 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8505 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8506 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8507 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8508 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8509 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8510 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8511 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8512 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8513 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8514 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8515 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8516 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8517 struct mlx5_ifc_pude_reg_bits pude_reg;
8518 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8519 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8520 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8521 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8522 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8523 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8524 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8525 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8526 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8527 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8528 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8529 u8 reserved_at_0[0x60e0];
e281682b
SM		 8530};
8531
8532union mlx5_ifc_debug_enhancements_document_bits {
8533 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8534 u8 reserved_at_0[0x200];
e281682b
SM		 8535};
8536
8537union mlx5_ifc_uplink_pci_interface_document_bits {
8538 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8539 u8 reserved_at_0[0x20060];
b775516b
EC		 8540};
8541
2cc43b49
MG		 8542struct mlx5_ifc_set_flow_table_root_out_bits {
8543 u8 status[0x8];
b4ff3a36 8544 u8 reserved_at_8[0x18];
2cc43b49
MG		 8545
8546 u8 syndrome[0x20];
8547
b4ff3a36 8548 u8 reserved_at_40[0x40];
2cc43b49
MG		 8549};
8550
8551struct mlx5_ifc_set_flow_table_root_in_bits {
8552 u8 opcode[0x10];
b4ff3a36 8553 u8 reserved_at_10[0x10];
2cc43b49 8554
b4ff3a36 8555 u8 reserved_at_20[0x10];
2cc43b49
MG		 8556 u8 op_mod[0x10];
8557
7d5e1423
SM		 8558 u8 other_vport[0x1];
8559 u8 reserved_at_41[0xf];
8560 u8 vport_number[0x10];
8561
8562 u8 reserved_at_60[0x20];
2cc43b49
MG		 8563
8564 u8 table_type[0x8];
b4ff3a36 8565 u8 reserved_at_88[0x18];
2cc43b49 8566
b4ff3a36 8567 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8568 u8 table_id[0x18];
8569
500a3d0d
ES		 8570 u8 reserved_at_c0[0x8];
8571 u8 underlay_qpn[0x18];
8572 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8573};
8574
34a40e68 8575enum {
84df61eb
AH		 8576 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8577 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8578};
8579
8580struct mlx5_ifc_modify_flow_table_out_bits {
8581 u8 status[0x8];
b4ff3a36 8582 u8 reserved_at_8[0x18];
34a40e68
MG		 8583
8584 u8 syndrome[0x20];
8585
b4ff3a36 8586 u8 reserved_at_40[0x40];
34a40e68
MG		 8587};
8588
8589struct mlx5_ifc_modify_flow_table_in_bits {
8590 u8 opcode[0x10];
b4ff3a36 8591 u8 reserved_at_10[0x10];
34a40e68 8592
b4ff3a36 8593 u8 reserved_at_20[0x10];
34a40e68
MG		 8594 u8 op_mod[0x10];
8595
7d5e1423
SM		 8596 u8 other_vport[0x1];
8597 u8 reserved_at_41[0xf];
8598 u8 vport_number[0x10];
34a40e68 8599
b4ff3a36 8600 u8 reserved_at_60[0x10];
34a40e68
MG		 8601 u8 modify_field_select[0x10];
8602
8603 u8 table_type[0x8];
b4ff3a36 8604 u8 reserved_at_88[0x18];
34a40e68 8605
b4ff3a36 8606 u8 reserved_at_a0[0x8];
34a40e68
MG		 8607 u8 table_id[0x18];
8608
0c90e9c6 8609 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8610};
8611
4f3961ee
SM		 8612struct mlx5_ifc_ets_tcn_config_reg_bits {
8613 u8 g[0x1];
8614 u8 b[0x1];
8615 u8 r[0x1];
8616 u8 reserved_at_3[0x9];
8617 u8 group[0x4];
8618 u8 reserved_at_10[0x9];
8619 u8 bw_allocation[0x7];
8620
8621 u8 reserved_at_20[0xc];
8622 u8 max_bw_units[0x4];
8623 u8 reserved_at_30[0x8];
8624 u8 max_bw_value[0x8];
8625};
8626
8627struct mlx5_ifc_ets_global_config_reg_bits {
8628 u8 reserved_at_0[0x2];
8629 u8 r[0x1];
8630 u8 reserved_at_3[0x1d];
8631
8632 u8 reserved_at_20[0xc];
8633 u8 max_bw_units[0x4];
8634 u8 reserved_at_30[0x8];
8635 u8 max_bw_value[0x8];
8636};
8637
8638struct mlx5_ifc_qetc_reg_bits {
8639 u8 reserved_at_0[0x8];
8640 u8 port_number[0x8];
8641 u8 reserved_at_10[0x30];
8642
8643 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8644 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8645};
8646
415a64aa
HN		 8647struct mlx5_ifc_qpdpm_dscp_reg_bits {
8648 u8 e[0x1];
8649 u8 reserved_at_01[0x0b];
8650 u8 prio[0x04];
8651};
8652
8653struct mlx5_ifc_qpdpm_reg_bits {
8654 u8 reserved_at_0[0x8];
8655 u8 local_port[0x8];
8656 u8 reserved_at_10[0x10];
8657 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8658};
8659
8660struct mlx5_ifc_qpts_reg_bits {
8661 u8 reserved_at_0[0x8];
8662 u8 local_port[0x8];
8663 u8 reserved_at_10[0x2d];
8664 u8 trust_state[0x3];
8665};
8666
4f3961ee
SM		 8667struct mlx5_ifc_qtct_reg_bits {
8668 u8 reserved_at_0[0x8];
8669 u8 port_number[0x8];
8670 u8 reserved_at_10[0xd];
8671 u8 prio[0x3];
8672
8673 u8 reserved_at_20[0x1d];
8674 u8 tclass[0x3];
8675};
8676
7d5e1423
SM		 8677struct mlx5_ifc_mcia_reg_bits {
8678 u8 l[0x1];
8679 u8 reserved_at_1[0x7];
8680 u8 module[0x8];
8681 u8 reserved_at_10[0x8];
8682 u8 status[0x8];
8683
8684 u8 i2c_device_address[0x8];
8685 u8 page_number[0x8];
8686 u8 device_address[0x10];
8687
8688 u8 reserved_at_40[0x10];
8689 u8 size[0x10];
8690
8691 u8 reserved_at_60[0x20];
8692
8693 u8 dword_0[0x20];
8694 u8 dword_1[0x20];
8695 u8 dword_2[0x20];
8696 u8 dword_3[0x20];
8697 u8 dword_4[0x20];
8698 u8 dword_5[0x20];
8699 u8 dword_6[0x20];
8700 u8 dword_7[0x20];
8701 u8 dword_8[0x20];
8702 u8 dword_9[0x20];
8703 u8 dword_10[0x20];
8704 u8 dword_11[0x20];
8705};
8706
7486216b
SM		 8707struct mlx5_ifc_dcbx_param_bits {
8708 u8 dcbx_cee_cap[0x1];
8709 u8 dcbx_ieee_cap[0x1];
8710 u8 dcbx_standby_cap[0x1];
8711 u8 reserved_at_0[0x5];
8712 u8 port_number[0x8];
8713 u8 reserved_at_10[0xa];
8714 u8 max_application_table_size[6];
8715 u8 reserved_at_20[0x15];
8716 u8 version_oper[0x3];
8717 u8 reserved_at_38[5];
8718 u8 version_admin[0x3];
8719 u8 willing_admin[0x1];
8720 u8 reserved_at_41[0x3];
8721 u8 pfc_cap_oper[0x4];
8722 u8 reserved_at_48[0x4];
8723 u8 pfc_cap_admin[0x4];
8724 u8 reserved_at_50[0x4];
8725 u8 num_of_tc_oper[0x4];
8726 u8 reserved_at_58[0x4];
8727 u8 num_of_tc_admin[0x4];
8728 u8 remote_willing[0x1];
8729 u8 reserved_at_61[3];
8730 u8 remote_pfc_cap[4];
8731 u8 reserved_at_68[0x14];
8732 u8 remote_num_of_tc[0x4];
8733 u8 reserved_at_80[0x18];
8734 u8 error[0x8];
8735 u8 reserved_at_a0[0x160];
8736};
84df61eb
AH		 8737
8738struct mlx5_ifc_lagc_bits {
8739 u8 reserved_at_0[0x1d];
8740 u8 lag_state[0x3];
8741
8742 u8 reserved_at_20[0x14];
8743 u8 tx_remap_affinity_2[0x4];
8744 u8 reserved_at_38[0x4];
8745 u8 tx_remap_affinity_1[0x4];
8746};
8747
8748struct mlx5_ifc_create_lag_out_bits {
8749 u8 status[0x8];
8750 u8 reserved_at_8[0x18];
8751
8752 u8 syndrome[0x20];
8753
8754 u8 reserved_at_40[0x40];
8755};
8756
8757struct mlx5_ifc_create_lag_in_bits {
8758 u8 opcode[0x10];
8759 u8 reserved_at_10[0x10];
8760
8761 u8 reserved_at_20[0x10];
8762 u8 op_mod[0x10];
8763
8764 struct mlx5_ifc_lagc_bits ctx;
8765};
8766
8767struct mlx5_ifc_modify_lag_out_bits {
8768 u8 status[0x8];
8769 u8 reserved_at_8[0x18];
8770
8771 u8 syndrome[0x20];
8772
8773 u8 reserved_at_40[0x40];
8774};
8775
8776struct mlx5_ifc_modify_lag_in_bits {
8777 u8 opcode[0x10];
8778 u8 reserved_at_10[0x10];
8779
8780 u8 reserved_at_20[0x10];
8781 u8 op_mod[0x10];
8782
8783 u8 reserved_at_40[0x20];
8784 u8 field_select[0x20];
8785
8786 struct mlx5_ifc_lagc_bits ctx;
8787};
8788
8789struct mlx5_ifc_query_lag_out_bits {
8790 u8 status[0x8];
8791 u8 reserved_at_8[0x18];
8792
8793 u8 syndrome[0x20];
8794
8795 u8 reserved_at_40[0x40];
8796
8797 struct mlx5_ifc_lagc_bits ctx;
8798};
8799
8800struct mlx5_ifc_query_lag_in_bits {
8801 u8 opcode[0x10];
8802 u8 reserved_at_10[0x10];
8803
8804 u8 reserved_at_20[0x10];
8805 u8 op_mod[0x10];
8806
8807 u8 reserved_at_40[0x40];
8808};
8809
8810struct mlx5_ifc_destroy_lag_out_bits {
8811 u8 status[0x8];
8812 u8 reserved_at_8[0x18];
8813
8814 u8 syndrome[0x20];
8815
8816 u8 reserved_at_40[0x40];
8817};
8818
8819struct mlx5_ifc_destroy_lag_in_bits {
8820 u8 opcode[0x10];
8821 u8 reserved_at_10[0x10];
8822
8823 u8 reserved_at_20[0x10];
8824 u8 op_mod[0x10];
8825
8826 u8 reserved_at_40[0x40];
8827};
8828
8829struct mlx5_ifc_create_vport_lag_out_bits {
8830 u8 status[0x8];
8831 u8 reserved_at_8[0x18];
8832
8833 u8 syndrome[0x20];
8834
8835 u8 reserved_at_40[0x40];
8836};
8837
8838struct mlx5_ifc_create_vport_lag_in_bits {
8839 u8 opcode[0x10];
8840 u8 reserved_at_10[0x10];
8841
8842 u8 reserved_at_20[0x10];
8843 u8 op_mod[0x10];
8844
8845 u8 reserved_at_40[0x40];
8846};
8847
8848struct mlx5_ifc_destroy_vport_lag_out_bits {
8849 u8 status[0x8];
8850 u8 reserved_at_8[0x18];
8851
8852 u8 syndrome[0x20];
8853
8854 u8 reserved_at_40[0x40];
8855};
8856
8857struct mlx5_ifc_destroy_vport_lag_in_bits {
8858 u8 opcode[0x10];
8859 u8 reserved_at_10[0x10];
8860
8861 u8 reserved_at_20[0x10];
8862 u8 op_mod[0x10];
8863
8864 u8 reserved_at_40[0x40];
8865};
8866
d29b796a 8867#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)