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net/mlx5e: Use inline MTTs in UMR WQEs
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 146 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 147 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
148 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
149 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
150 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
37e92a9d 151 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 152 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 153 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
154 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
155 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
156 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
157 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
158 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 159 MLX5_CMD_OP_ALLOC_PD = 0x800,
160 MLX5_CMD_OP_DEALLOC_PD = 0x801,
161 MLX5_CMD_OP_ALLOC_UAR = 0x802,
162 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
163 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
164 MLX5_CMD_OP_ACCESS_REG = 0x805,
165 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 166 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 167 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
168 MLX5_CMD_OP_MAD_IFC = 0x50d,
169 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
170 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
171 MLX5_CMD_OP_NOP = 0x80d,
172 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
173 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 174 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
175 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
176 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
177 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
178 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
179 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
180 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
181 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
182 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
183 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
184 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
185 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 186 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
187 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 188 MLX5_CMD_OP_CREATE_LAG = 0x840,
189 MLX5_CMD_OP_MODIFY_LAG = 0x841,
190 MLX5_CMD_OP_QUERY_LAG = 0x842,
191 MLX5_CMD_OP_DESTROY_LAG = 0x843,
192 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
193 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 194 MLX5_CMD_OP_CREATE_TIR = 0x900,
195 MLX5_CMD_OP_MODIFY_TIR = 0x901,
196 MLX5_CMD_OP_DESTROY_TIR = 0x902,
197 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 198 MLX5_CMD_OP_CREATE_SQ = 0x904,
199 MLX5_CMD_OP_MODIFY_SQ = 0x905,
200 MLX5_CMD_OP_DESTROY_SQ = 0x906,
201 MLX5_CMD_OP_QUERY_SQ = 0x907,
202 MLX5_CMD_OP_CREATE_RQ = 0x908,
203 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 204 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 205 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
206 MLX5_CMD_OP_QUERY_RQ = 0x90b,
207 MLX5_CMD_OP_CREATE_RMP = 0x90c,
208 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
209 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
210 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 211 MLX5_CMD_OP_CREATE_TIS = 0x912,
212 MLX5_CMD_OP_MODIFY_TIS = 0x913,
213 MLX5_CMD_OP_DESTROY_TIS = 0x914,
214 MLX5_CMD_OP_QUERY_TIS = 0x915,
215 MLX5_CMD_OP_CREATE_RQT = 0x916,
216 MLX5_CMD_OP_MODIFY_RQT = 0x917,
217 MLX5_CMD_OP_DESTROY_RQT = 0x918,
218 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 219 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 220 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
221 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
223 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
224 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
225 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
226 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
227 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 228 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 229 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
230 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
231 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 232 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 233 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
234 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 235 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
236 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 237 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
238 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
239 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
240 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
241 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 242 MLX5_CMD_OP_MAX
e281682b
SM		 243};
244
245struct mlx5_ifc_flow_table_fields_supported_bits {
246 u8 outer_dmac[0x1];
247 u8 outer_smac[0x1];
248 u8 outer_ether_type[0x1];
19cc7524 249 u8 outer_ip_version[0x1];
e281682b
SM		 250 u8 outer_first_prio[0x1];
251 u8 outer_first_cfi[0x1];
252 u8 outer_first_vid[0x1];
a8ade55f 253 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 254 u8 outer_second_prio[0x1];
255 u8 outer_second_cfi[0x1];
256 u8 outer_second_vid[0x1];
b4ff3a36 257 u8 reserved_at_b[0x1];
e281682b
SM		 258 u8 outer_sip[0x1];
259 u8 outer_dip[0x1];
260 u8 outer_frag[0x1];
261 u8 outer_ip_protocol[0x1];
262 u8 outer_ip_ecn[0x1];
263 u8 outer_ip_dscp[0x1];
264 u8 outer_udp_sport[0x1];
265 u8 outer_udp_dport[0x1];
266 u8 outer_tcp_sport[0x1];
267 u8 outer_tcp_dport[0x1];
268 u8 outer_tcp_flags[0x1];
269 u8 outer_gre_protocol[0x1];
270 u8 outer_gre_key[0x1];
271 u8 outer_vxlan_vni[0x1];
b4ff3a36 272 u8 reserved_at_1a[0x5];
e281682b
SM		 273 u8 source_eswitch_port[0x1];
274
275 u8 inner_dmac[0x1];
276 u8 inner_smac[0x1];
277 u8 inner_ether_type[0x1];
19cc7524 278 u8 inner_ip_version[0x1];
e281682b
SM		 279 u8 inner_first_prio[0x1];
280 u8 inner_first_cfi[0x1];
281 u8 inner_first_vid[0x1];
b4ff3a36 282 u8 reserved_at_27[0x1];
e281682b
SM		 283 u8 inner_second_prio[0x1];
284 u8 inner_second_cfi[0x1];
285 u8 inner_second_vid[0x1];
b4ff3a36 286 u8 reserved_at_2b[0x1];
e281682b
SM		 287 u8 inner_sip[0x1];
288 u8 inner_dip[0x1];
289 u8 inner_frag[0x1];
290 u8 inner_ip_protocol[0x1];
291 u8 inner_ip_ecn[0x1];
292 u8 inner_ip_dscp[0x1];
293 u8 inner_udp_sport[0x1];
294 u8 inner_udp_dport[0x1];
295 u8 inner_tcp_sport[0x1];
296 u8 inner_tcp_dport[0x1];
297 u8 inner_tcp_flags[0x1];
b4ff3a36 298 u8 reserved_at_37[0x9];
3346c487
BP		 299 u8 reserved_at_40[0x17];
300 u8 outer_esp_spi[0x1];
301 u8 reserved_at_58[0x2];
a550ddfc 302 u8 bth_dst_qp[0x1];
e281682b 303
a550ddfc 304 u8 reserved_at_5b[0x25];
e281682b
SM		 305};
306
307struct mlx5_ifc_flow_table_prop_layout_bits {
308 u8 ft_support[0x1];
9dc0b289
AV		 309 u8 reserved_at_1[0x1];
310 u8 flow_counter[0x1];
26a81453 311 u8 flow_modify_en[0x1];
2cc43b49 312 u8 modify_root[0x1];
34a40e68
MG		 313 u8 identified_miss_table_mode[0x1];
314 u8 flow_table_modify[0x1];
7adbde20
HHZ		 315 u8 encap[0x1];
316 u8 decap[0x1];
0c06897a
OG		 317 u8 reserved_at_9[0x1];
318 u8 pop_vlan[0x1];
319 u8 push_vlan[0x1];
320 u8 reserved_at_c[0x14];
e281682b 321
b4ff3a36 322 u8 reserved_at_20[0x2];
e281682b 323 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 324 u8 log_max_modify_header_context[0x8];
325 u8 max_modify_header_actions[0x8];
e281682b
SM		 326 u8 max_ft_level[0x8];
327
b4ff3a36 328 u8 reserved_at_40[0x20];
e281682b 329
b4ff3a36 330 u8 reserved_at_60[0x18];
e281682b
SM		 331 u8 log_max_ft_num[0x8];
332
b4ff3a36 333 u8 reserved_at_80[0x18];
e281682b
SM		 334 u8 log_max_destination[0x8];
335
16f1c5bb
RS		 336 u8 log_max_flow_counter[0x8];
337 u8 reserved_at_a8[0x10];
e281682b
SM		 338 u8 log_max_flow[0x8];
339
b4ff3a36 340 u8 reserved_at_c0[0x40];
e281682b
SM		 341
342 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
343
344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
345};
346
347struct mlx5_ifc_odp_per_transport_service_cap_bits {
348 u8 send[0x1];
349 u8 receive[0x1];
350 u8 write[0x1];
351 u8 read[0x1];
17d2f88f 352 u8 atomic[0x1];
e281682b 353 u8 srq_receive[0x1];
b4ff3a36 354 u8 reserved_at_6[0x1a];
e281682b
SM		 355};
356
b4d1f032 357struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 358 u8 reserved_at_0[0x60];
b4d1f032
MG		 359
360 u8 ipv4[0x20];
361};
362
363struct mlx5_ifc_ipv6_layout_bits {
364 u8 ipv6[16][0x8];
365};
366
367union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
368 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
369 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 370 u8 reserved_at_0[0x80];
b4d1f032
MG		 371};
372
e281682b
SM		 373struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
374 u8 smac_47_16[0x20];
375
376 u8 smac_15_0[0x10];
377 u8 ethertype[0x10];
378
379 u8 dmac_47_16[0x20];
380
381 u8 dmac_15_0[0x10];
382 u8 first_prio[0x3];
383 u8 first_cfi[0x1];
384 u8 first_vid[0xc];
385
386 u8 ip_protocol[0x8];
387 u8 ip_dscp[0x6];
388 u8 ip_ecn[0x2];
10543365
MHY		 389 u8 cvlan_tag[0x1];
390 u8 svlan_tag[0x1];
e281682b 391 u8 frag[0x1];
19cc7524 392 u8 ip_version[0x4];
e281682b
SM		 393 u8 tcp_flags[0x9];
394
395 u8 tcp_sport[0x10];
396 u8 tcp_dport[0x10];
397
a8ade55f
OG		 398 u8 reserved_at_c0[0x18];
399 u8 ttl_hoplimit[0x8];
e281682b
SM		 400
401 u8 udp_sport[0x10];
402 u8 udp_dport[0x10];
403
b4d1f032 404 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 405
b4d1f032 406 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 407};
408
409struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 410 u8 reserved_at_0[0x8];
411 u8 source_sqn[0x18];
e281682b 412
b4ff3a36 413 u8 reserved_at_20[0x10];
e281682b
SM		 414 u8 source_port[0x10];
415
416 u8 outer_second_prio[0x3];
417 u8 outer_second_cfi[0x1];
418 u8 outer_second_vid[0xc];
419 u8 inner_second_prio[0x3];
420 u8 inner_second_cfi[0x1];
421 u8 inner_second_vid[0xc];
422
10543365
MHY		 423 u8 outer_second_cvlan_tag[0x1];
424 u8 inner_second_cvlan_tag[0x1];
425 u8 outer_second_svlan_tag[0x1];
426 u8 inner_second_svlan_tag[0x1];
427 u8 reserved_at_64[0xc];
e281682b
SM		 428 u8 gre_protocol[0x10];
429
430 u8 gre_key_h[0x18];
431 u8 gre_key_l[0x8];
432
433 u8 vxlan_vni[0x18];
b4ff3a36 434 u8 reserved_at_b8[0x8];
e281682b 435
b4ff3a36 436 u8 reserved_at_c0[0x20];
e281682b 437
b4ff3a36 438 u8 reserved_at_e0[0xc];
e281682b
SM		 439 u8 outer_ipv6_flow_label[0x14];
440
b4ff3a36 441 u8 reserved_at_100[0xc];
e281682b
SM		 442 u8 inner_ipv6_flow_label[0x14];
443
a550ddfc
YH		 444 u8 reserved_at_120[0x28];
445 u8 bth_dst_qp[0x18];
3346c487
BP		 446 u8 reserved_at_160[0x20];
447 u8 outer_esp_spi[0x20];
448 u8 reserved_at_1a0[0x60];
e281682b
SM		 449};
450
451struct mlx5_ifc_cmd_pas_bits {
452 u8 pa_h[0x20];
453
454 u8 pa_l[0x14];
b4ff3a36 455 u8 reserved_at_34[0xc];
e281682b
SM		 456};
457
458struct mlx5_ifc_uint64_bits {
459 u8 hi[0x20];
460
461 u8 lo[0x20];
462};
463
464enum {
465 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
466 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
467 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
468 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
469 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
470 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
471 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
472 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
473 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
474 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
475};
476
477struct mlx5_ifc_ads_bits {
478 u8 fl[0x1];
479 u8 free_ar[0x1];
b4ff3a36 480 u8 reserved_at_2[0xe];
e281682b
SM		 481 u8 pkey_index[0x10];
482
b4ff3a36 483 u8 reserved_at_20[0x8];
e281682b
SM		 484 u8 grh[0x1];
485 u8 mlid[0x7];
486 u8 rlid[0x10];
487
488 u8 ack_timeout[0x5];
b4ff3a36 489 u8 reserved_at_45[0x3];
e281682b 490 u8 src_addr_index[0x8];
b4ff3a36 491 u8 reserved_at_50[0x4];
e281682b
SM		 492 u8 stat_rate[0x4];
493 u8 hop_limit[0x8];
494
b4ff3a36 495 u8 reserved_at_60[0x4];
e281682b
SM		 496 u8 tclass[0x8];
497 u8 flow_label[0x14];
498
499 u8 rgid_rip[16][0x8];
500
b4ff3a36 501 u8 reserved_at_100[0x4];
e281682b
SM		 502 u8 f_dscp[0x1];
503 u8 f_ecn[0x1];
b4ff3a36 504 u8 reserved_at_106[0x1];
e281682b
SM		 505 u8 f_eth_prio[0x1];
506 u8 ecn[0x2];
507 u8 dscp[0x6];
508 u8 udp_sport[0x10];
509
510 u8 dei_cfi[0x1];
511 u8 eth_prio[0x3];
512 u8 sl[0x4];
32f69e4b 513 u8 vhca_port_num[0x8];
e281682b
SM		 514 u8 rmac_47_32[0x10];
515
516 u8 rmac_31_0[0x20];
517};
518
519struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 520 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 521 u8 nic_rx_multi_path_tirs_fts[0x1];
522 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
523 u8 reserved_at_3[0x1fd];
e281682b
SM		 524
525 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
526
b4ff3a36 527 u8 reserved_at_400[0x200];
e281682b
SM		 528
529 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
530
531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
532
b4ff3a36 533 u8 reserved_at_a00[0x200];
e281682b
SM		 534
535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
536
b4ff3a36 537 u8 reserved_at_e00[0x7200];
e281682b
SM		 538};
539
495716b1 540struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 541 u8 reserved_at_0[0x200];
495716b1
SM		 542
543 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
544
545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
546
547 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
548
b4ff3a36 549 u8 reserved_at_800[0x7800];
495716b1
SM		 550};
551
d6666753
SM		 552struct mlx5_ifc_e_switch_cap_bits {
553 u8 vport_svlan_strip[0x1];
554 u8 vport_cvlan_strip[0x1];
555 u8 vport_svlan_insert[0x1];
556 u8 vport_cvlan_insert_if_not_exist[0x1];
557 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 558 u8 reserved_at_5[0x19];
559 u8 nic_vport_node_guid_modify[0x1];
560 u8 nic_vport_port_guid_modify[0x1];
d6666753 561
7adbde20
HHZ		 562 u8 vxlan_encap_decap[0x1];
563 u8 nvgre_encap_decap[0x1];
564 u8 reserved_at_22[0x9];
565 u8 log_max_encap_headers[0x5];
566 u8 reserved_2b[0x6];
567 u8 max_encap_header_size[0xa];
568
569 u8 reserved_40[0x7c0];
570
d6666753
SM		 571};
572
7486216b
SM		 573struct mlx5_ifc_qos_cap_bits {
574 u8 packet_pacing[0x1];
813f8540 575 u8 esw_scheduling[0x1];
c9497c98
MHY		 576 u8 esw_bw_share[0x1];
577 u8 esw_rate_limit[0x1];
578 u8 reserved_at_4[0x1c];
813f8540
MHY		 579
580 u8 reserved_at_20[0x20];
581
7486216b 582 u8 packet_pacing_max_rate[0x20];
813f8540 583
7486216b 584 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 585
586 u8 reserved_at_80[0x10];
7486216b 587 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 588
589 u8 esw_element_type[0x10];
590 u8 esw_tsar_type[0x10];
591
592 u8 reserved_at_c0[0x10];
593 u8 max_qos_para_vport[0x10];
594
595 u8 max_tsar_bw_share[0x20];
596
597 u8 reserved_at_100[0x700];
7486216b
SM		 598};
599
2fcb12df
IK		 600struct mlx5_ifc_debug_cap_bits {
601 u8 reserved_at_0[0x20];
602
603 u8 reserved_at_20[0x2];
604 u8 stall_detect[0x1];
605 u8 reserved_at_23[0x1d];
606
607 u8 reserved_at_40[0x7c0];
608};
609
e281682b
SM		 610struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
611 u8 csum_cap[0x1];
612 u8 vlan_cap[0x1];
613 u8 lro_cap[0x1];
614 u8 lro_psh_flag[0x1];
615 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 616 u8 reserved_at_5[0x2];
617 u8 wqe_vlan_insert[0x1];
66189961 618 u8 self_lb_en_modifiable[0x1];
b4ff3a36 619 u8 reserved_at_9[0x2];
e281682b 620 u8 max_lso_cap[0x5];
c226dc22 621 u8 multi_pkt_send_wqe[0x2];
cff92d7c 622 u8 wqe_inline_mode[0x2];
e281682b 623 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 624 u8 reg_umr_sq[0x1];
625 u8 scatter_fcs[0x1];
050da902 626 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 627 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 628 u8 reserved_at_1c[0x2];
27299841 629 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 630 u8 tunnel_stateless_vxlan[0x1];
631
547eede0
IT		 632 u8 swp[0x1];
633 u8 swp_csum[0x1];
634 u8 swp_lso[0x1];
4d350f1f
MG		 635 u8 reserved_at_23[0x1b];
636 u8 max_geneve_opt_len[0x1];
637 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 638
b4ff3a36 639 u8 reserved_at_40[0x10];
e281682b
SM		 640 u8 lro_min_mss_size[0x10];
641
b4ff3a36 642 u8 reserved_at_60[0x120];
e281682b
SM		 643
644 u8 lro_timer_supported_periods[4][0x20];
645
b4ff3a36 646 u8 reserved_at_200[0x600];
e281682b
SM		 647};
648
649struct mlx5_ifc_roce_cap_bits {
650 u8 roce_apm[0x1];
b4ff3a36 651 u8 reserved_at_1[0x1f];
e281682b 652
b4ff3a36 653 u8 reserved_at_20[0x60];
e281682b 654
b4ff3a36 655 u8 reserved_at_80[0xc];
e281682b 656 u8 l3_type[0x4];
b4ff3a36 657 u8 reserved_at_90[0x8];
e281682b
SM		 658 u8 roce_version[0x8];
659
b4ff3a36 660 u8 reserved_at_a0[0x10];
e281682b
SM		 661 u8 r_roce_dest_udp_port[0x10];
662
663 u8 r_roce_max_src_udp_port[0x10];
664 u8 r_roce_min_src_udp_port[0x10];
665
b4ff3a36 666 u8 reserved_at_e0[0x10];
e281682b
SM		 667 u8 roce_address_table_size[0x10];
668
b4ff3a36 669 u8 reserved_at_100[0x700];
e281682b
SM		 670};
671
672enum {
673 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
674 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
675 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
676 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
677 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
678 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
679 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
680 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
681 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
682};
683
684enum {
685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
689 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
690 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
691 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
692 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
693 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
694};
695
696struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 697 u8 reserved_at_0[0x40];
e281682b 698
bd10838a 699 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 700 u8 reserved_at_42[0x4];
bd10838a 701 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 702
b4ff3a36 703 u8 reserved_at_47[0x19];
e281682b 704
b4ff3a36 705 u8 reserved_at_60[0x20];
e281682b 706
b4ff3a36 707 u8 reserved_at_80[0x10];
f91e6d89 708 u8 atomic_operations[0x10];
e281682b 709
b4ff3a36 710 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 711 u8 atomic_size_qp[0x10];
712
b4ff3a36 713 u8 reserved_at_c0[0x10];
e281682b
SM		 714 u8 atomic_size_dc[0x10];
715
b4ff3a36 716 u8 reserved_at_e0[0x720];
e281682b
SM		 717};
718
719struct mlx5_ifc_odp_cap_bits {
b4ff3a36 720 u8 reserved_at_0[0x40];
e281682b
SM		 721
722 u8 sig[0x1];
b4ff3a36 723 u8 reserved_at_41[0x1f];
e281682b 724
b4ff3a36 725 u8 reserved_at_60[0x20];
e281682b
SM		 726
727 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
728
729 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
730
731 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
732
b4ff3a36 733 u8 reserved_at_e0[0x720];
e281682b
SM		 734};
735
3f0393a5
SG		 736struct mlx5_ifc_calc_op {
737 u8 reserved_at_0[0x10];
738 u8 reserved_at_10[0x9];
739 u8 op_swap_endianness[0x1];
740 u8 op_min[0x1];
741 u8 op_xor[0x1];
742 u8 op_or[0x1];
743 u8 op_and[0x1];
744 u8 op_max[0x1];
745 u8 op_add[0x1];
746};
747
748struct mlx5_ifc_vector_calc_cap_bits {
749 u8 calc_matrix[0x1];
750 u8 reserved_at_1[0x1f];
751 u8 reserved_at_20[0x8];
752 u8 max_vec_count[0x8];
753 u8 reserved_at_30[0xd];
754 u8 max_chunk_size[0x3];
755 struct mlx5_ifc_calc_op calc0;
756 struct mlx5_ifc_calc_op calc1;
757 struct mlx5_ifc_calc_op calc2;
758 struct mlx5_ifc_calc_op calc3;
759
760 u8 reserved_at_e0[0x720];
761};
762
e281682b
SM		 763enum {
764 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
765 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 766 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 767 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 768};
769
770enum {
771 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
772 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
773};
774
775enum {
776 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
777 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
778 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
779 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
780 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
781};
782
783enum {
784 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
785 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
786 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
787 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
788 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
789 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
790};
791
792enum {
793 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
794 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
795};
796
797enum {
798 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
799 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
800 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
801};
802
803enum {
804 MLX5_CAP_PORT_TYPE_IB = 0x0,
805 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 806};
807
1410a90a
MG		 808enum {
809 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
810 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
811 MLX5_CAP_UMR_FENCE_NONE = 0x2,
812};
813
b775516b 814struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 815 u8 reserved_at_0[0x30];
816 u8 vhca_id[0x10];
817
818 u8 reserved_at_40[0x40];
b775516b
EC		 819
820 u8 log_max_srq_sz[0x8];
821 u8 log_max_qp_sz[0x8];
b4ff3a36 822 u8 reserved_at_90[0xb];
b775516b
EC		 823 u8 log_max_qp[0x5];
824
b4ff3a36 825 u8 reserved_at_a0[0xb];
e281682b 826 u8 log_max_srq[0x5];
b4ff3a36 827 u8 reserved_at_b0[0x10];
b775516b 828
b4ff3a36 829 u8 reserved_at_c0[0x8];
b775516b 830 u8 log_max_cq_sz[0x8];
b4ff3a36 831 u8 reserved_at_d0[0xb];
b775516b
EC		 832 u8 log_max_cq[0x5];
833
834 u8 log_max_eq_sz[0x8];
b4ff3a36 835 u8 reserved_at_e8[0x2];
b775516b 836 u8 log_max_mkey[0x6];
b4ff3a36 837 u8 reserved_at_f0[0xc];
b775516b
EC		 838 u8 log_max_eq[0x4];
839
840 u8 max_indirection[0x8];
bcda1aca 841 u8 fixed_buffer_size[0x1];
b775516b 842 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 843 u8 force_teardown[0x1];
844 u8 reserved_at_111[0x1];
b775516b 845 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 846 u8 umr_extended_translation_offset[0x1];
847 u8 null_mkey[0x1];
b775516b
EC		 848 u8 log_max_klm_list_size[0x6];
849
b4ff3a36 850 u8 reserved_at_120[0xa];
b775516b 851 u8 log_max_ra_req_dc[0x6];
b4ff3a36 852 u8 reserved_at_130[0xa];
b775516b
EC		 853 u8 log_max_ra_res_dc[0x6];
854
b4ff3a36 855 u8 reserved_at_140[0xa];
b775516b 856 u8 log_max_ra_req_qp[0x6];
b4ff3a36 857 u8 reserved_at_150[0xa];
b775516b
EC		 858 u8 log_max_ra_res_qp[0x6];
859
f32f5bd2 860 u8 end_pad[0x1];
b775516b
EC		 861 u8 cc_query_allowed[0x1];
862 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 863 u8 start_pad[0x1];
864 u8 cache_line_128byte[0x1];
c02762eb
HN		 865 u8 reserved_at_165[0xa];
866 u8 qcam_reg[0x1];
e281682b 867 u8 gid_table_size[0x10];
b775516b 868
e281682b
SM		 869 u8 out_of_seq_cnt[0x1];
870 u8 vport_counters[0x1];
7486216b 871 u8 retransmission_q_counters[0x1];
2fcb12df 872 u8 debug[0x1];
83b502a1 873 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 874 u8 rq_delay_drop[0x1];
b775516b
EC		 875 u8 max_qp_cnt[0xa];
876 u8 pkey_table_size[0x10];
877
e281682b
SM		 878 u8 vport_group_manager[0x1];
879 u8 vhca_group_manager[0x1];
880 u8 ib_virt[0x1];
881 u8 eth_virt[0x1];
61c5b5c9 882 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 883 u8 ets[0x1];
884 u8 nic_flow_table[0x1];
54f0a411 885 u8 eswitch_flow_table[0x1];
e1c9c62b 886 u8 early_vf_enable[0x1];
cfdcbcea
GP		 887 u8 mcam_reg[0x1];
888 u8 pcam_reg[0x1];
b775516b 889 u8 local_ca_ack_delay[0x5];
4ce3bf2f 890 u8 port_module_event[0x1];
58dcb60a 891 u8 enhanced_error_q_counters[0x1];
7d5e1423 892 u8 ports_check[0x1];
7b13558f 893 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 894 u8 disable_link_up[0x1];
895 u8 beacon_led[0x1];
e281682b 896 u8 port_type[0x2];
b775516b
EC		 897 u8 num_ports[0x8];
898
f9a1ef72
EE		 899 u8 reserved_at_1c0[0x1];
900 u8 pps[0x1];
901 u8 pps_modify[0x1];
b775516b 902 u8 log_max_msg[0x5];
e1c9c62b 903 u8 reserved_at_1c8[0x4];
4f3961ee 904 u8 max_tc[0x4];
7486216b
SM		 905 u8 reserved_at_1d0[0x1];
906 u8 dcbx[0x1];
246ac981
MG		 907 u8 general_notification_event[0x1];
908 u8 reserved_at_1d3[0x2];
e29341fb 909 u8 fpga[0x1];
928cfe87
TT		 910 u8 rol_s[0x1];
911 u8 rol_g[0x1];
e1c9c62b 912 u8 reserved_at_1d8[0x1];
928cfe87
TT		 913 u8 wol_s[0x1];
914 u8 wol_g[0x1];
915 u8 wol_a[0x1];
916 u8 wol_b[0x1];
917 u8 wol_m[0x1];
918 u8 wol_u[0x1];
919 u8 wol_p[0x1];
b775516b
EC		 920
921 u8 stat_rate_support[0x10];
e1c9c62b 922 u8 reserved_at_1f0[0xc];
e281682b 923 u8 cqe_version[0x4];
b775516b 924
e281682b 925 u8 compact_address_vector[0x1];
7d5e1423 926 u8 striding_rq[0x1];
500a3d0d
ES		 927 u8 reserved_at_202[0x1];
928 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 929 u8 ipoib_basic_offloads[0x1];
1410a90a
MG		 930 u8 reserved_at_205[0x5];
931 u8 umr_fence[0x2];
932 u8 reserved_at_20c[0x3];
e281682b 933 u8 drain_sigerr[0x1];
b775516b
EC		 934 u8 cmdif_checksum[0x2];
935 u8 sigerr_cqe[0x1];
e1c9c62b 936 u8 reserved_at_213[0x1];
b775516b
EC		 937 u8 wq_signature[0x1];
938 u8 sctr_data_cqe[0x1];
e1c9c62b 939 u8 reserved_at_216[0x1];
b775516b
EC		 940 u8 sho[0x1];
941 u8 tph[0x1];
942 u8 rf[0x1];
e281682b 943 u8 dct[0x1];
7486216b 944 u8 qos[0x1];
e281682b 945 u8 eth_net_offloads[0x1];
b775516b
EC		 946 u8 roce[0x1];
947 u8 atomic[0x1];
e1c9c62b 948 u8 reserved_at_21f[0x1];
b775516b
EC		 949
950 u8 cq_oi[0x1];
951 u8 cq_resize[0x1];
952 u8 cq_moderation[0x1];
e1c9c62b 953 u8 reserved_at_223[0x3];
e281682b 954 u8 cq_eq_remap[0x1];
b775516b
EC		 955 u8 pg[0x1];
956 u8 block_lb_mc[0x1];
e1c9c62b 957 u8 reserved_at_229[0x1];
e281682b 958 u8 scqe_break_moderation[0x1];
7d5e1423 959 u8 cq_period_start_from_cqe[0x1];
b775516b 960 u8 cd[0x1];
e1c9c62b 961 u8 reserved_at_22d[0x1];
b775516b 962 u8 apm[0x1];
3f0393a5 963 u8 vector_calc[0x1];
7d5e1423 964 u8 umr_ptr_rlky[0x1];
d2370e0a 965 u8 imaicl[0x1];
e1c9c62b 966 u8 reserved_at_232[0x4];
b775516b
EC		 967 u8 qkv[0x1];
968 u8 pkv[0x1];
b11a4f9c
HE		 969 u8 set_deth_sqpn[0x1];
970 u8 reserved_at_239[0x3];
b775516b
EC		 971 u8 xrc[0x1];
972 u8 ud[0x1];
973 u8 uc[0x1];
974 u8 rc[0x1];
975
a6d51b68
EC		 976 u8 uar_4k[0x1];
977 u8 reserved_at_241[0x9];
b775516b 978 u8 uar_sz[0x6];
e1c9c62b 979 u8 reserved_at_250[0x8];
b775516b
EC		 980 u8 log_pg_sz[0x8];
981
982 u8 bf[0x1];
0dbc6fe0 983 u8 driver_version[0x1];
e281682b 984 u8 pad_tx_eth_packet[0x1];
e1c9c62b 985 u8 reserved_at_263[0x8];
b775516b 986 u8 log_bf_reg_size[0x5];
84df61eb
AH		 987
988 u8 reserved_at_270[0xb];
989 u8 lag_master[0x1];
990 u8 num_lag_ports[0x4];
b775516b 991
e1c9c62b 992 u8 reserved_at_280[0x10];
b775516b
EC		 993 u8 max_wqe_sz_sq[0x10];
994
e1c9c62b 995 u8 reserved_at_2a0[0x10];
b775516b
EC		 996 u8 max_wqe_sz_rq[0x10];
997
a8ffcc74 998 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 999 u8 max_wqe_sz_sq_dc[0x10];
1000
e1c9c62b 1001 u8 reserved_at_2e0[0x7];
b775516b
EC		 1002 u8 max_qp_mcg[0x19];
1003
e1c9c62b 1004 u8 reserved_at_300[0x18];
b775516b
EC		 1005 u8 log_max_mcg[0x8];
1006
e1c9c62b 1007 u8 reserved_at_320[0x3];
e281682b 1008 u8 log_max_transport_domain[0x5];
e1c9c62b 1009 u8 reserved_at_328[0x3];
b775516b 1010 u8 log_max_pd[0x5];
e1c9c62b 1011 u8 reserved_at_330[0xb];
b775516b
EC		 1012 u8 log_max_xrcd[0x5];
1013
5c298143 1014 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1015 u8 receive_discard_vport_down[0x1];
1016 u8 transmit_discard_vport_down[0x1];
1017 u8 reserved_at_343[0x5];
a351a1b0 1018 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1019 u8 max_flow_counter_15_0[0x10];
a351a1b0 1020
b775516b 1021
e1c9c62b 1022 u8 reserved_at_360[0x3];
b775516b 1023 u8 log_max_rq[0x5];
e1c9c62b 1024 u8 reserved_at_368[0x3];
b775516b 1025 u8 log_max_sq[0x5];
e1c9c62b 1026 u8 reserved_at_370[0x3];
b775516b 1027 u8 log_max_tir[0x5];
e1c9c62b 1028 u8 reserved_at_378[0x3];
b775516b
EC		 1029 u8 log_max_tis[0x5];
1030
e281682b 1031 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1032 u8 reserved_at_381[0x2];
e281682b 1033 u8 log_max_rmp[0x5];
e1c9c62b 1034 u8 reserved_at_388[0x3];
e281682b 1035 u8 log_max_rqt[0x5];
e1c9c62b 1036 u8 reserved_at_390[0x3];
e281682b 1037 u8 log_max_rqt_size[0x5];
e1c9c62b 1038 u8 reserved_at_398[0x3];
b775516b
EC		 1039 u8 log_max_tis_per_sq[0x5];
1040
e1c9c62b 1041 u8 reserved_at_3a0[0x3];
e281682b 1042 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1043 u8 reserved_at_3a8[0x3];
e281682b 1044 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1045 u8 reserved_at_3b0[0x3];
e281682b 1046 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1047 u8 reserved_at_3b8[0x3];
e281682b
SM		 1048 u8 log_min_stride_sz_sq[0x5];
1049
40817cdb
OG		 1050 u8 hairpin[0x1];
1051 u8 reserved_at_3c1[0x2];
1052 u8 log_max_hairpin_queues[0x5];
1053 u8 reserved_at_3c8[0x3];
1054 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1055 u8 reserved_at_3d0[0x3];
1056 u8 log_max_hairpin_num_packets[0x5];
1057 u8 reserved_at_3d8[0x3];
e281682b
SM		 1058 u8 log_max_wq_sz[0x5];
1059
54f0a411 1060 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1061 u8 disable_local_lb_uc[0x1];
1062 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1063 u8 log_min_hairpin_wq_data_sz[0x5];
1064 u8 reserved_at_3e8[0x3];
54f0a411 1065 u8 log_max_vlan_list[0x5];
e1c9c62b 1066 u8 reserved_at_3f0[0x3];
54f0a411 1067 u8 log_max_current_mc_list[0x5];
e1c9c62b 1068 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1069 u8 log_max_current_uc_list[0x5];
1070
e1c9c62b 1071 u8 reserved_at_400[0x80];
54f0a411 1072
e1c9c62b 1073 u8 reserved_at_480[0x3];
e281682b 1074 u8 log_max_l2_table[0x5];
e1c9c62b 1075 u8 reserved_at_488[0x8];
b775516b
EC		 1076 u8 log_uar_page_sz[0x10];
1077
e1c9c62b 1078 u8 reserved_at_4a0[0x20];
048ccca8 1079 u8 device_frequency_mhz[0x20];
b0844444 1080 u8 device_frequency_khz[0x20];
e1c9c62b 1081
a6d51b68
EC		 1082 u8 reserved_at_500[0x20];
1083 u8 num_of_uars_per_page[0x20];
1084 u8 reserved_at_540[0x40];
e1c9c62b 1085
0ff8e79c
GL		 1086 u8 reserved_at_580[0x3d];
1087 u8 cqe_128_always[0x1];
1088 u8 cqe_compression_128[0x1];
7d5e1423 1089 u8 cqe_compression[0x1];
b775516b 1090
7d5e1423
SM		 1091 u8 cqe_compression_timeout[0x10];
1092 u8 cqe_compression_max_num[0x10];
b775516b 1093
7486216b
SM		 1094 u8 reserved_at_5e0[0x10];
1095 u8 tag_matching[0x1];
1096 u8 rndv_offload_rc[0x1];
1097 u8 rndv_offload_dc[0x1];
1098 u8 log_tag_matching_list_sz[0x5];
7b13558f 1099 u8 reserved_at_5f8[0x3];
7486216b
SM		 1100 u8 log_max_xrq[0x5];
1101
32f69e4b
DJ		 1102 u8 affiliate_nic_vport_criteria[0x8];
1103 u8 native_port_num[0x8];
1104 u8 num_vhca_ports[0x8];
1105 u8 reserved_at_618[0x6];
1106 u8 sw_owner_id[0x1];
8737f818 1107 u8 reserved_at_61f[0x1e1];
b775516b
EC		 1108};
1109
81848731
SM		 1110enum mlx5_flow_destination_type {
1111 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1112 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1113 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1114
5f418378 1115 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1116 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1117};
b775516b 1118
e281682b
SM		 1119struct mlx5_ifc_dest_format_struct_bits {
1120 u8 destination_type[0x8];
1121 u8 destination_id[0x18];
b775516b 1122
b4ff3a36 1123 u8 reserved_at_20[0x20];
e281682b
SM		 1124};
1125
9dc0b289 1126struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1127 u8 flow_counter_id[0x20];
9dc0b289
AV		 1128
1129 u8 reserved_at_20[0x20];
1130};
1131
1132union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1133 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1134 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1135 u8 reserved_at_0[0x40];
1136};
1137
e281682b
SM		 1138struct mlx5_ifc_fte_match_param_bits {
1139 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1140
1141 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1142
1143 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1144
b4ff3a36 1145 u8 reserved_at_600[0xa00];
b775516b
EC		 1146};
1147
e281682b
SM		 1148enum {
1149 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1150 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1151 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1152 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1153 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1154};
b775516b 1155
e281682b
SM		 1156struct mlx5_ifc_rx_hash_field_select_bits {
1157 u8 l3_prot_type[0x1];
1158 u8 l4_prot_type[0x1];
1159 u8 selected_fields[0x1e];
1160};
b775516b 1161
e281682b
SM		 1162enum {
1163 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1164 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1165};
1166
e281682b
SM		 1167enum {
1168 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1169 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1170};
1171
1172struct mlx5_ifc_wq_bits {
1173 u8 wq_type[0x4];
1174 u8 wq_signature[0x1];
1175 u8 end_padding_mode[0x2];
1176 u8 cd_slave[0x1];
b4ff3a36 1177 u8 reserved_at_8[0x18];
b775516b 1178
e281682b
SM		 1179 u8 hds_skip_first_sge[0x1];
1180 u8 log2_hds_buf_size[0x3];
b4ff3a36 1181 u8 reserved_at_24[0x7];
e281682b
SM		 1182 u8 page_offset[0x5];
1183 u8 lwm[0x10];
b775516b 1184
b4ff3a36 1185 u8 reserved_at_40[0x8];
e281682b
SM		 1186 u8 pd[0x18];
1187
b4ff3a36 1188 u8 reserved_at_60[0x8];
e281682b
SM		 1189 u8 uar_page[0x18];
1190
1191 u8 dbr_addr[0x40];
1192
1193 u8 hw_counter[0x20];
1194
1195 u8 sw_counter[0x20];
1196
b4ff3a36 1197 u8 reserved_at_100[0xc];
e281682b 1198 u8 log_wq_stride[0x4];
b4ff3a36 1199 u8 reserved_at_110[0x3];
e281682b 1200 u8 log_wq_pg_sz[0x5];
b4ff3a36 1201 u8 reserved_at_118[0x3];
e281682b
SM		 1202 u8 log_wq_sz[0x5];
1203
4d533e0f
OG		 1204 u8 reserved_at_120[0x3];
1205 u8 log_hairpin_num_packets[0x5];
1206 u8 reserved_at_128[0x3];
40817cdb
OG		 1207 u8 log_hairpin_data_sz[0x5];
1208 u8 reserved_at_130[0x5];
1209
7d5e1423
SM		 1210 u8 log_wqe_num_of_strides[0x3];
1211 u8 two_byte_shift_en[0x1];
1212 u8 reserved_at_139[0x4];
1213 u8 log_wqe_stride_size[0x3];
1214
1215 u8 reserved_at_140[0x4c0];
b775516b 1216
e281682b 1217 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1218};
1219
e281682b 1220struct mlx5_ifc_rq_num_bits {
b4ff3a36 1221 u8 reserved_at_0[0x8];
e281682b
SM		 1222 u8 rq_num[0x18];
1223};
b775516b 1224
e281682b 1225struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1226 u8 reserved_at_0[0x10];
e281682b 1227 u8 mac_addr_47_32[0x10];
b775516b 1228
e281682b
SM		 1229 u8 mac_addr_31_0[0x20];
1230};
1231
c0046cf7 1232struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1233 u8 reserved_at_0[0x14];
c0046cf7
SM		 1234 u8 vlan[0x0c];
1235
b4ff3a36 1236 u8 reserved_at_20[0x20];
c0046cf7
SM		 1237};
1238
e281682b 1239struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1240 u8 reserved_at_0[0xa0];
e281682b
SM		 1241
1242 u8 min_time_between_cnps[0x20];
1243
b4ff3a36 1244 u8 reserved_at_c0[0x12];
e281682b 1245 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1246 u8 reserved_at_d8[0x4];
1247 u8 cnp_prio_mode[0x1];
e281682b
SM		 1248 u8 cnp_802p_prio[0x3];
1249
b4ff3a36 1250 u8 reserved_at_e0[0x720];
e281682b
SM		 1251};
1252
1253struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1254 u8 reserved_at_0[0x60];
e281682b 1255
b4ff3a36 1256 u8 reserved_at_60[0x4];
e281682b 1257 u8 clamp_tgt_rate[0x1];
b4ff3a36 1258 u8 reserved_at_65[0x3];
e281682b 1259 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1260 u8 reserved_at_69[0x17];
e281682b 1261
b4ff3a36 1262 u8 reserved_at_80[0x20];
e281682b
SM		 1263
1264 u8 rpg_time_reset[0x20];
1265
1266 u8 rpg_byte_reset[0x20];
1267
1268 u8 rpg_threshold[0x20];
1269
1270 u8 rpg_max_rate[0x20];
1271
1272 u8 rpg_ai_rate[0x20];
1273
1274 u8 rpg_hai_rate[0x20];
1275
1276 u8 rpg_gd[0x20];
1277
1278 u8 rpg_min_dec_fac[0x20];
1279
1280 u8 rpg_min_rate[0x20];
1281
b4ff3a36 1282 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1283
1284 u8 rate_to_set_on_first_cnp[0x20];
1285
1286 u8 dce_tcp_g[0x20];
1287
1288 u8 dce_tcp_rtt[0x20];
1289
1290 u8 rate_reduce_monitor_period[0x20];
1291
b4ff3a36 1292 u8 reserved_at_320[0x20];
e281682b
SM		 1293
1294 u8 initial_alpha_value[0x20];
1295
b4ff3a36 1296 u8 reserved_at_360[0x4a0];
e281682b
SM		 1297};
1298
1299struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1300 u8 reserved_at_0[0x80];
e281682b
SM		 1301
1302 u8 rppp_max_rps[0x20];
1303
1304 u8 rpg_time_reset[0x20];
1305
1306 u8 rpg_byte_reset[0x20];
1307
1308 u8 rpg_threshold[0x20];
1309
1310 u8 rpg_max_rate[0x20];
1311
1312 u8 rpg_ai_rate[0x20];
1313
1314 u8 rpg_hai_rate[0x20];
1315
1316 u8 rpg_gd[0x20];
1317
1318 u8 rpg_min_dec_fac[0x20];
1319
1320 u8 rpg_min_rate[0x20];
1321
b4ff3a36 1322 u8 reserved_at_1c0[0x640];
e281682b
SM		 1323};
1324
1325enum {
1326 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1327 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1328 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1329};
1330
1331struct mlx5_ifc_resize_field_select_bits {
1332 u8 resize_field_select[0x20];
1333};
1334
1335enum {
1336 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1337 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1338 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1339 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1340};
1341
1342struct mlx5_ifc_modify_field_select_bits {
1343 u8 modify_field_select[0x20];
1344};
1345
1346struct mlx5_ifc_field_select_r_roce_np_bits {
1347 u8 field_select_r_roce_np[0x20];
1348};
1349
1350struct mlx5_ifc_field_select_r_roce_rp_bits {
1351 u8 field_select_r_roce_rp[0x20];
1352};
1353
1354enum {
1355 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1356 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1357 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1358 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1359 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1360 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1361 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1362 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1363 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1364 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1365};
1366
1367struct mlx5_ifc_field_select_802_1qau_rp_bits {
1368 u8 field_select_8021qaurp[0x20];
1369};
1370
1371struct mlx5_ifc_phys_layer_cntrs_bits {
1372 u8 time_since_last_clear_high[0x20];
1373
1374 u8 time_since_last_clear_low[0x20];
1375
1376 u8 symbol_errors_high[0x20];
1377
1378 u8 symbol_errors_low[0x20];
1379
1380 u8 sync_headers_errors_high[0x20];
1381
1382 u8 sync_headers_errors_low[0x20];
1383
1384 u8 edpl_bip_errors_lane0_high[0x20];
1385
1386 u8 edpl_bip_errors_lane0_low[0x20];
1387
1388 u8 edpl_bip_errors_lane1_high[0x20];
1389
1390 u8 edpl_bip_errors_lane1_low[0x20];
1391
1392 u8 edpl_bip_errors_lane2_high[0x20];
1393
1394 u8 edpl_bip_errors_lane2_low[0x20];
1395
1396 u8 edpl_bip_errors_lane3_high[0x20];
1397
1398 u8 edpl_bip_errors_lane3_low[0x20];
1399
1400 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1401
1402 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1403
1404 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1405
1406 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1407
1408 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1409
1410 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1411
1412 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1413
1414 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1415
1416 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1417
1418 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1419
1420 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1421
1422 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1423
1424 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1425
1426 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1427
1428 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1429
1430 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1431
1432 u8 rs_fec_corrected_blocks_high[0x20];
1433
1434 u8 rs_fec_corrected_blocks_low[0x20];
1435
1436 u8 rs_fec_uncorrectable_blocks_high[0x20];
1437
1438 u8 rs_fec_uncorrectable_blocks_low[0x20];
1439
1440 u8 rs_fec_no_errors_blocks_high[0x20];
1441
1442 u8 rs_fec_no_errors_blocks_low[0x20];
1443
1444 u8 rs_fec_single_error_blocks_high[0x20];
1445
1446 u8 rs_fec_single_error_blocks_low[0x20];
1447
1448 u8 rs_fec_corrected_symbols_total_high[0x20];
1449
1450 u8 rs_fec_corrected_symbols_total_low[0x20];
1451
1452 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1453
1454 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1455
1456 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1457
1458 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1459
1460 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1461
1462 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1463
1464 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1465
1466 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1467
1468 u8 link_down_events[0x20];
1469
1470 u8 successful_recovery_events[0x20];
1471
b4ff3a36 1472 u8 reserved_at_640[0x180];
e281682b
SM		 1473};
1474
d8dc0508
GP		 1475struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1476 u8 time_since_last_clear_high[0x20];
1477
1478 u8 time_since_last_clear_low[0x20];
1479
1480 u8 phy_received_bits_high[0x20];
1481
1482 u8 phy_received_bits_low[0x20];
1483
1484 u8 phy_symbol_errors_high[0x20];
1485
1486 u8 phy_symbol_errors_low[0x20];
1487
1488 u8 phy_corrected_bits_high[0x20];
1489
1490 u8 phy_corrected_bits_low[0x20];
1491
1492 u8 phy_corrected_bits_lane0_high[0x20];
1493
1494 u8 phy_corrected_bits_lane0_low[0x20];
1495
1496 u8 phy_corrected_bits_lane1_high[0x20];
1497
1498 u8 phy_corrected_bits_lane1_low[0x20];
1499
1500 u8 phy_corrected_bits_lane2_high[0x20];
1501
1502 u8 phy_corrected_bits_lane2_low[0x20];
1503
1504 u8 phy_corrected_bits_lane3_high[0x20];
1505
1506 u8 phy_corrected_bits_lane3_low[0x20];
1507
1508 u8 reserved_at_200[0x5c0];
1509};
1510
1c64bf6f
MY		 1511struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1512 u8 symbol_error_counter[0x10];
1513
1514 u8 link_error_recovery_counter[0x8];
1515
1516 u8 link_downed_counter[0x8];
1517
1518 u8 port_rcv_errors[0x10];
1519
1520 u8 port_rcv_remote_physical_errors[0x10];
1521
1522 u8 port_rcv_switch_relay_errors[0x10];
1523
1524 u8 port_xmit_discards[0x10];
1525
1526 u8 port_xmit_constraint_errors[0x8];
1527
1528 u8 port_rcv_constraint_errors[0x8];
1529
1530 u8 reserved_at_70[0x8];
1531
1532 u8 link_overrun_errors[0x8];
1533
1534 u8 reserved_at_80[0x10];
1535
1536 u8 vl_15_dropped[0x10];
1537
133bea04
TW		 1538 u8 reserved_at_a0[0x80];
1539
1540 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1541};
1542
e281682b
SM		 1543struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1544 u8 transmit_queue_high[0x20];
1545
1546 u8 transmit_queue_low[0x20];
1547
b4ff3a36 1548 u8 reserved_at_40[0x780];
e281682b
SM		 1549};
1550
1551struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1552 u8 rx_octets_high[0x20];
1553
1554 u8 rx_octets_low[0x20];
1555
b4ff3a36 1556 u8 reserved_at_40[0xc0];
e281682b
SM		 1557
1558 u8 rx_frames_high[0x20];
1559
1560 u8 rx_frames_low[0x20];
1561
1562 u8 tx_octets_high[0x20];
1563
1564 u8 tx_octets_low[0x20];
1565
b4ff3a36 1566 u8 reserved_at_180[0xc0];
e281682b
SM		 1567
1568 u8 tx_frames_high[0x20];
1569
1570 u8 tx_frames_low[0x20];
1571
1572 u8 rx_pause_high[0x20];
1573
1574 u8 rx_pause_low[0x20];
1575
1576 u8 rx_pause_duration_high[0x20];
1577
1578 u8 rx_pause_duration_low[0x20];
1579
1580 u8 tx_pause_high[0x20];
1581
1582 u8 tx_pause_low[0x20];
1583
1584 u8 tx_pause_duration_high[0x20];
1585
1586 u8 tx_pause_duration_low[0x20];
1587
1588 u8 rx_pause_transition_high[0x20];
1589
1590 u8 rx_pause_transition_low[0x20];
1591
2fcb12df
IK		 1592 u8 reserved_at_3c0[0x40];
1593
1594 u8 device_stall_minor_watermark_cnt_high[0x20];
1595
1596 u8 device_stall_minor_watermark_cnt_low[0x20];
1597
1598 u8 device_stall_critical_watermark_cnt_high[0x20];
1599
1600 u8 device_stall_critical_watermark_cnt_low[0x20];
1601
1602 u8 reserved_at_480[0x340];
e281682b
SM		 1603};
1604
1605struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1606 u8 port_transmit_wait_high[0x20];
1607
1608 u8 port_transmit_wait_low[0x20];
1609
2dba0797
GP		 1610 u8 reserved_at_40[0x100];
1611
1612 u8 rx_buffer_almost_full_high[0x20];
1613
1614 u8 rx_buffer_almost_full_low[0x20];
1615
1616 u8 rx_buffer_full_high[0x20];
1617
1618 u8 rx_buffer_full_low[0x20];
1619
1620 u8 reserved_at_1c0[0x600];
e281682b
SM		 1621};
1622
1623struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1624 u8 dot3stats_alignment_errors_high[0x20];
1625
1626 u8 dot3stats_alignment_errors_low[0x20];
1627
1628 u8 dot3stats_fcs_errors_high[0x20];
1629
1630 u8 dot3stats_fcs_errors_low[0x20];
1631
1632 u8 dot3stats_single_collision_frames_high[0x20];
1633
1634 u8 dot3stats_single_collision_frames_low[0x20];
1635
1636 u8 dot3stats_multiple_collision_frames_high[0x20];
1637
1638 u8 dot3stats_multiple_collision_frames_low[0x20];
1639
1640 u8 dot3stats_sqe_test_errors_high[0x20];
1641
1642 u8 dot3stats_sqe_test_errors_low[0x20];
1643
1644 u8 dot3stats_deferred_transmissions_high[0x20];
1645
1646 u8 dot3stats_deferred_transmissions_low[0x20];
1647
1648 u8 dot3stats_late_collisions_high[0x20];
1649
1650 u8 dot3stats_late_collisions_low[0x20];
1651
1652 u8 dot3stats_excessive_collisions_high[0x20];
1653
1654 u8 dot3stats_excessive_collisions_low[0x20];
1655
1656 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1657
1658 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1659
1660 u8 dot3stats_carrier_sense_errors_high[0x20];
1661
1662 u8 dot3stats_carrier_sense_errors_low[0x20];
1663
1664 u8 dot3stats_frame_too_longs_high[0x20];
1665
1666 u8 dot3stats_frame_too_longs_low[0x20];
1667
1668 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1669
1670 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1671
1672 u8 dot3stats_symbol_errors_high[0x20];
1673
1674 u8 dot3stats_symbol_errors_low[0x20];
1675
1676 u8 dot3control_in_unknown_opcodes_high[0x20];
1677
1678 u8 dot3control_in_unknown_opcodes_low[0x20];
1679
1680 u8 dot3in_pause_frames_high[0x20];
1681
1682 u8 dot3in_pause_frames_low[0x20];
1683
1684 u8 dot3out_pause_frames_high[0x20];
1685
1686 u8 dot3out_pause_frames_low[0x20];
1687
b4ff3a36 1688 u8 reserved_at_400[0x3c0];
e281682b
SM		 1689};
1690
1691struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1692 u8 ether_stats_drop_events_high[0x20];
1693
1694 u8 ether_stats_drop_events_low[0x20];
1695
1696 u8 ether_stats_octets_high[0x20];
1697
1698 u8 ether_stats_octets_low[0x20];
1699
1700 u8 ether_stats_pkts_high[0x20];
1701
1702 u8 ether_stats_pkts_low[0x20];
1703
1704 u8 ether_stats_broadcast_pkts_high[0x20];
1705
1706 u8 ether_stats_broadcast_pkts_low[0x20];
1707
1708 u8 ether_stats_multicast_pkts_high[0x20];
1709
1710 u8 ether_stats_multicast_pkts_low[0x20];
1711
1712 u8 ether_stats_crc_align_errors_high[0x20];
1713
1714 u8 ether_stats_crc_align_errors_low[0x20];
1715
1716 u8 ether_stats_undersize_pkts_high[0x20];
1717
1718 u8 ether_stats_undersize_pkts_low[0x20];
1719
1720 u8 ether_stats_oversize_pkts_high[0x20];
1721
1722 u8 ether_stats_oversize_pkts_low[0x20];
1723
1724 u8 ether_stats_fragments_high[0x20];
1725
1726 u8 ether_stats_fragments_low[0x20];
1727
1728 u8 ether_stats_jabbers_high[0x20];
1729
1730 u8 ether_stats_jabbers_low[0x20];
1731
1732 u8 ether_stats_collisions_high[0x20];
1733
1734 u8 ether_stats_collisions_low[0x20];
1735
1736 u8 ether_stats_pkts64octets_high[0x20];
1737
1738 u8 ether_stats_pkts64octets_low[0x20];
1739
1740 u8 ether_stats_pkts65to127octets_high[0x20];
1741
1742 u8 ether_stats_pkts65to127octets_low[0x20];
1743
1744 u8 ether_stats_pkts128to255octets_high[0x20];
1745
1746 u8 ether_stats_pkts128to255octets_low[0x20];
1747
1748 u8 ether_stats_pkts256to511octets_high[0x20];
1749
1750 u8 ether_stats_pkts256to511octets_low[0x20];
1751
1752 u8 ether_stats_pkts512to1023octets_high[0x20];
1753
1754 u8 ether_stats_pkts512to1023octets_low[0x20];
1755
1756 u8 ether_stats_pkts1024to1518octets_high[0x20];
1757
1758 u8 ether_stats_pkts1024to1518octets_low[0x20];
1759
1760 u8 ether_stats_pkts1519to2047octets_high[0x20];
1761
1762 u8 ether_stats_pkts1519to2047octets_low[0x20];
1763
1764 u8 ether_stats_pkts2048to4095octets_high[0x20];
1765
1766 u8 ether_stats_pkts2048to4095octets_low[0x20];
1767
1768 u8 ether_stats_pkts4096to8191octets_high[0x20];
1769
1770 u8 ether_stats_pkts4096to8191octets_low[0x20];
1771
1772 u8 ether_stats_pkts8192to10239octets_high[0x20];
1773
1774 u8 ether_stats_pkts8192to10239octets_low[0x20];
1775
b4ff3a36 1776 u8 reserved_at_540[0x280];
e281682b
SM		 1777};
1778
1779struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1780 u8 if_in_octets_high[0x20];
1781
1782 u8 if_in_octets_low[0x20];
1783
1784 u8 if_in_ucast_pkts_high[0x20];
1785
1786 u8 if_in_ucast_pkts_low[0x20];
1787
1788 u8 if_in_discards_high[0x20];
1789
1790 u8 if_in_discards_low[0x20];
1791
1792 u8 if_in_errors_high[0x20];
1793
1794 u8 if_in_errors_low[0x20];
1795
1796 u8 if_in_unknown_protos_high[0x20];
1797
1798 u8 if_in_unknown_protos_low[0x20];
1799
1800 u8 if_out_octets_high[0x20];
1801
1802 u8 if_out_octets_low[0x20];
1803
1804 u8 if_out_ucast_pkts_high[0x20];
1805
1806 u8 if_out_ucast_pkts_low[0x20];
1807
1808 u8 if_out_discards_high[0x20];
1809
1810 u8 if_out_discards_low[0x20];
1811
1812 u8 if_out_errors_high[0x20];
1813
1814 u8 if_out_errors_low[0x20];
1815
1816 u8 if_in_multicast_pkts_high[0x20];
1817
1818 u8 if_in_multicast_pkts_low[0x20];
1819
1820 u8 if_in_broadcast_pkts_high[0x20];
1821
1822 u8 if_in_broadcast_pkts_low[0x20];
1823
1824 u8 if_out_multicast_pkts_high[0x20];
1825
1826 u8 if_out_multicast_pkts_low[0x20];
1827
1828 u8 if_out_broadcast_pkts_high[0x20];
1829
1830 u8 if_out_broadcast_pkts_low[0x20];
1831
b4ff3a36 1832 u8 reserved_at_340[0x480];
e281682b
SM		 1833};
1834
1835struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1836 u8 a_frames_transmitted_ok_high[0x20];
1837
1838 u8 a_frames_transmitted_ok_low[0x20];
1839
1840 u8 a_frames_received_ok_high[0x20];
1841
1842 u8 a_frames_received_ok_low[0x20];
1843
1844 u8 a_frame_check_sequence_errors_high[0x20];
1845
1846 u8 a_frame_check_sequence_errors_low[0x20];
1847
1848 u8 a_alignment_errors_high[0x20];
1849
1850 u8 a_alignment_errors_low[0x20];
1851
1852 u8 a_octets_transmitted_ok_high[0x20];
1853
1854 u8 a_octets_transmitted_ok_low[0x20];
1855
1856 u8 a_octets_received_ok_high[0x20];
1857
1858 u8 a_octets_received_ok_low[0x20];
1859
1860 u8 a_multicast_frames_xmitted_ok_high[0x20];
1861
1862 u8 a_multicast_frames_xmitted_ok_low[0x20];
1863
1864 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1865
1866 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1867
1868 u8 a_multicast_frames_received_ok_high[0x20];
1869
1870 u8 a_multicast_frames_received_ok_low[0x20];
1871
1872 u8 a_broadcast_frames_received_ok_high[0x20];
1873
1874 u8 a_broadcast_frames_received_ok_low[0x20];
1875
1876 u8 a_in_range_length_errors_high[0x20];
1877
1878 u8 a_in_range_length_errors_low[0x20];
1879
1880 u8 a_out_of_range_length_field_high[0x20];
1881
1882 u8 a_out_of_range_length_field_low[0x20];
1883
1884 u8 a_frame_too_long_errors_high[0x20];
1885
1886 u8 a_frame_too_long_errors_low[0x20];
1887
1888 u8 a_symbol_error_during_carrier_high[0x20];
1889
1890 u8 a_symbol_error_during_carrier_low[0x20];
1891
1892 u8 a_mac_control_frames_transmitted_high[0x20];
1893
1894 u8 a_mac_control_frames_transmitted_low[0x20];
1895
1896 u8 a_mac_control_frames_received_high[0x20];
1897
1898 u8 a_mac_control_frames_received_low[0x20];
1899
1900 u8 a_unsupported_opcodes_received_high[0x20];
1901
1902 u8 a_unsupported_opcodes_received_low[0x20];
1903
1904 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1905
1906 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1907
1908 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1909
1910 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1911
b4ff3a36 1912 u8 reserved_at_4c0[0x300];
e281682b
SM		 1913};
1914
8ed1a630
GP		 1915struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1916 u8 life_time_counter_high[0x20];
1917
1918 u8 life_time_counter_low[0x20];
1919
1920 u8 rx_errors[0x20];
1921
1922 u8 tx_errors[0x20];
1923
1924 u8 l0_to_recovery_eieos[0x20];
1925
1926 u8 l0_to_recovery_ts[0x20];
1927
1928 u8 l0_to_recovery_framing[0x20];
1929
1930 u8 l0_to_recovery_retrain[0x20];
1931
1932 u8 crc_error_dllp[0x20];
1933
1934 u8 crc_error_tlp[0x20];
1935
efae7f78
EBE		 1936 u8 tx_overflow_buffer_pkt_high[0x20];
1937
1938 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 1939
1940 u8 outbound_stalled_reads[0x20];
1941
1942 u8 outbound_stalled_writes[0x20];
1943
1944 u8 outbound_stalled_reads_events[0x20];
1945
1946 u8 outbound_stalled_writes_events[0x20];
1947
1948 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 1949};
1950
e281682b
SM		 1951struct mlx5_ifc_cmd_inter_comp_event_bits {
1952 u8 command_completion_vector[0x20];
1953
b4ff3a36 1954 u8 reserved_at_20[0xc0];
e281682b
SM		 1955};
1956
1957struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1958 u8 reserved_at_0[0x18];
e281682b 1959 u8 port_num[0x1];
b4ff3a36 1960 u8 reserved_at_19[0x3];
e281682b
SM		 1961 u8 vl[0x4];
1962
b4ff3a36 1963 u8 reserved_at_20[0xa0];
e281682b
SM		 1964};
1965
1966struct mlx5_ifc_db_bf_congestion_event_bits {
1967 u8 event_subtype[0x8];
b4ff3a36 1968 u8 reserved_at_8[0x8];
e281682b 1969 u8 congestion_level[0x8];
b4ff3a36 1970 u8 reserved_at_18[0x8];
e281682b 1971
b4ff3a36 1972 u8 reserved_at_20[0xa0];
e281682b
SM		 1973};
1974
1975struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1976 u8 reserved_at_0[0x60];
e281682b
SM		 1977
1978 u8 gpio_event_hi[0x20];
1979
1980 u8 gpio_event_lo[0x20];
1981
b4ff3a36 1982 u8 reserved_at_a0[0x40];
e281682b
SM		 1983};
1984
1985struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1986 u8 reserved_at_0[0x40];
e281682b
SM		 1987
1988 u8 port_num[0x4];
b4ff3a36 1989 u8 reserved_at_44[0x1c];
e281682b 1990
b4ff3a36 1991 u8 reserved_at_60[0x80];
e281682b
SM		 1992};
1993
1994struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1995 u8 reserved_at_0[0xe0];
e281682b
SM		 1996};
1997
1998enum {
1999 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2000 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2001};
2002
2003struct mlx5_ifc_cq_error_bits {
b4ff3a36 2004 u8 reserved_at_0[0x8];
e281682b
SM		 2005 u8 cqn[0x18];
2006
b4ff3a36 2007 u8 reserved_at_20[0x20];
e281682b 2008
b4ff3a36 2009 u8 reserved_at_40[0x18];
e281682b
SM		 2010 u8 syndrome[0x8];
2011
b4ff3a36 2012 u8 reserved_at_60[0x80];
e281682b
SM		 2013};
2014
2015struct mlx5_ifc_rdma_page_fault_event_bits {
2016 u8 bytes_committed[0x20];
2017
2018 u8 r_key[0x20];
2019
b4ff3a36 2020 u8 reserved_at_40[0x10];
e281682b
SM		 2021 u8 packet_len[0x10];
2022
2023 u8 rdma_op_len[0x20];
2024
2025 u8 rdma_va[0x40];
2026
b4ff3a36 2027 u8 reserved_at_c0[0x5];
e281682b
SM		 2028 u8 rdma[0x1];
2029 u8 write[0x1];
2030 u8 requestor[0x1];
2031 u8 qp_number[0x18];
2032};
2033
2034struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2035 u8 bytes_committed[0x20];
2036
b4ff3a36 2037 u8 reserved_at_20[0x10];
e281682b
SM		 2038 u8 wqe_index[0x10];
2039
b4ff3a36 2040 u8 reserved_at_40[0x10];
e281682b
SM		 2041 u8 len[0x10];
2042
b4ff3a36 2043 u8 reserved_at_60[0x60];
e281682b 2044
b4ff3a36 2045 u8 reserved_at_c0[0x5];
e281682b
SM		 2046 u8 rdma[0x1];
2047 u8 write_read[0x1];
2048 u8 requestor[0x1];
2049 u8 qpn[0x18];
2050};
2051
2052struct mlx5_ifc_qp_events_bits {
b4ff3a36 2053 u8 reserved_at_0[0xa0];
e281682b
SM		 2054
2055 u8 type[0x8];
b4ff3a36 2056 u8 reserved_at_a8[0x18];
e281682b 2057
b4ff3a36 2058 u8 reserved_at_c0[0x8];
e281682b
SM		 2059 u8 qpn_rqn_sqn[0x18];
2060};
2061
2062struct mlx5_ifc_dct_events_bits {
b4ff3a36 2063 u8 reserved_at_0[0xc0];
e281682b 2064
b4ff3a36 2065 u8 reserved_at_c0[0x8];
e281682b
SM		 2066 u8 dct_number[0x18];
2067};
2068
2069struct mlx5_ifc_comp_event_bits {
b4ff3a36 2070 u8 reserved_at_0[0xc0];
e281682b 2071
b4ff3a36 2072 u8 reserved_at_c0[0x8];
e281682b
SM		 2073 u8 cq_number[0x18];
2074};
2075
2076enum {
2077 MLX5_QPC_STATE_RST = 0x0,
2078 MLX5_QPC_STATE_INIT = 0x1,
2079 MLX5_QPC_STATE_RTR = 0x2,
2080 MLX5_QPC_STATE_RTS = 0x3,
2081 MLX5_QPC_STATE_SQER = 0x4,
2082 MLX5_QPC_STATE_ERR = 0x6,
2083 MLX5_QPC_STATE_SQD = 0x7,
2084 MLX5_QPC_STATE_SUSPENDED = 0x9,
2085};
2086
2087enum {
2088 MLX5_QPC_ST_RC = 0x0,
2089 MLX5_QPC_ST_UC = 0x1,
2090 MLX5_QPC_ST_UD = 0x2,
2091 MLX5_QPC_ST_XRC = 0x3,
2092 MLX5_QPC_ST_DCI = 0x5,
2093 MLX5_QPC_ST_QP0 = 0x7,
2094 MLX5_QPC_ST_QP1 = 0x8,
2095 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2096 MLX5_QPC_ST_REG_UMR = 0xc,
2097};
2098
2099enum {
2100 MLX5_QPC_PM_STATE_ARMED = 0x0,
2101 MLX5_QPC_PM_STATE_REARM = 0x1,
2102 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2103 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2104};
2105
6e44636a
AK		 2106enum {
2107 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2108};
2109
e281682b
SM		 2110enum {
2111 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2112 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2113};
2114
2115enum {
2116 MLX5_QPC_MTU_256_BYTES = 0x1,
2117 MLX5_QPC_MTU_512_BYTES = 0x2,
2118 MLX5_QPC_MTU_1K_BYTES = 0x3,
2119 MLX5_QPC_MTU_2K_BYTES = 0x4,
2120 MLX5_QPC_MTU_4K_BYTES = 0x5,
2121 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2122};
2123
2124enum {
2125 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2126 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2127 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2128 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2129 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2130 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2131 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2132 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2133};
2134
2135enum {
2136 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2137 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2138 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2139};
2140
2141enum {
2142 MLX5_QPC_CS_RES_DISABLE = 0x0,
2143 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2144 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2145};
2146
2147struct mlx5_ifc_qpc_bits {
2148 u8 state[0x4];
84df61eb 2149 u8 lag_tx_port_affinity[0x4];
e281682b 2150 u8 st[0x8];
b4ff3a36 2151 u8 reserved_at_10[0x3];
e281682b 2152 u8 pm_state[0x2];
6e44636a
AK		 2153 u8 reserved_at_15[0x3];
2154 u8 offload_type[0x4];
e281682b 2155 u8 end_padding_mode[0x2];
b4ff3a36 2156 u8 reserved_at_1e[0x2];
e281682b
SM		 2157
2158 u8 wq_signature[0x1];
2159 u8 block_lb_mc[0x1];
2160 u8 atomic_like_write_en[0x1];
2161 u8 latency_sensitive[0x1];
b4ff3a36 2162 u8 reserved_at_24[0x1];
e281682b 2163 u8 drain_sigerr[0x1];
b4ff3a36 2164 u8 reserved_at_26[0x2];
e281682b
SM		 2165 u8 pd[0x18];
2166
2167 u8 mtu[0x3];
2168 u8 log_msg_max[0x5];
b4ff3a36 2169 u8 reserved_at_48[0x1];
e281682b
SM		 2170 u8 log_rq_size[0x4];
2171 u8 log_rq_stride[0x3];
2172 u8 no_sq[0x1];
2173 u8 log_sq_size[0x4];
b4ff3a36 2174 u8 reserved_at_55[0x6];
e281682b 2175 u8 rlky[0x1];
1015c2e8 2176 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2177
2178 u8 counter_set_id[0x8];
2179 u8 uar_page[0x18];
2180
b4ff3a36 2181 u8 reserved_at_80[0x8];
e281682b
SM		 2182 u8 user_index[0x18];
2183
b4ff3a36 2184 u8 reserved_at_a0[0x3];
e281682b
SM		 2185 u8 log_page_size[0x5];
2186 u8 remote_qpn[0x18];
2187
2188 struct mlx5_ifc_ads_bits primary_address_path;
2189
2190 struct mlx5_ifc_ads_bits secondary_address_path;
2191
2192 u8 log_ack_req_freq[0x4];
b4ff3a36 2193 u8 reserved_at_384[0x4];
e281682b 2194 u8 log_sra_max[0x3];
b4ff3a36 2195 u8 reserved_at_38b[0x2];
e281682b
SM		 2196 u8 retry_count[0x3];
2197 u8 rnr_retry[0x3];
b4ff3a36 2198 u8 reserved_at_393[0x1];
e281682b
SM		 2199 u8 fre[0x1];
2200 u8 cur_rnr_retry[0x3];
2201 u8 cur_retry_count[0x3];
b4ff3a36 2202 u8 reserved_at_39b[0x5];
e281682b 2203
b4ff3a36 2204 u8 reserved_at_3a0[0x20];
e281682b 2205
b4ff3a36 2206 u8 reserved_at_3c0[0x8];
e281682b
SM		 2207 u8 next_send_psn[0x18];
2208
b4ff3a36 2209 u8 reserved_at_3e0[0x8];
e281682b
SM		 2210 u8 cqn_snd[0x18];
2211
09a7d9ec
SM		 2212 u8 reserved_at_400[0x8];
2213 u8 deth_sqpn[0x18];
2214
2215 u8 reserved_at_420[0x20];
e281682b 2216
b4ff3a36 2217 u8 reserved_at_440[0x8];
e281682b
SM		 2218 u8 last_acked_psn[0x18];
2219
b4ff3a36 2220 u8 reserved_at_460[0x8];
e281682b
SM		 2221 u8 ssn[0x18];
2222
b4ff3a36 2223 u8 reserved_at_480[0x8];
e281682b 2224 u8 log_rra_max[0x3];
b4ff3a36 2225 u8 reserved_at_48b[0x1];
e281682b
SM		 2226 u8 atomic_mode[0x4];
2227 u8 rre[0x1];
2228 u8 rwe[0x1];
2229 u8 rae[0x1];
b4ff3a36 2230 u8 reserved_at_493[0x1];
e281682b 2231 u8 page_offset[0x6];
b4ff3a36 2232 u8 reserved_at_49a[0x3];
e281682b
SM		 2233 u8 cd_slave_receive[0x1];
2234 u8 cd_slave_send[0x1];
2235 u8 cd_master[0x1];
2236
b4ff3a36 2237 u8 reserved_at_4a0[0x3];
e281682b
SM		 2238 u8 min_rnr_nak[0x5];
2239 u8 next_rcv_psn[0x18];
2240
b4ff3a36 2241 u8 reserved_at_4c0[0x8];
e281682b
SM		 2242 u8 xrcd[0x18];
2243
b4ff3a36 2244 u8 reserved_at_4e0[0x8];
e281682b
SM		 2245 u8 cqn_rcv[0x18];
2246
2247 u8 dbr_addr[0x40];
2248
2249 u8 q_key[0x20];
2250
b4ff3a36 2251 u8 reserved_at_560[0x5];
e281682b 2252 u8 rq_type[0x3];
7486216b 2253 u8 srqn_rmpn_xrqn[0x18];
e281682b 2254
b4ff3a36 2255 u8 reserved_at_580[0x8];
e281682b
SM		 2256 u8 rmsn[0x18];
2257
2258 u8 hw_sq_wqebb_counter[0x10];
2259 u8 sw_sq_wqebb_counter[0x10];
2260
2261 u8 hw_rq_counter[0x20];
2262
2263 u8 sw_rq_counter[0x20];
2264
b4ff3a36 2265 u8 reserved_at_600[0x20];
e281682b 2266
b4ff3a36 2267 u8 reserved_at_620[0xf];
e281682b
SM		 2268 u8 cgs[0x1];
2269 u8 cs_req[0x8];
2270 u8 cs_res[0x8];
2271
2272 u8 dc_access_key[0x40];
2273
b4ff3a36 2274 u8 reserved_at_680[0xc0];
e281682b
SM		 2275};
2276
2277struct mlx5_ifc_roce_addr_layout_bits {
2278 u8 source_l3_address[16][0x8];
2279
b4ff3a36 2280 u8 reserved_at_80[0x3];
e281682b
SM		 2281 u8 vlan_valid[0x1];
2282 u8 vlan_id[0xc];
2283 u8 source_mac_47_32[0x10];
2284
2285 u8 source_mac_31_0[0x20];
2286
b4ff3a36 2287 u8 reserved_at_c0[0x14];
e281682b
SM		 2288 u8 roce_l3_type[0x4];
2289 u8 roce_version[0x8];
2290
b4ff3a36 2291 u8 reserved_at_e0[0x20];
e281682b
SM		 2292};
2293
2294union mlx5_ifc_hca_cap_union_bits {
2295 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2296 struct mlx5_ifc_odp_cap_bits odp_cap;
2297 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2298 struct mlx5_ifc_roce_cap_bits roce_cap;
2299 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2300 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2301 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2302 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2303 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2304 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2305 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2306 u8 reserved_at_0[0x8000];
e281682b
SM		 2307};
2308
2309enum {
2310 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2311 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2312 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2313 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2314 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2315 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2316 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2317 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2318 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2319};
2320
2321struct mlx5_ifc_vlan_bits {
2322 u8 ethtype[0x10];
2323 u8 prio[0x3];
2324 u8 cfi[0x1];
2325 u8 vid[0xc];
e281682b
SM		 2326};
2327
2328struct mlx5_ifc_flow_context_bits {
0c06897a 2329 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2330
2331 u8 group_id[0x20];
2332
b4ff3a36 2333 u8 reserved_at_40[0x8];
e281682b
SM		 2334 u8 flow_tag[0x18];
2335
b4ff3a36 2336 u8 reserved_at_60[0x10];
e281682b
SM		 2337 u8 action[0x10];
2338
b4ff3a36 2339 u8 reserved_at_80[0x8];
e281682b
SM		 2340 u8 destination_list_size[0x18];
2341
9dc0b289
AV		 2342 u8 reserved_at_a0[0x8];
2343 u8 flow_counter_list_size[0x18];
2344
7adbde20
HHZ		 2345 u8 encap_id[0x20];
2346
2a69cb9f
OG		 2347 u8 modify_header_id[0x20];
2348
2349 u8 reserved_at_100[0x100];
e281682b
SM		 2350
2351 struct mlx5_ifc_fte_match_param_bits match_value;
2352
b4ff3a36 2353 u8 reserved_at_1200[0x600];
e281682b 2354
9dc0b289 2355 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2356};
2357
2358enum {
2359 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2360 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2361};
2362
2363struct mlx5_ifc_xrc_srqc_bits {
2364 u8 state[0x4];
2365 u8 log_xrc_srq_size[0x4];
b4ff3a36 2366 u8 reserved_at_8[0x18];
e281682b
SM		 2367
2368 u8 wq_signature[0x1];
2369 u8 cont_srq[0x1];
b4ff3a36 2370 u8 reserved_at_22[0x1];
e281682b
SM		 2371 u8 rlky[0x1];
2372 u8 basic_cyclic_rcv_wqe[0x1];
2373 u8 log_rq_stride[0x3];
2374 u8 xrcd[0x18];
2375
2376 u8 page_offset[0x6];
b4ff3a36 2377 u8 reserved_at_46[0x2];
e281682b
SM		 2378 u8 cqn[0x18];
2379
b4ff3a36 2380 u8 reserved_at_60[0x20];
e281682b
SM		 2381
2382 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2383 u8 reserved_at_81[0x1];
e281682b
SM		 2384 u8 log_page_size[0x6];
2385 u8 user_index[0x18];
2386
b4ff3a36 2387 u8 reserved_at_a0[0x20];
e281682b 2388
b4ff3a36 2389 u8 reserved_at_c0[0x8];
e281682b
SM		 2390 u8 pd[0x18];
2391
2392 u8 lwm[0x10];
2393 u8 wqe_cnt[0x10];
2394
b4ff3a36 2395 u8 reserved_at_100[0x40];
e281682b
SM		 2396
2397 u8 db_record_addr_h[0x20];
2398
2399 u8 db_record_addr_l[0x1e];
b4ff3a36 2400 u8 reserved_at_17e[0x2];
e281682b 2401
b4ff3a36 2402 u8 reserved_at_180[0x80];
e281682b
SM		 2403};
2404
61c5b5c9
MS		 2405struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2406 u8 counter_error_queues[0x20];
2407
2408 u8 total_error_queues[0x20];
2409
2410 u8 send_queue_priority_update_flow[0x20];
2411
2412 u8 reserved_at_60[0x20];
2413
2414 u8 nic_receive_steering_discard[0x40];
2415
2416 u8 receive_discard_vport_down[0x40];
2417
2418 u8 transmit_discard_vport_down[0x40];
2419
2420 u8 reserved_at_140[0xec0];
2421};
2422
e281682b
SM		 2423struct mlx5_ifc_traffic_counter_bits {
2424 u8 packets[0x40];
2425
2426 u8 octets[0x40];
2427};
2428
2429struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2430 u8 strict_lag_tx_port_affinity[0x1];
2431 u8 reserved_at_1[0x3];
2432 u8 lag_tx_port_affinity[0x04];
2433
2434 u8 reserved_at_8[0x4];
e281682b 2435 u8 prio[0x4];
b4ff3a36 2436 u8 reserved_at_10[0x10];
e281682b 2437
b4ff3a36 2438 u8 reserved_at_20[0x100];
e281682b 2439
b4ff3a36 2440 u8 reserved_at_120[0x8];
e281682b
SM		 2441 u8 transport_domain[0x18];
2442
500a3d0d
ES		 2443 u8 reserved_at_140[0x8];
2444 u8 underlay_qpn[0x18];
2445 u8 reserved_at_160[0x3a0];
e281682b
SM		 2446};
2447
2448enum {
2449 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2450 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2451};
2452
2453enum {
2454 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2455 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2456};
2457
2458enum {
2be6967c
SM		 2459 MLX5_RX_HASH_FN_NONE = 0x0,
2460 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2461 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2462};
2463
2464enum {
2465 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2466 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2467};
2468
2469struct mlx5_ifc_tirc_bits {
b4ff3a36 2470 u8 reserved_at_0[0x20];
e281682b
SM		 2471
2472 u8 disp_type[0x4];
b4ff3a36 2473 u8 reserved_at_24[0x1c];
e281682b 2474
b4ff3a36 2475 u8 reserved_at_40[0x40];
e281682b 2476
b4ff3a36 2477 u8 reserved_at_80[0x4];
e281682b
SM		 2478 u8 lro_timeout_period_usecs[0x10];
2479 u8 lro_enable_mask[0x4];
2480 u8 lro_max_ip_payload_size[0x8];
2481
b4ff3a36 2482 u8 reserved_at_a0[0x40];
e281682b 2483
b4ff3a36 2484 u8 reserved_at_e0[0x8];
e281682b
SM		 2485 u8 inline_rqn[0x18];
2486
2487 u8 rx_hash_symmetric[0x1];
b4ff3a36 2488 u8 reserved_at_101[0x1];
e281682b 2489 u8 tunneled_offload_en[0x1];
b4ff3a36 2490 u8 reserved_at_103[0x5];
e281682b
SM		 2491 u8 indirect_table[0x18];
2492
2493 u8 rx_hash_fn[0x4];
b4ff3a36 2494 u8 reserved_at_124[0x2];
e281682b
SM		 2495 u8 self_lb_block[0x2];
2496 u8 transport_domain[0x18];
2497
2498 u8 rx_hash_toeplitz_key[10][0x20];
2499
2500 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2501
2502 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2503
b4ff3a36 2504 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2505};
2506
2507enum {
2508 MLX5_SRQC_STATE_GOOD = 0x0,
2509 MLX5_SRQC_STATE_ERROR = 0x1,
2510};
2511
2512struct mlx5_ifc_srqc_bits {
2513 u8 state[0x4];
2514 u8 log_srq_size[0x4];
b4ff3a36 2515 u8 reserved_at_8[0x18];
e281682b
SM		 2516
2517 u8 wq_signature[0x1];
2518 u8 cont_srq[0x1];
b4ff3a36 2519 u8 reserved_at_22[0x1];
e281682b 2520 u8 rlky[0x1];
b4ff3a36 2521 u8 reserved_at_24[0x1];
e281682b
SM		 2522 u8 log_rq_stride[0x3];
2523 u8 xrcd[0x18];
2524
2525 u8 page_offset[0x6];
b4ff3a36 2526 u8 reserved_at_46[0x2];
e281682b
SM		 2527 u8 cqn[0x18];
2528
b4ff3a36 2529 u8 reserved_at_60[0x20];
e281682b 2530
b4ff3a36 2531 u8 reserved_at_80[0x2];
e281682b 2532 u8 log_page_size[0x6];
b4ff3a36 2533 u8 reserved_at_88[0x18];
e281682b 2534
b4ff3a36 2535 u8 reserved_at_a0[0x20];
e281682b 2536
b4ff3a36 2537 u8 reserved_at_c0[0x8];
e281682b
SM		 2538 u8 pd[0x18];
2539
2540 u8 lwm[0x10];
2541 u8 wqe_cnt[0x10];
2542
b4ff3a36 2543 u8 reserved_at_100[0x40];
e281682b 2544
01949d01 2545 u8 dbr_addr[0x40];
e281682b 2546
b4ff3a36 2547 u8 reserved_at_180[0x80];
e281682b
SM		 2548};
2549
2550enum {
2551 MLX5_SQC_STATE_RST = 0x0,
2552 MLX5_SQC_STATE_RDY = 0x1,
2553 MLX5_SQC_STATE_ERR = 0x3,
2554};
2555
2556struct mlx5_ifc_sqc_bits {
2557 u8 rlky[0x1];
2558 u8 cd_master[0x1];
2559 u8 fre[0x1];
2560 u8 flush_in_error_en[0x1];
795b609c 2561 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2562 u8 min_wqe_inline_mode[0x3];
e281682b 2563 u8 state[0x4];
7d5e1423 2564 u8 reg_umr[0x1];
547eede0 2565 u8 allow_swp[0x1];
40817cdb
OG		 2566 u8 hairpin[0x1];
2567 u8 reserved_at_f[0x11];
e281682b 2568
b4ff3a36 2569 u8 reserved_at_20[0x8];
e281682b
SM		 2570 u8 user_index[0x18];
2571
b4ff3a36 2572 u8 reserved_at_40[0x8];
e281682b
SM		 2573 u8 cqn[0x18];
2574
40817cdb
OG		 2575 u8 reserved_at_60[0x8];
2576 u8 hairpin_peer_rq[0x18];
2577
2578 u8 reserved_at_80[0x10];
2579 u8 hairpin_peer_vhca[0x10];
2580
2581 u8 reserved_at_a0[0x50];
e281682b 2582
7486216b 2583 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2584 u8 tis_lst_sz[0x10];
b4ff3a36 2585 u8 reserved_at_110[0x10];
e281682b 2586
b4ff3a36 2587 u8 reserved_at_120[0x40];
e281682b 2588
b4ff3a36 2589 u8 reserved_at_160[0x8];
e281682b
SM		 2590 u8 tis_num_0[0x18];
2591
2592 struct mlx5_ifc_wq_bits wq;
2593};
2594
813f8540
MHY		 2595enum {
2596 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2597 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2598 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2599 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2600};
2601
2602struct mlx5_ifc_scheduling_context_bits {
2603 u8 element_type[0x8];
2604 u8 reserved_at_8[0x18];
2605
2606 u8 element_attributes[0x20];
2607
2608 u8 parent_element_id[0x20];
2609
2610 u8 reserved_at_60[0x40];
2611
2612 u8 bw_share[0x20];
2613
2614 u8 max_average_bw[0x20];
2615
2616 u8 reserved_at_e0[0x120];
2617};
2618
e281682b 2619struct mlx5_ifc_rqtc_bits {
b4ff3a36 2620 u8 reserved_at_0[0xa0];
e281682b 2621
b4ff3a36 2622 u8 reserved_at_a0[0x10];
e281682b
SM		 2623 u8 rqt_max_size[0x10];
2624
b4ff3a36 2625 u8 reserved_at_c0[0x10];
e281682b
SM		 2626 u8 rqt_actual_size[0x10];
2627
b4ff3a36 2628 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2629
2630 struct mlx5_ifc_rq_num_bits rq_num[0];
2631};
2632
2633enum {
2634 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2635 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2636};
2637
2638enum {
2639 MLX5_RQC_STATE_RST = 0x0,
2640 MLX5_RQC_STATE_RDY = 0x1,
2641 MLX5_RQC_STATE_ERR = 0x3,
2642};
2643
2644struct mlx5_ifc_rqc_bits {
2645 u8 rlky[0x1];
03404e8a 2646 u8 delay_drop_en[0x1];
7d5e1423 2647 u8 scatter_fcs[0x1];
e281682b
SM		 2648 u8 vsd[0x1];
2649 u8 mem_rq_type[0x4];
2650 u8 state[0x4];
b4ff3a36 2651 u8 reserved_at_c[0x1];
e281682b 2652 u8 flush_in_error_en[0x1];
40817cdb
OG		 2653 u8 hairpin[0x1];
2654 u8 reserved_at_f[0x11];
e281682b 2655
b4ff3a36 2656 u8 reserved_at_20[0x8];
e281682b
SM		 2657 u8 user_index[0x18];
2658
b4ff3a36 2659 u8 reserved_at_40[0x8];
e281682b
SM		 2660 u8 cqn[0x18];
2661
2662 u8 counter_set_id[0x8];
b4ff3a36 2663 u8 reserved_at_68[0x18];
e281682b 2664
b4ff3a36 2665 u8 reserved_at_80[0x8];
e281682b
SM		 2666 u8 rmpn[0x18];
2667
40817cdb
OG		 2668 u8 reserved_at_a0[0x8];
2669 u8 hairpin_peer_sq[0x18];
2670
2671 u8 reserved_at_c0[0x10];
2672 u8 hairpin_peer_vhca[0x10];
2673
2674 u8 reserved_at_e0[0xa0];
e281682b
SM		 2675
2676 struct mlx5_ifc_wq_bits wq;
2677};
2678
2679enum {
2680 MLX5_RMPC_STATE_RDY = 0x1,
2681 MLX5_RMPC_STATE_ERR = 0x3,
2682};
2683
2684struct mlx5_ifc_rmpc_bits {
b4ff3a36 2685 u8 reserved_at_0[0x8];
e281682b 2686 u8 state[0x4];
b4ff3a36 2687 u8 reserved_at_c[0x14];
e281682b
SM		 2688
2689 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2690 u8 reserved_at_21[0x1f];
e281682b 2691
b4ff3a36 2692 u8 reserved_at_40[0x140];
e281682b
SM		 2693
2694 struct mlx5_ifc_wq_bits wq;
2695};
2696
e281682b 2697struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2698 u8 reserved_at_0[0x5];
2699 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2700 u8 reserved_at_8[0x15];
2701 u8 disable_mc_local_lb[0x1];
2702 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2703 u8 roce_en[0x1];
2704
d82b7318 2705 u8 arm_change_event[0x1];
b4ff3a36 2706 u8 reserved_at_21[0x1a];
d82b7318
SM		 2707 u8 event_on_mtu[0x1];
2708 u8 event_on_promisc_change[0x1];
2709 u8 event_on_vlan_change[0x1];
2710 u8 event_on_mc_address_change[0x1];
2711 u8 event_on_uc_address_change[0x1];
e281682b 2712
32f69e4b
DJ		 2713 u8 reserved_at_40[0xc];
2714
2715 u8 affiliation_criteria[0x4];
2716 u8 affiliated_vhca_id[0x10];
2717
2718 u8 reserved_at_60[0xd0];
d82b7318
SM		 2719
2720 u8 mtu[0x10];
2721
9efa7525
AS		 2722 u8 system_image_guid[0x40];
2723 u8 port_guid[0x40];
2724 u8 node_guid[0x40];
2725
b4ff3a36 2726 u8 reserved_at_200[0x140];
9efa7525 2727 u8 qkey_violation_counter[0x10];
b4ff3a36 2728 u8 reserved_at_350[0x430];
d82b7318
SM		 2729
2730 u8 promisc_uc[0x1];
2731 u8 promisc_mc[0x1];
2732 u8 promisc_all[0x1];
b4ff3a36 2733 u8 reserved_at_783[0x2];
e281682b 2734 u8 allowed_list_type[0x3];
b4ff3a36 2735 u8 reserved_at_788[0xc];
e281682b
SM		 2736 u8 allowed_list_size[0xc];
2737
2738 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2739
b4ff3a36 2740 u8 reserved_at_7e0[0x20];
e281682b
SM		 2741
2742 u8 current_uc_mac_address[0][0x40];
2743};
2744
2745enum {
2746 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2747 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2748 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2749 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2750};
2751
2752struct mlx5_ifc_mkc_bits {
b4ff3a36 2753 u8 reserved_at_0[0x1];
e281682b 2754 u8 free[0x1];
b4ff3a36 2755 u8 reserved_at_2[0xd];
e281682b
SM		 2756 u8 small_fence_on_rdma_read_response[0x1];
2757 u8 umr_en[0x1];
2758 u8 a[0x1];
2759 u8 rw[0x1];
2760 u8 rr[0x1];
2761 u8 lw[0x1];
2762 u8 lr[0x1];
2763 u8 access_mode[0x2];
b4ff3a36 2764 u8 reserved_at_18[0x8];
e281682b
SM		 2765
2766 u8 qpn[0x18];
2767 u8 mkey_7_0[0x8];
2768
b4ff3a36 2769 u8 reserved_at_40[0x20];
e281682b
SM		 2770
2771 u8 length64[0x1];
2772 u8 bsf_en[0x1];
2773 u8 sync_umr[0x1];
b4ff3a36 2774 u8 reserved_at_63[0x2];
e281682b 2775 u8 expected_sigerr_count[0x1];
b4ff3a36 2776 u8 reserved_at_66[0x1];
e281682b
SM		 2777 u8 en_rinval[0x1];
2778 u8 pd[0x18];
2779
2780 u8 start_addr[0x40];
2781
2782 u8 len[0x40];
2783
2784 u8 bsf_octword_size[0x20];
2785
b4ff3a36 2786 u8 reserved_at_120[0x80];
e281682b
SM		 2787
2788 u8 translations_octword_size[0x20];
2789
b4ff3a36 2790 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2791 u8 log_page_size[0x5];
2792
b4ff3a36 2793 u8 reserved_at_1e0[0x20];
e281682b
SM		 2794};
2795
2796struct mlx5_ifc_pkey_bits {
b4ff3a36 2797 u8 reserved_at_0[0x10];
e281682b
SM		 2798 u8 pkey[0x10];
2799};
2800
2801struct mlx5_ifc_array128_auto_bits {
2802 u8 array128_auto[16][0x8];
2803};
2804
2805struct mlx5_ifc_hca_vport_context_bits {
2806 u8 field_select[0x20];
2807
b4ff3a36 2808 u8 reserved_at_20[0xe0];
e281682b
SM		 2809
2810 u8 sm_virt_aware[0x1];
2811 u8 has_smi[0x1];
2812 u8 has_raw[0x1];
2813 u8 grh_required[0x1];
b4ff3a36 2814 u8 reserved_at_104[0xc];
707c4602
MD		 2815 u8 port_physical_state[0x4];
2816 u8 vport_state_policy[0x4];
2817 u8 port_state[0x4];
e281682b
SM		 2818 u8 vport_state[0x4];
2819
b4ff3a36 2820 u8 reserved_at_120[0x20];
707c4602
MD		 2821
2822 u8 system_image_guid[0x40];
e281682b
SM		 2823
2824 u8 port_guid[0x40];
2825
2826 u8 node_guid[0x40];
2827
2828 u8 cap_mask1[0x20];
2829
2830 u8 cap_mask1_field_select[0x20];
2831
2832 u8 cap_mask2[0x20];
2833
2834 u8 cap_mask2_field_select[0x20];
2835
b4ff3a36 2836 u8 reserved_at_280[0x80];
e281682b
SM		 2837
2838 u8 lid[0x10];
b4ff3a36 2839 u8 reserved_at_310[0x4];
e281682b
SM		 2840 u8 init_type_reply[0x4];
2841 u8 lmc[0x3];
2842 u8 subnet_timeout[0x5];
2843
2844 u8 sm_lid[0x10];
2845 u8 sm_sl[0x4];
b4ff3a36 2846 u8 reserved_at_334[0xc];
e281682b
SM		 2847
2848 u8 qkey_violation_counter[0x10];
2849 u8 pkey_violation_counter[0x10];
2850
b4ff3a36 2851 u8 reserved_at_360[0xca0];
e281682b
SM		 2852};
2853
d6666753 2854struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2855 u8 reserved_at_0[0x3];
d6666753
SM		 2856 u8 vport_svlan_strip[0x1];
2857 u8 vport_cvlan_strip[0x1];
2858 u8 vport_svlan_insert[0x1];
2859 u8 vport_cvlan_insert[0x2];
b4ff3a36 2860 u8 reserved_at_8[0x18];
d6666753 2861
b4ff3a36 2862 u8 reserved_at_20[0x20];
d6666753
SM		 2863
2864 u8 svlan_cfi[0x1];
2865 u8 svlan_pcp[0x3];
2866 u8 svlan_id[0xc];
2867 u8 cvlan_cfi[0x1];
2868 u8 cvlan_pcp[0x3];
2869 u8 cvlan_id[0xc];
2870
b4ff3a36 2871 u8 reserved_at_60[0x7a0];
d6666753
SM		 2872};
2873
e281682b
SM		 2874enum {
2875 MLX5_EQC_STATUS_OK = 0x0,
2876 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2877};
2878
2879enum {
2880 MLX5_EQC_ST_ARMED = 0x9,
2881 MLX5_EQC_ST_FIRED = 0xa,
2882};
2883
2884struct mlx5_ifc_eqc_bits {
2885 u8 status[0x4];
b4ff3a36 2886 u8 reserved_at_4[0x9];
e281682b
SM		 2887 u8 ec[0x1];
2888 u8 oi[0x1];
b4ff3a36 2889 u8 reserved_at_f[0x5];
e281682b 2890 u8 st[0x4];
b4ff3a36 2891 u8 reserved_at_18[0x8];
e281682b 2892
b4ff3a36 2893 u8 reserved_at_20[0x20];
e281682b 2894
b4ff3a36 2895 u8 reserved_at_40[0x14];
e281682b 2896 u8 page_offset[0x6];
b4ff3a36 2897 u8 reserved_at_5a[0x6];
e281682b 2898
b4ff3a36 2899 u8 reserved_at_60[0x3];
e281682b
SM		 2900 u8 log_eq_size[0x5];
2901 u8 uar_page[0x18];
2902
b4ff3a36 2903 u8 reserved_at_80[0x20];
e281682b 2904
b4ff3a36 2905 u8 reserved_at_a0[0x18];
e281682b
SM		 2906 u8 intr[0x8];
2907
b4ff3a36 2908 u8 reserved_at_c0[0x3];
e281682b 2909 u8 log_page_size[0x5];
b4ff3a36 2910 u8 reserved_at_c8[0x18];
e281682b 2911
b4ff3a36 2912 u8 reserved_at_e0[0x60];
e281682b 2913
b4ff3a36 2914 u8 reserved_at_140[0x8];
e281682b
SM		 2915 u8 consumer_counter[0x18];
2916
b4ff3a36 2917 u8 reserved_at_160[0x8];
e281682b
SM		 2918 u8 producer_counter[0x18];
2919
b4ff3a36 2920 u8 reserved_at_180[0x80];
e281682b
SM		 2921};
2922
2923enum {
2924 MLX5_DCTC_STATE_ACTIVE = 0x0,
2925 MLX5_DCTC_STATE_DRAINING = 0x1,
2926 MLX5_DCTC_STATE_DRAINED = 0x2,
2927};
2928
2929enum {
2930 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2931 MLX5_DCTC_CS_RES_NA = 0x1,
2932 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2933};
2934
2935enum {
2936 MLX5_DCTC_MTU_256_BYTES = 0x1,
2937 MLX5_DCTC_MTU_512_BYTES = 0x2,
2938 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2939 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2940 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2941};
2942
2943struct mlx5_ifc_dctc_bits {
b4ff3a36 2944 u8 reserved_at_0[0x4];
e281682b 2945 u8 state[0x4];
b4ff3a36 2946 u8 reserved_at_8[0x18];
e281682b 2947
b4ff3a36 2948 u8 reserved_at_20[0x8];
e281682b
SM		 2949 u8 user_index[0x18];
2950
b4ff3a36 2951 u8 reserved_at_40[0x8];
e281682b
SM		 2952 u8 cqn[0x18];
2953
2954 u8 counter_set_id[0x8];
2955 u8 atomic_mode[0x4];
2956 u8 rre[0x1];
2957 u8 rwe[0x1];
2958 u8 rae[0x1];
2959 u8 atomic_like_write_en[0x1];
2960 u8 latency_sensitive[0x1];
2961 u8 rlky[0x1];
2962 u8 free_ar[0x1];
b4ff3a36 2963 u8 reserved_at_73[0xd];
e281682b 2964
b4ff3a36 2965 u8 reserved_at_80[0x8];
e281682b 2966 u8 cs_res[0x8];
b4ff3a36 2967 u8 reserved_at_90[0x3];
e281682b 2968 u8 min_rnr_nak[0x5];
b4ff3a36 2969 u8 reserved_at_98[0x8];
e281682b 2970
b4ff3a36 2971 u8 reserved_at_a0[0x8];
7486216b 2972 u8 srqn_xrqn[0x18];
e281682b 2973
b4ff3a36 2974 u8 reserved_at_c0[0x8];
e281682b
SM		 2975 u8 pd[0x18];
2976
2977 u8 tclass[0x8];
b4ff3a36 2978 u8 reserved_at_e8[0x4];
e281682b
SM		 2979 u8 flow_label[0x14];
2980
2981 u8 dc_access_key[0x40];
2982
b4ff3a36 2983 u8 reserved_at_140[0x5];
e281682b
SM		 2984 u8 mtu[0x3];
2985 u8 port[0x8];
2986 u8 pkey_index[0x10];
2987
b4ff3a36 2988 u8 reserved_at_160[0x8];
e281682b 2989 u8 my_addr_index[0x8];
b4ff3a36 2990 u8 reserved_at_170[0x8];
e281682b
SM		 2991 u8 hop_limit[0x8];
2992
2993 u8 dc_access_key_violation_count[0x20];
2994
b4ff3a36 2995 u8 reserved_at_1a0[0x14];
e281682b
SM		 2996 u8 dei_cfi[0x1];
2997 u8 eth_prio[0x3];
2998 u8 ecn[0x2];
2999 u8 dscp[0x6];
3000
b4ff3a36 3001 u8 reserved_at_1c0[0x40];
e281682b
SM		 3002};
3003
3004enum {
3005 MLX5_CQC_STATUS_OK = 0x0,
3006 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3007 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3008};
3009
3010enum {
3011 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3012 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3013};
3014
3015enum {
3016 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3017 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3018 MLX5_CQC_ST_FIRED = 0xa,
3019};
3020
7d5e1423
SM		 3021enum {
3022 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3023 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3024 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3025};
3026
e281682b
SM		 3027struct mlx5_ifc_cqc_bits {
3028 u8 status[0x4];
b4ff3a36 3029 u8 reserved_at_4[0x4];
e281682b
SM		 3030 u8 cqe_sz[0x3];
3031 u8 cc[0x1];
b4ff3a36 3032 u8 reserved_at_c[0x1];
e281682b
SM		 3033 u8 scqe_break_moderation_en[0x1];
3034 u8 oi[0x1];
7d5e1423
SM		 3035 u8 cq_period_mode[0x2];
3036 u8 cqe_comp_en[0x1];
e281682b
SM		 3037 u8 mini_cqe_res_format[0x2];
3038 u8 st[0x4];
b4ff3a36 3039 u8 reserved_at_18[0x8];
e281682b 3040
b4ff3a36 3041 u8 reserved_at_20[0x20];
e281682b 3042
b4ff3a36 3043 u8 reserved_at_40[0x14];
e281682b 3044 u8 page_offset[0x6];
b4ff3a36 3045 u8 reserved_at_5a[0x6];
e281682b 3046
b4ff3a36 3047 u8 reserved_at_60[0x3];
e281682b
SM		 3048 u8 log_cq_size[0x5];
3049 u8 uar_page[0x18];
3050
b4ff3a36 3051 u8 reserved_at_80[0x4];
e281682b
SM		 3052 u8 cq_period[0xc];
3053 u8 cq_max_count[0x10];
3054
b4ff3a36 3055 u8 reserved_at_a0[0x18];
e281682b
SM		 3056 u8 c_eqn[0x8];
3057
b4ff3a36 3058 u8 reserved_at_c0[0x3];
e281682b 3059 u8 log_page_size[0x5];
b4ff3a36 3060 u8 reserved_at_c8[0x18];
e281682b 3061
b4ff3a36 3062 u8 reserved_at_e0[0x20];
e281682b 3063
b4ff3a36 3064 u8 reserved_at_100[0x8];
e281682b
SM		 3065 u8 last_notified_index[0x18];
3066
b4ff3a36 3067 u8 reserved_at_120[0x8];
e281682b
SM		 3068 u8 last_solicit_index[0x18];
3069
b4ff3a36 3070 u8 reserved_at_140[0x8];
e281682b
SM		 3071 u8 consumer_counter[0x18];
3072
b4ff3a36 3073 u8 reserved_at_160[0x8];
e281682b
SM		 3074 u8 producer_counter[0x18];
3075
b4ff3a36 3076 u8 reserved_at_180[0x40];
e281682b
SM		 3077
3078 u8 dbr_addr[0x40];
3079};
3080
3081union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3082 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3083 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3084 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3085 u8 reserved_at_0[0x800];
e281682b
SM		 3086};
3087
3088struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3089 u8 reserved_at_0[0xc0];
e281682b 3090
b4ff3a36 3091 u8 reserved_at_c0[0x8];
211e6c80
MD		 3092 u8 ieee_vendor_id[0x18];
3093
b4ff3a36 3094 u8 reserved_at_e0[0x10];
e281682b
SM		 3095 u8 vsd_vendor_id[0x10];
3096
3097 u8 vsd[208][0x8];
3098
3099 u8 vsd_contd_psid[16][0x8];
3100};
3101
7486216b
SM		 3102enum {
3103 MLX5_XRQC_STATE_GOOD = 0x0,
3104 MLX5_XRQC_STATE_ERROR = 0x1,
3105};
3106
3107enum {
3108 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3109 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3110};
3111
3112enum {
3113 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3114};
3115
3116struct mlx5_ifc_tag_matching_topology_context_bits {
3117 u8 log_matching_list_sz[0x4];
3118 u8 reserved_at_4[0xc];
3119 u8 append_next_index[0x10];
3120
3121 u8 sw_phase_cnt[0x10];
3122 u8 hw_phase_cnt[0x10];
3123
3124 u8 reserved_at_40[0x40];
3125};
3126
3127struct mlx5_ifc_xrqc_bits {
3128 u8 state[0x4];
3129 u8 rlkey[0x1];
3130 u8 reserved_at_5[0xf];
3131 u8 topology[0x4];
3132 u8 reserved_at_18[0x4];
3133 u8 offload[0x4];
3134
3135 u8 reserved_at_20[0x8];
3136 u8 user_index[0x18];
3137
3138 u8 reserved_at_40[0x8];
3139 u8 cqn[0x18];
3140
3141 u8 reserved_at_60[0xa0];
3142
3143 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3144
6e44636a 3145 u8 reserved_at_180[0x280];
7486216b
SM		 3146
3147 struct mlx5_ifc_wq_bits wq;
3148};
3149
e281682b
SM		 3150union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3151 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3152 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3153 u8 reserved_at_0[0x20];
e281682b
SM		 3154};
3155
3156union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3157 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3158 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3159 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3160 u8 reserved_at_0[0x20];
e281682b
SM		 3161};
3162
3163union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3164 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3165 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3166 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3167 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3168 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3169 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3170 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3171 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3172 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3173 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3174 u8 reserved_at_0[0x7c0];
e281682b
SM		 3175};
3176
8ed1a630
GP		 3177union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3178 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3179 u8 reserved_at_0[0x7c0];
3180};
3181
e281682b
SM		 3182union mlx5_ifc_event_auto_bits {
3183 struct mlx5_ifc_comp_event_bits comp_event;
3184 struct mlx5_ifc_dct_events_bits dct_events;
3185 struct mlx5_ifc_qp_events_bits qp_events;
3186 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3187 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3188 struct mlx5_ifc_cq_error_bits cq_error;
3189 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3190 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3191 struct mlx5_ifc_gpio_event_bits gpio_event;
3192 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3193 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3194 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3195 u8 reserved_at_0[0xe0];
e281682b
SM		 3196};
3197
3198struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3199 u8 reserved_at_0[0x100];
e281682b
SM		 3200
3201 u8 assert_existptr[0x20];
3202
3203 u8 assert_callra[0x20];
3204
b4ff3a36 3205 u8 reserved_at_140[0x40];
e281682b
SM		 3206
3207 u8 fw_version[0x20];
3208
3209 u8 hw_id[0x20];
3210
b4ff3a36 3211 u8 reserved_at_1c0[0x20];
e281682b
SM		 3212
3213 u8 irisc_index[0x8];
3214 u8 synd[0x8];
3215 u8 ext_synd[0x10];
3216};
3217
3218struct mlx5_ifc_register_loopback_control_bits {
3219 u8 no_lb[0x1];
b4ff3a36 3220 u8 reserved_at_1[0x7];
e281682b 3221 u8 port[0x8];
b4ff3a36 3222 u8 reserved_at_10[0x10];
e281682b 3223
b4ff3a36 3224 u8 reserved_at_20[0x60];
e281682b
SM		 3225};
3226
813f8540
MHY		 3227struct mlx5_ifc_vport_tc_element_bits {
3228 u8 traffic_class[0x4];
3229 u8 reserved_at_4[0xc];
3230 u8 vport_number[0x10];
3231};
3232
3233struct mlx5_ifc_vport_element_bits {
3234 u8 reserved_at_0[0x10];
3235 u8 vport_number[0x10];
3236};
3237
3238enum {
3239 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3240 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3241 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3242};
3243
3244struct mlx5_ifc_tsar_element_bits {
3245 u8 reserved_at_0[0x8];
3246 u8 tsar_type[0x8];
3247 u8 reserved_at_10[0x10];
3248};
3249
8812c24d
MD		 3250enum {
3251 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3252 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3253};
3254
e281682b
SM		 3255struct mlx5_ifc_teardown_hca_out_bits {
3256 u8 status[0x8];
b4ff3a36 3257 u8 reserved_at_8[0x18];
e281682b
SM		 3258
3259 u8 syndrome[0x20];
3260
8812c24d
MD		 3261 u8 reserved_at_40[0x3f];
3262
3263 u8 force_state[0x1];
e281682b
SM		 3264};
3265
3266enum {
3267 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3268 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3269};
3270
3271struct mlx5_ifc_teardown_hca_in_bits {
3272 u8 opcode[0x10];
b4ff3a36 3273 u8 reserved_at_10[0x10];
e281682b 3274
b4ff3a36 3275 u8 reserved_at_20[0x10];
e281682b
SM		 3276 u8 op_mod[0x10];
3277
b4ff3a36 3278 u8 reserved_at_40[0x10];
e281682b
SM		 3279 u8 profile[0x10];
3280
b4ff3a36 3281 u8 reserved_at_60[0x20];
e281682b
SM		 3282};
3283
3284struct mlx5_ifc_sqerr2rts_qp_out_bits {
3285 u8 status[0x8];
b4ff3a36 3286 u8 reserved_at_8[0x18];
e281682b
SM		 3287
3288 u8 syndrome[0x20];
3289
b4ff3a36 3290 u8 reserved_at_40[0x40];
e281682b
SM		 3291};
3292
3293struct mlx5_ifc_sqerr2rts_qp_in_bits {
3294 u8 opcode[0x10];
b4ff3a36 3295 u8 reserved_at_10[0x10];
e281682b 3296
b4ff3a36 3297 u8 reserved_at_20[0x10];
e281682b
SM		 3298 u8 op_mod[0x10];
3299
b4ff3a36 3300 u8 reserved_at_40[0x8];
e281682b
SM		 3301 u8 qpn[0x18];
3302
b4ff3a36 3303 u8 reserved_at_60[0x20];
e281682b
SM		 3304
3305 u8 opt_param_mask[0x20];
3306
b4ff3a36 3307 u8 reserved_at_a0[0x20];
e281682b
SM		 3308
3309 struct mlx5_ifc_qpc_bits qpc;
3310
b4ff3a36 3311 u8 reserved_at_800[0x80];
e281682b
SM		 3312};
3313
3314struct mlx5_ifc_sqd2rts_qp_out_bits {
3315 u8 status[0x8];
b4ff3a36 3316 u8 reserved_at_8[0x18];
e281682b
SM		 3317
3318 u8 syndrome[0x20];
3319
b4ff3a36 3320 u8 reserved_at_40[0x40];
e281682b
SM		 3321};
3322
3323struct mlx5_ifc_sqd2rts_qp_in_bits {
3324 u8 opcode[0x10];
b4ff3a36 3325 u8 reserved_at_10[0x10];
e281682b 3326
b4ff3a36 3327 u8 reserved_at_20[0x10];
e281682b
SM		 3328 u8 op_mod[0x10];
3329
b4ff3a36 3330 u8 reserved_at_40[0x8];
e281682b
SM		 3331 u8 qpn[0x18];
3332
b4ff3a36 3333 u8 reserved_at_60[0x20];
e281682b
SM		 3334
3335 u8 opt_param_mask[0x20];
3336
b4ff3a36 3337 u8 reserved_at_a0[0x20];
e281682b
SM		 3338
3339 struct mlx5_ifc_qpc_bits qpc;
3340
b4ff3a36 3341 u8 reserved_at_800[0x80];
e281682b
SM		 3342};
3343
3344struct mlx5_ifc_set_roce_address_out_bits {
3345 u8 status[0x8];
b4ff3a36 3346 u8 reserved_at_8[0x18];
e281682b
SM		 3347
3348 u8 syndrome[0x20];
3349
b4ff3a36 3350 u8 reserved_at_40[0x40];
e281682b
SM		 3351};
3352
3353struct mlx5_ifc_set_roce_address_in_bits {
3354 u8 opcode[0x10];
b4ff3a36 3355 u8 reserved_at_10[0x10];
e281682b 3356
b4ff3a36 3357 u8 reserved_at_20[0x10];
e281682b
SM		 3358 u8 op_mod[0x10];
3359
3360 u8 roce_address_index[0x10];
32f69e4b
DJ		 3361 u8 reserved_at_50[0xc];
3362 u8 vhca_port_num[0x4];
e281682b 3363
b4ff3a36 3364 u8 reserved_at_60[0x20];
e281682b
SM		 3365
3366 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3367};
3368
3369struct mlx5_ifc_set_mad_demux_out_bits {
3370 u8 status[0x8];
b4ff3a36 3371 u8 reserved_at_8[0x18];
e281682b
SM		 3372
3373 u8 syndrome[0x20];
3374
b4ff3a36 3375 u8 reserved_at_40[0x40];
e281682b
SM		 3376};
3377
3378enum {
3379 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3380 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3381};
3382
3383struct mlx5_ifc_set_mad_demux_in_bits {
3384 u8 opcode[0x10];
b4ff3a36 3385 u8 reserved_at_10[0x10];
e281682b 3386
b4ff3a36 3387 u8 reserved_at_20[0x10];
e281682b
SM		 3388 u8 op_mod[0x10];
3389
b4ff3a36 3390 u8 reserved_at_40[0x20];
e281682b 3391
b4ff3a36 3392 u8 reserved_at_60[0x6];
e281682b 3393 u8 demux_mode[0x2];
b4ff3a36 3394 u8 reserved_at_68[0x18];
e281682b
SM		 3395};
3396
3397struct mlx5_ifc_set_l2_table_entry_out_bits {
3398 u8 status[0x8];
b4ff3a36 3399 u8 reserved_at_8[0x18];
e281682b
SM		 3400
3401 u8 syndrome[0x20];
3402
b4ff3a36 3403 u8 reserved_at_40[0x40];
e281682b
SM		 3404};
3405
3406struct mlx5_ifc_set_l2_table_entry_in_bits {
3407 u8 opcode[0x10];
b4ff3a36 3408 u8 reserved_at_10[0x10];
e281682b 3409
b4ff3a36 3410 u8 reserved_at_20[0x10];
e281682b
SM		 3411 u8 op_mod[0x10];
3412
b4ff3a36 3413 u8 reserved_at_40[0x60];
e281682b 3414
b4ff3a36 3415 u8 reserved_at_a0[0x8];
e281682b
SM		 3416 u8 table_index[0x18];
3417
b4ff3a36 3418 u8 reserved_at_c0[0x20];
e281682b 3419
b4ff3a36 3420 u8 reserved_at_e0[0x13];
e281682b
SM		 3421 u8 vlan_valid[0x1];
3422 u8 vlan[0xc];
3423
3424 struct mlx5_ifc_mac_address_layout_bits mac_address;
3425
b4ff3a36 3426 u8 reserved_at_140[0xc0];
e281682b
SM		 3427};
3428
3429struct mlx5_ifc_set_issi_out_bits {
3430 u8 status[0x8];
b4ff3a36 3431 u8 reserved_at_8[0x18];
e281682b
SM		 3432
3433 u8 syndrome[0x20];
3434
b4ff3a36 3435 u8 reserved_at_40[0x40];
e281682b
SM		 3436};
3437
3438struct mlx5_ifc_set_issi_in_bits {
3439 u8 opcode[0x10];
b4ff3a36 3440 u8 reserved_at_10[0x10];
e281682b 3441
b4ff3a36 3442 u8 reserved_at_20[0x10];
e281682b
SM		 3443 u8 op_mod[0x10];
3444
b4ff3a36 3445 u8 reserved_at_40[0x10];
e281682b
SM		 3446 u8 current_issi[0x10];
3447
b4ff3a36 3448 u8 reserved_at_60[0x20];
e281682b
SM		 3449};
3450
3451struct mlx5_ifc_set_hca_cap_out_bits {
3452 u8 status[0x8];
b4ff3a36 3453 u8 reserved_at_8[0x18];
e281682b
SM		 3454
3455 u8 syndrome[0x20];
3456
b4ff3a36 3457 u8 reserved_at_40[0x40];
e281682b
SM		 3458};
3459
3460struct mlx5_ifc_set_hca_cap_in_bits {
3461 u8 opcode[0x10];
b4ff3a36 3462 u8 reserved_at_10[0x10];
e281682b 3463
b4ff3a36 3464 u8 reserved_at_20[0x10];
e281682b
SM		 3465 u8 op_mod[0x10];
3466
b4ff3a36 3467 u8 reserved_at_40[0x40];
e281682b
SM		 3468
3469 union mlx5_ifc_hca_cap_union_bits capability;
3470};
3471
26a81453
MG		 3472enum {
3473 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3474 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3475 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3476 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3477};
3478
e281682b
SM		 3479struct mlx5_ifc_set_fte_out_bits {
3480 u8 status[0x8];
b4ff3a36 3481 u8 reserved_at_8[0x18];
e281682b
SM		 3482
3483 u8 syndrome[0x20];
3484
b4ff3a36 3485 u8 reserved_at_40[0x40];
e281682b
SM		 3486};
3487
3488struct mlx5_ifc_set_fte_in_bits {
3489 u8 opcode[0x10];
b4ff3a36 3490 u8 reserved_at_10[0x10];
e281682b 3491
b4ff3a36 3492 u8 reserved_at_20[0x10];
e281682b
SM		 3493 u8 op_mod[0x10];
3494
7d5e1423
SM		 3495 u8 other_vport[0x1];
3496 u8 reserved_at_41[0xf];
3497 u8 vport_number[0x10];
3498
3499 u8 reserved_at_60[0x20];
e281682b
SM		 3500
3501 u8 table_type[0x8];
b4ff3a36 3502 u8 reserved_at_88[0x18];
e281682b 3503
b4ff3a36 3504 u8 reserved_at_a0[0x8];
e281682b
SM		 3505 u8 table_id[0x18];
3506
b4ff3a36 3507 u8 reserved_at_c0[0x18];
26a81453
MG		 3508 u8 modify_enable_mask[0x8];
3509
b4ff3a36 3510 u8 reserved_at_e0[0x20];
e281682b
SM		 3511
3512 u8 flow_index[0x20];
3513
b4ff3a36 3514 u8 reserved_at_120[0xe0];
e281682b
SM		 3515
3516 struct mlx5_ifc_flow_context_bits flow_context;
3517};
3518
3519struct mlx5_ifc_rts2rts_qp_out_bits {
3520 u8 status[0x8];
b4ff3a36 3521 u8 reserved_at_8[0x18];
e281682b
SM		 3522
3523 u8 syndrome[0x20];
3524
b4ff3a36 3525 u8 reserved_at_40[0x40];
e281682b
SM		 3526};
3527
3528struct mlx5_ifc_rts2rts_qp_in_bits {
3529 u8 opcode[0x10];
b4ff3a36 3530 u8 reserved_at_10[0x10];
e281682b 3531
b4ff3a36 3532 u8 reserved_at_20[0x10];
e281682b
SM		 3533 u8 op_mod[0x10];
3534
b4ff3a36 3535 u8 reserved_at_40[0x8];
e281682b
SM		 3536 u8 qpn[0x18];
3537
b4ff3a36 3538 u8 reserved_at_60[0x20];
e281682b
SM		 3539
3540 u8 opt_param_mask[0x20];
3541
b4ff3a36 3542 u8 reserved_at_a0[0x20];
e281682b
SM		 3543
3544 struct mlx5_ifc_qpc_bits qpc;
3545
b4ff3a36 3546 u8 reserved_at_800[0x80];
e281682b
SM		 3547};
3548
3549struct mlx5_ifc_rtr2rts_qp_out_bits {
3550 u8 status[0x8];
b4ff3a36 3551 u8 reserved_at_8[0x18];
e281682b
SM		 3552
3553 u8 syndrome[0x20];
3554
b4ff3a36 3555 u8 reserved_at_40[0x40];
e281682b
SM		 3556};
3557
3558struct mlx5_ifc_rtr2rts_qp_in_bits {
3559 u8 opcode[0x10];
b4ff3a36 3560 u8 reserved_at_10[0x10];
e281682b 3561
b4ff3a36 3562 u8 reserved_at_20[0x10];
e281682b
SM		 3563 u8 op_mod[0x10];
3564
b4ff3a36 3565 u8 reserved_at_40[0x8];
e281682b
SM		 3566 u8 qpn[0x18];
3567
b4ff3a36 3568 u8 reserved_at_60[0x20];
e281682b
SM		 3569
3570 u8 opt_param_mask[0x20];
3571
b4ff3a36 3572 u8 reserved_at_a0[0x20];
e281682b
SM		 3573
3574 struct mlx5_ifc_qpc_bits qpc;
3575
b4ff3a36 3576 u8 reserved_at_800[0x80];
e281682b
SM		 3577};
3578
3579struct mlx5_ifc_rst2init_qp_out_bits {
3580 u8 status[0x8];
b4ff3a36 3581 u8 reserved_at_8[0x18];
e281682b
SM		 3582
3583 u8 syndrome[0x20];
3584
b4ff3a36 3585 u8 reserved_at_40[0x40];
e281682b
SM		 3586};
3587
3588struct mlx5_ifc_rst2init_qp_in_bits {
3589 u8 opcode[0x10];
b4ff3a36 3590 u8 reserved_at_10[0x10];
e281682b 3591
b4ff3a36 3592 u8 reserved_at_20[0x10];
e281682b
SM		 3593 u8 op_mod[0x10];
3594
b4ff3a36 3595 u8 reserved_at_40[0x8];
e281682b
SM		 3596 u8 qpn[0x18];
3597
b4ff3a36 3598 u8 reserved_at_60[0x20];
e281682b
SM		 3599
3600 u8 opt_param_mask[0x20];
3601
b4ff3a36 3602 u8 reserved_at_a0[0x20];
e281682b
SM		 3603
3604 struct mlx5_ifc_qpc_bits qpc;
3605
b4ff3a36 3606 u8 reserved_at_800[0x80];
e281682b
SM		 3607};
3608
7486216b
SM		 3609struct mlx5_ifc_query_xrq_out_bits {
3610 u8 status[0x8];
3611 u8 reserved_at_8[0x18];
3612
3613 u8 syndrome[0x20];
3614
3615 u8 reserved_at_40[0x40];
3616
3617 struct mlx5_ifc_xrqc_bits xrq_context;
3618};
3619
3620struct mlx5_ifc_query_xrq_in_bits {
3621 u8 opcode[0x10];
3622 u8 reserved_at_10[0x10];
3623
3624 u8 reserved_at_20[0x10];
3625 u8 op_mod[0x10];
3626
3627 u8 reserved_at_40[0x8];
3628 u8 xrqn[0x18];
3629
3630 u8 reserved_at_60[0x20];
3631};
3632
e281682b
SM		 3633struct mlx5_ifc_query_xrc_srq_out_bits {
3634 u8 status[0x8];
b4ff3a36 3635 u8 reserved_at_8[0x18];
e281682b
SM		 3636
3637 u8 syndrome[0x20];
3638
b4ff3a36 3639 u8 reserved_at_40[0x40];
e281682b
SM		 3640
3641 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3642
b4ff3a36 3643 u8 reserved_at_280[0x600];
e281682b
SM		 3644
3645 u8 pas[0][0x40];
3646};
3647
3648struct mlx5_ifc_query_xrc_srq_in_bits {
3649 u8 opcode[0x10];
b4ff3a36 3650 u8 reserved_at_10[0x10];
e281682b 3651
b4ff3a36 3652 u8 reserved_at_20[0x10];
e281682b
SM		 3653 u8 op_mod[0x10];
3654
b4ff3a36 3655 u8 reserved_at_40[0x8];
e281682b
SM		 3656 u8 xrc_srqn[0x18];
3657
b4ff3a36 3658 u8 reserved_at_60[0x20];
e281682b
SM		 3659};
3660
3661enum {
3662 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3663 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3664};
3665
3666struct mlx5_ifc_query_vport_state_out_bits {
3667 u8 status[0x8];
b4ff3a36 3668 u8 reserved_at_8[0x18];
e281682b
SM		 3669
3670 u8 syndrome[0x20];
3671
b4ff3a36 3672 u8 reserved_at_40[0x20];
e281682b 3673
b4ff3a36 3674 u8 reserved_at_60[0x18];
e281682b
SM		 3675 u8 admin_state[0x4];
3676 u8 state[0x4];
3677};
3678
3679enum {
3680 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3681 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3682};
3683
3684struct mlx5_ifc_query_vport_state_in_bits {
3685 u8 opcode[0x10];
b4ff3a36 3686 u8 reserved_at_10[0x10];
e281682b 3687
b4ff3a36 3688 u8 reserved_at_20[0x10];
e281682b
SM		 3689 u8 op_mod[0x10];
3690
3691 u8 other_vport[0x1];
b4ff3a36 3692 u8 reserved_at_41[0xf];
e281682b
SM		 3693 u8 vport_number[0x10];
3694
b4ff3a36 3695 u8 reserved_at_60[0x20];
e281682b
SM		 3696};
3697
61c5b5c9
MS		 3698struct mlx5_ifc_query_vnic_env_out_bits {
3699 u8 status[0x8];
3700 u8 reserved_at_8[0x18];
3701
3702 u8 syndrome[0x20];
3703
3704 u8 reserved_at_40[0x40];
3705
3706 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3707};
3708
3709enum {
3710 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3711};
3712
3713struct mlx5_ifc_query_vnic_env_in_bits {
3714 u8 opcode[0x10];
3715 u8 reserved_at_10[0x10];
3716
3717 u8 reserved_at_20[0x10];
3718 u8 op_mod[0x10];
3719
3720 u8 other_vport[0x1];
3721 u8 reserved_at_41[0xf];
3722 u8 vport_number[0x10];
3723
3724 u8 reserved_at_60[0x20];
3725};
3726
e281682b
SM		 3727struct mlx5_ifc_query_vport_counter_out_bits {
3728 u8 status[0x8];
b4ff3a36 3729 u8 reserved_at_8[0x18];
e281682b
SM		 3730
3731 u8 syndrome[0x20];
3732
b4ff3a36 3733 u8 reserved_at_40[0x40];
e281682b
SM		 3734
3735 struct mlx5_ifc_traffic_counter_bits received_errors;
3736
3737 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3738
3739 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3740
3741 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3742
3743 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3744
3745 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3746
3747 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3748
3749 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3750
3751 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3752
3753 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3754
3755 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3756
3757 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3758
b4ff3a36 3759 u8 reserved_at_680[0xa00];
e281682b
SM		 3760};
3761
3762enum {
3763 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3764};
3765
3766struct mlx5_ifc_query_vport_counter_in_bits {
3767 u8 opcode[0x10];
b4ff3a36 3768 u8 reserved_at_10[0x10];
e281682b 3769
b4ff3a36 3770 u8 reserved_at_20[0x10];
e281682b
SM		 3771 u8 op_mod[0x10];
3772
3773 u8 other_vport[0x1];
b54ba277
MY		 3774 u8 reserved_at_41[0xb];
3775 u8 port_num[0x4];
e281682b
SM		 3776 u8 vport_number[0x10];
3777
b4ff3a36 3778 u8 reserved_at_60[0x60];
e281682b
SM		 3779
3780 u8 clear[0x1];
b4ff3a36 3781 u8 reserved_at_c1[0x1f];
e281682b 3782
b4ff3a36 3783 u8 reserved_at_e0[0x20];
e281682b
SM		 3784};
3785
3786struct mlx5_ifc_query_tis_out_bits {
3787 u8 status[0x8];
b4ff3a36 3788 u8 reserved_at_8[0x18];
e281682b
SM		 3789
3790 u8 syndrome[0x20];
3791
b4ff3a36 3792 u8 reserved_at_40[0x40];
e281682b
SM		 3793
3794 struct mlx5_ifc_tisc_bits tis_context;
3795};
3796
3797struct mlx5_ifc_query_tis_in_bits {
3798 u8 opcode[0x10];
b4ff3a36 3799 u8 reserved_at_10[0x10];
e281682b 3800
b4ff3a36 3801 u8 reserved_at_20[0x10];
e281682b
SM		 3802 u8 op_mod[0x10];
3803
b4ff3a36 3804 u8 reserved_at_40[0x8];
e281682b
SM		 3805 u8 tisn[0x18];
3806
b4ff3a36 3807 u8 reserved_at_60[0x20];
e281682b
SM		 3808};
3809
3810struct mlx5_ifc_query_tir_out_bits {
3811 u8 status[0x8];
b4ff3a36 3812 u8 reserved_at_8[0x18];
e281682b
SM		 3813
3814 u8 syndrome[0x20];
3815
b4ff3a36 3816 u8 reserved_at_40[0xc0];
e281682b
SM		 3817
3818 struct mlx5_ifc_tirc_bits tir_context;
3819};
3820
3821struct mlx5_ifc_query_tir_in_bits {
3822 u8 opcode[0x10];
b4ff3a36 3823 u8 reserved_at_10[0x10];
e281682b 3824
b4ff3a36 3825 u8 reserved_at_20[0x10];
e281682b
SM		 3826 u8 op_mod[0x10];
3827
b4ff3a36 3828 u8 reserved_at_40[0x8];
e281682b
SM		 3829 u8 tirn[0x18];
3830
b4ff3a36 3831 u8 reserved_at_60[0x20];
e281682b
SM		 3832};
3833
3834struct mlx5_ifc_query_srq_out_bits {
3835 u8 status[0x8];
b4ff3a36 3836 u8 reserved_at_8[0x18];
e281682b
SM		 3837
3838 u8 syndrome[0x20];
3839
b4ff3a36 3840 u8 reserved_at_40[0x40];
e281682b
SM		 3841
3842 struct mlx5_ifc_srqc_bits srq_context_entry;
3843
b4ff3a36 3844 u8 reserved_at_280[0x600];
e281682b
SM		 3845
3846 u8 pas[0][0x40];
3847};
3848
3849struct mlx5_ifc_query_srq_in_bits {
3850 u8 opcode[0x10];
b4ff3a36 3851 u8 reserved_at_10[0x10];
e281682b 3852
b4ff3a36 3853 u8 reserved_at_20[0x10];
e281682b
SM		 3854 u8 op_mod[0x10];
3855
b4ff3a36 3856 u8 reserved_at_40[0x8];
e281682b
SM		 3857 u8 srqn[0x18];
3858
b4ff3a36 3859 u8 reserved_at_60[0x20];
e281682b
SM		 3860};
3861
3862struct mlx5_ifc_query_sq_out_bits {
3863 u8 status[0x8];
b4ff3a36 3864 u8 reserved_at_8[0x18];
e281682b
SM		 3865
3866 u8 syndrome[0x20];
3867
b4ff3a36 3868 u8 reserved_at_40[0xc0];
e281682b
SM		 3869
3870 struct mlx5_ifc_sqc_bits sq_context;
3871};
3872
3873struct mlx5_ifc_query_sq_in_bits {
3874 u8 opcode[0x10];
b4ff3a36 3875 u8 reserved_at_10[0x10];
e281682b 3876
b4ff3a36 3877 u8 reserved_at_20[0x10];
e281682b
SM		 3878 u8 op_mod[0x10];
3879
b4ff3a36 3880 u8 reserved_at_40[0x8];
e281682b
SM		 3881 u8 sqn[0x18];
3882
b4ff3a36 3883 u8 reserved_at_60[0x20];
e281682b
SM		 3884};
3885
3886struct mlx5_ifc_query_special_contexts_out_bits {
3887 u8 status[0x8];
b4ff3a36 3888 u8 reserved_at_8[0x18];
e281682b
SM		 3889
3890 u8 syndrome[0x20];
3891
ec22eb53 3892 u8 dump_fill_mkey[0x20];
e281682b
SM		 3893
3894 u8 resd_lkey[0x20];
bcda1aca
AK		 3895
3896 u8 null_mkey[0x20];
3897
3898 u8 reserved_at_a0[0x60];
e281682b
SM		 3899};
3900
3901struct mlx5_ifc_query_special_contexts_in_bits {
3902 u8 opcode[0x10];
b4ff3a36 3903 u8 reserved_at_10[0x10];
e281682b 3904
b4ff3a36 3905 u8 reserved_at_20[0x10];
e281682b
SM		 3906 u8 op_mod[0x10];
3907
b4ff3a36 3908 u8 reserved_at_40[0x40];
e281682b
SM		 3909};
3910
813f8540
MHY		 3911struct mlx5_ifc_query_scheduling_element_out_bits {
3912 u8 opcode[0x10];
3913 u8 reserved_at_10[0x10];
3914
3915 u8 reserved_at_20[0x10];
3916 u8 op_mod[0x10];
3917
3918 u8 reserved_at_40[0xc0];
3919
3920 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3921
3922 u8 reserved_at_300[0x100];
3923};
3924
3925enum {
3926 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3927};
3928
3929struct mlx5_ifc_query_scheduling_element_in_bits {
3930 u8 opcode[0x10];
3931 u8 reserved_at_10[0x10];
3932
3933 u8 reserved_at_20[0x10];
3934 u8 op_mod[0x10];
3935
3936 u8 scheduling_hierarchy[0x8];
3937 u8 reserved_at_48[0x18];
3938
3939 u8 scheduling_element_id[0x20];
3940
3941 u8 reserved_at_80[0x180];
3942};
3943
e281682b
SM		 3944struct mlx5_ifc_query_rqt_out_bits {
3945 u8 status[0x8];
b4ff3a36 3946 u8 reserved_at_8[0x18];
e281682b
SM		 3947
3948 u8 syndrome[0x20];
3949
b4ff3a36 3950 u8 reserved_at_40[0xc0];
e281682b
SM		 3951
3952 struct mlx5_ifc_rqtc_bits rqt_context;
3953};
3954
3955struct mlx5_ifc_query_rqt_in_bits {
3956 u8 opcode[0x10];
b4ff3a36 3957 u8 reserved_at_10[0x10];
e281682b 3958
b4ff3a36 3959 u8 reserved_at_20[0x10];
e281682b
SM		 3960 u8 op_mod[0x10];
3961
b4ff3a36 3962 u8 reserved_at_40[0x8];
e281682b
SM		 3963 u8 rqtn[0x18];
3964
b4ff3a36 3965 u8 reserved_at_60[0x20];
e281682b
SM		 3966};
3967
3968struct mlx5_ifc_query_rq_out_bits {
3969 u8 status[0x8];
b4ff3a36 3970 u8 reserved_at_8[0x18];
e281682b
SM		 3971
3972 u8 syndrome[0x20];
3973
b4ff3a36 3974 u8 reserved_at_40[0xc0];
e281682b
SM		 3975
3976 struct mlx5_ifc_rqc_bits rq_context;
3977};
3978
3979struct mlx5_ifc_query_rq_in_bits {
3980 u8 opcode[0x10];
b4ff3a36 3981 u8 reserved_at_10[0x10];
e281682b 3982
b4ff3a36 3983 u8 reserved_at_20[0x10];
e281682b
SM		 3984 u8 op_mod[0x10];
3985
b4ff3a36 3986 u8 reserved_at_40[0x8];
e281682b
SM		 3987 u8 rqn[0x18];
3988
b4ff3a36 3989 u8 reserved_at_60[0x20];
e281682b
SM		 3990};
3991
3992struct mlx5_ifc_query_roce_address_out_bits {
3993 u8 status[0x8];
b4ff3a36 3994 u8 reserved_at_8[0x18];
e281682b
SM		 3995
3996 u8 syndrome[0x20];
3997
b4ff3a36 3998 u8 reserved_at_40[0x40];
e281682b
SM		 3999
4000 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4001};
4002
4003struct mlx5_ifc_query_roce_address_in_bits {
4004 u8 opcode[0x10];
b4ff3a36 4005 u8 reserved_at_10[0x10];
e281682b 4006
b4ff3a36 4007 u8 reserved_at_20[0x10];
e281682b
SM		 4008 u8 op_mod[0x10];
4009
4010 u8 roce_address_index[0x10];
32f69e4b
DJ		 4011 u8 reserved_at_50[0xc];
4012 u8 vhca_port_num[0x4];
e281682b 4013
b4ff3a36 4014 u8 reserved_at_60[0x20];
e281682b
SM		 4015};
4016
4017struct mlx5_ifc_query_rmp_out_bits {
4018 u8 status[0x8];
b4ff3a36 4019 u8 reserved_at_8[0x18];
e281682b
SM		 4020
4021 u8 syndrome[0x20];
4022
b4ff3a36 4023 u8 reserved_at_40[0xc0];
e281682b
SM		 4024
4025 struct mlx5_ifc_rmpc_bits rmp_context;
4026};
4027
4028struct mlx5_ifc_query_rmp_in_bits {
4029 u8 opcode[0x10];
b4ff3a36 4030 u8 reserved_at_10[0x10];
e281682b 4031
b4ff3a36 4032 u8 reserved_at_20[0x10];
e281682b
SM		 4033 u8 op_mod[0x10];
4034
b4ff3a36 4035 u8 reserved_at_40[0x8];
e281682b
SM		 4036 u8 rmpn[0x18];
4037
b4ff3a36 4038 u8 reserved_at_60[0x20];
e281682b
SM		 4039};
4040
4041struct mlx5_ifc_query_qp_out_bits {
4042 u8 status[0x8];
b4ff3a36 4043 u8 reserved_at_8[0x18];
e281682b
SM		 4044
4045 u8 syndrome[0x20];
4046
b4ff3a36 4047 u8 reserved_at_40[0x40];
e281682b
SM		 4048
4049 u8 opt_param_mask[0x20];
4050
b4ff3a36 4051 u8 reserved_at_a0[0x20];
e281682b
SM		 4052
4053 struct mlx5_ifc_qpc_bits qpc;
4054
b4ff3a36 4055 u8 reserved_at_800[0x80];
e281682b
SM		 4056
4057 u8 pas[0][0x40];
4058};
4059
4060struct mlx5_ifc_query_qp_in_bits {
4061 u8 opcode[0x10];
b4ff3a36 4062 u8 reserved_at_10[0x10];
e281682b 4063
b4ff3a36 4064 u8 reserved_at_20[0x10];
e281682b
SM		 4065 u8 op_mod[0x10];
4066
b4ff3a36 4067 u8 reserved_at_40[0x8];
e281682b
SM		 4068 u8 qpn[0x18];
4069
b4ff3a36 4070 u8 reserved_at_60[0x20];
e281682b
SM		 4071};
4072
4073struct mlx5_ifc_query_q_counter_out_bits {
4074 u8 status[0x8];
b4ff3a36 4075 u8 reserved_at_8[0x18];
e281682b
SM		 4076
4077 u8 syndrome[0x20];
4078
b4ff3a36 4079 u8 reserved_at_40[0x40];
e281682b
SM		 4080
4081 u8 rx_write_requests[0x20];
4082
b4ff3a36 4083 u8 reserved_at_a0[0x20];
e281682b
SM		 4084
4085 u8 rx_read_requests[0x20];
4086
b4ff3a36 4087 u8 reserved_at_e0[0x20];
e281682b
SM		 4088
4089 u8 rx_atomic_requests[0x20];
4090
b4ff3a36 4091 u8 reserved_at_120[0x20];
e281682b
SM		 4092
4093 u8 rx_dct_connect[0x20];
4094
b4ff3a36 4095 u8 reserved_at_160[0x20];
e281682b
SM		 4096
4097 u8 out_of_buffer[0x20];
4098
b4ff3a36 4099 u8 reserved_at_1a0[0x20];
e281682b
SM		 4100
4101 u8 out_of_sequence[0x20];
4102
7486216b
SM		 4103 u8 reserved_at_1e0[0x20];
4104
4105 u8 duplicate_request[0x20];
4106
4107 u8 reserved_at_220[0x20];
4108
4109 u8 rnr_nak_retry_err[0x20];
4110
4111 u8 reserved_at_260[0x20];
4112
4113 u8 packet_seq_err[0x20];
4114
4115 u8 reserved_at_2a0[0x20];
4116
4117 u8 implied_nak_seq_err[0x20];
4118
4119 u8 reserved_at_2e0[0x20];
4120
4121 u8 local_ack_timeout_err[0x20];
4122
58dcb60a
PP		 4123 u8 reserved_at_320[0xa0];
4124
4125 u8 resp_local_length_error[0x20];
4126
4127 u8 req_local_length_error[0x20];
4128
4129 u8 resp_local_qp_error[0x20];
4130
4131 u8 local_operation_error[0x20];
4132
4133 u8 resp_local_protection[0x20];
4134
4135 u8 req_local_protection[0x20];
4136
4137 u8 resp_cqe_error[0x20];
4138
4139 u8 req_cqe_error[0x20];
4140
4141 u8 req_mw_binding[0x20];
4142
4143 u8 req_bad_response[0x20];
4144
4145 u8 req_remote_invalid_request[0x20];
4146
4147 u8 resp_remote_invalid_request[0x20];
4148
4149 u8 req_remote_access_errors[0x20];
4150
4151 u8 resp_remote_access_errors[0x20];
4152
4153 u8 req_remote_operation_errors[0x20];
4154
4155 u8 req_transport_retries_exceeded[0x20];
4156
4157 u8 cq_overflow[0x20];
4158
4159 u8 resp_cqe_flush_error[0x20];
4160
4161 u8 req_cqe_flush_error[0x20];
4162
4163 u8 reserved_at_620[0x1e0];
e281682b
SM		 4164};
4165
4166struct mlx5_ifc_query_q_counter_in_bits {
4167 u8 opcode[0x10];
b4ff3a36 4168 u8 reserved_at_10[0x10];
e281682b 4169
b4ff3a36 4170 u8 reserved_at_20[0x10];
e281682b
SM		 4171 u8 op_mod[0x10];
4172
b4ff3a36 4173 u8 reserved_at_40[0x80];
e281682b
SM		 4174
4175 u8 clear[0x1];
b4ff3a36 4176 u8 reserved_at_c1[0x1f];
e281682b 4177
b4ff3a36 4178 u8 reserved_at_e0[0x18];
e281682b
SM		 4179 u8 counter_set_id[0x8];
4180};
4181
4182struct mlx5_ifc_query_pages_out_bits {
4183 u8 status[0x8];
b4ff3a36 4184 u8 reserved_at_8[0x18];
e281682b
SM		 4185
4186 u8 syndrome[0x20];
4187
b4ff3a36 4188 u8 reserved_at_40[0x10];
e281682b
SM		 4189 u8 function_id[0x10];
4190
4191 u8 num_pages[0x20];
4192};
4193
4194enum {
4195 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4196 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4197 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4198};
4199
4200struct mlx5_ifc_query_pages_in_bits {
4201 u8 opcode[0x10];
b4ff3a36 4202 u8 reserved_at_10[0x10];
e281682b 4203
b4ff3a36 4204 u8 reserved_at_20[0x10];
e281682b
SM		 4205 u8 op_mod[0x10];
4206
b4ff3a36 4207 u8 reserved_at_40[0x10];
e281682b
SM		 4208 u8 function_id[0x10];
4209
b4ff3a36 4210 u8 reserved_at_60[0x20];
e281682b
SM		 4211};
4212
4213struct mlx5_ifc_query_nic_vport_context_out_bits {
4214 u8 status[0x8];
b4ff3a36 4215 u8 reserved_at_8[0x18];
e281682b
SM		 4216
4217 u8 syndrome[0x20];
4218
b4ff3a36 4219 u8 reserved_at_40[0x40];
e281682b
SM		 4220
4221 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4222};
4223
4224struct mlx5_ifc_query_nic_vport_context_in_bits {
4225 u8 opcode[0x10];
b4ff3a36 4226 u8 reserved_at_10[0x10];
e281682b 4227
b4ff3a36 4228 u8 reserved_at_20[0x10];
e281682b
SM		 4229 u8 op_mod[0x10];
4230
4231 u8 other_vport[0x1];
b4ff3a36 4232 u8 reserved_at_41[0xf];
e281682b
SM		 4233 u8 vport_number[0x10];
4234
b4ff3a36 4235 u8 reserved_at_60[0x5];
e281682b 4236 u8 allowed_list_type[0x3];
b4ff3a36 4237 u8 reserved_at_68[0x18];
e281682b
SM		 4238};
4239
4240struct mlx5_ifc_query_mkey_out_bits {
4241 u8 status[0x8];
b4ff3a36 4242 u8 reserved_at_8[0x18];
e281682b
SM		 4243
4244 u8 syndrome[0x20];
4245
b4ff3a36 4246 u8 reserved_at_40[0x40];
e281682b
SM		 4247
4248 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4249
b4ff3a36 4250 u8 reserved_at_280[0x600];
e281682b
SM		 4251
4252 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4253
4254 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4255};
4256
4257struct mlx5_ifc_query_mkey_in_bits {
4258 u8 opcode[0x10];
b4ff3a36 4259 u8 reserved_at_10[0x10];
e281682b 4260
b4ff3a36 4261 u8 reserved_at_20[0x10];
e281682b
SM		 4262 u8 op_mod[0x10];
4263
b4ff3a36 4264 u8 reserved_at_40[0x8];
e281682b
SM		 4265 u8 mkey_index[0x18];
4266
4267 u8 pg_access[0x1];
b4ff3a36 4268 u8 reserved_at_61[0x1f];
e281682b
SM		 4269};
4270
4271struct mlx5_ifc_query_mad_demux_out_bits {
4272 u8 status[0x8];
b4ff3a36 4273 u8 reserved_at_8[0x18];
e281682b
SM		 4274
4275 u8 syndrome[0x20];
4276
b4ff3a36 4277 u8 reserved_at_40[0x40];
e281682b
SM		 4278
4279 u8 mad_dumux_parameters_block[0x20];
4280};
4281
4282struct mlx5_ifc_query_mad_demux_in_bits {
4283 u8 opcode[0x10];
b4ff3a36 4284 u8 reserved_at_10[0x10];
e281682b 4285
b4ff3a36 4286 u8 reserved_at_20[0x10];
e281682b
SM		 4287 u8 op_mod[0x10];
4288
b4ff3a36 4289 u8 reserved_at_40[0x40];
e281682b
SM		 4290};
4291
4292struct mlx5_ifc_query_l2_table_entry_out_bits {
4293 u8 status[0x8];
b4ff3a36 4294 u8 reserved_at_8[0x18];
e281682b
SM		 4295
4296 u8 syndrome[0x20];
4297
b4ff3a36 4298 u8 reserved_at_40[0xa0];
e281682b 4299
b4ff3a36 4300 u8 reserved_at_e0[0x13];
e281682b
SM		 4301 u8 vlan_valid[0x1];
4302 u8 vlan[0xc];
4303
4304 struct mlx5_ifc_mac_address_layout_bits mac_address;
4305
b4ff3a36 4306 u8 reserved_at_140[0xc0];
e281682b
SM		 4307};
4308
4309struct mlx5_ifc_query_l2_table_entry_in_bits {
4310 u8 opcode[0x10];
b4ff3a36 4311 u8 reserved_at_10[0x10];
e281682b 4312
b4ff3a36 4313 u8 reserved_at_20[0x10];
e281682b
SM		 4314 u8 op_mod[0x10];
4315
b4ff3a36 4316 u8 reserved_at_40[0x60];
e281682b 4317
b4ff3a36 4318 u8 reserved_at_a0[0x8];
e281682b
SM		 4319 u8 table_index[0x18];
4320
b4ff3a36 4321 u8 reserved_at_c0[0x140];
e281682b
SM		 4322};
4323
4324struct mlx5_ifc_query_issi_out_bits {
4325 u8 status[0x8];
b4ff3a36 4326 u8 reserved_at_8[0x18];
e281682b
SM		 4327
4328 u8 syndrome[0x20];
4329
b4ff3a36 4330 u8 reserved_at_40[0x10];
e281682b
SM		 4331 u8 current_issi[0x10];
4332
b4ff3a36 4333 u8 reserved_at_60[0xa0];
e281682b 4334
b4ff3a36 4335 u8 reserved_at_100[76][0x8];
e281682b
SM		 4336 u8 supported_issi_dw0[0x20];
4337};
4338
4339struct mlx5_ifc_query_issi_in_bits {
4340 u8 opcode[0x10];
b4ff3a36 4341 u8 reserved_at_10[0x10];
e281682b 4342
b4ff3a36 4343 u8 reserved_at_20[0x10];
e281682b
SM		 4344 u8 op_mod[0x10];
4345
b4ff3a36 4346 u8 reserved_at_40[0x40];
e281682b
SM		 4347};
4348
0dbc6fe0
SM		 4349struct mlx5_ifc_set_driver_version_out_bits {
4350 u8 status[0x8];
4351 u8 reserved_0[0x18];
4352
4353 u8 syndrome[0x20];
4354 u8 reserved_1[0x40];
4355};
4356
4357struct mlx5_ifc_set_driver_version_in_bits {
4358 u8 opcode[0x10];
4359 u8 reserved_0[0x10];
4360
4361 u8 reserved_1[0x10];
4362 u8 op_mod[0x10];
4363
4364 u8 reserved_2[0x40];
4365 u8 driver_version[64][0x8];
4366};
4367
e281682b
SM		 4368struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4369 u8 status[0x8];
b4ff3a36 4370 u8 reserved_at_8[0x18];
e281682b
SM		 4371
4372 u8 syndrome[0x20];
4373
b4ff3a36 4374 u8 reserved_at_40[0x40];
e281682b
SM		 4375
4376 struct mlx5_ifc_pkey_bits pkey[0];
4377};
4378
4379struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4380 u8 opcode[0x10];
b4ff3a36 4381 u8 reserved_at_10[0x10];
e281682b 4382
b4ff3a36 4383 u8 reserved_at_20[0x10];
e281682b
SM		 4384 u8 op_mod[0x10];
4385
4386 u8 other_vport[0x1];
b4ff3a36 4387 u8 reserved_at_41[0xb];
707c4602 4388 u8 port_num[0x4];
e281682b
SM		 4389 u8 vport_number[0x10];
4390
b4ff3a36 4391 u8 reserved_at_60[0x10];
e281682b
SM		 4392 u8 pkey_index[0x10];
4393};
4394
eff901d3
EC		 4395enum {
4396 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4397 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4398 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4399};
4400
e281682b
SM		 4401struct mlx5_ifc_query_hca_vport_gid_out_bits {
4402 u8 status[0x8];
b4ff3a36 4403 u8 reserved_at_8[0x18];
e281682b
SM		 4404
4405 u8 syndrome[0x20];
4406
b4ff3a36 4407 u8 reserved_at_40[0x20];
e281682b
SM		 4408
4409 u8 gids_num[0x10];
b4ff3a36 4410 u8 reserved_at_70[0x10];
e281682b
SM		 4411
4412 struct mlx5_ifc_array128_auto_bits gid[0];
4413};
4414
4415struct mlx5_ifc_query_hca_vport_gid_in_bits {
4416 u8 opcode[0x10];
b4ff3a36 4417 u8 reserved_at_10[0x10];
e281682b 4418
b4ff3a36 4419 u8 reserved_at_20[0x10];
e281682b
SM		 4420 u8 op_mod[0x10];
4421
4422 u8 other_vport[0x1];
b4ff3a36 4423 u8 reserved_at_41[0xb];
707c4602 4424 u8 port_num[0x4];
e281682b
SM		 4425 u8 vport_number[0x10];
4426
b4ff3a36 4427 u8 reserved_at_60[0x10];
e281682b
SM		 4428 u8 gid_index[0x10];
4429};
4430
4431struct mlx5_ifc_query_hca_vport_context_out_bits {
4432 u8 status[0x8];
b4ff3a36 4433 u8 reserved_at_8[0x18];
e281682b
SM		 4434
4435 u8 syndrome[0x20];
4436
b4ff3a36 4437 u8 reserved_at_40[0x40];
e281682b
SM		 4438
4439 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4440};
4441
4442struct mlx5_ifc_query_hca_vport_context_in_bits {
4443 u8 opcode[0x10];
b4ff3a36 4444 u8 reserved_at_10[0x10];
e281682b 4445
b4ff3a36 4446 u8 reserved_at_20[0x10];
e281682b
SM		 4447 u8 op_mod[0x10];
4448
4449 u8 other_vport[0x1];
b4ff3a36 4450 u8 reserved_at_41[0xb];
707c4602 4451 u8 port_num[0x4];
e281682b
SM		 4452 u8 vport_number[0x10];
4453
b4ff3a36 4454 u8 reserved_at_60[0x20];
e281682b
SM		 4455};
4456
4457struct mlx5_ifc_query_hca_cap_out_bits {
4458 u8 status[0x8];
b4ff3a36 4459 u8 reserved_at_8[0x18];
e281682b
SM		 4460
4461 u8 syndrome[0x20];
4462
b4ff3a36 4463 u8 reserved_at_40[0x40];
e281682b
SM		 4464
4465 union mlx5_ifc_hca_cap_union_bits capability;
4466};
4467
4468struct mlx5_ifc_query_hca_cap_in_bits {
4469 u8 opcode[0x10];
b4ff3a36 4470 u8 reserved_at_10[0x10];
e281682b 4471
b4ff3a36 4472 u8 reserved_at_20[0x10];
e281682b
SM		 4473 u8 op_mod[0x10];
4474
b4ff3a36 4475 u8 reserved_at_40[0x40];
e281682b
SM		 4476};
4477
4478struct mlx5_ifc_query_flow_table_out_bits {
4479 u8 status[0x8];
b4ff3a36 4480 u8 reserved_at_8[0x18];
e281682b
SM		 4481
4482 u8 syndrome[0x20];
4483
b4ff3a36 4484 u8 reserved_at_40[0x80];
e281682b 4485
b4ff3a36 4486 u8 reserved_at_c0[0x8];
e281682b 4487 u8 level[0x8];
b4ff3a36 4488 u8 reserved_at_d0[0x8];
e281682b
SM		 4489 u8 log_size[0x8];
4490
b4ff3a36 4491 u8 reserved_at_e0[0x120];
e281682b
SM		 4492};
4493
4494struct mlx5_ifc_query_flow_table_in_bits {
4495 u8 opcode[0x10];
b4ff3a36 4496 u8 reserved_at_10[0x10];
e281682b 4497
b4ff3a36 4498 u8 reserved_at_20[0x10];
e281682b
SM		 4499 u8 op_mod[0x10];
4500
b4ff3a36 4501 u8 reserved_at_40[0x40];
e281682b
SM		 4502
4503 u8 table_type[0x8];
b4ff3a36 4504 u8 reserved_at_88[0x18];
e281682b 4505
b4ff3a36 4506 u8 reserved_at_a0[0x8];
e281682b
SM		 4507 u8 table_id[0x18];
4508
b4ff3a36 4509 u8 reserved_at_c0[0x140];
e281682b
SM		 4510};
4511
4512struct mlx5_ifc_query_fte_out_bits {
4513 u8 status[0x8];
b4ff3a36 4514 u8 reserved_at_8[0x18];
e281682b
SM		 4515
4516 u8 syndrome[0x20];
4517
b4ff3a36 4518 u8 reserved_at_40[0x1c0];
e281682b
SM		 4519
4520 struct mlx5_ifc_flow_context_bits flow_context;
4521};
4522
4523struct mlx5_ifc_query_fte_in_bits {
4524 u8 opcode[0x10];
b4ff3a36 4525 u8 reserved_at_10[0x10];
e281682b 4526
b4ff3a36 4527 u8 reserved_at_20[0x10];
e281682b
SM		 4528 u8 op_mod[0x10];
4529
b4ff3a36 4530 u8 reserved_at_40[0x40];
e281682b
SM		 4531
4532 u8 table_type[0x8];
b4ff3a36 4533 u8 reserved_at_88[0x18];
e281682b 4534
b4ff3a36 4535 u8 reserved_at_a0[0x8];
e281682b
SM		 4536 u8 table_id[0x18];
4537
b4ff3a36 4538 u8 reserved_at_c0[0x40];
e281682b
SM		 4539
4540 u8 flow_index[0x20];
4541
b4ff3a36 4542 u8 reserved_at_120[0xe0];
e281682b
SM		 4543};
4544
4545enum {
4546 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4547 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4548 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4549};
4550
4551struct mlx5_ifc_query_flow_group_out_bits {
4552 u8 status[0x8];
b4ff3a36 4553 u8 reserved_at_8[0x18];
e281682b
SM		 4554
4555 u8 syndrome[0x20];
4556
b4ff3a36 4557 u8 reserved_at_40[0xa0];
e281682b
SM		 4558
4559 u8 start_flow_index[0x20];
4560
b4ff3a36 4561 u8 reserved_at_100[0x20];
e281682b
SM		 4562
4563 u8 end_flow_index[0x20];
4564
b4ff3a36 4565 u8 reserved_at_140[0xa0];
e281682b 4566
b4ff3a36 4567 u8 reserved_at_1e0[0x18];
e281682b
SM		 4568 u8 match_criteria_enable[0x8];
4569
4570 struct mlx5_ifc_fte_match_param_bits match_criteria;
4571
b4ff3a36 4572 u8 reserved_at_1200[0xe00];
e281682b
SM		 4573};
4574
4575struct mlx5_ifc_query_flow_group_in_bits {
4576 u8 opcode[0x10];
b4ff3a36 4577 u8 reserved_at_10[0x10];
e281682b 4578
b4ff3a36 4579 u8 reserved_at_20[0x10];
e281682b
SM		 4580 u8 op_mod[0x10];
4581
b4ff3a36 4582 u8 reserved_at_40[0x40];
e281682b
SM		 4583
4584 u8 table_type[0x8];
b4ff3a36 4585 u8 reserved_at_88[0x18];
e281682b 4586
b4ff3a36 4587 u8 reserved_at_a0[0x8];
e281682b
SM		 4588 u8 table_id[0x18];
4589
4590 u8 group_id[0x20];
4591
b4ff3a36 4592 u8 reserved_at_e0[0x120];
e281682b
SM		 4593};
4594
9dc0b289
AV		 4595struct mlx5_ifc_query_flow_counter_out_bits {
4596 u8 status[0x8];
4597 u8 reserved_at_8[0x18];
4598
4599 u8 syndrome[0x20];
4600
4601 u8 reserved_at_40[0x40];
4602
4603 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4604};
4605
4606struct mlx5_ifc_query_flow_counter_in_bits {
4607 u8 opcode[0x10];
4608 u8 reserved_at_10[0x10];
4609
4610 u8 reserved_at_20[0x10];
4611 u8 op_mod[0x10];
4612
4613 u8 reserved_at_40[0x80];
4614
4615 u8 clear[0x1];
4616 u8 reserved_at_c1[0xf];
4617 u8 num_of_counters[0x10];
4618
a8ffcc74 4619 u8 flow_counter_id[0x20];
9dc0b289
AV		 4620};
4621
d6666753
SM		 4622struct mlx5_ifc_query_esw_vport_context_out_bits {
4623 u8 status[0x8];
b4ff3a36 4624 u8 reserved_at_8[0x18];
d6666753
SM		 4625
4626 u8 syndrome[0x20];
4627
b4ff3a36 4628 u8 reserved_at_40[0x40];
d6666753
SM		 4629
4630 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4631};
4632
4633struct mlx5_ifc_query_esw_vport_context_in_bits {
4634 u8 opcode[0x10];
b4ff3a36 4635 u8 reserved_at_10[0x10];
d6666753 4636
b4ff3a36 4637 u8 reserved_at_20[0x10];
d6666753
SM		 4638 u8 op_mod[0x10];
4639
4640 u8 other_vport[0x1];
b4ff3a36 4641 u8 reserved_at_41[0xf];
d6666753
SM		 4642 u8 vport_number[0x10];
4643
b4ff3a36 4644 u8 reserved_at_60[0x20];
d6666753
SM		 4645};
4646
4647struct mlx5_ifc_modify_esw_vport_context_out_bits {
4648 u8 status[0x8];
b4ff3a36 4649 u8 reserved_at_8[0x18];
d6666753
SM		 4650
4651 u8 syndrome[0x20];
4652
b4ff3a36 4653 u8 reserved_at_40[0x40];
d6666753
SM		 4654};
4655
4656struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4657 u8 reserved_at_0[0x1c];
d6666753
SM		 4658 u8 vport_cvlan_insert[0x1];
4659 u8 vport_svlan_insert[0x1];
4660 u8 vport_cvlan_strip[0x1];
4661 u8 vport_svlan_strip[0x1];
4662};
4663
4664struct mlx5_ifc_modify_esw_vport_context_in_bits {
4665 u8 opcode[0x10];
b4ff3a36 4666 u8 reserved_at_10[0x10];
d6666753 4667
b4ff3a36 4668 u8 reserved_at_20[0x10];
d6666753
SM		 4669 u8 op_mod[0x10];
4670
4671 u8 other_vport[0x1];
b4ff3a36 4672 u8 reserved_at_41[0xf];
d6666753
SM		 4673 u8 vport_number[0x10];
4674
4675 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4676
4677 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4678};
4679
e281682b
SM		 4680struct mlx5_ifc_query_eq_out_bits {
4681 u8 status[0x8];
b4ff3a36 4682 u8 reserved_at_8[0x18];
e281682b
SM		 4683
4684 u8 syndrome[0x20];
4685
b4ff3a36 4686 u8 reserved_at_40[0x40];
e281682b
SM		 4687
4688 struct mlx5_ifc_eqc_bits eq_context_entry;
4689
b4ff3a36 4690 u8 reserved_at_280[0x40];
e281682b
SM		 4691
4692 u8 event_bitmask[0x40];
4693
b4ff3a36 4694 u8 reserved_at_300[0x580];
e281682b
SM		 4695
4696 u8 pas[0][0x40];
4697};
4698
4699struct mlx5_ifc_query_eq_in_bits {
4700 u8 opcode[0x10];
b4ff3a36 4701 u8 reserved_at_10[0x10];
e281682b 4702
b4ff3a36 4703 u8 reserved_at_20[0x10];
e281682b
SM		 4704 u8 op_mod[0x10];
4705
b4ff3a36 4706 u8 reserved_at_40[0x18];
e281682b
SM		 4707 u8 eq_number[0x8];
4708
b4ff3a36 4709 u8 reserved_at_60[0x20];
e281682b
SM		 4710};
4711
7adbde20
HHZ		 4712struct mlx5_ifc_encap_header_in_bits {
4713 u8 reserved_at_0[0x5];
4714 u8 header_type[0x3];
4715 u8 reserved_at_8[0xe];
4716 u8 encap_header_size[0xa];
4717
4718 u8 reserved_at_20[0x10];
4719 u8 encap_header[2][0x8];
4720
4721 u8 more_encap_header[0][0x8];
4722};
4723
4724struct mlx5_ifc_query_encap_header_out_bits {
4725 u8 status[0x8];
4726 u8 reserved_at_8[0x18];
4727
4728 u8 syndrome[0x20];
4729
4730 u8 reserved_at_40[0xa0];
4731
4732 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4733};
4734
4735struct mlx5_ifc_query_encap_header_in_bits {
4736 u8 opcode[0x10];
4737 u8 reserved_at_10[0x10];
4738
4739 u8 reserved_at_20[0x10];
4740 u8 op_mod[0x10];
4741
4742 u8 encap_id[0x20];
4743
4744 u8 reserved_at_60[0xa0];
4745};
4746
4747struct mlx5_ifc_alloc_encap_header_out_bits {
4748 u8 status[0x8];
4749 u8 reserved_at_8[0x18];
4750
4751 u8 syndrome[0x20];
4752
4753 u8 encap_id[0x20];
4754
4755 u8 reserved_at_60[0x20];
4756};
4757
4758struct mlx5_ifc_alloc_encap_header_in_bits {
4759 u8 opcode[0x10];
4760 u8 reserved_at_10[0x10];
4761
4762 u8 reserved_at_20[0x10];
4763 u8 op_mod[0x10];
4764
4765 u8 reserved_at_40[0xa0];
4766
4767 struct mlx5_ifc_encap_header_in_bits encap_header;
4768};
4769
4770struct mlx5_ifc_dealloc_encap_header_out_bits {
4771 u8 status[0x8];
4772 u8 reserved_at_8[0x18];
4773
4774 u8 syndrome[0x20];
4775
4776 u8 reserved_at_40[0x40];
4777};
4778
4779struct mlx5_ifc_dealloc_encap_header_in_bits {
4780 u8 opcode[0x10];
4781 u8 reserved_at_10[0x10];
4782
4783 u8 reserved_20[0x10];
4784 u8 op_mod[0x10];
4785
4786 u8 encap_id[0x20];
4787
4788 u8 reserved_60[0x20];
4789};
4790
2a69cb9f
OG		 4791struct mlx5_ifc_set_action_in_bits {
4792 u8 action_type[0x4];
4793 u8 field[0xc];
4794 u8 reserved_at_10[0x3];
4795 u8 offset[0x5];
4796 u8 reserved_at_18[0x3];
4797 u8 length[0x5];
4798
4799 u8 data[0x20];
4800};
4801
4802struct mlx5_ifc_add_action_in_bits {
4803 u8 action_type[0x4];
4804 u8 field[0xc];
4805 u8 reserved_at_10[0x10];
4806
4807 u8 data[0x20];
4808};
4809
4810union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4811 struct mlx5_ifc_set_action_in_bits set_action_in;
4812 struct mlx5_ifc_add_action_in_bits add_action_in;
4813 u8 reserved_at_0[0x40];
4814};
4815
4816enum {
4817 MLX5_ACTION_TYPE_SET = 0x1,
4818 MLX5_ACTION_TYPE_ADD = 0x2,
4819};
4820
4821enum {
4822 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4823 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4824 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4825 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4826 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4827 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4828 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4829 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4830 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4831 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4832 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4833 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4834 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4835 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4836 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4837 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4838 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4839 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4840 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4841 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4842 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4843 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4844 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4845};
4846
4847struct mlx5_ifc_alloc_modify_header_context_out_bits {
4848 u8 status[0x8];
4849 u8 reserved_at_8[0x18];
4850
4851 u8 syndrome[0x20];
4852
4853 u8 modify_header_id[0x20];
4854
4855 u8 reserved_at_60[0x20];
4856};
4857
4858struct mlx5_ifc_alloc_modify_header_context_in_bits {
4859 u8 opcode[0x10];
4860 u8 reserved_at_10[0x10];
4861
4862 u8 reserved_at_20[0x10];
4863 u8 op_mod[0x10];
4864
4865 u8 reserved_at_40[0x20];
4866
4867 u8 table_type[0x8];
4868 u8 reserved_at_68[0x10];
4869 u8 num_of_actions[0x8];
4870
4871 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4872};
4873
4874struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4875 u8 status[0x8];
4876 u8 reserved_at_8[0x18];
4877
4878 u8 syndrome[0x20];
4879
4880 u8 reserved_at_40[0x40];
4881};
4882
4883struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4884 u8 opcode[0x10];
4885 u8 reserved_at_10[0x10];
4886
4887 u8 reserved_at_20[0x10];
4888 u8 op_mod[0x10];
4889
4890 u8 modify_header_id[0x20];
4891
4892 u8 reserved_at_60[0x20];
4893};
4894
e281682b
SM		 4895struct mlx5_ifc_query_dct_out_bits {
4896 u8 status[0x8];
b4ff3a36 4897 u8 reserved_at_8[0x18];
e281682b
SM		 4898
4899 u8 syndrome[0x20];
4900
b4ff3a36 4901 u8 reserved_at_40[0x40];
e281682b
SM		 4902
4903 struct mlx5_ifc_dctc_bits dct_context_entry;
4904
b4ff3a36 4905 u8 reserved_at_280[0x180];
e281682b
SM		 4906};
4907
4908struct mlx5_ifc_query_dct_in_bits {
4909 u8 opcode[0x10];
b4ff3a36 4910 u8 reserved_at_10[0x10];
e281682b 4911
b4ff3a36 4912 u8 reserved_at_20[0x10];
e281682b
SM		 4913 u8 op_mod[0x10];
4914
b4ff3a36 4915 u8 reserved_at_40[0x8];
e281682b
SM		 4916 u8 dctn[0x18];
4917
b4ff3a36 4918 u8 reserved_at_60[0x20];
e281682b
SM		 4919};
4920
4921struct mlx5_ifc_query_cq_out_bits {
4922 u8 status[0x8];
b4ff3a36 4923 u8 reserved_at_8[0x18];
e281682b
SM		 4924
4925 u8 syndrome[0x20];
4926
b4ff3a36 4927 u8 reserved_at_40[0x40];
e281682b
SM		 4928
4929 struct mlx5_ifc_cqc_bits cq_context;
4930
b4ff3a36 4931 u8 reserved_at_280[0x600];
e281682b
SM		 4932
4933 u8 pas[0][0x40];
4934};
4935
4936struct mlx5_ifc_query_cq_in_bits {
4937 u8 opcode[0x10];
b4ff3a36 4938 u8 reserved_at_10[0x10];
e281682b 4939
b4ff3a36 4940 u8 reserved_at_20[0x10];
e281682b
SM		 4941 u8 op_mod[0x10];
4942
b4ff3a36 4943 u8 reserved_at_40[0x8];
e281682b
SM		 4944 u8 cqn[0x18];
4945
b4ff3a36 4946 u8 reserved_at_60[0x20];
e281682b
SM		 4947};
4948
4949struct mlx5_ifc_query_cong_status_out_bits {
4950 u8 status[0x8];
b4ff3a36 4951 u8 reserved_at_8[0x18];
e281682b
SM		 4952
4953 u8 syndrome[0x20];
4954
b4ff3a36 4955 u8 reserved_at_40[0x20];
e281682b
SM		 4956
4957 u8 enable[0x1];
4958 u8 tag_enable[0x1];
b4ff3a36 4959 u8 reserved_at_62[0x1e];
e281682b
SM		 4960};
4961
4962struct mlx5_ifc_query_cong_status_in_bits {
4963 u8 opcode[0x10];
b4ff3a36 4964 u8 reserved_at_10[0x10];
e281682b 4965
b4ff3a36 4966 u8 reserved_at_20[0x10];
e281682b
SM		 4967 u8 op_mod[0x10];
4968
b4ff3a36 4969 u8 reserved_at_40[0x18];
e281682b
SM		 4970 u8 priority[0x4];
4971 u8 cong_protocol[0x4];
4972
b4ff3a36 4973 u8 reserved_at_60[0x20];
e281682b
SM		 4974};
4975
4976struct mlx5_ifc_query_cong_statistics_out_bits {
4977 u8 status[0x8];
b4ff3a36 4978 u8 reserved_at_8[0x18];
e281682b
SM		 4979
4980 u8 syndrome[0x20];
4981
b4ff3a36 4982 u8 reserved_at_40[0x40];
e281682b 4983
e1f24a79 4984 u8 rp_cur_flows[0x20];
e281682b
SM		 4985
4986 u8 sum_flows[0x20];
4987
e1f24a79 4988 u8 rp_cnp_ignored_high[0x20];
e281682b 4989
e1f24a79 4990 u8 rp_cnp_ignored_low[0x20];
e281682b 4991
e1f24a79 4992 u8 rp_cnp_handled_high[0x20];
e281682b 4993
e1f24a79 4994 u8 rp_cnp_handled_low[0x20];
e281682b 4995
b4ff3a36 4996 u8 reserved_at_140[0x100];
e281682b
SM		 4997
4998 u8 time_stamp_high[0x20];
4999
5000 u8 time_stamp_low[0x20];
5001
5002 u8 accumulators_period[0x20];
5003
e1f24a79 5004 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5005
e1f24a79 5006 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5007
e1f24a79 5008 u8 np_cnp_sent_high[0x20];
e281682b 5009
e1f24a79 5010 u8 np_cnp_sent_low[0x20];
e281682b 5011
b4ff3a36 5012 u8 reserved_at_320[0x560];
e281682b
SM		 5013};
5014
5015struct mlx5_ifc_query_cong_statistics_in_bits {
5016 u8 opcode[0x10];
b4ff3a36 5017 u8 reserved_at_10[0x10];
e281682b 5018
b4ff3a36 5019 u8 reserved_at_20[0x10];
e281682b
SM		 5020 u8 op_mod[0x10];
5021
5022 u8 clear[0x1];
b4ff3a36 5023 u8 reserved_at_41[0x1f];
e281682b 5024
b4ff3a36 5025 u8 reserved_at_60[0x20];
e281682b
SM		 5026};
5027
5028struct mlx5_ifc_query_cong_params_out_bits {
5029 u8 status[0x8];
b4ff3a36 5030 u8 reserved_at_8[0x18];
e281682b
SM		 5031
5032 u8 syndrome[0x20];
5033
b4ff3a36 5034 u8 reserved_at_40[0x40];
e281682b
SM		 5035
5036 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5037};
5038
5039struct mlx5_ifc_query_cong_params_in_bits {
5040 u8 opcode[0x10];
b4ff3a36 5041 u8 reserved_at_10[0x10];
e281682b 5042
b4ff3a36 5043 u8 reserved_at_20[0x10];
e281682b
SM		 5044 u8 op_mod[0x10];
5045
b4ff3a36 5046 u8 reserved_at_40[0x1c];
e281682b
SM		 5047 u8 cong_protocol[0x4];
5048
b4ff3a36 5049 u8 reserved_at_60[0x20];
e281682b
SM		 5050};
5051
5052struct mlx5_ifc_query_adapter_out_bits {
5053 u8 status[0x8];
b4ff3a36 5054 u8 reserved_at_8[0x18];
e281682b
SM		 5055
5056 u8 syndrome[0x20];
5057
b4ff3a36 5058 u8 reserved_at_40[0x40];
e281682b
SM		 5059
5060 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5061};
5062
5063struct mlx5_ifc_query_adapter_in_bits {
5064 u8 opcode[0x10];
b4ff3a36 5065 u8 reserved_at_10[0x10];
e281682b 5066
b4ff3a36 5067 u8 reserved_at_20[0x10];
e281682b
SM		 5068 u8 op_mod[0x10];
5069
b4ff3a36 5070 u8 reserved_at_40[0x40];
e281682b
SM		 5071};
5072
5073struct mlx5_ifc_qp_2rst_out_bits {
5074 u8 status[0x8];
b4ff3a36 5075 u8 reserved_at_8[0x18];
e281682b
SM		 5076
5077 u8 syndrome[0x20];
5078
b4ff3a36 5079 u8 reserved_at_40[0x40];
e281682b
SM		 5080};
5081
5082struct mlx5_ifc_qp_2rst_in_bits {
5083 u8 opcode[0x10];
b4ff3a36 5084 u8 reserved_at_10[0x10];
e281682b 5085
b4ff3a36 5086 u8 reserved_at_20[0x10];
e281682b
SM		 5087 u8 op_mod[0x10];
5088
b4ff3a36 5089 u8 reserved_at_40[0x8];
e281682b
SM		 5090 u8 qpn[0x18];
5091
b4ff3a36 5092 u8 reserved_at_60[0x20];
e281682b
SM		 5093};
5094
5095struct mlx5_ifc_qp_2err_out_bits {
5096 u8 status[0x8];
b4ff3a36 5097 u8 reserved_at_8[0x18];
e281682b
SM		 5098
5099 u8 syndrome[0x20];
5100
b4ff3a36 5101 u8 reserved_at_40[0x40];
e281682b
SM		 5102};
5103
5104struct mlx5_ifc_qp_2err_in_bits {
5105 u8 opcode[0x10];
b4ff3a36 5106 u8 reserved_at_10[0x10];
e281682b 5107
b4ff3a36 5108 u8 reserved_at_20[0x10];
e281682b
SM		 5109 u8 op_mod[0x10];
5110
b4ff3a36 5111 u8 reserved_at_40[0x8];
e281682b
SM		 5112 u8 qpn[0x18];
5113
b4ff3a36 5114 u8 reserved_at_60[0x20];
e281682b
SM		 5115};
5116
5117struct mlx5_ifc_page_fault_resume_out_bits {
5118 u8 status[0x8];
b4ff3a36 5119 u8 reserved_at_8[0x18];
e281682b
SM		 5120
5121 u8 syndrome[0x20];
5122
b4ff3a36 5123 u8 reserved_at_40[0x40];
e281682b
SM		 5124};
5125
5126struct mlx5_ifc_page_fault_resume_in_bits {
5127 u8 opcode[0x10];
b4ff3a36 5128 u8 reserved_at_10[0x10];
e281682b 5129
b4ff3a36 5130 u8 reserved_at_20[0x10];
e281682b
SM		 5131 u8 op_mod[0x10];
5132
5133 u8 error[0x1];
b4ff3a36 5134 u8 reserved_at_41[0x4];
223cdc72
AK		 5135 u8 page_fault_type[0x3];
5136 u8 wq_number[0x18];
e281682b 5137
223cdc72
AK		 5138 u8 reserved_at_60[0x8];
5139 u8 token[0x18];
e281682b
SM		 5140};
5141
5142struct mlx5_ifc_nop_out_bits {
5143 u8 status[0x8];
b4ff3a36 5144 u8 reserved_at_8[0x18];
e281682b
SM		 5145
5146 u8 syndrome[0x20];
5147
b4ff3a36 5148 u8 reserved_at_40[0x40];
e281682b
SM		 5149};
5150
5151struct mlx5_ifc_nop_in_bits {
5152 u8 opcode[0x10];
b4ff3a36 5153 u8 reserved_at_10[0x10];
e281682b 5154
b4ff3a36 5155 u8 reserved_at_20[0x10];
e281682b
SM		 5156 u8 op_mod[0x10];
5157
b4ff3a36 5158 u8 reserved_at_40[0x40];
e281682b
SM		 5159};
5160
5161struct mlx5_ifc_modify_vport_state_out_bits {
5162 u8 status[0x8];
b4ff3a36 5163 u8 reserved_at_8[0x18];
e281682b
SM		 5164
5165 u8 syndrome[0x20];
5166
b4ff3a36 5167 u8 reserved_at_40[0x40];
e281682b
SM		 5168};
5169
5170struct mlx5_ifc_modify_vport_state_in_bits {
5171 u8 opcode[0x10];
b4ff3a36 5172 u8 reserved_at_10[0x10];
e281682b 5173
b4ff3a36 5174 u8 reserved_at_20[0x10];
e281682b
SM		 5175 u8 op_mod[0x10];
5176
5177 u8 other_vport[0x1];
b4ff3a36 5178 u8 reserved_at_41[0xf];
e281682b
SM		 5179 u8 vport_number[0x10];
5180
b4ff3a36 5181 u8 reserved_at_60[0x18];
e281682b 5182 u8 admin_state[0x4];
b4ff3a36 5183 u8 reserved_at_7c[0x4];
e281682b
SM		 5184};
5185
5186struct mlx5_ifc_modify_tis_out_bits {
5187 u8 status[0x8];
b4ff3a36 5188 u8 reserved_at_8[0x18];
e281682b
SM		 5189
5190 u8 syndrome[0x20];
5191
b4ff3a36 5192 u8 reserved_at_40[0x40];
e281682b
SM		 5193};
5194
75850d0b 5195struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5196 u8 reserved_at_0[0x20];
75850d0b 5197
84df61eb
AH		 5198 u8 reserved_at_20[0x1d];
5199 u8 lag_tx_port_affinity[0x1];
5200 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5201 u8 prio[0x1];
5202};
5203
e281682b
SM		 5204struct mlx5_ifc_modify_tis_in_bits {
5205 u8 opcode[0x10];
b4ff3a36 5206 u8 reserved_at_10[0x10];
e281682b 5207
b4ff3a36 5208 u8 reserved_at_20[0x10];
e281682b
SM		 5209 u8 op_mod[0x10];
5210
b4ff3a36 5211 u8 reserved_at_40[0x8];
e281682b
SM		 5212 u8 tisn[0x18];
5213
b4ff3a36 5214 u8 reserved_at_60[0x20];
e281682b 5215
75850d0b 5216 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5217
b4ff3a36 5218 u8 reserved_at_c0[0x40];
e281682b
SM		 5219
5220 struct mlx5_ifc_tisc_bits ctx;
5221};
5222
d9eea403 5223struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5224 u8 reserved_at_0[0x20];
d9eea403 5225
b4ff3a36 5226 u8 reserved_at_20[0x1b];
66189961 5227 u8 self_lb_en[0x1];
bdfc028d
TT		 5228 u8 reserved_at_3c[0x1];
5229 u8 hash[0x1];
5230 u8 reserved_at_3e[0x1];
d9eea403
AS		 5231 u8 lro[0x1];
5232};
5233
e281682b
SM		 5234struct mlx5_ifc_modify_tir_out_bits {
5235 u8 status[0x8];
b4ff3a36 5236 u8 reserved_at_8[0x18];
e281682b
SM		 5237
5238 u8 syndrome[0x20];
5239
b4ff3a36 5240 u8 reserved_at_40[0x40];
e281682b
SM		 5241};
5242
5243struct mlx5_ifc_modify_tir_in_bits {
5244 u8 opcode[0x10];
b4ff3a36 5245 u8 reserved_at_10[0x10];
e281682b 5246
b4ff3a36 5247 u8 reserved_at_20[0x10];
e281682b
SM		 5248 u8 op_mod[0x10];
5249
b4ff3a36 5250 u8 reserved_at_40[0x8];
e281682b
SM		 5251 u8 tirn[0x18];
5252
b4ff3a36 5253 u8 reserved_at_60[0x20];
e281682b 5254
d9eea403 5255 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5256
b4ff3a36 5257 u8 reserved_at_c0[0x40];
e281682b
SM		 5258
5259 struct mlx5_ifc_tirc_bits ctx;
5260};
5261
5262struct mlx5_ifc_modify_sq_out_bits {
5263 u8 status[0x8];
b4ff3a36 5264 u8 reserved_at_8[0x18];
e281682b
SM		 5265
5266 u8 syndrome[0x20];
5267
b4ff3a36 5268 u8 reserved_at_40[0x40];
e281682b
SM		 5269};
5270
5271struct mlx5_ifc_modify_sq_in_bits {
5272 u8 opcode[0x10];
b4ff3a36 5273 u8 reserved_at_10[0x10];
e281682b 5274
b4ff3a36 5275 u8 reserved_at_20[0x10];
e281682b
SM		 5276 u8 op_mod[0x10];
5277
5278 u8 sq_state[0x4];
b4ff3a36 5279 u8 reserved_at_44[0x4];
e281682b
SM		 5280 u8 sqn[0x18];
5281
b4ff3a36 5282 u8 reserved_at_60[0x20];
e281682b
SM		 5283
5284 u8 modify_bitmask[0x40];
5285
b4ff3a36 5286 u8 reserved_at_c0[0x40];
e281682b
SM		 5287
5288 struct mlx5_ifc_sqc_bits ctx;
5289};
5290
813f8540
MHY		 5291struct mlx5_ifc_modify_scheduling_element_out_bits {
5292 u8 status[0x8];
5293 u8 reserved_at_8[0x18];
5294
5295 u8 syndrome[0x20];
5296
5297 u8 reserved_at_40[0x1c0];
5298};
5299
5300enum {
5301 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5302 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5303};
5304
5305struct mlx5_ifc_modify_scheduling_element_in_bits {
5306 u8 opcode[0x10];
5307 u8 reserved_at_10[0x10];
5308
5309 u8 reserved_at_20[0x10];
5310 u8 op_mod[0x10];
5311
5312 u8 scheduling_hierarchy[0x8];
5313 u8 reserved_at_48[0x18];
5314
5315 u8 scheduling_element_id[0x20];
5316
5317 u8 reserved_at_80[0x20];
5318
5319 u8 modify_bitmask[0x20];
5320
5321 u8 reserved_at_c0[0x40];
5322
5323 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5324
5325 u8 reserved_at_300[0x100];
5326};
5327
e281682b
SM		 5328struct mlx5_ifc_modify_rqt_out_bits {
5329 u8 status[0x8];
b4ff3a36 5330 u8 reserved_at_8[0x18];
e281682b
SM		 5331
5332 u8 syndrome[0x20];
5333
b4ff3a36 5334 u8 reserved_at_40[0x40];
e281682b
SM		 5335};
5336
5c50368f 5337struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5338 u8 reserved_at_0[0x20];
5c50368f 5339
b4ff3a36 5340 u8 reserved_at_20[0x1f];
5c50368f
AS		 5341 u8 rqn_list[0x1];
5342};
5343
e281682b
SM		 5344struct mlx5_ifc_modify_rqt_in_bits {
5345 u8 opcode[0x10];
b4ff3a36 5346 u8 reserved_at_10[0x10];
e281682b 5347
b4ff3a36 5348 u8 reserved_at_20[0x10];
e281682b
SM		 5349 u8 op_mod[0x10];
5350
b4ff3a36 5351 u8 reserved_at_40[0x8];
e281682b
SM		 5352 u8 rqtn[0x18];
5353
b4ff3a36 5354 u8 reserved_at_60[0x20];
e281682b 5355
5c50368f 5356 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5357
b4ff3a36 5358 u8 reserved_at_c0[0x40];
e281682b
SM		 5359
5360 struct mlx5_ifc_rqtc_bits ctx;
5361};
5362
5363struct mlx5_ifc_modify_rq_out_bits {
5364 u8 status[0x8];
b4ff3a36 5365 u8 reserved_at_8[0x18];
e281682b
SM		 5366
5367 u8 syndrome[0x20];
5368
b4ff3a36 5369 u8 reserved_at_40[0x40];
e281682b
SM		 5370};
5371
83b502a1
AV		 5372enum {
5373 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5374 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5375 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5376};
5377
e281682b
SM		 5378struct mlx5_ifc_modify_rq_in_bits {
5379 u8 opcode[0x10];
b4ff3a36 5380 u8 reserved_at_10[0x10];
e281682b 5381
b4ff3a36 5382 u8 reserved_at_20[0x10];
e281682b
SM		 5383 u8 op_mod[0x10];
5384
5385 u8 rq_state[0x4];
b4ff3a36 5386 u8 reserved_at_44[0x4];
e281682b
SM		 5387 u8 rqn[0x18];
5388
b4ff3a36 5389 u8 reserved_at_60[0x20];
e281682b
SM		 5390
5391 u8 modify_bitmask[0x40];
5392
b4ff3a36 5393 u8 reserved_at_c0[0x40];
e281682b
SM		 5394
5395 struct mlx5_ifc_rqc_bits ctx;
5396};
5397
5398struct mlx5_ifc_modify_rmp_out_bits {
5399 u8 status[0x8];
b4ff3a36 5400 u8 reserved_at_8[0x18];
e281682b
SM		 5401
5402 u8 syndrome[0x20];
5403
b4ff3a36 5404 u8 reserved_at_40[0x40];
e281682b
SM		 5405};
5406
01949d01 5407struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5408 u8 reserved_at_0[0x20];
01949d01 5409
b4ff3a36 5410 u8 reserved_at_20[0x1f];
01949d01
HA		 5411 u8 lwm[0x1];
5412};
5413
e281682b
SM		 5414struct mlx5_ifc_modify_rmp_in_bits {
5415 u8 opcode[0x10];
b4ff3a36 5416 u8 reserved_at_10[0x10];
e281682b 5417
b4ff3a36 5418 u8 reserved_at_20[0x10];
e281682b
SM		 5419 u8 op_mod[0x10];
5420
5421 u8 rmp_state[0x4];
b4ff3a36 5422 u8 reserved_at_44[0x4];
e281682b
SM		 5423 u8 rmpn[0x18];
5424
b4ff3a36 5425 u8 reserved_at_60[0x20];
e281682b 5426
01949d01 5427 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5428
b4ff3a36 5429 u8 reserved_at_c0[0x40];
e281682b
SM		 5430
5431 struct mlx5_ifc_rmpc_bits ctx;
5432};
5433
5434struct mlx5_ifc_modify_nic_vport_context_out_bits {
5435 u8 status[0x8];
b4ff3a36 5436 u8 reserved_at_8[0x18];
e281682b
SM		 5437
5438 u8 syndrome[0x20];
5439
b4ff3a36 5440 u8 reserved_at_40[0x40];
e281682b
SM		 5441};
5442
5443struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5444 u8 reserved_at_0[0x12];
5445 u8 affiliation[0x1];
5446 u8 reserved_at_e[0x1];
bded747b
HN		 5447 u8 disable_uc_local_lb[0x1];
5448 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5449 u8 node_guid[0x1];
5450 u8 port_guid[0x1];
9def7121 5451 u8 min_inline[0x1];
d82b7318
SM		 5452 u8 mtu[0x1];
5453 u8 change_event[0x1];
5454 u8 promisc[0x1];
e281682b
SM		 5455 u8 permanent_address[0x1];
5456 u8 addresses_list[0x1];
5457 u8 roce_en[0x1];
b4ff3a36 5458 u8 reserved_at_1f[0x1];
e281682b
SM		 5459};
5460
5461struct mlx5_ifc_modify_nic_vport_context_in_bits {
5462 u8 opcode[0x10];
b4ff3a36 5463 u8 reserved_at_10[0x10];
e281682b 5464
b4ff3a36 5465 u8 reserved_at_20[0x10];
e281682b
SM		 5466 u8 op_mod[0x10];
5467
5468 u8 other_vport[0x1];
b4ff3a36 5469 u8 reserved_at_41[0xf];
e281682b
SM		 5470 u8 vport_number[0x10];
5471
5472 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5473
b4ff3a36 5474 u8 reserved_at_80[0x780];
e281682b
SM		 5475
5476 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5477};
5478
5479struct mlx5_ifc_modify_hca_vport_context_out_bits {
5480 u8 status[0x8];
b4ff3a36 5481 u8 reserved_at_8[0x18];
e281682b
SM		 5482
5483 u8 syndrome[0x20];
5484
b4ff3a36 5485 u8 reserved_at_40[0x40];
e281682b
SM		 5486};
5487
5488struct mlx5_ifc_modify_hca_vport_context_in_bits {
5489 u8 opcode[0x10];
b4ff3a36 5490 u8 reserved_at_10[0x10];
e281682b 5491
b4ff3a36 5492 u8 reserved_at_20[0x10];
e281682b
SM		 5493 u8 op_mod[0x10];
5494
5495 u8 other_vport[0x1];
b4ff3a36 5496 u8 reserved_at_41[0xb];
707c4602 5497 u8 port_num[0x4];
e281682b
SM		 5498 u8 vport_number[0x10];
5499
b4ff3a36 5500 u8 reserved_at_60[0x20];
e281682b
SM		 5501
5502 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5503};
5504
5505struct mlx5_ifc_modify_cq_out_bits {
5506 u8 status[0x8];
b4ff3a36 5507 u8 reserved_at_8[0x18];
e281682b
SM		 5508
5509 u8 syndrome[0x20];
5510
b4ff3a36 5511 u8 reserved_at_40[0x40];
e281682b
SM		 5512};
5513
5514enum {
5515 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5516 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5517};
5518
5519struct mlx5_ifc_modify_cq_in_bits {
5520 u8 opcode[0x10];
b4ff3a36 5521 u8 reserved_at_10[0x10];
e281682b 5522
b4ff3a36 5523 u8 reserved_at_20[0x10];
e281682b
SM		 5524 u8 op_mod[0x10];
5525
b4ff3a36 5526 u8 reserved_at_40[0x8];
e281682b
SM		 5527 u8 cqn[0x18];
5528
5529 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5530
5531 struct mlx5_ifc_cqc_bits cq_context;
5532
b4ff3a36 5533 u8 reserved_at_280[0x600];
e281682b
SM		 5534
5535 u8 pas[0][0x40];
5536};
5537
5538struct mlx5_ifc_modify_cong_status_out_bits {
5539 u8 status[0x8];
b4ff3a36 5540 u8 reserved_at_8[0x18];
e281682b
SM		 5541
5542 u8 syndrome[0x20];
5543
b4ff3a36 5544 u8 reserved_at_40[0x40];
e281682b
SM		 5545};
5546
5547struct mlx5_ifc_modify_cong_status_in_bits {
5548 u8 opcode[0x10];
b4ff3a36 5549 u8 reserved_at_10[0x10];
e281682b 5550
b4ff3a36 5551 u8 reserved_at_20[0x10];
e281682b
SM		 5552 u8 op_mod[0x10];
5553
b4ff3a36 5554 u8 reserved_at_40[0x18];
e281682b
SM		 5555 u8 priority[0x4];
5556 u8 cong_protocol[0x4];
5557
5558 u8 enable[0x1];
5559 u8 tag_enable[0x1];
b4ff3a36 5560 u8 reserved_at_62[0x1e];
e281682b
SM		 5561};
5562
5563struct mlx5_ifc_modify_cong_params_out_bits {
5564 u8 status[0x8];
b4ff3a36 5565 u8 reserved_at_8[0x18];
e281682b
SM		 5566
5567 u8 syndrome[0x20];
5568
b4ff3a36 5569 u8 reserved_at_40[0x40];
e281682b
SM		 5570};
5571
5572struct mlx5_ifc_modify_cong_params_in_bits {
5573 u8 opcode[0x10];
b4ff3a36 5574 u8 reserved_at_10[0x10];
e281682b 5575
b4ff3a36 5576 u8 reserved_at_20[0x10];
e281682b
SM		 5577 u8 op_mod[0x10];
5578
b4ff3a36 5579 u8 reserved_at_40[0x1c];
e281682b
SM		 5580 u8 cong_protocol[0x4];
5581
5582 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5583
b4ff3a36 5584 u8 reserved_at_80[0x80];
e281682b
SM		 5585
5586 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5587};
5588
5589struct mlx5_ifc_manage_pages_out_bits {
5590 u8 status[0x8];
b4ff3a36 5591 u8 reserved_at_8[0x18];
e281682b
SM		 5592
5593 u8 syndrome[0x20];
5594
5595 u8 output_num_entries[0x20];
5596
b4ff3a36 5597 u8 reserved_at_60[0x20];
e281682b
SM		 5598
5599 u8 pas[0][0x40];
5600};
5601
5602enum {
5603 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5604 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5605 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5606};
5607
5608struct mlx5_ifc_manage_pages_in_bits {
5609 u8 opcode[0x10];
b4ff3a36 5610 u8 reserved_at_10[0x10];
e281682b 5611
b4ff3a36 5612 u8 reserved_at_20[0x10];
e281682b
SM		 5613 u8 op_mod[0x10];
5614
b4ff3a36 5615 u8 reserved_at_40[0x10];
e281682b
SM		 5616 u8 function_id[0x10];
5617
5618 u8 input_num_entries[0x20];
5619
5620 u8 pas[0][0x40];
5621};
5622
5623struct mlx5_ifc_mad_ifc_out_bits {
5624 u8 status[0x8];
b4ff3a36 5625 u8 reserved_at_8[0x18];
e281682b
SM		 5626
5627 u8 syndrome[0x20];
5628
b4ff3a36 5629 u8 reserved_at_40[0x40];
e281682b
SM		 5630
5631 u8 response_mad_packet[256][0x8];
5632};
5633
5634struct mlx5_ifc_mad_ifc_in_bits {
5635 u8 opcode[0x10];
b4ff3a36 5636 u8 reserved_at_10[0x10];
e281682b 5637
b4ff3a36 5638 u8 reserved_at_20[0x10];
e281682b
SM		 5639 u8 op_mod[0x10];
5640
5641 u8 remote_lid[0x10];
b4ff3a36 5642 u8 reserved_at_50[0x8];
e281682b
SM		 5643 u8 port[0x8];
5644
b4ff3a36 5645 u8 reserved_at_60[0x20];
e281682b
SM		 5646
5647 u8 mad[256][0x8];
5648};
5649
5650struct mlx5_ifc_init_hca_out_bits {
5651 u8 status[0x8];
b4ff3a36 5652 u8 reserved_at_8[0x18];
e281682b
SM		 5653
5654 u8 syndrome[0x20];
5655
b4ff3a36 5656 u8 reserved_at_40[0x40];
e281682b
SM		 5657};
5658
5659struct mlx5_ifc_init_hca_in_bits {
5660 u8 opcode[0x10];
b4ff3a36 5661 u8 reserved_at_10[0x10];
e281682b 5662
b4ff3a36 5663 u8 reserved_at_20[0x10];
e281682b
SM		 5664 u8 op_mod[0x10];
5665
b4ff3a36 5666 u8 reserved_at_40[0x40];
8737f818 5667 u8 sw_owner_id[4][0x20];
e281682b
SM		 5668};
5669
5670struct mlx5_ifc_init2rtr_qp_out_bits {
5671 u8 status[0x8];
b4ff3a36 5672 u8 reserved_at_8[0x18];
e281682b
SM		 5673
5674 u8 syndrome[0x20];
5675
b4ff3a36 5676 u8 reserved_at_40[0x40];
e281682b
SM		 5677};
5678
5679struct mlx5_ifc_init2rtr_qp_in_bits {
5680 u8 opcode[0x10];
b4ff3a36 5681 u8 reserved_at_10[0x10];
e281682b 5682
b4ff3a36 5683 u8 reserved_at_20[0x10];
e281682b
SM		 5684 u8 op_mod[0x10];
5685
b4ff3a36 5686 u8 reserved_at_40[0x8];
e281682b
SM		 5687 u8 qpn[0x18];
5688
b4ff3a36 5689 u8 reserved_at_60[0x20];
e281682b
SM		 5690
5691 u8 opt_param_mask[0x20];
5692
b4ff3a36 5693 u8 reserved_at_a0[0x20];
e281682b
SM		 5694
5695 struct mlx5_ifc_qpc_bits qpc;
5696
b4ff3a36 5697 u8 reserved_at_800[0x80];
e281682b
SM		 5698};
5699
5700struct mlx5_ifc_init2init_qp_out_bits {
5701 u8 status[0x8];
b4ff3a36 5702 u8 reserved_at_8[0x18];
e281682b
SM		 5703
5704 u8 syndrome[0x20];
5705
b4ff3a36 5706 u8 reserved_at_40[0x40];
e281682b
SM		 5707};
5708
5709struct mlx5_ifc_init2init_qp_in_bits {
5710 u8 opcode[0x10];
b4ff3a36 5711 u8 reserved_at_10[0x10];
e281682b 5712
b4ff3a36 5713 u8 reserved_at_20[0x10];
e281682b
SM		 5714 u8 op_mod[0x10];
5715
b4ff3a36 5716 u8 reserved_at_40[0x8];
e281682b
SM		 5717 u8 qpn[0x18];
5718
b4ff3a36 5719 u8 reserved_at_60[0x20];
e281682b
SM		 5720
5721 u8 opt_param_mask[0x20];
5722
b4ff3a36 5723 u8 reserved_at_a0[0x20];
e281682b
SM		 5724
5725 struct mlx5_ifc_qpc_bits qpc;
5726
b4ff3a36 5727 u8 reserved_at_800[0x80];
e281682b
SM		 5728};
5729
5730struct mlx5_ifc_get_dropped_packet_log_out_bits {
5731 u8 status[0x8];
b4ff3a36 5732 u8 reserved_at_8[0x18];
e281682b
SM		 5733
5734 u8 syndrome[0x20];
5735
b4ff3a36 5736 u8 reserved_at_40[0x40];
e281682b
SM		 5737
5738 u8 packet_headers_log[128][0x8];
5739
5740 u8 packet_syndrome[64][0x8];
5741};
5742
5743struct mlx5_ifc_get_dropped_packet_log_in_bits {
5744 u8 opcode[0x10];
b4ff3a36 5745 u8 reserved_at_10[0x10];
e281682b 5746
b4ff3a36 5747 u8 reserved_at_20[0x10];
e281682b
SM		 5748 u8 op_mod[0x10];
5749
b4ff3a36 5750 u8 reserved_at_40[0x40];
e281682b
SM		 5751};
5752
5753struct mlx5_ifc_gen_eqe_in_bits {
5754 u8 opcode[0x10];
b4ff3a36 5755 u8 reserved_at_10[0x10];
e281682b 5756
b4ff3a36 5757 u8 reserved_at_20[0x10];
e281682b
SM		 5758 u8 op_mod[0x10];
5759
b4ff3a36 5760 u8 reserved_at_40[0x18];
e281682b
SM		 5761 u8 eq_number[0x8];
5762
b4ff3a36 5763 u8 reserved_at_60[0x20];
e281682b
SM		 5764
5765 u8 eqe[64][0x8];
5766};
5767
5768struct mlx5_ifc_gen_eq_out_bits {
5769 u8 status[0x8];
b4ff3a36 5770 u8 reserved_at_8[0x18];
e281682b
SM		 5771
5772 u8 syndrome[0x20];
5773
b4ff3a36 5774 u8 reserved_at_40[0x40];
e281682b
SM		 5775};
5776
5777struct mlx5_ifc_enable_hca_out_bits {
5778 u8 status[0x8];
b4ff3a36 5779 u8 reserved_at_8[0x18];
e281682b
SM		 5780
5781 u8 syndrome[0x20];
5782
b4ff3a36 5783 u8 reserved_at_40[0x20];
e281682b
SM		 5784};
5785
5786struct mlx5_ifc_enable_hca_in_bits {
5787 u8 opcode[0x10];
b4ff3a36 5788 u8 reserved_at_10[0x10];
e281682b 5789
b4ff3a36 5790 u8 reserved_at_20[0x10];
e281682b
SM		 5791 u8 op_mod[0x10];
5792
b4ff3a36 5793 u8 reserved_at_40[0x10];
e281682b
SM		 5794 u8 function_id[0x10];
5795
b4ff3a36 5796 u8 reserved_at_60[0x20];
e281682b
SM		 5797};
5798
5799struct mlx5_ifc_drain_dct_out_bits {
5800 u8 status[0x8];
b4ff3a36 5801 u8 reserved_at_8[0x18];
e281682b
SM		 5802
5803 u8 syndrome[0x20];
5804
b4ff3a36 5805 u8 reserved_at_40[0x40];
e281682b
SM		 5806};
5807
5808struct mlx5_ifc_drain_dct_in_bits {
5809 u8 opcode[0x10];
b4ff3a36 5810 u8 reserved_at_10[0x10];
e281682b 5811
b4ff3a36 5812 u8 reserved_at_20[0x10];
e281682b
SM		 5813 u8 op_mod[0x10];
5814
b4ff3a36 5815 u8 reserved_at_40[0x8];
e281682b
SM		 5816 u8 dctn[0x18];
5817
b4ff3a36 5818 u8 reserved_at_60[0x20];
e281682b
SM		 5819};
5820
5821struct mlx5_ifc_disable_hca_out_bits {
5822 u8 status[0x8];
b4ff3a36 5823 u8 reserved_at_8[0x18];
e281682b
SM		 5824
5825 u8 syndrome[0x20];
5826
b4ff3a36 5827 u8 reserved_at_40[0x20];
e281682b
SM		 5828};
5829
5830struct mlx5_ifc_disable_hca_in_bits {
5831 u8 opcode[0x10];
b4ff3a36 5832 u8 reserved_at_10[0x10];
e281682b 5833
b4ff3a36 5834 u8 reserved_at_20[0x10];
e281682b
SM		 5835 u8 op_mod[0x10];
5836
b4ff3a36 5837 u8 reserved_at_40[0x10];
e281682b
SM		 5838 u8 function_id[0x10];
5839
b4ff3a36 5840 u8 reserved_at_60[0x20];
e281682b
SM		 5841};
5842
5843struct mlx5_ifc_detach_from_mcg_out_bits {
5844 u8 status[0x8];
b4ff3a36 5845 u8 reserved_at_8[0x18];
e281682b
SM		 5846
5847 u8 syndrome[0x20];
5848
b4ff3a36 5849 u8 reserved_at_40[0x40];
e281682b
SM		 5850};
5851
5852struct mlx5_ifc_detach_from_mcg_in_bits {
5853 u8 opcode[0x10];
b4ff3a36 5854 u8 reserved_at_10[0x10];
e281682b 5855
b4ff3a36 5856 u8 reserved_at_20[0x10];
e281682b
SM		 5857 u8 op_mod[0x10];
5858
b4ff3a36 5859 u8 reserved_at_40[0x8];
e281682b
SM		 5860 u8 qpn[0x18];
5861
b4ff3a36 5862 u8 reserved_at_60[0x20];
e281682b
SM		 5863
5864 u8 multicast_gid[16][0x8];
5865};
5866
7486216b
SM		 5867struct mlx5_ifc_destroy_xrq_out_bits {
5868 u8 status[0x8];
5869 u8 reserved_at_8[0x18];
5870
5871 u8 syndrome[0x20];
5872
5873 u8 reserved_at_40[0x40];
5874};
5875
5876struct mlx5_ifc_destroy_xrq_in_bits {
5877 u8 opcode[0x10];
5878 u8 reserved_at_10[0x10];
5879
5880 u8 reserved_at_20[0x10];
5881 u8 op_mod[0x10];
5882
5883 u8 reserved_at_40[0x8];
5884 u8 xrqn[0x18];
5885
5886 u8 reserved_at_60[0x20];
5887};
5888
e281682b
SM		 5889struct mlx5_ifc_destroy_xrc_srq_out_bits {
5890 u8 status[0x8];
b4ff3a36 5891 u8 reserved_at_8[0x18];
e281682b
SM		 5892
5893 u8 syndrome[0x20];
5894
b4ff3a36 5895 u8 reserved_at_40[0x40];
e281682b
SM		 5896};
5897
5898struct mlx5_ifc_destroy_xrc_srq_in_bits {
5899 u8 opcode[0x10];
b4ff3a36 5900 u8 reserved_at_10[0x10];
e281682b 5901
b4ff3a36 5902 u8 reserved_at_20[0x10];
e281682b
SM		 5903 u8 op_mod[0x10];
5904
b4ff3a36 5905 u8 reserved_at_40[0x8];
e281682b
SM		 5906 u8 xrc_srqn[0x18];
5907
b4ff3a36 5908 u8 reserved_at_60[0x20];
e281682b
SM		 5909};
5910
5911struct mlx5_ifc_destroy_tis_out_bits {
5912 u8 status[0x8];
b4ff3a36 5913 u8 reserved_at_8[0x18];
e281682b
SM		 5914
5915 u8 syndrome[0x20];
5916
b4ff3a36 5917 u8 reserved_at_40[0x40];
e281682b
SM		 5918};
5919
5920struct mlx5_ifc_destroy_tis_in_bits {
5921 u8 opcode[0x10];
b4ff3a36 5922 u8 reserved_at_10[0x10];
e281682b 5923
b4ff3a36 5924 u8 reserved_at_20[0x10];
e281682b
SM		 5925 u8 op_mod[0x10];
5926
b4ff3a36 5927 u8 reserved_at_40[0x8];
e281682b
SM		 5928 u8 tisn[0x18];
5929
b4ff3a36 5930 u8 reserved_at_60[0x20];
e281682b
SM		 5931};
5932
5933struct mlx5_ifc_destroy_tir_out_bits {
5934 u8 status[0x8];
b4ff3a36 5935 u8 reserved_at_8[0x18];
e281682b
SM		 5936
5937 u8 syndrome[0x20];
5938
b4ff3a36 5939 u8 reserved_at_40[0x40];
e281682b
SM		 5940};
5941
5942struct mlx5_ifc_destroy_tir_in_bits {
5943 u8 opcode[0x10];
b4ff3a36 5944 u8 reserved_at_10[0x10];
e281682b 5945
b4ff3a36 5946 u8 reserved_at_20[0x10];
e281682b
SM		 5947 u8 op_mod[0x10];
5948
b4ff3a36 5949 u8 reserved_at_40[0x8];
e281682b
SM		 5950 u8 tirn[0x18];
5951
b4ff3a36 5952 u8 reserved_at_60[0x20];
e281682b
SM		 5953};
5954
5955struct mlx5_ifc_destroy_srq_out_bits {
5956 u8 status[0x8];
b4ff3a36 5957 u8 reserved_at_8[0x18];
e281682b
SM		 5958
5959 u8 syndrome[0x20];
5960
b4ff3a36 5961 u8 reserved_at_40[0x40];
e281682b
SM		 5962};
5963
5964struct mlx5_ifc_destroy_srq_in_bits {
5965 u8 opcode[0x10];
b4ff3a36 5966 u8 reserved_at_10[0x10];
e281682b 5967
b4ff3a36 5968 u8 reserved_at_20[0x10];
e281682b
SM		 5969 u8 op_mod[0x10];
5970
b4ff3a36 5971 u8 reserved_at_40[0x8];
e281682b
SM		 5972 u8 srqn[0x18];
5973
b4ff3a36 5974 u8 reserved_at_60[0x20];
e281682b
SM		 5975};
5976
5977struct mlx5_ifc_destroy_sq_out_bits {
5978 u8 status[0x8];
b4ff3a36 5979 u8 reserved_at_8[0x18];
e281682b
SM		 5980
5981 u8 syndrome[0x20];
5982
b4ff3a36 5983 u8 reserved_at_40[0x40];
e281682b
SM		 5984};
5985
5986struct mlx5_ifc_destroy_sq_in_bits {
5987 u8 opcode[0x10];
b4ff3a36 5988 u8 reserved_at_10[0x10];
e281682b 5989
b4ff3a36 5990 u8 reserved_at_20[0x10];
e281682b
SM		 5991 u8 op_mod[0x10];
5992
b4ff3a36 5993 u8 reserved_at_40[0x8];
e281682b
SM		 5994 u8 sqn[0x18];
5995
b4ff3a36 5996 u8 reserved_at_60[0x20];
e281682b
SM		 5997};
5998
813f8540
MHY		 5999struct mlx5_ifc_destroy_scheduling_element_out_bits {
6000 u8 status[0x8];
6001 u8 reserved_at_8[0x18];
6002
6003 u8 syndrome[0x20];
6004
6005 u8 reserved_at_40[0x1c0];
6006};
6007
6008struct mlx5_ifc_destroy_scheduling_element_in_bits {
6009 u8 opcode[0x10];
6010 u8 reserved_at_10[0x10];
6011
6012 u8 reserved_at_20[0x10];
6013 u8 op_mod[0x10];
6014
6015 u8 scheduling_hierarchy[0x8];
6016 u8 reserved_at_48[0x18];
6017
6018 u8 scheduling_element_id[0x20];
6019
6020 u8 reserved_at_80[0x180];
6021};
6022
e281682b
SM		 6023struct mlx5_ifc_destroy_rqt_out_bits {
6024 u8 status[0x8];
b4ff3a36 6025 u8 reserved_at_8[0x18];
e281682b
SM		 6026
6027 u8 syndrome[0x20];
6028
b4ff3a36 6029 u8 reserved_at_40[0x40];
e281682b
SM		 6030};
6031
6032struct mlx5_ifc_destroy_rqt_in_bits {
6033 u8 opcode[0x10];
b4ff3a36 6034 u8 reserved_at_10[0x10];
e281682b 6035
b4ff3a36 6036 u8 reserved_at_20[0x10];
e281682b
SM		 6037 u8 op_mod[0x10];
6038
b4ff3a36 6039 u8 reserved_at_40[0x8];
e281682b
SM		 6040 u8 rqtn[0x18];
6041
b4ff3a36 6042 u8 reserved_at_60[0x20];
e281682b
SM		 6043};
6044
6045struct mlx5_ifc_destroy_rq_out_bits {
6046 u8 status[0x8];
b4ff3a36 6047 u8 reserved_at_8[0x18];
e281682b
SM		 6048
6049 u8 syndrome[0x20];
6050
b4ff3a36 6051 u8 reserved_at_40[0x40];
e281682b
SM		 6052};
6053
6054struct mlx5_ifc_destroy_rq_in_bits {
6055 u8 opcode[0x10];
b4ff3a36 6056 u8 reserved_at_10[0x10];
e281682b 6057
b4ff3a36 6058 u8 reserved_at_20[0x10];
e281682b
SM		 6059 u8 op_mod[0x10];
6060
b4ff3a36 6061 u8 reserved_at_40[0x8];
e281682b
SM		 6062 u8 rqn[0x18];
6063
b4ff3a36 6064 u8 reserved_at_60[0x20];
e281682b
SM		 6065};
6066
c1e0bfc1
MG		 6067struct mlx5_ifc_set_delay_drop_params_in_bits {
6068 u8 opcode[0x10];
6069 u8 reserved_at_10[0x10];
6070
6071 u8 reserved_at_20[0x10];
6072 u8 op_mod[0x10];
6073
6074 u8 reserved_at_40[0x20];
6075
6076 u8 reserved_at_60[0x10];
6077 u8 delay_drop_timeout[0x10];
6078};
6079
6080struct mlx5_ifc_set_delay_drop_params_out_bits {
6081 u8 status[0x8];
6082 u8 reserved_at_8[0x18];
6083
6084 u8 syndrome[0x20];
6085
6086 u8 reserved_at_40[0x40];
6087};
6088
e281682b
SM		 6089struct mlx5_ifc_destroy_rmp_out_bits {
6090 u8 status[0x8];
b4ff3a36 6091 u8 reserved_at_8[0x18];
e281682b
SM		 6092
6093 u8 syndrome[0x20];
6094
b4ff3a36 6095 u8 reserved_at_40[0x40];
e281682b
SM		 6096};
6097
6098struct mlx5_ifc_destroy_rmp_in_bits {
6099 u8 opcode[0x10];
b4ff3a36 6100 u8 reserved_at_10[0x10];
e281682b 6101
b4ff3a36 6102 u8 reserved_at_20[0x10];
e281682b
SM		 6103 u8 op_mod[0x10];
6104
b4ff3a36 6105 u8 reserved_at_40[0x8];
e281682b
SM		 6106 u8 rmpn[0x18];
6107
b4ff3a36 6108 u8 reserved_at_60[0x20];
e281682b
SM		 6109};
6110
6111struct mlx5_ifc_destroy_qp_out_bits {
6112 u8 status[0x8];
b4ff3a36 6113 u8 reserved_at_8[0x18];
e281682b
SM		 6114
6115 u8 syndrome[0x20];
6116
b4ff3a36 6117 u8 reserved_at_40[0x40];
e281682b
SM		 6118};
6119
6120struct mlx5_ifc_destroy_qp_in_bits {
6121 u8 opcode[0x10];
b4ff3a36 6122 u8 reserved_at_10[0x10];
e281682b 6123
b4ff3a36 6124 u8 reserved_at_20[0x10];
e281682b
SM		 6125 u8 op_mod[0x10];
6126
b4ff3a36 6127 u8 reserved_at_40[0x8];
e281682b
SM		 6128 u8 qpn[0x18];
6129
b4ff3a36 6130 u8 reserved_at_60[0x20];
e281682b
SM		 6131};
6132
6133struct mlx5_ifc_destroy_psv_out_bits {
6134 u8 status[0x8];
b4ff3a36 6135 u8 reserved_at_8[0x18];
e281682b
SM		 6136
6137 u8 syndrome[0x20];
6138
b4ff3a36 6139 u8 reserved_at_40[0x40];
e281682b
SM		 6140};
6141
6142struct mlx5_ifc_destroy_psv_in_bits {
6143 u8 opcode[0x10];
b4ff3a36 6144 u8 reserved_at_10[0x10];
e281682b 6145
b4ff3a36 6146 u8 reserved_at_20[0x10];
e281682b
SM		 6147 u8 op_mod[0x10];
6148
b4ff3a36 6149 u8 reserved_at_40[0x8];
e281682b
SM		 6150 u8 psvn[0x18];
6151
b4ff3a36 6152 u8 reserved_at_60[0x20];
e281682b
SM		 6153};
6154
6155struct mlx5_ifc_destroy_mkey_out_bits {
6156 u8 status[0x8];
b4ff3a36 6157 u8 reserved_at_8[0x18];
e281682b
SM		 6158
6159 u8 syndrome[0x20];
6160
b4ff3a36 6161 u8 reserved_at_40[0x40];
e281682b
SM		 6162};
6163
6164struct mlx5_ifc_destroy_mkey_in_bits {
6165 u8 opcode[0x10];
b4ff3a36 6166 u8 reserved_at_10[0x10];
e281682b 6167
b4ff3a36 6168 u8 reserved_at_20[0x10];
e281682b
SM		 6169 u8 op_mod[0x10];
6170
b4ff3a36 6171 u8 reserved_at_40[0x8];
e281682b
SM		 6172 u8 mkey_index[0x18];
6173
b4ff3a36 6174 u8 reserved_at_60[0x20];
e281682b
SM		 6175};
6176
6177struct mlx5_ifc_destroy_flow_table_out_bits {
6178 u8 status[0x8];
b4ff3a36 6179 u8 reserved_at_8[0x18];
e281682b
SM		 6180
6181 u8 syndrome[0x20];
6182
b4ff3a36 6183 u8 reserved_at_40[0x40];
e281682b
SM		 6184};
6185
6186struct mlx5_ifc_destroy_flow_table_in_bits {
6187 u8 opcode[0x10];
b4ff3a36 6188 u8 reserved_at_10[0x10];
e281682b 6189
b4ff3a36 6190 u8 reserved_at_20[0x10];
e281682b
SM		 6191 u8 op_mod[0x10];
6192
7d5e1423
SM		 6193 u8 other_vport[0x1];
6194 u8 reserved_at_41[0xf];
6195 u8 vport_number[0x10];
6196
6197 u8 reserved_at_60[0x20];
e281682b
SM		 6198
6199 u8 table_type[0x8];
b4ff3a36 6200 u8 reserved_at_88[0x18];
e281682b 6201
b4ff3a36 6202 u8 reserved_at_a0[0x8];
e281682b
SM		 6203 u8 table_id[0x18];
6204
b4ff3a36 6205 u8 reserved_at_c0[0x140];
e281682b
SM		 6206};
6207
6208struct mlx5_ifc_destroy_flow_group_out_bits {
6209 u8 status[0x8];
b4ff3a36 6210 u8 reserved_at_8[0x18];
e281682b
SM		 6211
6212 u8 syndrome[0x20];
6213
b4ff3a36 6214 u8 reserved_at_40[0x40];
e281682b
SM		 6215};
6216
6217struct mlx5_ifc_destroy_flow_group_in_bits {
6218 u8 opcode[0x10];
b4ff3a36 6219 u8 reserved_at_10[0x10];
e281682b 6220
b4ff3a36 6221 u8 reserved_at_20[0x10];
e281682b
SM		 6222 u8 op_mod[0x10];
6223
7d5e1423
SM		 6224 u8 other_vport[0x1];
6225 u8 reserved_at_41[0xf];
6226 u8 vport_number[0x10];
6227
6228 u8 reserved_at_60[0x20];
e281682b
SM		 6229
6230 u8 table_type[0x8];
b4ff3a36 6231 u8 reserved_at_88[0x18];
e281682b 6232
b4ff3a36 6233 u8 reserved_at_a0[0x8];
e281682b
SM		 6234 u8 table_id[0x18];
6235
6236 u8 group_id[0x20];
6237
b4ff3a36 6238 u8 reserved_at_e0[0x120];
e281682b
SM		 6239};
6240
6241struct mlx5_ifc_destroy_eq_out_bits {
6242 u8 status[0x8];
b4ff3a36 6243 u8 reserved_at_8[0x18];
e281682b
SM		 6244
6245 u8 syndrome[0x20];
6246
b4ff3a36 6247 u8 reserved_at_40[0x40];
e281682b
SM		 6248};
6249
6250struct mlx5_ifc_destroy_eq_in_bits {
6251 u8 opcode[0x10];
b4ff3a36 6252 u8 reserved_at_10[0x10];
e281682b 6253
b4ff3a36 6254 u8 reserved_at_20[0x10];
e281682b
SM		 6255 u8 op_mod[0x10];
6256
b4ff3a36 6257 u8 reserved_at_40[0x18];
e281682b
SM		 6258 u8 eq_number[0x8];
6259
b4ff3a36 6260 u8 reserved_at_60[0x20];
e281682b
SM		 6261};
6262
6263struct mlx5_ifc_destroy_dct_out_bits {
6264 u8 status[0x8];
b4ff3a36 6265 u8 reserved_at_8[0x18];
e281682b
SM		 6266
6267 u8 syndrome[0x20];
6268
b4ff3a36 6269 u8 reserved_at_40[0x40];
e281682b
SM		 6270};
6271
6272struct mlx5_ifc_destroy_dct_in_bits {
6273 u8 opcode[0x10];
b4ff3a36 6274 u8 reserved_at_10[0x10];
e281682b 6275
b4ff3a36 6276 u8 reserved_at_20[0x10];
e281682b
SM		 6277 u8 op_mod[0x10];
6278
b4ff3a36 6279 u8 reserved_at_40[0x8];
e281682b
SM		 6280 u8 dctn[0x18];
6281
b4ff3a36 6282 u8 reserved_at_60[0x20];
e281682b
SM		 6283};
6284
6285struct mlx5_ifc_destroy_cq_out_bits {
6286 u8 status[0x8];
b4ff3a36 6287 u8 reserved_at_8[0x18];
e281682b
SM		 6288
6289 u8 syndrome[0x20];
6290
b4ff3a36 6291 u8 reserved_at_40[0x40];
e281682b
SM		 6292};
6293
6294struct mlx5_ifc_destroy_cq_in_bits {
6295 u8 opcode[0x10];
b4ff3a36 6296 u8 reserved_at_10[0x10];
e281682b 6297
b4ff3a36 6298 u8 reserved_at_20[0x10];
e281682b
SM		 6299 u8 op_mod[0x10];
6300
b4ff3a36 6301 u8 reserved_at_40[0x8];
e281682b
SM		 6302 u8 cqn[0x18];
6303
b4ff3a36 6304 u8 reserved_at_60[0x20];
e281682b
SM		 6305};
6306
6307struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6308 u8 status[0x8];
b4ff3a36 6309 u8 reserved_at_8[0x18];
e281682b
SM		 6310
6311 u8 syndrome[0x20];
6312
b4ff3a36 6313 u8 reserved_at_40[0x40];
e281682b
SM		 6314};
6315
6316struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6317 u8 opcode[0x10];
b4ff3a36 6318 u8 reserved_at_10[0x10];
e281682b 6319
b4ff3a36 6320 u8 reserved_at_20[0x10];
e281682b
SM		 6321 u8 op_mod[0x10];
6322
b4ff3a36 6323 u8 reserved_at_40[0x20];
e281682b 6324
b4ff3a36 6325 u8 reserved_at_60[0x10];
e281682b
SM		 6326 u8 vxlan_udp_port[0x10];
6327};
6328
6329struct mlx5_ifc_delete_l2_table_entry_out_bits {
6330 u8 status[0x8];
b4ff3a36 6331 u8 reserved_at_8[0x18];
e281682b
SM		 6332
6333 u8 syndrome[0x20];
6334
b4ff3a36 6335 u8 reserved_at_40[0x40];
e281682b
SM		 6336};
6337
6338struct mlx5_ifc_delete_l2_table_entry_in_bits {
6339 u8 opcode[0x10];
b4ff3a36 6340 u8 reserved_at_10[0x10];
e281682b 6341
b4ff3a36 6342 u8 reserved_at_20[0x10];
e281682b
SM		 6343 u8 op_mod[0x10];
6344
b4ff3a36 6345 u8 reserved_at_40[0x60];
e281682b 6346
b4ff3a36 6347 u8 reserved_at_a0[0x8];
e281682b
SM		 6348 u8 table_index[0x18];
6349
b4ff3a36 6350 u8 reserved_at_c0[0x140];
e281682b
SM		 6351};
6352
6353struct mlx5_ifc_delete_fte_out_bits {
6354 u8 status[0x8];
b4ff3a36 6355 u8 reserved_at_8[0x18];
e281682b
SM		 6356
6357 u8 syndrome[0x20];
6358
b4ff3a36 6359 u8 reserved_at_40[0x40];
e281682b
SM		 6360};
6361
6362struct mlx5_ifc_delete_fte_in_bits {
6363 u8 opcode[0x10];
b4ff3a36 6364 u8 reserved_at_10[0x10];
e281682b 6365
b4ff3a36 6366 u8 reserved_at_20[0x10];
e281682b
SM		 6367 u8 op_mod[0x10];
6368
7d5e1423
SM		 6369 u8 other_vport[0x1];
6370 u8 reserved_at_41[0xf];
6371 u8 vport_number[0x10];
6372
6373 u8 reserved_at_60[0x20];
e281682b
SM		 6374
6375 u8 table_type[0x8];
b4ff3a36 6376 u8 reserved_at_88[0x18];
e281682b 6377
b4ff3a36 6378 u8 reserved_at_a0[0x8];
e281682b
SM		 6379 u8 table_id[0x18];
6380
b4ff3a36 6381 u8 reserved_at_c0[0x40];
e281682b
SM		 6382
6383 u8 flow_index[0x20];
6384
b4ff3a36 6385 u8 reserved_at_120[0xe0];
e281682b
SM		 6386};
6387
6388struct mlx5_ifc_dealloc_xrcd_out_bits {
6389 u8 status[0x8];
b4ff3a36 6390 u8 reserved_at_8[0x18];
e281682b
SM		 6391
6392 u8 syndrome[0x20];
6393
b4ff3a36 6394 u8 reserved_at_40[0x40];
e281682b
SM		 6395};
6396
6397struct mlx5_ifc_dealloc_xrcd_in_bits {
6398 u8 opcode[0x10];
b4ff3a36 6399 u8 reserved_at_10[0x10];
e281682b 6400
b4ff3a36 6401 u8 reserved_at_20[0x10];
e281682b
SM		 6402 u8 op_mod[0x10];
6403
b4ff3a36 6404 u8 reserved_at_40[0x8];
e281682b
SM		 6405 u8 xrcd[0x18];
6406
b4ff3a36 6407 u8 reserved_at_60[0x20];
e281682b
SM		 6408};
6409
6410struct mlx5_ifc_dealloc_uar_out_bits {
6411 u8 status[0x8];
b4ff3a36 6412 u8 reserved_at_8[0x18];
e281682b
SM		 6413
6414 u8 syndrome[0x20];
6415
b4ff3a36 6416 u8 reserved_at_40[0x40];
e281682b
SM		 6417};
6418
6419struct mlx5_ifc_dealloc_uar_in_bits {
6420 u8 opcode[0x10];
b4ff3a36 6421 u8 reserved_at_10[0x10];
e281682b 6422
b4ff3a36 6423 u8 reserved_at_20[0x10];
e281682b
SM		 6424 u8 op_mod[0x10];
6425
b4ff3a36 6426 u8 reserved_at_40[0x8];
e281682b
SM		 6427 u8 uar[0x18];
6428
b4ff3a36 6429 u8 reserved_at_60[0x20];
e281682b
SM		 6430};
6431
6432struct mlx5_ifc_dealloc_transport_domain_out_bits {
6433 u8 status[0x8];
b4ff3a36 6434 u8 reserved_at_8[0x18];
e281682b
SM		 6435
6436 u8 syndrome[0x20];
6437
b4ff3a36 6438 u8 reserved_at_40[0x40];
e281682b
SM		 6439};
6440
6441struct mlx5_ifc_dealloc_transport_domain_in_bits {
6442 u8 opcode[0x10];
b4ff3a36 6443 u8 reserved_at_10[0x10];
e281682b 6444
b4ff3a36 6445 u8 reserved_at_20[0x10];
e281682b
SM		 6446 u8 op_mod[0x10];
6447
b4ff3a36 6448 u8 reserved_at_40[0x8];
e281682b
SM		 6449 u8 transport_domain[0x18];
6450
b4ff3a36 6451 u8 reserved_at_60[0x20];
e281682b
SM		 6452};
6453
6454struct mlx5_ifc_dealloc_q_counter_out_bits {
6455 u8 status[0x8];
b4ff3a36 6456 u8 reserved_at_8[0x18];
e281682b
SM		 6457
6458 u8 syndrome[0x20];
6459
b4ff3a36 6460 u8 reserved_at_40[0x40];
e281682b
SM		 6461};
6462
6463struct mlx5_ifc_dealloc_q_counter_in_bits {
6464 u8 opcode[0x10];
b4ff3a36 6465 u8 reserved_at_10[0x10];
e281682b 6466
b4ff3a36 6467 u8 reserved_at_20[0x10];
e281682b
SM		 6468 u8 op_mod[0x10];
6469
b4ff3a36 6470 u8 reserved_at_40[0x18];
e281682b
SM		 6471 u8 counter_set_id[0x8];
6472
b4ff3a36 6473 u8 reserved_at_60[0x20];
e281682b
SM		 6474};
6475
6476struct mlx5_ifc_dealloc_pd_out_bits {
6477 u8 status[0x8];
b4ff3a36 6478 u8 reserved_at_8[0x18];
e281682b
SM		 6479
6480 u8 syndrome[0x20];
6481
b4ff3a36 6482 u8 reserved_at_40[0x40];
e281682b
SM		 6483};
6484
6485struct mlx5_ifc_dealloc_pd_in_bits {
6486 u8 opcode[0x10];
b4ff3a36 6487 u8 reserved_at_10[0x10];
e281682b 6488
b4ff3a36 6489 u8 reserved_at_20[0x10];
e281682b
SM		 6490 u8 op_mod[0x10];
6491
b4ff3a36 6492 u8 reserved_at_40[0x8];
e281682b
SM		 6493 u8 pd[0x18];
6494
b4ff3a36 6495 u8 reserved_at_60[0x20];
e281682b
SM		 6496};
6497
9dc0b289
AV		 6498struct mlx5_ifc_dealloc_flow_counter_out_bits {
6499 u8 status[0x8];
6500 u8 reserved_at_8[0x18];
6501
6502 u8 syndrome[0x20];
6503
6504 u8 reserved_at_40[0x40];
6505};
6506
6507struct mlx5_ifc_dealloc_flow_counter_in_bits {
6508 u8 opcode[0x10];
6509 u8 reserved_at_10[0x10];
6510
6511 u8 reserved_at_20[0x10];
6512 u8 op_mod[0x10];
6513
a8ffcc74 6514 u8 flow_counter_id[0x20];
9dc0b289
AV		 6515
6516 u8 reserved_at_60[0x20];
6517};
6518
7486216b
SM		 6519struct mlx5_ifc_create_xrq_out_bits {
6520 u8 status[0x8];
6521 u8 reserved_at_8[0x18];
6522
6523 u8 syndrome[0x20];
6524
6525 u8 reserved_at_40[0x8];
6526 u8 xrqn[0x18];
6527
6528 u8 reserved_at_60[0x20];
6529};
6530
6531struct mlx5_ifc_create_xrq_in_bits {
6532 u8 opcode[0x10];
6533 u8 reserved_at_10[0x10];
6534
6535 u8 reserved_at_20[0x10];
6536 u8 op_mod[0x10];
6537
6538 u8 reserved_at_40[0x40];
6539
6540 struct mlx5_ifc_xrqc_bits xrq_context;
6541};
6542
e281682b
SM		 6543struct mlx5_ifc_create_xrc_srq_out_bits {
6544 u8 status[0x8];
b4ff3a36 6545 u8 reserved_at_8[0x18];
e281682b
SM		 6546
6547 u8 syndrome[0x20];
6548
b4ff3a36 6549 u8 reserved_at_40[0x8];
e281682b
SM		 6550 u8 xrc_srqn[0x18];
6551
b4ff3a36 6552 u8 reserved_at_60[0x20];
e281682b
SM		 6553};
6554
6555struct mlx5_ifc_create_xrc_srq_in_bits {
6556 u8 opcode[0x10];
b4ff3a36 6557 u8 reserved_at_10[0x10];
e281682b 6558
b4ff3a36 6559 u8 reserved_at_20[0x10];
e281682b
SM		 6560 u8 op_mod[0x10];
6561
b4ff3a36 6562 u8 reserved_at_40[0x40];
e281682b
SM		 6563
6564 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6565
b4ff3a36 6566 u8 reserved_at_280[0x600];
e281682b
SM		 6567
6568 u8 pas[0][0x40];
6569};
6570
6571struct mlx5_ifc_create_tis_out_bits {
6572 u8 status[0x8];
b4ff3a36 6573 u8 reserved_at_8[0x18];
e281682b
SM		 6574
6575 u8 syndrome[0x20];
6576
b4ff3a36 6577 u8 reserved_at_40[0x8];
e281682b
SM		 6578 u8 tisn[0x18];
6579
b4ff3a36 6580 u8 reserved_at_60[0x20];
e281682b
SM		 6581};
6582
6583struct mlx5_ifc_create_tis_in_bits {
6584 u8 opcode[0x10];
b4ff3a36 6585 u8 reserved_at_10[0x10];
e281682b 6586
b4ff3a36 6587 u8 reserved_at_20[0x10];
e281682b
SM		 6588 u8 op_mod[0x10];
6589
b4ff3a36 6590 u8 reserved_at_40[0xc0];
e281682b
SM		 6591
6592 struct mlx5_ifc_tisc_bits ctx;
6593};
6594
6595struct mlx5_ifc_create_tir_out_bits {
6596 u8 status[0x8];
b4ff3a36 6597 u8 reserved_at_8[0x18];
e281682b
SM		 6598
6599 u8 syndrome[0x20];
6600
b4ff3a36 6601 u8 reserved_at_40[0x8];
e281682b
SM		 6602 u8 tirn[0x18];
6603
b4ff3a36 6604 u8 reserved_at_60[0x20];
e281682b
SM		 6605};
6606
6607struct mlx5_ifc_create_tir_in_bits {
6608 u8 opcode[0x10];
b4ff3a36 6609 u8 reserved_at_10[0x10];
e281682b 6610
b4ff3a36 6611 u8 reserved_at_20[0x10];
e281682b
SM		 6612 u8 op_mod[0x10];
6613
b4ff3a36 6614 u8 reserved_at_40[0xc0];
e281682b
SM		 6615
6616 struct mlx5_ifc_tirc_bits ctx;
6617};
6618
6619struct mlx5_ifc_create_srq_out_bits {
6620 u8 status[0x8];
b4ff3a36 6621 u8 reserved_at_8[0x18];
e281682b
SM		 6622
6623 u8 syndrome[0x20];
6624
b4ff3a36 6625 u8 reserved_at_40[0x8];
e281682b
SM		 6626 u8 srqn[0x18];
6627
b4ff3a36 6628 u8 reserved_at_60[0x20];
e281682b
SM		 6629};
6630
6631struct mlx5_ifc_create_srq_in_bits {
6632 u8 opcode[0x10];
b4ff3a36 6633 u8 reserved_at_10[0x10];
e281682b 6634
b4ff3a36 6635 u8 reserved_at_20[0x10];
e281682b
SM		 6636 u8 op_mod[0x10];
6637
b4ff3a36 6638 u8 reserved_at_40[0x40];
e281682b
SM		 6639
6640 struct mlx5_ifc_srqc_bits srq_context_entry;
6641
b4ff3a36 6642 u8 reserved_at_280[0x600];
e281682b
SM		 6643
6644 u8 pas[0][0x40];
6645};
6646
6647struct mlx5_ifc_create_sq_out_bits {
6648 u8 status[0x8];
b4ff3a36 6649 u8 reserved_at_8[0x18];
e281682b
SM		 6650
6651 u8 syndrome[0x20];
6652
b4ff3a36 6653 u8 reserved_at_40[0x8];
e281682b
SM		 6654 u8 sqn[0x18];
6655
b4ff3a36 6656 u8 reserved_at_60[0x20];
e281682b
SM		 6657};
6658
6659struct mlx5_ifc_create_sq_in_bits {
6660 u8 opcode[0x10];
b4ff3a36 6661 u8 reserved_at_10[0x10];
e281682b 6662
b4ff3a36 6663 u8 reserved_at_20[0x10];
e281682b
SM		 6664 u8 op_mod[0x10];
6665
b4ff3a36 6666 u8 reserved_at_40[0xc0];
e281682b
SM		 6667
6668 struct mlx5_ifc_sqc_bits ctx;
6669};
6670
813f8540
MHY		 6671struct mlx5_ifc_create_scheduling_element_out_bits {
6672 u8 status[0x8];
6673 u8 reserved_at_8[0x18];
6674
6675 u8 syndrome[0x20];
6676
6677 u8 reserved_at_40[0x40];
6678
6679 u8 scheduling_element_id[0x20];
6680
6681 u8 reserved_at_a0[0x160];
6682};
6683
6684struct mlx5_ifc_create_scheduling_element_in_bits {
6685 u8 opcode[0x10];
6686 u8 reserved_at_10[0x10];
6687
6688 u8 reserved_at_20[0x10];
6689 u8 op_mod[0x10];
6690
6691 u8 scheduling_hierarchy[0x8];
6692 u8 reserved_at_48[0x18];
6693
6694 u8 reserved_at_60[0xa0];
6695
6696 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6697
6698 u8 reserved_at_300[0x100];
6699};
6700
e281682b
SM		 6701struct mlx5_ifc_create_rqt_out_bits {
6702 u8 status[0x8];
b4ff3a36 6703 u8 reserved_at_8[0x18];
e281682b
SM		 6704
6705 u8 syndrome[0x20];
6706
b4ff3a36 6707 u8 reserved_at_40[0x8];
e281682b
SM		 6708 u8 rqtn[0x18];
6709
b4ff3a36 6710 u8 reserved_at_60[0x20];
e281682b
SM		 6711};
6712
6713struct mlx5_ifc_create_rqt_in_bits {
6714 u8 opcode[0x10];
b4ff3a36 6715 u8 reserved_at_10[0x10];
e281682b 6716
b4ff3a36 6717 u8 reserved_at_20[0x10];
e281682b
SM		 6718 u8 op_mod[0x10];
6719
b4ff3a36 6720 u8 reserved_at_40[0xc0];
e281682b
SM		 6721
6722 struct mlx5_ifc_rqtc_bits rqt_context;
6723};
6724
6725struct mlx5_ifc_create_rq_out_bits {
6726 u8 status[0x8];
b4ff3a36 6727 u8 reserved_at_8[0x18];
e281682b
SM		 6728
6729 u8 syndrome[0x20];
6730
b4ff3a36 6731 u8 reserved_at_40[0x8];
e281682b
SM		 6732 u8 rqn[0x18];
6733
b4ff3a36 6734 u8 reserved_at_60[0x20];
e281682b
SM		 6735};
6736
6737struct mlx5_ifc_create_rq_in_bits {
6738 u8 opcode[0x10];
b4ff3a36 6739 u8 reserved_at_10[0x10];
e281682b 6740
b4ff3a36 6741 u8 reserved_at_20[0x10];
e281682b
SM		 6742 u8 op_mod[0x10];
6743
b4ff3a36 6744 u8 reserved_at_40[0xc0];
e281682b
SM		 6745
6746 struct mlx5_ifc_rqc_bits ctx;
6747};
6748
6749struct mlx5_ifc_create_rmp_out_bits {
6750 u8 status[0x8];
b4ff3a36 6751 u8 reserved_at_8[0x18];
e281682b
SM		 6752
6753 u8 syndrome[0x20];
6754
b4ff3a36 6755 u8 reserved_at_40[0x8];
e281682b
SM		 6756 u8 rmpn[0x18];
6757
b4ff3a36 6758 u8 reserved_at_60[0x20];
e281682b
SM		 6759};
6760
6761struct mlx5_ifc_create_rmp_in_bits {
6762 u8 opcode[0x10];
b4ff3a36 6763 u8 reserved_at_10[0x10];
e281682b 6764
b4ff3a36 6765 u8 reserved_at_20[0x10];
e281682b
SM		 6766 u8 op_mod[0x10];
6767
b4ff3a36 6768 u8 reserved_at_40[0xc0];
e281682b
SM		 6769
6770 struct mlx5_ifc_rmpc_bits ctx;
6771};
6772
6773struct mlx5_ifc_create_qp_out_bits {
6774 u8 status[0x8];
b4ff3a36 6775 u8 reserved_at_8[0x18];
e281682b
SM		 6776
6777 u8 syndrome[0x20];
6778
b4ff3a36 6779 u8 reserved_at_40[0x8];
e281682b
SM		 6780 u8 qpn[0x18];
6781
b4ff3a36 6782 u8 reserved_at_60[0x20];
e281682b
SM		 6783};
6784
6785struct mlx5_ifc_create_qp_in_bits {
6786 u8 opcode[0x10];
b4ff3a36 6787 u8 reserved_at_10[0x10];
e281682b 6788
b4ff3a36 6789 u8 reserved_at_20[0x10];
e281682b
SM		 6790 u8 op_mod[0x10];
6791
b4ff3a36 6792 u8 reserved_at_40[0x40];
e281682b
SM		 6793
6794 u8 opt_param_mask[0x20];
6795
b4ff3a36 6796 u8 reserved_at_a0[0x20];
e281682b
SM		 6797
6798 struct mlx5_ifc_qpc_bits qpc;
6799
b4ff3a36 6800 u8 reserved_at_800[0x80];
e281682b
SM		 6801
6802 u8 pas[0][0x40];
6803};
6804
6805struct mlx5_ifc_create_psv_out_bits {
6806 u8 status[0x8];
b4ff3a36 6807 u8 reserved_at_8[0x18];
e281682b
SM		 6808
6809 u8 syndrome[0x20];
6810
b4ff3a36 6811 u8 reserved_at_40[0x40];
e281682b 6812
b4ff3a36 6813 u8 reserved_at_80[0x8];
e281682b
SM		 6814 u8 psv0_index[0x18];
6815
b4ff3a36 6816 u8 reserved_at_a0[0x8];
e281682b
SM		 6817 u8 psv1_index[0x18];
6818
b4ff3a36 6819 u8 reserved_at_c0[0x8];
e281682b
SM		 6820 u8 psv2_index[0x18];
6821
b4ff3a36 6822 u8 reserved_at_e0[0x8];
e281682b
SM		 6823 u8 psv3_index[0x18];
6824};
6825
6826struct mlx5_ifc_create_psv_in_bits {
6827 u8 opcode[0x10];
b4ff3a36 6828 u8 reserved_at_10[0x10];
e281682b 6829
b4ff3a36 6830 u8 reserved_at_20[0x10];
e281682b
SM		 6831 u8 op_mod[0x10];
6832
6833 u8 num_psv[0x4];
b4ff3a36 6834 u8 reserved_at_44[0x4];
e281682b
SM		 6835 u8 pd[0x18];
6836
b4ff3a36 6837 u8 reserved_at_60[0x20];
e281682b
SM		 6838};
6839
6840struct mlx5_ifc_create_mkey_out_bits {
6841 u8 status[0x8];
b4ff3a36 6842 u8 reserved_at_8[0x18];
e281682b
SM		 6843
6844 u8 syndrome[0x20];
6845
b4ff3a36 6846 u8 reserved_at_40[0x8];
e281682b
SM		 6847 u8 mkey_index[0x18];
6848
b4ff3a36 6849 u8 reserved_at_60[0x20];
e281682b
SM		 6850};
6851
6852struct mlx5_ifc_create_mkey_in_bits {
6853 u8 opcode[0x10];
b4ff3a36 6854 u8 reserved_at_10[0x10];
e281682b 6855
b4ff3a36 6856 u8 reserved_at_20[0x10];
e281682b
SM		 6857 u8 op_mod[0x10];
6858
b4ff3a36 6859 u8 reserved_at_40[0x20];
e281682b
SM		 6860
6861 u8 pg_access[0x1];
b4ff3a36 6862 u8 reserved_at_61[0x1f];
e281682b
SM		 6863
6864 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6865
b4ff3a36 6866 u8 reserved_at_280[0x80];
e281682b
SM		 6867
6868 u8 translations_octword_actual_size[0x20];
6869
b4ff3a36 6870 u8 reserved_at_320[0x560];
e281682b
SM		 6871
6872 u8 klm_pas_mtt[0][0x20];
6873};
6874
6875struct mlx5_ifc_create_flow_table_out_bits {
6876 u8 status[0x8];
b4ff3a36 6877 u8 reserved_at_8[0x18];
e281682b
SM		 6878
6879 u8 syndrome[0x20];
6880
b4ff3a36 6881 u8 reserved_at_40[0x8];
e281682b
SM		 6882 u8 table_id[0x18];
6883
b4ff3a36 6884 u8 reserved_at_60[0x20];
e281682b
SM		 6885};
6886
0c90e9c6
MG		 6887struct mlx5_ifc_flow_table_context_bits {
6888 u8 encap_en[0x1];
6889 u8 decap_en[0x1];
6890 u8 reserved_at_2[0x2];
6891 u8 table_miss_action[0x4];
6892 u8 level[0x8];
6893 u8 reserved_at_10[0x8];
6894 u8 log_size[0x8];
6895
6896 u8 reserved_at_20[0x8];
6897 u8 table_miss_id[0x18];
6898
6899 u8 reserved_at_40[0x8];
6900 u8 lag_master_next_table_id[0x18];
6901
6902 u8 reserved_at_60[0xe0];
6903};
6904
e281682b
SM		 6905struct mlx5_ifc_create_flow_table_in_bits {
6906 u8 opcode[0x10];
b4ff3a36 6907 u8 reserved_at_10[0x10];
e281682b 6908
b4ff3a36 6909 u8 reserved_at_20[0x10];
e281682b
SM		 6910 u8 op_mod[0x10];
6911
7d5e1423
SM		 6912 u8 other_vport[0x1];
6913 u8 reserved_at_41[0xf];
6914 u8 vport_number[0x10];
6915
6916 u8 reserved_at_60[0x20];
e281682b
SM		 6917
6918 u8 table_type[0x8];
b4ff3a36 6919 u8 reserved_at_88[0x18];
e281682b 6920
b4ff3a36 6921 u8 reserved_at_a0[0x20];
e281682b 6922
0c90e9c6 6923 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6924};
6925
6926struct mlx5_ifc_create_flow_group_out_bits {
6927 u8 status[0x8];
b4ff3a36 6928 u8 reserved_at_8[0x18];
e281682b
SM		 6929
6930 u8 syndrome[0x20];
6931
b4ff3a36 6932 u8 reserved_at_40[0x8];
e281682b
SM		 6933 u8 group_id[0x18];
6934
b4ff3a36 6935 u8 reserved_at_60[0x20];
e281682b
SM		 6936};
6937
6938enum {
6939 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6940 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6941 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6942};
6943
6944struct mlx5_ifc_create_flow_group_in_bits {
6945 u8 opcode[0x10];
b4ff3a36 6946 u8 reserved_at_10[0x10];
e281682b 6947
b4ff3a36 6948 u8 reserved_at_20[0x10];
e281682b
SM		 6949 u8 op_mod[0x10];
6950
7d5e1423
SM		 6951 u8 other_vport[0x1];
6952 u8 reserved_at_41[0xf];
6953 u8 vport_number[0x10];
6954
6955 u8 reserved_at_60[0x20];
e281682b
SM		 6956
6957 u8 table_type[0x8];
b4ff3a36 6958 u8 reserved_at_88[0x18];
e281682b 6959
b4ff3a36 6960 u8 reserved_at_a0[0x8];
e281682b
SM		 6961 u8 table_id[0x18];
6962
b4ff3a36 6963 u8 reserved_at_c0[0x20];
e281682b
SM		 6964
6965 u8 start_flow_index[0x20];
6966
b4ff3a36 6967 u8 reserved_at_100[0x20];
e281682b
SM		 6968
6969 u8 end_flow_index[0x20];
6970
b4ff3a36 6971 u8 reserved_at_140[0xa0];
e281682b 6972
b4ff3a36 6973 u8 reserved_at_1e0[0x18];
e281682b
SM		 6974 u8 match_criteria_enable[0x8];
6975
6976 struct mlx5_ifc_fte_match_param_bits match_criteria;
6977
b4ff3a36 6978 u8 reserved_at_1200[0xe00];
e281682b
SM		 6979};
6980
6981struct mlx5_ifc_create_eq_out_bits {
6982 u8 status[0x8];
b4ff3a36 6983 u8 reserved_at_8[0x18];
e281682b
SM		 6984
6985 u8 syndrome[0x20];
6986
b4ff3a36 6987 u8 reserved_at_40[0x18];
e281682b
SM		 6988 u8 eq_number[0x8];
6989
b4ff3a36 6990 u8 reserved_at_60[0x20];
e281682b
SM		 6991};
6992
6993struct mlx5_ifc_create_eq_in_bits {
6994 u8 opcode[0x10];
b4ff3a36 6995 u8 reserved_at_10[0x10];
e281682b 6996
b4ff3a36 6997 u8 reserved_at_20[0x10];
e281682b
SM		 6998 u8 op_mod[0x10];
6999
b4ff3a36 7000 u8 reserved_at_40[0x40];
e281682b
SM		 7001
7002 struct mlx5_ifc_eqc_bits eq_context_entry;
7003
b4ff3a36 7004 u8 reserved_at_280[0x40];
e281682b
SM		 7005
7006 u8 event_bitmask[0x40];
7007
b4ff3a36 7008 u8 reserved_at_300[0x580];
e281682b
SM		 7009
7010 u8 pas[0][0x40];
7011};
7012
7013struct mlx5_ifc_create_dct_out_bits {
7014 u8 status[0x8];
b4ff3a36 7015 u8 reserved_at_8[0x18];
e281682b
SM		 7016
7017 u8 syndrome[0x20];
7018
b4ff3a36 7019 u8 reserved_at_40[0x8];
e281682b
SM		 7020 u8 dctn[0x18];
7021
b4ff3a36 7022 u8 reserved_at_60[0x20];
e281682b
SM		 7023};
7024
7025struct mlx5_ifc_create_dct_in_bits {
7026 u8 opcode[0x10];
b4ff3a36 7027 u8 reserved_at_10[0x10];
e281682b 7028
b4ff3a36 7029 u8 reserved_at_20[0x10];
e281682b
SM		 7030 u8 op_mod[0x10];
7031
b4ff3a36 7032 u8 reserved_at_40[0x40];
e281682b
SM		 7033
7034 struct mlx5_ifc_dctc_bits dct_context_entry;
7035
b4ff3a36 7036 u8 reserved_at_280[0x180];
e281682b
SM		 7037};
7038
7039struct mlx5_ifc_create_cq_out_bits {
7040 u8 status[0x8];
b4ff3a36 7041 u8 reserved_at_8[0x18];
e281682b
SM		 7042
7043 u8 syndrome[0x20];
7044
b4ff3a36 7045 u8 reserved_at_40[0x8];
e281682b
SM		 7046 u8 cqn[0x18];
7047
b4ff3a36 7048 u8 reserved_at_60[0x20];
e281682b
SM		 7049};
7050
7051struct mlx5_ifc_create_cq_in_bits {
7052 u8 opcode[0x10];
b4ff3a36 7053 u8 reserved_at_10[0x10];
e281682b 7054
b4ff3a36 7055 u8 reserved_at_20[0x10];
e281682b
SM		 7056 u8 op_mod[0x10];
7057
b4ff3a36 7058 u8 reserved_at_40[0x40];
e281682b
SM		 7059
7060 struct mlx5_ifc_cqc_bits cq_context;
7061
b4ff3a36 7062 u8 reserved_at_280[0x600];
e281682b
SM		 7063
7064 u8 pas[0][0x40];
7065};
7066
7067struct mlx5_ifc_config_int_moderation_out_bits {
7068 u8 status[0x8];
b4ff3a36 7069 u8 reserved_at_8[0x18];
e281682b
SM		 7070
7071 u8 syndrome[0x20];
7072
b4ff3a36 7073 u8 reserved_at_40[0x4];
e281682b
SM		 7074 u8 min_delay[0xc];
7075 u8 int_vector[0x10];
7076
b4ff3a36 7077 u8 reserved_at_60[0x20];
e281682b
SM		 7078};
7079
7080enum {
7081 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7082 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7083};
7084
7085struct mlx5_ifc_config_int_moderation_in_bits {
7086 u8 opcode[0x10];
b4ff3a36 7087 u8 reserved_at_10[0x10];
e281682b 7088
b4ff3a36 7089 u8 reserved_at_20[0x10];
e281682b
SM		 7090 u8 op_mod[0x10];
7091
b4ff3a36 7092 u8 reserved_at_40[0x4];
e281682b
SM		 7093 u8 min_delay[0xc];
7094 u8 int_vector[0x10];
7095
b4ff3a36 7096 u8 reserved_at_60[0x20];
e281682b
SM		 7097};
7098
7099struct mlx5_ifc_attach_to_mcg_out_bits {
7100 u8 status[0x8];
b4ff3a36 7101 u8 reserved_at_8[0x18];
e281682b
SM		 7102
7103 u8 syndrome[0x20];
7104
b4ff3a36 7105 u8 reserved_at_40[0x40];
e281682b
SM		 7106};
7107
7108struct mlx5_ifc_attach_to_mcg_in_bits {
7109 u8 opcode[0x10];
b4ff3a36 7110 u8 reserved_at_10[0x10];
e281682b 7111
b4ff3a36 7112 u8 reserved_at_20[0x10];
e281682b
SM		 7113 u8 op_mod[0x10];
7114
b4ff3a36 7115 u8 reserved_at_40[0x8];
e281682b
SM		 7116 u8 qpn[0x18];
7117
b4ff3a36 7118 u8 reserved_at_60[0x20];
e281682b
SM		 7119
7120 u8 multicast_gid[16][0x8];
7121};
7122
7486216b
SM		 7123struct mlx5_ifc_arm_xrq_out_bits {
7124 u8 status[0x8];
7125 u8 reserved_at_8[0x18];
7126
7127 u8 syndrome[0x20];
7128
7129 u8 reserved_at_40[0x40];
7130};
7131
7132struct mlx5_ifc_arm_xrq_in_bits {
7133 u8 opcode[0x10];
7134 u8 reserved_at_10[0x10];
7135
7136 u8 reserved_at_20[0x10];
7137 u8 op_mod[0x10];
7138
7139 u8 reserved_at_40[0x8];
7140 u8 xrqn[0x18];
7141
7142 u8 reserved_at_60[0x10];
7143 u8 lwm[0x10];
7144};
7145
e281682b
SM		 7146struct mlx5_ifc_arm_xrc_srq_out_bits {
7147 u8 status[0x8];
b4ff3a36 7148 u8 reserved_at_8[0x18];
e281682b
SM		 7149
7150 u8 syndrome[0x20];
7151
b4ff3a36 7152 u8 reserved_at_40[0x40];
e281682b
SM		 7153};
7154
7155enum {
7156 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7157};
7158
7159struct mlx5_ifc_arm_xrc_srq_in_bits {
7160 u8 opcode[0x10];
b4ff3a36 7161 u8 reserved_at_10[0x10];
e281682b 7162
b4ff3a36 7163 u8 reserved_at_20[0x10];
e281682b
SM		 7164 u8 op_mod[0x10];
7165
b4ff3a36 7166 u8 reserved_at_40[0x8];
e281682b
SM		 7167 u8 xrc_srqn[0x18];
7168
b4ff3a36 7169 u8 reserved_at_60[0x10];
e281682b
SM		 7170 u8 lwm[0x10];
7171};
7172
7173struct mlx5_ifc_arm_rq_out_bits {
7174 u8 status[0x8];
b4ff3a36 7175 u8 reserved_at_8[0x18];
e281682b
SM		 7176
7177 u8 syndrome[0x20];
7178
b4ff3a36 7179 u8 reserved_at_40[0x40];
e281682b
SM		 7180};
7181
7182enum {
7486216b
SM		 7183 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7184 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7185};
7186
7187struct mlx5_ifc_arm_rq_in_bits {
7188 u8 opcode[0x10];
b4ff3a36 7189 u8 reserved_at_10[0x10];
e281682b 7190
b4ff3a36 7191 u8 reserved_at_20[0x10];
e281682b
SM		 7192 u8 op_mod[0x10];
7193
b4ff3a36 7194 u8 reserved_at_40[0x8];
e281682b
SM		 7195 u8 srq_number[0x18];
7196
b4ff3a36 7197 u8 reserved_at_60[0x10];
e281682b
SM		 7198 u8 lwm[0x10];
7199};
7200
7201struct mlx5_ifc_arm_dct_out_bits {
7202 u8 status[0x8];
b4ff3a36 7203 u8 reserved_at_8[0x18];
e281682b
SM		 7204
7205 u8 syndrome[0x20];
7206
b4ff3a36 7207 u8 reserved_at_40[0x40];
e281682b
SM		 7208};
7209
7210struct mlx5_ifc_arm_dct_in_bits {
7211 u8 opcode[0x10];
b4ff3a36 7212 u8 reserved_at_10[0x10];
e281682b 7213
b4ff3a36 7214 u8 reserved_at_20[0x10];
e281682b
SM		 7215 u8 op_mod[0x10];
7216
b4ff3a36 7217 u8 reserved_at_40[0x8];
e281682b
SM		 7218 u8 dct_number[0x18];
7219
b4ff3a36 7220 u8 reserved_at_60[0x20];
e281682b
SM		 7221};
7222
7223struct mlx5_ifc_alloc_xrcd_out_bits {
7224 u8 status[0x8];
b4ff3a36 7225 u8 reserved_at_8[0x18];
e281682b
SM		 7226
7227 u8 syndrome[0x20];
7228
b4ff3a36 7229 u8 reserved_at_40[0x8];
e281682b
SM		 7230 u8 xrcd[0x18];
7231
b4ff3a36 7232 u8 reserved_at_60[0x20];
e281682b
SM		 7233};
7234
7235struct mlx5_ifc_alloc_xrcd_in_bits {
7236 u8 opcode[0x10];
b4ff3a36 7237 u8 reserved_at_10[0x10];
e281682b 7238
b4ff3a36 7239 u8 reserved_at_20[0x10];
e281682b
SM		 7240 u8 op_mod[0x10];
7241
b4ff3a36 7242 u8 reserved_at_40[0x40];
e281682b
SM		 7243};
7244
7245struct mlx5_ifc_alloc_uar_out_bits {
7246 u8 status[0x8];
b4ff3a36 7247 u8 reserved_at_8[0x18];
e281682b
SM		 7248
7249 u8 syndrome[0x20];
7250
b4ff3a36 7251 u8 reserved_at_40[0x8];
e281682b
SM		 7252 u8 uar[0x18];
7253
b4ff3a36 7254 u8 reserved_at_60[0x20];
e281682b
SM		 7255};
7256
7257struct mlx5_ifc_alloc_uar_in_bits {
7258 u8 opcode[0x10];
b4ff3a36 7259 u8 reserved_at_10[0x10];
e281682b 7260
b4ff3a36 7261 u8 reserved_at_20[0x10];
e281682b
SM		 7262 u8 op_mod[0x10];
7263
b4ff3a36 7264 u8 reserved_at_40[0x40];
e281682b
SM		 7265};
7266
7267struct mlx5_ifc_alloc_transport_domain_out_bits {
7268 u8 status[0x8];
b4ff3a36 7269 u8 reserved_at_8[0x18];
e281682b
SM		 7270
7271 u8 syndrome[0x20];
7272
b4ff3a36 7273 u8 reserved_at_40[0x8];
e281682b
SM		 7274 u8 transport_domain[0x18];
7275
b4ff3a36 7276 u8 reserved_at_60[0x20];
e281682b
SM		 7277};
7278
7279struct mlx5_ifc_alloc_transport_domain_in_bits {
7280 u8 opcode[0x10];
b4ff3a36 7281 u8 reserved_at_10[0x10];
e281682b 7282
b4ff3a36 7283 u8 reserved_at_20[0x10];
e281682b
SM		 7284 u8 op_mod[0x10];
7285
b4ff3a36 7286 u8 reserved_at_40[0x40];
e281682b
SM		 7287};
7288
7289struct mlx5_ifc_alloc_q_counter_out_bits {
7290 u8 status[0x8];
b4ff3a36 7291 u8 reserved_at_8[0x18];
e281682b
SM		 7292
7293 u8 syndrome[0x20];
7294
b4ff3a36 7295 u8 reserved_at_40[0x18];
e281682b
SM		 7296 u8 counter_set_id[0x8];
7297
b4ff3a36 7298 u8 reserved_at_60[0x20];
e281682b
SM		 7299};
7300
7301struct mlx5_ifc_alloc_q_counter_in_bits {
7302 u8 opcode[0x10];
b4ff3a36 7303 u8 reserved_at_10[0x10];
e281682b 7304
b4ff3a36 7305 u8 reserved_at_20[0x10];
e281682b
SM		 7306 u8 op_mod[0x10];
7307
b4ff3a36 7308 u8 reserved_at_40[0x40];
e281682b
SM		 7309};
7310
7311struct mlx5_ifc_alloc_pd_out_bits {
7312 u8 status[0x8];
b4ff3a36 7313 u8 reserved_at_8[0x18];
e281682b
SM		 7314
7315 u8 syndrome[0x20];
7316
b4ff3a36 7317 u8 reserved_at_40[0x8];
e281682b
SM		 7318 u8 pd[0x18];
7319
b4ff3a36 7320 u8 reserved_at_60[0x20];
e281682b
SM		 7321};
7322
7323struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7324 u8 opcode[0x10];
7325 u8 reserved_at_10[0x10];
7326
7327 u8 reserved_at_20[0x10];
7328 u8 op_mod[0x10];
7329
7330 u8 reserved_at_40[0x40];
7331};
7332
7333struct mlx5_ifc_alloc_flow_counter_out_bits {
7334 u8 status[0x8];
7335 u8 reserved_at_8[0x18];
7336
7337 u8 syndrome[0x20];
7338
a8ffcc74 7339 u8 flow_counter_id[0x20];
9dc0b289
AV		 7340
7341 u8 reserved_at_60[0x20];
7342};
7343
7344struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7345 u8 opcode[0x10];
b4ff3a36 7346 u8 reserved_at_10[0x10];
e281682b 7347
b4ff3a36 7348 u8 reserved_at_20[0x10];
e281682b
SM		 7349 u8 op_mod[0x10];
7350
b4ff3a36 7351 u8 reserved_at_40[0x40];
e281682b
SM		 7352};
7353
7354struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7355 u8 status[0x8];
b4ff3a36 7356 u8 reserved_at_8[0x18];
e281682b
SM		 7357
7358 u8 syndrome[0x20];
7359
b4ff3a36 7360 u8 reserved_at_40[0x40];
e281682b
SM		 7361};
7362
7363struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7364 u8 opcode[0x10];
b4ff3a36 7365 u8 reserved_at_10[0x10];
e281682b 7366
b4ff3a36 7367 u8 reserved_at_20[0x10];
e281682b
SM		 7368 u8 op_mod[0x10];
7369
b4ff3a36 7370 u8 reserved_at_40[0x20];
e281682b 7371
b4ff3a36 7372 u8 reserved_at_60[0x10];
e281682b
SM		 7373 u8 vxlan_udp_port[0x10];
7374};
7375
37e92a9d 7376struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7377 u8 status[0x8];
7378 u8 reserved_at_8[0x18];
7379
7380 u8 syndrome[0x20];
7381
7382 u8 reserved_at_40[0x40];
7383};
7384
37e92a9d 7385struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7386 u8 opcode[0x10];
7387 u8 reserved_at_10[0x10];
7388
7389 u8 reserved_at_20[0x10];
7390 u8 op_mod[0x10];
7391
7392 u8 reserved_at_40[0x10];
7393 u8 rate_limit_index[0x10];
7394
7395 u8 reserved_at_60[0x20];
7396
7397 u8 rate_limit[0x20];
37e92a9d
EBE		 7398
7399 u8 reserved_at_a0[0x160];
7486216b
SM		 7400};
7401
e281682b
SM		 7402struct mlx5_ifc_access_register_out_bits {
7403 u8 status[0x8];
b4ff3a36 7404 u8 reserved_at_8[0x18];
e281682b
SM		 7405
7406 u8 syndrome[0x20];
7407
b4ff3a36 7408 u8 reserved_at_40[0x40];
e281682b
SM		 7409
7410 u8 register_data[0][0x20];
7411};
7412
7413enum {
7414 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7415 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7416};
7417
7418struct mlx5_ifc_access_register_in_bits {
7419 u8 opcode[0x10];
b4ff3a36 7420 u8 reserved_at_10[0x10];
e281682b 7421
b4ff3a36 7422 u8 reserved_at_20[0x10];
e281682b
SM		 7423 u8 op_mod[0x10];
7424
b4ff3a36 7425 u8 reserved_at_40[0x10];
e281682b
SM		 7426 u8 register_id[0x10];
7427
7428 u8 argument[0x20];
7429
7430 u8 register_data[0][0x20];
7431};
7432
7433struct mlx5_ifc_sltp_reg_bits {
7434 u8 status[0x4];
7435 u8 version[0x4];
7436 u8 local_port[0x8];
7437 u8 pnat[0x2];
b4ff3a36 7438 u8 reserved_at_12[0x2];
e281682b 7439 u8 lane[0x4];
b4ff3a36 7440 u8 reserved_at_18[0x8];
e281682b 7441
b4ff3a36 7442 u8 reserved_at_20[0x20];
e281682b 7443
b4ff3a36 7444 u8 reserved_at_40[0x7];
e281682b
SM		 7445 u8 polarity[0x1];
7446 u8 ob_tap0[0x8];
7447 u8 ob_tap1[0x8];
7448 u8 ob_tap2[0x8];
7449
b4ff3a36 7450 u8 reserved_at_60[0xc];
e281682b
SM		 7451 u8 ob_preemp_mode[0x4];
7452 u8 ob_reg[0x8];
7453 u8 ob_bias[0x8];
7454
b4ff3a36 7455 u8 reserved_at_80[0x20];
e281682b
SM		 7456};
7457
7458struct mlx5_ifc_slrg_reg_bits {
7459 u8 status[0x4];
7460 u8 version[0x4];
7461 u8 local_port[0x8];
7462 u8 pnat[0x2];
b4ff3a36 7463 u8 reserved_at_12[0x2];
e281682b 7464 u8 lane[0x4];
b4ff3a36 7465 u8 reserved_at_18[0x8];
e281682b
SM		 7466
7467 u8 time_to_link_up[0x10];
b4ff3a36 7468 u8 reserved_at_30[0xc];
e281682b
SM		 7469 u8 grade_lane_speed[0x4];
7470
7471 u8 grade_version[0x8];
7472 u8 grade[0x18];
7473
b4ff3a36 7474 u8 reserved_at_60[0x4];
e281682b
SM		 7475 u8 height_grade_type[0x4];
7476 u8 height_grade[0x18];
7477
7478 u8 height_dz[0x10];
7479 u8 height_dv[0x10];
7480
b4ff3a36 7481 u8 reserved_at_a0[0x10];
e281682b
SM		 7482 u8 height_sigma[0x10];
7483
b4ff3a36 7484 u8 reserved_at_c0[0x20];
e281682b 7485
b4ff3a36 7486 u8 reserved_at_e0[0x4];
e281682b
SM		 7487 u8 phase_grade_type[0x4];
7488 u8 phase_grade[0x18];
7489
b4ff3a36 7490 u8 reserved_at_100[0x8];
e281682b 7491 u8 phase_eo_pos[0x8];
b4ff3a36 7492 u8 reserved_at_110[0x8];
e281682b
SM		 7493 u8 phase_eo_neg[0x8];
7494
7495 u8 ffe_set_tested[0x10];
7496 u8 test_errors_per_lane[0x10];
7497};
7498
7499struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7500 u8 reserved_at_0[0x8];
e281682b 7501 u8 local_port[0x8];
b4ff3a36 7502 u8 reserved_at_10[0x10];
e281682b 7503
b4ff3a36 7504 u8 reserved_at_20[0x1c];
e281682b
SM		 7505 u8 vl_hw_cap[0x4];
7506
b4ff3a36 7507 u8 reserved_at_40[0x1c];
e281682b
SM		 7508 u8 vl_admin[0x4];
7509
b4ff3a36 7510 u8 reserved_at_60[0x1c];
e281682b
SM		 7511 u8 vl_operational[0x4];
7512};
7513
7514struct mlx5_ifc_pude_reg_bits {
7515 u8 swid[0x8];
7516 u8 local_port[0x8];
b4ff3a36 7517 u8 reserved_at_10[0x4];
e281682b 7518 u8 admin_status[0x4];
b4ff3a36 7519 u8 reserved_at_18[0x4];
e281682b
SM		 7520 u8 oper_status[0x4];
7521
b4ff3a36 7522 u8 reserved_at_20[0x60];
e281682b
SM		 7523};
7524
7525struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7526 u8 reserved_at_0[0x1];
7486216b 7527 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7528 u8 an_disable_cap[0x1];
7529 u8 reserved_at_3[0x5];
e281682b 7530 u8 local_port[0x8];
b4ff3a36 7531 u8 reserved_at_10[0xd];
e281682b
SM		 7532 u8 proto_mask[0x3];
7533
7486216b
SM		 7534 u8 an_status[0x4];
7535 u8 reserved_at_24[0x3c];
e281682b
SM		 7536
7537 u8 eth_proto_capability[0x20];
7538
7539 u8 ib_link_width_capability[0x10];
7540 u8 ib_proto_capability[0x10];
7541
b4ff3a36 7542 u8 reserved_at_a0[0x20];
e281682b
SM		 7543
7544 u8 eth_proto_admin[0x20];
7545
7546 u8 ib_link_width_admin[0x10];
7547 u8 ib_proto_admin[0x10];
7548
b4ff3a36 7549 u8 reserved_at_100[0x20];
e281682b
SM		 7550
7551 u8 eth_proto_oper[0x20];
7552
7553 u8 ib_link_width_oper[0x10];
7554 u8 ib_proto_oper[0x10];
7555
5b4793f8
EBE		 7556 u8 reserved_at_160[0x1c];
7557 u8 connector_type[0x4];
e281682b
SM		 7558
7559 u8 eth_proto_lp_advertise[0x20];
7560
b4ff3a36 7561 u8 reserved_at_1a0[0x60];
e281682b
SM		 7562};
7563
7d5e1423
SM		 7564struct mlx5_ifc_mlcr_reg_bits {
7565 u8 reserved_at_0[0x8];
7566 u8 local_port[0x8];
7567 u8 reserved_at_10[0x20];
7568
7569 u8 beacon_duration[0x10];
7570 u8 reserved_at_40[0x10];
7571
7572 u8 beacon_remain[0x10];
7573};
7574
e281682b 7575struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7576 u8 reserved_at_0[0x20];
e281682b
SM		 7577
7578 u8 algorithm_options[0x10];
b4ff3a36 7579 u8 reserved_at_30[0x4];
e281682b
SM		 7580 u8 repetitions_mode[0x4];
7581 u8 num_of_repetitions[0x8];
7582
7583 u8 grade_version[0x8];
7584 u8 height_grade_type[0x4];
7585 u8 phase_grade_type[0x4];
7586 u8 height_grade_weight[0x8];
7587 u8 phase_grade_weight[0x8];
7588
7589 u8 gisim_measure_bits[0x10];
7590 u8 adaptive_tap_measure_bits[0x10];
7591
7592 u8 ber_bath_high_error_threshold[0x10];
7593 u8 ber_bath_mid_error_threshold[0x10];
7594
7595 u8 ber_bath_low_error_threshold[0x10];
7596 u8 one_ratio_high_threshold[0x10];
7597
7598 u8 one_ratio_high_mid_threshold[0x10];
7599 u8 one_ratio_low_mid_threshold[0x10];
7600
7601 u8 one_ratio_low_threshold[0x10];
7602 u8 ndeo_error_threshold[0x10];
7603
7604 u8 mixer_offset_step_size[0x10];
b4ff3a36 7605 u8 reserved_at_110[0x8];
e281682b
SM		 7606 u8 mix90_phase_for_voltage_bath[0x8];
7607
7608 u8 mixer_offset_start[0x10];
7609 u8 mixer_offset_end[0x10];
7610
b4ff3a36 7611 u8 reserved_at_140[0x15];
e281682b
SM		 7612 u8 ber_test_time[0xb];
7613};
7614
7615struct mlx5_ifc_pspa_reg_bits {
7616 u8 swid[0x8];
7617 u8 local_port[0x8];
7618 u8 sub_port[0x8];
b4ff3a36 7619 u8 reserved_at_18[0x8];
e281682b 7620
b4ff3a36 7621 u8 reserved_at_20[0x20];
e281682b
SM		 7622};
7623
7624struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7625 u8 reserved_at_0[0x8];
e281682b 7626 u8 local_port[0x8];
b4ff3a36 7627 u8 reserved_at_10[0x5];
e281682b 7628 u8 prio[0x3];
b4ff3a36 7629 u8 reserved_at_18[0x6];
e281682b
SM		 7630 u8 mode[0x2];
7631
b4ff3a36 7632 u8 reserved_at_20[0x20];
e281682b 7633
b4ff3a36 7634 u8 reserved_at_40[0x10];
e281682b
SM		 7635 u8 min_threshold[0x10];
7636
b4ff3a36 7637 u8 reserved_at_60[0x10];
e281682b
SM		 7638 u8 max_threshold[0x10];
7639
b4ff3a36 7640 u8 reserved_at_80[0x10];
e281682b
SM		 7641 u8 mark_probability_denominator[0x10];
7642
b4ff3a36 7643 u8 reserved_at_a0[0x60];
e281682b
SM		 7644};
7645
7646struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7647 u8 reserved_at_0[0x8];
e281682b 7648 u8 local_port[0x8];
b4ff3a36 7649 u8 reserved_at_10[0x10];
e281682b 7650
b4ff3a36 7651 u8 reserved_at_20[0x60];
e281682b 7652
b4ff3a36 7653 u8 reserved_at_80[0x1c];
e281682b
SM		 7654 u8 wrps_admin[0x4];
7655
b4ff3a36 7656 u8 reserved_at_a0[0x1c];
e281682b
SM		 7657 u8 wrps_status[0x4];
7658
b4ff3a36 7659 u8 reserved_at_c0[0x8];
e281682b 7660 u8 up_threshold[0x8];
b4ff3a36 7661 u8 reserved_at_d0[0x8];
e281682b
SM		 7662 u8 down_threshold[0x8];
7663
b4ff3a36 7664 u8 reserved_at_e0[0x20];
e281682b 7665
b4ff3a36 7666 u8 reserved_at_100[0x1c];
e281682b
SM		 7667 u8 srps_admin[0x4];
7668
b4ff3a36 7669 u8 reserved_at_120[0x1c];
e281682b
SM		 7670 u8 srps_status[0x4];
7671
b4ff3a36 7672 u8 reserved_at_140[0x40];
e281682b
SM		 7673};
7674
7675struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7676 u8 reserved_at_0[0x8];
e281682b 7677 u8 local_port[0x8];
b4ff3a36 7678 u8 reserved_at_10[0x10];
e281682b 7679
b4ff3a36 7680 u8 reserved_at_20[0x8];
e281682b 7681 u8 lb_cap[0x8];
b4ff3a36 7682 u8 reserved_at_30[0x8];
e281682b
SM		 7683 u8 lb_en[0x8];
7684};
7685
7686struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7687 u8 reserved_at_0[0x8];
e281682b 7688 u8 local_port[0x8];
b4ff3a36 7689 u8 reserved_at_10[0x10];
e281682b 7690
b4ff3a36 7691 u8 reserved_at_20[0x20];
e281682b
SM		 7692
7693 u8 port_profile_mode[0x8];
7694 u8 static_port_profile[0x8];
7695 u8 active_port_profile[0x8];
b4ff3a36 7696 u8 reserved_at_58[0x8];
e281682b
SM		 7697
7698 u8 retransmission_active[0x8];
7699 u8 fec_mode_active[0x18];
7700
b4ff3a36 7701 u8 reserved_at_80[0x20];
e281682b
SM		 7702};
7703
7704struct mlx5_ifc_ppcnt_reg_bits {
7705 u8 swid[0x8];
7706 u8 local_port[0x8];
7707 u8 pnat[0x2];
b4ff3a36 7708 u8 reserved_at_12[0x8];
e281682b
SM		 7709 u8 grp[0x6];
7710
7711 u8 clr[0x1];
b4ff3a36 7712 u8 reserved_at_21[0x1c];
e281682b
SM		 7713 u8 prio_tc[0x3];
7714
7715 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7716};
7717
8ed1a630
GP		 7718struct mlx5_ifc_mpcnt_reg_bits {
7719 u8 reserved_at_0[0x8];
7720 u8 pcie_index[0x8];
7721 u8 reserved_at_10[0xa];
7722 u8 grp[0x6];
7723
7724 u8 clr[0x1];
7725 u8 reserved_at_21[0x1f];
7726
7727 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7728};
7729
e281682b 7730struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7731 u8 reserved_at_0[0x3];
e281682b 7732 u8 single_mac[0x1];
b4ff3a36 7733 u8 reserved_at_4[0x4];
e281682b
SM		 7734 u8 local_port[0x8];
7735 u8 mac_47_32[0x10];
7736
7737 u8 mac_31_0[0x20];
7738
b4ff3a36 7739 u8 reserved_at_40[0x40];
e281682b
SM		 7740};
7741
7742struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7743 u8 reserved_at_0[0x8];
e281682b 7744 u8 local_port[0x8];
b4ff3a36 7745 u8 reserved_at_10[0x10];
e281682b
SM		 7746
7747 u8 max_mtu[0x10];
b4ff3a36 7748 u8 reserved_at_30[0x10];
e281682b
SM		 7749
7750 u8 admin_mtu[0x10];
b4ff3a36 7751 u8 reserved_at_50[0x10];
e281682b
SM		 7752
7753 u8 oper_mtu[0x10];
b4ff3a36 7754 u8 reserved_at_70[0x10];
e281682b
SM		 7755};
7756
7757struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7758 u8 reserved_at_0[0x8];
e281682b 7759 u8 module[0x8];
b4ff3a36 7760 u8 reserved_at_10[0x10];
e281682b 7761
b4ff3a36 7762 u8 reserved_at_20[0x18];
e281682b
SM		 7763 u8 attenuation_5g[0x8];
7764
b4ff3a36 7765 u8 reserved_at_40[0x18];
e281682b
SM		 7766 u8 attenuation_7g[0x8];
7767
b4ff3a36 7768 u8 reserved_at_60[0x18];
e281682b
SM		 7769 u8 attenuation_12g[0x8];
7770};
7771
7772struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7773 u8 reserved_at_0[0x8];
e281682b 7774 u8 module[0x8];
b4ff3a36 7775 u8 reserved_at_10[0xc];
e281682b
SM		 7776 u8 module_status[0x4];
7777
b4ff3a36 7778 u8 reserved_at_20[0x60];
e281682b
SM		 7779};
7780
7781struct mlx5_ifc_pmpc_reg_bits {
7782 u8 module_state_updated[32][0x8];
7783};
7784
7785struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7786 u8 reserved_at_0[0x4];
e281682b
SM		 7787 u8 mlpn_status[0x4];
7788 u8 local_port[0x8];
b4ff3a36 7789 u8 reserved_at_10[0x10];
e281682b
SM		 7790
7791 u8 e[0x1];
b4ff3a36 7792 u8 reserved_at_21[0x1f];
e281682b
SM		 7793};
7794
7795struct mlx5_ifc_pmlp_reg_bits {
7796 u8 rxtx[0x1];
b4ff3a36 7797 u8 reserved_at_1[0x7];
e281682b 7798 u8 local_port[0x8];
b4ff3a36 7799 u8 reserved_at_10[0x8];
e281682b
SM		 7800 u8 width[0x8];
7801
7802 u8 lane0_module_mapping[0x20];
7803
7804 u8 lane1_module_mapping[0x20];
7805
7806 u8 lane2_module_mapping[0x20];
7807
7808 u8 lane3_module_mapping[0x20];
7809
b4ff3a36 7810 u8 reserved_at_a0[0x160];
e281682b
SM		 7811};
7812
7813struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7814 u8 reserved_at_0[0x8];
e281682b 7815 u8 module[0x8];
b4ff3a36 7816 u8 reserved_at_10[0x4];
e281682b 7817 u8 admin_status[0x4];
b4ff3a36 7818 u8 reserved_at_18[0x4];
e281682b
SM		 7819 u8 oper_status[0x4];
7820
7821 u8 ase[0x1];
7822 u8 ee[0x1];
b4ff3a36 7823 u8 reserved_at_22[0x1c];
e281682b
SM		 7824 u8 e[0x2];
7825
b4ff3a36 7826 u8 reserved_at_40[0x40];
e281682b
SM		 7827};
7828
7829struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7830 u8 reserved_at_0[0x4];
e281682b 7831 u8 profile_id[0xc];
b4ff3a36 7832 u8 reserved_at_10[0x4];
e281682b 7833 u8 proto_mask[0x4];
b4ff3a36 7834 u8 reserved_at_18[0x8];
e281682b 7835
b4ff3a36 7836 u8 reserved_at_20[0x10];
e281682b
SM		 7837 u8 lane_speed[0x10];
7838
b4ff3a36 7839 u8 reserved_at_40[0x17];
e281682b
SM		 7840 u8 lpbf[0x1];
7841 u8 fec_mode_policy[0x8];
7842
7843 u8 retransmission_capability[0x8];
7844 u8 fec_mode_capability[0x18];
7845
7846 u8 retransmission_support_admin[0x8];
7847 u8 fec_mode_support_admin[0x18];
7848
7849 u8 retransmission_request_admin[0x8];
7850 u8 fec_mode_request_admin[0x18];
7851
b4ff3a36 7852 u8 reserved_at_c0[0x80];
e281682b
SM		 7853};
7854
7855struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7856 u8 reserved_at_0[0x8];
e281682b 7857 u8 local_port[0x8];
b4ff3a36 7858 u8 reserved_at_10[0x8];
e281682b
SM		 7859 u8 ib_port[0x8];
7860
b4ff3a36 7861 u8 reserved_at_20[0x60];
e281682b
SM		 7862};
7863
7864struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7865 u8 reserved_at_0[0x8];
e281682b 7866 u8 local_port[0x8];
b4ff3a36 7867 u8 reserved_at_10[0xd];
e281682b
SM		 7868 u8 lbf_mode[0x3];
7869
b4ff3a36 7870 u8 reserved_at_20[0x20];
e281682b
SM		 7871};
7872
7873struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7874 u8 reserved_at_0[0x8];
e281682b 7875 u8 local_port[0x8];
b4ff3a36 7876 u8 reserved_at_10[0x10];
e281682b
SM		 7877
7878 u8 dic[0x1];
b4ff3a36 7879 u8 reserved_at_21[0x19];
e281682b 7880 u8 ipg[0x4];
b4ff3a36 7881 u8 reserved_at_3e[0x2];
e281682b
SM		 7882};
7883
7884struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7885 u8 reserved_at_0[0x8];
e281682b 7886 u8 local_port[0x8];
b4ff3a36 7887 u8 reserved_at_10[0x10];
e281682b 7888
b4ff3a36 7889 u8 reserved_at_20[0xe0];
e281682b
SM		 7890
7891 u8 port_filter[8][0x20];
7892
7893 u8 port_filter_update_en[8][0x20];
7894};
7895
7896struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7897 u8 reserved_at_0[0x8];
e281682b 7898 u8 local_port[0x8];
2afa609f
IK		 7899 u8 reserved_at_10[0xb];
7900 u8 ppan_mask_n[0x1];
7901 u8 minor_stall_mask[0x1];
7902 u8 critical_stall_mask[0x1];
7903 u8 reserved_at_1e[0x2];
e281682b
SM		 7904
7905 u8 ppan[0x4];
b4ff3a36 7906 u8 reserved_at_24[0x4];
e281682b 7907 u8 prio_mask_tx[0x8];
b4ff3a36 7908 u8 reserved_at_30[0x8];
e281682b
SM		 7909 u8 prio_mask_rx[0x8];
7910
7911 u8 pptx[0x1];
7912 u8 aptx[0x1];
2afa609f
IK		 7913 u8 pptx_mask_n[0x1];
7914 u8 reserved_at_43[0x5];
e281682b 7915 u8 pfctx[0x8];
b4ff3a36 7916 u8 reserved_at_50[0x10];
e281682b
SM		 7917
7918 u8 pprx[0x1];
7919 u8 aprx[0x1];
2afa609f
IK		 7920 u8 pprx_mask_n[0x1];
7921 u8 reserved_at_63[0x5];
e281682b 7922 u8 pfcrx[0x8];
b4ff3a36 7923 u8 reserved_at_70[0x10];
e281682b 7924
2afa609f
IK		 7925 u8 device_stall_minor_watermark[0x10];
7926 u8 device_stall_critical_watermark[0x10];
7927
7928 u8 reserved_at_a0[0x60];
e281682b
SM		 7929};
7930
7931struct mlx5_ifc_pelc_reg_bits {
7932 u8 op[0x4];
b4ff3a36 7933 u8 reserved_at_4[0x4];
e281682b 7934 u8 local_port[0x8];
b4ff3a36 7935 u8 reserved_at_10[0x10];
e281682b
SM		 7936
7937 u8 op_admin[0x8];
7938 u8 op_capability[0x8];
7939 u8 op_request[0x8];
7940 u8 op_active[0x8];
7941
7942 u8 admin[0x40];
7943
7944 u8 capability[0x40];
7945
7946 u8 request[0x40];
7947
7948 u8 active[0x40];
7949
b4ff3a36 7950 u8 reserved_at_140[0x80];
e281682b
SM		 7951};
7952
7953struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7954 u8 reserved_at_0[0x8];
e281682b 7955 u8 local_port[0x8];
b4ff3a36 7956 u8 reserved_at_10[0x10];
e281682b 7957
b4ff3a36 7958 u8 reserved_at_20[0xc];
e281682b 7959 u8 error_count[0x4];
b4ff3a36 7960 u8 reserved_at_30[0x10];
e281682b 7961
b4ff3a36 7962 u8 reserved_at_40[0xc];
e281682b 7963 u8 lane[0x4];
b4ff3a36 7964 u8 reserved_at_50[0x8];
e281682b
SM		 7965 u8 error_type[0x8];
7966};
7967
cfdcbcea 7968struct mlx5_ifc_pcam_enhanced_features_bits {
2fcb12df 7969 u8 reserved_at_0[0x76];
cfdcbcea 7970
2fcb12df
IK		 7971 u8 pfcc_mask[0x1];
7972 u8 reserved_at_77[0x4];
2dba0797 7973 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 7974 u8 ptys_connector_type[0x1];
7975 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 7976 u8 ppcnt_discard_group[0x1];
7977 u8 ppcnt_statistical_group[0x1];
7978};
7979
7980struct mlx5_ifc_pcam_reg_bits {
7981 u8 reserved_at_0[0x8];
7982 u8 feature_group[0x8];
7983 u8 reserved_at_10[0x8];
7984 u8 access_reg_group[0x8];
7985
7986 u8 reserved_at_20[0x20];
7987
7988 union {
7989 u8 reserved_at_0[0x80];
7990 } port_access_reg_cap_mask;
7991
7992 u8 reserved_at_c0[0x80];
7993
7994 union {
7995 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7996 u8 reserved_at_0[0x80];
7997 } feature_cap_mask;
7998
7999 u8 reserved_at_1c0[0xc0];
8000};
8001
8002struct mlx5_ifc_mcam_enhanced_features_bits {
5405fa26
GP		 8003 u8 reserved_at_0[0x7b];
8004 u8 pcie_outbound_stalled[0x1];
efae7f78 8005 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8006 u8 mtpps_enh_out_per_adj[0x1];
8007 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8008 u8 pcie_performance_group[0x1];
8009};
8010
0ab87743
OG		 8011struct mlx5_ifc_mcam_access_reg_bits {
8012 u8 reserved_at_0[0x1c];
8013 u8 mcda[0x1];
8014 u8 mcc[0x1];
8015 u8 mcqi[0x1];
8016 u8 reserved_at_1f[0x1];
8017
8018 u8 regs_95_to_64[0x20];
8019 u8 regs_63_to_32[0x20];
8020 u8 regs_31_to_0[0x20];
8021};
8022
cfdcbcea
GP		 8023struct mlx5_ifc_mcam_reg_bits {
8024 u8 reserved_at_0[0x8];
8025 u8 feature_group[0x8];
8026 u8 reserved_at_10[0x8];
8027 u8 access_reg_group[0x8];
8028
8029 u8 reserved_at_20[0x20];
8030
8031 union {
0ab87743 8032 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8033 u8 reserved_at_0[0x80];
8034 } mng_access_reg_cap_mask;
8035
8036 u8 reserved_at_c0[0x80];
8037
8038 union {
8039 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8040 u8 reserved_at_0[0x80];
8041 } mng_feature_cap_mask;
8042
8043 u8 reserved_at_1c0[0x80];
8044};
8045
c02762eb
HN		 8046struct mlx5_ifc_qcam_access_reg_cap_mask {
8047 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8048 u8 qpdpm[0x1];
8049 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8050 u8 qdpm[0x1];
8051 u8 qpts[0x1];
8052 u8 qcap[0x1];
8053 u8 qcam_access_reg_cap_mask_0[0x1];
8054};
8055
8056struct mlx5_ifc_qcam_qos_feature_cap_mask {
8057 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8058 u8 qpts_trust_both[0x1];
8059};
8060
8061struct mlx5_ifc_qcam_reg_bits {
8062 u8 reserved_at_0[0x8];
8063 u8 feature_group[0x8];
8064 u8 reserved_at_10[0x8];
8065 u8 access_reg_group[0x8];
8066 u8 reserved_at_20[0x20];
8067
8068 union {
8069 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8070 u8 reserved_at_0[0x80];
8071 } qos_access_reg_cap_mask;
8072
8073 u8 reserved_at_c0[0x80];
8074
8075 union {
8076 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8077 u8 reserved_at_0[0x80];
8078 } qos_feature_cap_mask;
8079
8080 u8 reserved_at_1c0[0x80];
8081};
8082
e281682b 8083struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8084 u8 reserved_at_0[0x8];
e281682b 8085 u8 local_port[0x8];
b4ff3a36 8086 u8 reserved_at_10[0x10];
e281682b
SM		 8087
8088 u8 port_capability_mask[4][0x20];
8089};
8090
8091struct mlx5_ifc_paos_reg_bits {
8092 u8 swid[0x8];
8093 u8 local_port[0x8];
b4ff3a36 8094 u8 reserved_at_10[0x4];
e281682b 8095 u8 admin_status[0x4];
b4ff3a36 8096 u8 reserved_at_18[0x4];
e281682b
SM		 8097 u8 oper_status[0x4];
8098
8099 u8 ase[0x1];
8100 u8 ee[0x1];
b4ff3a36 8101 u8 reserved_at_22[0x1c];
e281682b
SM		 8102 u8 e[0x2];
8103
b4ff3a36 8104 u8 reserved_at_40[0x40];
e281682b
SM		 8105};
8106
8107struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8108 u8 reserved_at_0[0x8];
e281682b 8109 u8 opamp_group[0x8];
b4ff3a36 8110 u8 reserved_at_10[0xc];
e281682b
SM		 8111 u8 opamp_group_type[0x4];
8112
8113 u8 start_index[0x10];
b4ff3a36 8114 u8 reserved_at_30[0x4];
e281682b
SM		 8115 u8 num_of_indices[0xc];
8116
8117 u8 index_data[18][0x10];
8118};
8119
7d5e1423
SM		 8120struct mlx5_ifc_pcmr_reg_bits {
8121 u8 reserved_at_0[0x8];
8122 u8 local_port[0x8];
8123 u8 reserved_at_10[0x2e];
8124 u8 fcs_cap[0x1];
8125 u8 reserved_at_3f[0x1f];
8126 u8 fcs_chk[0x1];
8127 u8 reserved_at_5f[0x1];
8128};
8129
e281682b 8130struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8131 u8 reserved_at_0[0x6];
e281682b 8132 u8 rx_lane[0x2];
b4ff3a36 8133 u8 reserved_at_8[0x6];
e281682b 8134 u8 tx_lane[0x2];
b4ff3a36 8135 u8 reserved_at_10[0x8];
e281682b
SM		 8136 u8 module[0x8];
8137};
8138
8139struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8140 u8 reserved_at_0[0x6];
e281682b
SM		 8141 u8 lossy[0x1];
8142 u8 epsb[0x1];
b4ff3a36 8143 u8 reserved_at_8[0xc];
e281682b
SM		 8144 u8 size[0xc];
8145
8146 u8 xoff_threshold[0x10];
8147 u8 xon_threshold[0x10];
8148};
8149
8150struct mlx5_ifc_set_node_in_bits {
8151 u8 node_description[64][0x8];
8152};
8153
8154struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8155 u8 reserved_at_0[0x18];
e281682b
SM		 8156 u8 power_settings_level[0x8];
8157
b4ff3a36 8158 u8 reserved_at_20[0x60];
e281682b
SM		 8159};
8160
8161struct mlx5_ifc_register_host_endianness_bits {
8162 u8 he[0x1];
b4ff3a36 8163 u8 reserved_at_1[0x1f];
e281682b 8164
b4ff3a36 8165 u8 reserved_at_20[0x60];
e281682b
SM		 8166};
8167
8168struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8169 u8 reserved_at_0[0x20];
e281682b
SM		 8170
8171 u8 mkey[0x20];
8172
8173 u8 addressh_63_32[0x20];
8174
8175 u8 addressl_31_0[0x20];
8176};
8177
8178struct mlx5_ifc_ud_adrs_vector_bits {
8179 u8 dc_key[0x40];
8180
8181 u8 ext[0x1];
b4ff3a36 8182 u8 reserved_at_41[0x7];
e281682b
SM		 8183 u8 destination_qp_dct[0x18];
8184
8185 u8 static_rate[0x4];
8186 u8 sl_eth_prio[0x4];
8187 u8 fl[0x1];
8188 u8 mlid[0x7];
8189 u8 rlid_udp_sport[0x10];
8190
b4ff3a36 8191 u8 reserved_at_80[0x20];
e281682b
SM		 8192
8193 u8 rmac_47_16[0x20];
8194
8195 u8 rmac_15_0[0x10];
8196 u8 tclass[0x8];
8197 u8 hop_limit[0x8];
8198
b4ff3a36 8199 u8 reserved_at_e0[0x1];
e281682b 8200 u8 grh[0x1];
b4ff3a36 8201 u8 reserved_at_e2[0x2];
e281682b
SM		 8202 u8 src_addr_index[0x8];
8203 u8 flow_label[0x14];
8204
8205 u8 rgid_rip[16][0x8];
8206};
8207
8208struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8209 u8 reserved_at_0[0x10];
e281682b
SM		 8210 u8 function_id[0x10];
8211
8212 u8 num_pages[0x20];
8213
b4ff3a36 8214 u8 reserved_at_40[0xa0];
e281682b
SM		 8215};
8216
8217struct mlx5_ifc_eqe_bits {
b4ff3a36 8218 u8 reserved_at_0[0x8];
e281682b 8219 u8 event_type[0x8];
b4ff3a36 8220 u8 reserved_at_10[0x8];
e281682b
SM		 8221 u8 event_sub_type[0x8];
8222
b4ff3a36 8223 u8 reserved_at_20[0xe0];
e281682b
SM		 8224
8225 union mlx5_ifc_event_auto_bits event_data;
8226
b4ff3a36 8227 u8 reserved_at_1e0[0x10];
e281682b 8228 u8 signature[0x8];
b4ff3a36 8229 u8 reserved_at_1f8[0x7];
e281682b
SM		 8230 u8 owner[0x1];
8231};
8232
8233enum {
8234 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8235};
8236
8237struct mlx5_ifc_cmd_queue_entry_bits {
8238 u8 type[0x8];
b4ff3a36 8239 u8 reserved_at_8[0x18];
e281682b
SM		 8240
8241 u8 input_length[0x20];
8242
8243 u8 input_mailbox_pointer_63_32[0x20];
8244
8245 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8246 u8 reserved_at_77[0x9];
e281682b
SM		 8247
8248 u8 command_input_inline_data[16][0x8];
8249
8250 u8 command_output_inline_data[16][0x8];
8251
8252 u8 output_mailbox_pointer_63_32[0x20];
8253
8254 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8255 u8 reserved_at_1b7[0x9];
e281682b
SM		 8256
8257 u8 output_length[0x20];
8258
8259 u8 token[0x8];
8260 u8 signature[0x8];
b4ff3a36 8261 u8 reserved_at_1f0[0x8];
e281682b
SM		 8262 u8 status[0x7];
8263 u8 ownership[0x1];
8264};
8265
8266struct mlx5_ifc_cmd_out_bits {
8267 u8 status[0x8];
b4ff3a36 8268 u8 reserved_at_8[0x18];
e281682b
SM		 8269
8270 u8 syndrome[0x20];
8271
8272 u8 command_output[0x20];
8273};
8274
8275struct mlx5_ifc_cmd_in_bits {
8276 u8 opcode[0x10];
b4ff3a36 8277 u8 reserved_at_10[0x10];
e281682b 8278
b4ff3a36 8279 u8 reserved_at_20[0x10];
e281682b
SM		 8280 u8 op_mod[0x10];
8281
8282 u8 command[0][0x20];
8283};
8284
8285struct mlx5_ifc_cmd_if_box_bits {
8286 u8 mailbox_data[512][0x8];
8287
b4ff3a36 8288 u8 reserved_at_1000[0x180];
e281682b
SM		 8289
8290 u8 next_pointer_63_32[0x20];
8291
8292 u8 next_pointer_31_10[0x16];
b4ff3a36 8293 u8 reserved_at_11b6[0xa];
e281682b
SM		 8294
8295 u8 block_number[0x20];
8296
b4ff3a36 8297 u8 reserved_at_11e0[0x8];
e281682b
SM		 8298 u8 token[0x8];
8299 u8 ctrl_signature[0x8];
8300 u8 signature[0x8];
8301};
8302
8303struct mlx5_ifc_mtt_bits {
8304 u8 ptag_63_32[0x20];
8305
8306 u8 ptag_31_8[0x18];
b4ff3a36 8307 u8 reserved_at_38[0x6];
e281682b
SM		 8308 u8 wr_en[0x1];
8309 u8 rd_en[0x1];
8310};
8311
928cfe87
TT		 8312struct mlx5_ifc_query_wol_rol_out_bits {
8313 u8 status[0x8];
8314 u8 reserved_at_8[0x18];
8315
8316 u8 syndrome[0x20];
8317
8318 u8 reserved_at_40[0x10];
8319 u8 rol_mode[0x8];
8320 u8 wol_mode[0x8];
8321
8322 u8 reserved_at_60[0x20];
8323};
8324
8325struct mlx5_ifc_query_wol_rol_in_bits {
8326 u8 opcode[0x10];
8327 u8 reserved_at_10[0x10];
8328
8329 u8 reserved_at_20[0x10];
8330 u8 op_mod[0x10];
8331
8332 u8 reserved_at_40[0x40];
8333};
8334
8335struct mlx5_ifc_set_wol_rol_out_bits {
8336 u8 status[0x8];
8337 u8 reserved_at_8[0x18];
8338
8339 u8 syndrome[0x20];
8340
8341 u8 reserved_at_40[0x40];
8342};
8343
8344struct mlx5_ifc_set_wol_rol_in_bits {
8345 u8 opcode[0x10];
8346 u8 reserved_at_10[0x10];
8347
8348 u8 reserved_at_20[0x10];
8349 u8 op_mod[0x10];
8350
8351 u8 rol_mode_valid[0x1];
8352 u8 wol_mode_valid[0x1];
8353 u8 reserved_at_42[0xe];
8354 u8 rol_mode[0x8];
8355 u8 wol_mode[0x8];
8356
8357 u8 reserved_at_60[0x20];
8358};
8359
e281682b
SM		 8360enum {
8361 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8362 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8363 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8364};
8365
8366enum {
8367 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8368 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8369 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8370};
8371
8372enum {
8373 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8374 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8375 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8376 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8377 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8378 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8379 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8380 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8381 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8382 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8383 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8384};
8385
8386struct mlx5_ifc_initial_seg_bits {
8387 u8 fw_rev_minor[0x10];
8388 u8 fw_rev_major[0x10];
8389
8390 u8 cmd_interface_rev[0x10];
8391 u8 fw_rev_subminor[0x10];
8392
b4ff3a36 8393 u8 reserved_at_40[0x40];
e281682b
SM		 8394
8395 u8 cmdq_phy_addr_63_32[0x20];
8396
8397 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8398 u8 reserved_at_b4[0x2];
e281682b
SM		 8399 u8 nic_interface[0x2];
8400 u8 log_cmdq_size[0x4];
8401 u8 log_cmdq_stride[0x4];
8402
8403 u8 command_doorbell_vector[0x20];
8404
b4ff3a36 8405 u8 reserved_at_e0[0xf00];
e281682b
SM		 8406
8407 u8 initializing[0x1];
b4ff3a36 8408 u8 reserved_at_fe1[0x4];
e281682b 8409 u8 nic_interface_supported[0x3];
b4ff3a36 8410 u8 reserved_at_fe8[0x18];
e281682b
SM		 8411
8412 struct mlx5_ifc_health_buffer_bits health_buffer;
8413
8414 u8 no_dram_nic_offset[0x20];
8415
b4ff3a36 8416 u8 reserved_at_1220[0x6e40];
e281682b 8417
b4ff3a36 8418 u8 reserved_at_8060[0x1f];
e281682b
SM		 8419 u8 clear_int[0x1];
8420
8421 u8 health_syndrome[0x8];
8422 u8 health_counter[0x18];
8423
b4ff3a36 8424 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8425};
8426
f9a1ef72
EE		 8427struct mlx5_ifc_mtpps_reg_bits {
8428 u8 reserved_at_0[0xc];
8429 u8 cap_number_of_pps_pins[0x4];
8430 u8 reserved_at_10[0x4];
8431 u8 cap_max_num_of_pps_in_pins[0x4];
8432 u8 reserved_at_18[0x4];
8433 u8 cap_max_num_of_pps_out_pins[0x4];
8434
8435 u8 reserved_at_20[0x24];
8436 u8 cap_pin_3_mode[0x4];
8437 u8 reserved_at_48[0x4];
8438 u8 cap_pin_2_mode[0x4];
8439 u8 reserved_at_50[0x4];
8440 u8 cap_pin_1_mode[0x4];
8441 u8 reserved_at_58[0x4];
8442 u8 cap_pin_0_mode[0x4];
8443
8444 u8 reserved_at_60[0x4];
8445 u8 cap_pin_7_mode[0x4];
8446 u8 reserved_at_68[0x4];
8447 u8 cap_pin_6_mode[0x4];
8448 u8 reserved_at_70[0x4];
8449 u8 cap_pin_5_mode[0x4];
8450 u8 reserved_at_78[0x4];
8451 u8 cap_pin_4_mode[0x4];
8452
fa367688
EE		 8453 u8 field_select[0x20];
8454 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8455
8456 u8 enable[0x1];
8457 u8 reserved_at_101[0xb];
8458 u8 pattern[0x4];
8459 u8 reserved_at_110[0x4];
8460 u8 pin_mode[0x4];
8461 u8 pin[0x8];
8462
8463 u8 reserved_at_120[0x20];
8464
8465 u8 time_stamp[0x40];
8466
8467 u8 out_pulse_duration[0x10];
8468 u8 out_periodic_adjustment[0x10];
fa367688 8469 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8470
fa367688 8471 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8472};
8473
8474struct mlx5_ifc_mtppse_reg_bits {
8475 u8 reserved_at_0[0x18];
8476 u8 pin[0x8];
8477 u8 event_arm[0x1];
8478 u8 reserved_at_21[0x1b];
8479 u8 event_generation_mode[0x4];
8480 u8 reserved_at_40[0x40];
8481};
8482
47176289
OG		 8483struct mlx5_ifc_mcqi_cap_bits {
8484 u8 supported_info_bitmask[0x20];
8485
8486 u8 component_size[0x20];
8487
8488 u8 max_component_size[0x20];
8489
8490 u8 log_mcda_word_size[0x4];
8491 u8 reserved_at_64[0xc];
8492 u8 mcda_max_write_size[0x10];
8493
8494 u8 rd_en[0x1];
8495 u8 reserved_at_81[0x1];
8496 u8 match_chip_id[0x1];
8497 u8 match_psid[0x1];
8498 u8 check_user_timestamp[0x1];
8499 u8 match_base_guid_mac[0x1];
8500 u8 reserved_at_86[0x1a];
8501};
8502
8503struct mlx5_ifc_mcqi_reg_bits {
8504 u8 read_pending_component[0x1];
8505 u8 reserved_at_1[0xf];
8506 u8 component_index[0x10];
8507
8508 u8 reserved_at_20[0x20];
8509
8510 u8 reserved_at_40[0x1b];
8511 u8 info_type[0x5];
8512
8513 u8 info_size[0x20];
8514
8515 u8 offset[0x20];
8516
8517 u8 reserved_at_a0[0x10];
8518 u8 data_size[0x10];
8519
8520 u8 data[0][0x20];
8521};
8522
8523struct mlx5_ifc_mcc_reg_bits {
8524 u8 reserved_at_0[0x4];
8525 u8 time_elapsed_since_last_cmd[0xc];
8526 u8 reserved_at_10[0x8];
8527 u8 instruction[0x8];
8528
8529 u8 reserved_at_20[0x10];
8530 u8 component_index[0x10];
8531
8532 u8 reserved_at_40[0x8];
8533 u8 update_handle[0x18];
8534
8535 u8 handle_owner_type[0x4];
8536 u8 handle_owner_host_id[0x4];
8537 u8 reserved_at_68[0x1];
8538 u8 control_progress[0x7];
8539 u8 error_code[0x8];
8540 u8 reserved_at_78[0x4];
8541 u8 control_state[0x4];
8542
8543 u8 component_size[0x20];
8544
8545 u8 reserved_at_a0[0x60];
8546};
8547
8548struct mlx5_ifc_mcda_reg_bits {
8549 u8 reserved_at_0[0x8];
8550 u8 update_handle[0x18];
8551
8552 u8 offset[0x20];
8553
8554 u8 reserved_at_40[0x10];
8555 u8 size[0x10];
8556
8557 u8 reserved_at_60[0x20];
8558
8559 u8 data[0][0x20];
8560};
8561
e281682b
SM		 8562union mlx5_ifc_ports_control_registers_document_bits {
8563 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8564 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8565 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8566 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8567 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8568 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8569 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8570 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8571 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8572 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8573 struct mlx5_ifc_paos_reg_bits paos_reg;
8574 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8575 struct mlx5_ifc_peir_reg_bits peir_reg;
8576 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8577 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8578 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8579 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8580 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8581 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8582 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8583 struct mlx5_ifc_plib_reg_bits plib_reg;
8584 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8585 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8586 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8587 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8588 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8589 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8590 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8591 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8592 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8593 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8594 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8595 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8596 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8597 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8598 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8599 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8600 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8601 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8602 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8603 struct mlx5_ifc_pude_reg_bits pude_reg;
8604 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8605 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8606 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8607 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8608 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8609 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8610 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8611 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8612 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8613 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8614 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8615 u8 reserved_at_0[0x60e0];
e281682b
SM		 8616};
8617
8618union mlx5_ifc_debug_enhancements_document_bits {
8619 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8620 u8 reserved_at_0[0x200];
e281682b
SM		 8621};
8622
8623union mlx5_ifc_uplink_pci_interface_document_bits {
8624 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8625 u8 reserved_at_0[0x20060];
b775516b
EC		 8626};
8627
2cc43b49
MG		 8628struct mlx5_ifc_set_flow_table_root_out_bits {
8629 u8 status[0x8];
b4ff3a36 8630 u8 reserved_at_8[0x18];
2cc43b49
MG		 8631
8632 u8 syndrome[0x20];
8633
b4ff3a36 8634 u8 reserved_at_40[0x40];
2cc43b49
MG		 8635};
8636
8637struct mlx5_ifc_set_flow_table_root_in_bits {
8638 u8 opcode[0x10];
b4ff3a36 8639 u8 reserved_at_10[0x10];
2cc43b49 8640
b4ff3a36 8641 u8 reserved_at_20[0x10];
2cc43b49
MG		 8642 u8 op_mod[0x10];
8643
7d5e1423
SM		 8644 u8 other_vport[0x1];
8645 u8 reserved_at_41[0xf];
8646 u8 vport_number[0x10];
8647
8648 u8 reserved_at_60[0x20];
2cc43b49
MG		 8649
8650 u8 table_type[0x8];
b4ff3a36 8651 u8 reserved_at_88[0x18];
2cc43b49 8652
b4ff3a36 8653 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8654 u8 table_id[0x18];
8655
500a3d0d
ES		 8656 u8 reserved_at_c0[0x8];
8657 u8 underlay_qpn[0x18];
8658 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8659};
8660
34a40e68 8661enum {
84df61eb
AH		 8662 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8663 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8664};
8665
8666struct mlx5_ifc_modify_flow_table_out_bits {
8667 u8 status[0x8];
b4ff3a36 8668 u8 reserved_at_8[0x18];
34a40e68
MG		 8669
8670 u8 syndrome[0x20];
8671
b4ff3a36 8672 u8 reserved_at_40[0x40];
34a40e68
MG		 8673};
8674
8675struct mlx5_ifc_modify_flow_table_in_bits {
8676 u8 opcode[0x10];
b4ff3a36 8677 u8 reserved_at_10[0x10];
34a40e68 8678
b4ff3a36 8679 u8 reserved_at_20[0x10];
34a40e68
MG		 8680 u8 op_mod[0x10];
8681
7d5e1423
SM		 8682 u8 other_vport[0x1];
8683 u8 reserved_at_41[0xf];
8684 u8 vport_number[0x10];
34a40e68 8685
b4ff3a36 8686 u8 reserved_at_60[0x10];
34a40e68
MG		 8687 u8 modify_field_select[0x10];
8688
8689 u8 table_type[0x8];
b4ff3a36 8690 u8 reserved_at_88[0x18];
34a40e68 8691
b4ff3a36 8692 u8 reserved_at_a0[0x8];
34a40e68
MG		 8693 u8 table_id[0x18];
8694
0c90e9c6 8695 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8696};
8697
4f3961ee
SM		 8698struct mlx5_ifc_ets_tcn_config_reg_bits {
8699 u8 g[0x1];
8700 u8 b[0x1];
8701 u8 r[0x1];
8702 u8 reserved_at_3[0x9];
8703 u8 group[0x4];
8704 u8 reserved_at_10[0x9];
8705 u8 bw_allocation[0x7];
8706
8707 u8 reserved_at_20[0xc];
8708 u8 max_bw_units[0x4];
8709 u8 reserved_at_30[0x8];
8710 u8 max_bw_value[0x8];
8711};
8712
8713struct mlx5_ifc_ets_global_config_reg_bits {
8714 u8 reserved_at_0[0x2];
8715 u8 r[0x1];
8716 u8 reserved_at_3[0x1d];
8717
8718 u8 reserved_at_20[0xc];
8719 u8 max_bw_units[0x4];
8720 u8 reserved_at_30[0x8];
8721 u8 max_bw_value[0x8];
8722};
8723
8724struct mlx5_ifc_qetc_reg_bits {
8725 u8 reserved_at_0[0x8];
8726 u8 port_number[0x8];
8727 u8 reserved_at_10[0x30];
8728
8729 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8730 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8731};
8732
415a64aa
HN		 8733struct mlx5_ifc_qpdpm_dscp_reg_bits {
8734 u8 e[0x1];
8735 u8 reserved_at_01[0x0b];
8736 u8 prio[0x04];
8737};
8738
8739struct mlx5_ifc_qpdpm_reg_bits {
8740 u8 reserved_at_0[0x8];
8741 u8 local_port[0x8];
8742 u8 reserved_at_10[0x10];
8743 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8744};
8745
8746struct mlx5_ifc_qpts_reg_bits {
8747 u8 reserved_at_0[0x8];
8748 u8 local_port[0x8];
8749 u8 reserved_at_10[0x2d];
8750 u8 trust_state[0x3];
8751};
8752
4f3961ee
SM		 8753struct mlx5_ifc_qtct_reg_bits {
8754 u8 reserved_at_0[0x8];
8755 u8 port_number[0x8];
8756 u8 reserved_at_10[0xd];
8757 u8 prio[0x3];
8758
8759 u8 reserved_at_20[0x1d];
8760 u8 tclass[0x3];
8761};
8762
7d5e1423
SM		 8763struct mlx5_ifc_mcia_reg_bits {
8764 u8 l[0x1];
8765 u8 reserved_at_1[0x7];
8766 u8 module[0x8];
8767 u8 reserved_at_10[0x8];
8768 u8 status[0x8];
8769
8770 u8 i2c_device_address[0x8];
8771 u8 page_number[0x8];
8772 u8 device_address[0x10];
8773
8774 u8 reserved_at_40[0x10];
8775 u8 size[0x10];
8776
8777 u8 reserved_at_60[0x20];
8778
8779 u8 dword_0[0x20];
8780 u8 dword_1[0x20];
8781 u8 dword_2[0x20];
8782 u8 dword_3[0x20];
8783 u8 dword_4[0x20];
8784 u8 dword_5[0x20];
8785 u8 dword_6[0x20];
8786 u8 dword_7[0x20];
8787 u8 dword_8[0x20];
8788 u8 dword_9[0x20];
8789 u8 dword_10[0x20];
8790 u8 dword_11[0x20];
8791};
8792
7486216b
SM		 8793struct mlx5_ifc_dcbx_param_bits {
8794 u8 dcbx_cee_cap[0x1];
8795 u8 dcbx_ieee_cap[0x1];
8796 u8 dcbx_standby_cap[0x1];
8797 u8 reserved_at_0[0x5];
8798 u8 port_number[0x8];
8799 u8 reserved_at_10[0xa];
8800 u8 max_application_table_size[6];
8801 u8 reserved_at_20[0x15];
8802 u8 version_oper[0x3];
8803 u8 reserved_at_38[5];
8804 u8 version_admin[0x3];
8805 u8 willing_admin[0x1];
8806 u8 reserved_at_41[0x3];
8807 u8 pfc_cap_oper[0x4];
8808 u8 reserved_at_48[0x4];
8809 u8 pfc_cap_admin[0x4];
8810 u8 reserved_at_50[0x4];
8811 u8 num_of_tc_oper[0x4];
8812 u8 reserved_at_58[0x4];
8813 u8 num_of_tc_admin[0x4];
8814 u8 remote_willing[0x1];
8815 u8 reserved_at_61[3];
8816 u8 remote_pfc_cap[4];
8817 u8 reserved_at_68[0x14];
8818 u8 remote_num_of_tc[0x4];
8819 u8 reserved_at_80[0x18];
8820 u8 error[0x8];
8821 u8 reserved_at_a0[0x160];
8822};
84df61eb
AH		 8823
8824struct mlx5_ifc_lagc_bits {
8825 u8 reserved_at_0[0x1d];
8826 u8 lag_state[0x3];
8827
8828 u8 reserved_at_20[0x14];
8829 u8 tx_remap_affinity_2[0x4];
8830 u8 reserved_at_38[0x4];
8831 u8 tx_remap_affinity_1[0x4];
8832};
8833
8834struct mlx5_ifc_create_lag_out_bits {
8835 u8 status[0x8];
8836 u8 reserved_at_8[0x18];
8837
8838 u8 syndrome[0x20];
8839
8840 u8 reserved_at_40[0x40];
8841};
8842
8843struct mlx5_ifc_create_lag_in_bits {
8844 u8 opcode[0x10];
8845 u8 reserved_at_10[0x10];
8846
8847 u8 reserved_at_20[0x10];
8848 u8 op_mod[0x10];
8849
8850 struct mlx5_ifc_lagc_bits ctx;
8851};
8852
8853struct mlx5_ifc_modify_lag_out_bits {
8854 u8 status[0x8];
8855 u8 reserved_at_8[0x18];
8856
8857 u8 syndrome[0x20];
8858
8859 u8 reserved_at_40[0x40];
8860};
8861
8862struct mlx5_ifc_modify_lag_in_bits {
8863 u8 opcode[0x10];
8864 u8 reserved_at_10[0x10];
8865
8866 u8 reserved_at_20[0x10];
8867 u8 op_mod[0x10];
8868
8869 u8 reserved_at_40[0x20];
8870 u8 field_select[0x20];
8871
8872 struct mlx5_ifc_lagc_bits ctx;
8873};
8874
8875struct mlx5_ifc_query_lag_out_bits {
8876 u8 status[0x8];
8877 u8 reserved_at_8[0x18];
8878
8879 u8 syndrome[0x20];
8880
8881 u8 reserved_at_40[0x40];
8882
8883 struct mlx5_ifc_lagc_bits ctx;
8884};
8885
8886struct mlx5_ifc_query_lag_in_bits {
8887 u8 opcode[0x10];
8888 u8 reserved_at_10[0x10];
8889
8890 u8 reserved_at_20[0x10];
8891 u8 op_mod[0x10];
8892
8893 u8 reserved_at_40[0x40];
8894};
8895
8896struct mlx5_ifc_destroy_lag_out_bits {
8897 u8 status[0x8];
8898 u8 reserved_at_8[0x18];
8899
8900 u8 syndrome[0x20];
8901
8902 u8 reserved_at_40[0x40];
8903};
8904
8905struct mlx5_ifc_destroy_lag_in_bits {
8906 u8 opcode[0x10];
8907 u8 reserved_at_10[0x10];
8908
8909 u8 reserved_at_20[0x10];
8910 u8 op_mod[0x10];
8911
8912 u8 reserved_at_40[0x40];
8913};
8914
8915struct mlx5_ifc_create_vport_lag_out_bits {
8916 u8 status[0x8];
8917 u8 reserved_at_8[0x18];
8918
8919 u8 syndrome[0x20];
8920
8921 u8 reserved_at_40[0x40];
8922};
8923
8924struct mlx5_ifc_create_vport_lag_in_bits {
8925 u8 opcode[0x10];
8926 u8 reserved_at_10[0x10];
8927
8928 u8 reserved_at_20[0x10];
8929 u8 op_mod[0x10];
8930
8931 u8 reserved_at_40[0x40];
8932};
8933
8934struct mlx5_ifc_destroy_vport_lag_out_bits {
8935 u8 status[0x8];
8936 u8 reserved_at_8[0x18];
8937
8938 u8 syndrome[0x20];
8939
8940 u8 reserved_at_40[0x40];
8941};
8942
8943struct mlx5_ifc_destroy_vport_lag_in_bits {
8944 u8 opcode[0x10];
8945 u8 reserved_at_10[0x10];
8946
8947 u8 reserved_at_20[0x10];
8948 u8 op_mod[0x10];
8949
8950 u8 reserved_at_40[0x40];
8951};
8952
d29b796a 8953#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)