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RDMA/rtrs-srv-sysfs: fix missing put_device
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
66enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71};
72
f91e6d89
EBE		 73enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
59e9e8e4 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
f91e6d89
EBE		 78};
79
38b7ca92 80enum {
2acc7957 81 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 82};
83
9fba2b9b
AL		 84enum {
85 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
86};
87
88enum {
89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
b169e64a 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90fbca59 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
b169e64a
YK		 92};
93
94enum {
95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
8a06a79b 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
e4075c44
YH		 97 MLX5_OBJ_TYPE_MKEY = 0xff01,
98 MLX5_OBJ_TYPE_QP = 0xff02,
99 MLX5_OBJ_TYPE_PSV = 0xff03,
100 MLX5_OBJ_TYPE_RMP = 0xff04,
101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 MLX5_OBJ_TYPE_RQ = 0xff06,
103 MLX5_OBJ_TYPE_SQ = 0xff07,
104 MLX5_OBJ_TYPE_TIR = 0xff08,
105 MLX5_OBJ_TYPE_TIS = 0xff09,
106 MLX5_OBJ_TYPE_DCT = 0xff0a,
107 MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 MLX5_OBJ_TYPE_RQT = 0xff0e,
109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 MLX5_OBJ_TYPE_CQ = 0xff10,
9fba2b9b
AL		 111};
112
d29b796a
EC		 113enum {
114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
116 MLX5_CMD_OP_INIT_HCA = 0x102,
117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
118 MLX5_CMD_OP_ENABLE_HCA = 0x104,
119 MLX5_CMD_OP_DISABLE_HCA = 0x105,
120 MLX5_CMD_OP_QUERY_PAGES = 0x107,
121 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
122 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
124 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
1759d322
PP		 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
127 MLX5_CMD_OP_ALLOC_SF = 0x113,
128 MLX5_CMD_OP_DEALLOC_SF = 0x114,
d29b796a
EC		 129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 136 MLX5_CMD_OP_CREATE_EQ = 0x301,
137 MLX5_CMD_OP_DESTROY_EQ = 0x302,
138 MLX5_CMD_OP_QUERY_EQ = 0x303,
139 MLX5_CMD_OP_GEN_EQE = 0x304,
140 MLX5_CMD_OP_CREATE_CQ = 0x400,
141 MLX5_CMD_OP_DESTROY_CQ = 0x401,
142 MLX5_CMD_OP_QUERY_CQ = 0x402,
143 MLX5_CMD_OP_MODIFY_CQ = 0x403,
144 MLX5_CMD_OP_CREATE_QP = 0x500,
145 MLX5_CMD_OP_DESTROY_QP = 0x501,
146 MLX5_CMD_OP_RST2INIT_QP = 0x502,
147 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
148 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
149 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
151 MLX5_CMD_OP_2ERR_QP = 0x507,
152 MLX5_CMD_OP_2RST_QP = 0x50a,
153 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
156 MLX5_CMD_OP_CREATE_PSV = 0x600,
157 MLX5_CMD_OP_DESTROY_PSV = 0x601,
158 MLX5_CMD_OP_CREATE_SRQ = 0x700,
159 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
160 MLX5_CMD_OP_QUERY_SRQ = 0x702,
161 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 166 MLX5_CMD_OP_CREATE_DCT = 0x710,
167 MLX5_CMD_OP_DESTROY_DCT = 0x711,
168 MLX5_CMD_OP_DRAIN_DCT = 0x712,
169 MLX5_CMD_OP_QUERY_DCT = 0x713,
170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 171 MLX5_CMD_OP_CREATE_XRQ = 0x717,
172 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
173 MLX5_CMD_OP_QUERY_XRQ = 0x719,
174 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
b1635ee6
YH		 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
cd56f929 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
d29b796a
EC		 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 208 MLX5_CMD_OP_ALLOC_PD = 0x800,
209 MLX5_CMD_OP_DEALLOC_PD = 0x801,
210 MLX5_CMD_OP_ALLOC_UAR = 0x802,
211 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
213 MLX5_CMD_OP_ACCESS_REG = 0x805,
214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
217 MLX5_CMD_OP_MAD_IFC = 0x50d,
218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
220 MLX5_CMD_OP_NOP = 0x80d,
221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 237 MLX5_CMD_OP_CREATE_LAG = 0x840,
238 MLX5_CMD_OP_MODIFY_LAG = 0x841,
239 MLX5_CMD_OP_QUERY_LAG = 0x842,
240 MLX5_CMD_OP_DESTROY_LAG = 0x843,
241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 243 MLX5_CMD_OP_CREATE_TIR = 0x900,
244 MLX5_CMD_OP_MODIFY_TIR = 0x901,
245 MLX5_CMD_OP_DESTROY_TIR = 0x902,
246 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 247 MLX5_CMD_OP_CREATE_SQ = 0x904,
248 MLX5_CMD_OP_MODIFY_SQ = 0x905,
249 MLX5_CMD_OP_DESTROY_SQ = 0x906,
250 MLX5_CMD_OP_QUERY_SQ = 0x907,
251 MLX5_CMD_OP_CREATE_RQ = 0x908,
252 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
255 MLX5_CMD_OP_QUERY_RQ = 0x90b,
256 MLX5_CMD_OP_CREATE_RMP = 0x90c,
257 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
258 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
259 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 260 MLX5_CMD_OP_CREATE_TIS = 0x912,
261 MLX5_CMD_OP_MODIFY_TIS = 0x913,
262 MLX5_CMD_OP_DESTROY_TIS = 0x914,
263 MLX5_CMD_OP_QUERY_TIS = 0x915,
264 MLX5_CMD_OP_CREATE_RQT = 0x916,
265 MLX5_CMD_OP_MODIFY_RQT = 0x917,
266 MLX5_CMD_OP_DESTROY_RQT = 0x918,
267 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
d32d7c52 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
349125ba
PP		 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
86d56a1a 304 MLX5_CMD_OP_MAX
e281682b
SM		 305};
306
719598c9
YH		 307/* Valid range for general commands that don't work over an object */
308enum {
309 MLX5_CMD_OP_GENERAL_START = 0xb00,
310 MLX5_CMD_OP_GENERAL_END = 0xd00,
311};
312
e281682b
SM		 313struct mlx5_ifc_flow_table_fields_supported_bits {
314 u8 outer_dmac[0x1];
315 u8 outer_smac[0x1];
316 u8 outer_ether_type[0x1];
19cc7524 317 u8 outer_ip_version[0x1];
e281682b
SM		 318 u8 outer_first_prio[0x1];
319 u8 outer_first_cfi[0x1];
320 u8 outer_first_vid[0x1];
a8ade55f 321 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 322 u8 outer_second_prio[0x1];
323 u8 outer_second_cfi[0x1];
324 u8 outer_second_vid[0x1];
b4ff3a36 325 u8 reserved_at_b[0x1];
e281682b
SM		 326 u8 outer_sip[0x1];
327 u8 outer_dip[0x1];
328 u8 outer_frag[0x1];
329 u8 outer_ip_protocol[0x1];
330 u8 outer_ip_ecn[0x1];
331 u8 outer_ip_dscp[0x1];
332 u8 outer_udp_sport[0x1];
333 u8 outer_udp_dport[0x1];
334 u8 outer_tcp_sport[0x1];
335 u8 outer_tcp_dport[0x1];
336 u8 outer_tcp_flags[0x1];
337 u8 outer_gre_protocol[0x1];
338 u8 outer_gre_key[0x1];
339 u8 outer_vxlan_vni[0x1];
75d90e7d
YK		 340 u8 outer_geneve_vni[0x1];
341 u8 outer_geneve_oam[0x1];
342 u8 outer_geneve_protocol_type[0x1];
343 u8 outer_geneve_opt_len[0x1];
344 u8 reserved_at_1e[0x1];
e281682b
SM		 345 u8 source_eswitch_port[0x1];
346
347 u8 inner_dmac[0x1];
348 u8 inner_smac[0x1];
349 u8 inner_ether_type[0x1];
19cc7524 350 u8 inner_ip_version[0x1];
e281682b
SM		 351 u8 inner_first_prio[0x1];
352 u8 inner_first_cfi[0x1];
353 u8 inner_first_vid[0x1];
b4ff3a36 354 u8 reserved_at_27[0x1];
e281682b
SM		 355 u8 inner_second_prio[0x1];
356 u8 inner_second_cfi[0x1];
357 u8 inner_second_vid[0x1];
b4ff3a36 358 u8 reserved_at_2b[0x1];
e281682b
SM		 359 u8 inner_sip[0x1];
360 u8 inner_dip[0x1];
361 u8 inner_frag[0x1];
362 u8 inner_ip_protocol[0x1];
363 u8 inner_ip_ecn[0x1];
364 u8 inner_ip_dscp[0x1];
365 u8 inner_udp_sport[0x1];
366 u8 inner_udp_dport[0x1];
367 u8 inner_tcp_sport[0x1];
368 u8 inner_tcp_dport[0x1];
369 u8 inner_tcp_flags[0x1];
b4ff3a36 370 u8 reserved_at_37[0x9];
71c6e863 371
b169e64a
YK		 372 u8 geneve_tlv_option_0_data[0x1];
373 u8 reserved_at_41[0x4];
71c6e863
AL		 374 u8 outer_first_mpls_over_udp[0x4];
375 u8 outer_first_mpls_over_gre[0x4];
376 u8 inner_first_mpls[0x4];
377 u8 outer_first_mpls[0x4];
378 u8 reserved_at_55[0x2];
3346c487 379 u8 outer_esp_spi[0x1];
71c6e863 380 u8 reserved_at_58[0x2];
a550ddfc 381 u8 bth_dst_qp[0x1];
822e114b 382 u8 reserved_at_5b[0x5];
e281682b 383
822e114b
PB		 384 u8 reserved_at_60[0x18];
385 u8 metadata_reg_c_7[0x1];
386 u8 metadata_reg_c_6[0x1];
387 u8 metadata_reg_c_5[0x1];
388 u8 metadata_reg_c_4[0x1];
389 u8 metadata_reg_c_3[0x1];
390 u8 metadata_reg_c_2[0x1];
391 u8 metadata_reg_c_1[0x1];
392 u8 metadata_reg_c_0[0x1];
e281682b
SM		 393};
394
395struct mlx5_ifc_flow_table_prop_layout_bits {
396 u8 ft_support[0x1];
9dc0b289
AV		 397 u8 reserved_at_1[0x1];
398 u8 flow_counter[0x1];
26a81453 399 u8 flow_modify_en[0x1];
2cc43b49 400 u8 modify_root[0x1];
34a40e68
MG		 401 u8 identified_miss_table_mode[0x1];
402 u8 flow_table_modify[0x1];
60786f09 403 u8 reformat[0x1];
7adbde20 404 u8 decap[0x1];
0c06897a
OG		 405 u8 reserved_at_9[0x1];
406 u8 pop_vlan[0x1];
407 u8 push_vlan[0x1];
8da6fe2a
JL		 408 u8 reserved_at_c[0x1];
409 u8 pop_vlan_2[0x1];
410 u8 push_vlan_2[0x1];
bea4e1f6 411 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 412 u8 reserved_at_10[0x1];
413 u8 sw_owner[0x1];
bea4e1f6
MB		 414 u8 reformat_l3_tunnel_to_l2[0x1];
415 u8 reformat_l2_to_l3_tunnel[0x1];
416 u8 reformat_and_modify_action[0x1];
822e114b
PB		 417 u8 ignore_flow_level[0x1];
418 u8 reserved_at_16[0x1];
f6f7d6b5 419 u8 table_miss_action_domain[0x1];
c6d4e45d 420 u8 termination_table[0x1];
e0ebd8eb 421 u8 reformat_and_fwd_to_table[0x1];
78fb6122
HN		 422 u8 reserved_at_1a[0x2];
423 u8 ipsec_encrypt[0x1];
424 u8 ipsec_decrypt[0x1];
9d8feb46
AV		 425 u8 sw_owner_v2[0x1];
426 u8 reserved_at_1f[0x1];
78fb6122 427
613f53fe
EC		 428 u8 termination_table_raw_traffic[0x1];
429 u8 reserved_at_21[0x1];
e281682b 430 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 431 u8 log_max_modify_header_context[0x8];
432 u8 max_modify_header_actions[0x8];
e281682b
SM		 433 u8 max_ft_level[0x8];
434
b4ff3a36 435 u8 reserved_at_40[0x20];
e281682b 436
b4ff3a36 437 u8 reserved_at_60[0x18];
e281682b
SM		 438 u8 log_max_ft_num[0x8];
439
b4ff3a36 440 u8 reserved_at_80[0x18];
e281682b
SM		 441 u8 log_max_destination[0x8];
442
16f1c5bb
RS		 443 u8 log_max_flow_counter[0x8];
444 u8 reserved_at_a8[0x10];
e281682b
SM		 445 u8 log_max_flow[0x8];
446
b4ff3a36 447 u8 reserved_at_c0[0x40];
e281682b
SM		 448
449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
450
451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
452};
453
454struct mlx5_ifc_odp_per_transport_service_cap_bits {
455 u8 send[0x1];
456 u8 receive[0x1];
457 u8 write[0x1];
458 u8 read[0x1];
17d2f88f 459 u8 atomic[0x1];
e281682b 460 u8 srq_receive[0x1];
b4ff3a36 461 u8 reserved_at_6[0x1a];
e281682b
SM		 462};
463
464struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
465 u8 smac_47_16[0x20];
466
467 u8 smac_15_0[0x10];
468 u8 ethertype[0x10];
469
470 u8 dmac_47_16[0x20];
471
472 u8 dmac_15_0[0x10];
473 u8 first_prio[0x3];
474 u8 first_cfi[0x1];
475 u8 first_vid[0xc];
476
477 u8 ip_protocol[0x8];
478 u8 ip_dscp[0x6];
479 u8 ip_ecn[0x2];
10543365
MHY		 480 u8 cvlan_tag[0x1];
481 u8 svlan_tag[0x1];
e281682b 482 u8 frag[0x1];
19cc7524 483 u8 ip_version[0x4];
e281682b
SM		 484 u8 tcp_flags[0x9];
485
486 u8 tcp_sport[0x10];
487 u8 tcp_dport[0x10];
488
a8ade55f
OG		 489 u8 reserved_at_c0[0x18];
490 u8 ttl_hoplimit[0x8];
e281682b
SM		 491
492 u8 udp_sport[0x10];
493 u8 udp_dport[0x10];
494
b4d1f032 495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 496
b4d1f032 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 498};
499
5886a96a
OS		 500struct mlx5_ifc_nvgre_key_bits {
501 u8 hi[0x18];
502 u8 lo[0x8];
503};
504
505union mlx5_ifc_gre_key_bits {
506 struct mlx5_ifc_nvgre_key_bits nvgre;
507 u8 key[0x20];
508};
509
e281682b 510struct mlx5_ifc_fte_match_set_misc_bits {
97b5484e 511 u8 gre_c_present[0x1];
d32d7c52 512 u8 reserved_at_1[0x1];
97b5484e
AV		 513 u8 gre_k_present[0x1];
514 u8 gre_s_present[0x1];
515 u8 source_vhca_port[0x4];
7486216b 516 u8 source_sqn[0x18];
e281682b 517
3e99df87 518 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 519 u8 source_port[0x10];
520
521 u8 outer_second_prio[0x3];
522 u8 outer_second_cfi[0x1];
523 u8 outer_second_vid[0xc];
524 u8 inner_second_prio[0x3];
525 u8 inner_second_cfi[0x1];
526 u8 inner_second_vid[0xc];
527
10543365
MHY		 528 u8 outer_second_cvlan_tag[0x1];
529 u8 inner_second_cvlan_tag[0x1];
530 u8 outer_second_svlan_tag[0x1];
531 u8 inner_second_svlan_tag[0x1];
532 u8 reserved_at_64[0xc];
e281682b
SM		 533 u8 gre_protocol[0x10];
534
5886a96a 535 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 536
537 u8 vxlan_vni[0x18];
b4ff3a36 538 u8 reserved_at_b8[0x8];
e281682b 539
75d90e7d
YK		 540 u8 geneve_vni[0x18];
541 u8 reserved_at_d8[0x7];
542 u8 geneve_oam[0x1];
e281682b 543
b4ff3a36 544 u8 reserved_at_e0[0xc];
e281682b
SM		 545 u8 outer_ipv6_flow_label[0x14];
546
b4ff3a36 547 u8 reserved_at_100[0xc];
e281682b
SM		 548 u8 inner_ipv6_flow_label[0x14];
549
75d90e7d
YK		 550 u8 reserved_at_120[0xa];
551 u8 geneve_opt_len[0x6];
552 u8 geneve_protocol_type[0x10];
553
554 u8 reserved_at_140[0x8];
a550ddfc 555 u8 bth_dst_qp[0x18];
3346c487
BP		 556 u8 reserved_at_160[0x20];
557 u8 outer_esp_spi[0x20];
558 u8 reserved_at_1a0[0x60];
e281682b
SM		 559};
560
71c6e863
AL		 561struct mlx5_ifc_fte_match_mpls_bits {
562 u8 mpls_label[0x14];
563 u8 mpls_exp[0x3];
564 u8 mpls_s_bos[0x1];
565 u8 mpls_ttl[0x8];
566};
567
568struct mlx5_ifc_fte_match_set_misc2_bits {
569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
570
571 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
572
573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
574
575 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
576
65c0f2c1
JL		 577 u8 metadata_reg_c_7[0x20];
578
579 u8 metadata_reg_c_6[0x20];
580
581 u8 metadata_reg_c_5[0x20];
582
583 u8 metadata_reg_c_4[0x20];
584
585 u8 metadata_reg_c_3[0x20];
586
587 u8 metadata_reg_c_2[0x20];
588
589 u8 metadata_reg_c_1[0x20];
590
591 u8 metadata_reg_c_0[0x20];
71c6e863
AL		 592
593 u8 metadata_reg_a[0x20];
594
356d411c 595 u8 reserved_at_1a0[0x60];
71c6e863
AL		 596};
597
b169e64a 598struct mlx5_ifc_fte_match_set_misc3_bits {
97b5484e
AV		 599 u8 inner_tcp_seq_num[0x20];
600
601 u8 outer_tcp_seq_num[0x20];
602
603 u8 inner_tcp_ack_num[0x20];
604
605 u8 outer_tcp_ack_num[0x20];
606
607 u8 reserved_at_80[0x8];
608 u8 outer_vxlan_gpe_vni[0x18];
609
610 u8 outer_vxlan_gpe_next_protocol[0x8];
611 u8 outer_vxlan_gpe_flags[0x8];
612 u8 reserved_at_b0[0x10];
613
614 u8 icmp_header_data[0x20];
615
616 u8 icmpv6_header_data[0x20];
617
618 u8 icmp_type[0x8];
619 u8 icmp_code[0x8];
620 u8 icmpv6_type[0x8];
621 u8 icmpv6_code[0x8];
622
b169e64a 623 u8 geneve_tlv_option_0_data[0x20];
97b5484e 624
b169e64a
YK		 625 u8 reserved_at_140[0xc0];
626};
627
7da3ad6c
MS		 628struct mlx5_ifc_fte_match_set_misc4_bits {
629 u8 prog_sample_field_value_0[0x20];
630
631 u8 prog_sample_field_id_0[0x20];
632
633 u8 prog_sample_field_value_1[0x20];
634
635 u8 prog_sample_field_id_1[0x20];
636
637 u8 prog_sample_field_value_2[0x20];
638
639 u8 prog_sample_field_id_2[0x20];
640
641 u8 prog_sample_field_value_3[0x20];
642
643 u8 prog_sample_field_id_3[0x20];
644
645 u8 reserved_at_100[0x100];
646};
647
e281682b
SM		 648struct mlx5_ifc_cmd_pas_bits {
649 u8 pa_h[0x20];
650
651 u8 pa_l[0x14];
b4ff3a36 652 u8 reserved_at_34[0xc];
e281682b
SM		 653};
654
655struct mlx5_ifc_uint64_bits {
656 u8 hi[0x20];
657
658 u8 lo[0x20];
659};
660
661enum {
662 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
663 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
664 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
665 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
666 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
667 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
668 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
669 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
670 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
671 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
672};
673
674struct mlx5_ifc_ads_bits {
675 u8 fl[0x1];
676 u8 free_ar[0x1];
b4ff3a36 677 u8 reserved_at_2[0xe];
e281682b
SM		 678 u8 pkey_index[0x10];
679
b4ff3a36 680 u8 reserved_at_20[0x8];
e281682b
SM		 681 u8 grh[0x1];
682 u8 mlid[0x7];
683 u8 rlid[0x10];
684
685 u8 ack_timeout[0x5];
b4ff3a36 686 u8 reserved_at_45[0x3];
e281682b 687 u8 src_addr_index[0x8];
b4ff3a36 688 u8 reserved_at_50[0x4];
e281682b
SM		 689 u8 stat_rate[0x4];
690 u8 hop_limit[0x8];
691
b4ff3a36 692 u8 reserved_at_60[0x4];
e281682b
SM		 693 u8 tclass[0x8];
694 u8 flow_label[0x14];
695
696 u8 rgid_rip[16][0x8];
697
b4ff3a36 698 u8 reserved_at_100[0x4];
e281682b
SM		 699 u8 f_dscp[0x1];
700 u8 f_ecn[0x1];
b4ff3a36 701 u8 reserved_at_106[0x1];
e281682b
SM		 702 u8 f_eth_prio[0x1];
703 u8 ecn[0x2];
704 u8 dscp[0x6];
705 u8 udp_sport[0x10];
706
707 u8 dei_cfi[0x1];
708 u8 eth_prio[0x3];
709 u8 sl[0x4];
32f69e4b 710 u8 vhca_port_num[0x8];
e281682b
SM		 711 u8 rmac_47_32[0x10];
712
713 u8 rmac_31_0[0x20];
714};
715
716struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 717 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 718 u8 nic_rx_multi_path_tirs_fts[0x1];
719 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
13a7e459
ES		 720 u8 reserved_at_3[0x4];
721 u8 sw_owner_reformat_supported[0x1];
722 u8 reserved_at_8[0x18];
723
bea4e1f6
MB		 724 u8 encap_general_header[0x1];
725 u8 reserved_at_21[0xa];
726 u8 log_max_packet_reformat_context[0x5];
727 u8 reserved_at_30[0x6];
728 u8 max_encap_header_size[0xa];
729 u8 reserved_at_40[0x1c0];
e281682b
SM		 730
731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
732
d83eb50e 733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
e281682b
SM		 734
735 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
736
737 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
738
24670b1a 739 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
e281682b
SM		 740
741 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
742
97b5484e
AV		 743 u8 reserved_at_e00[0x1200];
744
745 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
746
747 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
748
749 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
750
751 u8 reserved_at_20c0[0x5f40];
e281682b
SM		 752};
753
65c0f2c1
JL		 754enum {
755 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
756 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
757 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
758 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
759 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
760 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
761 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
762 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
763};
764
495716b1 765struct mlx5_ifc_flow_table_eswitch_cap_bits {
65c0f2c1 766 u8 fdb_to_vport_reg_c_id[0x8];
822e114b
PB		 767 u8 reserved_at_8[0xd];
768 u8 fdb_modify_header_fwd_to_table[0x1];
769 u8 reserved_at_16[0x1];
65c0f2c1
JL		 770 u8 flow_source[0x1];
771 u8 reserved_at_18[0x2];
b9aa0ba1 772 u8 multi_fdb_encap[0x1];
86f5d0f3 773 u8 egress_acl_forward_to_vport[0x1];
663f146f
VP		 774 u8 fdb_multi_path_to_table[0x1];
775 u8 reserved_at_1d[0x3];
776
777 u8 reserved_at_20[0x1e0];
495716b1
SM		 778
779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
780
781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
782
783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
784
97b5484e
AV		 785 u8 reserved_at_800[0x1000];
786
787 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
788
789 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
790
791 u8 sw_steering_uplink_icm_address_rx[0x40];
792
793 u8 sw_steering_uplink_icm_address_tx[0x40];
794
795 u8 reserved_at_1900[0x6700];
495716b1
SM		 796};
797
8bb957d2
SK		 798enum {
799 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
800 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
801};
802
d6666753
SM		 803struct mlx5_ifc_e_switch_cap_bits {
804 u8 vport_svlan_strip[0x1];
805 u8 vport_cvlan_strip[0x1];
806 u8 vport_svlan_insert[0x1];
807 u8 vport_cvlan_insert_if_not_exist[0x1];
808 u8 vport_cvlan_insert_overwrite[0x1];
65c0f2c1
JL		 809 u8 reserved_at_5[0x3];
810 u8 esw_uplink_ingress_acl[0x1];
811 u8 reserved_at_9[0x10];
6706a3b9
VP		 812 u8 esw_functions_changed[0x1];
813 u8 reserved_at_1a[0x1];
81cd229c 814 u8 ecpf_vport_exists[0x1];
8bb957d2 815 u8 counter_eswitch_affinity[0x1];
a6d04569 816 u8 merged_eswitch[0x1];
23898c76
NO		 817 u8 nic_vport_node_guid_modify[0x1];
818 u8 nic_vport_port_guid_modify[0x1];
d6666753 819
7adbde20
HHZ		 820 u8 vxlan_encap_decap[0x1];
821 u8 nvgre_encap_decap[0x1];
1b115498
EB		 822 u8 reserved_at_22[0x1];
823 u8 log_max_fdb_encap_uplink[0x5];
824 u8 reserved_at_21[0x3];
60786f09 825 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 826 u8 reserved_2b[0x6];
827 u8 max_encap_header_size[0xa];
828
1759d322
PP		 829 u8 reserved_at_40[0xb];
830 u8 log_max_esw_sf[0x5];
831 u8 esw_sf_base_id[0x10];
832
833 u8 reserved_at_60[0x7a0];
7adbde20 834
d6666753
SM		 835};
836
7486216b
SM		 837struct mlx5_ifc_qos_cap_bits {
838 u8 packet_pacing[0x1];
813f8540 839 u8 esw_scheduling[0x1];
c9497c98
MHY		 840 u8 esw_bw_share[0x1];
841 u8 esw_rate_limit[0x1];
05d3ac97
BW		 842 u8 reserved_at_4[0x1];
843 u8 packet_pacing_burst_bound[0x1];
844 u8 packet_pacing_typical_size[0x1];
1326034b
YH		 845 u8 reserved_at_7[0x4];
846 u8 packet_pacing_uid[0x1];
847 u8 reserved_at_c[0x14];
813f8540
MHY		 848
849 u8 reserved_at_20[0x20];
850
7486216b 851 u8 packet_pacing_max_rate[0x20];
813f8540 852
7486216b 853 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 854
855 u8 reserved_at_80[0x10];
7486216b 856 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 857
858 u8 esw_element_type[0x10];
859 u8 esw_tsar_type[0x10];
860
861 u8 reserved_at_c0[0x10];
862 u8 max_qos_para_vport[0x10];
863
864 u8 max_tsar_bw_share[0x20];
865
866 u8 reserved_at_100[0x700];
7486216b
SM		 867};
868
2fcb12df 869struct mlx5_ifc_debug_cap_bits {
0b9055a1
MS		 870 u8 core_dump_general[0x1];
871 u8 core_dump_qp[0x1];
609b8272
AL		 872 u8 reserved_at_2[0x7];
873 u8 resource_dump[0x1];
874 u8 reserved_at_a[0x16];
2fcb12df
IK		 875
876 u8 reserved_at_20[0x2];
877 u8 stall_detect[0x1];
878 u8 reserved_at_23[0x1d];
879
880 u8 reserved_at_40[0x7c0];
881};
882
e281682b
SM		 883struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
884 u8 csum_cap[0x1];
885 u8 vlan_cap[0x1];
886 u8 lro_cap[0x1];
887 u8 lro_psh_flag[0x1];
888 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 889 u8 reserved_at_5[0x2];
890 u8 wqe_vlan_insert[0x1];
66189961 891 u8 self_lb_en_modifiable[0x1];
b4ff3a36 892 u8 reserved_at_9[0x2];
e281682b 893 u8 max_lso_cap[0x5];
c226dc22 894 u8 multi_pkt_send_wqe[0x2];
cff92d7c 895 u8 wqe_inline_mode[0x2];
e281682b 896 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 897 u8 reg_umr_sq[0x1];
898 u8 scatter_fcs[0x1];
050da902 899 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 900 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 901 u8 reserved_at_1c[0x2];
27299841 902 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 903 u8 tunnel_stateless_vxlan[0x1];
904
547eede0
IT		 905 u8 swp[0x1];
906 u8 swp_csum[0x1];
907 u8 swp_lso[0x1];
db849faa 908 u8 cqe_checksum_full[0x1];
41e684ef
AV		 909 u8 tunnel_stateless_geneve_tx[0x1];
910 u8 tunnel_stateless_mpls_over_udp[0x1];
911 u8 tunnel_stateless_mpls_over_gre[0x1];
912 u8 tunnel_stateless_vxlan_gpe[0x1];
913 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
caa18547 914 u8 tunnel_stateless_ip_over_ip[0x1];
2b58f6d9 915 u8 insert_trailer[0x1];
21adf05d
AL		 916 u8 reserved_at_2b[0x1];
917 u8 tunnel_stateless_ip_over_ip_rx[0x1];
918 u8 tunnel_stateless_ip_over_ip_tx[0x1];
919 u8 reserved_at_2e[0x2];
22a65aa8
GP		 920 u8 max_vxlan_udp_ports[0x8];
921 u8 reserved_at_38[0x6];
4d350f1f
MG		 922 u8 max_geneve_opt_len[0x1];
923 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 924
b4ff3a36 925 u8 reserved_at_40[0x10];
e281682b
SM		 926 u8 lro_min_mss_size[0x10];
927
b4ff3a36 928 u8 reserved_at_60[0x120];
e281682b
SM		 929
930 u8 lro_timer_supported_periods[4][0x20];
931
b4ff3a36 932 u8 reserved_at_200[0x600];
e281682b
SM		 933};
934
935struct mlx5_ifc_roce_cap_bits {
936 u8 roce_apm[0x1];
59e9e8e4
MZ		 937 u8 reserved_at_1[0x3];
938 u8 sw_r_roce_src_udp_port[0x1];
939 u8 reserved_at_5[0x1b];
e281682b 940
b4ff3a36 941 u8 reserved_at_20[0x60];
e281682b 942
b4ff3a36 943 u8 reserved_at_80[0xc];
e281682b 944 u8 l3_type[0x4];
b4ff3a36 945 u8 reserved_at_90[0x8];
e281682b
SM		 946 u8 roce_version[0x8];
947
b4ff3a36 948 u8 reserved_at_a0[0x10];
e281682b
SM		 949 u8 r_roce_dest_udp_port[0x10];
950
951 u8 r_roce_max_src_udp_port[0x10];
952 u8 r_roce_min_src_udp_port[0x10];
953
b4ff3a36 954 u8 reserved_at_e0[0x10];
e281682b
SM		 955 u8 roce_address_table_size[0x10];
956
b4ff3a36 957 u8 reserved_at_100[0x700];
e281682b
SM		 958};
959
97b5484e
AV		 960struct mlx5_ifc_sync_steering_in_bits {
961 u8 opcode[0x10];
962 u8 uid[0x10];
963
964 u8 reserved_at_20[0x10];
965 u8 op_mod[0x10];
966
967 u8 reserved_at_40[0xc0];
968};
969
970struct mlx5_ifc_sync_steering_out_bits {
971 u8 status[0x8];
972 u8 reserved_at_8[0x18];
973
974 u8 syndrome[0x20];
975
976 u8 reserved_at_40[0x40];
977};
978
e72bd817
AL		 979struct mlx5_ifc_device_mem_cap_bits {
980 u8 memic[0x1];
981 u8 reserved_at_1[0x1f];
982
983 u8 reserved_at_20[0xb];
984 u8 log_min_memic_alloc_size[0x5];
985 u8 reserved_at_30[0x8];
986 u8 log_max_memic_addr_alignment[0x8];
987
988 u8 memic_bar_start_addr[0x40];
989
990 u8 memic_bar_size[0x20];
991
992 u8 max_memic_size[0x20];
993
9fba2b9b
AL		 994 u8 steering_sw_icm_start_address[0x40];
995
996 u8 reserved_at_100[0x8];
997 u8 log_header_modify_sw_icm_size[0x8];
998 u8 reserved_at_110[0x2];
999 u8 log_sw_icm_alloc_granularity[0x6];
1000 u8 log_steering_sw_icm_size[0x8];
1001
1002 u8 reserved_at_120[0x20];
1003
1004 u8 header_modify_sw_icm_start_address[0x40];
1005
1006 u8 reserved_at_180[0x680];
e72bd817
AL		 1007};
1008
b9a7ba55
YH		 1009struct mlx5_ifc_device_event_cap_bits {
1010 u8 user_affiliated_events[4][0x40];
1011
1012 u8 user_unaffiliated_events[4][0x40];
1013};
1014
8a06a79b
EC		 1015struct mlx5_ifc_virtio_emulation_cap_bits {
1016 u8 desc_tunnel_offload_type[0x1];
1017 u8 eth_frame_offload_type[0x1];
1018 u8 virtio_version_1_0[0x1];
1019 u8 device_features_bits_mask[0xd];
1020 u8 event_mode[0x8];
1021 u8 virtio_queue_type[0x8];
90fbca59 1022
8a06a79b
EC		 1023 u8 max_tunnel_desc[0x10];
1024 u8 reserved_at_30[0x3];
90fbca59
YH		 1025 u8 log_doorbell_stride[0x5];
1026 u8 reserved_at_38[0x3];
1027 u8 log_doorbell_bar_size[0x5];
1028
1029 u8 doorbell_bar_offset[0x40];
1030
8a06a79b
EC		 1031 u8 max_emulated_devices[0x8];
1032 u8 max_num_virtio_queues[0x18];
1033
1034 u8 reserved_at_a0[0x60];
1035
1036 u8 umem_1_buffer_param_a[0x20];
1037
1038 u8 umem_1_buffer_param_b[0x20];
1039
1040 u8 umem_2_buffer_param_a[0x20];
1041
1042 u8 umem_2_buffer_param_b[0x20];
1043
1044 u8 umem_3_buffer_param_a[0x20];
1045
1046 u8 umem_3_buffer_param_b[0x20];
1047
1048 u8 reserved_at_1c0[0x640];
90fbca59
YH		 1049};
1050
e281682b
SM		 1051enum {
1052 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1053 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1054 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1055 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1056 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1057 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1058 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1059 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1060 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1061};
1062
1063enum {
1064 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1065 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1066 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1067 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1068 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1069 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1070 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1071 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1072 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1073};
1074
1075struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 1076 u8 reserved_at_0[0x40];
e281682b 1077
bd10838a 1078 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 1079 u8 reserved_at_42[0x4];
bd10838a 1080 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 1081
b4ff3a36 1082 u8 reserved_at_47[0x19];
e281682b 1083
b4ff3a36 1084 u8 reserved_at_60[0x20];
e281682b 1085
b4ff3a36 1086 u8 reserved_at_80[0x10];
f91e6d89 1087 u8 atomic_operations[0x10];
e281682b 1088
b4ff3a36 1089 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 1090 u8 atomic_size_qp[0x10];
1091
b4ff3a36 1092 u8 reserved_at_c0[0x10];
e281682b
SM		 1093 u8 atomic_size_dc[0x10];
1094
b4ff3a36 1095 u8 reserved_at_e0[0x720];
e281682b
SM		 1096};
1097
1098struct mlx5_ifc_odp_cap_bits {
b4ff3a36 1099 u8 reserved_at_0[0x40];
e281682b
SM		 1100
1101 u8 sig[0x1];
b4ff3a36 1102 u8 reserved_at_41[0x1f];
e281682b 1103
b4ff3a36 1104 u8 reserved_at_60[0x20];
e281682b
SM		 1105
1106 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1107
1108 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1109
1110 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1111
dda7a817
MS		 1112 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1113
00679b63
MG		 1114 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1115
1116 u8 reserved_at_120[0x6E0];
e281682b
SM		 1117};
1118
3f0393a5
SG		 1119struct mlx5_ifc_calc_op {
1120 u8 reserved_at_0[0x10];
1121 u8 reserved_at_10[0x9];
1122 u8 op_swap_endianness[0x1];
1123 u8 op_min[0x1];
1124 u8 op_xor[0x1];
1125 u8 op_or[0x1];
1126 u8 op_and[0x1];
1127 u8 op_max[0x1];
1128 u8 op_add[0x1];
1129};
1130
1131struct mlx5_ifc_vector_calc_cap_bits {
1132 u8 calc_matrix[0x1];
1133 u8 reserved_at_1[0x1f];
1134 u8 reserved_at_20[0x8];
1135 u8 max_vec_count[0x8];
1136 u8 reserved_at_30[0xd];
1137 u8 max_chunk_size[0x3];
1138 struct mlx5_ifc_calc_op calc0;
1139 struct mlx5_ifc_calc_op calc1;
1140 struct mlx5_ifc_calc_op calc2;
1141 struct mlx5_ifc_calc_op calc3;
1142
c74d90c1 1143 u8 reserved_at_c0[0x720];
3f0393a5
SG		 1144};
1145
a12ff35e
EBE		 1146struct mlx5_ifc_tls_cap_bits {
1147 u8 tls_1_2_aes_gcm_128[0x1];
1148 u8 tls_1_3_aes_gcm_128[0x1];
1149 u8 tls_1_2_aes_gcm_256[0x1];
1150 u8 tls_1_3_aes_gcm_256[0x1];
1151 u8 reserved_at_4[0x1c];
1152
1153 u8 reserved_at_20[0x7e0];
1154};
1155
2b58f6d9
RS		 1156struct mlx5_ifc_ipsec_cap_bits {
1157 u8 ipsec_full_offload[0x1];
1158 u8 ipsec_crypto_offload[0x1];
1159 u8 ipsec_esn[0x1];
1160 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1161 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1162 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1163 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1164 u8 reserved_at_7[0x4];
1165 u8 log_max_ipsec_offload[0x5];
1166 u8 reserved_at_10[0x10];
1167
1168 u8 min_log_ipsec_full_replay_window[0x8];
1169 u8 max_log_ipsec_full_replay_window[0x8];
1170 u8 reserved_at_30[0x7d0];
1171};
1172
e281682b
SM		 1173enum {
1174 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1175 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 1176 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 1177 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 1178};
1179
1180enum {
1181 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1182 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1183};
1184
1185enum {
1186 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1187 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1188 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1189 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1190 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1191};
1192
1193enum {
1194 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1195 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1196 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1197 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1198 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1199 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1200};
1201
1202enum {
1203 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1204 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1205};
1206
1207enum {
1208 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1209 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1210 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1211};
1212
1213enum {
1214 MLX5_CAP_PORT_TYPE_IB = 0x0,
1215 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 1216};
1217
1410a90a
MG		 1218enum {
1219 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1220 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1221 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1222};
1223
97b5484e 1224enum {
a18fab48 1225 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
97b5484e
AV		 1226 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1227 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1228 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1229};
1230
9d43faac
YH		 1231enum {
1232 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 1233 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 1234};
1235
8536a6bf
GT		 1236#define MLX5_FC_BULK_SIZE_FACTOR 128
1237
1238enum mlx5_fc_bulk_alloc_bitmask {
1239 MLX5_FC_BULK_128 = (1 << 0),
1240 MLX5_FC_BULK_256 = (1 << 1),
1241 MLX5_FC_BULK_512 = (1 << 2),
1242 MLX5_FC_BULK_1024 = (1 << 3),
1243 MLX5_FC_BULK_2048 = (1 << 4),
1244 MLX5_FC_BULK_4096 = (1 << 5),
1245 MLX5_FC_BULK_8192 = (1 << 6),
1246 MLX5_FC_BULK_16384 = (1 << 7),
1247};
1248
1249#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1250
d421e466
YK		 1251enum {
1252 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1253 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1254};
1255
b775516b 1256struct mlx5_ifc_cmd_hca_cap_bits {
959af556
YH		 1257 u8 reserved_at_0[0x1f];
1258 u8 vhca_resource_manager[0x1];
349125ba
PP		 1259
1260 u8 reserved_at_20[0x3];
1261 u8 event_on_vhca_state_teardown_request[0x1];
1262 u8 event_on_vhca_state_in_use[0x1];
1263 u8 event_on_vhca_state_active[0x1];
1264 u8 event_on_vhca_state_allocated[0x1];
1265 u8 event_on_vhca_state_invalid[0x1];
1266 u8 reserved_at_28[0x8];
32f69e4b
DJ		 1267 u8 vhca_id[0x10];
1268
1269 u8 reserved_at_40[0x40];
b775516b
EC		 1270
1271 u8 log_max_srq_sz[0x8];
1272 u8 log_max_qp_sz[0x8];
b9a7ba55
YH		 1273 u8 event_cap[0x1];
1274 u8 reserved_at_91[0x7];
316793fb
EB		 1275 u8 prio_tag_required[0x1];
1276 u8 reserved_at_99[0x2];
b775516b
EC		 1277 u8 log_max_qp[0x5];
1278
6b646a7e
LR		 1279 u8 reserved_at_a0[0x3];
1280 u8 ece_support[0x1];
1281 u8 reserved_at_a4[0x7];
e281682b 1282 u8 log_max_srq[0x5];
9c9be85f
AL		 1283 u8 reserved_at_b0[0x1];
1284 u8 uplink_follow[0x1];
59d2ae1d
EBE		 1285 u8 ts_cqe_to_dest_cqn[0x1];
1286 u8 reserved_at_b3[0xd];
b775516b 1287
7d47433c 1288 u8 max_sgl_for_optimized_performance[0x8];
b775516b 1289 u8 log_max_cq_sz[0x8];
042dd05b
ML		 1290 u8 relaxed_ordering_write_umr[0x1];
1291 u8 relaxed_ordering_read_umr[0x1];
1292 u8 reserved_at_d2[0x7];
8a06a79b
EC		 1293 u8 virtio_net_device_emualtion_manager[0x1];
1294 u8 virtio_blk_device_emualtion_manager[0x1];
b775516b
EC		 1295 u8 log_max_cq[0x5];
1296
1297 u8 log_max_eq_sz[0x8];
a880a6dd
MG		 1298 u8 relaxed_ordering_write[0x1];
1299 u8 relaxed_ordering_read[0x1];
b775516b 1300 u8 log_max_mkey[0x6];
b183ee27
LR		 1301 u8 reserved_at_f0[0x8];
1302 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 1303 u8 reserved_at_f9[0x2];
1304 u8 fast_teardown[0x1];
b775516b
EC		 1305 u8 log_max_eq[0x4];
1306
1307 u8 max_indirection[0x8];
bcda1aca 1308 u8 fixed_buffer_size[0x1];
b775516b 1309 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 1310 u8 force_teardown[0x1];
1311 u8 reserved_at_111[0x1];
b775516b 1312 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 1313 u8 umr_extended_translation_offset[0x1];
1314 u8 null_mkey[0x1];
b775516b
EC		 1315 u8 log_max_klm_list_size[0x6];
1316
b4ff3a36 1317 u8 reserved_at_120[0xa];
b775516b 1318 u8 log_max_ra_req_dc[0x6];
b4ff3a36 1319 u8 reserved_at_130[0xa];
b775516b
EC		 1320 u8 log_max_ra_res_dc[0x6];
1321
0e1533bb
EBE		 1322 u8 reserved_at_140[0x6];
1323 u8 release_all_pages[0x1];
1324 u8 reserved_at_147[0x2];
8fd5b75d 1325 u8 roce_accl[0x1];
b775516b 1326 u8 log_max_ra_req_qp[0x6];
b4ff3a36 1327 u8 reserved_at_150[0xa];
b775516b
EC		 1328 u8 log_max_ra_res_qp[0x6];
1329
f32f5bd2 1330 u8 end_pad[0x1];
b775516b
EC		 1331 u8 cc_query_allowed[0x1];
1332 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 1333 u8 start_pad[0x1];
1334 u8 cache_line_128byte[0x1];
f8efee08
MZ		 1335 u8 reserved_at_165[0x4];
1336 u8 rts2rts_qp_counters_set_id[0x1];
30b10e89
MS		 1337 u8 reserved_at_16a[0x2];
1338 u8 vnic_env_int_rq_oob[0x1];
948d3f90
AL		 1339 u8 sbcam_reg[0x1];
1340 u8 reserved_at_16e[0x1];
c02762eb 1341 u8 qcam_reg[0x1];
e281682b 1342 u8 gid_table_size[0x10];
b775516b 1343
e281682b
SM		 1344 u8 out_of_seq_cnt[0x1];
1345 u8 vport_counters[0x1];
7486216b 1346 u8 retransmission_q_counters[0x1];
2fcb12df 1347 u8 debug[0x1];
83b502a1 1348 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1349 u8 rq_delay_drop[0x1];
b775516b
EC		 1350 u8 max_qp_cnt[0xa];
1351 u8 pkey_table_size[0x10];
1352
e281682b
SM		 1353 u8 vport_group_manager[0x1];
1354 u8 vhca_group_manager[0x1];
1355 u8 ib_virt[0x1];
1356 u8 eth_virt[0x1];
61c5b5c9 1357 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1358 u8 ets[0x1];
1359 u8 nic_flow_table[0x1];
0efc8562 1360 u8 eswitch_manager[0x1];
e72bd817 1361 u8 device_memory[0x1];
cfdcbcea
GP		 1362 u8 mcam_reg[0x1];
1363 u8 pcam_reg[0x1];
b775516b 1364 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1365 u8 port_module_event[0x1];
58dcb60a 1366 u8 enhanced_error_q_counters[0x1];
7d5e1423 1367 u8 ports_check[0x1];
7b13558f 1368 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1369 u8 disable_link_up[0x1];
1370 u8 beacon_led[0x1];
e281682b 1371 u8 port_type[0x2];
b775516b
EC		 1372 u8 num_ports[0x8];
1373
f9a1ef72
EE		 1374 u8 reserved_at_1c0[0x1];
1375 u8 pps[0x1];
1376 u8 pps_modify[0x1];
b775516b 1377 u8 log_max_msg[0x5];
e1c9c62b 1378 u8 reserved_at_1c8[0x4];
4f3961ee 1379 u8 max_tc[0x4];
1865ea9a 1380 u8 temp_warn_event[0x1];
7486216b 1381 u8 dcbx[0x1];
246ac981
MG		 1382 u8 general_notification_event[0x1];
1383 u8 reserved_at_1d3[0x2];
e29341fb 1384 u8 fpga[0x1];
928cfe87
TT		 1385 u8 rol_s[0x1];
1386 u8 rol_g[0x1];
e1c9c62b 1387 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1388 u8 wol_s[0x1];
1389 u8 wol_g[0x1];
1390 u8 wol_a[0x1];
1391 u8 wol_b[0x1];
1392 u8 wol_m[0x1];
1393 u8 wol_u[0x1];
1394 u8 wol_p[0x1];
b775516b
EC		 1395
1396 u8 stat_rate_support[0x10];
3df01077
MS		 1397 u8 reserved_at_1f0[0x1];
1398 u8 pci_sync_for_fw_update_event[0x1];
cfc1a89e
MG		 1399 u8 reserved_at_1f2[0x6];
1400 u8 init2_lag_tx_port_affinity[0x1];
1401 u8 reserved_at_1fa[0x3];
e281682b 1402 u8 cqe_version[0x4];
b775516b 1403
e281682b 1404 u8 compact_address_vector[0x1];
7d5e1423 1405 u8 striding_rq[0x1];
500a3d0d
ES		 1406 u8 reserved_at_202[0x1];
1407 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1408 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1409 u8 reserved_at_205[0x1];
1410 u8 repeated_block_disabled[0x1];
1411 u8 umr_modify_entity_size_disabled[0x1];
1412 u8 umr_modify_atomic_disabled[0x1];
1413 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1414 u8 umr_fence[0x2];
94a04d1d
YC		 1415 u8 dc_req_scat_data_cqe[0x1];
1416 u8 reserved_at_20d[0x2];
e281682b 1417 u8 drain_sigerr[0x1];
b775516b
EC		 1418 u8 cmdif_checksum[0x2];
1419 u8 sigerr_cqe[0x1];
e1c9c62b 1420 u8 reserved_at_213[0x1];
b775516b
EC		 1421 u8 wq_signature[0x1];
1422 u8 sctr_data_cqe[0x1];
e1c9c62b 1423 u8 reserved_at_216[0x1];
b775516b
EC		 1424 u8 sho[0x1];
1425 u8 tph[0x1];
1426 u8 rf[0x1];
e281682b 1427 u8 dct[0x1];
7486216b 1428 u8 qos[0x1];
e281682b 1429 u8 eth_net_offloads[0x1];
b775516b
EC		 1430 u8 roce[0x1];
1431 u8 atomic[0x1];
e1c9c62b 1432 u8 reserved_at_21f[0x1];
b775516b
EC		 1433
1434 u8 cq_oi[0x1];
1435 u8 cq_resize[0x1];
1436 u8 cq_moderation[0x1];
e1c9c62b 1437 u8 reserved_at_223[0x3];
e281682b 1438 u8 cq_eq_remap[0x1];
b775516b
EC		 1439 u8 pg[0x1];
1440 u8 block_lb_mc[0x1];
e1c9c62b 1441 u8 reserved_at_229[0x1];
e281682b 1442 u8 scqe_break_moderation[0x1];
7d5e1423 1443 u8 cq_period_start_from_cqe[0x1];
b775516b 1444 u8 cd[0x1];
e1c9c62b 1445 u8 reserved_at_22d[0x1];
b775516b 1446 u8 apm[0x1];
3f0393a5 1447 u8 vector_calc[0x1];
7d5e1423 1448 u8 umr_ptr_rlky[0x1];
d2370e0a 1449 u8 imaicl[0x1];
3fd3c80a
DG		 1450 u8 qp_packet_based[0x1];
1451 u8 reserved_at_233[0x3];
b775516b
EC		 1452 u8 qkv[0x1];
1453 u8 pkv[0x1];
b11a4f9c
HE		 1454 u8 set_deth_sqpn[0x1];
1455 u8 reserved_at_239[0x3];
b775516b
EC		 1456 u8 xrc[0x1];
1457 u8 ud[0x1];
1458 u8 uc[0x1];
1459 u8 rc[0x1];
1460
a6d51b68
EC		 1461 u8 uar_4k[0x1];
1462 u8 reserved_at_241[0x9];
b775516b 1463 u8 uar_sz[0x6];
e1c9c62b 1464 u8 reserved_at_250[0x8];
b775516b
EC		 1465 u8 log_pg_sz[0x8];
1466
1467 u8 bf[0x1];
0dbc6fe0 1468 u8 driver_version[0x1];
e281682b 1469 u8 pad_tx_eth_packet[0x1];
4dca6509
MG		 1470 u8 reserved_at_263[0x3];
1471 u8 mkey_by_name[0x1];
1472 u8 reserved_at_267[0x4];
1473
b775516b 1474 u8 log_bf_reg_size[0x5];
84df61eb 1475
7c4b1ab9
MZ		 1476 u8 reserved_at_270[0x6];
1477 u8 lag_dct[0x2];
1eba383f
MM		 1478 u8 lag_tx_port_affinity[0x1];
1479 u8 reserved_at_279[0x2];
84df61eb
AH		 1480 u8 lag_master[0x1];
1481 u8 num_lag_ports[0x4];
b775516b 1482
e1c9c62b 1483 u8 reserved_at_280[0x10];
b775516b
EC		 1484 u8 max_wqe_sz_sq[0x10];
1485
e1c9c62b 1486 u8 reserved_at_2a0[0x10];
b775516b
EC		 1487 u8 max_wqe_sz_rq[0x10];
1488
a8ffcc74 1489 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1490 u8 max_wqe_sz_sq_dc[0x10];
1491
e1c9c62b 1492 u8 reserved_at_2e0[0x7];
b775516b
EC		 1493 u8 max_qp_mcg[0x19];
1494
8536a6bf
GT		 1495 u8 reserved_at_300[0x10];
1496 u8 flow_counter_bulk_alloc[0x8];
b775516b
EC		 1497 u8 log_max_mcg[0x8];
1498
e1c9c62b 1499 u8 reserved_at_320[0x3];
e281682b 1500 u8 log_max_transport_domain[0x5];
e1c9c62b 1501 u8 reserved_at_328[0x3];
b775516b 1502 u8 log_max_pd[0x5];
e1c9c62b 1503 u8 reserved_at_330[0xb];
b775516b
EC		 1504 u8 log_max_xrcd[0x5];
1505
5c298143 1506 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1507 u8 receive_discard_vport_down[0x1];
1508 u8 transmit_discard_vport_down[0x1];
1509 u8 reserved_at_343[0x5];
a351a1b0 1510 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1511 u8 max_flow_counter_15_0[0x10];
a351a1b0 1512
b775516b 1513
e1c9c62b 1514 u8 reserved_at_360[0x3];
b775516b 1515 u8 log_max_rq[0x5];
e1c9c62b 1516 u8 reserved_at_368[0x3];
b775516b 1517 u8 log_max_sq[0x5];
e1c9c62b 1518 u8 reserved_at_370[0x3];
b775516b 1519 u8 log_max_tir[0x5];
e1c9c62b 1520 u8 reserved_at_378[0x3];
b775516b
EC		 1521 u8 log_max_tis[0x5];
1522
e281682b 1523 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1524 u8 reserved_at_381[0x2];
e281682b 1525 u8 log_max_rmp[0x5];
e1c9c62b 1526 u8 reserved_at_388[0x3];
e281682b 1527 u8 log_max_rqt[0x5];
e1c9c62b 1528 u8 reserved_at_390[0x3];
e281682b 1529 u8 log_max_rqt_size[0x5];
e1c9c62b 1530 u8 reserved_at_398[0x3];
b775516b
EC		 1531 u8 log_max_tis_per_sq[0x5];
1532
619a8f2a
TT		 1533 u8 ext_stride_num_range[0x1];
1534 u8 reserved_at_3a1[0x2];
e281682b 1535 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1536 u8 reserved_at_3a8[0x3];
e281682b 1537 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1538 u8 reserved_at_3b0[0x3];
e281682b 1539 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1540 u8 reserved_at_3b8[0x3];
e281682b
SM		 1541 u8 log_min_stride_sz_sq[0x5];
1542
40817cdb
OG		 1543 u8 hairpin[0x1];
1544 u8 reserved_at_3c1[0x2];
1545 u8 log_max_hairpin_queues[0x5];
1546 u8 reserved_at_3c8[0x3];
1547 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1548 u8 reserved_at_3d0[0x3];
1549 u8 log_max_hairpin_num_packets[0x5];
1550 u8 reserved_at_3d8[0x3];
e281682b
SM		 1551 u8 log_max_wq_sz[0x5];
1552
54f0a411 1553 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1554 u8 disable_local_lb_uc[0x1];
1555 u8 disable_local_lb_mc[0x1];
40817cdb 1556 u8 log_min_hairpin_wq_data_sz[0x5];
349125ba
PP		 1557 u8 reserved_at_3e8[0x2];
1558 u8 vhca_state[0x1];
54f0a411 1559 u8 log_max_vlan_list[0x5];
e1c9c62b 1560 u8 reserved_at_3f0[0x3];
54f0a411 1561 u8 log_max_current_mc_list[0x5];
e1c9c62b 1562 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1563 u8 log_max_current_uc_list[0x5];
1564
38b7ca92
YH		 1565 u8 general_obj_types[0x40];
1566
d421e466
YK		 1567 u8 reserved_at_440[0x4];
1568 u8 steering_format_version[0x4];
1569 u8 create_qp_start_hint[0x18];
342ac844 1570
61c00cca 1571 u8 reserved_at_460[0x3];
6e3722ba 1572 u8 log_max_uctx[0x5];
2b58f6d9
RS		 1573 u8 reserved_at_468[0x2];
1574 u8 ipsec_offload[0x1];
6e3722ba 1575 u8 log_max_umem[0x5];
342ac844 1576 u8 max_num_eqs[0x10];
54f0a411 1577
61c00cca
TT		 1578 u8 reserved_at_480[0x1];
1579 u8 tls_tx[0x1];
ee5cdf7a 1580 u8 tls_rx[0x1];
e281682b 1581 u8 log_max_l2_table[0x5];
e1c9c62b 1582 u8 reserved_at_488[0x8];
b775516b
EC		 1583 u8 log_uar_page_sz[0x10];
1584
e1c9c62b 1585 u8 reserved_at_4a0[0x20];
048ccca8 1586 u8 device_frequency_mhz[0x20];
b0844444 1587 u8 device_frequency_khz[0x20];
e1c9c62b 1588
a6d51b68
EC		 1589 u8 reserved_at_500[0x20];
1590 u8 num_of_uars_per_page[0x20];
e1c9c62b 1591
e818e255 1592 u8 flex_parser_protocols[0x20];
e1c9c62b 1593
b169e64a
YK		 1594 u8 max_geneve_tlv_options[0x8];
1595 u8 reserved_at_568[0x3];
1596 u8 max_geneve_tlv_option_data_len[0x5];
1597 u8 reserved_at_570[0x10];
e1c9c62b 1598
a12ff35e
EBE		 1599 u8 reserved_at_580[0x33];
1600 u8 log_max_dek[0x5];
1601 u8 reserved_at_5b8[0x4];
ab741b2e 1602 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1603 u8 cqe_128_always[0x1];
1604 u8 cqe_compression_128[0x1];
7d5e1423 1605 u8 cqe_compression[0x1];
b775516b 1606
7d5e1423
SM		 1607 u8 cqe_compression_timeout[0x10];
1608 u8 cqe_compression_max_num[0x10];
b775516b 1609
7486216b
SM		 1610 u8 reserved_at_5e0[0x10];
1611 u8 tag_matching[0x1];
1612 u8 rndv_offload_rc[0x1];
1613 u8 rndv_offload_dc[0x1];
1614 u8 log_tag_matching_list_sz[0x5];
7b13558f 1615 u8 reserved_at_5f8[0x3];
7486216b
SM		 1616 u8 log_max_xrq[0x5];
1617
32f69e4b
DJ		 1618 u8 affiliate_nic_vport_criteria[0x8];
1619 u8 native_port_num[0x8];
1620 u8 num_vhca_ports[0x8];
1621 u8 reserved_at_618[0x6];
1622 u8 sw_owner_id[0x1];
9d43faac
YH		 1623 u8 reserved_at_61f[0x1];
1624
fd4572b3
ED		 1625 u8 max_num_of_monitor_counters[0x10];
1626 u8 num_ppcnt_monitor_counters[0x10];
1627
349125ba 1628 u8 max_num_sf[0x10];
fd4572b3
ED		 1629 u8 num_q_monitor_counters[0x10];
1630
1759d322
PP		 1631 u8 reserved_at_660[0x20];
1632
1633 u8 sf[0x1];
1634 u8 sf_set_partition[0x1];
1635 u8 reserved_at_682[0x1];
1636 u8 log_max_sf[0x5];
1637 u8 reserved_at_688[0x8];
1638 u8 log_min_sf_size[0x8];
1639 u8 max_num_sf_partitions[0x8];
9d43faac
YH		 1640
1641 u8 uctx_cap[0x20];
1642
b169e64a
YK		 1643 u8 reserved_at_6c0[0x4];
1644 u8 flex_parser_id_geneve_tlv_option_0[0x4];
97b5484e
AV		 1645 u8 flex_parser_id_icmp_dw1[0x4];
1646 u8 flex_parser_id_icmp_dw0[0x4];
1647 u8 flex_parser_id_icmpv6_dw1[0x4];
1648 u8 flex_parser_id_icmpv6_dw0[0x4];
1649 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1650 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1651
1652 u8 reserved_at_6e0[0x10];
1759d322
PP		 1653 u8 sf_base_id[0x10];
1654
1dd7382b
MG		 1655 u8 reserved_at_700[0x80];
1656 u8 vhca_tunnel_commands[0x40];
1657 u8 reserved_at_7c0[0x40];
b775516b
EC		 1658};
1659
81848731
SM		 1660enum mlx5_flow_destination_type {
1661 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1662 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1663 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
38730630 1664 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
bd5251db 1665
5f418378 1666 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1667 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
664000b6 1668 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
e281682b 1669};
b775516b 1670
f6f7d6b5
MG		 1671enum mlx5_flow_table_miss_action {
1672 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1673 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1674 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1675};
1676
e281682b
SM		 1677struct mlx5_ifc_dest_format_struct_bits {
1678 u8 destination_type[0x8];
1679 u8 destination_id[0x18];
1b115498 1680
b17f7fc1 1681 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1682 u8 packet_reformat[0x1];
1683 u8 reserved_at_22[0xe];
b17f7fc1 1684 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1685};
1686
9dc0b289 1687struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1688 u8 flow_counter_id[0x20];
9dc0b289
AV		 1689
1690 u8 reserved_at_20[0x20];
1691};
1692
1b115498
EB		 1693struct mlx5_ifc_extended_dest_format_bits {
1694 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1695
1696 u8 packet_reformat_id[0x20];
1697
1698 u8 reserved_at_60[0x20];
1699};
1700
9dc0b289 1701union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
6dfef396 1702 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
9dc0b289 1703 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
9dc0b289
AV		 1704};
1705
e281682b
SM		 1706struct mlx5_ifc_fte_match_param_bits {
1707 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1708
1709 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1710
1711 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1712
71c6e863
AL		 1713 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1714
b169e64a
YK		 1715 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1716
7da3ad6c
MS		 1717 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1718
1719 u8 reserved_at_c00[0x400];
b775516b
EC		 1720};
1721
e281682b
SM		 1722enum {
1723 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1724 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1725 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1726 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1727 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1728};
b775516b 1729
e281682b
SM		 1730struct mlx5_ifc_rx_hash_field_select_bits {
1731 u8 l3_prot_type[0x1];
1732 u8 l4_prot_type[0x1];
1733 u8 selected_fields[0x1e];
1734};
b775516b 1735
e281682b
SM		 1736enum {
1737 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1738 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1739};
1740
e281682b
SM		 1741enum {
1742 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1743 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1744};
1745
1746struct mlx5_ifc_wq_bits {
1747 u8 wq_type[0x4];
1748 u8 wq_signature[0x1];
1749 u8 end_padding_mode[0x2];
1750 u8 cd_slave[0x1];
b4ff3a36 1751 u8 reserved_at_8[0x18];
b775516b 1752
e281682b
SM		 1753 u8 hds_skip_first_sge[0x1];
1754 u8 log2_hds_buf_size[0x3];
b4ff3a36 1755 u8 reserved_at_24[0x7];
e281682b
SM		 1756 u8 page_offset[0x5];
1757 u8 lwm[0x10];
b775516b 1758
b4ff3a36 1759 u8 reserved_at_40[0x8];
e281682b
SM		 1760 u8 pd[0x18];
1761
b4ff3a36 1762 u8 reserved_at_60[0x8];
e281682b
SM		 1763 u8 uar_page[0x18];
1764
1765 u8 dbr_addr[0x40];
1766
1767 u8 hw_counter[0x20];
1768
1769 u8 sw_counter[0x20];
1770
b4ff3a36 1771 u8 reserved_at_100[0xc];
e281682b 1772 u8 log_wq_stride[0x4];
b4ff3a36 1773 u8 reserved_at_110[0x3];
e281682b 1774 u8 log_wq_pg_sz[0x5];
b4ff3a36 1775 u8 reserved_at_118[0x3];
e281682b
SM		 1776 u8 log_wq_sz[0x5];
1777
bd371975
LR		 1778 u8 dbr_umem_valid[0x1];
1779 u8 wq_umem_valid[0x1];
1780 u8 reserved_at_122[0x1];
4d533e0f
OG		 1781 u8 log_hairpin_num_packets[0x5];
1782 u8 reserved_at_128[0x3];
40817cdb 1783 u8 log_hairpin_data_sz[0x5];
40817cdb 1784
619a8f2a
TT		 1785 u8 reserved_at_130[0x4];
1786 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1787 u8 two_byte_shift_en[0x1];
1788 u8 reserved_at_139[0x4];
1789 u8 log_wqe_stride_size[0x3];
1790
1791 u8 reserved_at_140[0x4c0];
b775516b 1792
b6ca09cb 1793 struct mlx5_ifc_cmd_pas_bits pas[];
b775516b
EC		 1794};
1795
e281682b 1796struct mlx5_ifc_rq_num_bits {
b4ff3a36 1797 u8 reserved_at_0[0x8];
e281682b
SM		 1798 u8 rq_num[0x18];
1799};
b775516b 1800
e281682b 1801struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1802 u8 reserved_at_0[0x10];
e281682b 1803 u8 mac_addr_47_32[0x10];
b775516b 1804
e281682b
SM		 1805 u8 mac_addr_31_0[0x20];
1806};
1807
c0046cf7 1808struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1809 u8 reserved_at_0[0x14];
c0046cf7
SM		 1810 u8 vlan[0x0c];
1811
b4ff3a36 1812 u8 reserved_at_20[0x20];
c0046cf7
SM		 1813};
1814
e281682b 1815struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1816 u8 reserved_at_0[0xa0];
e281682b
SM		 1817
1818 u8 min_time_between_cnps[0x20];
1819
b4ff3a36 1820 u8 reserved_at_c0[0x12];
e281682b 1821 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1822 u8 reserved_at_d8[0x4];
1823 u8 cnp_prio_mode[0x1];
e281682b
SM		 1824 u8 cnp_802p_prio[0x3];
1825
b4ff3a36 1826 u8 reserved_at_e0[0x720];
e281682b
SM		 1827};
1828
1829struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1830 u8 reserved_at_0[0x60];
e281682b 1831
b4ff3a36 1832 u8 reserved_at_60[0x4];
e281682b 1833 u8 clamp_tgt_rate[0x1];
b4ff3a36 1834 u8 reserved_at_65[0x3];
e281682b 1835 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1836 u8 reserved_at_69[0x17];
e281682b 1837
b4ff3a36 1838 u8 reserved_at_80[0x20];
e281682b
SM		 1839
1840 u8 rpg_time_reset[0x20];
1841
1842 u8 rpg_byte_reset[0x20];
1843
1844 u8 rpg_threshold[0x20];
1845
1846 u8 rpg_max_rate[0x20];
1847
1848 u8 rpg_ai_rate[0x20];
1849
1850 u8 rpg_hai_rate[0x20];
1851
1852 u8 rpg_gd[0x20];
1853
1854 u8 rpg_min_dec_fac[0x20];
1855
1856 u8 rpg_min_rate[0x20];
1857
b4ff3a36 1858 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1859
1860 u8 rate_to_set_on_first_cnp[0x20];
1861
1862 u8 dce_tcp_g[0x20];
1863
1864 u8 dce_tcp_rtt[0x20];
1865
1866 u8 rate_reduce_monitor_period[0x20];
1867
b4ff3a36 1868 u8 reserved_at_320[0x20];
e281682b
SM		 1869
1870 u8 initial_alpha_value[0x20];
1871
b4ff3a36 1872 u8 reserved_at_360[0x4a0];
e281682b
SM		 1873};
1874
1875struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1876 u8 reserved_at_0[0x80];
e281682b
SM		 1877
1878 u8 rppp_max_rps[0x20];
1879
1880 u8 rpg_time_reset[0x20];
1881
1882 u8 rpg_byte_reset[0x20];
1883
1884 u8 rpg_threshold[0x20];
1885
1886 u8 rpg_max_rate[0x20];
1887
1888 u8 rpg_ai_rate[0x20];
1889
1890 u8 rpg_hai_rate[0x20];
1891
1892 u8 rpg_gd[0x20];
1893
1894 u8 rpg_min_dec_fac[0x20];
1895
1896 u8 rpg_min_rate[0x20];
1897
b4ff3a36 1898 u8 reserved_at_1c0[0x640];
e281682b
SM		 1899};
1900
1901enum {
1902 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1903 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1904 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1905};
1906
1907struct mlx5_ifc_resize_field_select_bits {
1908 u8 resize_field_select[0x20];
1909};
1910
609b8272
AL		 1911struct mlx5_ifc_resource_dump_bits {
1912 u8 more_dump[0x1];
1913 u8 inline_dump[0x1];
1914 u8 reserved_at_2[0xa];
1915 u8 seq_num[0x4];
1916 u8 segment_type[0x10];
1917
1918 u8 reserved_at_20[0x10];
1919 u8 vhca_id[0x10];
1920
1921 u8 index1[0x20];
1922
1923 u8 index2[0x20];
1924
1925 u8 num_of_obj1[0x10];
1926 u8 num_of_obj2[0x10];
1927
1928 u8 reserved_at_a0[0x20];
1929
1930 u8 device_opaque[0x40];
1931
1932 u8 mkey[0x20];
1933
1934 u8 size[0x20];
1935
1936 u8 address[0x40];
1937
1938 u8 inline_data[52][0x20];
1939};
1940
1941struct mlx5_ifc_resource_dump_menu_record_bits {
1942 u8 reserved_at_0[0x4];
1943 u8 num_of_obj2_supports_active[0x1];
1944 u8 num_of_obj2_supports_all[0x1];
1945 u8 must_have_num_of_obj2[0x1];
1946 u8 support_num_of_obj2[0x1];
1947 u8 num_of_obj1_supports_active[0x1];
1948 u8 num_of_obj1_supports_all[0x1];
1949 u8 must_have_num_of_obj1[0x1];
1950 u8 support_num_of_obj1[0x1];
1951 u8 must_have_index2[0x1];
1952 u8 support_index2[0x1];
1953 u8 must_have_index1[0x1];
1954 u8 support_index1[0x1];
1955 u8 segment_type[0x10];
1956
1957 u8 segment_name[4][0x20];
1958
1959 u8 index1_name[4][0x20];
1960
1961 u8 index2_name[4][0x20];
1962};
1963
1964struct mlx5_ifc_resource_dump_segment_header_bits {
1965 u8 length_dw[0x10];
1966 u8 segment_type[0x10];
1967};
1968
1969struct mlx5_ifc_resource_dump_command_segment_bits {
1970 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1971
1972 u8 segment_called[0x10];
1973 u8 vhca_id[0x10];
1974
1975 u8 index1[0x20];
1976
1977 u8 index2[0x20];
1978
1979 u8 num_of_obj1[0x10];
1980 u8 num_of_obj2[0x10];
1981};
1982
1983struct mlx5_ifc_resource_dump_error_segment_bits {
1984 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1985
1986 u8 reserved_at_20[0x10];
1987 u8 syndrome_id[0x10];
1988
1989 u8 reserved_at_40[0x40];
1990
1991 u8 error[8][0x20];
1992};
1993
1994struct mlx5_ifc_resource_dump_info_segment_bits {
1995 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1996
1997 u8 reserved_at_20[0x18];
1998 u8 dump_version[0x8];
1999
2000 u8 hw_version[0x20];
2001
2002 u8 fw_version[0x20];
2003};
2004
2005struct mlx5_ifc_resource_dump_menu_segment_bits {
2006 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2007
2008 u8 reserved_at_20[0x10];
2009 u8 num_of_records[0x10];
2010
b6ca09cb 2011 struct mlx5_ifc_resource_dump_menu_record_bits record[];
609b8272
AL		 2012};
2013
2014struct mlx5_ifc_resource_dump_resource_segment_bits {
2015 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2016
2017 u8 reserved_at_20[0x20];
2018
2019 u8 index1[0x20];
2020
2021 u8 index2[0x20];
2022
b6ca09cb 2023 u8 payload[][0x20];
609b8272
AL		 2024};
2025
2026struct mlx5_ifc_resource_dump_terminate_segment_bits {
2027 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2028};
2029
2030struct mlx5_ifc_menu_resource_dump_response_bits {
2031 struct mlx5_ifc_resource_dump_info_segment_bits info;
2032 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2033 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2034 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2035};
2036
e281682b
SM		 2037enum {
2038 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2039 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2040 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2041 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2042};
2043
2044struct mlx5_ifc_modify_field_select_bits {
2045 u8 modify_field_select[0x20];
2046};
2047
2048struct mlx5_ifc_field_select_r_roce_np_bits {
2049 u8 field_select_r_roce_np[0x20];
2050};
2051
2052struct mlx5_ifc_field_select_r_roce_rp_bits {
2053 u8 field_select_r_roce_rp[0x20];
2054};
2055
2056enum {
2057 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2058 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2059 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2060 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2061 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2062 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2063 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2064 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2065 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2066 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2067};
2068
2069struct mlx5_ifc_field_select_802_1qau_rp_bits {
2070 u8 field_select_8021qaurp[0x20];
2071};
2072
2073struct mlx5_ifc_phys_layer_cntrs_bits {
2074 u8 time_since_last_clear_high[0x20];
2075
2076 u8 time_since_last_clear_low[0x20];
2077
2078 u8 symbol_errors_high[0x20];
2079
2080 u8 symbol_errors_low[0x20];
2081
2082 u8 sync_headers_errors_high[0x20];
2083
2084 u8 sync_headers_errors_low[0x20];
2085
2086 u8 edpl_bip_errors_lane0_high[0x20];
2087
2088 u8 edpl_bip_errors_lane0_low[0x20];
2089
2090 u8 edpl_bip_errors_lane1_high[0x20];
2091
2092 u8 edpl_bip_errors_lane1_low[0x20];
2093
2094 u8 edpl_bip_errors_lane2_high[0x20];
2095
2096 u8 edpl_bip_errors_lane2_low[0x20];
2097
2098 u8 edpl_bip_errors_lane3_high[0x20];
2099
2100 u8 edpl_bip_errors_lane3_low[0x20];
2101
2102 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2103
2104 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2105
2106 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2107
2108 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2109
2110 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2111
2112 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2113
2114 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2115
2116 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2117
2118 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2119
2120 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2121
2122 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2123
2124 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2125
2126 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2127
2128 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2129
2130 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2131
2132 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2133
2134 u8 rs_fec_corrected_blocks_high[0x20];
2135
2136 u8 rs_fec_corrected_blocks_low[0x20];
2137
2138 u8 rs_fec_uncorrectable_blocks_high[0x20];
2139
2140 u8 rs_fec_uncorrectable_blocks_low[0x20];
2141
2142 u8 rs_fec_no_errors_blocks_high[0x20];
2143
2144 u8 rs_fec_no_errors_blocks_low[0x20];
2145
2146 u8 rs_fec_single_error_blocks_high[0x20];
2147
2148 u8 rs_fec_single_error_blocks_low[0x20];
2149
2150 u8 rs_fec_corrected_symbols_total_high[0x20];
2151
2152 u8 rs_fec_corrected_symbols_total_low[0x20];
2153
2154 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2155
2156 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2157
2158 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2159
2160 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2161
2162 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2163
2164 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2165
2166 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2167
2168 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2169
2170 u8 link_down_events[0x20];
2171
2172 u8 successful_recovery_events[0x20];
2173
b4ff3a36 2174 u8 reserved_at_640[0x180];
e281682b
SM		 2175};
2176
d8dc0508
GP		 2177struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2178 u8 time_since_last_clear_high[0x20];
2179
2180 u8 time_since_last_clear_low[0x20];
2181
2182 u8 phy_received_bits_high[0x20];
2183
2184 u8 phy_received_bits_low[0x20];
2185
2186 u8 phy_symbol_errors_high[0x20];
2187
2188 u8 phy_symbol_errors_low[0x20];
2189
2190 u8 phy_corrected_bits_high[0x20];
2191
2192 u8 phy_corrected_bits_low[0x20];
2193
2194 u8 phy_corrected_bits_lane0_high[0x20];
2195
2196 u8 phy_corrected_bits_lane0_low[0x20];
2197
2198 u8 phy_corrected_bits_lane1_high[0x20];
2199
2200 u8 phy_corrected_bits_lane1_low[0x20];
2201
2202 u8 phy_corrected_bits_lane2_high[0x20];
2203
2204 u8 phy_corrected_bits_lane2_low[0x20];
2205
2206 u8 phy_corrected_bits_lane3_high[0x20];
2207
2208 u8 phy_corrected_bits_lane3_low[0x20];
2209
2210 u8 reserved_at_200[0x5c0];
2211};
2212
1c64bf6f
MY		 2213struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2214 u8 symbol_error_counter[0x10];
2215
2216 u8 link_error_recovery_counter[0x8];
2217
2218 u8 link_downed_counter[0x8];
2219
2220 u8 port_rcv_errors[0x10];
2221
2222 u8 port_rcv_remote_physical_errors[0x10];
2223
2224 u8 port_rcv_switch_relay_errors[0x10];
2225
2226 u8 port_xmit_discards[0x10];
2227
2228 u8 port_xmit_constraint_errors[0x8];
2229
2230 u8 port_rcv_constraint_errors[0x8];
2231
2232 u8 reserved_at_70[0x8];
2233
2234 u8 link_overrun_errors[0x8];
2235
2236 u8 reserved_at_80[0x10];
2237
2238 u8 vl_15_dropped[0x10];
2239
133bea04
TW		 2240 u8 reserved_at_a0[0x80];
2241
2242 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 2243};
2244
948d3f90 2245struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
e281682b
SM		 2246 u8 transmit_queue_high[0x20];
2247
2248 u8 transmit_queue_low[0x20];
2249
948d3f90
AL		 2250 u8 no_buffer_discard_uc_high[0x20];
2251
2252 u8 no_buffer_discard_uc_low[0x20];
2253
2254 u8 reserved_at_80[0x740];
2255};
2256
2257struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2258 u8 wred_discard_high[0x20];
2259
2260 u8 wred_discard_low[0x20];
2261
2262 u8 ecn_marked_tc_high[0x20];
2263
2264 u8 ecn_marked_tc_low[0x20];
2265
2266 u8 reserved_at_80[0x740];
e281682b
SM		 2267};
2268
2269struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2270 u8 rx_octets_high[0x20];
2271
2272 u8 rx_octets_low[0x20];
2273
b4ff3a36 2274 u8 reserved_at_40[0xc0];
e281682b
SM		 2275
2276 u8 rx_frames_high[0x20];
2277
2278 u8 rx_frames_low[0x20];
2279
2280 u8 tx_octets_high[0x20];
2281
2282 u8 tx_octets_low[0x20];
2283
b4ff3a36 2284 u8 reserved_at_180[0xc0];
e281682b
SM		 2285
2286 u8 tx_frames_high[0x20];
2287
2288 u8 tx_frames_low[0x20];
2289
2290 u8 rx_pause_high[0x20];
2291
2292 u8 rx_pause_low[0x20];
2293
2294 u8 rx_pause_duration_high[0x20];
2295
2296 u8 rx_pause_duration_low[0x20];
2297
2298 u8 tx_pause_high[0x20];
2299
2300 u8 tx_pause_low[0x20];
2301
2302 u8 tx_pause_duration_high[0x20];
2303
2304 u8 tx_pause_duration_low[0x20];
2305
2306 u8 rx_pause_transition_high[0x20];
2307
2308 u8 rx_pause_transition_low[0x20];
2309
827a8cb2
AL		 2310 u8 rx_discards_high[0x20];
2311
2312 u8 rx_discards_low[0x20];
2fcb12df
IK		 2313
2314 u8 device_stall_minor_watermark_cnt_high[0x20];
2315
2316 u8 device_stall_minor_watermark_cnt_low[0x20];
2317
2318 u8 device_stall_critical_watermark_cnt_high[0x20];
2319
2320 u8 device_stall_critical_watermark_cnt_low[0x20];
2321
2322 u8 reserved_at_480[0x340];
e281682b
SM		 2323};
2324
2325struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2326 u8 port_transmit_wait_high[0x20];
2327
2328 u8 port_transmit_wait_low[0x20];
2329
2dba0797
GP		 2330 u8 reserved_at_40[0x100];
2331
2332 u8 rx_buffer_almost_full_high[0x20];
2333
2334 u8 rx_buffer_almost_full_low[0x20];
2335
2336 u8 rx_buffer_full_high[0x20];
2337
2338 u8 rx_buffer_full_low[0x20];
2339
0af5107c
TB		 2340 u8 rx_icrc_encapsulated_high[0x20];
2341
2342 u8 rx_icrc_encapsulated_low[0x20];
2343
2344 u8 reserved_at_200[0x5c0];
e281682b
SM		 2345};
2346
2347struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2348 u8 dot3stats_alignment_errors_high[0x20];
2349
2350 u8 dot3stats_alignment_errors_low[0x20];
2351
2352 u8 dot3stats_fcs_errors_high[0x20];
2353
2354 u8 dot3stats_fcs_errors_low[0x20];
2355
2356 u8 dot3stats_single_collision_frames_high[0x20];
2357
2358 u8 dot3stats_single_collision_frames_low[0x20];
2359
2360 u8 dot3stats_multiple_collision_frames_high[0x20];
2361
2362 u8 dot3stats_multiple_collision_frames_low[0x20];
2363
2364 u8 dot3stats_sqe_test_errors_high[0x20];
2365
2366 u8 dot3stats_sqe_test_errors_low[0x20];
2367
2368 u8 dot3stats_deferred_transmissions_high[0x20];
2369
2370 u8 dot3stats_deferred_transmissions_low[0x20];
2371
2372 u8 dot3stats_late_collisions_high[0x20];
2373
2374 u8 dot3stats_late_collisions_low[0x20];
2375
2376 u8 dot3stats_excessive_collisions_high[0x20];
2377
2378 u8 dot3stats_excessive_collisions_low[0x20];
2379
2380 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2381
2382 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2383
2384 u8 dot3stats_carrier_sense_errors_high[0x20];
2385
2386 u8 dot3stats_carrier_sense_errors_low[0x20];
2387
2388 u8 dot3stats_frame_too_longs_high[0x20];
2389
2390 u8 dot3stats_frame_too_longs_low[0x20];
2391
2392 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2393
2394 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2395
2396 u8 dot3stats_symbol_errors_high[0x20];
2397
2398 u8 dot3stats_symbol_errors_low[0x20];
2399
2400 u8 dot3control_in_unknown_opcodes_high[0x20];
2401
2402 u8 dot3control_in_unknown_opcodes_low[0x20];
2403
2404 u8 dot3in_pause_frames_high[0x20];
2405
2406 u8 dot3in_pause_frames_low[0x20];
2407
2408 u8 dot3out_pause_frames_high[0x20];
2409
2410 u8 dot3out_pause_frames_low[0x20];
2411
b4ff3a36 2412 u8 reserved_at_400[0x3c0];
e281682b
SM		 2413};
2414
2415struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2416 u8 ether_stats_drop_events_high[0x20];
2417
2418 u8 ether_stats_drop_events_low[0x20];
2419
2420 u8 ether_stats_octets_high[0x20];
2421
2422 u8 ether_stats_octets_low[0x20];
2423
2424 u8 ether_stats_pkts_high[0x20];
2425
2426 u8 ether_stats_pkts_low[0x20];
2427
2428 u8 ether_stats_broadcast_pkts_high[0x20];
2429
2430 u8 ether_stats_broadcast_pkts_low[0x20];
2431
2432 u8 ether_stats_multicast_pkts_high[0x20];
2433
2434 u8 ether_stats_multicast_pkts_low[0x20];
2435
2436 u8 ether_stats_crc_align_errors_high[0x20];
2437
2438 u8 ether_stats_crc_align_errors_low[0x20];
2439
2440 u8 ether_stats_undersize_pkts_high[0x20];
2441
2442 u8 ether_stats_undersize_pkts_low[0x20];
2443
2444 u8 ether_stats_oversize_pkts_high[0x20];
2445
2446 u8 ether_stats_oversize_pkts_low[0x20];
2447
2448 u8 ether_stats_fragments_high[0x20];
2449
2450 u8 ether_stats_fragments_low[0x20];
2451
2452 u8 ether_stats_jabbers_high[0x20];
2453
2454 u8 ether_stats_jabbers_low[0x20];
2455
2456 u8 ether_stats_collisions_high[0x20];
2457
2458 u8 ether_stats_collisions_low[0x20];
2459
2460 u8 ether_stats_pkts64octets_high[0x20];
2461
2462 u8 ether_stats_pkts64octets_low[0x20];
2463
2464 u8 ether_stats_pkts65to127octets_high[0x20];
2465
2466 u8 ether_stats_pkts65to127octets_low[0x20];
2467
2468 u8 ether_stats_pkts128to255octets_high[0x20];
2469
2470 u8 ether_stats_pkts128to255octets_low[0x20];
2471
2472 u8 ether_stats_pkts256to511octets_high[0x20];
2473
2474 u8 ether_stats_pkts256to511octets_low[0x20];
2475
2476 u8 ether_stats_pkts512to1023octets_high[0x20];
2477
2478 u8 ether_stats_pkts512to1023octets_low[0x20];
2479
2480 u8 ether_stats_pkts1024to1518octets_high[0x20];
2481
2482 u8 ether_stats_pkts1024to1518octets_low[0x20];
2483
2484 u8 ether_stats_pkts1519to2047octets_high[0x20];
2485
2486 u8 ether_stats_pkts1519to2047octets_low[0x20];
2487
2488 u8 ether_stats_pkts2048to4095octets_high[0x20];
2489
2490 u8 ether_stats_pkts2048to4095octets_low[0x20];
2491
2492 u8 ether_stats_pkts4096to8191octets_high[0x20];
2493
2494 u8 ether_stats_pkts4096to8191octets_low[0x20];
2495
2496 u8 ether_stats_pkts8192to10239octets_high[0x20];
2497
2498 u8 ether_stats_pkts8192to10239octets_low[0x20];
2499
b4ff3a36 2500 u8 reserved_at_540[0x280];
e281682b
SM		 2501};
2502
2503struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2504 u8 if_in_octets_high[0x20];
2505
2506 u8 if_in_octets_low[0x20];
2507
2508 u8 if_in_ucast_pkts_high[0x20];
2509
2510 u8 if_in_ucast_pkts_low[0x20];
2511
2512 u8 if_in_discards_high[0x20];
2513
2514 u8 if_in_discards_low[0x20];
2515
2516 u8 if_in_errors_high[0x20];
2517
2518 u8 if_in_errors_low[0x20];
2519
2520 u8 if_in_unknown_protos_high[0x20];
2521
2522 u8 if_in_unknown_protos_low[0x20];
2523
2524 u8 if_out_octets_high[0x20];
2525
2526 u8 if_out_octets_low[0x20];
2527
2528 u8 if_out_ucast_pkts_high[0x20];
2529
2530 u8 if_out_ucast_pkts_low[0x20];
2531
2532 u8 if_out_discards_high[0x20];
2533
2534 u8 if_out_discards_low[0x20];
2535
2536 u8 if_out_errors_high[0x20];
2537
2538 u8 if_out_errors_low[0x20];
2539
2540 u8 if_in_multicast_pkts_high[0x20];
2541
2542 u8 if_in_multicast_pkts_low[0x20];
2543
2544 u8 if_in_broadcast_pkts_high[0x20];
2545
2546 u8 if_in_broadcast_pkts_low[0x20];
2547
2548 u8 if_out_multicast_pkts_high[0x20];
2549
2550 u8 if_out_multicast_pkts_low[0x20];
2551
2552 u8 if_out_broadcast_pkts_high[0x20];
2553
2554 u8 if_out_broadcast_pkts_low[0x20];
2555
b4ff3a36 2556 u8 reserved_at_340[0x480];
e281682b
SM		 2557};
2558
2559struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2560 u8 a_frames_transmitted_ok_high[0x20];
2561
2562 u8 a_frames_transmitted_ok_low[0x20];
2563
2564 u8 a_frames_received_ok_high[0x20];
2565
2566 u8 a_frames_received_ok_low[0x20];
2567
2568 u8 a_frame_check_sequence_errors_high[0x20];
2569
2570 u8 a_frame_check_sequence_errors_low[0x20];
2571
2572 u8 a_alignment_errors_high[0x20];
2573
2574 u8 a_alignment_errors_low[0x20];
2575
2576 u8 a_octets_transmitted_ok_high[0x20];
2577
2578 u8 a_octets_transmitted_ok_low[0x20];
2579
2580 u8 a_octets_received_ok_high[0x20];
2581
2582 u8 a_octets_received_ok_low[0x20];
2583
2584 u8 a_multicast_frames_xmitted_ok_high[0x20];
2585
2586 u8 a_multicast_frames_xmitted_ok_low[0x20];
2587
2588 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2589
2590 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2591
2592 u8 a_multicast_frames_received_ok_high[0x20];
2593
2594 u8 a_multicast_frames_received_ok_low[0x20];
2595
2596 u8 a_broadcast_frames_received_ok_high[0x20];
2597
2598 u8 a_broadcast_frames_received_ok_low[0x20];
2599
2600 u8 a_in_range_length_errors_high[0x20];
2601
2602 u8 a_in_range_length_errors_low[0x20];
2603
2604 u8 a_out_of_range_length_field_high[0x20];
2605
2606 u8 a_out_of_range_length_field_low[0x20];
2607
2608 u8 a_frame_too_long_errors_high[0x20];
2609
2610 u8 a_frame_too_long_errors_low[0x20];
2611
2612 u8 a_symbol_error_during_carrier_high[0x20];
2613
2614 u8 a_symbol_error_during_carrier_low[0x20];
2615
2616 u8 a_mac_control_frames_transmitted_high[0x20];
2617
2618 u8 a_mac_control_frames_transmitted_low[0x20];
2619
2620 u8 a_mac_control_frames_received_high[0x20];
2621
2622 u8 a_mac_control_frames_received_low[0x20];
2623
2624 u8 a_unsupported_opcodes_received_high[0x20];
2625
2626 u8 a_unsupported_opcodes_received_low[0x20];
2627
2628 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2629
2630 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2631
2632 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2633
2634 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2635
b4ff3a36 2636 u8 reserved_at_4c0[0x300];
e281682b
SM		 2637};
2638
8ed1a630
GP		 2639struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2640 u8 life_time_counter_high[0x20];
2641
2642 u8 life_time_counter_low[0x20];
2643
2644 u8 rx_errors[0x20];
2645
2646 u8 tx_errors[0x20];
2647
2648 u8 l0_to_recovery_eieos[0x20];
2649
2650 u8 l0_to_recovery_ts[0x20];
2651
2652 u8 l0_to_recovery_framing[0x20];
2653
2654 u8 l0_to_recovery_retrain[0x20];
2655
2656 u8 crc_error_dllp[0x20];
2657
2658 u8 crc_error_tlp[0x20];
2659
efae7f78
EBE		 2660 u8 tx_overflow_buffer_pkt_high[0x20];
2661
2662 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2663
2664 u8 outbound_stalled_reads[0x20];
2665
2666 u8 outbound_stalled_writes[0x20];
2667
2668 u8 outbound_stalled_reads_events[0x20];
2669
2670 u8 outbound_stalled_writes_events[0x20];
2671
2672 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2673};
2674
e281682b
SM		 2675struct mlx5_ifc_cmd_inter_comp_event_bits {
2676 u8 command_completion_vector[0x20];
2677
b4ff3a36 2678 u8 reserved_at_20[0xc0];
e281682b
SM		 2679};
2680
2681struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2682 u8 reserved_at_0[0x18];
e281682b 2683 u8 port_num[0x1];
b4ff3a36 2684 u8 reserved_at_19[0x3];
e281682b
SM		 2685 u8 vl[0x4];
2686
b4ff3a36 2687 u8 reserved_at_20[0xa0];
e281682b
SM		 2688};
2689
2690struct mlx5_ifc_db_bf_congestion_event_bits {
2691 u8 event_subtype[0x8];
b4ff3a36 2692 u8 reserved_at_8[0x8];
e281682b 2693 u8 congestion_level[0x8];
b4ff3a36 2694 u8 reserved_at_18[0x8];
e281682b 2695
b4ff3a36 2696 u8 reserved_at_20[0xa0];
e281682b
SM		 2697};
2698
2699struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2700 u8 reserved_at_0[0x60];
e281682b
SM		 2701
2702 u8 gpio_event_hi[0x20];
2703
2704 u8 gpio_event_lo[0x20];
2705
b4ff3a36 2706 u8 reserved_at_a0[0x40];
e281682b
SM		 2707};
2708
2709struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2710 u8 reserved_at_0[0x40];
e281682b
SM		 2711
2712 u8 port_num[0x4];
b4ff3a36 2713 u8 reserved_at_44[0x1c];
e281682b 2714
b4ff3a36 2715 u8 reserved_at_60[0x80];
e281682b
SM		 2716};
2717
2718struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2719 u8 reserved_at_0[0xe0];
e281682b
SM		 2720};
2721
2722enum {
2723 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2724 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2725};
2726
2727struct mlx5_ifc_cq_error_bits {
b4ff3a36 2728 u8 reserved_at_0[0x8];
e281682b
SM		 2729 u8 cqn[0x18];
2730
b4ff3a36 2731 u8 reserved_at_20[0x20];
e281682b 2732
b4ff3a36 2733 u8 reserved_at_40[0x18];
e281682b
SM		 2734 u8 syndrome[0x8];
2735
b4ff3a36 2736 u8 reserved_at_60[0x80];
e281682b
SM		 2737};
2738
2739struct mlx5_ifc_rdma_page_fault_event_bits {
2740 u8 bytes_committed[0x20];
2741
2742 u8 r_key[0x20];
2743
b4ff3a36 2744 u8 reserved_at_40[0x10];
e281682b
SM		 2745 u8 packet_len[0x10];
2746
2747 u8 rdma_op_len[0x20];
2748
2749 u8 rdma_va[0x40];
2750
b4ff3a36 2751 u8 reserved_at_c0[0x5];
e281682b
SM		 2752 u8 rdma[0x1];
2753 u8 write[0x1];
2754 u8 requestor[0x1];
2755 u8 qp_number[0x18];
2756};
2757
2758struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2759 u8 bytes_committed[0x20];
2760
b4ff3a36 2761 u8 reserved_at_20[0x10];
e281682b
SM		 2762 u8 wqe_index[0x10];
2763
b4ff3a36 2764 u8 reserved_at_40[0x10];
e281682b
SM		 2765 u8 len[0x10];
2766
b4ff3a36 2767 u8 reserved_at_60[0x60];
e281682b 2768
b4ff3a36 2769 u8 reserved_at_c0[0x5];
e281682b
SM		 2770 u8 rdma[0x1];
2771 u8 write_read[0x1];
2772 u8 requestor[0x1];
2773 u8 qpn[0x18];
2774};
2775
2776struct mlx5_ifc_qp_events_bits {
b4ff3a36 2777 u8 reserved_at_0[0xa0];
e281682b
SM		 2778
2779 u8 type[0x8];
b4ff3a36 2780 u8 reserved_at_a8[0x18];
e281682b 2781
b4ff3a36 2782 u8 reserved_at_c0[0x8];
e281682b
SM		 2783 u8 qpn_rqn_sqn[0x18];
2784};
2785
2786struct mlx5_ifc_dct_events_bits {
b4ff3a36 2787 u8 reserved_at_0[0xc0];
e281682b 2788
b4ff3a36 2789 u8 reserved_at_c0[0x8];
e281682b
SM		 2790 u8 dct_number[0x18];
2791};
2792
2793struct mlx5_ifc_comp_event_bits {
b4ff3a36 2794 u8 reserved_at_0[0xc0];
e281682b 2795
b4ff3a36 2796 u8 reserved_at_c0[0x8];
e281682b
SM		 2797 u8 cq_number[0x18];
2798};
2799
2800enum {
2801 MLX5_QPC_STATE_RST = 0x0,
2802 MLX5_QPC_STATE_INIT = 0x1,
2803 MLX5_QPC_STATE_RTR = 0x2,
2804 MLX5_QPC_STATE_RTS = 0x3,
2805 MLX5_QPC_STATE_SQER = 0x4,
2806 MLX5_QPC_STATE_ERR = 0x6,
2807 MLX5_QPC_STATE_SQD = 0x7,
2808 MLX5_QPC_STATE_SUSPENDED = 0x9,
2809};
2810
2811enum {
2812 MLX5_QPC_ST_RC = 0x0,
2813 MLX5_QPC_ST_UC = 0x1,
2814 MLX5_QPC_ST_UD = 0x2,
2815 MLX5_QPC_ST_XRC = 0x3,
2816 MLX5_QPC_ST_DCI = 0x5,
2817 MLX5_QPC_ST_QP0 = 0x7,
2818 MLX5_QPC_ST_QP1 = 0x8,
2819 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2820 MLX5_QPC_ST_REG_UMR = 0xc,
2821};
2822
2823enum {
2824 MLX5_QPC_PM_STATE_ARMED = 0x0,
2825 MLX5_QPC_PM_STATE_REARM = 0x1,
2826 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2827 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2828};
2829
6e44636a
AK		 2830enum {
2831 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2832};
2833
e281682b
SM		 2834enum {
2835 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2836 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2837};
2838
2839enum {
2840 MLX5_QPC_MTU_256_BYTES = 0x1,
2841 MLX5_QPC_MTU_512_BYTES = 0x2,
2842 MLX5_QPC_MTU_1K_BYTES = 0x3,
2843 MLX5_QPC_MTU_2K_BYTES = 0x4,
2844 MLX5_QPC_MTU_4K_BYTES = 0x5,
2845 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2846};
2847
2848enum {
2849 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2850 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2851 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2852 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2853 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2854 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2855 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2856 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2857};
2858
2859enum {
2860 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2861 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2862 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2863};
2864
2865enum {
2866 MLX5_QPC_CS_RES_DISABLE = 0x0,
2867 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2868 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2869};
2870
2871struct mlx5_ifc_qpc_bits {
2872 u8 state[0x4];
84df61eb 2873 u8 lag_tx_port_affinity[0x4];
e281682b 2874 u8 st[0x8];
b4ff3a36 2875 u8 reserved_at_10[0x3];
e281682b 2876 u8 pm_state[0x2];
3fd3c80a
DG		 2877 u8 reserved_at_15[0x1];
2878 u8 req_e2e_credit_mode[0x2];
6e44636a 2879 u8 offload_type[0x4];
e281682b 2880 u8 end_padding_mode[0x2];
b4ff3a36 2881 u8 reserved_at_1e[0x2];
e281682b
SM		 2882
2883 u8 wq_signature[0x1];
2884 u8 block_lb_mc[0x1];
2885 u8 atomic_like_write_en[0x1];
2886 u8 latency_sensitive[0x1];
b4ff3a36 2887 u8 reserved_at_24[0x1];
e281682b 2888 u8 drain_sigerr[0x1];
b4ff3a36 2889 u8 reserved_at_26[0x2];
e281682b
SM		 2890 u8 pd[0x18];
2891
2892 u8 mtu[0x3];
2893 u8 log_msg_max[0x5];
b4ff3a36 2894 u8 reserved_at_48[0x1];
e281682b
SM		 2895 u8 log_rq_size[0x4];
2896 u8 log_rq_stride[0x3];
2897 u8 no_sq[0x1];
2898 u8 log_sq_size[0x4];
b4ff3a36 2899 u8 reserved_at_55[0x6];
e281682b 2900 u8 rlky[0x1];
1015c2e8 2901 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2902
2903 u8 counter_set_id[0x8];
2904 u8 uar_page[0x18];
2905
b4ff3a36 2906 u8 reserved_at_80[0x8];
e281682b
SM		 2907 u8 user_index[0x18];
2908
b4ff3a36 2909 u8 reserved_at_a0[0x3];
e281682b
SM		 2910 u8 log_page_size[0x5];
2911 u8 remote_qpn[0x18];
2912
2913 struct mlx5_ifc_ads_bits primary_address_path;
2914
2915 struct mlx5_ifc_ads_bits secondary_address_path;
2916
2917 u8 log_ack_req_freq[0x4];
b4ff3a36 2918 u8 reserved_at_384[0x4];
e281682b 2919 u8 log_sra_max[0x3];
b4ff3a36 2920 u8 reserved_at_38b[0x2];
e281682b
SM		 2921 u8 retry_count[0x3];
2922 u8 rnr_retry[0x3];
b4ff3a36 2923 u8 reserved_at_393[0x1];
e281682b
SM		 2924 u8 fre[0x1];
2925 u8 cur_rnr_retry[0x3];
2926 u8 cur_retry_count[0x3];
b4ff3a36 2927 u8 reserved_at_39b[0x5];
e281682b 2928
b4ff3a36 2929 u8 reserved_at_3a0[0x20];
e281682b 2930
b4ff3a36 2931 u8 reserved_at_3c0[0x8];
e281682b
SM		 2932 u8 next_send_psn[0x18];
2933
b4ff3a36 2934 u8 reserved_at_3e0[0x8];
e281682b
SM		 2935 u8 cqn_snd[0x18];
2936
09a7d9ec
SM		 2937 u8 reserved_at_400[0x8];
2938 u8 deth_sqpn[0x18];
2939
2940 u8 reserved_at_420[0x20];
e281682b 2941
b4ff3a36 2942 u8 reserved_at_440[0x8];
e281682b
SM		 2943 u8 last_acked_psn[0x18];
2944
b4ff3a36 2945 u8 reserved_at_460[0x8];
e281682b
SM		 2946 u8 ssn[0x18];
2947
b4ff3a36 2948 u8 reserved_at_480[0x8];
e281682b 2949 u8 log_rra_max[0x3];
b4ff3a36 2950 u8 reserved_at_48b[0x1];
e281682b
SM		 2951 u8 atomic_mode[0x4];
2952 u8 rre[0x1];
2953 u8 rwe[0x1];
2954 u8 rae[0x1];
b4ff3a36 2955 u8 reserved_at_493[0x1];
e281682b 2956 u8 page_offset[0x6];
b4ff3a36 2957 u8 reserved_at_49a[0x3];
e281682b
SM		 2958 u8 cd_slave_receive[0x1];
2959 u8 cd_slave_send[0x1];
2960 u8 cd_master[0x1];
2961
b4ff3a36 2962 u8 reserved_at_4a0[0x3];
e281682b
SM		 2963 u8 min_rnr_nak[0x5];
2964 u8 next_rcv_psn[0x18];
2965
b4ff3a36 2966 u8 reserved_at_4c0[0x8];
e281682b
SM		 2967 u8 xrcd[0x18];
2968
b4ff3a36 2969 u8 reserved_at_4e0[0x8];
e281682b
SM		 2970 u8 cqn_rcv[0x18];
2971
2972 u8 dbr_addr[0x40];
2973
2974 u8 q_key[0x20];
2975
b4ff3a36 2976 u8 reserved_at_560[0x5];
e281682b 2977 u8 rq_type[0x3];
7486216b 2978 u8 srqn_rmpn_xrqn[0x18];
e281682b 2979
b4ff3a36 2980 u8 reserved_at_580[0x8];
e281682b
SM		 2981 u8 rmsn[0x18];
2982
2983 u8 hw_sq_wqebb_counter[0x10];
2984 u8 sw_sq_wqebb_counter[0x10];
2985
2986 u8 hw_rq_counter[0x20];
2987
2988 u8 sw_rq_counter[0x20];
2989
b4ff3a36 2990 u8 reserved_at_600[0x20];
e281682b 2991
b4ff3a36 2992 u8 reserved_at_620[0xf];
e281682b
SM		 2993 u8 cgs[0x1];
2994 u8 cs_req[0x8];
2995 u8 cs_res[0x8];
2996
2997 u8 dc_access_key[0x40];
2998
bd371975
LR		 2999 u8 reserved_at_680[0x3];
3000 u8 dbr_umem_valid[0x1];
3001
3002 u8 reserved_at_684[0xbc];
e281682b
SM		 3003};
3004
3005struct mlx5_ifc_roce_addr_layout_bits {
3006 u8 source_l3_address[16][0x8];
3007
b4ff3a36 3008 u8 reserved_at_80[0x3];
e281682b
SM		 3009 u8 vlan_valid[0x1];
3010 u8 vlan_id[0xc];
3011 u8 source_mac_47_32[0x10];
3012
3013 u8 source_mac_31_0[0x20];
3014
b4ff3a36 3015 u8 reserved_at_c0[0x14];
e281682b
SM		 3016 u8 roce_l3_type[0x4];
3017 u8 roce_version[0x8];
3018
b4ff3a36 3019 u8 reserved_at_e0[0x20];
e281682b
SM		 3020};
3021
3022union mlx5_ifc_hca_cap_union_bits {
3023 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3024 struct mlx5_ifc_odp_cap_bits odp_cap;
3025 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3026 struct mlx5_ifc_roce_cap_bits roce_cap;
3027 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3028 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 3029 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 3030 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 3031 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 3032 struct mlx5_ifc_qos_cap_bits qos_cap;
0b9055a1 3033 struct mlx5_ifc_debug_cap_bits debug_cap;
e29341fb 3034 struct mlx5_ifc_fpga_cap_bits fpga_cap;
a12ff35e 3035 struct mlx5_ifc_tls_cap_bits tls_cap;
97b5484e 3036 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
8a06a79b 3037 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
b4ff3a36 3038 u8 reserved_at_0[0x8000];
e281682b
SM		 3039};
3040
3041enum {
3042 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3043 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3044 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 3045 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 3046 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 3047 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 3048 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 3049 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3050 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 3051 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3052 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
78fb6122
HN		 3053 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3054 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
0c06897a
OG		 3055};
3056
65c0f2c1
JL		 3057enum {
3058 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3059 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3060 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3061};
3062
0c06897a
OG		 3063struct mlx5_ifc_vlan_bits {
3064 u8 ethtype[0x10];
3065 u8 prio[0x3];
3066 u8 cfi[0x1];
3067 u8 vid[0xc];
e281682b
SM		 3068};
3069
3070struct mlx5_ifc_flow_context_bits {
0c06897a 3071 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 3072
3073 u8 group_id[0x20];
3074
b4ff3a36 3075 u8 reserved_at_40[0x8];
e281682b
SM		 3076 u8 flow_tag[0x18];
3077
b4ff3a36 3078 u8 reserved_at_60[0x10];
e281682b
SM		 3079 u8 action[0x10];
3080
1b115498 3081 u8 extended_destination[0x1];
65c0f2c1
JL		 3082 u8 reserved_at_81[0x1];
3083 u8 flow_source[0x2];
3084 u8 reserved_at_84[0x4];
e281682b
SM		 3085 u8 destination_list_size[0x18];
3086
9dc0b289
AV		 3087 u8 reserved_at_a0[0x8];
3088 u8 flow_counter_list_size[0x18];
3089
60786f09 3090 u8 packet_reformat_id[0x20];
7adbde20 3091
2a69cb9f
OG		 3092 u8 modify_header_id[0x20];
3093
8da6fe2a
JL		 3094 struct mlx5_ifc_vlan_bits push_vlan_2;
3095
78fb6122
HN		 3096 u8 ipsec_obj_id[0x20];
3097 u8 reserved_at_140[0xc0];
e281682b
SM		 3098
3099 struct mlx5_ifc_fte_match_param_bits match_value;
3100
b4ff3a36 3101 u8 reserved_at_1200[0x600];
e281682b 3102
b6ca09cb 3103 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
e281682b
SM		 3104};
3105
3106enum {
3107 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3108 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3109};
3110
3111struct mlx5_ifc_xrc_srqc_bits {
3112 u8 state[0x4];
3113 u8 log_xrc_srq_size[0x4];
b4ff3a36 3114 u8 reserved_at_8[0x18];
e281682b
SM		 3115
3116 u8 wq_signature[0x1];
3117 u8 cont_srq[0x1];
99b77fef 3118 u8 reserved_at_22[0x1];
e281682b
SM		 3119 u8 rlky[0x1];
3120 u8 basic_cyclic_rcv_wqe[0x1];
3121 u8 log_rq_stride[0x3];
3122 u8 xrcd[0x18];
3123
3124 u8 page_offset[0x6];
99b77fef
YH		 3125 u8 reserved_at_46[0x1];
3126 u8 dbr_umem_valid[0x1];
e281682b
SM		 3127 u8 cqn[0x18];
3128
b4ff3a36 3129 u8 reserved_at_60[0x20];
e281682b
SM		 3130
3131 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 3132 u8 reserved_at_81[0x1];
e281682b
SM		 3133 u8 log_page_size[0x6];
3134 u8 user_index[0x18];
3135
b4ff3a36 3136 u8 reserved_at_a0[0x20];
e281682b 3137
b4ff3a36 3138 u8 reserved_at_c0[0x8];
e281682b
SM		 3139 u8 pd[0x18];
3140
3141 u8 lwm[0x10];
3142 u8 wqe_cnt[0x10];
3143
b4ff3a36 3144 u8 reserved_at_100[0x40];
e281682b
SM		 3145
3146 u8 db_record_addr_h[0x20];
3147
3148 u8 db_record_addr_l[0x1e];
b4ff3a36 3149 u8 reserved_at_17e[0x2];
e281682b 3150
b4ff3a36 3151 u8 reserved_at_180[0x80];
e281682b
SM		 3152};
3153
61c5b5c9
MS		 3154struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3155 u8 counter_error_queues[0x20];
3156
3157 u8 total_error_queues[0x20];
3158
3159 u8 send_queue_priority_update_flow[0x20];
3160
3161 u8 reserved_at_60[0x20];
3162
3163 u8 nic_receive_steering_discard[0x40];
3164
3165 u8 receive_discard_vport_down[0x40];
3166
3167 u8 transmit_discard_vport_down[0x40];
3168
30b10e89
MS		 3169 u8 reserved_at_140[0xa0];
3170
3171 u8 internal_rq_out_of_buffer[0x20];
3172
3173 u8 reserved_at_200[0xe00];
61c5b5c9
MS		 3174};
3175
e281682b
SM		 3176struct mlx5_ifc_traffic_counter_bits {
3177 u8 packets[0x40];
3178
3179 u8 octets[0x40];
3180};
3181
3182struct mlx5_ifc_tisc_bits {
84df61eb 3183 u8 strict_lag_tx_port_affinity[0x1];
a12ff35e 3184 u8 tls_en[0x1];
7761f9ee 3185 u8 reserved_at_2[0x2];
84df61eb
AH		 3186 u8 lag_tx_port_affinity[0x04];
3187
3188 u8 reserved_at_8[0x4];
e281682b 3189 u8 prio[0x4];
b4ff3a36 3190 u8 reserved_at_10[0x10];
e281682b 3191
b4ff3a36 3192 u8 reserved_at_20[0x100];
e281682b 3193
b4ff3a36 3194 u8 reserved_at_120[0x8];
e281682b
SM		 3195 u8 transport_domain[0x18];
3196
500a3d0d
ES		 3197 u8 reserved_at_140[0x8];
3198 u8 underlay_qpn[0x18];
a12ff35e
EBE		 3199
3200 u8 reserved_at_160[0x8];
3201 u8 pd[0x18];
3202
3203 u8 reserved_at_180[0x380];
e281682b
SM		 3204};
3205
3206enum {
3207 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3208 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3209};
3210
3211enum {
3212 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
3213 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
3214};
3215
3216enum {
2be6967c
SM		 3217 MLX5_RX_HASH_FN_NONE = 0x0,
3218 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3219 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 3220};
3221
3222enum {
5d773ff4
MB		 3223 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3224 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 3225};
3226
3227struct mlx5_ifc_tirc_bits {
b4ff3a36 3228 u8 reserved_at_0[0x20];
e281682b
SM		 3229
3230 u8 disp_type[0x4];
ee5cdf7a
TT		 3231 u8 tls_en[0x1];
3232 u8 reserved_at_25[0x1b];
e281682b 3233
b4ff3a36 3234 u8 reserved_at_40[0x40];
e281682b 3235
b4ff3a36 3236 u8 reserved_at_80[0x4];
e281682b
SM		 3237 u8 lro_timeout_period_usecs[0x10];
3238 u8 lro_enable_mask[0x4];
3239 u8 lro_max_ip_payload_size[0x8];
3240
b4ff3a36 3241 u8 reserved_at_a0[0x40];
e281682b 3242
b4ff3a36 3243 u8 reserved_at_e0[0x8];
e281682b
SM		 3244 u8 inline_rqn[0x18];
3245
3246 u8 rx_hash_symmetric[0x1];
b4ff3a36 3247 u8 reserved_at_101[0x1];
e281682b 3248 u8 tunneled_offload_en[0x1];
b4ff3a36 3249 u8 reserved_at_103[0x5];
e281682b
SM		 3250 u8 indirect_table[0x18];
3251
3252 u8 rx_hash_fn[0x4];
b4ff3a36 3253 u8 reserved_at_124[0x2];
e281682b
SM		 3254 u8 self_lb_block[0x2];
3255 u8 transport_domain[0x18];
3256
3257 u8 rx_hash_toeplitz_key[10][0x20];
3258
3259 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3260
3261 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3262
b4ff3a36 3263 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 3264};
3265
3266enum {
3267 MLX5_SRQC_STATE_GOOD = 0x0,
3268 MLX5_SRQC_STATE_ERROR = 0x1,
3269};
3270
3271struct mlx5_ifc_srqc_bits {
3272 u8 state[0x4];
3273 u8 log_srq_size[0x4];
b4ff3a36 3274 u8 reserved_at_8[0x18];
e281682b
SM		 3275
3276 u8 wq_signature[0x1];
3277 u8 cont_srq[0x1];
b4ff3a36 3278 u8 reserved_at_22[0x1];
e281682b 3279 u8 rlky[0x1];
b4ff3a36 3280 u8 reserved_at_24[0x1];
e281682b
SM		 3281 u8 log_rq_stride[0x3];
3282 u8 xrcd[0x18];
3283
3284 u8 page_offset[0x6];
b4ff3a36 3285 u8 reserved_at_46[0x2];
e281682b
SM		 3286 u8 cqn[0x18];
3287
b4ff3a36 3288 u8 reserved_at_60[0x20];
e281682b 3289
b4ff3a36 3290 u8 reserved_at_80[0x2];
e281682b 3291 u8 log_page_size[0x6];
b4ff3a36 3292 u8 reserved_at_88[0x18];
e281682b 3293
b4ff3a36 3294 u8 reserved_at_a0[0x20];
e281682b 3295
b4ff3a36 3296 u8 reserved_at_c0[0x8];
e281682b
SM		 3297 u8 pd[0x18];
3298
3299 u8 lwm[0x10];
3300 u8 wqe_cnt[0x10];
3301
b4ff3a36 3302 u8 reserved_at_100[0x40];
e281682b 3303
01949d01 3304 u8 dbr_addr[0x40];
e281682b 3305
b4ff3a36 3306 u8 reserved_at_180[0x80];
e281682b
SM		 3307};
3308
3309enum {
3310 MLX5_SQC_STATE_RST = 0x0,
3311 MLX5_SQC_STATE_RDY = 0x1,
3312 MLX5_SQC_STATE_ERR = 0x3,
3313};
3314
3315struct mlx5_ifc_sqc_bits {
3316 u8 rlky[0x1];
3317 u8 cd_master[0x1];
3318 u8 fre[0x1];
3319 u8 flush_in_error_en[0x1];
795b609c 3320 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 3321 u8 min_wqe_inline_mode[0x3];
e281682b 3322 u8 state[0x4];
7d5e1423 3323 u8 reg_umr[0x1];
547eede0 3324 u8 allow_swp[0x1];
40817cdb
OG		 3325 u8 hairpin[0x1];
3326 u8 reserved_at_f[0x11];
e281682b 3327
b4ff3a36 3328 u8 reserved_at_20[0x8];
e281682b
SM		 3329 u8 user_index[0x18];
3330
b4ff3a36 3331 u8 reserved_at_40[0x8];
e281682b
SM		 3332 u8 cqn[0x18];
3333
40817cdb
OG		 3334 u8 reserved_at_60[0x8];
3335 u8 hairpin_peer_rq[0x18];
3336
3337 u8 reserved_at_80[0x10];
3338 u8 hairpin_peer_vhca[0x10];
3339
59d2ae1d 3340 u8 reserved_at_a0[0x20];
e281682b 3341
59d2ae1d
EBE		 3342 u8 reserved_at_c0[0x8];
3343 u8 ts_cqe_to_dest_cqn[0x18];
e281682b 3344
59d2ae1d 3345 u8 reserved_at_e0[0x10];
7486216b 3346 u8 packet_pacing_rate_limit_index[0x10];
e281682b 3347 u8 tis_lst_sz[0x10];
b4ff3a36 3348 u8 reserved_at_110[0x10];
e281682b 3349
b4ff3a36 3350 u8 reserved_at_120[0x40];
e281682b 3351
b4ff3a36 3352 u8 reserved_at_160[0x8];
e281682b
SM		 3353 u8 tis_num_0[0x18];
3354
3355 struct mlx5_ifc_wq_bits wq;
3356};
3357
813f8540
MHY		 3358enum {
3359 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3360 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3361 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3362 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3363};
3364
6cedde45
EC		 3365enum {
3366 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3367 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3368 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3369 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3370};
3371
813f8540
MHY		 3372struct mlx5_ifc_scheduling_context_bits {
3373 u8 element_type[0x8];
3374 u8 reserved_at_8[0x18];
3375
3376 u8 element_attributes[0x20];
3377
3378 u8 parent_element_id[0x20];
3379
3380 u8 reserved_at_60[0x40];
3381
3382 u8 bw_share[0x20];
3383
3384 u8 max_average_bw[0x20];
3385
3386 u8 reserved_at_e0[0x120];
3387};
3388
e281682b 3389struct mlx5_ifc_rqtc_bits {
8a06a79b 3390 u8 reserved_at_0[0xa0];
e281682b 3391
8a06a79b
EC		 3392 u8 reserved_at_a0[0x5];
3393 u8 list_q_type[0x3];
3394 u8 reserved_at_a8[0x8];
3395 u8 rqt_max_size[0x10];
e281682b 3396
8a06a79b
EC		 3397 u8 rq_vhca_id_format[0x1];
3398 u8 reserved_at_c1[0xf];
3399 u8 rqt_actual_size[0x10];
e281682b 3400
8a06a79b 3401 u8 reserved_at_e0[0x6a0];
e281682b 3402
b6ca09cb 3403 struct mlx5_ifc_rq_num_bits rq_num[];
e281682b
SM		 3404};
3405
3406enum {
3407 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3408 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3409};
3410
3411enum {
3412 MLX5_RQC_STATE_RST = 0x0,
3413 MLX5_RQC_STATE_RDY = 0x1,
3414 MLX5_RQC_STATE_ERR = 0x3,
3415};
3416
3417struct mlx5_ifc_rqc_bits {
3418 u8 rlky[0x1];
03404e8a 3419 u8 delay_drop_en[0x1];
7d5e1423 3420 u8 scatter_fcs[0x1];
e281682b
SM		 3421 u8 vsd[0x1];
3422 u8 mem_rq_type[0x4];
3423 u8 state[0x4];
b4ff3a36 3424 u8 reserved_at_c[0x1];
e281682b 3425 u8 flush_in_error_en[0x1];
40817cdb
OG		 3426 u8 hairpin[0x1];
3427 u8 reserved_at_f[0x11];
e281682b 3428
b4ff3a36 3429 u8 reserved_at_20[0x8];
e281682b
SM		 3430 u8 user_index[0x18];
3431
b4ff3a36 3432 u8 reserved_at_40[0x8];
e281682b
SM		 3433 u8 cqn[0x18];
3434
3435 u8 counter_set_id[0x8];
b4ff3a36 3436 u8 reserved_at_68[0x18];
e281682b 3437
b4ff3a36 3438 u8 reserved_at_80[0x8];
e281682b
SM		 3439 u8 rmpn[0x18];
3440
40817cdb
OG		 3441 u8 reserved_at_a0[0x8];
3442 u8 hairpin_peer_sq[0x18];
3443
3444 u8 reserved_at_c0[0x10];
3445 u8 hairpin_peer_vhca[0x10];
3446
3447 u8 reserved_at_e0[0xa0];
e281682b
SM		 3448
3449 struct mlx5_ifc_wq_bits wq;
3450};
3451
3452enum {
3453 MLX5_RMPC_STATE_RDY = 0x1,
3454 MLX5_RMPC_STATE_ERR = 0x3,
3455};
3456
3457struct mlx5_ifc_rmpc_bits {
b4ff3a36 3458 u8 reserved_at_0[0x8];
e281682b 3459 u8 state[0x4];
b4ff3a36 3460 u8 reserved_at_c[0x14];
e281682b
SM		 3461
3462 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 3463 u8 reserved_at_21[0x1f];
e281682b 3464
b4ff3a36 3465 u8 reserved_at_40[0x140];
e281682b
SM		 3466
3467 struct mlx5_ifc_wq_bits wq;
3468};
3469
e281682b 3470struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 3471 u8 reserved_at_0[0x5];
3472 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 3473 u8 reserved_at_8[0x15];
3474 u8 disable_mc_local_lb[0x1];
3475 u8 disable_uc_local_lb[0x1];
e281682b
SM		 3476 u8 roce_en[0x1];
3477
d82b7318 3478 u8 arm_change_event[0x1];
b4ff3a36 3479 u8 reserved_at_21[0x1a];
d82b7318
SM		 3480 u8 event_on_mtu[0x1];
3481 u8 event_on_promisc_change[0x1];
3482 u8 event_on_vlan_change[0x1];
3483 u8 event_on_mc_address_change[0x1];
3484 u8 event_on_uc_address_change[0x1];
e281682b 3485
32f69e4b
DJ		 3486 u8 reserved_at_40[0xc];
3487
3488 u8 affiliation_criteria[0x4];
3489 u8 affiliated_vhca_id[0x10];
3490
3491 u8 reserved_at_60[0xd0];
d82b7318
SM		 3492
3493 u8 mtu[0x10];
3494
9efa7525
AS		 3495 u8 system_image_guid[0x40];
3496 u8 port_guid[0x40];
3497 u8 node_guid[0x40];
3498
b4ff3a36 3499 u8 reserved_at_200[0x140];
9efa7525 3500 u8 qkey_violation_counter[0x10];
b4ff3a36 3501 u8 reserved_at_350[0x430];
d82b7318
SM		 3502
3503 u8 promisc_uc[0x1];
3504 u8 promisc_mc[0x1];
3505 u8 promisc_all[0x1];
b4ff3a36 3506 u8 reserved_at_783[0x2];
e281682b 3507 u8 allowed_list_type[0x3];
b4ff3a36 3508 u8 reserved_at_788[0xc];
e281682b
SM		 3509 u8 allowed_list_size[0xc];
3510
3511 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3512
b4ff3a36 3513 u8 reserved_at_7e0[0x20];
e281682b 3514
b6ca09cb 3515 u8 current_uc_mac_address[][0x40];
e281682b
SM		 3516};
3517
3518enum {
3519 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3520 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3521 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 3522 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 3523 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 3524 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 3525};
3526
3527struct mlx5_ifc_mkc_bits {
b4ff3a36 3528 u8 reserved_at_0[0x1];
e281682b 3529 u8 free[0x1];
cdbd0d2b
AL		 3530 u8 reserved_at_2[0x1];
3531 u8 access_mode_4_2[0x3];
3532 u8 reserved_at_6[0x7];
3533 u8 relaxed_ordering_write[0x1];
3534 u8 reserved_at_e[0x1];
e281682b
SM		 3535 u8 small_fence_on_rdma_read_response[0x1];
3536 u8 umr_en[0x1];
3537 u8 a[0x1];
3538 u8 rw[0x1];
3539 u8 rr[0x1];
3540 u8 lw[0x1];
3541 u8 lr[0x1];
cdbd0d2b 3542 u8 access_mode_1_0[0x2];
b4ff3a36 3543 u8 reserved_at_18[0x8];
e281682b
SM		 3544
3545 u8 qpn[0x18];
3546 u8 mkey_7_0[0x8];
3547
b4ff3a36 3548 u8 reserved_at_40[0x20];
e281682b
SM		 3549
3550 u8 length64[0x1];
3551 u8 bsf_en[0x1];
3552 u8 sync_umr[0x1];
b4ff3a36 3553 u8 reserved_at_63[0x2];
e281682b 3554 u8 expected_sigerr_count[0x1];
b4ff3a36 3555 u8 reserved_at_66[0x1];
e281682b
SM		 3556 u8 en_rinval[0x1];
3557 u8 pd[0x18];
3558
3559 u8 start_addr[0x40];
3560
3561 u8 len[0x40];
3562
3563 u8 bsf_octword_size[0x20];
3564
b4ff3a36 3565 u8 reserved_at_120[0x80];
e281682b
SM		 3566
3567 u8 translations_octword_size[0x20];
3568
a880a6dd
MG		 3569 u8 reserved_at_1c0[0x19];
3570 u8 relaxed_ordering_read[0x1];
3571 u8 reserved_at_1d9[0x1];
e281682b
SM		 3572 u8 log_page_size[0x5];
3573
b4ff3a36 3574 u8 reserved_at_1e0[0x20];
e281682b
SM		 3575};
3576
3577struct mlx5_ifc_pkey_bits {
b4ff3a36 3578 u8 reserved_at_0[0x10];
e281682b
SM		 3579 u8 pkey[0x10];
3580};
3581
3582struct mlx5_ifc_array128_auto_bits {
3583 u8 array128_auto[16][0x8];
3584};
3585
3586struct mlx5_ifc_hca_vport_context_bits {
3587 u8 field_select[0x20];
3588
b4ff3a36 3589 u8 reserved_at_20[0xe0];
e281682b
SM		 3590
3591 u8 sm_virt_aware[0x1];
3592 u8 has_smi[0x1];
3593 u8 has_raw[0x1];
3594 u8 grh_required[0x1];
b4ff3a36 3595 u8 reserved_at_104[0xc];
707c4602
MD		 3596 u8 port_physical_state[0x4];
3597 u8 vport_state_policy[0x4];
3598 u8 port_state[0x4];
e281682b
SM		 3599 u8 vport_state[0x4];
3600
b4ff3a36 3601 u8 reserved_at_120[0x20];
707c4602
MD		 3602
3603 u8 system_image_guid[0x40];
e281682b
SM		 3604
3605 u8 port_guid[0x40];
3606
3607 u8 node_guid[0x40];
3608
3609 u8 cap_mask1[0x20];
3610
3611 u8 cap_mask1_field_select[0x20];
3612
3613 u8 cap_mask2[0x20];
3614
3615 u8 cap_mask2_field_select[0x20];
3616
b4ff3a36 3617 u8 reserved_at_280[0x80];
e281682b
SM		 3618
3619 u8 lid[0x10];
b4ff3a36 3620 u8 reserved_at_310[0x4];
e281682b
SM		 3621 u8 init_type_reply[0x4];
3622 u8 lmc[0x3];
3623 u8 subnet_timeout[0x5];
3624
3625 u8 sm_lid[0x10];
3626 u8 sm_sl[0x4];
b4ff3a36 3627 u8 reserved_at_334[0xc];
e281682b
SM		 3628
3629 u8 qkey_violation_counter[0x10];
3630 u8 pkey_violation_counter[0x10];
3631
b4ff3a36 3632 u8 reserved_at_360[0xca0];
e281682b
SM		 3633};
3634
d6666753 3635struct mlx5_ifc_esw_vport_context_bits {
65c0f2c1
JL		 3636 u8 fdb_to_vport_reg_c[0x1];
3637 u8 reserved_at_1[0x2];
d6666753
SM		 3638 u8 vport_svlan_strip[0x1];
3639 u8 vport_cvlan_strip[0x1];
3640 u8 vport_svlan_insert[0x1];
3641 u8 vport_cvlan_insert[0x2];
65c0f2c1
JL		 3642 u8 fdb_to_vport_reg_c_id[0x8];
3643 u8 reserved_at_10[0x10];
d6666753 3644
b4ff3a36 3645 u8 reserved_at_20[0x20];
d6666753
SM		 3646
3647 u8 svlan_cfi[0x1];
3648 u8 svlan_pcp[0x3];
3649 u8 svlan_id[0xc];
3650 u8 cvlan_cfi[0x1];
3651 u8 cvlan_pcp[0x3];
3652 u8 cvlan_id[0xc];
3653
97b5484e
AV		 3654 u8 reserved_at_60[0x720];
3655
3656 u8 sw_steering_vport_icm_address_rx[0x40];
3657
3658 u8 sw_steering_vport_icm_address_tx[0x40];
d6666753
SM		 3659};
3660
e281682b
SM		 3661enum {
3662 MLX5_EQC_STATUS_OK = 0x0,
3663 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3664};
3665
3666enum {
3667 MLX5_EQC_ST_ARMED = 0x9,
3668 MLX5_EQC_ST_FIRED = 0xa,
3669};
3670
3671struct mlx5_ifc_eqc_bits {
3672 u8 status[0x4];
b4ff3a36 3673 u8 reserved_at_4[0x9];
e281682b
SM		 3674 u8 ec[0x1];
3675 u8 oi[0x1];
b4ff3a36 3676 u8 reserved_at_f[0x5];
e281682b 3677 u8 st[0x4];
b4ff3a36 3678 u8 reserved_at_18[0x8];
e281682b 3679
b4ff3a36 3680 u8 reserved_at_20[0x20];
e281682b 3681
b4ff3a36 3682 u8 reserved_at_40[0x14];
e281682b 3683 u8 page_offset[0x6];
b4ff3a36 3684 u8 reserved_at_5a[0x6];
e281682b 3685
b4ff3a36 3686 u8 reserved_at_60[0x3];
e281682b
SM		 3687 u8 log_eq_size[0x5];
3688 u8 uar_page[0x18];
3689
b4ff3a36 3690 u8 reserved_at_80[0x20];
e281682b 3691
b4ff3a36 3692 u8 reserved_at_a0[0x18];
e281682b
SM		 3693 u8 intr[0x8];
3694
b4ff3a36 3695 u8 reserved_at_c0[0x3];
e281682b 3696 u8 log_page_size[0x5];
b4ff3a36 3697 u8 reserved_at_c8[0x18];
e281682b 3698
b4ff3a36 3699 u8 reserved_at_e0[0x60];
e281682b 3700
b4ff3a36 3701 u8 reserved_at_140[0x8];
e281682b
SM		 3702 u8 consumer_counter[0x18];
3703
b4ff3a36 3704 u8 reserved_at_160[0x8];
e281682b
SM		 3705 u8 producer_counter[0x18];
3706
b4ff3a36 3707 u8 reserved_at_180[0x80];
e281682b
SM		 3708};
3709
3710enum {
3711 MLX5_DCTC_STATE_ACTIVE = 0x0,
3712 MLX5_DCTC_STATE_DRAINING = 0x1,
3713 MLX5_DCTC_STATE_DRAINED = 0x2,
3714};
3715
3716enum {
3717 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3718 MLX5_DCTC_CS_RES_NA = 0x1,
3719 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3720};
3721
3722enum {
3723 MLX5_DCTC_MTU_256_BYTES = 0x1,
3724 MLX5_DCTC_MTU_512_BYTES = 0x2,
3725 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3726 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3727 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3728};
3729
3730struct mlx5_ifc_dctc_bits {
b4ff3a36 3731 u8 reserved_at_0[0x4];
e281682b 3732 u8 state[0x4];
b4ff3a36 3733 u8 reserved_at_8[0x18];
e281682b 3734
b4ff3a36 3735 u8 reserved_at_20[0x8];
e281682b
SM		 3736 u8 user_index[0x18];
3737
b4ff3a36 3738 u8 reserved_at_40[0x8];
e281682b
SM		 3739 u8 cqn[0x18];
3740
3741 u8 counter_set_id[0x8];
3742 u8 atomic_mode[0x4];
3743 u8 rre[0x1];
3744 u8 rwe[0x1];
3745 u8 rae[0x1];
3746 u8 atomic_like_write_en[0x1];
3747 u8 latency_sensitive[0x1];
3748 u8 rlky[0x1];
3749 u8 free_ar[0x1];
b4ff3a36 3750 u8 reserved_at_73[0xd];
e281682b 3751
b4ff3a36 3752 u8 reserved_at_80[0x8];
e281682b 3753 u8 cs_res[0x8];
b4ff3a36 3754 u8 reserved_at_90[0x3];
e281682b 3755 u8 min_rnr_nak[0x5];
b4ff3a36 3756 u8 reserved_at_98[0x8];
e281682b 3757
b4ff3a36 3758 u8 reserved_at_a0[0x8];
7486216b 3759 u8 srqn_xrqn[0x18];
e281682b 3760
b4ff3a36 3761 u8 reserved_at_c0[0x8];
e281682b
SM		 3762 u8 pd[0x18];
3763
3764 u8 tclass[0x8];
b4ff3a36 3765 u8 reserved_at_e8[0x4];
e281682b
SM		 3766 u8 flow_label[0x14];
3767
3768 u8 dc_access_key[0x40];
3769
b4ff3a36 3770 u8 reserved_at_140[0x5];
e281682b
SM		 3771 u8 mtu[0x3];
3772 u8 port[0x8];
3773 u8 pkey_index[0x10];
3774
b4ff3a36 3775 u8 reserved_at_160[0x8];
e281682b 3776 u8 my_addr_index[0x8];
b4ff3a36 3777 u8 reserved_at_170[0x8];
e281682b
SM		 3778 u8 hop_limit[0x8];
3779
3780 u8 dc_access_key_violation_count[0x20];
3781
b4ff3a36 3782 u8 reserved_at_1a0[0x14];
e281682b
SM		 3783 u8 dei_cfi[0x1];
3784 u8 eth_prio[0x3];
3785 u8 ecn[0x2];
3786 u8 dscp[0x6];
3787
a645a89d
LR		 3788 u8 reserved_at_1c0[0x20];
3789 u8 ece[0x20];
e281682b
SM		 3790};
3791
3792enum {
3793 MLX5_CQC_STATUS_OK = 0x0,
3794 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3795 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3796};
3797
3798enum {
3799 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3800 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3801};
3802
3803enum {
3804 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3805 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3806 MLX5_CQC_ST_FIRED = 0xa,
3807};
3808
7d5e1423
SM		 3809enum {
3810 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3811 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3812 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3813};
3814
e281682b
SM		 3815struct mlx5_ifc_cqc_bits {
3816 u8 status[0x4];
bd371975
LR		 3817 u8 reserved_at_4[0x2];
3818 u8 dbr_umem_valid[0x1];
3819 u8 reserved_at_7[0x1];
e281682b
SM		 3820 u8 cqe_sz[0x3];
3821 u8 cc[0x1];
b4ff3a36 3822 u8 reserved_at_c[0x1];
e281682b
SM		 3823 u8 scqe_break_moderation_en[0x1];
3824 u8 oi[0x1];
7d5e1423
SM		 3825 u8 cq_period_mode[0x2];
3826 u8 cqe_comp_en[0x1];
e281682b
SM		 3827 u8 mini_cqe_res_format[0x2];
3828 u8 st[0x4];
b4ff3a36 3829 u8 reserved_at_18[0x8];
e281682b 3830
b4ff3a36 3831 u8 reserved_at_20[0x20];
e281682b 3832
b4ff3a36 3833 u8 reserved_at_40[0x14];
e281682b 3834 u8 page_offset[0x6];
b4ff3a36 3835 u8 reserved_at_5a[0x6];
e281682b 3836
b4ff3a36 3837 u8 reserved_at_60[0x3];
e281682b
SM		 3838 u8 log_cq_size[0x5];
3839 u8 uar_page[0x18];
3840
b4ff3a36 3841 u8 reserved_at_80[0x4];
e281682b
SM		 3842 u8 cq_period[0xc];
3843 u8 cq_max_count[0x10];
3844
b4ff3a36 3845 u8 reserved_at_a0[0x18];
e281682b
SM		 3846 u8 c_eqn[0x8];
3847
b4ff3a36 3848 u8 reserved_at_c0[0x3];
e281682b 3849 u8 log_page_size[0x5];
b4ff3a36 3850 u8 reserved_at_c8[0x18];
e281682b 3851
b4ff3a36 3852 u8 reserved_at_e0[0x20];
e281682b 3853
b4ff3a36 3854 u8 reserved_at_100[0x8];
e281682b
SM		 3855 u8 last_notified_index[0x18];
3856
b4ff3a36 3857 u8 reserved_at_120[0x8];
e281682b
SM		 3858 u8 last_solicit_index[0x18];
3859
b4ff3a36 3860 u8 reserved_at_140[0x8];
e281682b
SM		 3861 u8 consumer_counter[0x18];
3862
b4ff3a36 3863 u8 reserved_at_160[0x8];
e281682b
SM		 3864 u8 producer_counter[0x18];
3865
b4ff3a36 3866 u8 reserved_at_180[0x40];
e281682b
SM		 3867
3868 u8 dbr_addr[0x40];
3869};
3870
3871union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3872 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3873 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3874 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3875 u8 reserved_at_0[0x800];
e281682b
SM		 3876};
3877
3878struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3879 u8 reserved_at_0[0xc0];
e281682b 3880
b4ff3a36 3881 u8 reserved_at_c0[0x8];
211e6c80
MD		 3882 u8 ieee_vendor_id[0x18];
3883
b4ff3a36 3884 u8 reserved_at_e0[0x10];
e281682b
SM		 3885 u8 vsd_vendor_id[0x10];
3886
3887 u8 vsd[208][0x8];
3888
3889 u8 vsd_contd_psid[16][0x8];
3890};
3891
7486216b
SM		 3892enum {
3893 MLX5_XRQC_STATE_GOOD = 0x0,
3894 MLX5_XRQC_STATE_ERROR = 0x1,
3895};
3896
3897enum {
3898 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3899 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3900};
3901
3902enum {
3903 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3904};
3905
3906struct mlx5_ifc_tag_matching_topology_context_bits {
3907 u8 log_matching_list_sz[0x4];
3908 u8 reserved_at_4[0xc];
3909 u8 append_next_index[0x10];
3910
3911 u8 sw_phase_cnt[0x10];
3912 u8 hw_phase_cnt[0x10];
3913
3914 u8 reserved_at_40[0x40];
3915};
3916
3917struct mlx5_ifc_xrqc_bits {
3918 u8 state[0x4];
3919 u8 rlkey[0x1];
3920 u8 reserved_at_5[0xf];
3921 u8 topology[0x4];
3922 u8 reserved_at_18[0x4];
3923 u8 offload[0x4];
3924
3925 u8 reserved_at_20[0x8];
3926 u8 user_index[0x18];
3927
3928 u8 reserved_at_40[0x8];
3929 u8 cqn[0x18];
3930
3931 u8 reserved_at_60[0xa0];
3932
3933 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3934
6e44636a 3935 u8 reserved_at_180[0x280];
7486216b
SM		 3936
3937 struct mlx5_ifc_wq_bits wq;
3938};
3939
e281682b
SM		 3940union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3941 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3942 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3943 u8 reserved_at_0[0x20];
e281682b
SM		 3944};
3945
3946union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3947 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3948 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3949 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3950 u8 reserved_at_0[0x20];
e281682b
SM		 3951};
3952
3953union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3954 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3955 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3956 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3957 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3958 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3959 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 3960 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3961 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
1c64bf6f 3962 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3963 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3964 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3965 u8 reserved_at_0[0x7c0];
e281682b
SM		 3966};
3967
8ed1a630
GP		 3968union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3969 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3970 u8 reserved_at_0[0x7c0];
3971};
3972
e281682b
SM		 3973union mlx5_ifc_event_auto_bits {
3974 struct mlx5_ifc_comp_event_bits comp_event;
3975 struct mlx5_ifc_dct_events_bits dct_events;
3976 struct mlx5_ifc_qp_events_bits qp_events;
3977 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3978 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3979 struct mlx5_ifc_cq_error_bits cq_error;
3980 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3981 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3982 struct mlx5_ifc_gpio_event_bits gpio_event;
3983 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3984 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3985 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3986 u8 reserved_at_0[0xe0];
e281682b
SM		 3987};
3988
3989struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3990 u8 reserved_at_0[0x100];
e281682b
SM		 3991
3992 u8 assert_existptr[0x20];
3993
3994 u8 assert_callra[0x20];
3995
b4ff3a36 3996 u8 reserved_at_140[0x40];
e281682b
SM		 3997
3998 u8 fw_version[0x20];
3999
4000 u8 hw_id[0x20];
4001
b4ff3a36 4002 u8 reserved_at_1c0[0x20];
e281682b
SM		 4003
4004 u8 irisc_index[0x8];
4005 u8 synd[0x8];
4006 u8 ext_synd[0x10];
4007};
4008
4009struct mlx5_ifc_register_loopback_control_bits {
4010 u8 no_lb[0x1];
b4ff3a36 4011 u8 reserved_at_1[0x7];
e281682b 4012 u8 port[0x8];
b4ff3a36 4013 u8 reserved_at_10[0x10];
e281682b 4014
b4ff3a36 4015 u8 reserved_at_20[0x60];
e281682b
SM		 4016};
4017
813f8540
MHY		 4018struct mlx5_ifc_vport_tc_element_bits {
4019 u8 traffic_class[0x4];
4020 u8 reserved_at_4[0xc];
4021 u8 vport_number[0x10];
4022};
4023
4024struct mlx5_ifc_vport_element_bits {
4025 u8 reserved_at_0[0x10];
4026 u8 vport_number[0x10];
4027};
4028
4029enum {
4030 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4031 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4032 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4033};
4034
4035struct mlx5_ifc_tsar_element_bits {
4036 u8 reserved_at_0[0x8];
4037 u8 tsar_type[0x8];
4038 u8 reserved_at_10[0x10];
4039};
4040
8812c24d
MD		 4041enum {
4042 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4043 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4044};
4045
e281682b
SM		 4046struct mlx5_ifc_teardown_hca_out_bits {
4047 u8 status[0x8];
b4ff3a36 4048 u8 reserved_at_8[0x18];
e281682b
SM		 4049
4050 u8 syndrome[0x20];
4051
8812c24d
MD		 4052 u8 reserved_at_40[0x3f];
4053
fcd29ad1 4054 u8 state[0x1];
e281682b
SM		 4055};
4056
4057enum {
4058 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 4059 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 4060 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 4061};
4062
4063struct mlx5_ifc_teardown_hca_in_bits {
4064 u8 opcode[0x10];
b4ff3a36 4065 u8 reserved_at_10[0x10];
e281682b 4066
b4ff3a36 4067 u8 reserved_at_20[0x10];
e281682b
SM		 4068 u8 op_mod[0x10];
4069
b4ff3a36 4070 u8 reserved_at_40[0x10];
e281682b
SM		 4071 u8 profile[0x10];
4072
b4ff3a36 4073 u8 reserved_at_60[0x20];
e281682b
SM		 4074};
4075
4076struct mlx5_ifc_sqerr2rts_qp_out_bits {
4077 u8 status[0x8];
b4ff3a36 4078 u8 reserved_at_8[0x18];
e281682b
SM		 4079
4080 u8 syndrome[0x20];
4081
b4ff3a36 4082 u8 reserved_at_40[0x40];
e281682b
SM		 4083};
4084
4085struct mlx5_ifc_sqerr2rts_qp_in_bits {
4086 u8 opcode[0x10];
4ac63ec7 4087 u8 uid[0x10];
e281682b 4088
b4ff3a36 4089 u8 reserved_at_20[0x10];
e281682b
SM		 4090 u8 op_mod[0x10];
4091
b4ff3a36 4092 u8 reserved_at_40[0x8];
e281682b
SM		 4093 u8 qpn[0x18];
4094
b4ff3a36 4095 u8 reserved_at_60[0x20];
e281682b
SM		 4096
4097 u8 opt_param_mask[0x20];
4098
b4ff3a36 4099 u8 reserved_at_a0[0x20];
e281682b
SM		 4100
4101 struct mlx5_ifc_qpc_bits qpc;
4102
b4ff3a36 4103 u8 reserved_at_800[0x80];
e281682b
SM		 4104};
4105
4106struct mlx5_ifc_sqd2rts_qp_out_bits {
4107 u8 status[0x8];
b4ff3a36 4108 u8 reserved_at_8[0x18];
e281682b
SM		 4109
4110 u8 syndrome[0x20];
4111
b4ff3a36 4112 u8 reserved_at_40[0x40];
e281682b
SM		 4113};
4114
4115struct mlx5_ifc_sqd2rts_qp_in_bits {
4116 u8 opcode[0x10];
4ac63ec7 4117 u8 uid[0x10];
e281682b 4118
b4ff3a36 4119 u8 reserved_at_20[0x10];
e281682b
SM		 4120 u8 op_mod[0x10];
4121
b4ff3a36 4122 u8 reserved_at_40[0x8];
e281682b
SM		 4123 u8 qpn[0x18];
4124
b4ff3a36 4125 u8 reserved_at_60[0x20];
e281682b
SM		 4126
4127 u8 opt_param_mask[0x20];
4128
b4ff3a36 4129 u8 reserved_at_a0[0x20];
e281682b
SM		 4130
4131 struct mlx5_ifc_qpc_bits qpc;
4132
b4ff3a36 4133 u8 reserved_at_800[0x80];
e281682b
SM		 4134};
4135
4136struct mlx5_ifc_set_roce_address_out_bits {
4137 u8 status[0x8];
b4ff3a36 4138 u8 reserved_at_8[0x18];
e281682b
SM		 4139
4140 u8 syndrome[0x20];
4141
b4ff3a36 4142 u8 reserved_at_40[0x40];
e281682b
SM		 4143};
4144
4145struct mlx5_ifc_set_roce_address_in_bits {
4146 u8 opcode[0x10];
b4ff3a36 4147 u8 reserved_at_10[0x10];
e281682b 4148
b4ff3a36 4149 u8 reserved_at_20[0x10];
e281682b
SM		 4150 u8 op_mod[0x10];
4151
4152 u8 roce_address_index[0x10];
32f69e4b
DJ		 4153 u8 reserved_at_50[0xc];
4154 u8 vhca_port_num[0x4];
e281682b 4155
b4ff3a36 4156 u8 reserved_at_60[0x20];
e281682b
SM		 4157
4158 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4159};
4160
4161struct mlx5_ifc_set_mad_demux_out_bits {
4162 u8 status[0x8];
b4ff3a36 4163 u8 reserved_at_8[0x18];
e281682b
SM		 4164
4165 u8 syndrome[0x20];
4166
b4ff3a36 4167 u8 reserved_at_40[0x40];
e281682b
SM		 4168};
4169
4170enum {
4171 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4172 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4173};
4174
4175struct mlx5_ifc_set_mad_demux_in_bits {
4176 u8 opcode[0x10];
b4ff3a36 4177 u8 reserved_at_10[0x10];
e281682b 4178
b4ff3a36 4179 u8 reserved_at_20[0x10];
e281682b
SM		 4180 u8 op_mod[0x10];
4181
b4ff3a36 4182 u8 reserved_at_40[0x20];
e281682b 4183
b4ff3a36 4184 u8 reserved_at_60[0x6];
e281682b 4185 u8 demux_mode[0x2];
b4ff3a36 4186 u8 reserved_at_68[0x18];
e281682b
SM		 4187};
4188
4189struct mlx5_ifc_set_l2_table_entry_out_bits {
4190 u8 status[0x8];
b4ff3a36 4191 u8 reserved_at_8[0x18];
e281682b
SM		 4192
4193 u8 syndrome[0x20];
4194
b4ff3a36 4195 u8 reserved_at_40[0x40];
e281682b
SM		 4196};
4197
4198struct mlx5_ifc_set_l2_table_entry_in_bits {
4199 u8 opcode[0x10];
b4ff3a36 4200 u8 reserved_at_10[0x10];
e281682b 4201
b4ff3a36 4202 u8 reserved_at_20[0x10];
e281682b
SM		 4203 u8 op_mod[0x10];
4204
b4ff3a36 4205 u8 reserved_at_40[0x60];
e281682b 4206
b4ff3a36 4207 u8 reserved_at_a0[0x8];
e281682b
SM		 4208 u8 table_index[0x18];
4209
b4ff3a36 4210 u8 reserved_at_c0[0x20];
e281682b 4211
b4ff3a36 4212 u8 reserved_at_e0[0x13];
e281682b
SM		 4213 u8 vlan_valid[0x1];
4214 u8 vlan[0xc];
4215
4216 struct mlx5_ifc_mac_address_layout_bits mac_address;
4217
b4ff3a36 4218 u8 reserved_at_140[0xc0];
e281682b
SM		 4219};
4220
4221struct mlx5_ifc_set_issi_out_bits {
4222 u8 status[0x8];
b4ff3a36 4223 u8 reserved_at_8[0x18];
e281682b
SM		 4224
4225 u8 syndrome[0x20];
4226
b4ff3a36 4227 u8 reserved_at_40[0x40];
e281682b
SM		 4228};
4229
4230struct mlx5_ifc_set_issi_in_bits {
4231 u8 opcode[0x10];
b4ff3a36 4232 u8 reserved_at_10[0x10];
e281682b 4233
b4ff3a36 4234 u8 reserved_at_20[0x10];
e281682b
SM		 4235 u8 op_mod[0x10];
4236
b4ff3a36 4237 u8 reserved_at_40[0x10];
e281682b
SM		 4238 u8 current_issi[0x10];
4239
b4ff3a36 4240 u8 reserved_at_60[0x20];
e281682b
SM		 4241};
4242
4243struct mlx5_ifc_set_hca_cap_out_bits {
4244 u8 status[0x8];
b4ff3a36 4245 u8 reserved_at_8[0x18];
e281682b
SM		 4246
4247 u8 syndrome[0x20];
4248
b4ff3a36 4249 u8 reserved_at_40[0x40];
e281682b
SM		 4250};
4251
4252struct mlx5_ifc_set_hca_cap_in_bits {
4253 u8 opcode[0x10];
b4ff3a36 4254 u8 reserved_at_10[0x10];
e281682b 4255
b4ff3a36 4256 u8 reserved_at_20[0x10];
e281682b
SM		 4257 u8 op_mod[0x10];
4258
959af556
YH		 4259 u8 other_function[0x1];
4260 u8 reserved_at_41[0xf];
4261 u8 function_id[0x10];
4262
4263 u8 reserved_at_60[0x20];
e281682b
SM		 4264
4265 union mlx5_ifc_hca_cap_union_bits capability;
4266};
4267
26a81453
MG		 4268enum {
4269 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4270 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4271 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2b58f6d9
RS		 4272 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4273 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
26a81453
MG		 4274};
4275
e281682b
SM		 4276struct mlx5_ifc_set_fte_out_bits {
4277 u8 status[0x8];
b4ff3a36 4278 u8 reserved_at_8[0x18];
e281682b
SM		 4279
4280 u8 syndrome[0x20];
4281
b4ff3a36 4282 u8 reserved_at_40[0x40];
e281682b
SM		 4283};
4284
4285struct mlx5_ifc_set_fte_in_bits {
4286 u8 opcode[0x10];
b4ff3a36 4287 u8 reserved_at_10[0x10];
e281682b 4288
b4ff3a36 4289 u8 reserved_at_20[0x10];
e281682b
SM		 4290 u8 op_mod[0x10];
4291
7d5e1423
SM		 4292 u8 other_vport[0x1];
4293 u8 reserved_at_41[0xf];
4294 u8 vport_number[0x10];
4295
4296 u8 reserved_at_60[0x20];
e281682b
SM		 4297
4298 u8 table_type[0x8];
b4ff3a36 4299 u8 reserved_at_88[0x18];
e281682b 4300
b4ff3a36 4301 u8 reserved_at_a0[0x8];
e281682b
SM		 4302 u8 table_id[0x18];
4303
822e114b
PB		 4304 u8 ignore_flow_level[0x1];
4305 u8 reserved_at_c1[0x17];
26a81453
MG		 4306 u8 modify_enable_mask[0x8];
4307
b4ff3a36 4308 u8 reserved_at_e0[0x20];
e281682b
SM		 4309
4310 u8 flow_index[0x20];
4311
b4ff3a36 4312 u8 reserved_at_120[0xe0];
e281682b
SM		 4313
4314 struct mlx5_ifc_flow_context_bits flow_context;
4315};
4316
4317struct mlx5_ifc_rts2rts_qp_out_bits {
4318 u8 status[0x8];
b4ff3a36 4319 u8 reserved_at_8[0x18];
e281682b
SM		 4320
4321 u8 syndrome[0x20];
4322
6b646a7e
LR		 4323 u8 reserved_at_40[0x20];
4324 u8 ece[0x20];
e281682b
SM		 4325};
4326
4327struct mlx5_ifc_rts2rts_qp_in_bits {
4328 u8 opcode[0x10];
4ac63ec7 4329 u8 uid[0x10];
e281682b 4330
b4ff3a36 4331 u8 reserved_at_20[0x10];
e281682b
SM		 4332 u8 op_mod[0x10];
4333
b4ff3a36 4334 u8 reserved_at_40[0x8];
e281682b
SM		 4335 u8 qpn[0x18];
4336
b4ff3a36 4337 u8 reserved_at_60[0x20];
e281682b
SM		 4338
4339 u8 opt_param_mask[0x20];
4340
6b646a7e 4341 u8 ece[0x20];
e281682b
SM		 4342
4343 struct mlx5_ifc_qpc_bits qpc;
4344
b4ff3a36 4345 u8 reserved_at_800[0x80];
e281682b
SM		 4346};
4347
4348struct mlx5_ifc_rtr2rts_qp_out_bits {
4349 u8 status[0x8];
b4ff3a36 4350 u8 reserved_at_8[0x18];
e281682b
SM		 4351
4352 u8 syndrome[0x20];
4353
6b646a7e
LR		 4354 u8 reserved_at_40[0x20];
4355 u8 ece[0x20];
e281682b
SM		 4356};
4357
4358struct mlx5_ifc_rtr2rts_qp_in_bits {
4359 u8 opcode[0x10];
4ac63ec7 4360 u8 uid[0x10];
e281682b 4361
b4ff3a36 4362 u8 reserved_at_20[0x10];
e281682b
SM		 4363 u8 op_mod[0x10];
4364
b4ff3a36 4365 u8 reserved_at_40[0x8];
e281682b
SM		 4366 u8 qpn[0x18];
4367
b4ff3a36 4368 u8 reserved_at_60[0x20];
e281682b
SM		 4369
4370 u8 opt_param_mask[0x20];
4371
6b646a7e 4372 u8 ece[0x20];
e281682b
SM		 4373
4374 struct mlx5_ifc_qpc_bits qpc;
4375
b4ff3a36 4376 u8 reserved_at_800[0x80];
e281682b
SM		 4377};
4378
4379struct mlx5_ifc_rst2init_qp_out_bits {
4380 u8 status[0x8];
b4ff3a36 4381 u8 reserved_at_8[0x18];
e281682b
SM		 4382
4383 u8 syndrome[0x20];
4384
ab183d46
LR		 4385 u8 reserved_at_40[0x20];
4386 u8 ece[0x20];
e281682b
SM		 4387};
4388
4389struct mlx5_ifc_rst2init_qp_in_bits {
4390 u8 opcode[0x10];
4ac63ec7 4391 u8 uid[0x10];
e281682b 4392
b4ff3a36 4393 u8 reserved_at_20[0x10];
e281682b
SM		 4394 u8 op_mod[0x10];
4395
b4ff3a36 4396 u8 reserved_at_40[0x8];
e281682b
SM		 4397 u8 qpn[0x18];
4398
b4ff3a36 4399 u8 reserved_at_60[0x20];
e281682b
SM		 4400
4401 u8 opt_param_mask[0x20];
4402
ab183d46 4403 u8 ece[0x20];
e281682b
SM		 4404
4405 struct mlx5_ifc_qpc_bits qpc;
4406
b4ff3a36 4407 u8 reserved_at_800[0x80];
e281682b
SM		 4408};
4409
7486216b
SM		 4410struct mlx5_ifc_query_xrq_out_bits {
4411 u8 status[0x8];
4412 u8 reserved_at_8[0x18];
4413
4414 u8 syndrome[0x20];
4415
4416 u8 reserved_at_40[0x40];
4417
4418 struct mlx5_ifc_xrqc_bits xrq_context;
4419};
4420
4421struct mlx5_ifc_query_xrq_in_bits {
4422 u8 opcode[0x10];
4423 u8 reserved_at_10[0x10];
4424
4425 u8 reserved_at_20[0x10];
4426 u8 op_mod[0x10];
4427
4428 u8 reserved_at_40[0x8];
4429 u8 xrqn[0x18];
4430
4431 u8 reserved_at_60[0x20];
4432};
4433
e281682b
SM		 4434struct mlx5_ifc_query_xrc_srq_out_bits {
4435 u8 status[0x8];
b4ff3a36 4436 u8 reserved_at_8[0x18];
e281682b
SM		 4437
4438 u8 syndrome[0x20];
4439
b4ff3a36 4440 u8 reserved_at_40[0x40];
e281682b
SM		 4441
4442 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4443
b4ff3a36 4444 u8 reserved_at_280[0x600];
e281682b 4445
b6ca09cb 4446 u8 pas[][0x40];
e281682b
SM		 4447};
4448
4449struct mlx5_ifc_query_xrc_srq_in_bits {
4450 u8 opcode[0x10];
b4ff3a36 4451 u8 reserved_at_10[0x10];
e281682b 4452
b4ff3a36 4453 u8 reserved_at_20[0x10];
e281682b
SM		 4454 u8 op_mod[0x10];
4455
b4ff3a36 4456 u8 reserved_at_40[0x8];
e281682b
SM		 4457 u8 xrc_srqn[0x18];
4458
b4ff3a36 4459 u8 reserved_at_60[0x20];
e281682b
SM		 4460};
4461
4462enum {
4463 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4464 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4465};
4466
4467struct mlx5_ifc_query_vport_state_out_bits {
4468 u8 status[0x8];
b4ff3a36 4469 u8 reserved_at_8[0x18];
e281682b
SM		 4470
4471 u8 syndrome[0x20];
4472
b4ff3a36 4473 u8 reserved_at_40[0x20];
e281682b 4474
b4ff3a36 4475 u8 reserved_at_60[0x18];
e281682b
SM		 4476 u8 admin_state[0x4];
4477 u8 state[0x4];
4478};
4479
4480enum {
cc9c82a8
EBE		 4481 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4482 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
7d0314b1 4483 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
e281682b
SM		 4484};
4485
fd4572b3
ED		 4486struct mlx5_ifc_arm_monitor_counter_in_bits {
4487 u8 opcode[0x10];
4488 u8 uid[0x10];
4489
4490 u8 reserved_at_20[0x10];
4491 u8 op_mod[0x10];
4492
4493 u8 reserved_at_40[0x20];
4494
4495 u8 reserved_at_60[0x20];
4496};
4497
4498struct mlx5_ifc_arm_monitor_counter_out_bits {
4499 u8 status[0x8];
4500 u8 reserved_at_8[0x18];
4501
4502 u8 syndrome[0x20];
4503
4504 u8 reserved_at_40[0x40];
4505};
4506
4507enum {
4508 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4509 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4510};
4511
4512enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 4513 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4514 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4515 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4516 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4517 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4518 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 4519};
4520
4521enum {
4c8b8518 4522 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 4523};
4524
4525struct mlx5_ifc_monitor_counter_output_bits {
4526 u8 reserved_at_0[0x4];
4527 u8 type[0x4];
4528 u8 reserved_at_8[0x8];
4529 u8 counter[0x10];
4530
4531 u8 counter_group_id[0x20];
4532};
4533
4534#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4535#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4536#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4537 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4538
4539struct mlx5_ifc_set_monitor_counter_in_bits {
4540 u8 opcode[0x10];
4541 u8 uid[0x10];
4542
4543 u8 reserved_at_20[0x10];
4544 u8 op_mod[0x10];
4545
4546 u8 reserved_at_40[0x10];
4547 u8 num_of_counters[0x10];
4548
4549 u8 reserved_at_60[0x20];
4550
4551 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4552};
4553
4554struct mlx5_ifc_set_monitor_counter_out_bits {
4555 u8 status[0x8];
4556 u8 reserved_at_8[0x18];
4557
4558 u8 syndrome[0x20];
4559
4560 u8 reserved_at_40[0x40];
4561};
4562
e281682b
SM		 4563struct mlx5_ifc_query_vport_state_in_bits {
4564 u8 opcode[0x10];
b4ff3a36 4565 u8 reserved_at_10[0x10];
e281682b 4566
b4ff3a36 4567 u8 reserved_at_20[0x10];
e281682b
SM		 4568 u8 op_mod[0x10];
4569
4570 u8 other_vport[0x1];
b4ff3a36 4571 u8 reserved_at_41[0xf];
e281682b
SM		 4572 u8 vport_number[0x10];
4573
b4ff3a36 4574 u8 reserved_at_60[0x20];
e281682b
SM		 4575};
4576
61c5b5c9
MS		 4577struct mlx5_ifc_query_vnic_env_out_bits {
4578 u8 status[0x8];
4579 u8 reserved_at_8[0x18];
4580
4581 u8 syndrome[0x20];
4582
4583 u8 reserved_at_40[0x40];
4584
4585 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4586};
4587
4588enum {
4589 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4590};
4591
4592struct mlx5_ifc_query_vnic_env_in_bits {
4593 u8 opcode[0x10];
4594 u8 reserved_at_10[0x10];
4595
4596 u8 reserved_at_20[0x10];
4597 u8 op_mod[0x10];
4598
4599 u8 other_vport[0x1];
4600 u8 reserved_at_41[0xf];
4601 u8 vport_number[0x10];
4602
4603 u8 reserved_at_60[0x20];
4604};
4605
e281682b
SM		 4606struct mlx5_ifc_query_vport_counter_out_bits {
4607 u8 status[0x8];
b4ff3a36 4608 u8 reserved_at_8[0x18];
e281682b
SM		 4609
4610 u8 syndrome[0x20];
4611
b4ff3a36 4612 u8 reserved_at_40[0x40];
e281682b
SM		 4613
4614 struct mlx5_ifc_traffic_counter_bits received_errors;
4615
4616 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4617
4618 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4619
4620 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4621
4622 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4623
4624 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4625
4626 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4627
4628 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4629
4630 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4631
4632 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4633
4634 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4635
4636 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4637
b4ff3a36 4638 u8 reserved_at_680[0xa00];
e281682b
SM		 4639};
4640
4641enum {
4642 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4643};
4644
4645struct mlx5_ifc_query_vport_counter_in_bits {
4646 u8 opcode[0x10];
b4ff3a36 4647 u8 reserved_at_10[0x10];
e281682b 4648
b4ff3a36 4649 u8 reserved_at_20[0x10];
e281682b
SM		 4650 u8 op_mod[0x10];
4651
4652 u8 other_vport[0x1];
b54ba277
MY		 4653 u8 reserved_at_41[0xb];
4654 u8 port_num[0x4];
e281682b
SM		 4655 u8 vport_number[0x10];
4656
b4ff3a36 4657 u8 reserved_at_60[0x60];
e281682b
SM		 4658
4659 u8 clear[0x1];
b4ff3a36 4660 u8 reserved_at_c1[0x1f];
e281682b 4661
b4ff3a36 4662 u8 reserved_at_e0[0x20];
e281682b
SM		 4663};
4664
4665struct mlx5_ifc_query_tis_out_bits {
4666 u8 status[0x8];
b4ff3a36 4667 u8 reserved_at_8[0x18];
e281682b
SM		 4668
4669 u8 syndrome[0x20];
4670
b4ff3a36 4671 u8 reserved_at_40[0x40];
e281682b
SM		 4672
4673 struct mlx5_ifc_tisc_bits tis_context;
4674};
4675
4676struct mlx5_ifc_query_tis_in_bits {
4677 u8 opcode[0x10];
b4ff3a36 4678 u8 reserved_at_10[0x10];
e281682b 4679
b4ff3a36 4680 u8 reserved_at_20[0x10];
e281682b
SM		 4681 u8 op_mod[0x10];
4682
b4ff3a36 4683 u8 reserved_at_40[0x8];
e281682b
SM		 4684 u8 tisn[0x18];
4685
b4ff3a36 4686 u8 reserved_at_60[0x20];
e281682b
SM		 4687};
4688
4689struct mlx5_ifc_query_tir_out_bits {
4690 u8 status[0x8];
b4ff3a36 4691 u8 reserved_at_8[0x18];
e281682b
SM		 4692
4693 u8 syndrome[0x20];
4694
b4ff3a36 4695 u8 reserved_at_40[0xc0];
e281682b
SM		 4696
4697 struct mlx5_ifc_tirc_bits tir_context;
4698};
4699
4700struct mlx5_ifc_query_tir_in_bits {
4701 u8 opcode[0x10];
b4ff3a36 4702 u8 reserved_at_10[0x10];
e281682b 4703
b4ff3a36 4704 u8 reserved_at_20[0x10];
e281682b
SM		 4705 u8 op_mod[0x10];
4706
b4ff3a36 4707 u8 reserved_at_40[0x8];
e281682b
SM		 4708 u8 tirn[0x18];
4709
b4ff3a36 4710 u8 reserved_at_60[0x20];
e281682b
SM		 4711};
4712
4713struct mlx5_ifc_query_srq_out_bits {
4714 u8 status[0x8];
b4ff3a36 4715 u8 reserved_at_8[0x18];
e281682b
SM		 4716
4717 u8 syndrome[0x20];
4718
b4ff3a36 4719 u8 reserved_at_40[0x40];
e281682b
SM		 4720
4721 struct mlx5_ifc_srqc_bits srq_context_entry;
4722
b4ff3a36 4723 u8 reserved_at_280[0x600];
e281682b 4724
b6ca09cb 4725 u8 pas[][0x40];
e281682b
SM		 4726};
4727
4728struct mlx5_ifc_query_srq_in_bits {
4729 u8 opcode[0x10];
b4ff3a36 4730 u8 reserved_at_10[0x10];
e281682b 4731
b4ff3a36 4732 u8 reserved_at_20[0x10];
e281682b
SM		 4733 u8 op_mod[0x10];
4734
b4ff3a36 4735 u8 reserved_at_40[0x8];
e281682b
SM		 4736 u8 srqn[0x18];
4737
b4ff3a36 4738 u8 reserved_at_60[0x20];
e281682b
SM		 4739};
4740
4741struct mlx5_ifc_query_sq_out_bits {
4742 u8 status[0x8];
b4ff3a36 4743 u8 reserved_at_8[0x18];
e281682b
SM		 4744
4745 u8 syndrome[0x20];
4746
b4ff3a36 4747 u8 reserved_at_40[0xc0];
e281682b
SM		 4748
4749 struct mlx5_ifc_sqc_bits sq_context;
4750};
4751
4752struct mlx5_ifc_query_sq_in_bits {
4753 u8 opcode[0x10];
b4ff3a36 4754 u8 reserved_at_10[0x10];
e281682b 4755
b4ff3a36 4756 u8 reserved_at_20[0x10];
e281682b
SM		 4757 u8 op_mod[0x10];
4758
b4ff3a36 4759 u8 reserved_at_40[0x8];
e281682b
SM		 4760 u8 sqn[0x18];
4761
b4ff3a36 4762 u8 reserved_at_60[0x20];
e281682b
SM		 4763};
4764
4765struct mlx5_ifc_query_special_contexts_out_bits {
4766 u8 status[0x8];
b4ff3a36 4767 u8 reserved_at_8[0x18];
e281682b
SM		 4768
4769 u8 syndrome[0x20];
4770
ec22eb53 4771 u8 dump_fill_mkey[0x20];
e281682b
SM		 4772
4773 u8 resd_lkey[0x20];
bcda1aca
AK		 4774
4775 u8 null_mkey[0x20];
4776
4777 u8 reserved_at_a0[0x60];
e281682b
SM		 4778};
4779
4780struct mlx5_ifc_query_special_contexts_in_bits {
4781 u8 opcode[0x10];
b4ff3a36 4782 u8 reserved_at_10[0x10];
e281682b 4783
b4ff3a36 4784 u8 reserved_at_20[0x10];
e281682b
SM		 4785 u8 op_mod[0x10];
4786
b4ff3a36 4787 u8 reserved_at_40[0x40];
e281682b
SM		 4788};
4789
813f8540
MHY		 4790struct mlx5_ifc_query_scheduling_element_out_bits {
4791 u8 opcode[0x10];
4792 u8 reserved_at_10[0x10];
4793
4794 u8 reserved_at_20[0x10];
4795 u8 op_mod[0x10];
4796
4797 u8 reserved_at_40[0xc0];
4798
4799 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4800
4801 u8 reserved_at_300[0x100];
4802};
4803
4804enum {
4805 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4806};
4807
4808struct mlx5_ifc_query_scheduling_element_in_bits {
4809 u8 opcode[0x10];
4810 u8 reserved_at_10[0x10];
4811
4812 u8 reserved_at_20[0x10];
4813 u8 op_mod[0x10];
4814
4815 u8 scheduling_hierarchy[0x8];
4816 u8 reserved_at_48[0x18];
4817
4818 u8 scheduling_element_id[0x20];
4819
4820 u8 reserved_at_80[0x180];
4821};
4822
e281682b
SM		 4823struct mlx5_ifc_query_rqt_out_bits {
4824 u8 status[0x8];
b4ff3a36 4825 u8 reserved_at_8[0x18];
e281682b
SM		 4826
4827 u8 syndrome[0x20];
4828
b4ff3a36 4829 u8 reserved_at_40[0xc0];
e281682b
SM		 4830
4831 struct mlx5_ifc_rqtc_bits rqt_context;
4832};
4833
4834struct mlx5_ifc_query_rqt_in_bits {
4835 u8 opcode[0x10];
b4ff3a36 4836 u8 reserved_at_10[0x10];
e281682b 4837
b4ff3a36 4838 u8 reserved_at_20[0x10];
e281682b
SM		 4839 u8 op_mod[0x10];
4840
b4ff3a36 4841 u8 reserved_at_40[0x8];
e281682b
SM		 4842 u8 rqtn[0x18];
4843
b4ff3a36 4844 u8 reserved_at_60[0x20];
e281682b
SM		 4845};
4846
4847struct mlx5_ifc_query_rq_out_bits {
4848 u8 status[0x8];
b4ff3a36 4849 u8 reserved_at_8[0x18];
e281682b
SM		 4850
4851 u8 syndrome[0x20];
4852
b4ff3a36 4853 u8 reserved_at_40[0xc0];
e281682b
SM		 4854
4855 struct mlx5_ifc_rqc_bits rq_context;
4856};
4857
4858struct mlx5_ifc_query_rq_in_bits {
4859 u8 opcode[0x10];
b4ff3a36 4860 u8 reserved_at_10[0x10];
e281682b 4861
b4ff3a36 4862 u8 reserved_at_20[0x10];
e281682b
SM		 4863 u8 op_mod[0x10];
4864
b4ff3a36 4865 u8 reserved_at_40[0x8];
e281682b
SM		 4866 u8 rqn[0x18];
4867
b4ff3a36 4868 u8 reserved_at_60[0x20];
e281682b
SM		 4869};
4870
4871struct mlx5_ifc_query_roce_address_out_bits {
4872 u8 status[0x8];
b4ff3a36 4873 u8 reserved_at_8[0x18];
e281682b
SM		 4874
4875 u8 syndrome[0x20];
4876
b4ff3a36 4877 u8 reserved_at_40[0x40];
e281682b
SM		 4878
4879 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4880};
4881
4882struct mlx5_ifc_query_roce_address_in_bits {
4883 u8 opcode[0x10];
b4ff3a36 4884 u8 reserved_at_10[0x10];
e281682b 4885
b4ff3a36 4886 u8 reserved_at_20[0x10];
e281682b
SM		 4887 u8 op_mod[0x10];
4888
4889 u8 roce_address_index[0x10];
32f69e4b
DJ		 4890 u8 reserved_at_50[0xc];
4891 u8 vhca_port_num[0x4];
e281682b 4892
b4ff3a36 4893 u8 reserved_at_60[0x20];
e281682b
SM		 4894};
4895
4896struct mlx5_ifc_query_rmp_out_bits {
4897 u8 status[0x8];
b4ff3a36 4898 u8 reserved_at_8[0x18];
e281682b
SM		 4899
4900 u8 syndrome[0x20];
4901
b4ff3a36 4902 u8 reserved_at_40[0xc0];
e281682b
SM		 4903
4904 struct mlx5_ifc_rmpc_bits rmp_context;
4905};
4906
4907struct mlx5_ifc_query_rmp_in_bits {
4908 u8 opcode[0x10];
b4ff3a36 4909 u8 reserved_at_10[0x10];
e281682b 4910
b4ff3a36 4911 u8 reserved_at_20[0x10];
e281682b
SM		 4912 u8 op_mod[0x10];
4913
b4ff3a36 4914 u8 reserved_at_40[0x8];
e281682b
SM		 4915 u8 rmpn[0x18];
4916
b4ff3a36 4917 u8 reserved_at_60[0x20];
e281682b
SM		 4918};
4919
4920struct mlx5_ifc_query_qp_out_bits {
4921 u8 status[0x8];
b4ff3a36 4922 u8 reserved_at_8[0x18];
e281682b
SM		 4923
4924 u8 syndrome[0x20];
4925
6b646a7e
LR		 4926 u8 reserved_at_40[0x20];
4927 u8 ece[0x20];
e281682b
SM		 4928
4929 u8 opt_param_mask[0x20];
4930
b4ff3a36 4931 u8 reserved_at_a0[0x20];
e281682b
SM		 4932
4933 struct mlx5_ifc_qpc_bits qpc;
4934
b4ff3a36 4935 u8 reserved_at_800[0x80];
e281682b 4936
b6ca09cb 4937 u8 pas[][0x40];
e281682b
SM		 4938};
4939
4940struct mlx5_ifc_query_qp_in_bits {
4941 u8 opcode[0x10];
b4ff3a36 4942 u8 reserved_at_10[0x10];
e281682b 4943
b4ff3a36 4944 u8 reserved_at_20[0x10];
e281682b
SM		 4945 u8 op_mod[0x10];
4946
b4ff3a36 4947 u8 reserved_at_40[0x8];
e281682b
SM		 4948 u8 qpn[0x18];
4949
b4ff3a36 4950 u8 reserved_at_60[0x20];
e281682b
SM		 4951};
4952
4953struct mlx5_ifc_query_q_counter_out_bits {
4954 u8 status[0x8];
b4ff3a36 4955 u8 reserved_at_8[0x18];
e281682b
SM		 4956
4957 u8 syndrome[0x20];
4958
b4ff3a36 4959 u8 reserved_at_40[0x40];
e281682b
SM		 4960
4961 u8 rx_write_requests[0x20];
4962
b4ff3a36 4963 u8 reserved_at_a0[0x20];
e281682b
SM		 4964
4965 u8 rx_read_requests[0x20];
4966
b4ff3a36 4967 u8 reserved_at_e0[0x20];
e281682b
SM		 4968
4969 u8 rx_atomic_requests[0x20];
4970
b4ff3a36 4971 u8 reserved_at_120[0x20];
e281682b
SM		 4972
4973 u8 rx_dct_connect[0x20];
4974
b4ff3a36 4975 u8 reserved_at_160[0x20];
e281682b
SM		 4976
4977 u8 out_of_buffer[0x20];
4978
b4ff3a36 4979 u8 reserved_at_1a0[0x20];
e281682b
SM		 4980
4981 u8 out_of_sequence[0x20];
4982
7486216b
SM		 4983 u8 reserved_at_1e0[0x20];
4984
4985 u8 duplicate_request[0x20];
4986
4987 u8 reserved_at_220[0x20];
4988
4989 u8 rnr_nak_retry_err[0x20];
4990
4991 u8 reserved_at_260[0x20];
4992
4993 u8 packet_seq_err[0x20];
4994
4995 u8 reserved_at_2a0[0x20];
4996
4997 u8 implied_nak_seq_err[0x20];
4998
4999 u8 reserved_at_2e0[0x20];
5000
5001 u8 local_ack_timeout_err[0x20];
5002
58dcb60a
PP		 5003 u8 reserved_at_320[0xa0];
5004
5005 u8 resp_local_length_error[0x20];
5006
5007 u8 req_local_length_error[0x20];
5008
5009 u8 resp_local_qp_error[0x20];
5010
5011 u8 local_operation_error[0x20];
5012
5013 u8 resp_local_protection[0x20];
5014
5015 u8 req_local_protection[0x20];
5016
5017 u8 resp_cqe_error[0x20];
5018
5019 u8 req_cqe_error[0x20];
5020
5021 u8 req_mw_binding[0x20];
5022
5023 u8 req_bad_response[0x20];
5024
5025 u8 req_remote_invalid_request[0x20];
5026
5027 u8 resp_remote_invalid_request[0x20];
5028
5029 u8 req_remote_access_errors[0x20];
5030
5031 u8 resp_remote_access_errors[0x20];
5032
5033 u8 req_remote_operation_errors[0x20];
5034
5035 u8 req_transport_retries_exceeded[0x20];
5036
5037 u8 cq_overflow[0x20];
5038
5039 u8 resp_cqe_flush_error[0x20];
5040
5041 u8 req_cqe_flush_error[0x20];
5042
8fd5b75d
LR		 5043 u8 reserved_at_620[0x20];
5044
5045 u8 roce_adp_retrans[0x20];
5046
5047 u8 roce_adp_retrans_to[0x20];
5048
5049 u8 roce_slow_restart[0x20];
5050
5051 u8 roce_slow_restart_cnps[0x20];
5052
5053 u8 roce_slow_restart_trans[0x20];
5054
5055 u8 reserved_at_6e0[0x120];
e281682b
SM		 5056};
5057
5058struct mlx5_ifc_query_q_counter_in_bits {
5059 u8 opcode[0x10];
b4ff3a36 5060 u8 reserved_at_10[0x10];
e281682b 5061
b4ff3a36 5062 u8 reserved_at_20[0x10];
e281682b
SM		 5063 u8 op_mod[0x10];
5064
b4ff3a36 5065 u8 reserved_at_40[0x80];
e281682b
SM		 5066
5067 u8 clear[0x1];
b4ff3a36 5068 u8 reserved_at_c1[0x1f];
e281682b 5069
b4ff3a36 5070 u8 reserved_at_e0[0x18];
e281682b
SM		 5071 u8 counter_set_id[0x8];
5072};
5073
5074struct mlx5_ifc_query_pages_out_bits {
5075 u8 status[0x8];
b4ff3a36 5076 u8 reserved_at_8[0x18];
e281682b
SM		 5077
5078 u8 syndrome[0x20];
5079
591905ba
BW		 5080 u8 embedded_cpu_function[0x1];
5081 u8 reserved_at_41[0xf];
e281682b
SM		 5082 u8 function_id[0x10];
5083
5084 u8 num_pages[0x20];
5085};
5086
5087enum {
5088 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5089 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5090 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5091};
5092
5093struct mlx5_ifc_query_pages_in_bits {
5094 u8 opcode[0x10];
b4ff3a36 5095 u8 reserved_at_10[0x10];
e281682b 5096
b4ff3a36 5097 u8 reserved_at_20[0x10];
e281682b
SM		 5098 u8 op_mod[0x10];
5099
591905ba
BW		 5100 u8 embedded_cpu_function[0x1];
5101 u8 reserved_at_41[0xf];
e281682b
SM		 5102 u8 function_id[0x10];
5103
b4ff3a36 5104 u8 reserved_at_60[0x20];
e281682b
SM		 5105};
5106
5107struct mlx5_ifc_query_nic_vport_context_out_bits {
5108 u8 status[0x8];
b4ff3a36 5109 u8 reserved_at_8[0x18];
e281682b
SM		 5110
5111 u8 syndrome[0x20];
5112
b4ff3a36 5113 u8 reserved_at_40[0x40];
e281682b
SM		 5114
5115 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5116};
5117
5118struct mlx5_ifc_query_nic_vport_context_in_bits {
5119 u8 opcode[0x10];
b4ff3a36 5120 u8 reserved_at_10[0x10];
e281682b 5121
b4ff3a36 5122 u8 reserved_at_20[0x10];
e281682b
SM		 5123 u8 op_mod[0x10];
5124
5125 u8 other_vport[0x1];
b4ff3a36 5126 u8 reserved_at_41[0xf];
e281682b
SM		 5127 u8 vport_number[0x10];
5128
b4ff3a36 5129 u8 reserved_at_60[0x5];
e281682b 5130 u8 allowed_list_type[0x3];
b4ff3a36 5131 u8 reserved_at_68[0x18];
e281682b
SM		 5132};
5133
5134struct mlx5_ifc_query_mkey_out_bits {
5135 u8 status[0x8];
b4ff3a36 5136 u8 reserved_at_8[0x18];
e281682b
SM		 5137
5138 u8 syndrome[0x20];
5139
b4ff3a36 5140 u8 reserved_at_40[0x40];
e281682b
SM		 5141
5142 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5143
b4ff3a36 5144 u8 reserved_at_280[0x600];
e281682b
SM		 5145
5146 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5147
5148 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5149};
5150
5151struct mlx5_ifc_query_mkey_in_bits {
5152 u8 opcode[0x10];
b4ff3a36 5153 u8 reserved_at_10[0x10];
e281682b 5154
b4ff3a36 5155 u8 reserved_at_20[0x10];
e281682b
SM		 5156 u8 op_mod[0x10];
5157
b4ff3a36 5158 u8 reserved_at_40[0x8];
e281682b
SM		 5159 u8 mkey_index[0x18];
5160
5161 u8 pg_access[0x1];
b4ff3a36 5162 u8 reserved_at_61[0x1f];
e281682b
SM		 5163};
5164
5165struct mlx5_ifc_query_mad_demux_out_bits {
5166 u8 status[0x8];
b4ff3a36 5167 u8 reserved_at_8[0x18];
e281682b
SM		 5168
5169 u8 syndrome[0x20];
5170
b4ff3a36 5171 u8 reserved_at_40[0x40];
e281682b
SM		 5172
5173 u8 mad_dumux_parameters_block[0x20];
5174};
5175
5176struct mlx5_ifc_query_mad_demux_in_bits {
5177 u8 opcode[0x10];
b4ff3a36 5178 u8 reserved_at_10[0x10];
e281682b 5179
b4ff3a36 5180 u8 reserved_at_20[0x10];
e281682b
SM		 5181 u8 op_mod[0x10];
5182
b4ff3a36 5183 u8 reserved_at_40[0x40];
e281682b
SM		 5184};
5185
5186struct mlx5_ifc_query_l2_table_entry_out_bits {
5187 u8 status[0x8];
b4ff3a36 5188 u8 reserved_at_8[0x18];
e281682b
SM		 5189
5190 u8 syndrome[0x20];
5191
b4ff3a36 5192 u8 reserved_at_40[0xa0];
e281682b 5193
b4ff3a36 5194 u8 reserved_at_e0[0x13];
e281682b
SM		 5195 u8 vlan_valid[0x1];
5196 u8 vlan[0xc];
5197
5198 struct mlx5_ifc_mac_address_layout_bits mac_address;
5199
b4ff3a36 5200 u8 reserved_at_140[0xc0];
e281682b
SM		 5201};
5202
5203struct mlx5_ifc_query_l2_table_entry_in_bits {
5204 u8 opcode[0x10];
b4ff3a36 5205 u8 reserved_at_10[0x10];
e281682b 5206
b4ff3a36 5207 u8 reserved_at_20[0x10];
e281682b
SM		 5208 u8 op_mod[0x10];
5209
b4ff3a36 5210 u8 reserved_at_40[0x60];
e281682b 5211
b4ff3a36 5212 u8 reserved_at_a0[0x8];
e281682b
SM		 5213 u8 table_index[0x18];
5214
b4ff3a36 5215 u8 reserved_at_c0[0x140];
e281682b
SM		 5216};
5217
5218struct mlx5_ifc_query_issi_out_bits {
5219 u8 status[0x8];
b4ff3a36 5220 u8 reserved_at_8[0x18];
e281682b
SM		 5221
5222 u8 syndrome[0x20];
5223
b4ff3a36 5224 u8 reserved_at_40[0x10];
e281682b
SM		 5225 u8 current_issi[0x10];
5226
b4ff3a36 5227 u8 reserved_at_60[0xa0];
e281682b 5228
b4ff3a36 5229 u8 reserved_at_100[76][0x8];
e281682b
SM		 5230 u8 supported_issi_dw0[0x20];
5231};
5232
5233struct mlx5_ifc_query_issi_in_bits {
5234 u8 opcode[0x10];
b4ff3a36 5235 u8 reserved_at_10[0x10];
e281682b 5236
b4ff3a36 5237 u8 reserved_at_20[0x10];
e281682b
SM		 5238 u8 op_mod[0x10];
5239
b4ff3a36 5240 u8 reserved_at_40[0x40];
e281682b
SM		 5241};
5242
0dbc6fe0
SM		 5243struct mlx5_ifc_set_driver_version_out_bits {
5244 u8 status[0x8];
5245 u8 reserved_0[0x18];
5246
5247 u8 syndrome[0x20];
5248 u8 reserved_1[0x40];
5249};
5250
5251struct mlx5_ifc_set_driver_version_in_bits {
5252 u8 opcode[0x10];
5253 u8 reserved_0[0x10];
5254
5255 u8 reserved_1[0x10];
5256 u8 op_mod[0x10];
5257
5258 u8 reserved_2[0x40];
5259 u8 driver_version[64][0x8];
5260};
5261
e281682b
SM		 5262struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5263 u8 status[0x8];
b4ff3a36 5264 u8 reserved_at_8[0x18];
e281682b
SM		 5265
5266 u8 syndrome[0x20];
5267
b4ff3a36 5268 u8 reserved_at_40[0x40];
e281682b 5269
b6ca09cb 5270 struct mlx5_ifc_pkey_bits pkey[];
e281682b
SM		 5271};
5272
5273struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5274 u8 opcode[0x10];
b4ff3a36 5275 u8 reserved_at_10[0x10];
e281682b 5276
b4ff3a36 5277 u8 reserved_at_20[0x10];
e281682b
SM		 5278 u8 op_mod[0x10];
5279
5280 u8 other_vport[0x1];
b4ff3a36 5281 u8 reserved_at_41[0xb];
707c4602 5282 u8 port_num[0x4];
e281682b
SM		 5283 u8 vport_number[0x10];
5284
b4ff3a36 5285 u8 reserved_at_60[0x10];
e281682b
SM		 5286 u8 pkey_index[0x10];
5287};
5288
eff901d3
EC		 5289enum {
5290 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5291 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5292 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5293};
5294
e281682b
SM		 5295struct mlx5_ifc_query_hca_vport_gid_out_bits {
5296 u8 status[0x8];
b4ff3a36 5297 u8 reserved_at_8[0x18];
e281682b
SM		 5298
5299 u8 syndrome[0x20];
5300
b4ff3a36 5301 u8 reserved_at_40[0x20];
e281682b
SM		 5302
5303 u8 gids_num[0x10];
b4ff3a36 5304 u8 reserved_at_70[0x10];
e281682b 5305
b6ca09cb 5306 struct mlx5_ifc_array128_auto_bits gid[];
e281682b
SM		 5307};
5308
5309struct mlx5_ifc_query_hca_vport_gid_in_bits {
5310 u8 opcode[0x10];
b4ff3a36 5311 u8 reserved_at_10[0x10];
e281682b 5312
b4ff3a36 5313 u8 reserved_at_20[0x10];
e281682b
SM		 5314 u8 op_mod[0x10];
5315
5316 u8 other_vport[0x1];
b4ff3a36 5317 u8 reserved_at_41[0xb];
707c4602 5318 u8 port_num[0x4];
e281682b
SM		 5319 u8 vport_number[0x10];
5320
b4ff3a36 5321 u8 reserved_at_60[0x10];
e281682b
SM		 5322 u8 gid_index[0x10];
5323};
5324
5325struct mlx5_ifc_query_hca_vport_context_out_bits {
5326 u8 status[0x8];
b4ff3a36 5327 u8 reserved_at_8[0x18];
e281682b
SM		 5328
5329 u8 syndrome[0x20];
5330
b4ff3a36 5331 u8 reserved_at_40[0x40];
e281682b
SM		 5332
5333 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5334};
5335
5336struct mlx5_ifc_query_hca_vport_context_in_bits {
5337 u8 opcode[0x10];
b4ff3a36 5338 u8 reserved_at_10[0x10];
e281682b 5339
b4ff3a36 5340 u8 reserved_at_20[0x10];
e281682b
SM		 5341 u8 op_mod[0x10];
5342
5343 u8 other_vport[0x1];
b4ff3a36 5344 u8 reserved_at_41[0xb];
707c4602 5345 u8 port_num[0x4];
e281682b
SM		 5346 u8 vport_number[0x10];
5347
b4ff3a36 5348 u8 reserved_at_60[0x20];
e281682b
SM		 5349};
5350
5351struct mlx5_ifc_query_hca_cap_out_bits {
5352 u8 status[0x8];
b4ff3a36 5353 u8 reserved_at_8[0x18];
e281682b
SM		 5354
5355 u8 syndrome[0x20];
5356
b4ff3a36 5357 u8 reserved_at_40[0x40];
e281682b
SM		 5358
5359 union mlx5_ifc_hca_cap_union_bits capability;
5360};
5361
5362struct mlx5_ifc_query_hca_cap_in_bits {
5363 u8 opcode[0x10];
b4ff3a36 5364 u8 reserved_at_10[0x10];
e281682b 5365
b4ff3a36 5366 u8 reserved_at_20[0x10];
e281682b
SM		 5367 u8 op_mod[0x10];
5368
97b5484e
AV		 5369 u8 other_function[0x1];
5370 u8 reserved_at_41[0xf];
5371 u8 function_id[0x10];
5372
5373 u8 reserved_at_60[0x20];
e281682b
SM		 5374};
5375
97b5484e
AV		 5376struct mlx5_ifc_other_hca_cap_bits {
5377 u8 roce[0x1];
d32d7c52 5378 u8 reserved_at_1[0x27f];
97b5484e
AV		 5379};
5380
5381struct mlx5_ifc_query_other_hca_cap_out_bits {
e281682b 5382 u8 status[0x8];
d32d7c52 5383 u8 reserved_at_8[0x18];
e281682b
SM		 5384
5385 u8 syndrome[0x20];
5386
d32d7c52 5387 u8 reserved_at_40[0x40];
e281682b 5388
97b5484e
AV		 5389 struct mlx5_ifc_other_hca_cap_bits other_capability;
5390};
5391
5392struct mlx5_ifc_query_other_hca_cap_in_bits {
5393 u8 opcode[0x10];
d32d7c52 5394 u8 reserved_at_10[0x10];
97b5484e 5395
d32d7c52 5396 u8 reserved_at_20[0x10];
97b5484e
AV		 5397 u8 op_mod[0x10];
5398
d32d7c52 5399 u8 reserved_at_40[0x10];
97b5484e
AV		 5400 u8 function_id[0x10];
5401
d32d7c52 5402 u8 reserved_at_60[0x20];
97b5484e
AV		 5403};
5404
5405struct mlx5_ifc_modify_other_hca_cap_out_bits {
5406 u8 status[0x8];
d32d7c52 5407 u8 reserved_at_8[0x18];
97b5484e
AV		 5408
5409 u8 syndrome[0x20];
5410
d32d7c52 5411 u8 reserved_at_40[0x40];
97b5484e
AV		 5412};
5413
5414struct mlx5_ifc_modify_other_hca_cap_in_bits {
5415 u8 opcode[0x10];
d32d7c52 5416 u8 reserved_at_10[0x10];
97b5484e 5417
d32d7c52 5418 u8 reserved_at_20[0x10];
97b5484e
AV		 5419 u8 op_mod[0x10];
5420
d32d7c52 5421 u8 reserved_at_40[0x10];
97b5484e
AV		 5422 u8 function_id[0x10];
5423 u8 field_select[0x20];
5424
5425 struct mlx5_ifc_other_hca_cap_bits other_capability;
5426};
5427
5428struct mlx5_ifc_flow_table_context_bits {
5429 u8 reformat_en[0x1];
5430 u8 decap_en[0x1];
5431 u8 sw_owner[0x1];
5432 u8 termination_table[0x1];
5433 u8 table_miss_action[0x4];
e281682b 5434 u8 level[0x8];
97b5484e 5435 u8 reserved_at_10[0x8];
e281682b
SM		 5436 u8 log_size[0x8];
5437
97b5484e
AV		 5438 u8 reserved_at_20[0x8];
5439 u8 table_miss_id[0x18];
5440
5441 u8 reserved_at_40[0x8];
5442 u8 lag_master_next_table_id[0x18];
5443
5444 u8 reserved_at_60[0x60];
5445
5446 u8 sw_owner_icm_root_1[0x40];
5447
5448 u8 sw_owner_icm_root_0[0x40];
5449
5450};
5451
5452struct mlx5_ifc_query_flow_table_out_bits {
5453 u8 status[0x8];
5454 u8 reserved_at_8[0x18];
5455
5456 u8 syndrome[0x20];
5457
5458 u8 reserved_at_40[0x80];
5459
5460 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 5461};
5462
5463struct mlx5_ifc_query_flow_table_in_bits {
5464 u8 opcode[0x10];
b4ff3a36 5465 u8 reserved_at_10[0x10];
e281682b 5466
b4ff3a36 5467 u8 reserved_at_20[0x10];
e281682b
SM		 5468 u8 op_mod[0x10];
5469
b4ff3a36 5470 u8 reserved_at_40[0x40];
e281682b
SM		 5471
5472 u8 table_type[0x8];
b4ff3a36 5473 u8 reserved_at_88[0x18];
e281682b 5474
b4ff3a36 5475 u8 reserved_at_a0[0x8];
e281682b
SM		 5476 u8 table_id[0x18];
5477
b4ff3a36 5478 u8 reserved_at_c0[0x140];
e281682b
SM		 5479};
5480
5481struct mlx5_ifc_query_fte_out_bits {
5482 u8 status[0x8];
b4ff3a36 5483 u8 reserved_at_8[0x18];
e281682b
SM		 5484
5485 u8 syndrome[0x20];
5486
b4ff3a36 5487 u8 reserved_at_40[0x1c0];
e281682b
SM		 5488
5489 struct mlx5_ifc_flow_context_bits flow_context;
5490};
5491
5492struct mlx5_ifc_query_fte_in_bits {
5493 u8 opcode[0x10];
b4ff3a36 5494 u8 reserved_at_10[0x10];
e281682b 5495
b4ff3a36 5496 u8 reserved_at_20[0x10];
e281682b
SM		 5497 u8 op_mod[0x10];
5498
b4ff3a36 5499 u8 reserved_at_40[0x40];
e281682b
SM		 5500
5501 u8 table_type[0x8];
b4ff3a36 5502 u8 reserved_at_88[0x18];
e281682b 5503
b4ff3a36 5504 u8 reserved_at_a0[0x8];
e281682b
SM		 5505 u8 table_id[0x18];
5506
b4ff3a36 5507 u8 reserved_at_c0[0x40];
e281682b
SM		 5508
5509 u8 flow_index[0x20];
5510
b4ff3a36 5511 u8 reserved_at_120[0xe0];
e281682b
SM		 5512};
5513
5514enum {
5515 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5516 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5517 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 5518 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
b169e64a 5519 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
7da3ad6c 5520 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
e281682b
SM		 5521};
5522
5523struct mlx5_ifc_query_flow_group_out_bits {
5524 u8 status[0x8];
b4ff3a36 5525 u8 reserved_at_8[0x18];
e281682b
SM		 5526
5527 u8 syndrome[0x20];
5528
b4ff3a36 5529 u8 reserved_at_40[0xa0];
e281682b
SM		 5530
5531 u8 start_flow_index[0x20];
5532
b4ff3a36 5533 u8 reserved_at_100[0x20];
e281682b
SM		 5534
5535 u8 end_flow_index[0x20];
5536
b4ff3a36 5537 u8 reserved_at_140[0xa0];
e281682b 5538
b4ff3a36 5539 u8 reserved_at_1e0[0x18];
e281682b
SM		 5540 u8 match_criteria_enable[0x8];
5541
5542 struct mlx5_ifc_fte_match_param_bits match_criteria;
5543
b4ff3a36 5544 u8 reserved_at_1200[0xe00];
e281682b
SM		 5545};
5546
5547struct mlx5_ifc_query_flow_group_in_bits {
5548 u8 opcode[0x10];
b4ff3a36 5549 u8 reserved_at_10[0x10];
e281682b 5550
b4ff3a36 5551 u8 reserved_at_20[0x10];
e281682b
SM		 5552 u8 op_mod[0x10];
5553
b4ff3a36 5554 u8 reserved_at_40[0x40];
e281682b
SM		 5555
5556 u8 table_type[0x8];
b4ff3a36 5557 u8 reserved_at_88[0x18];
e281682b 5558
b4ff3a36 5559 u8 reserved_at_a0[0x8];
e281682b
SM		 5560 u8 table_id[0x18];
5561
5562 u8 group_id[0x20];
5563
b4ff3a36 5564 u8 reserved_at_e0[0x120];
e281682b
SM		 5565};
5566
9dc0b289
AV		 5567struct mlx5_ifc_query_flow_counter_out_bits {
5568 u8 status[0x8];
5569 u8 reserved_at_8[0x18];
5570
5571 u8 syndrome[0x20];
5572
5573 u8 reserved_at_40[0x40];
5574
b6ca09cb 5575 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
9dc0b289
AV		 5576};
5577
5578struct mlx5_ifc_query_flow_counter_in_bits {
5579 u8 opcode[0x10];
5580 u8 reserved_at_10[0x10];
5581
5582 u8 reserved_at_20[0x10];
5583 u8 op_mod[0x10];
5584
5585 u8 reserved_at_40[0x80];
5586
5587 u8 clear[0x1];
5588 u8 reserved_at_c1[0xf];
5589 u8 num_of_counters[0x10];
5590
a8ffcc74 5591 u8 flow_counter_id[0x20];
9dc0b289
AV		 5592};
5593
d6666753
SM		 5594struct mlx5_ifc_query_esw_vport_context_out_bits {
5595 u8 status[0x8];
b4ff3a36 5596 u8 reserved_at_8[0x18];
d6666753
SM		 5597
5598 u8 syndrome[0x20];
5599
b4ff3a36 5600 u8 reserved_at_40[0x40];
d6666753
SM		 5601
5602 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5603};
5604
5605struct mlx5_ifc_query_esw_vport_context_in_bits {
5606 u8 opcode[0x10];
b4ff3a36 5607 u8 reserved_at_10[0x10];
d6666753 5608
b4ff3a36 5609 u8 reserved_at_20[0x10];
d6666753
SM		 5610 u8 op_mod[0x10];
5611
5612 u8 other_vport[0x1];
b4ff3a36 5613 u8 reserved_at_41[0xf];
d6666753
SM		 5614 u8 vport_number[0x10];
5615
b4ff3a36 5616 u8 reserved_at_60[0x20];
d6666753
SM		 5617};
5618
5619struct mlx5_ifc_modify_esw_vport_context_out_bits {
5620 u8 status[0x8];
b4ff3a36 5621 u8 reserved_at_8[0x18];
d6666753
SM		 5622
5623 u8 syndrome[0x20];
5624
b4ff3a36 5625 u8 reserved_at_40[0x40];
d6666753
SM		 5626};
5627
5628struct mlx5_ifc_esw_vport_context_fields_select_bits {
65c0f2c1
JL		 5629 u8 reserved_at_0[0x1b];
5630 u8 fdb_to_vport_reg_c_id[0x1];
d6666753
SM		 5631 u8 vport_cvlan_insert[0x1];
5632 u8 vport_svlan_insert[0x1];
5633 u8 vport_cvlan_strip[0x1];
5634 u8 vport_svlan_strip[0x1];
5635};
5636
5637struct mlx5_ifc_modify_esw_vport_context_in_bits {
5638 u8 opcode[0x10];
b4ff3a36 5639 u8 reserved_at_10[0x10];
d6666753 5640
b4ff3a36 5641 u8 reserved_at_20[0x10];
d6666753
SM		 5642 u8 op_mod[0x10];
5643
5644 u8 other_vport[0x1];
b4ff3a36 5645 u8 reserved_at_41[0xf];
d6666753
SM		 5646 u8 vport_number[0x10];
5647
5648 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5649
5650 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5651};
5652
e281682b
SM		 5653struct mlx5_ifc_query_eq_out_bits {
5654 u8 status[0x8];
b4ff3a36 5655 u8 reserved_at_8[0x18];
e281682b
SM		 5656
5657 u8 syndrome[0x20];
5658
b4ff3a36 5659 u8 reserved_at_40[0x40];
e281682b
SM		 5660
5661 struct mlx5_ifc_eqc_bits eq_context_entry;
5662
b4ff3a36 5663 u8 reserved_at_280[0x40];
e281682b
SM		 5664
5665 u8 event_bitmask[0x40];
5666
b4ff3a36 5667 u8 reserved_at_300[0x580];
e281682b 5668
b6ca09cb 5669 u8 pas[][0x40];
e281682b
SM		 5670};
5671
5672struct mlx5_ifc_query_eq_in_bits {
5673 u8 opcode[0x10];
b4ff3a36 5674 u8 reserved_at_10[0x10];
e281682b 5675
b4ff3a36 5676 u8 reserved_at_20[0x10];
e281682b
SM		 5677 u8 op_mod[0x10];
5678
b4ff3a36 5679 u8 reserved_at_40[0x18];
e281682b
SM		 5680 u8 eq_number[0x8];
5681
b4ff3a36 5682 u8 reserved_at_60[0x20];
e281682b
SM		 5683};
5684
60786f09 5685struct mlx5_ifc_packet_reformat_context_in_bits {
7adbde20 5686 u8 reserved_at_0[0x5];
60786f09 5687 u8 reformat_type[0x3];
7adbde20 5688 u8 reserved_at_8[0xe];
60786f09 5689 u8 reformat_data_size[0xa];
7adbde20
HHZ		 5690
5691 u8 reserved_at_20[0x10];
60786f09 5692 u8 reformat_data[2][0x8];
7adbde20 5693
b6ca09cb 5694 u8 more_reformat_data[][0x8];
7adbde20
HHZ		 5695};
5696
60786f09 5697struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 5698 u8 status[0x8];
5699 u8 reserved_at_8[0x18];
5700
5701 u8 syndrome[0x20];
5702
5703 u8 reserved_at_40[0xa0];
5704
b6ca09cb 5705 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7adbde20
HHZ		 5706};
5707
60786f09 5708struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 5709 u8 opcode[0x10];
5710 u8 reserved_at_10[0x10];
5711
5712 u8 reserved_at_20[0x10];
5713 u8 op_mod[0x10];
5714
60786f09 5715 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5716
5717 u8 reserved_at_60[0xa0];
5718};
5719
60786f09 5720struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5721 u8 status[0x8];
5722 u8 reserved_at_8[0x18];
5723
5724 u8 syndrome[0x20];
5725
60786f09 5726 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5727
5728 u8 reserved_at_60[0x20];
5729};
5730
97b5484e 5731enum mlx5_reformat_ctx_type {
60786f09
MB		 5732 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5733 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 5734 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5735 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5736 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
e0e7a386
MB		 5737};
5738
60786f09 5739struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5740 u8 opcode[0x10];
5741 u8 reserved_at_10[0x10];
5742
5743 u8 reserved_at_20[0x10];
5744 u8 op_mod[0x10];
5745
5746 u8 reserved_at_40[0xa0];
5747
60786f09 5748 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 5749};
5750
60786f09 5751struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5752 u8 status[0x8];
5753 u8 reserved_at_8[0x18];
5754
5755 u8 syndrome[0x20];
5756
5757 u8 reserved_at_40[0x40];
5758};
5759
60786f09 5760struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5761 u8 opcode[0x10];
5762 u8 reserved_at_10[0x10];
5763
5764 u8 reserved_20[0x10];
5765 u8 op_mod[0x10];
5766
60786f09 5767 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5768
5769 u8 reserved_60[0x20];
5770};
5771
2a69cb9f
OG		 5772struct mlx5_ifc_set_action_in_bits {
5773 u8 action_type[0x4];
5774 u8 field[0xc];
5775 u8 reserved_at_10[0x3];
5776 u8 offset[0x5];
5777 u8 reserved_at_18[0x3];
5778 u8 length[0x5];
5779
5780 u8 data[0x20];
5781};
5782
5783struct mlx5_ifc_add_action_in_bits {
5784 u8 action_type[0x4];
5785 u8 field[0xc];
5786 u8 reserved_at_10[0x10];
5787
5788 u8 data[0x20];
5789};
5790
31d8bde1
HI		 5791struct mlx5_ifc_copy_action_in_bits {
5792 u8 action_type[0x4];
5793 u8 src_field[0xc];
5794 u8 reserved_at_10[0x3];
5795 u8 src_offset[0x5];
5796 u8 reserved_at_18[0x3];
5797 u8 length[0x5];
5798
5799 u8 reserved_at_20[0x4];
5800 u8 dst_field[0xc];
5801 u8 reserved_at_30[0x3];
5802 u8 dst_offset[0x5];
5803 u8 reserved_at_38[0x8];
5804};
5805
d65dbedf
HN		 5806union mlx5_ifc_set_add_copy_action_in_auto_bits {
5807 struct mlx5_ifc_set_action_in_bits set_action_in;
5808 struct mlx5_ifc_add_action_in_bits add_action_in;
822e114b 5809 struct mlx5_ifc_copy_action_in_bits copy_action_in;
2a69cb9f
OG		 5810 u8 reserved_at_0[0x40];
5811};
5812
5813enum {
5814 MLX5_ACTION_TYPE_SET = 0x1,
5815 MLX5_ACTION_TYPE_ADD = 0x2,
31d8bde1 5816 MLX5_ACTION_TYPE_COPY = 0x3,
2a69cb9f
OG		 5817};
5818
5819enum {
5820 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5821 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5822 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5823 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5824 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5825 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5826 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5827 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5828 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5829 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5830 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5831 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5832 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5833 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5834 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5835 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5836 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5837 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5838 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5839 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5840 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5841 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0eb69bb9 5842 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
0c0316f5 5843 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
97b5484e
AV		 5844 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5845 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
65c0f2c1 5846 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
97b5484e
AV		 5847 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5848 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5849 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5850 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5851 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
822e114b
PB		 5852 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5853 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
97b5484e
AV		 5854 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5855 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
78fb6122 5856 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
2a69cb9f
OG		 5857};
5858
5859struct mlx5_ifc_alloc_modify_header_context_out_bits {
5860 u8 status[0x8];
5861 u8 reserved_at_8[0x18];
5862
5863 u8 syndrome[0x20];
5864
5865 u8 modify_header_id[0x20];
5866
5867 u8 reserved_at_60[0x20];
5868};
5869
5870struct mlx5_ifc_alloc_modify_header_context_in_bits {
5871 u8 opcode[0x10];
5872 u8 reserved_at_10[0x10];
5873
5874 u8 reserved_at_20[0x10];
5875 u8 op_mod[0x10];
5876
5877 u8 reserved_at_40[0x20];
5878
5879 u8 table_type[0x8];
5880 u8 reserved_at_68[0x10];
5881 u8 num_of_actions[0x8];
5882
29056207 5883 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
2a69cb9f
OG		 5884};
5885
5886struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5887 u8 status[0x8];
5888 u8 reserved_at_8[0x18];
5889
5890 u8 syndrome[0x20];
5891
5892 u8 reserved_at_40[0x40];
5893};
5894
5895struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5896 u8 opcode[0x10];
5897 u8 reserved_at_10[0x10];
5898
5899 u8 reserved_at_20[0x10];
5900 u8 op_mod[0x10];
5901
5902 u8 modify_header_id[0x20];
5903
5904 u8 reserved_at_60[0x20];
5905};
5906
ab0da5a5
YH		 5907struct mlx5_ifc_query_modify_header_context_in_bits {
5908 u8 opcode[0x10];
5909 u8 uid[0x10];
5910
5911 u8 reserved_at_20[0x10];
5912 u8 op_mod[0x10];
5913
5914 u8 modify_header_id[0x20];
5915
5916 u8 reserved_at_60[0xa0];
5917};
5918
e281682b
SM		 5919struct mlx5_ifc_query_dct_out_bits {
5920 u8 status[0x8];
b4ff3a36 5921 u8 reserved_at_8[0x18];
e281682b
SM		 5922
5923 u8 syndrome[0x20];
5924
b4ff3a36 5925 u8 reserved_at_40[0x40];
e281682b
SM		 5926
5927 struct mlx5_ifc_dctc_bits dct_context_entry;
5928
b4ff3a36 5929 u8 reserved_at_280[0x180];
e281682b
SM		 5930};
5931
5932struct mlx5_ifc_query_dct_in_bits {
5933 u8 opcode[0x10];
b4ff3a36 5934 u8 reserved_at_10[0x10];
e281682b 5935
b4ff3a36 5936 u8 reserved_at_20[0x10];
e281682b
SM		 5937 u8 op_mod[0x10];
5938
b4ff3a36 5939 u8 reserved_at_40[0x8];
e281682b
SM		 5940 u8 dctn[0x18];
5941
b4ff3a36 5942 u8 reserved_at_60[0x20];
e281682b
SM		 5943};
5944
5945struct mlx5_ifc_query_cq_out_bits {
5946 u8 status[0x8];
b4ff3a36 5947 u8 reserved_at_8[0x18];
e281682b
SM		 5948
5949 u8 syndrome[0x20];
5950
b4ff3a36 5951 u8 reserved_at_40[0x40];
e281682b
SM		 5952
5953 struct mlx5_ifc_cqc_bits cq_context;
5954
b4ff3a36 5955 u8 reserved_at_280[0x600];
e281682b 5956
b6ca09cb 5957 u8 pas[][0x40];
e281682b
SM		 5958};
5959
5960struct mlx5_ifc_query_cq_in_bits {
5961 u8 opcode[0x10];
b4ff3a36 5962 u8 reserved_at_10[0x10];
e281682b 5963
b4ff3a36 5964 u8 reserved_at_20[0x10];
e281682b
SM		 5965 u8 op_mod[0x10];
5966
b4ff3a36 5967 u8 reserved_at_40[0x8];
e281682b
SM		 5968 u8 cqn[0x18];
5969
b4ff3a36 5970 u8 reserved_at_60[0x20];
e281682b
SM		 5971};
5972
5973struct mlx5_ifc_query_cong_status_out_bits {
5974 u8 status[0x8];
b4ff3a36 5975 u8 reserved_at_8[0x18];
e281682b
SM		 5976
5977 u8 syndrome[0x20];
5978
b4ff3a36 5979 u8 reserved_at_40[0x20];
e281682b
SM		 5980
5981 u8 enable[0x1];
5982 u8 tag_enable[0x1];
b4ff3a36 5983 u8 reserved_at_62[0x1e];
e281682b
SM		 5984};
5985
5986struct mlx5_ifc_query_cong_status_in_bits {
5987 u8 opcode[0x10];
b4ff3a36 5988 u8 reserved_at_10[0x10];
e281682b 5989
b4ff3a36 5990 u8 reserved_at_20[0x10];
e281682b
SM		 5991 u8 op_mod[0x10];
5992
b4ff3a36 5993 u8 reserved_at_40[0x18];
e281682b
SM		 5994 u8 priority[0x4];
5995 u8 cong_protocol[0x4];
5996
b4ff3a36 5997 u8 reserved_at_60[0x20];
e281682b
SM		 5998};
5999
6000struct mlx5_ifc_query_cong_statistics_out_bits {
6001 u8 status[0x8];
b4ff3a36 6002 u8 reserved_at_8[0x18];
e281682b
SM		 6003
6004 u8 syndrome[0x20];
6005
b4ff3a36 6006 u8 reserved_at_40[0x40];
e281682b 6007
e1f24a79 6008 u8 rp_cur_flows[0x20];
e281682b
SM		 6009
6010 u8 sum_flows[0x20];
6011
e1f24a79 6012 u8 rp_cnp_ignored_high[0x20];
e281682b 6013
e1f24a79 6014 u8 rp_cnp_ignored_low[0x20];
e281682b 6015
e1f24a79 6016 u8 rp_cnp_handled_high[0x20];
e281682b 6017
e1f24a79 6018 u8 rp_cnp_handled_low[0x20];
e281682b 6019
b4ff3a36 6020 u8 reserved_at_140[0x100];
e281682b
SM		 6021
6022 u8 time_stamp_high[0x20];
6023
6024 u8 time_stamp_low[0x20];
6025
6026 u8 accumulators_period[0x20];
6027
e1f24a79 6028 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 6029
e1f24a79 6030 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 6031
e1f24a79 6032 u8 np_cnp_sent_high[0x20];
e281682b 6033
e1f24a79 6034 u8 np_cnp_sent_low[0x20];
e281682b 6035
b4ff3a36 6036 u8 reserved_at_320[0x560];
e281682b
SM		 6037};
6038
6039struct mlx5_ifc_query_cong_statistics_in_bits {
6040 u8 opcode[0x10];
b4ff3a36 6041 u8 reserved_at_10[0x10];
e281682b 6042
b4ff3a36 6043 u8 reserved_at_20[0x10];
e281682b
SM		 6044 u8 op_mod[0x10];
6045
6046 u8 clear[0x1];
b4ff3a36 6047 u8 reserved_at_41[0x1f];
e281682b 6048
b4ff3a36 6049 u8 reserved_at_60[0x20];
e281682b
SM		 6050};
6051
6052struct mlx5_ifc_query_cong_params_out_bits {
6053 u8 status[0x8];
b4ff3a36 6054 u8 reserved_at_8[0x18];
e281682b
SM		 6055
6056 u8 syndrome[0x20];
6057
b4ff3a36 6058 u8 reserved_at_40[0x40];
e281682b
SM		 6059
6060 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6061};
6062
6063struct mlx5_ifc_query_cong_params_in_bits {
6064 u8 opcode[0x10];
b4ff3a36 6065 u8 reserved_at_10[0x10];
e281682b 6066
b4ff3a36 6067 u8 reserved_at_20[0x10];
e281682b
SM		 6068 u8 op_mod[0x10];
6069
b4ff3a36 6070 u8 reserved_at_40[0x1c];
e281682b
SM		 6071 u8 cong_protocol[0x4];
6072
b4ff3a36 6073 u8 reserved_at_60[0x20];
e281682b
SM		 6074};
6075
6076struct mlx5_ifc_query_adapter_out_bits {
6077 u8 status[0x8];
b4ff3a36 6078 u8 reserved_at_8[0x18];
e281682b
SM		 6079
6080 u8 syndrome[0x20];
6081
b4ff3a36 6082 u8 reserved_at_40[0x40];
e281682b
SM		 6083
6084 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6085};
6086
6087struct mlx5_ifc_query_adapter_in_bits {
6088 u8 opcode[0x10];
b4ff3a36 6089 u8 reserved_at_10[0x10];
e281682b 6090
b4ff3a36 6091 u8 reserved_at_20[0x10];
e281682b
SM		 6092 u8 op_mod[0x10];
6093
b4ff3a36 6094 u8 reserved_at_40[0x40];
e281682b
SM		 6095};
6096
6097struct mlx5_ifc_qp_2rst_out_bits {
6098 u8 status[0x8];
b4ff3a36 6099 u8 reserved_at_8[0x18];
e281682b
SM		 6100
6101 u8 syndrome[0x20];
6102
b4ff3a36 6103 u8 reserved_at_40[0x40];
e281682b
SM		 6104};
6105
6106struct mlx5_ifc_qp_2rst_in_bits {
6107 u8 opcode[0x10];
4ac63ec7 6108 u8 uid[0x10];
e281682b 6109
b4ff3a36 6110 u8 reserved_at_20[0x10];
e281682b
SM		 6111 u8 op_mod[0x10];
6112
b4ff3a36 6113 u8 reserved_at_40[0x8];
e281682b
SM		 6114 u8 qpn[0x18];
6115
b4ff3a36 6116 u8 reserved_at_60[0x20];
e281682b
SM		 6117};
6118
6119struct mlx5_ifc_qp_2err_out_bits {
6120 u8 status[0x8];
b4ff3a36 6121 u8 reserved_at_8[0x18];
e281682b
SM		 6122
6123 u8 syndrome[0x20];
6124
b4ff3a36 6125 u8 reserved_at_40[0x40];
e281682b
SM		 6126};
6127
6128struct mlx5_ifc_qp_2err_in_bits {
6129 u8 opcode[0x10];
4ac63ec7 6130 u8 uid[0x10];
e281682b 6131
b4ff3a36 6132 u8 reserved_at_20[0x10];
e281682b
SM		 6133 u8 op_mod[0x10];
6134
b4ff3a36 6135 u8 reserved_at_40[0x8];
e281682b
SM		 6136 u8 qpn[0x18];
6137
b4ff3a36 6138 u8 reserved_at_60[0x20];
e281682b
SM		 6139};
6140
6141struct mlx5_ifc_page_fault_resume_out_bits {
6142 u8 status[0x8];
b4ff3a36 6143 u8 reserved_at_8[0x18];
e281682b
SM		 6144
6145 u8 syndrome[0x20];
6146
b4ff3a36 6147 u8 reserved_at_40[0x40];
e281682b
SM		 6148};
6149
6150struct mlx5_ifc_page_fault_resume_in_bits {
6151 u8 opcode[0x10];
b4ff3a36 6152 u8 reserved_at_10[0x10];
e281682b 6153
b4ff3a36 6154 u8 reserved_at_20[0x10];
e281682b
SM		 6155 u8 op_mod[0x10];
6156
6157 u8 error[0x1];
b4ff3a36 6158 u8 reserved_at_41[0x4];
223cdc72
AK		 6159 u8 page_fault_type[0x3];
6160 u8 wq_number[0x18];
e281682b 6161
223cdc72
AK		 6162 u8 reserved_at_60[0x8];
6163 u8 token[0x18];
e281682b
SM		 6164};
6165
6166struct mlx5_ifc_nop_out_bits {
6167 u8 status[0x8];
b4ff3a36 6168 u8 reserved_at_8[0x18];
e281682b
SM		 6169
6170 u8 syndrome[0x20];
6171
b4ff3a36 6172 u8 reserved_at_40[0x40];
e281682b
SM		 6173};
6174
6175struct mlx5_ifc_nop_in_bits {
6176 u8 opcode[0x10];
b4ff3a36 6177 u8 reserved_at_10[0x10];
e281682b 6178
b4ff3a36 6179 u8 reserved_at_20[0x10];
e281682b
SM		 6180 u8 op_mod[0x10];
6181
b4ff3a36 6182 u8 reserved_at_40[0x40];
e281682b
SM		 6183};
6184
6185struct mlx5_ifc_modify_vport_state_out_bits {
6186 u8 status[0x8];
b4ff3a36 6187 u8 reserved_at_8[0x18];
e281682b
SM		 6188
6189 u8 syndrome[0x20];
6190
b4ff3a36 6191 u8 reserved_at_40[0x40];
e281682b
SM		 6192};
6193
6194struct mlx5_ifc_modify_vport_state_in_bits {
6195 u8 opcode[0x10];
b4ff3a36 6196 u8 reserved_at_10[0x10];
e281682b 6197
b4ff3a36 6198 u8 reserved_at_20[0x10];
e281682b
SM		 6199 u8 op_mod[0x10];
6200
6201 u8 other_vport[0x1];
b4ff3a36 6202 u8 reserved_at_41[0xf];
e281682b
SM		 6203 u8 vport_number[0x10];
6204
b4ff3a36 6205 u8 reserved_at_60[0x18];
e281682b 6206 u8 admin_state[0x4];
b4ff3a36 6207 u8 reserved_at_7c[0x4];
e281682b
SM		 6208};
6209
6210struct mlx5_ifc_modify_tis_out_bits {
6211 u8 status[0x8];
b4ff3a36 6212 u8 reserved_at_8[0x18];
e281682b
SM		 6213
6214 u8 syndrome[0x20];
6215
b4ff3a36 6216 u8 reserved_at_40[0x40];
e281682b
SM		 6217};
6218
75850d0b 6219struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 6220 u8 reserved_at_0[0x20];
75850d0b 6221
84df61eb
AH		 6222 u8 reserved_at_20[0x1d];
6223 u8 lag_tx_port_affinity[0x1];
6224 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 6225 u8 prio[0x1];
6226};
6227
e281682b
SM		 6228struct mlx5_ifc_modify_tis_in_bits {
6229 u8 opcode[0x10];
bd371975 6230 u8 uid[0x10];
e281682b 6231
b4ff3a36 6232 u8 reserved_at_20[0x10];
e281682b
SM		 6233 u8 op_mod[0x10];
6234
b4ff3a36 6235 u8 reserved_at_40[0x8];
e281682b
SM		 6236 u8 tisn[0x18];
6237
b4ff3a36 6238 u8 reserved_at_60[0x20];
e281682b 6239
75850d0b 6240 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 6241
b4ff3a36 6242 u8 reserved_at_c0[0x40];
e281682b
SM		 6243
6244 struct mlx5_ifc_tisc_bits ctx;
6245};
6246
d9eea403 6247struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 6248 u8 reserved_at_0[0x20];
d9eea403 6249
b4ff3a36 6250 u8 reserved_at_20[0x1b];
66189961 6251 u8 self_lb_en[0x1];
bdfc028d
TT		 6252 u8 reserved_at_3c[0x1];
6253 u8 hash[0x1];
6254 u8 reserved_at_3e[0x1];
d9eea403
AS		 6255 u8 lro[0x1];
6256};
6257
e281682b
SM		 6258struct mlx5_ifc_modify_tir_out_bits {
6259 u8 status[0x8];
b4ff3a36 6260 u8 reserved_at_8[0x18];
e281682b
SM		 6261
6262 u8 syndrome[0x20];
6263
b4ff3a36 6264 u8 reserved_at_40[0x40];
e281682b
SM		 6265};
6266
6267struct mlx5_ifc_modify_tir_in_bits {
6268 u8 opcode[0x10];
bd371975 6269 u8 uid[0x10];
e281682b 6270
b4ff3a36 6271 u8 reserved_at_20[0x10];
e281682b
SM		 6272 u8 op_mod[0x10];
6273
b4ff3a36 6274 u8 reserved_at_40[0x8];
e281682b
SM		 6275 u8 tirn[0x18];
6276
b4ff3a36 6277 u8 reserved_at_60[0x20];
e281682b 6278
d9eea403 6279 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 6280
b4ff3a36 6281 u8 reserved_at_c0[0x40];
e281682b
SM		 6282
6283 struct mlx5_ifc_tirc_bits ctx;
6284};
6285
6286struct mlx5_ifc_modify_sq_out_bits {
6287 u8 status[0x8];
b4ff3a36 6288 u8 reserved_at_8[0x18];
e281682b
SM		 6289
6290 u8 syndrome[0x20];
6291
b4ff3a36 6292 u8 reserved_at_40[0x40];
e281682b
SM		 6293};
6294
6295struct mlx5_ifc_modify_sq_in_bits {
6296 u8 opcode[0x10];
430ae0d5 6297 u8 uid[0x10];
e281682b 6298
b4ff3a36 6299 u8 reserved_at_20[0x10];
e281682b
SM		 6300 u8 op_mod[0x10];
6301
6302 u8 sq_state[0x4];
b4ff3a36 6303 u8 reserved_at_44[0x4];
e281682b
SM		 6304 u8 sqn[0x18];
6305
b4ff3a36 6306 u8 reserved_at_60[0x20];
e281682b
SM		 6307
6308 u8 modify_bitmask[0x40];
6309
b4ff3a36 6310 u8 reserved_at_c0[0x40];
e281682b
SM		 6311
6312 struct mlx5_ifc_sqc_bits ctx;
6313};
6314
813f8540
MHY		 6315struct mlx5_ifc_modify_scheduling_element_out_bits {
6316 u8 status[0x8];
6317 u8 reserved_at_8[0x18];
6318
6319 u8 syndrome[0x20];
6320
6321 u8 reserved_at_40[0x1c0];
6322};
6323
6324enum {
6325 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6326 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6327};
6328
6329struct mlx5_ifc_modify_scheduling_element_in_bits {
6330 u8 opcode[0x10];
6331 u8 reserved_at_10[0x10];
6332
6333 u8 reserved_at_20[0x10];
6334 u8 op_mod[0x10];
6335
6336 u8 scheduling_hierarchy[0x8];
6337 u8 reserved_at_48[0x18];
6338
6339 u8 scheduling_element_id[0x20];
6340
6341 u8 reserved_at_80[0x20];
6342
6343 u8 modify_bitmask[0x20];
6344
6345 u8 reserved_at_c0[0x40];
6346
6347 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6348
6349 u8 reserved_at_300[0x100];
6350};
6351
e281682b
SM		 6352struct mlx5_ifc_modify_rqt_out_bits {
6353 u8 status[0x8];
b4ff3a36 6354 u8 reserved_at_8[0x18];
e281682b
SM		 6355
6356 u8 syndrome[0x20];
6357
b4ff3a36 6358 u8 reserved_at_40[0x40];
e281682b
SM		 6359};
6360
5c50368f 6361struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 6362 u8 reserved_at_0[0x20];
5c50368f 6363
b4ff3a36 6364 u8 reserved_at_20[0x1f];
5c50368f
AS		 6365 u8 rqn_list[0x1];
6366};
6367
e281682b
SM		 6368struct mlx5_ifc_modify_rqt_in_bits {
6369 u8 opcode[0x10];
bd371975 6370 u8 uid[0x10];
e281682b 6371
b4ff3a36 6372 u8 reserved_at_20[0x10];
e281682b
SM		 6373 u8 op_mod[0x10];
6374
b4ff3a36 6375 u8 reserved_at_40[0x8];
e281682b
SM		 6376 u8 rqtn[0x18];
6377
b4ff3a36 6378 u8 reserved_at_60[0x20];
e281682b 6379
5c50368f 6380 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 6381
b4ff3a36 6382 u8 reserved_at_c0[0x40];
e281682b
SM		 6383
6384 struct mlx5_ifc_rqtc_bits ctx;
6385};
6386
6387struct mlx5_ifc_modify_rq_out_bits {
6388 u8 status[0x8];
b4ff3a36 6389 u8 reserved_at_8[0x18];
e281682b
SM		 6390
6391 u8 syndrome[0x20];
6392
b4ff3a36 6393 u8 reserved_at_40[0x40];
e281682b
SM		 6394};
6395
83b502a1
AV		 6396enum {
6397 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 6398 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 6399 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 6400};
6401
e281682b
SM		 6402struct mlx5_ifc_modify_rq_in_bits {
6403 u8 opcode[0x10];
d269b3af 6404 u8 uid[0x10];
e281682b 6405
b4ff3a36 6406 u8 reserved_at_20[0x10];
e281682b
SM		 6407 u8 op_mod[0x10];
6408
6409 u8 rq_state[0x4];
b4ff3a36 6410 u8 reserved_at_44[0x4];
e281682b
SM		 6411 u8 rqn[0x18];
6412
b4ff3a36 6413 u8 reserved_at_60[0x20];
e281682b
SM		 6414
6415 u8 modify_bitmask[0x40];
6416
b4ff3a36 6417 u8 reserved_at_c0[0x40];
e281682b
SM		 6418
6419 struct mlx5_ifc_rqc_bits ctx;
6420};
6421
6422struct mlx5_ifc_modify_rmp_out_bits {
6423 u8 status[0x8];
b4ff3a36 6424 u8 reserved_at_8[0x18];
e281682b
SM		 6425
6426 u8 syndrome[0x20];
6427
b4ff3a36 6428 u8 reserved_at_40[0x40];
e281682b
SM		 6429};
6430
01949d01 6431struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 6432 u8 reserved_at_0[0x20];
01949d01 6433
b4ff3a36 6434 u8 reserved_at_20[0x1f];
01949d01
HA		 6435 u8 lwm[0x1];
6436};
6437
e281682b
SM		 6438struct mlx5_ifc_modify_rmp_in_bits {
6439 u8 opcode[0x10];
a0d8c054 6440 u8 uid[0x10];
e281682b 6441
b4ff3a36 6442 u8 reserved_at_20[0x10];
e281682b
SM		 6443 u8 op_mod[0x10];
6444
6445 u8 rmp_state[0x4];
b4ff3a36 6446 u8 reserved_at_44[0x4];
e281682b
SM		 6447 u8 rmpn[0x18];
6448
b4ff3a36 6449 u8 reserved_at_60[0x20];
e281682b 6450
01949d01 6451 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 6452
b4ff3a36 6453 u8 reserved_at_c0[0x40];
e281682b
SM		 6454
6455 struct mlx5_ifc_rmpc_bits ctx;
6456};
6457
6458struct mlx5_ifc_modify_nic_vport_context_out_bits {
6459 u8 status[0x8];
b4ff3a36 6460 u8 reserved_at_8[0x18];
e281682b
SM		 6461
6462 u8 syndrome[0x20];
6463
b4ff3a36 6464 u8 reserved_at_40[0x40];
e281682b
SM		 6465};
6466
6467struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 6468 u8 reserved_at_0[0x12];
6469 u8 affiliation[0x1];
c74d90c1 6470 u8 reserved_at_13[0x1];
bded747b
HN		 6471 u8 disable_uc_local_lb[0x1];
6472 u8 disable_mc_local_lb[0x1];
23898c76
NO		 6473 u8 node_guid[0x1];
6474 u8 port_guid[0x1];
9def7121 6475 u8 min_inline[0x1];
d82b7318
SM		 6476 u8 mtu[0x1];
6477 u8 change_event[0x1];
6478 u8 promisc[0x1];
e281682b
SM		 6479 u8 permanent_address[0x1];
6480 u8 addresses_list[0x1];
6481 u8 roce_en[0x1];
b4ff3a36 6482 u8 reserved_at_1f[0x1];
e281682b
SM		 6483};
6484
6485struct mlx5_ifc_modify_nic_vport_context_in_bits {
6486 u8 opcode[0x10];
b4ff3a36 6487 u8 reserved_at_10[0x10];
e281682b 6488
b4ff3a36 6489 u8 reserved_at_20[0x10];
e281682b
SM		 6490 u8 op_mod[0x10];
6491
6492 u8 other_vport[0x1];
b4ff3a36 6493 u8 reserved_at_41[0xf];
e281682b
SM		 6494 u8 vport_number[0x10];
6495
6496 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6497
b4ff3a36 6498 u8 reserved_at_80[0x780];
e281682b
SM		 6499
6500 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6501};
6502
6503struct mlx5_ifc_modify_hca_vport_context_out_bits {
6504 u8 status[0x8];
b4ff3a36 6505 u8 reserved_at_8[0x18];
e281682b
SM		 6506
6507 u8 syndrome[0x20];
6508
b4ff3a36 6509 u8 reserved_at_40[0x40];
e281682b
SM		 6510};
6511
6512struct mlx5_ifc_modify_hca_vport_context_in_bits {
6513 u8 opcode[0x10];
b4ff3a36 6514 u8 reserved_at_10[0x10];
e281682b 6515
b4ff3a36 6516 u8 reserved_at_20[0x10];
e281682b
SM		 6517 u8 op_mod[0x10];
6518
6519 u8 other_vport[0x1];
b4ff3a36 6520 u8 reserved_at_41[0xb];
707c4602 6521 u8 port_num[0x4];
e281682b
SM		 6522 u8 vport_number[0x10];
6523
b4ff3a36 6524 u8 reserved_at_60[0x20];
e281682b
SM		 6525
6526 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6527};
6528
6529struct mlx5_ifc_modify_cq_out_bits {
6530 u8 status[0x8];
b4ff3a36 6531 u8 reserved_at_8[0x18];
e281682b
SM		 6532
6533 u8 syndrome[0x20];
6534
b4ff3a36 6535 u8 reserved_at_40[0x40];
e281682b
SM		 6536};
6537
6538enum {
6539 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6540 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6541};
6542
6543struct mlx5_ifc_modify_cq_in_bits {
6544 u8 opcode[0x10];
9ba481e2 6545 u8 uid[0x10];
e281682b 6546
b4ff3a36 6547 u8 reserved_at_20[0x10];
e281682b
SM		 6548 u8 op_mod[0x10];
6549
b4ff3a36 6550 u8 reserved_at_40[0x8];
e281682b
SM		 6551 u8 cqn[0x18];
6552
6553 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6554
6555 struct mlx5_ifc_cqc_bits cq_context;
6556
7a32f296 6557 u8 reserved_at_280[0x60];
bd371975
LR		 6558
6559 u8 cq_umem_valid[0x1];
7a32f296
ES		 6560 u8 reserved_at_2e1[0x1f];
6561
6562 u8 reserved_at_300[0x580];
e281682b 6563
b6ca09cb 6564 u8 pas[][0x40];
e281682b
SM		 6565};
6566
6567struct mlx5_ifc_modify_cong_status_out_bits {
6568 u8 status[0x8];
b4ff3a36 6569 u8 reserved_at_8[0x18];
e281682b
SM		 6570
6571 u8 syndrome[0x20];
6572
b4ff3a36 6573 u8 reserved_at_40[0x40];
e281682b
SM		 6574};
6575
6576struct mlx5_ifc_modify_cong_status_in_bits {
6577 u8 opcode[0x10];
b4ff3a36 6578 u8 reserved_at_10[0x10];
e281682b 6579
b4ff3a36 6580 u8 reserved_at_20[0x10];
e281682b
SM		 6581 u8 op_mod[0x10];
6582
b4ff3a36 6583 u8 reserved_at_40[0x18];
e281682b
SM		 6584 u8 priority[0x4];
6585 u8 cong_protocol[0x4];
6586
6587 u8 enable[0x1];
6588 u8 tag_enable[0x1];
b4ff3a36 6589 u8 reserved_at_62[0x1e];
e281682b
SM		 6590};
6591
6592struct mlx5_ifc_modify_cong_params_out_bits {
6593 u8 status[0x8];
b4ff3a36 6594 u8 reserved_at_8[0x18];
e281682b
SM		 6595
6596 u8 syndrome[0x20];
6597
b4ff3a36 6598 u8 reserved_at_40[0x40];
e281682b
SM		 6599};
6600
6601struct mlx5_ifc_modify_cong_params_in_bits {
6602 u8 opcode[0x10];
b4ff3a36 6603 u8 reserved_at_10[0x10];
e281682b 6604
b4ff3a36 6605 u8 reserved_at_20[0x10];
e281682b
SM		 6606 u8 op_mod[0x10];
6607
b4ff3a36 6608 u8 reserved_at_40[0x1c];
e281682b
SM		 6609 u8 cong_protocol[0x4];
6610
6611 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6612
b4ff3a36 6613 u8 reserved_at_80[0x80];
e281682b
SM		 6614
6615 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6616};
6617
6618struct mlx5_ifc_manage_pages_out_bits {
6619 u8 status[0x8];
b4ff3a36 6620 u8 reserved_at_8[0x18];
e281682b
SM		 6621
6622 u8 syndrome[0x20];
6623
6624 u8 output_num_entries[0x20];
6625
b4ff3a36 6626 u8 reserved_at_60[0x20];
e281682b 6627
b6ca09cb 6628 u8 pas[][0x40];
e281682b
SM		 6629};
6630
6631enum {
6632 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6633 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6634 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6635};
6636
6637struct mlx5_ifc_manage_pages_in_bits {
6638 u8 opcode[0x10];
b4ff3a36 6639 u8 reserved_at_10[0x10];
e281682b 6640
b4ff3a36 6641 u8 reserved_at_20[0x10];
e281682b
SM		 6642 u8 op_mod[0x10];
6643
591905ba
BW		 6644 u8 embedded_cpu_function[0x1];
6645 u8 reserved_at_41[0xf];
e281682b
SM		 6646 u8 function_id[0x10];
6647
6648 u8 input_num_entries[0x20];
6649
b6ca09cb 6650 u8 pas[][0x40];
e281682b
SM		 6651};
6652
6653struct mlx5_ifc_mad_ifc_out_bits {
6654 u8 status[0x8];
b4ff3a36 6655 u8 reserved_at_8[0x18];
e281682b
SM		 6656
6657 u8 syndrome[0x20];
6658
b4ff3a36 6659 u8 reserved_at_40[0x40];
e281682b
SM		 6660
6661 u8 response_mad_packet[256][0x8];
6662};
6663
6664struct mlx5_ifc_mad_ifc_in_bits {
6665 u8 opcode[0x10];
b4ff3a36 6666 u8 reserved_at_10[0x10];
e281682b 6667
b4ff3a36 6668 u8 reserved_at_20[0x10];
e281682b
SM		 6669 u8 op_mod[0x10];
6670
6671 u8 remote_lid[0x10];
b4ff3a36 6672 u8 reserved_at_50[0x8];
e281682b
SM		 6673 u8 port[0x8];
6674
b4ff3a36 6675 u8 reserved_at_60[0x20];
e281682b
SM		 6676
6677 u8 mad[256][0x8];
6678};
6679
6680struct mlx5_ifc_init_hca_out_bits {
6681 u8 status[0x8];
b4ff3a36 6682 u8 reserved_at_8[0x18];
e281682b
SM		 6683
6684 u8 syndrome[0x20];
6685
b4ff3a36 6686 u8 reserved_at_40[0x40];
e281682b
SM		 6687};
6688
6689struct mlx5_ifc_init_hca_in_bits {
6690 u8 opcode[0x10];
b4ff3a36 6691 u8 reserved_at_10[0x10];
e281682b 6692
b4ff3a36 6693 u8 reserved_at_20[0x10];
e281682b
SM		 6694 u8 op_mod[0x10];
6695
b4ff3a36 6696 u8 reserved_at_40[0x40];
8737f818 6697 u8 sw_owner_id[4][0x20];
e281682b
SM		 6698};
6699
6700struct mlx5_ifc_init2rtr_qp_out_bits {
6701 u8 status[0x8];
b4ff3a36 6702 u8 reserved_at_8[0x18];
e281682b
SM		 6703
6704 u8 syndrome[0x20];
6705
6b646a7e
LR		 6706 u8 reserved_at_40[0x20];
6707 u8 ece[0x20];
e281682b
SM		 6708};
6709
6710struct mlx5_ifc_init2rtr_qp_in_bits {
6711 u8 opcode[0x10];
4ac63ec7 6712 u8 uid[0x10];
e281682b 6713
b4ff3a36 6714 u8 reserved_at_20[0x10];
e281682b
SM		 6715 u8 op_mod[0x10];
6716
b4ff3a36 6717 u8 reserved_at_40[0x8];
e281682b
SM		 6718 u8 qpn[0x18];
6719
b4ff3a36 6720 u8 reserved_at_60[0x20];
e281682b
SM		 6721
6722 u8 opt_param_mask[0x20];
6723
6b646a7e 6724 u8 ece[0x20];
e281682b
SM		 6725
6726 struct mlx5_ifc_qpc_bits qpc;
6727
b4ff3a36 6728 u8 reserved_at_800[0x80];
e281682b
SM		 6729};
6730
6731struct mlx5_ifc_init2init_qp_out_bits {
6732 u8 status[0x8];
b4ff3a36 6733 u8 reserved_at_8[0x18];
e281682b
SM		 6734
6735 u8 syndrome[0x20];
6736
ab183d46
LR		 6737 u8 reserved_at_40[0x20];
6738 u8 ece[0x20];
e281682b
SM		 6739};
6740
6741struct mlx5_ifc_init2init_qp_in_bits {
6742 u8 opcode[0x10];
4ac63ec7 6743 u8 uid[0x10];
e281682b 6744
b4ff3a36 6745 u8 reserved_at_20[0x10];
e281682b
SM		 6746 u8 op_mod[0x10];
6747
b4ff3a36 6748 u8 reserved_at_40[0x8];
e281682b
SM		 6749 u8 qpn[0x18];
6750
b4ff3a36 6751 u8 reserved_at_60[0x20];
e281682b
SM		 6752
6753 u8 opt_param_mask[0x20];
6754
ab183d46 6755 u8 ece[0x20];
e281682b
SM		 6756
6757 struct mlx5_ifc_qpc_bits qpc;
6758
b4ff3a36 6759 u8 reserved_at_800[0x80];
e281682b
SM		 6760};
6761
6762struct mlx5_ifc_get_dropped_packet_log_out_bits {
6763 u8 status[0x8];
b4ff3a36 6764 u8 reserved_at_8[0x18];
e281682b
SM		 6765
6766 u8 syndrome[0x20];
6767
b4ff3a36 6768 u8 reserved_at_40[0x40];
e281682b
SM		 6769
6770 u8 packet_headers_log[128][0x8];
6771
6772 u8 packet_syndrome[64][0x8];
6773};
6774
6775struct mlx5_ifc_get_dropped_packet_log_in_bits {
6776 u8 opcode[0x10];
b4ff3a36 6777 u8 reserved_at_10[0x10];
e281682b 6778
b4ff3a36 6779 u8 reserved_at_20[0x10];
e281682b
SM		 6780 u8 op_mod[0x10];
6781
b4ff3a36 6782 u8 reserved_at_40[0x40];
e281682b
SM		 6783};
6784
6785struct mlx5_ifc_gen_eqe_in_bits {
6786 u8 opcode[0x10];
b4ff3a36 6787 u8 reserved_at_10[0x10];
e281682b 6788
b4ff3a36 6789 u8 reserved_at_20[0x10];
e281682b
SM		 6790 u8 op_mod[0x10];
6791
b4ff3a36 6792 u8 reserved_at_40[0x18];
e281682b
SM		 6793 u8 eq_number[0x8];
6794
b4ff3a36 6795 u8 reserved_at_60[0x20];
e281682b
SM		 6796
6797 u8 eqe[64][0x8];
6798};
6799
6800struct mlx5_ifc_gen_eq_out_bits {
6801 u8 status[0x8];
b4ff3a36 6802 u8 reserved_at_8[0x18];
e281682b
SM		 6803
6804 u8 syndrome[0x20];
6805
b4ff3a36 6806 u8 reserved_at_40[0x40];
e281682b
SM		 6807};
6808
6809struct mlx5_ifc_enable_hca_out_bits {
6810 u8 status[0x8];
b4ff3a36 6811 u8 reserved_at_8[0x18];
e281682b
SM		 6812
6813 u8 syndrome[0x20];
6814
b4ff3a36 6815 u8 reserved_at_40[0x20];
e281682b
SM		 6816};
6817
6818struct mlx5_ifc_enable_hca_in_bits {
6819 u8 opcode[0x10];
b4ff3a36 6820 u8 reserved_at_10[0x10];
e281682b 6821
b4ff3a36 6822 u8 reserved_at_20[0x10];
e281682b
SM		 6823 u8 op_mod[0x10];
6824
22e939a9
BW		 6825 u8 embedded_cpu_function[0x1];
6826 u8 reserved_at_41[0xf];
e281682b
SM		 6827 u8 function_id[0x10];
6828
b4ff3a36 6829 u8 reserved_at_60[0x20];
e281682b
SM		 6830};
6831
6832struct mlx5_ifc_drain_dct_out_bits {
6833 u8 status[0x8];
b4ff3a36 6834 u8 reserved_at_8[0x18];
e281682b
SM		 6835
6836 u8 syndrome[0x20];
6837
b4ff3a36 6838 u8 reserved_at_40[0x40];
e281682b
SM		 6839};
6840
6841struct mlx5_ifc_drain_dct_in_bits {
6842 u8 opcode[0x10];
774ea6ee 6843 u8 uid[0x10];
e281682b 6844
b4ff3a36 6845 u8 reserved_at_20[0x10];
e281682b
SM		 6846 u8 op_mod[0x10];
6847
b4ff3a36 6848 u8 reserved_at_40[0x8];
e281682b
SM		 6849 u8 dctn[0x18];
6850
b4ff3a36 6851 u8 reserved_at_60[0x20];
e281682b
SM		 6852};
6853
6854struct mlx5_ifc_disable_hca_out_bits {
6855 u8 status[0x8];
b4ff3a36 6856 u8 reserved_at_8[0x18];
e281682b
SM		 6857
6858 u8 syndrome[0x20];
6859
b4ff3a36 6860 u8 reserved_at_40[0x20];
e281682b
SM		 6861};
6862
6863struct mlx5_ifc_disable_hca_in_bits {
6864 u8 opcode[0x10];
b4ff3a36 6865 u8 reserved_at_10[0x10];
e281682b 6866
b4ff3a36 6867 u8 reserved_at_20[0x10];
e281682b
SM		 6868 u8 op_mod[0x10];
6869
22e939a9
BW		 6870 u8 embedded_cpu_function[0x1];
6871 u8 reserved_at_41[0xf];
e281682b
SM		 6872 u8 function_id[0x10];
6873
b4ff3a36 6874 u8 reserved_at_60[0x20];
e281682b
SM		 6875};
6876
6877struct mlx5_ifc_detach_from_mcg_out_bits {
6878 u8 status[0x8];
b4ff3a36 6879 u8 reserved_at_8[0x18];
e281682b
SM		 6880
6881 u8 syndrome[0x20];
6882
b4ff3a36 6883 u8 reserved_at_40[0x40];
e281682b
SM		 6884};
6885
6886struct mlx5_ifc_detach_from_mcg_in_bits {
6887 u8 opcode[0x10];
bd371975 6888 u8 uid[0x10];
e281682b 6889
b4ff3a36 6890 u8 reserved_at_20[0x10];
e281682b
SM		 6891 u8 op_mod[0x10];
6892
b4ff3a36 6893 u8 reserved_at_40[0x8];
e281682b
SM		 6894 u8 qpn[0x18];
6895
b4ff3a36 6896 u8 reserved_at_60[0x20];
e281682b
SM		 6897
6898 u8 multicast_gid[16][0x8];
6899};
6900
7486216b
SM		 6901struct mlx5_ifc_destroy_xrq_out_bits {
6902 u8 status[0x8];
6903 u8 reserved_at_8[0x18];
6904
6905 u8 syndrome[0x20];
6906
6907 u8 reserved_at_40[0x40];
6908};
6909
6910struct mlx5_ifc_destroy_xrq_in_bits {
6911 u8 opcode[0x10];
a0d8c054 6912 u8 uid[0x10];
7486216b
SM		 6913
6914 u8 reserved_at_20[0x10];
6915 u8 op_mod[0x10];
6916
6917 u8 reserved_at_40[0x8];
6918 u8 xrqn[0x18];
6919
6920 u8 reserved_at_60[0x20];
6921};
6922
e281682b
SM		 6923struct mlx5_ifc_destroy_xrc_srq_out_bits {
6924 u8 status[0x8];
b4ff3a36 6925 u8 reserved_at_8[0x18];
e281682b
SM		 6926
6927 u8 syndrome[0x20];
6928
b4ff3a36 6929 u8 reserved_at_40[0x40];
e281682b
SM		 6930};
6931
6932struct mlx5_ifc_destroy_xrc_srq_in_bits {
6933 u8 opcode[0x10];
a0d8c054 6934 u8 uid[0x10];
e281682b 6935
b4ff3a36 6936 u8 reserved_at_20[0x10];
e281682b
SM		 6937 u8 op_mod[0x10];
6938
b4ff3a36 6939 u8 reserved_at_40[0x8];
e281682b
SM		 6940 u8 xrc_srqn[0x18];
6941
b4ff3a36 6942 u8 reserved_at_60[0x20];
e281682b
SM		 6943};
6944
6945struct mlx5_ifc_destroy_tis_out_bits {
6946 u8 status[0x8];
b4ff3a36 6947 u8 reserved_at_8[0x18];
e281682b
SM		 6948
6949 u8 syndrome[0x20];
6950
b4ff3a36 6951 u8 reserved_at_40[0x40];
e281682b
SM		 6952};
6953
6954struct mlx5_ifc_destroy_tis_in_bits {
6955 u8 opcode[0x10];
bd371975 6956 u8 uid[0x10];
e281682b 6957
b4ff3a36 6958 u8 reserved_at_20[0x10];
e281682b
SM		 6959 u8 op_mod[0x10];
6960
b4ff3a36 6961 u8 reserved_at_40[0x8];
e281682b
SM		 6962 u8 tisn[0x18];
6963
b4ff3a36 6964 u8 reserved_at_60[0x20];
e281682b
SM		 6965};
6966
6967struct mlx5_ifc_destroy_tir_out_bits {
6968 u8 status[0x8];
b4ff3a36 6969 u8 reserved_at_8[0x18];
e281682b
SM		 6970
6971 u8 syndrome[0x20];
6972
b4ff3a36 6973 u8 reserved_at_40[0x40];
e281682b
SM		 6974};
6975
6976struct mlx5_ifc_destroy_tir_in_bits {
6977 u8 opcode[0x10];
bd371975 6978 u8 uid[0x10];
e281682b 6979
b4ff3a36 6980 u8 reserved_at_20[0x10];
e281682b
SM		 6981 u8 op_mod[0x10];
6982
b4ff3a36 6983 u8 reserved_at_40[0x8];
e281682b
SM		 6984 u8 tirn[0x18];
6985
b4ff3a36 6986 u8 reserved_at_60[0x20];
e281682b
SM		 6987};
6988
6989struct mlx5_ifc_destroy_srq_out_bits {
6990 u8 status[0x8];
b4ff3a36 6991 u8 reserved_at_8[0x18];
e281682b
SM		 6992
6993 u8 syndrome[0x20];
6994
b4ff3a36 6995 u8 reserved_at_40[0x40];
e281682b
SM		 6996};
6997
6998struct mlx5_ifc_destroy_srq_in_bits {
6999 u8 opcode[0x10];
a0d8c054 7000 u8 uid[0x10];
e281682b 7001
b4ff3a36 7002 u8 reserved_at_20[0x10];
e281682b
SM		 7003 u8 op_mod[0x10];
7004
b4ff3a36 7005 u8 reserved_at_40[0x8];
e281682b
SM		 7006 u8 srqn[0x18];
7007
b4ff3a36 7008 u8 reserved_at_60[0x20];
e281682b
SM		 7009};
7010
7011struct mlx5_ifc_destroy_sq_out_bits {
7012 u8 status[0x8];
b4ff3a36 7013 u8 reserved_at_8[0x18];
e281682b
SM		 7014
7015 u8 syndrome[0x20];
7016
b4ff3a36 7017 u8 reserved_at_40[0x40];
e281682b
SM		 7018};
7019
7020struct mlx5_ifc_destroy_sq_in_bits {
7021 u8 opcode[0x10];
430ae0d5 7022 u8 uid[0x10];
e281682b 7023
b4ff3a36 7024 u8 reserved_at_20[0x10];
e281682b
SM		 7025 u8 op_mod[0x10];
7026
b4ff3a36 7027 u8 reserved_at_40[0x8];
e281682b
SM		 7028 u8 sqn[0x18];
7029
b4ff3a36 7030 u8 reserved_at_60[0x20];
e281682b
SM		 7031};
7032
813f8540
MHY		 7033struct mlx5_ifc_destroy_scheduling_element_out_bits {
7034 u8 status[0x8];
7035 u8 reserved_at_8[0x18];
7036
7037 u8 syndrome[0x20];
7038
7039 u8 reserved_at_40[0x1c0];
7040};
7041
7042struct mlx5_ifc_destroy_scheduling_element_in_bits {
7043 u8 opcode[0x10];
7044 u8 reserved_at_10[0x10];
7045
7046 u8 reserved_at_20[0x10];
7047 u8 op_mod[0x10];
7048
7049 u8 scheduling_hierarchy[0x8];
7050 u8 reserved_at_48[0x18];
7051
7052 u8 scheduling_element_id[0x20];
7053
7054 u8 reserved_at_80[0x180];
7055};
7056
e281682b
SM		 7057struct mlx5_ifc_destroy_rqt_out_bits {
7058 u8 status[0x8];
b4ff3a36 7059 u8 reserved_at_8[0x18];
e281682b
SM		 7060
7061 u8 syndrome[0x20];
7062
b4ff3a36 7063 u8 reserved_at_40[0x40];
e281682b
SM		 7064};
7065
7066struct mlx5_ifc_destroy_rqt_in_bits {
7067 u8 opcode[0x10];
bd371975 7068 u8 uid[0x10];
e281682b 7069
b4ff3a36 7070 u8 reserved_at_20[0x10];
e281682b
SM		 7071 u8 op_mod[0x10];
7072
b4ff3a36 7073 u8 reserved_at_40[0x8];
e281682b
SM		 7074 u8 rqtn[0x18];
7075
b4ff3a36 7076 u8 reserved_at_60[0x20];
e281682b
SM		 7077};
7078
7079struct mlx5_ifc_destroy_rq_out_bits {
7080 u8 status[0x8];
b4ff3a36 7081 u8 reserved_at_8[0x18];
e281682b
SM		 7082
7083 u8 syndrome[0x20];
7084
b4ff3a36 7085 u8 reserved_at_40[0x40];
e281682b
SM		 7086};
7087
7088struct mlx5_ifc_destroy_rq_in_bits {
7089 u8 opcode[0x10];
d269b3af 7090 u8 uid[0x10];
e281682b 7091
b4ff3a36 7092 u8 reserved_at_20[0x10];
e281682b
SM		 7093 u8 op_mod[0x10];
7094
b4ff3a36 7095 u8 reserved_at_40[0x8];
e281682b
SM		 7096 u8 rqn[0x18];
7097
b4ff3a36 7098 u8 reserved_at_60[0x20];
e281682b
SM		 7099};
7100
c1e0bfc1
MG		 7101struct mlx5_ifc_set_delay_drop_params_in_bits {
7102 u8 opcode[0x10];
7103 u8 reserved_at_10[0x10];
7104
7105 u8 reserved_at_20[0x10];
7106 u8 op_mod[0x10];
7107
7108 u8 reserved_at_40[0x20];
7109
7110 u8 reserved_at_60[0x10];
7111 u8 delay_drop_timeout[0x10];
7112};
7113
7114struct mlx5_ifc_set_delay_drop_params_out_bits {
7115 u8 status[0x8];
7116 u8 reserved_at_8[0x18];
7117
7118 u8 syndrome[0x20];
7119
7120 u8 reserved_at_40[0x40];
7121};
7122
e281682b
SM		 7123struct mlx5_ifc_destroy_rmp_out_bits {
7124 u8 status[0x8];
b4ff3a36 7125 u8 reserved_at_8[0x18];
e281682b
SM		 7126
7127 u8 syndrome[0x20];
7128
b4ff3a36 7129 u8 reserved_at_40[0x40];
e281682b
SM		 7130};
7131
7132struct mlx5_ifc_destroy_rmp_in_bits {
7133 u8 opcode[0x10];
a0d8c054 7134 u8 uid[0x10];
e281682b 7135
b4ff3a36 7136 u8 reserved_at_20[0x10];
e281682b
SM		 7137 u8 op_mod[0x10];
7138
b4ff3a36 7139 u8 reserved_at_40[0x8];
e281682b
SM		 7140 u8 rmpn[0x18];
7141
b4ff3a36 7142 u8 reserved_at_60[0x20];
e281682b
SM		 7143};
7144
7145struct mlx5_ifc_destroy_qp_out_bits {
7146 u8 status[0x8];
b4ff3a36 7147 u8 reserved_at_8[0x18];
e281682b
SM		 7148
7149 u8 syndrome[0x20];
7150
b4ff3a36 7151 u8 reserved_at_40[0x40];
e281682b
SM		 7152};
7153
7154struct mlx5_ifc_destroy_qp_in_bits {
7155 u8 opcode[0x10];
4ac63ec7 7156 u8 uid[0x10];
e281682b 7157
b4ff3a36 7158 u8 reserved_at_20[0x10];
e281682b
SM		 7159 u8 op_mod[0x10];
7160
b4ff3a36 7161 u8 reserved_at_40[0x8];
e281682b
SM		 7162 u8 qpn[0x18];
7163
b4ff3a36 7164 u8 reserved_at_60[0x20];
e281682b
SM		 7165};
7166
7167struct mlx5_ifc_destroy_psv_out_bits {
7168 u8 status[0x8];
b4ff3a36 7169 u8 reserved_at_8[0x18];
e281682b
SM		 7170
7171 u8 syndrome[0x20];
7172
b4ff3a36 7173 u8 reserved_at_40[0x40];
e281682b
SM		 7174};
7175
7176struct mlx5_ifc_destroy_psv_in_bits {
7177 u8 opcode[0x10];
b4ff3a36 7178 u8 reserved_at_10[0x10];
e281682b 7179
b4ff3a36 7180 u8 reserved_at_20[0x10];
e281682b
SM		 7181 u8 op_mod[0x10];
7182
b4ff3a36 7183 u8 reserved_at_40[0x8];
e281682b
SM		 7184 u8 psvn[0x18];
7185
b4ff3a36 7186 u8 reserved_at_60[0x20];
e281682b
SM		 7187};
7188
7189struct mlx5_ifc_destroy_mkey_out_bits {
7190 u8 status[0x8];
b4ff3a36 7191 u8 reserved_at_8[0x18];
e281682b
SM		 7192
7193 u8 syndrome[0x20];
7194
b4ff3a36 7195 u8 reserved_at_40[0x40];
e281682b
SM		 7196};
7197
7198struct mlx5_ifc_destroy_mkey_in_bits {
7199 u8 opcode[0x10];
8a06a79b 7200 u8 uid[0x10];
e281682b 7201
b4ff3a36 7202 u8 reserved_at_20[0x10];
e281682b
SM		 7203 u8 op_mod[0x10];
7204
b4ff3a36 7205 u8 reserved_at_40[0x8];
e281682b
SM		 7206 u8 mkey_index[0x18];
7207
b4ff3a36 7208 u8 reserved_at_60[0x20];
e281682b
SM		 7209};
7210
7211struct mlx5_ifc_destroy_flow_table_out_bits {
7212 u8 status[0x8];
b4ff3a36 7213 u8 reserved_at_8[0x18];
e281682b
SM		 7214
7215 u8 syndrome[0x20];
7216
b4ff3a36 7217 u8 reserved_at_40[0x40];
e281682b
SM		 7218};
7219
7220struct mlx5_ifc_destroy_flow_table_in_bits {
7221 u8 opcode[0x10];
b4ff3a36 7222 u8 reserved_at_10[0x10];
e281682b 7223
b4ff3a36 7224 u8 reserved_at_20[0x10];
e281682b
SM		 7225 u8 op_mod[0x10];
7226
7d5e1423
SM		 7227 u8 other_vport[0x1];
7228 u8 reserved_at_41[0xf];
7229 u8 vport_number[0x10];
7230
7231 u8 reserved_at_60[0x20];
e281682b
SM		 7232
7233 u8 table_type[0x8];
b4ff3a36 7234 u8 reserved_at_88[0x18];
e281682b 7235
b4ff3a36 7236 u8 reserved_at_a0[0x8];
e281682b
SM		 7237 u8 table_id[0x18];
7238
b4ff3a36 7239 u8 reserved_at_c0[0x140];
e281682b
SM		 7240};
7241
7242struct mlx5_ifc_destroy_flow_group_out_bits {
7243 u8 status[0x8];
b4ff3a36 7244 u8 reserved_at_8[0x18];
e281682b
SM		 7245
7246 u8 syndrome[0x20];
7247
b4ff3a36 7248 u8 reserved_at_40[0x40];
e281682b
SM		 7249};
7250
7251struct mlx5_ifc_destroy_flow_group_in_bits {
7252 u8 opcode[0x10];
b4ff3a36 7253 u8 reserved_at_10[0x10];
e281682b 7254
b4ff3a36 7255 u8 reserved_at_20[0x10];
e281682b
SM		 7256 u8 op_mod[0x10];
7257
7d5e1423
SM		 7258 u8 other_vport[0x1];
7259 u8 reserved_at_41[0xf];
7260 u8 vport_number[0x10];
7261
7262 u8 reserved_at_60[0x20];
e281682b
SM		 7263
7264 u8 table_type[0x8];
b4ff3a36 7265 u8 reserved_at_88[0x18];
e281682b 7266
b4ff3a36 7267 u8 reserved_at_a0[0x8];
e281682b
SM		 7268 u8 table_id[0x18];
7269
7270 u8 group_id[0x20];
7271
b4ff3a36 7272 u8 reserved_at_e0[0x120];
e281682b
SM		 7273};
7274
7275struct mlx5_ifc_destroy_eq_out_bits {
7276 u8 status[0x8];
b4ff3a36 7277 u8 reserved_at_8[0x18];
e281682b
SM		 7278
7279 u8 syndrome[0x20];
7280
b4ff3a36 7281 u8 reserved_at_40[0x40];
e281682b
SM		 7282};
7283
7284struct mlx5_ifc_destroy_eq_in_bits {
7285 u8 opcode[0x10];
b4ff3a36 7286 u8 reserved_at_10[0x10];
e281682b 7287
b4ff3a36 7288 u8 reserved_at_20[0x10];
e281682b
SM		 7289 u8 op_mod[0x10];
7290
b4ff3a36 7291 u8 reserved_at_40[0x18];
e281682b
SM		 7292 u8 eq_number[0x8];
7293
b4ff3a36 7294 u8 reserved_at_60[0x20];
e281682b
SM		 7295};
7296
7297struct mlx5_ifc_destroy_dct_out_bits {
7298 u8 status[0x8];
b4ff3a36 7299 u8 reserved_at_8[0x18];
e281682b
SM		 7300
7301 u8 syndrome[0x20];
7302
b4ff3a36 7303 u8 reserved_at_40[0x40];
e281682b
SM		 7304};
7305
7306struct mlx5_ifc_destroy_dct_in_bits {
7307 u8 opcode[0x10];
774ea6ee 7308 u8 uid[0x10];
e281682b 7309
b4ff3a36 7310 u8 reserved_at_20[0x10];
e281682b
SM		 7311 u8 op_mod[0x10];
7312
b4ff3a36 7313 u8 reserved_at_40[0x8];
e281682b
SM		 7314 u8 dctn[0x18];
7315
b4ff3a36 7316 u8 reserved_at_60[0x20];
e281682b
SM		 7317};
7318
7319struct mlx5_ifc_destroy_cq_out_bits {
7320 u8 status[0x8];
b4ff3a36 7321 u8 reserved_at_8[0x18];
e281682b
SM		 7322
7323 u8 syndrome[0x20];
7324
b4ff3a36 7325 u8 reserved_at_40[0x40];
e281682b
SM		 7326};
7327
7328struct mlx5_ifc_destroy_cq_in_bits {
7329 u8 opcode[0x10];
9ba481e2 7330 u8 uid[0x10];
e281682b 7331
b4ff3a36 7332 u8 reserved_at_20[0x10];
e281682b
SM		 7333 u8 op_mod[0x10];
7334
b4ff3a36 7335 u8 reserved_at_40[0x8];
e281682b
SM		 7336 u8 cqn[0x18];
7337
b4ff3a36 7338 u8 reserved_at_60[0x20];
e281682b
SM		 7339};
7340
7341struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7342 u8 status[0x8];
b4ff3a36 7343 u8 reserved_at_8[0x18];
e281682b
SM		 7344
7345 u8 syndrome[0x20];
7346
b4ff3a36 7347 u8 reserved_at_40[0x40];
e281682b
SM		 7348};
7349
7350struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7351 u8 opcode[0x10];
b4ff3a36 7352 u8 reserved_at_10[0x10];
e281682b 7353
b4ff3a36 7354 u8 reserved_at_20[0x10];
e281682b
SM		 7355 u8 op_mod[0x10];
7356
b4ff3a36 7357 u8 reserved_at_40[0x20];
e281682b 7358
b4ff3a36 7359 u8 reserved_at_60[0x10];
e281682b
SM		 7360 u8 vxlan_udp_port[0x10];
7361};
7362
7363struct mlx5_ifc_delete_l2_table_entry_out_bits {
7364 u8 status[0x8];
b4ff3a36 7365 u8 reserved_at_8[0x18];
e281682b
SM		 7366
7367 u8 syndrome[0x20];
7368
b4ff3a36 7369 u8 reserved_at_40[0x40];
e281682b
SM		 7370};
7371
7372struct mlx5_ifc_delete_l2_table_entry_in_bits {
7373 u8 opcode[0x10];
b4ff3a36 7374 u8 reserved_at_10[0x10];
e281682b 7375
b4ff3a36 7376 u8 reserved_at_20[0x10];
e281682b
SM		 7377 u8 op_mod[0x10];
7378
b4ff3a36 7379 u8 reserved_at_40[0x60];
e281682b 7380
b4ff3a36 7381 u8 reserved_at_a0[0x8];
e281682b
SM		 7382 u8 table_index[0x18];
7383
b4ff3a36 7384 u8 reserved_at_c0[0x140];
e281682b
SM		 7385};
7386
7387struct mlx5_ifc_delete_fte_out_bits {
7388 u8 status[0x8];
b4ff3a36 7389 u8 reserved_at_8[0x18];
e281682b
SM		 7390
7391 u8 syndrome[0x20];
7392
b4ff3a36 7393 u8 reserved_at_40[0x40];
e281682b
SM		 7394};
7395
7396struct mlx5_ifc_delete_fte_in_bits {
7397 u8 opcode[0x10];
b4ff3a36 7398 u8 reserved_at_10[0x10];
e281682b 7399
b4ff3a36 7400 u8 reserved_at_20[0x10];
e281682b
SM		 7401 u8 op_mod[0x10];
7402
7d5e1423
SM		 7403 u8 other_vport[0x1];
7404 u8 reserved_at_41[0xf];
7405 u8 vport_number[0x10];
7406
7407 u8 reserved_at_60[0x20];
e281682b
SM		 7408
7409 u8 table_type[0x8];
b4ff3a36 7410 u8 reserved_at_88[0x18];
e281682b 7411
b4ff3a36 7412 u8 reserved_at_a0[0x8];
e281682b
SM		 7413 u8 table_id[0x18];
7414
b4ff3a36 7415 u8 reserved_at_c0[0x40];
e281682b
SM		 7416
7417 u8 flow_index[0x20];
7418
b4ff3a36 7419 u8 reserved_at_120[0xe0];
e281682b
SM		 7420};
7421
7422struct mlx5_ifc_dealloc_xrcd_out_bits {
7423 u8 status[0x8];
b4ff3a36 7424 u8 reserved_at_8[0x18];
e281682b
SM		 7425
7426 u8 syndrome[0x20];
7427
b4ff3a36 7428 u8 reserved_at_40[0x40];
e281682b
SM		 7429};
7430
7431struct mlx5_ifc_dealloc_xrcd_in_bits {
7432 u8 opcode[0x10];
bd371975 7433 u8 uid[0x10];
e281682b 7434
b4ff3a36 7435 u8 reserved_at_20[0x10];
e281682b
SM		 7436 u8 op_mod[0x10];
7437
b4ff3a36 7438 u8 reserved_at_40[0x8];
e281682b
SM		 7439 u8 xrcd[0x18];
7440
b4ff3a36 7441 u8 reserved_at_60[0x20];
e281682b
SM		 7442};
7443
7444struct mlx5_ifc_dealloc_uar_out_bits {
7445 u8 status[0x8];
b4ff3a36 7446 u8 reserved_at_8[0x18];
e281682b
SM		 7447
7448 u8 syndrome[0x20];
7449
b4ff3a36 7450 u8 reserved_at_40[0x40];
e281682b
SM		 7451};
7452
7453struct mlx5_ifc_dealloc_uar_in_bits {
7454 u8 opcode[0x10];
b4ff3a36 7455 u8 reserved_at_10[0x10];
e281682b 7456
b4ff3a36 7457 u8 reserved_at_20[0x10];
e281682b
SM		 7458 u8 op_mod[0x10];
7459
b4ff3a36 7460 u8 reserved_at_40[0x8];
e281682b
SM		 7461 u8 uar[0x18];
7462
b4ff3a36 7463 u8 reserved_at_60[0x20];
e281682b
SM		 7464};
7465
7466struct mlx5_ifc_dealloc_transport_domain_out_bits {
7467 u8 status[0x8];
b4ff3a36 7468 u8 reserved_at_8[0x18];
e281682b
SM		 7469
7470 u8 syndrome[0x20];
7471
b4ff3a36 7472 u8 reserved_at_40[0x40];
e281682b
SM		 7473};
7474
7475struct mlx5_ifc_dealloc_transport_domain_in_bits {
7476 u8 opcode[0x10];
71bef2fd 7477 u8 uid[0x10];
e281682b 7478
b4ff3a36 7479 u8 reserved_at_20[0x10];
e281682b
SM		 7480 u8 op_mod[0x10];
7481
b4ff3a36 7482 u8 reserved_at_40[0x8];
e281682b
SM		 7483 u8 transport_domain[0x18];
7484
b4ff3a36 7485 u8 reserved_at_60[0x20];
e281682b
SM		 7486};
7487
7488struct mlx5_ifc_dealloc_q_counter_out_bits {
7489 u8 status[0x8];
b4ff3a36 7490 u8 reserved_at_8[0x18];
e281682b
SM		 7491
7492 u8 syndrome[0x20];
7493
b4ff3a36 7494 u8 reserved_at_40[0x40];
e281682b
SM		 7495};
7496
7497struct mlx5_ifc_dealloc_q_counter_in_bits {
7498 u8 opcode[0x10];
b4ff3a36 7499 u8 reserved_at_10[0x10];
e281682b 7500
b4ff3a36 7501 u8 reserved_at_20[0x10];
e281682b
SM		 7502 u8 op_mod[0x10];
7503
b4ff3a36 7504 u8 reserved_at_40[0x18];
e281682b
SM		 7505 u8 counter_set_id[0x8];
7506
b4ff3a36 7507 u8 reserved_at_60[0x20];
e281682b
SM		 7508};
7509
7510struct mlx5_ifc_dealloc_pd_out_bits {
7511 u8 status[0x8];
b4ff3a36 7512 u8 reserved_at_8[0x18];
e281682b
SM		 7513
7514 u8 syndrome[0x20];
7515
b4ff3a36 7516 u8 reserved_at_40[0x40];
e281682b
SM		 7517};
7518
7519struct mlx5_ifc_dealloc_pd_in_bits {
7520 u8 opcode[0x10];
bd371975 7521 u8 uid[0x10];
e281682b 7522
b4ff3a36 7523 u8 reserved_at_20[0x10];
e281682b
SM		 7524 u8 op_mod[0x10];
7525
b4ff3a36 7526 u8 reserved_at_40[0x8];
e281682b
SM		 7527 u8 pd[0x18];
7528
b4ff3a36 7529 u8 reserved_at_60[0x20];
e281682b
SM		 7530};
7531
9dc0b289
AV		 7532struct mlx5_ifc_dealloc_flow_counter_out_bits {
7533 u8 status[0x8];
7534 u8 reserved_at_8[0x18];
7535
7536 u8 syndrome[0x20];
7537
7538 u8 reserved_at_40[0x40];
7539};
7540
7541struct mlx5_ifc_dealloc_flow_counter_in_bits {
7542 u8 opcode[0x10];
7543 u8 reserved_at_10[0x10];
7544
7545 u8 reserved_at_20[0x10];
7546 u8 op_mod[0x10];
7547
a8ffcc74 7548 u8 flow_counter_id[0x20];
9dc0b289
AV		 7549
7550 u8 reserved_at_60[0x20];
7551};
7552
7486216b
SM		 7553struct mlx5_ifc_create_xrq_out_bits {
7554 u8 status[0x8];
7555 u8 reserved_at_8[0x18];
7556
7557 u8 syndrome[0x20];
7558
7559 u8 reserved_at_40[0x8];
7560 u8 xrqn[0x18];
7561
7562 u8 reserved_at_60[0x20];
7563};
7564
7565struct mlx5_ifc_create_xrq_in_bits {
7566 u8 opcode[0x10];
a0d8c054 7567 u8 uid[0x10];
7486216b
SM		 7568
7569 u8 reserved_at_20[0x10];
7570 u8 op_mod[0x10];
7571
7572 u8 reserved_at_40[0x40];
7573
7574 struct mlx5_ifc_xrqc_bits xrq_context;
7575};
7576
e281682b
SM		 7577struct mlx5_ifc_create_xrc_srq_out_bits {
7578 u8 status[0x8];
b4ff3a36 7579 u8 reserved_at_8[0x18];
e281682b
SM		 7580
7581 u8 syndrome[0x20];
7582
b4ff3a36 7583 u8 reserved_at_40[0x8];
e281682b
SM		 7584 u8 xrc_srqn[0x18];
7585
b4ff3a36 7586 u8 reserved_at_60[0x20];
e281682b
SM		 7587};
7588
7589struct mlx5_ifc_create_xrc_srq_in_bits {
7590 u8 opcode[0x10];
a0d8c054 7591 u8 uid[0x10];
e281682b 7592
b4ff3a36 7593 u8 reserved_at_20[0x10];
e281682b
SM		 7594 u8 op_mod[0x10];
7595
b4ff3a36 7596 u8 reserved_at_40[0x40];
e281682b
SM		 7597
7598 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7599
99b77fef
YH		 7600 u8 reserved_at_280[0x60];
7601
bd371975 7602 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 7603 u8 reserved_at_2e1[0x1f];
7604
7605 u8 reserved_at_300[0x580];
e281682b 7606
b6ca09cb 7607 u8 pas[][0x40];
e281682b
SM		 7608};
7609
7610struct mlx5_ifc_create_tis_out_bits {
7611 u8 status[0x8];
b4ff3a36 7612 u8 reserved_at_8[0x18];
e281682b
SM		 7613
7614 u8 syndrome[0x20];
7615
b4ff3a36 7616 u8 reserved_at_40[0x8];
e281682b
SM		 7617 u8 tisn[0x18];
7618
b4ff3a36 7619 u8 reserved_at_60[0x20];
e281682b
SM		 7620};
7621
7622struct mlx5_ifc_create_tis_in_bits {
7623 u8 opcode[0x10];
bd371975 7624 u8 uid[0x10];
e281682b 7625
b4ff3a36 7626 u8 reserved_at_20[0x10];
e281682b
SM		 7627 u8 op_mod[0x10];
7628
b4ff3a36 7629 u8 reserved_at_40[0xc0];
e281682b
SM		 7630
7631 struct mlx5_ifc_tisc_bits ctx;
7632};
7633
7634struct mlx5_ifc_create_tir_out_bits {
7635 u8 status[0x8];
3e070470 7636 u8 icm_address_63_40[0x18];
e281682b
SM		 7637
7638 u8 syndrome[0x20];
7639
3e070470 7640 u8 icm_address_39_32[0x8];
e281682b
SM		 7641 u8 tirn[0x18];
7642
3e070470 7643 u8 icm_address_31_0[0x20];
e281682b
SM		 7644};
7645
7646struct mlx5_ifc_create_tir_in_bits {
7647 u8 opcode[0x10];
bd371975 7648 u8 uid[0x10];
e281682b 7649
b4ff3a36 7650 u8 reserved_at_20[0x10];
e281682b
SM		 7651 u8 op_mod[0x10];
7652
b4ff3a36 7653 u8 reserved_at_40[0xc0];
e281682b
SM		 7654
7655 struct mlx5_ifc_tirc_bits ctx;
7656};
7657
7658struct mlx5_ifc_create_srq_out_bits {
7659 u8 status[0x8];
b4ff3a36 7660 u8 reserved_at_8[0x18];
e281682b
SM		 7661
7662 u8 syndrome[0x20];
7663
b4ff3a36 7664 u8 reserved_at_40[0x8];
e281682b
SM		 7665 u8 srqn[0x18];
7666
b4ff3a36 7667 u8 reserved_at_60[0x20];
e281682b
SM		 7668};
7669
7670struct mlx5_ifc_create_srq_in_bits {
7671 u8 opcode[0x10];
a0d8c054 7672 u8 uid[0x10];
e281682b 7673
b4ff3a36 7674 u8 reserved_at_20[0x10];
e281682b
SM		 7675 u8 op_mod[0x10];
7676
b4ff3a36 7677 u8 reserved_at_40[0x40];
e281682b
SM		 7678
7679 struct mlx5_ifc_srqc_bits srq_context_entry;
7680
b4ff3a36 7681 u8 reserved_at_280[0x600];
e281682b 7682
b6ca09cb 7683 u8 pas[][0x40];
e281682b
SM		 7684};
7685
7686struct mlx5_ifc_create_sq_out_bits {
7687 u8 status[0x8];
b4ff3a36 7688 u8 reserved_at_8[0x18];
e281682b
SM		 7689
7690 u8 syndrome[0x20];
7691
b4ff3a36 7692 u8 reserved_at_40[0x8];
e281682b
SM		 7693 u8 sqn[0x18];
7694
b4ff3a36 7695 u8 reserved_at_60[0x20];
e281682b
SM		 7696};
7697
7698struct mlx5_ifc_create_sq_in_bits {
7699 u8 opcode[0x10];
430ae0d5 7700 u8 uid[0x10];
e281682b 7701
b4ff3a36 7702 u8 reserved_at_20[0x10];
e281682b
SM		 7703 u8 op_mod[0x10];
7704
b4ff3a36 7705 u8 reserved_at_40[0xc0];
e281682b
SM		 7706
7707 struct mlx5_ifc_sqc_bits ctx;
7708};
7709
813f8540
MHY		 7710struct mlx5_ifc_create_scheduling_element_out_bits {
7711 u8 status[0x8];
7712 u8 reserved_at_8[0x18];
7713
7714 u8 syndrome[0x20];
7715
7716 u8 reserved_at_40[0x40];
7717
7718 u8 scheduling_element_id[0x20];
7719
7720 u8 reserved_at_a0[0x160];
7721};
7722
7723struct mlx5_ifc_create_scheduling_element_in_bits {
7724 u8 opcode[0x10];
7725 u8 reserved_at_10[0x10];
7726
7727 u8 reserved_at_20[0x10];
7728 u8 op_mod[0x10];
7729
7730 u8 scheduling_hierarchy[0x8];
7731 u8 reserved_at_48[0x18];
7732
7733 u8 reserved_at_60[0xa0];
7734
7735 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7736
7737 u8 reserved_at_300[0x100];
7738};
7739
e281682b
SM		 7740struct mlx5_ifc_create_rqt_out_bits {
7741 u8 status[0x8];
b4ff3a36 7742 u8 reserved_at_8[0x18];
e281682b
SM		 7743
7744 u8 syndrome[0x20];
7745
b4ff3a36 7746 u8 reserved_at_40[0x8];
e281682b
SM		 7747 u8 rqtn[0x18];
7748
b4ff3a36 7749 u8 reserved_at_60[0x20];
e281682b
SM		 7750};
7751
7752struct mlx5_ifc_create_rqt_in_bits {
7753 u8 opcode[0x10];
bd371975 7754 u8 uid[0x10];
e281682b 7755
b4ff3a36 7756 u8 reserved_at_20[0x10];
e281682b
SM		 7757 u8 op_mod[0x10];
7758
b4ff3a36 7759 u8 reserved_at_40[0xc0];
e281682b
SM		 7760
7761 struct mlx5_ifc_rqtc_bits rqt_context;
7762};
7763
7764struct mlx5_ifc_create_rq_out_bits {
7765 u8 status[0x8];
b4ff3a36 7766 u8 reserved_at_8[0x18];
e281682b
SM		 7767
7768 u8 syndrome[0x20];
7769
b4ff3a36 7770 u8 reserved_at_40[0x8];
e281682b
SM		 7771 u8 rqn[0x18];
7772
b4ff3a36 7773 u8 reserved_at_60[0x20];
e281682b
SM		 7774};
7775
7776struct mlx5_ifc_create_rq_in_bits {
7777 u8 opcode[0x10];
d269b3af 7778 u8 uid[0x10];
e281682b 7779
b4ff3a36 7780 u8 reserved_at_20[0x10];
e281682b
SM		 7781 u8 op_mod[0x10];
7782
b4ff3a36 7783 u8 reserved_at_40[0xc0];
e281682b
SM		 7784
7785 struct mlx5_ifc_rqc_bits ctx;
7786};
7787
7788struct mlx5_ifc_create_rmp_out_bits {
7789 u8 status[0x8];
b4ff3a36 7790 u8 reserved_at_8[0x18];
e281682b
SM		 7791
7792 u8 syndrome[0x20];
7793
b4ff3a36 7794 u8 reserved_at_40[0x8];
e281682b
SM		 7795 u8 rmpn[0x18];
7796
b4ff3a36 7797 u8 reserved_at_60[0x20];
e281682b
SM		 7798};
7799
7800struct mlx5_ifc_create_rmp_in_bits {
7801 u8 opcode[0x10];
a0d8c054 7802 u8 uid[0x10];
e281682b 7803
b4ff3a36 7804 u8 reserved_at_20[0x10];
e281682b
SM		 7805 u8 op_mod[0x10];
7806
b4ff3a36 7807 u8 reserved_at_40[0xc0];
e281682b
SM		 7808
7809 struct mlx5_ifc_rmpc_bits ctx;
7810};
7811
7812struct mlx5_ifc_create_qp_out_bits {
7813 u8 status[0x8];
b4ff3a36 7814 u8 reserved_at_8[0x18];
e281682b
SM		 7815
7816 u8 syndrome[0x20];
7817
b4ff3a36 7818 u8 reserved_at_40[0x8];
e281682b
SM		 7819 u8 qpn[0x18];
7820
6b646a7e 7821 u8 ece[0x20];
e281682b
SM		 7822};
7823
7824struct mlx5_ifc_create_qp_in_bits {
7825 u8 opcode[0x10];
4ac63ec7 7826 u8 uid[0x10];
e281682b 7827
b4ff3a36 7828 u8 reserved_at_20[0x10];
e281682b
SM		 7829 u8 op_mod[0x10];
7830
4dca6509
MG		 7831 u8 reserved_at_40[0x8];
7832 u8 input_qpn[0x18];
e281682b 7833
4dca6509 7834 u8 reserved_at_60[0x20];
e281682b
SM		 7835 u8 opt_param_mask[0x20];
7836
6b646a7e 7837 u8 ece[0x20];
e281682b
SM		 7838
7839 struct mlx5_ifc_qpc_bits qpc;
7840
bd371975
LR		 7841 u8 reserved_at_800[0x60];
7842
7843 u8 wq_umem_valid[0x1];
7844 u8 reserved_at_861[0x1f];
e281682b 7845
b6ca09cb 7846 u8 pas[][0x40];
e281682b
SM		 7847};
7848
7849struct mlx5_ifc_create_psv_out_bits {
7850 u8 status[0x8];
b4ff3a36 7851 u8 reserved_at_8[0x18];
e281682b
SM		 7852
7853 u8 syndrome[0x20];
7854
b4ff3a36 7855 u8 reserved_at_40[0x40];
e281682b 7856
b4ff3a36 7857 u8 reserved_at_80[0x8];
e281682b
SM		 7858 u8 psv0_index[0x18];
7859
b4ff3a36 7860 u8 reserved_at_a0[0x8];
e281682b
SM		 7861 u8 psv1_index[0x18];
7862
b4ff3a36 7863 u8 reserved_at_c0[0x8];
e281682b
SM		 7864 u8 psv2_index[0x18];
7865
b4ff3a36 7866 u8 reserved_at_e0[0x8];
e281682b
SM		 7867 u8 psv3_index[0x18];
7868};
7869
7870struct mlx5_ifc_create_psv_in_bits {
7871 u8 opcode[0x10];
b4ff3a36 7872 u8 reserved_at_10[0x10];
e281682b 7873
b4ff3a36 7874 u8 reserved_at_20[0x10];
e281682b
SM		 7875 u8 op_mod[0x10];
7876
7877 u8 num_psv[0x4];
b4ff3a36 7878 u8 reserved_at_44[0x4];
e281682b
SM		 7879 u8 pd[0x18];
7880
b4ff3a36 7881 u8 reserved_at_60[0x20];
e281682b
SM		 7882};
7883
7884struct mlx5_ifc_create_mkey_out_bits {
7885 u8 status[0x8];
b4ff3a36 7886 u8 reserved_at_8[0x18];
e281682b
SM		 7887
7888 u8 syndrome[0x20];
7889
b4ff3a36 7890 u8 reserved_at_40[0x8];
e281682b
SM		 7891 u8 mkey_index[0x18];
7892
b4ff3a36 7893 u8 reserved_at_60[0x20];
e281682b
SM		 7894};
7895
7896struct mlx5_ifc_create_mkey_in_bits {
7897 u8 opcode[0x10];
8a06a79b 7898 u8 uid[0x10];
e281682b 7899
b4ff3a36 7900 u8 reserved_at_20[0x10];
e281682b
SM		 7901 u8 op_mod[0x10];
7902
b4ff3a36 7903 u8 reserved_at_40[0x20];
e281682b
SM		 7904
7905 u8 pg_access[0x1];
bd371975
LR		 7906 u8 mkey_umem_valid[0x1];
7907 u8 reserved_at_62[0x1e];
e281682b
SM		 7908
7909 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7910
b4ff3a36 7911 u8 reserved_at_280[0x80];
e281682b
SM		 7912
7913 u8 translations_octword_actual_size[0x20];
7914
b4ff3a36 7915 u8 reserved_at_320[0x560];
e281682b 7916
b6ca09cb 7917 u8 klm_pas_mtt[][0x20];
e281682b
SM		 7918};
7919
97b5484e
AV		 7920enum {
7921 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7922 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7923 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7924 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7925 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7926 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7927 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7928};
7929
e281682b
SM		 7930struct mlx5_ifc_create_flow_table_out_bits {
7931 u8 status[0x8];
97b5484e 7932 u8 icm_address_63_40[0x18];
e281682b
SM		 7933
7934 u8 syndrome[0x20];
7935
97b5484e 7936 u8 icm_address_39_32[0x8];
e281682b
SM		 7937 u8 table_id[0x18];
7938
97b5484e 7939 u8 icm_address_31_0[0x20];
0c90e9c6
MG		 7940};
7941
e281682b
SM		 7942struct mlx5_ifc_create_flow_table_in_bits {
7943 u8 opcode[0x10];
b4ff3a36 7944 u8 reserved_at_10[0x10];
e281682b 7945
b4ff3a36 7946 u8 reserved_at_20[0x10];
e281682b
SM		 7947 u8 op_mod[0x10];
7948
7d5e1423
SM		 7949 u8 other_vport[0x1];
7950 u8 reserved_at_41[0xf];
7951 u8 vport_number[0x10];
7952
7953 u8 reserved_at_60[0x20];
e281682b
SM		 7954
7955 u8 table_type[0x8];
b4ff3a36 7956 u8 reserved_at_88[0x18];
e281682b 7957
b4ff3a36 7958 u8 reserved_at_a0[0x20];
e281682b 7959
0c90e9c6 7960 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 7961};
7962
7963struct mlx5_ifc_create_flow_group_out_bits {
7964 u8 status[0x8];
b4ff3a36 7965 u8 reserved_at_8[0x18];
e281682b
SM		 7966
7967 u8 syndrome[0x20];
7968
b4ff3a36 7969 u8 reserved_at_40[0x8];
e281682b
SM		 7970 u8 group_id[0x18];
7971
b4ff3a36 7972 u8 reserved_at_60[0x20];
e281682b
SM		 7973};
7974
7975enum {
71c6e863
AL		 7976 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7977 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7978 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7979 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 7980};
7981
7982struct mlx5_ifc_create_flow_group_in_bits {
7983 u8 opcode[0x10];
b4ff3a36 7984 u8 reserved_at_10[0x10];
e281682b 7985
b4ff3a36 7986 u8 reserved_at_20[0x10];
e281682b
SM		 7987 u8 op_mod[0x10];
7988
7d5e1423
SM		 7989 u8 other_vport[0x1];
7990 u8 reserved_at_41[0xf];
7991 u8 vport_number[0x10];
7992
7993 u8 reserved_at_60[0x20];
e281682b
SM		 7994
7995 u8 table_type[0x8];
b4ff3a36 7996 u8 reserved_at_88[0x18];
e281682b 7997
b4ff3a36 7998 u8 reserved_at_a0[0x8];
e281682b
SM		 7999 u8 table_id[0x18];
8000
3e99df87
SK		 8001 u8 source_eswitch_owner_vhca_id_valid[0x1];
8002
8003 u8 reserved_at_c1[0x1f];
e281682b
SM		 8004
8005 u8 start_flow_index[0x20];
8006
b4ff3a36 8007 u8 reserved_at_100[0x20];
e281682b
SM		 8008
8009 u8 end_flow_index[0x20];
8010
b4ff3a36 8011 u8 reserved_at_140[0xa0];
e281682b 8012
b4ff3a36 8013 u8 reserved_at_1e0[0x18];
e281682b
SM		 8014 u8 match_criteria_enable[0x8];
8015
8016 struct mlx5_ifc_fte_match_param_bits match_criteria;
8017
b4ff3a36 8018 u8 reserved_at_1200[0xe00];
e281682b
SM		 8019};
8020
8021struct mlx5_ifc_create_eq_out_bits {
8022 u8 status[0x8];
b4ff3a36 8023 u8 reserved_at_8[0x18];
e281682b
SM		 8024
8025 u8 syndrome[0x20];
8026
b4ff3a36 8027 u8 reserved_at_40[0x18];
e281682b
SM		 8028 u8 eq_number[0x8];
8029
b4ff3a36 8030 u8 reserved_at_60[0x20];
e281682b
SM		 8031};
8032
8033struct mlx5_ifc_create_eq_in_bits {
8034 u8 opcode[0x10];
c191f934 8035 u8 uid[0x10];
e281682b 8036
b4ff3a36 8037 u8 reserved_at_20[0x10];
e281682b
SM		 8038 u8 op_mod[0x10];
8039
b4ff3a36 8040 u8 reserved_at_40[0x40];
e281682b
SM		 8041
8042 struct mlx5_ifc_eqc_bits eq_context_entry;
8043
b4ff3a36 8044 u8 reserved_at_280[0x40];
e281682b 8045
b9a7ba55 8046 u8 event_bitmask[4][0x40];
e281682b 8047
b9a7ba55 8048 u8 reserved_at_3c0[0x4c0];
e281682b 8049
b6ca09cb 8050 u8 pas[][0x40];
e281682b
SM		 8051};
8052
8053struct mlx5_ifc_create_dct_out_bits {
8054 u8 status[0x8];
b4ff3a36 8055 u8 reserved_at_8[0x18];
e281682b
SM		 8056
8057 u8 syndrome[0x20];
8058
b4ff3a36 8059 u8 reserved_at_40[0x8];
e281682b
SM		 8060 u8 dctn[0x18];
8061
a645a89d 8062 u8 ece[0x20];
e281682b
SM		 8063};
8064
8065struct mlx5_ifc_create_dct_in_bits {
8066 u8 opcode[0x10];
774ea6ee 8067 u8 uid[0x10];
e281682b 8068
b4ff3a36 8069 u8 reserved_at_20[0x10];
e281682b
SM		 8070 u8 op_mod[0x10];
8071
b4ff3a36 8072 u8 reserved_at_40[0x40];
e281682b
SM		 8073
8074 struct mlx5_ifc_dctc_bits dct_context_entry;
8075
b4ff3a36 8076 u8 reserved_at_280[0x180];
e281682b
SM		 8077};
8078
8079struct mlx5_ifc_create_cq_out_bits {
8080 u8 status[0x8];
b4ff3a36 8081 u8 reserved_at_8[0x18];
e281682b
SM		 8082
8083 u8 syndrome[0x20];
8084
b4ff3a36 8085 u8 reserved_at_40[0x8];
e281682b
SM		 8086 u8 cqn[0x18];
8087
b4ff3a36 8088 u8 reserved_at_60[0x20];
e281682b
SM		 8089};
8090
8091struct mlx5_ifc_create_cq_in_bits {
8092 u8 opcode[0x10];
9ba481e2 8093 u8 uid[0x10];
e281682b 8094
b4ff3a36 8095 u8 reserved_at_20[0x10];
e281682b
SM		 8096 u8 op_mod[0x10];
8097
b4ff3a36 8098 u8 reserved_at_40[0x40];
e281682b
SM		 8099
8100 struct mlx5_ifc_cqc_bits cq_context;
8101
bd371975
LR		 8102 u8 reserved_at_280[0x60];
8103
8104 u8 cq_umem_valid[0x1];
8105 u8 reserved_at_2e1[0x59f];
e281682b 8106
b6ca09cb 8107 u8 pas[][0x40];
e281682b
SM		 8108};
8109
8110struct mlx5_ifc_config_int_moderation_out_bits {
8111 u8 status[0x8];
b4ff3a36 8112 u8 reserved_at_8[0x18];
e281682b
SM		 8113
8114 u8 syndrome[0x20];
8115
b4ff3a36 8116 u8 reserved_at_40[0x4];
e281682b
SM		 8117 u8 min_delay[0xc];
8118 u8 int_vector[0x10];
8119
b4ff3a36 8120 u8 reserved_at_60[0x20];
e281682b
SM		 8121};
8122
8123enum {
8124 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8125 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8126};
8127
8128struct mlx5_ifc_config_int_moderation_in_bits {
8129 u8 opcode[0x10];
b4ff3a36 8130 u8 reserved_at_10[0x10];
e281682b 8131
b4ff3a36 8132 u8 reserved_at_20[0x10];
e281682b
SM		 8133 u8 op_mod[0x10];
8134
b4ff3a36 8135 u8 reserved_at_40[0x4];
e281682b
SM		 8136 u8 min_delay[0xc];
8137 u8 int_vector[0x10];
8138
b4ff3a36 8139 u8 reserved_at_60[0x20];
e281682b
SM		 8140};
8141
8142struct mlx5_ifc_attach_to_mcg_out_bits {
8143 u8 status[0x8];
b4ff3a36 8144 u8 reserved_at_8[0x18];
e281682b
SM		 8145
8146 u8 syndrome[0x20];
8147
b4ff3a36 8148 u8 reserved_at_40[0x40];
e281682b
SM		 8149};
8150
8151struct mlx5_ifc_attach_to_mcg_in_bits {
8152 u8 opcode[0x10];
bd371975 8153 u8 uid[0x10];
e281682b 8154
b4ff3a36 8155 u8 reserved_at_20[0x10];
e281682b
SM		 8156 u8 op_mod[0x10];
8157
b4ff3a36 8158 u8 reserved_at_40[0x8];
e281682b
SM		 8159 u8 qpn[0x18];
8160
b4ff3a36 8161 u8 reserved_at_60[0x20];
e281682b
SM		 8162
8163 u8 multicast_gid[16][0x8];
8164};
8165
7486216b
SM		 8166struct mlx5_ifc_arm_xrq_out_bits {
8167 u8 status[0x8];
8168 u8 reserved_at_8[0x18];
8169
8170 u8 syndrome[0x20];
8171
8172 u8 reserved_at_40[0x40];
8173};
8174
8175struct mlx5_ifc_arm_xrq_in_bits {
8176 u8 opcode[0x10];
8177 u8 reserved_at_10[0x10];
8178
8179 u8 reserved_at_20[0x10];
8180 u8 op_mod[0x10];
8181
8182 u8 reserved_at_40[0x8];
8183 u8 xrqn[0x18];
8184
8185 u8 reserved_at_60[0x10];
8186 u8 lwm[0x10];
8187};
8188
e281682b
SM		 8189struct mlx5_ifc_arm_xrc_srq_out_bits {
8190 u8 status[0x8];
b4ff3a36 8191 u8 reserved_at_8[0x18];
e281682b
SM		 8192
8193 u8 syndrome[0x20];
8194
b4ff3a36 8195 u8 reserved_at_40[0x40];
e281682b
SM		 8196};
8197
8198enum {
8199 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8200};
8201
8202struct mlx5_ifc_arm_xrc_srq_in_bits {
8203 u8 opcode[0x10];
a0d8c054 8204 u8 uid[0x10];
e281682b 8205
b4ff3a36 8206 u8 reserved_at_20[0x10];
e281682b
SM		 8207 u8 op_mod[0x10];
8208
b4ff3a36 8209 u8 reserved_at_40[0x8];
e281682b
SM		 8210 u8 xrc_srqn[0x18];
8211
b4ff3a36 8212 u8 reserved_at_60[0x10];
e281682b
SM		 8213 u8 lwm[0x10];
8214};
8215
8216struct mlx5_ifc_arm_rq_out_bits {
8217 u8 status[0x8];
b4ff3a36 8218 u8 reserved_at_8[0x18];
e281682b
SM		 8219
8220 u8 syndrome[0x20];
8221
b4ff3a36 8222 u8 reserved_at_40[0x40];
e281682b
SM		 8223};
8224
8225enum {
7486216b
SM		 8226 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8227 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 8228};
8229
8230struct mlx5_ifc_arm_rq_in_bits {
8231 u8 opcode[0x10];
a0d8c054 8232 u8 uid[0x10];
e281682b 8233
b4ff3a36 8234 u8 reserved_at_20[0x10];
e281682b
SM		 8235 u8 op_mod[0x10];
8236
b4ff3a36 8237 u8 reserved_at_40[0x8];
e281682b
SM		 8238 u8 srq_number[0x18];
8239
b4ff3a36 8240 u8 reserved_at_60[0x10];
e281682b
SM		 8241 u8 lwm[0x10];
8242};
8243
8244struct mlx5_ifc_arm_dct_out_bits {
8245 u8 status[0x8];
b4ff3a36 8246 u8 reserved_at_8[0x18];
e281682b
SM		 8247
8248 u8 syndrome[0x20];
8249
b4ff3a36 8250 u8 reserved_at_40[0x40];
e281682b
SM		 8251};
8252
8253struct mlx5_ifc_arm_dct_in_bits {
8254 u8 opcode[0x10];
b4ff3a36 8255 u8 reserved_at_10[0x10];
e281682b 8256
b4ff3a36 8257 u8 reserved_at_20[0x10];
e281682b
SM		 8258 u8 op_mod[0x10];
8259
b4ff3a36 8260 u8 reserved_at_40[0x8];
e281682b
SM		 8261 u8 dct_number[0x18];
8262
b4ff3a36 8263 u8 reserved_at_60[0x20];
e281682b
SM		 8264};
8265
8266struct mlx5_ifc_alloc_xrcd_out_bits {
8267 u8 status[0x8];
b4ff3a36 8268 u8 reserved_at_8[0x18];
e281682b
SM		 8269
8270 u8 syndrome[0x20];
8271
b4ff3a36 8272 u8 reserved_at_40[0x8];
e281682b
SM		 8273 u8 xrcd[0x18];
8274
b4ff3a36 8275 u8 reserved_at_60[0x20];
e281682b
SM		 8276};
8277
8278struct mlx5_ifc_alloc_xrcd_in_bits {
8279 u8 opcode[0x10];
bd371975 8280 u8 uid[0x10];
e281682b 8281
b4ff3a36 8282 u8 reserved_at_20[0x10];
e281682b
SM		 8283 u8 op_mod[0x10];
8284
b4ff3a36 8285 u8 reserved_at_40[0x40];
e281682b
SM		 8286};
8287
8288struct mlx5_ifc_alloc_uar_out_bits {
8289 u8 status[0x8];
b4ff3a36 8290 u8 reserved_at_8[0x18];
e281682b
SM		 8291
8292 u8 syndrome[0x20];
8293
b4ff3a36 8294 u8 reserved_at_40[0x8];
e281682b
SM		 8295 u8 uar[0x18];
8296
b4ff3a36 8297 u8 reserved_at_60[0x20];
e281682b
SM		 8298};
8299
8300struct mlx5_ifc_alloc_uar_in_bits {
8301 u8 opcode[0x10];
b4ff3a36 8302 u8 reserved_at_10[0x10];
e281682b 8303
b4ff3a36 8304 u8 reserved_at_20[0x10];
e281682b
SM		 8305 u8 op_mod[0x10];
8306
b4ff3a36 8307 u8 reserved_at_40[0x40];
e281682b
SM		 8308};
8309
8310struct mlx5_ifc_alloc_transport_domain_out_bits {
8311 u8 status[0x8];
b4ff3a36 8312 u8 reserved_at_8[0x18];
e281682b
SM		 8313
8314 u8 syndrome[0x20];
8315
b4ff3a36 8316 u8 reserved_at_40[0x8];
e281682b
SM		 8317 u8 transport_domain[0x18];
8318
b4ff3a36 8319 u8 reserved_at_60[0x20];
e281682b
SM		 8320};
8321
8322struct mlx5_ifc_alloc_transport_domain_in_bits {
8323 u8 opcode[0x10];
71bef2fd 8324 u8 uid[0x10];
e281682b 8325
b4ff3a36 8326 u8 reserved_at_20[0x10];
e281682b
SM		 8327 u8 op_mod[0x10];
8328
b4ff3a36 8329 u8 reserved_at_40[0x40];
e281682b
SM		 8330};
8331
8332struct mlx5_ifc_alloc_q_counter_out_bits {
8333 u8 status[0x8];
b4ff3a36 8334 u8 reserved_at_8[0x18];
e281682b
SM		 8335
8336 u8 syndrome[0x20];
8337
b4ff3a36 8338 u8 reserved_at_40[0x18];
e281682b
SM		 8339 u8 counter_set_id[0x8];
8340
b4ff3a36 8341 u8 reserved_at_60[0x20];
e281682b
SM		 8342};
8343
8344struct mlx5_ifc_alloc_q_counter_in_bits {
8345 u8 opcode[0x10];
2acc7957 8346 u8 uid[0x10];
e281682b 8347
b4ff3a36 8348 u8 reserved_at_20[0x10];
e281682b
SM		 8349 u8 op_mod[0x10];
8350
b4ff3a36 8351 u8 reserved_at_40[0x40];
e281682b
SM		 8352};
8353
8354struct mlx5_ifc_alloc_pd_out_bits {
8355 u8 status[0x8];
b4ff3a36 8356 u8 reserved_at_8[0x18];
e281682b
SM		 8357
8358 u8 syndrome[0x20];
8359
b4ff3a36 8360 u8 reserved_at_40[0x8];
e281682b
SM		 8361 u8 pd[0x18];
8362
b4ff3a36 8363 u8 reserved_at_60[0x20];
e281682b
SM		 8364};
8365
8366struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 8367 u8 opcode[0x10];
bd371975 8368 u8 uid[0x10];
9dc0b289
AV		 8369
8370 u8 reserved_at_20[0x10];
8371 u8 op_mod[0x10];
8372
8373 u8 reserved_at_40[0x40];
8374};
8375
8376struct mlx5_ifc_alloc_flow_counter_out_bits {
8377 u8 status[0x8];
8378 u8 reserved_at_8[0x18];
8379
8380 u8 syndrome[0x20];
8381
a8ffcc74 8382 u8 flow_counter_id[0x20];
9dc0b289
AV		 8383
8384 u8 reserved_at_60[0x20];
8385};
8386
8387struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 8388 u8 opcode[0x10];
b4ff3a36 8389 u8 reserved_at_10[0x10];
e281682b 8390
b4ff3a36 8391 u8 reserved_at_20[0x10];
e281682b
SM		 8392 u8 op_mod[0x10];
8393
8536a6bf
GT		 8394 u8 reserved_at_40[0x38];
8395 u8 flow_counter_bulk[0x8];
e281682b
SM		 8396};
8397
8398struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8399 u8 status[0x8];
b4ff3a36 8400 u8 reserved_at_8[0x18];
e281682b
SM		 8401
8402 u8 syndrome[0x20];
8403
b4ff3a36 8404 u8 reserved_at_40[0x40];
e281682b
SM		 8405};
8406
8407struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8408 u8 opcode[0x10];
b4ff3a36 8409 u8 reserved_at_10[0x10];
e281682b 8410
b4ff3a36 8411 u8 reserved_at_20[0x10];
e281682b
SM		 8412 u8 op_mod[0x10];
8413
b4ff3a36 8414 u8 reserved_at_40[0x20];
e281682b 8415
b4ff3a36 8416 u8 reserved_at_60[0x10];
e281682b
SM		 8417 u8 vxlan_udp_port[0x10];
8418};
8419
37e92a9d 8420struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 8421 u8 status[0x8];
8422 u8 reserved_at_8[0x18];
8423
8424 u8 syndrome[0x20];
8425
8426 u8 reserved_at_40[0x40];
8427};
8428
1326034b
YH		 8429struct mlx5_ifc_set_pp_rate_limit_context_bits {
8430 u8 rate_limit[0x20];
8431
8432 u8 burst_upper_bound[0x20];
8433
8434 u8 reserved_at_40[0x10];
8435 u8 typical_packet_size[0x10];
8436
8437 u8 reserved_at_60[0x120];
8438};
8439
37e92a9d 8440struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b 8441 u8 opcode[0x10];
1326034b 8442 u8 uid[0x10];
7486216b
SM		 8443
8444 u8 reserved_at_20[0x10];
8445 u8 op_mod[0x10];
8446
8447 u8 reserved_at_40[0x10];
8448 u8 rate_limit_index[0x10];
8449
8450 u8 reserved_at_60[0x20];
8451
1326034b 8452 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
7486216b
SM		 8453};
8454
e281682b
SM		 8455struct mlx5_ifc_access_register_out_bits {
8456 u8 status[0x8];
b4ff3a36 8457 u8 reserved_at_8[0x18];
e281682b
SM		 8458
8459 u8 syndrome[0x20];
8460
b4ff3a36 8461 u8 reserved_at_40[0x40];
e281682b 8462
b6ca09cb 8463 u8 register_data[][0x20];
e281682b
SM		 8464};
8465
8466enum {
8467 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8468 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8469};
8470
8471struct mlx5_ifc_access_register_in_bits {
8472 u8 opcode[0x10];
b4ff3a36 8473 u8 reserved_at_10[0x10];
e281682b 8474
b4ff3a36 8475 u8 reserved_at_20[0x10];
e281682b
SM		 8476 u8 op_mod[0x10];
8477
b4ff3a36 8478 u8 reserved_at_40[0x10];
e281682b
SM		 8479 u8 register_id[0x10];
8480
8481 u8 argument[0x20];
8482
b6ca09cb 8483 u8 register_data[][0x20];
e281682b
SM		 8484};
8485
8486struct mlx5_ifc_sltp_reg_bits {
8487 u8 status[0x4];
8488 u8 version[0x4];
8489 u8 local_port[0x8];
8490 u8 pnat[0x2];
b4ff3a36 8491 u8 reserved_at_12[0x2];
e281682b 8492 u8 lane[0x4];
b4ff3a36 8493 u8 reserved_at_18[0x8];
e281682b 8494
b4ff3a36 8495 u8 reserved_at_20[0x20];
e281682b 8496
b4ff3a36 8497 u8 reserved_at_40[0x7];
e281682b
SM		 8498 u8 polarity[0x1];
8499 u8 ob_tap0[0x8];
8500 u8 ob_tap1[0x8];
8501 u8 ob_tap2[0x8];
8502
b4ff3a36 8503 u8 reserved_at_60[0xc];
e281682b
SM		 8504 u8 ob_preemp_mode[0x4];
8505 u8 ob_reg[0x8];
8506 u8 ob_bias[0x8];
8507
b4ff3a36 8508 u8 reserved_at_80[0x20];
e281682b
SM		 8509};
8510
8511struct mlx5_ifc_slrg_reg_bits {
8512 u8 status[0x4];
8513 u8 version[0x4];
8514 u8 local_port[0x8];
8515 u8 pnat[0x2];
b4ff3a36 8516 u8 reserved_at_12[0x2];
e281682b 8517 u8 lane[0x4];
b4ff3a36 8518 u8 reserved_at_18[0x8];
e281682b
SM		 8519
8520 u8 time_to_link_up[0x10];
b4ff3a36 8521 u8 reserved_at_30[0xc];
e281682b
SM		 8522 u8 grade_lane_speed[0x4];
8523
8524 u8 grade_version[0x8];
8525 u8 grade[0x18];
8526
b4ff3a36 8527 u8 reserved_at_60[0x4];
e281682b
SM		 8528 u8 height_grade_type[0x4];
8529 u8 height_grade[0x18];
8530
8531 u8 height_dz[0x10];
8532 u8 height_dv[0x10];
8533
b4ff3a36 8534 u8 reserved_at_a0[0x10];
e281682b
SM		 8535 u8 height_sigma[0x10];
8536
b4ff3a36 8537 u8 reserved_at_c0[0x20];
e281682b 8538
b4ff3a36 8539 u8 reserved_at_e0[0x4];
e281682b
SM		 8540 u8 phase_grade_type[0x4];
8541 u8 phase_grade[0x18];
8542
b4ff3a36 8543 u8 reserved_at_100[0x8];
e281682b 8544 u8 phase_eo_pos[0x8];
b4ff3a36 8545 u8 reserved_at_110[0x8];
e281682b
SM		 8546 u8 phase_eo_neg[0x8];
8547
8548 u8 ffe_set_tested[0x10];
8549 u8 test_errors_per_lane[0x10];
8550};
8551
8552struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 8553 u8 reserved_at_0[0x8];
e281682b 8554 u8 local_port[0x8];
b4ff3a36 8555 u8 reserved_at_10[0x10];
e281682b 8556
b4ff3a36 8557 u8 reserved_at_20[0x1c];
e281682b
SM		 8558 u8 vl_hw_cap[0x4];
8559
b4ff3a36 8560 u8 reserved_at_40[0x1c];
e281682b
SM		 8561 u8 vl_admin[0x4];
8562
b4ff3a36 8563 u8 reserved_at_60[0x1c];
e281682b
SM		 8564 u8 vl_operational[0x4];
8565};
8566
8567struct mlx5_ifc_pude_reg_bits {
8568 u8 swid[0x8];
8569 u8 local_port[0x8];
b4ff3a36 8570 u8 reserved_at_10[0x4];
e281682b 8571 u8 admin_status[0x4];
b4ff3a36 8572 u8 reserved_at_18[0x4];
e281682b
SM		 8573 u8 oper_status[0x4];
8574
b4ff3a36 8575 u8 reserved_at_20[0x60];
e281682b
SM		 8576};
8577
8578struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 8579 u8 reserved_at_0[0x1];
7486216b 8580 u8 an_disable_admin[0x1];
e7e31ca4
BW		 8581 u8 an_disable_cap[0x1];
8582 u8 reserved_at_3[0x5];
e281682b 8583 u8 local_port[0x8];
b4ff3a36 8584 u8 reserved_at_10[0xd];
e281682b
SM		 8585 u8 proto_mask[0x3];
8586
7486216b 8587 u8 an_status[0x4];
dc392fc5
MB		 8588 u8 reserved_at_24[0xc];
8589 u8 data_rate_oper[0x10];
a0a89989
AL		 8590
8591 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 8592
8593 u8 eth_proto_capability[0x20];
8594
8595 u8 ib_link_width_capability[0x10];
8596 u8 ib_proto_capability[0x10];
8597
a0a89989 8598 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 8599
8600 u8 eth_proto_admin[0x20];
8601
8602 u8 ib_link_width_admin[0x10];
8603 u8 ib_proto_admin[0x10];
8604
a0a89989 8605 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 8606
8607 u8 eth_proto_oper[0x20];
8608
8609 u8 ib_link_width_oper[0x10];
8610 u8 ib_proto_oper[0x10];
8611
5b4793f8
EBE		 8612 u8 reserved_at_160[0x1c];
8613 u8 connector_type[0x4];
e281682b
SM		 8614
8615 u8 eth_proto_lp_advertise[0x20];
8616
b4ff3a36 8617 u8 reserved_at_1a0[0x60];
e281682b
SM		 8618};
8619
7d5e1423
SM		 8620struct mlx5_ifc_mlcr_reg_bits {
8621 u8 reserved_at_0[0x8];
8622 u8 local_port[0x8];
8623 u8 reserved_at_10[0x20];
8624
8625 u8 beacon_duration[0x10];
8626 u8 reserved_at_40[0x10];
8627
8628 u8 beacon_remain[0x10];
8629};
8630
e281682b 8631struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 8632 u8 reserved_at_0[0x20];
e281682b
SM		 8633
8634 u8 algorithm_options[0x10];
b4ff3a36 8635 u8 reserved_at_30[0x4];
e281682b
SM		 8636 u8 repetitions_mode[0x4];
8637 u8 num_of_repetitions[0x8];
8638
8639 u8 grade_version[0x8];
8640 u8 height_grade_type[0x4];
8641 u8 phase_grade_type[0x4];
8642 u8 height_grade_weight[0x8];
8643 u8 phase_grade_weight[0x8];
8644
8645 u8 gisim_measure_bits[0x10];
8646 u8 adaptive_tap_measure_bits[0x10];
8647
8648 u8 ber_bath_high_error_threshold[0x10];
8649 u8 ber_bath_mid_error_threshold[0x10];
8650
8651 u8 ber_bath_low_error_threshold[0x10];
8652 u8 one_ratio_high_threshold[0x10];
8653
8654 u8 one_ratio_high_mid_threshold[0x10];
8655 u8 one_ratio_low_mid_threshold[0x10];
8656
8657 u8 one_ratio_low_threshold[0x10];
8658 u8 ndeo_error_threshold[0x10];
8659
8660 u8 mixer_offset_step_size[0x10];
b4ff3a36 8661 u8 reserved_at_110[0x8];
e281682b
SM		 8662 u8 mix90_phase_for_voltage_bath[0x8];
8663
8664 u8 mixer_offset_start[0x10];
8665 u8 mixer_offset_end[0x10];
8666
b4ff3a36 8667 u8 reserved_at_140[0x15];
e281682b
SM		 8668 u8 ber_test_time[0xb];
8669};
8670
8671struct mlx5_ifc_pspa_reg_bits {
8672 u8 swid[0x8];
8673 u8 local_port[0x8];
8674 u8 sub_port[0x8];
b4ff3a36 8675 u8 reserved_at_18[0x8];
e281682b 8676
b4ff3a36 8677 u8 reserved_at_20[0x20];
e281682b
SM		 8678};
8679
8680struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 8681 u8 reserved_at_0[0x8];
e281682b 8682 u8 local_port[0x8];
b4ff3a36 8683 u8 reserved_at_10[0x5];
e281682b 8684 u8 prio[0x3];
b4ff3a36 8685 u8 reserved_at_18[0x6];
e281682b
SM		 8686 u8 mode[0x2];
8687
b4ff3a36 8688 u8 reserved_at_20[0x20];
e281682b 8689
b4ff3a36 8690 u8 reserved_at_40[0x10];
e281682b
SM		 8691 u8 min_threshold[0x10];
8692
b4ff3a36 8693 u8 reserved_at_60[0x10];
e281682b
SM		 8694 u8 max_threshold[0x10];
8695
b4ff3a36 8696 u8 reserved_at_80[0x10];
e281682b
SM		 8697 u8 mark_probability_denominator[0x10];
8698
b4ff3a36 8699 u8 reserved_at_a0[0x60];
e281682b
SM		 8700};
8701
8702struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 8703 u8 reserved_at_0[0x8];
e281682b 8704 u8 local_port[0x8];
b4ff3a36 8705 u8 reserved_at_10[0x10];
e281682b 8706
b4ff3a36 8707 u8 reserved_at_20[0x60];
e281682b 8708
b4ff3a36 8709 u8 reserved_at_80[0x1c];
e281682b
SM		 8710 u8 wrps_admin[0x4];
8711
b4ff3a36 8712 u8 reserved_at_a0[0x1c];
e281682b
SM		 8713 u8 wrps_status[0x4];
8714
b4ff3a36 8715 u8 reserved_at_c0[0x8];
e281682b 8716 u8 up_threshold[0x8];
b4ff3a36 8717 u8 reserved_at_d0[0x8];
e281682b
SM		 8718 u8 down_threshold[0x8];
8719
b4ff3a36 8720 u8 reserved_at_e0[0x20];
e281682b 8721
b4ff3a36 8722 u8 reserved_at_100[0x1c];
e281682b
SM		 8723 u8 srps_admin[0x4];
8724
b4ff3a36 8725 u8 reserved_at_120[0x1c];
e281682b
SM		 8726 u8 srps_status[0x4];
8727
b4ff3a36 8728 u8 reserved_at_140[0x40];
e281682b
SM		 8729};
8730
8731struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 8732 u8 reserved_at_0[0x8];
e281682b 8733 u8 local_port[0x8];
b4ff3a36 8734 u8 reserved_at_10[0x10];
e281682b 8735
b4ff3a36 8736 u8 reserved_at_20[0x8];
e281682b 8737 u8 lb_cap[0x8];
b4ff3a36 8738 u8 reserved_at_30[0x8];
e281682b
SM		 8739 u8 lb_en[0x8];
8740};
8741
8742struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 8743 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 8744 u8 local_port[0x8];
8745 u8 reserved_at_10[0x10];
e281682b 8746
4b5b9c7d 8747 u8 reserved_at_20[0x20];
e281682b 8748
4b5b9c7d
SA		 8749 u8 port_profile_mode[0x8];
8750 u8 static_port_profile[0x8];
8751 u8 active_port_profile[0x8];
8752 u8 reserved_at_58[0x8];
e281682b 8753
4b5b9c7d
SA		 8754 u8 retransmission_active[0x8];
8755 u8 fec_mode_active[0x18];
e281682b 8756
4b5b9c7d
SA		 8757 u8 rs_fec_correction_bypass_cap[0x4];
8758 u8 reserved_at_84[0x8];
8759 u8 fec_override_cap_56g[0x4];
8760 u8 fec_override_cap_100g[0x4];
8761 u8 fec_override_cap_50g[0x4];
8762 u8 fec_override_cap_25g[0x4];
8763 u8 fec_override_cap_10g_40g[0x4];
8764
8765 u8 rs_fec_correction_bypass_admin[0x4];
8766 u8 reserved_at_a4[0x8];
8767 u8 fec_override_admin_56g[0x4];
8768 u8 fec_override_admin_100g[0x4];
8769 u8 fec_override_admin_50g[0x4];
8770 u8 fec_override_admin_25g[0x4];
8771 u8 fec_override_admin_10g_40g[0x4];
a58837f5
AL		 8772
8773 u8 fec_override_cap_400g_8x[0x10];
8774 u8 fec_override_cap_200g_4x[0x10];
8775
8776 u8 fec_override_cap_100g_2x[0x10];
8777 u8 fec_override_cap_50g_1x[0x10];
8778
8779 u8 fec_override_admin_400g_8x[0x10];
8780 u8 fec_override_admin_200g_4x[0x10];
8781
8782 u8 fec_override_admin_100g_2x[0x10];
8783 u8 fec_override_admin_50g_1x[0x10];
e281682b
SM		 8784};
8785
8786struct mlx5_ifc_ppcnt_reg_bits {
8787 u8 swid[0x8];
8788 u8 local_port[0x8];
8789 u8 pnat[0x2];
b4ff3a36 8790 u8 reserved_at_12[0x8];
e281682b
SM		 8791 u8 grp[0x6];
8792
8793 u8 clr[0x1];
b4ff3a36 8794 u8 reserved_at_21[0x1c];
e281682b
SM		 8795 u8 prio_tc[0x3];
8796
8797 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8798};
8799
4039049b
AL		 8800struct mlx5_ifc_mpein_reg_bits {
8801 u8 reserved_at_0[0x2];
8802 u8 depth[0x6];
8803 u8 pcie_index[0x8];
8804 u8 node[0x8];
8805 u8 reserved_at_18[0x8];
8806
8807 u8 capability_mask[0x20];
8808
8809 u8 reserved_at_40[0x8];
8810 u8 link_width_enabled[0x8];
8811 u8 link_speed_enabled[0x10];
8812
8813 u8 lane0_physical_position[0x8];
8814 u8 link_width_active[0x8];
8815 u8 link_speed_active[0x10];
8816
8817 u8 num_of_pfs[0x10];
8818 u8 num_of_vfs[0x10];
8819
8820 u8 bdf0[0x10];
8821 u8 reserved_at_b0[0x10];
8822
8823 u8 max_read_request_size[0x4];
8824 u8 max_payload_size[0x4];
8825 u8 reserved_at_c8[0x5];
8826 u8 pwr_status[0x3];
8827 u8 port_type[0x4];
8828 u8 reserved_at_d4[0xb];
8829 u8 lane_reversal[0x1];
8830
8831 u8 reserved_at_e0[0x14];
8832 u8 pci_power[0xc];
8833
8834 u8 reserved_at_100[0x20];
8835
8836 u8 device_status[0x10];
8837 u8 port_state[0x8];
8838 u8 reserved_at_138[0x8];
8839
8840 u8 reserved_at_140[0x10];
8841 u8 receiver_detect_result[0x10];
8842
8843 u8 reserved_at_160[0x20];
8844};
8845
8ed1a630
GP		 8846struct mlx5_ifc_mpcnt_reg_bits {
8847 u8 reserved_at_0[0x8];
8848 u8 pcie_index[0x8];
8849 u8 reserved_at_10[0xa];
8850 u8 grp[0x6];
8851
8852 u8 clr[0x1];
8853 u8 reserved_at_21[0x1f];
8854
8855 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8856};
8857
e281682b 8858struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 8859 u8 reserved_at_0[0x3];
e281682b 8860 u8 single_mac[0x1];
b4ff3a36 8861 u8 reserved_at_4[0x4];
e281682b
SM		 8862 u8 local_port[0x8];
8863 u8 mac_47_32[0x10];
8864
8865 u8 mac_31_0[0x20];
8866
b4ff3a36 8867 u8 reserved_at_40[0x40];
e281682b
SM		 8868};
8869
8870struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 8871 u8 reserved_at_0[0x8];
e281682b 8872 u8 local_port[0x8];
b4ff3a36 8873 u8 reserved_at_10[0x10];
e281682b
SM		 8874
8875 u8 max_mtu[0x10];
b4ff3a36 8876 u8 reserved_at_30[0x10];
e281682b
SM		 8877
8878 u8 admin_mtu[0x10];
b4ff3a36 8879 u8 reserved_at_50[0x10];
e281682b
SM		 8880
8881 u8 oper_mtu[0x10];
b4ff3a36 8882 u8 reserved_at_70[0x10];
e281682b
SM		 8883};
8884
8885struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 8886 u8 reserved_at_0[0x8];
e281682b 8887 u8 module[0x8];
b4ff3a36 8888 u8 reserved_at_10[0x10];
e281682b 8889
b4ff3a36 8890 u8 reserved_at_20[0x18];
e281682b
SM		 8891 u8 attenuation_5g[0x8];
8892
b4ff3a36 8893 u8 reserved_at_40[0x18];
e281682b
SM		 8894 u8 attenuation_7g[0x8];
8895
b4ff3a36 8896 u8 reserved_at_60[0x18];
e281682b
SM		 8897 u8 attenuation_12g[0x8];
8898};
8899
8900struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 8901 u8 reserved_at_0[0x8];
e281682b 8902 u8 module[0x8];
b4ff3a36 8903 u8 reserved_at_10[0xc];
e281682b
SM		 8904 u8 module_status[0x4];
8905
b4ff3a36 8906 u8 reserved_at_20[0x60];
e281682b
SM		 8907};
8908
8909struct mlx5_ifc_pmpc_reg_bits {
8910 u8 module_state_updated[32][0x8];
8911};
8912
8913struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 8914 u8 reserved_at_0[0x4];
e281682b
SM		 8915 u8 mlpn_status[0x4];
8916 u8 local_port[0x8];
b4ff3a36 8917 u8 reserved_at_10[0x10];
e281682b
SM		 8918
8919 u8 e[0x1];
b4ff3a36 8920 u8 reserved_at_21[0x1f];
e281682b
SM		 8921};
8922
8923struct mlx5_ifc_pmlp_reg_bits {
8924 u8 rxtx[0x1];
b4ff3a36 8925 u8 reserved_at_1[0x7];
e281682b 8926 u8 local_port[0x8];
b4ff3a36 8927 u8 reserved_at_10[0x8];
e281682b
SM		 8928 u8 width[0x8];
8929
8930 u8 lane0_module_mapping[0x20];
8931
8932 u8 lane1_module_mapping[0x20];
8933
8934 u8 lane2_module_mapping[0x20];
8935
8936 u8 lane3_module_mapping[0x20];
8937
b4ff3a36 8938 u8 reserved_at_a0[0x160];
e281682b
SM		 8939};
8940
8941struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 8942 u8 reserved_at_0[0x8];
e281682b 8943 u8 module[0x8];
b4ff3a36 8944 u8 reserved_at_10[0x4];
e281682b 8945 u8 admin_status[0x4];
b4ff3a36 8946 u8 reserved_at_18[0x4];
e281682b
SM		 8947 u8 oper_status[0x4];
8948
8949 u8 ase[0x1];
8950 u8 ee[0x1];
b4ff3a36 8951 u8 reserved_at_22[0x1c];
e281682b
SM		 8952 u8 e[0x2];
8953
b4ff3a36 8954 u8 reserved_at_40[0x40];
e281682b
SM		 8955};
8956
8957struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 8958 u8 reserved_at_0[0x4];
e281682b 8959 u8 profile_id[0xc];
b4ff3a36 8960 u8 reserved_at_10[0x4];
e281682b 8961 u8 proto_mask[0x4];
b4ff3a36 8962 u8 reserved_at_18[0x8];
e281682b 8963
b4ff3a36 8964 u8 reserved_at_20[0x10];
e281682b
SM		 8965 u8 lane_speed[0x10];
8966
b4ff3a36 8967 u8 reserved_at_40[0x17];
e281682b
SM		 8968 u8 lpbf[0x1];
8969 u8 fec_mode_policy[0x8];
8970
8971 u8 retransmission_capability[0x8];
8972 u8 fec_mode_capability[0x18];
8973
8974 u8 retransmission_support_admin[0x8];
8975 u8 fec_mode_support_admin[0x18];
8976
8977 u8 retransmission_request_admin[0x8];
8978 u8 fec_mode_request_admin[0x18];
8979
b4ff3a36 8980 u8 reserved_at_c0[0x80];
e281682b
SM		 8981};
8982
8983struct mlx5_ifc_plib_reg_bits {
b4ff3a36 8984 u8 reserved_at_0[0x8];
e281682b 8985 u8 local_port[0x8];
b4ff3a36 8986 u8 reserved_at_10[0x8];
e281682b
SM		 8987 u8 ib_port[0x8];
8988
b4ff3a36 8989 u8 reserved_at_20[0x60];
e281682b
SM		 8990};
8991
8992struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 8993 u8 reserved_at_0[0x8];
e281682b 8994 u8 local_port[0x8];
b4ff3a36 8995 u8 reserved_at_10[0xd];
e281682b
SM		 8996 u8 lbf_mode[0x3];
8997
b4ff3a36 8998 u8 reserved_at_20[0x20];
e281682b
SM		 8999};
9000
9001struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 9002 u8 reserved_at_0[0x8];
e281682b 9003 u8 local_port[0x8];
b4ff3a36 9004 u8 reserved_at_10[0x10];
e281682b
SM		 9005
9006 u8 dic[0x1];
b4ff3a36 9007 u8 reserved_at_21[0x19];
e281682b 9008 u8 ipg[0x4];
b4ff3a36 9009 u8 reserved_at_3e[0x2];
e281682b
SM		 9010};
9011
9012struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 9013 u8 reserved_at_0[0x8];
e281682b 9014 u8 local_port[0x8];
b4ff3a36 9015 u8 reserved_at_10[0x10];
e281682b 9016
b4ff3a36 9017 u8 reserved_at_20[0xe0];
e281682b
SM		 9018
9019 u8 port_filter[8][0x20];
9020
9021 u8 port_filter_update_en[8][0x20];
9022};
9023
9024struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 9025 u8 reserved_at_0[0x8];
e281682b 9026 u8 local_port[0x8];
2afa609f
IK		 9027 u8 reserved_at_10[0xb];
9028 u8 ppan_mask_n[0x1];
9029 u8 minor_stall_mask[0x1];
9030 u8 critical_stall_mask[0x1];
9031 u8 reserved_at_1e[0x2];
e281682b
SM		 9032
9033 u8 ppan[0x4];
b4ff3a36 9034 u8 reserved_at_24[0x4];
e281682b 9035 u8 prio_mask_tx[0x8];
b4ff3a36 9036 u8 reserved_at_30[0x8];
e281682b
SM		 9037 u8 prio_mask_rx[0x8];
9038
9039 u8 pptx[0x1];
9040 u8 aptx[0x1];
2afa609f
IK		 9041 u8 pptx_mask_n[0x1];
9042 u8 reserved_at_43[0x5];
e281682b 9043 u8 pfctx[0x8];
b4ff3a36 9044 u8 reserved_at_50[0x10];
e281682b
SM		 9045
9046 u8 pprx[0x1];
9047 u8 aprx[0x1];
2afa609f
IK		 9048 u8 pprx_mask_n[0x1];
9049 u8 reserved_at_63[0x5];
e281682b 9050 u8 pfcrx[0x8];
b4ff3a36 9051 u8 reserved_at_70[0x10];
e281682b 9052
2afa609f
IK		 9053 u8 device_stall_minor_watermark[0x10];
9054 u8 device_stall_critical_watermark[0x10];
9055
9056 u8 reserved_at_a0[0x60];
e281682b
SM		 9057};
9058
9059struct mlx5_ifc_pelc_reg_bits {
9060 u8 op[0x4];
b4ff3a36 9061 u8 reserved_at_4[0x4];
e281682b 9062 u8 local_port[0x8];
b4ff3a36 9063 u8 reserved_at_10[0x10];
e281682b
SM		 9064
9065 u8 op_admin[0x8];
9066 u8 op_capability[0x8];
9067 u8 op_request[0x8];
9068 u8 op_active[0x8];
9069
9070 u8 admin[0x40];
9071
9072 u8 capability[0x40];
9073
9074 u8 request[0x40];
9075
9076 u8 active[0x40];
9077
b4ff3a36 9078 u8 reserved_at_140[0x80];
e281682b
SM		 9079};
9080
9081struct mlx5_ifc_peir_reg_bits {
b4ff3a36 9082 u8 reserved_at_0[0x8];
e281682b 9083 u8 local_port[0x8];
b4ff3a36 9084 u8 reserved_at_10[0x10];
e281682b 9085
b4ff3a36 9086 u8 reserved_at_20[0xc];
e281682b 9087 u8 error_count[0x4];
b4ff3a36 9088 u8 reserved_at_30[0x10];
e281682b 9089
b4ff3a36 9090 u8 reserved_at_40[0xc];
e281682b 9091 u8 lane[0x4];
b4ff3a36 9092 u8 reserved_at_50[0x8];
e281682b
SM		 9093 u8 error_type[0x8];
9094};
9095
5e022dd3
EBE		 9096struct mlx5_ifc_mpegc_reg_bits {
9097 u8 reserved_at_0[0x30];
9098 u8 field_select[0x10];
9099
9100 u8 tx_overflow_sense[0x1];
9101 u8 mark_cqe[0x1];
9102 u8 mark_cnp[0x1];
9103 u8 reserved_at_43[0x1b];
9104 u8 tx_lossy_overflow_oper[0x2];
9105
9106 u8 reserved_at_60[0x100];
9107};
9108
cfdcbcea 9109struct mlx5_ifc_pcam_enhanced_features_bits {
a58837f5
AL		 9110 u8 reserved_at_0[0x68];
9111 u8 fec_50G_per_lane_in_pplm[0x1];
9112 u8 reserved_at_69[0x4];
0af5107c 9113 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 9114 u8 reserved_at_6e[0x4];
9115 u8 ptys_extended_ethernet[0x1];
9116 u8 reserved_at_73[0x3];
2fcb12df 9117 u8 pfcc_mask[0x1];
67daf118
SA		 9118 u8 reserved_at_77[0x3];
9119 u8 per_lane_error_counters[0x1];
2dba0797 9120 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 9121 u8 ptys_connector_type[0x1];
9122 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 9123 u8 ppcnt_discard_group[0x1];
9124 u8 ppcnt_statistical_group[0x1];
9125};
9126
df5f1361
HN		 9127struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9128 u8 port_access_reg_cap_mask_127_to_96[0x20];
9129 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 9130
9131 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9132 u8 pplm[0x1];
9133 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 9134
9135 u8 port_access_reg_cap_mask_31_to_13[0x13];
9136 u8 pbmc[0x1];
9137 u8 pptb[0x1];
75370eb0
ED		 9138 u8 port_access_reg_cap_mask_10_to_09[0x2];
9139 u8 ppcnt[0x1];
9140 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 9141};
9142
cfdcbcea
GP		 9143struct mlx5_ifc_pcam_reg_bits {
9144 u8 reserved_at_0[0x8];
9145 u8 feature_group[0x8];
9146 u8 reserved_at_10[0x8];
9147 u8 access_reg_group[0x8];
9148
9149 u8 reserved_at_20[0x20];
9150
9151 union {
df5f1361 9152 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 9153 u8 reserved_at_0[0x80];
9154 } port_access_reg_cap_mask;
9155
9156 u8 reserved_at_c0[0x80];
9157
9158 union {
9159 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9160 u8 reserved_at_0[0x80];
9161 } feature_cap_mask;
9162
9163 u8 reserved_at_1c0[0xc0];
9164};
9165
9166struct mlx5_ifc_mcam_enhanced_features_bits {
4039049b
AL		 9167 u8 reserved_at_0[0x6e];
9168 u8 pci_status_and_power[0x1];
9169 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 9170 u8 mark_tx_action_cnp[0x1];
9171 u8 mark_tx_action_cqe[0x1];
9172 u8 dynamic_tx_overflow[0x1];
9173 u8 reserved_at_77[0x4];
5405fa26 9174 u8 pcie_outbound_stalled[0x1];
efae7f78 9175 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 9176 u8 mtpps_enh_out_per_adj[0x1];
9177 u8 mtpps_fs[0x1];
cfdcbcea
GP		 9178 u8 pcie_performance_group[0x1];
9179};
9180
0ab87743
OG		 9181struct mlx5_ifc_mcam_access_reg_bits {
9182 u8 reserved_at_0[0x1c];
9183 u8 mcda[0x1];
9184 u8 mcc[0x1];
9185 u8 mcqi[0x1];
a82e0b5b 9186 u8 mcqs[0x1];
0ab87743 9187
5e022dd3
EBE		 9188 u8 regs_95_to_87[0x9];
9189 u8 mpegc[0x1];
9190 u8 regs_85_to_68[0x12];
eff8ea8f
FD		 9191 u8 tracer_registers[0x4];
9192
0ab87743
OG		 9193 u8 regs_63_to_32[0x20];
9194 u8 regs_31_to_0[0x20];
9195};
9196
f397464e
EBE		 9197struct mlx5_ifc_mcam_access_reg_bits1 {
9198 u8 regs_127_to_96[0x20];
9199
9200 u8 regs_95_to_64[0x20];
9201
9202 u8 regs_63_to_32[0x20];
9203
9204 u8 regs_31_to_0[0x20];
9205};
9206
9207struct mlx5_ifc_mcam_access_reg_bits2 {
9208 u8 regs_127_to_99[0x1d];
9209 u8 mirc[0x1];
9210 u8 regs_97_to_96[0x2];
9211
9212 u8 regs_95_to_64[0x20];
9213
9214 u8 regs_63_to_32[0x20];
9215
9216 u8 regs_31_to_0[0x20];
9217};
9218
cfdcbcea
GP		 9219struct mlx5_ifc_mcam_reg_bits {
9220 u8 reserved_at_0[0x8];
9221 u8 feature_group[0x8];
9222 u8 reserved_at_10[0x8];
9223 u8 access_reg_group[0x8];
9224
9225 u8 reserved_at_20[0x20];
9226
9227 union {
0ab87743 9228 struct mlx5_ifc_mcam_access_reg_bits access_regs;
f397464e
EBE		 9229 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9230 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
cfdcbcea
GP		 9231 u8 reserved_at_0[0x80];
9232 } mng_access_reg_cap_mask;
9233
9234 u8 reserved_at_c0[0x80];
9235
9236 union {
9237 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9238 u8 reserved_at_0[0x80];
9239 } mng_feature_cap_mask;
9240
9241 u8 reserved_at_1c0[0x80];
9242};
9243
c02762eb
HN		 9244struct mlx5_ifc_qcam_access_reg_cap_mask {
9245 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9246 u8 qpdpm[0x1];
9247 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9248 u8 qdpm[0x1];
9249 u8 qpts[0x1];
9250 u8 qcap[0x1];
9251 u8 qcam_access_reg_cap_mask_0[0x1];
9252};
9253
9254struct mlx5_ifc_qcam_qos_feature_cap_mask {
9255 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9256 u8 qpts_trust_both[0x1];
9257};
9258
9259struct mlx5_ifc_qcam_reg_bits {
9260 u8 reserved_at_0[0x8];
9261 u8 feature_group[0x8];
9262 u8 reserved_at_10[0x8];
9263 u8 access_reg_group[0x8];
9264 u8 reserved_at_20[0x20];
9265
9266 union {
9267 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9268 u8 reserved_at_0[0x80];
9269 } qos_access_reg_cap_mask;
9270
9271 u8 reserved_at_c0[0x80];
9272
9273 union {
9274 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9275 u8 reserved_at_0[0x80];
9276 } qos_feature_cap_mask;
9277
9278 u8 reserved_at_1c0[0x80];
9279};
9280
0b9055a1
MS		 9281struct mlx5_ifc_core_dump_reg_bits {
9282 u8 reserved_at_0[0x18];
9283 u8 core_dump_type[0x8];
9284
9285 u8 reserved_at_20[0x30];
9286 u8 vhca_id[0x10];
9287
9288 u8 reserved_at_60[0x8];
9289 u8 qpn[0x18];
9290 u8 reserved_at_80[0x180];
9291};
9292
e281682b 9293struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 9294 u8 reserved_at_0[0x8];
e281682b 9295 u8 local_port[0x8];
b4ff3a36 9296 u8 reserved_at_10[0x10];
e281682b
SM		 9297
9298 u8 port_capability_mask[4][0x20];
9299};
9300
9301struct mlx5_ifc_paos_reg_bits {
9302 u8 swid[0x8];
9303 u8 local_port[0x8];
b4ff3a36 9304 u8 reserved_at_10[0x4];
e281682b 9305 u8 admin_status[0x4];
b4ff3a36 9306 u8 reserved_at_18[0x4];
e281682b
SM		 9307 u8 oper_status[0x4];
9308
9309 u8 ase[0x1];
9310 u8 ee[0x1];
b4ff3a36 9311 u8 reserved_at_22[0x1c];
e281682b
SM		 9312 u8 e[0x2];
9313
b4ff3a36 9314 u8 reserved_at_40[0x40];
e281682b
SM		 9315};
9316
9317struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 9318 u8 reserved_at_0[0x8];
e281682b 9319 u8 opamp_group[0x8];
b4ff3a36 9320 u8 reserved_at_10[0xc];
e281682b
SM		 9321 u8 opamp_group_type[0x4];
9322
9323 u8 start_index[0x10];
b4ff3a36 9324 u8 reserved_at_30[0x4];
e281682b
SM		 9325 u8 num_of_indices[0xc];
9326
9327 u8 index_data[18][0x10];
9328};
9329
7d5e1423
SM		 9330struct mlx5_ifc_pcmr_reg_bits {
9331 u8 reserved_at_0[0x8];
9332 u8 local_port[0x8];
0dcaafc0
EB		 9333 u8 reserved_at_10[0x10];
9334 u8 entropy_force_cap[0x1];
9335 u8 entropy_calc_cap[0x1];
9336 u8 entropy_gre_calc_cap[0x1];
9337 u8 reserved_at_23[0x1b];
7d5e1423 9338 u8 fcs_cap[0x1];
0dcaafc0
EB		 9339 u8 reserved_at_3f[0x1];
9340 u8 entropy_force[0x1];
9341 u8 entropy_calc[0x1];
9342 u8 entropy_gre_calc[0x1];
9343 u8 reserved_at_43[0x1b];
7d5e1423
SM		 9344 u8 fcs_chk[0x1];
9345 u8 reserved_at_5f[0x1];
9346};
9347
e281682b 9348struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 9349 u8 reserved_at_0[0x6];
e281682b 9350 u8 rx_lane[0x2];
b4ff3a36 9351 u8 reserved_at_8[0x6];
e281682b 9352 u8 tx_lane[0x2];
b4ff3a36 9353 u8 reserved_at_10[0x8];
e281682b
SM		 9354 u8 module[0x8];
9355};
9356
9357struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 9358 u8 reserved_at_0[0x6];
e281682b
SM		 9359 u8 lossy[0x1];
9360 u8 epsb[0x1];
b4ff3a36 9361 u8 reserved_at_8[0xc];
e281682b
SM		 9362 u8 size[0xc];
9363
9364 u8 xoff_threshold[0x10];
9365 u8 xon_threshold[0x10];
9366};
9367
9368struct mlx5_ifc_set_node_in_bits {
9369 u8 node_description[64][0x8];
9370};
9371
9372struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 9373 u8 reserved_at_0[0x18];
e281682b
SM		 9374 u8 power_settings_level[0x8];
9375
b4ff3a36 9376 u8 reserved_at_20[0x60];
e281682b
SM		 9377};
9378
9379struct mlx5_ifc_register_host_endianness_bits {
9380 u8 he[0x1];
b4ff3a36 9381 u8 reserved_at_1[0x1f];
e281682b 9382
b4ff3a36 9383 u8 reserved_at_20[0x60];
e281682b
SM		 9384};
9385
9386struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 9387 u8 reserved_at_0[0x20];
e281682b
SM		 9388
9389 u8 mkey[0x20];
9390
9391 u8 addressh_63_32[0x20];
9392
9393 u8 addressl_31_0[0x20];
9394};
9395
9396struct mlx5_ifc_ud_adrs_vector_bits {
9397 u8 dc_key[0x40];
9398
9399 u8 ext[0x1];
b4ff3a36 9400 u8 reserved_at_41[0x7];
e281682b
SM		 9401 u8 destination_qp_dct[0x18];
9402
9403 u8 static_rate[0x4];
9404 u8 sl_eth_prio[0x4];
9405 u8 fl[0x1];
9406 u8 mlid[0x7];
9407 u8 rlid_udp_sport[0x10];
9408
b4ff3a36 9409 u8 reserved_at_80[0x20];
e281682b
SM		 9410
9411 u8 rmac_47_16[0x20];
9412
9413 u8 rmac_15_0[0x10];
9414 u8 tclass[0x8];
9415 u8 hop_limit[0x8];
9416
b4ff3a36 9417 u8 reserved_at_e0[0x1];
e281682b 9418 u8 grh[0x1];
b4ff3a36 9419 u8 reserved_at_e2[0x2];
e281682b
SM		 9420 u8 src_addr_index[0x8];
9421 u8 flow_label[0x14];
9422
9423 u8 rgid_rip[16][0x8];
9424};
9425
9426struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 9427 u8 reserved_at_0[0x10];
e281682b
SM		 9428 u8 function_id[0x10];
9429
9430 u8 num_pages[0x20];
9431
b4ff3a36 9432 u8 reserved_at_40[0xa0];
e281682b
SM		 9433};
9434
9435struct mlx5_ifc_eqe_bits {
b4ff3a36 9436 u8 reserved_at_0[0x8];
e281682b 9437 u8 event_type[0x8];
b4ff3a36 9438 u8 reserved_at_10[0x8];
e281682b
SM		 9439 u8 event_sub_type[0x8];
9440
b4ff3a36 9441 u8 reserved_at_20[0xe0];
e281682b
SM		 9442
9443 union mlx5_ifc_event_auto_bits event_data;
9444
b4ff3a36 9445 u8 reserved_at_1e0[0x10];
e281682b 9446 u8 signature[0x8];
b4ff3a36 9447 u8 reserved_at_1f8[0x7];
e281682b
SM		 9448 u8 owner[0x1];
9449};
9450
9451enum {
9452 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9453};
9454
9455struct mlx5_ifc_cmd_queue_entry_bits {
9456 u8 type[0x8];
b4ff3a36 9457 u8 reserved_at_8[0x18];
e281682b
SM		 9458
9459 u8 input_length[0x20];
9460
9461 u8 input_mailbox_pointer_63_32[0x20];
9462
9463 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 9464 u8 reserved_at_77[0x9];
e281682b
SM		 9465
9466 u8 command_input_inline_data[16][0x8];
9467
9468 u8 command_output_inline_data[16][0x8];
9469
9470 u8 output_mailbox_pointer_63_32[0x20];
9471
9472 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 9473 u8 reserved_at_1b7[0x9];
e281682b
SM		 9474
9475 u8 output_length[0x20];
9476
9477 u8 token[0x8];
9478 u8 signature[0x8];
b4ff3a36 9479 u8 reserved_at_1f0[0x8];
e281682b
SM		 9480 u8 status[0x7];
9481 u8 ownership[0x1];
9482};
9483
9484struct mlx5_ifc_cmd_out_bits {
9485 u8 status[0x8];
b4ff3a36 9486 u8 reserved_at_8[0x18];
e281682b
SM		 9487
9488 u8 syndrome[0x20];
9489
9490 u8 command_output[0x20];
9491};
9492
9493struct mlx5_ifc_cmd_in_bits {
9494 u8 opcode[0x10];
b4ff3a36 9495 u8 reserved_at_10[0x10];
e281682b 9496
b4ff3a36 9497 u8 reserved_at_20[0x10];
e281682b
SM		 9498 u8 op_mod[0x10];
9499
b6ca09cb 9500 u8 command[][0x20];
e281682b
SM		 9501};
9502
9503struct mlx5_ifc_cmd_if_box_bits {
9504 u8 mailbox_data[512][0x8];
9505
b4ff3a36 9506 u8 reserved_at_1000[0x180];
e281682b
SM		 9507
9508 u8 next_pointer_63_32[0x20];
9509
9510 u8 next_pointer_31_10[0x16];
b4ff3a36 9511 u8 reserved_at_11b6[0xa];
e281682b
SM		 9512
9513 u8 block_number[0x20];
9514
b4ff3a36 9515 u8 reserved_at_11e0[0x8];
e281682b
SM		 9516 u8 token[0x8];
9517 u8 ctrl_signature[0x8];
9518 u8 signature[0x8];
9519};
9520
9521struct mlx5_ifc_mtt_bits {
9522 u8 ptag_63_32[0x20];
9523
9524 u8 ptag_31_8[0x18];
b4ff3a36 9525 u8 reserved_at_38[0x6];
e281682b
SM		 9526 u8 wr_en[0x1];
9527 u8 rd_en[0x1];
9528};
9529
928cfe87
TT		 9530struct mlx5_ifc_query_wol_rol_out_bits {
9531 u8 status[0x8];
9532 u8 reserved_at_8[0x18];
9533
9534 u8 syndrome[0x20];
9535
9536 u8 reserved_at_40[0x10];
9537 u8 rol_mode[0x8];
9538 u8 wol_mode[0x8];
9539
9540 u8 reserved_at_60[0x20];
9541};
9542
9543struct mlx5_ifc_query_wol_rol_in_bits {
9544 u8 opcode[0x10];
9545 u8 reserved_at_10[0x10];
9546
9547 u8 reserved_at_20[0x10];
9548 u8 op_mod[0x10];
9549
9550 u8 reserved_at_40[0x40];
9551};
9552
9553struct mlx5_ifc_set_wol_rol_out_bits {
9554 u8 status[0x8];
9555 u8 reserved_at_8[0x18];
9556
9557 u8 syndrome[0x20];
9558
9559 u8 reserved_at_40[0x40];
9560};
9561
9562struct mlx5_ifc_set_wol_rol_in_bits {
9563 u8 opcode[0x10];
9564 u8 reserved_at_10[0x10];
9565
9566 u8 reserved_at_20[0x10];
9567 u8 op_mod[0x10];
9568
9569 u8 rol_mode_valid[0x1];
9570 u8 wol_mode_valid[0x1];
9571 u8 reserved_at_42[0xe];
9572 u8 rol_mode[0x8];
9573 u8 wol_mode[0x8];
9574
9575 u8 reserved_at_60[0x20];
9576};
9577
e281682b
SM		 9578enum {
9579 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9580 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9581 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9582};
9583
9584enum {
9585 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9586 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9587 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9588};
9589
9590enum {
9591 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9592 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9593 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9594 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9595 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9596 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9597 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9598 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9599 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9600 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9601 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9602};
9603
9604struct mlx5_ifc_initial_seg_bits {
9605 u8 fw_rev_minor[0x10];
9606 u8 fw_rev_major[0x10];
9607
9608 u8 cmd_interface_rev[0x10];
9609 u8 fw_rev_subminor[0x10];
9610
b4ff3a36 9611 u8 reserved_at_40[0x40];
e281682b
SM		 9612
9613 u8 cmdq_phy_addr_63_32[0x20];
9614
9615 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 9616 u8 reserved_at_b4[0x2];
e281682b
SM		 9617 u8 nic_interface[0x2];
9618 u8 log_cmdq_size[0x4];
9619 u8 log_cmdq_stride[0x4];
9620
9621 u8 command_doorbell_vector[0x20];
9622
b4ff3a36 9623 u8 reserved_at_e0[0xf00];
e281682b
SM		 9624
9625 u8 initializing[0x1];
b4ff3a36 9626 u8 reserved_at_fe1[0x4];
e281682b 9627 u8 nic_interface_supported[0x3];
591905ba
BW		 9628 u8 embedded_cpu[0x1];
9629 u8 reserved_at_fe9[0x17];
e281682b
SM		 9630
9631 struct mlx5_ifc_health_buffer_bits health_buffer;
9632
9633 u8 no_dram_nic_offset[0x20];
9634
b4ff3a36 9635 u8 reserved_at_1220[0x6e40];
e281682b 9636
b4ff3a36 9637 u8 reserved_at_8060[0x1f];
e281682b
SM		 9638 u8 clear_int[0x1];
9639
9640 u8 health_syndrome[0x8];
9641 u8 health_counter[0x18];
9642
b4ff3a36 9643 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 9644};
9645
f9a1ef72
EE		 9646struct mlx5_ifc_mtpps_reg_bits {
9647 u8 reserved_at_0[0xc];
9648 u8 cap_number_of_pps_pins[0x4];
9649 u8 reserved_at_10[0x4];
9650 u8 cap_max_num_of_pps_in_pins[0x4];
9651 u8 reserved_at_18[0x4];
9652 u8 cap_max_num_of_pps_out_pins[0x4];
9653
9654 u8 reserved_at_20[0x24];
9655 u8 cap_pin_3_mode[0x4];
9656 u8 reserved_at_48[0x4];
9657 u8 cap_pin_2_mode[0x4];
9658 u8 reserved_at_50[0x4];
9659 u8 cap_pin_1_mode[0x4];
9660 u8 reserved_at_58[0x4];
9661 u8 cap_pin_0_mode[0x4];
9662
9663 u8 reserved_at_60[0x4];
9664 u8 cap_pin_7_mode[0x4];
9665 u8 reserved_at_68[0x4];
9666 u8 cap_pin_6_mode[0x4];
9667 u8 reserved_at_70[0x4];
9668 u8 cap_pin_5_mode[0x4];
9669 u8 reserved_at_78[0x4];
9670 u8 cap_pin_4_mode[0x4];
9671
fa367688
EE		 9672 u8 field_select[0x20];
9673 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 9674
9675 u8 enable[0x1];
9676 u8 reserved_at_101[0xb];
9677 u8 pattern[0x4];
9678 u8 reserved_at_110[0x4];
9679 u8 pin_mode[0x4];
9680 u8 pin[0x8];
9681
9682 u8 reserved_at_120[0x20];
9683
9684 u8 time_stamp[0x40];
9685
9686 u8 out_pulse_duration[0x10];
9687 u8 out_periodic_adjustment[0x10];
fa367688 9688 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 9689
fa367688 9690 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 9691};
9692
9693struct mlx5_ifc_mtppse_reg_bits {
9694 u8 reserved_at_0[0x18];
9695 u8 pin[0x8];
9696 u8 event_arm[0x1];
9697 u8 reserved_at_21[0x1b];
9698 u8 event_generation_mode[0x4];
9699 u8 reserved_at_40[0x40];
9700};
9701
a82e0b5b
SA		 9702struct mlx5_ifc_mcqs_reg_bits {
9703 u8 last_index_flag[0x1];
9704 u8 reserved_at_1[0x7];
9705 u8 fw_device[0x8];
9706 u8 component_index[0x10];
9707
9708 u8 reserved_at_20[0x10];
9709 u8 identifier[0x10];
9710
9711 u8 reserved_at_40[0x17];
9712 u8 component_status[0x5];
9713 u8 component_update_state[0x4];
9714
9715 u8 last_update_state_changer_type[0x4];
9716 u8 last_update_state_changer_host_id[0x4];
9717 u8 reserved_at_68[0x18];
9718};
9719
47176289
OG		 9720struct mlx5_ifc_mcqi_cap_bits {
9721 u8 supported_info_bitmask[0x20];
9722
9723 u8 component_size[0x20];
9724
9725 u8 max_component_size[0x20];
9726
9727 u8 log_mcda_word_size[0x4];
9728 u8 reserved_at_64[0xc];
9729 u8 mcda_max_write_size[0x10];
9730
9731 u8 rd_en[0x1];
9732 u8 reserved_at_81[0x1];
9733 u8 match_chip_id[0x1];
9734 u8 match_psid[0x1];
9735 u8 check_user_timestamp[0x1];
9736 u8 match_base_guid_mac[0x1];
9737 u8 reserved_at_86[0x1a];
9738};
9739
a82e0b5b
SA		 9740struct mlx5_ifc_mcqi_version_bits {
9741 u8 reserved_at_0[0x2];
9742 u8 build_time_valid[0x1];
9743 u8 user_defined_time_valid[0x1];
9744 u8 reserved_at_4[0x14];
9745 u8 version_string_length[0x8];
9746
9747 u8 version[0x20];
9748
9749 u8 build_time[0x40];
9750
9751 u8 user_defined_time[0x40];
9752
9753 u8 build_tool_version[0x20];
9754
9755 u8 reserved_at_e0[0x20];
9756
9757 u8 version_string[92][0x8];
9758};
9759
9760struct mlx5_ifc_mcqi_activation_method_bits {
9761 u8 pending_server_ac_power_cycle[0x1];
9762 u8 pending_server_dc_power_cycle[0x1];
9763 u8 pending_server_reboot[0x1];
9764 u8 pending_fw_reset[0x1];
9765 u8 auto_activate[0x1];
9766 u8 all_hosts_sync[0x1];
9767 u8 device_hw_reset[0x1];
9768 u8 reserved_at_7[0x19];
9769};
9770
9771union mlx5_ifc_mcqi_reg_data_bits {
9772 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9773 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9774 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9775};
9776
47176289
OG		 9777struct mlx5_ifc_mcqi_reg_bits {
9778 u8 read_pending_component[0x1];
9779 u8 reserved_at_1[0xf];
9780 u8 component_index[0x10];
9781
9782 u8 reserved_at_20[0x20];
9783
9784 u8 reserved_at_40[0x1b];
9785 u8 info_type[0x5];
9786
9787 u8 info_size[0x20];
9788
9789 u8 offset[0x20];
9790
9791 u8 reserved_at_a0[0x10];
9792 u8 data_size[0x10];
9793
b6ca09cb 9794 union mlx5_ifc_mcqi_reg_data_bits data[];
47176289
OG		 9795};
9796
9797struct mlx5_ifc_mcc_reg_bits {
9798 u8 reserved_at_0[0x4];
9799 u8 time_elapsed_since_last_cmd[0xc];
9800 u8 reserved_at_10[0x8];
9801 u8 instruction[0x8];
9802
9803 u8 reserved_at_20[0x10];
9804 u8 component_index[0x10];
9805
9806 u8 reserved_at_40[0x8];
9807 u8 update_handle[0x18];
9808
9809 u8 handle_owner_type[0x4];
9810 u8 handle_owner_host_id[0x4];
9811 u8 reserved_at_68[0x1];
9812 u8 control_progress[0x7];
9813 u8 error_code[0x8];
9814 u8 reserved_at_78[0x4];
9815 u8 control_state[0x4];
9816
9817 u8 component_size[0x20];
9818
9819 u8 reserved_at_a0[0x60];
9820};
9821
9822struct mlx5_ifc_mcda_reg_bits {
9823 u8 reserved_at_0[0x8];
9824 u8 update_handle[0x18];
9825
9826 u8 offset[0x20];
9827
9828 u8 reserved_at_40[0x10];
9829 u8 size[0x10];
9830
9831 u8 reserved_at_60[0x20];
9832
29056207 9833 u8 data[][0x20];
47176289
OG		 9834};
9835
06939536
MS		 9836enum {
9837 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9838 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9839};
9840
9841enum {
9842 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9843 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9844 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9845};
9846
9847struct mlx5_ifc_mfrl_reg_bits {
9848 u8 reserved_at_0[0x20];
9849
9850 u8 reserved_at_20[0x2];
9851 u8 pci_sync_for_fw_update_start[0x1];
9852 u8 pci_sync_for_fw_update_resp[0x2];
9853 u8 rst_type_sel[0x3];
9854 u8 reserved_at_28[0x8];
9855 u8 reset_type[0x8];
9856 u8 reset_level[0x8];
9857};
9858
bab58ba1
EBE		 9859struct mlx5_ifc_mirc_reg_bits {
9860 u8 reserved_at_0[0x18];
9861 u8 status_code[0x8];
9862
9863 u8 reserved_at_20[0x20];
9864};
9865
e281682b
SM		 9866union mlx5_ifc_ports_control_registers_document_bits {
9867 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9868 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9869 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9870 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9871 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9872 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9873 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 9874 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9875 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
e281682b
SM		 9876 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9877 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9878 struct mlx5_ifc_paos_reg_bits paos_reg;
9879 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9880 struct mlx5_ifc_peir_reg_bits peir_reg;
9881 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9882 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 9883 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 9884 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9885 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9886 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9887 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9888 struct mlx5_ifc_plib_reg_bits plib_reg;
9889 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9890 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9891 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9892 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9893 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9894 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9895 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9896 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9897 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9898 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 9899 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 9900 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 9901 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9902 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9903 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9904 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9905 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9906 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9907 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 9908 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 9909 struct mlx5_ifc_pude_reg_bits pude_reg;
9910 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9911 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9912 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 9913 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9914 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 9915 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 9916 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9917 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 9918 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9919 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9920 struct mlx5_ifc_mcda_reg_bits mcda_reg;
bab58ba1 9921 struct mlx5_ifc_mirc_reg_bits mirc_reg;
06939536 9922 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
b4ff3a36 9923 u8 reserved_at_0[0x60e0];
e281682b
SM		 9924};
9925
9926union mlx5_ifc_debug_enhancements_document_bits {
9927 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 9928 u8 reserved_at_0[0x200];
e281682b
SM		 9929};
9930
9931union mlx5_ifc_uplink_pci_interface_document_bits {
9932 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 9933 u8 reserved_at_0[0x20060];
b775516b
EC		 9934};
9935
2cc43b49
MG		 9936struct mlx5_ifc_set_flow_table_root_out_bits {
9937 u8 status[0x8];
b4ff3a36 9938 u8 reserved_at_8[0x18];
2cc43b49
MG		 9939
9940 u8 syndrome[0x20];
9941
b4ff3a36 9942 u8 reserved_at_40[0x40];
2cc43b49
MG		 9943};
9944
9945struct mlx5_ifc_set_flow_table_root_in_bits {
9946 u8 opcode[0x10];
b4ff3a36 9947 u8 reserved_at_10[0x10];
2cc43b49 9948
b4ff3a36 9949 u8 reserved_at_20[0x10];
2cc43b49
MG		 9950 u8 op_mod[0x10];
9951
7d5e1423
SM		 9952 u8 other_vport[0x1];
9953 u8 reserved_at_41[0xf];
9954 u8 vport_number[0x10];
9955
9956 u8 reserved_at_60[0x20];
2cc43b49
MG		 9957
9958 u8 table_type[0x8];
b4ff3a36 9959 u8 reserved_at_88[0x18];
2cc43b49 9960
b4ff3a36 9961 u8 reserved_at_a0[0x8];
2cc43b49
MG		 9962 u8 table_id[0x18];
9963
500a3d0d
ES		 9964 u8 reserved_at_c0[0x8];
9965 u8 underlay_qpn[0x18];
9966 u8 reserved_at_e0[0x120];
2cc43b49
MG		 9967};
9968
34a40e68 9969enum {
84df61eb
AH		 9970 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9971 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 9972};
9973
9974struct mlx5_ifc_modify_flow_table_out_bits {
9975 u8 status[0x8];
b4ff3a36 9976 u8 reserved_at_8[0x18];
34a40e68
MG		 9977
9978 u8 syndrome[0x20];
9979
b4ff3a36 9980 u8 reserved_at_40[0x40];
34a40e68
MG		 9981};
9982
9983struct mlx5_ifc_modify_flow_table_in_bits {
9984 u8 opcode[0x10];
b4ff3a36 9985 u8 reserved_at_10[0x10];
34a40e68 9986
b4ff3a36 9987 u8 reserved_at_20[0x10];
34a40e68
MG		 9988 u8 op_mod[0x10];
9989
7d5e1423
SM		 9990 u8 other_vport[0x1];
9991 u8 reserved_at_41[0xf];
9992 u8 vport_number[0x10];
34a40e68 9993
b4ff3a36 9994 u8 reserved_at_60[0x10];
34a40e68
MG		 9995 u8 modify_field_select[0x10];
9996
9997 u8 table_type[0x8];
b4ff3a36 9998 u8 reserved_at_88[0x18];
34a40e68 9999
b4ff3a36 10000 u8 reserved_at_a0[0x8];
34a40e68
MG		 10001 u8 table_id[0x18];
10002
0c90e9c6 10003 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 10004};
10005
4f3961ee
SM		 10006struct mlx5_ifc_ets_tcn_config_reg_bits {
10007 u8 g[0x1];
10008 u8 b[0x1];
10009 u8 r[0x1];
10010 u8 reserved_at_3[0x9];
10011 u8 group[0x4];
10012 u8 reserved_at_10[0x9];
10013 u8 bw_allocation[0x7];
10014
10015 u8 reserved_at_20[0xc];
10016 u8 max_bw_units[0x4];
10017 u8 reserved_at_30[0x8];
10018 u8 max_bw_value[0x8];
10019};
10020
10021struct mlx5_ifc_ets_global_config_reg_bits {
10022 u8 reserved_at_0[0x2];
10023 u8 r[0x1];
10024 u8 reserved_at_3[0x1d];
10025
10026 u8 reserved_at_20[0xc];
10027 u8 max_bw_units[0x4];
10028 u8 reserved_at_30[0x8];
10029 u8 max_bw_value[0x8];
10030};
10031
10032struct mlx5_ifc_qetc_reg_bits {
10033 u8 reserved_at_0[0x8];
10034 u8 port_number[0x8];
10035 u8 reserved_at_10[0x30];
10036
10037 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10038 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10039};
10040
415a64aa
HN		 10041struct mlx5_ifc_qpdpm_dscp_reg_bits {
10042 u8 e[0x1];
10043 u8 reserved_at_01[0x0b];
10044 u8 prio[0x04];
10045};
10046
10047struct mlx5_ifc_qpdpm_reg_bits {
10048 u8 reserved_at_0[0x8];
10049 u8 local_port[0x8];
10050 u8 reserved_at_10[0x10];
10051 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10052};
10053
10054struct mlx5_ifc_qpts_reg_bits {
10055 u8 reserved_at_0[0x8];
10056 u8 local_port[0x8];
10057 u8 reserved_at_10[0x2d];
10058 u8 trust_state[0x3];
10059};
10060
50b4a3c2
HN		 10061struct mlx5_ifc_pptb_reg_bits {
10062 u8 reserved_at_0[0x2];
10063 u8 mm[0x2];
10064 u8 reserved_at_4[0x4];
10065 u8 local_port[0x8];
10066 u8 reserved_at_10[0x6];
10067 u8 cm[0x1];
10068 u8 um[0x1];
10069 u8 pm[0x8];
10070
10071 u8 prio_x_buff[0x20];
10072
10073 u8 pm_msb[0x8];
10074 u8 reserved_at_48[0x10];
10075 u8 ctrl_buff[0x4];
10076 u8 untagged_buff[0x4];
10077};
10078
88b3d5c9
EBE		 10079struct mlx5_ifc_sbcam_reg_bits {
10080 u8 reserved_at_0[0x8];
10081 u8 feature_group[0x8];
10082 u8 reserved_at_10[0x8];
10083 u8 access_reg_group[0x8];
10084
10085 u8 reserved_at_20[0x20];
10086
10087 u8 sb_access_reg_cap_mask[4][0x20];
10088
10089 u8 reserved_at_c0[0x80];
10090
10091 u8 sb_feature_cap_mask[4][0x20];
10092
10093 u8 reserved_at_1c0[0x40];
10094
10095 u8 cap_total_buffer_size[0x20];
10096
10097 u8 cap_cell_size[0x10];
10098 u8 cap_max_pg_buffers[0x8];
10099 u8 cap_num_pool_supported[0x8];
10100
10101 u8 reserved_at_240[0x8];
10102 u8 cap_sbsr_stat_size[0x8];
10103 u8 cap_max_tclass_data[0x8];
10104 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10105};
10106
50b4a3c2
HN		 10107struct mlx5_ifc_pbmc_reg_bits {
10108 u8 reserved_at_0[0x8];
10109 u8 local_port[0x8];
10110 u8 reserved_at_10[0x10];
10111
10112 u8 xoff_timer_value[0x10];
10113 u8 xoff_refresh[0x10];
10114
10115 u8 reserved_at_40[0x9];
10116 u8 fullness_threshold[0x7];
10117 u8 port_buffer_size[0x10];
10118
10119 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10120
10121 u8 reserved_at_2e0[0x40];
10122};
10123
4f3961ee
SM		 10124struct mlx5_ifc_qtct_reg_bits {
10125 u8 reserved_at_0[0x8];
10126 u8 port_number[0x8];
10127 u8 reserved_at_10[0xd];
10128 u8 prio[0x3];
10129
10130 u8 reserved_at_20[0x1d];
10131 u8 tclass[0x3];
10132};
10133
7d5e1423
SM		 10134struct mlx5_ifc_mcia_reg_bits {
10135 u8 l[0x1];
10136 u8 reserved_at_1[0x7];
10137 u8 module[0x8];
10138 u8 reserved_at_10[0x8];
10139 u8 status[0x8];
10140
10141 u8 i2c_device_address[0x8];
10142 u8 page_number[0x8];
10143 u8 device_address[0x10];
10144
10145 u8 reserved_at_40[0x10];
10146 u8 size[0x10];
10147
10148 u8 reserved_at_60[0x20];
10149
10150 u8 dword_0[0x20];
10151 u8 dword_1[0x20];
10152 u8 dword_2[0x20];
10153 u8 dword_3[0x20];
10154 u8 dword_4[0x20];
10155 u8 dword_5[0x20];
10156 u8 dword_6[0x20];
10157 u8 dword_7[0x20];
10158 u8 dword_8[0x20];
10159 u8 dword_9[0x20];
10160 u8 dword_10[0x20];
10161 u8 dword_11[0x20];
10162};
10163
7486216b
SM		 10164struct mlx5_ifc_dcbx_param_bits {
10165 u8 dcbx_cee_cap[0x1];
10166 u8 dcbx_ieee_cap[0x1];
10167 u8 dcbx_standby_cap[0x1];
c74d90c1 10168 u8 reserved_at_3[0x5];
7486216b
SM		 10169 u8 port_number[0x8];
10170 u8 reserved_at_10[0xa];
10171 u8 max_application_table_size[6];
10172 u8 reserved_at_20[0x15];
10173 u8 version_oper[0x3];
10174 u8 reserved_at_38[5];
10175 u8 version_admin[0x3];
10176 u8 willing_admin[0x1];
10177 u8 reserved_at_41[0x3];
10178 u8 pfc_cap_oper[0x4];
10179 u8 reserved_at_48[0x4];
10180 u8 pfc_cap_admin[0x4];
10181 u8 reserved_at_50[0x4];
10182 u8 num_of_tc_oper[0x4];
10183 u8 reserved_at_58[0x4];
10184 u8 num_of_tc_admin[0x4];
10185 u8 remote_willing[0x1];
10186 u8 reserved_at_61[3];
10187 u8 remote_pfc_cap[4];
10188 u8 reserved_at_68[0x14];
10189 u8 remote_num_of_tc[0x4];
10190 u8 reserved_at_80[0x18];
10191 u8 error[0x8];
10192 u8 reserved_at_a0[0x160];
10193};
84df61eb
AH		 10194
10195struct mlx5_ifc_lagc_bits {
10196 u8 reserved_at_0[0x1d];
10197 u8 lag_state[0x3];
10198
10199 u8 reserved_at_20[0x14];
10200 u8 tx_remap_affinity_2[0x4];
10201 u8 reserved_at_38[0x4];
10202 u8 tx_remap_affinity_1[0x4];
10203};
10204
10205struct mlx5_ifc_create_lag_out_bits {
10206 u8 status[0x8];
10207 u8 reserved_at_8[0x18];
10208
10209 u8 syndrome[0x20];
10210
10211 u8 reserved_at_40[0x40];
10212};
10213
10214struct mlx5_ifc_create_lag_in_bits {
10215 u8 opcode[0x10];
10216 u8 reserved_at_10[0x10];
10217
10218 u8 reserved_at_20[0x10];
10219 u8 op_mod[0x10];
10220
10221 struct mlx5_ifc_lagc_bits ctx;
10222};
10223
10224struct mlx5_ifc_modify_lag_out_bits {
10225 u8 status[0x8];
10226 u8 reserved_at_8[0x18];
10227
10228 u8 syndrome[0x20];
10229
10230 u8 reserved_at_40[0x40];
10231};
10232
10233struct mlx5_ifc_modify_lag_in_bits {
10234 u8 opcode[0x10];
10235 u8 reserved_at_10[0x10];
10236
10237 u8 reserved_at_20[0x10];
10238 u8 op_mod[0x10];
10239
10240 u8 reserved_at_40[0x20];
10241 u8 field_select[0x20];
10242
10243 struct mlx5_ifc_lagc_bits ctx;
10244};
10245
10246struct mlx5_ifc_query_lag_out_bits {
10247 u8 status[0x8];
10248 u8 reserved_at_8[0x18];
10249
10250 u8 syndrome[0x20];
10251
84df61eb
AH		 10252 struct mlx5_ifc_lagc_bits ctx;
10253};
10254
10255struct mlx5_ifc_query_lag_in_bits {
10256 u8 opcode[0x10];
10257 u8 reserved_at_10[0x10];
10258
10259 u8 reserved_at_20[0x10];
10260 u8 op_mod[0x10];
10261
10262 u8 reserved_at_40[0x40];
10263};
10264
10265struct mlx5_ifc_destroy_lag_out_bits {
10266 u8 status[0x8];
10267 u8 reserved_at_8[0x18];
10268
10269 u8 syndrome[0x20];
10270
10271 u8 reserved_at_40[0x40];
10272};
10273
10274struct mlx5_ifc_destroy_lag_in_bits {
10275 u8 opcode[0x10];
10276 u8 reserved_at_10[0x10];
10277
10278 u8 reserved_at_20[0x10];
10279 u8 op_mod[0x10];
10280
10281 u8 reserved_at_40[0x40];
10282};
10283
10284struct mlx5_ifc_create_vport_lag_out_bits {
10285 u8 status[0x8];
10286 u8 reserved_at_8[0x18];
10287
10288 u8 syndrome[0x20];
10289
10290 u8 reserved_at_40[0x40];
10291};
10292
10293struct mlx5_ifc_create_vport_lag_in_bits {
10294 u8 opcode[0x10];
10295 u8 reserved_at_10[0x10];
10296
10297 u8 reserved_at_20[0x10];
10298 u8 op_mod[0x10];
10299
10300 u8 reserved_at_40[0x40];
10301};
10302
10303struct mlx5_ifc_destroy_vport_lag_out_bits {
10304 u8 status[0x8];
10305 u8 reserved_at_8[0x18];
10306
10307 u8 syndrome[0x20];
10308
10309 u8 reserved_at_40[0x40];
10310};
10311
10312struct mlx5_ifc_destroy_vport_lag_in_bits {
10313 u8 opcode[0x10];
10314 u8 reserved_at_10[0x10];
10315
10316 u8 reserved_at_20[0x10];
10317 u8 op_mod[0x10];
10318
10319 u8 reserved_at_40[0x40];
10320};
10321
24da0016
AL		 10322struct mlx5_ifc_alloc_memic_in_bits {
10323 u8 opcode[0x10];
10324 u8 reserved_at_10[0x10];
10325
10326 u8 reserved_at_20[0x10];
10327 u8 op_mod[0x10];
10328
10329 u8 reserved_at_30[0x20];
10330
10331 u8 reserved_at_40[0x18];
10332 u8 log_memic_addr_alignment[0x8];
10333
10334 u8 range_start_addr[0x40];
10335
10336 u8 range_size[0x20];
10337
10338 u8 memic_size[0x20];
10339};
10340
10341struct mlx5_ifc_alloc_memic_out_bits {
10342 u8 status[0x8];
10343 u8 reserved_at_8[0x18];
10344
10345 u8 syndrome[0x20];
10346
10347 u8 memic_start_addr[0x40];
10348};
10349
10350struct mlx5_ifc_dealloc_memic_in_bits {
10351 u8 opcode[0x10];
10352 u8 reserved_at_10[0x10];
10353
10354 u8 reserved_at_20[0x10];
10355 u8 op_mod[0x10];
10356
10357 u8 reserved_at_40[0x40];
10358
10359 u8 memic_start_addr[0x40];
10360
10361 u8 memic_size[0x20];
10362
10363 u8 reserved_at_e0[0x20];
10364};
10365
10366struct mlx5_ifc_dealloc_memic_out_bits {
10367 u8 status[0x8];
10368 u8 reserved_at_8[0x18];
10369
10370 u8 syndrome[0x20];
10371
10372 u8 reserved_at_40[0x40];
10373};
10374
38b7ca92
YH		 10375struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10376 u8 opcode[0x10];
10377 u8 uid[0x10];
10378
1dd7382b 10379 u8 vhca_tunnel_id[0x10];
38b7ca92
YH		 10380 u8 obj_type[0x10];
10381
10382 u8 obj_id[0x20];
10383
10384 u8 reserved_at_60[0x20];
10385};
10386
10387struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10388 u8 status[0x8];
10389 u8 reserved_at_8[0x18];
10390
10391 u8 syndrome[0x20];
10392
10393 u8 obj_id[0x20];
10394
10395 u8 reserved_at_60[0x20];
10396};
10397
10398struct mlx5_ifc_umem_bits {
6e3722ba 10399 u8 reserved_at_0[0x80];
38b7ca92 10400
6e3722ba 10401 u8 reserved_at_80[0x1b];
38b7ca92
YH		 10402 u8 log_page_size[0x5];
10403
10404 u8 page_offset[0x20];
10405
10406 u8 num_of_mtt[0x40];
10407
b6ca09cb 10408 struct mlx5_ifc_mtt_bits mtt[];
38b7ca92
YH		 10409};
10410
10411struct mlx5_ifc_uctx_bits {
9d43faac
YH		 10412 u8 cap[0x20];
10413
6e3722ba 10414 u8 reserved_at_20[0x160];
38b7ca92
YH		 10415};
10416
9fba2b9b
AL		 10417struct mlx5_ifc_sw_icm_bits {
10418 u8 modify_field_select[0x40];
10419
10420 u8 reserved_at_40[0x18];
10421 u8 log_sw_icm_size[0x8];
10422
10423 u8 reserved_at_60[0x20];
10424
10425 u8 sw_icm_start_addr[0x40];
10426
10427 u8 reserved_at_c0[0x140];
91a40a48 10428};
b169e64a
YK		 10429
10430struct mlx5_ifc_geneve_tlv_option_bits {
10431 u8 modify_field_select[0x40];
10432
10433 u8 reserved_at_40[0x18];
10434 u8 geneve_option_fte_index[0x8];
10435
10436 u8 option_class[0x10];
10437 u8 option_type[0x8];
10438 u8 reserved_at_78[0x3];
10439 u8 option_data_length[0x5];
10440
10441 u8 reserved_at_80[0x180];
9fba2b9b
AL		 10442};
10443
38b7ca92 10444struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 10445 u8 opcode[0x10];
10446 u8 uid[0x10];
10447
10448 u8 reserved_at_20[0x10];
10449 u8 op_mod[0x10];
10450
10451 u8 reserved_at_40[0x40];
10452
10453 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 10454};
10455
8a06a79b
EC		 10456struct mlx5_ifc_create_umem_out_bits {
10457 u8 status[0x8];
10458 u8 reserved_at_8[0x18];
10459
10460 u8 syndrome[0x20];
10461
10462 u8 reserved_at_40[0x8];
10463 u8 umem_id[0x18];
10464
10465 u8 reserved_at_60[0x20];
10466};
10467
10468struct mlx5_ifc_destroy_umem_in_bits {
10469 u8 opcode[0x10];
10470 u8 uid[0x10];
10471
10472 u8 reserved_at_20[0x10];
10473 u8 op_mod[0x10];
10474
10475 u8 reserved_at_40[0x8];
10476 u8 umem_id[0x18];
10477
10478 u8 reserved_at_60[0x20];
10479};
10480
10481struct mlx5_ifc_destroy_umem_out_bits {
10482 u8 status[0x8];
10483 u8 reserved_at_8[0x18];
10484
10485 u8 syndrome[0x20];
10486
10487 u8 reserved_at_40[0x40];
10488};
10489
38b7ca92 10490struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 10491 u8 opcode[0x10];
10492 u8 reserved_at_10[0x10];
10493
10494 u8 reserved_at_20[0x10];
10495 u8 op_mod[0x10];
10496
10497 u8 reserved_at_40[0x40];
10498
10499 struct mlx5_ifc_uctx_bits uctx;
10500};
10501
8a06a79b
EC		 10502struct mlx5_ifc_create_uctx_out_bits {
10503 u8 status[0x8];
10504 u8 reserved_at_8[0x18];
10505
10506 u8 syndrome[0x20];
10507
10508 u8 reserved_at_40[0x10];
10509 u8 uid[0x10];
10510
10511 u8 reserved_at_60[0x20];
10512};
10513
6e3722ba
YH		 10514struct mlx5_ifc_destroy_uctx_in_bits {
10515 u8 opcode[0x10];
10516 u8 reserved_at_10[0x10];
10517
10518 u8 reserved_at_20[0x10];
10519 u8 op_mod[0x10];
10520
10521 u8 reserved_at_40[0x10];
10522 u8 uid[0x10];
10523
10524 u8 reserved_at_60[0x20];
38b7ca92
YH		 10525};
10526
8a06a79b
EC		 10527struct mlx5_ifc_destroy_uctx_out_bits {
10528 u8 status[0x8];
10529 u8 reserved_at_8[0x18];
10530
10531 u8 syndrome[0x20];
10532
10533 u8 reserved_at_40[0x40];
10534};
10535
9fba2b9b
AL		 10536struct mlx5_ifc_create_sw_icm_in_bits {
10537 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10538 struct mlx5_ifc_sw_icm_bits sw_icm;
10539};
10540
b169e64a
YK		 10541struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10542 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10543 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10544};
10545
eff8ea8f
FD		 10546struct mlx5_ifc_mtrc_string_db_param_bits {
10547 u8 string_db_base_address[0x20];
10548
10549 u8 reserved_at_20[0x8];
10550 u8 string_db_size[0x18];
10551};
10552
10553struct mlx5_ifc_mtrc_cap_bits {
10554 u8 trace_owner[0x1];
10555 u8 trace_to_memory[0x1];
10556 u8 reserved_at_2[0x4];
10557 u8 trc_ver[0x2];
10558 u8 reserved_at_8[0x14];
10559 u8 num_string_db[0x4];
10560
10561 u8 first_string_trace[0x8];
10562 u8 num_string_trace[0x8];
10563 u8 reserved_at_30[0x28];
10564
10565 u8 log_max_trace_buffer_size[0x8];
10566
10567 u8 reserved_at_60[0x20];
10568
10569 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10570
10571 u8 reserved_at_280[0x180];
10572};
10573
10574struct mlx5_ifc_mtrc_conf_bits {
10575 u8 reserved_at_0[0x1c];
10576 u8 trace_mode[0x4];
10577 u8 reserved_at_20[0x18];
10578 u8 log_trace_buffer_size[0x8];
10579 u8 trace_mkey[0x20];
10580 u8 reserved_at_60[0x3a0];
10581};
10582
10583struct mlx5_ifc_mtrc_stdb_bits {
10584 u8 string_db_index[0x4];
10585 u8 reserved_at_4[0x4];
10586 u8 read_size[0x18];
10587 u8 start_offset[0x20];
b6ca09cb 10588 u8 string_db_data[];
eff8ea8f
FD		 10589};
10590
10591struct mlx5_ifc_mtrc_ctrl_bits {
10592 u8 trace_status[0x2];
10593 u8 reserved_at_2[0x2];
10594 u8 arm_event[0x1];
10595 u8 reserved_at_5[0xb];
10596 u8 modify_field_select[0x10];
10597 u8 reserved_at_20[0x2b];
10598 u8 current_timestamp52_32[0x15];
10599 u8 current_timestamp31_0[0x20];
10600 u8 reserved_at_80[0x180];
10601};
10602
c3a4e9f1
BW		 10603struct mlx5_ifc_host_params_context_bits {
10604 u8 host_number[0x8];
5ccf2770
BW		 10605 u8 reserved_at_8[0x7];
10606 u8 host_pf_disabled[0x1];
c3a4e9f1
BW		 10607 u8 host_num_of_vfs[0x10];
10608
86eec50b 10609 u8 host_total_vfs[0x10];
c3a4e9f1
BW		 10610 u8 host_pci_bus[0x10];
10611
10612 u8 reserved_at_40[0x10];
10613 u8 host_pci_device[0x10];
10614
10615 u8 reserved_at_60[0x10];
10616 u8 host_pci_function[0x10];
10617
10618 u8 reserved_at_80[0x180];
10619};
10620
cd56f929 10621struct mlx5_ifc_query_esw_functions_in_bits {
c3a4e9f1
BW		 10622 u8 opcode[0x10];
10623 u8 reserved_at_10[0x10];
10624
10625 u8 reserved_at_20[0x10];
10626 u8 op_mod[0x10];
10627
10628 u8 reserved_at_40[0x40];
10629};
10630
cd56f929 10631struct mlx5_ifc_query_esw_functions_out_bits {
c3a4e9f1
BW		 10632 u8 status[0x8];
10633 u8 reserved_at_8[0x18];
10634
10635 u8 syndrome[0x20];
10636
10637 u8 reserved_at_40[0x40];
10638
10639 struct mlx5_ifc_host_params_context_bits host_params_context;
10640
10641 u8 reserved_at_280[0x180];
b6ca09cb 10642 u8 host_sf_enable[][0x40];
1759d322
PP		 10643};
10644
10645struct mlx5_ifc_sf_partition_bits {
10646 u8 reserved_at_0[0x10];
10647 u8 log_num_sf[0x8];
10648 u8 log_sf_bar_size[0x8];
10649};
10650
10651struct mlx5_ifc_query_sf_partitions_out_bits {
10652 u8 status[0x8];
10653 u8 reserved_at_8[0x18];
10654
10655 u8 syndrome[0x20];
10656
10657 u8 reserved_at_40[0x18];
10658 u8 num_sf_partitions[0x8];
10659
10660 u8 reserved_at_60[0x20];
10661
b6ca09cb 10662 struct mlx5_ifc_sf_partition_bits sf_partition[];
1759d322
PP		 10663};
10664
10665struct mlx5_ifc_query_sf_partitions_in_bits {
10666 u8 opcode[0x10];
10667 u8 reserved_at_10[0x10];
10668
10669 u8 reserved_at_20[0x10];
10670 u8 op_mod[0x10];
10671
10672 u8 reserved_at_40[0x40];
10673};
10674
10675struct mlx5_ifc_dealloc_sf_out_bits {
10676 u8 status[0x8];
10677 u8 reserved_at_8[0x18];
10678
10679 u8 syndrome[0x20];
10680
10681 u8 reserved_at_40[0x40];
10682};
10683
10684struct mlx5_ifc_dealloc_sf_in_bits {
10685 u8 opcode[0x10];
10686 u8 reserved_at_10[0x10];
10687
10688 u8 reserved_at_20[0x10];
10689 u8 op_mod[0x10];
10690
10691 u8 reserved_at_40[0x10];
10692 u8 function_id[0x10];
10693
10694 u8 reserved_at_60[0x20];
10695};
10696
10697struct mlx5_ifc_alloc_sf_out_bits {
10698 u8 status[0x8];
10699 u8 reserved_at_8[0x18];
10700
10701 u8 syndrome[0x20];
10702
10703 u8 reserved_at_40[0x40];
10704};
10705
10706struct mlx5_ifc_alloc_sf_in_bits {
10707 u8 opcode[0x10];
10708 u8 reserved_at_10[0x10];
10709
10710 u8 reserved_at_20[0x10];
10711 u8 op_mod[0x10];
10712
10713 u8 reserved_at_40[0x10];
10714 u8 function_id[0x10];
10715
10716 u8 reserved_at_60[0x20];
c3a4e9f1
BW		 10717};
10718
e4075c44
YH		 10719struct mlx5_ifc_affiliated_event_header_bits {
10720 u8 reserved_at_0[0x10];
10721 u8 obj_type[0x10];
10722
10723 u8 obj_id[0x20];
10724};
10725
a12ff35e 10726enum {
49e27134
PP		 10727 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
10728 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
10729 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
a12ff35e
EBE		 10730};
10731
10732enum {
10733 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
2b58f6d9 10734 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
2a297089 10735 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
2b58f6d9
RS		 10736};
10737
10738enum {
10739 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10740 MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10741 MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10742};
10743
10744struct mlx5_ifc_ipsec_obj_bits {
10745 u8 modify_field_select[0x40];
10746 u8 full_offload[0x1];
10747 u8 reserved_at_41[0x1];
10748 u8 esn_en[0x1];
10749 u8 esn_overlap[0x1];
10750 u8 reserved_at_44[0x2];
10751 u8 icv_length[0x2];
10752 u8 reserved_at_48[0x4];
10753 u8 aso_return_reg[0x4];
10754 u8 reserved_at_50[0x10];
10755
10756 u8 esn_msb[0x20];
10757
10758 u8 reserved_at_80[0x8];
10759 u8 dekn[0x18];
10760
10761 u8 salt[0x20];
10762
10763 u8 implicit_iv[0x40];
10764
10765 u8 reserved_at_100[0x700];
10766};
10767
10768struct mlx5_ifc_create_ipsec_obj_in_bits {
10769 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10770 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10771};
10772
10773enum {
10774 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10775 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10776};
10777
10778struct mlx5_ifc_query_ipsec_obj_out_bits {
10779 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10780 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10781};
10782
10783struct mlx5_ifc_modify_ipsec_obj_in_bits {
10784 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10785 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
a12ff35e
EBE		 10786};
10787
10788struct mlx5_ifc_encryption_key_obj_bits {
10789 u8 modify_field_select[0x40];
10790
10791 u8 reserved_at_40[0x14];
10792 u8 key_size[0x4];
10793 u8 reserved_at_58[0x4];
10794 u8 key_type[0x4];
10795
10796 u8 reserved_at_60[0x8];
10797 u8 pd[0x18];
10798
10799 u8 reserved_at_80[0x180];
10800 u8 key[8][0x20];
10801
10802 u8 reserved_at_300[0x500];
10803};
10804
10805struct mlx5_ifc_create_encryption_key_in_bits {
10806 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10807 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10808};
10809
2a297089
CM		 10810struct mlx5_ifc_sampler_obj_bits {
10811 u8 modify_field_select[0x40];
10812
10813 u8 table_type[0x8];
10814 u8 level[0x8];
10815 u8 reserved_at_50[0xf];
10816 u8 ignore_flow_level[0x1];
10817
10818 u8 sample_ratio[0x20];
10819
10820 u8 reserved_at_80[0x8];
10821 u8 sample_table_id[0x18];
10822
10823 u8 reserved_at_a0[0x8];
10824 u8 default_table_id[0x18];
10825
10826 u8 sw_steering_icm_address_rx[0x40];
10827 u8 sw_steering_icm_address_tx[0x40];
10828
10829 u8 reserved_at_140[0xa0];
10830};
10831
10832struct mlx5_ifc_create_sampler_obj_in_bits {
10833 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10834 struct mlx5_ifc_sampler_obj_bits sampler_object;
10835};
10836
a12ff35e
EBE		 10837enum {
10838 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10839 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10840};
10841
10842enum {
bd673da6
SM		 10843 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10844 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
a12ff35e
EBE		 10845};
10846
10847struct mlx5_ifc_tls_static_params_bits {
10848 u8 const_2[0x2];
10849 u8 tls_version[0x4];
10850 u8 const_1[0x2];
10851 u8 reserved_at_8[0x14];
10852 u8 encryption_standard[0x4];
10853
10854 u8 reserved_at_20[0x20];
10855
10856 u8 initial_record_number[0x40];
10857
10858 u8 resync_tcp_sn[0x20];
10859
10860 u8 gcm_iv[0x20];
10861
10862 u8 implicit_iv[0x40];
10863
10864 u8 reserved_at_100[0x8];
10865 u8 dek_index[0x18];
10866
10867 u8 reserved_at_120[0xe0];
10868};
10869
10870struct mlx5_ifc_tls_progress_params_bits {
a12ff35e
EBE		 10871 u8 next_record_tcp_sn[0x20];
10872
10873 u8 hw_resync_tcp_sn[0x20];
10874
10875 u8 record_tracker_state[0x2];
10876 u8 auth_state[0x2];
2d1b69ed 10877 u8 reserved_at_44[0x4];
a12ff35e
EBE		 10878 u8 hw_offset_record_number[0x18];
10879};
10880
1dcb6c36
EC		 10881enum {
10882 MLX5_MTT_PERM_READ = 1 << 0,
10883 MLX5_MTT_PERM_WRITE = 1 << 1,
10884 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
10885};
10886
d29b796a 10887#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)