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net/mlx5: Add XRC transport to ODP device capabilities layout
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
66enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71};
72
f91e6d89
EBE		 73enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
76};
77
38b7ca92 78enum {
2acc7957 79 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 80};
81
d29b796a
EC		 82enum {
83 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
84 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
85 MLX5_CMD_OP_INIT_HCA = 0x102,
86 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
87 MLX5_CMD_OP_ENABLE_HCA = 0x104,
88 MLX5_CMD_OP_DISABLE_HCA = 0x105,
89 MLX5_CMD_OP_QUERY_PAGES = 0x107,
90 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
91 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 92 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
93 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 94 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 95 MLX5_CMD_OP_CREATE_MKEY = 0x200,
96 MLX5_CMD_OP_QUERY_MKEY = 0x201,
97 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
98 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
99 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 100 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
101 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 102 MLX5_CMD_OP_CREATE_EQ = 0x301,
103 MLX5_CMD_OP_DESTROY_EQ = 0x302,
104 MLX5_CMD_OP_QUERY_EQ = 0x303,
105 MLX5_CMD_OP_GEN_EQE = 0x304,
106 MLX5_CMD_OP_CREATE_CQ = 0x400,
107 MLX5_CMD_OP_DESTROY_CQ = 0x401,
108 MLX5_CMD_OP_QUERY_CQ = 0x402,
109 MLX5_CMD_OP_MODIFY_CQ = 0x403,
110 MLX5_CMD_OP_CREATE_QP = 0x500,
111 MLX5_CMD_OP_DESTROY_QP = 0x501,
112 MLX5_CMD_OP_RST2INIT_QP = 0x502,
113 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
114 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
115 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
116 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
117 MLX5_CMD_OP_2ERR_QP = 0x507,
118 MLX5_CMD_OP_2RST_QP = 0x50a,
119 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 120 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 121 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
122 MLX5_CMD_OP_CREATE_PSV = 0x600,
123 MLX5_CMD_OP_DESTROY_PSV = 0x601,
124 MLX5_CMD_OP_CREATE_SRQ = 0x700,
125 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
126 MLX5_CMD_OP_QUERY_SRQ = 0x702,
127 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 128 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
129 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
130 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
131 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 132 MLX5_CMD_OP_CREATE_DCT = 0x710,
133 MLX5_CMD_OP_DESTROY_DCT = 0x711,
134 MLX5_CMD_OP_DRAIN_DCT = 0x712,
135 MLX5_CMD_OP_QUERY_DCT = 0x713,
136 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 137 MLX5_CMD_OP_CREATE_XRQ = 0x717,
138 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
139 MLX5_CMD_OP_QUERY_XRQ = 0x719,
140 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 141 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
142 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
143 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
d29b796a
EC		 144 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
145 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
146 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
147 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
148 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
149 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 150 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 151 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 152 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
153 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
154 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
155 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 156 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 157 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
158 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
159 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
160 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 161 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
162 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 163 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 164 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 165 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
166 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
167 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
168 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
169 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
170 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 171 MLX5_CMD_OP_ALLOC_PD = 0x800,
172 MLX5_CMD_OP_DEALLOC_PD = 0x801,
173 MLX5_CMD_OP_ALLOC_UAR = 0x802,
174 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
175 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
176 MLX5_CMD_OP_ACCESS_REG = 0x805,
177 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 178 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 179 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
180 MLX5_CMD_OP_MAD_IFC = 0x50d,
181 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
182 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
183 MLX5_CMD_OP_NOP = 0x80d,
184 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
185 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 186 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
187 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
188 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
189 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
190 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
191 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
192 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
193 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
194 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
195 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
196 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
197 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 198 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
199 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 200 MLX5_CMD_OP_CREATE_LAG = 0x840,
201 MLX5_CMD_OP_MODIFY_LAG = 0x841,
202 MLX5_CMD_OP_QUERY_LAG = 0x842,
203 MLX5_CMD_OP_DESTROY_LAG = 0x843,
204 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
205 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 206 MLX5_CMD_OP_CREATE_TIR = 0x900,
207 MLX5_CMD_OP_MODIFY_TIR = 0x901,
208 MLX5_CMD_OP_DESTROY_TIR = 0x902,
209 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 210 MLX5_CMD_OP_CREATE_SQ = 0x904,
211 MLX5_CMD_OP_MODIFY_SQ = 0x905,
212 MLX5_CMD_OP_DESTROY_SQ = 0x906,
213 MLX5_CMD_OP_QUERY_SQ = 0x907,
214 MLX5_CMD_OP_CREATE_RQ = 0x908,
215 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 216 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 217 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
218 MLX5_CMD_OP_QUERY_RQ = 0x90b,
219 MLX5_CMD_OP_CREATE_RMP = 0x90c,
220 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
221 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
222 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 223 MLX5_CMD_OP_CREATE_TIS = 0x912,
224 MLX5_CMD_OP_MODIFY_TIS = 0x913,
225 MLX5_CMD_OP_DESTROY_TIS = 0x914,
226 MLX5_CMD_OP_QUERY_TIS = 0x915,
227 MLX5_CMD_OP_CREATE_RQT = 0x916,
228 MLX5_CMD_OP_MODIFY_RQT = 0x917,
229 MLX5_CMD_OP_DESTROY_RQT = 0x918,
230 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 231 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 232 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
233 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
234 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
235 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
236 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
237 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
238 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
239 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 240 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
242 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
243 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 244 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 245 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
246 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 247 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 260 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
261 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
262 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
263 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
86d56a1a 264 MLX5_CMD_OP_MAX
e281682b
SM		 265};
266
719598c9
YH		 267/* Valid range for general commands that don't work over an object */
268enum {
269 MLX5_CMD_OP_GENERAL_START = 0xb00,
270 MLX5_CMD_OP_GENERAL_END = 0xd00,
271};
272
e281682b
SM		 273struct mlx5_ifc_flow_table_fields_supported_bits {
274 u8 outer_dmac[0x1];
275 u8 outer_smac[0x1];
276 u8 outer_ether_type[0x1];
19cc7524 277 u8 outer_ip_version[0x1];
e281682b
SM		 278 u8 outer_first_prio[0x1];
279 u8 outer_first_cfi[0x1];
280 u8 outer_first_vid[0x1];
a8ade55f 281 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 282 u8 outer_second_prio[0x1];
283 u8 outer_second_cfi[0x1];
284 u8 outer_second_vid[0x1];
b4ff3a36 285 u8 reserved_at_b[0x1];
e281682b
SM		 286 u8 outer_sip[0x1];
287 u8 outer_dip[0x1];
288 u8 outer_frag[0x1];
289 u8 outer_ip_protocol[0x1];
290 u8 outer_ip_ecn[0x1];
291 u8 outer_ip_dscp[0x1];
292 u8 outer_udp_sport[0x1];
293 u8 outer_udp_dport[0x1];
294 u8 outer_tcp_sport[0x1];
295 u8 outer_tcp_dport[0x1];
296 u8 outer_tcp_flags[0x1];
297 u8 outer_gre_protocol[0x1];
298 u8 outer_gre_key[0x1];
299 u8 outer_vxlan_vni[0x1];
b4ff3a36 300 u8 reserved_at_1a[0x5];
e281682b
SM		 301 u8 source_eswitch_port[0x1];
302
303 u8 inner_dmac[0x1];
304 u8 inner_smac[0x1];
305 u8 inner_ether_type[0x1];
19cc7524 306 u8 inner_ip_version[0x1];
e281682b
SM		 307 u8 inner_first_prio[0x1];
308 u8 inner_first_cfi[0x1];
309 u8 inner_first_vid[0x1];
b4ff3a36 310 u8 reserved_at_27[0x1];
e281682b
SM		 311 u8 inner_second_prio[0x1];
312 u8 inner_second_cfi[0x1];
313 u8 inner_second_vid[0x1];
b4ff3a36 314 u8 reserved_at_2b[0x1];
e281682b
SM		 315 u8 inner_sip[0x1];
316 u8 inner_dip[0x1];
317 u8 inner_frag[0x1];
318 u8 inner_ip_protocol[0x1];
319 u8 inner_ip_ecn[0x1];
320 u8 inner_ip_dscp[0x1];
321 u8 inner_udp_sport[0x1];
322 u8 inner_udp_dport[0x1];
323 u8 inner_tcp_sport[0x1];
324 u8 inner_tcp_dport[0x1];
325 u8 inner_tcp_flags[0x1];
b4ff3a36 326 u8 reserved_at_37[0x9];
71c6e863
AL		 327
328 u8 reserved_at_40[0x5];
329 u8 outer_first_mpls_over_udp[0x4];
330 u8 outer_first_mpls_over_gre[0x4];
331 u8 inner_first_mpls[0x4];
332 u8 outer_first_mpls[0x4];
333 u8 reserved_at_55[0x2];
3346c487 334 u8 outer_esp_spi[0x1];
71c6e863 335 u8 reserved_at_58[0x2];
a550ddfc 336 u8 bth_dst_qp[0x1];
e281682b 337
a550ddfc 338 u8 reserved_at_5b[0x25];
e281682b
SM		 339};
340
341struct mlx5_ifc_flow_table_prop_layout_bits {
342 u8 ft_support[0x1];
9dc0b289
AV		 343 u8 reserved_at_1[0x1];
344 u8 flow_counter[0x1];
26a81453 345 u8 flow_modify_en[0x1];
2cc43b49 346 u8 modify_root[0x1];
34a40e68
MG		 347 u8 identified_miss_table_mode[0x1];
348 u8 flow_table_modify[0x1];
60786f09 349 u8 reformat[0x1];
7adbde20 350 u8 decap[0x1];
0c06897a
OG		 351 u8 reserved_at_9[0x1];
352 u8 pop_vlan[0x1];
353 u8 push_vlan[0x1];
8da6fe2a
JL		 354 u8 reserved_at_c[0x1];
355 u8 pop_vlan_2[0x1];
356 u8 push_vlan_2[0x1];
bea4e1f6
MB		 357 u8 reformat_and_vlan_action[0x1];
358 u8 reserved_at_10[0x2];
359 u8 reformat_l3_tunnel_to_l2[0x1];
360 u8 reformat_l2_to_l3_tunnel[0x1];
361 u8 reformat_and_modify_action[0x1];
c74d90c1 362 u8 reserved_at_15[0xb];
b4ff3a36 363 u8 reserved_at_20[0x2];
e281682b 364 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 365 u8 log_max_modify_header_context[0x8];
366 u8 max_modify_header_actions[0x8];
e281682b
SM		 367 u8 max_ft_level[0x8];
368
b4ff3a36 369 u8 reserved_at_40[0x20];
e281682b 370
b4ff3a36 371 u8 reserved_at_60[0x18];
e281682b
SM		 372 u8 log_max_ft_num[0x8];
373
b4ff3a36 374 u8 reserved_at_80[0x18];
e281682b
SM		 375 u8 log_max_destination[0x8];
376
16f1c5bb
RS		 377 u8 log_max_flow_counter[0x8];
378 u8 reserved_at_a8[0x10];
e281682b
SM		 379 u8 log_max_flow[0x8];
380
b4ff3a36 381 u8 reserved_at_c0[0x40];
e281682b
SM		 382
383 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
384
385 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
386};
387
388struct mlx5_ifc_odp_per_transport_service_cap_bits {
389 u8 send[0x1];
390 u8 receive[0x1];
391 u8 write[0x1];
392 u8 read[0x1];
17d2f88f 393 u8 atomic[0x1];
e281682b 394 u8 srq_receive[0x1];
b4ff3a36 395 u8 reserved_at_6[0x1a];
e281682b
SM		 396};
397
398struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
399 u8 smac_47_16[0x20];
400
401 u8 smac_15_0[0x10];
402 u8 ethertype[0x10];
403
404 u8 dmac_47_16[0x20];
405
406 u8 dmac_15_0[0x10];
407 u8 first_prio[0x3];
408 u8 first_cfi[0x1];
409 u8 first_vid[0xc];
410
411 u8 ip_protocol[0x8];
412 u8 ip_dscp[0x6];
413 u8 ip_ecn[0x2];
10543365
MHY		 414 u8 cvlan_tag[0x1];
415 u8 svlan_tag[0x1];
e281682b 416 u8 frag[0x1];
19cc7524 417 u8 ip_version[0x4];
e281682b
SM		 418 u8 tcp_flags[0x9];
419
420 u8 tcp_sport[0x10];
421 u8 tcp_dport[0x10];
422
a8ade55f
OG		 423 u8 reserved_at_c0[0x18];
424 u8 ttl_hoplimit[0x8];
e281682b
SM		 425
426 u8 udp_sport[0x10];
427 u8 udp_dport[0x10];
428
b4d1f032 429 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 430
b4d1f032 431 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 432};
433
5886a96a
OS		 434struct mlx5_ifc_nvgre_key_bits {
435 u8 hi[0x18];
436 u8 lo[0x8];
437};
438
439union mlx5_ifc_gre_key_bits {
440 struct mlx5_ifc_nvgre_key_bits nvgre;
441 u8 key[0x20];
442};
443
e281682b 444struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 445 u8 reserved_at_0[0x8];
446 u8 source_sqn[0x18];
e281682b 447
3e99df87 448 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 449 u8 source_port[0x10];
450
451 u8 outer_second_prio[0x3];
452 u8 outer_second_cfi[0x1];
453 u8 outer_second_vid[0xc];
454 u8 inner_second_prio[0x3];
455 u8 inner_second_cfi[0x1];
456 u8 inner_second_vid[0xc];
457
10543365
MHY		 458 u8 outer_second_cvlan_tag[0x1];
459 u8 inner_second_cvlan_tag[0x1];
460 u8 outer_second_svlan_tag[0x1];
461 u8 inner_second_svlan_tag[0x1];
462 u8 reserved_at_64[0xc];
e281682b
SM		 463 u8 gre_protocol[0x10];
464
5886a96a 465 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 466
467 u8 vxlan_vni[0x18];
b4ff3a36 468 u8 reserved_at_b8[0x8];
e281682b 469
b4ff3a36 470 u8 reserved_at_c0[0x20];
e281682b 471
b4ff3a36 472 u8 reserved_at_e0[0xc];
e281682b
SM		 473 u8 outer_ipv6_flow_label[0x14];
474
b4ff3a36 475 u8 reserved_at_100[0xc];
e281682b
SM		 476 u8 inner_ipv6_flow_label[0x14];
477
a550ddfc
YH		 478 u8 reserved_at_120[0x28];
479 u8 bth_dst_qp[0x18];
3346c487
BP		 480 u8 reserved_at_160[0x20];
481 u8 outer_esp_spi[0x20];
482 u8 reserved_at_1a0[0x60];
e281682b
SM		 483};
484
71c6e863
AL		 485struct mlx5_ifc_fte_match_mpls_bits {
486 u8 mpls_label[0x14];
487 u8 mpls_exp[0x3];
488 u8 mpls_s_bos[0x1];
489 u8 mpls_ttl[0x8];
490};
491
492struct mlx5_ifc_fte_match_set_misc2_bits {
493 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
494
495 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
496
497 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
498
499 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
500
501 u8 reserved_at_80[0x100];
502
503 u8 metadata_reg_a[0x20];
504
505 u8 reserved_at_1a0[0x60];
506};
507
e281682b
SM		 508struct mlx5_ifc_cmd_pas_bits {
509 u8 pa_h[0x20];
510
511 u8 pa_l[0x14];
b4ff3a36 512 u8 reserved_at_34[0xc];
e281682b
SM		 513};
514
515struct mlx5_ifc_uint64_bits {
516 u8 hi[0x20];
517
518 u8 lo[0x20];
519};
520
521enum {
522 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
523 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
524 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
525 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
526 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
527 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
528 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
529 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
530 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
531 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
532};
533
534struct mlx5_ifc_ads_bits {
535 u8 fl[0x1];
536 u8 free_ar[0x1];
b4ff3a36 537 u8 reserved_at_2[0xe];
e281682b
SM		 538 u8 pkey_index[0x10];
539
b4ff3a36 540 u8 reserved_at_20[0x8];
e281682b
SM		 541 u8 grh[0x1];
542 u8 mlid[0x7];
543 u8 rlid[0x10];
544
545 u8 ack_timeout[0x5];
b4ff3a36 546 u8 reserved_at_45[0x3];
e281682b 547 u8 src_addr_index[0x8];
b4ff3a36 548 u8 reserved_at_50[0x4];
e281682b
SM		 549 u8 stat_rate[0x4];
550 u8 hop_limit[0x8];
551
b4ff3a36 552 u8 reserved_at_60[0x4];
e281682b
SM		 553 u8 tclass[0x8];
554 u8 flow_label[0x14];
555
556 u8 rgid_rip[16][0x8];
557
b4ff3a36 558 u8 reserved_at_100[0x4];
e281682b
SM		 559 u8 f_dscp[0x1];
560 u8 f_ecn[0x1];
b4ff3a36 561 u8 reserved_at_106[0x1];
e281682b
SM		 562 u8 f_eth_prio[0x1];
563 u8 ecn[0x2];
564 u8 dscp[0x6];
565 u8 udp_sport[0x10];
566
567 u8 dei_cfi[0x1];
568 u8 eth_prio[0x3];
569 u8 sl[0x4];
32f69e4b 570 u8 vhca_port_num[0x8];
e281682b
SM		 571 u8 rmac_47_32[0x10];
572
573 u8 rmac_31_0[0x20];
574};
575
576struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 577 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 578 u8 nic_rx_multi_path_tirs_fts[0x1];
579 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
bea4e1f6
MB		 580 u8 reserved_at_3[0x1d];
581 u8 encap_general_header[0x1];
582 u8 reserved_at_21[0xa];
583 u8 log_max_packet_reformat_context[0x5];
584 u8 reserved_at_30[0x6];
585 u8 max_encap_header_size[0xa];
586 u8 reserved_at_40[0x1c0];
e281682b
SM		 587
588 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
589
b4ff3a36 590 u8 reserved_at_400[0x200];
e281682b
SM		 591
592 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
593
594 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
595
b4ff3a36 596 u8 reserved_at_a00[0x200];
e281682b
SM		 597
598 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
599
b4ff3a36 600 u8 reserved_at_e00[0x7200];
e281682b
SM		 601};
602
495716b1 603struct mlx5_ifc_flow_table_eswitch_cap_bits {
663f146f 604 u8 reserved_at_0[0x1a];
b9aa0ba1 605 u8 multi_fdb_encap[0x1];
663f146f
VP		 606 u8 reserved_at_1b[0x1];
607 u8 fdb_multi_path_to_table[0x1];
608 u8 reserved_at_1d[0x3];
609
610 u8 reserved_at_20[0x1e0];
495716b1
SM		 611
612 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
613
614 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
615
616 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
617
b4ff3a36 618 u8 reserved_at_800[0x7800];
495716b1
SM		 619};
620
8bb957d2
SK		 621enum {
622 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
623 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
624};
625
d6666753
SM		 626struct mlx5_ifc_e_switch_cap_bits {
627 u8 vport_svlan_strip[0x1];
628 u8 vport_cvlan_strip[0x1];
629 u8 vport_svlan_insert[0x1];
630 u8 vport_cvlan_insert_if_not_exist[0x1];
631 u8 vport_cvlan_insert_overwrite[0x1];
8bb957d2
SK		 632 u8 reserved_at_5[0x17];
633 u8 counter_eswitch_affinity[0x1];
a6d04569 634 u8 merged_eswitch[0x1];
23898c76
NO		 635 u8 nic_vport_node_guid_modify[0x1];
636 u8 nic_vport_port_guid_modify[0x1];
d6666753 637
7adbde20
HHZ		 638 u8 vxlan_encap_decap[0x1];
639 u8 nvgre_encap_decap[0x1];
1b115498
EB		 640 u8 reserved_at_22[0x1];
641 u8 log_max_fdb_encap_uplink[0x5];
642 u8 reserved_at_21[0x3];
60786f09 643 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 644 u8 reserved_2b[0x6];
645 u8 max_encap_header_size[0xa];
646
647 u8 reserved_40[0x7c0];
648
d6666753
SM		 649};
650
7486216b
SM		 651struct mlx5_ifc_qos_cap_bits {
652 u8 packet_pacing[0x1];
813f8540 653 u8 esw_scheduling[0x1];
c9497c98
MHY		 654 u8 esw_bw_share[0x1];
655 u8 esw_rate_limit[0x1];
05d3ac97
BW		 656 u8 reserved_at_4[0x1];
657 u8 packet_pacing_burst_bound[0x1];
658 u8 packet_pacing_typical_size[0x1];
659 u8 reserved_at_7[0x19];
813f8540
MHY		 660
661 u8 reserved_at_20[0x20];
662
7486216b 663 u8 packet_pacing_max_rate[0x20];
813f8540 664
7486216b 665 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 666
667 u8 reserved_at_80[0x10];
7486216b 668 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 669
670 u8 esw_element_type[0x10];
671 u8 esw_tsar_type[0x10];
672
673 u8 reserved_at_c0[0x10];
674 u8 max_qos_para_vport[0x10];
675
676 u8 max_tsar_bw_share[0x20];
677
678 u8 reserved_at_100[0x700];
7486216b
SM		 679};
680
2fcb12df
IK		 681struct mlx5_ifc_debug_cap_bits {
682 u8 reserved_at_0[0x20];
683
684 u8 reserved_at_20[0x2];
685 u8 stall_detect[0x1];
686 u8 reserved_at_23[0x1d];
687
688 u8 reserved_at_40[0x7c0];
689};
690
e281682b
SM		 691struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
692 u8 csum_cap[0x1];
693 u8 vlan_cap[0x1];
694 u8 lro_cap[0x1];
695 u8 lro_psh_flag[0x1];
696 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 697 u8 reserved_at_5[0x2];
698 u8 wqe_vlan_insert[0x1];
66189961 699 u8 self_lb_en_modifiable[0x1];
b4ff3a36 700 u8 reserved_at_9[0x2];
e281682b 701 u8 max_lso_cap[0x5];
c226dc22 702 u8 multi_pkt_send_wqe[0x2];
cff92d7c 703 u8 wqe_inline_mode[0x2];
e281682b 704 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 705 u8 reg_umr_sq[0x1];
706 u8 scatter_fcs[0x1];
050da902 707 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 708 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 709 u8 reserved_at_1c[0x2];
27299841 710 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 711 u8 tunnel_stateless_vxlan[0x1];
712
547eede0
IT		 713 u8 swp[0x1];
714 u8 swp_csum[0x1];
715 u8 swp_lso[0x1];
22a65aa8
GP		 716 u8 reserved_at_23[0xd];
717 u8 max_vxlan_udp_ports[0x8];
718 u8 reserved_at_38[0x6];
4d350f1f
MG		 719 u8 max_geneve_opt_len[0x1];
720 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 721
b4ff3a36 722 u8 reserved_at_40[0x10];
e281682b
SM		 723 u8 lro_min_mss_size[0x10];
724
b4ff3a36 725 u8 reserved_at_60[0x120];
e281682b
SM		 726
727 u8 lro_timer_supported_periods[4][0x20];
728
b4ff3a36 729 u8 reserved_at_200[0x600];
e281682b
SM		 730};
731
732struct mlx5_ifc_roce_cap_bits {
733 u8 roce_apm[0x1];
b4ff3a36 734 u8 reserved_at_1[0x1f];
e281682b 735
b4ff3a36 736 u8 reserved_at_20[0x60];
e281682b 737
b4ff3a36 738 u8 reserved_at_80[0xc];
e281682b 739 u8 l3_type[0x4];
b4ff3a36 740 u8 reserved_at_90[0x8];
e281682b
SM		 741 u8 roce_version[0x8];
742
b4ff3a36 743 u8 reserved_at_a0[0x10];
e281682b
SM		 744 u8 r_roce_dest_udp_port[0x10];
745
746 u8 r_roce_max_src_udp_port[0x10];
747 u8 r_roce_min_src_udp_port[0x10];
748
b4ff3a36 749 u8 reserved_at_e0[0x10];
e281682b
SM		 750 u8 roce_address_table_size[0x10];
751
b4ff3a36 752 u8 reserved_at_100[0x700];
e281682b
SM		 753};
754
e72bd817
AL		 755struct mlx5_ifc_device_mem_cap_bits {
756 u8 memic[0x1];
757 u8 reserved_at_1[0x1f];
758
759 u8 reserved_at_20[0xb];
760 u8 log_min_memic_alloc_size[0x5];
761 u8 reserved_at_30[0x8];
762 u8 log_max_memic_addr_alignment[0x8];
763
764 u8 memic_bar_start_addr[0x40];
765
766 u8 memic_bar_size[0x20];
767
768 u8 max_memic_size[0x20];
769
770 u8 reserved_at_c0[0x740];
771};
772
e281682b
SM		 773enum {
774 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
775 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
776 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
777 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
778 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
779 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
780 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
781 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
782 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
783};
784
785enum {
786 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
787 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
788 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
789 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
790 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
791 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
792 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
793 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
794 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
795};
796
797struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 798 u8 reserved_at_0[0x40];
e281682b 799
bd10838a 800 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 801 u8 reserved_at_42[0x4];
bd10838a 802 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 803
b4ff3a36 804 u8 reserved_at_47[0x19];
e281682b 805
b4ff3a36 806 u8 reserved_at_60[0x20];
e281682b 807
b4ff3a36 808 u8 reserved_at_80[0x10];
f91e6d89 809 u8 atomic_operations[0x10];
e281682b 810
b4ff3a36 811 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 812 u8 atomic_size_qp[0x10];
813
b4ff3a36 814 u8 reserved_at_c0[0x10];
e281682b
SM		 815 u8 atomic_size_dc[0x10];
816
b4ff3a36 817 u8 reserved_at_e0[0x720];
e281682b
SM		 818};
819
820struct mlx5_ifc_odp_cap_bits {
b4ff3a36 821 u8 reserved_at_0[0x40];
e281682b
SM		 822
823 u8 sig[0x1];
b4ff3a36 824 u8 reserved_at_41[0x1f];
e281682b 825
b4ff3a36 826 u8 reserved_at_60[0x20];
e281682b
SM		 827
828 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
829
830 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
831
832 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
833
dda7a817
MS		 834 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
835
836 u8 reserved_at_100[0x700];
e281682b
SM		 837};
838
3f0393a5
SG		 839struct mlx5_ifc_calc_op {
840 u8 reserved_at_0[0x10];
841 u8 reserved_at_10[0x9];
842 u8 op_swap_endianness[0x1];
843 u8 op_min[0x1];
844 u8 op_xor[0x1];
845 u8 op_or[0x1];
846 u8 op_and[0x1];
847 u8 op_max[0x1];
848 u8 op_add[0x1];
849};
850
851struct mlx5_ifc_vector_calc_cap_bits {
852 u8 calc_matrix[0x1];
853 u8 reserved_at_1[0x1f];
854 u8 reserved_at_20[0x8];
855 u8 max_vec_count[0x8];
856 u8 reserved_at_30[0xd];
857 u8 max_chunk_size[0x3];
858 struct mlx5_ifc_calc_op calc0;
859 struct mlx5_ifc_calc_op calc1;
860 struct mlx5_ifc_calc_op calc2;
861 struct mlx5_ifc_calc_op calc3;
862
c74d90c1 863 u8 reserved_at_c0[0x720];
3f0393a5
SG		 864};
865
e281682b
SM		 866enum {
867 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
868 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 869 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 870 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 871};
872
873enum {
874 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
875 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
876};
877
878enum {
879 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
880 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
881 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
882 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
883 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
884};
885
886enum {
887 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
888 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
889 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
890 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
891 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
892 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
893};
894
895enum {
896 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
897 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
898};
899
900enum {
901 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
902 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
903 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
904};
905
906enum {
907 MLX5_CAP_PORT_TYPE_IB = 0x0,
908 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 909};
910
1410a90a
MG		 911enum {
912 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
913 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
914 MLX5_CAP_UMR_FENCE_NONE = 0x2,
915};
916
9d43faac
YH		 917enum {
918 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
919};
920
b775516b 921struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 922 u8 reserved_at_0[0x30];
923 u8 vhca_id[0x10];
924
925 u8 reserved_at_40[0x40];
b775516b
EC		 926
927 u8 log_max_srq_sz[0x8];
928 u8 log_max_qp_sz[0x8];
b4ff3a36 929 u8 reserved_at_90[0xb];
b775516b
EC		 930 u8 log_max_qp[0x5];
931
b4ff3a36 932 u8 reserved_at_a0[0xb];
e281682b 933 u8 log_max_srq[0x5];
b4ff3a36 934 u8 reserved_at_b0[0x10];
b775516b 935
b4ff3a36 936 u8 reserved_at_c0[0x8];
b775516b 937 u8 log_max_cq_sz[0x8];
b4ff3a36 938 u8 reserved_at_d0[0xb];
b775516b
EC		 939 u8 log_max_cq[0x5];
940
941 u8 log_max_eq_sz[0x8];
b4ff3a36 942 u8 reserved_at_e8[0x2];
b775516b 943 u8 log_max_mkey[0x6];
b183ee27
LR		 944 u8 reserved_at_f0[0x8];
945 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 946 u8 reserved_at_f9[0x2];
947 u8 fast_teardown[0x1];
b775516b
EC		 948 u8 log_max_eq[0x4];
949
950 u8 max_indirection[0x8];
bcda1aca 951 u8 fixed_buffer_size[0x1];
b775516b 952 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 953 u8 force_teardown[0x1];
954 u8 reserved_at_111[0x1];
b775516b 955 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 956 u8 umr_extended_translation_offset[0x1];
957 u8 null_mkey[0x1];
b775516b
EC		 958 u8 log_max_klm_list_size[0x6];
959
b4ff3a36 960 u8 reserved_at_120[0xa];
b775516b 961 u8 log_max_ra_req_dc[0x6];
b4ff3a36 962 u8 reserved_at_130[0xa];
b775516b
EC		 963 u8 log_max_ra_res_dc[0x6];
964
b4ff3a36 965 u8 reserved_at_140[0xa];
b775516b 966 u8 log_max_ra_req_qp[0x6];
b4ff3a36 967 u8 reserved_at_150[0xa];
b775516b
EC		 968 u8 log_max_ra_res_qp[0x6];
969
f32f5bd2 970 u8 end_pad[0x1];
b775516b
EC		 971 u8 cc_query_allowed[0x1];
972 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 973 u8 start_pad[0x1];
974 u8 cache_line_128byte[0x1];
c02762eb
HN		 975 u8 reserved_at_165[0xa];
976 u8 qcam_reg[0x1];
e281682b 977 u8 gid_table_size[0x10];
b775516b 978
e281682b
SM		 979 u8 out_of_seq_cnt[0x1];
980 u8 vport_counters[0x1];
7486216b 981 u8 retransmission_q_counters[0x1];
2fcb12df 982 u8 debug[0x1];
83b502a1 983 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 984 u8 rq_delay_drop[0x1];
b775516b
EC		 985 u8 max_qp_cnt[0xa];
986 u8 pkey_table_size[0x10];
987
e281682b
SM		 988 u8 vport_group_manager[0x1];
989 u8 vhca_group_manager[0x1];
990 u8 ib_virt[0x1];
991 u8 eth_virt[0x1];
61c5b5c9 992 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 993 u8 ets[0x1];
994 u8 nic_flow_table[0x1];
0efc8562 995 u8 eswitch_manager[0x1];
e72bd817 996 u8 device_memory[0x1];
cfdcbcea
GP		 997 u8 mcam_reg[0x1];
998 u8 pcam_reg[0x1];
b775516b 999 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1000 u8 port_module_event[0x1];
58dcb60a 1001 u8 enhanced_error_q_counters[0x1];
7d5e1423 1002 u8 ports_check[0x1];
7b13558f 1003 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1004 u8 disable_link_up[0x1];
1005 u8 beacon_led[0x1];
e281682b 1006 u8 port_type[0x2];
b775516b
EC		 1007 u8 num_ports[0x8];
1008
f9a1ef72
EE		 1009 u8 reserved_at_1c0[0x1];
1010 u8 pps[0x1];
1011 u8 pps_modify[0x1];
b775516b 1012 u8 log_max_msg[0x5];
e1c9c62b 1013 u8 reserved_at_1c8[0x4];
4f3961ee 1014 u8 max_tc[0x4];
1865ea9a 1015 u8 temp_warn_event[0x1];
7486216b 1016 u8 dcbx[0x1];
246ac981
MG		 1017 u8 general_notification_event[0x1];
1018 u8 reserved_at_1d3[0x2];
e29341fb 1019 u8 fpga[0x1];
928cfe87
TT		 1020 u8 rol_s[0x1];
1021 u8 rol_g[0x1];
e1c9c62b 1022 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1023 u8 wol_s[0x1];
1024 u8 wol_g[0x1];
1025 u8 wol_a[0x1];
1026 u8 wol_b[0x1];
1027 u8 wol_m[0x1];
1028 u8 wol_u[0x1];
1029 u8 wol_p[0x1];
b775516b
EC		 1030
1031 u8 stat_rate_support[0x10];
e1c9c62b 1032 u8 reserved_at_1f0[0xc];
e281682b 1033 u8 cqe_version[0x4];
b775516b 1034
e281682b 1035 u8 compact_address_vector[0x1];
7d5e1423 1036 u8 striding_rq[0x1];
500a3d0d
ES		 1037 u8 reserved_at_202[0x1];
1038 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1039 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1040 u8 reserved_at_205[0x1];
1041 u8 repeated_block_disabled[0x1];
1042 u8 umr_modify_entity_size_disabled[0x1];
1043 u8 umr_modify_atomic_disabled[0x1];
1044 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1045 u8 umr_fence[0x2];
94a04d1d
YC		 1046 u8 dc_req_scat_data_cqe[0x1];
1047 u8 reserved_at_20d[0x2];
e281682b 1048 u8 drain_sigerr[0x1];
b775516b
EC		 1049 u8 cmdif_checksum[0x2];
1050 u8 sigerr_cqe[0x1];
e1c9c62b 1051 u8 reserved_at_213[0x1];
b775516b
EC		 1052 u8 wq_signature[0x1];
1053 u8 sctr_data_cqe[0x1];
e1c9c62b 1054 u8 reserved_at_216[0x1];
b775516b
EC		 1055 u8 sho[0x1];
1056 u8 tph[0x1];
1057 u8 rf[0x1];
e281682b 1058 u8 dct[0x1];
7486216b 1059 u8 qos[0x1];
e281682b 1060 u8 eth_net_offloads[0x1];
b775516b
EC		 1061 u8 roce[0x1];
1062 u8 atomic[0x1];
e1c9c62b 1063 u8 reserved_at_21f[0x1];
b775516b
EC		 1064
1065 u8 cq_oi[0x1];
1066 u8 cq_resize[0x1];
1067 u8 cq_moderation[0x1];
e1c9c62b 1068 u8 reserved_at_223[0x3];
e281682b 1069 u8 cq_eq_remap[0x1];
b775516b
EC		 1070 u8 pg[0x1];
1071 u8 block_lb_mc[0x1];
e1c9c62b 1072 u8 reserved_at_229[0x1];
e281682b 1073 u8 scqe_break_moderation[0x1];
7d5e1423 1074 u8 cq_period_start_from_cqe[0x1];
b775516b 1075 u8 cd[0x1];
e1c9c62b 1076 u8 reserved_at_22d[0x1];
b775516b 1077 u8 apm[0x1];
3f0393a5 1078 u8 vector_calc[0x1];
7d5e1423 1079 u8 umr_ptr_rlky[0x1];
d2370e0a 1080 u8 imaicl[0x1];
3fd3c80a
DG		 1081 u8 qp_packet_based[0x1];
1082 u8 reserved_at_233[0x3];
b775516b
EC		 1083 u8 qkv[0x1];
1084 u8 pkv[0x1];
b11a4f9c
HE		 1085 u8 set_deth_sqpn[0x1];
1086 u8 reserved_at_239[0x3];
b775516b
EC		 1087 u8 xrc[0x1];
1088 u8 ud[0x1];
1089 u8 uc[0x1];
1090 u8 rc[0x1];
1091
a6d51b68
EC		 1092 u8 uar_4k[0x1];
1093 u8 reserved_at_241[0x9];
b775516b 1094 u8 uar_sz[0x6];
e1c9c62b 1095 u8 reserved_at_250[0x8];
b775516b
EC		 1096 u8 log_pg_sz[0x8];
1097
1098 u8 bf[0x1];
0dbc6fe0 1099 u8 driver_version[0x1];
e281682b 1100 u8 pad_tx_eth_packet[0x1];
e1c9c62b 1101 u8 reserved_at_263[0x8];
b775516b 1102 u8 log_bf_reg_size[0x5];
84df61eb
AH		 1103
1104 u8 reserved_at_270[0xb];
1105 u8 lag_master[0x1];
1106 u8 num_lag_ports[0x4];
b775516b 1107
e1c9c62b 1108 u8 reserved_at_280[0x10];
b775516b
EC		 1109 u8 max_wqe_sz_sq[0x10];
1110
e1c9c62b 1111 u8 reserved_at_2a0[0x10];
b775516b
EC		 1112 u8 max_wqe_sz_rq[0x10];
1113
a8ffcc74 1114 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1115 u8 max_wqe_sz_sq_dc[0x10];
1116
e1c9c62b 1117 u8 reserved_at_2e0[0x7];
b775516b
EC		 1118 u8 max_qp_mcg[0x19];
1119
e1c9c62b 1120 u8 reserved_at_300[0x18];
b775516b
EC		 1121 u8 log_max_mcg[0x8];
1122
e1c9c62b 1123 u8 reserved_at_320[0x3];
e281682b 1124 u8 log_max_transport_domain[0x5];
e1c9c62b 1125 u8 reserved_at_328[0x3];
b775516b 1126 u8 log_max_pd[0x5];
e1c9c62b 1127 u8 reserved_at_330[0xb];
b775516b
EC		 1128 u8 log_max_xrcd[0x5];
1129
5c298143 1130 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1131 u8 receive_discard_vport_down[0x1];
1132 u8 transmit_discard_vport_down[0x1];
1133 u8 reserved_at_343[0x5];
a351a1b0 1134 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1135 u8 max_flow_counter_15_0[0x10];
a351a1b0 1136
b775516b 1137
e1c9c62b 1138 u8 reserved_at_360[0x3];
b775516b 1139 u8 log_max_rq[0x5];
e1c9c62b 1140 u8 reserved_at_368[0x3];
b775516b 1141 u8 log_max_sq[0x5];
e1c9c62b 1142 u8 reserved_at_370[0x3];
b775516b 1143 u8 log_max_tir[0x5];
e1c9c62b 1144 u8 reserved_at_378[0x3];
b775516b
EC		 1145 u8 log_max_tis[0x5];
1146
e281682b 1147 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1148 u8 reserved_at_381[0x2];
e281682b 1149 u8 log_max_rmp[0x5];
e1c9c62b 1150 u8 reserved_at_388[0x3];
e281682b 1151 u8 log_max_rqt[0x5];
e1c9c62b 1152 u8 reserved_at_390[0x3];
e281682b 1153 u8 log_max_rqt_size[0x5];
e1c9c62b 1154 u8 reserved_at_398[0x3];
b775516b
EC		 1155 u8 log_max_tis_per_sq[0x5];
1156
619a8f2a
TT		 1157 u8 ext_stride_num_range[0x1];
1158 u8 reserved_at_3a1[0x2];
e281682b 1159 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1160 u8 reserved_at_3a8[0x3];
e281682b 1161 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1162 u8 reserved_at_3b0[0x3];
e281682b 1163 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1164 u8 reserved_at_3b8[0x3];
e281682b
SM		 1165 u8 log_min_stride_sz_sq[0x5];
1166
40817cdb
OG		 1167 u8 hairpin[0x1];
1168 u8 reserved_at_3c1[0x2];
1169 u8 log_max_hairpin_queues[0x5];
1170 u8 reserved_at_3c8[0x3];
1171 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1172 u8 reserved_at_3d0[0x3];
1173 u8 log_max_hairpin_num_packets[0x5];
1174 u8 reserved_at_3d8[0x3];
e281682b
SM		 1175 u8 log_max_wq_sz[0x5];
1176
54f0a411 1177 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1178 u8 disable_local_lb_uc[0x1];
1179 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1180 u8 log_min_hairpin_wq_data_sz[0x5];
1181 u8 reserved_at_3e8[0x3];
54f0a411 1182 u8 log_max_vlan_list[0x5];
e1c9c62b 1183 u8 reserved_at_3f0[0x3];
54f0a411 1184 u8 log_max_current_mc_list[0x5];
e1c9c62b 1185 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1186 u8 log_max_current_uc_list[0x5];
1187
38b7ca92
YH		 1188 u8 general_obj_types[0x40];
1189
342ac844
DD		 1190 u8 reserved_at_440[0x20];
1191
6e3722ba
YH		 1192 u8 reserved_at_460[0x3];
1193 u8 log_max_uctx[0x5];
1194 u8 reserved_at_468[0x3];
1195 u8 log_max_umem[0x5];
342ac844 1196 u8 max_num_eqs[0x10];
54f0a411 1197
e1c9c62b 1198 u8 reserved_at_480[0x3];
e281682b 1199 u8 log_max_l2_table[0x5];
e1c9c62b 1200 u8 reserved_at_488[0x8];
b775516b
EC		 1201 u8 log_uar_page_sz[0x10];
1202
e1c9c62b 1203 u8 reserved_at_4a0[0x20];
048ccca8 1204 u8 device_frequency_mhz[0x20];
b0844444 1205 u8 device_frequency_khz[0x20];
e1c9c62b 1206
a6d51b68
EC		 1207 u8 reserved_at_500[0x20];
1208 u8 num_of_uars_per_page[0x20];
e1c9c62b 1209
e818e255
AL		 1210 u8 flex_parser_protocols[0x20];
1211 u8 reserved_at_560[0x20];
e1c9c62b 1212
ab741b2e
YC		 1213 u8 reserved_at_580[0x3c];
1214 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1215 u8 cqe_128_always[0x1];
1216 u8 cqe_compression_128[0x1];
7d5e1423 1217 u8 cqe_compression[0x1];
b775516b 1218
7d5e1423
SM		 1219 u8 cqe_compression_timeout[0x10];
1220 u8 cqe_compression_max_num[0x10];
b775516b 1221
7486216b
SM		 1222 u8 reserved_at_5e0[0x10];
1223 u8 tag_matching[0x1];
1224 u8 rndv_offload_rc[0x1];
1225 u8 rndv_offload_dc[0x1];
1226 u8 log_tag_matching_list_sz[0x5];
7b13558f 1227 u8 reserved_at_5f8[0x3];
7486216b
SM		 1228 u8 log_max_xrq[0x5];
1229
32f69e4b
DJ		 1230 u8 affiliate_nic_vport_criteria[0x8];
1231 u8 native_port_num[0x8];
1232 u8 num_vhca_ports[0x8];
1233 u8 reserved_at_618[0x6];
1234 u8 sw_owner_id[0x1];
9d43faac
YH		 1235 u8 reserved_at_61f[0x1];
1236
fd4572b3
ED		 1237 u8 max_num_of_monitor_counters[0x10];
1238 u8 num_ppcnt_monitor_counters[0x10];
1239
1240 u8 reserved_at_640[0x10];
1241 u8 num_q_monitor_counters[0x10];
1242
1243 u8 reserved_at_660[0x40];
9d43faac
YH		 1244
1245 u8 uctx_cap[0x20];
1246
1247 u8 reserved_at_6c0[0x140];
b775516b
EC		 1248};
1249
81848731
SM		 1250enum mlx5_flow_destination_type {
1251 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1252 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1253 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1254
5f418378 1255 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1256 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
664000b6 1257 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
e281682b 1258};
b775516b 1259
e281682b
SM		 1260struct mlx5_ifc_dest_format_struct_bits {
1261 u8 destination_type[0x8];
1262 u8 destination_id[0x18];
1b115498 1263
b17f7fc1 1264 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1265 u8 packet_reformat[0x1];
1266 u8 reserved_at_22[0xe];
b17f7fc1 1267 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1268};
1269
9dc0b289 1270struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1271 u8 flow_counter_id[0x20];
9dc0b289
AV		 1272
1273 u8 reserved_at_20[0x20];
1274};
1275
1b115498
EB		 1276struct mlx5_ifc_extended_dest_format_bits {
1277 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1278
1279 u8 packet_reformat_id[0x20];
1280
1281 u8 reserved_at_60[0x20];
1282};
1283
9dc0b289
AV		 1284union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1285 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1286 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1287 u8 reserved_at_0[0x40];
1288};
1289
e281682b
SM		 1290struct mlx5_ifc_fte_match_param_bits {
1291 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1292
1293 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1294
1295 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1296
71c6e863
AL		 1297 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1298
1299 u8 reserved_at_800[0x800];
b775516b
EC		 1300};
1301
e281682b
SM		 1302enum {
1303 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1304 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1305 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1306 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1307 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1308};
b775516b 1309
e281682b
SM		 1310struct mlx5_ifc_rx_hash_field_select_bits {
1311 u8 l3_prot_type[0x1];
1312 u8 l4_prot_type[0x1];
1313 u8 selected_fields[0x1e];
1314};
b775516b 1315
e281682b
SM		 1316enum {
1317 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1318 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1319};
1320
e281682b
SM		 1321enum {
1322 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1323 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1324};
1325
1326struct mlx5_ifc_wq_bits {
1327 u8 wq_type[0x4];
1328 u8 wq_signature[0x1];
1329 u8 end_padding_mode[0x2];
1330 u8 cd_slave[0x1];
b4ff3a36 1331 u8 reserved_at_8[0x18];
b775516b 1332
e281682b
SM		 1333 u8 hds_skip_first_sge[0x1];
1334 u8 log2_hds_buf_size[0x3];
b4ff3a36 1335 u8 reserved_at_24[0x7];
e281682b
SM		 1336 u8 page_offset[0x5];
1337 u8 lwm[0x10];
b775516b 1338
b4ff3a36 1339 u8 reserved_at_40[0x8];
e281682b
SM		 1340 u8 pd[0x18];
1341
b4ff3a36 1342 u8 reserved_at_60[0x8];
e281682b
SM		 1343 u8 uar_page[0x18];
1344
1345 u8 dbr_addr[0x40];
1346
1347 u8 hw_counter[0x20];
1348
1349 u8 sw_counter[0x20];
1350
b4ff3a36 1351 u8 reserved_at_100[0xc];
e281682b 1352 u8 log_wq_stride[0x4];
b4ff3a36 1353 u8 reserved_at_110[0x3];
e281682b 1354 u8 log_wq_pg_sz[0x5];
b4ff3a36 1355 u8 reserved_at_118[0x3];
e281682b
SM		 1356 u8 log_wq_sz[0x5];
1357
bd371975
LR		 1358 u8 dbr_umem_valid[0x1];
1359 u8 wq_umem_valid[0x1];
1360 u8 reserved_at_122[0x1];
4d533e0f
OG		 1361 u8 log_hairpin_num_packets[0x5];
1362 u8 reserved_at_128[0x3];
40817cdb 1363 u8 log_hairpin_data_sz[0x5];
40817cdb 1364
619a8f2a
TT		 1365 u8 reserved_at_130[0x4];
1366 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1367 u8 two_byte_shift_en[0x1];
1368 u8 reserved_at_139[0x4];
1369 u8 log_wqe_stride_size[0x3];
1370
1371 u8 reserved_at_140[0x4c0];
b775516b 1372
e281682b 1373 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1374};
1375
e281682b 1376struct mlx5_ifc_rq_num_bits {
b4ff3a36 1377 u8 reserved_at_0[0x8];
e281682b
SM		 1378 u8 rq_num[0x18];
1379};
b775516b 1380
e281682b 1381struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1382 u8 reserved_at_0[0x10];
e281682b 1383 u8 mac_addr_47_32[0x10];
b775516b 1384
e281682b
SM		 1385 u8 mac_addr_31_0[0x20];
1386};
1387
c0046cf7 1388struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1389 u8 reserved_at_0[0x14];
c0046cf7
SM		 1390 u8 vlan[0x0c];
1391
b4ff3a36 1392 u8 reserved_at_20[0x20];
c0046cf7
SM		 1393};
1394
e281682b 1395struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1396 u8 reserved_at_0[0xa0];
e281682b
SM		 1397
1398 u8 min_time_between_cnps[0x20];
1399
b4ff3a36 1400 u8 reserved_at_c0[0x12];
e281682b 1401 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1402 u8 reserved_at_d8[0x4];
1403 u8 cnp_prio_mode[0x1];
e281682b
SM		 1404 u8 cnp_802p_prio[0x3];
1405
b4ff3a36 1406 u8 reserved_at_e0[0x720];
e281682b
SM		 1407};
1408
1409struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1410 u8 reserved_at_0[0x60];
e281682b 1411
b4ff3a36 1412 u8 reserved_at_60[0x4];
e281682b 1413 u8 clamp_tgt_rate[0x1];
b4ff3a36 1414 u8 reserved_at_65[0x3];
e281682b 1415 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1416 u8 reserved_at_69[0x17];
e281682b 1417
b4ff3a36 1418 u8 reserved_at_80[0x20];
e281682b
SM		 1419
1420 u8 rpg_time_reset[0x20];
1421
1422 u8 rpg_byte_reset[0x20];
1423
1424 u8 rpg_threshold[0x20];
1425
1426 u8 rpg_max_rate[0x20];
1427
1428 u8 rpg_ai_rate[0x20];
1429
1430 u8 rpg_hai_rate[0x20];
1431
1432 u8 rpg_gd[0x20];
1433
1434 u8 rpg_min_dec_fac[0x20];
1435
1436 u8 rpg_min_rate[0x20];
1437
b4ff3a36 1438 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1439
1440 u8 rate_to_set_on_first_cnp[0x20];
1441
1442 u8 dce_tcp_g[0x20];
1443
1444 u8 dce_tcp_rtt[0x20];
1445
1446 u8 rate_reduce_monitor_period[0x20];
1447
b4ff3a36 1448 u8 reserved_at_320[0x20];
e281682b
SM		 1449
1450 u8 initial_alpha_value[0x20];
1451
b4ff3a36 1452 u8 reserved_at_360[0x4a0];
e281682b
SM		 1453};
1454
1455struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1456 u8 reserved_at_0[0x80];
e281682b
SM		 1457
1458 u8 rppp_max_rps[0x20];
1459
1460 u8 rpg_time_reset[0x20];
1461
1462 u8 rpg_byte_reset[0x20];
1463
1464 u8 rpg_threshold[0x20];
1465
1466 u8 rpg_max_rate[0x20];
1467
1468 u8 rpg_ai_rate[0x20];
1469
1470 u8 rpg_hai_rate[0x20];
1471
1472 u8 rpg_gd[0x20];
1473
1474 u8 rpg_min_dec_fac[0x20];
1475
1476 u8 rpg_min_rate[0x20];
1477
b4ff3a36 1478 u8 reserved_at_1c0[0x640];
e281682b
SM		 1479};
1480
1481enum {
1482 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1483 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1484 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1485};
1486
1487struct mlx5_ifc_resize_field_select_bits {
1488 u8 resize_field_select[0x20];
1489};
1490
1491enum {
1492 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1493 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1494 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1495 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1496};
1497
1498struct mlx5_ifc_modify_field_select_bits {
1499 u8 modify_field_select[0x20];
1500};
1501
1502struct mlx5_ifc_field_select_r_roce_np_bits {
1503 u8 field_select_r_roce_np[0x20];
1504};
1505
1506struct mlx5_ifc_field_select_r_roce_rp_bits {
1507 u8 field_select_r_roce_rp[0x20];
1508};
1509
1510enum {
1511 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1512 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1513 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1514 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1515 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1516 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1517 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1518 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1519 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1520 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1521};
1522
1523struct mlx5_ifc_field_select_802_1qau_rp_bits {
1524 u8 field_select_8021qaurp[0x20];
1525};
1526
1527struct mlx5_ifc_phys_layer_cntrs_bits {
1528 u8 time_since_last_clear_high[0x20];
1529
1530 u8 time_since_last_clear_low[0x20];
1531
1532 u8 symbol_errors_high[0x20];
1533
1534 u8 symbol_errors_low[0x20];
1535
1536 u8 sync_headers_errors_high[0x20];
1537
1538 u8 sync_headers_errors_low[0x20];
1539
1540 u8 edpl_bip_errors_lane0_high[0x20];
1541
1542 u8 edpl_bip_errors_lane0_low[0x20];
1543
1544 u8 edpl_bip_errors_lane1_high[0x20];
1545
1546 u8 edpl_bip_errors_lane1_low[0x20];
1547
1548 u8 edpl_bip_errors_lane2_high[0x20];
1549
1550 u8 edpl_bip_errors_lane2_low[0x20];
1551
1552 u8 edpl_bip_errors_lane3_high[0x20];
1553
1554 u8 edpl_bip_errors_lane3_low[0x20];
1555
1556 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1557
1558 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1559
1560 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1561
1562 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1563
1564 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1565
1566 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1567
1568 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1569
1570 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1571
1572 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1573
1574 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1575
1576 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1577
1578 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1579
1580 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1581
1582 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1583
1584 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1585
1586 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1587
1588 u8 rs_fec_corrected_blocks_high[0x20];
1589
1590 u8 rs_fec_corrected_blocks_low[0x20];
1591
1592 u8 rs_fec_uncorrectable_blocks_high[0x20];
1593
1594 u8 rs_fec_uncorrectable_blocks_low[0x20];
1595
1596 u8 rs_fec_no_errors_blocks_high[0x20];
1597
1598 u8 rs_fec_no_errors_blocks_low[0x20];
1599
1600 u8 rs_fec_single_error_blocks_high[0x20];
1601
1602 u8 rs_fec_single_error_blocks_low[0x20];
1603
1604 u8 rs_fec_corrected_symbols_total_high[0x20];
1605
1606 u8 rs_fec_corrected_symbols_total_low[0x20];
1607
1608 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1609
1610 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1611
1612 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1613
1614 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1615
1616 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1617
1618 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1619
1620 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1621
1622 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1623
1624 u8 link_down_events[0x20];
1625
1626 u8 successful_recovery_events[0x20];
1627
b4ff3a36 1628 u8 reserved_at_640[0x180];
e281682b
SM		 1629};
1630
d8dc0508
GP		 1631struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1632 u8 time_since_last_clear_high[0x20];
1633
1634 u8 time_since_last_clear_low[0x20];
1635
1636 u8 phy_received_bits_high[0x20];
1637
1638 u8 phy_received_bits_low[0x20];
1639
1640 u8 phy_symbol_errors_high[0x20];
1641
1642 u8 phy_symbol_errors_low[0x20];
1643
1644 u8 phy_corrected_bits_high[0x20];
1645
1646 u8 phy_corrected_bits_low[0x20];
1647
1648 u8 phy_corrected_bits_lane0_high[0x20];
1649
1650 u8 phy_corrected_bits_lane0_low[0x20];
1651
1652 u8 phy_corrected_bits_lane1_high[0x20];
1653
1654 u8 phy_corrected_bits_lane1_low[0x20];
1655
1656 u8 phy_corrected_bits_lane2_high[0x20];
1657
1658 u8 phy_corrected_bits_lane2_low[0x20];
1659
1660 u8 phy_corrected_bits_lane3_high[0x20];
1661
1662 u8 phy_corrected_bits_lane3_low[0x20];
1663
1664 u8 reserved_at_200[0x5c0];
1665};
1666
1c64bf6f
MY		 1667struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1668 u8 symbol_error_counter[0x10];
1669
1670 u8 link_error_recovery_counter[0x8];
1671
1672 u8 link_downed_counter[0x8];
1673
1674 u8 port_rcv_errors[0x10];
1675
1676 u8 port_rcv_remote_physical_errors[0x10];
1677
1678 u8 port_rcv_switch_relay_errors[0x10];
1679
1680 u8 port_xmit_discards[0x10];
1681
1682 u8 port_xmit_constraint_errors[0x8];
1683
1684 u8 port_rcv_constraint_errors[0x8];
1685
1686 u8 reserved_at_70[0x8];
1687
1688 u8 link_overrun_errors[0x8];
1689
1690 u8 reserved_at_80[0x10];
1691
1692 u8 vl_15_dropped[0x10];
1693
133bea04
TW		 1694 u8 reserved_at_a0[0x80];
1695
1696 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1697};
1698
e281682b
SM		 1699struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1700 u8 transmit_queue_high[0x20];
1701
1702 u8 transmit_queue_low[0x20];
1703
b4ff3a36 1704 u8 reserved_at_40[0x780];
e281682b
SM		 1705};
1706
1707struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1708 u8 rx_octets_high[0x20];
1709
1710 u8 rx_octets_low[0x20];
1711
b4ff3a36 1712 u8 reserved_at_40[0xc0];
e281682b
SM		 1713
1714 u8 rx_frames_high[0x20];
1715
1716 u8 rx_frames_low[0x20];
1717
1718 u8 tx_octets_high[0x20];
1719
1720 u8 tx_octets_low[0x20];
1721
b4ff3a36 1722 u8 reserved_at_180[0xc0];
e281682b
SM		 1723
1724 u8 tx_frames_high[0x20];
1725
1726 u8 tx_frames_low[0x20];
1727
1728 u8 rx_pause_high[0x20];
1729
1730 u8 rx_pause_low[0x20];
1731
1732 u8 rx_pause_duration_high[0x20];
1733
1734 u8 rx_pause_duration_low[0x20];
1735
1736 u8 tx_pause_high[0x20];
1737
1738 u8 tx_pause_low[0x20];
1739
1740 u8 tx_pause_duration_high[0x20];
1741
1742 u8 tx_pause_duration_low[0x20];
1743
1744 u8 rx_pause_transition_high[0x20];
1745
1746 u8 rx_pause_transition_low[0x20];
1747
2fcb12df
IK		 1748 u8 reserved_at_3c0[0x40];
1749
1750 u8 device_stall_minor_watermark_cnt_high[0x20];
1751
1752 u8 device_stall_minor_watermark_cnt_low[0x20];
1753
1754 u8 device_stall_critical_watermark_cnt_high[0x20];
1755
1756 u8 device_stall_critical_watermark_cnt_low[0x20];
1757
1758 u8 reserved_at_480[0x340];
e281682b
SM		 1759};
1760
1761struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1762 u8 port_transmit_wait_high[0x20];
1763
1764 u8 port_transmit_wait_low[0x20];
1765
2dba0797
GP		 1766 u8 reserved_at_40[0x100];
1767
1768 u8 rx_buffer_almost_full_high[0x20];
1769
1770 u8 rx_buffer_almost_full_low[0x20];
1771
1772 u8 rx_buffer_full_high[0x20];
1773
1774 u8 rx_buffer_full_low[0x20];
1775
0af5107c
TB		 1776 u8 rx_icrc_encapsulated_high[0x20];
1777
1778 u8 rx_icrc_encapsulated_low[0x20];
1779
1780 u8 reserved_at_200[0x5c0];
e281682b
SM		 1781};
1782
1783struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1784 u8 dot3stats_alignment_errors_high[0x20];
1785
1786 u8 dot3stats_alignment_errors_low[0x20];
1787
1788 u8 dot3stats_fcs_errors_high[0x20];
1789
1790 u8 dot3stats_fcs_errors_low[0x20];
1791
1792 u8 dot3stats_single_collision_frames_high[0x20];
1793
1794 u8 dot3stats_single_collision_frames_low[0x20];
1795
1796 u8 dot3stats_multiple_collision_frames_high[0x20];
1797
1798 u8 dot3stats_multiple_collision_frames_low[0x20];
1799
1800 u8 dot3stats_sqe_test_errors_high[0x20];
1801
1802 u8 dot3stats_sqe_test_errors_low[0x20];
1803
1804 u8 dot3stats_deferred_transmissions_high[0x20];
1805
1806 u8 dot3stats_deferred_transmissions_low[0x20];
1807
1808 u8 dot3stats_late_collisions_high[0x20];
1809
1810 u8 dot3stats_late_collisions_low[0x20];
1811
1812 u8 dot3stats_excessive_collisions_high[0x20];
1813
1814 u8 dot3stats_excessive_collisions_low[0x20];
1815
1816 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1817
1818 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1819
1820 u8 dot3stats_carrier_sense_errors_high[0x20];
1821
1822 u8 dot3stats_carrier_sense_errors_low[0x20];
1823
1824 u8 dot3stats_frame_too_longs_high[0x20];
1825
1826 u8 dot3stats_frame_too_longs_low[0x20];
1827
1828 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1829
1830 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1831
1832 u8 dot3stats_symbol_errors_high[0x20];
1833
1834 u8 dot3stats_symbol_errors_low[0x20];
1835
1836 u8 dot3control_in_unknown_opcodes_high[0x20];
1837
1838 u8 dot3control_in_unknown_opcodes_low[0x20];
1839
1840 u8 dot3in_pause_frames_high[0x20];
1841
1842 u8 dot3in_pause_frames_low[0x20];
1843
1844 u8 dot3out_pause_frames_high[0x20];
1845
1846 u8 dot3out_pause_frames_low[0x20];
1847
b4ff3a36 1848 u8 reserved_at_400[0x3c0];
e281682b
SM		 1849};
1850
1851struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1852 u8 ether_stats_drop_events_high[0x20];
1853
1854 u8 ether_stats_drop_events_low[0x20];
1855
1856 u8 ether_stats_octets_high[0x20];
1857
1858 u8 ether_stats_octets_low[0x20];
1859
1860 u8 ether_stats_pkts_high[0x20];
1861
1862 u8 ether_stats_pkts_low[0x20];
1863
1864 u8 ether_stats_broadcast_pkts_high[0x20];
1865
1866 u8 ether_stats_broadcast_pkts_low[0x20];
1867
1868 u8 ether_stats_multicast_pkts_high[0x20];
1869
1870 u8 ether_stats_multicast_pkts_low[0x20];
1871
1872 u8 ether_stats_crc_align_errors_high[0x20];
1873
1874 u8 ether_stats_crc_align_errors_low[0x20];
1875
1876 u8 ether_stats_undersize_pkts_high[0x20];
1877
1878 u8 ether_stats_undersize_pkts_low[0x20];
1879
1880 u8 ether_stats_oversize_pkts_high[0x20];
1881
1882 u8 ether_stats_oversize_pkts_low[0x20];
1883
1884 u8 ether_stats_fragments_high[0x20];
1885
1886 u8 ether_stats_fragments_low[0x20];
1887
1888 u8 ether_stats_jabbers_high[0x20];
1889
1890 u8 ether_stats_jabbers_low[0x20];
1891
1892 u8 ether_stats_collisions_high[0x20];
1893
1894 u8 ether_stats_collisions_low[0x20];
1895
1896 u8 ether_stats_pkts64octets_high[0x20];
1897
1898 u8 ether_stats_pkts64octets_low[0x20];
1899
1900 u8 ether_stats_pkts65to127octets_high[0x20];
1901
1902 u8 ether_stats_pkts65to127octets_low[0x20];
1903
1904 u8 ether_stats_pkts128to255octets_high[0x20];
1905
1906 u8 ether_stats_pkts128to255octets_low[0x20];
1907
1908 u8 ether_stats_pkts256to511octets_high[0x20];
1909
1910 u8 ether_stats_pkts256to511octets_low[0x20];
1911
1912 u8 ether_stats_pkts512to1023octets_high[0x20];
1913
1914 u8 ether_stats_pkts512to1023octets_low[0x20];
1915
1916 u8 ether_stats_pkts1024to1518octets_high[0x20];
1917
1918 u8 ether_stats_pkts1024to1518octets_low[0x20];
1919
1920 u8 ether_stats_pkts1519to2047octets_high[0x20];
1921
1922 u8 ether_stats_pkts1519to2047octets_low[0x20];
1923
1924 u8 ether_stats_pkts2048to4095octets_high[0x20];
1925
1926 u8 ether_stats_pkts2048to4095octets_low[0x20];
1927
1928 u8 ether_stats_pkts4096to8191octets_high[0x20];
1929
1930 u8 ether_stats_pkts4096to8191octets_low[0x20];
1931
1932 u8 ether_stats_pkts8192to10239octets_high[0x20];
1933
1934 u8 ether_stats_pkts8192to10239octets_low[0x20];
1935
b4ff3a36 1936 u8 reserved_at_540[0x280];
e281682b
SM		 1937};
1938
1939struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1940 u8 if_in_octets_high[0x20];
1941
1942 u8 if_in_octets_low[0x20];
1943
1944 u8 if_in_ucast_pkts_high[0x20];
1945
1946 u8 if_in_ucast_pkts_low[0x20];
1947
1948 u8 if_in_discards_high[0x20];
1949
1950 u8 if_in_discards_low[0x20];
1951
1952 u8 if_in_errors_high[0x20];
1953
1954 u8 if_in_errors_low[0x20];
1955
1956 u8 if_in_unknown_protos_high[0x20];
1957
1958 u8 if_in_unknown_protos_low[0x20];
1959
1960 u8 if_out_octets_high[0x20];
1961
1962 u8 if_out_octets_low[0x20];
1963
1964 u8 if_out_ucast_pkts_high[0x20];
1965
1966 u8 if_out_ucast_pkts_low[0x20];
1967
1968 u8 if_out_discards_high[0x20];
1969
1970 u8 if_out_discards_low[0x20];
1971
1972 u8 if_out_errors_high[0x20];
1973
1974 u8 if_out_errors_low[0x20];
1975
1976 u8 if_in_multicast_pkts_high[0x20];
1977
1978 u8 if_in_multicast_pkts_low[0x20];
1979
1980 u8 if_in_broadcast_pkts_high[0x20];
1981
1982 u8 if_in_broadcast_pkts_low[0x20];
1983
1984 u8 if_out_multicast_pkts_high[0x20];
1985
1986 u8 if_out_multicast_pkts_low[0x20];
1987
1988 u8 if_out_broadcast_pkts_high[0x20];
1989
1990 u8 if_out_broadcast_pkts_low[0x20];
1991
b4ff3a36 1992 u8 reserved_at_340[0x480];
e281682b
SM		 1993};
1994
1995struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1996 u8 a_frames_transmitted_ok_high[0x20];
1997
1998 u8 a_frames_transmitted_ok_low[0x20];
1999
2000 u8 a_frames_received_ok_high[0x20];
2001
2002 u8 a_frames_received_ok_low[0x20];
2003
2004 u8 a_frame_check_sequence_errors_high[0x20];
2005
2006 u8 a_frame_check_sequence_errors_low[0x20];
2007
2008 u8 a_alignment_errors_high[0x20];
2009
2010 u8 a_alignment_errors_low[0x20];
2011
2012 u8 a_octets_transmitted_ok_high[0x20];
2013
2014 u8 a_octets_transmitted_ok_low[0x20];
2015
2016 u8 a_octets_received_ok_high[0x20];
2017
2018 u8 a_octets_received_ok_low[0x20];
2019
2020 u8 a_multicast_frames_xmitted_ok_high[0x20];
2021
2022 u8 a_multicast_frames_xmitted_ok_low[0x20];
2023
2024 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2025
2026 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2027
2028 u8 a_multicast_frames_received_ok_high[0x20];
2029
2030 u8 a_multicast_frames_received_ok_low[0x20];
2031
2032 u8 a_broadcast_frames_received_ok_high[0x20];
2033
2034 u8 a_broadcast_frames_received_ok_low[0x20];
2035
2036 u8 a_in_range_length_errors_high[0x20];
2037
2038 u8 a_in_range_length_errors_low[0x20];
2039
2040 u8 a_out_of_range_length_field_high[0x20];
2041
2042 u8 a_out_of_range_length_field_low[0x20];
2043
2044 u8 a_frame_too_long_errors_high[0x20];
2045
2046 u8 a_frame_too_long_errors_low[0x20];
2047
2048 u8 a_symbol_error_during_carrier_high[0x20];
2049
2050 u8 a_symbol_error_during_carrier_low[0x20];
2051
2052 u8 a_mac_control_frames_transmitted_high[0x20];
2053
2054 u8 a_mac_control_frames_transmitted_low[0x20];
2055
2056 u8 a_mac_control_frames_received_high[0x20];
2057
2058 u8 a_mac_control_frames_received_low[0x20];
2059
2060 u8 a_unsupported_opcodes_received_high[0x20];
2061
2062 u8 a_unsupported_opcodes_received_low[0x20];
2063
2064 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2065
2066 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2067
2068 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2069
2070 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2071
b4ff3a36 2072 u8 reserved_at_4c0[0x300];
e281682b
SM		 2073};
2074
8ed1a630
GP		 2075struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2076 u8 life_time_counter_high[0x20];
2077
2078 u8 life_time_counter_low[0x20];
2079
2080 u8 rx_errors[0x20];
2081
2082 u8 tx_errors[0x20];
2083
2084 u8 l0_to_recovery_eieos[0x20];
2085
2086 u8 l0_to_recovery_ts[0x20];
2087
2088 u8 l0_to_recovery_framing[0x20];
2089
2090 u8 l0_to_recovery_retrain[0x20];
2091
2092 u8 crc_error_dllp[0x20];
2093
2094 u8 crc_error_tlp[0x20];
2095
efae7f78
EBE		 2096 u8 tx_overflow_buffer_pkt_high[0x20];
2097
2098 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2099
2100 u8 outbound_stalled_reads[0x20];
2101
2102 u8 outbound_stalled_writes[0x20];
2103
2104 u8 outbound_stalled_reads_events[0x20];
2105
2106 u8 outbound_stalled_writes_events[0x20];
2107
2108 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2109};
2110
e281682b
SM		 2111struct mlx5_ifc_cmd_inter_comp_event_bits {
2112 u8 command_completion_vector[0x20];
2113
b4ff3a36 2114 u8 reserved_at_20[0xc0];
e281682b
SM		 2115};
2116
2117struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2118 u8 reserved_at_0[0x18];
e281682b 2119 u8 port_num[0x1];
b4ff3a36 2120 u8 reserved_at_19[0x3];
e281682b
SM		 2121 u8 vl[0x4];
2122
b4ff3a36 2123 u8 reserved_at_20[0xa0];
e281682b
SM		 2124};
2125
2126struct mlx5_ifc_db_bf_congestion_event_bits {
2127 u8 event_subtype[0x8];
b4ff3a36 2128 u8 reserved_at_8[0x8];
e281682b 2129 u8 congestion_level[0x8];
b4ff3a36 2130 u8 reserved_at_18[0x8];
e281682b 2131
b4ff3a36 2132 u8 reserved_at_20[0xa0];
e281682b
SM		 2133};
2134
2135struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2136 u8 reserved_at_0[0x60];
e281682b
SM		 2137
2138 u8 gpio_event_hi[0x20];
2139
2140 u8 gpio_event_lo[0x20];
2141
b4ff3a36 2142 u8 reserved_at_a0[0x40];
e281682b
SM		 2143};
2144
2145struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2146 u8 reserved_at_0[0x40];
e281682b
SM		 2147
2148 u8 port_num[0x4];
b4ff3a36 2149 u8 reserved_at_44[0x1c];
e281682b 2150
b4ff3a36 2151 u8 reserved_at_60[0x80];
e281682b
SM		 2152};
2153
2154struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2155 u8 reserved_at_0[0xe0];
e281682b
SM		 2156};
2157
2158enum {
2159 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2160 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2161};
2162
2163struct mlx5_ifc_cq_error_bits {
b4ff3a36 2164 u8 reserved_at_0[0x8];
e281682b
SM		 2165 u8 cqn[0x18];
2166
b4ff3a36 2167 u8 reserved_at_20[0x20];
e281682b 2168
b4ff3a36 2169 u8 reserved_at_40[0x18];
e281682b
SM		 2170 u8 syndrome[0x8];
2171
b4ff3a36 2172 u8 reserved_at_60[0x80];
e281682b
SM		 2173};
2174
2175struct mlx5_ifc_rdma_page_fault_event_bits {
2176 u8 bytes_committed[0x20];
2177
2178 u8 r_key[0x20];
2179
b4ff3a36 2180 u8 reserved_at_40[0x10];
e281682b
SM		 2181 u8 packet_len[0x10];
2182
2183 u8 rdma_op_len[0x20];
2184
2185 u8 rdma_va[0x40];
2186
b4ff3a36 2187 u8 reserved_at_c0[0x5];
e281682b
SM		 2188 u8 rdma[0x1];
2189 u8 write[0x1];
2190 u8 requestor[0x1];
2191 u8 qp_number[0x18];
2192};
2193
2194struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2195 u8 bytes_committed[0x20];
2196
b4ff3a36 2197 u8 reserved_at_20[0x10];
e281682b
SM		 2198 u8 wqe_index[0x10];
2199
b4ff3a36 2200 u8 reserved_at_40[0x10];
e281682b
SM		 2201 u8 len[0x10];
2202
b4ff3a36 2203 u8 reserved_at_60[0x60];
e281682b 2204
b4ff3a36 2205 u8 reserved_at_c0[0x5];
e281682b
SM		 2206 u8 rdma[0x1];
2207 u8 write_read[0x1];
2208 u8 requestor[0x1];
2209 u8 qpn[0x18];
2210};
2211
2212struct mlx5_ifc_qp_events_bits {
b4ff3a36 2213 u8 reserved_at_0[0xa0];
e281682b
SM		 2214
2215 u8 type[0x8];
b4ff3a36 2216 u8 reserved_at_a8[0x18];
e281682b 2217
b4ff3a36 2218 u8 reserved_at_c0[0x8];
e281682b
SM		 2219 u8 qpn_rqn_sqn[0x18];
2220};
2221
2222struct mlx5_ifc_dct_events_bits {
b4ff3a36 2223 u8 reserved_at_0[0xc0];
e281682b 2224
b4ff3a36 2225 u8 reserved_at_c0[0x8];
e281682b
SM		 2226 u8 dct_number[0x18];
2227};
2228
2229struct mlx5_ifc_comp_event_bits {
b4ff3a36 2230 u8 reserved_at_0[0xc0];
e281682b 2231
b4ff3a36 2232 u8 reserved_at_c0[0x8];
e281682b
SM		 2233 u8 cq_number[0x18];
2234};
2235
2236enum {
2237 MLX5_QPC_STATE_RST = 0x0,
2238 MLX5_QPC_STATE_INIT = 0x1,
2239 MLX5_QPC_STATE_RTR = 0x2,
2240 MLX5_QPC_STATE_RTS = 0x3,
2241 MLX5_QPC_STATE_SQER = 0x4,
2242 MLX5_QPC_STATE_ERR = 0x6,
2243 MLX5_QPC_STATE_SQD = 0x7,
2244 MLX5_QPC_STATE_SUSPENDED = 0x9,
2245};
2246
2247enum {
2248 MLX5_QPC_ST_RC = 0x0,
2249 MLX5_QPC_ST_UC = 0x1,
2250 MLX5_QPC_ST_UD = 0x2,
2251 MLX5_QPC_ST_XRC = 0x3,
2252 MLX5_QPC_ST_DCI = 0x5,
2253 MLX5_QPC_ST_QP0 = 0x7,
2254 MLX5_QPC_ST_QP1 = 0x8,
2255 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2256 MLX5_QPC_ST_REG_UMR = 0xc,
2257};
2258
2259enum {
2260 MLX5_QPC_PM_STATE_ARMED = 0x0,
2261 MLX5_QPC_PM_STATE_REARM = 0x1,
2262 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2263 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2264};
2265
6e44636a
AK		 2266enum {
2267 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2268};
2269
e281682b
SM		 2270enum {
2271 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2272 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2273};
2274
2275enum {
2276 MLX5_QPC_MTU_256_BYTES = 0x1,
2277 MLX5_QPC_MTU_512_BYTES = 0x2,
2278 MLX5_QPC_MTU_1K_BYTES = 0x3,
2279 MLX5_QPC_MTU_2K_BYTES = 0x4,
2280 MLX5_QPC_MTU_4K_BYTES = 0x5,
2281 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2282};
2283
2284enum {
2285 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2286 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2287 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2288 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2289 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2290 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2291 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2292 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2293};
2294
2295enum {
2296 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2297 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2298 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2299};
2300
2301enum {
2302 MLX5_QPC_CS_RES_DISABLE = 0x0,
2303 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2304 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2305};
2306
2307struct mlx5_ifc_qpc_bits {
2308 u8 state[0x4];
84df61eb 2309 u8 lag_tx_port_affinity[0x4];
e281682b 2310 u8 st[0x8];
b4ff3a36 2311 u8 reserved_at_10[0x3];
e281682b 2312 u8 pm_state[0x2];
3fd3c80a
DG		 2313 u8 reserved_at_15[0x1];
2314 u8 req_e2e_credit_mode[0x2];
6e44636a 2315 u8 offload_type[0x4];
e281682b 2316 u8 end_padding_mode[0x2];
b4ff3a36 2317 u8 reserved_at_1e[0x2];
e281682b
SM		 2318
2319 u8 wq_signature[0x1];
2320 u8 block_lb_mc[0x1];
2321 u8 atomic_like_write_en[0x1];
2322 u8 latency_sensitive[0x1];
b4ff3a36 2323 u8 reserved_at_24[0x1];
e281682b 2324 u8 drain_sigerr[0x1];
b4ff3a36 2325 u8 reserved_at_26[0x2];
e281682b
SM		 2326 u8 pd[0x18];
2327
2328 u8 mtu[0x3];
2329 u8 log_msg_max[0x5];
b4ff3a36 2330 u8 reserved_at_48[0x1];
e281682b
SM		 2331 u8 log_rq_size[0x4];
2332 u8 log_rq_stride[0x3];
2333 u8 no_sq[0x1];
2334 u8 log_sq_size[0x4];
b4ff3a36 2335 u8 reserved_at_55[0x6];
e281682b 2336 u8 rlky[0x1];
1015c2e8 2337 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2338
2339 u8 counter_set_id[0x8];
2340 u8 uar_page[0x18];
2341
b4ff3a36 2342 u8 reserved_at_80[0x8];
e281682b
SM		 2343 u8 user_index[0x18];
2344
b4ff3a36 2345 u8 reserved_at_a0[0x3];
e281682b
SM		 2346 u8 log_page_size[0x5];
2347 u8 remote_qpn[0x18];
2348
2349 struct mlx5_ifc_ads_bits primary_address_path;
2350
2351 struct mlx5_ifc_ads_bits secondary_address_path;
2352
2353 u8 log_ack_req_freq[0x4];
b4ff3a36 2354 u8 reserved_at_384[0x4];
e281682b 2355 u8 log_sra_max[0x3];
b4ff3a36 2356 u8 reserved_at_38b[0x2];
e281682b
SM		 2357 u8 retry_count[0x3];
2358 u8 rnr_retry[0x3];
b4ff3a36 2359 u8 reserved_at_393[0x1];
e281682b
SM		 2360 u8 fre[0x1];
2361 u8 cur_rnr_retry[0x3];
2362 u8 cur_retry_count[0x3];
b4ff3a36 2363 u8 reserved_at_39b[0x5];
e281682b 2364
b4ff3a36 2365 u8 reserved_at_3a0[0x20];
e281682b 2366
b4ff3a36 2367 u8 reserved_at_3c0[0x8];
e281682b
SM		 2368 u8 next_send_psn[0x18];
2369
b4ff3a36 2370 u8 reserved_at_3e0[0x8];
e281682b
SM		 2371 u8 cqn_snd[0x18];
2372
09a7d9ec
SM		 2373 u8 reserved_at_400[0x8];
2374 u8 deth_sqpn[0x18];
2375
2376 u8 reserved_at_420[0x20];
e281682b 2377
b4ff3a36 2378 u8 reserved_at_440[0x8];
e281682b
SM		 2379 u8 last_acked_psn[0x18];
2380
b4ff3a36 2381 u8 reserved_at_460[0x8];
e281682b
SM		 2382 u8 ssn[0x18];
2383
b4ff3a36 2384 u8 reserved_at_480[0x8];
e281682b 2385 u8 log_rra_max[0x3];
b4ff3a36 2386 u8 reserved_at_48b[0x1];
e281682b
SM		 2387 u8 atomic_mode[0x4];
2388 u8 rre[0x1];
2389 u8 rwe[0x1];
2390 u8 rae[0x1];
b4ff3a36 2391 u8 reserved_at_493[0x1];
e281682b 2392 u8 page_offset[0x6];
b4ff3a36 2393 u8 reserved_at_49a[0x3];
e281682b
SM		 2394 u8 cd_slave_receive[0x1];
2395 u8 cd_slave_send[0x1];
2396 u8 cd_master[0x1];
2397
b4ff3a36 2398 u8 reserved_at_4a0[0x3];
e281682b
SM		 2399 u8 min_rnr_nak[0x5];
2400 u8 next_rcv_psn[0x18];
2401
b4ff3a36 2402 u8 reserved_at_4c0[0x8];
e281682b
SM		 2403 u8 xrcd[0x18];
2404
b4ff3a36 2405 u8 reserved_at_4e0[0x8];
e281682b
SM		 2406 u8 cqn_rcv[0x18];
2407
2408 u8 dbr_addr[0x40];
2409
2410 u8 q_key[0x20];
2411
b4ff3a36 2412 u8 reserved_at_560[0x5];
e281682b 2413 u8 rq_type[0x3];
7486216b 2414 u8 srqn_rmpn_xrqn[0x18];
e281682b 2415
b4ff3a36 2416 u8 reserved_at_580[0x8];
e281682b
SM		 2417 u8 rmsn[0x18];
2418
2419 u8 hw_sq_wqebb_counter[0x10];
2420 u8 sw_sq_wqebb_counter[0x10];
2421
2422 u8 hw_rq_counter[0x20];
2423
2424 u8 sw_rq_counter[0x20];
2425
b4ff3a36 2426 u8 reserved_at_600[0x20];
e281682b 2427
b4ff3a36 2428 u8 reserved_at_620[0xf];
e281682b
SM		 2429 u8 cgs[0x1];
2430 u8 cs_req[0x8];
2431 u8 cs_res[0x8];
2432
2433 u8 dc_access_key[0x40];
2434
bd371975
LR		 2435 u8 reserved_at_680[0x3];
2436 u8 dbr_umem_valid[0x1];
2437
2438 u8 reserved_at_684[0xbc];
e281682b
SM		 2439};
2440
2441struct mlx5_ifc_roce_addr_layout_bits {
2442 u8 source_l3_address[16][0x8];
2443
b4ff3a36 2444 u8 reserved_at_80[0x3];
e281682b
SM		 2445 u8 vlan_valid[0x1];
2446 u8 vlan_id[0xc];
2447 u8 source_mac_47_32[0x10];
2448
2449 u8 source_mac_31_0[0x20];
2450
b4ff3a36 2451 u8 reserved_at_c0[0x14];
e281682b
SM		 2452 u8 roce_l3_type[0x4];
2453 u8 roce_version[0x8];
2454
b4ff3a36 2455 u8 reserved_at_e0[0x20];
e281682b
SM		 2456};
2457
2458union mlx5_ifc_hca_cap_union_bits {
2459 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2460 struct mlx5_ifc_odp_cap_bits odp_cap;
2461 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2462 struct mlx5_ifc_roce_cap_bits roce_cap;
2463 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2464 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2465 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2466 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2467 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2468 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2469 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2470 u8 reserved_at_0[0x8000];
e281682b
SM		 2471};
2472
2473enum {
2474 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2475 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2476 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2477 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 2478 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 2479 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2480 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2481 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2482 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 2483 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2484 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
0c06897a
OG		 2485};
2486
2487struct mlx5_ifc_vlan_bits {
2488 u8 ethtype[0x10];
2489 u8 prio[0x3];
2490 u8 cfi[0x1];
2491 u8 vid[0xc];
e281682b
SM		 2492};
2493
2494struct mlx5_ifc_flow_context_bits {
0c06897a 2495 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2496
2497 u8 group_id[0x20];
2498
b4ff3a36 2499 u8 reserved_at_40[0x8];
e281682b
SM		 2500 u8 flow_tag[0x18];
2501
b4ff3a36 2502 u8 reserved_at_60[0x10];
e281682b
SM		 2503 u8 action[0x10];
2504
1b115498
EB		 2505 u8 extended_destination[0x1];
2506 u8 reserved_at_80[0x7];
e281682b
SM		 2507 u8 destination_list_size[0x18];
2508
9dc0b289
AV		 2509 u8 reserved_at_a0[0x8];
2510 u8 flow_counter_list_size[0x18];
2511
60786f09 2512 u8 packet_reformat_id[0x20];
7adbde20 2513
2a69cb9f
OG		 2514 u8 modify_header_id[0x20];
2515
8da6fe2a
JL		 2516 struct mlx5_ifc_vlan_bits push_vlan_2;
2517
2518 u8 reserved_at_120[0xe0];
e281682b
SM		 2519
2520 struct mlx5_ifc_fte_match_param_bits match_value;
2521
b4ff3a36 2522 u8 reserved_at_1200[0x600];
e281682b 2523
9dc0b289 2524 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2525};
2526
2527enum {
2528 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2529 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2530};
2531
2532struct mlx5_ifc_xrc_srqc_bits {
2533 u8 state[0x4];
2534 u8 log_xrc_srq_size[0x4];
b4ff3a36 2535 u8 reserved_at_8[0x18];
e281682b
SM		 2536
2537 u8 wq_signature[0x1];
2538 u8 cont_srq[0x1];
99b77fef 2539 u8 reserved_at_22[0x1];
e281682b
SM		 2540 u8 rlky[0x1];
2541 u8 basic_cyclic_rcv_wqe[0x1];
2542 u8 log_rq_stride[0x3];
2543 u8 xrcd[0x18];
2544
2545 u8 page_offset[0x6];
99b77fef
YH		 2546 u8 reserved_at_46[0x1];
2547 u8 dbr_umem_valid[0x1];
e281682b
SM		 2548 u8 cqn[0x18];
2549
b4ff3a36 2550 u8 reserved_at_60[0x20];
e281682b
SM		 2551
2552 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2553 u8 reserved_at_81[0x1];
e281682b
SM		 2554 u8 log_page_size[0x6];
2555 u8 user_index[0x18];
2556
b4ff3a36 2557 u8 reserved_at_a0[0x20];
e281682b 2558
b4ff3a36 2559 u8 reserved_at_c0[0x8];
e281682b
SM		 2560 u8 pd[0x18];
2561
2562 u8 lwm[0x10];
2563 u8 wqe_cnt[0x10];
2564
b4ff3a36 2565 u8 reserved_at_100[0x40];
e281682b
SM		 2566
2567 u8 db_record_addr_h[0x20];
2568
2569 u8 db_record_addr_l[0x1e];
b4ff3a36 2570 u8 reserved_at_17e[0x2];
e281682b 2571
b4ff3a36 2572 u8 reserved_at_180[0x80];
e281682b
SM		 2573};
2574
61c5b5c9
MS		 2575struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2576 u8 counter_error_queues[0x20];
2577
2578 u8 total_error_queues[0x20];
2579
2580 u8 send_queue_priority_update_flow[0x20];
2581
2582 u8 reserved_at_60[0x20];
2583
2584 u8 nic_receive_steering_discard[0x40];
2585
2586 u8 receive_discard_vport_down[0x40];
2587
2588 u8 transmit_discard_vport_down[0x40];
2589
2590 u8 reserved_at_140[0xec0];
2591};
2592
e281682b
SM		 2593struct mlx5_ifc_traffic_counter_bits {
2594 u8 packets[0x40];
2595
2596 u8 octets[0x40];
2597};
2598
2599struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2600 u8 strict_lag_tx_port_affinity[0x1];
2601 u8 reserved_at_1[0x3];
2602 u8 lag_tx_port_affinity[0x04];
2603
2604 u8 reserved_at_8[0x4];
e281682b 2605 u8 prio[0x4];
b4ff3a36 2606 u8 reserved_at_10[0x10];
e281682b 2607
b4ff3a36 2608 u8 reserved_at_20[0x100];
e281682b 2609
b4ff3a36 2610 u8 reserved_at_120[0x8];
e281682b
SM		 2611 u8 transport_domain[0x18];
2612
500a3d0d
ES		 2613 u8 reserved_at_140[0x8];
2614 u8 underlay_qpn[0x18];
2615 u8 reserved_at_160[0x3a0];
e281682b
SM		 2616};
2617
2618enum {
2619 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2620 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2621};
2622
2623enum {
2624 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2625 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2626};
2627
2628enum {
2be6967c
SM		 2629 MLX5_RX_HASH_FN_NONE = 0x0,
2630 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2631 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2632};
2633
2634enum {
5d773ff4
MB		 2635 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2636 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 2637};
2638
2639struct mlx5_ifc_tirc_bits {
b4ff3a36 2640 u8 reserved_at_0[0x20];
e281682b
SM		 2641
2642 u8 disp_type[0x4];
b4ff3a36 2643 u8 reserved_at_24[0x1c];
e281682b 2644
b4ff3a36 2645 u8 reserved_at_40[0x40];
e281682b 2646
b4ff3a36 2647 u8 reserved_at_80[0x4];
e281682b
SM		 2648 u8 lro_timeout_period_usecs[0x10];
2649 u8 lro_enable_mask[0x4];
2650 u8 lro_max_ip_payload_size[0x8];
2651
b4ff3a36 2652 u8 reserved_at_a0[0x40];
e281682b 2653
b4ff3a36 2654 u8 reserved_at_e0[0x8];
e281682b
SM		 2655 u8 inline_rqn[0x18];
2656
2657 u8 rx_hash_symmetric[0x1];
b4ff3a36 2658 u8 reserved_at_101[0x1];
e281682b 2659 u8 tunneled_offload_en[0x1];
b4ff3a36 2660 u8 reserved_at_103[0x5];
e281682b
SM		 2661 u8 indirect_table[0x18];
2662
2663 u8 rx_hash_fn[0x4];
b4ff3a36 2664 u8 reserved_at_124[0x2];
e281682b
SM		 2665 u8 self_lb_block[0x2];
2666 u8 transport_domain[0x18];
2667
2668 u8 rx_hash_toeplitz_key[10][0x20];
2669
2670 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2671
2672 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2673
b4ff3a36 2674 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2675};
2676
2677enum {
2678 MLX5_SRQC_STATE_GOOD = 0x0,
2679 MLX5_SRQC_STATE_ERROR = 0x1,
2680};
2681
2682struct mlx5_ifc_srqc_bits {
2683 u8 state[0x4];
2684 u8 log_srq_size[0x4];
b4ff3a36 2685 u8 reserved_at_8[0x18];
e281682b
SM		 2686
2687 u8 wq_signature[0x1];
2688 u8 cont_srq[0x1];
b4ff3a36 2689 u8 reserved_at_22[0x1];
e281682b 2690 u8 rlky[0x1];
b4ff3a36 2691 u8 reserved_at_24[0x1];
e281682b
SM		 2692 u8 log_rq_stride[0x3];
2693 u8 xrcd[0x18];
2694
2695 u8 page_offset[0x6];
b4ff3a36 2696 u8 reserved_at_46[0x2];
e281682b
SM		 2697 u8 cqn[0x18];
2698
b4ff3a36 2699 u8 reserved_at_60[0x20];
e281682b 2700
b4ff3a36 2701 u8 reserved_at_80[0x2];
e281682b 2702 u8 log_page_size[0x6];
b4ff3a36 2703 u8 reserved_at_88[0x18];
e281682b 2704
b4ff3a36 2705 u8 reserved_at_a0[0x20];
e281682b 2706
b4ff3a36 2707 u8 reserved_at_c0[0x8];
e281682b
SM		 2708 u8 pd[0x18];
2709
2710 u8 lwm[0x10];
2711 u8 wqe_cnt[0x10];
2712
b4ff3a36 2713 u8 reserved_at_100[0x40];
e281682b 2714
01949d01 2715 u8 dbr_addr[0x40];
e281682b 2716
b4ff3a36 2717 u8 reserved_at_180[0x80];
e281682b
SM		 2718};
2719
2720enum {
2721 MLX5_SQC_STATE_RST = 0x0,
2722 MLX5_SQC_STATE_RDY = 0x1,
2723 MLX5_SQC_STATE_ERR = 0x3,
2724};
2725
2726struct mlx5_ifc_sqc_bits {
2727 u8 rlky[0x1];
2728 u8 cd_master[0x1];
2729 u8 fre[0x1];
2730 u8 flush_in_error_en[0x1];
795b609c 2731 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2732 u8 min_wqe_inline_mode[0x3];
e281682b 2733 u8 state[0x4];
7d5e1423 2734 u8 reg_umr[0x1];
547eede0 2735 u8 allow_swp[0x1];
40817cdb
OG		 2736 u8 hairpin[0x1];
2737 u8 reserved_at_f[0x11];
e281682b 2738
b4ff3a36 2739 u8 reserved_at_20[0x8];
e281682b
SM		 2740 u8 user_index[0x18];
2741
b4ff3a36 2742 u8 reserved_at_40[0x8];
e281682b
SM		 2743 u8 cqn[0x18];
2744
40817cdb
OG		 2745 u8 reserved_at_60[0x8];
2746 u8 hairpin_peer_rq[0x18];
2747
2748 u8 reserved_at_80[0x10];
2749 u8 hairpin_peer_vhca[0x10];
2750
2751 u8 reserved_at_a0[0x50];
e281682b 2752
7486216b 2753 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2754 u8 tis_lst_sz[0x10];
b4ff3a36 2755 u8 reserved_at_110[0x10];
e281682b 2756
b4ff3a36 2757 u8 reserved_at_120[0x40];
e281682b 2758
b4ff3a36 2759 u8 reserved_at_160[0x8];
e281682b
SM		 2760 u8 tis_num_0[0x18];
2761
2762 struct mlx5_ifc_wq_bits wq;
2763};
2764
813f8540
MHY		 2765enum {
2766 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2767 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2768 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2769 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2770};
2771
2772struct mlx5_ifc_scheduling_context_bits {
2773 u8 element_type[0x8];
2774 u8 reserved_at_8[0x18];
2775
2776 u8 element_attributes[0x20];
2777
2778 u8 parent_element_id[0x20];
2779
2780 u8 reserved_at_60[0x40];
2781
2782 u8 bw_share[0x20];
2783
2784 u8 max_average_bw[0x20];
2785
2786 u8 reserved_at_e0[0x120];
2787};
2788
e281682b 2789struct mlx5_ifc_rqtc_bits {
b4ff3a36 2790 u8 reserved_at_0[0xa0];
e281682b 2791
b4ff3a36 2792 u8 reserved_at_a0[0x10];
e281682b
SM		 2793 u8 rqt_max_size[0x10];
2794
b4ff3a36 2795 u8 reserved_at_c0[0x10];
e281682b
SM		 2796 u8 rqt_actual_size[0x10];
2797
b4ff3a36 2798 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2799
2800 struct mlx5_ifc_rq_num_bits rq_num[0];
2801};
2802
2803enum {
2804 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2805 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2806};
2807
2808enum {
2809 MLX5_RQC_STATE_RST = 0x0,
2810 MLX5_RQC_STATE_RDY = 0x1,
2811 MLX5_RQC_STATE_ERR = 0x3,
2812};
2813
2814struct mlx5_ifc_rqc_bits {
2815 u8 rlky[0x1];
03404e8a 2816 u8 delay_drop_en[0x1];
7d5e1423 2817 u8 scatter_fcs[0x1];
e281682b
SM		 2818 u8 vsd[0x1];
2819 u8 mem_rq_type[0x4];
2820 u8 state[0x4];
b4ff3a36 2821 u8 reserved_at_c[0x1];
e281682b 2822 u8 flush_in_error_en[0x1];
40817cdb
OG		 2823 u8 hairpin[0x1];
2824 u8 reserved_at_f[0x11];
e281682b 2825
b4ff3a36 2826 u8 reserved_at_20[0x8];
e281682b
SM		 2827 u8 user_index[0x18];
2828
b4ff3a36 2829 u8 reserved_at_40[0x8];
e281682b
SM		 2830 u8 cqn[0x18];
2831
2832 u8 counter_set_id[0x8];
b4ff3a36 2833 u8 reserved_at_68[0x18];
e281682b 2834
b4ff3a36 2835 u8 reserved_at_80[0x8];
e281682b
SM		 2836 u8 rmpn[0x18];
2837
40817cdb
OG		 2838 u8 reserved_at_a0[0x8];
2839 u8 hairpin_peer_sq[0x18];
2840
2841 u8 reserved_at_c0[0x10];
2842 u8 hairpin_peer_vhca[0x10];
2843
2844 u8 reserved_at_e0[0xa0];
e281682b
SM		 2845
2846 struct mlx5_ifc_wq_bits wq;
2847};
2848
2849enum {
2850 MLX5_RMPC_STATE_RDY = 0x1,
2851 MLX5_RMPC_STATE_ERR = 0x3,
2852};
2853
2854struct mlx5_ifc_rmpc_bits {
b4ff3a36 2855 u8 reserved_at_0[0x8];
e281682b 2856 u8 state[0x4];
b4ff3a36 2857 u8 reserved_at_c[0x14];
e281682b
SM		 2858
2859 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2860 u8 reserved_at_21[0x1f];
e281682b 2861
b4ff3a36 2862 u8 reserved_at_40[0x140];
e281682b
SM		 2863
2864 struct mlx5_ifc_wq_bits wq;
2865};
2866
e281682b 2867struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2868 u8 reserved_at_0[0x5];
2869 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2870 u8 reserved_at_8[0x15];
2871 u8 disable_mc_local_lb[0x1];
2872 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2873 u8 roce_en[0x1];
2874
d82b7318 2875 u8 arm_change_event[0x1];
b4ff3a36 2876 u8 reserved_at_21[0x1a];
d82b7318
SM		 2877 u8 event_on_mtu[0x1];
2878 u8 event_on_promisc_change[0x1];
2879 u8 event_on_vlan_change[0x1];
2880 u8 event_on_mc_address_change[0x1];
2881 u8 event_on_uc_address_change[0x1];
e281682b 2882
32f69e4b
DJ		 2883 u8 reserved_at_40[0xc];
2884
2885 u8 affiliation_criteria[0x4];
2886 u8 affiliated_vhca_id[0x10];
2887
2888 u8 reserved_at_60[0xd0];
d82b7318
SM		 2889
2890 u8 mtu[0x10];
2891
9efa7525
AS		 2892 u8 system_image_guid[0x40];
2893 u8 port_guid[0x40];
2894 u8 node_guid[0x40];
2895
b4ff3a36 2896 u8 reserved_at_200[0x140];
9efa7525 2897 u8 qkey_violation_counter[0x10];
b4ff3a36 2898 u8 reserved_at_350[0x430];
d82b7318
SM		 2899
2900 u8 promisc_uc[0x1];
2901 u8 promisc_mc[0x1];
2902 u8 promisc_all[0x1];
b4ff3a36 2903 u8 reserved_at_783[0x2];
e281682b 2904 u8 allowed_list_type[0x3];
b4ff3a36 2905 u8 reserved_at_788[0xc];
e281682b
SM		 2906 u8 allowed_list_size[0xc];
2907
2908 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2909
b4ff3a36 2910 u8 reserved_at_7e0[0x20];
e281682b
SM		 2911
2912 u8 current_uc_mac_address[0][0x40];
2913};
2914
2915enum {
2916 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2917 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2918 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2919 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
cdbd0d2b 2920 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 2921};
2922
2923struct mlx5_ifc_mkc_bits {
b4ff3a36 2924 u8 reserved_at_0[0x1];
e281682b 2925 u8 free[0x1];
cdbd0d2b
AL		 2926 u8 reserved_at_2[0x1];
2927 u8 access_mode_4_2[0x3];
2928 u8 reserved_at_6[0x7];
2929 u8 relaxed_ordering_write[0x1];
2930 u8 reserved_at_e[0x1];
e281682b
SM		 2931 u8 small_fence_on_rdma_read_response[0x1];
2932 u8 umr_en[0x1];
2933 u8 a[0x1];
2934 u8 rw[0x1];
2935 u8 rr[0x1];
2936 u8 lw[0x1];
2937 u8 lr[0x1];
cdbd0d2b 2938 u8 access_mode_1_0[0x2];
b4ff3a36 2939 u8 reserved_at_18[0x8];
e281682b
SM		 2940
2941 u8 qpn[0x18];
2942 u8 mkey_7_0[0x8];
2943
b4ff3a36 2944 u8 reserved_at_40[0x20];
e281682b
SM		 2945
2946 u8 length64[0x1];
2947 u8 bsf_en[0x1];
2948 u8 sync_umr[0x1];
b4ff3a36 2949 u8 reserved_at_63[0x2];
e281682b 2950 u8 expected_sigerr_count[0x1];
b4ff3a36 2951 u8 reserved_at_66[0x1];
e281682b
SM		 2952 u8 en_rinval[0x1];
2953 u8 pd[0x18];
2954
2955 u8 start_addr[0x40];
2956
2957 u8 len[0x40];
2958
2959 u8 bsf_octword_size[0x20];
2960
b4ff3a36 2961 u8 reserved_at_120[0x80];
e281682b
SM		 2962
2963 u8 translations_octword_size[0x20];
2964
b4ff3a36 2965 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2966 u8 log_page_size[0x5];
2967
b4ff3a36 2968 u8 reserved_at_1e0[0x20];
e281682b
SM		 2969};
2970
2971struct mlx5_ifc_pkey_bits {
b4ff3a36 2972 u8 reserved_at_0[0x10];
e281682b
SM		 2973 u8 pkey[0x10];
2974};
2975
2976struct mlx5_ifc_array128_auto_bits {
2977 u8 array128_auto[16][0x8];
2978};
2979
2980struct mlx5_ifc_hca_vport_context_bits {
2981 u8 field_select[0x20];
2982
b4ff3a36 2983 u8 reserved_at_20[0xe0];
e281682b
SM		 2984
2985 u8 sm_virt_aware[0x1];
2986 u8 has_smi[0x1];
2987 u8 has_raw[0x1];
2988 u8 grh_required[0x1];
b4ff3a36 2989 u8 reserved_at_104[0xc];
707c4602
MD		 2990 u8 port_physical_state[0x4];
2991 u8 vport_state_policy[0x4];
2992 u8 port_state[0x4];
e281682b
SM		 2993 u8 vport_state[0x4];
2994
b4ff3a36 2995 u8 reserved_at_120[0x20];
707c4602
MD		 2996
2997 u8 system_image_guid[0x40];
e281682b
SM		 2998
2999 u8 port_guid[0x40];
3000
3001 u8 node_guid[0x40];
3002
3003 u8 cap_mask1[0x20];
3004
3005 u8 cap_mask1_field_select[0x20];
3006
3007 u8 cap_mask2[0x20];
3008
3009 u8 cap_mask2_field_select[0x20];
3010
b4ff3a36 3011 u8 reserved_at_280[0x80];
e281682b
SM		 3012
3013 u8 lid[0x10];
b4ff3a36 3014 u8 reserved_at_310[0x4];
e281682b
SM		 3015 u8 init_type_reply[0x4];
3016 u8 lmc[0x3];
3017 u8 subnet_timeout[0x5];
3018
3019 u8 sm_lid[0x10];
3020 u8 sm_sl[0x4];
b4ff3a36 3021 u8 reserved_at_334[0xc];
e281682b
SM		 3022
3023 u8 qkey_violation_counter[0x10];
3024 u8 pkey_violation_counter[0x10];
3025
b4ff3a36 3026 u8 reserved_at_360[0xca0];
e281682b
SM		 3027};
3028
d6666753 3029struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 3030 u8 reserved_at_0[0x3];
d6666753
SM		 3031 u8 vport_svlan_strip[0x1];
3032 u8 vport_cvlan_strip[0x1];
3033 u8 vport_svlan_insert[0x1];
3034 u8 vport_cvlan_insert[0x2];
b4ff3a36 3035 u8 reserved_at_8[0x18];
d6666753 3036
b4ff3a36 3037 u8 reserved_at_20[0x20];
d6666753
SM		 3038
3039 u8 svlan_cfi[0x1];
3040 u8 svlan_pcp[0x3];
3041 u8 svlan_id[0xc];
3042 u8 cvlan_cfi[0x1];
3043 u8 cvlan_pcp[0x3];
3044 u8 cvlan_id[0xc];
3045
b4ff3a36 3046 u8 reserved_at_60[0x7a0];
d6666753
SM		 3047};
3048
e281682b
SM		 3049enum {
3050 MLX5_EQC_STATUS_OK = 0x0,
3051 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3052};
3053
3054enum {
3055 MLX5_EQC_ST_ARMED = 0x9,
3056 MLX5_EQC_ST_FIRED = 0xa,
3057};
3058
3059struct mlx5_ifc_eqc_bits {
3060 u8 status[0x4];
b4ff3a36 3061 u8 reserved_at_4[0x9];
e281682b
SM		 3062 u8 ec[0x1];
3063 u8 oi[0x1];
b4ff3a36 3064 u8 reserved_at_f[0x5];
e281682b 3065 u8 st[0x4];
b4ff3a36 3066 u8 reserved_at_18[0x8];
e281682b 3067
b4ff3a36 3068 u8 reserved_at_20[0x20];
e281682b 3069
b4ff3a36 3070 u8 reserved_at_40[0x14];
e281682b 3071 u8 page_offset[0x6];
b4ff3a36 3072 u8 reserved_at_5a[0x6];
e281682b 3073
b4ff3a36 3074 u8 reserved_at_60[0x3];
e281682b
SM		 3075 u8 log_eq_size[0x5];
3076 u8 uar_page[0x18];
3077
b4ff3a36 3078 u8 reserved_at_80[0x20];
e281682b 3079
b4ff3a36 3080 u8 reserved_at_a0[0x18];
e281682b
SM		 3081 u8 intr[0x8];
3082
b4ff3a36 3083 u8 reserved_at_c0[0x3];
e281682b 3084 u8 log_page_size[0x5];
b4ff3a36 3085 u8 reserved_at_c8[0x18];
e281682b 3086
b4ff3a36 3087 u8 reserved_at_e0[0x60];
e281682b 3088
b4ff3a36 3089 u8 reserved_at_140[0x8];
e281682b
SM		 3090 u8 consumer_counter[0x18];
3091
b4ff3a36 3092 u8 reserved_at_160[0x8];
e281682b
SM		 3093 u8 producer_counter[0x18];
3094
b4ff3a36 3095 u8 reserved_at_180[0x80];
e281682b
SM		 3096};
3097
3098enum {
3099 MLX5_DCTC_STATE_ACTIVE = 0x0,
3100 MLX5_DCTC_STATE_DRAINING = 0x1,
3101 MLX5_DCTC_STATE_DRAINED = 0x2,
3102};
3103
3104enum {
3105 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3106 MLX5_DCTC_CS_RES_NA = 0x1,
3107 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3108};
3109
3110enum {
3111 MLX5_DCTC_MTU_256_BYTES = 0x1,
3112 MLX5_DCTC_MTU_512_BYTES = 0x2,
3113 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3114 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3115 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3116};
3117
3118struct mlx5_ifc_dctc_bits {
b4ff3a36 3119 u8 reserved_at_0[0x4];
e281682b 3120 u8 state[0x4];
b4ff3a36 3121 u8 reserved_at_8[0x18];
e281682b 3122
b4ff3a36 3123 u8 reserved_at_20[0x8];
e281682b
SM		 3124 u8 user_index[0x18];
3125
b4ff3a36 3126 u8 reserved_at_40[0x8];
e281682b
SM		 3127 u8 cqn[0x18];
3128
3129 u8 counter_set_id[0x8];
3130 u8 atomic_mode[0x4];
3131 u8 rre[0x1];
3132 u8 rwe[0x1];
3133 u8 rae[0x1];
3134 u8 atomic_like_write_en[0x1];
3135 u8 latency_sensitive[0x1];
3136 u8 rlky[0x1];
3137 u8 free_ar[0x1];
b4ff3a36 3138 u8 reserved_at_73[0xd];
e281682b 3139
b4ff3a36 3140 u8 reserved_at_80[0x8];
e281682b 3141 u8 cs_res[0x8];
b4ff3a36 3142 u8 reserved_at_90[0x3];
e281682b 3143 u8 min_rnr_nak[0x5];
b4ff3a36 3144 u8 reserved_at_98[0x8];
e281682b 3145
b4ff3a36 3146 u8 reserved_at_a0[0x8];
7486216b 3147 u8 srqn_xrqn[0x18];
e281682b 3148
b4ff3a36 3149 u8 reserved_at_c0[0x8];
e281682b
SM		 3150 u8 pd[0x18];
3151
3152 u8 tclass[0x8];
b4ff3a36 3153 u8 reserved_at_e8[0x4];
e281682b
SM		 3154 u8 flow_label[0x14];
3155
3156 u8 dc_access_key[0x40];
3157
b4ff3a36 3158 u8 reserved_at_140[0x5];
e281682b
SM		 3159 u8 mtu[0x3];
3160 u8 port[0x8];
3161 u8 pkey_index[0x10];
3162
b4ff3a36 3163 u8 reserved_at_160[0x8];
e281682b 3164 u8 my_addr_index[0x8];
b4ff3a36 3165 u8 reserved_at_170[0x8];
e281682b
SM		 3166 u8 hop_limit[0x8];
3167
3168 u8 dc_access_key_violation_count[0x20];
3169
b4ff3a36 3170 u8 reserved_at_1a0[0x14];
e281682b
SM		 3171 u8 dei_cfi[0x1];
3172 u8 eth_prio[0x3];
3173 u8 ecn[0x2];
3174 u8 dscp[0x6];
3175
b4ff3a36 3176 u8 reserved_at_1c0[0x40];
e281682b
SM		 3177};
3178
3179enum {
3180 MLX5_CQC_STATUS_OK = 0x0,
3181 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3182 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3183};
3184
3185enum {
3186 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3187 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3188};
3189
3190enum {
3191 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3192 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3193 MLX5_CQC_ST_FIRED = 0xa,
3194};
3195
7d5e1423
SM		 3196enum {
3197 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3198 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3199 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3200};
3201
e281682b
SM		 3202struct mlx5_ifc_cqc_bits {
3203 u8 status[0x4];
bd371975
LR		 3204 u8 reserved_at_4[0x2];
3205 u8 dbr_umem_valid[0x1];
3206 u8 reserved_at_7[0x1];
e281682b
SM		 3207 u8 cqe_sz[0x3];
3208 u8 cc[0x1];
b4ff3a36 3209 u8 reserved_at_c[0x1];
e281682b
SM		 3210 u8 scqe_break_moderation_en[0x1];
3211 u8 oi[0x1];
7d5e1423
SM		 3212 u8 cq_period_mode[0x2];
3213 u8 cqe_comp_en[0x1];
e281682b
SM		 3214 u8 mini_cqe_res_format[0x2];
3215 u8 st[0x4];
b4ff3a36 3216 u8 reserved_at_18[0x8];
e281682b 3217
b4ff3a36 3218 u8 reserved_at_20[0x20];
e281682b 3219
b4ff3a36 3220 u8 reserved_at_40[0x14];
e281682b 3221 u8 page_offset[0x6];
b4ff3a36 3222 u8 reserved_at_5a[0x6];
e281682b 3223
b4ff3a36 3224 u8 reserved_at_60[0x3];
e281682b
SM		 3225 u8 log_cq_size[0x5];
3226 u8 uar_page[0x18];
3227
b4ff3a36 3228 u8 reserved_at_80[0x4];
e281682b
SM		 3229 u8 cq_period[0xc];
3230 u8 cq_max_count[0x10];
3231
b4ff3a36 3232 u8 reserved_at_a0[0x18];
e281682b
SM		 3233 u8 c_eqn[0x8];
3234
b4ff3a36 3235 u8 reserved_at_c0[0x3];
e281682b 3236 u8 log_page_size[0x5];
b4ff3a36 3237 u8 reserved_at_c8[0x18];
e281682b 3238
b4ff3a36 3239 u8 reserved_at_e0[0x20];
e281682b 3240
b4ff3a36 3241 u8 reserved_at_100[0x8];
e281682b
SM		 3242 u8 last_notified_index[0x18];
3243
b4ff3a36 3244 u8 reserved_at_120[0x8];
e281682b
SM		 3245 u8 last_solicit_index[0x18];
3246
b4ff3a36 3247 u8 reserved_at_140[0x8];
e281682b
SM		 3248 u8 consumer_counter[0x18];
3249
b4ff3a36 3250 u8 reserved_at_160[0x8];
e281682b
SM		 3251 u8 producer_counter[0x18];
3252
b4ff3a36 3253 u8 reserved_at_180[0x40];
e281682b
SM		 3254
3255 u8 dbr_addr[0x40];
3256};
3257
3258union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3259 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3260 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3261 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3262 u8 reserved_at_0[0x800];
e281682b
SM		 3263};
3264
3265struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3266 u8 reserved_at_0[0xc0];
e281682b 3267
b4ff3a36 3268 u8 reserved_at_c0[0x8];
211e6c80
MD		 3269 u8 ieee_vendor_id[0x18];
3270
b4ff3a36 3271 u8 reserved_at_e0[0x10];
e281682b
SM		 3272 u8 vsd_vendor_id[0x10];
3273
3274 u8 vsd[208][0x8];
3275
3276 u8 vsd_contd_psid[16][0x8];
3277};
3278
7486216b
SM		 3279enum {
3280 MLX5_XRQC_STATE_GOOD = 0x0,
3281 MLX5_XRQC_STATE_ERROR = 0x1,
3282};
3283
3284enum {
3285 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3286 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3287};
3288
3289enum {
3290 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3291};
3292
3293struct mlx5_ifc_tag_matching_topology_context_bits {
3294 u8 log_matching_list_sz[0x4];
3295 u8 reserved_at_4[0xc];
3296 u8 append_next_index[0x10];
3297
3298 u8 sw_phase_cnt[0x10];
3299 u8 hw_phase_cnt[0x10];
3300
3301 u8 reserved_at_40[0x40];
3302};
3303
3304struct mlx5_ifc_xrqc_bits {
3305 u8 state[0x4];
3306 u8 rlkey[0x1];
3307 u8 reserved_at_5[0xf];
3308 u8 topology[0x4];
3309 u8 reserved_at_18[0x4];
3310 u8 offload[0x4];
3311
3312 u8 reserved_at_20[0x8];
3313 u8 user_index[0x18];
3314
3315 u8 reserved_at_40[0x8];
3316 u8 cqn[0x18];
3317
3318 u8 reserved_at_60[0xa0];
3319
3320 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3321
6e44636a 3322 u8 reserved_at_180[0x280];
7486216b
SM		 3323
3324 struct mlx5_ifc_wq_bits wq;
3325};
3326
e281682b
SM		 3327union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3328 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3329 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3330 u8 reserved_at_0[0x20];
e281682b
SM		 3331};
3332
3333union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3334 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3335 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3336 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3337 u8 reserved_at_0[0x20];
e281682b
SM		 3338};
3339
3340union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3341 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3342 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3343 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3344 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3345 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3346 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3347 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3348 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3349 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3350 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3351 u8 reserved_at_0[0x7c0];
e281682b
SM		 3352};
3353
8ed1a630
GP		 3354union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3355 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3356 u8 reserved_at_0[0x7c0];
3357};
3358
e281682b
SM		 3359union mlx5_ifc_event_auto_bits {
3360 struct mlx5_ifc_comp_event_bits comp_event;
3361 struct mlx5_ifc_dct_events_bits dct_events;
3362 struct mlx5_ifc_qp_events_bits qp_events;
3363 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3364 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3365 struct mlx5_ifc_cq_error_bits cq_error;
3366 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3367 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3368 struct mlx5_ifc_gpio_event_bits gpio_event;
3369 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3370 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3371 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3372 u8 reserved_at_0[0xe0];
e281682b
SM		 3373};
3374
3375struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3376 u8 reserved_at_0[0x100];
e281682b
SM		 3377
3378 u8 assert_existptr[0x20];
3379
3380 u8 assert_callra[0x20];
3381
b4ff3a36 3382 u8 reserved_at_140[0x40];
e281682b
SM		 3383
3384 u8 fw_version[0x20];
3385
3386 u8 hw_id[0x20];
3387
b4ff3a36 3388 u8 reserved_at_1c0[0x20];
e281682b
SM		 3389
3390 u8 irisc_index[0x8];
3391 u8 synd[0x8];
3392 u8 ext_synd[0x10];
3393};
3394
3395struct mlx5_ifc_register_loopback_control_bits {
3396 u8 no_lb[0x1];
b4ff3a36 3397 u8 reserved_at_1[0x7];
e281682b 3398 u8 port[0x8];
b4ff3a36 3399 u8 reserved_at_10[0x10];
e281682b 3400
b4ff3a36 3401 u8 reserved_at_20[0x60];
e281682b
SM		 3402};
3403
813f8540
MHY		 3404struct mlx5_ifc_vport_tc_element_bits {
3405 u8 traffic_class[0x4];
3406 u8 reserved_at_4[0xc];
3407 u8 vport_number[0x10];
3408};
3409
3410struct mlx5_ifc_vport_element_bits {
3411 u8 reserved_at_0[0x10];
3412 u8 vport_number[0x10];
3413};
3414
3415enum {
3416 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3417 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3418 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3419};
3420
3421struct mlx5_ifc_tsar_element_bits {
3422 u8 reserved_at_0[0x8];
3423 u8 tsar_type[0x8];
3424 u8 reserved_at_10[0x10];
3425};
3426
8812c24d
MD		 3427enum {
3428 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3429 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3430};
3431
e281682b
SM		 3432struct mlx5_ifc_teardown_hca_out_bits {
3433 u8 status[0x8];
b4ff3a36 3434 u8 reserved_at_8[0x18];
e281682b
SM		 3435
3436 u8 syndrome[0x20];
3437
8812c24d
MD		 3438 u8 reserved_at_40[0x3f];
3439
fcd29ad1 3440 u8 state[0x1];
e281682b
SM		 3441};
3442
3443enum {
3444 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3445 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 3446 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 3447};
3448
3449struct mlx5_ifc_teardown_hca_in_bits {
3450 u8 opcode[0x10];
b4ff3a36 3451 u8 reserved_at_10[0x10];
e281682b 3452
b4ff3a36 3453 u8 reserved_at_20[0x10];
e281682b
SM		 3454 u8 op_mod[0x10];
3455
b4ff3a36 3456 u8 reserved_at_40[0x10];
e281682b
SM		 3457 u8 profile[0x10];
3458
b4ff3a36 3459 u8 reserved_at_60[0x20];
e281682b
SM		 3460};
3461
3462struct mlx5_ifc_sqerr2rts_qp_out_bits {
3463 u8 status[0x8];
b4ff3a36 3464 u8 reserved_at_8[0x18];
e281682b
SM		 3465
3466 u8 syndrome[0x20];
3467
b4ff3a36 3468 u8 reserved_at_40[0x40];
e281682b
SM		 3469};
3470
3471struct mlx5_ifc_sqerr2rts_qp_in_bits {
3472 u8 opcode[0x10];
4ac63ec7 3473 u8 uid[0x10];
e281682b 3474
b4ff3a36 3475 u8 reserved_at_20[0x10];
e281682b
SM		 3476 u8 op_mod[0x10];
3477
b4ff3a36 3478 u8 reserved_at_40[0x8];
e281682b
SM		 3479 u8 qpn[0x18];
3480
b4ff3a36 3481 u8 reserved_at_60[0x20];
e281682b
SM		 3482
3483 u8 opt_param_mask[0x20];
3484
b4ff3a36 3485 u8 reserved_at_a0[0x20];
e281682b
SM		 3486
3487 struct mlx5_ifc_qpc_bits qpc;
3488
b4ff3a36 3489 u8 reserved_at_800[0x80];
e281682b
SM		 3490};
3491
3492struct mlx5_ifc_sqd2rts_qp_out_bits {
3493 u8 status[0x8];
b4ff3a36 3494 u8 reserved_at_8[0x18];
e281682b
SM		 3495
3496 u8 syndrome[0x20];
3497
b4ff3a36 3498 u8 reserved_at_40[0x40];
e281682b
SM		 3499};
3500
3501struct mlx5_ifc_sqd2rts_qp_in_bits {
3502 u8 opcode[0x10];
4ac63ec7 3503 u8 uid[0x10];
e281682b 3504
b4ff3a36 3505 u8 reserved_at_20[0x10];
e281682b
SM		 3506 u8 op_mod[0x10];
3507
b4ff3a36 3508 u8 reserved_at_40[0x8];
e281682b
SM		 3509 u8 qpn[0x18];
3510
b4ff3a36 3511 u8 reserved_at_60[0x20];
e281682b
SM		 3512
3513 u8 opt_param_mask[0x20];
3514
b4ff3a36 3515 u8 reserved_at_a0[0x20];
e281682b
SM		 3516
3517 struct mlx5_ifc_qpc_bits qpc;
3518
b4ff3a36 3519 u8 reserved_at_800[0x80];
e281682b
SM		 3520};
3521
3522struct mlx5_ifc_set_roce_address_out_bits {
3523 u8 status[0x8];
b4ff3a36 3524 u8 reserved_at_8[0x18];
e281682b
SM		 3525
3526 u8 syndrome[0x20];
3527
b4ff3a36 3528 u8 reserved_at_40[0x40];
e281682b
SM		 3529};
3530
3531struct mlx5_ifc_set_roce_address_in_bits {
3532 u8 opcode[0x10];
b4ff3a36 3533 u8 reserved_at_10[0x10];
e281682b 3534
b4ff3a36 3535 u8 reserved_at_20[0x10];
e281682b
SM		 3536 u8 op_mod[0x10];
3537
3538 u8 roce_address_index[0x10];
32f69e4b
DJ		 3539 u8 reserved_at_50[0xc];
3540 u8 vhca_port_num[0x4];
e281682b 3541
b4ff3a36 3542 u8 reserved_at_60[0x20];
e281682b
SM		 3543
3544 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3545};
3546
3547struct mlx5_ifc_set_mad_demux_out_bits {
3548 u8 status[0x8];
b4ff3a36 3549 u8 reserved_at_8[0x18];
e281682b
SM		 3550
3551 u8 syndrome[0x20];
3552
b4ff3a36 3553 u8 reserved_at_40[0x40];
e281682b
SM		 3554};
3555
3556enum {
3557 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3558 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3559};
3560
3561struct mlx5_ifc_set_mad_demux_in_bits {
3562 u8 opcode[0x10];
b4ff3a36 3563 u8 reserved_at_10[0x10];
e281682b 3564
b4ff3a36 3565 u8 reserved_at_20[0x10];
e281682b
SM		 3566 u8 op_mod[0x10];
3567
b4ff3a36 3568 u8 reserved_at_40[0x20];
e281682b 3569
b4ff3a36 3570 u8 reserved_at_60[0x6];
e281682b 3571 u8 demux_mode[0x2];
b4ff3a36 3572 u8 reserved_at_68[0x18];
e281682b
SM		 3573};
3574
3575struct mlx5_ifc_set_l2_table_entry_out_bits {
3576 u8 status[0x8];
b4ff3a36 3577 u8 reserved_at_8[0x18];
e281682b
SM		 3578
3579 u8 syndrome[0x20];
3580
b4ff3a36 3581 u8 reserved_at_40[0x40];
e281682b
SM		 3582};
3583
3584struct mlx5_ifc_set_l2_table_entry_in_bits {
3585 u8 opcode[0x10];
b4ff3a36 3586 u8 reserved_at_10[0x10];
e281682b 3587
b4ff3a36 3588 u8 reserved_at_20[0x10];
e281682b
SM		 3589 u8 op_mod[0x10];
3590
b4ff3a36 3591 u8 reserved_at_40[0x60];
e281682b 3592
b4ff3a36 3593 u8 reserved_at_a0[0x8];
e281682b
SM		 3594 u8 table_index[0x18];
3595
b4ff3a36 3596 u8 reserved_at_c0[0x20];
e281682b 3597
b4ff3a36 3598 u8 reserved_at_e0[0x13];
e281682b
SM		 3599 u8 vlan_valid[0x1];
3600 u8 vlan[0xc];
3601
3602 struct mlx5_ifc_mac_address_layout_bits mac_address;
3603
b4ff3a36 3604 u8 reserved_at_140[0xc0];
e281682b
SM		 3605};
3606
3607struct mlx5_ifc_set_issi_out_bits {
3608 u8 status[0x8];
b4ff3a36 3609 u8 reserved_at_8[0x18];
e281682b
SM		 3610
3611 u8 syndrome[0x20];
3612
b4ff3a36 3613 u8 reserved_at_40[0x40];
e281682b
SM		 3614};
3615
3616struct mlx5_ifc_set_issi_in_bits {
3617 u8 opcode[0x10];
b4ff3a36 3618 u8 reserved_at_10[0x10];
e281682b 3619
b4ff3a36 3620 u8 reserved_at_20[0x10];
e281682b
SM		 3621 u8 op_mod[0x10];
3622
b4ff3a36 3623 u8 reserved_at_40[0x10];
e281682b
SM		 3624 u8 current_issi[0x10];
3625
b4ff3a36 3626 u8 reserved_at_60[0x20];
e281682b
SM		 3627};
3628
3629struct mlx5_ifc_set_hca_cap_out_bits {
3630 u8 status[0x8];
b4ff3a36 3631 u8 reserved_at_8[0x18];
e281682b
SM		 3632
3633 u8 syndrome[0x20];
3634
b4ff3a36 3635 u8 reserved_at_40[0x40];
e281682b
SM		 3636};
3637
3638struct mlx5_ifc_set_hca_cap_in_bits {
3639 u8 opcode[0x10];
b4ff3a36 3640 u8 reserved_at_10[0x10];
e281682b 3641
b4ff3a36 3642 u8 reserved_at_20[0x10];
e281682b
SM		 3643 u8 op_mod[0x10];
3644
b4ff3a36 3645 u8 reserved_at_40[0x40];
e281682b
SM		 3646
3647 union mlx5_ifc_hca_cap_union_bits capability;
3648};
3649
26a81453
MG		 3650enum {
3651 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3652 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3653 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3654 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3655};
3656
e281682b
SM		 3657struct mlx5_ifc_set_fte_out_bits {
3658 u8 status[0x8];
b4ff3a36 3659 u8 reserved_at_8[0x18];
e281682b
SM		 3660
3661 u8 syndrome[0x20];
3662
b4ff3a36 3663 u8 reserved_at_40[0x40];
e281682b
SM		 3664};
3665
3666struct mlx5_ifc_set_fte_in_bits {
3667 u8 opcode[0x10];
b4ff3a36 3668 u8 reserved_at_10[0x10];
e281682b 3669
b4ff3a36 3670 u8 reserved_at_20[0x10];
e281682b
SM		 3671 u8 op_mod[0x10];
3672
7d5e1423
SM		 3673 u8 other_vport[0x1];
3674 u8 reserved_at_41[0xf];
3675 u8 vport_number[0x10];
3676
3677 u8 reserved_at_60[0x20];
e281682b
SM		 3678
3679 u8 table_type[0x8];
b4ff3a36 3680 u8 reserved_at_88[0x18];
e281682b 3681
b4ff3a36 3682 u8 reserved_at_a0[0x8];
e281682b
SM		 3683 u8 table_id[0x18];
3684
b4ff3a36 3685 u8 reserved_at_c0[0x18];
26a81453
MG		 3686 u8 modify_enable_mask[0x8];
3687
b4ff3a36 3688 u8 reserved_at_e0[0x20];
e281682b
SM		 3689
3690 u8 flow_index[0x20];
3691
b4ff3a36 3692 u8 reserved_at_120[0xe0];
e281682b
SM		 3693
3694 struct mlx5_ifc_flow_context_bits flow_context;
3695};
3696
3697struct mlx5_ifc_rts2rts_qp_out_bits {
3698 u8 status[0x8];
b4ff3a36 3699 u8 reserved_at_8[0x18];
e281682b
SM		 3700
3701 u8 syndrome[0x20];
3702
b4ff3a36 3703 u8 reserved_at_40[0x40];
e281682b
SM		 3704};
3705
3706struct mlx5_ifc_rts2rts_qp_in_bits {
3707 u8 opcode[0x10];
4ac63ec7 3708 u8 uid[0x10];
e281682b 3709
b4ff3a36 3710 u8 reserved_at_20[0x10];
e281682b
SM		 3711 u8 op_mod[0x10];
3712
b4ff3a36 3713 u8 reserved_at_40[0x8];
e281682b
SM		 3714 u8 qpn[0x18];
3715
b4ff3a36 3716 u8 reserved_at_60[0x20];
e281682b
SM		 3717
3718 u8 opt_param_mask[0x20];
3719
b4ff3a36 3720 u8 reserved_at_a0[0x20];
e281682b
SM		 3721
3722 struct mlx5_ifc_qpc_bits qpc;
3723
b4ff3a36 3724 u8 reserved_at_800[0x80];
e281682b
SM		 3725};
3726
3727struct mlx5_ifc_rtr2rts_qp_out_bits {
3728 u8 status[0x8];
b4ff3a36 3729 u8 reserved_at_8[0x18];
e281682b
SM		 3730
3731 u8 syndrome[0x20];
3732
b4ff3a36 3733 u8 reserved_at_40[0x40];
e281682b
SM		 3734};
3735
3736struct mlx5_ifc_rtr2rts_qp_in_bits {
3737 u8 opcode[0x10];
4ac63ec7 3738 u8 uid[0x10];
e281682b 3739
b4ff3a36 3740 u8 reserved_at_20[0x10];
e281682b
SM		 3741 u8 op_mod[0x10];
3742
b4ff3a36 3743 u8 reserved_at_40[0x8];
e281682b
SM		 3744 u8 qpn[0x18];
3745
b4ff3a36 3746 u8 reserved_at_60[0x20];
e281682b
SM		 3747
3748 u8 opt_param_mask[0x20];
3749
b4ff3a36 3750 u8 reserved_at_a0[0x20];
e281682b
SM		 3751
3752 struct mlx5_ifc_qpc_bits qpc;
3753
b4ff3a36 3754 u8 reserved_at_800[0x80];
e281682b
SM		 3755};
3756
3757struct mlx5_ifc_rst2init_qp_out_bits {
3758 u8 status[0x8];
b4ff3a36 3759 u8 reserved_at_8[0x18];
e281682b
SM		 3760
3761 u8 syndrome[0x20];
3762
b4ff3a36 3763 u8 reserved_at_40[0x40];
e281682b
SM		 3764};
3765
3766struct mlx5_ifc_rst2init_qp_in_bits {
3767 u8 opcode[0x10];
4ac63ec7 3768 u8 uid[0x10];
e281682b 3769
b4ff3a36 3770 u8 reserved_at_20[0x10];
e281682b
SM		 3771 u8 op_mod[0x10];
3772
b4ff3a36 3773 u8 reserved_at_40[0x8];
e281682b
SM		 3774 u8 qpn[0x18];
3775
b4ff3a36 3776 u8 reserved_at_60[0x20];
e281682b
SM		 3777
3778 u8 opt_param_mask[0x20];
3779
b4ff3a36 3780 u8 reserved_at_a0[0x20];
e281682b
SM		 3781
3782 struct mlx5_ifc_qpc_bits qpc;
3783
b4ff3a36 3784 u8 reserved_at_800[0x80];
e281682b
SM		 3785};
3786
7486216b
SM		 3787struct mlx5_ifc_query_xrq_out_bits {
3788 u8 status[0x8];
3789 u8 reserved_at_8[0x18];
3790
3791 u8 syndrome[0x20];
3792
3793 u8 reserved_at_40[0x40];
3794
3795 struct mlx5_ifc_xrqc_bits xrq_context;
3796};
3797
3798struct mlx5_ifc_query_xrq_in_bits {
3799 u8 opcode[0x10];
3800 u8 reserved_at_10[0x10];
3801
3802 u8 reserved_at_20[0x10];
3803 u8 op_mod[0x10];
3804
3805 u8 reserved_at_40[0x8];
3806 u8 xrqn[0x18];
3807
3808 u8 reserved_at_60[0x20];
3809};
3810
e281682b
SM		 3811struct mlx5_ifc_query_xrc_srq_out_bits {
3812 u8 status[0x8];
b4ff3a36 3813 u8 reserved_at_8[0x18];
e281682b
SM		 3814
3815 u8 syndrome[0x20];
3816
b4ff3a36 3817 u8 reserved_at_40[0x40];
e281682b
SM		 3818
3819 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3820
b4ff3a36 3821 u8 reserved_at_280[0x600];
e281682b
SM		 3822
3823 u8 pas[0][0x40];
3824};
3825
3826struct mlx5_ifc_query_xrc_srq_in_bits {
3827 u8 opcode[0x10];
b4ff3a36 3828 u8 reserved_at_10[0x10];
e281682b 3829
b4ff3a36 3830 u8 reserved_at_20[0x10];
e281682b
SM		 3831 u8 op_mod[0x10];
3832
b4ff3a36 3833 u8 reserved_at_40[0x8];
e281682b
SM		 3834 u8 xrc_srqn[0x18];
3835
b4ff3a36 3836 u8 reserved_at_60[0x20];
e281682b
SM		 3837};
3838
3839enum {
3840 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3841 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3842};
3843
3844struct mlx5_ifc_query_vport_state_out_bits {
3845 u8 status[0x8];
b4ff3a36 3846 u8 reserved_at_8[0x18];
e281682b
SM		 3847
3848 u8 syndrome[0x20];
3849
b4ff3a36 3850 u8 reserved_at_40[0x20];
e281682b 3851
b4ff3a36 3852 u8 reserved_at_60[0x18];
e281682b
SM		 3853 u8 admin_state[0x4];
3854 u8 state[0x4];
3855};
3856
3857enum {
cc9c82a8
EBE		 3858 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
3859 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3860};
3861
fd4572b3
ED		 3862struct mlx5_ifc_arm_monitor_counter_in_bits {
3863 u8 opcode[0x10];
3864 u8 uid[0x10];
3865
3866 u8 reserved_at_20[0x10];
3867 u8 op_mod[0x10];
3868
3869 u8 reserved_at_40[0x20];
3870
3871 u8 reserved_at_60[0x20];
3872};
3873
3874struct mlx5_ifc_arm_monitor_counter_out_bits {
3875 u8 status[0x8];
3876 u8 reserved_at_8[0x18];
3877
3878 u8 syndrome[0x20];
3879
3880 u8 reserved_at_40[0x40];
3881};
3882
3883enum {
3884 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
3885 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
3886};
3887
3888enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 3889 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
3890 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
3891 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
3892 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
3893 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
3894 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 3895};
3896
3897enum {
4c8b8518 3898 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 3899};
3900
3901struct mlx5_ifc_monitor_counter_output_bits {
3902 u8 reserved_at_0[0x4];
3903 u8 type[0x4];
3904 u8 reserved_at_8[0x8];
3905 u8 counter[0x10];
3906
3907 u8 counter_group_id[0x20];
3908};
3909
3910#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
3911#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
3912#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
3913 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
3914
3915struct mlx5_ifc_set_monitor_counter_in_bits {
3916 u8 opcode[0x10];
3917 u8 uid[0x10];
3918
3919 u8 reserved_at_20[0x10];
3920 u8 op_mod[0x10];
3921
3922 u8 reserved_at_40[0x10];
3923 u8 num_of_counters[0x10];
3924
3925 u8 reserved_at_60[0x20];
3926
3927 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
3928};
3929
3930struct mlx5_ifc_set_monitor_counter_out_bits {
3931 u8 status[0x8];
3932 u8 reserved_at_8[0x18];
3933
3934 u8 syndrome[0x20];
3935
3936 u8 reserved_at_40[0x40];
3937};
3938
e281682b
SM		 3939struct mlx5_ifc_query_vport_state_in_bits {
3940 u8 opcode[0x10];
b4ff3a36 3941 u8 reserved_at_10[0x10];
e281682b 3942
b4ff3a36 3943 u8 reserved_at_20[0x10];
e281682b
SM		 3944 u8 op_mod[0x10];
3945
3946 u8 other_vport[0x1];
b4ff3a36 3947 u8 reserved_at_41[0xf];
e281682b
SM		 3948 u8 vport_number[0x10];
3949
b4ff3a36 3950 u8 reserved_at_60[0x20];
e281682b
SM		 3951};
3952
61c5b5c9
MS		 3953struct mlx5_ifc_query_vnic_env_out_bits {
3954 u8 status[0x8];
3955 u8 reserved_at_8[0x18];
3956
3957 u8 syndrome[0x20];
3958
3959 u8 reserved_at_40[0x40];
3960
3961 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3962};
3963
3964enum {
3965 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3966};
3967
3968struct mlx5_ifc_query_vnic_env_in_bits {
3969 u8 opcode[0x10];
3970 u8 reserved_at_10[0x10];
3971
3972 u8 reserved_at_20[0x10];
3973 u8 op_mod[0x10];
3974
3975 u8 other_vport[0x1];
3976 u8 reserved_at_41[0xf];
3977 u8 vport_number[0x10];
3978
3979 u8 reserved_at_60[0x20];
3980};
3981
e281682b
SM		 3982struct mlx5_ifc_query_vport_counter_out_bits {
3983 u8 status[0x8];
b4ff3a36 3984 u8 reserved_at_8[0x18];
e281682b
SM		 3985
3986 u8 syndrome[0x20];
3987
b4ff3a36 3988 u8 reserved_at_40[0x40];
e281682b
SM		 3989
3990 struct mlx5_ifc_traffic_counter_bits received_errors;
3991
3992 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3993
3994 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3995
3996 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3997
3998 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3999
4000 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4001
4002 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4003
4004 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4005
4006 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4007
4008 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4009
4010 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4011
4012 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4013
b4ff3a36 4014 u8 reserved_at_680[0xa00];
e281682b
SM		 4015};
4016
4017enum {
4018 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4019};
4020
4021struct mlx5_ifc_query_vport_counter_in_bits {
4022 u8 opcode[0x10];
b4ff3a36 4023 u8 reserved_at_10[0x10];
e281682b 4024
b4ff3a36 4025 u8 reserved_at_20[0x10];
e281682b
SM		 4026 u8 op_mod[0x10];
4027
4028 u8 other_vport[0x1];
b54ba277
MY		 4029 u8 reserved_at_41[0xb];
4030 u8 port_num[0x4];
e281682b
SM		 4031 u8 vport_number[0x10];
4032
b4ff3a36 4033 u8 reserved_at_60[0x60];
e281682b
SM		 4034
4035 u8 clear[0x1];
b4ff3a36 4036 u8 reserved_at_c1[0x1f];
e281682b 4037
b4ff3a36 4038 u8 reserved_at_e0[0x20];
e281682b
SM		 4039};
4040
4041struct mlx5_ifc_query_tis_out_bits {
4042 u8 status[0x8];
b4ff3a36 4043 u8 reserved_at_8[0x18];
e281682b
SM		 4044
4045 u8 syndrome[0x20];
4046
b4ff3a36 4047 u8 reserved_at_40[0x40];
e281682b
SM		 4048
4049 struct mlx5_ifc_tisc_bits tis_context;
4050};
4051
4052struct mlx5_ifc_query_tis_in_bits {
4053 u8 opcode[0x10];
b4ff3a36 4054 u8 reserved_at_10[0x10];
e281682b 4055
b4ff3a36 4056 u8 reserved_at_20[0x10];
e281682b
SM		 4057 u8 op_mod[0x10];
4058
b4ff3a36 4059 u8 reserved_at_40[0x8];
e281682b
SM		 4060 u8 tisn[0x18];
4061
b4ff3a36 4062 u8 reserved_at_60[0x20];
e281682b
SM		 4063};
4064
4065struct mlx5_ifc_query_tir_out_bits {
4066 u8 status[0x8];
b4ff3a36 4067 u8 reserved_at_8[0x18];
e281682b
SM		 4068
4069 u8 syndrome[0x20];
4070
b4ff3a36 4071 u8 reserved_at_40[0xc0];
e281682b
SM		 4072
4073 struct mlx5_ifc_tirc_bits tir_context;
4074};
4075
4076struct mlx5_ifc_query_tir_in_bits {
4077 u8 opcode[0x10];
b4ff3a36 4078 u8 reserved_at_10[0x10];
e281682b 4079
b4ff3a36 4080 u8 reserved_at_20[0x10];
e281682b
SM		 4081 u8 op_mod[0x10];
4082
b4ff3a36 4083 u8 reserved_at_40[0x8];
e281682b
SM		 4084 u8 tirn[0x18];
4085
b4ff3a36 4086 u8 reserved_at_60[0x20];
e281682b
SM		 4087};
4088
4089struct mlx5_ifc_query_srq_out_bits {
4090 u8 status[0x8];
b4ff3a36 4091 u8 reserved_at_8[0x18];
e281682b
SM		 4092
4093 u8 syndrome[0x20];
4094
b4ff3a36 4095 u8 reserved_at_40[0x40];
e281682b
SM		 4096
4097 struct mlx5_ifc_srqc_bits srq_context_entry;
4098
b4ff3a36 4099 u8 reserved_at_280[0x600];
e281682b
SM		 4100
4101 u8 pas[0][0x40];
4102};
4103
4104struct mlx5_ifc_query_srq_in_bits {
4105 u8 opcode[0x10];
b4ff3a36 4106 u8 reserved_at_10[0x10];
e281682b 4107
b4ff3a36 4108 u8 reserved_at_20[0x10];
e281682b
SM		 4109 u8 op_mod[0x10];
4110
b4ff3a36 4111 u8 reserved_at_40[0x8];
e281682b
SM		 4112 u8 srqn[0x18];
4113
b4ff3a36 4114 u8 reserved_at_60[0x20];
e281682b
SM		 4115};
4116
4117struct mlx5_ifc_query_sq_out_bits {
4118 u8 status[0x8];
b4ff3a36 4119 u8 reserved_at_8[0x18];
e281682b
SM		 4120
4121 u8 syndrome[0x20];
4122
b4ff3a36 4123 u8 reserved_at_40[0xc0];
e281682b
SM		 4124
4125 struct mlx5_ifc_sqc_bits sq_context;
4126};
4127
4128struct mlx5_ifc_query_sq_in_bits {
4129 u8 opcode[0x10];
b4ff3a36 4130 u8 reserved_at_10[0x10];
e281682b 4131
b4ff3a36 4132 u8 reserved_at_20[0x10];
e281682b
SM		 4133 u8 op_mod[0x10];
4134
b4ff3a36 4135 u8 reserved_at_40[0x8];
e281682b
SM		 4136 u8 sqn[0x18];
4137
b4ff3a36 4138 u8 reserved_at_60[0x20];
e281682b
SM		 4139};
4140
4141struct mlx5_ifc_query_special_contexts_out_bits {
4142 u8 status[0x8];
b4ff3a36 4143 u8 reserved_at_8[0x18];
e281682b
SM		 4144
4145 u8 syndrome[0x20];
4146
ec22eb53 4147 u8 dump_fill_mkey[0x20];
e281682b
SM		 4148
4149 u8 resd_lkey[0x20];
bcda1aca
AK		 4150
4151 u8 null_mkey[0x20];
4152
4153 u8 reserved_at_a0[0x60];
e281682b
SM		 4154};
4155
4156struct mlx5_ifc_query_special_contexts_in_bits {
4157 u8 opcode[0x10];
b4ff3a36 4158 u8 reserved_at_10[0x10];
e281682b 4159
b4ff3a36 4160 u8 reserved_at_20[0x10];
e281682b
SM		 4161 u8 op_mod[0x10];
4162
b4ff3a36 4163 u8 reserved_at_40[0x40];
e281682b
SM		 4164};
4165
813f8540
MHY		 4166struct mlx5_ifc_query_scheduling_element_out_bits {
4167 u8 opcode[0x10];
4168 u8 reserved_at_10[0x10];
4169
4170 u8 reserved_at_20[0x10];
4171 u8 op_mod[0x10];
4172
4173 u8 reserved_at_40[0xc0];
4174
4175 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4176
4177 u8 reserved_at_300[0x100];
4178};
4179
4180enum {
4181 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4182};
4183
4184struct mlx5_ifc_query_scheduling_element_in_bits {
4185 u8 opcode[0x10];
4186 u8 reserved_at_10[0x10];
4187
4188 u8 reserved_at_20[0x10];
4189 u8 op_mod[0x10];
4190
4191 u8 scheduling_hierarchy[0x8];
4192 u8 reserved_at_48[0x18];
4193
4194 u8 scheduling_element_id[0x20];
4195
4196 u8 reserved_at_80[0x180];
4197};
4198
e281682b
SM		 4199struct mlx5_ifc_query_rqt_out_bits {
4200 u8 status[0x8];
b4ff3a36 4201 u8 reserved_at_8[0x18];
e281682b
SM		 4202
4203 u8 syndrome[0x20];
4204
b4ff3a36 4205 u8 reserved_at_40[0xc0];
e281682b
SM		 4206
4207 struct mlx5_ifc_rqtc_bits rqt_context;
4208};
4209
4210struct mlx5_ifc_query_rqt_in_bits {
4211 u8 opcode[0x10];
b4ff3a36 4212 u8 reserved_at_10[0x10];
e281682b 4213
b4ff3a36 4214 u8 reserved_at_20[0x10];
e281682b
SM		 4215 u8 op_mod[0x10];
4216
b4ff3a36 4217 u8 reserved_at_40[0x8];
e281682b
SM		 4218 u8 rqtn[0x18];
4219
b4ff3a36 4220 u8 reserved_at_60[0x20];
e281682b
SM		 4221};
4222
4223struct mlx5_ifc_query_rq_out_bits {
4224 u8 status[0x8];
b4ff3a36 4225 u8 reserved_at_8[0x18];
e281682b
SM		 4226
4227 u8 syndrome[0x20];
4228
b4ff3a36 4229 u8 reserved_at_40[0xc0];
e281682b
SM		 4230
4231 struct mlx5_ifc_rqc_bits rq_context;
4232};
4233
4234struct mlx5_ifc_query_rq_in_bits {
4235 u8 opcode[0x10];
b4ff3a36 4236 u8 reserved_at_10[0x10];
e281682b 4237
b4ff3a36 4238 u8 reserved_at_20[0x10];
e281682b
SM		 4239 u8 op_mod[0x10];
4240
b4ff3a36 4241 u8 reserved_at_40[0x8];
e281682b
SM		 4242 u8 rqn[0x18];
4243
b4ff3a36 4244 u8 reserved_at_60[0x20];
e281682b
SM		 4245};
4246
4247struct mlx5_ifc_query_roce_address_out_bits {
4248 u8 status[0x8];
b4ff3a36 4249 u8 reserved_at_8[0x18];
e281682b
SM		 4250
4251 u8 syndrome[0x20];
4252
b4ff3a36 4253 u8 reserved_at_40[0x40];
e281682b
SM		 4254
4255 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4256};
4257
4258struct mlx5_ifc_query_roce_address_in_bits {
4259 u8 opcode[0x10];
b4ff3a36 4260 u8 reserved_at_10[0x10];
e281682b 4261
b4ff3a36 4262 u8 reserved_at_20[0x10];
e281682b
SM		 4263 u8 op_mod[0x10];
4264
4265 u8 roce_address_index[0x10];
32f69e4b
DJ		 4266 u8 reserved_at_50[0xc];
4267 u8 vhca_port_num[0x4];
e281682b 4268
b4ff3a36 4269 u8 reserved_at_60[0x20];
e281682b
SM		 4270};
4271
4272struct mlx5_ifc_query_rmp_out_bits {
4273 u8 status[0x8];
b4ff3a36 4274 u8 reserved_at_8[0x18];
e281682b
SM		 4275
4276 u8 syndrome[0x20];
4277
b4ff3a36 4278 u8 reserved_at_40[0xc0];
e281682b
SM		 4279
4280 struct mlx5_ifc_rmpc_bits rmp_context;
4281};
4282
4283struct mlx5_ifc_query_rmp_in_bits {
4284 u8 opcode[0x10];
b4ff3a36 4285 u8 reserved_at_10[0x10];
e281682b 4286
b4ff3a36 4287 u8 reserved_at_20[0x10];
e281682b
SM		 4288 u8 op_mod[0x10];
4289
b4ff3a36 4290 u8 reserved_at_40[0x8];
e281682b
SM		 4291 u8 rmpn[0x18];
4292
b4ff3a36 4293 u8 reserved_at_60[0x20];
e281682b
SM		 4294};
4295
4296struct mlx5_ifc_query_qp_out_bits {
4297 u8 status[0x8];
b4ff3a36 4298 u8 reserved_at_8[0x18];
e281682b
SM		 4299
4300 u8 syndrome[0x20];
4301
b4ff3a36 4302 u8 reserved_at_40[0x40];
e281682b
SM		 4303
4304 u8 opt_param_mask[0x20];
4305
b4ff3a36 4306 u8 reserved_at_a0[0x20];
e281682b
SM		 4307
4308 struct mlx5_ifc_qpc_bits qpc;
4309
b4ff3a36 4310 u8 reserved_at_800[0x80];
e281682b
SM		 4311
4312 u8 pas[0][0x40];
4313};
4314
4315struct mlx5_ifc_query_qp_in_bits {
4316 u8 opcode[0x10];
b4ff3a36 4317 u8 reserved_at_10[0x10];
e281682b 4318
b4ff3a36 4319 u8 reserved_at_20[0x10];
e281682b
SM		 4320 u8 op_mod[0x10];
4321
b4ff3a36 4322 u8 reserved_at_40[0x8];
e281682b
SM		 4323 u8 qpn[0x18];
4324
b4ff3a36 4325 u8 reserved_at_60[0x20];
e281682b
SM		 4326};
4327
4328struct mlx5_ifc_query_q_counter_out_bits {
4329 u8 status[0x8];
b4ff3a36 4330 u8 reserved_at_8[0x18];
e281682b
SM		 4331
4332 u8 syndrome[0x20];
4333
b4ff3a36 4334 u8 reserved_at_40[0x40];
e281682b
SM		 4335
4336 u8 rx_write_requests[0x20];
4337
b4ff3a36 4338 u8 reserved_at_a0[0x20];
e281682b
SM		 4339
4340 u8 rx_read_requests[0x20];
4341
b4ff3a36 4342 u8 reserved_at_e0[0x20];
e281682b
SM		 4343
4344 u8 rx_atomic_requests[0x20];
4345
b4ff3a36 4346 u8 reserved_at_120[0x20];
e281682b
SM		 4347
4348 u8 rx_dct_connect[0x20];
4349
b4ff3a36 4350 u8 reserved_at_160[0x20];
e281682b
SM		 4351
4352 u8 out_of_buffer[0x20];
4353
b4ff3a36 4354 u8 reserved_at_1a0[0x20];
e281682b
SM		 4355
4356 u8 out_of_sequence[0x20];
4357
7486216b
SM		 4358 u8 reserved_at_1e0[0x20];
4359
4360 u8 duplicate_request[0x20];
4361
4362 u8 reserved_at_220[0x20];
4363
4364 u8 rnr_nak_retry_err[0x20];
4365
4366 u8 reserved_at_260[0x20];
4367
4368 u8 packet_seq_err[0x20];
4369
4370 u8 reserved_at_2a0[0x20];
4371
4372 u8 implied_nak_seq_err[0x20];
4373
4374 u8 reserved_at_2e0[0x20];
4375
4376 u8 local_ack_timeout_err[0x20];
4377
58dcb60a
PP		 4378 u8 reserved_at_320[0xa0];
4379
4380 u8 resp_local_length_error[0x20];
4381
4382 u8 req_local_length_error[0x20];
4383
4384 u8 resp_local_qp_error[0x20];
4385
4386 u8 local_operation_error[0x20];
4387
4388 u8 resp_local_protection[0x20];
4389
4390 u8 req_local_protection[0x20];
4391
4392 u8 resp_cqe_error[0x20];
4393
4394 u8 req_cqe_error[0x20];
4395
4396 u8 req_mw_binding[0x20];
4397
4398 u8 req_bad_response[0x20];
4399
4400 u8 req_remote_invalid_request[0x20];
4401
4402 u8 resp_remote_invalid_request[0x20];
4403
4404 u8 req_remote_access_errors[0x20];
4405
4406 u8 resp_remote_access_errors[0x20];
4407
4408 u8 req_remote_operation_errors[0x20];
4409
4410 u8 req_transport_retries_exceeded[0x20];
4411
4412 u8 cq_overflow[0x20];
4413
4414 u8 resp_cqe_flush_error[0x20];
4415
4416 u8 req_cqe_flush_error[0x20];
4417
4418 u8 reserved_at_620[0x1e0];
e281682b
SM		 4419};
4420
4421struct mlx5_ifc_query_q_counter_in_bits {
4422 u8 opcode[0x10];
b4ff3a36 4423 u8 reserved_at_10[0x10];
e281682b 4424
b4ff3a36 4425 u8 reserved_at_20[0x10];
e281682b
SM		 4426 u8 op_mod[0x10];
4427
b4ff3a36 4428 u8 reserved_at_40[0x80];
e281682b
SM		 4429
4430 u8 clear[0x1];
b4ff3a36 4431 u8 reserved_at_c1[0x1f];
e281682b 4432
b4ff3a36 4433 u8 reserved_at_e0[0x18];
e281682b
SM		 4434 u8 counter_set_id[0x8];
4435};
4436
4437struct mlx5_ifc_query_pages_out_bits {
4438 u8 status[0x8];
b4ff3a36 4439 u8 reserved_at_8[0x18];
e281682b
SM		 4440
4441 u8 syndrome[0x20];
4442
b4ff3a36 4443 u8 reserved_at_40[0x10];
e281682b
SM		 4444 u8 function_id[0x10];
4445
4446 u8 num_pages[0x20];
4447};
4448
4449enum {
4450 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4451 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4452 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4453};
4454
4455struct mlx5_ifc_query_pages_in_bits {
4456 u8 opcode[0x10];
b4ff3a36 4457 u8 reserved_at_10[0x10];
e281682b 4458
b4ff3a36 4459 u8 reserved_at_20[0x10];
e281682b
SM		 4460 u8 op_mod[0x10];
4461
b4ff3a36 4462 u8 reserved_at_40[0x10];
e281682b
SM		 4463 u8 function_id[0x10];
4464
b4ff3a36 4465 u8 reserved_at_60[0x20];
e281682b
SM		 4466};
4467
4468struct mlx5_ifc_query_nic_vport_context_out_bits {
4469 u8 status[0x8];
b4ff3a36 4470 u8 reserved_at_8[0x18];
e281682b
SM		 4471
4472 u8 syndrome[0x20];
4473
b4ff3a36 4474 u8 reserved_at_40[0x40];
e281682b
SM		 4475
4476 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4477};
4478
4479struct mlx5_ifc_query_nic_vport_context_in_bits {
4480 u8 opcode[0x10];
b4ff3a36 4481 u8 reserved_at_10[0x10];
e281682b 4482
b4ff3a36 4483 u8 reserved_at_20[0x10];
e281682b
SM		 4484 u8 op_mod[0x10];
4485
4486 u8 other_vport[0x1];
b4ff3a36 4487 u8 reserved_at_41[0xf];
e281682b
SM		 4488 u8 vport_number[0x10];
4489
b4ff3a36 4490 u8 reserved_at_60[0x5];
e281682b 4491 u8 allowed_list_type[0x3];
b4ff3a36 4492 u8 reserved_at_68[0x18];
e281682b
SM		 4493};
4494
4495struct mlx5_ifc_query_mkey_out_bits {
4496 u8 status[0x8];
b4ff3a36 4497 u8 reserved_at_8[0x18];
e281682b
SM		 4498
4499 u8 syndrome[0x20];
4500
b4ff3a36 4501 u8 reserved_at_40[0x40];
e281682b
SM		 4502
4503 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4504
b4ff3a36 4505 u8 reserved_at_280[0x600];
e281682b
SM		 4506
4507 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4508
4509 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4510};
4511
4512struct mlx5_ifc_query_mkey_in_bits {
4513 u8 opcode[0x10];
b4ff3a36 4514 u8 reserved_at_10[0x10];
e281682b 4515
b4ff3a36 4516 u8 reserved_at_20[0x10];
e281682b
SM		 4517 u8 op_mod[0x10];
4518
b4ff3a36 4519 u8 reserved_at_40[0x8];
e281682b
SM		 4520 u8 mkey_index[0x18];
4521
4522 u8 pg_access[0x1];
b4ff3a36 4523 u8 reserved_at_61[0x1f];
e281682b
SM		 4524};
4525
4526struct mlx5_ifc_query_mad_demux_out_bits {
4527 u8 status[0x8];
b4ff3a36 4528 u8 reserved_at_8[0x18];
e281682b
SM		 4529
4530 u8 syndrome[0x20];
4531
b4ff3a36 4532 u8 reserved_at_40[0x40];
e281682b
SM		 4533
4534 u8 mad_dumux_parameters_block[0x20];
4535};
4536
4537struct mlx5_ifc_query_mad_demux_in_bits {
4538 u8 opcode[0x10];
b4ff3a36 4539 u8 reserved_at_10[0x10];
e281682b 4540
b4ff3a36 4541 u8 reserved_at_20[0x10];
e281682b
SM		 4542 u8 op_mod[0x10];
4543
b4ff3a36 4544 u8 reserved_at_40[0x40];
e281682b
SM		 4545};
4546
4547struct mlx5_ifc_query_l2_table_entry_out_bits {
4548 u8 status[0x8];
b4ff3a36 4549 u8 reserved_at_8[0x18];
e281682b
SM		 4550
4551 u8 syndrome[0x20];
4552
b4ff3a36 4553 u8 reserved_at_40[0xa0];
e281682b 4554
b4ff3a36 4555 u8 reserved_at_e0[0x13];
e281682b
SM		 4556 u8 vlan_valid[0x1];
4557 u8 vlan[0xc];
4558
4559 struct mlx5_ifc_mac_address_layout_bits mac_address;
4560
b4ff3a36 4561 u8 reserved_at_140[0xc0];
e281682b
SM		 4562};
4563
4564struct mlx5_ifc_query_l2_table_entry_in_bits {
4565 u8 opcode[0x10];
b4ff3a36 4566 u8 reserved_at_10[0x10];
e281682b 4567
b4ff3a36 4568 u8 reserved_at_20[0x10];
e281682b
SM		 4569 u8 op_mod[0x10];
4570
b4ff3a36 4571 u8 reserved_at_40[0x60];
e281682b 4572
b4ff3a36 4573 u8 reserved_at_a0[0x8];
e281682b
SM		 4574 u8 table_index[0x18];
4575
b4ff3a36 4576 u8 reserved_at_c0[0x140];
e281682b
SM		 4577};
4578
4579struct mlx5_ifc_query_issi_out_bits {
4580 u8 status[0x8];
b4ff3a36 4581 u8 reserved_at_8[0x18];
e281682b
SM		 4582
4583 u8 syndrome[0x20];
4584
b4ff3a36 4585 u8 reserved_at_40[0x10];
e281682b
SM		 4586 u8 current_issi[0x10];
4587
b4ff3a36 4588 u8 reserved_at_60[0xa0];
e281682b 4589
b4ff3a36 4590 u8 reserved_at_100[76][0x8];
e281682b
SM		 4591 u8 supported_issi_dw0[0x20];
4592};
4593
4594struct mlx5_ifc_query_issi_in_bits {
4595 u8 opcode[0x10];
b4ff3a36 4596 u8 reserved_at_10[0x10];
e281682b 4597
b4ff3a36 4598 u8 reserved_at_20[0x10];
e281682b
SM		 4599 u8 op_mod[0x10];
4600
b4ff3a36 4601 u8 reserved_at_40[0x40];
e281682b
SM		 4602};
4603
0dbc6fe0
SM		 4604struct mlx5_ifc_set_driver_version_out_bits {
4605 u8 status[0x8];
4606 u8 reserved_0[0x18];
4607
4608 u8 syndrome[0x20];
4609 u8 reserved_1[0x40];
4610};
4611
4612struct mlx5_ifc_set_driver_version_in_bits {
4613 u8 opcode[0x10];
4614 u8 reserved_0[0x10];
4615
4616 u8 reserved_1[0x10];
4617 u8 op_mod[0x10];
4618
4619 u8 reserved_2[0x40];
4620 u8 driver_version[64][0x8];
4621};
4622
e281682b
SM		 4623struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4624 u8 status[0x8];
b4ff3a36 4625 u8 reserved_at_8[0x18];
e281682b
SM		 4626
4627 u8 syndrome[0x20];
4628
b4ff3a36 4629 u8 reserved_at_40[0x40];
e281682b
SM		 4630
4631 struct mlx5_ifc_pkey_bits pkey[0];
4632};
4633
4634struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4635 u8 opcode[0x10];
b4ff3a36 4636 u8 reserved_at_10[0x10];
e281682b 4637
b4ff3a36 4638 u8 reserved_at_20[0x10];
e281682b
SM		 4639 u8 op_mod[0x10];
4640
4641 u8 other_vport[0x1];
b4ff3a36 4642 u8 reserved_at_41[0xb];
707c4602 4643 u8 port_num[0x4];
e281682b
SM		 4644 u8 vport_number[0x10];
4645
b4ff3a36 4646 u8 reserved_at_60[0x10];
e281682b
SM		 4647 u8 pkey_index[0x10];
4648};
4649
eff901d3
EC		 4650enum {
4651 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4652 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4653 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4654};
4655
e281682b
SM		 4656struct mlx5_ifc_query_hca_vport_gid_out_bits {
4657 u8 status[0x8];
b4ff3a36 4658 u8 reserved_at_8[0x18];
e281682b
SM		 4659
4660 u8 syndrome[0x20];
4661
b4ff3a36 4662 u8 reserved_at_40[0x20];
e281682b
SM		 4663
4664 u8 gids_num[0x10];
b4ff3a36 4665 u8 reserved_at_70[0x10];
e281682b
SM		 4666
4667 struct mlx5_ifc_array128_auto_bits gid[0];
4668};
4669
4670struct mlx5_ifc_query_hca_vport_gid_in_bits {
4671 u8 opcode[0x10];
b4ff3a36 4672 u8 reserved_at_10[0x10];
e281682b 4673
b4ff3a36 4674 u8 reserved_at_20[0x10];
e281682b
SM		 4675 u8 op_mod[0x10];
4676
4677 u8 other_vport[0x1];
b4ff3a36 4678 u8 reserved_at_41[0xb];
707c4602 4679 u8 port_num[0x4];
e281682b
SM		 4680 u8 vport_number[0x10];
4681
b4ff3a36 4682 u8 reserved_at_60[0x10];
e281682b
SM		 4683 u8 gid_index[0x10];
4684};
4685
4686struct mlx5_ifc_query_hca_vport_context_out_bits {
4687 u8 status[0x8];
b4ff3a36 4688 u8 reserved_at_8[0x18];
e281682b
SM		 4689
4690 u8 syndrome[0x20];
4691
b4ff3a36 4692 u8 reserved_at_40[0x40];
e281682b
SM		 4693
4694 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4695};
4696
4697struct mlx5_ifc_query_hca_vport_context_in_bits {
4698 u8 opcode[0x10];
b4ff3a36 4699 u8 reserved_at_10[0x10];
e281682b 4700
b4ff3a36 4701 u8 reserved_at_20[0x10];
e281682b
SM		 4702 u8 op_mod[0x10];
4703
4704 u8 other_vport[0x1];
b4ff3a36 4705 u8 reserved_at_41[0xb];
707c4602 4706 u8 port_num[0x4];
e281682b
SM		 4707 u8 vport_number[0x10];
4708
b4ff3a36 4709 u8 reserved_at_60[0x20];
e281682b
SM		 4710};
4711
4712struct mlx5_ifc_query_hca_cap_out_bits {
4713 u8 status[0x8];
b4ff3a36 4714 u8 reserved_at_8[0x18];
e281682b
SM		 4715
4716 u8 syndrome[0x20];
4717
b4ff3a36 4718 u8 reserved_at_40[0x40];
e281682b
SM		 4719
4720 union mlx5_ifc_hca_cap_union_bits capability;
4721};
4722
4723struct mlx5_ifc_query_hca_cap_in_bits {
4724 u8 opcode[0x10];
b4ff3a36 4725 u8 reserved_at_10[0x10];
e281682b 4726
b4ff3a36 4727 u8 reserved_at_20[0x10];
e281682b
SM		 4728 u8 op_mod[0x10];
4729
b4ff3a36 4730 u8 reserved_at_40[0x40];
e281682b
SM		 4731};
4732
4733struct mlx5_ifc_query_flow_table_out_bits {
4734 u8 status[0x8];
b4ff3a36 4735 u8 reserved_at_8[0x18];
e281682b
SM		 4736
4737 u8 syndrome[0x20];
4738
b4ff3a36 4739 u8 reserved_at_40[0x80];
e281682b 4740
b4ff3a36 4741 u8 reserved_at_c0[0x8];
e281682b 4742 u8 level[0x8];
b4ff3a36 4743 u8 reserved_at_d0[0x8];
e281682b
SM		 4744 u8 log_size[0x8];
4745
b4ff3a36 4746 u8 reserved_at_e0[0x120];
e281682b
SM		 4747};
4748
4749struct mlx5_ifc_query_flow_table_in_bits {
4750 u8 opcode[0x10];
b4ff3a36 4751 u8 reserved_at_10[0x10];
e281682b 4752
b4ff3a36 4753 u8 reserved_at_20[0x10];
e281682b
SM		 4754 u8 op_mod[0x10];
4755
b4ff3a36 4756 u8 reserved_at_40[0x40];
e281682b
SM		 4757
4758 u8 table_type[0x8];
b4ff3a36 4759 u8 reserved_at_88[0x18];
e281682b 4760
b4ff3a36 4761 u8 reserved_at_a0[0x8];
e281682b
SM		 4762 u8 table_id[0x18];
4763
b4ff3a36 4764 u8 reserved_at_c0[0x140];
e281682b
SM		 4765};
4766
4767struct mlx5_ifc_query_fte_out_bits {
4768 u8 status[0x8];
b4ff3a36 4769 u8 reserved_at_8[0x18];
e281682b
SM		 4770
4771 u8 syndrome[0x20];
4772
b4ff3a36 4773 u8 reserved_at_40[0x1c0];
e281682b
SM		 4774
4775 struct mlx5_ifc_flow_context_bits flow_context;
4776};
4777
4778struct mlx5_ifc_query_fte_in_bits {
4779 u8 opcode[0x10];
b4ff3a36 4780 u8 reserved_at_10[0x10];
e281682b 4781
b4ff3a36 4782 u8 reserved_at_20[0x10];
e281682b
SM		 4783 u8 op_mod[0x10];
4784
b4ff3a36 4785 u8 reserved_at_40[0x40];
e281682b
SM		 4786
4787 u8 table_type[0x8];
b4ff3a36 4788 u8 reserved_at_88[0x18];
e281682b 4789
b4ff3a36 4790 u8 reserved_at_a0[0x8];
e281682b
SM		 4791 u8 table_id[0x18];
4792
b4ff3a36 4793 u8 reserved_at_c0[0x40];
e281682b
SM		 4794
4795 u8 flow_index[0x20];
4796
b4ff3a36 4797 u8 reserved_at_120[0xe0];
e281682b
SM		 4798};
4799
4800enum {
4801 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4802 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4803 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 4804 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 4805};
4806
4807struct mlx5_ifc_query_flow_group_out_bits {
4808 u8 status[0x8];
b4ff3a36 4809 u8 reserved_at_8[0x18];
e281682b
SM		 4810
4811 u8 syndrome[0x20];
4812
b4ff3a36 4813 u8 reserved_at_40[0xa0];
e281682b
SM		 4814
4815 u8 start_flow_index[0x20];
4816
b4ff3a36 4817 u8 reserved_at_100[0x20];
e281682b
SM		 4818
4819 u8 end_flow_index[0x20];
4820
b4ff3a36 4821 u8 reserved_at_140[0xa0];
e281682b 4822
b4ff3a36 4823 u8 reserved_at_1e0[0x18];
e281682b
SM		 4824 u8 match_criteria_enable[0x8];
4825
4826 struct mlx5_ifc_fte_match_param_bits match_criteria;
4827
b4ff3a36 4828 u8 reserved_at_1200[0xe00];
e281682b
SM		 4829};
4830
4831struct mlx5_ifc_query_flow_group_in_bits {
4832 u8 opcode[0x10];
b4ff3a36 4833 u8 reserved_at_10[0x10];
e281682b 4834
b4ff3a36 4835 u8 reserved_at_20[0x10];
e281682b
SM		 4836 u8 op_mod[0x10];
4837
b4ff3a36 4838 u8 reserved_at_40[0x40];
e281682b
SM		 4839
4840 u8 table_type[0x8];
b4ff3a36 4841 u8 reserved_at_88[0x18];
e281682b 4842
b4ff3a36 4843 u8 reserved_at_a0[0x8];
e281682b
SM		 4844 u8 table_id[0x18];
4845
4846 u8 group_id[0x20];
4847
b4ff3a36 4848 u8 reserved_at_e0[0x120];
e281682b
SM		 4849};
4850
9dc0b289
AV		 4851struct mlx5_ifc_query_flow_counter_out_bits {
4852 u8 status[0x8];
4853 u8 reserved_at_8[0x18];
4854
4855 u8 syndrome[0x20];
4856
4857 u8 reserved_at_40[0x40];
4858
4859 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4860};
4861
4862struct mlx5_ifc_query_flow_counter_in_bits {
4863 u8 opcode[0x10];
4864 u8 reserved_at_10[0x10];
4865
4866 u8 reserved_at_20[0x10];
4867 u8 op_mod[0x10];
4868
4869 u8 reserved_at_40[0x80];
4870
4871 u8 clear[0x1];
4872 u8 reserved_at_c1[0xf];
4873 u8 num_of_counters[0x10];
4874
a8ffcc74 4875 u8 flow_counter_id[0x20];
9dc0b289
AV		 4876};
4877
d6666753
SM		 4878struct mlx5_ifc_query_esw_vport_context_out_bits {
4879 u8 status[0x8];
b4ff3a36 4880 u8 reserved_at_8[0x18];
d6666753
SM		 4881
4882 u8 syndrome[0x20];
4883
b4ff3a36 4884 u8 reserved_at_40[0x40];
d6666753
SM		 4885
4886 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4887};
4888
4889struct mlx5_ifc_query_esw_vport_context_in_bits {
4890 u8 opcode[0x10];
b4ff3a36 4891 u8 reserved_at_10[0x10];
d6666753 4892
b4ff3a36 4893 u8 reserved_at_20[0x10];
d6666753
SM		 4894 u8 op_mod[0x10];
4895
4896 u8 other_vport[0x1];
b4ff3a36 4897 u8 reserved_at_41[0xf];
d6666753
SM		 4898 u8 vport_number[0x10];
4899
b4ff3a36 4900 u8 reserved_at_60[0x20];
d6666753
SM		 4901};
4902
4903struct mlx5_ifc_modify_esw_vport_context_out_bits {
4904 u8 status[0x8];
b4ff3a36 4905 u8 reserved_at_8[0x18];
d6666753
SM		 4906
4907 u8 syndrome[0x20];
4908
b4ff3a36 4909 u8 reserved_at_40[0x40];
d6666753
SM		 4910};
4911
4912struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4913 u8 reserved_at_0[0x1c];
d6666753
SM		 4914 u8 vport_cvlan_insert[0x1];
4915 u8 vport_svlan_insert[0x1];
4916 u8 vport_cvlan_strip[0x1];
4917 u8 vport_svlan_strip[0x1];
4918};
4919
4920struct mlx5_ifc_modify_esw_vport_context_in_bits {
4921 u8 opcode[0x10];
b4ff3a36 4922 u8 reserved_at_10[0x10];
d6666753 4923
b4ff3a36 4924 u8 reserved_at_20[0x10];
d6666753
SM		 4925 u8 op_mod[0x10];
4926
4927 u8 other_vport[0x1];
b4ff3a36 4928 u8 reserved_at_41[0xf];
d6666753
SM		 4929 u8 vport_number[0x10];
4930
4931 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4932
4933 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4934};
4935
e281682b
SM		 4936struct mlx5_ifc_query_eq_out_bits {
4937 u8 status[0x8];
b4ff3a36 4938 u8 reserved_at_8[0x18];
e281682b
SM		 4939
4940 u8 syndrome[0x20];
4941
b4ff3a36 4942 u8 reserved_at_40[0x40];
e281682b
SM		 4943
4944 struct mlx5_ifc_eqc_bits eq_context_entry;
4945
b4ff3a36 4946 u8 reserved_at_280[0x40];
e281682b
SM		 4947
4948 u8 event_bitmask[0x40];
4949
b4ff3a36 4950 u8 reserved_at_300[0x580];
e281682b
SM		 4951
4952 u8 pas[0][0x40];
4953};
4954
4955struct mlx5_ifc_query_eq_in_bits {
4956 u8 opcode[0x10];
b4ff3a36 4957 u8 reserved_at_10[0x10];
e281682b 4958
b4ff3a36 4959 u8 reserved_at_20[0x10];
e281682b
SM		 4960 u8 op_mod[0x10];
4961
b4ff3a36 4962 u8 reserved_at_40[0x18];
e281682b
SM		 4963 u8 eq_number[0x8];
4964
b4ff3a36 4965 u8 reserved_at_60[0x20];
e281682b
SM		 4966};
4967
60786f09 4968struct mlx5_ifc_packet_reformat_context_in_bits {
7adbde20 4969 u8 reserved_at_0[0x5];
60786f09 4970 u8 reformat_type[0x3];
7adbde20 4971 u8 reserved_at_8[0xe];
60786f09 4972 u8 reformat_data_size[0xa];
7adbde20
HHZ		 4973
4974 u8 reserved_at_20[0x10];
60786f09 4975 u8 reformat_data[2][0x8];
7adbde20 4976
60786f09 4977 u8 more_reformat_data[0][0x8];
7adbde20
HHZ		 4978};
4979
60786f09 4980struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 4981 u8 status[0x8];
4982 u8 reserved_at_8[0x18];
4983
4984 u8 syndrome[0x20];
4985
4986 u8 reserved_at_40[0xa0];
4987
60786f09 4988 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
7adbde20
HHZ		 4989};
4990
60786f09 4991struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 4992 u8 opcode[0x10];
4993 u8 reserved_at_10[0x10];
4994
4995 u8 reserved_at_20[0x10];
4996 u8 op_mod[0x10];
4997
60786f09 4998 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 4999
5000 u8 reserved_at_60[0xa0];
5001};
5002
60786f09 5003struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5004 u8 status[0x8];
5005 u8 reserved_at_8[0x18];
5006
5007 u8 syndrome[0x20];
5008
60786f09 5009 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5010
5011 u8 reserved_at_60[0x20];
5012};
5013
e0e7a386 5014enum {
60786f09
MB		 5015 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5016 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 5017 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5018 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5019 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
e0e7a386
MB		 5020};
5021
60786f09 5022struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5023 u8 opcode[0x10];
5024 u8 reserved_at_10[0x10];
5025
5026 u8 reserved_at_20[0x10];
5027 u8 op_mod[0x10];
5028
5029 u8 reserved_at_40[0xa0];
5030
60786f09 5031 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 5032};
5033
60786f09 5034struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5035 u8 status[0x8];
5036 u8 reserved_at_8[0x18];
5037
5038 u8 syndrome[0x20];
5039
5040 u8 reserved_at_40[0x40];
5041};
5042
60786f09 5043struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5044 u8 opcode[0x10];
5045 u8 reserved_at_10[0x10];
5046
5047 u8 reserved_20[0x10];
5048 u8 op_mod[0x10];
5049
60786f09 5050 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5051
5052 u8 reserved_60[0x20];
5053};
5054
2a69cb9f
OG		 5055struct mlx5_ifc_set_action_in_bits {
5056 u8 action_type[0x4];
5057 u8 field[0xc];
5058 u8 reserved_at_10[0x3];
5059 u8 offset[0x5];
5060 u8 reserved_at_18[0x3];
5061 u8 length[0x5];
5062
5063 u8 data[0x20];
5064};
5065
5066struct mlx5_ifc_add_action_in_bits {
5067 u8 action_type[0x4];
5068 u8 field[0xc];
5069 u8 reserved_at_10[0x10];
5070
5071 u8 data[0x20];
5072};
5073
5074union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5075 struct mlx5_ifc_set_action_in_bits set_action_in;
5076 struct mlx5_ifc_add_action_in_bits add_action_in;
5077 u8 reserved_at_0[0x40];
5078};
5079
5080enum {
5081 MLX5_ACTION_TYPE_SET = 0x1,
5082 MLX5_ACTION_TYPE_ADD = 0x2,
5083};
5084
5085enum {
5086 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5087 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5088 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5089 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5090 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5091 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5092 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5093 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5094 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5095 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5096 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5097 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5098 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5099 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5100 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5101 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5102 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5103 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5104 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5105 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5106 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5107 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 5108 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 5109};
5110
5111struct mlx5_ifc_alloc_modify_header_context_out_bits {
5112 u8 status[0x8];
5113 u8 reserved_at_8[0x18];
5114
5115 u8 syndrome[0x20];
5116
5117 u8 modify_header_id[0x20];
5118
5119 u8 reserved_at_60[0x20];
5120};
5121
5122struct mlx5_ifc_alloc_modify_header_context_in_bits {
5123 u8 opcode[0x10];
5124 u8 reserved_at_10[0x10];
5125
5126 u8 reserved_at_20[0x10];
5127 u8 op_mod[0x10];
5128
5129 u8 reserved_at_40[0x20];
5130
5131 u8 table_type[0x8];
5132 u8 reserved_at_68[0x10];
5133 u8 num_of_actions[0x8];
5134
5135 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5136};
5137
5138struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5139 u8 status[0x8];
5140 u8 reserved_at_8[0x18];
5141
5142 u8 syndrome[0x20];
5143
5144 u8 reserved_at_40[0x40];
5145};
5146
5147struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5148 u8 opcode[0x10];
5149 u8 reserved_at_10[0x10];
5150
5151 u8 reserved_at_20[0x10];
5152 u8 op_mod[0x10];
5153
5154 u8 modify_header_id[0x20];
5155
5156 u8 reserved_at_60[0x20];
5157};
5158
e281682b
SM		 5159struct mlx5_ifc_query_dct_out_bits {
5160 u8 status[0x8];
b4ff3a36 5161 u8 reserved_at_8[0x18];
e281682b
SM		 5162
5163 u8 syndrome[0x20];
5164
b4ff3a36 5165 u8 reserved_at_40[0x40];
e281682b
SM		 5166
5167 struct mlx5_ifc_dctc_bits dct_context_entry;
5168
b4ff3a36 5169 u8 reserved_at_280[0x180];
e281682b
SM		 5170};
5171
5172struct mlx5_ifc_query_dct_in_bits {
5173 u8 opcode[0x10];
b4ff3a36 5174 u8 reserved_at_10[0x10];
e281682b 5175
b4ff3a36 5176 u8 reserved_at_20[0x10];
e281682b
SM		 5177 u8 op_mod[0x10];
5178
b4ff3a36 5179 u8 reserved_at_40[0x8];
e281682b
SM		 5180 u8 dctn[0x18];
5181
b4ff3a36 5182 u8 reserved_at_60[0x20];
e281682b
SM		 5183};
5184
5185struct mlx5_ifc_query_cq_out_bits {
5186 u8 status[0x8];
b4ff3a36 5187 u8 reserved_at_8[0x18];
e281682b
SM		 5188
5189 u8 syndrome[0x20];
5190
b4ff3a36 5191 u8 reserved_at_40[0x40];
e281682b
SM		 5192
5193 struct mlx5_ifc_cqc_bits cq_context;
5194
b4ff3a36 5195 u8 reserved_at_280[0x600];
e281682b
SM		 5196
5197 u8 pas[0][0x40];
5198};
5199
5200struct mlx5_ifc_query_cq_in_bits {
5201 u8 opcode[0x10];
b4ff3a36 5202 u8 reserved_at_10[0x10];
e281682b 5203
b4ff3a36 5204 u8 reserved_at_20[0x10];
e281682b
SM		 5205 u8 op_mod[0x10];
5206
b4ff3a36 5207 u8 reserved_at_40[0x8];
e281682b
SM		 5208 u8 cqn[0x18];
5209
b4ff3a36 5210 u8 reserved_at_60[0x20];
e281682b
SM		 5211};
5212
5213struct mlx5_ifc_query_cong_status_out_bits {
5214 u8 status[0x8];
b4ff3a36 5215 u8 reserved_at_8[0x18];
e281682b
SM		 5216
5217 u8 syndrome[0x20];
5218
b4ff3a36 5219 u8 reserved_at_40[0x20];
e281682b
SM		 5220
5221 u8 enable[0x1];
5222 u8 tag_enable[0x1];
b4ff3a36 5223 u8 reserved_at_62[0x1e];
e281682b
SM		 5224};
5225
5226struct mlx5_ifc_query_cong_status_in_bits {
5227 u8 opcode[0x10];
b4ff3a36 5228 u8 reserved_at_10[0x10];
e281682b 5229
b4ff3a36 5230 u8 reserved_at_20[0x10];
e281682b
SM		 5231 u8 op_mod[0x10];
5232
b4ff3a36 5233 u8 reserved_at_40[0x18];
e281682b
SM		 5234 u8 priority[0x4];
5235 u8 cong_protocol[0x4];
5236
b4ff3a36 5237 u8 reserved_at_60[0x20];
e281682b
SM		 5238};
5239
5240struct mlx5_ifc_query_cong_statistics_out_bits {
5241 u8 status[0x8];
b4ff3a36 5242 u8 reserved_at_8[0x18];
e281682b
SM		 5243
5244 u8 syndrome[0x20];
5245
b4ff3a36 5246 u8 reserved_at_40[0x40];
e281682b 5247
e1f24a79 5248 u8 rp_cur_flows[0x20];
e281682b
SM		 5249
5250 u8 sum_flows[0x20];
5251
e1f24a79 5252 u8 rp_cnp_ignored_high[0x20];
e281682b 5253
e1f24a79 5254 u8 rp_cnp_ignored_low[0x20];
e281682b 5255
e1f24a79 5256 u8 rp_cnp_handled_high[0x20];
e281682b 5257
e1f24a79 5258 u8 rp_cnp_handled_low[0x20];
e281682b 5259
b4ff3a36 5260 u8 reserved_at_140[0x100];
e281682b
SM		 5261
5262 u8 time_stamp_high[0x20];
5263
5264 u8 time_stamp_low[0x20];
5265
5266 u8 accumulators_period[0x20];
5267
e1f24a79 5268 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5269
e1f24a79 5270 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5271
e1f24a79 5272 u8 np_cnp_sent_high[0x20];
e281682b 5273
e1f24a79 5274 u8 np_cnp_sent_low[0x20];
e281682b 5275
b4ff3a36 5276 u8 reserved_at_320[0x560];
e281682b
SM		 5277};
5278
5279struct mlx5_ifc_query_cong_statistics_in_bits {
5280 u8 opcode[0x10];
b4ff3a36 5281 u8 reserved_at_10[0x10];
e281682b 5282
b4ff3a36 5283 u8 reserved_at_20[0x10];
e281682b
SM		 5284 u8 op_mod[0x10];
5285
5286 u8 clear[0x1];
b4ff3a36 5287 u8 reserved_at_41[0x1f];
e281682b 5288
b4ff3a36 5289 u8 reserved_at_60[0x20];
e281682b
SM		 5290};
5291
5292struct mlx5_ifc_query_cong_params_out_bits {
5293 u8 status[0x8];
b4ff3a36 5294 u8 reserved_at_8[0x18];
e281682b
SM		 5295
5296 u8 syndrome[0x20];
5297
b4ff3a36 5298 u8 reserved_at_40[0x40];
e281682b
SM		 5299
5300 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5301};
5302
5303struct mlx5_ifc_query_cong_params_in_bits {
5304 u8 opcode[0x10];
b4ff3a36 5305 u8 reserved_at_10[0x10];
e281682b 5306
b4ff3a36 5307 u8 reserved_at_20[0x10];
e281682b
SM		 5308 u8 op_mod[0x10];
5309
b4ff3a36 5310 u8 reserved_at_40[0x1c];
e281682b
SM		 5311 u8 cong_protocol[0x4];
5312
b4ff3a36 5313 u8 reserved_at_60[0x20];
e281682b
SM		 5314};
5315
5316struct mlx5_ifc_query_adapter_out_bits {
5317 u8 status[0x8];
b4ff3a36 5318 u8 reserved_at_8[0x18];
e281682b
SM		 5319
5320 u8 syndrome[0x20];
5321
b4ff3a36 5322 u8 reserved_at_40[0x40];
e281682b
SM		 5323
5324 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5325};
5326
5327struct mlx5_ifc_query_adapter_in_bits {
5328 u8 opcode[0x10];
b4ff3a36 5329 u8 reserved_at_10[0x10];
e281682b 5330
b4ff3a36 5331 u8 reserved_at_20[0x10];
e281682b
SM		 5332 u8 op_mod[0x10];
5333
b4ff3a36 5334 u8 reserved_at_40[0x40];
e281682b
SM		 5335};
5336
5337struct mlx5_ifc_qp_2rst_out_bits {
5338 u8 status[0x8];
b4ff3a36 5339 u8 reserved_at_8[0x18];
e281682b
SM		 5340
5341 u8 syndrome[0x20];
5342
b4ff3a36 5343 u8 reserved_at_40[0x40];
e281682b
SM		 5344};
5345
5346struct mlx5_ifc_qp_2rst_in_bits {
5347 u8 opcode[0x10];
4ac63ec7 5348 u8 uid[0x10];
e281682b 5349
b4ff3a36 5350 u8 reserved_at_20[0x10];
e281682b
SM		 5351 u8 op_mod[0x10];
5352
b4ff3a36 5353 u8 reserved_at_40[0x8];
e281682b
SM		 5354 u8 qpn[0x18];
5355
b4ff3a36 5356 u8 reserved_at_60[0x20];
e281682b
SM		 5357};
5358
5359struct mlx5_ifc_qp_2err_out_bits {
5360 u8 status[0x8];
b4ff3a36 5361 u8 reserved_at_8[0x18];
e281682b
SM		 5362
5363 u8 syndrome[0x20];
5364
b4ff3a36 5365 u8 reserved_at_40[0x40];
e281682b
SM		 5366};
5367
5368struct mlx5_ifc_qp_2err_in_bits {
5369 u8 opcode[0x10];
4ac63ec7 5370 u8 uid[0x10];
e281682b 5371
b4ff3a36 5372 u8 reserved_at_20[0x10];
e281682b
SM		 5373 u8 op_mod[0x10];
5374
b4ff3a36 5375 u8 reserved_at_40[0x8];
e281682b
SM		 5376 u8 qpn[0x18];
5377
b4ff3a36 5378 u8 reserved_at_60[0x20];
e281682b
SM		 5379};
5380
5381struct mlx5_ifc_page_fault_resume_out_bits {
5382 u8 status[0x8];
b4ff3a36 5383 u8 reserved_at_8[0x18];
e281682b
SM		 5384
5385 u8 syndrome[0x20];
5386
b4ff3a36 5387 u8 reserved_at_40[0x40];
e281682b
SM		 5388};
5389
5390struct mlx5_ifc_page_fault_resume_in_bits {
5391 u8 opcode[0x10];
b4ff3a36 5392 u8 reserved_at_10[0x10];
e281682b 5393
b4ff3a36 5394 u8 reserved_at_20[0x10];
e281682b
SM		 5395 u8 op_mod[0x10];
5396
5397 u8 error[0x1];
b4ff3a36 5398 u8 reserved_at_41[0x4];
223cdc72
AK		 5399 u8 page_fault_type[0x3];
5400 u8 wq_number[0x18];
e281682b 5401
223cdc72
AK		 5402 u8 reserved_at_60[0x8];
5403 u8 token[0x18];
e281682b
SM		 5404};
5405
5406struct mlx5_ifc_nop_out_bits {
5407 u8 status[0x8];
b4ff3a36 5408 u8 reserved_at_8[0x18];
e281682b
SM		 5409
5410 u8 syndrome[0x20];
5411
b4ff3a36 5412 u8 reserved_at_40[0x40];
e281682b
SM		 5413};
5414
5415struct mlx5_ifc_nop_in_bits {
5416 u8 opcode[0x10];
b4ff3a36 5417 u8 reserved_at_10[0x10];
e281682b 5418
b4ff3a36 5419 u8 reserved_at_20[0x10];
e281682b
SM		 5420 u8 op_mod[0x10];
5421
b4ff3a36 5422 u8 reserved_at_40[0x40];
e281682b
SM		 5423};
5424
5425struct mlx5_ifc_modify_vport_state_out_bits {
5426 u8 status[0x8];
b4ff3a36 5427 u8 reserved_at_8[0x18];
e281682b
SM		 5428
5429 u8 syndrome[0x20];
5430
b4ff3a36 5431 u8 reserved_at_40[0x40];
e281682b
SM		 5432};
5433
5434struct mlx5_ifc_modify_vport_state_in_bits {
5435 u8 opcode[0x10];
b4ff3a36 5436 u8 reserved_at_10[0x10];
e281682b 5437
b4ff3a36 5438 u8 reserved_at_20[0x10];
e281682b
SM		 5439 u8 op_mod[0x10];
5440
5441 u8 other_vport[0x1];
b4ff3a36 5442 u8 reserved_at_41[0xf];
e281682b
SM		 5443 u8 vport_number[0x10];
5444
b4ff3a36 5445 u8 reserved_at_60[0x18];
e281682b 5446 u8 admin_state[0x4];
b4ff3a36 5447 u8 reserved_at_7c[0x4];
e281682b
SM		 5448};
5449
5450struct mlx5_ifc_modify_tis_out_bits {
5451 u8 status[0x8];
b4ff3a36 5452 u8 reserved_at_8[0x18];
e281682b
SM		 5453
5454 u8 syndrome[0x20];
5455
b4ff3a36 5456 u8 reserved_at_40[0x40];
e281682b
SM		 5457};
5458
75850d0b 5459struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5460 u8 reserved_at_0[0x20];
75850d0b 5461
84df61eb
AH		 5462 u8 reserved_at_20[0x1d];
5463 u8 lag_tx_port_affinity[0x1];
5464 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5465 u8 prio[0x1];
5466};
5467
e281682b
SM		 5468struct mlx5_ifc_modify_tis_in_bits {
5469 u8 opcode[0x10];
bd371975 5470 u8 uid[0x10];
e281682b 5471
b4ff3a36 5472 u8 reserved_at_20[0x10];
e281682b
SM		 5473 u8 op_mod[0x10];
5474
b4ff3a36 5475 u8 reserved_at_40[0x8];
e281682b
SM		 5476 u8 tisn[0x18];
5477
b4ff3a36 5478 u8 reserved_at_60[0x20];
e281682b 5479
75850d0b 5480 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5481
b4ff3a36 5482 u8 reserved_at_c0[0x40];
e281682b
SM		 5483
5484 struct mlx5_ifc_tisc_bits ctx;
5485};
5486
d9eea403 5487struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5488 u8 reserved_at_0[0x20];
d9eea403 5489
b4ff3a36 5490 u8 reserved_at_20[0x1b];
66189961 5491 u8 self_lb_en[0x1];
bdfc028d
TT		 5492 u8 reserved_at_3c[0x1];
5493 u8 hash[0x1];
5494 u8 reserved_at_3e[0x1];
d9eea403
AS		 5495 u8 lro[0x1];
5496};
5497
e281682b
SM		 5498struct mlx5_ifc_modify_tir_out_bits {
5499 u8 status[0x8];
b4ff3a36 5500 u8 reserved_at_8[0x18];
e281682b
SM		 5501
5502 u8 syndrome[0x20];
5503
b4ff3a36 5504 u8 reserved_at_40[0x40];
e281682b
SM		 5505};
5506
5507struct mlx5_ifc_modify_tir_in_bits {
5508 u8 opcode[0x10];
bd371975 5509 u8 uid[0x10];
e281682b 5510
b4ff3a36 5511 u8 reserved_at_20[0x10];
e281682b
SM		 5512 u8 op_mod[0x10];
5513
b4ff3a36 5514 u8 reserved_at_40[0x8];
e281682b
SM		 5515 u8 tirn[0x18];
5516
b4ff3a36 5517 u8 reserved_at_60[0x20];
e281682b 5518
d9eea403 5519 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5520
b4ff3a36 5521 u8 reserved_at_c0[0x40];
e281682b
SM		 5522
5523 struct mlx5_ifc_tirc_bits ctx;
5524};
5525
5526struct mlx5_ifc_modify_sq_out_bits {
5527 u8 status[0x8];
b4ff3a36 5528 u8 reserved_at_8[0x18];
e281682b
SM		 5529
5530 u8 syndrome[0x20];
5531
b4ff3a36 5532 u8 reserved_at_40[0x40];
e281682b
SM		 5533};
5534
5535struct mlx5_ifc_modify_sq_in_bits {
5536 u8 opcode[0x10];
430ae0d5 5537 u8 uid[0x10];
e281682b 5538
b4ff3a36 5539 u8 reserved_at_20[0x10];
e281682b
SM		 5540 u8 op_mod[0x10];
5541
5542 u8 sq_state[0x4];
b4ff3a36 5543 u8 reserved_at_44[0x4];
e281682b
SM		 5544 u8 sqn[0x18];
5545
b4ff3a36 5546 u8 reserved_at_60[0x20];
e281682b
SM		 5547
5548 u8 modify_bitmask[0x40];
5549
b4ff3a36 5550 u8 reserved_at_c0[0x40];
e281682b
SM		 5551
5552 struct mlx5_ifc_sqc_bits ctx;
5553};
5554
813f8540
MHY		 5555struct mlx5_ifc_modify_scheduling_element_out_bits {
5556 u8 status[0x8];
5557 u8 reserved_at_8[0x18];
5558
5559 u8 syndrome[0x20];
5560
5561 u8 reserved_at_40[0x1c0];
5562};
5563
5564enum {
5565 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5566 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5567};
5568
5569struct mlx5_ifc_modify_scheduling_element_in_bits {
5570 u8 opcode[0x10];
5571 u8 reserved_at_10[0x10];
5572
5573 u8 reserved_at_20[0x10];
5574 u8 op_mod[0x10];
5575
5576 u8 scheduling_hierarchy[0x8];
5577 u8 reserved_at_48[0x18];
5578
5579 u8 scheduling_element_id[0x20];
5580
5581 u8 reserved_at_80[0x20];
5582
5583 u8 modify_bitmask[0x20];
5584
5585 u8 reserved_at_c0[0x40];
5586
5587 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5588
5589 u8 reserved_at_300[0x100];
5590};
5591
e281682b
SM		 5592struct mlx5_ifc_modify_rqt_out_bits {
5593 u8 status[0x8];
b4ff3a36 5594 u8 reserved_at_8[0x18];
e281682b
SM		 5595
5596 u8 syndrome[0x20];
5597
b4ff3a36 5598 u8 reserved_at_40[0x40];
e281682b
SM		 5599};
5600
5c50368f 5601struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5602 u8 reserved_at_0[0x20];
5c50368f 5603
b4ff3a36 5604 u8 reserved_at_20[0x1f];
5c50368f
AS		 5605 u8 rqn_list[0x1];
5606};
5607
e281682b
SM		 5608struct mlx5_ifc_modify_rqt_in_bits {
5609 u8 opcode[0x10];
bd371975 5610 u8 uid[0x10];
e281682b 5611
b4ff3a36 5612 u8 reserved_at_20[0x10];
e281682b
SM		 5613 u8 op_mod[0x10];
5614
b4ff3a36 5615 u8 reserved_at_40[0x8];
e281682b
SM		 5616 u8 rqtn[0x18];
5617
b4ff3a36 5618 u8 reserved_at_60[0x20];
e281682b 5619
5c50368f 5620 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5621
b4ff3a36 5622 u8 reserved_at_c0[0x40];
e281682b
SM		 5623
5624 struct mlx5_ifc_rqtc_bits ctx;
5625};
5626
5627struct mlx5_ifc_modify_rq_out_bits {
5628 u8 status[0x8];
b4ff3a36 5629 u8 reserved_at_8[0x18];
e281682b
SM		 5630
5631 u8 syndrome[0x20];
5632
b4ff3a36 5633 u8 reserved_at_40[0x40];
e281682b
SM		 5634};
5635
83b502a1
AV		 5636enum {
5637 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5638 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5639 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5640};
5641
e281682b
SM		 5642struct mlx5_ifc_modify_rq_in_bits {
5643 u8 opcode[0x10];
d269b3af 5644 u8 uid[0x10];
e281682b 5645
b4ff3a36 5646 u8 reserved_at_20[0x10];
e281682b
SM		 5647 u8 op_mod[0x10];
5648
5649 u8 rq_state[0x4];
b4ff3a36 5650 u8 reserved_at_44[0x4];
e281682b
SM		 5651 u8 rqn[0x18];
5652
b4ff3a36 5653 u8 reserved_at_60[0x20];
e281682b
SM		 5654
5655 u8 modify_bitmask[0x40];
5656
b4ff3a36 5657 u8 reserved_at_c0[0x40];
e281682b
SM		 5658
5659 struct mlx5_ifc_rqc_bits ctx;
5660};
5661
5662struct mlx5_ifc_modify_rmp_out_bits {
5663 u8 status[0x8];
b4ff3a36 5664 u8 reserved_at_8[0x18];
e281682b
SM		 5665
5666 u8 syndrome[0x20];
5667
b4ff3a36 5668 u8 reserved_at_40[0x40];
e281682b
SM		 5669};
5670
01949d01 5671struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5672 u8 reserved_at_0[0x20];
01949d01 5673
b4ff3a36 5674 u8 reserved_at_20[0x1f];
01949d01
HA		 5675 u8 lwm[0x1];
5676};
5677
e281682b
SM		 5678struct mlx5_ifc_modify_rmp_in_bits {
5679 u8 opcode[0x10];
a0d8c054 5680 u8 uid[0x10];
e281682b 5681
b4ff3a36 5682 u8 reserved_at_20[0x10];
e281682b
SM		 5683 u8 op_mod[0x10];
5684
5685 u8 rmp_state[0x4];
b4ff3a36 5686 u8 reserved_at_44[0x4];
e281682b
SM		 5687 u8 rmpn[0x18];
5688
b4ff3a36 5689 u8 reserved_at_60[0x20];
e281682b 5690
01949d01 5691 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5692
b4ff3a36 5693 u8 reserved_at_c0[0x40];
e281682b
SM		 5694
5695 struct mlx5_ifc_rmpc_bits ctx;
5696};
5697
5698struct mlx5_ifc_modify_nic_vport_context_out_bits {
5699 u8 status[0x8];
b4ff3a36 5700 u8 reserved_at_8[0x18];
e281682b
SM		 5701
5702 u8 syndrome[0x20];
5703
b4ff3a36 5704 u8 reserved_at_40[0x40];
e281682b
SM		 5705};
5706
5707struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5708 u8 reserved_at_0[0x12];
5709 u8 affiliation[0x1];
c74d90c1 5710 u8 reserved_at_13[0x1];
bded747b
HN		 5711 u8 disable_uc_local_lb[0x1];
5712 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5713 u8 node_guid[0x1];
5714 u8 port_guid[0x1];
9def7121 5715 u8 min_inline[0x1];
d82b7318
SM		 5716 u8 mtu[0x1];
5717 u8 change_event[0x1];
5718 u8 promisc[0x1];
e281682b
SM		 5719 u8 permanent_address[0x1];
5720 u8 addresses_list[0x1];
5721 u8 roce_en[0x1];
b4ff3a36 5722 u8 reserved_at_1f[0x1];
e281682b
SM		 5723};
5724
5725struct mlx5_ifc_modify_nic_vport_context_in_bits {
5726 u8 opcode[0x10];
b4ff3a36 5727 u8 reserved_at_10[0x10];
e281682b 5728
b4ff3a36 5729 u8 reserved_at_20[0x10];
e281682b
SM		 5730 u8 op_mod[0x10];
5731
5732 u8 other_vport[0x1];
b4ff3a36 5733 u8 reserved_at_41[0xf];
e281682b
SM		 5734 u8 vport_number[0x10];
5735
5736 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5737
b4ff3a36 5738 u8 reserved_at_80[0x780];
e281682b
SM		 5739
5740 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5741};
5742
5743struct mlx5_ifc_modify_hca_vport_context_out_bits {
5744 u8 status[0x8];
b4ff3a36 5745 u8 reserved_at_8[0x18];
e281682b
SM		 5746
5747 u8 syndrome[0x20];
5748
b4ff3a36 5749 u8 reserved_at_40[0x40];
e281682b
SM		 5750};
5751
5752struct mlx5_ifc_modify_hca_vport_context_in_bits {
5753 u8 opcode[0x10];
b4ff3a36 5754 u8 reserved_at_10[0x10];
e281682b 5755
b4ff3a36 5756 u8 reserved_at_20[0x10];
e281682b
SM		 5757 u8 op_mod[0x10];
5758
5759 u8 other_vport[0x1];
b4ff3a36 5760 u8 reserved_at_41[0xb];
707c4602 5761 u8 port_num[0x4];
e281682b
SM		 5762 u8 vport_number[0x10];
5763
b4ff3a36 5764 u8 reserved_at_60[0x20];
e281682b
SM		 5765
5766 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5767};
5768
5769struct mlx5_ifc_modify_cq_out_bits {
5770 u8 status[0x8];
b4ff3a36 5771 u8 reserved_at_8[0x18];
e281682b
SM		 5772
5773 u8 syndrome[0x20];
5774
b4ff3a36 5775 u8 reserved_at_40[0x40];
e281682b
SM		 5776};
5777
5778enum {
5779 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5780 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5781};
5782
5783struct mlx5_ifc_modify_cq_in_bits {
5784 u8 opcode[0x10];
9ba481e2 5785 u8 uid[0x10];
e281682b 5786
b4ff3a36 5787 u8 reserved_at_20[0x10];
e281682b
SM		 5788 u8 op_mod[0x10];
5789
b4ff3a36 5790 u8 reserved_at_40[0x8];
e281682b
SM		 5791 u8 cqn[0x18];
5792
5793 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5794
5795 struct mlx5_ifc_cqc_bits cq_context;
5796
bd371975
LR		 5797 u8 reserved_at_280[0x40];
5798
5799 u8 cq_umem_valid[0x1];
5800 u8 reserved_at_2c1[0x5bf];
e281682b
SM		 5801
5802 u8 pas[0][0x40];
5803};
5804
5805struct mlx5_ifc_modify_cong_status_out_bits {
5806 u8 status[0x8];
b4ff3a36 5807 u8 reserved_at_8[0x18];
e281682b
SM		 5808
5809 u8 syndrome[0x20];
5810
b4ff3a36 5811 u8 reserved_at_40[0x40];
e281682b
SM		 5812};
5813
5814struct mlx5_ifc_modify_cong_status_in_bits {
5815 u8 opcode[0x10];
b4ff3a36 5816 u8 reserved_at_10[0x10];
e281682b 5817
b4ff3a36 5818 u8 reserved_at_20[0x10];
e281682b
SM		 5819 u8 op_mod[0x10];
5820
b4ff3a36 5821 u8 reserved_at_40[0x18];
e281682b
SM		 5822 u8 priority[0x4];
5823 u8 cong_protocol[0x4];
5824
5825 u8 enable[0x1];
5826 u8 tag_enable[0x1];
b4ff3a36 5827 u8 reserved_at_62[0x1e];
e281682b
SM		 5828};
5829
5830struct mlx5_ifc_modify_cong_params_out_bits {
5831 u8 status[0x8];
b4ff3a36 5832 u8 reserved_at_8[0x18];
e281682b
SM		 5833
5834 u8 syndrome[0x20];
5835
b4ff3a36 5836 u8 reserved_at_40[0x40];
e281682b
SM		 5837};
5838
5839struct mlx5_ifc_modify_cong_params_in_bits {
5840 u8 opcode[0x10];
b4ff3a36 5841 u8 reserved_at_10[0x10];
e281682b 5842
b4ff3a36 5843 u8 reserved_at_20[0x10];
e281682b
SM		 5844 u8 op_mod[0x10];
5845
b4ff3a36 5846 u8 reserved_at_40[0x1c];
e281682b
SM		 5847 u8 cong_protocol[0x4];
5848
5849 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5850
b4ff3a36 5851 u8 reserved_at_80[0x80];
e281682b
SM		 5852
5853 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5854};
5855
5856struct mlx5_ifc_manage_pages_out_bits {
5857 u8 status[0x8];
b4ff3a36 5858 u8 reserved_at_8[0x18];
e281682b
SM		 5859
5860 u8 syndrome[0x20];
5861
5862 u8 output_num_entries[0x20];
5863
b4ff3a36 5864 u8 reserved_at_60[0x20];
e281682b
SM		 5865
5866 u8 pas[0][0x40];
5867};
5868
5869enum {
5870 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5871 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5872 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5873};
5874
5875struct mlx5_ifc_manage_pages_in_bits {
5876 u8 opcode[0x10];
b4ff3a36 5877 u8 reserved_at_10[0x10];
e281682b 5878
b4ff3a36 5879 u8 reserved_at_20[0x10];
e281682b
SM		 5880 u8 op_mod[0x10];
5881
b4ff3a36 5882 u8 reserved_at_40[0x10];
e281682b
SM		 5883 u8 function_id[0x10];
5884
5885 u8 input_num_entries[0x20];
5886
5887 u8 pas[0][0x40];
5888};
5889
5890struct mlx5_ifc_mad_ifc_out_bits {
5891 u8 status[0x8];
b4ff3a36 5892 u8 reserved_at_8[0x18];
e281682b
SM		 5893
5894 u8 syndrome[0x20];
5895
b4ff3a36 5896 u8 reserved_at_40[0x40];
e281682b
SM		 5897
5898 u8 response_mad_packet[256][0x8];
5899};
5900
5901struct mlx5_ifc_mad_ifc_in_bits {
5902 u8 opcode[0x10];
b4ff3a36 5903 u8 reserved_at_10[0x10];
e281682b 5904
b4ff3a36 5905 u8 reserved_at_20[0x10];
e281682b
SM		 5906 u8 op_mod[0x10];
5907
5908 u8 remote_lid[0x10];
b4ff3a36 5909 u8 reserved_at_50[0x8];
e281682b
SM		 5910 u8 port[0x8];
5911
b4ff3a36 5912 u8 reserved_at_60[0x20];
e281682b
SM		 5913
5914 u8 mad[256][0x8];
5915};
5916
5917struct mlx5_ifc_init_hca_out_bits {
5918 u8 status[0x8];
b4ff3a36 5919 u8 reserved_at_8[0x18];
e281682b
SM		 5920
5921 u8 syndrome[0x20];
5922
b4ff3a36 5923 u8 reserved_at_40[0x40];
e281682b
SM		 5924};
5925
5926struct mlx5_ifc_init_hca_in_bits {
5927 u8 opcode[0x10];
b4ff3a36 5928 u8 reserved_at_10[0x10];
e281682b 5929
b4ff3a36 5930 u8 reserved_at_20[0x10];
e281682b
SM		 5931 u8 op_mod[0x10];
5932
b4ff3a36 5933 u8 reserved_at_40[0x40];
8737f818 5934 u8 sw_owner_id[4][0x20];
e281682b
SM		 5935};
5936
5937struct mlx5_ifc_init2rtr_qp_out_bits {
5938 u8 status[0x8];
b4ff3a36 5939 u8 reserved_at_8[0x18];
e281682b
SM		 5940
5941 u8 syndrome[0x20];
5942
b4ff3a36 5943 u8 reserved_at_40[0x40];
e281682b
SM		 5944};
5945
5946struct mlx5_ifc_init2rtr_qp_in_bits {
5947 u8 opcode[0x10];
4ac63ec7 5948 u8 uid[0x10];
e281682b 5949
b4ff3a36 5950 u8 reserved_at_20[0x10];
e281682b
SM		 5951 u8 op_mod[0x10];
5952
b4ff3a36 5953 u8 reserved_at_40[0x8];
e281682b
SM		 5954 u8 qpn[0x18];
5955
b4ff3a36 5956 u8 reserved_at_60[0x20];
e281682b
SM		 5957
5958 u8 opt_param_mask[0x20];
5959
b4ff3a36 5960 u8 reserved_at_a0[0x20];
e281682b
SM		 5961
5962 struct mlx5_ifc_qpc_bits qpc;
5963
b4ff3a36 5964 u8 reserved_at_800[0x80];
e281682b
SM		 5965};
5966
5967struct mlx5_ifc_init2init_qp_out_bits {
5968 u8 status[0x8];
b4ff3a36 5969 u8 reserved_at_8[0x18];
e281682b
SM		 5970
5971 u8 syndrome[0x20];
5972
b4ff3a36 5973 u8 reserved_at_40[0x40];
e281682b
SM		 5974};
5975
5976struct mlx5_ifc_init2init_qp_in_bits {
5977 u8 opcode[0x10];
4ac63ec7 5978 u8 uid[0x10];
e281682b 5979
b4ff3a36 5980 u8 reserved_at_20[0x10];
e281682b
SM		 5981 u8 op_mod[0x10];
5982
b4ff3a36 5983 u8 reserved_at_40[0x8];
e281682b
SM		 5984 u8 qpn[0x18];
5985
b4ff3a36 5986 u8 reserved_at_60[0x20];
e281682b
SM		 5987
5988 u8 opt_param_mask[0x20];
5989
b4ff3a36 5990 u8 reserved_at_a0[0x20];
e281682b
SM		 5991
5992 struct mlx5_ifc_qpc_bits qpc;
5993
b4ff3a36 5994 u8 reserved_at_800[0x80];
e281682b
SM		 5995};
5996
5997struct mlx5_ifc_get_dropped_packet_log_out_bits {
5998 u8 status[0x8];
b4ff3a36 5999 u8 reserved_at_8[0x18];
e281682b
SM		 6000
6001 u8 syndrome[0x20];
6002
b4ff3a36 6003 u8 reserved_at_40[0x40];
e281682b
SM		 6004
6005 u8 packet_headers_log[128][0x8];
6006
6007 u8 packet_syndrome[64][0x8];
6008};
6009
6010struct mlx5_ifc_get_dropped_packet_log_in_bits {
6011 u8 opcode[0x10];
b4ff3a36 6012 u8 reserved_at_10[0x10];
e281682b 6013
b4ff3a36 6014 u8 reserved_at_20[0x10];
e281682b
SM		 6015 u8 op_mod[0x10];
6016
b4ff3a36 6017 u8 reserved_at_40[0x40];
e281682b
SM		 6018};
6019
6020struct mlx5_ifc_gen_eqe_in_bits {
6021 u8 opcode[0x10];
b4ff3a36 6022 u8 reserved_at_10[0x10];
e281682b 6023
b4ff3a36 6024 u8 reserved_at_20[0x10];
e281682b
SM		 6025 u8 op_mod[0x10];
6026
b4ff3a36 6027 u8 reserved_at_40[0x18];
e281682b
SM		 6028 u8 eq_number[0x8];
6029
b4ff3a36 6030 u8 reserved_at_60[0x20];
e281682b
SM		 6031
6032 u8 eqe[64][0x8];
6033};
6034
6035struct mlx5_ifc_gen_eq_out_bits {
6036 u8 status[0x8];
b4ff3a36 6037 u8 reserved_at_8[0x18];
e281682b
SM		 6038
6039 u8 syndrome[0x20];
6040
b4ff3a36 6041 u8 reserved_at_40[0x40];
e281682b
SM		 6042};
6043
6044struct mlx5_ifc_enable_hca_out_bits {
6045 u8 status[0x8];
b4ff3a36 6046 u8 reserved_at_8[0x18];
e281682b
SM		 6047
6048 u8 syndrome[0x20];
6049
b4ff3a36 6050 u8 reserved_at_40[0x20];
e281682b
SM		 6051};
6052
6053struct mlx5_ifc_enable_hca_in_bits {
6054 u8 opcode[0x10];
b4ff3a36 6055 u8 reserved_at_10[0x10];
e281682b 6056
b4ff3a36 6057 u8 reserved_at_20[0x10];
e281682b
SM		 6058 u8 op_mod[0x10];
6059
b4ff3a36 6060 u8 reserved_at_40[0x10];
e281682b
SM		 6061 u8 function_id[0x10];
6062
b4ff3a36 6063 u8 reserved_at_60[0x20];
e281682b
SM		 6064};
6065
6066struct mlx5_ifc_drain_dct_out_bits {
6067 u8 status[0x8];
b4ff3a36 6068 u8 reserved_at_8[0x18];
e281682b
SM		 6069
6070 u8 syndrome[0x20];
6071
b4ff3a36 6072 u8 reserved_at_40[0x40];
e281682b
SM		 6073};
6074
6075struct mlx5_ifc_drain_dct_in_bits {
6076 u8 opcode[0x10];
774ea6ee 6077 u8 uid[0x10];
e281682b 6078
b4ff3a36 6079 u8 reserved_at_20[0x10];
e281682b
SM		 6080 u8 op_mod[0x10];
6081
b4ff3a36 6082 u8 reserved_at_40[0x8];
e281682b
SM		 6083 u8 dctn[0x18];
6084
b4ff3a36 6085 u8 reserved_at_60[0x20];
e281682b
SM		 6086};
6087
6088struct mlx5_ifc_disable_hca_out_bits {
6089 u8 status[0x8];
b4ff3a36 6090 u8 reserved_at_8[0x18];
e281682b
SM		 6091
6092 u8 syndrome[0x20];
6093
b4ff3a36 6094 u8 reserved_at_40[0x20];
e281682b
SM		 6095};
6096
6097struct mlx5_ifc_disable_hca_in_bits {
6098 u8 opcode[0x10];
b4ff3a36 6099 u8 reserved_at_10[0x10];
e281682b 6100
b4ff3a36 6101 u8 reserved_at_20[0x10];
e281682b
SM		 6102 u8 op_mod[0x10];
6103
b4ff3a36 6104 u8 reserved_at_40[0x10];
e281682b
SM		 6105 u8 function_id[0x10];
6106
b4ff3a36 6107 u8 reserved_at_60[0x20];
e281682b
SM		 6108};
6109
6110struct mlx5_ifc_detach_from_mcg_out_bits {
6111 u8 status[0x8];
b4ff3a36 6112 u8 reserved_at_8[0x18];
e281682b
SM		 6113
6114 u8 syndrome[0x20];
6115
b4ff3a36 6116 u8 reserved_at_40[0x40];
e281682b
SM		 6117};
6118
6119struct mlx5_ifc_detach_from_mcg_in_bits {
6120 u8 opcode[0x10];
bd371975 6121 u8 uid[0x10];
e281682b 6122
b4ff3a36 6123 u8 reserved_at_20[0x10];
e281682b
SM		 6124 u8 op_mod[0x10];
6125
b4ff3a36 6126 u8 reserved_at_40[0x8];
e281682b
SM		 6127 u8 qpn[0x18];
6128
b4ff3a36 6129 u8 reserved_at_60[0x20];
e281682b
SM		 6130
6131 u8 multicast_gid[16][0x8];
6132};
6133
7486216b
SM		 6134struct mlx5_ifc_destroy_xrq_out_bits {
6135 u8 status[0x8];
6136 u8 reserved_at_8[0x18];
6137
6138 u8 syndrome[0x20];
6139
6140 u8 reserved_at_40[0x40];
6141};
6142
6143struct mlx5_ifc_destroy_xrq_in_bits {
6144 u8 opcode[0x10];
a0d8c054 6145 u8 uid[0x10];
7486216b
SM		 6146
6147 u8 reserved_at_20[0x10];
6148 u8 op_mod[0x10];
6149
6150 u8 reserved_at_40[0x8];
6151 u8 xrqn[0x18];
6152
6153 u8 reserved_at_60[0x20];
6154};
6155
e281682b
SM		 6156struct mlx5_ifc_destroy_xrc_srq_out_bits {
6157 u8 status[0x8];
b4ff3a36 6158 u8 reserved_at_8[0x18];
e281682b
SM		 6159
6160 u8 syndrome[0x20];
6161
b4ff3a36 6162 u8 reserved_at_40[0x40];
e281682b
SM		 6163};
6164
6165struct mlx5_ifc_destroy_xrc_srq_in_bits {
6166 u8 opcode[0x10];
a0d8c054 6167 u8 uid[0x10];
e281682b 6168
b4ff3a36 6169 u8 reserved_at_20[0x10];
e281682b
SM		 6170 u8 op_mod[0x10];
6171
b4ff3a36 6172 u8 reserved_at_40[0x8];
e281682b
SM		 6173 u8 xrc_srqn[0x18];
6174
b4ff3a36 6175 u8 reserved_at_60[0x20];
e281682b
SM		 6176};
6177
6178struct mlx5_ifc_destroy_tis_out_bits {
6179 u8 status[0x8];
b4ff3a36 6180 u8 reserved_at_8[0x18];
e281682b
SM		 6181
6182 u8 syndrome[0x20];
6183
b4ff3a36 6184 u8 reserved_at_40[0x40];
e281682b
SM		 6185};
6186
6187struct mlx5_ifc_destroy_tis_in_bits {
6188 u8 opcode[0x10];
bd371975 6189 u8 uid[0x10];
e281682b 6190
b4ff3a36 6191 u8 reserved_at_20[0x10];
e281682b
SM		 6192 u8 op_mod[0x10];
6193
b4ff3a36 6194 u8 reserved_at_40[0x8];
e281682b
SM		 6195 u8 tisn[0x18];
6196
b4ff3a36 6197 u8 reserved_at_60[0x20];
e281682b
SM		 6198};
6199
6200struct mlx5_ifc_destroy_tir_out_bits {
6201 u8 status[0x8];
b4ff3a36 6202 u8 reserved_at_8[0x18];
e281682b
SM		 6203
6204 u8 syndrome[0x20];
6205
b4ff3a36 6206 u8 reserved_at_40[0x40];
e281682b
SM		 6207};
6208
6209struct mlx5_ifc_destroy_tir_in_bits {
6210 u8 opcode[0x10];
bd371975 6211 u8 uid[0x10];
e281682b 6212
b4ff3a36 6213 u8 reserved_at_20[0x10];
e281682b
SM		 6214 u8 op_mod[0x10];
6215
b4ff3a36 6216 u8 reserved_at_40[0x8];
e281682b
SM		 6217 u8 tirn[0x18];
6218
b4ff3a36 6219 u8 reserved_at_60[0x20];
e281682b
SM		 6220};
6221
6222struct mlx5_ifc_destroy_srq_out_bits {
6223 u8 status[0x8];
b4ff3a36 6224 u8 reserved_at_8[0x18];
e281682b
SM		 6225
6226 u8 syndrome[0x20];
6227
b4ff3a36 6228 u8 reserved_at_40[0x40];
e281682b
SM		 6229};
6230
6231struct mlx5_ifc_destroy_srq_in_bits {
6232 u8 opcode[0x10];
a0d8c054 6233 u8 uid[0x10];
e281682b 6234
b4ff3a36 6235 u8 reserved_at_20[0x10];
e281682b
SM		 6236 u8 op_mod[0x10];
6237
b4ff3a36 6238 u8 reserved_at_40[0x8];
e281682b
SM		 6239 u8 srqn[0x18];
6240
b4ff3a36 6241 u8 reserved_at_60[0x20];
e281682b
SM		 6242};
6243
6244struct mlx5_ifc_destroy_sq_out_bits {
6245 u8 status[0x8];
b4ff3a36 6246 u8 reserved_at_8[0x18];
e281682b
SM		 6247
6248 u8 syndrome[0x20];
6249
b4ff3a36 6250 u8 reserved_at_40[0x40];
e281682b
SM		 6251};
6252
6253struct mlx5_ifc_destroy_sq_in_bits {
6254 u8 opcode[0x10];
430ae0d5 6255 u8 uid[0x10];
e281682b 6256
b4ff3a36 6257 u8 reserved_at_20[0x10];
e281682b
SM		 6258 u8 op_mod[0x10];
6259
b4ff3a36 6260 u8 reserved_at_40[0x8];
e281682b
SM		 6261 u8 sqn[0x18];
6262
b4ff3a36 6263 u8 reserved_at_60[0x20];
e281682b
SM		 6264};
6265
813f8540
MHY		 6266struct mlx5_ifc_destroy_scheduling_element_out_bits {
6267 u8 status[0x8];
6268 u8 reserved_at_8[0x18];
6269
6270 u8 syndrome[0x20];
6271
6272 u8 reserved_at_40[0x1c0];
6273};
6274
6275struct mlx5_ifc_destroy_scheduling_element_in_bits {
6276 u8 opcode[0x10];
6277 u8 reserved_at_10[0x10];
6278
6279 u8 reserved_at_20[0x10];
6280 u8 op_mod[0x10];
6281
6282 u8 scheduling_hierarchy[0x8];
6283 u8 reserved_at_48[0x18];
6284
6285 u8 scheduling_element_id[0x20];
6286
6287 u8 reserved_at_80[0x180];
6288};
6289
e281682b
SM		 6290struct mlx5_ifc_destroy_rqt_out_bits {
6291 u8 status[0x8];
b4ff3a36 6292 u8 reserved_at_8[0x18];
e281682b
SM		 6293
6294 u8 syndrome[0x20];
6295
b4ff3a36 6296 u8 reserved_at_40[0x40];
e281682b
SM		 6297};
6298
6299struct mlx5_ifc_destroy_rqt_in_bits {
6300 u8 opcode[0x10];
bd371975 6301 u8 uid[0x10];
e281682b 6302
b4ff3a36 6303 u8 reserved_at_20[0x10];
e281682b
SM		 6304 u8 op_mod[0x10];
6305
b4ff3a36 6306 u8 reserved_at_40[0x8];
e281682b
SM		 6307 u8 rqtn[0x18];
6308
b4ff3a36 6309 u8 reserved_at_60[0x20];
e281682b
SM		 6310};
6311
6312struct mlx5_ifc_destroy_rq_out_bits {
6313 u8 status[0x8];
b4ff3a36 6314 u8 reserved_at_8[0x18];
e281682b
SM		 6315
6316 u8 syndrome[0x20];
6317
b4ff3a36 6318 u8 reserved_at_40[0x40];
e281682b
SM		 6319};
6320
6321struct mlx5_ifc_destroy_rq_in_bits {
6322 u8 opcode[0x10];
d269b3af 6323 u8 uid[0x10];
e281682b 6324
b4ff3a36 6325 u8 reserved_at_20[0x10];
e281682b
SM		 6326 u8 op_mod[0x10];
6327
b4ff3a36 6328 u8 reserved_at_40[0x8];
e281682b
SM		 6329 u8 rqn[0x18];
6330
b4ff3a36 6331 u8 reserved_at_60[0x20];
e281682b
SM		 6332};
6333
c1e0bfc1
MG		 6334struct mlx5_ifc_set_delay_drop_params_in_bits {
6335 u8 opcode[0x10];
6336 u8 reserved_at_10[0x10];
6337
6338 u8 reserved_at_20[0x10];
6339 u8 op_mod[0x10];
6340
6341 u8 reserved_at_40[0x20];
6342
6343 u8 reserved_at_60[0x10];
6344 u8 delay_drop_timeout[0x10];
6345};
6346
6347struct mlx5_ifc_set_delay_drop_params_out_bits {
6348 u8 status[0x8];
6349 u8 reserved_at_8[0x18];
6350
6351 u8 syndrome[0x20];
6352
6353 u8 reserved_at_40[0x40];
6354};
6355
e281682b
SM		 6356struct mlx5_ifc_destroy_rmp_out_bits {
6357 u8 status[0x8];
b4ff3a36 6358 u8 reserved_at_8[0x18];
e281682b
SM		 6359
6360 u8 syndrome[0x20];
6361
b4ff3a36 6362 u8 reserved_at_40[0x40];
e281682b
SM		 6363};
6364
6365struct mlx5_ifc_destroy_rmp_in_bits {
6366 u8 opcode[0x10];
a0d8c054 6367 u8 uid[0x10];
e281682b 6368
b4ff3a36 6369 u8 reserved_at_20[0x10];
e281682b
SM		 6370 u8 op_mod[0x10];
6371
b4ff3a36 6372 u8 reserved_at_40[0x8];
e281682b
SM		 6373 u8 rmpn[0x18];
6374
b4ff3a36 6375 u8 reserved_at_60[0x20];
e281682b
SM		 6376};
6377
6378struct mlx5_ifc_destroy_qp_out_bits {
6379 u8 status[0x8];
b4ff3a36 6380 u8 reserved_at_8[0x18];
e281682b
SM		 6381
6382 u8 syndrome[0x20];
6383
b4ff3a36 6384 u8 reserved_at_40[0x40];
e281682b
SM		 6385};
6386
6387struct mlx5_ifc_destroy_qp_in_bits {
6388 u8 opcode[0x10];
4ac63ec7 6389 u8 uid[0x10];
e281682b 6390
b4ff3a36 6391 u8 reserved_at_20[0x10];
e281682b
SM		 6392 u8 op_mod[0x10];
6393
b4ff3a36 6394 u8 reserved_at_40[0x8];
e281682b
SM		 6395 u8 qpn[0x18];
6396
b4ff3a36 6397 u8 reserved_at_60[0x20];
e281682b
SM		 6398};
6399
6400struct mlx5_ifc_destroy_psv_out_bits {
6401 u8 status[0x8];
b4ff3a36 6402 u8 reserved_at_8[0x18];
e281682b
SM		 6403
6404 u8 syndrome[0x20];
6405
b4ff3a36 6406 u8 reserved_at_40[0x40];
e281682b
SM		 6407};
6408
6409struct mlx5_ifc_destroy_psv_in_bits {
6410 u8 opcode[0x10];
b4ff3a36 6411 u8 reserved_at_10[0x10];
e281682b 6412
b4ff3a36 6413 u8 reserved_at_20[0x10];
e281682b
SM		 6414 u8 op_mod[0x10];
6415
b4ff3a36 6416 u8 reserved_at_40[0x8];
e281682b
SM		 6417 u8 psvn[0x18];
6418
b4ff3a36 6419 u8 reserved_at_60[0x20];
e281682b
SM		 6420};
6421
6422struct mlx5_ifc_destroy_mkey_out_bits {
6423 u8 status[0x8];
b4ff3a36 6424 u8 reserved_at_8[0x18];
e281682b
SM		 6425
6426 u8 syndrome[0x20];
6427
b4ff3a36 6428 u8 reserved_at_40[0x40];
e281682b
SM		 6429};
6430
6431struct mlx5_ifc_destroy_mkey_in_bits {
6432 u8 opcode[0x10];
b4ff3a36 6433 u8 reserved_at_10[0x10];
e281682b 6434
b4ff3a36 6435 u8 reserved_at_20[0x10];
e281682b
SM		 6436 u8 op_mod[0x10];
6437
b4ff3a36 6438 u8 reserved_at_40[0x8];
e281682b
SM		 6439 u8 mkey_index[0x18];
6440
b4ff3a36 6441 u8 reserved_at_60[0x20];
e281682b
SM		 6442};
6443
6444struct mlx5_ifc_destroy_flow_table_out_bits {
6445 u8 status[0x8];
b4ff3a36 6446 u8 reserved_at_8[0x18];
e281682b
SM		 6447
6448 u8 syndrome[0x20];
6449
b4ff3a36 6450 u8 reserved_at_40[0x40];
e281682b
SM		 6451};
6452
6453struct mlx5_ifc_destroy_flow_table_in_bits {
6454 u8 opcode[0x10];
b4ff3a36 6455 u8 reserved_at_10[0x10];
e281682b 6456
b4ff3a36 6457 u8 reserved_at_20[0x10];
e281682b
SM		 6458 u8 op_mod[0x10];
6459
7d5e1423
SM		 6460 u8 other_vport[0x1];
6461 u8 reserved_at_41[0xf];
6462 u8 vport_number[0x10];
6463
6464 u8 reserved_at_60[0x20];
e281682b
SM		 6465
6466 u8 table_type[0x8];
b4ff3a36 6467 u8 reserved_at_88[0x18];
e281682b 6468
b4ff3a36 6469 u8 reserved_at_a0[0x8];
e281682b
SM		 6470 u8 table_id[0x18];
6471
b4ff3a36 6472 u8 reserved_at_c0[0x140];
e281682b
SM		 6473};
6474
6475struct mlx5_ifc_destroy_flow_group_out_bits {
6476 u8 status[0x8];
b4ff3a36 6477 u8 reserved_at_8[0x18];
e281682b
SM		 6478
6479 u8 syndrome[0x20];
6480
b4ff3a36 6481 u8 reserved_at_40[0x40];
e281682b
SM		 6482};
6483
6484struct mlx5_ifc_destroy_flow_group_in_bits {
6485 u8 opcode[0x10];
b4ff3a36 6486 u8 reserved_at_10[0x10];
e281682b 6487
b4ff3a36 6488 u8 reserved_at_20[0x10];
e281682b
SM		 6489 u8 op_mod[0x10];
6490
7d5e1423
SM		 6491 u8 other_vport[0x1];
6492 u8 reserved_at_41[0xf];
6493 u8 vport_number[0x10];
6494
6495 u8 reserved_at_60[0x20];
e281682b
SM		 6496
6497 u8 table_type[0x8];
b4ff3a36 6498 u8 reserved_at_88[0x18];
e281682b 6499
b4ff3a36 6500 u8 reserved_at_a0[0x8];
e281682b
SM		 6501 u8 table_id[0x18];
6502
6503 u8 group_id[0x20];
6504
b4ff3a36 6505 u8 reserved_at_e0[0x120];
e281682b
SM		 6506};
6507
6508struct mlx5_ifc_destroy_eq_out_bits {
6509 u8 status[0x8];
b4ff3a36 6510 u8 reserved_at_8[0x18];
e281682b
SM		 6511
6512 u8 syndrome[0x20];
6513
b4ff3a36 6514 u8 reserved_at_40[0x40];
e281682b
SM		 6515};
6516
6517struct mlx5_ifc_destroy_eq_in_bits {
6518 u8 opcode[0x10];
b4ff3a36 6519 u8 reserved_at_10[0x10];
e281682b 6520
b4ff3a36 6521 u8 reserved_at_20[0x10];
e281682b
SM		 6522 u8 op_mod[0x10];
6523
b4ff3a36 6524 u8 reserved_at_40[0x18];
e281682b
SM		 6525 u8 eq_number[0x8];
6526
b4ff3a36 6527 u8 reserved_at_60[0x20];
e281682b
SM		 6528};
6529
6530struct mlx5_ifc_destroy_dct_out_bits {
6531 u8 status[0x8];
b4ff3a36 6532 u8 reserved_at_8[0x18];
e281682b
SM		 6533
6534 u8 syndrome[0x20];
6535
b4ff3a36 6536 u8 reserved_at_40[0x40];
e281682b
SM		 6537};
6538
6539struct mlx5_ifc_destroy_dct_in_bits {
6540 u8 opcode[0x10];
774ea6ee 6541 u8 uid[0x10];
e281682b 6542
b4ff3a36 6543 u8 reserved_at_20[0x10];
e281682b
SM		 6544 u8 op_mod[0x10];
6545
b4ff3a36 6546 u8 reserved_at_40[0x8];
e281682b
SM		 6547 u8 dctn[0x18];
6548
b4ff3a36 6549 u8 reserved_at_60[0x20];
e281682b
SM		 6550};
6551
6552struct mlx5_ifc_destroy_cq_out_bits {
6553 u8 status[0x8];
b4ff3a36 6554 u8 reserved_at_8[0x18];
e281682b
SM		 6555
6556 u8 syndrome[0x20];
6557
b4ff3a36 6558 u8 reserved_at_40[0x40];
e281682b
SM		 6559};
6560
6561struct mlx5_ifc_destroy_cq_in_bits {
6562 u8 opcode[0x10];
9ba481e2 6563 u8 uid[0x10];
e281682b 6564
b4ff3a36 6565 u8 reserved_at_20[0x10];
e281682b
SM		 6566 u8 op_mod[0x10];
6567
b4ff3a36 6568 u8 reserved_at_40[0x8];
e281682b
SM		 6569 u8 cqn[0x18];
6570
b4ff3a36 6571 u8 reserved_at_60[0x20];
e281682b
SM		 6572};
6573
6574struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6575 u8 status[0x8];
b4ff3a36 6576 u8 reserved_at_8[0x18];
e281682b
SM		 6577
6578 u8 syndrome[0x20];
6579
b4ff3a36 6580 u8 reserved_at_40[0x40];
e281682b
SM		 6581};
6582
6583struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6584 u8 opcode[0x10];
b4ff3a36 6585 u8 reserved_at_10[0x10];
e281682b 6586
b4ff3a36 6587 u8 reserved_at_20[0x10];
e281682b
SM		 6588 u8 op_mod[0x10];
6589
b4ff3a36 6590 u8 reserved_at_40[0x20];
e281682b 6591
b4ff3a36 6592 u8 reserved_at_60[0x10];
e281682b
SM		 6593 u8 vxlan_udp_port[0x10];
6594};
6595
6596struct mlx5_ifc_delete_l2_table_entry_out_bits {
6597 u8 status[0x8];
b4ff3a36 6598 u8 reserved_at_8[0x18];
e281682b
SM		 6599
6600 u8 syndrome[0x20];
6601
b4ff3a36 6602 u8 reserved_at_40[0x40];
e281682b
SM		 6603};
6604
6605struct mlx5_ifc_delete_l2_table_entry_in_bits {
6606 u8 opcode[0x10];
b4ff3a36 6607 u8 reserved_at_10[0x10];
e281682b 6608
b4ff3a36 6609 u8 reserved_at_20[0x10];
e281682b
SM		 6610 u8 op_mod[0x10];
6611
b4ff3a36 6612 u8 reserved_at_40[0x60];
e281682b 6613
b4ff3a36 6614 u8 reserved_at_a0[0x8];
e281682b
SM		 6615 u8 table_index[0x18];
6616
b4ff3a36 6617 u8 reserved_at_c0[0x140];
e281682b
SM		 6618};
6619
6620struct mlx5_ifc_delete_fte_out_bits {
6621 u8 status[0x8];
b4ff3a36 6622 u8 reserved_at_8[0x18];
e281682b
SM		 6623
6624 u8 syndrome[0x20];
6625
b4ff3a36 6626 u8 reserved_at_40[0x40];
e281682b
SM		 6627};
6628
6629struct mlx5_ifc_delete_fte_in_bits {
6630 u8 opcode[0x10];
b4ff3a36 6631 u8 reserved_at_10[0x10];
e281682b 6632
b4ff3a36 6633 u8 reserved_at_20[0x10];
e281682b
SM		 6634 u8 op_mod[0x10];
6635
7d5e1423
SM		 6636 u8 other_vport[0x1];
6637 u8 reserved_at_41[0xf];
6638 u8 vport_number[0x10];
6639
6640 u8 reserved_at_60[0x20];
e281682b
SM		 6641
6642 u8 table_type[0x8];
b4ff3a36 6643 u8 reserved_at_88[0x18];
e281682b 6644
b4ff3a36 6645 u8 reserved_at_a0[0x8];
e281682b
SM		 6646 u8 table_id[0x18];
6647
b4ff3a36 6648 u8 reserved_at_c0[0x40];
e281682b
SM		 6649
6650 u8 flow_index[0x20];
6651
b4ff3a36 6652 u8 reserved_at_120[0xe0];
e281682b
SM		 6653};
6654
6655struct mlx5_ifc_dealloc_xrcd_out_bits {
6656 u8 status[0x8];
b4ff3a36 6657 u8 reserved_at_8[0x18];
e281682b
SM		 6658
6659 u8 syndrome[0x20];
6660
b4ff3a36 6661 u8 reserved_at_40[0x40];
e281682b
SM		 6662};
6663
6664struct mlx5_ifc_dealloc_xrcd_in_bits {
6665 u8 opcode[0x10];
bd371975 6666 u8 uid[0x10];
e281682b 6667
b4ff3a36 6668 u8 reserved_at_20[0x10];
e281682b
SM		 6669 u8 op_mod[0x10];
6670
b4ff3a36 6671 u8 reserved_at_40[0x8];
e281682b
SM		 6672 u8 xrcd[0x18];
6673
b4ff3a36 6674 u8 reserved_at_60[0x20];
e281682b
SM		 6675};
6676
6677struct mlx5_ifc_dealloc_uar_out_bits {
6678 u8 status[0x8];
b4ff3a36 6679 u8 reserved_at_8[0x18];
e281682b
SM		 6680
6681 u8 syndrome[0x20];
6682
b4ff3a36 6683 u8 reserved_at_40[0x40];
e281682b
SM		 6684};
6685
6686struct mlx5_ifc_dealloc_uar_in_bits {
6687 u8 opcode[0x10];
b4ff3a36 6688 u8 reserved_at_10[0x10];
e281682b 6689
b4ff3a36 6690 u8 reserved_at_20[0x10];
e281682b
SM		 6691 u8 op_mod[0x10];
6692
b4ff3a36 6693 u8 reserved_at_40[0x8];
e281682b
SM		 6694 u8 uar[0x18];
6695
b4ff3a36 6696 u8 reserved_at_60[0x20];
e281682b
SM		 6697};
6698
6699struct mlx5_ifc_dealloc_transport_domain_out_bits {
6700 u8 status[0x8];
b4ff3a36 6701 u8 reserved_at_8[0x18];
e281682b
SM		 6702
6703 u8 syndrome[0x20];
6704
b4ff3a36 6705 u8 reserved_at_40[0x40];
e281682b
SM		 6706};
6707
6708struct mlx5_ifc_dealloc_transport_domain_in_bits {
6709 u8 opcode[0x10];
71bef2fd 6710 u8 uid[0x10];
e281682b 6711
b4ff3a36 6712 u8 reserved_at_20[0x10];
e281682b
SM		 6713 u8 op_mod[0x10];
6714
b4ff3a36 6715 u8 reserved_at_40[0x8];
e281682b
SM		 6716 u8 transport_domain[0x18];
6717
b4ff3a36 6718 u8 reserved_at_60[0x20];
e281682b
SM		 6719};
6720
6721struct mlx5_ifc_dealloc_q_counter_out_bits {
6722 u8 status[0x8];
b4ff3a36 6723 u8 reserved_at_8[0x18];
e281682b
SM		 6724
6725 u8 syndrome[0x20];
6726
b4ff3a36 6727 u8 reserved_at_40[0x40];
e281682b
SM		 6728};
6729
6730struct mlx5_ifc_dealloc_q_counter_in_bits {
6731 u8 opcode[0x10];
b4ff3a36 6732 u8 reserved_at_10[0x10];
e281682b 6733
b4ff3a36 6734 u8 reserved_at_20[0x10];
e281682b
SM		 6735 u8 op_mod[0x10];
6736
b4ff3a36 6737 u8 reserved_at_40[0x18];
e281682b
SM		 6738 u8 counter_set_id[0x8];
6739
b4ff3a36 6740 u8 reserved_at_60[0x20];
e281682b
SM		 6741};
6742
6743struct mlx5_ifc_dealloc_pd_out_bits {
6744 u8 status[0x8];
b4ff3a36 6745 u8 reserved_at_8[0x18];
e281682b
SM		 6746
6747 u8 syndrome[0x20];
6748
b4ff3a36 6749 u8 reserved_at_40[0x40];
e281682b
SM		 6750};
6751
6752struct mlx5_ifc_dealloc_pd_in_bits {
6753 u8 opcode[0x10];
bd371975 6754 u8 uid[0x10];
e281682b 6755
b4ff3a36 6756 u8 reserved_at_20[0x10];
e281682b
SM		 6757 u8 op_mod[0x10];
6758
b4ff3a36 6759 u8 reserved_at_40[0x8];
e281682b
SM		 6760 u8 pd[0x18];
6761
b4ff3a36 6762 u8 reserved_at_60[0x20];
e281682b
SM		 6763};
6764
9dc0b289
AV		 6765struct mlx5_ifc_dealloc_flow_counter_out_bits {
6766 u8 status[0x8];
6767 u8 reserved_at_8[0x18];
6768
6769 u8 syndrome[0x20];
6770
6771 u8 reserved_at_40[0x40];
6772};
6773
6774struct mlx5_ifc_dealloc_flow_counter_in_bits {
6775 u8 opcode[0x10];
6776 u8 reserved_at_10[0x10];
6777
6778 u8 reserved_at_20[0x10];
6779 u8 op_mod[0x10];
6780
a8ffcc74 6781 u8 flow_counter_id[0x20];
9dc0b289
AV		 6782
6783 u8 reserved_at_60[0x20];
6784};
6785
7486216b
SM		 6786struct mlx5_ifc_create_xrq_out_bits {
6787 u8 status[0x8];
6788 u8 reserved_at_8[0x18];
6789
6790 u8 syndrome[0x20];
6791
6792 u8 reserved_at_40[0x8];
6793 u8 xrqn[0x18];
6794
6795 u8 reserved_at_60[0x20];
6796};
6797
6798struct mlx5_ifc_create_xrq_in_bits {
6799 u8 opcode[0x10];
a0d8c054 6800 u8 uid[0x10];
7486216b
SM		 6801
6802 u8 reserved_at_20[0x10];
6803 u8 op_mod[0x10];
6804
6805 u8 reserved_at_40[0x40];
6806
6807 struct mlx5_ifc_xrqc_bits xrq_context;
6808};
6809
e281682b
SM		 6810struct mlx5_ifc_create_xrc_srq_out_bits {
6811 u8 status[0x8];
b4ff3a36 6812 u8 reserved_at_8[0x18];
e281682b
SM		 6813
6814 u8 syndrome[0x20];
6815
b4ff3a36 6816 u8 reserved_at_40[0x8];
e281682b
SM		 6817 u8 xrc_srqn[0x18];
6818
b4ff3a36 6819 u8 reserved_at_60[0x20];
e281682b
SM		 6820};
6821
6822struct mlx5_ifc_create_xrc_srq_in_bits {
6823 u8 opcode[0x10];
a0d8c054 6824 u8 uid[0x10];
e281682b 6825
b4ff3a36 6826 u8 reserved_at_20[0x10];
e281682b
SM		 6827 u8 op_mod[0x10];
6828
b4ff3a36 6829 u8 reserved_at_40[0x40];
e281682b
SM		 6830
6831 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6832
99b77fef
YH		 6833 u8 reserved_at_280[0x60];
6834
bd371975 6835 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 6836 u8 reserved_at_2e1[0x1f];
6837
6838 u8 reserved_at_300[0x580];
e281682b
SM		 6839
6840 u8 pas[0][0x40];
6841};
6842
6843struct mlx5_ifc_create_tis_out_bits {
6844 u8 status[0x8];
b4ff3a36 6845 u8 reserved_at_8[0x18];
e281682b
SM		 6846
6847 u8 syndrome[0x20];
6848
b4ff3a36 6849 u8 reserved_at_40[0x8];
e281682b
SM		 6850 u8 tisn[0x18];
6851
b4ff3a36 6852 u8 reserved_at_60[0x20];
e281682b
SM		 6853};
6854
6855struct mlx5_ifc_create_tis_in_bits {
6856 u8 opcode[0x10];
bd371975 6857 u8 uid[0x10];
e281682b 6858
b4ff3a36 6859 u8 reserved_at_20[0x10];
e281682b
SM		 6860 u8 op_mod[0x10];
6861
b4ff3a36 6862 u8 reserved_at_40[0xc0];
e281682b
SM		 6863
6864 struct mlx5_ifc_tisc_bits ctx;
6865};
6866
6867struct mlx5_ifc_create_tir_out_bits {
6868 u8 status[0x8];
b4ff3a36 6869 u8 reserved_at_8[0x18];
e281682b
SM		 6870
6871 u8 syndrome[0x20];
6872
b4ff3a36 6873 u8 reserved_at_40[0x8];
e281682b
SM		 6874 u8 tirn[0x18];
6875
b4ff3a36 6876 u8 reserved_at_60[0x20];
e281682b
SM		 6877};
6878
6879struct mlx5_ifc_create_tir_in_bits {
6880 u8 opcode[0x10];
bd371975 6881 u8 uid[0x10];
e281682b 6882
b4ff3a36 6883 u8 reserved_at_20[0x10];
e281682b
SM		 6884 u8 op_mod[0x10];
6885
b4ff3a36 6886 u8 reserved_at_40[0xc0];
e281682b
SM		 6887
6888 struct mlx5_ifc_tirc_bits ctx;
6889};
6890
6891struct mlx5_ifc_create_srq_out_bits {
6892 u8 status[0x8];
b4ff3a36 6893 u8 reserved_at_8[0x18];
e281682b
SM		 6894
6895 u8 syndrome[0x20];
6896
b4ff3a36 6897 u8 reserved_at_40[0x8];
e281682b
SM		 6898 u8 srqn[0x18];
6899
b4ff3a36 6900 u8 reserved_at_60[0x20];
e281682b
SM		 6901};
6902
6903struct mlx5_ifc_create_srq_in_bits {
6904 u8 opcode[0x10];
a0d8c054 6905 u8 uid[0x10];
e281682b 6906
b4ff3a36 6907 u8 reserved_at_20[0x10];
e281682b
SM		 6908 u8 op_mod[0x10];
6909
b4ff3a36 6910 u8 reserved_at_40[0x40];
e281682b
SM		 6911
6912 struct mlx5_ifc_srqc_bits srq_context_entry;
6913
b4ff3a36 6914 u8 reserved_at_280[0x600];
e281682b
SM		 6915
6916 u8 pas[0][0x40];
6917};
6918
6919struct mlx5_ifc_create_sq_out_bits {
6920 u8 status[0x8];
b4ff3a36 6921 u8 reserved_at_8[0x18];
e281682b
SM		 6922
6923 u8 syndrome[0x20];
6924
b4ff3a36 6925 u8 reserved_at_40[0x8];
e281682b
SM		 6926 u8 sqn[0x18];
6927
b4ff3a36 6928 u8 reserved_at_60[0x20];
e281682b
SM		 6929};
6930
6931struct mlx5_ifc_create_sq_in_bits {
6932 u8 opcode[0x10];
430ae0d5 6933 u8 uid[0x10];
e281682b 6934
b4ff3a36 6935 u8 reserved_at_20[0x10];
e281682b
SM		 6936 u8 op_mod[0x10];
6937
b4ff3a36 6938 u8 reserved_at_40[0xc0];
e281682b
SM		 6939
6940 struct mlx5_ifc_sqc_bits ctx;
6941};
6942
813f8540
MHY		 6943struct mlx5_ifc_create_scheduling_element_out_bits {
6944 u8 status[0x8];
6945 u8 reserved_at_8[0x18];
6946
6947 u8 syndrome[0x20];
6948
6949 u8 reserved_at_40[0x40];
6950
6951 u8 scheduling_element_id[0x20];
6952
6953 u8 reserved_at_a0[0x160];
6954};
6955
6956struct mlx5_ifc_create_scheduling_element_in_bits {
6957 u8 opcode[0x10];
6958 u8 reserved_at_10[0x10];
6959
6960 u8 reserved_at_20[0x10];
6961 u8 op_mod[0x10];
6962
6963 u8 scheduling_hierarchy[0x8];
6964 u8 reserved_at_48[0x18];
6965
6966 u8 reserved_at_60[0xa0];
6967
6968 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6969
6970 u8 reserved_at_300[0x100];
6971};
6972
e281682b
SM		 6973struct mlx5_ifc_create_rqt_out_bits {
6974 u8 status[0x8];
b4ff3a36 6975 u8 reserved_at_8[0x18];
e281682b
SM		 6976
6977 u8 syndrome[0x20];
6978
b4ff3a36 6979 u8 reserved_at_40[0x8];
e281682b
SM		 6980 u8 rqtn[0x18];
6981
b4ff3a36 6982 u8 reserved_at_60[0x20];
e281682b
SM		 6983};
6984
6985struct mlx5_ifc_create_rqt_in_bits {
6986 u8 opcode[0x10];
bd371975 6987 u8 uid[0x10];
e281682b 6988
b4ff3a36 6989 u8 reserved_at_20[0x10];
e281682b
SM		 6990 u8 op_mod[0x10];
6991
b4ff3a36 6992 u8 reserved_at_40[0xc0];
e281682b
SM		 6993
6994 struct mlx5_ifc_rqtc_bits rqt_context;
6995};
6996
6997struct mlx5_ifc_create_rq_out_bits {
6998 u8 status[0x8];
b4ff3a36 6999 u8 reserved_at_8[0x18];
e281682b
SM		 7000
7001 u8 syndrome[0x20];
7002
b4ff3a36 7003 u8 reserved_at_40[0x8];
e281682b
SM		 7004 u8 rqn[0x18];
7005
b4ff3a36 7006 u8 reserved_at_60[0x20];
e281682b
SM		 7007};
7008
7009struct mlx5_ifc_create_rq_in_bits {
7010 u8 opcode[0x10];
d269b3af 7011 u8 uid[0x10];
e281682b 7012
b4ff3a36 7013 u8 reserved_at_20[0x10];
e281682b
SM		 7014 u8 op_mod[0x10];
7015
b4ff3a36 7016 u8 reserved_at_40[0xc0];
e281682b
SM		 7017
7018 struct mlx5_ifc_rqc_bits ctx;
7019};
7020
7021struct mlx5_ifc_create_rmp_out_bits {
7022 u8 status[0x8];
b4ff3a36 7023 u8 reserved_at_8[0x18];
e281682b
SM		 7024
7025 u8 syndrome[0x20];
7026
b4ff3a36 7027 u8 reserved_at_40[0x8];
e281682b
SM		 7028 u8 rmpn[0x18];
7029
b4ff3a36 7030 u8 reserved_at_60[0x20];
e281682b
SM		 7031};
7032
7033struct mlx5_ifc_create_rmp_in_bits {
7034 u8 opcode[0x10];
a0d8c054 7035 u8 uid[0x10];
e281682b 7036
b4ff3a36 7037 u8 reserved_at_20[0x10];
e281682b
SM		 7038 u8 op_mod[0x10];
7039
b4ff3a36 7040 u8 reserved_at_40[0xc0];
e281682b
SM		 7041
7042 struct mlx5_ifc_rmpc_bits ctx;
7043};
7044
7045struct mlx5_ifc_create_qp_out_bits {
7046 u8 status[0x8];
b4ff3a36 7047 u8 reserved_at_8[0x18];
e281682b
SM		 7048
7049 u8 syndrome[0x20];
7050
b4ff3a36 7051 u8 reserved_at_40[0x8];
e281682b
SM		 7052 u8 qpn[0x18];
7053
b4ff3a36 7054 u8 reserved_at_60[0x20];
e281682b
SM		 7055};
7056
7057struct mlx5_ifc_create_qp_in_bits {
7058 u8 opcode[0x10];
4ac63ec7 7059 u8 uid[0x10];
e281682b 7060
b4ff3a36 7061 u8 reserved_at_20[0x10];
e281682b
SM		 7062 u8 op_mod[0x10];
7063
b4ff3a36 7064 u8 reserved_at_40[0x40];
e281682b
SM		 7065
7066 u8 opt_param_mask[0x20];
7067
b4ff3a36 7068 u8 reserved_at_a0[0x20];
e281682b
SM		 7069
7070 struct mlx5_ifc_qpc_bits qpc;
7071
bd371975
LR		 7072 u8 reserved_at_800[0x60];
7073
7074 u8 wq_umem_valid[0x1];
7075 u8 reserved_at_861[0x1f];
e281682b
SM		 7076
7077 u8 pas[0][0x40];
7078};
7079
7080struct mlx5_ifc_create_psv_out_bits {
7081 u8 status[0x8];
b4ff3a36 7082 u8 reserved_at_8[0x18];
e281682b
SM		 7083
7084 u8 syndrome[0x20];
7085
b4ff3a36 7086 u8 reserved_at_40[0x40];
e281682b 7087
b4ff3a36 7088 u8 reserved_at_80[0x8];
e281682b
SM		 7089 u8 psv0_index[0x18];
7090
b4ff3a36 7091 u8 reserved_at_a0[0x8];
e281682b
SM		 7092 u8 psv1_index[0x18];
7093
b4ff3a36 7094 u8 reserved_at_c0[0x8];
e281682b
SM		 7095 u8 psv2_index[0x18];
7096
b4ff3a36 7097 u8 reserved_at_e0[0x8];
e281682b
SM		 7098 u8 psv3_index[0x18];
7099};
7100
7101struct mlx5_ifc_create_psv_in_bits {
7102 u8 opcode[0x10];
b4ff3a36 7103 u8 reserved_at_10[0x10];
e281682b 7104
b4ff3a36 7105 u8 reserved_at_20[0x10];
e281682b
SM		 7106 u8 op_mod[0x10];
7107
7108 u8 num_psv[0x4];
b4ff3a36 7109 u8 reserved_at_44[0x4];
e281682b
SM		 7110 u8 pd[0x18];
7111
b4ff3a36 7112 u8 reserved_at_60[0x20];
e281682b
SM		 7113};
7114
7115struct mlx5_ifc_create_mkey_out_bits {
7116 u8 status[0x8];
b4ff3a36 7117 u8 reserved_at_8[0x18];
e281682b
SM		 7118
7119 u8 syndrome[0x20];
7120
b4ff3a36 7121 u8 reserved_at_40[0x8];
e281682b
SM		 7122 u8 mkey_index[0x18];
7123
b4ff3a36 7124 u8 reserved_at_60[0x20];
e281682b
SM		 7125};
7126
7127struct mlx5_ifc_create_mkey_in_bits {
7128 u8 opcode[0x10];
b4ff3a36 7129 u8 reserved_at_10[0x10];
e281682b 7130
b4ff3a36 7131 u8 reserved_at_20[0x10];
e281682b
SM		 7132 u8 op_mod[0x10];
7133
b4ff3a36 7134 u8 reserved_at_40[0x20];
e281682b
SM		 7135
7136 u8 pg_access[0x1];
bd371975
LR		 7137 u8 mkey_umem_valid[0x1];
7138 u8 reserved_at_62[0x1e];
e281682b
SM		 7139
7140 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7141
b4ff3a36 7142 u8 reserved_at_280[0x80];
e281682b
SM		 7143
7144 u8 translations_octword_actual_size[0x20];
7145
b4ff3a36 7146 u8 reserved_at_320[0x560];
e281682b
SM		 7147
7148 u8 klm_pas_mtt[0][0x20];
7149};
7150
7151struct mlx5_ifc_create_flow_table_out_bits {
7152 u8 status[0x8];
b4ff3a36 7153 u8 reserved_at_8[0x18];
e281682b
SM		 7154
7155 u8 syndrome[0x20];
7156
b4ff3a36 7157 u8 reserved_at_40[0x8];
e281682b
SM		 7158 u8 table_id[0x18];
7159
b4ff3a36 7160 u8 reserved_at_60[0x20];
e281682b
SM		 7161};
7162
0c90e9c6 7163struct mlx5_ifc_flow_table_context_bits {
60786f09 7164 u8 reformat_en[0x1];
0c90e9c6
MG		 7165 u8 decap_en[0x1];
7166 u8 reserved_at_2[0x2];
7167 u8 table_miss_action[0x4];
7168 u8 level[0x8];
7169 u8 reserved_at_10[0x8];
7170 u8 log_size[0x8];
7171
7172 u8 reserved_at_20[0x8];
7173 u8 table_miss_id[0x18];
7174
7175 u8 reserved_at_40[0x8];
7176 u8 lag_master_next_table_id[0x18];
7177
7178 u8 reserved_at_60[0xe0];
7179};
7180
e281682b
SM		 7181struct mlx5_ifc_create_flow_table_in_bits {
7182 u8 opcode[0x10];
b4ff3a36 7183 u8 reserved_at_10[0x10];
e281682b 7184
b4ff3a36 7185 u8 reserved_at_20[0x10];
e281682b
SM		 7186 u8 op_mod[0x10];
7187
7d5e1423
SM		 7188 u8 other_vport[0x1];
7189 u8 reserved_at_41[0xf];
7190 u8 vport_number[0x10];
7191
7192 u8 reserved_at_60[0x20];
e281682b
SM		 7193
7194 u8 table_type[0x8];
b4ff3a36 7195 u8 reserved_at_88[0x18];
e281682b 7196
b4ff3a36 7197 u8 reserved_at_a0[0x20];
e281682b 7198
0c90e9c6 7199 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 7200};
7201
7202struct mlx5_ifc_create_flow_group_out_bits {
7203 u8 status[0x8];
b4ff3a36 7204 u8 reserved_at_8[0x18];
e281682b
SM		 7205
7206 u8 syndrome[0x20];
7207
b4ff3a36 7208 u8 reserved_at_40[0x8];
e281682b
SM		 7209 u8 group_id[0x18];
7210
b4ff3a36 7211 u8 reserved_at_60[0x20];
e281682b
SM		 7212};
7213
7214enum {
71c6e863
AL		 7215 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7216 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7217 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7218 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 7219};
7220
7221struct mlx5_ifc_create_flow_group_in_bits {
7222 u8 opcode[0x10];
b4ff3a36 7223 u8 reserved_at_10[0x10];
e281682b 7224
b4ff3a36 7225 u8 reserved_at_20[0x10];
e281682b
SM		 7226 u8 op_mod[0x10];
7227
7d5e1423
SM		 7228 u8 other_vport[0x1];
7229 u8 reserved_at_41[0xf];
7230 u8 vport_number[0x10];
7231
7232 u8 reserved_at_60[0x20];
e281682b
SM		 7233
7234 u8 table_type[0x8];
b4ff3a36 7235 u8 reserved_at_88[0x18];
e281682b 7236
b4ff3a36 7237 u8 reserved_at_a0[0x8];
e281682b
SM		 7238 u8 table_id[0x18];
7239
3e99df87
SK		 7240 u8 source_eswitch_owner_vhca_id_valid[0x1];
7241
7242 u8 reserved_at_c1[0x1f];
e281682b
SM		 7243
7244 u8 start_flow_index[0x20];
7245
b4ff3a36 7246 u8 reserved_at_100[0x20];
e281682b
SM		 7247
7248 u8 end_flow_index[0x20];
7249
b4ff3a36 7250 u8 reserved_at_140[0xa0];
e281682b 7251
b4ff3a36 7252 u8 reserved_at_1e0[0x18];
e281682b
SM		 7253 u8 match_criteria_enable[0x8];
7254
7255 struct mlx5_ifc_fte_match_param_bits match_criteria;
7256
b4ff3a36 7257 u8 reserved_at_1200[0xe00];
e281682b
SM		 7258};
7259
7260struct mlx5_ifc_create_eq_out_bits {
7261 u8 status[0x8];
b4ff3a36 7262 u8 reserved_at_8[0x18];
e281682b
SM		 7263
7264 u8 syndrome[0x20];
7265
b4ff3a36 7266 u8 reserved_at_40[0x18];
e281682b
SM		 7267 u8 eq_number[0x8];
7268
b4ff3a36 7269 u8 reserved_at_60[0x20];
e281682b
SM		 7270};
7271
7272struct mlx5_ifc_create_eq_in_bits {
7273 u8 opcode[0x10];
b4ff3a36 7274 u8 reserved_at_10[0x10];
e281682b 7275
b4ff3a36 7276 u8 reserved_at_20[0x10];
e281682b
SM		 7277 u8 op_mod[0x10];
7278
b4ff3a36 7279 u8 reserved_at_40[0x40];
e281682b
SM		 7280
7281 struct mlx5_ifc_eqc_bits eq_context_entry;
7282
b4ff3a36 7283 u8 reserved_at_280[0x40];
e281682b
SM		 7284
7285 u8 event_bitmask[0x40];
7286
b4ff3a36 7287 u8 reserved_at_300[0x580];
e281682b
SM		 7288
7289 u8 pas[0][0x40];
7290};
7291
7292struct mlx5_ifc_create_dct_out_bits {
7293 u8 status[0x8];
b4ff3a36 7294 u8 reserved_at_8[0x18];
e281682b
SM		 7295
7296 u8 syndrome[0x20];
7297
b4ff3a36 7298 u8 reserved_at_40[0x8];
e281682b
SM		 7299 u8 dctn[0x18];
7300
b4ff3a36 7301 u8 reserved_at_60[0x20];
e281682b
SM		 7302};
7303
7304struct mlx5_ifc_create_dct_in_bits {
7305 u8 opcode[0x10];
774ea6ee 7306 u8 uid[0x10];
e281682b 7307
b4ff3a36 7308 u8 reserved_at_20[0x10];
e281682b
SM		 7309 u8 op_mod[0x10];
7310
b4ff3a36 7311 u8 reserved_at_40[0x40];
e281682b
SM		 7312
7313 struct mlx5_ifc_dctc_bits dct_context_entry;
7314
b4ff3a36 7315 u8 reserved_at_280[0x180];
e281682b
SM		 7316};
7317
7318struct mlx5_ifc_create_cq_out_bits {
7319 u8 status[0x8];
b4ff3a36 7320 u8 reserved_at_8[0x18];
e281682b
SM		 7321
7322 u8 syndrome[0x20];
7323
b4ff3a36 7324 u8 reserved_at_40[0x8];
e281682b
SM		 7325 u8 cqn[0x18];
7326
b4ff3a36 7327 u8 reserved_at_60[0x20];
e281682b
SM		 7328};
7329
7330struct mlx5_ifc_create_cq_in_bits {
7331 u8 opcode[0x10];
9ba481e2 7332 u8 uid[0x10];
e281682b 7333
b4ff3a36 7334 u8 reserved_at_20[0x10];
e281682b
SM		 7335 u8 op_mod[0x10];
7336
b4ff3a36 7337 u8 reserved_at_40[0x40];
e281682b
SM		 7338
7339 struct mlx5_ifc_cqc_bits cq_context;
7340
bd371975
LR		 7341 u8 reserved_at_280[0x60];
7342
7343 u8 cq_umem_valid[0x1];
7344 u8 reserved_at_2e1[0x59f];
e281682b
SM		 7345
7346 u8 pas[0][0x40];
7347};
7348
7349struct mlx5_ifc_config_int_moderation_out_bits {
7350 u8 status[0x8];
b4ff3a36 7351 u8 reserved_at_8[0x18];
e281682b
SM		 7352
7353 u8 syndrome[0x20];
7354
b4ff3a36 7355 u8 reserved_at_40[0x4];
e281682b
SM		 7356 u8 min_delay[0xc];
7357 u8 int_vector[0x10];
7358
b4ff3a36 7359 u8 reserved_at_60[0x20];
e281682b
SM		 7360};
7361
7362enum {
7363 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7364 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7365};
7366
7367struct mlx5_ifc_config_int_moderation_in_bits {
7368 u8 opcode[0x10];
b4ff3a36 7369 u8 reserved_at_10[0x10];
e281682b 7370
b4ff3a36 7371 u8 reserved_at_20[0x10];
e281682b
SM		 7372 u8 op_mod[0x10];
7373
b4ff3a36 7374 u8 reserved_at_40[0x4];
e281682b
SM		 7375 u8 min_delay[0xc];
7376 u8 int_vector[0x10];
7377
b4ff3a36 7378 u8 reserved_at_60[0x20];
e281682b
SM		 7379};
7380
7381struct mlx5_ifc_attach_to_mcg_out_bits {
7382 u8 status[0x8];
b4ff3a36 7383 u8 reserved_at_8[0x18];
e281682b
SM		 7384
7385 u8 syndrome[0x20];
7386
b4ff3a36 7387 u8 reserved_at_40[0x40];
e281682b
SM		 7388};
7389
7390struct mlx5_ifc_attach_to_mcg_in_bits {
7391 u8 opcode[0x10];
bd371975 7392 u8 uid[0x10];
e281682b 7393
b4ff3a36 7394 u8 reserved_at_20[0x10];
e281682b
SM		 7395 u8 op_mod[0x10];
7396
b4ff3a36 7397 u8 reserved_at_40[0x8];
e281682b
SM		 7398 u8 qpn[0x18];
7399
b4ff3a36 7400 u8 reserved_at_60[0x20];
e281682b
SM		 7401
7402 u8 multicast_gid[16][0x8];
7403};
7404
7486216b
SM		 7405struct mlx5_ifc_arm_xrq_out_bits {
7406 u8 status[0x8];
7407 u8 reserved_at_8[0x18];
7408
7409 u8 syndrome[0x20];
7410
7411 u8 reserved_at_40[0x40];
7412};
7413
7414struct mlx5_ifc_arm_xrq_in_bits {
7415 u8 opcode[0x10];
7416 u8 reserved_at_10[0x10];
7417
7418 u8 reserved_at_20[0x10];
7419 u8 op_mod[0x10];
7420
7421 u8 reserved_at_40[0x8];
7422 u8 xrqn[0x18];
7423
7424 u8 reserved_at_60[0x10];
7425 u8 lwm[0x10];
7426};
7427
e281682b
SM		 7428struct mlx5_ifc_arm_xrc_srq_out_bits {
7429 u8 status[0x8];
b4ff3a36 7430 u8 reserved_at_8[0x18];
e281682b
SM		 7431
7432 u8 syndrome[0x20];
7433
b4ff3a36 7434 u8 reserved_at_40[0x40];
e281682b
SM		 7435};
7436
7437enum {
7438 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7439};
7440
7441struct mlx5_ifc_arm_xrc_srq_in_bits {
7442 u8 opcode[0x10];
a0d8c054 7443 u8 uid[0x10];
e281682b 7444
b4ff3a36 7445 u8 reserved_at_20[0x10];
e281682b
SM		 7446 u8 op_mod[0x10];
7447
b4ff3a36 7448 u8 reserved_at_40[0x8];
e281682b
SM		 7449 u8 xrc_srqn[0x18];
7450
b4ff3a36 7451 u8 reserved_at_60[0x10];
e281682b
SM		 7452 u8 lwm[0x10];
7453};
7454
7455struct mlx5_ifc_arm_rq_out_bits {
7456 u8 status[0x8];
b4ff3a36 7457 u8 reserved_at_8[0x18];
e281682b
SM		 7458
7459 u8 syndrome[0x20];
7460
b4ff3a36 7461 u8 reserved_at_40[0x40];
e281682b
SM		 7462};
7463
7464enum {
7486216b
SM		 7465 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7466 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7467};
7468
7469struct mlx5_ifc_arm_rq_in_bits {
7470 u8 opcode[0x10];
a0d8c054 7471 u8 uid[0x10];
e281682b 7472
b4ff3a36 7473 u8 reserved_at_20[0x10];
e281682b
SM		 7474 u8 op_mod[0x10];
7475
b4ff3a36 7476 u8 reserved_at_40[0x8];
e281682b
SM		 7477 u8 srq_number[0x18];
7478
b4ff3a36 7479 u8 reserved_at_60[0x10];
e281682b
SM		 7480 u8 lwm[0x10];
7481};
7482
7483struct mlx5_ifc_arm_dct_out_bits {
7484 u8 status[0x8];
b4ff3a36 7485 u8 reserved_at_8[0x18];
e281682b
SM		 7486
7487 u8 syndrome[0x20];
7488
b4ff3a36 7489 u8 reserved_at_40[0x40];
e281682b
SM		 7490};
7491
7492struct mlx5_ifc_arm_dct_in_bits {
7493 u8 opcode[0x10];
b4ff3a36 7494 u8 reserved_at_10[0x10];
e281682b 7495
b4ff3a36 7496 u8 reserved_at_20[0x10];
e281682b
SM		 7497 u8 op_mod[0x10];
7498
b4ff3a36 7499 u8 reserved_at_40[0x8];
e281682b
SM		 7500 u8 dct_number[0x18];
7501
b4ff3a36 7502 u8 reserved_at_60[0x20];
e281682b
SM		 7503};
7504
7505struct mlx5_ifc_alloc_xrcd_out_bits {
7506 u8 status[0x8];
b4ff3a36 7507 u8 reserved_at_8[0x18];
e281682b
SM		 7508
7509 u8 syndrome[0x20];
7510
b4ff3a36 7511 u8 reserved_at_40[0x8];
e281682b
SM		 7512 u8 xrcd[0x18];
7513
b4ff3a36 7514 u8 reserved_at_60[0x20];
e281682b
SM		 7515};
7516
7517struct mlx5_ifc_alloc_xrcd_in_bits {
7518 u8 opcode[0x10];
bd371975 7519 u8 uid[0x10];
e281682b 7520
b4ff3a36 7521 u8 reserved_at_20[0x10];
e281682b
SM		 7522 u8 op_mod[0x10];
7523
b4ff3a36 7524 u8 reserved_at_40[0x40];
e281682b
SM		 7525};
7526
7527struct mlx5_ifc_alloc_uar_out_bits {
7528 u8 status[0x8];
b4ff3a36 7529 u8 reserved_at_8[0x18];
e281682b
SM		 7530
7531 u8 syndrome[0x20];
7532
b4ff3a36 7533 u8 reserved_at_40[0x8];
e281682b
SM		 7534 u8 uar[0x18];
7535
b4ff3a36 7536 u8 reserved_at_60[0x20];
e281682b
SM		 7537};
7538
7539struct mlx5_ifc_alloc_uar_in_bits {
7540 u8 opcode[0x10];
b4ff3a36 7541 u8 reserved_at_10[0x10];
e281682b 7542
b4ff3a36 7543 u8 reserved_at_20[0x10];
e281682b
SM		 7544 u8 op_mod[0x10];
7545
b4ff3a36 7546 u8 reserved_at_40[0x40];
e281682b
SM		 7547};
7548
7549struct mlx5_ifc_alloc_transport_domain_out_bits {
7550 u8 status[0x8];
b4ff3a36 7551 u8 reserved_at_8[0x18];
e281682b
SM		 7552
7553 u8 syndrome[0x20];
7554
b4ff3a36 7555 u8 reserved_at_40[0x8];
e281682b
SM		 7556 u8 transport_domain[0x18];
7557
b4ff3a36 7558 u8 reserved_at_60[0x20];
e281682b
SM		 7559};
7560
7561struct mlx5_ifc_alloc_transport_domain_in_bits {
7562 u8 opcode[0x10];
71bef2fd 7563 u8 uid[0x10];
e281682b 7564
b4ff3a36 7565 u8 reserved_at_20[0x10];
e281682b
SM		 7566 u8 op_mod[0x10];
7567
b4ff3a36 7568 u8 reserved_at_40[0x40];
e281682b
SM		 7569};
7570
7571struct mlx5_ifc_alloc_q_counter_out_bits {
7572 u8 status[0x8];
b4ff3a36 7573 u8 reserved_at_8[0x18];
e281682b
SM		 7574
7575 u8 syndrome[0x20];
7576
b4ff3a36 7577 u8 reserved_at_40[0x18];
e281682b
SM		 7578 u8 counter_set_id[0x8];
7579
b4ff3a36 7580 u8 reserved_at_60[0x20];
e281682b
SM		 7581};
7582
7583struct mlx5_ifc_alloc_q_counter_in_bits {
7584 u8 opcode[0x10];
2acc7957 7585 u8 uid[0x10];
e281682b 7586
b4ff3a36 7587 u8 reserved_at_20[0x10];
e281682b
SM		 7588 u8 op_mod[0x10];
7589
b4ff3a36 7590 u8 reserved_at_40[0x40];
e281682b
SM		 7591};
7592
7593struct mlx5_ifc_alloc_pd_out_bits {
7594 u8 status[0x8];
b4ff3a36 7595 u8 reserved_at_8[0x18];
e281682b
SM		 7596
7597 u8 syndrome[0x20];
7598
b4ff3a36 7599 u8 reserved_at_40[0x8];
e281682b
SM		 7600 u8 pd[0x18];
7601
b4ff3a36 7602 u8 reserved_at_60[0x20];
e281682b
SM		 7603};
7604
7605struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 7606 u8 opcode[0x10];
bd371975 7607 u8 uid[0x10];
9dc0b289
AV		 7608
7609 u8 reserved_at_20[0x10];
7610 u8 op_mod[0x10];
7611
7612 u8 reserved_at_40[0x40];
7613};
7614
7615struct mlx5_ifc_alloc_flow_counter_out_bits {
7616 u8 status[0x8];
7617 u8 reserved_at_8[0x18];
7618
7619 u8 syndrome[0x20];
7620
a8ffcc74 7621 u8 flow_counter_id[0x20];
9dc0b289
AV		 7622
7623 u8 reserved_at_60[0x20];
7624};
7625
7626struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7627 u8 opcode[0x10];
b4ff3a36 7628 u8 reserved_at_10[0x10];
e281682b 7629
b4ff3a36 7630 u8 reserved_at_20[0x10];
e281682b
SM		 7631 u8 op_mod[0x10];
7632
b4ff3a36 7633 u8 reserved_at_40[0x40];
e281682b
SM		 7634};
7635
7636struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7637 u8 status[0x8];
b4ff3a36 7638 u8 reserved_at_8[0x18];
e281682b
SM		 7639
7640 u8 syndrome[0x20];
7641
b4ff3a36 7642 u8 reserved_at_40[0x40];
e281682b
SM		 7643};
7644
7645struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7646 u8 opcode[0x10];
b4ff3a36 7647 u8 reserved_at_10[0x10];
e281682b 7648
b4ff3a36 7649 u8 reserved_at_20[0x10];
e281682b
SM		 7650 u8 op_mod[0x10];
7651
b4ff3a36 7652 u8 reserved_at_40[0x20];
e281682b 7653
b4ff3a36 7654 u8 reserved_at_60[0x10];
e281682b
SM		 7655 u8 vxlan_udp_port[0x10];
7656};
7657
37e92a9d 7658struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7659 u8 status[0x8];
7660 u8 reserved_at_8[0x18];
7661
7662 u8 syndrome[0x20];
7663
7664 u8 reserved_at_40[0x40];
7665};
7666
37e92a9d 7667struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7668 u8 opcode[0x10];
7669 u8 reserved_at_10[0x10];
7670
7671 u8 reserved_at_20[0x10];
7672 u8 op_mod[0x10];
7673
7674 u8 reserved_at_40[0x10];
7675 u8 rate_limit_index[0x10];
7676
7677 u8 reserved_at_60[0x20];
7678
7679 u8 rate_limit[0x20];
37e92a9d 7680
05d3ac97
BW		 7681 u8 burst_upper_bound[0x20];
7682
7683 u8 reserved_at_c0[0x10];
7684 u8 typical_packet_size[0x10];
7685
7686 u8 reserved_at_e0[0x120];
7486216b
SM		 7687};
7688
e281682b
SM		 7689struct mlx5_ifc_access_register_out_bits {
7690 u8 status[0x8];
b4ff3a36 7691 u8 reserved_at_8[0x18];
e281682b
SM		 7692
7693 u8 syndrome[0x20];
7694
b4ff3a36 7695 u8 reserved_at_40[0x40];
e281682b
SM		 7696
7697 u8 register_data[0][0x20];
7698};
7699
7700enum {
7701 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7702 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7703};
7704
7705struct mlx5_ifc_access_register_in_bits {
7706 u8 opcode[0x10];
b4ff3a36 7707 u8 reserved_at_10[0x10];
e281682b 7708
b4ff3a36 7709 u8 reserved_at_20[0x10];
e281682b
SM		 7710 u8 op_mod[0x10];
7711
b4ff3a36 7712 u8 reserved_at_40[0x10];
e281682b
SM		 7713 u8 register_id[0x10];
7714
7715 u8 argument[0x20];
7716
7717 u8 register_data[0][0x20];
7718};
7719
7720struct mlx5_ifc_sltp_reg_bits {
7721 u8 status[0x4];
7722 u8 version[0x4];
7723 u8 local_port[0x8];
7724 u8 pnat[0x2];
b4ff3a36 7725 u8 reserved_at_12[0x2];
e281682b 7726 u8 lane[0x4];
b4ff3a36 7727 u8 reserved_at_18[0x8];
e281682b 7728
b4ff3a36 7729 u8 reserved_at_20[0x20];
e281682b 7730
b4ff3a36 7731 u8 reserved_at_40[0x7];
e281682b
SM		 7732 u8 polarity[0x1];
7733 u8 ob_tap0[0x8];
7734 u8 ob_tap1[0x8];
7735 u8 ob_tap2[0x8];
7736
b4ff3a36 7737 u8 reserved_at_60[0xc];
e281682b
SM		 7738 u8 ob_preemp_mode[0x4];
7739 u8 ob_reg[0x8];
7740 u8 ob_bias[0x8];
7741
b4ff3a36 7742 u8 reserved_at_80[0x20];
e281682b
SM		 7743};
7744
7745struct mlx5_ifc_slrg_reg_bits {
7746 u8 status[0x4];
7747 u8 version[0x4];
7748 u8 local_port[0x8];
7749 u8 pnat[0x2];
b4ff3a36 7750 u8 reserved_at_12[0x2];
e281682b 7751 u8 lane[0x4];
b4ff3a36 7752 u8 reserved_at_18[0x8];
e281682b
SM		 7753
7754 u8 time_to_link_up[0x10];
b4ff3a36 7755 u8 reserved_at_30[0xc];
e281682b
SM		 7756 u8 grade_lane_speed[0x4];
7757
7758 u8 grade_version[0x8];
7759 u8 grade[0x18];
7760
b4ff3a36 7761 u8 reserved_at_60[0x4];
e281682b
SM		 7762 u8 height_grade_type[0x4];
7763 u8 height_grade[0x18];
7764
7765 u8 height_dz[0x10];
7766 u8 height_dv[0x10];
7767
b4ff3a36 7768 u8 reserved_at_a0[0x10];
e281682b
SM		 7769 u8 height_sigma[0x10];
7770
b4ff3a36 7771 u8 reserved_at_c0[0x20];
e281682b 7772
b4ff3a36 7773 u8 reserved_at_e0[0x4];
e281682b
SM		 7774 u8 phase_grade_type[0x4];
7775 u8 phase_grade[0x18];
7776
b4ff3a36 7777 u8 reserved_at_100[0x8];
e281682b 7778 u8 phase_eo_pos[0x8];
b4ff3a36 7779 u8 reserved_at_110[0x8];
e281682b
SM		 7780 u8 phase_eo_neg[0x8];
7781
7782 u8 ffe_set_tested[0x10];
7783 u8 test_errors_per_lane[0x10];
7784};
7785
7786struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7787 u8 reserved_at_0[0x8];
e281682b 7788 u8 local_port[0x8];
b4ff3a36 7789 u8 reserved_at_10[0x10];
e281682b 7790
b4ff3a36 7791 u8 reserved_at_20[0x1c];
e281682b
SM		 7792 u8 vl_hw_cap[0x4];
7793
b4ff3a36 7794 u8 reserved_at_40[0x1c];
e281682b
SM		 7795 u8 vl_admin[0x4];
7796
b4ff3a36 7797 u8 reserved_at_60[0x1c];
e281682b
SM		 7798 u8 vl_operational[0x4];
7799};
7800
7801struct mlx5_ifc_pude_reg_bits {
7802 u8 swid[0x8];
7803 u8 local_port[0x8];
b4ff3a36 7804 u8 reserved_at_10[0x4];
e281682b 7805 u8 admin_status[0x4];
b4ff3a36 7806 u8 reserved_at_18[0x4];
e281682b
SM		 7807 u8 oper_status[0x4];
7808
b4ff3a36 7809 u8 reserved_at_20[0x60];
e281682b
SM		 7810};
7811
7812struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7813 u8 reserved_at_0[0x1];
7486216b 7814 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7815 u8 an_disable_cap[0x1];
7816 u8 reserved_at_3[0x5];
e281682b 7817 u8 local_port[0x8];
b4ff3a36 7818 u8 reserved_at_10[0xd];
e281682b
SM		 7819 u8 proto_mask[0x3];
7820
7486216b
SM		 7821 u8 an_status[0x4];
7822 u8 reserved_at_24[0x3c];
e281682b
SM		 7823
7824 u8 eth_proto_capability[0x20];
7825
7826 u8 ib_link_width_capability[0x10];
7827 u8 ib_proto_capability[0x10];
7828
b4ff3a36 7829 u8 reserved_at_a0[0x20];
e281682b
SM		 7830
7831 u8 eth_proto_admin[0x20];
7832
7833 u8 ib_link_width_admin[0x10];
7834 u8 ib_proto_admin[0x10];
7835
b4ff3a36 7836 u8 reserved_at_100[0x20];
e281682b
SM		 7837
7838 u8 eth_proto_oper[0x20];
7839
7840 u8 ib_link_width_oper[0x10];
7841 u8 ib_proto_oper[0x10];
7842
5b4793f8
EBE		 7843 u8 reserved_at_160[0x1c];
7844 u8 connector_type[0x4];
e281682b
SM		 7845
7846 u8 eth_proto_lp_advertise[0x20];
7847
b4ff3a36 7848 u8 reserved_at_1a0[0x60];
e281682b
SM		 7849};
7850
7d5e1423
SM		 7851struct mlx5_ifc_mlcr_reg_bits {
7852 u8 reserved_at_0[0x8];
7853 u8 local_port[0x8];
7854 u8 reserved_at_10[0x20];
7855
7856 u8 beacon_duration[0x10];
7857 u8 reserved_at_40[0x10];
7858
7859 u8 beacon_remain[0x10];
7860};
7861
e281682b 7862struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7863 u8 reserved_at_0[0x20];
e281682b
SM		 7864
7865 u8 algorithm_options[0x10];
b4ff3a36 7866 u8 reserved_at_30[0x4];
e281682b
SM		 7867 u8 repetitions_mode[0x4];
7868 u8 num_of_repetitions[0x8];
7869
7870 u8 grade_version[0x8];
7871 u8 height_grade_type[0x4];
7872 u8 phase_grade_type[0x4];
7873 u8 height_grade_weight[0x8];
7874 u8 phase_grade_weight[0x8];
7875
7876 u8 gisim_measure_bits[0x10];
7877 u8 adaptive_tap_measure_bits[0x10];
7878
7879 u8 ber_bath_high_error_threshold[0x10];
7880 u8 ber_bath_mid_error_threshold[0x10];
7881
7882 u8 ber_bath_low_error_threshold[0x10];
7883 u8 one_ratio_high_threshold[0x10];
7884
7885 u8 one_ratio_high_mid_threshold[0x10];
7886 u8 one_ratio_low_mid_threshold[0x10];
7887
7888 u8 one_ratio_low_threshold[0x10];
7889 u8 ndeo_error_threshold[0x10];
7890
7891 u8 mixer_offset_step_size[0x10];
b4ff3a36 7892 u8 reserved_at_110[0x8];
e281682b
SM		 7893 u8 mix90_phase_for_voltage_bath[0x8];
7894
7895 u8 mixer_offset_start[0x10];
7896 u8 mixer_offset_end[0x10];
7897
b4ff3a36 7898 u8 reserved_at_140[0x15];
e281682b
SM		 7899 u8 ber_test_time[0xb];
7900};
7901
7902struct mlx5_ifc_pspa_reg_bits {
7903 u8 swid[0x8];
7904 u8 local_port[0x8];
7905 u8 sub_port[0x8];
b4ff3a36 7906 u8 reserved_at_18[0x8];
e281682b 7907
b4ff3a36 7908 u8 reserved_at_20[0x20];
e281682b
SM		 7909};
7910
7911struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7912 u8 reserved_at_0[0x8];
e281682b 7913 u8 local_port[0x8];
b4ff3a36 7914 u8 reserved_at_10[0x5];
e281682b 7915 u8 prio[0x3];
b4ff3a36 7916 u8 reserved_at_18[0x6];
e281682b
SM		 7917 u8 mode[0x2];
7918
b4ff3a36 7919 u8 reserved_at_20[0x20];
e281682b 7920
b4ff3a36 7921 u8 reserved_at_40[0x10];
e281682b
SM		 7922 u8 min_threshold[0x10];
7923
b4ff3a36 7924 u8 reserved_at_60[0x10];
e281682b
SM		 7925 u8 max_threshold[0x10];
7926
b4ff3a36 7927 u8 reserved_at_80[0x10];
e281682b
SM		 7928 u8 mark_probability_denominator[0x10];
7929
b4ff3a36 7930 u8 reserved_at_a0[0x60];
e281682b
SM		 7931};
7932
7933struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7934 u8 reserved_at_0[0x8];
e281682b 7935 u8 local_port[0x8];
b4ff3a36 7936 u8 reserved_at_10[0x10];
e281682b 7937
b4ff3a36 7938 u8 reserved_at_20[0x60];
e281682b 7939
b4ff3a36 7940 u8 reserved_at_80[0x1c];
e281682b
SM		 7941 u8 wrps_admin[0x4];
7942
b4ff3a36 7943 u8 reserved_at_a0[0x1c];
e281682b
SM		 7944 u8 wrps_status[0x4];
7945
b4ff3a36 7946 u8 reserved_at_c0[0x8];
e281682b 7947 u8 up_threshold[0x8];
b4ff3a36 7948 u8 reserved_at_d0[0x8];
e281682b
SM		 7949 u8 down_threshold[0x8];
7950
b4ff3a36 7951 u8 reserved_at_e0[0x20];
e281682b 7952
b4ff3a36 7953 u8 reserved_at_100[0x1c];
e281682b
SM		 7954 u8 srps_admin[0x4];
7955
b4ff3a36 7956 u8 reserved_at_120[0x1c];
e281682b
SM		 7957 u8 srps_status[0x4];
7958
b4ff3a36 7959 u8 reserved_at_140[0x40];
e281682b
SM		 7960};
7961
7962struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7963 u8 reserved_at_0[0x8];
e281682b 7964 u8 local_port[0x8];
b4ff3a36 7965 u8 reserved_at_10[0x10];
e281682b 7966
b4ff3a36 7967 u8 reserved_at_20[0x8];
e281682b 7968 u8 lb_cap[0x8];
b4ff3a36 7969 u8 reserved_at_30[0x8];
e281682b
SM		 7970 u8 lb_en[0x8];
7971};
7972
7973struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7974 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 7975 u8 local_port[0x8];
7976 u8 reserved_at_10[0x10];
e281682b 7977
4b5b9c7d 7978 u8 reserved_at_20[0x20];
e281682b 7979
4b5b9c7d
SA		 7980 u8 port_profile_mode[0x8];
7981 u8 static_port_profile[0x8];
7982 u8 active_port_profile[0x8];
7983 u8 reserved_at_58[0x8];
e281682b 7984
4b5b9c7d
SA		 7985 u8 retransmission_active[0x8];
7986 u8 fec_mode_active[0x18];
e281682b 7987
4b5b9c7d
SA		 7988 u8 rs_fec_correction_bypass_cap[0x4];
7989 u8 reserved_at_84[0x8];
7990 u8 fec_override_cap_56g[0x4];
7991 u8 fec_override_cap_100g[0x4];
7992 u8 fec_override_cap_50g[0x4];
7993 u8 fec_override_cap_25g[0x4];
7994 u8 fec_override_cap_10g_40g[0x4];
7995
7996 u8 rs_fec_correction_bypass_admin[0x4];
7997 u8 reserved_at_a4[0x8];
7998 u8 fec_override_admin_56g[0x4];
7999 u8 fec_override_admin_100g[0x4];
8000 u8 fec_override_admin_50g[0x4];
8001 u8 fec_override_admin_25g[0x4];
8002 u8 fec_override_admin_10g_40g[0x4];
e281682b
SM		 8003};
8004
8005struct mlx5_ifc_ppcnt_reg_bits {
8006 u8 swid[0x8];
8007 u8 local_port[0x8];
8008 u8 pnat[0x2];
b4ff3a36 8009 u8 reserved_at_12[0x8];
e281682b
SM		 8010 u8 grp[0x6];
8011
8012 u8 clr[0x1];
b4ff3a36 8013 u8 reserved_at_21[0x1c];
e281682b
SM		 8014 u8 prio_tc[0x3];
8015
8016 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8017};
8018
8ed1a630
GP		 8019struct mlx5_ifc_mpcnt_reg_bits {
8020 u8 reserved_at_0[0x8];
8021 u8 pcie_index[0x8];
8022 u8 reserved_at_10[0xa];
8023 u8 grp[0x6];
8024
8025 u8 clr[0x1];
8026 u8 reserved_at_21[0x1f];
8027
8028 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8029};
8030
e281682b 8031struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 8032 u8 reserved_at_0[0x3];
e281682b 8033 u8 single_mac[0x1];
b4ff3a36 8034 u8 reserved_at_4[0x4];
e281682b
SM		 8035 u8 local_port[0x8];
8036 u8 mac_47_32[0x10];
8037
8038 u8 mac_31_0[0x20];
8039
b4ff3a36 8040 u8 reserved_at_40[0x40];
e281682b
SM		 8041};
8042
8043struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 8044 u8 reserved_at_0[0x8];
e281682b 8045 u8 local_port[0x8];
b4ff3a36 8046 u8 reserved_at_10[0x10];
e281682b
SM		 8047
8048 u8 max_mtu[0x10];
b4ff3a36 8049 u8 reserved_at_30[0x10];
e281682b
SM		 8050
8051 u8 admin_mtu[0x10];
b4ff3a36 8052 u8 reserved_at_50[0x10];
e281682b
SM		 8053
8054 u8 oper_mtu[0x10];
b4ff3a36 8055 u8 reserved_at_70[0x10];
e281682b
SM		 8056};
8057
8058struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 8059 u8 reserved_at_0[0x8];
e281682b 8060 u8 module[0x8];
b4ff3a36 8061 u8 reserved_at_10[0x10];
e281682b 8062
b4ff3a36 8063 u8 reserved_at_20[0x18];
e281682b
SM		 8064 u8 attenuation_5g[0x8];
8065
b4ff3a36 8066 u8 reserved_at_40[0x18];
e281682b
SM		 8067 u8 attenuation_7g[0x8];
8068
b4ff3a36 8069 u8 reserved_at_60[0x18];
e281682b
SM		 8070 u8 attenuation_12g[0x8];
8071};
8072
8073struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 8074 u8 reserved_at_0[0x8];
e281682b 8075 u8 module[0x8];
b4ff3a36 8076 u8 reserved_at_10[0xc];
e281682b
SM		 8077 u8 module_status[0x4];
8078
b4ff3a36 8079 u8 reserved_at_20[0x60];
e281682b
SM		 8080};
8081
8082struct mlx5_ifc_pmpc_reg_bits {
8083 u8 module_state_updated[32][0x8];
8084};
8085
8086struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 8087 u8 reserved_at_0[0x4];
e281682b
SM		 8088 u8 mlpn_status[0x4];
8089 u8 local_port[0x8];
b4ff3a36 8090 u8 reserved_at_10[0x10];
e281682b
SM		 8091
8092 u8 e[0x1];
b4ff3a36 8093 u8 reserved_at_21[0x1f];
e281682b
SM		 8094};
8095
8096struct mlx5_ifc_pmlp_reg_bits {
8097 u8 rxtx[0x1];
b4ff3a36 8098 u8 reserved_at_1[0x7];
e281682b 8099 u8 local_port[0x8];
b4ff3a36 8100 u8 reserved_at_10[0x8];
e281682b
SM		 8101 u8 width[0x8];
8102
8103 u8 lane0_module_mapping[0x20];
8104
8105 u8 lane1_module_mapping[0x20];
8106
8107 u8 lane2_module_mapping[0x20];
8108
8109 u8 lane3_module_mapping[0x20];
8110
b4ff3a36 8111 u8 reserved_at_a0[0x160];
e281682b
SM		 8112};
8113
8114struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 8115 u8 reserved_at_0[0x8];
e281682b 8116 u8 module[0x8];
b4ff3a36 8117 u8 reserved_at_10[0x4];
e281682b 8118 u8 admin_status[0x4];
b4ff3a36 8119 u8 reserved_at_18[0x4];
e281682b
SM		 8120 u8 oper_status[0x4];
8121
8122 u8 ase[0x1];
8123 u8 ee[0x1];
b4ff3a36 8124 u8 reserved_at_22[0x1c];
e281682b
SM		 8125 u8 e[0x2];
8126
b4ff3a36 8127 u8 reserved_at_40[0x40];
e281682b
SM		 8128};
8129
8130struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 8131 u8 reserved_at_0[0x4];
e281682b 8132 u8 profile_id[0xc];
b4ff3a36 8133 u8 reserved_at_10[0x4];
e281682b 8134 u8 proto_mask[0x4];
b4ff3a36 8135 u8 reserved_at_18[0x8];
e281682b 8136
b4ff3a36 8137 u8 reserved_at_20[0x10];
e281682b
SM		 8138 u8 lane_speed[0x10];
8139
b4ff3a36 8140 u8 reserved_at_40[0x17];
e281682b
SM		 8141 u8 lpbf[0x1];
8142 u8 fec_mode_policy[0x8];
8143
8144 u8 retransmission_capability[0x8];
8145 u8 fec_mode_capability[0x18];
8146
8147 u8 retransmission_support_admin[0x8];
8148 u8 fec_mode_support_admin[0x18];
8149
8150 u8 retransmission_request_admin[0x8];
8151 u8 fec_mode_request_admin[0x18];
8152
b4ff3a36 8153 u8 reserved_at_c0[0x80];
e281682b
SM		 8154};
8155
8156struct mlx5_ifc_plib_reg_bits {
b4ff3a36 8157 u8 reserved_at_0[0x8];
e281682b 8158 u8 local_port[0x8];
b4ff3a36 8159 u8 reserved_at_10[0x8];
e281682b
SM		 8160 u8 ib_port[0x8];
8161
b4ff3a36 8162 u8 reserved_at_20[0x60];
e281682b
SM		 8163};
8164
8165struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 8166 u8 reserved_at_0[0x8];
e281682b 8167 u8 local_port[0x8];
b4ff3a36 8168 u8 reserved_at_10[0xd];
e281682b
SM		 8169 u8 lbf_mode[0x3];
8170
b4ff3a36 8171 u8 reserved_at_20[0x20];
e281682b
SM		 8172};
8173
8174struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 8175 u8 reserved_at_0[0x8];
e281682b 8176 u8 local_port[0x8];
b4ff3a36 8177 u8 reserved_at_10[0x10];
e281682b
SM		 8178
8179 u8 dic[0x1];
b4ff3a36 8180 u8 reserved_at_21[0x19];
e281682b 8181 u8 ipg[0x4];
b4ff3a36 8182 u8 reserved_at_3e[0x2];
e281682b
SM		 8183};
8184
8185struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 8186 u8 reserved_at_0[0x8];
e281682b 8187 u8 local_port[0x8];
b4ff3a36 8188 u8 reserved_at_10[0x10];
e281682b 8189
b4ff3a36 8190 u8 reserved_at_20[0xe0];
e281682b
SM		 8191
8192 u8 port_filter[8][0x20];
8193
8194 u8 port_filter_update_en[8][0x20];
8195};
8196
8197struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 8198 u8 reserved_at_0[0x8];
e281682b 8199 u8 local_port[0x8];
2afa609f
IK		 8200 u8 reserved_at_10[0xb];
8201 u8 ppan_mask_n[0x1];
8202 u8 minor_stall_mask[0x1];
8203 u8 critical_stall_mask[0x1];
8204 u8 reserved_at_1e[0x2];
e281682b
SM		 8205
8206 u8 ppan[0x4];
b4ff3a36 8207 u8 reserved_at_24[0x4];
e281682b 8208 u8 prio_mask_tx[0x8];
b4ff3a36 8209 u8 reserved_at_30[0x8];
e281682b
SM		 8210 u8 prio_mask_rx[0x8];
8211
8212 u8 pptx[0x1];
8213 u8 aptx[0x1];
2afa609f
IK		 8214 u8 pptx_mask_n[0x1];
8215 u8 reserved_at_43[0x5];
e281682b 8216 u8 pfctx[0x8];
b4ff3a36 8217 u8 reserved_at_50[0x10];
e281682b
SM		 8218
8219 u8 pprx[0x1];
8220 u8 aprx[0x1];
2afa609f
IK		 8221 u8 pprx_mask_n[0x1];
8222 u8 reserved_at_63[0x5];
e281682b 8223 u8 pfcrx[0x8];
b4ff3a36 8224 u8 reserved_at_70[0x10];
e281682b 8225
2afa609f
IK		 8226 u8 device_stall_minor_watermark[0x10];
8227 u8 device_stall_critical_watermark[0x10];
8228
8229 u8 reserved_at_a0[0x60];
e281682b
SM		 8230};
8231
8232struct mlx5_ifc_pelc_reg_bits {
8233 u8 op[0x4];
b4ff3a36 8234 u8 reserved_at_4[0x4];
e281682b 8235 u8 local_port[0x8];
b4ff3a36 8236 u8 reserved_at_10[0x10];
e281682b
SM		 8237
8238 u8 op_admin[0x8];
8239 u8 op_capability[0x8];
8240 u8 op_request[0x8];
8241 u8 op_active[0x8];
8242
8243 u8 admin[0x40];
8244
8245 u8 capability[0x40];
8246
8247 u8 request[0x40];
8248
8249 u8 active[0x40];
8250
b4ff3a36 8251 u8 reserved_at_140[0x80];
e281682b
SM		 8252};
8253
8254struct mlx5_ifc_peir_reg_bits {
b4ff3a36 8255 u8 reserved_at_0[0x8];
e281682b 8256 u8 local_port[0x8];
b4ff3a36 8257 u8 reserved_at_10[0x10];
e281682b 8258
b4ff3a36 8259 u8 reserved_at_20[0xc];
e281682b 8260 u8 error_count[0x4];
b4ff3a36 8261 u8 reserved_at_30[0x10];
e281682b 8262
b4ff3a36 8263 u8 reserved_at_40[0xc];
e281682b 8264 u8 lane[0x4];
b4ff3a36 8265 u8 reserved_at_50[0x8];
e281682b
SM		 8266 u8 error_type[0x8];
8267};
8268
5e022dd3
EBE		 8269struct mlx5_ifc_mpegc_reg_bits {
8270 u8 reserved_at_0[0x30];
8271 u8 field_select[0x10];
8272
8273 u8 tx_overflow_sense[0x1];
8274 u8 mark_cqe[0x1];
8275 u8 mark_cnp[0x1];
8276 u8 reserved_at_43[0x1b];
8277 u8 tx_lossy_overflow_oper[0x2];
8278
8279 u8 reserved_at_60[0x100];
8280};
8281
cfdcbcea 8282struct mlx5_ifc_pcam_enhanced_features_bits {
0af5107c
TB		 8283 u8 reserved_at_0[0x6d];
8284 u8 rx_icrc_encapsulated_counter[0x1];
8285 u8 reserved_at_6e[0x8];
2fcb12df 8286 u8 pfcc_mask[0x1];
67daf118
SA		 8287 u8 reserved_at_77[0x3];
8288 u8 per_lane_error_counters[0x1];
2dba0797 8289 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8290 u8 ptys_connector_type[0x1];
8291 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8292 u8 ppcnt_discard_group[0x1];
8293 u8 ppcnt_statistical_group[0x1];
8294};
8295
df5f1361
HN		 8296struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8297 u8 port_access_reg_cap_mask_127_to_96[0x20];
8298 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 8299
8300 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8301 u8 pplm[0x1];
8302 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 8303
8304 u8 port_access_reg_cap_mask_31_to_13[0x13];
8305 u8 pbmc[0x1];
8306 u8 pptb[0x1];
75370eb0
ED		 8307 u8 port_access_reg_cap_mask_10_to_09[0x2];
8308 u8 ppcnt[0x1];
8309 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 8310};
8311
cfdcbcea
GP		 8312struct mlx5_ifc_pcam_reg_bits {
8313 u8 reserved_at_0[0x8];
8314 u8 feature_group[0x8];
8315 u8 reserved_at_10[0x8];
8316 u8 access_reg_group[0x8];
8317
8318 u8 reserved_at_20[0x20];
8319
8320 union {
df5f1361 8321 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 8322 u8 reserved_at_0[0x80];
8323 } port_access_reg_cap_mask;
8324
8325 u8 reserved_at_c0[0x80];
8326
8327 union {
8328 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8329 u8 reserved_at_0[0x80];
8330 } feature_cap_mask;
8331
8332 u8 reserved_at_1c0[0xc0];
8333};
8334
8335struct mlx5_ifc_mcam_enhanced_features_bits {
5e022dd3
EBE		 8336 u8 reserved_at_0[0x74];
8337 u8 mark_tx_action_cnp[0x1];
8338 u8 mark_tx_action_cqe[0x1];
8339 u8 dynamic_tx_overflow[0x1];
8340 u8 reserved_at_77[0x4];
5405fa26 8341 u8 pcie_outbound_stalled[0x1];
efae7f78 8342 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8343 u8 mtpps_enh_out_per_adj[0x1];
8344 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8345 u8 pcie_performance_group[0x1];
8346};
8347
0ab87743
OG		 8348struct mlx5_ifc_mcam_access_reg_bits {
8349 u8 reserved_at_0[0x1c];
8350 u8 mcda[0x1];
8351 u8 mcc[0x1];
8352 u8 mcqi[0x1];
8353 u8 reserved_at_1f[0x1];
8354
5e022dd3
EBE		 8355 u8 regs_95_to_87[0x9];
8356 u8 mpegc[0x1];
8357 u8 regs_85_to_68[0x12];
eff8ea8f
FD		 8358 u8 tracer_registers[0x4];
8359
0ab87743
OG		 8360 u8 regs_63_to_32[0x20];
8361 u8 regs_31_to_0[0x20];
8362};
8363
cfdcbcea
GP		 8364struct mlx5_ifc_mcam_reg_bits {
8365 u8 reserved_at_0[0x8];
8366 u8 feature_group[0x8];
8367 u8 reserved_at_10[0x8];
8368 u8 access_reg_group[0x8];
8369
8370 u8 reserved_at_20[0x20];
8371
8372 union {
0ab87743 8373 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8374 u8 reserved_at_0[0x80];
8375 } mng_access_reg_cap_mask;
8376
8377 u8 reserved_at_c0[0x80];
8378
8379 union {
8380 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8381 u8 reserved_at_0[0x80];
8382 } mng_feature_cap_mask;
8383
8384 u8 reserved_at_1c0[0x80];
8385};
8386
c02762eb
HN		 8387struct mlx5_ifc_qcam_access_reg_cap_mask {
8388 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8389 u8 qpdpm[0x1];
8390 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8391 u8 qdpm[0x1];
8392 u8 qpts[0x1];
8393 u8 qcap[0x1];
8394 u8 qcam_access_reg_cap_mask_0[0x1];
8395};
8396
8397struct mlx5_ifc_qcam_qos_feature_cap_mask {
8398 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8399 u8 qpts_trust_both[0x1];
8400};
8401
8402struct mlx5_ifc_qcam_reg_bits {
8403 u8 reserved_at_0[0x8];
8404 u8 feature_group[0x8];
8405 u8 reserved_at_10[0x8];
8406 u8 access_reg_group[0x8];
8407 u8 reserved_at_20[0x20];
8408
8409 union {
8410 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8411 u8 reserved_at_0[0x80];
8412 } qos_access_reg_cap_mask;
8413
8414 u8 reserved_at_c0[0x80];
8415
8416 union {
8417 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8418 u8 reserved_at_0[0x80];
8419 } qos_feature_cap_mask;
8420
8421 u8 reserved_at_1c0[0x80];
8422};
8423
e281682b 8424struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8425 u8 reserved_at_0[0x8];
e281682b 8426 u8 local_port[0x8];
b4ff3a36 8427 u8 reserved_at_10[0x10];
e281682b
SM		 8428
8429 u8 port_capability_mask[4][0x20];
8430};
8431
8432struct mlx5_ifc_paos_reg_bits {
8433 u8 swid[0x8];
8434 u8 local_port[0x8];
b4ff3a36 8435 u8 reserved_at_10[0x4];
e281682b 8436 u8 admin_status[0x4];
b4ff3a36 8437 u8 reserved_at_18[0x4];
e281682b
SM		 8438 u8 oper_status[0x4];
8439
8440 u8 ase[0x1];
8441 u8 ee[0x1];
b4ff3a36 8442 u8 reserved_at_22[0x1c];
e281682b
SM		 8443 u8 e[0x2];
8444
b4ff3a36 8445 u8 reserved_at_40[0x40];
e281682b
SM		 8446};
8447
8448struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8449 u8 reserved_at_0[0x8];
e281682b 8450 u8 opamp_group[0x8];
b4ff3a36 8451 u8 reserved_at_10[0xc];
e281682b
SM		 8452 u8 opamp_group_type[0x4];
8453
8454 u8 start_index[0x10];
b4ff3a36 8455 u8 reserved_at_30[0x4];
e281682b
SM		 8456 u8 num_of_indices[0xc];
8457
8458 u8 index_data[18][0x10];
8459};
8460
7d5e1423
SM		 8461struct mlx5_ifc_pcmr_reg_bits {
8462 u8 reserved_at_0[0x8];
8463 u8 local_port[0x8];
8464 u8 reserved_at_10[0x2e];
8465 u8 fcs_cap[0x1];
8466 u8 reserved_at_3f[0x1f];
8467 u8 fcs_chk[0x1];
8468 u8 reserved_at_5f[0x1];
8469};
8470
e281682b 8471struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8472 u8 reserved_at_0[0x6];
e281682b 8473 u8 rx_lane[0x2];
b4ff3a36 8474 u8 reserved_at_8[0x6];
e281682b 8475 u8 tx_lane[0x2];
b4ff3a36 8476 u8 reserved_at_10[0x8];
e281682b
SM		 8477 u8 module[0x8];
8478};
8479
8480struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8481 u8 reserved_at_0[0x6];
e281682b
SM		 8482 u8 lossy[0x1];
8483 u8 epsb[0x1];
b4ff3a36 8484 u8 reserved_at_8[0xc];
e281682b
SM		 8485 u8 size[0xc];
8486
8487 u8 xoff_threshold[0x10];
8488 u8 xon_threshold[0x10];
8489};
8490
8491struct mlx5_ifc_set_node_in_bits {
8492 u8 node_description[64][0x8];
8493};
8494
8495struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8496 u8 reserved_at_0[0x18];
e281682b
SM		 8497 u8 power_settings_level[0x8];
8498
b4ff3a36 8499 u8 reserved_at_20[0x60];
e281682b
SM		 8500};
8501
8502struct mlx5_ifc_register_host_endianness_bits {
8503 u8 he[0x1];
b4ff3a36 8504 u8 reserved_at_1[0x1f];
e281682b 8505
b4ff3a36 8506 u8 reserved_at_20[0x60];
e281682b
SM		 8507};
8508
8509struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8510 u8 reserved_at_0[0x20];
e281682b
SM		 8511
8512 u8 mkey[0x20];
8513
8514 u8 addressh_63_32[0x20];
8515
8516 u8 addressl_31_0[0x20];
8517};
8518
8519struct mlx5_ifc_ud_adrs_vector_bits {
8520 u8 dc_key[0x40];
8521
8522 u8 ext[0x1];
b4ff3a36 8523 u8 reserved_at_41[0x7];
e281682b
SM		 8524 u8 destination_qp_dct[0x18];
8525
8526 u8 static_rate[0x4];
8527 u8 sl_eth_prio[0x4];
8528 u8 fl[0x1];
8529 u8 mlid[0x7];
8530 u8 rlid_udp_sport[0x10];
8531
b4ff3a36 8532 u8 reserved_at_80[0x20];
e281682b
SM		 8533
8534 u8 rmac_47_16[0x20];
8535
8536 u8 rmac_15_0[0x10];
8537 u8 tclass[0x8];
8538 u8 hop_limit[0x8];
8539
b4ff3a36 8540 u8 reserved_at_e0[0x1];
e281682b 8541 u8 grh[0x1];
b4ff3a36 8542 u8 reserved_at_e2[0x2];
e281682b
SM		 8543 u8 src_addr_index[0x8];
8544 u8 flow_label[0x14];
8545
8546 u8 rgid_rip[16][0x8];
8547};
8548
8549struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8550 u8 reserved_at_0[0x10];
e281682b
SM		 8551 u8 function_id[0x10];
8552
8553 u8 num_pages[0x20];
8554
b4ff3a36 8555 u8 reserved_at_40[0xa0];
e281682b
SM		 8556};
8557
8558struct mlx5_ifc_eqe_bits {
b4ff3a36 8559 u8 reserved_at_0[0x8];
e281682b 8560 u8 event_type[0x8];
b4ff3a36 8561 u8 reserved_at_10[0x8];
e281682b
SM		 8562 u8 event_sub_type[0x8];
8563
b4ff3a36 8564 u8 reserved_at_20[0xe0];
e281682b
SM		 8565
8566 union mlx5_ifc_event_auto_bits event_data;
8567
b4ff3a36 8568 u8 reserved_at_1e0[0x10];
e281682b 8569 u8 signature[0x8];
b4ff3a36 8570 u8 reserved_at_1f8[0x7];
e281682b
SM		 8571 u8 owner[0x1];
8572};
8573
8574enum {
8575 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8576};
8577
8578struct mlx5_ifc_cmd_queue_entry_bits {
8579 u8 type[0x8];
b4ff3a36 8580 u8 reserved_at_8[0x18];
e281682b
SM		 8581
8582 u8 input_length[0x20];
8583
8584 u8 input_mailbox_pointer_63_32[0x20];
8585
8586 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8587 u8 reserved_at_77[0x9];
e281682b
SM		 8588
8589 u8 command_input_inline_data[16][0x8];
8590
8591 u8 command_output_inline_data[16][0x8];
8592
8593 u8 output_mailbox_pointer_63_32[0x20];
8594
8595 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8596 u8 reserved_at_1b7[0x9];
e281682b
SM		 8597
8598 u8 output_length[0x20];
8599
8600 u8 token[0x8];
8601 u8 signature[0x8];
b4ff3a36 8602 u8 reserved_at_1f0[0x8];
e281682b
SM		 8603 u8 status[0x7];
8604 u8 ownership[0x1];
8605};
8606
8607struct mlx5_ifc_cmd_out_bits {
8608 u8 status[0x8];
b4ff3a36 8609 u8 reserved_at_8[0x18];
e281682b
SM		 8610
8611 u8 syndrome[0x20];
8612
8613 u8 command_output[0x20];
8614};
8615
8616struct mlx5_ifc_cmd_in_bits {
8617 u8 opcode[0x10];
b4ff3a36 8618 u8 reserved_at_10[0x10];
e281682b 8619
b4ff3a36 8620 u8 reserved_at_20[0x10];
e281682b
SM		 8621 u8 op_mod[0x10];
8622
8623 u8 command[0][0x20];
8624};
8625
8626struct mlx5_ifc_cmd_if_box_bits {
8627 u8 mailbox_data[512][0x8];
8628
b4ff3a36 8629 u8 reserved_at_1000[0x180];
e281682b
SM		 8630
8631 u8 next_pointer_63_32[0x20];
8632
8633 u8 next_pointer_31_10[0x16];
b4ff3a36 8634 u8 reserved_at_11b6[0xa];
e281682b
SM		 8635
8636 u8 block_number[0x20];
8637
b4ff3a36 8638 u8 reserved_at_11e0[0x8];
e281682b
SM		 8639 u8 token[0x8];
8640 u8 ctrl_signature[0x8];
8641 u8 signature[0x8];
8642};
8643
8644struct mlx5_ifc_mtt_bits {
8645 u8 ptag_63_32[0x20];
8646
8647 u8 ptag_31_8[0x18];
b4ff3a36 8648 u8 reserved_at_38[0x6];
e281682b
SM		 8649 u8 wr_en[0x1];
8650 u8 rd_en[0x1];
8651};
8652
928cfe87
TT		 8653struct mlx5_ifc_query_wol_rol_out_bits {
8654 u8 status[0x8];
8655 u8 reserved_at_8[0x18];
8656
8657 u8 syndrome[0x20];
8658
8659 u8 reserved_at_40[0x10];
8660 u8 rol_mode[0x8];
8661 u8 wol_mode[0x8];
8662
8663 u8 reserved_at_60[0x20];
8664};
8665
8666struct mlx5_ifc_query_wol_rol_in_bits {
8667 u8 opcode[0x10];
8668 u8 reserved_at_10[0x10];
8669
8670 u8 reserved_at_20[0x10];
8671 u8 op_mod[0x10];
8672
8673 u8 reserved_at_40[0x40];
8674};
8675
8676struct mlx5_ifc_set_wol_rol_out_bits {
8677 u8 status[0x8];
8678 u8 reserved_at_8[0x18];
8679
8680 u8 syndrome[0x20];
8681
8682 u8 reserved_at_40[0x40];
8683};
8684
8685struct mlx5_ifc_set_wol_rol_in_bits {
8686 u8 opcode[0x10];
8687 u8 reserved_at_10[0x10];
8688
8689 u8 reserved_at_20[0x10];
8690 u8 op_mod[0x10];
8691
8692 u8 rol_mode_valid[0x1];
8693 u8 wol_mode_valid[0x1];
8694 u8 reserved_at_42[0xe];
8695 u8 rol_mode[0x8];
8696 u8 wol_mode[0x8];
8697
8698 u8 reserved_at_60[0x20];
8699};
8700
e281682b
SM		 8701enum {
8702 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8703 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8704 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8705};
8706
8707enum {
8708 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8709 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8710 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8711};
8712
8713enum {
8714 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8715 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8716 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8717 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8718 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8725};
8726
8727struct mlx5_ifc_initial_seg_bits {
8728 u8 fw_rev_minor[0x10];
8729 u8 fw_rev_major[0x10];
8730
8731 u8 cmd_interface_rev[0x10];
8732 u8 fw_rev_subminor[0x10];
8733
b4ff3a36 8734 u8 reserved_at_40[0x40];
e281682b
SM		 8735
8736 u8 cmdq_phy_addr_63_32[0x20];
8737
8738 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8739 u8 reserved_at_b4[0x2];
e281682b
SM		 8740 u8 nic_interface[0x2];
8741 u8 log_cmdq_size[0x4];
8742 u8 log_cmdq_stride[0x4];
8743
8744 u8 command_doorbell_vector[0x20];
8745
b4ff3a36 8746 u8 reserved_at_e0[0xf00];
e281682b
SM		 8747
8748 u8 initializing[0x1];
b4ff3a36 8749 u8 reserved_at_fe1[0x4];
e281682b 8750 u8 nic_interface_supported[0x3];
b4ff3a36 8751 u8 reserved_at_fe8[0x18];
e281682b
SM		 8752
8753 struct mlx5_ifc_health_buffer_bits health_buffer;
8754
8755 u8 no_dram_nic_offset[0x20];
8756
b4ff3a36 8757 u8 reserved_at_1220[0x6e40];
e281682b 8758
b4ff3a36 8759 u8 reserved_at_8060[0x1f];
e281682b
SM		 8760 u8 clear_int[0x1];
8761
8762 u8 health_syndrome[0x8];
8763 u8 health_counter[0x18];
8764
b4ff3a36 8765 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8766};
8767
f9a1ef72
EE		 8768struct mlx5_ifc_mtpps_reg_bits {
8769 u8 reserved_at_0[0xc];
8770 u8 cap_number_of_pps_pins[0x4];
8771 u8 reserved_at_10[0x4];
8772 u8 cap_max_num_of_pps_in_pins[0x4];
8773 u8 reserved_at_18[0x4];
8774 u8 cap_max_num_of_pps_out_pins[0x4];
8775
8776 u8 reserved_at_20[0x24];
8777 u8 cap_pin_3_mode[0x4];
8778 u8 reserved_at_48[0x4];
8779 u8 cap_pin_2_mode[0x4];
8780 u8 reserved_at_50[0x4];
8781 u8 cap_pin_1_mode[0x4];
8782 u8 reserved_at_58[0x4];
8783 u8 cap_pin_0_mode[0x4];
8784
8785 u8 reserved_at_60[0x4];
8786 u8 cap_pin_7_mode[0x4];
8787 u8 reserved_at_68[0x4];
8788 u8 cap_pin_6_mode[0x4];
8789 u8 reserved_at_70[0x4];
8790 u8 cap_pin_5_mode[0x4];
8791 u8 reserved_at_78[0x4];
8792 u8 cap_pin_4_mode[0x4];
8793
fa367688
EE		 8794 u8 field_select[0x20];
8795 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8796
8797 u8 enable[0x1];
8798 u8 reserved_at_101[0xb];
8799 u8 pattern[0x4];
8800 u8 reserved_at_110[0x4];
8801 u8 pin_mode[0x4];
8802 u8 pin[0x8];
8803
8804 u8 reserved_at_120[0x20];
8805
8806 u8 time_stamp[0x40];
8807
8808 u8 out_pulse_duration[0x10];
8809 u8 out_periodic_adjustment[0x10];
fa367688 8810 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8811
fa367688 8812 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8813};
8814
8815struct mlx5_ifc_mtppse_reg_bits {
8816 u8 reserved_at_0[0x18];
8817 u8 pin[0x8];
8818 u8 event_arm[0x1];
8819 u8 reserved_at_21[0x1b];
8820 u8 event_generation_mode[0x4];
8821 u8 reserved_at_40[0x40];
8822};
8823
47176289
OG		 8824struct mlx5_ifc_mcqi_cap_bits {
8825 u8 supported_info_bitmask[0x20];
8826
8827 u8 component_size[0x20];
8828
8829 u8 max_component_size[0x20];
8830
8831 u8 log_mcda_word_size[0x4];
8832 u8 reserved_at_64[0xc];
8833 u8 mcda_max_write_size[0x10];
8834
8835 u8 rd_en[0x1];
8836 u8 reserved_at_81[0x1];
8837 u8 match_chip_id[0x1];
8838 u8 match_psid[0x1];
8839 u8 check_user_timestamp[0x1];
8840 u8 match_base_guid_mac[0x1];
8841 u8 reserved_at_86[0x1a];
8842};
8843
8844struct mlx5_ifc_mcqi_reg_bits {
8845 u8 read_pending_component[0x1];
8846 u8 reserved_at_1[0xf];
8847 u8 component_index[0x10];
8848
8849 u8 reserved_at_20[0x20];
8850
8851 u8 reserved_at_40[0x1b];
8852 u8 info_type[0x5];
8853
8854 u8 info_size[0x20];
8855
8856 u8 offset[0x20];
8857
8858 u8 reserved_at_a0[0x10];
8859 u8 data_size[0x10];
8860
8861 u8 data[0][0x20];
8862};
8863
8864struct mlx5_ifc_mcc_reg_bits {
8865 u8 reserved_at_0[0x4];
8866 u8 time_elapsed_since_last_cmd[0xc];
8867 u8 reserved_at_10[0x8];
8868 u8 instruction[0x8];
8869
8870 u8 reserved_at_20[0x10];
8871 u8 component_index[0x10];
8872
8873 u8 reserved_at_40[0x8];
8874 u8 update_handle[0x18];
8875
8876 u8 handle_owner_type[0x4];
8877 u8 handle_owner_host_id[0x4];
8878 u8 reserved_at_68[0x1];
8879 u8 control_progress[0x7];
8880 u8 error_code[0x8];
8881 u8 reserved_at_78[0x4];
8882 u8 control_state[0x4];
8883
8884 u8 component_size[0x20];
8885
8886 u8 reserved_at_a0[0x60];
8887};
8888
8889struct mlx5_ifc_mcda_reg_bits {
8890 u8 reserved_at_0[0x8];
8891 u8 update_handle[0x18];
8892
8893 u8 offset[0x20];
8894
8895 u8 reserved_at_40[0x10];
8896 u8 size[0x10];
8897
8898 u8 reserved_at_60[0x20];
8899
8900 u8 data[0][0x20];
8901};
8902
e281682b
SM		 8903union mlx5_ifc_ports_control_registers_document_bits {
8904 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8905 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8906 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8907 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8908 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8909 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8910 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8911 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8912 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8913 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8914 struct mlx5_ifc_paos_reg_bits paos_reg;
8915 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8916 struct mlx5_ifc_peir_reg_bits peir_reg;
8917 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8918 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8919 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8920 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8921 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8922 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8923 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8924 struct mlx5_ifc_plib_reg_bits plib_reg;
8925 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8926 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8927 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8928 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8929 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8930 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8931 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8932 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8933 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8934 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8935 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8936 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8937 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8938 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8939 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8940 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8941 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8942 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8943 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8944 struct mlx5_ifc_pude_reg_bits pude_reg;
8945 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8946 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8947 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8948 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8949 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8950 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8951 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8952 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8953 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8954 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8955 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8956 u8 reserved_at_0[0x60e0];
e281682b
SM		 8957};
8958
8959union mlx5_ifc_debug_enhancements_document_bits {
8960 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8961 u8 reserved_at_0[0x200];
e281682b
SM		 8962};
8963
8964union mlx5_ifc_uplink_pci_interface_document_bits {
8965 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8966 u8 reserved_at_0[0x20060];
b775516b
EC		 8967};
8968
2cc43b49
MG		 8969struct mlx5_ifc_set_flow_table_root_out_bits {
8970 u8 status[0x8];
b4ff3a36 8971 u8 reserved_at_8[0x18];
2cc43b49
MG		 8972
8973 u8 syndrome[0x20];
8974
b4ff3a36 8975 u8 reserved_at_40[0x40];
2cc43b49
MG		 8976};
8977
8978struct mlx5_ifc_set_flow_table_root_in_bits {
8979 u8 opcode[0x10];
b4ff3a36 8980 u8 reserved_at_10[0x10];
2cc43b49 8981
b4ff3a36 8982 u8 reserved_at_20[0x10];
2cc43b49
MG		 8983 u8 op_mod[0x10];
8984
7d5e1423
SM		 8985 u8 other_vport[0x1];
8986 u8 reserved_at_41[0xf];
8987 u8 vport_number[0x10];
8988
8989 u8 reserved_at_60[0x20];
2cc43b49
MG		 8990
8991 u8 table_type[0x8];
b4ff3a36 8992 u8 reserved_at_88[0x18];
2cc43b49 8993
b4ff3a36 8994 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8995 u8 table_id[0x18];
8996
500a3d0d
ES		 8997 u8 reserved_at_c0[0x8];
8998 u8 underlay_qpn[0x18];
8999 u8 reserved_at_e0[0x120];
2cc43b49
MG		 9000};
9001
34a40e68 9002enum {
84df61eb
AH		 9003 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9004 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 9005};
9006
9007struct mlx5_ifc_modify_flow_table_out_bits {
9008 u8 status[0x8];
b4ff3a36 9009 u8 reserved_at_8[0x18];
34a40e68
MG		 9010
9011 u8 syndrome[0x20];
9012
b4ff3a36 9013 u8 reserved_at_40[0x40];
34a40e68
MG		 9014};
9015
9016struct mlx5_ifc_modify_flow_table_in_bits {
9017 u8 opcode[0x10];
b4ff3a36 9018 u8 reserved_at_10[0x10];
34a40e68 9019
b4ff3a36 9020 u8 reserved_at_20[0x10];
34a40e68
MG		 9021 u8 op_mod[0x10];
9022
7d5e1423
SM		 9023 u8 other_vport[0x1];
9024 u8 reserved_at_41[0xf];
9025 u8 vport_number[0x10];
34a40e68 9026
b4ff3a36 9027 u8 reserved_at_60[0x10];
34a40e68
MG		 9028 u8 modify_field_select[0x10];
9029
9030 u8 table_type[0x8];
b4ff3a36 9031 u8 reserved_at_88[0x18];
34a40e68 9032
b4ff3a36 9033 u8 reserved_at_a0[0x8];
34a40e68
MG		 9034 u8 table_id[0x18];
9035
0c90e9c6 9036 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 9037};
9038
4f3961ee
SM		 9039struct mlx5_ifc_ets_tcn_config_reg_bits {
9040 u8 g[0x1];
9041 u8 b[0x1];
9042 u8 r[0x1];
9043 u8 reserved_at_3[0x9];
9044 u8 group[0x4];
9045 u8 reserved_at_10[0x9];
9046 u8 bw_allocation[0x7];
9047
9048 u8 reserved_at_20[0xc];
9049 u8 max_bw_units[0x4];
9050 u8 reserved_at_30[0x8];
9051 u8 max_bw_value[0x8];
9052};
9053
9054struct mlx5_ifc_ets_global_config_reg_bits {
9055 u8 reserved_at_0[0x2];
9056 u8 r[0x1];
9057 u8 reserved_at_3[0x1d];
9058
9059 u8 reserved_at_20[0xc];
9060 u8 max_bw_units[0x4];
9061 u8 reserved_at_30[0x8];
9062 u8 max_bw_value[0x8];
9063};
9064
9065struct mlx5_ifc_qetc_reg_bits {
9066 u8 reserved_at_0[0x8];
9067 u8 port_number[0x8];
9068 u8 reserved_at_10[0x30];
9069
9070 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9071 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9072};
9073
415a64aa
HN		 9074struct mlx5_ifc_qpdpm_dscp_reg_bits {
9075 u8 e[0x1];
9076 u8 reserved_at_01[0x0b];
9077 u8 prio[0x04];
9078};
9079
9080struct mlx5_ifc_qpdpm_reg_bits {
9081 u8 reserved_at_0[0x8];
9082 u8 local_port[0x8];
9083 u8 reserved_at_10[0x10];
9084 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9085};
9086
9087struct mlx5_ifc_qpts_reg_bits {
9088 u8 reserved_at_0[0x8];
9089 u8 local_port[0x8];
9090 u8 reserved_at_10[0x2d];
9091 u8 trust_state[0x3];
9092};
9093
50b4a3c2
HN		 9094struct mlx5_ifc_pptb_reg_bits {
9095 u8 reserved_at_0[0x2];
9096 u8 mm[0x2];
9097 u8 reserved_at_4[0x4];
9098 u8 local_port[0x8];
9099 u8 reserved_at_10[0x6];
9100 u8 cm[0x1];
9101 u8 um[0x1];
9102 u8 pm[0x8];
9103
9104 u8 prio_x_buff[0x20];
9105
9106 u8 pm_msb[0x8];
9107 u8 reserved_at_48[0x10];
9108 u8 ctrl_buff[0x4];
9109 u8 untagged_buff[0x4];
9110};
9111
9112struct mlx5_ifc_pbmc_reg_bits {
9113 u8 reserved_at_0[0x8];
9114 u8 local_port[0x8];
9115 u8 reserved_at_10[0x10];
9116
9117 u8 xoff_timer_value[0x10];
9118 u8 xoff_refresh[0x10];
9119
9120 u8 reserved_at_40[0x9];
9121 u8 fullness_threshold[0x7];
9122 u8 port_buffer_size[0x10];
9123
9124 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9125
9126 u8 reserved_at_2e0[0x40];
9127};
9128
4f3961ee
SM		 9129struct mlx5_ifc_qtct_reg_bits {
9130 u8 reserved_at_0[0x8];
9131 u8 port_number[0x8];
9132 u8 reserved_at_10[0xd];
9133 u8 prio[0x3];
9134
9135 u8 reserved_at_20[0x1d];
9136 u8 tclass[0x3];
9137};
9138
7d5e1423
SM		 9139struct mlx5_ifc_mcia_reg_bits {
9140 u8 l[0x1];
9141 u8 reserved_at_1[0x7];
9142 u8 module[0x8];
9143 u8 reserved_at_10[0x8];
9144 u8 status[0x8];
9145
9146 u8 i2c_device_address[0x8];
9147 u8 page_number[0x8];
9148 u8 device_address[0x10];
9149
9150 u8 reserved_at_40[0x10];
9151 u8 size[0x10];
9152
9153 u8 reserved_at_60[0x20];
9154
9155 u8 dword_0[0x20];
9156 u8 dword_1[0x20];
9157 u8 dword_2[0x20];
9158 u8 dword_3[0x20];
9159 u8 dword_4[0x20];
9160 u8 dword_5[0x20];
9161 u8 dword_6[0x20];
9162 u8 dword_7[0x20];
9163 u8 dword_8[0x20];
9164 u8 dword_9[0x20];
9165 u8 dword_10[0x20];
9166 u8 dword_11[0x20];
9167};
9168
7486216b
SM		 9169struct mlx5_ifc_dcbx_param_bits {
9170 u8 dcbx_cee_cap[0x1];
9171 u8 dcbx_ieee_cap[0x1];
9172 u8 dcbx_standby_cap[0x1];
c74d90c1 9173 u8 reserved_at_3[0x5];
7486216b
SM		 9174 u8 port_number[0x8];
9175 u8 reserved_at_10[0xa];
9176 u8 max_application_table_size[6];
9177 u8 reserved_at_20[0x15];
9178 u8 version_oper[0x3];
9179 u8 reserved_at_38[5];
9180 u8 version_admin[0x3];
9181 u8 willing_admin[0x1];
9182 u8 reserved_at_41[0x3];
9183 u8 pfc_cap_oper[0x4];
9184 u8 reserved_at_48[0x4];
9185 u8 pfc_cap_admin[0x4];
9186 u8 reserved_at_50[0x4];
9187 u8 num_of_tc_oper[0x4];
9188 u8 reserved_at_58[0x4];
9189 u8 num_of_tc_admin[0x4];
9190 u8 remote_willing[0x1];
9191 u8 reserved_at_61[3];
9192 u8 remote_pfc_cap[4];
9193 u8 reserved_at_68[0x14];
9194 u8 remote_num_of_tc[0x4];
9195 u8 reserved_at_80[0x18];
9196 u8 error[0x8];
9197 u8 reserved_at_a0[0x160];
9198};
84df61eb
AH		 9199
9200struct mlx5_ifc_lagc_bits {
9201 u8 reserved_at_0[0x1d];
9202 u8 lag_state[0x3];
9203
9204 u8 reserved_at_20[0x14];
9205 u8 tx_remap_affinity_2[0x4];
9206 u8 reserved_at_38[0x4];
9207 u8 tx_remap_affinity_1[0x4];
9208};
9209
9210struct mlx5_ifc_create_lag_out_bits {
9211 u8 status[0x8];
9212 u8 reserved_at_8[0x18];
9213
9214 u8 syndrome[0x20];
9215
9216 u8 reserved_at_40[0x40];
9217};
9218
9219struct mlx5_ifc_create_lag_in_bits {
9220 u8 opcode[0x10];
9221 u8 reserved_at_10[0x10];
9222
9223 u8 reserved_at_20[0x10];
9224 u8 op_mod[0x10];
9225
9226 struct mlx5_ifc_lagc_bits ctx;
9227};
9228
9229struct mlx5_ifc_modify_lag_out_bits {
9230 u8 status[0x8];
9231 u8 reserved_at_8[0x18];
9232
9233 u8 syndrome[0x20];
9234
9235 u8 reserved_at_40[0x40];
9236};
9237
9238struct mlx5_ifc_modify_lag_in_bits {
9239 u8 opcode[0x10];
9240 u8 reserved_at_10[0x10];
9241
9242 u8 reserved_at_20[0x10];
9243 u8 op_mod[0x10];
9244
9245 u8 reserved_at_40[0x20];
9246 u8 field_select[0x20];
9247
9248 struct mlx5_ifc_lagc_bits ctx;
9249};
9250
9251struct mlx5_ifc_query_lag_out_bits {
9252 u8 status[0x8];
9253 u8 reserved_at_8[0x18];
9254
9255 u8 syndrome[0x20];
9256
9257 u8 reserved_at_40[0x40];
9258
9259 struct mlx5_ifc_lagc_bits ctx;
9260};
9261
9262struct mlx5_ifc_query_lag_in_bits {
9263 u8 opcode[0x10];
9264 u8 reserved_at_10[0x10];
9265
9266 u8 reserved_at_20[0x10];
9267 u8 op_mod[0x10];
9268
9269 u8 reserved_at_40[0x40];
9270};
9271
9272struct mlx5_ifc_destroy_lag_out_bits {
9273 u8 status[0x8];
9274 u8 reserved_at_8[0x18];
9275
9276 u8 syndrome[0x20];
9277
9278 u8 reserved_at_40[0x40];
9279};
9280
9281struct mlx5_ifc_destroy_lag_in_bits {
9282 u8 opcode[0x10];
9283 u8 reserved_at_10[0x10];
9284
9285 u8 reserved_at_20[0x10];
9286 u8 op_mod[0x10];
9287
9288 u8 reserved_at_40[0x40];
9289};
9290
9291struct mlx5_ifc_create_vport_lag_out_bits {
9292 u8 status[0x8];
9293 u8 reserved_at_8[0x18];
9294
9295 u8 syndrome[0x20];
9296
9297 u8 reserved_at_40[0x40];
9298};
9299
9300struct mlx5_ifc_create_vport_lag_in_bits {
9301 u8 opcode[0x10];
9302 u8 reserved_at_10[0x10];
9303
9304 u8 reserved_at_20[0x10];
9305 u8 op_mod[0x10];
9306
9307 u8 reserved_at_40[0x40];
9308};
9309
9310struct mlx5_ifc_destroy_vport_lag_out_bits {
9311 u8 status[0x8];
9312 u8 reserved_at_8[0x18];
9313
9314 u8 syndrome[0x20];
9315
9316 u8 reserved_at_40[0x40];
9317};
9318
9319struct mlx5_ifc_destroy_vport_lag_in_bits {
9320 u8 opcode[0x10];
9321 u8 reserved_at_10[0x10];
9322
9323 u8 reserved_at_20[0x10];
9324 u8 op_mod[0x10];
9325
9326 u8 reserved_at_40[0x40];
9327};
9328
24da0016
AL		 9329struct mlx5_ifc_alloc_memic_in_bits {
9330 u8 opcode[0x10];
9331 u8 reserved_at_10[0x10];
9332
9333 u8 reserved_at_20[0x10];
9334 u8 op_mod[0x10];
9335
9336 u8 reserved_at_30[0x20];
9337
9338 u8 reserved_at_40[0x18];
9339 u8 log_memic_addr_alignment[0x8];
9340
9341 u8 range_start_addr[0x40];
9342
9343 u8 range_size[0x20];
9344
9345 u8 memic_size[0x20];
9346};
9347
9348struct mlx5_ifc_alloc_memic_out_bits {
9349 u8 status[0x8];
9350 u8 reserved_at_8[0x18];
9351
9352 u8 syndrome[0x20];
9353
9354 u8 memic_start_addr[0x40];
9355};
9356
9357struct mlx5_ifc_dealloc_memic_in_bits {
9358 u8 opcode[0x10];
9359 u8 reserved_at_10[0x10];
9360
9361 u8 reserved_at_20[0x10];
9362 u8 op_mod[0x10];
9363
9364 u8 reserved_at_40[0x40];
9365
9366 u8 memic_start_addr[0x40];
9367
9368 u8 memic_size[0x20];
9369
9370 u8 reserved_at_e0[0x20];
9371};
9372
9373struct mlx5_ifc_dealloc_memic_out_bits {
9374 u8 status[0x8];
9375 u8 reserved_at_8[0x18];
9376
9377 u8 syndrome[0x20];
9378
9379 u8 reserved_at_40[0x40];
9380};
9381
38b7ca92
YH		 9382struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9383 u8 opcode[0x10];
9384 u8 uid[0x10];
9385
9386 u8 reserved_at_20[0x10];
9387 u8 obj_type[0x10];
9388
9389 u8 obj_id[0x20];
9390
9391 u8 reserved_at_60[0x20];
9392};
9393
9394struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9395 u8 status[0x8];
9396 u8 reserved_at_8[0x18];
9397
9398 u8 syndrome[0x20];
9399
9400 u8 obj_id[0x20];
9401
9402 u8 reserved_at_60[0x20];
9403};
9404
9405struct mlx5_ifc_umem_bits {
6e3722ba 9406 u8 reserved_at_0[0x80];
38b7ca92 9407
6e3722ba 9408 u8 reserved_at_80[0x1b];
38b7ca92
YH		 9409 u8 log_page_size[0x5];
9410
9411 u8 page_offset[0x20];
9412
9413 u8 num_of_mtt[0x40];
9414
9415 struct mlx5_ifc_mtt_bits mtt[0];
9416};
9417
9418struct mlx5_ifc_uctx_bits {
9d43faac
YH		 9419 u8 cap[0x20];
9420
6e3722ba 9421 u8 reserved_at_20[0x160];
38b7ca92
YH		 9422};
9423
9424struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 9425 u8 opcode[0x10];
9426 u8 uid[0x10];
9427
9428 u8 reserved_at_20[0x10];
9429 u8 op_mod[0x10];
9430
9431 u8 reserved_at_40[0x40];
9432
9433 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 9434};
9435
9436struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 9437 u8 opcode[0x10];
9438 u8 reserved_at_10[0x10];
9439
9440 u8 reserved_at_20[0x10];
9441 u8 op_mod[0x10];
9442
9443 u8 reserved_at_40[0x40];
9444
9445 struct mlx5_ifc_uctx_bits uctx;
9446};
9447
9448struct mlx5_ifc_destroy_uctx_in_bits {
9449 u8 opcode[0x10];
9450 u8 reserved_at_10[0x10];
9451
9452 u8 reserved_at_20[0x10];
9453 u8 op_mod[0x10];
9454
9455 u8 reserved_at_40[0x10];
9456 u8 uid[0x10];
9457
9458 u8 reserved_at_60[0x20];
38b7ca92
YH		 9459};
9460
eff8ea8f
FD		 9461struct mlx5_ifc_mtrc_string_db_param_bits {
9462 u8 string_db_base_address[0x20];
9463
9464 u8 reserved_at_20[0x8];
9465 u8 string_db_size[0x18];
9466};
9467
9468struct mlx5_ifc_mtrc_cap_bits {
9469 u8 trace_owner[0x1];
9470 u8 trace_to_memory[0x1];
9471 u8 reserved_at_2[0x4];
9472 u8 trc_ver[0x2];
9473 u8 reserved_at_8[0x14];
9474 u8 num_string_db[0x4];
9475
9476 u8 first_string_trace[0x8];
9477 u8 num_string_trace[0x8];
9478 u8 reserved_at_30[0x28];
9479
9480 u8 log_max_trace_buffer_size[0x8];
9481
9482 u8 reserved_at_60[0x20];
9483
9484 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9485
9486 u8 reserved_at_280[0x180];
9487};
9488
9489struct mlx5_ifc_mtrc_conf_bits {
9490 u8 reserved_at_0[0x1c];
9491 u8 trace_mode[0x4];
9492 u8 reserved_at_20[0x18];
9493 u8 log_trace_buffer_size[0x8];
9494 u8 trace_mkey[0x20];
9495 u8 reserved_at_60[0x3a0];
9496};
9497
9498struct mlx5_ifc_mtrc_stdb_bits {
9499 u8 string_db_index[0x4];
9500 u8 reserved_at_4[0x4];
9501 u8 read_size[0x18];
9502 u8 start_offset[0x20];
9503 u8 string_db_data[0];
9504};
9505
9506struct mlx5_ifc_mtrc_ctrl_bits {
9507 u8 trace_status[0x2];
9508 u8 reserved_at_2[0x2];
9509 u8 arm_event[0x1];
9510 u8 reserved_at_5[0xb];
9511 u8 modify_field_select[0x10];
9512 u8 reserved_at_20[0x2b];
9513 u8 current_timestamp52_32[0x15];
9514 u8 current_timestamp31_0[0x20];
9515 u8 reserved_at_80[0x180];
9516};
9517
d29b796a 9518#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)