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net/mlx5: Remove not used MLX5_CAP_BITS_RW_MASK
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
f91e6d89
EBE		 66enum {
67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
59e9e8e4 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
f91e6d89
EBE		 71};
72
38b7ca92 73enum {
2acc7957 74 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 75};
76
9fba2b9b
AL		 77enum {
78 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
79};
80
81enum {
82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
b169e64a 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90fbca59 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
b169e64a
YK		 85};
86
87enum {
88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
8a06a79b 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
1892a3d4 90 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
e7e2519e 91 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
e4075c44
YH		 92 MLX5_OBJ_TYPE_MKEY = 0xff01,
93 MLX5_OBJ_TYPE_QP = 0xff02,
94 MLX5_OBJ_TYPE_PSV = 0xff03,
95 MLX5_OBJ_TYPE_RMP = 0xff04,
96 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
97 MLX5_OBJ_TYPE_RQ = 0xff06,
98 MLX5_OBJ_TYPE_SQ = 0xff07,
99 MLX5_OBJ_TYPE_TIR = 0xff08,
100 MLX5_OBJ_TYPE_TIS = 0xff09,
101 MLX5_OBJ_TYPE_DCT = 0xff0a,
102 MLX5_OBJ_TYPE_XRQ = 0xff0b,
103 MLX5_OBJ_TYPE_RQT = 0xff0e,
104 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
105 MLX5_OBJ_TYPE_CQ = 0xff10,
9fba2b9b
AL		 106};
107
d29b796a
EC		 108enum {
109 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
110 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
111 MLX5_CMD_OP_INIT_HCA = 0x102,
112 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
113 MLX5_CMD_OP_ENABLE_HCA = 0x104,
114 MLX5_CMD_OP_DISABLE_HCA = 0x105,
115 MLX5_CMD_OP_QUERY_PAGES = 0x107,
116 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
117 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 118 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
119 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 120 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
1759d322
PP		 121 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
122 MLX5_CMD_OP_ALLOC_SF = 0x113,
123 MLX5_CMD_OP_DEALLOC_SF = 0x114,
adfdaff3
YH		 124 MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
125 MLX5_CMD_OP_RESUME_VHCA = 0x116,
126 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
127 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
128 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
d29b796a
EC		 129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
63f9c44b 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
d29b796a
EC		 137 MLX5_CMD_OP_CREATE_EQ = 0x301,
138 MLX5_CMD_OP_DESTROY_EQ = 0x302,
139 MLX5_CMD_OP_QUERY_EQ = 0x303,
140 MLX5_CMD_OP_GEN_EQE = 0x304,
141 MLX5_CMD_OP_CREATE_CQ = 0x400,
142 MLX5_CMD_OP_DESTROY_CQ = 0x401,
143 MLX5_CMD_OP_QUERY_CQ = 0x402,
144 MLX5_CMD_OP_MODIFY_CQ = 0x403,
145 MLX5_CMD_OP_CREATE_QP = 0x500,
146 MLX5_CMD_OP_DESTROY_QP = 0x501,
147 MLX5_CMD_OP_RST2INIT_QP = 0x502,
148 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
149 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
150 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
152 MLX5_CMD_OP_2ERR_QP = 0x507,
153 MLX5_CMD_OP_2RST_QP = 0x50a,
154 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
157 MLX5_CMD_OP_CREATE_PSV = 0x600,
158 MLX5_CMD_OP_DESTROY_PSV = 0x601,
159 MLX5_CMD_OP_CREATE_SRQ = 0x700,
160 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
161 MLX5_CMD_OP_QUERY_SRQ = 0x702,
162 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 167 MLX5_CMD_OP_CREATE_DCT = 0x710,
168 MLX5_CMD_OP_DESTROY_DCT = 0x711,
169 MLX5_CMD_OP_DRAIN_DCT = 0x712,
170 MLX5_CMD_OP_QUERY_DCT = 0x713,
171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 172 MLX5_CMD_OP_CREATE_XRQ = 0x717,
173 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
174 MLX5_CMD_OP_QUERY_XRQ = 0x719,
175 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
b1635ee6
YH		 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
cd56f929 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
d29b796a
EC		 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 209 MLX5_CMD_OP_ALLOC_PD = 0x800,
210 MLX5_CMD_OP_DEALLOC_PD = 0x801,
211 MLX5_CMD_OP_ALLOC_UAR = 0x802,
212 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
214 MLX5_CMD_OP_ACCESS_REG = 0x805,
215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
218 MLX5_CMD_OP_MAD_IFC = 0x50d,
219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
221 MLX5_CMD_OP_NOP = 0x80d,
222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 238 MLX5_CMD_OP_CREATE_LAG = 0x840,
239 MLX5_CMD_OP_MODIFY_LAG = 0x841,
240 MLX5_CMD_OP_QUERY_LAG = 0x842,
241 MLX5_CMD_OP_DESTROY_LAG = 0x843,
242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 244 MLX5_CMD_OP_CREATE_TIR = 0x900,
245 MLX5_CMD_OP_MODIFY_TIR = 0x901,
246 MLX5_CMD_OP_DESTROY_TIR = 0x902,
247 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 248 MLX5_CMD_OP_CREATE_SQ = 0x904,
249 MLX5_CMD_OP_MODIFY_SQ = 0x905,
250 MLX5_CMD_OP_DESTROY_SQ = 0x906,
251 MLX5_CMD_OP_QUERY_SQ = 0x907,
252 MLX5_CMD_OP_CREATE_RQ = 0x908,
253 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
256 MLX5_CMD_OP_QUERY_RQ = 0x90b,
257 MLX5_CMD_OP_CREATE_RMP = 0x90c,
258 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
259 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
260 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 261 MLX5_CMD_OP_CREATE_TIS = 0x912,
262 MLX5_CMD_OP_MODIFY_TIS = 0x913,
263 MLX5_CMD_OP_DESTROY_TIS = 0x914,
264 MLX5_CMD_OP_QUERY_TIS = 0x915,
265 MLX5_CMD_OP_CREATE_RQT = 0x916,
266 MLX5_CMD_OP_MODIFY_RQT = 0x917,
267 MLX5_CMD_OP_DESTROY_RQT = 0x918,
268 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
300 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
d32d7c52 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
349125ba
PP		 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
86d56a1a 305 MLX5_CMD_OP_MAX
e281682b
SM		 306};
307
719598c9
YH		 308/* Valid range for general commands that don't work over an object */
309enum {
310 MLX5_CMD_OP_GENERAL_START = 0xb00,
311 MLX5_CMD_OP_GENERAL_END = 0xd00,
312};
313
e281682b
SM		 314struct mlx5_ifc_flow_table_fields_supported_bits {
315 u8 outer_dmac[0x1];
316 u8 outer_smac[0x1];
317 u8 outer_ether_type[0x1];
19cc7524 318 u8 outer_ip_version[0x1];
e281682b
SM		 319 u8 outer_first_prio[0x1];
320 u8 outer_first_cfi[0x1];
321 u8 outer_first_vid[0x1];
a8ade55f 322 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 323 u8 outer_second_prio[0x1];
324 u8 outer_second_cfi[0x1];
325 u8 outer_second_vid[0x1];
b4ff3a36 326 u8 reserved_at_b[0x1];
e281682b
SM		 327 u8 outer_sip[0x1];
328 u8 outer_dip[0x1];
329 u8 outer_frag[0x1];
330 u8 outer_ip_protocol[0x1];
331 u8 outer_ip_ecn[0x1];
332 u8 outer_ip_dscp[0x1];
333 u8 outer_udp_sport[0x1];
334 u8 outer_udp_dport[0x1];
335 u8 outer_tcp_sport[0x1];
336 u8 outer_tcp_dport[0x1];
337 u8 outer_tcp_flags[0x1];
338 u8 outer_gre_protocol[0x1];
339 u8 outer_gre_key[0x1];
340 u8 outer_vxlan_vni[0x1];
75d90e7d
YK		 341 u8 outer_geneve_vni[0x1];
342 u8 outer_geneve_oam[0x1];
343 u8 outer_geneve_protocol_type[0x1];
344 u8 outer_geneve_opt_len[0x1];
8208461d 345 u8 source_vhca_port[0x1];
e281682b
SM		 346 u8 source_eswitch_port[0x1];
347
348 u8 inner_dmac[0x1];
349 u8 inner_smac[0x1];
350 u8 inner_ether_type[0x1];
19cc7524 351 u8 inner_ip_version[0x1];
e281682b
SM		 352 u8 inner_first_prio[0x1];
353 u8 inner_first_cfi[0x1];
354 u8 inner_first_vid[0x1];
b4ff3a36 355 u8 reserved_at_27[0x1];
e281682b
SM		 356 u8 inner_second_prio[0x1];
357 u8 inner_second_cfi[0x1];
358 u8 inner_second_vid[0x1];
b4ff3a36 359 u8 reserved_at_2b[0x1];
e281682b
SM		 360 u8 inner_sip[0x1];
361 u8 inner_dip[0x1];
362 u8 inner_frag[0x1];
363 u8 inner_ip_protocol[0x1];
364 u8 inner_ip_ecn[0x1];
365 u8 inner_ip_dscp[0x1];
366 u8 inner_udp_sport[0x1];
367 u8 inner_udp_dport[0x1];
368 u8 inner_tcp_sport[0x1];
369 u8 inner_tcp_dport[0x1];
370 u8 inner_tcp_flags[0x1];
b4ff3a36 371 u8 reserved_at_37[0x9];
71c6e863 372
b169e64a 373 u8 geneve_tlv_option_0_data[0x1];
f59464e2
YK		 374 u8 geneve_tlv_option_0_exist[0x1];
375 u8 reserved_at_42[0x3];
71c6e863
AL		 376 u8 outer_first_mpls_over_udp[0x4];
377 u8 outer_first_mpls_over_gre[0x4];
378 u8 inner_first_mpls[0x4];
379 u8 outer_first_mpls[0x4];
380 u8 reserved_at_55[0x2];
3346c487 381 u8 outer_esp_spi[0x1];
71c6e863 382 u8 reserved_at_58[0x2];
a550ddfc 383 u8 bth_dst_qp[0x1];
822e114b 384 u8 reserved_at_5b[0x5];
e281682b 385
822e114b
PB		 386 u8 reserved_at_60[0x18];
387 u8 metadata_reg_c_7[0x1];
388 u8 metadata_reg_c_6[0x1];
389 u8 metadata_reg_c_5[0x1];
390 u8 metadata_reg_c_4[0x1];
391 u8 metadata_reg_c_3[0x1];
392 u8 metadata_reg_c_2[0x1];
393 u8 metadata_reg_c_1[0x1];
394 u8 metadata_reg_c_0[0x1];
e281682b
SM		 395};
396
8208461d
AL		 397struct mlx5_ifc_flow_table_fields_supported_2_bits {
398 u8 reserved_at_0[0xe];
399 u8 bth_opcode[0x1];
400 u8 reserved_at_f[0x11];
401
402 u8 reserved_at_20[0x60];
403};
404
e281682b
SM		 405struct mlx5_ifc_flow_table_prop_layout_bits {
406 u8 ft_support[0x1];
9dc0b289
AV		 407 u8 reserved_at_1[0x1];
408 u8 flow_counter[0x1];
26a81453 409 u8 flow_modify_en[0x1];
2cc43b49 410 u8 modify_root[0x1];
34a40e68
MG		 411 u8 identified_miss_table_mode[0x1];
412 u8 flow_table_modify[0x1];
60786f09 413 u8 reformat[0x1];
7adbde20 414 u8 decap[0x1];
0c06897a
OG		 415 u8 reserved_at_9[0x1];
416 u8 pop_vlan[0x1];
417 u8 push_vlan[0x1];
8da6fe2a
JL		 418 u8 reserved_at_c[0x1];
419 u8 pop_vlan_2[0x1];
420 u8 push_vlan_2[0x1];
bea4e1f6 421 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 422 u8 reserved_at_10[0x1];
423 u8 sw_owner[0x1];
bea4e1f6
MB		 424 u8 reformat_l3_tunnel_to_l2[0x1];
425 u8 reformat_l2_to_l3_tunnel[0x1];
426 u8 reformat_and_modify_action[0x1];
822e114b
PB		 427 u8 ignore_flow_level[0x1];
428 u8 reserved_at_16[0x1];
f6f7d6b5 429 u8 table_miss_action_domain[0x1];
c6d4e45d 430 u8 termination_table[0x1];
e0ebd8eb 431 u8 reformat_and_fwd_to_table[0x1];
78fb6122
HN		 432 u8 reserved_at_1a[0x2];
433 u8 ipsec_encrypt[0x1];
434 u8 ipsec_decrypt[0x1];
9d8feb46
AV		 435 u8 sw_owner_v2[0x1];
436 u8 reserved_at_1f[0x1];
78fb6122 437
613f53fe
EC		 438 u8 termination_table_raw_traffic[0x1];
439 u8 reserved_at_21[0x1];
e281682b 440 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 441 u8 log_max_modify_header_context[0x8];
442 u8 max_modify_header_actions[0x8];
e281682b
SM		 443 u8 max_ft_level[0x8];
444
f5d23ee1
JL		 445 u8 reserved_at_40[0x6];
446 u8 execute_aso[0x1];
447 u8 reserved_at_47[0x19];
e281682b 448
67133eaa
YK		 449 u8 reserved_at_60[0x2];
450 u8 reformat_insert[0x1];
451 u8 reformat_remove[0x1];
452 u8 reserver_at_64[0x14];
e281682b
SM		 453 u8 log_max_ft_num[0x8];
454
a14587df
RS		 455 u8 reserved_at_80[0x10];
456 u8 log_max_flow_counter[0x8];
e281682b
SM		 457 u8 log_max_destination[0x8];
458
a14587df 459 u8 reserved_at_a0[0x18];
e281682b
SM		 460 u8 log_max_flow[0x8];
461
b4ff3a36 462 u8 reserved_at_c0[0x40];
e281682b
SM		 463
464 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
465
466 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
467};
468
469struct mlx5_ifc_odp_per_transport_service_cap_bits {
470 u8 send[0x1];
471 u8 receive[0x1];
472 u8 write[0x1];
473 u8 read[0x1];
17d2f88f 474 u8 atomic[0x1];
e281682b 475 u8 srq_receive[0x1];
b4ff3a36 476 u8 reserved_at_6[0x1a];
e281682b
SM		 477};
478
479struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
480 u8 smac_47_16[0x20];
481
482 u8 smac_15_0[0x10];
483 u8 ethertype[0x10];
484
485 u8 dmac_47_16[0x20];
486
487 u8 dmac_15_0[0x10];
488 u8 first_prio[0x3];
489 u8 first_cfi[0x1];
490 u8 first_vid[0xc];
491
492 u8 ip_protocol[0x8];
493 u8 ip_dscp[0x6];
494 u8 ip_ecn[0x2];
10543365
MHY		 495 u8 cvlan_tag[0x1];
496 u8 svlan_tag[0x1];
e281682b 497 u8 frag[0x1];
19cc7524 498 u8 ip_version[0x4];
e281682b
SM		 499 u8 tcp_flags[0x9];
500
501 u8 tcp_sport[0x10];
502 u8 tcp_dport[0x10];
503
5c422bfa
YK		 504 u8 reserved_at_c0[0x10];
505 u8 ipv4_ihl[0x4];
506 u8 reserved_at_c4[0x4];
507
a8ade55f 508 u8 ttl_hoplimit[0x8];
e281682b
SM		 509
510 u8 udp_sport[0x10];
511 u8 udp_dport[0x10];
512
b4d1f032 513 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 514
b4d1f032 515 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 516};
517
5886a96a
OS		 518struct mlx5_ifc_nvgre_key_bits {
519 u8 hi[0x18];
520 u8 lo[0x8];
521};
522
523union mlx5_ifc_gre_key_bits {
524 struct mlx5_ifc_nvgre_key_bits nvgre;
525 u8 key[0x20];
526};
527
e281682b 528struct mlx5_ifc_fte_match_set_misc_bits {
97b5484e 529 u8 gre_c_present[0x1];
d32d7c52 530 u8 reserved_at_1[0x1];
97b5484e
AV		 531 u8 gre_k_present[0x1];
532 u8 gre_s_present[0x1];
533 u8 source_vhca_port[0x4];
7486216b 534 u8 source_sqn[0x18];
e281682b 535
3e99df87 536 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 537 u8 source_port[0x10];
538
539 u8 outer_second_prio[0x3];
540 u8 outer_second_cfi[0x1];
541 u8 outer_second_vid[0xc];
542 u8 inner_second_prio[0x3];
543 u8 inner_second_cfi[0x1];
544 u8 inner_second_vid[0xc];
545
10543365
MHY		 546 u8 outer_second_cvlan_tag[0x1];
547 u8 inner_second_cvlan_tag[0x1];
548 u8 outer_second_svlan_tag[0x1];
549 u8 inner_second_svlan_tag[0x1];
550 u8 reserved_at_64[0xc];
e281682b
SM		 551 u8 gre_protocol[0x10];
552
5886a96a 553 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 554
555 u8 vxlan_vni[0x18];
8208461d 556 u8 bth_opcode[0x8];
e281682b 557
75d90e7d 558 u8 geneve_vni[0x18];
f59464e2
YK		 559 u8 reserved_at_d8[0x6];
560 u8 geneve_tlv_option_0_exist[0x1];
75d90e7d 561 u8 geneve_oam[0x1];
e281682b 562
b4ff3a36 563 u8 reserved_at_e0[0xc];
e281682b
SM		 564 u8 outer_ipv6_flow_label[0x14];
565
b4ff3a36 566 u8 reserved_at_100[0xc];
e281682b
SM		 567 u8 inner_ipv6_flow_label[0x14];
568
75d90e7d
YK		 569 u8 reserved_at_120[0xa];
570 u8 geneve_opt_len[0x6];
571 u8 geneve_protocol_type[0x10];
572
573 u8 reserved_at_140[0x8];
a550ddfc 574 u8 bth_dst_qp[0x18];
3346c487
BP		 575 u8 reserved_at_160[0x20];
576 u8 outer_esp_spi[0x20];
577 u8 reserved_at_1a0[0x60];
e281682b
SM		 578};
579
71c6e863
AL		 580struct mlx5_ifc_fte_match_mpls_bits {
581 u8 mpls_label[0x14];
582 u8 mpls_exp[0x3];
583 u8 mpls_s_bos[0x1];
584 u8 mpls_ttl[0x8];
585};
586
587struct mlx5_ifc_fte_match_set_misc2_bits {
588 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
589
590 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
591
592 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
593
594 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
595
65c0f2c1
JL		 596 u8 metadata_reg_c_7[0x20];
597
598 u8 metadata_reg_c_6[0x20];
599
600 u8 metadata_reg_c_5[0x20];
601
602 u8 metadata_reg_c_4[0x20];
603
604 u8 metadata_reg_c_3[0x20];
605
606 u8 metadata_reg_c_2[0x20];
607
608 u8 metadata_reg_c_1[0x20];
609
610 u8 metadata_reg_c_0[0x20];
71c6e863
AL		 611
612 u8 metadata_reg_a[0x20];
613
356d411c 614 u8 reserved_at_1a0[0x60];
71c6e863
AL		 615};
616
b169e64a 617struct mlx5_ifc_fte_match_set_misc3_bits {
97b5484e
AV		 618 u8 inner_tcp_seq_num[0x20];
619
620 u8 outer_tcp_seq_num[0x20];
621
622 u8 inner_tcp_ack_num[0x20];
623
624 u8 outer_tcp_ack_num[0x20];
625
626 u8 reserved_at_80[0x8];
627 u8 outer_vxlan_gpe_vni[0x18];
628
629 u8 outer_vxlan_gpe_next_protocol[0x8];
630 u8 outer_vxlan_gpe_flags[0x8];
631 u8 reserved_at_b0[0x10];
632
633 u8 icmp_header_data[0x20];
634
635 u8 icmpv6_header_data[0x20];
636
637 u8 icmp_type[0x8];
638 u8 icmp_code[0x8];
639 u8 icmpv6_type[0x8];
640 u8 icmpv6_code[0x8];
641
b169e64a 642 u8 geneve_tlv_option_0_data[0x20];
97b5484e 643
704cfecd
YK		 644 u8 gtpu_teid[0x20];
645
646 u8 gtpu_msg_type[0x8];
647 u8 gtpu_msg_flags[0x8];
648 u8 reserved_at_170[0x10];
649
650 u8 gtpu_dw_2[0x20];
651
652 u8 gtpu_first_ext_dw_0[0x20];
653
654 u8 gtpu_dw_0[0x20];
655
656 u8 reserved_at_1e0[0x20];
b169e64a
YK		 657};
658
7da3ad6c
MS		 659struct mlx5_ifc_fte_match_set_misc4_bits {
660 u8 prog_sample_field_value_0[0x20];
661
662 u8 prog_sample_field_id_0[0x20];
663
664 u8 prog_sample_field_value_1[0x20];
665
666 u8 prog_sample_field_id_1[0x20];
667
668 u8 prog_sample_field_value_2[0x20];
669
670 u8 prog_sample_field_id_2[0x20];
671
672 u8 prog_sample_field_value_3[0x20];
673
674 u8 prog_sample_field_id_3[0x20];
675
676 u8 reserved_at_100[0x100];
677};
678
0f2a6c3b
MS		 679struct mlx5_ifc_fte_match_set_misc5_bits {
680 u8 macsec_tag_0[0x20];
681
682 u8 macsec_tag_1[0x20];
683
684 u8 macsec_tag_2[0x20];
685
686 u8 macsec_tag_3[0x20];
687
688 u8 tunnel_header_0[0x20];
689
690 u8 tunnel_header_1[0x20];
691
692 u8 tunnel_header_2[0x20];
693
694 u8 tunnel_header_3[0x20];
695
696 u8 reserved_at_100[0x100];
697};
698
e281682b
SM		 699struct mlx5_ifc_cmd_pas_bits {
700 u8 pa_h[0x20];
701
702 u8 pa_l[0x14];
b4ff3a36 703 u8 reserved_at_34[0xc];
e281682b
SM		 704};
705
706struct mlx5_ifc_uint64_bits {
707 u8 hi[0x20];
708
709 u8 lo[0x20];
710};
711
712enum {
713 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
714 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
715 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
716 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
717 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
718 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
719 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
720 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
721 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
722 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
723};
724
725struct mlx5_ifc_ads_bits {
726 u8 fl[0x1];
727 u8 free_ar[0x1];
b4ff3a36 728 u8 reserved_at_2[0xe];
e281682b
SM		 729 u8 pkey_index[0x10];
730
b4ff3a36 731 u8 reserved_at_20[0x8];
e281682b
SM		 732 u8 grh[0x1];
733 u8 mlid[0x7];
734 u8 rlid[0x10];
735
736 u8 ack_timeout[0x5];
b4ff3a36 737 u8 reserved_at_45[0x3];
e281682b 738 u8 src_addr_index[0x8];
b4ff3a36 739 u8 reserved_at_50[0x4];
e281682b
SM		 740 u8 stat_rate[0x4];
741 u8 hop_limit[0x8];
742
b4ff3a36 743 u8 reserved_at_60[0x4];
e281682b
SM		 744 u8 tclass[0x8];
745 u8 flow_label[0x14];
746
747 u8 rgid_rip[16][0x8];
748
b4ff3a36 749 u8 reserved_at_100[0x4];
e281682b
SM		 750 u8 f_dscp[0x1];
751 u8 f_ecn[0x1];
b4ff3a36 752 u8 reserved_at_106[0x1];
e281682b
SM		 753 u8 f_eth_prio[0x1];
754 u8 ecn[0x2];
755 u8 dscp[0x6];
756 u8 udp_sport[0x10];
757
758 u8 dei_cfi[0x1];
759 u8 eth_prio[0x3];
760 u8 sl[0x4];
32f69e4b 761 u8 vhca_port_num[0x8];
e281682b
SM		 762 u8 rmac_47_32[0x10];
763
764 u8 rmac_31_0[0x20];
765};
766
767struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 768 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 769 u8 nic_rx_multi_path_tirs_fts[0x1];
770 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
13a7e459
ES		 771 u8 reserved_at_3[0x4];
772 u8 sw_owner_reformat_supported[0x1];
773 u8 reserved_at_8[0x18];
774
bea4e1f6
MB		 775 u8 encap_general_header[0x1];
776 u8 reserved_at_21[0xa];
777 u8 log_max_packet_reformat_context[0x5];
778 u8 reserved_at_30[0x6];
779 u8 max_encap_header_size[0xa];
780 u8 reserved_at_40[0x1c0];
e281682b
SM		 781
782 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
783
d83eb50e 784 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
e281682b
SM		 785
786 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
787
788 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
789
24670b1a 790 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
e281682b
SM		 791
792 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
793
8208461d
AL		 794 u8 reserved_at_e00[0x700];
795
796 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
797
798 u8 reserved_at_1580[0x280];
799
800 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
801
802 u8 reserved_at_1880[0x780];
97b5484e
AV		 803
804 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
805
806 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
807
808 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
809
810 u8 reserved_at_20c0[0x5f40];
e281682b
SM		 811};
812
425a563a
MG		 813struct mlx5_ifc_port_selection_cap_bits {
814 u8 reserved_at_0[0x10];
815 u8 port_select_flow_table[0x1];
816 u8 reserved_at_11[0xf];
817
818 u8 reserved_at_20[0x1e0];
819
820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
821
822 u8 reserved_at_400[0x7c00];
823};
824
65c0f2c1
JL		 825enum {
826 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
827 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
828 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
829 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
830 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
831 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
832 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
833 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
834};
835
495716b1 836struct mlx5_ifc_flow_table_eswitch_cap_bits {
65c0f2c1 837 u8 fdb_to_vport_reg_c_id[0x8];
822e114b
PB		 838 u8 reserved_at_8[0xd];
839 u8 fdb_modify_header_fwd_to_table[0x1];
4ff725e1 840 u8 fdb_ipv4_ttl_modify[0x1];
65c0f2c1
JL		 841 u8 flow_source[0x1];
842 u8 reserved_at_18[0x2];
b9aa0ba1 843 u8 multi_fdb_encap[0x1];
86f5d0f3 844 u8 egress_acl_forward_to_vport[0x1];
663f146f
VP		 845 u8 fdb_multi_path_to_table[0x1];
846 u8 reserved_at_1d[0x3];
847
848 u8 reserved_at_20[0x1e0];
495716b1
SM		 849
850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
851
852 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
853
854 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
855
97b5484e
AV		 856 u8 reserved_at_800[0x1000];
857
858 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
859
860 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
861
862 u8 sw_steering_uplink_icm_address_rx[0x40];
863
864 u8 sw_steering_uplink_icm_address_tx[0x40];
865
866 u8 reserved_at_1900[0x6700];
495716b1
SM		 867};
868
8bb957d2
SK		 869enum {
870 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
871 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
872};
873
d6666753
SM		 874struct mlx5_ifc_e_switch_cap_bits {
875 u8 vport_svlan_strip[0x1];
876 u8 vport_cvlan_strip[0x1];
877 u8 vport_svlan_insert[0x1];
878 u8 vport_cvlan_insert_if_not_exist[0x1];
879 u8 vport_cvlan_insert_overwrite[0x1];
c3e666f1
MB		 880 u8 reserved_at_5[0x2];
881 u8 esw_shared_ingress_acl[0x1];
65c0f2c1 882 u8 esw_uplink_ingress_acl[0x1];
c3e666f1
MB		 883 u8 root_ft_on_other_esw[0x1];
884 u8 reserved_at_a[0xf];
6706a3b9
VP		 885 u8 esw_functions_changed[0x1];
886 u8 reserved_at_1a[0x1];
81cd229c 887 u8 ecpf_vport_exists[0x1];
8bb957d2 888 u8 counter_eswitch_affinity[0x1];
a6d04569 889 u8 merged_eswitch[0x1];
23898c76
NO		 890 u8 nic_vport_node_guid_modify[0x1];
891 u8 nic_vport_port_guid_modify[0x1];
d6666753 892
7adbde20
HHZ		 893 u8 vxlan_encap_decap[0x1];
894 u8 nvgre_encap_decap[0x1];
1b115498
EB		 895 u8 reserved_at_22[0x1];
896 u8 log_max_fdb_encap_uplink[0x5];
897 u8 reserved_at_21[0x3];
60786f09 898 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 899 u8 reserved_2b[0x6];
900 u8 max_encap_header_size[0xa];
901
1759d322
PP		 902 u8 reserved_at_40[0xb];
903 u8 log_max_esw_sf[0x5];
904 u8 esw_sf_base_id[0x10];
905
906 u8 reserved_at_60[0x7a0];
7adbde20 907
d6666753
SM		 908};
909
7486216b
SM		 910struct mlx5_ifc_qos_cap_bits {
911 u8 packet_pacing[0x1];
813f8540 912 u8 esw_scheduling[0x1];
c9497c98
MHY		 913 u8 esw_bw_share[0x1];
914 u8 esw_rate_limit[0x1];
05d3ac97
BW		 915 u8 reserved_at_4[0x1];
916 u8 packet_pacing_burst_bound[0x1];
917 u8 packet_pacing_typical_size[0x1];
214baf22
MM		 918 u8 reserved_at_7[0x1];
919 u8 nic_sq_scheduling[0x1];
920 u8 nic_bw_share[0x1];
921 u8 nic_rate_limit[0x1];
1326034b 922 u8 packet_pacing_uid[0x1];
1ae258f8
DL		 923 u8 log_esw_max_sched_depth[0x4];
924 u8 reserved_at_10[0x10];
813f8540 925
214baf22
MM		 926 u8 reserved_at_20[0xb];
927 u8 log_max_qos_nic_queue_group[0x5];
928 u8 reserved_at_30[0x10];
813f8540 929
7486216b 930 u8 packet_pacing_max_rate[0x20];
813f8540 931
7486216b 932 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 933
934 u8 reserved_at_80[0x10];
7486216b 935 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 936
937 u8 esw_element_type[0x10];
938 u8 esw_tsar_type[0x10];
939
940 u8 reserved_at_c0[0x10];
941 u8 max_qos_para_vport[0x10];
942
943 u8 max_tsar_bw_share[0x20];
944
f5d23ee1
JL		 945 u8 reserved_at_100[0x20];
946
947 u8 reserved_at_120[0x3];
948 u8 log_meter_aso_granularity[0x5];
949 u8 reserved_at_128[0x3];
950 u8 log_meter_aso_max_alloc[0x5];
951 u8 reserved_at_130[0x3];
952 u8 log_max_num_meter_aso[0x5];
953 u8 reserved_at_138[0x8];
954
955 u8 reserved_at_140[0x6c0];
7486216b
SM		 956};
957
2fcb12df 958struct mlx5_ifc_debug_cap_bits {
0b9055a1
MS		 959 u8 core_dump_general[0x1];
960 u8 core_dump_qp[0x1];
609b8272
AL		 961 u8 reserved_at_2[0x7];
962 u8 resource_dump[0x1];
963 u8 reserved_at_a[0x16];
2fcb12df
IK		 964
965 u8 reserved_at_20[0x2];
966 u8 stall_detect[0x1];
967 u8 reserved_at_23[0x1d];
968
969 u8 reserved_at_40[0x7c0];
970};
971
e281682b
SM		 972struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
973 u8 csum_cap[0x1];
974 u8 vlan_cap[0x1];
975 u8 lro_cap[0x1];
976 u8 lro_psh_flag[0x1];
977 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 978 u8 reserved_at_5[0x2];
979 u8 wqe_vlan_insert[0x1];
66189961 980 u8 self_lb_en_modifiable[0x1];
b4ff3a36 981 u8 reserved_at_9[0x2];
e281682b 982 u8 max_lso_cap[0x5];
c226dc22 983 u8 multi_pkt_send_wqe[0x2];
cff92d7c 984 u8 wqe_inline_mode[0x2];
e281682b 985 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 986 u8 reg_umr_sq[0x1];
987 u8 scatter_fcs[0x1];
050da902 988 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 989 u8 tunnel_lso_const_out_ip_id[0x1];
26ab7b38
MM		 990 u8 tunnel_lro_gre[0x1];
991 u8 tunnel_lro_vxlan[0x1];
27299841 992 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 993 u8 tunnel_stateless_vxlan[0x1];
994
547eede0
IT		 995 u8 swp[0x1];
996 u8 swp_csum[0x1];
997 u8 swp_lso[0x1];
db849faa 998 u8 cqe_checksum_full[0x1];
41e684ef
AV		 999 u8 tunnel_stateless_geneve_tx[0x1];
1000 u8 tunnel_stateless_mpls_over_udp[0x1];
1001 u8 tunnel_stateless_mpls_over_gre[0x1];
1002 u8 tunnel_stateless_vxlan_gpe[0x1];
1003 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
caa18547 1004 u8 tunnel_stateless_ip_over_ip[0x1];
2b58f6d9 1005 u8 insert_trailer[0x1];
21adf05d
AL		 1006 u8 reserved_at_2b[0x1];
1007 u8 tunnel_stateless_ip_over_ip_rx[0x1];
1008 u8 tunnel_stateless_ip_over_ip_tx[0x1];
1009 u8 reserved_at_2e[0x2];
22a65aa8
GP		 1010 u8 max_vxlan_udp_ports[0x8];
1011 u8 reserved_at_38[0x6];
4d350f1f
MG		 1012 u8 max_geneve_opt_len[0x1];
1013 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 1014
b4ff3a36 1015 u8 reserved_at_40[0x10];
e281682b
SM		 1016 u8 lro_min_mss_size[0x10];
1017
b4ff3a36 1018 u8 reserved_at_60[0x120];
e281682b
SM		 1019
1020 u8 lro_timer_supported_periods[4][0x20];
1021
b4ff3a36 1022 u8 reserved_at_200[0x600];
e281682b
SM		 1023};
1024
a6a217dd 1025enum {
9a1ac95a
AL		 1026 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1027 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1028 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
a6a217dd
AL		 1029};
1030
e281682b
SM		 1031struct mlx5_ifc_roce_cap_bits {
1032 u8 roce_apm[0x1];
59e9e8e4
MZ		 1033 u8 reserved_at_1[0x3];
1034 u8 sw_r_roce_src_udp_port[0x1];
7304d603
YK		 1035 u8 fl_rc_qp_when_roce_disabled[0x1];
1036 u8 fl_rc_qp_when_roce_enabled[0x1];
1037 u8 reserved_at_7[0x17];
a6a217dd 1038 u8 qp_ts_format[0x2];
e281682b 1039
b4ff3a36 1040 u8 reserved_at_20[0x60];
e281682b 1041
b4ff3a36 1042 u8 reserved_at_80[0xc];
e281682b 1043 u8 l3_type[0x4];
b4ff3a36 1044 u8 reserved_at_90[0x8];
e281682b
SM		 1045 u8 roce_version[0x8];
1046
b4ff3a36 1047 u8 reserved_at_a0[0x10];
e281682b
SM		 1048 u8 r_roce_dest_udp_port[0x10];
1049
1050 u8 r_roce_max_src_udp_port[0x10];
1051 u8 r_roce_min_src_udp_port[0x10];
1052
b4ff3a36 1053 u8 reserved_at_e0[0x10];
e281682b
SM		 1054 u8 roce_address_table_size[0x10];
1055
b4ff3a36 1056 u8 reserved_at_100[0x700];
e281682b
SM		 1057};
1058
97b5484e
AV		 1059struct mlx5_ifc_sync_steering_in_bits {
1060 u8 opcode[0x10];
1061 u8 uid[0x10];
1062
1063 u8 reserved_at_20[0x10];
1064 u8 op_mod[0x10];
1065
1066 u8 reserved_at_40[0xc0];
1067};
1068
1069struct mlx5_ifc_sync_steering_out_bits {
1070 u8 status[0x8];
1071 u8 reserved_at_8[0x18];
1072
1073 u8 syndrome[0x20];
1074
1075 u8 reserved_at_40[0x40];
1076};
1077
e72bd817
AL		 1078struct mlx5_ifc_device_mem_cap_bits {
1079 u8 memic[0x1];
1080 u8 reserved_at_1[0x1f];
1081
1082 u8 reserved_at_20[0xb];
1083 u8 log_min_memic_alloc_size[0x5];
1084 u8 reserved_at_30[0x8];
1085 u8 log_max_memic_addr_alignment[0x8];
1086
1087 u8 memic_bar_start_addr[0x40];
1088
1089 u8 memic_bar_size[0x20];
1090
1091 u8 max_memic_size[0x20];
1092
9fba2b9b
AL		 1093 u8 steering_sw_icm_start_address[0x40];
1094
1095 u8 reserved_at_100[0x8];
1096 u8 log_header_modify_sw_icm_size[0x8];
1097 u8 reserved_at_110[0x2];
1098 u8 log_sw_icm_alloc_granularity[0x6];
1099 u8 log_steering_sw_icm_size[0x8];
1100
795e10b4
YK		 1101 u8 reserved_at_120[0x18];
1102 u8 log_header_modify_pattern_sw_icm_size[0x8];
9fba2b9b
AL		 1103
1104 u8 header_modify_sw_icm_start_address[0x40];
1105
795e10b4
YK		 1106 u8 reserved_at_180[0x40];
1107
1108 u8 header_modify_pattern_sw_icm_start_address[0x40];
63f9c44b
MG		 1109
1110 u8 memic_operations[0x20];
1111
1112 u8 reserved_at_220[0x5e0];
e72bd817
AL		 1113};
1114
b9a7ba55
YH		 1115struct mlx5_ifc_device_event_cap_bits {
1116 u8 user_affiliated_events[4][0x40];
1117
1118 u8 user_unaffiliated_events[4][0x40];
1119};
1120
8a06a79b
EC		 1121struct mlx5_ifc_virtio_emulation_cap_bits {
1122 u8 desc_tunnel_offload_type[0x1];
1123 u8 eth_frame_offload_type[0x1];
1124 u8 virtio_version_1_0[0x1];
1125 u8 device_features_bits_mask[0xd];
1126 u8 event_mode[0x8];
1127 u8 virtio_queue_type[0x8];
90fbca59 1128
8a06a79b
EC		 1129 u8 max_tunnel_desc[0x10];
1130 u8 reserved_at_30[0x3];
90fbca59
YH		 1131 u8 log_doorbell_stride[0x5];
1132 u8 reserved_at_38[0x3];
1133 u8 log_doorbell_bar_size[0x5];
1134
1135 u8 doorbell_bar_offset[0x40];
1136
8a06a79b
EC		 1137 u8 max_emulated_devices[0x8];
1138 u8 max_num_virtio_queues[0x18];
1139
1140 u8 reserved_at_a0[0x60];
1141
1142 u8 umem_1_buffer_param_a[0x20];
1143
1144 u8 umem_1_buffer_param_b[0x20];
1145
1146 u8 umem_2_buffer_param_a[0x20];
1147
1148 u8 umem_2_buffer_param_b[0x20];
1149
1150 u8 umem_3_buffer_param_a[0x20];
1151
1152 u8 umem_3_buffer_param_b[0x20];
1153
1154 u8 reserved_at_1c0[0x640];
90fbca59
YH		 1155};
1156
e281682b
SM		 1157enum {
1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1164 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1165 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1166 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1167};
1168
1169enum {
1170 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1171 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1172 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1173 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1174 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1175 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1176 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1177 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1178 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1179};
1180
1181struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 1182 u8 reserved_at_0[0x40];
e281682b 1183
bd10838a 1184 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 1185 u8 reserved_at_42[0x4];
bd10838a 1186 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 1187
b4ff3a36 1188 u8 reserved_at_47[0x19];
e281682b 1189
b4ff3a36 1190 u8 reserved_at_60[0x20];
e281682b 1191
b4ff3a36 1192 u8 reserved_at_80[0x10];
f91e6d89 1193 u8 atomic_operations[0x10];
e281682b 1194
b4ff3a36 1195 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 1196 u8 atomic_size_qp[0x10];
1197
b4ff3a36 1198 u8 reserved_at_c0[0x10];
e281682b
SM		 1199 u8 atomic_size_dc[0x10];
1200
b4ff3a36 1201 u8 reserved_at_e0[0x720];
e281682b
SM		 1202};
1203
1204struct mlx5_ifc_odp_cap_bits {
b4ff3a36 1205 u8 reserved_at_0[0x40];
e281682b
SM		 1206
1207 u8 sig[0x1];
b4ff3a36 1208 u8 reserved_at_41[0x1f];
e281682b 1209
b4ff3a36 1210 u8 reserved_at_60[0x20];
e281682b
SM		 1211
1212 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1213
1214 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1215
1216 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1217
dda7a817
MS		 1218 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1219
00679b63
MG		 1220 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1221
1222 u8 reserved_at_120[0x6E0];
e281682b
SM		 1223};
1224
3f0393a5
SG		 1225struct mlx5_ifc_calc_op {
1226 u8 reserved_at_0[0x10];
1227 u8 reserved_at_10[0x9];
1228 u8 op_swap_endianness[0x1];
1229 u8 op_min[0x1];
1230 u8 op_xor[0x1];
1231 u8 op_or[0x1];
1232 u8 op_and[0x1];
1233 u8 op_max[0x1];
1234 u8 op_add[0x1];
1235};
1236
1237struct mlx5_ifc_vector_calc_cap_bits {
1238 u8 calc_matrix[0x1];
1239 u8 reserved_at_1[0x1f];
1240 u8 reserved_at_20[0x8];
1241 u8 max_vec_count[0x8];
1242 u8 reserved_at_30[0xd];
1243 u8 max_chunk_size[0x3];
1244 struct mlx5_ifc_calc_op calc0;
1245 struct mlx5_ifc_calc_op calc1;
1246 struct mlx5_ifc_calc_op calc2;
1247 struct mlx5_ifc_calc_op calc3;
1248
c74d90c1 1249 u8 reserved_at_c0[0x720];
3f0393a5
SG		 1250};
1251
a12ff35e
EBE		 1252struct mlx5_ifc_tls_cap_bits {
1253 u8 tls_1_2_aes_gcm_128[0x1];
1254 u8 tls_1_3_aes_gcm_128[0x1];
1255 u8 tls_1_2_aes_gcm_256[0x1];
1256 u8 tls_1_3_aes_gcm_256[0x1];
1257 u8 reserved_at_4[0x1c];
1258
1259 u8 reserved_at_20[0x7e0];
1260};
1261
2b58f6d9
RS		 1262struct mlx5_ifc_ipsec_cap_bits {
1263 u8 ipsec_full_offload[0x1];
1264 u8 ipsec_crypto_offload[0x1];
1265 u8 ipsec_esn[0x1];
1266 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1267 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1268 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1269 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1270 u8 reserved_at_7[0x4];
1271 u8 log_max_ipsec_offload[0x5];
1272 u8 reserved_at_10[0x10];
1273
1274 u8 min_log_ipsec_full_replay_window[0x8];
1275 u8 max_log_ipsec_full_replay_window[0x8];
1276 u8 reserved_at_30[0x7d0];
1277};
1278
e281682b
SM		 1279enum {
1280 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1281 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 1282 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 1283 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 1284};
1285
1286enum {
1287 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1288 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1289};
1290
1291enum {
1292 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1293 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1294 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1295 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1296 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1297};
1298
1299enum {
1300 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1301 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1302 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1303 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1304 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1305 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1306};
1307
1308enum {
1309 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1310 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1311};
1312
1313enum {
1314 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1315 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1316 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1317};
1318
1319enum {
1320 MLX5_CAP_PORT_TYPE_IB = 0x0,
1321 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 1322};
1323
1410a90a
MG		 1324enum {
1325 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1326 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1327 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1328};
1329
97b5484e 1330enum {
a18fab48 1331 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
704cfecd 1332 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
c3fb0e28 1333 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
97b5484e
AV		 1334 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1335 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1336 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
704cfecd
YK		 1337 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1338 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1339 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1340 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1341 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1342 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
97b5484e
AV		 1343};
1344
9d43faac
YH		 1345enum {
1346 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 1347 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 1348};
1349
8536a6bf
GT		 1350#define MLX5_FC_BULK_SIZE_FACTOR 128
1351
1352enum mlx5_fc_bulk_alloc_bitmask {
1353 MLX5_FC_BULK_128 = (1 << 0),
1354 MLX5_FC_BULK_256 = (1 << 1),
1355 MLX5_FC_BULK_512 = (1 << 2),
1356 MLX5_FC_BULK_1024 = (1 << 3),
1357 MLX5_FC_BULK_2048 = (1 << 4),
1358 MLX5_FC_BULK_4096 = (1 << 5),
1359 MLX5_FC_BULK_8192 = (1 << 6),
1360 MLX5_FC_BULK_16384 = (1 << 7),
1361};
1362
1363#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1364
216214c6
YK		 1365#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1366
d421e466
YK		 1367enum {
1368 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1369 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
6862c787 1370 MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
d421e466
YK		 1371};
1372
b775516b 1373struct mlx5_ifc_cmd_hca_cap_bits {
959af556
YH		 1374 u8 reserved_at_0[0x1f];
1375 u8 vhca_resource_manager[0x1];
349125ba 1376
67133eaa 1377 u8 hca_cap_2[0x1];
94db3317 1378 u8 create_lag_when_not_master_up[0x1];
4b2c5fa9 1379 u8 dtor[0x1];
349125ba
PP		 1380 u8 event_on_vhca_state_teardown_request[0x1];
1381 u8 event_on_vhca_state_in_use[0x1];
1382 u8 event_on_vhca_state_active[0x1];
1383 u8 event_on_vhca_state_allocated[0x1];
1384 u8 event_on_vhca_state_invalid[0x1];
1385 u8 reserved_at_28[0x8];
32f69e4b
DJ		 1386 u8 vhca_id[0x10];
1387
1388 u8 reserved_at_40[0x40];
b775516b
EC		 1389
1390 u8 log_max_srq_sz[0x8];
1391 u8 log_max_qp_sz[0x8];
b9a7ba55 1392 u8 event_cap[0x1];
aeacb52a
YK		 1393 u8 reserved_at_91[0x2];
1394 u8 isolate_vl_tc_new[0x1];
1395 u8 reserved_at_94[0x4];
316793fb
EB		 1396 u8 prio_tag_required[0x1];
1397 u8 reserved_at_99[0x2];
b775516b
EC		 1398 u8 log_max_qp[0x5];
1399
6b646a7e
LR		 1400 u8 reserved_at_a0[0x3];
1401 u8 ece_support[0x1];
838b00a2
PB		 1402 u8 reserved_at_a4[0x5];
1403 u8 reg_c_preserve[0x1];
1404 u8 reserved_at_aa[0x1];
e281682b 1405 u8 log_max_srq[0x5];
9c9be85f
AL		 1406 u8 reserved_at_b0[0x1];
1407 u8 uplink_follow[0x1];
59d2ae1d 1408 u8 ts_cqe_to_dest_cqn[0x1];
7025329d
BBI		 1409 u8 reserved_at_b3[0x7];
1410 u8 shampo[0x1];
1411 u8 reserved_at_bb[0x5];
b775516b 1412
7d47433c 1413 u8 max_sgl_for_optimized_performance[0x8];
b775516b 1414 u8 log_max_cq_sz[0x8];
042dd05b
ML		 1415 u8 relaxed_ordering_write_umr[0x1];
1416 u8 relaxed_ordering_read_umr[0x1];
1417 u8 reserved_at_d2[0x7];
8a06a79b
EC		 1418 u8 virtio_net_device_emualtion_manager[0x1];
1419 u8 virtio_blk_device_emualtion_manager[0x1];
b775516b
EC		 1420 u8 log_max_cq[0x5];
1421
1422 u8 log_max_eq_sz[0x8];
a880a6dd
MG		 1423 u8 relaxed_ordering_write[0x1];
1424 u8 relaxed_ordering_read[0x1];
b775516b 1425 u8 log_max_mkey[0x6];
b183ee27
LR		 1426 u8 reserved_at_f0[0x8];
1427 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 1428 u8 reserved_at_f9[0x2];
1429 u8 fast_teardown[0x1];
b775516b
EC		 1430 u8 log_max_eq[0x4];
1431
1432 u8 max_indirection[0x8];
bcda1aca 1433 u8 fixed_buffer_size[0x1];
b775516b 1434 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 1435 u8 force_teardown[0x1];
1436 u8 reserved_at_111[0x1];
b775516b 1437 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 1438 u8 umr_extended_translation_offset[0x1];
1439 u8 null_mkey[0x1];
b775516b
EC		 1440 u8 log_max_klm_list_size[0x6];
1441
b4ff3a36 1442 u8 reserved_at_120[0xa];
b775516b 1443 u8 log_max_ra_req_dc[0x6];
3e94e61b
SM		 1444 u8 reserved_at_130[0x9];
1445 u8 vnic_env_cq_overrun[0x1];
b775516b
EC		 1446 u8 log_max_ra_res_dc[0x6];
1447
d2cb8dda 1448 u8 reserved_at_140[0x5];
0e1533bb 1449 u8 release_all_pages[0x1];
d2cb8dda 1450 u8 must_not_use[0x1];
0e1533bb 1451 u8 reserved_at_147[0x2];
8fd5b75d 1452 u8 roce_accl[0x1];
b775516b 1453 u8 log_max_ra_req_qp[0x6];
b4ff3a36 1454 u8 reserved_at_150[0xa];
b775516b
EC		 1455 u8 log_max_ra_res_qp[0x6];
1456
f32f5bd2 1457 u8 end_pad[0x1];
b775516b
EC		 1458 u8 cc_query_allowed[0x1];
1459 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 1460 u8 start_pad[0x1];
1461 u8 cache_line_128byte[0x1];
f8efee08
MZ		 1462 u8 reserved_at_165[0x4];
1463 u8 rts2rts_qp_counters_set_id[0x1];
30b10e89
MS		 1464 u8 reserved_at_16a[0x2];
1465 u8 vnic_env_int_rq_oob[0x1];
948d3f90
AL		 1466 u8 sbcam_reg[0x1];
1467 u8 reserved_at_16e[0x1];
c02762eb 1468 u8 qcam_reg[0x1];
e281682b 1469 u8 gid_table_size[0x10];
b775516b 1470
e281682b
SM		 1471 u8 out_of_seq_cnt[0x1];
1472 u8 vport_counters[0x1];
7486216b 1473 u8 retransmission_q_counters[0x1];
2fcb12df 1474 u8 debug[0x1];
83b502a1 1475 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1476 u8 rq_delay_drop[0x1];
b775516b
EC		 1477 u8 max_qp_cnt[0xa];
1478 u8 pkey_table_size[0x10];
1479
e281682b
SM		 1480 u8 vport_group_manager[0x1];
1481 u8 vhca_group_manager[0x1];
1482 u8 ib_virt[0x1];
1483 u8 eth_virt[0x1];
61c5b5c9 1484 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1485 u8 ets[0x1];
1486 u8 nic_flow_table[0x1];
0efc8562 1487 u8 eswitch_manager[0x1];
e72bd817 1488 u8 device_memory[0x1];
cfdcbcea
GP		 1489 u8 mcam_reg[0x1];
1490 u8 pcam_reg[0x1];
b775516b 1491 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1492 u8 port_module_event[0x1];
58dcb60a 1493 u8 enhanced_error_q_counters[0x1];
7d5e1423 1494 u8 ports_check[0x1];
7b13558f 1495 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1496 u8 disable_link_up[0x1];
1497 u8 beacon_led[0x1];
e281682b 1498 u8 port_type[0x2];
b775516b
EC		 1499 u8 num_ports[0x8];
1500
f9a1ef72
EE		 1501 u8 reserved_at_1c0[0x1];
1502 u8 pps[0x1];
1503 u8 pps_modify[0x1];
b775516b 1504 u8 log_max_msg[0x5];
e1c9c62b 1505 u8 reserved_at_1c8[0x4];
4f3961ee 1506 u8 max_tc[0x4];
1865ea9a 1507 u8 temp_warn_event[0x1];
7486216b 1508 u8 dcbx[0x1];
246ac981
MG		 1509 u8 general_notification_event[0x1];
1510 u8 reserved_at_1d3[0x2];
e29341fb 1511 u8 fpga[0x1];
928cfe87
TT		 1512 u8 rol_s[0x1];
1513 u8 rol_g[0x1];
e1c9c62b 1514 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1515 u8 wol_s[0x1];
1516 u8 wol_g[0x1];
1517 u8 wol_a[0x1];
1518 u8 wol_b[0x1];
1519 u8 wol_m[0x1];
1520 u8 wol_u[0x1];
1521 u8 wol_p[0x1];
b775516b
EC		 1522
1523 u8 stat_rate_support[0x10];
3df01077
MS		 1524 u8 reserved_at_1f0[0x1];
1525 u8 pci_sync_for_fw_update_event[0x1];
cfc1a89e
MG		 1526 u8 reserved_at_1f2[0x6];
1527 u8 init2_lag_tx_port_affinity[0x1];
1528 u8 reserved_at_1fa[0x3];
e281682b 1529 u8 cqe_version[0x4];
b775516b 1530
e281682b 1531 u8 compact_address_vector[0x1];
7d5e1423 1532 u8 striding_rq[0x1];
500a3d0d
ES		 1533 u8 reserved_at_202[0x1];
1534 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1535 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1536 u8 reserved_at_205[0x1];
1537 u8 repeated_block_disabled[0x1];
1538 u8 umr_modify_entity_size_disabled[0x1];
1539 u8 umr_modify_atomic_disabled[0x1];
1540 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1541 u8 umr_fence[0x2];
94a04d1d
YC		 1542 u8 dc_req_scat_data_cqe[0x1];
1543 u8 reserved_at_20d[0x2];
e281682b 1544 u8 drain_sigerr[0x1];
b775516b
EC		 1545 u8 cmdif_checksum[0x2];
1546 u8 sigerr_cqe[0x1];
e1c9c62b 1547 u8 reserved_at_213[0x1];
b775516b
EC		 1548 u8 wq_signature[0x1];
1549 u8 sctr_data_cqe[0x1];
e1c9c62b 1550 u8 reserved_at_216[0x1];
b775516b
EC		 1551 u8 sho[0x1];
1552 u8 tph[0x1];
1553 u8 rf[0x1];
e281682b 1554 u8 dct[0x1];
7486216b 1555 u8 qos[0x1];
e281682b 1556 u8 eth_net_offloads[0x1];
b775516b
EC		 1557 u8 roce[0x1];
1558 u8 atomic[0x1];
e1c9c62b 1559 u8 reserved_at_21f[0x1];
b775516b
EC		 1560
1561 u8 cq_oi[0x1];
1562 u8 cq_resize[0x1];
1563 u8 cq_moderation[0x1];
e1c9c62b 1564 u8 reserved_at_223[0x3];
e281682b 1565 u8 cq_eq_remap[0x1];
b775516b
EC		 1566 u8 pg[0x1];
1567 u8 block_lb_mc[0x1];
e1c9c62b 1568 u8 reserved_at_229[0x1];
e281682b 1569 u8 scqe_break_moderation[0x1];
7d5e1423 1570 u8 cq_period_start_from_cqe[0x1];
b775516b 1571 u8 cd[0x1];
e1c9c62b 1572 u8 reserved_at_22d[0x1];
b775516b 1573 u8 apm[0x1];
3f0393a5 1574 u8 vector_calc[0x1];
7d5e1423 1575 u8 umr_ptr_rlky[0x1];
d2370e0a 1576 u8 imaicl[0x1];
3fd3c80a
DG		 1577 u8 qp_packet_based[0x1];
1578 u8 reserved_at_233[0x3];
b775516b
EC		 1579 u8 qkv[0x1];
1580 u8 pkv[0x1];
b11a4f9c
HE		 1581 u8 set_deth_sqpn[0x1];
1582 u8 reserved_at_239[0x3];
b775516b
EC		 1583 u8 xrc[0x1];
1584 u8 ud[0x1];
1585 u8 uc[0x1];
1586 u8 rc[0x1];
1587
a6d51b68
EC		 1588 u8 uar_4k[0x1];
1589 u8 reserved_at_241[0x9];
b775516b 1590 u8 uar_sz[0x6];
425a563a
MG		 1591 u8 port_selection_cap[0x1];
1592 u8 reserved_at_248[0x1];
e13cd45d
EC		 1593 u8 umem_uid_0[0x1];
1594 u8 reserved_at_250[0x5];
b775516b
EC		 1595 u8 log_pg_sz[0x8];
1596
1597 u8 bf[0x1];
0dbc6fe0 1598 u8 driver_version[0x1];
e281682b 1599 u8 pad_tx_eth_packet[0x1];
4dca6509
MG		 1600 u8 reserved_at_263[0x3];
1601 u8 mkey_by_name[0x1];
1602 u8 reserved_at_267[0x4];
1603
b775516b 1604 u8 log_bf_reg_size[0x5];
84df61eb 1605
7c4b1ab9
MZ		 1606 u8 reserved_at_270[0x6];
1607 u8 lag_dct[0x2];
1eba383f 1608 u8 lag_tx_port_affinity[0x1];
c3e666f1
MB		 1609 u8 lag_native_fdb_selection[0x1];
1610 u8 reserved_at_27a[0x1];
84df61eb
AH		 1611 u8 lag_master[0x1];
1612 u8 num_lag_ports[0x4];
b775516b 1613
e1c9c62b 1614 u8 reserved_at_280[0x10];
b775516b
EC		 1615 u8 max_wqe_sz_sq[0x10];
1616
e1c9c62b 1617 u8 reserved_at_2a0[0x10];
b775516b
EC		 1618 u8 max_wqe_sz_rq[0x10];
1619
a8ffcc74 1620 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1621 u8 max_wqe_sz_sq_dc[0x10];
1622
e1c9c62b 1623 u8 reserved_at_2e0[0x7];
b775516b
EC		 1624 u8 max_qp_mcg[0x19];
1625
8536a6bf
GT		 1626 u8 reserved_at_300[0x10];
1627 u8 flow_counter_bulk_alloc[0x8];
b775516b
EC		 1628 u8 log_max_mcg[0x8];
1629
e1c9c62b 1630 u8 reserved_at_320[0x3];
e281682b 1631 u8 log_max_transport_domain[0x5];
e1c9c62b 1632 u8 reserved_at_328[0x3];
b775516b 1633 u8 log_max_pd[0x5];
e1c9c62b 1634 u8 reserved_at_330[0xb];
b775516b
EC		 1635 u8 log_max_xrcd[0x5];
1636
5c298143 1637 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1638 u8 receive_discard_vport_down[0x1];
1639 u8 transmit_discard_vport_down[0x1];
3e94e61b
SM		 1640 u8 eq_overrun_count[0x1];
1641 u8 reserved_at_344[0x1];
1642 u8 invalid_command_count[0x1];
1643 u8 quota_exceeded_count[0x1];
1644 u8 reserved_at_347[0x1];
a351a1b0 1645 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1646 u8 max_flow_counter_15_0[0x10];
a351a1b0 1647
b775516b 1648
e1c9c62b 1649 u8 reserved_at_360[0x3];
b775516b 1650 u8 log_max_rq[0x5];
e1c9c62b 1651 u8 reserved_at_368[0x3];
b775516b 1652 u8 log_max_sq[0x5];
e1c9c62b 1653 u8 reserved_at_370[0x3];
b775516b 1654 u8 log_max_tir[0x5];
e1c9c62b 1655 u8 reserved_at_378[0x3];
b775516b
EC		 1656 u8 log_max_tis[0x5];
1657
e281682b 1658 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1659 u8 reserved_at_381[0x2];
e281682b 1660 u8 log_max_rmp[0x5];
e1c9c62b 1661 u8 reserved_at_388[0x3];
e281682b 1662 u8 log_max_rqt[0x5];
e1c9c62b 1663 u8 reserved_at_390[0x3];
e281682b 1664 u8 log_max_rqt_size[0x5];
e1c9c62b 1665 u8 reserved_at_398[0x3];
b775516b
EC		 1666 u8 log_max_tis_per_sq[0x5];
1667
619a8f2a 1668 u8 ext_stride_num_range[0x1];
fbfa97b4 1669 u8 roce_rw_supported[0x1];
685b1afd 1670 u8 log_max_current_uc_list_wr_supported[0x1];
e281682b 1671 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1672 u8 reserved_at_3a8[0x3];
e281682b 1673 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1674 u8 reserved_at_3b0[0x3];
e281682b 1675 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1676 u8 reserved_at_3b8[0x3];
e281682b
SM		 1677 u8 log_min_stride_sz_sq[0x5];
1678
40817cdb
OG		 1679 u8 hairpin[0x1];
1680 u8 reserved_at_3c1[0x2];
1681 u8 log_max_hairpin_queues[0x5];
1682 u8 reserved_at_3c8[0x3];
1683 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1684 u8 reserved_at_3d0[0x3];
1685 u8 log_max_hairpin_num_packets[0x5];
1686 u8 reserved_at_3d8[0x3];
e281682b
SM		 1687 u8 log_max_wq_sz[0x5];
1688
54f0a411 1689 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1690 u8 disable_local_lb_uc[0x1];
1691 u8 disable_local_lb_mc[0x1];
40817cdb 1692 u8 log_min_hairpin_wq_data_sz[0x5];
349125ba
PP		 1693 u8 reserved_at_3e8[0x2];
1694 u8 vhca_state[0x1];
54f0a411 1695 u8 log_max_vlan_list[0x5];
e1c9c62b 1696 u8 reserved_at_3f0[0x3];
54f0a411 1697 u8 log_max_current_mc_list[0x5];
e1c9c62b 1698 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1699 u8 log_max_current_uc_list[0x5];
1700
38b7ca92
YH		 1701 u8 general_obj_types[0x40];
1702
a6a217dd
AL		 1703 u8 sq_ts_format[0x2];
1704 u8 rq_ts_format[0x2];
d421e466
YK		 1705 u8 steering_format_version[0x4];
1706 u8 create_qp_start_hint[0x18];
342ac844 1707
61c00cca 1708 u8 reserved_at_460[0x3];
6e3722ba 1709 u8 log_max_uctx[0x5];
2b58f6d9
RS		 1710 u8 reserved_at_468[0x2];
1711 u8 ipsec_offload[0x1];
6e3722ba 1712 u8 log_max_umem[0x5];
342ac844 1713 u8 max_num_eqs[0x10];
54f0a411 1714
61c00cca
TT		 1715 u8 reserved_at_480[0x1];
1716 u8 tls_tx[0x1];
ee5cdf7a 1717 u8 tls_rx[0x1];
e281682b 1718 u8 log_max_l2_table[0x5];
e1c9c62b 1719 u8 reserved_at_488[0x8];
b775516b
EC		 1720 u8 log_uar_page_sz[0x10];
1721
e1c9c62b 1722 u8 reserved_at_4a0[0x20];
048ccca8 1723 u8 device_frequency_mhz[0x20];
b0844444 1724 u8 device_frequency_khz[0x20];
e1c9c62b 1725
a6d51b68
EC		 1726 u8 reserved_at_500[0x20];
1727 u8 num_of_uars_per_page[0x20];
e1c9c62b 1728
e818e255 1729 u8 flex_parser_protocols[0x20];
e1c9c62b 1730
b169e64a
YK		 1731 u8 max_geneve_tlv_options[0x8];
1732 u8 reserved_at_568[0x3];
1733 u8 max_geneve_tlv_option_data_len[0x5];
1734 u8 reserved_at_570[0x10];
e1c9c62b 1735
96cd2dd6
LN		 1736 u8 reserved_at_580[0xb];
1737 u8 log_max_dci_stream_channels[0x5];
1738 u8 reserved_at_590[0x3];
1739 u8 log_max_dci_errored_streams[0x5];
1740 u8 reserved_at_598[0x8];
1741
1742 u8 reserved_at_5a0[0x13];
a12ff35e
EBE		 1743 u8 log_max_dek[0x5];
1744 u8 reserved_at_5b8[0x4];
ab741b2e 1745 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1746 u8 cqe_128_always[0x1];
1747 u8 cqe_compression_128[0x1];
7d5e1423 1748 u8 cqe_compression[0x1];
b775516b 1749
7d5e1423
SM		 1750 u8 cqe_compression_timeout[0x10];
1751 u8 cqe_compression_max_num[0x10];
b775516b 1752
704cfecd
YK		 1753 u8 reserved_at_5e0[0x8];
1754 u8 flex_parser_id_gtpu_dw_0[0x4];
1755 u8 reserved_at_5ec[0x4];
7486216b
SM		 1756 u8 tag_matching[0x1];
1757 u8 rndv_offload_rc[0x1];
1758 u8 rndv_offload_dc[0x1];
1759 u8 log_tag_matching_list_sz[0x5];
7b13558f 1760 u8 reserved_at_5f8[0x3];
7486216b
SM		 1761 u8 log_max_xrq[0x5];
1762
32f69e4b
DJ		 1763 u8 affiliate_nic_vport_criteria[0x8];
1764 u8 native_port_num[0x8];
1765 u8 num_vhca_ports[0x8];
704cfecd
YK		 1766 u8 flex_parser_id_gtpu_teid[0x4];
1767 u8 reserved_at_61c[0x2];
32f69e4b 1768 u8 sw_owner_id[0x1];
9d43faac
YH		 1769 u8 reserved_at_61f[0x1];
1770
fd4572b3
ED		 1771 u8 max_num_of_monitor_counters[0x10];
1772 u8 num_ppcnt_monitor_counters[0x10];
1773
349125ba 1774 u8 max_num_sf[0x10];
fd4572b3
ED		 1775 u8 num_q_monitor_counters[0x10];
1776
1759d322
PP		 1777 u8 reserved_at_660[0x20];
1778
1779 u8 sf[0x1];
1780 u8 sf_set_partition[0x1];
1781 u8 reserved_at_682[0x1];
1782 u8 log_max_sf[0x5];
7232c132 1783 u8 apu[0x1];
adfdaff3
YH		 1784 u8 reserved_at_689[0x4];
1785 u8 migration[0x1];
1786 u8 reserved_at_68e[0x2];
1759d322
PP		 1787 u8 log_min_sf_size[0x8];
1788 u8 max_num_sf_partitions[0x8];
9d43faac
YH		 1789
1790 u8 uctx_cap[0x20];
1791
b169e64a
YK		 1792 u8 reserved_at_6c0[0x4];
1793 u8 flex_parser_id_geneve_tlv_option_0[0x4];
97b5484e
AV		 1794 u8 flex_parser_id_icmp_dw1[0x4];
1795 u8 flex_parser_id_icmp_dw0[0x4];
1796 u8 flex_parser_id_icmpv6_dw1[0x4];
1797 u8 flex_parser_id_icmpv6_dw0[0x4];
1798 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1799 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1800
e7e2519e 1801 u8 max_num_match_definer[0x10];
1759d322
PP		 1802 u8 sf_base_id[0x10];
1803
704cfecd
YK		 1804 u8 flex_parser_id_gtpu_dw_2[0x4];
1805 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
0b989c1e
LR		 1806 u8 num_total_dynamic_vf_msix[0x18];
1807 u8 reserved_at_720[0x14];
1808 u8 dynamic_msix_table_size[0xc];
1809 u8 reserved_at_740[0xc];
1810 u8 min_dynamic_vf_msix_table_size[0x4];
1811 u8 reserved_at_750[0x4];
1812 u8 max_dynamic_vf_msix_table_size[0xc];
1813
1814 u8 reserved_at_760[0x20];
1dd7382b 1815 u8 vhca_tunnel_commands[0x40];
e7e2519e 1816 u8 match_definer_format_supported[0x40];
b775516b
EC		 1817};
1818
67133eaa
YK		 1819struct mlx5_ifc_cmd_hca_cap_2_bits {
1820 u8 reserved_at_0[0xa0];
1821
1822 u8 max_reformat_insert_size[0x8];
1823 u8 max_reformat_insert_offset[0x8];
1824 u8 max_reformat_remove_size[0x8];
1825 u8 max_reformat_remove_offset[0x8];
1826
1827 u8 reserved_at_c0[0x740];
1828};
1829
d639af62
MB		 1830enum mlx5_ifc_flow_destination_type {
1831 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1832 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1833 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
1834 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1835 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
e281682b 1836};
b775516b 1837
f6f7d6b5
MG		 1838enum mlx5_flow_table_miss_action {
1839 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1840 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1841 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1842};
1843
e281682b
SM		 1844struct mlx5_ifc_dest_format_struct_bits {
1845 u8 destination_type[0x8];
1846 u8 destination_id[0x18];
1b115498 1847
b17f7fc1 1848 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1849 u8 packet_reformat[0x1];
1850 u8 reserved_at_22[0xe];
b17f7fc1 1851 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1852};
1853
9dc0b289 1854struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1855 u8 flow_counter_id[0x20];
9dc0b289
AV		 1856
1857 u8 reserved_at_20[0x20];
1858};
1859
1b115498
EB		 1860struct mlx5_ifc_extended_dest_format_bits {
1861 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1862
1863 u8 packet_reformat_id[0x20];
1864
1865 u8 reserved_at_60[0x20];
1866};
1867
9dc0b289 1868union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
6dfef396 1869 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
9dc0b289 1870 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
9dc0b289
AV		 1871};
1872
e281682b
SM		 1873struct mlx5_ifc_fte_match_param_bits {
1874 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1875
1876 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1877
1878 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1879
71c6e863
AL		 1880 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1881
b169e64a
YK		 1882 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1883
7da3ad6c
MS		 1884 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1885
0f2a6c3b
MS		 1886 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1887
1888 u8 reserved_at_e00[0x200];
b775516b
EC		 1889};
1890
e281682b
SM		 1891enum {
1892 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1893 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1894 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1895 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1896 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1897};
b775516b 1898
e281682b
SM		 1899struct mlx5_ifc_rx_hash_field_select_bits {
1900 u8 l3_prot_type[0x1];
1901 u8 l4_prot_type[0x1];
1902 u8 selected_fields[0x1e];
1903};
b775516b 1904
e281682b
SM		 1905enum {
1906 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1907 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1908};
1909
e281682b
SM		 1910enum {
1911 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1912 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1913};
1914
1915struct mlx5_ifc_wq_bits {
1916 u8 wq_type[0x4];
1917 u8 wq_signature[0x1];
1918 u8 end_padding_mode[0x2];
1919 u8 cd_slave[0x1];
b4ff3a36 1920 u8 reserved_at_8[0x18];
b775516b 1921
e281682b
SM		 1922 u8 hds_skip_first_sge[0x1];
1923 u8 log2_hds_buf_size[0x3];
b4ff3a36 1924 u8 reserved_at_24[0x7];
e281682b
SM		 1925 u8 page_offset[0x5];
1926 u8 lwm[0x10];
b775516b 1927
b4ff3a36 1928 u8 reserved_at_40[0x8];
e281682b
SM		 1929 u8 pd[0x18];
1930
b4ff3a36 1931 u8 reserved_at_60[0x8];
e281682b
SM		 1932 u8 uar_page[0x18];
1933
1934 u8 dbr_addr[0x40];
1935
1936 u8 hw_counter[0x20];
1937
1938 u8 sw_counter[0x20];
1939
b4ff3a36 1940 u8 reserved_at_100[0xc];
e281682b 1941 u8 log_wq_stride[0x4];
b4ff3a36 1942 u8 reserved_at_110[0x3];
e281682b 1943 u8 log_wq_pg_sz[0x5];
b4ff3a36 1944 u8 reserved_at_118[0x3];
e281682b
SM		 1945 u8 log_wq_sz[0x5];
1946
bd371975
LR		 1947 u8 dbr_umem_valid[0x1];
1948 u8 wq_umem_valid[0x1];
1949 u8 reserved_at_122[0x1];
4d533e0f
OG		 1950 u8 log_hairpin_num_packets[0x5];
1951 u8 reserved_at_128[0x3];
40817cdb 1952 u8 log_hairpin_data_sz[0x5];
40817cdb 1953
619a8f2a
TT		 1954 u8 reserved_at_130[0x4];
1955 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1956 u8 two_byte_shift_en[0x1];
1957 u8 reserved_at_139[0x4];
1958 u8 log_wqe_stride_size[0x3];
1959
7025329d
BBI		 1960 u8 reserved_at_140[0x80];
1961
1962 u8 headers_mkey[0x20];
1963
1964 u8 shampo_enable[0x1];
1965 u8 reserved_at_1e1[0x4];
1966 u8 log_reservation_size[0x3];
1967 u8 reserved_at_1e8[0x5];
1968 u8 log_max_num_of_packets_per_reservation[0x3];
1969 u8 reserved_at_1f0[0x6];
1970 u8 log_headers_entry_size[0x2];
1971 u8 reserved_at_1f8[0x4];
1972 u8 log_headers_buffer_entry_num[0x4];
1973
1974 u8 reserved_at_200[0x400];
b775516b 1975
b6ca09cb 1976 struct mlx5_ifc_cmd_pas_bits pas[];
b775516b
EC		 1977};
1978
e281682b 1979struct mlx5_ifc_rq_num_bits {
b4ff3a36 1980 u8 reserved_at_0[0x8];
e281682b
SM		 1981 u8 rq_num[0x18];
1982};
b775516b 1983
e281682b 1984struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1985 u8 reserved_at_0[0x10];
e281682b 1986 u8 mac_addr_47_32[0x10];
b775516b 1987
e281682b
SM		 1988 u8 mac_addr_31_0[0x20];
1989};
1990
c0046cf7 1991struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1992 u8 reserved_at_0[0x14];
c0046cf7
SM		 1993 u8 vlan[0x0c];
1994
b4ff3a36 1995 u8 reserved_at_20[0x20];
c0046cf7
SM		 1996};
1997
e281682b 1998struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1999 u8 reserved_at_0[0xa0];
e281682b
SM		 2000
2001 u8 min_time_between_cnps[0x20];
2002
b4ff3a36 2003 u8 reserved_at_c0[0x12];
e281682b 2004 u8 cnp_dscp[0x6];
4a2da0b8
PP		 2005 u8 reserved_at_d8[0x4];
2006 u8 cnp_prio_mode[0x1];
e281682b
SM		 2007 u8 cnp_802p_prio[0x3];
2008
b4ff3a36 2009 u8 reserved_at_e0[0x720];
e281682b
SM		 2010};
2011
2012struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 2013 u8 reserved_at_0[0x60];
e281682b 2014
b4ff3a36 2015 u8 reserved_at_60[0x4];
e281682b 2016 u8 clamp_tgt_rate[0x1];
b4ff3a36 2017 u8 reserved_at_65[0x3];
e281682b 2018 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 2019 u8 reserved_at_69[0x17];
e281682b 2020
b4ff3a36 2021 u8 reserved_at_80[0x20];
e281682b
SM		 2022
2023 u8 rpg_time_reset[0x20];
2024
2025 u8 rpg_byte_reset[0x20];
2026
2027 u8 rpg_threshold[0x20];
2028
2029 u8 rpg_max_rate[0x20];
2030
2031 u8 rpg_ai_rate[0x20];
2032
2033 u8 rpg_hai_rate[0x20];
2034
2035 u8 rpg_gd[0x20];
2036
2037 u8 rpg_min_dec_fac[0x20];
2038
2039 u8 rpg_min_rate[0x20];
2040
b4ff3a36 2041 u8 reserved_at_1c0[0xe0];
e281682b
SM		 2042
2043 u8 rate_to_set_on_first_cnp[0x20];
2044
2045 u8 dce_tcp_g[0x20];
2046
2047 u8 dce_tcp_rtt[0x20];
2048
2049 u8 rate_reduce_monitor_period[0x20];
2050
b4ff3a36 2051 u8 reserved_at_320[0x20];
e281682b
SM		 2052
2053 u8 initial_alpha_value[0x20];
2054
b4ff3a36 2055 u8 reserved_at_360[0x4a0];
e281682b
SM		 2056};
2057
2058struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 2059 u8 reserved_at_0[0x80];
e281682b
SM		 2060
2061 u8 rppp_max_rps[0x20];
2062
2063 u8 rpg_time_reset[0x20];
2064
2065 u8 rpg_byte_reset[0x20];
2066
2067 u8 rpg_threshold[0x20];
2068
2069 u8 rpg_max_rate[0x20];
2070
2071 u8 rpg_ai_rate[0x20];
2072
2073 u8 rpg_hai_rate[0x20];
2074
2075 u8 rpg_gd[0x20];
2076
2077 u8 rpg_min_dec_fac[0x20];
2078
2079 u8 rpg_min_rate[0x20];
2080
b4ff3a36 2081 u8 reserved_at_1c0[0x640];
e281682b
SM		 2082};
2083
2084enum {
2085 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2086 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2087 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2088};
2089
2090struct mlx5_ifc_resize_field_select_bits {
2091 u8 resize_field_select[0x20];
2092};
2093
609b8272
AL		 2094struct mlx5_ifc_resource_dump_bits {
2095 u8 more_dump[0x1];
2096 u8 inline_dump[0x1];
2097 u8 reserved_at_2[0xa];
2098 u8 seq_num[0x4];
2099 u8 segment_type[0x10];
2100
2101 u8 reserved_at_20[0x10];
2102 u8 vhca_id[0x10];
2103
2104 u8 index1[0x20];
2105
2106 u8 index2[0x20];
2107
2108 u8 num_of_obj1[0x10];
2109 u8 num_of_obj2[0x10];
2110
2111 u8 reserved_at_a0[0x20];
2112
2113 u8 device_opaque[0x40];
2114
2115 u8 mkey[0x20];
2116
2117 u8 size[0x20];
2118
2119 u8 address[0x40];
2120
2121 u8 inline_data[52][0x20];
2122};
2123
2124struct mlx5_ifc_resource_dump_menu_record_bits {
2125 u8 reserved_at_0[0x4];
2126 u8 num_of_obj2_supports_active[0x1];
2127 u8 num_of_obj2_supports_all[0x1];
2128 u8 must_have_num_of_obj2[0x1];
2129 u8 support_num_of_obj2[0x1];
2130 u8 num_of_obj1_supports_active[0x1];
2131 u8 num_of_obj1_supports_all[0x1];
2132 u8 must_have_num_of_obj1[0x1];
2133 u8 support_num_of_obj1[0x1];
2134 u8 must_have_index2[0x1];
2135 u8 support_index2[0x1];
2136 u8 must_have_index1[0x1];
2137 u8 support_index1[0x1];
2138 u8 segment_type[0x10];
2139
2140 u8 segment_name[4][0x20];
2141
2142 u8 index1_name[4][0x20];
2143
2144 u8 index2_name[4][0x20];
2145};
2146
2147struct mlx5_ifc_resource_dump_segment_header_bits {
2148 u8 length_dw[0x10];
2149 u8 segment_type[0x10];
2150};
2151
2152struct mlx5_ifc_resource_dump_command_segment_bits {
2153 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2154
2155 u8 segment_called[0x10];
2156 u8 vhca_id[0x10];
2157
2158 u8 index1[0x20];
2159
2160 u8 index2[0x20];
2161
2162 u8 num_of_obj1[0x10];
2163 u8 num_of_obj2[0x10];
2164};
2165
2166struct mlx5_ifc_resource_dump_error_segment_bits {
2167 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2168
2169 u8 reserved_at_20[0x10];
2170 u8 syndrome_id[0x10];
2171
2172 u8 reserved_at_40[0x40];
2173
2174 u8 error[8][0x20];
2175};
2176
2177struct mlx5_ifc_resource_dump_info_segment_bits {
2178 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2179
2180 u8 reserved_at_20[0x18];
2181 u8 dump_version[0x8];
2182
2183 u8 hw_version[0x20];
2184
2185 u8 fw_version[0x20];
2186};
2187
2188struct mlx5_ifc_resource_dump_menu_segment_bits {
2189 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2190
2191 u8 reserved_at_20[0x10];
2192 u8 num_of_records[0x10];
2193
b6ca09cb 2194 struct mlx5_ifc_resource_dump_menu_record_bits record[];
609b8272
AL		 2195};
2196
2197struct mlx5_ifc_resource_dump_resource_segment_bits {
2198 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2199
2200 u8 reserved_at_20[0x20];
2201
2202 u8 index1[0x20];
2203
2204 u8 index2[0x20];
2205
b6ca09cb 2206 u8 payload[][0x20];
609b8272
AL		 2207};
2208
2209struct mlx5_ifc_resource_dump_terminate_segment_bits {
2210 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2211};
2212
2213struct mlx5_ifc_menu_resource_dump_response_bits {
2214 struct mlx5_ifc_resource_dump_info_segment_bits info;
2215 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2216 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2217 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2218};
2219
e281682b
SM		 2220enum {
2221 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2222 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2223 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2224 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2225};
2226
2227struct mlx5_ifc_modify_field_select_bits {
2228 u8 modify_field_select[0x20];
2229};
2230
2231struct mlx5_ifc_field_select_r_roce_np_bits {
2232 u8 field_select_r_roce_np[0x20];
2233};
2234
2235struct mlx5_ifc_field_select_r_roce_rp_bits {
2236 u8 field_select_r_roce_rp[0x20];
2237};
2238
2239enum {
2240 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2241 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2242 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2243 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2244 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2245 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2246 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2247 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2248 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2249 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2250};
2251
2252struct mlx5_ifc_field_select_802_1qau_rp_bits {
2253 u8 field_select_8021qaurp[0x20];
2254};
2255
2256struct mlx5_ifc_phys_layer_cntrs_bits {
2257 u8 time_since_last_clear_high[0x20];
2258
2259 u8 time_since_last_clear_low[0x20];
2260
2261 u8 symbol_errors_high[0x20];
2262
2263 u8 symbol_errors_low[0x20];
2264
2265 u8 sync_headers_errors_high[0x20];
2266
2267 u8 sync_headers_errors_low[0x20];
2268
2269 u8 edpl_bip_errors_lane0_high[0x20];
2270
2271 u8 edpl_bip_errors_lane0_low[0x20];
2272
2273 u8 edpl_bip_errors_lane1_high[0x20];
2274
2275 u8 edpl_bip_errors_lane1_low[0x20];
2276
2277 u8 edpl_bip_errors_lane2_high[0x20];
2278
2279 u8 edpl_bip_errors_lane2_low[0x20];
2280
2281 u8 edpl_bip_errors_lane3_high[0x20];
2282
2283 u8 edpl_bip_errors_lane3_low[0x20];
2284
2285 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2286
2287 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2288
2289 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2290
2291 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2292
2293 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2294
2295 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2296
2297 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2298
2299 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2300
2301 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2302
2303 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2304
2305 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2306
2307 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2308
2309 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2310
2311 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2312
2313 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2314
2315 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2316
2317 u8 rs_fec_corrected_blocks_high[0x20];
2318
2319 u8 rs_fec_corrected_blocks_low[0x20];
2320
2321 u8 rs_fec_uncorrectable_blocks_high[0x20];
2322
2323 u8 rs_fec_uncorrectable_blocks_low[0x20];
2324
2325 u8 rs_fec_no_errors_blocks_high[0x20];
2326
2327 u8 rs_fec_no_errors_blocks_low[0x20];
2328
2329 u8 rs_fec_single_error_blocks_high[0x20];
2330
2331 u8 rs_fec_single_error_blocks_low[0x20];
2332
2333 u8 rs_fec_corrected_symbols_total_high[0x20];
2334
2335 u8 rs_fec_corrected_symbols_total_low[0x20];
2336
2337 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2338
2339 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2340
2341 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2342
2343 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2344
2345 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2346
2347 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2348
2349 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2350
2351 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2352
2353 u8 link_down_events[0x20];
2354
2355 u8 successful_recovery_events[0x20];
2356
b4ff3a36 2357 u8 reserved_at_640[0x180];
e281682b
SM		 2358};
2359
d8dc0508
GP		 2360struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2361 u8 time_since_last_clear_high[0x20];
2362
2363 u8 time_since_last_clear_low[0x20];
2364
2365 u8 phy_received_bits_high[0x20];
2366
2367 u8 phy_received_bits_low[0x20];
2368
2369 u8 phy_symbol_errors_high[0x20];
2370
2371 u8 phy_symbol_errors_low[0x20];
2372
2373 u8 phy_corrected_bits_high[0x20];
2374
2375 u8 phy_corrected_bits_low[0x20];
2376
2377 u8 phy_corrected_bits_lane0_high[0x20];
2378
2379 u8 phy_corrected_bits_lane0_low[0x20];
2380
2381 u8 phy_corrected_bits_lane1_high[0x20];
2382
2383 u8 phy_corrected_bits_lane1_low[0x20];
2384
2385 u8 phy_corrected_bits_lane2_high[0x20];
2386
2387 u8 phy_corrected_bits_lane2_low[0x20];
2388
2389 u8 phy_corrected_bits_lane3_high[0x20];
2390
2391 u8 phy_corrected_bits_lane3_low[0x20];
2392
2393 u8 reserved_at_200[0x5c0];
2394};
2395
1c64bf6f
MY		 2396struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2397 u8 symbol_error_counter[0x10];
2398
2399 u8 link_error_recovery_counter[0x8];
2400
2401 u8 link_downed_counter[0x8];
2402
2403 u8 port_rcv_errors[0x10];
2404
2405 u8 port_rcv_remote_physical_errors[0x10];
2406
2407 u8 port_rcv_switch_relay_errors[0x10];
2408
2409 u8 port_xmit_discards[0x10];
2410
2411 u8 port_xmit_constraint_errors[0x8];
2412
2413 u8 port_rcv_constraint_errors[0x8];
2414
2415 u8 reserved_at_70[0x8];
2416
2417 u8 link_overrun_errors[0x8];
2418
2419 u8 reserved_at_80[0x10];
2420
2421 u8 vl_15_dropped[0x10];
2422
133bea04
TW		 2423 u8 reserved_at_a0[0x80];
2424
2425 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 2426};
2427
948d3f90 2428struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
e281682b
SM		 2429 u8 transmit_queue_high[0x20];
2430
2431 u8 transmit_queue_low[0x20];
2432
948d3f90
AL		 2433 u8 no_buffer_discard_uc_high[0x20];
2434
2435 u8 no_buffer_discard_uc_low[0x20];
2436
2437 u8 reserved_at_80[0x740];
2438};
2439
2440struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2441 u8 wred_discard_high[0x20];
2442
2443 u8 wred_discard_low[0x20];
2444
2445 u8 ecn_marked_tc_high[0x20];
2446
2447 u8 ecn_marked_tc_low[0x20];
2448
2449 u8 reserved_at_80[0x740];
e281682b
SM		 2450};
2451
2452struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2453 u8 rx_octets_high[0x20];
2454
2455 u8 rx_octets_low[0x20];
2456
b4ff3a36 2457 u8 reserved_at_40[0xc0];
e281682b
SM		 2458
2459 u8 rx_frames_high[0x20];
2460
2461 u8 rx_frames_low[0x20];
2462
2463 u8 tx_octets_high[0x20];
2464
2465 u8 tx_octets_low[0x20];
2466
b4ff3a36 2467 u8 reserved_at_180[0xc0];
e281682b
SM		 2468
2469 u8 tx_frames_high[0x20];
2470
2471 u8 tx_frames_low[0x20];
2472
2473 u8 rx_pause_high[0x20];
2474
2475 u8 rx_pause_low[0x20];
2476
2477 u8 rx_pause_duration_high[0x20];
2478
2479 u8 rx_pause_duration_low[0x20];
2480
2481 u8 tx_pause_high[0x20];
2482
2483 u8 tx_pause_low[0x20];
2484
2485 u8 tx_pause_duration_high[0x20];
2486
2487 u8 tx_pause_duration_low[0x20];
2488
2489 u8 rx_pause_transition_high[0x20];
2490
2491 u8 rx_pause_transition_low[0x20];
2492
827a8cb2
AL		 2493 u8 rx_discards_high[0x20];
2494
2495 u8 rx_discards_low[0x20];
2fcb12df
IK		 2496
2497 u8 device_stall_minor_watermark_cnt_high[0x20];
2498
2499 u8 device_stall_minor_watermark_cnt_low[0x20];
2500
2501 u8 device_stall_critical_watermark_cnt_high[0x20];
2502
2503 u8 device_stall_critical_watermark_cnt_low[0x20];
2504
2505 u8 reserved_at_480[0x340];
e281682b
SM		 2506};
2507
2508struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2509 u8 port_transmit_wait_high[0x20];
2510
2511 u8 port_transmit_wait_low[0x20];
2512
2dba0797
GP		 2513 u8 reserved_at_40[0x100];
2514
2515 u8 rx_buffer_almost_full_high[0x20];
2516
2517 u8 rx_buffer_almost_full_low[0x20];
2518
2519 u8 rx_buffer_full_high[0x20];
2520
2521 u8 rx_buffer_full_low[0x20];
2522
0af5107c
TB		 2523 u8 rx_icrc_encapsulated_high[0x20];
2524
2525 u8 rx_icrc_encapsulated_low[0x20];
2526
2527 u8 reserved_at_200[0x5c0];
e281682b
SM		 2528};
2529
2530struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2531 u8 dot3stats_alignment_errors_high[0x20];
2532
2533 u8 dot3stats_alignment_errors_low[0x20];
2534
2535 u8 dot3stats_fcs_errors_high[0x20];
2536
2537 u8 dot3stats_fcs_errors_low[0x20];
2538
2539 u8 dot3stats_single_collision_frames_high[0x20];
2540
2541 u8 dot3stats_single_collision_frames_low[0x20];
2542
2543 u8 dot3stats_multiple_collision_frames_high[0x20];
2544
2545 u8 dot3stats_multiple_collision_frames_low[0x20];
2546
2547 u8 dot3stats_sqe_test_errors_high[0x20];
2548
2549 u8 dot3stats_sqe_test_errors_low[0x20];
2550
2551 u8 dot3stats_deferred_transmissions_high[0x20];
2552
2553 u8 dot3stats_deferred_transmissions_low[0x20];
2554
2555 u8 dot3stats_late_collisions_high[0x20];
2556
2557 u8 dot3stats_late_collisions_low[0x20];
2558
2559 u8 dot3stats_excessive_collisions_high[0x20];
2560
2561 u8 dot3stats_excessive_collisions_low[0x20];
2562
2563 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2564
2565 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2566
2567 u8 dot3stats_carrier_sense_errors_high[0x20];
2568
2569 u8 dot3stats_carrier_sense_errors_low[0x20];
2570
2571 u8 dot3stats_frame_too_longs_high[0x20];
2572
2573 u8 dot3stats_frame_too_longs_low[0x20];
2574
2575 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2576
2577 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2578
2579 u8 dot3stats_symbol_errors_high[0x20];
2580
2581 u8 dot3stats_symbol_errors_low[0x20];
2582
2583 u8 dot3control_in_unknown_opcodes_high[0x20];
2584
2585 u8 dot3control_in_unknown_opcodes_low[0x20];
2586
2587 u8 dot3in_pause_frames_high[0x20];
2588
2589 u8 dot3in_pause_frames_low[0x20];
2590
2591 u8 dot3out_pause_frames_high[0x20];
2592
2593 u8 dot3out_pause_frames_low[0x20];
2594
b4ff3a36 2595 u8 reserved_at_400[0x3c0];
e281682b
SM		 2596};
2597
2598struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2599 u8 ether_stats_drop_events_high[0x20];
2600
2601 u8 ether_stats_drop_events_low[0x20];
2602
2603 u8 ether_stats_octets_high[0x20];
2604
2605 u8 ether_stats_octets_low[0x20];
2606
2607 u8 ether_stats_pkts_high[0x20];
2608
2609 u8 ether_stats_pkts_low[0x20];
2610
2611 u8 ether_stats_broadcast_pkts_high[0x20];
2612
2613 u8 ether_stats_broadcast_pkts_low[0x20];
2614
2615 u8 ether_stats_multicast_pkts_high[0x20];
2616
2617 u8 ether_stats_multicast_pkts_low[0x20];
2618
2619 u8 ether_stats_crc_align_errors_high[0x20];
2620
2621 u8 ether_stats_crc_align_errors_low[0x20];
2622
2623 u8 ether_stats_undersize_pkts_high[0x20];
2624
2625 u8 ether_stats_undersize_pkts_low[0x20];
2626
2627 u8 ether_stats_oversize_pkts_high[0x20];
2628
2629 u8 ether_stats_oversize_pkts_low[0x20];
2630
2631 u8 ether_stats_fragments_high[0x20];
2632
2633 u8 ether_stats_fragments_low[0x20];
2634
2635 u8 ether_stats_jabbers_high[0x20];
2636
2637 u8 ether_stats_jabbers_low[0x20];
2638
2639 u8 ether_stats_collisions_high[0x20];
2640
2641 u8 ether_stats_collisions_low[0x20];
2642
2643 u8 ether_stats_pkts64octets_high[0x20];
2644
2645 u8 ether_stats_pkts64octets_low[0x20];
2646
2647 u8 ether_stats_pkts65to127octets_high[0x20];
2648
2649 u8 ether_stats_pkts65to127octets_low[0x20];
2650
2651 u8 ether_stats_pkts128to255octets_high[0x20];
2652
2653 u8 ether_stats_pkts128to255octets_low[0x20];
2654
2655 u8 ether_stats_pkts256to511octets_high[0x20];
2656
2657 u8 ether_stats_pkts256to511octets_low[0x20];
2658
2659 u8 ether_stats_pkts512to1023octets_high[0x20];
2660
2661 u8 ether_stats_pkts512to1023octets_low[0x20];
2662
2663 u8 ether_stats_pkts1024to1518octets_high[0x20];
2664
2665 u8 ether_stats_pkts1024to1518octets_low[0x20];
2666
2667 u8 ether_stats_pkts1519to2047octets_high[0x20];
2668
2669 u8 ether_stats_pkts1519to2047octets_low[0x20];
2670
2671 u8 ether_stats_pkts2048to4095octets_high[0x20];
2672
2673 u8 ether_stats_pkts2048to4095octets_low[0x20];
2674
2675 u8 ether_stats_pkts4096to8191octets_high[0x20];
2676
2677 u8 ether_stats_pkts4096to8191octets_low[0x20];
2678
2679 u8 ether_stats_pkts8192to10239octets_high[0x20];
2680
2681 u8 ether_stats_pkts8192to10239octets_low[0x20];
2682
b4ff3a36 2683 u8 reserved_at_540[0x280];
e281682b
SM		 2684};
2685
2686struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2687 u8 if_in_octets_high[0x20];
2688
2689 u8 if_in_octets_low[0x20];
2690
2691 u8 if_in_ucast_pkts_high[0x20];
2692
2693 u8 if_in_ucast_pkts_low[0x20];
2694
2695 u8 if_in_discards_high[0x20];
2696
2697 u8 if_in_discards_low[0x20];
2698
2699 u8 if_in_errors_high[0x20];
2700
2701 u8 if_in_errors_low[0x20];
2702
2703 u8 if_in_unknown_protos_high[0x20];
2704
2705 u8 if_in_unknown_protos_low[0x20];
2706
2707 u8 if_out_octets_high[0x20];
2708
2709 u8 if_out_octets_low[0x20];
2710
2711 u8 if_out_ucast_pkts_high[0x20];
2712
2713 u8 if_out_ucast_pkts_low[0x20];
2714
2715 u8 if_out_discards_high[0x20];
2716
2717 u8 if_out_discards_low[0x20];
2718
2719 u8 if_out_errors_high[0x20];
2720
2721 u8 if_out_errors_low[0x20];
2722
2723 u8 if_in_multicast_pkts_high[0x20];
2724
2725 u8 if_in_multicast_pkts_low[0x20];
2726
2727 u8 if_in_broadcast_pkts_high[0x20];
2728
2729 u8 if_in_broadcast_pkts_low[0x20];
2730
2731 u8 if_out_multicast_pkts_high[0x20];
2732
2733 u8 if_out_multicast_pkts_low[0x20];
2734
2735 u8 if_out_broadcast_pkts_high[0x20];
2736
2737 u8 if_out_broadcast_pkts_low[0x20];
2738
b4ff3a36 2739 u8 reserved_at_340[0x480];
e281682b
SM		 2740};
2741
2742struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2743 u8 a_frames_transmitted_ok_high[0x20];
2744
2745 u8 a_frames_transmitted_ok_low[0x20];
2746
2747 u8 a_frames_received_ok_high[0x20];
2748
2749 u8 a_frames_received_ok_low[0x20];
2750
2751 u8 a_frame_check_sequence_errors_high[0x20];
2752
2753 u8 a_frame_check_sequence_errors_low[0x20];
2754
2755 u8 a_alignment_errors_high[0x20];
2756
2757 u8 a_alignment_errors_low[0x20];
2758
2759 u8 a_octets_transmitted_ok_high[0x20];
2760
2761 u8 a_octets_transmitted_ok_low[0x20];
2762
2763 u8 a_octets_received_ok_high[0x20];
2764
2765 u8 a_octets_received_ok_low[0x20];
2766
2767 u8 a_multicast_frames_xmitted_ok_high[0x20];
2768
2769 u8 a_multicast_frames_xmitted_ok_low[0x20];
2770
2771 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2772
2773 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2774
2775 u8 a_multicast_frames_received_ok_high[0x20];
2776
2777 u8 a_multicast_frames_received_ok_low[0x20];
2778
2779 u8 a_broadcast_frames_received_ok_high[0x20];
2780
2781 u8 a_broadcast_frames_received_ok_low[0x20];
2782
2783 u8 a_in_range_length_errors_high[0x20];
2784
2785 u8 a_in_range_length_errors_low[0x20];
2786
2787 u8 a_out_of_range_length_field_high[0x20];
2788
2789 u8 a_out_of_range_length_field_low[0x20];
2790
2791 u8 a_frame_too_long_errors_high[0x20];
2792
2793 u8 a_frame_too_long_errors_low[0x20];
2794
2795 u8 a_symbol_error_during_carrier_high[0x20];
2796
2797 u8 a_symbol_error_during_carrier_low[0x20];
2798
2799 u8 a_mac_control_frames_transmitted_high[0x20];
2800
2801 u8 a_mac_control_frames_transmitted_low[0x20];
2802
2803 u8 a_mac_control_frames_received_high[0x20];
2804
2805 u8 a_mac_control_frames_received_low[0x20];
2806
2807 u8 a_unsupported_opcodes_received_high[0x20];
2808
2809 u8 a_unsupported_opcodes_received_low[0x20];
2810
2811 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2812
2813 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2814
2815 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2816
2817 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2818
b4ff3a36 2819 u8 reserved_at_4c0[0x300];
e281682b
SM		 2820};
2821
8ed1a630
GP		 2822struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2823 u8 life_time_counter_high[0x20];
2824
2825 u8 life_time_counter_low[0x20];
2826
2827 u8 rx_errors[0x20];
2828
2829 u8 tx_errors[0x20];
2830
2831 u8 l0_to_recovery_eieos[0x20];
2832
2833 u8 l0_to_recovery_ts[0x20];
2834
2835 u8 l0_to_recovery_framing[0x20];
2836
2837 u8 l0_to_recovery_retrain[0x20];
2838
2839 u8 crc_error_dllp[0x20];
2840
2841 u8 crc_error_tlp[0x20];
2842
efae7f78
EBE		 2843 u8 tx_overflow_buffer_pkt_high[0x20];
2844
2845 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2846
2847 u8 outbound_stalled_reads[0x20];
2848
2849 u8 outbound_stalled_writes[0x20];
2850
2851 u8 outbound_stalled_reads_events[0x20];
2852
2853 u8 outbound_stalled_writes_events[0x20];
2854
2855 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2856};
2857
e281682b
SM		 2858struct mlx5_ifc_cmd_inter_comp_event_bits {
2859 u8 command_completion_vector[0x20];
2860
b4ff3a36 2861 u8 reserved_at_20[0xc0];
e281682b
SM		 2862};
2863
2864struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2865 u8 reserved_at_0[0x18];
e281682b 2866 u8 port_num[0x1];
b4ff3a36 2867 u8 reserved_at_19[0x3];
e281682b
SM		 2868 u8 vl[0x4];
2869
b4ff3a36 2870 u8 reserved_at_20[0xa0];
e281682b
SM		 2871};
2872
2873struct mlx5_ifc_db_bf_congestion_event_bits {
2874 u8 event_subtype[0x8];
b4ff3a36 2875 u8 reserved_at_8[0x8];
e281682b 2876 u8 congestion_level[0x8];
b4ff3a36 2877 u8 reserved_at_18[0x8];
e281682b 2878
b4ff3a36 2879 u8 reserved_at_20[0xa0];
e281682b
SM		 2880};
2881
2882struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2883 u8 reserved_at_0[0x60];
e281682b
SM		 2884
2885 u8 gpio_event_hi[0x20];
2886
2887 u8 gpio_event_lo[0x20];
2888
b4ff3a36 2889 u8 reserved_at_a0[0x40];
e281682b
SM		 2890};
2891
2892struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2893 u8 reserved_at_0[0x40];
e281682b
SM		 2894
2895 u8 port_num[0x4];
b4ff3a36 2896 u8 reserved_at_44[0x1c];
e281682b 2897
b4ff3a36 2898 u8 reserved_at_60[0x80];
e281682b
SM		 2899};
2900
2901struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2902 u8 reserved_at_0[0xe0];
e281682b
SM		 2903};
2904
4b2c5fa9
AT		 2905struct mlx5_ifc_default_timeout_bits {
2906 u8 to_multiplier[0x3];
2907 u8 reserved_at_3[0x9];
2908 u8 to_value[0x14];
2909};
2910
2911struct mlx5_ifc_dtor_reg_bits {
2912 u8 reserved_at_0[0x20];
2913
2914 struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2915
2916 u8 reserved_at_40[0x60];
2917
2918 struct mlx5_ifc_default_timeout_bits health_poll_to;
2919
2920 struct mlx5_ifc_default_timeout_bits full_crdump_to;
2921
2922 struct mlx5_ifc_default_timeout_bits fw_reset_to;
2923
2924 struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2925
2926 struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2927
2928 struct mlx5_ifc_default_timeout_bits tear_down_to;
2929
2930 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2931
2932 struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2933
2934 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
2935
2936 u8 reserved_at_1c0[0x40];
2937};
2938
e281682b
SM		 2939enum {
2940 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2941 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2942};
2943
2944struct mlx5_ifc_cq_error_bits {
b4ff3a36 2945 u8 reserved_at_0[0x8];
e281682b
SM		 2946 u8 cqn[0x18];
2947
b4ff3a36 2948 u8 reserved_at_20[0x20];
e281682b 2949
b4ff3a36 2950 u8 reserved_at_40[0x18];
e281682b
SM		 2951 u8 syndrome[0x8];
2952
b4ff3a36 2953 u8 reserved_at_60[0x80];
e281682b
SM		 2954};
2955
2956struct mlx5_ifc_rdma_page_fault_event_bits {
2957 u8 bytes_committed[0x20];
2958
2959 u8 r_key[0x20];
2960
b4ff3a36 2961 u8 reserved_at_40[0x10];
e281682b
SM		 2962 u8 packet_len[0x10];
2963
2964 u8 rdma_op_len[0x20];
2965
2966 u8 rdma_va[0x40];
2967
b4ff3a36 2968 u8 reserved_at_c0[0x5];
e281682b
SM		 2969 u8 rdma[0x1];
2970 u8 write[0x1];
2971 u8 requestor[0x1];
2972 u8 qp_number[0x18];
2973};
2974
2975struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2976 u8 bytes_committed[0x20];
2977
b4ff3a36 2978 u8 reserved_at_20[0x10];
e281682b
SM		 2979 u8 wqe_index[0x10];
2980
b4ff3a36 2981 u8 reserved_at_40[0x10];
e281682b
SM		 2982 u8 len[0x10];
2983
b4ff3a36 2984 u8 reserved_at_60[0x60];
e281682b 2985
b4ff3a36 2986 u8 reserved_at_c0[0x5];
e281682b
SM		 2987 u8 rdma[0x1];
2988 u8 write_read[0x1];
2989 u8 requestor[0x1];
2990 u8 qpn[0x18];
2991};
2992
2993struct mlx5_ifc_qp_events_bits {
b4ff3a36 2994 u8 reserved_at_0[0xa0];
e281682b
SM		 2995
2996 u8 type[0x8];
b4ff3a36 2997 u8 reserved_at_a8[0x18];
e281682b 2998
b4ff3a36 2999 u8 reserved_at_c0[0x8];
e281682b
SM		 3000 u8 qpn_rqn_sqn[0x18];
3001};
3002
3003struct mlx5_ifc_dct_events_bits {
b4ff3a36 3004 u8 reserved_at_0[0xc0];
e281682b 3005
b4ff3a36 3006 u8 reserved_at_c0[0x8];
e281682b
SM		 3007 u8 dct_number[0x18];
3008};
3009
3010struct mlx5_ifc_comp_event_bits {
b4ff3a36 3011 u8 reserved_at_0[0xc0];
e281682b 3012
b4ff3a36 3013 u8 reserved_at_c0[0x8];
e281682b
SM		 3014 u8 cq_number[0x18];
3015};
3016
3017enum {
3018 MLX5_QPC_STATE_RST = 0x0,
3019 MLX5_QPC_STATE_INIT = 0x1,
3020 MLX5_QPC_STATE_RTR = 0x2,
3021 MLX5_QPC_STATE_RTS = 0x3,
3022 MLX5_QPC_STATE_SQER = 0x4,
3023 MLX5_QPC_STATE_ERR = 0x6,
3024 MLX5_QPC_STATE_SQD = 0x7,
3025 MLX5_QPC_STATE_SUSPENDED = 0x9,
3026};
3027
3028enum {
3029 MLX5_QPC_ST_RC = 0x0,
3030 MLX5_QPC_ST_UC = 0x1,
3031 MLX5_QPC_ST_UD = 0x2,
3032 MLX5_QPC_ST_XRC = 0x3,
3033 MLX5_QPC_ST_DCI = 0x5,
3034 MLX5_QPC_ST_QP0 = 0x7,
3035 MLX5_QPC_ST_QP1 = 0x8,
3036 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3037 MLX5_QPC_ST_REG_UMR = 0xc,
3038};
3039
3040enum {
3041 MLX5_QPC_PM_STATE_ARMED = 0x0,
3042 MLX5_QPC_PM_STATE_REARM = 0x1,
3043 MLX5_QPC_PM_STATE_RESERVED = 0x2,
3044 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3045};
3046
6e44636a
AK		 3047enum {
3048 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3049};
3050
e281682b
SM		 3051enum {
3052 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3053 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3054};
3055
3056enum {
3057 MLX5_QPC_MTU_256_BYTES = 0x1,
3058 MLX5_QPC_MTU_512_BYTES = 0x2,
3059 MLX5_QPC_MTU_1K_BYTES = 0x3,
3060 MLX5_QPC_MTU_2K_BYTES = 0x4,
3061 MLX5_QPC_MTU_4K_BYTES = 0x5,
3062 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3063};
3064
3065enum {
3066 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3067 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3068 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3069 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3070 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3071 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3072 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3073 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3074};
3075
3076enum {
3077 MLX5_QPC_CS_REQ_DISABLE = 0x0,
3078 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3079 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3080};
3081
3082enum {
3083 MLX5_QPC_CS_RES_DISABLE = 0x0,
3084 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3085 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3086};
3087
a6a217dd 3088enum {
9a1ac95a
AL		 3089 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3090 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3091 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
a6a217dd
AL		 3092};
3093
e281682b
SM		 3094struct mlx5_ifc_qpc_bits {
3095 u8 state[0x4];
84df61eb 3096 u8 lag_tx_port_affinity[0x4];
e281682b 3097 u8 st[0x8];
7304d603
YK		 3098 u8 reserved_at_10[0x2];
3099 u8 isolate_vl_tc[0x1];
e281682b 3100 u8 pm_state[0x2];
3fd3c80a
DG		 3101 u8 reserved_at_15[0x1];
3102 u8 req_e2e_credit_mode[0x2];
6e44636a 3103 u8 offload_type[0x4];
e281682b 3104 u8 end_padding_mode[0x2];
b4ff3a36 3105 u8 reserved_at_1e[0x2];
e281682b
SM		 3106
3107 u8 wq_signature[0x1];
3108 u8 block_lb_mc[0x1];
3109 u8 atomic_like_write_en[0x1];
3110 u8 latency_sensitive[0x1];
b4ff3a36 3111 u8 reserved_at_24[0x1];
e281682b 3112 u8 drain_sigerr[0x1];
b4ff3a36 3113 u8 reserved_at_26[0x2];
e281682b
SM		 3114 u8 pd[0x18];
3115
3116 u8 mtu[0x3];
3117 u8 log_msg_max[0x5];
b4ff3a36 3118 u8 reserved_at_48[0x1];
e281682b
SM		 3119 u8 log_rq_size[0x4];
3120 u8 log_rq_stride[0x3];
3121 u8 no_sq[0x1];
3122 u8 log_sq_size[0x4];
a6a217dd
AL		 3123 u8 reserved_at_55[0x3];
3124 u8 ts_format[0x2];
3125 u8 reserved_at_5a[0x1];
e281682b 3126 u8 rlky[0x1];
1015c2e8 3127 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 3128
3129 u8 counter_set_id[0x8];
3130 u8 uar_page[0x18];
3131
b4ff3a36 3132 u8 reserved_at_80[0x8];
e281682b
SM		 3133 u8 user_index[0x18];
3134
b4ff3a36 3135 u8 reserved_at_a0[0x3];
e281682b
SM		 3136 u8 log_page_size[0x5];
3137 u8 remote_qpn[0x18];
3138
3139 struct mlx5_ifc_ads_bits primary_address_path;
3140
3141 struct mlx5_ifc_ads_bits secondary_address_path;
3142
3143 u8 log_ack_req_freq[0x4];
b4ff3a36 3144 u8 reserved_at_384[0x4];
e281682b 3145 u8 log_sra_max[0x3];
b4ff3a36 3146 u8 reserved_at_38b[0x2];
e281682b
SM		 3147 u8 retry_count[0x3];
3148 u8 rnr_retry[0x3];
b4ff3a36 3149 u8 reserved_at_393[0x1];
e281682b
SM		 3150 u8 fre[0x1];
3151 u8 cur_rnr_retry[0x3];
3152 u8 cur_retry_count[0x3];
b4ff3a36 3153 u8 reserved_at_39b[0x5];
e281682b 3154
b4ff3a36 3155 u8 reserved_at_3a0[0x20];
e281682b 3156
b4ff3a36 3157 u8 reserved_at_3c0[0x8];
e281682b
SM		 3158 u8 next_send_psn[0x18];
3159
96cd2dd6
LN		 3160 u8 reserved_at_3e0[0x3];
3161 u8 log_num_dci_stream_channels[0x5];
e281682b
SM		 3162 u8 cqn_snd[0x18];
3163
96cd2dd6
LN		 3164 u8 reserved_at_400[0x3];
3165 u8 log_num_dci_errored_streams[0x5];
09a7d9ec
SM		 3166 u8 deth_sqpn[0x18];
3167
3168 u8 reserved_at_420[0x20];
e281682b 3169
b4ff3a36 3170 u8 reserved_at_440[0x8];
e281682b
SM		 3171 u8 last_acked_psn[0x18];
3172
b4ff3a36 3173 u8 reserved_at_460[0x8];
e281682b
SM		 3174 u8 ssn[0x18];
3175
b4ff3a36 3176 u8 reserved_at_480[0x8];
e281682b 3177 u8 log_rra_max[0x3];
b4ff3a36 3178 u8 reserved_at_48b[0x1];
e281682b
SM		 3179 u8 atomic_mode[0x4];
3180 u8 rre[0x1];
3181 u8 rwe[0x1];
3182 u8 rae[0x1];
b4ff3a36 3183 u8 reserved_at_493[0x1];
e281682b 3184 u8 page_offset[0x6];
b4ff3a36 3185 u8 reserved_at_49a[0x3];
e281682b
SM		 3186 u8 cd_slave_receive[0x1];
3187 u8 cd_slave_send[0x1];
3188 u8 cd_master[0x1];
3189
b4ff3a36 3190 u8 reserved_at_4a0[0x3];
e281682b
SM		 3191 u8 min_rnr_nak[0x5];
3192 u8 next_rcv_psn[0x18];
3193
b4ff3a36 3194 u8 reserved_at_4c0[0x8];
e281682b
SM		 3195 u8 xrcd[0x18];
3196
b4ff3a36 3197 u8 reserved_at_4e0[0x8];
e281682b
SM		 3198 u8 cqn_rcv[0x18];
3199
3200 u8 dbr_addr[0x40];
3201
3202 u8 q_key[0x20];
3203
b4ff3a36 3204 u8 reserved_at_560[0x5];
e281682b 3205 u8 rq_type[0x3];
7486216b 3206 u8 srqn_rmpn_xrqn[0x18];
e281682b 3207
b4ff3a36 3208 u8 reserved_at_580[0x8];
e281682b
SM		 3209 u8 rmsn[0x18];
3210
3211 u8 hw_sq_wqebb_counter[0x10];
3212 u8 sw_sq_wqebb_counter[0x10];
3213
3214 u8 hw_rq_counter[0x20];
3215
3216 u8 sw_rq_counter[0x20];
3217
b4ff3a36 3218 u8 reserved_at_600[0x20];
e281682b 3219
b4ff3a36 3220 u8 reserved_at_620[0xf];
e281682b
SM		 3221 u8 cgs[0x1];
3222 u8 cs_req[0x8];
3223 u8 cs_res[0x8];
3224
3225 u8 dc_access_key[0x40];
3226
bd371975
LR		 3227 u8 reserved_at_680[0x3];
3228 u8 dbr_umem_valid[0x1];
3229
3230 u8 reserved_at_684[0xbc];
e281682b
SM		 3231};
3232
3233struct mlx5_ifc_roce_addr_layout_bits {
3234 u8 source_l3_address[16][0x8];
3235
b4ff3a36 3236 u8 reserved_at_80[0x3];
e281682b
SM		 3237 u8 vlan_valid[0x1];
3238 u8 vlan_id[0xc];
3239 u8 source_mac_47_32[0x10];
3240
3241 u8 source_mac_31_0[0x20];
3242
b4ff3a36 3243 u8 reserved_at_c0[0x14];
e281682b
SM		 3244 u8 roce_l3_type[0x4];
3245 u8 roce_version[0x8];
3246
b4ff3a36 3247 u8 reserved_at_e0[0x20];
e281682b
SM		 3248};
3249
7025329d
BBI		 3250struct mlx5_ifc_shampo_cap_bits {
3251 u8 reserved_at_0[0x3];
3252 u8 shampo_log_max_reservation_size[0x5];
3253 u8 reserved_at_8[0x3];
3254 u8 shampo_log_min_reservation_size[0x5];
3255 u8 shampo_min_mss_size[0x10];
3256
3257 u8 reserved_at_20[0x3];
3258 u8 shampo_max_log_headers_entry_size[0x5];
3259 u8 reserved_at_28[0x18];
3260
3261 u8 reserved_at_40[0x7c0];
3262};
3263
e281682b
SM		 3264union mlx5_ifc_hca_cap_union_bits {
3265 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
67133eaa 3266 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
e281682b
SM		 3267 struct mlx5_ifc_odp_cap_bits odp_cap;
3268 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3269 struct mlx5_ifc_roce_cap_bits roce_cap;
3270 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3271 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 3272 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 3273 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
425a563a 3274 struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3f0393a5 3275 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 3276 struct mlx5_ifc_qos_cap_bits qos_cap;
0b9055a1 3277 struct mlx5_ifc_debug_cap_bits debug_cap;
e29341fb 3278 struct mlx5_ifc_fpga_cap_bits fpga_cap;
a12ff35e 3279 struct mlx5_ifc_tls_cap_bits tls_cap;
97b5484e 3280 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
8a06a79b 3281 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
7025329d 3282 struct mlx5_ifc_shampo_cap_bits shampo_cap;
b4ff3a36 3283 u8 reserved_at_0[0x8000];
e281682b
SM		 3284};
3285
3286enum {
3287 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3288 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3289 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 3290 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 3291 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 3292 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 3293 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 3294 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3295 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 3296 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3297 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
78fb6122
HN		 3298 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3299 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
f5d23ee1 3300 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
0c06897a
OG		 3301};
3302
65c0f2c1
JL		 3303enum {
3304 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3305 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3306 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3307};
3308
0c06897a
OG		 3309struct mlx5_ifc_vlan_bits {
3310 u8 ethtype[0x10];
3311 u8 prio[0x3];
3312 u8 cfi[0x1];
3313 u8 vid[0xc];
e281682b
SM		 3314};
3315
f5d23ee1
JL		 3316enum {
3317 MLX5_FLOW_METER_COLOR_RED = 0x0,
3318 MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
3319 MLX5_FLOW_METER_COLOR_GREEN = 0x2,
3320 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3321};
3322
3323enum {
3324 MLX5_EXE_ASO_FLOW_METER = 0x2,
3325};
3326
3327struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3328 u8 return_reg_id[0x4];
3329 u8 aso_type[0x4];
3330 u8 reserved_at_8[0x14];
3331 u8 action[0x1];
3332 u8 init_color[0x2];
3333 u8 meter_id[0x1];
3334};
3335
3336union mlx5_ifc_exe_aso_ctrl {
3337 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3338};
3339
3340struct mlx5_ifc_execute_aso_bits {
3341 u8 valid[0x1];
3342 u8 reserved_at_1[0x7];
3343 u8 aso_object_id[0x18];
3344
3345 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3346};
3347
e281682b 3348struct mlx5_ifc_flow_context_bits {
0c06897a 3349 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 3350
3351 u8 group_id[0x20];
3352
b4ff3a36 3353 u8 reserved_at_40[0x8];
e281682b
SM		 3354 u8 flow_tag[0x18];
3355
b4ff3a36 3356 u8 reserved_at_60[0x10];
e281682b
SM		 3357 u8 action[0x10];
3358
1b115498 3359 u8 extended_destination[0x1];
65c0f2c1
JL		 3360 u8 reserved_at_81[0x1];
3361 u8 flow_source[0x2];
3362 u8 reserved_at_84[0x4];
e281682b
SM		 3363 u8 destination_list_size[0x18];
3364
9dc0b289
AV		 3365 u8 reserved_at_a0[0x8];
3366 u8 flow_counter_list_size[0x18];
3367
60786f09 3368 u8 packet_reformat_id[0x20];
7adbde20 3369
2a69cb9f
OG		 3370 u8 modify_header_id[0x20];
3371
8da6fe2a
JL		 3372 struct mlx5_ifc_vlan_bits push_vlan_2;
3373
78fb6122
HN		 3374 u8 ipsec_obj_id[0x20];
3375 u8 reserved_at_140[0xc0];
e281682b
SM		 3376
3377 struct mlx5_ifc_fte_match_param_bits match_value;
3378
f5d23ee1
JL		 3379 struct mlx5_ifc_execute_aso_bits execute_aso[4];
3380
3381 u8 reserved_at_1300[0x500];
e281682b 3382
b6ca09cb 3383 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
e281682b
SM		 3384};
3385
3386enum {
3387 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3388 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3389};
3390
3391struct mlx5_ifc_xrc_srqc_bits {
3392 u8 state[0x4];
3393 u8 log_xrc_srq_size[0x4];
b4ff3a36 3394 u8 reserved_at_8[0x18];
e281682b
SM		 3395
3396 u8 wq_signature[0x1];
3397 u8 cont_srq[0x1];
99b77fef 3398 u8 reserved_at_22[0x1];
e281682b
SM		 3399 u8 rlky[0x1];
3400 u8 basic_cyclic_rcv_wqe[0x1];
3401 u8 log_rq_stride[0x3];
3402 u8 xrcd[0x18];
3403
3404 u8 page_offset[0x6];
99b77fef
YH		 3405 u8 reserved_at_46[0x1];
3406 u8 dbr_umem_valid[0x1];
e281682b
SM		 3407 u8 cqn[0x18];
3408
b4ff3a36 3409 u8 reserved_at_60[0x20];
e281682b
SM		 3410
3411 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 3412 u8 reserved_at_81[0x1];
e281682b
SM		 3413 u8 log_page_size[0x6];
3414 u8 user_index[0x18];
3415
b4ff3a36 3416 u8 reserved_at_a0[0x20];
e281682b 3417
b4ff3a36 3418 u8 reserved_at_c0[0x8];
e281682b
SM		 3419 u8 pd[0x18];
3420
3421 u8 lwm[0x10];
3422 u8 wqe_cnt[0x10];
3423
b4ff3a36 3424 u8 reserved_at_100[0x40];
e281682b
SM		 3425
3426 u8 db_record_addr_h[0x20];
3427
3428 u8 db_record_addr_l[0x1e];
b4ff3a36 3429 u8 reserved_at_17e[0x2];
e281682b 3430
b4ff3a36 3431 u8 reserved_at_180[0x80];
e281682b
SM		 3432};
3433
61c5b5c9
MS		 3434struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3435 u8 counter_error_queues[0x20];
3436
3437 u8 total_error_queues[0x20];
3438
3439 u8 send_queue_priority_update_flow[0x20];
3440
3441 u8 reserved_at_60[0x20];
3442
3443 u8 nic_receive_steering_discard[0x40];
3444
3445 u8 receive_discard_vport_down[0x40];
3446
3447 u8 transmit_discard_vport_down[0x40];
3448
3e94e61b
SM		 3449 u8 async_eq_overrun[0x20];
3450
3451 u8 comp_eq_overrun[0x20];
3452
3453 u8 reserved_at_180[0x20];
3454
3455 u8 invalid_command[0x20];
3456
3457 u8 quota_exceeded_command[0x20];
30b10e89
MS		 3458
3459 u8 internal_rq_out_of_buffer[0x20];
3460
3e94e61b
SM		 3461 u8 cq_overrun[0x20];
3462
3463 u8 reserved_at_220[0xde0];
61c5b5c9
MS		 3464};
3465
e281682b
SM		 3466struct mlx5_ifc_traffic_counter_bits {
3467 u8 packets[0x40];
3468
3469 u8 octets[0x40];
3470};
3471
3472struct mlx5_ifc_tisc_bits {
84df61eb 3473 u8 strict_lag_tx_port_affinity[0x1];
a12ff35e 3474 u8 tls_en[0x1];
7761f9ee 3475 u8 reserved_at_2[0x2];
84df61eb
AH		 3476 u8 lag_tx_port_affinity[0x04];
3477
3478 u8 reserved_at_8[0x4];
e281682b 3479 u8 prio[0x4];
b4ff3a36 3480 u8 reserved_at_10[0x10];
e281682b 3481
b4ff3a36 3482 u8 reserved_at_20[0x100];
e281682b 3483
b4ff3a36 3484 u8 reserved_at_120[0x8];
e281682b
SM		 3485 u8 transport_domain[0x18];
3486
500a3d0d
ES		 3487 u8 reserved_at_140[0x8];
3488 u8 underlay_qpn[0x18];
a12ff35e
EBE		 3489
3490 u8 reserved_at_160[0x8];
3491 u8 pd[0x18];
3492
3493 u8 reserved_at_180[0x380];
e281682b
SM		 3494};
3495
3496enum {
3497 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3498 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3499};
3500
3501enum {
50f477fe
BBI		 3502 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3503 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
e281682b
SM		 3504};
3505
3506enum {
2be6967c
SM		 3507 MLX5_RX_HASH_FN_NONE = 0x0,
3508 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3509 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 3510};
3511
3512enum {
5d773ff4
MB		 3513 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3514 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 3515};
3516
3517struct mlx5_ifc_tirc_bits {
b4ff3a36 3518 u8 reserved_at_0[0x20];
e281682b
SM		 3519
3520 u8 disp_type[0x4];
ee5cdf7a
TT		 3521 u8 tls_en[0x1];
3522 u8 reserved_at_25[0x1b];
e281682b 3523
b4ff3a36 3524 u8 reserved_at_40[0x40];
e281682b 3525
b4ff3a36 3526 u8 reserved_at_80[0x4];
e281682b 3527 u8 lro_timeout_period_usecs[0x10];
50f477fe 3528 u8 packet_merge_mask[0x4];
e281682b
SM		 3529 u8 lro_max_ip_payload_size[0x8];
3530
b4ff3a36 3531 u8 reserved_at_a0[0x40];
e281682b 3532
b4ff3a36 3533 u8 reserved_at_e0[0x8];
e281682b
SM		 3534 u8 inline_rqn[0x18];
3535
3536 u8 rx_hash_symmetric[0x1];
b4ff3a36 3537 u8 reserved_at_101[0x1];
e281682b 3538 u8 tunneled_offload_en[0x1];
b4ff3a36 3539 u8 reserved_at_103[0x5];
e281682b
SM		 3540 u8 indirect_table[0x18];
3541
3542 u8 rx_hash_fn[0x4];
b4ff3a36 3543 u8 reserved_at_124[0x2];
e281682b
SM		 3544 u8 self_lb_block[0x2];
3545 u8 transport_domain[0x18];
3546
3547 u8 rx_hash_toeplitz_key[10][0x20];
3548
3549 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3550
3551 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3552
b4ff3a36 3553 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 3554};
3555
3556enum {
3557 MLX5_SRQC_STATE_GOOD = 0x0,
3558 MLX5_SRQC_STATE_ERROR = 0x1,
3559};
3560
3561struct mlx5_ifc_srqc_bits {
3562 u8 state[0x4];
3563 u8 log_srq_size[0x4];
b4ff3a36 3564 u8 reserved_at_8[0x18];
e281682b
SM		 3565
3566 u8 wq_signature[0x1];
3567 u8 cont_srq[0x1];
b4ff3a36 3568 u8 reserved_at_22[0x1];
e281682b 3569 u8 rlky[0x1];
b4ff3a36 3570 u8 reserved_at_24[0x1];
e281682b
SM		 3571 u8 log_rq_stride[0x3];
3572 u8 xrcd[0x18];
3573
3574 u8 page_offset[0x6];
b4ff3a36 3575 u8 reserved_at_46[0x2];
e281682b
SM		 3576 u8 cqn[0x18];
3577
b4ff3a36 3578 u8 reserved_at_60[0x20];
e281682b 3579
b4ff3a36 3580 u8 reserved_at_80[0x2];
e281682b 3581 u8 log_page_size[0x6];
b4ff3a36 3582 u8 reserved_at_88[0x18];
e281682b 3583
b4ff3a36 3584 u8 reserved_at_a0[0x20];
e281682b 3585
b4ff3a36 3586 u8 reserved_at_c0[0x8];
e281682b
SM		 3587 u8 pd[0x18];
3588
3589 u8 lwm[0x10];
3590 u8 wqe_cnt[0x10];
3591
b4ff3a36 3592 u8 reserved_at_100[0x40];
e281682b 3593
01949d01 3594 u8 dbr_addr[0x40];
e281682b 3595
b4ff3a36 3596 u8 reserved_at_180[0x80];
e281682b
SM		 3597};
3598
3599enum {
3600 MLX5_SQC_STATE_RST = 0x0,
3601 MLX5_SQC_STATE_RDY = 0x1,
3602 MLX5_SQC_STATE_ERR = 0x3,
3603};
3604
3605struct mlx5_ifc_sqc_bits {
3606 u8 rlky[0x1];
3607 u8 cd_master[0x1];
3608 u8 fre[0x1];
3609 u8 flush_in_error_en[0x1];
795b609c 3610 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 3611 u8 min_wqe_inline_mode[0x3];
e281682b 3612 u8 state[0x4];
7d5e1423 3613 u8 reg_umr[0x1];
547eede0 3614 u8 allow_swp[0x1];
40817cdb 3615 u8 hairpin[0x1];
a6a217dd
AL		 3616 u8 reserved_at_f[0xb];
3617 u8 ts_format[0x2];
3618 u8 reserved_at_1c[0x4];
e281682b 3619
b4ff3a36 3620 u8 reserved_at_20[0x8];
e281682b
SM		 3621 u8 user_index[0x18];
3622
b4ff3a36 3623 u8 reserved_at_40[0x8];
e281682b
SM		 3624 u8 cqn[0x18];
3625
40817cdb
OG		 3626 u8 reserved_at_60[0x8];
3627 u8 hairpin_peer_rq[0x18];
3628
3629 u8 reserved_at_80[0x10];
3630 u8 hairpin_peer_vhca[0x10];
3631
59d2ae1d 3632 u8 reserved_at_a0[0x20];
e281682b 3633
59d2ae1d
EBE		 3634 u8 reserved_at_c0[0x8];
3635 u8 ts_cqe_to_dest_cqn[0x18];
e281682b 3636
59d2ae1d 3637 u8 reserved_at_e0[0x10];
7486216b 3638 u8 packet_pacing_rate_limit_index[0x10];
e281682b 3639 u8 tis_lst_sz[0x10];
214baf22 3640 u8 qos_queue_group_id[0x10];
e281682b 3641
b4ff3a36 3642 u8 reserved_at_120[0x40];
e281682b 3643
b4ff3a36 3644 u8 reserved_at_160[0x8];
e281682b
SM		 3645 u8 tis_num_0[0x18];
3646
3647 struct mlx5_ifc_wq_bits wq;
3648};
3649
813f8540
MHY		 3650enum {
3651 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3652 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3653 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3654 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
214baf22 3655 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
813f8540
MHY		 3656};
3657
6cedde45
EC		 3658enum {
3659 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3660 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3661 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3662 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3663};
3664
813f8540
MHY		 3665struct mlx5_ifc_scheduling_context_bits {
3666 u8 element_type[0x8];
3667 u8 reserved_at_8[0x18];
3668
3669 u8 element_attributes[0x20];
3670
3671 u8 parent_element_id[0x20];
3672
3673 u8 reserved_at_60[0x40];
3674
3675 u8 bw_share[0x20];
3676
3677 u8 max_average_bw[0x20];
3678
3679 u8 reserved_at_e0[0x120];
3680};
3681
e281682b 3682struct mlx5_ifc_rqtc_bits {
8a06a79b 3683 u8 reserved_at_0[0xa0];
e281682b 3684
8a06a79b
EC		 3685 u8 reserved_at_a0[0x5];
3686 u8 list_q_type[0x3];
3687 u8 reserved_at_a8[0x8];
3688 u8 rqt_max_size[0x10];
e281682b 3689
8a06a79b
EC		 3690 u8 rq_vhca_id_format[0x1];
3691 u8 reserved_at_c1[0xf];
3692 u8 rqt_actual_size[0x10];
e281682b 3693
8a06a79b 3694 u8 reserved_at_e0[0x6a0];
e281682b 3695
b6ca09cb 3696 struct mlx5_ifc_rq_num_bits rq_num[];
e281682b
SM		 3697};
3698
3699enum {
3700 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3701 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3702};
3703
3704enum {
3705 MLX5_RQC_STATE_RST = 0x0,
3706 MLX5_RQC_STATE_RDY = 0x1,
3707 MLX5_RQC_STATE_ERR = 0x3,
3708};
3709
7025329d
BBI		 3710enum {
3711 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3712 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3713 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3714};
3715
3716enum {
3717 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3718 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3719 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3720};
3721
e281682b
SM		 3722struct mlx5_ifc_rqc_bits {
3723 u8 rlky[0x1];
03404e8a 3724 u8 delay_drop_en[0x1];
7d5e1423 3725 u8 scatter_fcs[0x1];
e281682b
SM		 3726 u8 vsd[0x1];
3727 u8 mem_rq_type[0x4];
3728 u8 state[0x4];
b4ff3a36 3729 u8 reserved_at_c[0x1];
e281682b 3730 u8 flush_in_error_en[0x1];
40817cdb 3731 u8 hairpin[0x1];
a6a217dd
AL		 3732 u8 reserved_at_f[0xb];
3733 u8 ts_format[0x2];
3734 u8 reserved_at_1c[0x4];
e281682b 3735
b4ff3a36 3736 u8 reserved_at_20[0x8];
e281682b
SM		 3737 u8 user_index[0x18];
3738
b4ff3a36 3739 u8 reserved_at_40[0x8];
e281682b
SM		 3740 u8 cqn[0x18];
3741
3742 u8 counter_set_id[0x8];
b4ff3a36 3743 u8 reserved_at_68[0x18];
e281682b 3744
b4ff3a36 3745 u8 reserved_at_80[0x8];
e281682b
SM		 3746 u8 rmpn[0x18];
3747
40817cdb
OG		 3748 u8 reserved_at_a0[0x8];
3749 u8 hairpin_peer_sq[0x18];
3750
3751 u8 reserved_at_c0[0x10];
3752 u8 hairpin_peer_vhca[0x10];
3753
7025329d
BBI		 3754 u8 reserved_at_e0[0x46];
3755 u8 shampo_no_match_alignment_granularity[0x2];
3756 u8 reserved_at_128[0x6];
3757 u8 shampo_match_criteria_type[0x2];
3758 u8 reservation_timeout[0x10];
3759
3760 u8 reserved_at_140[0x40];
e281682b
SM		 3761
3762 struct mlx5_ifc_wq_bits wq;
3763};
3764
3765enum {
3766 MLX5_RMPC_STATE_RDY = 0x1,
3767 MLX5_RMPC_STATE_ERR = 0x3,
3768};
3769
3770struct mlx5_ifc_rmpc_bits {
b4ff3a36 3771 u8 reserved_at_0[0x8];
e281682b 3772 u8 state[0x4];
b4ff3a36 3773 u8 reserved_at_c[0x14];
e281682b
SM		 3774
3775 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 3776 u8 reserved_at_21[0x1f];
e281682b 3777
b4ff3a36 3778 u8 reserved_at_40[0x140];
e281682b
SM		 3779
3780 struct mlx5_ifc_wq_bits wq;
3781};
3782
e281682b 3783struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 3784 u8 reserved_at_0[0x5];
3785 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 3786 u8 reserved_at_8[0x15];
3787 u8 disable_mc_local_lb[0x1];
3788 u8 disable_uc_local_lb[0x1];
e281682b
SM		 3789 u8 roce_en[0x1];
3790
d82b7318 3791 u8 arm_change_event[0x1];
b4ff3a36 3792 u8 reserved_at_21[0x1a];
d82b7318
SM		 3793 u8 event_on_mtu[0x1];
3794 u8 event_on_promisc_change[0x1];
3795 u8 event_on_vlan_change[0x1];
3796 u8 event_on_mc_address_change[0x1];
3797 u8 event_on_uc_address_change[0x1];
e281682b 3798
32f69e4b
DJ		 3799 u8 reserved_at_40[0xc];
3800
3801 u8 affiliation_criteria[0x4];
3802 u8 affiliated_vhca_id[0x10];
3803
3804 u8 reserved_at_60[0xd0];
d82b7318
SM		 3805
3806 u8 mtu[0x10];
3807
9efa7525
AS		 3808 u8 system_image_guid[0x40];
3809 u8 port_guid[0x40];
3810 u8 node_guid[0x40];
3811
b4ff3a36 3812 u8 reserved_at_200[0x140];
9efa7525 3813 u8 qkey_violation_counter[0x10];
b4ff3a36 3814 u8 reserved_at_350[0x430];
d82b7318
SM		 3815
3816 u8 promisc_uc[0x1];
3817 u8 promisc_mc[0x1];
3818 u8 promisc_all[0x1];
b4ff3a36 3819 u8 reserved_at_783[0x2];
e281682b 3820 u8 allowed_list_type[0x3];
b4ff3a36 3821 u8 reserved_at_788[0xc];
e281682b
SM		 3822 u8 allowed_list_size[0xc];
3823
3824 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3825
b4ff3a36 3826 u8 reserved_at_7e0[0x20];
e281682b 3827
b6ca09cb 3828 u8 current_uc_mac_address[][0x40];
e281682b
SM		 3829};
3830
3831enum {
3832 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3833 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3834 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 3835 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 3836 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 3837 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 3838};
3839
3840struct mlx5_ifc_mkc_bits {
b4ff3a36 3841 u8 reserved_at_0[0x1];
e281682b 3842 u8 free[0x1];
cdbd0d2b
AL		 3843 u8 reserved_at_2[0x1];
3844 u8 access_mode_4_2[0x3];
3845 u8 reserved_at_6[0x7];
3846 u8 relaxed_ordering_write[0x1];
3847 u8 reserved_at_e[0x1];
e281682b
SM		 3848 u8 small_fence_on_rdma_read_response[0x1];
3849 u8 umr_en[0x1];
3850 u8 a[0x1];
3851 u8 rw[0x1];
3852 u8 rr[0x1];
3853 u8 lw[0x1];
3854 u8 lr[0x1];
cdbd0d2b 3855 u8 access_mode_1_0[0x2];
b4ff3a36 3856 u8 reserved_at_18[0x8];
e281682b
SM		 3857
3858 u8 qpn[0x18];
3859 u8 mkey_7_0[0x8];
3860
b4ff3a36 3861 u8 reserved_at_40[0x20];
e281682b
SM		 3862
3863 u8 length64[0x1];
3864 u8 bsf_en[0x1];
3865 u8 sync_umr[0x1];
b4ff3a36 3866 u8 reserved_at_63[0x2];
e281682b 3867 u8 expected_sigerr_count[0x1];
b4ff3a36 3868 u8 reserved_at_66[0x1];
e281682b
SM		 3869 u8 en_rinval[0x1];
3870 u8 pd[0x18];
3871
3872 u8 start_addr[0x40];
3873
3874 u8 len[0x40];
3875
3876 u8 bsf_octword_size[0x20];
3877
b4ff3a36 3878 u8 reserved_at_120[0x80];
e281682b
SM		 3879
3880 u8 translations_octword_size[0x20];
3881
a880a6dd
MG		 3882 u8 reserved_at_1c0[0x19];
3883 u8 relaxed_ordering_read[0x1];
3884 u8 reserved_at_1d9[0x1];
e281682b
SM		 3885 u8 log_page_size[0x5];
3886
b4ff3a36 3887 u8 reserved_at_1e0[0x20];
e281682b
SM		 3888};
3889
3890struct mlx5_ifc_pkey_bits {
b4ff3a36 3891 u8 reserved_at_0[0x10];
e281682b
SM		 3892 u8 pkey[0x10];
3893};
3894
3895struct mlx5_ifc_array128_auto_bits {
3896 u8 array128_auto[16][0x8];
3897};
3898
3899struct mlx5_ifc_hca_vport_context_bits {
3900 u8 field_select[0x20];
3901
b4ff3a36 3902 u8 reserved_at_20[0xe0];
e281682b
SM		 3903
3904 u8 sm_virt_aware[0x1];
3905 u8 has_smi[0x1];
3906 u8 has_raw[0x1];
3907 u8 grh_required[0x1];
b4ff3a36 3908 u8 reserved_at_104[0xc];
707c4602
MD		 3909 u8 port_physical_state[0x4];
3910 u8 vport_state_policy[0x4];
3911 u8 port_state[0x4];
e281682b
SM		 3912 u8 vport_state[0x4];
3913
b4ff3a36 3914 u8 reserved_at_120[0x20];
707c4602
MD		 3915
3916 u8 system_image_guid[0x40];
e281682b
SM		 3917
3918 u8 port_guid[0x40];
3919
3920 u8 node_guid[0x40];
3921
3922 u8 cap_mask1[0x20];
3923
3924 u8 cap_mask1_field_select[0x20];
3925
3926 u8 cap_mask2[0x20];
3927
3928 u8 cap_mask2_field_select[0x20];
3929
b4ff3a36 3930 u8 reserved_at_280[0x80];
e281682b
SM		 3931
3932 u8 lid[0x10];
b4ff3a36 3933 u8 reserved_at_310[0x4];
e281682b
SM		 3934 u8 init_type_reply[0x4];
3935 u8 lmc[0x3];
3936 u8 subnet_timeout[0x5];
3937
3938 u8 sm_lid[0x10];
3939 u8 sm_sl[0x4];
b4ff3a36 3940 u8 reserved_at_334[0xc];
e281682b
SM		 3941
3942 u8 qkey_violation_counter[0x10];
3943 u8 pkey_violation_counter[0x10];
3944
b4ff3a36 3945 u8 reserved_at_360[0xca0];
e281682b
SM		 3946};
3947
d6666753 3948struct mlx5_ifc_esw_vport_context_bits {
65c0f2c1
JL		 3949 u8 fdb_to_vport_reg_c[0x1];
3950 u8 reserved_at_1[0x2];
d6666753
SM		 3951 u8 vport_svlan_strip[0x1];
3952 u8 vport_cvlan_strip[0x1];
3953 u8 vport_svlan_insert[0x1];
3954 u8 vport_cvlan_insert[0x2];
65c0f2c1
JL		 3955 u8 fdb_to_vport_reg_c_id[0x8];
3956 u8 reserved_at_10[0x10];
d6666753 3957
b4ff3a36 3958 u8 reserved_at_20[0x20];
d6666753
SM		 3959
3960 u8 svlan_cfi[0x1];
3961 u8 svlan_pcp[0x3];
3962 u8 svlan_id[0xc];
3963 u8 cvlan_cfi[0x1];
3964 u8 cvlan_pcp[0x3];
3965 u8 cvlan_id[0xc];
3966
97b5484e
AV		 3967 u8 reserved_at_60[0x720];
3968
3969 u8 sw_steering_vport_icm_address_rx[0x40];
3970
3971 u8 sw_steering_vport_icm_address_tx[0x40];
d6666753
SM		 3972};
3973
e281682b
SM		 3974enum {
3975 MLX5_EQC_STATUS_OK = 0x0,
3976 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3977};
3978
3979enum {
3980 MLX5_EQC_ST_ARMED = 0x9,
3981 MLX5_EQC_ST_FIRED = 0xa,
3982};
3983
3984struct mlx5_ifc_eqc_bits {
3985 u8 status[0x4];
b4ff3a36 3986 u8 reserved_at_4[0x9];
e281682b
SM		 3987 u8 ec[0x1];
3988 u8 oi[0x1];
b4ff3a36 3989 u8 reserved_at_f[0x5];
e281682b 3990 u8 st[0x4];
b4ff3a36 3991 u8 reserved_at_18[0x8];
e281682b 3992
b4ff3a36 3993 u8 reserved_at_20[0x20];
e281682b 3994
b4ff3a36 3995 u8 reserved_at_40[0x14];
e281682b 3996 u8 page_offset[0x6];
b4ff3a36 3997 u8 reserved_at_5a[0x6];
e281682b 3998
b4ff3a36 3999 u8 reserved_at_60[0x3];
e281682b
SM		 4000 u8 log_eq_size[0x5];
4001 u8 uar_page[0x18];
4002
b4ff3a36 4003 u8 reserved_at_80[0x20];
e281682b 4004
3af26495
SD		 4005 u8 reserved_at_a0[0x14];
4006 u8 intr[0xc];
e281682b 4007
b4ff3a36 4008 u8 reserved_at_c0[0x3];
e281682b 4009 u8 log_page_size[0x5];
b4ff3a36 4010 u8 reserved_at_c8[0x18];
e281682b 4011
b4ff3a36 4012 u8 reserved_at_e0[0x60];
e281682b 4013
b4ff3a36 4014 u8 reserved_at_140[0x8];
e281682b
SM		 4015 u8 consumer_counter[0x18];
4016
b4ff3a36 4017 u8 reserved_at_160[0x8];
e281682b
SM		 4018 u8 producer_counter[0x18];
4019
b4ff3a36 4020 u8 reserved_at_180[0x80];
e281682b
SM		 4021};
4022
4023enum {
4024 MLX5_DCTC_STATE_ACTIVE = 0x0,
4025 MLX5_DCTC_STATE_DRAINING = 0x1,
4026 MLX5_DCTC_STATE_DRAINED = 0x2,
4027};
4028
4029enum {
4030 MLX5_DCTC_CS_RES_DISABLE = 0x0,
4031 MLX5_DCTC_CS_RES_NA = 0x1,
4032 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
4033};
4034
4035enum {
4036 MLX5_DCTC_MTU_256_BYTES = 0x1,
4037 MLX5_DCTC_MTU_512_BYTES = 0x2,
4038 MLX5_DCTC_MTU_1K_BYTES = 0x3,
4039 MLX5_DCTC_MTU_2K_BYTES = 0x4,
4040 MLX5_DCTC_MTU_4K_BYTES = 0x5,
4041};
4042
4043struct mlx5_ifc_dctc_bits {
b4ff3a36 4044 u8 reserved_at_0[0x4];
e281682b 4045 u8 state[0x4];
b4ff3a36 4046 u8 reserved_at_8[0x18];
e281682b 4047
b4ff3a36 4048 u8 reserved_at_20[0x8];
e281682b
SM		 4049 u8 user_index[0x18];
4050
b4ff3a36 4051 u8 reserved_at_40[0x8];
e281682b
SM		 4052 u8 cqn[0x18];
4053
4054 u8 counter_set_id[0x8];
4055 u8 atomic_mode[0x4];
4056 u8 rre[0x1];
4057 u8 rwe[0x1];
4058 u8 rae[0x1];
4059 u8 atomic_like_write_en[0x1];
4060 u8 latency_sensitive[0x1];
4061 u8 rlky[0x1];
4062 u8 free_ar[0x1];
b4ff3a36 4063 u8 reserved_at_73[0xd];
e281682b 4064
b4ff3a36 4065 u8 reserved_at_80[0x8];
e281682b 4066 u8 cs_res[0x8];
b4ff3a36 4067 u8 reserved_at_90[0x3];
e281682b 4068 u8 min_rnr_nak[0x5];
b4ff3a36 4069 u8 reserved_at_98[0x8];
e281682b 4070
b4ff3a36 4071 u8 reserved_at_a0[0x8];
7486216b 4072 u8 srqn_xrqn[0x18];
e281682b 4073
b4ff3a36 4074 u8 reserved_at_c0[0x8];
e281682b
SM		 4075 u8 pd[0x18];
4076
4077 u8 tclass[0x8];
b4ff3a36 4078 u8 reserved_at_e8[0x4];
e281682b
SM		 4079 u8 flow_label[0x14];
4080
4081 u8 dc_access_key[0x40];
4082
b4ff3a36 4083 u8 reserved_at_140[0x5];
e281682b
SM		 4084 u8 mtu[0x3];
4085 u8 port[0x8];
4086 u8 pkey_index[0x10];
4087
b4ff3a36 4088 u8 reserved_at_160[0x8];
e281682b 4089 u8 my_addr_index[0x8];
b4ff3a36 4090 u8 reserved_at_170[0x8];
e281682b
SM		 4091 u8 hop_limit[0x8];
4092
4093 u8 dc_access_key_violation_count[0x20];
4094
b4ff3a36 4095 u8 reserved_at_1a0[0x14];
e281682b
SM		 4096 u8 dei_cfi[0x1];
4097 u8 eth_prio[0x3];
4098 u8 ecn[0x2];
4099 u8 dscp[0x6];
4100
a645a89d
LR		 4101 u8 reserved_at_1c0[0x20];
4102 u8 ece[0x20];
e281682b
SM		 4103};
4104
4105enum {
4106 MLX5_CQC_STATUS_OK = 0x0,
4107 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4108 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4109};
4110
4111enum {
4112 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4113 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4114};
4115
4116enum {
4117 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4118 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4119 MLX5_CQC_ST_FIRED = 0xa,
4120};
4121
7d5e1423
SM		 4122enum {
4123 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4124 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 4125 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 4126};
4127
e281682b
SM		 4128struct mlx5_ifc_cqc_bits {
4129 u8 status[0x4];
bd371975
LR		 4130 u8 reserved_at_4[0x2];
4131 u8 dbr_umem_valid[0x1];
616d5769 4132 u8 apu_cq[0x1];
e281682b
SM		 4133 u8 cqe_sz[0x3];
4134 u8 cc[0x1];
b4ff3a36 4135 u8 reserved_at_c[0x1];
e281682b
SM		 4136 u8 scqe_break_moderation_en[0x1];
4137 u8 oi[0x1];
7d5e1423
SM		 4138 u8 cq_period_mode[0x2];
4139 u8 cqe_comp_en[0x1];
e281682b
SM		 4140 u8 mini_cqe_res_format[0x2];
4141 u8 st[0x4];
b4ff3a36 4142 u8 reserved_at_18[0x8];
e281682b 4143
b4ff3a36 4144 u8 reserved_at_20[0x20];
e281682b 4145
b4ff3a36 4146 u8 reserved_at_40[0x14];
e281682b 4147 u8 page_offset[0x6];
b4ff3a36 4148 u8 reserved_at_5a[0x6];
e281682b 4149
b4ff3a36 4150 u8 reserved_at_60[0x3];
e281682b
SM		 4151 u8 log_cq_size[0x5];
4152 u8 uar_page[0x18];
4153
b4ff3a36 4154 u8 reserved_at_80[0x4];
e281682b
SM		 4155 u8 cq_period[0xc];
4156 u8 cq_max_count[0x10];
4157
616d5769 4158 u8 c_eqn_or_apu_element[0x20];
e281682b 4159
b4ff3a36 4160 u8 reserved_at_c0[0x3];
e281682b 4161 u8 log_page_size[0x5];
b4ff3a36 4162 u8 reserved_at_c8[0x18];
e281682b 4163
b4ff3a36 4164 u8 reserved_at_e0[0x20];
e281682b 4165
b4ff3a36 4166 u8 reserved_at_100[0x8];
e281682b
SM		 4167 u8 last_notified_index[0x18];
4168
b4ff3a36 4169 u8 reserved_at_120[0x8];
e281682b
SM		 4170 u8 last_solicit_index[0x18];
4171
b4ff3a36 4172 u8 reserved_at_140[0x8];
e281682b
SM		 4173 u8 consumer_counter[0x18];
4174
b4ff3a36 4175 u8 reserved_at_160[0x8];
e281682b
SM		 4176 u8 producer_counter[0x18];
4177
b4ff3a36 4178 u8 reserved_at_180[0x40];
e281682b
SM		 4179
4180 u8 dbr_addr[0x40];
4181};
4182
4183union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4184 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4185 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4186 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 4187 u8 reserved_at_0[0x800];
e281682b
SM		 4188};
4189
4190struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 4191 u8 reserved_at_0[0xc0];
e281682b 4192
b4ff3a36 4193 u8 reserved_at_c0[0x8];
211e6c80
MD		 4194 u8 ieee_vendor_id[0x18];
4195
b4ff3a36 4196 u8 reserved_at_e0[0x10];
e281682b
SM		 4197 u8 vsd_vendor_id[0x10];
4198
4199 u8 vsd[208][0x8];
4200
4201 u8 vsd_contd_psid[16][0x8];
4202};
4203
7486216b
SM		 4204enum {
4205 MLX5_XRQC_STATE_GOOD = 0x0,
4206 MLX5_XRQC_STATE_ERROR = 0x1,
4207};
4208
4209enum {
4210 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4211 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4212};
4213
4214enum {
4215 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4216};
4217
4218struct mlx5_ifc_tag_matching_topology_context_bits {
4219 u8 log_matching_list_sz[0x4];
4220 u8 reserved_at_4[0xc];
4221 u8 append_next_index[0x10];
4222
4223 u8 sw_phase_cnt[0x10];
4224 u8 hw_phase_cnt[0x10];
4225
4226 u8 reserved_at_40[0x40];
4227};
4228
4229struct mlx5_ifc_xrqc_bits {
4230 u8 state[0x4];
4231 u8 rlkey[0x1];
4232 u8 reserved_at_5[0xf];
4233 u8 topology[0x4];
4234 u8 reserved_at_18[0x4];
4235 u8 offload[0x4];
4236
4237 u8 reserved_at_20[0x8];
4238 u8 user_index[0x18];
4239
4240 u8 reserved_at_40[0x8];
4241 u8 cqn[0x18];
4242
4243 u8 reserved_at_60[0xa0];
4244
4245 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4246
6e44636a 4247 u8 reserved_at_180[0x280];
7486216b
SM		 4248
4249 struct mlx5_ifc_wq_bits wq;
4250};
4251
e281682b
SM		 4252union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4253 struct mlx5_ifc_modify_field_select_bits modify_field_select;
4254 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 4255 u8 reserved_at_0[0x20];
e281682b
SM		 4256};
4257
4258union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4259 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4260 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4261 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 4262 u8 reserved_at_0[0x20];
e281682b
SM		 4263};
4264
4265union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4266 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4267 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4268 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4269 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4270 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4271 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 4272 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4273 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
1c64bf6f 4274 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 4275 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 4276 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 4277 u8 reserved_at_0[0x7c0];
e281682b
SM		 4278};
4279
8ed1a630
GP		 4280union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4281 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4282 u8 reserved_at_0[0x7c0];
4283};
4284
e281682b
SM		 4285union mlx5_ifc_event_auto_bits {
4286 struct mlx5_ifc_comp_event_bits comp_event;
4287 struct mlx5_ifc_dct_events_bits dct_events;
4288 struct mlx5_ifc_qp_events_bits qp_events;
4289 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4290 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4291 struct mlx5_ifc_cq_error_bits cq_error;
4292 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4293 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4294 struct mlx5_ifc_gpio_event_bits gpio_event;
4295 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4296 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4297 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 4298 u8 reserved_at_0[0xe0];
e281682b
SM		 4299};
4300
4301struct mlx5_ifc_health_buffer_bits {
b4ff3a36 4302 u8 reserved_at_0[0x100];
e281682b
SM		 4303
4304 u8 assert_existptr[0x20];
4305
4306 u8 assert_callra[0x20];
4307
cb464ba5
AL		 4308 u8 reserved_at_140[0x20];
4309
4310 u8 time[0x20];
e281682b
SM		 4311
4312 u8 fw_version[0x20];
4313
4314 u8 hw_id[0x20];
4315
cb464ba5
AL		 4316 u8 rfr[0x1];
4317 u8 reserved_at_1c1[0x3];
4318 u8 valid[0x1];
4319 u8 severity[0x3];
4320 u8 reserved_at_1c8[0x18];
e281682b
SM		 4321
4322 u8 irisc_index[0x8];
4323 u8 synd[0x8];
4324 u8 ext_synd[0x10];
4325};
4326
4327struct mlx5_ifc_register_loopback_control_bits {
4328 u8 no_lb[0x1];
b4ff3a36 4329 u8 reserved_at_1[0x7];
e281682b 4330 u8 port[0x8];
b4ff3a36 4331 u8 reserved_at_10[0x10];
e281682b 4332
b4ff3a36 4333 u8 reserved_at_20[0x60];
e281682b
SM		 4334};
4335
813f8540
MHY		 4336struct mlx5_ifc_vport_tc_element_bits {
4337 u8 traffic_class[0x4];
4338 u8 reserved_at_4[0xc];
4339 u8 vport_number[0x10];
4340};
4341
4342struct mlx5_ifc_vport_element_bits {
4343 u8 reserved_at_0[0x10];
4344 u8 vport_number[0x10];
4345};
4346
4347enum {
4348 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4349 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4350 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4351};
4352
4353struct mlx5_ifc_tsar_element_bits {
4354 u8 reserved_at_0[0x8];
4355 u8 tsar_type[0x8];
4356 u8 reserved_at_10[0x10];
4357};
4358
8812c24d
MD		 4359enum {
4360 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4361 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4362};
4363
e281682b
SM		 4364struct mlx5_ifc_teardown_hca_out_bits {
4365 u8 status[0x8];
b4ff3a36 4366 u8 reserved_at_8[0x18];
e281682b
SM		 4367
4368 u8 syndrome[0x20];
4369
8812c24d
MD		 4370 u8 reserved_at_40[0x3f];
4371
fcd29ad1 4372 u8 state[0x1];
e281682b
SM		 4373};
4374
4375enum {
4376 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 4377 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 4378 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 4379};
4380
4381struct mlx5_ifc_teardown_hca_in_bits {
4382 u8 opcode[0x10];
b4ff3a36 4383 u8 reserved_at_10[0x10];
e281682b 4384
b4ff3a36 4385 u8 reserved_at_20[0x10];
e281682b
SM		 4386 u8 op_mod[0x10];
4387
b4ff3a36 4388 u8 reserved_at_40[0x10];
e281682b
SM		 4389 u8 profile[0x10];
4390
b4ff3a36 4391 u8 reserved_at_60[0x20];
e281682b
SM		 4392};
4393
4394struct mlx5_ifc_sqerr2rts_qp_out_bits {
4395 u8 status[0x8];
b4ff3a36 4396 u8 reserved_at_8[0x18];
e281682b
SM		 4397
4398 u8 syndrome[0x20];
4399
b4ff3a36 4400 u8 reserved_at_40[0x40];
e281682b
SM		 4401};
4402
4403struct mlx5_ifc_sqerr2rts_qp_in_bits {
4404 u8 opcode[0x10];
4ac63ec7 4405 u8 uid[0x10];
e281682b 4406
b4ff3a36 4407 u8 reserved_at_20[0x10];
e281682b
SM		 4408 u8 op_mod[0x10];
4409
b4ff3a36 4410 u8 reserved_at_40[0x8];
e281682b
SM		 4411 u8 qpn[0x18];
4412
b4ff3a36 4413 u8 reserved_at_60[0x20];
e281682b
SM		 4414
4415 u8 opt_param_mask[0x20];
4416
b4ff3a36 4417 u8 reserved_at_a0[0x20];
e281682b
SM		 4418
4419 struct mlx5_ifc_qpc_bits qpc;
4420
b4ff3a36 4421 u8 reserved_at_800[0x80];
e281682b
SM		 4422};
4423
4424struct mlx5_ifc_sqd2rts_qp_out_bits {
4425 u8 status[0x8];
b4ff3a36 4426 u8 reserved_at_8[0x18];
e281682b
SM		 4427
4428 u8 syndrome[0x20];
4429
b4ff3a36 4430 u8 reserved_at_40[0x40];
e281682b
SM		 4431};
4432
4433struct mlx5_ifc_sqd2rts_qp_in_bits {
4434 u8 opcode[0x10];
4ac63ec7 4435 u8 uid[0x10];
e281682b 4436
b4ff3a36 4437 u8 reserved_at_20[0x10];
e281682b
SM		 4438 u8 op_mod[0x10];
4439
b4ff3a36 4440 u8 reserved_at_40[0x8];
e281682b
SM		 4441 u8 qpn[0x18];
4442
b4ff3a36 4443 u8 reserved_at_60[0x20];
e281682b
SM		 4444
4445 u8 opt_param_mask[0x20];
4446
b4ff3a36 4447 u8 reserved_at_a0[0x20];
e281682b
SM		 4448
4449 struct mlx5_ifc_qpc_bits qpc;
4450
b4ff3a36 4451 u8 reserved_at_800[0x80];
e281682b
SM		 4452};
4453
4454struct mlx5_ifc_set_roce_address_out_bits {
4455 u8 status[0x8];
b4ff3a36 4456 u8 reserved_at_8[0x18];
e281682b
SM		 4457
4458 u8 syndrome[0x20];
4459
b4ff3a36 4460 u8 reserved_at_40[0x40];
e281682b
SM		 4461};
4462
4463struct mlx5_ifc_set_roce_address_in_bits {
4464 u8 opcode[0x10];
b4ff3a36 4465 u8 reserved_at_10[0x10];
e281682b 4466
b4ff3a36 4467 u8 reserved_at_20[0x10];
e281682b
SM		 4468 u8 op_mod[0x10];
4469
4470 u8 roce_address_index[0x10];
32f69e4b
DJ		 4471 u8 reserved_at_50[0xc];
4472 u8 vhca_port_num[0x4];
e281682b 4473
b4ff3a36 4474 u8 reserved_at_60[0x20];
e281682b
SM		 4475
4476 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4477};
4478
4479struct mlx5_ifc_set_mad_demux_out_bits {
4480 u8 status[0x8];
b4ff3a36 4481 u8 reserved_at_8[0x18];
e281682b
SM		 4482
4483 u8 syndrome[0x20];
4484
b4ff3a36 4485 u8 reserved_at_40[0x40];
e281682b
SM		 4486};
4487
4488enum {
4489 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4490 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4491};
4492
4493struct mlx5_ifc_set_mad_demux_in_bits {
4494 u8 opcode[0x10];
b4ff3a36 4495 u8 reserved_at_10[0x10];
e281682b 4496
b4ff3a36 4497 u8 reserved_at_20[0x10];
e281682b
SM		 4498 u8 op_mod[0x10];
4499
b4ff3a36 4500 u8 reserved_at_40[0x20];
e281682b 4501
b4ff3a36 4502 u8 reserved_at_60[0x6];
e281682b 4503 u8 demux_mode[0x2];
b4ff3a36 4504 u8 reserved_at_68[0x18];
e281682b
SM		 4505};
4506
4507struct mlx5_ifc_set_l2_table_entry_out_bits {
4508 u8 status[0x8];
b4ff3a36 4509 u8 reserved_at_8[0x18];
e281682b
SM		 4510
4511 u8 syndrome[0x20];
4512
b4ff3a36 4513 u8 reserved_at_40[0x40];
e281682b
SM		 4514};
4515
4516struct mlx5_ifc_set_l2_table_entry_in_bits {
4517 u8 opcode[0x10];
b4ff3a36 4518 u8 reserved_at_10[0x10];
e281682b 4519
b4ff3a36 4520 u8 reserved_at_20[0x10];
e281682b
SM		 4521 u8 op_mod[0x10];
4522
b4ff3a36 4523 u8 reserved_at_40[0x60];
e281682b 4524
b4ff3a36 4525 u8 reserved_at_a0[0x8];
e281682b
SM		 4526 u8 table_index[0x18];
4527
b4ff3a36 4528 u8 reserved_at_c0[0x20];
e281682b 4529
b4ff3a36 4530 u8 reserved_at_e0[0x13];
e281682b
SM		 4531 u8 vlan_valid[0x1];
4532 u8 vlan[0xc];
4533
4534 struct mlx5_ifc_mac_address_layout_bits mac_address;
4535
b4ff3a36 4536 u8 reserved_at_140[0xc0];
e281682b
SM		 4537};
4538
4539struct mlx5_ifc_set_issi_out_bits {
4540 u8 status[0x8];
b4ff3a36 4541 u8 reserved_at_8[0x18];
e281682b
SM		 4542
4543 u8 syndrome[0x20];
4544
b4ff3a36 4545 u8 reserved_at_40[0x40];
e281682b
SM		 4546};
4547
4548struct mlx5_ifc_set_issi_in_bits {
4549 u8 opcode[0x10];
b4ff3a36 4550 u8 reserved_at_10[0x10];
e281682b 4551
b4ff3a36 4552 u8 reserved_at_20[0x10];
e281682b
SM		 4553 u8 op_mod[0x10];
4554
b4ff3a36 4555 u8 reserved_at_40[0x10];
e281682b
SM		 4556 u8 current_issi[0x10];
4557
b4ff3a36 4558 u8 reserved_at_60[0x20];
e281682b
SM		 4559};
4560
4561struct mlx5_ifc_set_hca_cap_out_bits {
4562 u8 status[0x8];
b4ff3a36 4563 u8 reserved_at_8[0x18];
e281682b
SM		 4564
4565 u8 syndrome[0x20];
4566
b4ff3a36 4567 u8 reserved_at_40[0x40];
e281682b
SM		 4568};
4569
4570struct mlx5_ifc_set_hca_cap_in_bits {
4571 u8 opcode[0x10];
b4ff3a36 4572 u8 reserved_at_10[0x10];
e281682b 4573
b4ff3a36 4574 u8 reserved_at_20[0x10];
e281682b
SM		 4575 u8 op_mod[0x10];
4576
959af556
YH		 4577 u8 other_function[0x1];
4578 u8 reserved_at_41[0xf];
4579 u8 function_id[0x10];
4580
4581 u8 reserved_at_60[0x20];
e281682b
SM		 4582
4583 union mlx5_ifc_hca_cap_union_bits capability;
4584};
4585
26a81453
MG		 4586enum {
4587 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4588 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4589 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2b58f6d9
RS		 4590 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4591 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
26a81453
MG		 4592};
4593
e281682b
SM		 4594struct mlx5_ifc_set_fte_out_bits {
4595 u8 status[0x8];
b4ff3a36 4596 u8 reserved_at_8[0x18];
e281682b
SM		 4597
4598 u8 syndrome[0x20];
4599
b4ff3a36 4600 u8 reserved_at_40[0x40];
e281682b
SM		 4601};
4602
4603struct mlx5_ifc_set_fte_in_bits {
4604 u8 opcode[0x10];
b4ff3a36 4605 u8 reserved_at_10[0x10];
e281682b 4606
b4ff3a36 4607 u8 reserved_at_20[0x10];
e281682b
SM		 4608 u8 op_mod[0x10];
4609
7d5e1423
SM		 4610 u8 other_vport[0x1];
4611 u8 reserved_at_41[0xf];
4612 u8 vport_number[0x10];
4613
4614 u8 reserved_at_60[0x20];
e281682b
SM		 4615
4616 u8 table_type[0x8];
b4ff3a36 4617 u8 reserved_at_88[0x18];
e281682b 4618
b4ff3a36 4619 u8 reserved_at_a0[0x8];
e281682b
SM		 4620 u8 table_id[0x18];
4621
822e114b
PB		 4622 u8 ignore_flow_level[0x1];
4623 u8 reserved_at_c1[0x17];
26a81453
MG		 4624 u8 modify_enable_mask[0x8];
4625
b4ff3a36 4626 u8 reserved_at_e0[0x20];
e281682b
SM		 4627
4628 u8 flow_index[0x20];
4629
b4ff3a36 4630 u8 reserved_at_120[0xe0];
e281682b
SM		 4631
4632 struct mlx5_ifc_flow_context_bits flow_context;
4633};
4634
4635struct mlx5_ifc_rts2rts_qp_out_bits {
4636 u8 status[0x8];
b4ff3a36 4637 u8 reserved_at_8[0x18];
e281682b
SM		 4638
4639 u8 syndrome[0x20];
4640
6b646a7e
LR		 4641 u8 reserved_at_40[0x20];
4642 u8 ece[0x20];
e281682b
SM		 4643};
4644
4645struct mlx5_ifc_rts2rts_qp_in_bits {
4646 u8 opcode[0x10];
4ac63ec7 4647 u8 uid[0x10];
e281682b 4648
b4ff3a36 4649 u8 reserved_at_20[0x10];
e281682b
SM		 4650 u8 op_mod[0x10];
4651
b4ff3a36 4652 u8 reserved_at_40[0x8];
e281682b
SM		 4653 u8 qpn[0x18];
4654
b4ff3a36 4655 u8 reserved_at_60[0x20];
e281682b
SM		 4656
4657 u8 opt_param_mask[0x20];
4658
6b646a7e 4659 u8 ece[0x20];
e281682b
SM		 4660
4661 struct mlx5_ifc_qpc_bits qpc;
4662
b4ff3a36 4663 u8 reserved_at_800[0x80];
e281682b
SM		 4664};
4665
4666struct mlx5_ifc_rtr2rts_qp_out_bits {
4667 u8 status[0x8];
b4ff3a36 4668 u8 reserved_at_8[0x18];
e281682b
SM		 4669
4670 u8 syndrome[0x20];
4671
6b646a7e
LR		 4672 u8 reserved_at_40[0x20];
4673 u8 ece[0x20];
e281682b
SM		 4674};
4675
4676struct mlx5_ifc_rtr2rts_qp_in_bits {
4677 u8 opcode[0x10];
4ac63ec7 4678 u8 uid[0x10];
e281682b 4679
b4ff3a36 4680 u8 reserved_at_20[0x10];
e281682b
SM		 4681 u8 op_mod[0x10];
4682
b4ff3a36 4683 u8 reserved_at_40[0x8];
e281682b
SM		 4684 u8 qpn[0x18];
4685
b4ff3a36 4686 u8 reserved_at_60[0x20];
e281682b
SM		 4687
4688 u8 opt_param_mask[0x20];
4689
6b646a7e 4690 u8 ece[0x20];
e281682b
SM		 4691
4692 struct mlx5_ifc_qpc_bits qpc;
4693
b4ff3a36 4694 u8 reserved_at_800[0x80];
e281682b
SM		 4695};
4696
4697struct mlx5_ifc_rst2init_qp_out_bits {
4698 u8 status[0x8];
b4ff3a36 4699 u8 reserved_at_8[0x18];
e281682b
SM		 4700
4701 u8 syndrome[0x20];
4702
ab183d46
LR		 4703 u8 reserved_at_40[0x20];
4704 u8 ece[0x20];
e281682b
SM		 4705};
4706
4707struct mlx5_ifc_rst2init_qp_in_bits {
4708 u8 opcode[0x10];
4ac63ec7 4709 u8 uid[0x10];
e281682b 4710
b4ff3a36 4711 u8 reserved_at_20[0x10];
e281682b
SM		 4712 u8 op_mod[0x10];
4713
b4ff3a36 4714 u8 reserved_at_40[0x8];
e281682b
SM		 4715 u8 qpn[0x18];
4716
b4ff3a36 4717 u8 reserved_at_60[0x20];
e281682b
SM		 4718
4719 u8 opt_param_mask[0x20];
4720
ab183d46 4721 u8 ece[0x20];
e281682b
SM		 4722
4723 struct mlx5_ifc_qpc_bits qpc;
4724
b4ff3a36 4725 u8 reserved_at_800[0x80];
e281682b
SM		 4726};
4727
7486216b
SM		 4728struct mlx5_ifc_query_xrq_out_bits {
4729 u8 status[0x8];
4730 u8 reserved_at_8[0x18];
4731
4732 u8 syndrome[0x20];
4733
4734 u8 reserved_at_40[0x40];
4735
4736 struct mlx5_ifc_xrqc_bits xrq_context;
4737};
4738
4739struct mlx5_ifc_query_xrq_in_bits {
4740 u8 opcode[0x10];
4741 u8 reserved_at_10[0x10];
4742
4743 u8 reserved_at_20[0x10];
4744 u8 op_mod[0x10];
4745
4746 u8 reserved_at_40[0x8];
4747 u8 xrqn[0x18];
4748
4749 u8 reserved_at_60[0x20];
4750};
4751
e281682b
SM		 4752struct mlx5_ifc_query_xrc_srq_out_bits {
4753 u8 status[0x8];
b4ff3a36 4754 u8 reserved_at_8[0x18];
e281682b
SM		 4755
4756 u8 syndrome[0x20];
4757
b4ff3a36 4758 u8 reserved_at_40[0x40];
e281682b
SM		 4759
4760 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4761
b4ff3a36 4762 u8 reserved_at_280[0x600];
e281682b 4763
b6ca09cb 4764 u8 pas[][0x40];
e281682b
SM		 4765};
4766
4767struct mlx5_ifc_query_xrc_srq_in_bits {
4768 u8 opcode[0x10];
b4ff3a36 4769 u8 reserved_at_10[0x10];
e281682b 4770
b4ff3a36 4771 u8 reserved_at_20[0x10];
e281682b
SM		 4772 u8 op_mod[0x10];
4773
b4ff3a36 4774 u8 reserved_at_40[0x8];
e281682b
SM		 4775 u8 xrc_srqn[0x18];
4776
b4ff3a36 4777 u8 reserved_at_60[0x20];
e281682b
SM		 4778};
4779
4780enum {
4781 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4782 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4783};
4784
4785struct mlx5_ifc_query_vport_state_out_bits {
4786 u8 status[0x8];
b4ff3a36 4787 u8 reserved_at_8[0x18];
e281682b
SM		 4788
4789 u8 syndrome[0x20];
4790
b4ff3a36 4791 u8 reserved_at_40[0x20];
e281682b 4792
b4ff3a36 4793 u8 reserved_at_60[0x18];
e281682b
SM		 4794 u8 admin_state[0x4];
4795 u8 state[0x4];
4796};
4797
4798enum {
cc9c82a8
EBE		 4799 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4800 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
7d0314b1 4801 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
e281682b
SM		 4802};
4803
fd4572b3
ED		 4804struct mlx5_ifc_arm_monitor_counter_in_bits {
4805 u8 opcode[0x10];
4806 u8 uid[0x10];
4807
4808 u8 reserved_at_20[0x10];
4809 u8 op_mod[0x10];
4810
4811 u8 reserved_at_40[0x20];
4812
4813 u8 reserved_at_60[0x20];
4814};
4815
4816struct mlx5_ifc_arm_monitor_counter_out_bits {
4817 u8 status[0x8];
4818 u8 reserved_at_8[0x18];
4819
4820 u8 syndrome[0x20];
4821
4822 u8 reserved_at_40[0x40];
4823};
4824
4825enum {
4826 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4827 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4828};
4829
4830enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 4831 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4832 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4833 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4834 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4835 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4836 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 4837};
4838
4839enum {
4c8b8518 4840 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 4841};
4842
4843struct mlx5_ifc_monitor_counter_output_bits {
4844 u8 reserved_at_0[0x4];
4845 u8 type[0x4];
4846 u8 reserved_at_8[0x8];
4847 u8 counter[0x10];
4848
4849 u8 counter_group_id[0x20];
4850};
4851
4852#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4853#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4854#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4855 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4856
4857struct mlx5_ifc_set_monitor_counter_in_bits {
4858 u8 opcode[0x10];
4859 u8 uid[0x10];
4860
4861 u8 reserved_at_20[0x10];
4862 u8 op_mod[0x10];
4863
4864 u8 reserved_at_40[0x10];
4865 u8 num_of_counters[0x10];
4866
4867 u8 reserved_at_60[0x20];
4868
4869 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4870};
4871
4872struct mlx5_ifc_set_monitor_counter_out_bits {
4873 u8 status[0x8];
4874 u8 reserved_at_8[0x18];
4875
4876 u8 syndrome[0x20];
4877
4878 u8 reserved_at_40[0x40];
4879};
4880
e281682b
SM		 4881struct mlx5_ifc_query_vport_state_in_bits {
4882 u8 opcode[0x10];
b4ff3a36 4883 u8 reserved_at_10[0x10];
e281682b 4884
b4ff3a36 4885 u8 reserved_at_20[0x10];
e281682b
SM		 4886 u8 op_mod[0x10];
4887
4888 u8 other_vport[0x1];
b4ff3a36 4889 u8 reserved_at_41[0xf];
e281682b
SM		 4890 u8 vport_number[0x10];
4891
b4ff3a36 4892 u8 reserved_at_60[0x20];
e281682b
SM		 4893};
4894
61c5b5c9
MS		 4895struct mlx5_ifc_query_vnic_env_out_bits {
4896 u8 status[0x8];
4897 u8 reserved_at_8[0x18];
4898
4899 u8 syndrome[0x20];
4900
4901 u8 reserved_at_40[0x40];
4902
4903 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4904};
4905
4906enum {
4907 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4908};
4909
4910struct mlx5_ifc_query_vnic_env_in_bits {
4911 u8 opcode[0x10];
4912 u8 reserved_at_10[0x10];
4913
4914 u8 reserved_at_20[0x10];
4915 u8 op_mod[0x10];
4916
4917 u8 other_vport[0x1];
4918 u8 reserved_at_41[0xf];
4919 u8 vport_number[0x10];
4920
4921 u8 reserved_at_60[0x20];
4922};
4923
e281682b
SM		 4924struct mlx5_ifc_query_vport_counter_out_bits {
4925 u8 status[0x8];
b4ff3a36 4926 u8 reserved_at_8[0x18];
e281682b
SM		 4927
4928 u8 syndrome[0x20];
4929
b4ff3a36 4930 u8 reserved_at_40[0x40];
e281682b
SM		 4931
4932 struct mlx5_ifc_traffic_counter_bits received_errors;
4933
4934 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4935
4936 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4937
4938 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4939
4940 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4941
4942 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4943
4944 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4945
4946 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4947
4948 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4949
4950 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4951
4952 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4953
4954 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4955
b4ff3a36 4956 u8 reserved_at_680[0xa00];
e281682b
SM		 4957};
4958
4959enum {
4960 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4961};
4962
4963struct mlx5_ifc_query_vport_counter_in_bits {
4964 u8 opcode[0x10];
b4ff3a36 4965 u8 reserved_at_10[0x10];
e281682b 4966
b4ff3a36 4967 u8 reserved_at_20[0x10];
e281682b
SM		 4968 u8 op_mod[0x10];
4969
4970 u8 other_vport[0x1];
b54ba277
MY		 4971 u8 reserved_at_41[0xb];
4972 u8 port_num[0x4];
e281682b
SM		 4973 u8 vport_number[0x10];
4974
b4ff3a36 4975 u8 reserved_at_60[0x60];
e281682b
SM		 4976
4977 u8 clear[0x1];
b4ff3a36 4978 u8 reserved_at_c1[0x1f];
e281682b 4979
b4ff3a36 4980 u8 reserved_at_e0[0x20];
e281682b
SM		 4981};
4982
4983struct mlx5_ifc_query_tis_out_bits {
4984 u8 status[0x8];
b4ff3a36 4985 u8 reserved_at_8[0x18];
e281682b
SM		 4986
4987 u8 syndrome[0x20];
4988
b4ff3a36 4989 u8 reserved_at_40[0x40];
e281682b
SM		 4990
4991 struct mlx5_ifc_tisc_bits tis_context;
4992};
4993
4994struct mlx5_ifc_query_tis_in_bits {
4995 u8 opcode[0x10];
b4ff3a36 4996 u8 reserved_at_10[0x10];
e281682b 4997
b4ff3a36 4998 u8 reserved_at_20[0x10];
e281682b
SM		 4999 u8 op_mod[0x10];
5000
b4ff3a36 5001 u8 reserved_at_40[0x8];
e281682b
SM		 5002 u8 tisn[0x18];
5003
b4ff3a36 5004 u8 reserved_at_60[0x20];
e281682b
SM		 5005};
5006
5007struct mlx5_ifc_query_tir_out_bits {
5008 u8 status[0x8];
b4ff3a36 5009 u8 reserved_at_8[0x18];
e281682b
SM		 5010
5011 u8 syndrome[0x20];
5012
b4ff3a36 5013 u8 reserved_at_40[0xc0];
e281682b
SM		 5014
5015 struct mlx5_ifc_tirc_bits tir_context;
5016};
5017
5018struct mlx5_ifc_query_tir_in_bits {
5019 u8 opcode[0x10];
b4ff3a36 5020 u8 reserved_at_10[0x10];
e281682b 5021
b4ff3a36 5022 u8 reserved_at_20[0x10];
e281682b
SM		 5023 u8 op_mod[0x10];
5024
b4ff3a36 5025 u8 reserved_at_40[0x8];
e281682b
SM		 5026 u8 tirn[0x18];
5027
b4ff3a36 5028 u8 reserved_at_60[0x20];
e281682b
SM		 5029};
5030
5031struct mlx5_ifc_query_srq_out_bits {
5032 u8 status[0x8];
b4ff3a36 5033 u8 reserved_at_8[0x18];
e281682b
SM		 5034
5035 u8 syndrome[0x20];
5036
b4ff3a36 5037 u8 reserved_at_40[0x40];
e281682b
SM		 5038
5039 struct mlx5_ifc_srqc_bits srq_context_entry;
5040
b4ff3a36 5041 u8 reserved_at_280[0x600];
e281682b 5042
b6ca09cb 5043 u8 pas[][0x40];
e281682b
SM		 5044};
5045
5046struct mlx5_ifc_query_srq_in_bits {
5047 u8 opcode[0x10];
b4ff3a36 5048 u8 reserved_at_10[0x10];
e281682b 5049
b4ff3a36 5050 u8 reserved_at_20[0x10];
e281682b
SM		 5051 u8 op_mod[0x10];
5052
b4ff3a36 5053 u8 reserved_at_40[0x8];
e281682b
SM		 5054 u8 srqn[0x18];
5055
b4ff3a36 5056 u8 reserved_at_60[0x20];
e281682b
SM		 5057};
5058
5059struct mlx5_ifc_query_sq_out_bits {
5060 u8 status[0x8];
b4ff3a36 5061 u8 reserved_at_8[0x18];
e281682b
SM		 5062
5063 u8 syndrome[0x20];
5064
b4ff3a36 5065 u8 reserved_at_40[0xc0];
e281682b
SM		 5066
5067 struct mlx5_ifc_sqc_bits sq_context;
5068};
5069
5070struct mlx5_ifc_query_sq_in_bits {
5071 u8 opcode[0x10];
b4ff3a36 5072 u8 reserved_at_10[0x10];
e281682b 5073
b4ff3a36 5074 u8 reserved_at_20[0x10];
e281682b
SM		 5075 u8 op_mod[0x10];
5076
b4ff3a36 5077 u8 reserved_at_40[0x8];
e281682b
SM		 5078 u8 sqn[0x18];
5079
b4ff3a36 5080 u8 reserved_at_60[0x20];
e281682b
SM		 5081};
5082
5083struct mlx5_ifc_query_special_contexts_out_bits {
5084 u8 status[0x8];
b4ff3a36 5085 u8 reserved_at_8[0x18];
e281682b
SM		 5086
5087 u8 syndrome[0x20];
5088
ec22eb53 5089 u8 dump_fill_mkey[0x20];
e281682b
SM		 5090
5091 u8 resd_lkey[0x20];
bcda1aca
AK		 5092
5093 u8 null_mkey[0x20];
5094
5095 u8 reserved_at_a0[0x60];
e281682b
SM		 5096};
5097
5098struct mlx5_ifc_query_special_contexts_in_bits {
5099 u8 opcode[0x10];
b4ff3a36 5100 u8 reserved_at_10[0x10];
e281682b 5101
b4ff3a36 5102 u8 reserved_at_20[0x10];
e281682b
SM		 5103 u8 op_mod[0x10];
5104
b4ff3a36 5105 u8 reserved_at_40[0x40];
e281682b
SM		 5106};
5107
813f8540
MHY		 5108struct mlx5_ifc_query_scheduling_element_out_bits {
5109 u8 opcode[0x10];
5110 u8 reserved_at_10[0x10];
5111
5112 u8 reserved_at_20[0x10];
5113 u8 op_mod[0x10];
5114
5115 u8 reserved_at_40[0xc0];
5116
5117 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5118
5119 u8 reserved_at_300[0x100];
5120};
5121
5122enum {
5123 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
214baf22 5124 SCHEDULING_HIERARCHY_NIC = 0x3,
813f8540
MHY		 5125};
5126
5127struct mlx5_ifc_query_scheduling_element_in_bits {
5128 u8 opcode[0x10];
5129 u8 reserved_at_10[0x10];
5130
5131 u8 reserved_at_20[0x10];
5132 u8 op_mod[0x10];
5133
5134 u8 scheduling_hierarchy[0x8];
5135 u8 reserved_at_48[0x18];
5136
5137 u8 scheduling_element_id[0x20];
5138
5139 u8 reserved_at_80[0x180];
5140};
5141
e281682b
SM		 5142struct mlx5_ifc_query_rqt_out_bits {
5143 u8 status[0x8];
b4ff3a36 5144 u8 reserved_at_8[0x18];
e281682b
SM		 5145
5146 u8 syndrome[0x20];
5147
b4ff3a36 5148 u8 reserved_at_40[0xc0];
e281682b
SM		 5149
5150 struct mlx5_ifc_rqtc_bits rqt_context;
5151};
5152
5153struct mlx5_ifc_query_rqt_in_bits {
5154 u8 opcode[0x10];
b4ff3a36 5155 u8 reserved_at_10[0x10];
e281682b 5156
b4ff3a36 5157 u8 reserved_at_20[0x10];
e281682b
SM		 5158 u8 op_mod[0x10];
5159
b4ff3a36 5160 u8 reserved_at_40[0x8];
e281682b
SM		 5161 u8 rqtn[0x18];
5162
b4ff3a36 5163 u8 reserved_at_60[0x20];
e281682b
SM		 5164};
5165
5166struct mlx5_ifc_query_rq_out_bits {
5167 u8 status[0x8];
b4ff3a36 5168 u8 reserved_at_8[0x18];
e281682b
SM		 5169
5170 u8 syndrome[0x20];
5171
b4ff3a36 5172 u8 reserved_at_40[0xc0];
e281682b
SM		 5173
5174 struct mlx5_ifc_rqc_bits rq_context;
5175};
5176
5177struct mlx5_ifc_query_rq_in_bits {
5178 u8 opcode[0x10];
b4ff3a36 5179 u8 reserved_at_10[0x10];
e281682b 5180
b4ff3a36 5181 u8 reserved_at_20[0x10];
e281682b
SM		 5182 u8 op_mod[0x10];
5183
b4ff3a36 5184 u8 reserved_at_40[0x8];
e281682b
SM		 5185 u8 rqn[0x18];
5186
b4ff3a36 5187 u8 reserved_at_60[0x20];
e281682b
SM		 5188};
5189
5190struct mlx5_ifc_query_roce_address_out_bits {
5191 u8 status[0x8];
b4ff3a36 5192 u8 reserved_at_8[0x18];
e281682b
SM		 5193
5194 u8 syndrome[0x20];
5195
b4ff3a36 5196 u8 reserved_at_40[0x40];
e281682b
SM		 5197
5198 struct mlx5_ifc_roce_addr_layout_bits roce_address;
5199};
5200
5201struct mlx5_ifc_query_roce_address_in_bits {
5202 u8 opcode[0x10];
b4ff3a36 5203 u8 reserved_at_10[0x10];
e281682b 5204
b4ff3a36 5205 u8 reserved_at_20[0x10];
e281682b
SM		 5206 u8 op_mod[0x10];
5207
5208 u8 roce_address_index[0x10];
32f69e4b
DJ		 5209 u8 reserved_at_50[0xc];
5210 u8 vhca_port_num[0x4];
e281682b 5211
b4ff3a36 5212 u8 reserved_at_60[0x20];
e281682b
SM		 5213};
5214
5215struct mlx5_ifc_query_rmp_out_bits {
5216 u8 status[0x8];
b4ff3a36 5217 u8 reserved_at_8[0x18];
e281682b
SM		 5218
5219 u8 syndrome[0x20];
5220
b4ff3a36 5221 u8 reserved_at_40[0xc0];
e281682b
SM		 5222
5223 struct mlx5_ifc_rmpc_bits rmp_context;
5224};
5225
5226struct mlx5_ifc_query_rmp_in_bits {
5227 u8 opcode[0x10];
b4ff3a36 5228 u8 reserved_at_10[0x10];
e281682b 5229
b4ff3a36 5230 u8 reserved_at_20[0x10];
e281682b
SM		 5231 u8 op_mod[0x10];
5232
b4ff3a36 5233 u8 reserved_at_40[0x8];
e281682b
SM		 5234 u8 rmpn[0x18];
5235
b4ff3a36 5236 u8 reserved_at_60[0x20];
e281682b
SM		 5237};
5238
5239struct mlx5_ifc_query_qp_out_bits {
5240 u8 status[0x8];
b4ff3a36 5241 u8 reserved_at_8[0x18];
e281682b
SM		 5242
5243 u8 syndrome[0x20];
5244
3fc2a9e8 5245 u8 reserved_at_40[0x40];
e281682b
SM		 5246
5247 u8 opt_param_mask[0x20];
5248
3fc2a9e8 5249 u8 ece[0x20];
e281682b
SM		 5250
5251 struct mlx5_ifc_qpc_bits qpc;
5252
b4ff3a36 5253 u8 reserved_at_800[0x80];
e281682b 5254
b6ca09cb 5255 u8 pas[][0x40];
e281682b
SM		 5256};
5257
5258struct mlx5_ifc_query_qp_in_bits {
5259 u8 opcode[0x10];
b4ff3a36 5260 u8 reserved_at_10[0x10];
e281682b 5261
b4ff3a36 5262 u8 reserved_at_20[0x10];
e281682b
SM		 5263 u8 op_mod[0x10];
5264
b4ff3a36 5265 u8 reserved_at_40[0x8];
e281682b
SM		 5266 u8 qpn[0x18];
5267
b4ff3a36 5268 u8 reserved_at_60[0x20];
e281682b
SM		 5269};
5270
5271struct mlx5_ifc_query_q_counter_out_bits {
5272 u8 status[0x8];
b4ff3a36 5273 u8 reserved_at_8[0x18];
e281682b
SM		 5274
5275 u8 syndrome[0x20];
5276
b4ff3a36 5277 u8 reserved_at_40[0x40];
e281682b
SM		 5278
5279 u8 rx_write_requests[0x20];
5280
b4ff3a36 5281 u8 reserved_at_a0[0x20];
e281682b
SM		 5282
5283 u8 rx_read_requests[0x20];
5284
b4ff3a36 5285 u8 reserved_at_e0[0x20];
e281682b
SM		 5286
5287 u8 rx_atomic_requests[0x20];
5288
b4ff3a36 5289 u8 reserved_at_120[0x20];
e281682b
SM		 5290
5291 u8 rx_dct_connect[0x20];
5292
b4ff3a36 5293 u8 reserved_at_160[0x20];
e281682b
SM		 5294
5295 u8 out_of_buffer[0x20];
5296
b4ff3a36 5297 u8 reserved_at_1a0[0x20];
e281682b
SM		 5298
5299 u8 out_of_sequence[0x20];
5300
7486216b
SM		 5301 u8 reserved_at_1e0[0x20];
5302
5303 u8 duplicate_request[0x20];
5304
5305 u8 reserved_at_220[0x20];
5306
5307 u8 rnr_nak_retry_err[0x20];
5308
5309 u8 reserved_at_260[0x20];
5310
5311 u8 packet_seq_err[0x20];
5312
5313 u8 reserved_at_2a0[0x20];
5314
5315 u8 implied_nak_seq_err[0x20];
5316
5317 u8 reserved_at_2e0[0x20];
5318
5319 u8 local_ack_timeout_err[0x20];
5320
58dcb60a
PP		 5321 u8 reserved_at_320[0xa0];
5322
5323 u8 resp_local_length_error[0x20];
5324
5325 u8 req_local_length_error[0x20];
5326
5327 u8 resp_local_qp_error[0x20];
5328
5329 u8 local_operation_error[0x20];
5330
5331 u8 resp_local_protection[0x20];
5332
5333 u8 req_local_protection[0x20];
5334
5335 u8 resp_cqe_error[0x20];
5336
5337 u8 req_cqe_error[0x20];
5338
5339 u8 req_mw_binding[0x20];
5340
5341 u8 req_bad_response[0x20];
5342
5343 u8 req_remote_invalid_request[0x20];
5344
5345 u8 resp_remote_invalid_request[0x20];
5346
5347 u8 req_remote_access_errors[0x20];
5348
5349 u8 resp_remote_access_errors[0x20];
5350
5351 u8 req_remote_operation_errors[0x20];
5352
5353 u8 req_transport_retries_exceeded[0x20];
5354
5355 u8 cq_overflow[0x20];
5356
5357 u8 resp_cqe_flush_error[0x20];
5358
5359 u8 req_cqe_flush_error[0x20];
5360
8fd5b75d
LR		 5361 u8 reserved_at_620[0x20];
5362
5363 u8 roce_adp_retrans[0x20];
5364
5365 u8 roce_adp_retrans_to[0x20];
5366
5367 u8 roce_slow_restart[0x20];
5368
5369 u8 roce_slow_restart_cnps[0x20];
5370
5371 u8 roce_slow_restart_trans[0x20];
5372
5373 u8 reserved_at_6e0[0x120];
e281682b
SM		 5374};
5375
5376struct mlx5_ifc_query_q_counter_in_bits {
5377 u8 opcode[0x10];
b4ff3a36 5378 u8 reserved_at_10[0x10];
e281682b 5379
b4ff3a36 5380 u8 reserved_at_20[0x10];
e281682b
SM		 5381 u8 op_mod[0x10];
5382
b4ff3a36 5383 u8 reserved_at_40[0x80];
e281682b
SM		 5384
5385 u8 clear[0x1];
b4ff3a36 5386 u8 reserved_at_c1[0x1f];
e281682b 5387
b4ff3a36 5388 u8 reserved_at_e0[0x18];
e281682b
SM		 5389 u8 counter_set_id[0x8];
5390};
5391
5392struct mlx5_ifc_query_pages_out_bits {
5393 u8 status[0x8];
b4ff3a36 5394 u8 reserved_at_8[0x18];
e281682b
SM		 5395
5396 u8 syndrome[0x20];
5397
591905ba
BW		 5398 u8 embedded_cpu_function[0x1];
5399 u8 reserved_at_41[0xf];
e281682b
SM		 5400 u8 function_id[0x10];
5401
5402 u8 num_pages[0x20];
5403};
5404
5405enum {
5406 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5407 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5408 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5409};
5410
5411struct mlx5_ifc_query_pages_in_bits {
5412 u8 opcode[0x10];
b4ff3a36 5413 u8 reserved_at_10[0x10];
e281682b 5414
b4ff3a36 5415 u8 reserved_at_20[0x10];
e281682b
SM		 5416 u8 op_mod[0x10];
5417
591905ba
BW		 5418 u8 embedded_cpu_function[0x1];
5419 u8 reserved_at_41[0xf];
e281682b
SM		 5420 u8 function_id[0x10];
5421
b4ff3a36 5422 u8 reserved_at_60[0x20];
e281682b
SM		 5423};
5424
5425struct mlx5_ifc_query_nic_vport_context_out_bits {
5426 u8 status[0x8];
b4ff3a36 5427 u8 reserved_at_8[0x18];
e281682b
SM		 5428
5429 u8 syndrome[0x20];
5430
b4ff3a36 5431 u8 reserved_at_40[0x40];
e281682b
SM		 5432
5433 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5434};
5435
5436struct mlx5_ifc_query_nic_vport_context_in_bits {
5437 u8 opcode[0x10];
b4ff3a36 5438 u8 reserved_at_10[0x10];
e281682b 5439
b4ff3a36 5440 u8 reserved_at_20[0x10];
e281682b
SM		 5441 u8 op_mod[0x10];
5442
5443 u8 other_vport[0x1];
b4ff3a36 5444 u8 reserved_at_41[0xf];
e281682b
SM		 5445 u8 vport_number[0x10];
5446
b4ff3a36 5447 u8 reserved_at_60[0x5];
e281682b 5448 u8 allowed_list_type[0x3];
b4ff3a36 5449 u8 reserved_at_68[0x18];
e281682b
SM		 5450};
5451
5452struct mlx5_ifc_query_mkey_out_bits {
5453 u8 status[0x8];
b4ff3a36 5454 u8 reserved_at_8[0x18];
e281682b
SM		 5455
5456 u8 syndrome[0x20];
5457
b4ff3a36 5458 u8 reserved_at_40[0x40];
e281682b
SM		 5459
5460 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5461
b4ff3a36 5462 u8 reserved_at_280[0x600];
e281682b
SM		 5463
5464 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5465
5466 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5467};
5468
5469struct mlx5_ifc_query_mkey_in_bits {
5470 u8 opcode[0x10];
b4ff3a36 5471 u8 reserved_at_10[0x10];
e281682b 5472
b4ff3a36 5473 u8 reserved_at_20[0x10];
e281682b
SM		 5474 u8 op_mod[0x10];
5475
b4ff3a36 5476 u8 reserved_at_40[0x8];
e281682b
SM		 5477 u8 mkey_index[0x18];
5478
5479 u8 pg_access[0x1];
b4ff3a36 5480 u8 reserved_at_61[0x1f];
e281682b
SM		 5481};
5482
5483struct mlx5_ifc_query_mad_demux_out_bits {
5484 u8 status[0x8];
b4ff3a36 5485 u8 reserved_at_8[0x18];
e281682b
SM		 5486
5487 u8 syndrome[0x20];
5488
b4ff3a36 5489 u8 reserved_at_40[0x40];
e281682b
SM		 5490
5491 u8 mad_dumux_parameters_block[0x20];
5492};
5493
5494struct mlx5_ifc_query_mad_demux_in_bits {
5495 u8 opcode[0x10];
b4ff3a36 5496 u8 reserved_at_10[0x10];
e281682b 5497
b4ff3a36 5498 u8 reserved_at_20[0x10];
e281682b
SM		 5499 u8 op_mod[0x10];
5500
b4ff3a36 5501 u8 reserved_at_40[0x40];
e281682b
SM		 5502};
5503
5504struct mlx5_ifc_query_l2_table_entry_out_bits {
5505 u8 status[0x8];
b4ff3a36 5506 u8 reserved_at_8[0x18];
e281682b
SM		 5507
5508 u8 syndrome[0x20];
5509
b4ff3a36 5510 u8 reserved_at_40[0xa0];
e281682b 5511
b4ff3a36 5512 u8 reserved_at_e0[0x13];
e281682b
SM		 5513 u8 vlan_valid[0x1];
5514 u8 vlan[0xc];
5515
5516 struct mlx5_ifc_mac_address_layout_bits mac_address;
5517
b4ff3a36 5518 u8 reserved_at_140[0xc0];
e281682b
SM		 5519};
5520
5521struct mlx5_ifc_query_l2_table_entry_in_bits {
5522 u8 opcode[0x10];
b4ff3a36 5523 u8 reserved_at_10[0x10];
e281682b 5524
b4ff3a36 5525 u8 reserved_at_20[0x10];
e281682b
SM		 5526 u8 op_mod[0x10];
5527
b4ff3a36 5528 u8 reserved_at_40[0x60];
e281682b 5529
b4ff3a36 5530 u8 reserved_at_a0[0x8];
e281682b
SM		 5531 u8 table_index[0x18];
5532
b4ff3a36 5533 u8 reserved_at_c0[0x140];
e281682b
SM		 5534};
5535
5536struct mlx5_ifc_query_issi_out_bits {
5537 u8 status[0x8];
b4ff3a36 5538 u8 reserved_at_8[0x18];
e281682b
SM		 5539
5540 u8 syndrome[0x20];
5541
b4ff3a36 5542 u8 reserved_at_40[0x10];
e281682b
SM		 5543 u8 current_issi[0x10];
5544
b4ff3a36 5545 u8 reserved_at_60[0xa0];
e281682b 5546
b4ff3a36 5547 u8 reserved_at_100[76][0x8];
e281682b
SM		 5548 u8 supported_issi_dw0[0x20];
5549};
5550
5551struct mlx5_ifc_query_issi_in_bits {
5552 u8 opcode[0x10];
b4ff3a36 5553 u8 reserved_at_10[0x10];
e281682b 5554
b4ff3a36 5555 u8 reserved_at_20[0x10];
e281682b
SM		 5556 u8 op_mod[0x10];
5557
b4ff3a36 5558 u8 reserved_at_40[0x40];
e281682b
SM		 5559};
5560
0dbc6fe0
SM		 5561struct mlx5_ifc_set_driver_version_out_bits {
5562 u8 status[0x8];
5563 u8 reserved_0[0x18];
5564
5565 u8 syndrome[0x20];
5566 u8 reserved_1[0x40];
5567};
5568
5569struct mlx5_ifc_set_driver_version_in_bits {
5570 u8 opcode[0x10];
5571 u8 reserved_0[0x10];
5572
5573 u8 reserved_1[0x10];
5574 u8 op_mod[0x10];
5575
5576 u8 reserved_2[0x40];
5577 u8 driver_version[64][0x8];
5578};
5579
e281682b
SM		 5580struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5581 u8 status[0x8];
b4ff3a36 5582 u8 reserved_at_8[0x18];
e281682b
SM		 5583
5584 u8 syndrome[0x20];
5585
b4ff3a36 5586 u8 reserved_at_40[0x40];
e281682b 5587
b6ca09cb 5588 struct mlx5_ifc_pkey_bits pkey[];
e281682b
SM		 5589};
5590
5591struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5592 u8 opcode[0x10];
b4ff3a36 5593 u8 reserved_at_10[0x10];
e281682b 5594
b4ff3a36 5595 u8 reserved_at_20[0x10];
e281682b
SM		 5596 u8 op_mod[0x10];
5597
5598 u8 other_vport[0x1];
b4ff3a36 5599 u8 reserved_at_41[0xb];
707c4602 5600 u8 port_num[0x4];
e281682b
SM		 5601 u8 vport_number[0x10];
5602
b4ff3a36 5603 u8 reserved_at_60[0x10];
e281682b
SM		 5604 u8 pkey_index[0x10];
5605};
5606
eff901d3
EC		 5607enum {
5608 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5609 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5610 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5611};
5612
e281682b
SM		 5613struct mlx5_ifc_query_hca_vport_gid_out_bits {
5614 u8 status[0x8];
b4ff3a36 5615 u8 reserved_at_8[0x18];
e281682b
SM		 5616
5617 u8 syndrome[0x20];
5618
b4ff3a36 5619 u8 reserved_at_40[0x20];
e281682b
SM		 5620
5621 u8 gids_num[0x10];
b4ff3a36 5622 u8 reserved_at_70[0x10];
e281682b 5623
b6ca09cb 5624 struct mlx5_ifc_array128_auto_bits gid[];
e281682b
SM		 5625};
5626
5627struct mlx5_ifc_query_hca_vport_gid_in_bits {
5628 u8 opcode[0x10];
b4ff3a36 5629 u8 reserved_at_10[0x10];
e281682b 5630
b4ff3a36 5631 u8 reserved_at_20[0x10];
e281682b
SM		 5632 u8 op_mod[0x10];
5633
5634 u8 other_vport[0x1];
b4ff3a36 5635 u8 reserved_at_41[0xb];
707c4602 5636 u8 port_num[0x4];
e281682b
SM		 5637 u8 vport_number[0x10];
5638
b4ff3a36 5639 u8 reserved_at_60[0x10];
e281682b
SM		 5640 u8 gid_index[0x10];
5641};
5642
5643struct mlx5_ifc_query_hca_vport_context_out_bits {
5644 u8 status[0x8];
b4ff3a36 5645 u8 reserved_at_8[0x18];
e281682b
SM		 5646
5647 u8 syndrome[0x20];
5648
b4ff3a36 5649 u8 reserved_at_40[0x40];
e281682b
SM		 5650
5651 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5652};
5653
5654struct mlx5_ifc_query_hca_vport_context_in_bits {
5655 u8 opcode[0x10];
b4ff3a36 5656 u8 reserved_at_10[0x10];
e281682b 5657
b4ff3a36 5658 u8 reserved_at_20[0x10];
e281682b
SM		 5659 u8 op_mod[0x10];
5660
5661 u8 other_vport[0x1];
b4ff3a36 5662 u8 reserved_at_41[0xb];
707c4602 5663 u8 port_num[0x4];
e281682b
SM		 5664 u8 vport_number[0x10];
5665
b4ff3a36 5666 u8 reserved_at_60[0x20];
e281682b
SM		 5667};
5668
5669struct mlx5_ifc_query_hca_cap_out_bits {
5670 u8 status[0x8];
b4ff3a36 5671 u8 reserved_at_8[0x18];
e281682b
SM		 5672
5673 u8 syndrome[0x20];
5674
b4ff3a36 5675 u8 reserved_at_40[0x40];
e281682b
SM		 5676
5677 union mlx5_ifc_hca_cap_union_bits capability;
5678};
5679
5680struct mlx5_ifc_query_hca_cap_in_bits {
5681 u8 opcode[0x10];
b4ff3a36 5682 u8 reserved_at_10[0x10];
e281682b 5683
b4ff3a36 5684 u8 reserved_at_20[0x10];
e281682b
SM		 5685 u8 op_mod[0x10];
5686
97b5484e
AV		 5687 u8 other_function[0x1];
5688 u8 reserved_at_41[0xf];
5689 u8 function_id[0x10];
5690
5691 u8 reserved_at_60[0x20];
e281682b
SM		 5692};
5693
97b5484e
AV		 5694struct mlx5_ifc_other_hca_cap_bits {
5695 u8 roce[0x1];
d32d7c52 5696 u8 reserved_at_1[0x27f];
97b5484e
AV		 5697};
5698
5699struct mlx5_ifc_query_other_hca_cap_out_bits {
e281682b 5700 u8 status[0x8];
d32d7c52 5701 u8 reserved_at_8[0x18];
e281682b
SM		 5702
5703 u8 syndrome[0x20];
5704
d32d7c52 5705 u8 reserved_at_40[0x40];
e281682b 5706
97b5484e
AV		 5707 struct mlx5_ifc_other_hca_cap_bits other_capability;
5708};
5709
5710struct mlx5_ifc_query_other_hca_cap_in_bits {
5711 u8 opcode[0x10];
d32d7c52 5712 u8 reserved_at_10[0x10];
97b5484e 5713
d32d7c52 5714 u8 reserved_at_20[0x10];
97b5484e
AV		 5715 u8 op_mod[0x10];
5716
d32d7c52 5717 u8 reserved_at_40[0x10];
97b5484e
AV		 5718 u8 function_id[0x10];
5719
d32d7c52 5720 u8 reserved_at_60[0x20];
97b5484e
AV		 5721};
5722
5723struct mlx5_ifc_modify_other_hca_cap_out_bits {
5724 u8 status[0x8];
d32d7c52 5725 u8 reserved_at_8[0x18];
97b5484e
AV		 5726
5727 u8 syndrome[0x20];
5728
d32d7c52 5729 u8 reserved_at_40[0x40];
97b5484e
AV		 5730};
5731
5732struct mlx5_ifc_modify_other_hca_cap_in_bits {
5733 u8 opcode[0x10];
d32d7c52 5734 u8 reserved_at_10[0x10];
97b5484e 5735
d32d7c52 5736 u8 reserved_at_20[0x10];
97b5484e
AV		 5737 u8 op_mod[0x10];
5738
d32d7c52 5739 u8 reserved_at_40[0x10];
97b5484e
AV		 5740 u8 function_id[0x10];
5741 u8 field_select[0x20];
5742
5743 struct mlx5_ifc_other_hca_cap_bits other_capability;
5744};
5745
5746struct mlx5_ifc_flow_table_context_bits {
5747 u8 reformat_en[0x1];
5748 u8 decap_en[0x1];
5749 u8 sw_owner[0x1];
5750 u8 termination_table[0x1];
5751 u8 table_miss_action[0x4];
e281682b 5752 u8 level[0x8];
97b5484e 5753 u8 reserved_at_10[0x8];
e281682b
SM		 5754 u8 log_size[0x8];
5755
97b5484e
AV		 5756 u8 reserved_at_20[0x8];
5757 u8 table_miss_id[0x18];
5758
5759 u8 reserved_at_40[0x8];
5760 u8 lag_master_next_table_id[0x18];
5761
5762 u8 reserved_at_60[0x60];
5763
5764 u8 sw_owner_icm_root_1[0x40];
5765
5766 u8 sw_owner_icm_root_0[0x40];
5767
5768};
5769
5770struct mlx5_ifc_query_flow_table_out_bits {
5771 u8 status[0x8];
5772 u8 reserved_at_8[0x18];
5773
5774 u8 syndrome[0x20];
5775
5776 u8 reserved_at_40[0x80];
5777
5778 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 5779};
5780
5781struct mlx5_ifc_query_flow_table_in_bits {
5782 u8 opcode[0x10];
b4ff3a36 5783 u8 reserved_at_10[0x10];
e281682b 5784
b4ff3a36 5785 u8 reserved_at_20[0x10];
e281682b
SM		 5786 u8 op_mod[0x10];
5787
b4ff3a36 5788 u8 reserved_at_40[0x40];
e281682b
SM		 5789
5790 u8 table_type[0x8];
b4ff3a36 5791 u8 reserved_at_88[0x18];
e281682b 5792
b4ff3a36 5793 u8 reserved_at_a0[0x8];
e281682b
SM		 5794 u8 table_id[0x18];
5795
b4ff3a36 5796 u8 reserved_at_c0[0x140];
e281682b
SM		 5797};
5798
5799struct mlx5_ifc_query_fte_out_bits {
5800 u8 status[0x8];
b4ff3a36 5801 u8 reserved_at_8[0x18];
e281682b
SM		 5802
5803 u8 syndrome[0x20];
5804
b4ff3a36 5805 u8 reserved_at_40[0x1c0];
e281682b
SM		 5806
5807 struct mlx5_ifc_flow_context_bits flow_context;
5808};
5809
5810struct mlx5_ifc_query_fte_in_bits {
5811 u8 opcode[0x10];
b4ff3a36 5812 u8 reserved_at_10[0x10];
e281682b 5813
b4ff3a36 5814 u8 reserved_at_20[0x10];
e281682b
SM		 5815 u8 op_mod[0x10];
5816
b4ff3a36 5817 u8 reserved_at_40[0x40];
e281682b
SM		 5818
5819 u8 table_type[0x8];
b4ff3a36 5820 u8 reserved_at_88[0x18];
e281682b 5821
b4ff3a36 5822 u8 reserved_at_a0[0x8];
e281682b
SM		 5823 u8 table_id[0x18];
5824
b4ff3a36 5825 u8 reserved_at_c0[0x40];
e281682b
SM		 5826
5827 u8 flow_index[0x20];
5828
b4ff3a36 5829 u8 reserved_at_120[0xe0];
e281682b
SM		 5830};
5831
e7e2519e
MG		 5832struct mlx5_ifc_match_definer_format_0_bits {
5833 u8 reserved_at_0[0x100];
5834
5835 u8 metadata_reg_c_0[0x20];
5836
5837 u8 metadata_reg_c_1[0x20];
5838
5839 u8 outer_dmac_47_16[0x20];
5840
5841 u8 outer_dmac_15_0[0x10];
5842 u8 outer_ethertype[0x10];
5843
5844 u8 reserved_at_180[0x1];
5845 u8 sx_sniffer[0x1];
5846 u8 functional_lb[0x1];
5847 u8 outer_ip_frag[0x1];
5848 u8 outer_qp_type[0x2];
5849 u8 outer_encap_type[0x2];
5850 u8 port_number[0x2];
5851 u8 outer_l3_type[0x2];
5852 u8 outer_l4_type[0x2];
5853 u8 outer_first_vlan_type[0x2];
5854 u8 outer_first_vlan_prio[0x3];
5855 u8 outer_first_vlan_cfi[0x1];
5856 u8 outer_first_vlan_vid[0xc];
5857
5858 u8 outer_l4_type_ext[0x4];
5859 u8 reserved_at_1a4[0x2];
5860 u8 outer_ipsec_layer[0x2];
5861 u8 outer_l2_type[0x2];
5862 u8 force_lb[0x1];
5863 u8 outer_l2_ok[0x1];
5864 u8 outer_l3_ok[0x1];
5865 u8 outer_l4_ok[0x1];
5866 u8 outer_second_vlan_type[0x2];
5867 u8 outer_second_vlan_prio[0x3];
5868 u8 outer_second_vlan_cfi[0x1];
5869 u8 outer_second_vlan_vid[0xc];
5870
5871 u8 outer_smac_47_16[0x20];
5872
5873 u8 outer_smac_15_0[0x10];
5874 u8 inner_ipv4_checksum_ok[0x1];
5875 u8 inner_l4_checksum_ok[0x1];
5876 u8 outer_ipv4_checksum_ok[0x1];
5877 u8 outer_l4_checksum_ok[0x1];
5878 u8 inner_l3_ok[0x1];
5879 u8 inner_l4_ok[0x1];
5880 u8 outer_l3_ok_duplicate[0x1];
5881 u8 outer_l4_ok_duplicate[0x1];
5882 u8 outer_tcp_cwr[0x1];
5883 u8 outer_tcp_ece[0x1];
5884 u8 outer_tcp_urg[0x1];
5885 u8 outer_tcp_ack[0x1];
5886 u8 outer_tcp_psh[0x1];
5887 u8 outer_tcp_rst[0x1];
5888 u8 outer_tcp_syn[0x1];
5889 u8 outer_tcp_fin[0x1];
5890};
5891
5892struct mlx5_ifc_match_definer_format_22_bits {
5893 u8 reserved_at_0[0x100];
5894
5895 u8 outer_ip_src_addr[0x20];
5896
5897 u8 outer_ip_dest_addr[0x20];
5898
5899 u8 outer_l4_sport[0x10];
5900 u8 outer_l4_dport[0x10];
5901
5902 u8 reserved_at_160[0x1];
5903 u8 sx_sniffer[0x1];
5904 u8 functional_lb[0x1];
5905 u8 outer_ip_frag[0x1];
5906 u8 outer_qp_type[0x2];
5907 u8 outer_encap_type[0x2];
5908 u8 port_number[0x2];
5909 u8 outer_l3_type[0x2];
5910 u8 outer_l4_type[0x2];
5911 u8 outer_first_vlan_type[0x2];
5912 u8 outer_first_vlan_prio[0x3];
5913 u8 outer_first_vlan_cfi[0x1];
5914 u8 outer_first_vlan_vid[0xc];
5915
5916 u8 metadata_reg_c_0[0x20];
5917
5918 u8 outer_dmac_47_16[0x20];
5919
5920 u8 outer_smac_47_16[0x20];
5921
5922 u8 outer_smac_15_0[0x10];
5923 u8 outer_dmac_15_0[0x10];
5924};
5925
5926struct mlx5_ifc_match_definer_format_23_bits {
5927 u8 reserved_at_0[0x100];
5928
5929 u8 inner_ip_src_addr[0x20];
5930
5931 u8 inner_ip_dest_addr[0x20];
5932
5933 u8 inner_l4_sport[0x10];
5934 u8 inner_l4_dport[0x10];
5935
5936 u8 reserved_at_160[0x1];
5937 u8 sx_sniffer[0x1];
5938 u8 functional_lb[0x1];
5939 u8 inner_ip_frag[0x1];
5940 u8 inner_qp_type[0x2];
5941 u8 inner_encap_type[0x2];
5942 u8 port_number[0x2];
5943 u8 inner_l3_type[0x2];
5944 u8 inner_l4_type[0x2];
5945 u8 inner_first_vlan_type[0x2];
5946 u8 inner_first_vlan_prio[0x3];
5947 u8 inner_first_vlan_cfi[0x1];
5948 u8 inner_first_vlan_vid[0xc];
5949
5950 u8 tunnel_header_0[0x20];
5951
5952 u8 inner_dmac_47_16[0x20];
5953
5954 u8 inner_smac_47_16[0x20];
5955
5956 u8 inner_smac_15_0[0x10];
5957 u8 inner_dmac_15_0[0x10];
5958};
5959
5960struct mlx5_ifc_match_definer_format_29_bits {
5961 u8 reserved_at_0[0xc0];
5962
5963 u8 outer_ip_dest_addr[0x80];
5964
5965 u8 outer_ip_src_addr[0x80];
5966
5967 u8 outer_l4_sport[0x10];
5968 u8 outer_l4_dport[0x10];
5969
5970 u8 reserved_at_1e0[0x20];
5971};
5972
5973struct mlx5_ifc_match_definer_format_30_bits {
5974 u8 reserved_at_0[0xa0];
5975
5976 u8 outer_ip_dest_addr[0x80];
5977
5978 u8 outer_ip_src_addr[0x80];
5979
5980 u8 outer_dmac_47_16[0x20];
5981
5982 u8 outer_smac_47_16[0x20];
5983
5984 u8 outer_smac_15_0[0x10];
5985 u8 outer_dmac_15_0[0x10];
5986};
5987
5988struct mlx5_ifc_match_definer_format_31_bits {
5989 u8 reserved_at_0[0xc0];
5990
5991 u8 inner_ip_dest_addr[0x80];
5992
5993 u8 inner_ip_src_addr[0x80];
5994
5995 u8 inner_l4_sport[0x10];
5996 u8 inner_l4_dport[0x10];
5997
5998 u8 reserved_at_1e0[0x20];
5999};
6000
6001struct mlx5_ifc_match_definer_format_32_bits {
6002 u8 reserved_at_0[0xa0];
6003
6004 u8 inner_ip_dest_addr[0x80];
6005
6006 u8 inner_ip_src_addr[0x80];
6007
6008 u8 inner_dmac_47_16[0x20];
6009
6010 u8 inner_smac_47_16[0x20];
6011
6012 u8 inner_smac_15_0[0x10];
6013 u8 inner_dmac_15_0[0x10];
6014};
6015
6016struct mlx5_ifc_match_definer_bits {
6017 u8 modify_field_select[0x40];
6018
6019 u8 reserved_at_40[0x40];
6020
6021 u8 reserved_at_80[0x10];
6022 u8 format_id[0x10];
6023
6024 u8 reserved_at_a0[0x160];
6025
6026 u8 match_mask[16][0x20];
6027};
6028
6029struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6030 u8 opcode[0x10];
6031 u8 uid[0x10];
6032
6033 u8 vhca_tunnel_id[0x10];
6034 u8 obj_type[0x10];
6035
6036 u8 obj_id[0x20];
6037
f5d23ee1
JL		 6038 u8 reserved_at_60[0x3];
6039 u8 log_obj_range[0x5];
6040 u8 reserved_at_68[0x18];
e7e2519e
MG		 6041};
6042
6043struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6044 u8 status[0x8];
6045 u8 reserved_at_8[0x18];
6046
6047 u8 syndrome[0x20];
6048
6049 u8 obj_id[0x20];
6050
6051 u8 reserved_at_60[0x20];
6052};
6053
6054struct mlx5_ifc_create_match_definer_in_bits {
6055 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6056
6057 struct mlx5_ifc_match_definer_bits obj_context;
6058};
6059
6060struct mlx5_ifc_create_match_definer_out_bits {
6061 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6062};
6063
e281682b
SM		 6064enum {
6065 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6066 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6067 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 6068 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
b169e64a 6069 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
7da3ad6c 6070 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
0f2a6c3b 6071 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
e281682b
SM		 6072};
6073
6074struct mlx5_ifc_query_flow_group_out_bits {
6075 u8 status[0x8];
b4ff3a36 6076 u8 reserved_at_8[0x18];
e281682b
SM		 6077
6078 u8 syndrome[0x20];
6079
b4ff3a36 6080 u8 reserved_at_40[0xa0];
e281682b
SM		 6081
6082 u8 start_flow_index[0x20];
6083
b4ff3a36 6084 u8 reserved_at_100[0x20];
e281682b
SM		 6085
6086 u8 end_flow_index[0x20];
6087
b4ff3a36 6088 u8 reserved_at_140[0xa0];
e281682b 6089
b4ff3a36 6090 u8 reserved_at_1e0[0x18];
e281682b
SM		 6091 u8 match_criteria_enable[0x8];
6092
6093 struct mlx5_ifc_fte_match_param_bits match_criteria;
6094
b4ff3a36 6095 u8 reserved_at_1200[0xe00];
e281682b
SM		 6096};
6097
6098struct mlx5_ifc_query_flow_group_in_bits {
6099 u8 opcode[0x10];
b4ff3a36 6100 u8 reserved_at_10[0x10];
e281682b 6101
b4ff3a36 6102 u8 reserved_at_20[0x10];
e281682b
SM		 6103 u8 op_mod[0x10];
6104
b4ff3a36 6105 u8 reserved_at_40[0x40];
e281682b
SM		 6106
6107 u8 table_type[0x8];
b4ff3a36 6108 u8 reserved_at_88[0x18];
e281682b 6109
b4ff3a36 6110 u8 reserved_at_a0[0x8];
e281682b
SM		 6111 u8 table_id[0x18];
6112
6113 u8 group_id[0x20];
6114
b4ff3a36 6115 u8 reserved_at_e0[0x120];
e281682b
SM		 6116};
6117
9dc0b289
AV		 6118struct mlx5_ifc_query_flow_counter_out_bits {
6119 u8 status[0x8];
6120 u8 reserved_at_8[0x18];
6121
6122 u8 syndrome[0x20];
6123
6124 u8 reserved_at_40[0x40];
6125
b6ca09cb 6126 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
9dc0b289
AV		 6127};
6128
6129struct mlx5_ifc_query_flow_counter_in_bits {
6130 u8 opcode[0x10];
6131 u8 reserved_at_10[0x10];
6132
6133 u8 reserved_at_20[0x10];
6134 u8 op_mod[0x10];
6135
6136 u8 reserved_at_40[0x80];
6137
6138 u8 clear[0x1];
6139 u8 reserved_at_c1[0xf];
6140 u8 num_of_counters[0x10];
6141
a8ffcc74 6142 u8 flow_counter_id[0x20];
9dc0b289
AV		 6143};
6144
d6666753
SM		 6145struct mlx5_ifc_query_esw_vport_context_out_bits {
6146 u8 status[0x8];
b4ff3a36 6147 u8 reserved_at_8[0x18];
d6666753
SM		 6148
6149 u8 syndrome[0x20];
6150
b4ff3a36 6151 u8 reserved_at_40[0x40];
d6666753
SM		 6152
6153 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6154};
6155
6156struct mlx5_ifc_query_esw_vport_context_in_bits {
6157 u8 opcode[0x10];
b4ff3a36 6158 u8 reserved_at_10[0x10];
d6666753 6159
b4ff3a36 6160 u8 reserved_at_20[0x10];
d6666753
SM		 6161 u8 op_mod[0x10];
6162
6163 u8 other_vport[0x1];
b4ff3a36 6164 u8 reserved_at_41[0xf];
d6666753
SM		 6165 u8 vport_number[0x10];
6166
b4ff3a36 6167 u8 reserved_at_60[0x20];
d6666753
SM		 6168};
6169
6170struct mlx5_ifc_modify_esw_vport_context_out_bits {
6171 u8 status[0x8];
b4ff3a36 6172 u8 reserved_at_8[0x18];
d6666753
SM		 6173
6174 u8 syndrome[0x20];
6175
b4ff3a36 6176 u8 reserved_at_40[0x40];
d6666753
SM		 6177};
6178
6179struct mlx5_ifc_esw_vport_context_fields_select_bits {
65c0f2c1
JL		 6180 u8 reserved_at_0[0x1b];
6181 u8 fdb_to_vport_reg_c_id[0x1];
d6666753
SM		 6182 u8 vport_cvlan_insert[0x1];
6183 u8 vport_svlan_insert[0x1];
6184 u8 vport_cvlan_strip[0x1];
6185 u8 vport_svlan_strip[0x1];
6186};
6187
6188struct mlx5_ifc_modify_esw_vport_context_in_bits {
6189 u8 opcode[0x10];
b4ff3a36 6190 u8 reserved_at_10[0x10];
d6666753 6191
b4ff3a36 6192 u8 reserved_at_20[0x10];
d6666753
SM		 6193 u8 op_mod[0x10];
6194
6195 u8 other_vport[0x1];
b4ff3a36 6196 u8 reserved_at_41[0xf];
d6666753
SM		 6197 u8 vport_number[0x10];
6198
6199 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6200
6201 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6202};
6203
e281682b
SM		 6204struct mlx5_ifc_query_eq_out_bits {
6205 u8 status[0x8];
b4ff3a36 6206 u8 reserved_at_8[0x18];
e281682b
SM		 6207
6208 u8 syndrome[0x20];
6209
b4ff3a36 6210 u8 reserved_at_40[0x40];
e281682b
SM		 6211
6212 struct mlx5_ifc_eqc_bits eq_context_entry;
6213
b4ff3a36 6214 u8 reserved_at_280[0x40];
e281682b
SM		 6215
6216 u8 event_bitmask[0x40];
6217
b4ff3a36 6218 u8 reserved_at_300[0x580];
e281682b 6219
b6ca09cb 6220 u8 pas[][0x40];
e281682b
SM		 6221};
6222
6223struct mlx5_ifc_query_eq_in_bits {
6224 u8 opcode[0x10];
b4ff3a36 6225 u8 reserved_at_10[0x10];
e281682b 6226
b4ff3a36 6227 u8 reserved_at_20[0x10];
e281682b
SM		 6228 u8 op_mod[0x10];
6229
b4ff3a36 6230 u8 reserved_at_40[0x18];
e281682b
SM		 6231 u8 eq_number[0x8];
6232
b4ff3a36 6233 u8 reserved_at_60[0x20];
e281682b
SM		 6234};
6235
60786f09 6236struct mlx5_ifc_packet_reformat_context_in_bits {
67133eaa
YK		 6237 u8 reformat_type[0x8];
6238 u8 reserved_at_8[0x4];
6239 u8 reformat_param_0[0x4];
6240 u8 reserved_at_10[0x6];
60786f09 6241 u8 reformat_data_size[0xa];
7adbde20 6242
67133eaa
YK		 6243 u8 reformat_param_1[0x8];
6244 u8 reserved_at_28[0x8];
60786f09 6245 u8 reformat_data[2][0x8];
7adbde20 6246
b6ca09cb 6247 u8 more_reformat_data[][0x8];
7adbde20
HHZ		 6248};
6249
60786f09 6250struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 6251 u8 status[0x8];
6252 u8 reserved_at_8[0x18];
6253
6254 u8 syndrome[0x20];
6255
6256 u8 reserved_at_40[0xa0];
6257
b6ca09cb 6258 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7adbde20
HHZ		 6259};
6260
60786f09 6261struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 6262 u8 opcode[0x10];
6263 u8 reserved_at_10[0x10];
6264
6265 u8 reserved_at_20[0x10];
6266 u8 op_mod[0x10];
6267
60786f09 6268 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6269
6270 u8 reserved_at_60[0xa0];
6271};
6272
60786f09 6273struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 6274 u8 status[0x8];
6275 u8 reserved_at_8[0x18];
6276
6277 u8 syndrome[0x20];
6278
60786f09 6279 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6280
6281 u8 reserved_at_60[0x20];
6282};
6283
67133eaa
YK		 6284enum {
6285 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6286 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6287 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6288};
6289
97b5484e 6290enum mlx5_reformat_ctx_type {
60786f09
MB		 6291 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6292 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 6293 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6294 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6295 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
67133eaa
YK		 6296 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6297 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
e0e7a386
MB		 6298};
6299
60786f09 6300struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 6301 u8 opcode[0x10];
6302 u8 reserved_at_10[0x10];
6303
6304 u8 reserved_at_20[0x10];
6305 u8 op_mod[0x10];
6306
6307 u8 reserved_at_40[0xa0];
6308
60786f09 6309 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 6310};
6311
60786f09 6312struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 6313 u8 status[0x8];
6314 u8 reserved_at_8[0x18];
6315
6316 u8 syndrome[0x20];
6317
6318 u8 reserved_at_40[0x40];
6319};
6320
60786f09 6321struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 6322 u8 opcode[0x10];
6323 u8 reserved_at_10[0x10];
6324
6325 u8 reserved_20[0x10];
6326 u8 op_mod[0x10];
6327
60786f09 6328 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6329
6330 u8 reserved_60[0x20];
6331};
6332
2a69cb9f
OG		 6333struct mlx5_ifc_set_action_in_bits {
6334 u8 action_type[0x4];
6335 u8 field[0xc];
6336 u8 reserved_at_10[0x3];
6337 u8 offset[0x5];
6338 u8 reserved_at_18[0x3];
6339 u8 length[0x5];
6340
6341 u8 data[0x20];
6342};
6343
6344struct mlx5_ifc_add_action_in_bits {
6345 u8 action_type[0x4];
6346 u8 field[0xc];
6347 u8 reserved_at_10[0x10];
6348
6349 u8 data[0x20];
6350};
6351
31d8bde1
HI		 6352struct mlx5_ifc_copy_action_in_bits {
6353 u8 action_type[0x4];
6354 u8 src_field[0xc];
6355 u8 reserved_at_10[0x3];
6356 u8 src_offset[0x5];
6357 u8 reserved_at_18[0x3];
6358 u8 length[0x5];
6359
6360 u8 reserved_at_20[0x4];
6361 u8 dst_field[0xc];
6362 u8 reserved_at_30[0x3];
6363 u8 dst_offset[0x5];
6364 u8 reserved_at_38[0x8];
6365};
6366
d65dbedf
HN		 6367union mlx5_ifc_set_add_copy_action_in_auto_bits {
6368 struct mlx5_ifc_set_action_in_bits set_action_in;
6369 struct mlx5_ifc_add_action_in_bits add_action_in;
822e114b 6370 struct mlx5_ifc_copy_action_in_bits copy_action_in;
2a69cb9f
OG		 6371 u8 reserved_at_0[0x40];
6372};
6373
6374enum {
6375 MLX5_ACTION_TYPE_SET = 0x1,
6376 MLX5_ACTION_TYPE_ADD = 0x2,
31d8bde1 6377 MLX5_ACTION_TYPE_COPY = 0x3,
2a69cb9f
OG		 6378};
6379
6380enum {
6381 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6382 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6383 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6384 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6385 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6386 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6387 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6388 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6389 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6390 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6391 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6392 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6393 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6394 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6395 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6396 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6397 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6398 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6399 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6400 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6401 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6402 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0eb69bb9 6403 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
0c0316f5 6404 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
97b5484e
AV		 6405 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6406 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
65c0f2c1 6407 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
97b5484e
AV		 6408 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6409 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6410 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6411 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6412 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
822e114b
PB		 6413 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6414 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
97b5484e
AV		 6415 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6416 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
78fb6122 6417 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
67133eaa
YK		 6418 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6419 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
2a69cb9f
OG		 6420};
6421
6422struct mlx5_ifc_alloc_modify_header_context_out_bits {
6423 u8 status[0x8];
6424 u8 reserved_at_8[0x18];
6425
6426 u8 syndrome[0x20];
6427
6428 u8 modify_header_id[0x20];
6429
6430 u8 reserved_at_60[0x20];
6431};
6432
6433struct mlx5_ifc_alloc_modify_header_context_in_bits {
6434 u8 opcode[0x10];
6435 u8 reserved_at_10[0x10];
6436
6437 u8 reserved_at_20[0x10];
6438 u8 op_mod[0x10];
6439
6440 u8 reserved_at_40[0x20];
6441
6442 u8 table_type[0x8];
6443 u8 reserved_at_68[0x10];
6444 u8 num_of_actions[0x8];
6445
29056207 6446 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
2a69cb9f
OG		 6447};
6448
6449struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6450 u8 status[0x8];
6451 u8 reserved_at_8[0x18];
6452
6453 u8 syndrome[0x20];
6454
6455 u8 reserved_at_40[0x40];
6456};
6457
6458struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6459 u8 opcode[0x10];
6460 u8 reserved_at_10[0x10];
6461
6462 u8 reserved_at_20[0x10];
6463 u8 op_mod[0x10];
6464
6465 u8 modify_header_id[0x20];
6466
6467 u8 reserved_at_60[0x20];
6468};
6469
ab0da5a5
YH		 6470struct mlx5_ifc_query_modify_header_context_in_bits {
6471 u8 opcode[0x10];
6472 u8 uid[0x10];
6473
6474 u8 reserved_at_20[0x10];
6475 u8 op_mod[0x10];
6476
6477 u8 modify_header_id[0x20];
6478
6479 u8 reserved_at_60[0xa0];
6480};
6481
e281682b
SM		 6482struct mlx5_ifc_query_dct_out_bits {
6483 u8 status[0x8];
b4ff3a36 6484 u8 reserved_at_8[0x18];
e281682b
SM		 6485
6486 u8 syndrome[0x20];
6487
b4ff3a36 6488 u8 reserved_at_40[0x40];
e281682b
SM		 6489
6490 struct mlx5_ifc_dctc_bits dct_context_entry;
6491
b4ff3a36 6492 u8 reserved_at_280[0x180];
e281682b
SM		 6493};
6494
6495struct mlx5_ifc_query_dct_in_bits {
6496 u8 opcode[0x10];
b4ff3a36 6497 u8 reserved_at_10[0x10];
e281682b 6498
b4ff3a36 6499 u8 reserved_at_20[0x10];
e281682b
SM		 6500 u8 op_mod[0x10];
6501
b4ff3a36 6502 u8 reserved_at_40[0x8];
e281682b
SM		 6503 u8 dctn[0x18];
6504
b4ff3a36 6505 u8 reserved_at_60[0x20];
e281682b
SM		 6506};
6507
6508struct mlx5_ifc_query_cq_out_bits {
6509 u8 status[0x8];
b4ff3a36 6510 u8 reserved_at_8[0x18];
e281682b
SM		 6511
6512 u8 syndrome[0x20];
6513
b4ff3a36 6514 u8 reserved_at_40[0x40];
e281682b
SM		 6515
6516 struct mlx5_ifc_cqc_bits cq_context;
6517
b4ff3a36 6518 u8 reserved_at_280[0x600];
e281682b 6519
b6ca09cb 6520 u8 pas[][0x40];
e281682b
SM		 6521};
6522
6523struct mlx5_ifc_query_cq_in_bits {
6524 u8 opcode[0x10];
b4ff3a36 6525 u8 reserved_at_10[0x10];
e281682b 6526
b4ff3a36 6527 u8 reserved_at_20[0x10];
e281682b
SM		 6528 u8 op_mod[0x10];
6529
b4ff3a36 6530 u8 reserved_at_40[0x8];
e281682b
SM		 6531 u8 cqn[0x18];
6532
b4ff3a36 6533 u8 reserved_at_60[0x20];
e281682b
SM		 6534};
6535
6536struct mlx5_ifc_query_cong_status_out_bits {
6537 u8 status[0x8];
b4ff3a36 6538 u8 reserved_at_8[0x18];
e281682b
SM		 6539
6540 u8 syndrome[0x20];
6541
b4ff3a36 6542 u8 reserved_at_40[0x20];
e281682b
SM		 6543
6544 u8 enable[0x1];
6545 u8 tag_enable[0x1];
b4ff3a36 6546 u8 reserved_at_62[0x1e];
e281682b
SM		 6547};
6548
6549struct mlx5_ifc_query_cong_status_in_bits {
6550 u8 opcode[0x10];
b4ff3a36 6551 u8 reserved_at_10[0x10];
e281682b 6552
b4ff3a36 6553 u8 reserved_at_20[0x10];
e281682b
SM		 6554 u8 op_mod[0x10];
6555
b4ff3a36 6556 u8 reserved_at_40[0x18];
e281682b
SM		 6557 u8 priority[0x4];
6558 u8 cong_protocol[0x4];
6559
b4ff3a36 6560 u8 reserved_at_60[0x20];
e281682b
SM		 6561};
6562
6563struct mlx5_ifc_query_cong_statistics_out_bits {
6564 u8 status[0x8];
b4ff3a36 6565 u8 reserved_at_8[0x18];
e281682b
SM		 6566
6567 u8 syndrome[0x20];
6568
b4ff3a36 6569 u8 reserved_at_40[0x40];
e281682b 6570
e1f24a79 6571 u8 rp_cur_flows[0x20];
e281682b
SM		 6572
6573 u8 sum_flows[0x20];
6574
e1f24a79 6575 u8 rp_cnp_ignored_high[0x20];
e281682b 6576
e1f24a79 6577 u8 rp_cnp_ignored_low[0x20];
e281682b 6578
e1f24a79 6579 u8 rp_cnp_handled_high[0x20];
e281682b 6580
e1f24a79 6581 u8 rp_cnp_handled_low[0x20];
e281682b 6582
b4ff3a36 6583 u8 reserved_at_140[0x100];
e281682b
SM		 6584
6585 u8 time_stamp_high[0x20];
6586
6587 u8 time_stamp_low[0x20];
6588
6589 u8 accumulators_period[0x20];
6590
e1f24a79 6591 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 6592
e1f24a79 6593 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 6594
e1f24a79 6595 u8 np_cnp_sent_high[0x20];
e281682b 6596
e1f24a79 6597 u8 np_cnp_sent_low[0x20];
e281682b 6598
b4ff3a36 6599 u8 reserved_at_320[0x560];
e281682b
SM		 6600};
6601
6602struct mlx5_ifc_query_cong_statistics_in_bits {
6603 u8 opcode[0x10];
b4ff3a36 6604 u8 reserved_at_10[0x10];
e281682b 6605
b4ff3a36 6606 u8 reserved_at_20[0x10];
e281682b
SM		 6607 u8 op_mod[0x10];
6608
6609 u8 clear[0x1];
b4ff3a36 6610 u8 reserved_at_41[0x1f];
e281682b 6611
b4ff3a36 6612 u8 reserved_at_60[0x20];
e281682b
SM		 6613};
6614
6615struct mlx5_ifc_query_cong_params_out_bits {
6616 u8 status[0x8];
b4ff3a36 6617 u8 reserved_at_8[0x18];
e281682b
SM		 6618
6619 u8 syndrome[0x20];
6620
b4ff3a36 6621 u8 reserved_at_40[0x40];
e281682b
SM		 6622
6623 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6624};
6625
6626struct mlx5_ifc_query_cong_params_in_bits {
6627 u8 opcode[0x10];
b4ff3a36 6628 u8 reserved_at_10[0x10];
e281682b 6629
b4ff3a36 6630 u8 reserved_at_20[0x10];
e281682b
SM		 6631 u8 op_mod[0x10];
6632
b4ff3a36 6633 u8 reserved_at_40[0x1c];
e281682b
SM		 6634 u8 cong_protocol[0x4];
6635
b4ff3a36 6636 u8 reserved_at_60[0x20];
e281682b
SM		 6637};
6638
6639struct mlx5_ifc_query_adapter_out_bits {
6640 u8 status[0x8];
b4ff3a36 6641 u8 reserved_at_8[0x18];
e281682b
SM		 6642
6643 u8 syndrome[0x20];
6644
b4ff3a36 6645 u8 reserved_at_40[0x40];
e281682b
SM		 6646
6647 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6648};
6649
6650struct mlx5_ifc_query_adapter_in_bits {
6651 u8 opcode[0x10];
b4ff3a36 6652 u8 reserved_at_10[0x10];
e281682b 6653
b4ff3a36 6654 u8 reserved_at_20[0x10];
e281682b
SM		 6655 u8 op_mod[0x10];
6656
b4ff3a36 6657 u8 reserved_at_40[0x40];
e281682b
SM		 6658};
6659
6660struct mlx5_ifc_qp_2rst_out_bits {
6661 u8 status[0x8];
b4ff3a36 6662 u8 reserved_at_8[0x18];
e281682b
SM		 6663
6664 u8 syndrome[0x20];
6665
b4ff3a36 6666 u8 reserved_at_40[0x40];
e281682b
SM		 6667};
6668
6669struct mlx5_ifc_qp_2rst_in_bits {
6670 u8 opcode[0x10];
4ac63ec7 6671 u8 uid[0x10];
e281682b 6672
b4ff3a36 6673 u8 reserved_at_20[0x10];
e281682b
SM		 6674 u8 op_mod[0x10];
6675
b4ff3a36 6676 u8 reserved_at_40[0x8];
e281682b
SM		 6677 u8 qpn[0x18];
6678
b4ff3a36 6679 u8 reserved_at_60[0x20];
e281682b
SM		 6680};
6681
6682struct mlx5_ifc_qp_2err_out_bits {
6683 u8 status[0x8];
b4ff3a36 6684 u8 reserved_at_8[0x18];
e281682b
SM		 6685
6686 u8 syndrome[0x20];
6687
b4ff3a36 6688 u8 reserved_at_40[0x40];
e281682b
SM		 6689};
6690
6691struct mlx5_ifc_qp_2err_in_bits {
6692 u8 opcode[0x10];
4ac63ec7 6693 u8 uid[0x10];
e281682b 6694
b4ff3a36 6695 u8 reserved_at_20[0x10];
e281682b
SM		 6696 u8 op_mod[0x10];
6697
b4ff3a36 6698 u8 reserved_at_40[0x8];
e281682b
SM		 6699 u8 qpn[0x18];
6700
b4ff3a36 6701 u8 reserved_at_60[0x20];
e281682b
SM		 6702};
6703
6704struct mlx5_ifc_page_fault_resume_out_bits {
6705 u8 status[0x8];
b4ff3a36 6706 u8 reserved_at_8[0x18];
e281682b
SM		 6707
6708 u8 syndrome[0x20];
6709
b4ff3a36 6710 u8 reserved_at_40[0x40];
e281682b
SM		 6711};
6712
6713struct mlx5_ifc_page_fault_resume_in_bits {
6714 u8 opcode[0x10];
b4ff3a36 6715 u8 reserved_at_10[0x10];
e281682b 6716
b4ff3a36 6717 u8 reserved_at_20[0x10];
e281682b
SM		 6718 u8 op_mod[0x10];
6719
6720 u8 error[0x1];
b4ff3a36 6721 u8 reserved_at_41[0x4];
223cdc72
AK		 6722 u8 page_fault_type[0x3];
6723 u8 wq_number[0x18];
e281682b 6724
223cdc72
AK		 6725 u8 reserved_at_60[0x8];
6726 u8 token[0x18];
e281682b
SM		 6727};
6728
6729struct mlx5_ifc_nop_out_bits {
6730 u8 status[0x8];
b4ff3a36 6731 u8 reserved_at_8[0x18];
e281682b
SM		 6732
6733 u8 syndrome[0x20];
6734
b4ff3a36 6735 u8 reserved_at_40[0x40];
e281682b
SM		 6736};
6737
6738struct mlx5_ifc_nop_in_bits {
6739 u8 opcode[0x10];
b4ff3a36 6740 u8 reserved_at_10[0x10];
e281682b 6741
b4ff3a36 6742 u8 reserved_at_20[0x10];
e281682b
SM		 6743 u8 op_mod[0x10];
6744
b4ff3a36 6745 u8 reserved_at_40[0x40];
e281682b
SM		 6746};
6747
6748struct mlx5_ifc_modify_vport_state_out_bits {
6749 u8 status[0x8];
b4ff3a36 6750 u8 reserved_at_8[0x18];
e281682b
SM		 6751
6752 u8 syndrome[0x20];
6753
b4ff3a36 6754 u8 reserved_at_40[0x40];
e281682b
SM		 6755};
6756
6757struct mlx5_ifc_modify_vport_state_in_bits {
6758 u8 opcode[0x10];
b4ff3a36 6759 u8 reserved_at_10[0x10];
e281682b 6760
b4ff3a36 6761 u8 reserved_at_20[0x10];
e281682b
SM		 6762 u8 op_mod[0x10];
6763
6764 u8 other_vport[0x1];
b4ff3a36 6765 u8 reserved_at_41[0xf];
e281682b
SM		 6766 u8 vport_number[0x10];
6767
b4ff3a36 6768 u8 reserved_at_60[0x18];
e281682b 6769 u8 admin_state[0x4];
b4ff3a36 6770 u8 reserved_at_7c[0x4];
e281682b
SM		 6771};
6772
6773struct mlx5_ifc_modify_tis_out_bits {
6774 u8 status[0x8];
b4ff3a36 6775 u8 reserved_at_8[0x18];
e281682b
SM		 6776
6777 u8 syndrome[0x20];
6778
b4ff3a36 6779 u8 reserved_at_40[0x40];
e281682b
SM		 6780};
6781
75850d0b 6782struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 6783 u8 reserved_at_0[0x20];
75850d0b 6784
84df61eb
AH		 6785 u8 reserved_at_20[0x1d];
6786 u8 lag_tx_port_affinity[0x1];
6787 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 6788 u8 prio[0x1];
6789};
6790
e281682b
SM		 6791struct mlx5_ifc_modify_tis_in_bits {
6792 u8 opcode[0x10];
bd371975 6793 u8 uid[0x10];
e281682b 6794
b4ff3a36 6795 u8 reserved_at_20[0x10];
e281682b
SM		 6796 u8 op_mod[0x10];
6797
b4ff3a36 6798 u8 reserved_at_40[0x8];
e281682b
SM		 6799 u8 tisn[0x18];
6800
b4ff3a36 6801 u8 reserved_at_60[0x20];
e281682b 6802
75850d0b 6803 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 6804
b4ff3a36 6805 u8 reserved_at_c0[0x40];
e281682b
SM		 6806
6807 struct mlx5_ifc_tisc_bits ctx;
6808};
6809
d9eea403 6810struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 6811 u8 reserved_at_0[0x20];
d9eea403 6812
b4ff3a36 6813 u8 reserved_at_20[0x1b];
66189961 6814 u8 self_lb_en[0x1];
bdfc028d
TT		 6815 u8 reserved_at_3c[0x1];
6816 u8 hash[0x1];
6817 u8 reserved_at_3e[0x1];
eaee12f0 6818 u8 packet_merge[0x1];
d9eea403
AS		 6819};
6820
e281682b
SM		 6821struct mlx5_ifc_modify_tir_out_bits {
6822 u8 status[0x8];
b4ff3a36 6823 u8 reserved_at_8[0x18];
e281682b
SM		 6824
6825 u8 syndrome[0x20];
6826
b4ff3a36 6827 u8 reserved_at_40[0x40];
e281682b
SM		 6828};
6829
6830struct mlx5_ifc_modify_tir_in_bits {
6831 u8 opcode[0x10];
bd371975 6832 u8 uid[0x10];
e281682b 6833
b4ff3a36 6834 u8 reserved_at_20[0x10];
e281682b
SM		 6835 u8 op_mod[0x10];
6836
b4ff3a36 6837 u8 reserved_at_40[0x8];
e281682b
SM		 6838 u8 tirn[0x18];
6839
b4ff3a36 6840 u8 reserved_at_60[0x20];
e281682b 6841
d9eea403 6842 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 6843
b4ff3a36 6844 u8 reserved_at_c0[0x40];
e281682b
SM		 6845
6846 struct mlx5_ifc_tirc_bits ctx;
6847};
6848
6849struct mlx5_ifc_modify_sq_out_bits {
6850 u8 status[0x8];
b4ff3a36 6851 u8 reserved_at_8[0x18];
e281682b
SM		 6852
6853 u8 syndrome[0x20];
6854
b4ff3a36 6855 u8 reserved_at_40[0x40];
e281682b
SM		 6856};
6857
6858struct mlx5_ifc_modify_sq_in_bits {
6859 u8 opcode[0x10];
430ae0d5 6860 u8 uid[0x10];
e281682b 6861
b4ff3a36 6862 u8 reserved_at_20[0x10];
e281682b
SM		 6863 u8 op_mod[0x10];
6864
6865 u8 sq_state[0x4];
b4ff3a36 6866 u8 reserved_at_44[0x4];
e281682b
SM		 6867 u8 sqn[0x18];
6868
b4ff3a36 6869 u8 reserved_at_60[0x20];
e281682b
SM		 6870
6871 u8 modify_bitmask[0x40];
6872
b4ff3a36 6873 u8 reserved_at_c0[0x40];
e281682b
SM		 6874
6875 struct mlx5_ifc_sqc_bits ctx;
6876};
6877
813f8540
MHY		 6878struct mlx5_ifc_modify_scheduling_element_out_bits {
6879 u8 status[0x8];
6880 u8 reserved_at_8[0x18];
6881
6882 u8 syndrome[0x20];
6883
6884 u8 reserved_at_40[0x1c0];
6885};
6886
6887enum {
6888 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6889 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6890};
6891
6892struct mlx5_ifc_modify_scheduling_element_in_bits {
6893 u8 opcode[0x10];
6894 u8 reserved_at_10[0x10];
6895
6896 u8 reserved_at_20[0x10];
6897 u8 op_mod[0x10];
6898
6899 u8 scheduling_hierarchy[0x8];
6900 u8 reserved_at_48[0x18];
6901
6902 u8 scheduling_element_id[0x20];
6903
6904 u8 reserved_at_80[0x20];
6905
6906 u8 modify_bitmask[0x20];
6907
6908 u8 reserved_at_c0[0x40];
6909
6910 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6911
6912 u8 reserved_at_300[0x100];
6913};
6914
e281682b
SM		 6915struct mlx5_ifc_modify_rqt_out_bits {
6916 u8 status[0x8];
b4ff3a36 6917 u8 reserved_at_8[0x18];
e281682b
SM		 6918
6919 u8 syndrome[0x20];
6920
b4ff3a36 6921 u8 reserved_at_40[0x40];
e281682b
SM		 6922};
6923
5c50368f 6924struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 6925 u8 reserved_at_0[0x20];
5c50368f 6926
b4ff3a36 6927 u8 reserved_at_20[0x1f];
5c50368f
AS		 6928 u8 rqn_list[0x1];
6929};
6930
e281682b
SM		 6931struct mlx5_ifc_modify_rqt_in_bits {
6932 u8 opcode[0x10];
bd371975 6933 u8 uid[0x10];
e281682b 6934
b4ff3a36 6935 u8 reserved_at_20[0x10];
e281682b
SM		 6936 u8 op_mod[0x10];
6937
b4ff3a36 6938 u8 reserved_at_40[0x8];
e281682b
SM		 6939 u8 rqtn[0x18];
6940
b4ff3a36 6941 u8 reserved_at_60[0x20];
e281682b 6942
5c50368f 6943 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 6944
b4ff3a36 6945 u8 reserved_at_c0[0x40];
e281682b
SM		 6946
6947 struct mlx5_ifc_rqtc_bits ctx;
6948};
6949
6950struct mlx5_ifc_modify_rq_out_bits {
6951 u8 status[0x8];
b4ff3a36 6952 u8 reserved_at_8[0x18];
e281682b
SM		 6953
6954 u8 syndrome[0x20];
6955
b4ff3a36 6956 u8 reserved_at_40[0x40];
e281682b
SM		 6957};
6958
83b502a1
AV		 6959enum {
6960 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 6961 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 6962 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 6963};
6964
e281682b
SM		 6965struct mlx5_ifc_modify_rq_in_bits {
6966 u8 opcode[0x10];
d269b3af 6967 u8 uid[0x10];
e281682b 6968
b4ff3a36 6969 u8 reserved_at_20[0x10];
e281682b
SM		 6970 u8 op_mod[0x10];
6971
6972 u8 rq_state[0x4];
b4ff3a36 6973 u8 reserved_at_44[0x4];
e281682b
SM		 6974 u8 rqn[0x18];
6975
b4ff3a36 6976 u8 reserved_at_60[0x20];
e281682b
SM		 6977
6978 u8 modify_bitmask[0x40];
6979
b4ff3a36 6980 u8 reserved_at_c0[0x40];
e281682b
SM		 6981
6982 struct mlx5_ifc_rqc_bits ctx;
6983};
6984
6985struct mlx5_ifc_modify_rmp_out_bits {
6986 u8 status[0x8];
b4ff3a36 6987 u8 reserved_at_8[0x18];
e281682b
SM		 6988
6989 u8 syndrome[0x20];
6990
b4ff3a36 6991 u8 reserved_at_40[0x40];
e281682b
SM		 6992};
6993
01949d01 6994struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 6995 u8 reserved_at_0[0x20];
01949d01 6996
b4ff3a36 6997 u8 reserved_at_20[0x1f];
01949d01
HA		 6998 u8 lwm[0x1];
6999};
7000
e281682b
SM		 7001struct mlx5_ifc_modify_rmp_in_bits {
7002 u8 opcode[0x10];
a0d8c054 7003 u8 uid[0x10];
e281682b 7004
b4ff3a36 7005 u8 reserved_at_20[0x10];
e281682b
SM		 7006 u8 op_mod[0x10];
7007
7008 u8 rmp_state[0x4];
b4ff3a36 7009 u8 reserved_at_44[0x4];
e281682b
SM		 7010 u8 rmpn[0x18];
7011
b4ff3a36 7012 u8 reserved_at_60[0x20];
e281682b 7013
01949d01 7014 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 7015
b4ff3a36 7016 u8 reserved_at_c0[0x40];
e281682b
SM		 7017
7018 struct mlx5_ifc_rmpc_bits ctx;
7019};
7020
7021struct mlx5_ifc_modify_nic_vport_context_out_bits {
7022 u8 status[0x8];
b4ff3a36 7023 u8 reserved_at_8[0x18];
e281682b
SM		 7024
7025 u8 syndrome[0x20];
7026
b4ff3a36 7027 u8 reserved_at_40[0x40];
e281682b
SM		 7028};
7029
7030struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 7031 u8 reserved_at_0[0x12];
7032 u8 affiliation[0x1];
c74d90c1 7033 u8 reserved_at_13[0x1];
bded747b
HN		 7034 u8 disable_uc_local_lb[0x1];
7035 u8 disable_mc_local_lb[0x1];
23898c76
NO		 7036 u8 node_guid[0x1];
7037 u8 port_guid[0x1];
9def7121 7038 u8 min_inline[0x1];
d82b7318
SM		 7039 u8 mtu[0x1];
7040 u8 change_event[0x1];
7041 u8 promisc[0x1];
e281682b
SM		 7042 u8 permanent_address[0x1];
7043 u8 addresses_list[0x1];
7044 u8 roce_en[0x1];
b4ff3a36 7045 u8 reserved_at_1f[0x1];
e281682b
SM		 7046};
7047
7048struct mlx5_ifc_modify_nic_vport_context_in_bits {
7049 u8 opcode[0x10];
b4ff3a36 7050 u8 reserved_at_10[0x10];
e281682b 7051
b4ff3a36 7052 u8 reserved_at_20[0x10];
e281682b
SM		 7053 u8 op_mod[0x10];
7054
7055 u8 other_vport[0x1];
b4ff3a36 7056 u8 reserved_at_41[0xf];
e281682b
SM		 7057 u8 vport_number[0x10];
7058
7059 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7060
b4ff3a36 7061 u8 reserved_at_80[0x780];
e281682b
SM		 7062
7063 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7064};
7065
7066struct mlx5_ifc_modify_hca_vport_context_out_bits {
7067 u8 status[0x8];
b4ff3a36 7068 u8 reserved_at_8[0x18];
e281682b
SM		 7069
7070 u8 syndrome[0x20];
7071
b4ff3a36 7072 u8 reserved_at_40[0x40];
e281682b
SM		 7073};
7074
7075struct mlx5_ifc_modify_hca_vport_context_in_bits {
7076 u8 opcode[0x10];
b4ff3a36 7077 u8 reserved_at_10[0x10];
e281682b 7078
b4ff3a36 7079 u8 reserved_at_20[0x10];
e281682b
SM		 7080 u8 op_mod[0x10];
7081
7082 u8 other_vport[0x1];
b4ff3a36 7083 u8 reserved_at_41[0xb];
707c4602 7084 u8 port_num[0x4];
e281682b
SM		 7085 u8 vport_number[0x10];
7086
b4ff3a36 7087 u8 reserved_at_60[0x20];
e281682b
SM		 7088
7089 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7090};
7091
7092struct mlx5_ifc_modify_cq_out_bits {
7093 u8 status[0x8];
b4ff3a36 7094 u8 reserved_at_8[0x18];
e281682b
SM		 7095
7096 u8 syndrome[0x20];
7097
b4ff3a36 7098 u8 reserved_at_40[0x40];
e281682b
SM		 7099};
7100
7101enum {
7102 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7103 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7104};
7105
7106struct mlx5_ifc_modify_cq_in_bits {
7107 u8 opcode[0x10];
9ba481e2 7108 u8 uid[0x10];
e281682b 7109
b4ff3a36 7110 u8 reserved_at_20[0x10];
e281682b
SM		 7111 u8 op_mod[0x10];
7112
b4ff3a36 7113 u8 reserved_at_40[0x8];
e281682b
SM		 7114 u8 cqn[0x18];
7115
7116 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7117
7118 struct mlx5_ifc_cqc_bits cq_context;
7119
7a32f296 7120 u8 reserved_at_280[0x60];
bd371975
LR		 7121
7122 u8 cq_umem_valid[0x1];
7a32f296
ES		 7123 u8 reserved_at_2e1[0x1f];
7124
7125 u8 reserved_at_300[0x580];
e281682b 7126
b6ca09cb 7127 u8 pas[][0x40];
e281682b
SM		 7128};
7129
7130struct mlx5_ifc_modify_cong_status_out_bits {
7131 u8 status[0x8];
b4ff3a36 7132 u8 reserved_at_8[0x18];
e281682b
SM		 7133
7134 u8 syndrome[0x20];
7135
b4ff3a36 7136 u8 reserved_at_40[0x40];
e281682b
SM		 7137};
7138
7139struct mlx5_ifc_modify_cong_status_in_bits {
7140 u8 opcode[0x10];
b4ff3a36 7141 u8 reserved_at_10[0x10];
e281682b 7142
b4ff3a36 7143 u8 reserved_at_20[0x10];
e281682b
SM		 7144 u8 op_mod[0x10];
7145
b4ff3a36 7146 u8 reserved_at_40[0x18];
e281682b
SM		 7147 u8 priority[0x4];
7148 u8 cong_protocol[0x4];
7149
7150 u8 enable[0x1];
7151 u8 tag_enable[0x1];
b4ff3a36 7152 u8 reserved_at_62[0x1e];
e281682b
SM		 7153};
7154
7155struct mlx5_ifc_modify_cong_params_out_bits {
7156 u8 status[0x8];
b4ff3a36 7157 u8 reserved_at_8[0x18];
e281682b
SM		 7158
7159 u8 syndrome[0x20];
7160
b4ff3a36 7161 u8 reserved_at_40[0x40];
e281682b
SM		 7162};
7163
7164struct mlx5_ifc_modify_cong_params_in_bits {
7165 u8 opcode[0x10];
b4ff3a36 7166 u8 reserved_at_10[0x10];
e281682b 7167
b4ff3a36 7168 u8 reserved_at_20[0x10];
e281682b
SM		 7169 u8 op_mod[0x10];
7170
b4ff3a36 7171 u8 reserved_at_40[0x1c];
e281682b
SM		 7172 u8 cong_protocol[0x4];
7173
7174 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7175
b4ff3a36 7176 u8 reserved_at_80[0x80];
e281682b
SM		 7177
7178 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7179};
7180
7181struct mlx5_ifc_manage_pages_out_bits {
7182 u8 status[0x8];
b4ff3a36 7183 u8 reserved_at_8[0x18];
e281682b
SM		 7184
7185 u8 syndrome[0x20];
7186
7187 u8 output_num_entries[0x20];
7188
b4ff3a36 7189 u8 reserved_at_60[0x20];
e281682b 7190
b6ca09cb 7191 u8 pas[][0x40];
e281682b
SM		 7192};
7193
7194enum {
7195 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7196 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7197 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7198};
7199
7200struct mlx5_ifc_manage_pages_in_bits {
7201 u8 opcode[0x10];
b4ff3a36 7202 u8 reserved_at_10[0x10];
e281682b 7203
b4ff3a36 7204 u8 reserved_at_20[0x10];
e281682b
SM		 7205 u8 op_mod[0x10];
7206
591905ba
BW		 7207 u8 embedded_cpu_function[0x1];
7208 u8 reserved_at_41[0xf];
e281682b
SM		 7209 u8 function_id[0x10];
7210
7211 u8 input_num_entries[0x20];
7212
b6ca09cb 7213 u8 pas[][0x40];
e281682b
SM		 7214};
7215
7216struct mlx5_ifc_mad_ifc_out_bits {
7217 u8 status[0x8];
b4ff3a36 7218 u8 reserved_at_8[0x18];
e281682b
SM		 7219
7220 u8 syndrome[0x20];
7221
b4ff3a36 7222 u8 reserved_at_40[0x40];
e281682b
SM		 7223
7224 u8 response_mad_packet[256][0x8];
7225};
7226
7227struct mlx5_ifc_mad_ifc_in_bits {
7228 u8 opcode[0x10];
b4ff3a36 7229 u8 reserved_at_10[0x10];
e281682b 7230
b4ff3a36 7231 u8 reserved_at_20[0x10];
e281682b
SM		 7232 u8 op_mod[0x10];
7233
7234 u8 remote_lid[0x10];
b4ff3a36 7235 u8 reserved_at_50[0x8];
e281682b
SM		 7236 u8 port[0x8];
7237
b4ff3a36 7238 u8 reserved_at_60[0x20];
e281682b
SM		 7239
7240 u8 mad[256][0x8];
7241};
7242
7243struct mlx5_ifc_init_hca_out_bits {
7244 u8 status[0x8];
b4ff3a36 7245 u8 reserved_at_8[0x18];
e281682b
SM		 7246
7247 u8 syndrome[0x20];
7248
b4ff3a36 7249 u8 reserved_at_40[0x40];
e281682b
SM		 7250};
7251
7252struct mlx5_ifc_init_hca_in_bits {
7253 u8 opcode[0x10];
b4ff3a36 7254 u8 reserved_at_10[0x10];
e281682b 7255
b4ff3a36 7256 u8 reserved_at_20[0x10];
e281682b
SM		 7257 u8 op_mod[0x10];
7258
b4ff3a36 7259 u8 reserved_at_40[0x40];
8737f818 7260 u8 sw_owner_id[4][0x20];
e281682b
SM		 7261};
7262
7263struct mlx5_ifc_init2rtr_qp_out_bits {
7264 u8 status[0x8];
b4ff3a36 7265 u8 reserved_at_8[0x18];
e281682b
SM		 7266
7267 u8 syndrome[0x20];
7268
6b646a7e
LR		 7269 u8 reserved_at_40[0x20];
7270 u8 ece[0x20];
e281682b
SM		 7271};
7272
7273struct mlx5_ifc_init2rtr_qp_in_bits {
7274 u8 opcode[0x10];
4ac63ec7 7275 u8 uid[0x10];
e281682b 7276
b4ff3a36 7277 u8 reserved_at_20[0x10];
e281682b
SM		 7278 u8 op_mod[0x10];
7279
b4ff3a36 7280 u8 reserved_at_40[0x8];
e281682b
SM		 7281 u8 qpn[0x18];
7282
b4ff3a36 7283 u8 reserved_at_60[0x20];
e281682b
SM		 7284
7285 u8 opt_param_mask[0x20];
7286
6b646a7e 7287 u8 ece[0x20];
e281682b
SM		 7288
7289 struct mlx5_ifc_qpc_bits qpc;
7290
b4ff3a36 7291 u8 reserved_at_800[0x80];
e281682b
SM		 7292};
7293
7294struct mlx5_ifc_init2init_qp_out_bits {
7295 u8 status[0x8];
b4ff3a36 7296 u8 reserved_at_8[0x18];
e281682b
SM		 7297
7298 u8 syndrome[0x20];
7299
ab183d46
LR		 7300 u8 reserved_at_40[0x20];
7301 u8 ece[0x20];
e281682b
SM		 7302};
7303
7304struct mlx5_ifc_init2init_qp_in_bits {
7305 u8 opcode[0x10];
4ac63ec7 7306 u8 uid[0x10];
e281682b 7307
b4ff3a36 7308 u8 reserved_at_20[0x10];
e281682b
SM		 7309 u8 op_mod[0x10];
7310
b4ff3a36 7311 u8 reserved_at_40[0x8];
e281682b
SM		 7312 u8 qpn[0x18];
7313
b4ff3a36 7314 u8 reserved_at_60[0x20];
e281682b
SM		 7315
7316 u8 opt_param_mask[0x20];
7317
ab183d46 7318 u8 ece[0x20];
e281682b
SM		 7319
7320 struct mlx5_ifc_qpc_bits qpc;
7321
b4ff3a36 7322 u8 reserved_at_800[0x80];
e281682b
SM		 7323};
7324
7325struct mlx5_ifc_get_dropped_packet_log_out_bits {
7326 u8 status[0x8];
b4ff3a36 7327 u8 reserved_at_8[0x18];
e281682b
SM		 7328
7329 u8 syndrome[0x20];
7330
b4ff3a36 7331 u8 reserved_at_40[0x40];
e281682b
SM		 7332
7333 u8 packet_headers_log[128][0x8];
7334
7335 u8 packet_syndrome[64][0x8];
7336};
7337
7338struct mlx5_ifc_get_dropped_packet_log_in_bits {
7339 u8 opcode[0x10];
b4ff3a36 7340 u8 reserved_at_10[0x10];
e281682b 7341
b4ff3a36 7342 u8 reserved_at_20[0x10];
e281682b
SM		 7343 u8 op_mod[0x10];
7344
b4ff3a36 7345 u8 reserved_at_40[0x40];
e281682b
SM		 7346};
7347
7348struct mlx5_ifc_gen_eqe_in_bits {
7349 u8 opcode[0x10];
b4ff3a36 7350 u8 reserved_at_10[0x10];
e281682b 7351
b4ff3a36 7352 u8 reserved_at_20[0x10];
e281682b
SM		 7353 u8 op_mod[0x10];
7354
b4ff3a36 7355 u8 reserved_at_40[0x18];
e281682b
SM		 7356 u8 eq_number[0x8];
7357
b4ff3a36 7358 u8 reserved_at_60[0x20];
e281682b
SM		 7359
7360 u8 eqe[64][0x8];
7361};
7362
7363struct mlx5_ifc_gen_eq_out_bits {
7364 u8 status[0x8];
b4ff3a36 7365 u8 reserved_at_8[0x18];
e281682b
SM		 7366
7367 u8 syndrome[0x20];
7368
b4ff3a36 7369 u8 reserved_at_40[0x40];
e281682b
SM		 7370};
7371
7372struct mlx5_ifc_enable_hca_out_bits {
7373 u8 status[0x8];
b4ff3a36 7374 u8 reserved_at_8[0x18];
e281682b
SM		 7375
7376 u8 syndrome[0x20];
7377
b4ff3a36 7378 u8 reserved_at_40[0x20];
e281682b
SM		 7379};
7380
7381struct mlx5_ifc_enable_hca_in_bits {
7382 u8 opcode[0x10];
b4ff3a36 7383 u8 reserved_at_10[0x10];
e281682b 7384
b4ff3a36 7385 u8 reserved_at_20[0x10];
e281682b
SM		 7386 u8 op_mod[0x10];
7387
22e939a9
BW		 7388 u8 embedded_cpu_function[0x1];
7389 u8 reserved_at_41[0xf];
e281682b
SM		 7390 u8 function_id[0x10];
7391
b4ff3a36 7392 u8 reserved_at_60[0x20];
e281682b
SM		 7393};
7394
7395struct mlx5_ifc_drain_dct_out_bits {
7396 u8 status[0x8];
b4ff3a36 7397 u8 reserved_at_8[0x18];
e281682b
SM		 7398
7399 u8 syndrome[0x20];
7400
b4ff3a36 7401 u8 reserved_at_40[0x40];
e281682b
SM		 7402};
7403
7404struct mlx5_ifc_drain_dct_in_bits {
7405 u8 opcode[0x10];
774ea6ee 7406 u8 uid[0x10];
e281682b 7407
b4ff3a36 7408 u8 reserved_at_20[0x10];
e281682b
SM		 7409 u8 op_mod[0x10];
7410
b4ff3a36 7411 u8 reserved_at_40[0x8];
e281682b
SM		 7412 u8 dctn[0x18];
7413
b4ff3a36 7414 u8 reserved_at_60[0x20];
e281682b
SM		 7415};
7416
7417struct mlx5_ifc_disable_hca_out_bits {
7418 u8 status[0x8];
b4ff3a36 7419 u8 reserved_at_8[0x18];
e281682b
SM		 7420
7421 u8 syndrome[0x20];
7422
b4ff3a36 7423 u8 reserved_at_40[0x20];
e281682b
SM		 7424};
7425
7426struct mlx5_ifc_disable_hca_in_bits {
7427 u8 opcode[0x10];
b4ff3a36 7428 u8 reserved_at_10[0x10];
e281682b 7429
b4ff3a36 7430 u8 reserved_at_20[0x10];
e281682b
SM		 7431 u8 op_mod[0x10];
7432
22e939a9
BW		 7433 u8 embedded_cpu_function[0x1];
7434 u8 reserved_at_41[0xf];
e281682b
SM		 7435 u8 function_id[0x10];
7436
b4ff3a36 7437 u8 reserved_at_60[0x20];
e281682b
SM		 7438};
7439
7440struct mlx5_ifc_detach_from_mcg_out_bits {
7441 u8 status[0x8];
b4ff3a36 7442 u8 reserved_at_8[0x18];
e281682b
SM		 7443
7444 u8 syndrome[0x20];
7445
b4ff3a36 7446 u8 reserved_at_40[0x40];
e281682b
SM		 7447};
7448
7449struct mlx5_ifc_detach_from_mcg_in_bits {
7450 u8 opcode[0x10];
bd371975 7451 u8 uid[0x10];
e281682b 7452
b4ff3a36 7453 u8 reserved_at_20[0x10];
e281682b
SM		 7454 u8 op_mod[0x10];
7455
b4ff3a36 7456 u8 reserved_at_40[0x8];
e281682b
SM		 7457 u8 qpn[0x18];
7458
b4ff3a36 7459 u8 reserved_at_60[0x20];
e281682b
SM		 7460
7461 u8 multicast_gid[16][0x8];
7462};
7463
7486216b
SM		 7464struct mlx5_ifc_destroy_xrq_out_bits {
7465 u8 status[0x8];
7466 u8 reserved_at_8[0x18];
7467
7468 u8 syndrome[0x20];
7469
7470 u8 reserved_at_40[0x40];
7471};
7472
7473struct mlx5_ifc_destroy_xrq_in_bits {
7474 u8 opcode[0x10];
a0d8c054 7475 u8 uid[0x10];
7486216b
SM		 7476
7477 u8 reserved_at_20[0x10];
7478 u8 op_mod[0x10];
7479
7480 u8 reserved_at_40[0x8];
7481 u8 xrqn[0x18];
7482
7483 u8 reserved_at_60[0x20];
7484};
7485
e281682b
SM		 7486struct mlx5_ifc_destroy_xrc_srq_out_bits {
7487 u8 status[0x8];
b4ff3a36 7488 u8 reserved_at_8[0x18];
e281682b
SM		 7489
7490 u8 syndrome[0x20];
7491
b4ff3a36 7492 u8 reserved_at_40[0x40];
e281682b
SM		 7493};
7494
7495struct mlx5_ifc_destroy_xrc_srq_in_bits {
7496 u8 opcode[0x10];
a0d8c054 7497 u8 uid[0x10];
e281682b 7498
b4ff3a36 7499 u8 reserved_at_20[0x10];
e281682b
SM		 7500 u8 op_mod[0x10];
7501
b4ff3a36 7502 u8 reserved_at_40[0x8];
e281682b
SM		 7503 u8 xrc_srqn[0x18];
7504
b4ff3a36 7505 u8 reserved_at_60[0x20];
e281682b
SM		 7506};
7507
7508struct mlx5_ifc_destroy_tis_out_bits {
7509 u8 status[0x8];
b4ff3a36 7510 u8 reserved_at_8[0x18];
e281682b
SM		 7511
7512 u8 syndrome[0x20];
7513
b4ff3a36 7514 u8 reserved_at_40[0x40];
e281682b
SM		 7515};
7516
7517struct mlx5_ifc_destroy_tis_in_bits {
7518 u8 opcode[0x10];
bd371975 7519 u8 uid[0x10];
e281682b 7520
b4ff3a36 7521 u8 reserved_at_20[0x10];
e281682b
SM		 7522 u8 op_mod[0x10];
7523
b4ff3a36 7524 u8 reserved_at_40[0x8];
e281682b
SM		 7525 u8 tisn[0x18];
7526
b4ff3a36 7527 u8 reserved_at_60[0x20];
e281682b
SM		 7528};
7529
7530struct mlx5_ifc_destroy_tir_out_bits {
7531 u8 status[0x8];
b4ff3a36 7532 u8 reserved_at_8[0x18];
e281682b
SM		 7533
7534 u8 syndrome[0x20];
7535
b4ff3a36 7536 u8 reserved_at_40[0x40];
e281682b
SM		 7537};
7538
7539struct mlx5_ifc_destroy_tir_in_bits {
7540 u8 opcode[0x10];
bd371975 7541 u8 uid[0x10];
e281682b 7542
b4ff3a36 7543 u8 reserved_at_20[0x10];
e281682b
SM		 7544 u8 op_mod[0x10];
7545
b4ff3a36 7546 u8 reserved_at_40[0x8];
e281682b
SM		 7547 u8 tirn[0x18];
7548
b4ff3a36 7549 u8 reserved_at_60[0x20];
e281682b
SM		 7550};
7551
7552struct mlx5_ifc_destroy_srq_out_bits {
7553 u8 status[0x8];
b4ff3a36 7554 u8 reserved_at_8[0x18];
e281682b
SM		 7555
7556 u8 syndrome[0x20];
7557
b4ff3a36 7558 u8 reserved_at_40[0x40];
e281682b
SM		 7559};
7560
7561struct mlx5_ifc_destroy_srq_in_bits {
7562 u8 opcode[0x10];
a0d8c054 7563 u8 uid[0x10];
e281682b 7564
b4ff3a36 7565 u8 reserved_at_20[0x10];
e281682b
SM		 7566 u8 op_mod[0x10];
7567
b4ff3a36 7568 u8 reserved_at_40[0x8];
e281682b
SM		 7569 u8 srqn[0x18];
7570
b4ff3a36 7571 u8 reserved_at_60[0x20];
e281682b
SM		 7572};
7573
7574struct mlx5_ifc_destroy_sq_out_bits {
7575 u8 status[0x8];
b4ff3a36 7576 u8 reserved_at_8[0x18];
e281682b
SM		 7577
7578 u8 syndrome[0x20];
7579
b4ff3a36 7580 u8 reserved_at_40[0x40];
e281682b
SM		 7581};
7582
7583struct mlx5_ifc_destroy_sq_in_bits {
7584 u8 opcode[0x10];
430ae0d5 7585 u8 uid[0x10];
e281682b 7586
b4ff3a36 7587 u8 reserved_at_20[0x10];
e281682b
SM		 7588 u8 op_mod[0x10];
7589
b4ff3a36 7590 u8 reserved_at_40[0x8];
e281682b
SM		 7591 u8 sqn[0x18];
7592
b4ff3a36 7593 u8 reserved_at_60[0x20];
e281682b
SM		 7594};
7595
813f8540
MHY		 7596struct mlx5_ifc_destroy_scheduling_element_out_bits {
7597 u8 status[0x8];
7598 u8 reserved_at_8[0x18];
7599
7600 u8 syndrome[0x20];
7601
7602 u8 reserved_at_40[0x1c0];
7603};
7604
7605struct mlx5_ifc_destroy_scheduling_element_in_bits {
7606 u8 opcode[0x10];
7607 u8 reserved_at_10[0x10];
7608
7609 u8 reserved_at_20[0x10];
7610 u8 op_mod[0x10];
7611
7612 u8 scheduling_hierarchy[0x8];
7613 u8 reserved_at_48[0x18];
7614
7615 u8 scheduling_element_id[0x20];
7616
7617 u8 reserved_at_80[0x180];
7618};
7619
e281682b
SM		 7620struct mlx5_ifc_destroy_rqt_out_bits {
7621 u8 status[0x8];
b4ff3a36 7622 u8 reserved_at_8[0x18];
e281682b
SM		 7623
7624 u8 syndrome[0x20];
7625
b4ff3a36 7626 u8 reserved_at_40[0x40];
e281682b
SM		 7627};
7628
7629struct mlx5_ifc_destroy_rqt_in_bits {
7630 u8 opcode[0x10];
bd371975 7631 u8 uid[0x10];
e281682b 7632
b4ff3a36 7633 u8 reserved_at_20[0x10];
e281682b
SM		 7634 u8 op_mod[0x10];
7635
b4ff3a36 7636 u8 reserved_at_40[0x8];
e281682b
SM		 7637 u8 rqtn[0x18];
7638
b4ff3a36 7639 u8 reserved_at_60[0x20];
e281682b
SM		 7640};
7641
7642struct mlx5_ifc_destroy_rq_out_bits {
7643 u8 status[0x8];
b4ff3a36 7644 u8 reserved_at_8[0x18];
e281682b
SM		 7645
7646 u8 syndrome[0x20];
7647
b4ff3a36 7648 u8 reserved_at_40[0x40];
e281682b
SM		 7649};
7650
7651struct mlx5_ifc_destroy_rq_in_bits {
7652 u8 opcode[0x10];
d269b3af 7653 u8 uid[0x10];
e281682b 7654
b4ff3a36 7655 u8 reserved_at_20[0x10];
e281682b
SM		 7656 u8 op_mod[0x10];
7657
b4ff3a36 7658 u8 reserved_at_40[0x8];
e281682b
SM		 7659 u8 rqn[0x18];
7660
b4ff3a36 7661 u8 reserved_at_60[0x20];
e281682b
SM		 7662};
7663
c1e0bfc1
MG		 7664struct mlx5_ifc_set_delay_drop_params_in_bits {
7665 u8 opcode[0x10];
7666 u8 reserved_at_10[0x10];
7667
7668 u8 reserved_at_20[0x10];
7669 u8 op_mod[0x10];
7670
7671 u8 reserved_at_40[0x20];
7672
7673 u8 reserved_at_60[0x10];
7674 u8 delay_drop_timeout[0x10];
7675};
7676
7677struct mlx5_ifc_set_delay_drop_params_out_bits {
7678 u8 status[0x8];
7679 u8 reserved_at_8[0x18];
7680
7681 u8 syndrome[0x20];
7682
7683 u8 reserved_at_40[0x40];
7684};
7685
e281682b
SM		 7686struct mlx5_ifc_destroy_rmp_out_bits {
7687 u8 status[0x8];
b4ff3a36 7688 u8 reserved_at_8[0x18];
e281682b
SM		 7689
7690 u8 syndrome[0x20];
7691
b4ff3a36 7692 u8 reserved_at_40[0x40];
e281682b
SM		 7693};
7694
7695struct mlx5_ifc_destroy_rmp_in_bits {
7696 u8 opcode[0x10];
a0d8c054 7697 u8 uid[0x10];
e281682b 7698
b4ff3a36 7699 u8 reserved_at_20[0x10];
e281682b
SM		 7700 u8 op_mod[0x10];
7701
b4ff3a36 7702 u8 reserved_at_40[0x8];
e281682b
SM		 7703 u8 rmpn[0x18];
7704
b4ff3a36 7705 u8 reserved_at_60[0x20];
e281682b
SM		 7706};
7707
7708struct mlx5_ifc_destroy_qp_out_bits {
7709 u8 status[0x8];
b4ff3a36 7710 u8 reserved_at_8[0x18];
e281682b
SM		 7711
7712 u8 syndrome[0x20];
7713
b4ff3a36 7714 u8 reserved_at_40[0x40];
e281682b
SM		 7715};
7716
7717struct mlx5_ifc_destroy_qp_in_bits {
7718 u8 opcode[0x10];
4ac63ec7 7719 u8 uid[0x10];
e281682b 7720
b4ff3a36 7721 u8 reserved_at_20[0x10];
e281682b
SM		 7722 u8 op_mod[0x10];
7723
b4ff3a36 7724 u8 reserved_at_40[0x8];
e281682b
SM		 7725 u8 qpn[0x18];
7726
b4ff3a36 7727 u8 reserved_at_60[0x20];
e281682b
SM		 7728};
7729
7730struct mlx5_ifc_destroy_psv_out_bits {
7731 u8 status[0x8];
b4ff3a36 7732 u8 reserved_at_8[0x18];
e281682b
SM		 7733
7734 u8 syndrome[0x20];
7735
b4ff3a36 7736 u8 reserved_at_40[0x40];
e281682b
SM		 7737};
7738
7739struct mlx5_ifc_destroy_psv_in_bits {
7740 u8 opcode[0x10];
b4ff3a36 7741 u8 reserved_at_10[0x10];
e281682b 7742
b4ff3a36 7743 u8 reserved_at_20[0x10];
e281682b
SM		 7744 u8 op_mod[0x10];
7745
b4ff3a36 7746 u8 reserved_at_40[0x8];
e281682b
SM		 7747 u8 psvn[0x18];
7748
b4ff3a36 7749 u8 reserved_at_60[0x20];
e281682b
SM		 7750};
7751
7752struct mlx5_ifc_destroy_mkey_out_bits {
7753 u8 status[0x8];
b4ff3a36 7754 u8 reserved_at_8[0x18];
e281682b
SM		 7755
7756 u8 syndrome[0x20];
7757
b4ff3a36 7758 u8 reserved_at_40[0x40];
e281682b
SM		 7759};
7760
7761struct mlx5_ifc_destroy_mkey_in_bits {
7762 u8 opcode[0x10];
8a06a79b 7763 u8 uid[0x10];
e281682b 7764
b4ff3a36 7765 u8 reserved_at_20[0x10];
e281682b
SM		 7766 u8 op_mod[0x10];
7767
b4ff3a36 7768 u8 reserved_at_40[0x8];
e281682b
SM		 7769 u8 mkey_index[0x18];
7770
b4ff3a36 7771 u8 reserved_at_60[0x20];
e281682b
SM		 7772};
7773
7774struct mlx5_ifc_destroy_flow_table_out_bits {
7775 u8 status[0x8];
b4ff3a36 7776 u8 reserved_at_8[0x18];
e281682b
SM		 7777
7778 u8 syndrome[0x20];
7779
b4ff3a36 7780 u8 reserved_at_40[0x40];
e281682b
SM		 7781};
7782
7783struct mlx5_ifc_destroy_flow_table_in_bits {
7784 u8 opcode[0x10];
b4ff3a36 7785 u8 reserved_at_10[0x10];
e281682b 7786
b4ff3a36 7787 u8 reserved_at_20[0x10];
e281682b
SM		 7788 u8 op_mod[0x10];
7789
7d5e1423
SM		 7790 u8 other_vport[0x1];
7791 u8 reserved_at_41[0xf];
7792 u8 vport_number[0x10];
7793
7794 u8 reserved_at_60[0x20];
e281682b
SM		 7795
7796 u8 table_type[0x8];
b4ff3a36 7797 u8 reserved_at_88[0x18];
e281682b 7798
b4ff3a36 7799 u8 reserved_at_a0[0x8];
e281682b
SM		 7800 u8 table_id[0x18];
7801
b4ff3a36 7802 u8 reserved_at_c0[0x140];
e281682b
SM		 7803};
7804
7805struct mlx5_ifc_destroy_flow_group_out_bits {
7806 u8 status[0x8];
b4ff3a36 7807 u8 reserved_at_8[0x18];
e281682b
SM		 7808
7809 u8 syndrome[0x20];
7810
b4ff3a36 7811 u8 reserved_at_40[0x40];
e281682b
SM		 7812};
7813
7814struct mlx5_ifc_destroy_flow_group_in_bits {
7815 u8 opcode[0x10];
b4ff3a36 7816 u8 reserved_at_10[0x10];
e281682b 7817
b4ff3a36 7818 u8 reserved_at_20[0x10];
e281682b
SM		 7819 u8 op_mod[0x10];
7820
7d5e1423
SM		 7821 u8 other_vport[0x1];
7822 u8 reserved_at_41[0xf];
7823 u8 vport_number[0x10];
7824
7825 u8 reserved_at_60[0x20];
e281682b
SM		 7826
7827 u8 table_type[0x8];
b4ff3a36 7828 u8 reserved_at_88[0x18];
e281682b 7829
b4ff3a36 7830 u8 reserved_at_a0[0x8];
e281682b
SM		 7831 u8 table_id[0x18];
7832
7833 u8 group_id[0x20];
7834
b4ff3a36 7835 u8 reserved_at_e0[0x120];
e281682b
SM		 7836};
7837
7838struct mlx5_ifc_destroy_eq_out_bits {
7839 u8 status[0x8];
b4ff3a36 7840 u8 reserved_at_8[0x18];
e281682b
SM		 7841
7842 u8 syndrome[0x20];
7843
b4ff3a36 7844 u8 reserved_at_40[0x40];
e281682b
SM		 7845};
7846
7847struct mlx5_ifc_destroy_eq_in_bits {
7848 u8 opcode[0x10];
b4ff3a36 7849 u8 reserved_at_10[0x10];
e281682b 7850
b4ff3a36 7851 u8 reserved_at_20[0x10];
e281682b
SM		 7852 u8 op_mod[0x10];
7853
b4ff3a36 7854 u8 reserved_at_40[0x18];
e281682b
SM		 7855 u8 eq_number[0x8];
7856
b4ff3a36 7857 u8 reserved_at_60[0x20];
e281682b
SM		 7858};
7859
7860struct mlx5_ifc_destroy_dct_out_bits {
7861 u8 status[0x8];
b4ff3a36 7862 u8 reserved_at_8[0x18];
e281682b
SM		 7863
7864 u8 syndrome[0x20];
7865
b4ff3a36 7866 u8 reserved_at_40[0x40];
e281682b
SM		 7867};
7868
7869struct mlx5_ifc_destroy_dct_in_bits {
7870 u8 opcode[0x10];
774ea6ee 7871 u8 uid[0x10];
e281682b 7872
b4ff3a36 7873 u8 reserved_at_20[0x10];
e281682b
SM		 7874 u8 op_mod[0x10];
7875
b4ff3a36 7876 u8 reserved_at_40[0x8];
e281682b
SM		 7877 u8 dctn[0x18];
7878
b4ff3a36 7879 u8 reserved_at_60[0x20];
e281682b
SM		 7880};
7881
7882struct mlx5_ifc_destroy_cq_out_bits {
7883 u8 status[0x8];
b4ff3a36 7884 u8 reserved_at_8[0x18];
e281682b
SM		 7885
7886 u8 syndrome[0x20];
7887
b4ff3a36 7888 u8 reserved_at_40[0x40];
e281682b
SM		 7889};
7890
7891struct mlx5_ifc_destroy_cq_in_bits {
7892 u8 opcode[0x10];
9ba481e2 7893 u8 uid[0x10];
e281682b 7894
b4ff3a36 7895 u8 reserved_at_20[0x10];
e281682b
SM		 7896 u8 op_mod[0x10];
7897
b4ff3a36 7898 u8 reserved_at_40[0x8];
e281682b
SM		 7899 u8 cqn[0x18];
7900
b4ff3a36 7901 u8 reserved_at_60[0x20];
e281682b
SM		 7902};
7903
7904struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7905 u8 status[0x8];
b4ff3a36 7906 u8 reserved_at_8[0x18];
e281682b
SM		 7907
7908 u8 syndrome[0x20];
7909
b4ff3a36 7910 u8 reserved_at_40[0x40];
e281682b
SM		 7911};
7912
7913struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7914 u8 opcode[0x10];
b4ff3a36 7915 u8 reserved_at_10[0x10];
e281682b 7916
b4ff3a36 7917 u8 reserved_at_20[0x10];
e281682b
SM		 7918 u8 op_mod[0x10];
7919
b4ff3a36 7920 u8 reserved_at_40[0x20];
e281682b 7921
b4ff3a36 7922 u8 reserved_at_60[0x10];
e281682b
SM		 7923 u8 vxlan_udp_port[0x10];
7924};
7925
7926struct mlx5_ifc_delete_l2_table_entry_out_bits {
7927 u8 status[0x8];
b4ff3a36 7928 u8 reserved_at_8[0x18];
e281682b
SM		 7929
7930 u8 syndrome[0x20];
7931
b4ff3a36 7932 u8 reserved_at_40[0x40];
e281682b
SM		 7933};
7934
7935struct mlx5_ifc_delete_l2_table_entry_in_bits {
7936 u8 opcode[0x10];
b4ff3a36 7937 u8 reserved_at_10[0x10];
e281682b 7938
b4ff3a36 7939 u8 reserved_at_20[0x10];
e281682b
SM		 7940 u8 op_mod[0x10];
7941
b4ff3a36 7942 u8 reserved_at_40[0x60];
e281682b 7943
b4ff3a36 7944 u8 reserved_at_a0[0x8];
e281682b
SM		 7945 u8 table_index[0x18];
7946
b4ff3a36 7947 u8 reserved_at_c0[0x140];
e281682b
SM		 7948};
7949
7950struct mlx5_ifc_delete_fte_out_bits {
7951 u8 status[0x8];
b4ff3a36 7952 u8 reserved_at_8[0x18];
e281682b
SM		 7953
7954 u8 syndrome[0x20];
7955
b4ff3a36 7956 u8 reserved_at_40[0x40];
e281682b
SM		 7957};
7958
7959struct mlx5_ifc_delete_fte_in_bits {
7960 u8 opcode[0x10];
b4ff3a36 7961 u8 reserved_at_10[0x10];
e281682b 7962
b4ff3a36 7963 u8 reserved_at_20[0x10];
e281682b
SM		 7964 u8 op_mod[0x10];
7965
7d5e1423
SM		 7966 u8 other_vport[0x1];
7967 u8 reserved_at_41[0xf];
7968 u8 vport_number[0x10];
7969
7970 u8 reserved_at_60[0x20];
e281682b
SM		 7971
7972 u8 table_type[0x8];
b4ff3a36 7973 u8 reserved_at_88[0x18];
e281682b 7974
b4ff3a36 7975 u8 reserved_at_a0[0x8];
e281682b
SM		 7976 u8 table_id[0x18];
7977
b4ff3a36 7978 u8 reserved_at_c0[0x40];
e281682b
SM		 7979
7980 u8 flow_index[0x20];
7981
b4ff3a36 7982 u8 reserved_at_120[0xe0];
e281682b
SM		 7983};
7984
7985struct mlx5_ifc_dealloc_xrcd_out_bits {
7986 u8 status[0x8];
b4ff3a36 7987 u8 reserved_at_8[0x18];
e281682b
SM		 7988
7989 u8 syndrome[0x20];
7990
b4ff3a36 7991 u8 reserved_at_40[0x40];
e281682b
SM		 7992};
7993
7994struct mlx5_ifc_dealloc_xrcd_in_bits {
7995 u8 opcode[0x10];
bd371975 7996 u8 uid[0x10];
e281682b 7997
b4ff3a36 7998 u8 reserved_at_20[0x10];
e281682b
SM		 7999 u8 op_mod[0x10];
8000
b4ff3a36 8001 u8 reserved_at_40[0x8];
e281682b
SM		 8002 u8 xrcd[0x18];
8003
b4ff3a36 8004 u8 reserved_at_60[0x20];
e281682b
SM		 8005};
8006
8007struct mlx5_ifc_dealloc_uar_out_bits {
8008 u8 status[0x8];
b4ff3a36 8009 u8 reserved_at_8[0x18];
e281682b
SM		 8010
8011 u8 syndrome[0x20];
8012
b4ff3a36 8013 u8 reserved_at_40[0x40];
e281682b
SM		 8014};
8015
8016struct mlx5_ifc_dealloc_uar_in_bits {
8017 u8 opcode[0x10];
8de1e9b0 8018 u8 uid[0x10];
e281682b 8019
b4ff3a36 8020 u8 reserved_at_20[0x10];
e281682b
SM		 8021 u8 op_mod[0x10];
8022
b4ff3a36 8023 u8 reserved_at_40[0x8];
e281682b
SM		 8024 u8 uar[0x18];
8025
b4ff3a36 8026 u8 reserved_at_60[0x20];
e281682b
SM		 8027};
8028
8029struct mlx5_ifc_dealloc_transport_domain_out_bits {
8030 u8 status[0x8];
b4ff3a36 8031 u8 reserved_at_8[0x18];
e281682b
SM		 8032
8033 u8 syndrome[0x20];
8034
b4ff3a36 8035 u8 reserved_at_40[0x40];
e281682b
SM		 8036};
8037
8038struct mlx5_ifc_dealloc_transport_domain_in_bits {
8039 u8 opcode[0x10];
71bef2fd 8040 u8 uid[0x10];
e281682b 8041
b4ff3a36 8042 u8 reserved_at_20[0x10];
e281682b
SM		 8043 u8 op_mod[0x10];
8044
b4ff3a36 8045 u8 reserved_at_40[0x8];
e281682b
SM		 8046 u8 transport_domain[0x18];
8047
b4ff3a36 8048 u8 reserved_at_60[0x20];
e281682b
SM		 8049};
8050
8051struct mlx5_ifc_dealloc_q_counter_out_bits {
8052 u8 status[0x8];
b4ff3a36 8053 u8 reserved_at_8[0x18];
e281682b
SM		 8054
8055 u8 syndrome[0x20];
8056
b4ff3a36 8057 u8 reserved_at_40[0x40];
e281682b
SM		 8058};
8059
8060struct mlx5_ifc_dealloc_q_counter_in_bits {
8061 u8 opcode[0x10];
b4ff3a36 8062 u8 reserved_at_10[0x10];
e281682b 8063
b4ff3a36 8064 u8 reserved_at_20[0x10];
e281682b
SM		 8065 u8 op_mod[0x10];
8066
b4ff3a36 8067 u8 reserved_at_40[0x18];
e281682b
SM		 8068 u8 counter_set_id[0x8];
8069
b4ff3a36 8070 u8 reserved_at_60[0x20];
e281682b
SM		 8071};
8072
8073struct mlx5_ifc_dealloc_pd_out_bits {
8074 u8 status[0x8];
b4ff3a36 8075 u8 reserved_at_8[0x18];
e281682b
SM		 8076
8077 u8 syndrome[0x20];
8078
b4ff3a36 8079 u8 reserved_at_40[0x40];
e281682b
SM		 8080};
8081
8082struct mlx5_ifc_dealloc_pd_in_bits {
8083 u8 opcode[0x10];
bd371975 8084 u8 uid[0x10];
e281682b 8085
b4ff3a36 8086 u8 reserved_at_20[0x10];
e281682b
SM		 8087 u8 op_mod[0x10];
8088
b4ff3a36 8089 u8 reserved_at_40[0x8];
e281682b
SM		 8090 u8 pd[0x18];
8091
b4ff3a36 8092 u8 reserved_at_60[0x20];
e281682b
SM		 8093};
8094
9dc0b289
AV		 8095struct mlx5_ifc_dealloc_flow_counter_out_bits {
8096 u8 status[0x8];
8097 u8 reserved_at_8[0x18];
8098
8099 u8 syndrome[0x20];
8100
8101 u8 reserved_at_40[0x40];
8102};
8103
8104struct mlx5_ifc_dealloc_flow_counter_in_bits {
8105 u8 opcode[0x10];
8106 u8 reserved_at_10[0x10];
8107
8108 u8 reserved_at_20[0x10];
8109 u8 op_mod[0x10];
8110
a8ffcc74 8111 u8 flow_counter_id[0x20];
9dc0b289
AV		 8112
8113 u8 reserved_at_60[0x20];
8114};
8115
7486216b
SM		 8116struct mlx5_ifc_create_xrq_out_bits {
8117 u8 status[0x8];
8118 u8 reserved_at_8[0x18];
8119
8120 u8 syndrome[0x20];
8121
8122 u8 reserved_at_40[0x8];
8123 u8 xrqn[0x18];
8124
8125 u8 reserved_at_60[0x20];
8126};
8127
8128struct mlx5_ifc_create_xrq_in_bits {
8129 u8 opcode[0x10];
a0d8c054 8130 u8 uid[0x10];
7486216b
SM		 8131
8132 u8 reserved_at_20[0x10];
8133 u8 op_mod[0x10];
8134
8135 u8 reserved_at_40[0x40];
8136
8137 struct mlx5_ifc_xrqc_bits xrq_context;
8138};
8139
e281682b
SM		 8140struct mlx5_ifc_create_xrc_srq_out_bits {
8141 u8 status[0x8];
b4ff3a36 8142 u8 reserved_at_8[0x18];
e281682b
SM		 8143
8144 u8 syndrome[0x20];
8145
b4ff3a36 8146 u8 reserved_at_40[0x8];
e281682b
SM		 8147 u8 xrc_srqn[0x18];
8148
b4ff3a36 8149 u8 reserved_at_60[0x20];
e281682b
SM		 8150};
8151
8152struct mlx5_ifc_create_xrc_srq_in_bits {
8153 u8 opcode[0x10];
a0d8c054 8154 u8 uid[0x10];
e281682b 8155
b4ff3a36 8156 u8 reserved_at_20[0x10];
e281682b
SM		 8157 u8 op_mod[0x10];
8158
b4ff3a36 8159 u8 reserved_at_40[0x40];
e281682b
SM		 8160
8161 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8162
99b77fef
YH		 8163 u8 reserved_at_280[0x60];
8164
bd371975 8165 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 8166 u8 reserved_at_2e1[0x1f];
8167
8168 u8 reserved_at_300[0x580];
e281682b 8169
b6ca09cb 8170 u8 pas[][0x40];
e281682b
SM		 8171};
8172
8173struct mlx5_ifc_create_tis_out_bits {
8174 u8 status[0x8];
b4ff3a36 8175 u8 reserved_at_8[0x18];
e281682b
SM		 8176
8177 u8 syndrome[0x20];
8178
b4ff3a36 8179 u8 reserved_at_40[0x8];
e281682b
SM		 8180 u8 tisn[0x18];
8181
b4ff3a36 8182 u8 reserved_at_60[0x20];
e281682b
SM		 8183};
8184
8185struct mlx5_ifc_create_tis_in_bits {
8186 u8 opcode[0x10];
bd371975 8187 u8 uid[0x10];
e281682b 8188
b4ff3a36 8189 u8 reserved_at_20[0x10];
e281682b
SM		 8190 u8 op_mod[0x10];
8191
b4ff3a36 8192 u8 reserved_at_40[0xc0];
e281682b
SM		 8193
8194 struct mlx5_ifc_tisc_bits ctx;
8195};
8196
8197struct mlx5_ifc_create_tir_out_bits {
8198 u8 status[0x8];
3e070470 8199 u8 icm_address_63_40[0x18];
e281682b
SM		 8200
8201 u8 syndrome[0x20];
8202
3e070470 8203 u8 icm_address_39_32[0x8];
e281682b
SM		 8204 u8 tirn[0x18];
8205
3e070470 8206 u8 icm_address_31_0[0x20];
e281682b
SM		 8207};
8208
8209struct mlx5_ifc_create_tir_in_bits {
8210 u8 opcode[0x10];
bd371975 8211 u8 uid[0x10];
e281682b 8212
b4ff3a36 8213 u8 reserved_at_20[0x10];
e281682b
SM		 8214 u8 op_mod[0x10];
8215
b4ff3a36 8216 u8 reserved_at_40[0xc0];
e281682b
SM		 8217
8218 struct mlx5_ifc_tirc_bits ctx;
8219};
8220
8221struct mlx5_ifc_create_srq_out_bits {
8222 u8 status[0x8];
b4ff3a36 8223 u8 reserved_at_8[0x18];
e281682b
SM		 8224
8225 u8 syndrome[0x20];
8226
b4ff3a36 8227 u8 reserved_at_40[0x8];
e281682b
SM		 8228 u8 srqn[0x18];
8229
b4ff3a36 8230 u8 reserved_at_60[0x20];
e281682b
SM		 8231};
8232
8233struct mlx5_ifc_create_srq_in_bits {
8234 u8 opcode[0x10];
a0d8c054 8235 u8 uid[0x10];
e281682b 8236
b4ff3a36 8237 u8 reserved_at_20[0x10];
e281682b
SM		 8238 u8 op_mod[0x10];
8239
b4ff3a36 8240 u8 reserved_at_40[0x40];
e281682b
SM		 8241
8242 struct mlx5_ifc_srqc_bits srq_context_entry;
8243
b4ff3a36 8244 u8 reserved_at_280[0x600];
e281682b 8245
b6ca09cb 8246 u8 pas[][0x40];
e281682b
SM		 8247};
8248
8249struct mlx5_ifc_create_sq_out_bits {
8250 u8 status[0x8];
b4ff3a36 8251 u8 reserved_at_8[0x18];
e281682b
SM		 8252
8253 u8 syndrome[0x20];
8254
b4ff3a36 8255 u8 reserved_at_40[0x8];
e281682b
SM		 8256 u8 sqn[0x18];
8257
b4ff3a36 8258 u8 reserved_at_60[0x20];
e281682b
SM		 8259};
8260
8261struct mlx5_ifc_create_sq_in_bits {
8262 u8 opcode[0x10];
430ae0d5 8263 u8 uid[0x10];
e281682b 8264
b4ff3a36 8265 u8 reserved_at_20[0x10];
e281682b
SM		 8266 u8 op_mod[0x10];
8267
b4ff3a36 8268 u8 reserved_at_40[0xc0];
e281682b
SM		 8269
8270 struct mlx5_ifc_sqc_bits ctx;
8271};
8272
813f8540
MHY		 8273struct mlx5_ifc_create_scheduling_element_out_bits {
8274 u8 status[0x8];
8275 u8 reserved_at_8[0x18];
8276
8277 u8 syndrome[0x20];
8278
8279 u8 reserved_at_40[0x40];
8280
8281 u8 scheduling_element_id[0x20];
8282
8283 u8 reserved_at_a0[0x160];
8284};
8285
8286struct mlx5_ifc_create_scheduling_element_in_bits {
8287 u8 opcode[0x10];
8288 u8 reserved_at_10[0x10];
8289
8290 u8 reserved_at_20[0x10];
8291 u8 op_mod[0x10];
8292
8293 u8 scheduling_hierarchy[0x8];
8294 u8 reserved_at_48[0x18];
8295
8296 u8 reserved_at_60[0xa0];
8297
8298 struct mlx5_ifc_scheduling_context_bits scheduling_context;
8299
8300 u8 reserved_at_300[0x100];
8301};
8302
e281682b
SM		 8303struct mlx5_ifc_create_rqt_out_bits {
8304 u8 status[0x8];
b4ff3a36 8305 u8 reserved_at_8[0x18];
e281682b
SM		 8306
8307 u8 syndrome[0x20];
8308
b4ff3a36 8309 u8 reserved_at_40[0x8];
e281682b
SM		 8310 u8 rqtn[0x18];
8311
b4ff3a36 8312 u8 reserved_at_60[0x20];
e281682b
SM		 8313};
8314
8315struct mlx5_ifc_create_rqt_in_bits {
8316 u8 opcode[0x10];
bd371975 8317 u8 uid[0x10];
e281682b 8318
b4ff3a36 8319 u8 reserved_at_20[0x10];
e281682b
SM		 8320 u8 op_mod[0x10];
8321
b4ff3a36 8322 u8 reserved_at_40[0xc0];
e281682b
SM		 8323
8324 struct mlx5_ifc_rqtc_bits rqt_context;
8325};
8326
8327struct mlx5_ifc_create_rq_out_bits {
8328 u8 status[0x8];
b4ff3a36 8329 u8 reserved_at_8[0x18];
e281682b
SM		 8330
8331 u8 syndrome[0x20];
8332
b4ff3a36 8333 u8 reserved_at_40[0x8];
e281682b
SM		 8334 u8 rqn[0x18];
8335
b4ff3a36 8336 u8 reserved_at_60[0x20];
e281682b
SM		 8337};
8338
8339struct mlx5_ifc_create_rq_in_bits {
8340 u8 opcode[0x10];
d269b3af 8341 u8 uid[0x10];
e281682b 8342
b4ff3a36 8343 u8 reserved_at_20[0x10];
e281682b
SM		 8344 u8 op_mod[0x10];
8345
b4ff3a36 8346 u8 reserved_at_40[0xc0];
e281682b
SM		 8347
8348 struct mlx5_ifc_rqc_bits ctx;
8349};
8350
8351struct mlx5_ifc_create_rmp_out_bits {
8352 u8 status[0x8];
b4ff3a36 8353 u8 reserved_at_8[0x18];
e281682b
SM		 8354
8355 u8 syndrome[0x20];
8356
b4ff3a36 8357 u8 reserved_at_40[0x8];
e281682b
SM		 8358 u8 rmpn[0x18];
8359
b4ff3a36 8360 u8 reserved_at_60[0x20];
e281682b
SM		 8361};
8362
8363struct mlx5_ifc_create_rmp_in_bits {
8364 u8 opcode[0x10];
a0d8c054 8365 u8 uid[0x10];
e281682b 8366
b4ff3a36 8367 u8 reserved_at_20[0x10];
e281682b
SM		 8368 u8 op_mod[0x10];
8369
b4ff3a36 8370 u8 reserved_at_40[0xc0];
e281682b
SM		 8371
8372 struct mlx5_ifc_rmpc_bits ctx;
8373};
8374
8375struct mlx5_ifc_create_qp_out_bits {
8376 u8 status[0x8];
b4ff3a36 8377 u8 reserved_at_8[0x18];
e281682b
SM		 8378
8379 u8 syndrome[0x20];
8380
b4ff3a36 8381 u8 reserved_at_40[0x8];
e281682b
SM		 8382 u8 qpn[0x18];
8383
6b646a7e 8384 u8 ece[0x20];
e281682b
SM		 8385};
8386
8387struct mlx5_ifc_create_qp_in_bits {
8388 u8 opcode[0x10];
4ac63ec7 8389 u8 uid[0x10];
e281682b 8390
b4ff3a36 8391 u8 reserved_at_20[0x10];
e281682b
SM		 8392 u8 op_mod[0x10];
8393
4dca6509
MG		 8394 u8 reserved_at_40[0x8];
8395 u8 input_qpn[0x18];
e281682b 8396
4dca6509 8397 u8 reserved_at_60[0x20];
e281682b
SM		 8398 u8 opt_param_mask[0x20];
8399
6b646a7e 8400 u8 ece[0x20];
e281682b
SM		 8401
8402 struct mlx5_ifc_qpc_bits qpc;
8403
bd371975
LR		 8404 u8 reserved_at_800[0x60];
8405
8406 u8 wq_umem_valid[0x1];
8407 u8 reserved_at_861[0x1f];
e281682b 8408
b6ca09cb 8409 u8 pas[][0x40];
e281682b
SM		 8410};
8411
8412struct mlx5_ifc_create_psv_out_bits {
8413 u8 status[0x8];
b4ff3a36 8414 u8 reserved_at_8[0x18];
e281682b
SM		 8415
8416 u8 syndrome[0x20];
8417
b4ff3a36 8418 u8 reserved_at_40[0x40];
e281682b 8419
b4ff3a36 8420 u8 reserved_at_80[0x8];
e281682b
SM		 8421 u8 psv0_index[0x18];
8422
b4ff3a36 8423 u8 reserved_at_a0[0x8];
e281682b
SM		 8424 u8 psv1_index[0x18];
8425
b4ff3a36 8426 u8 reserved_at_c0[0x8];
e281682b
SM		 8427 u8 psv2_index[0x18];
8428
b4ff3a36 8429 u8 reserved_at_e0[0x8];
e281682b
SM		 8430 u8 psv3_index[0x18];
8431};
8432
8433struct mlx5_ifc_create_psv_in_bits {
8434 u8 opcode[0x10];
b4ff3a36 8435 u8 reserved_at_10[0x10];
e281682b 8436
b4ff3a36 8437 u8 reserved_at_20[0x10];
e281682b
SM		 8438 u8 op_mod[0x10];
8439
8440 u8 num_psv[0x4];
b4ff3a36 8441 u8 reserved_at_44[0x4];
e281682b
SM		 8442 u8 pd[0x18];
8443
b4ff3a36 8444 u8 reserved_at_60[0x20];
e281682b
SM		 8445};
8446
8447struct mlx5_ifc_create_mkey_out_bits {
8448 u8 status[0x8];
b4ff3a36 8449 u8 reserved_at_8[0x18];
e281682b
SM		 8450
8451 u8 syndrome[0x20];
8452
b4ff3a36 8453 u8 reserved_at_40[0x8];
e281682b
SM		 8454 u8 mkey_index[0x18];
8455
b4ff3a36 8456 u8 reserved_at_60[0x20];
e281682b
SM		 8457};
8458
8459struct mlx5_ifc_create_mkey_in_bits {
8460 u8 opcode[0x10];
8a06a79b 8461 u8 uid[0x10];
e281682b 8462
b4ff3a36 8463 u8 reserved_at_20[0x10];
e281682b
SM		 8464 u8 op_mod[0x10];
8465
b4ff3a36 8466 u8 reserved_at_40[0x20];
e281682b
SM		 8467
8468 u8 pg_access[0x1];
bd371975
LR		 8469 u8 mkey_umem_valid[0x1];
8470 u8 reserved_at_62[0x1e];
e281682b
SM		 8471
8472 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8473
b4ff3a36 8474 u8 reserved_at_280[0x80];
e281682b
SM		 8475
8476 u8 translations_octword_actual_size[0x20];
8477
b4ff3a36 8478 u8 reserved_at_320[0x560];
e281682b 8479
b6ca09cb 8480 u8 klm_pas_mtt[][0x20];
e281682b
SM		 8481};
8482
97b5484e
AV		 8483enum {
8484 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8485 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8486 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8487 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8488 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8489 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8490 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8491};
8492
e281682b
SM		 8493struct mlx5_ifc_create_flow_table_out_bits {
8494 u8 status[0x8];
97b5484e 8495 u8 icm_address_63_40[0x18];
e281682b
SM		 8496
8497 u8 syndrome[0x20];
8498
97b5484e 8499 u8 icm_address_39_32[0x8];
e281682b
SM		 8500 u8 table_id[0x18];
8501
97b5484e 8502 u8 icm_address_31_0[0x20];
0c90e9c6
MG		 8503};
8504
e281682b
SM		 8505struct mlx5_ifc_create_flow_table_in_bits {
8506 u8 opcode[0x10];
b4ff3a36 8507 u8 reserved_at_10[0x10];
e281682b 8508
b4ff3a36 8509 u8 reserved_at_20[0x10];
e281682b
SM		 8510 u8 op_mod[0x10];
8511
7d5e1423
SM		 8512 u8 other_vport[0x1];
8513 u8 reserved_at_41[0xf];
8514 u8 vport_number[0x10];
8515
8516 u8 reserved_at_60[0x20];
e281682b
SM		 8517
8518 u8 table_type[0x8];
b4ff3a36 8519 u8 reserved_at_88[0x18];
e281682b 8520
b4ff3a36 8521 u8 reserved_at_a0[0x20];
e281682b 8522
0c90e9c6 8523 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 8524};
8525
8526struct mlx5_ifc_create_flow_group_out_bits {
8527 u8 status[0x8];
b4ff3a36 8528 u8 reserved_at_8[0x18];
e281682b
SM		 8529
8530 u8 syndrome[0x20];
8531
b4ff3a36 8532 u8 reserved_at_40[0x8];
e281682b
SM		 8533 u8 group_id[0x18];
8534
b4ff3a36 8535 u8 reserved_at_60[0x20];
e281682b
SM		 8536};
8537
e7e2519e
MG		 8538enum {
8539 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8540 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8541};
8542
e281682b 8543enum {
71c6e863
AL		 8544 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8545 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8546 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8547 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 8548};
8549
8550struct mlx5_ifc_create_flow_group_in_bits {
8551 u8 opcode[0x10];
b4ff3a36 8552 u8 reserved_at_10[0x10];
e281682b 8553
b4ff3a36 8554 u8 reserved_at_20[0x10];
e281682b
SM		 8555 u8 op_mod[0x10];
8556
7d5e1423
SM		 8557 u8 other_vport[0x1];
8558 u8 reserved_at_41[0xf];
8559 u8 vport_number[0x10];
8560
8561 u8 reserved_at_60[0x20];
e281682b
SM		 8562
8563 u8 table_type[0x8];
e7e2519e
MG		 8564 u8 reserved_at_88[0x4];
8565 u8 group_type[0x4];
8566 u8 reserved_at_90[0x10];
e281682b 8567
b4ff3a36 8568 u8 reserved_at_a0[0x8];
e281682b
SM		 8569 u8 table_id[0x18];
8570
3e99df87
SK		 8571 u8 source_eswitch_owner_vhca_id_valid[0x1];
8572
8573 u8 reserved_at_c1[0x1f];
e281682b
SM		 8574
8575 u8 start_flow_index[0x20];
8576
b4ff3a36 8577 u8 reserved_at_100[0x20];
e281682b
SM		 8578
8579 u8 end_flow_index[0x20];
8580
e7e2519e
MG		 8581 u8 reserved_at_140[0x10];
8582 u8 match_definer_id[0x10];
8583
8584 u8 reserved_at_160[0x80];
e281682b 8585
b4ff3a36 8586 u8 reserved_at_1e0[0x18];
e281682b
SM		 8587 u8 match_criteria_enable[0x8];
8588
8589 struct mlx5_ifc_fte_match_param_bits match_criteria;
8590
b4ff3a36 8591 u8 reserved_at_1200[0xe00];
e281682b
SM		 8592};
8593
8594struct mlx5_ifc_create_eq_out_bits {
8595 u8 status[0x8];
b4ff3a36 8596 u8 reserved_at_8[0x18];
e281682b
SM		 8597
8598 u8 syndrome[0x20];
8599
b4ff3a36 8600 u8 reserved_at_40[0x18];
e281682b
SM		 8601 u8 eq_number[0x8];
8602
b4ff3a36 8603 u8 reserved_at_60[0x20];
e281682b
SM		 8604};
8605
8606struct mlx5_ifc_create_eq_in_bits {
8607 u8 opcode[0x10];
c191f934 8608 u8 uid[0x10];
e281682b 8609
b4ff3a36 8610 u8 reserved_at_20[0x10];
e281682b
SM		 8611 u8 op_mod[0x10];
8612
b4ff3a36 8613 u8 reserved_at_40[0x40];
e281682b
SM		 8614
8615 struct mlx5_ifc_eqc_bits eq_context_entry;
8616
b4ff3a36 8617 u8 reserved_at_280[0x40];
e281682b 8618
b9a7ba55 8619 u8 event_bitmask[4][0x40];
e281682b 8620
b9a7ba55 8621 u8 reserved_at_3c0[0x4c0];
e281682b 8622
b6ca09cb 8623 u8 pas[][0x40];
e281682b
SM		 8624};
8625
8626struct mlx5_ifc_create_dct_out_bits {
8627 u8 status[0x8];
b4ff3a36 8628 u8 reserved_at_8[0x18];
e281682b
SM		 8629
8630 u8 syndrome[0x20];
8631
b4ff3a36 8632 u8 reserved_at_40[0x8];
e281682b
SM		 8633 u8 dctn[0x18];
8634
a645a89d 8635 u8 ece[0x20];
e281682b
SM		 8636};
8637
8638struct mlx5_ifc_create_dct_in_bits {
8639 u8 opcode[0x10];
774ea6ee 8640 u8 uid[0x10];
e281682b 8641
b4ff3a36 8642 u8 reserved_at_20[0x10];
e281682b
SM		 8643 u8 op_mod[0x10];
8644
b4ff3a36 8645 u8 reserved_at_40[0x40];
e281682b
SM		 8646
8647 struct mlx5_ifc_dctc_bits dct_context_entry;
8648
b4ff3a36 8649 u8 reserved_at_280[0x180];
e281682b
SM		 8650};
8651
8652struct mlx5_ifc_create_cq_out_bits {
8653 u8 status[0x8];
b4ff3a36 8654 u8 reserved_at_8[0x18];
e281682b
SM		 8655
8656 u8 syndrome[0x20];
8657
b4ff3a36 8658 u8 reserved_at_40[0x8];
e281682b
SM		 8659 u8 cqn[0x18];
8660
b4ff3a36 8661 u8 reserved_at_60[0x20];
e281682b
SM		 8662};
8663
8664struct mlx5_ifc_create_cq_in_bits {
8665 u8 opcode[0x10];
9ba481e2 8666 u8 uid[0x10];
e281682b 8667
b4ff3a36 8668 u8 reserved_at_20[0x10];
e281682b
SM		 8669 u8 op_mod[0x10];
8670
b4ff3a36 8671 u8 reserved_at_40[0x40];
e281682b
SM		 8672
8673 struct mlx5_ifc_cqc_bits cq_context;
8674
bd371975
LR		 8675 u8 reserved_at_280[0x60];
8676
8677 u8 cq_umem_valid[0x1];
8678 u8 reserved_at_2e1[0x59f];
e281682b 8679
b6ca09cb 8680 u8 pas[][0x40];
e281682b
SM		 8681};
8682
8683struct mlx5_ifc_config_int_moderation_out_bits {
8684 u8 status[0x8];
b4ff3a36 8685 u8 reserved_at_8[0x18];
e281682b
SM		 8686
8687 u8 syndrome[0x20];
8688
b4ff3a36 8689 u8 reserved_at_40[0x4];
e281682b
SM		 8690 u8 min_delay[0xc];
8691 u8 int_vector[0x10];
8692
b4ff3a36 8693 u8 reserved_at_60[0x20];
e281682b
SM		 8694};
8695
8696enum {
8697 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8698 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8699};
8700
8701struct mlx5_ifc_config_int_moderation_in_bits {
8702 u8 opcode[0x10];
b4ff3a36 8703 u8 reserved_at_10[0x10];
e281682b 8704
b4ff3a36 8705 u8 reserved_at_20[0x10];
e281682b
SM		 8706 u8 op_mod[0x10];
8707
b4ff3a36 8708 u8 reserved_at_40[0x4];
e281682b
SM		 8709 u8 min_delay[0xc];
8710 u8 int_vector[0x10];
8711
b4ff3a36 8712 u8 reserved_at_60[0x20];
e281682b
SM		 8713};
8714
8715struct mlx5_ifc_attach_to_mcg_out_bits {
8716 u8 status[0x8];
b4ff3a36 8717 u8 reserved_at_8[0x18];
e281682b
SM		 8718
8719 u8 syndrome[0x20];
8720
b4ff3a36 8721 u8 reserved_at_40[0x40];
e281682b
SM		 8722};
8723
8724struct mlx5_ifc_attach_to_mcg_in_bits {
8725 u8 opcode[0x10];
bd371975 8726 u8 uid[0x10];
e281682b 8727
b4ff3a36 8728 u8 reserved_at_20[0x10];
e281682b
SM		 8729 u8 op_mod[0x10];
8730
b4ff3a36 8731 u8 reserved_at_40[0x8];
e281682b
SM		 8732 u8 qpn[0x18];
8733
b4ff3a36 8734 u8 reserved_at_60[0x20];
e281682b
SM		 8735
8736 u8 multicast_gid[16][0x8];
8737};
8738
7486216b
SM		 8739struct mlx5_ifc_arm_xrq_out_bits {
8740 u8 status[0x8];
8741 u8 reserved_at_8[0x18];
8742
8743 u8 syndrome[0x20];
8744
8745 u8 reserved_at_40[0x40];
8746};
8747
8748struct mlx5_ifc_arm_xrq_in_bits {
8749 u8 opcode[0x10];
8750 u8 reserved_at_10[0x10];
8751
8752 u8 reserved_at_20[0x10];
8753 u8 op_mod[0x10];
8754
8755 u8 reserved_at_40[0x8];
8756 u8 xrqn[0x18];
8757
8758 u8 reserved_at_60[0x10];
8759 u8 lwm[0x10];
8760};
8761
e281682b
SM		 8762struct mlx5_ifc_arm_xrc_srq_out_bits {
8763 u8 status[0x8];
b4ff3a36 8764 u8 reserved_at_8[0x18];
e281682b
SM		 8765
8766 u8 syndrome[0x20];
8767
b4ff3a36 8768 u8 reserved_at_40[0x40];
e281682b
SM		 8769};
8770
8771enum {
8772 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8773};
8774
8775struct mlx5_ifc_arm_xrc_srq_in_bits {
8776 u8 opcode[0x10];
a0d8c054 8777 u8 uid[0x10];
e281682b 8778
b4ff3a36 8779 u8 reserved_at_20[0x10];
e281682b
SM		 8780 u8 op_mod[0x10];
8781
b4ff3a36 8782 u8 reserved_at_40[0x8];
e281682b
SM		 8783 u8 xrc_srqn[0x18];
8784
b4ff3a36 8785 u8 reserved_at_60[0x10];
e281682b
SM		 8786 u8 lwm[0x10];
8787};
8788
8789struct mlx5_ifc_arm_rq_out_bits {
8790 u8 status[0x8];
b4ff3a36 8791 u8 reserved_at_8[0x18];
e281682b
SM		 8792
8793 u8 syndrome[0x20];
8794
b4ff3a36 8795 u8 reserved_at_40[0x40];
e281682b
SM		 8796};
8797
8798enum {
7486216b
SM		 8799 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8800 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 8801};
8802
8803struct mlx5_ifc_arm_rq_in_bits {
8804 u8 opcode[0x10];
a0d8c054 8805 u8 uid[0x10];
e281682b 8806
b4ff3a36 8807 u8 reserved_at_20[0x10];
e281682b
SM		 8808 u8 op_mod[0x10];
8809
b4ff3a36 8810 u8 reserved_at_40[0x8];
e281682b
SM		 8811 u8 srq_number[0x18];
8812
b4ff3a36 8813 u8 reserved_at_60[0x10];
e281682b
SM		 8814 u8 lwm[0x10];
8815};
8816
8817struct mlx5_ifc_arm_dct_out_bits {
8818 u8 status[0x8];
b4ff3a36 8819 u8 reserved_at_8[0x18];
e281682b
SM		 8820
8821 u8 syndrome[0x20];
8822
b4ff3a36 8823 u8 reserved_at_40[0x40];
e281682b
SM		 8824};
8825
8826struct mlx5_ifc_arm_dct_in_bits {
8827 u8 opcode[0x10];
b4ff3a36 8828 u8 reserved_at_10[0x10];
e281682b 8829
b4ff3a36 8830 u8 reserved_at_20[0x10];
e281682b
SM		 8831 u8 op_mod[0x10];
8832
b4ff3a36 8833 u8 reserved_at_40[0x8];
e281682b
SM		 8834 u8 dct_number[0x18];
8835
b4ff3a36 8836 u8 reserved_at_60[0x20];
e281682b
SM		 8837};
8838
8839struct mlx5_ifc_alloc_xrcd_out_bits {
8840 u8 status[0x8];
b4ff3a36 8841 u8 reserved_at_8[0x18];
e281682b
SM		 8842
8843 u8 syndrome[0x20];
8844
b4ff3a36 8845 u8 reserved_at_40[0x8];
e281682b
SM		 8846 u8 xrcd[0x18];
8847
b4ff3a36 8848 u8 reserved_at_60[0x20];
e281682b
SM		 8849};
8850
8851struct mlx5_ifc_alloc_xrcd_in_bits {
8852 u8 opcode[0x10];
bd371975 8853 u8 uid[0x10];
e281682b 8854
b4ff3a36 8855 u8 reserved_at_20[0x10];
e281682b
SM		 8856 u8 op_mod[0x10];
8857
b4ff3a36 8858 u8 reserved_at_40[0x40];
e281682b
SM		 8859};
8860
8861struct mlx5_ifc_alloc_uar_out_bits {
8862 u8 status[0x8];
b4ff3a36 8863 u8 reserved_at_8[0x18];
e281682b
SM		 8864
8865 u8 syndrome[0x20];
8866
b4ff3a36 8867 u8 reserved_at_40[0x8];
e281682b
SM		 8868 u8 uar[0x18];
8869
b4ff3a36 8870 u8 reserved_at_60[0x20];
e281682b
SM		 8871};
8872
8873struct mlx5_ifc_alloc_uar_in_bits {
8874 u8 opcode[0x10];
8de1e9b0 8875 u8 uid[0x10];
e281682b 8876
b4ff3a36 8877 u8 reserved_at_20[0x10];
e281682b
SM		 8878 u8 op_mod[0x10];
8879
b4ff3a36 8880 u8 reserved_at_40[0x40];
e281682b
SM		 8881};
8882
8883struct mlx5_ifc_alloc_transport_domain_out_bits {
8884 u8 status[0x8];
b4ff3a36 8885 u8 reserved_at_8[0x18];
e281682b
SM		 8886
8887 u8 syndrome[0x20];
8888
b4ff3a36 8889 u8 reserved_at_40[0x8];
e281682b
SM		 8890 u8 transport_domain[0x18];
8891
b4ff3a36 8892 u8 reserved_at_60[0x20];
e281682b
SM		 8893};
8894
8895struct mlx5_ifc_alloc_transport_domain_in_bits {
8896 u8 opcode[0x10];
71bef2fd 8897 u8 uid[0x10];
e281682b 8898
b4ff3a36 8899 u8 reserved_at_20[0x10];
e281682b
SM		 8900 u8 op_mod[0x10];
8901
b4ff3a36 8902 u8 reserved_at_40[0x40];
e281682b
SM		 8903};
8904
8905struct mlx5_ifc_alloc_q_counter_out_bits {
8906 u8 status[0x8];
b4ff3a36 8907 u8 reserved_at_8[0x18];
e281682b
SM		 8908
8909 u8 syndrome[0x20];
8910
b4ff3a36 8911 u8 reserved_at_40[0x18];
e281682b
SM		 8912 u8 counter_set_id[0x8];
8913
b4ff3a36 8914 u8 reserved_at_60[0x20];
e281682b
SM		 8915};
8916
8917struct mlx5_ifc_alloc_q_counter_in_bits {
8918 u8 opcode[0x10];
2acc7957 8919 u8 uid[0x10];
e281682b 8920
b4ff3a36 8921 u8 reserved_at_20[0x10];
e281682b
SM		 8922 u8 op_mod[0x10];
8923
b4ff3a36 8924 u8 reserved_at_40[0x40];
e281682b
SM		 8925};
8926
8927struct mlx5_ifc_alloc_pd_out_bits {
8928 u8 status[0x8];
b4ff3a36 8929 u8 reserved_at_8[0x18];
e281682b
SM		 8930
8931 u8 syndrome[0x20];
8932
b4ff3a36 8933 u8 reserved_at_40[0x8];
e281682b
SM		 8934 u8 pd[0x18];
8935
b4ff3a36 8936 u8 reserved_at_60[0x20];
e281682b
SM		 8937};
8938
8939struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 8940 u8 opcode[0x10];
bd371975 8941 u8 uid[0x10];
9dc0b289
AV		 8942
8943 u8 reserved_at_20[0x10];
8944 u8 op_mod[0x10];
8945
8946 u8 reserved_at_40[0x40];
8947};
8948
8949struct mlx5_ifc_alloc_flow_counter_out_bits {
8950 u8 status[0x8];
8951 u8 reserved_at_8[0x18];
8952
8953 u8 syndrome[0x20];
8954
a8ffcc74 8955 u8 flow_counter_id[0x20];
9dc0b289
AV		 8956
8957 u8 reserved_at_60[0x20];
8958};
8959
8960struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 8961 u8 opcode[0x10];
b4ff3a36 8962 u8 reserved_at_10[0x10];
e281682b 8963
b4ff3a36 8964 u8 reserved_at_20[0x10];
e281682b
SM		 8965 u8 op_mod[0x10];
8966
8536a6bf
GT		 8967 u8 reserved_at_40[0x38];
8968 u8 flow_counter_bulk[0x8];
e281682b
SM		 8969};
8970
8971struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8972 u8 status[0x8];
b4ff3a36 8973 u8 reserved_at_8[0x18];
e281682b
SM		 8974
8975 u8 syndrome[0x20];
8976
b4ff3a36 8977 u8 reserved_at_40[0x40];
e281682b
SM		 8978};
8979
8980struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8981 u8 opcode[0x10];
b4ff3a36 8982 u8 reserved_at_10[0x10];
e281682b 8983
b4ff3a36 8984 u8 reserved_at_20[0x10];
e281682b
SM		 8985 u8 op_mod[0x10];
8986
b4ff3a36 8987 u8 reserved_at_40[0x20];
e281682b 8988
b4ff3a36 8989 u8 reserved_at_60[0x10];
e281682b
SM		 8990 u8 vxlan_udp_port[0x10];
8991};
8992
37e92a9d 8993struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 8994 u8 status[0x8];
8995 u8 reserved_at_8[0x18];
8996
8997 u8 syndrome[0x20];
8998
8999 u8 reserved_at_40[0x40];
9000};
9001
1326034b
YH		 9002struct mlx5_ifc_set_pp_rate_limit_context_bits {
9003 u8 rate_limit[0x20];
9004
9005 u8 burst_upper_bound[0x20];
9006
9007 u8 reserved_at_40[0x10];
9008 u8 typical_packet_size[0x10];
9009
9010 u8 reserved_at_60[0x120];
9011};
9012
37e92a9d 9013struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b 9014 u8 opcode[0x10];
1326034b 9015 u8 uid[0x10];
7486216b
SM		 9016
9017 u8 reserved_at_20[0x10];
9018 u8 op_mod[0x10];
9019
9020 u8 reserved_at_40[0x10];
9021 u8 rate_limit_index[0x10];
9022
9023 u8 reserved_at_60[0x20];
9024
1326034b 9025 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
7486216b
SM		 9026};
9027
e281682b
SM		 9028struct mlx5_ifc_access_register_out_bits {
9029 u8 status[0x8];
b4ff3a36 9030 u8 reserved_at_8[0x18];
e281682b
SM		 9031
9032 u8 syndrome[0x20];
9033
b4ff3a36 9034 u8 reserved_at_40[0x40];
e281682b 9035
b6ca09cb 9036 u8 register_data[][0x20];
e281682b
SM		 9037};
9038
9039enum {
9040 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
9041 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
9042};
9043
9044struct mlx5_ifc_access_register_in_bits {
9045 u8 opcode[0x10];
b4ff3a36 9046 u8 reserved_at_10[0x10];
e281682b 9047
b4ff3a36 9048 u8 reserved_at_20[0x10];
e281682b
SM		 9049 u8 op_mod[0x10];
9050
b4ff3a36 9051 u8 reserved_at_40[0x10];
e281682b
SM		 9052 u8 register_id[0x10];
9053
9054 u8 argument[0x20];
9055
b6ca09cb 9056 u8 register_data[][0x20];
e281682b
SM		 9057};
9058
9059struct mlx5_ifc_sltp_reg_bits {
9060 u8 status[0x4];
9061 u8 version[0x4];
9062 u8 local_port[0x8];
9063 u8 pnat[0x2];
b4ff3a36 9064 u8 reserved_at_12[0x2];
e281682b 9065 u8 lane[0x4];
b4ff3a36 9066 u8 reserved_at_18[0x8];
e281682b 9067
b4ff3a36 9068 u8 reserved_at_20[0x20];
e281682b 9069
b4ff3a36 9070 u8 reserved_at_40[0x7];
e281682b
SM		 9071 u8 polarity[0x1];
9072 u8 ob_tap0[0x8];
9073 u8 ob_tap1[0x8];
9074 u8 ob_tap2[0x8];
9075
b4ff3a36 9076 u8 reserved_at_60[0xc];
e281682b
SM		 9077 u8 ob_preemp_mode[0x4];
9078 u8 ob_reg[0x8];
9079 u8 ob_bias[0x8];
9080
b4ff3a36 9081 u8 reserved_at_80[0x20];
e281682b
SM		 9082};
9083
9084struct mlx5_ifc_slrg_reg_bits {
9085 u8 status[0x4];
9086 u8 version[0x4];
9087 u8 local_port[0x8];
9088 u8 pnat[0x2];
b4ff3a36 9089 u8 reserved_at_12[0x2];
e281682b 9090 u8 lane[0x4];
b4ff3a36 9091 u8 reserved_at_18[0x8];
e281682b
SM		 9092
9093 u8 time_to_link_up[0x10];
b4ff3a36 9094 u8 reserved_at_30[0xc];
e281682b
SM		 9095 u8 grade_lane_speed[0x4];
9096
9097 u8 grade_version[0x8];
9098 u8 grade[0x18];
9099
b4ff3a36 9100 u8 reserved_at_60[0x4];
e281682b
SM		 9101 u8 height_grade_type[0x4];
9102 u8 height_grade[0x18];
9103
9104 u8 height_dz[0x10];
9105 u8 height_dv[0x10];
9106
b4ff3a36 9107 u8 reserved_at_a0[0x10];
e281682b
SM		 9108 u8 height_sigma[0x10];
9109
b4ff3a36 9110 u8 reserved_at_c0[0x20];
e281682b 9111
b4ff3a36 9112 u8 reserved_at_e0[0x4];
e281682b
SM		 9113 u8 phase_grade_type[0x4];
9114 u8 phase_grade[0x18];
9115
b4ff3a36 9116 u8 reserved_at_100[0x8];
e281682b 9117 u8 phase_eo_pos[0x8];
b4ff3a36 9118 u8 reserved_at_110[0x8];
e281682b
SM		 9119 u8 phase_eo_neg[0x8];
9120
9121 u8 ffe_set_tested[0x10];
9122 u8 test_errors_per_lane[0x10];
9123};
9124
9125struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 9126 u8 reserved_at_0[0x8];
e281682b 9127 u8 local_port[0x8];
b4ff3a36 9128 u8 reserved_at_10[0x10];
e281682b 9129
b4ff3a36 9130 u8 reserved_at_20[0x1c];
e281682b
SM		 9131 u8 vl_hw_cap[0x4];
9132
b4ff3a36 9133 u8 reserved_at_40[0x1c];
e281682b
SM		 9134 u8 vl_admin[0x4];
9135
b4ff3a36 9136 u8 reserved_at_60[0x1c];
e281682b
SM		 9137 u8 vl_operational[0x4];
9138};
9139
9140struct mlx5_ifc_pude_reg_bits {
9141 u8 swid[0x8];
9142 u8 local_port[0x8];
b4ff3a36 9143 u8 reserved_at_10[0x4];
e281682b 9144 u8 admin_status[0x4];
b4ff3a36 9145 u8 reserved_at_18[0x4];
e281682b
SM		 9146 u8 oper_status[0x4];
9147
b4ff3a36 9148 u8 reserved_at_20[0x60];
e281682b
SM		 9149};
9150
9151struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 9152 u8 reserved_at_0[0x1];
7486216b 9153 u8 an_disable_admin[0x1];
e7e31ca4
BW		 9154 u8 an_disable_cap[0x1];
9155 u8 reserved_at_3[0x5];
e281682b 9156 u8 local_port[0x8];
b4ff3a36 9157 u8 reserved_at_10[0xd];
e281682b
SM		 9158 u8 proto_mask[0x3];
9159
7486216b 9160 u8 an_status[0x4];
dc392fc5
MB		 9161 u8 reserved_at_24[0xc];
9162 u8 data_rate_oper[0x10];
a0a89989
AL		 9163
9164 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 9165
9166 u8 eth_proto_capability[0x20];
9167
9168 u8 ib_link_width_capability[0x10];
9169 u8 ib_proto_capability[0x10];
9170
a0a89989 9171 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 9172
9173 u8 eth_proto_admin[0x20];
9174
9175 u8 ib_link_width_admin[0x10];
9176 u8 ib_proto_admin[0x10];
9177
a0a89989 9178 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 9179
9180 u8 eth_proto_oper[0x20];
9181
9182 u8 ib_link_width_oper[0x10];
9183 u8 ib_proto_oper[0x10];
9184
5b4793f8
EBE		 9185 u8 reserved_at_160[0x1c];
9186 u8 connector_type[0x4];
e281682b
SM		 9187
9188 u8 eth_proto_lp_advertise[0x20];
9189
b4ff3a36 9190 u8 reserved_at_1a0[0x60];
e281682b
SM		 9191};
9192
7d5e1423
SM		 9193struct mlx5_ifc_mlcr_reg_bits {
9194 u8 reserved_at_0[0x8];
9195 u8 local_port[0x8];
9196 u8 reserved_at_10[0x20];
9197
9198 u8 beacon_duration[0x10];
9199 u8 reserved_at_40[0x10];
9200
9201 u8 beacon_remain[0x10];
9202};
9203
e281682b 9204struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 9205 u8 reserved_at_0[0x20];
e281682b
SM		 9206
9207 u8 algorithm_options[0x10];
b4ff3a36 9208 u8 reserved_at_30[0x4];
e281682b
SM		 9209 u8 repetitions_mode[0x4];
9210 u8 num_of_repetitions[0x8];
9211
9212 u8 grade_version[0x8];
9213 u8 height_grade_type[0x4];
9214 u8 phase_grade_type[0x4];
9215 u8 height_grade_weight[0x8];
9216 u8 phase_grade_weight[0x8];
9217
9218 u8 gisim_measure_bits[0x10];
9219 u8 adaptive_tap_measure_bits[0x10];
9220
9221 u8 ber_bath_high_error_threshold[0x10];
9222 u8 ber_bath_mid_error_threshold[0x10];
9223
9224 u8 ber_bath_low_error_threshold[0x10];
9225 u8 one_ratio_high_threshold[0x10];
9226
9227 u8 one_ratio_high_mid_threshold[0x10];
9228 u8 one_ratio_low_mid_threshold[0x10];
9229
9230 u8 one_ratio_low_threshold[0x10];
9231 u8 ndeo_error_threshold[0x10];
9232
9233 u8 mixer_offset_step_size[0x10];
b4ff3a36 9234 u8 reserved_at_110[0x8];
e281682b
SM		 9235 u8 mix90_phase_for_voltage_bath[0x8];
9236
9237 u8 mixer_offset_start[0x10];
9238 u8 mixer_offset_end[0x10];
9239
b4ff3a36 9240 u8 reserved_at_140[0x15];
e281682b
SM		 9241 u8 ber_test_time[0xb];
9242};
9243
9244struct mlx5_ifc_pspa_reg_bits {
9245 u8 swid[0x8];
9246 u8 local_port[0x8];
9247 u8 sub_port[0x8];
b4ff3a36 9248 u8 reserved_at_18[0x8];
e281682b 9249
b4ff3a36 9250 u8 reserved_at_20[0x20];
e281682b
SM		 9251};
9252
9253struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 9254 u8 reserved_at_0[0x8];
e281682b 9255 u8 local_port[0x8];
b4ff3a36 9256 u8 reserved_at_10[0x5];
e281682b 9257 u8 prio[0x3];
b4ff3a36 9258 u8 reserved_at_18[0x6];
e281682b
SM		 9259 u8 mode[0x2];
9260
b4ff3a36 9261 u8 reserved_at_20[0x20];
e281682b 9262
b4ff3a36 9263 u8 reserved_at_40[0x10];
e281682b
SM		 9264 u8 min_threshold[0x10];
9265
b4ff3a36 9266 u8 reserved_at_60[0x10];
e281682b
SM		 9267 u8 max_threshold[0x10];
9268
b4ff3a36 9269 u8 reserved_at_80[0x10];
e281682b
SM		 9270 u8 mark_probability_denominator[0x10];
9271
b4ff3a36 9272 u8 reserved_at_a0[0x60];
e281682b
SM		 9273};
9274
9275struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 9276 u8 reserved_at_0[0x8];
e281682b 9277 u8 local_port[0x8];
b4ff3a36 9278 u8 reserved_at_10[0x10];
e281682b 9279
b4ff3a36 9280 u8 reserved_at_20[0x60];
e281682b 9281
b4ff3a36 9282 u8 reserved_at_80[0x1c];
e281682b
SM		 9283 u8 wrps_admin[0x4];
9284
b4ff3a36 9285 u8 reserved_at_a0[0x1c];
e281682b
SM		 9286 u8 wrps_status[0x4];
9287
b4ff3a36 9288 u8 reserved_at_c0[0x8];
e281682b 9289 u8 up_threshold[0x8];
b4ff3a36 9290 u8 reserved_at_d0[0x8];
e281682b
SM		 9291 u8 down_threshold[0x8];
9292
b4ff3a36 9293 u8 reserved_at_e0[0x20];
e281682b 9294
b4ff3a36 9295 u8 reserved_at_100[0x1c];
e281682b
SM		 9296 u8 srps_admin[0x4];
9297
b4ff3a36 9298 u8 reserved_at_120[0x1c];
e281682b
SM		 9299 u8 srps_status[0x4];
9300
b4ff3a36 9301 u8 reserved_at_140[0x40];
e281682b
SM		 9302};
9303
9304struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 9305 u8 reserved_at_0[0x8];
e281682b 9306 u8 local_port[0x8];
b4ff3a36 9307 u8 reserved_at_10[0x10];
e281682b 9308
b4ff3a36 9309 u8 reserved_at_20[0x8];
e281682b 9310 u8 lb_cap[0x8];
b4ff3a36 9311 u8 reserved_at_30[0x8];
e281682b
SM		 9312 u8 lb_en[0x8];
9313};
9314
9315struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 9316 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 9317 u8 local_port[0x8];
9318 u8 reserved_at_10[0x10];
e281682b 9319
4b5b9c7d 9320 u8 reserved_at_20[0x20];
e281682b 9321
4b5b9c7d
SA		 9322 u8 port_profile_mode[0x8];
9323 u8 static_port_profile[0x8];
9324 u8 active_port_profile[0x8];
9325 u8 reserved_at_58[0x8];
e281682b 9326
4b5b9c7d
SA		 9327 u8 retransmission_active[0x8];
9328 u8 fec_mode_active[0x18];
e281682b 9329
4b5b9c7d
SA		 9330 u8 rs_fec_correction_bypass_cap[0x4];
9331 u8 reserved_at_84[0x8];
9332 u8 fec_override_cap_56g[0x4];
9333 u8 fec_override_cap_100g[0x4];
9334 u8 fec_override_cap_50g[0x4];
9335 u8 fec_override_cap_25g[0x4];
9336 u8 fec_override_cap_10g_40g[0x4];
9337
9338 u8 rs_fec_correction_bypass_admin[0x4];
9339 u8 reserved_at_a4[0x8];
9340 u8 fec_override_admin_56g[0x4];
9341 u8 fec_override_admin_100g[0x4];
9342 u8 fec_override_admin_50g[0x4];
9343 u8 fec_override_admin_25g[0x4];
9344 u8 fec_override_admin_10g_40g[0x4];
a58837f5
AL		 9345
9346 u8 fec_override_cap_400g_8x[0x10];
9347 u8 fec_override_cap_200g_4x[0x10];
9348
9349 u8 fec_override_cap_100g_2x[0x10];
9350 u8 fec_override_cap_50g_1x[0x10];
9351
9352 u8 fec_override_admin_400g_8x[0x10];
9353 u8 fec_override_admin_200g_4x[0x10];
9354
9355 u8 fec_override_admin_100g_2x[0x10];
9356 u8 fec_override_admin_50g_1x[0x10];
ce28f0fd
AL		 9357
9358 u8 reserved_at_140[0x140];
e281682b
SM		 9359};
9360
9361struct mlx5_ifc_ppcnt_reg_bits {
9362 u8 swid[0x8];
9363 u8 local_port[0x8];
9364 u8 pnat[0x2];
b4ff3a36 9365 u8 reserved_at_12[0x8];
e281682b
SM		 9366 u8 grp[0x6];
9367
9368 u8 clr[0x1];
b4ff3a36 9369 u8 reserved_at_21[0x1c];
e281682b
SM		 9370 u8 prio_tc[0x3];
9371
9372 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9373};
9374
4039049b
AL		 9375struct mlx5_ifc_mpein_reg_bits {
9376 u8 reserved_at_0[0x2];
9377 u8 depth[0x6];
9378 u8 pcie_index[0x8];
9379 u8 node[0x8];
9380 u8 reserved_at_18[0x8];
9381
9382 u8 capability_mask[0x20];
9383
9384 u8 reserved_at_40[0x8];
9385 u8 link_width_enabled[0x8];
9386 u8 link_speed_enabled[0x10];
9387
9388 u8 lane0_physical_position[0x8];
9389 u8 link_width_active[0x8];
9390 u8 link_speed_active[0x10];
9391
9392 u8 num_of_pfs[0x10];
9393 u8 num_of_vfs[0x10];
9394
9395 u8 bdf0[0x10];
9396 u8 reserved_at_b0[0x10];
9397
9398 u8 max_read_request_size[0x4];
9399 u8 max_payload_size[0x4];
9400 u8 reserved_at_c8[0x5];
9401 u8 pwr_status[0x3];
9402 u8 port_type[0x4];
9403 u8 reserved_at_d4[0xb];
9404 u8 lane_reversal[0x1];
9405
9406 u8 reserved_at_e0[0x14];
9407 u8 pci_power[0xc];
9408
9409 u8 reserved_at_100[0x20];
9410
9411 u8 device_status[0x10];
9412 u8 port_state[0x8];
9413 u8 reserved_at_138[0x8];
9414
9415 u8 reserved_at_140[0x10];
9416 u8 receiver_detect_result[0x10];
9417
9418 u8 reserved_at_160[0x20];
9419};
9420
8ed1a630
GP		 9421struct mlx5_ifc_mpcnt_reg_bits {
9422 u8 reserved_at_0[0x8];
9423 u8 pcie_index[0x8];
9424 u8 reserved_at_10[0xa];
9425 u8 grp[0x6];
9426
9427 u8 clr[0x1];
9428 u8 reserved_at_21[0x1f];
9429
9430 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9431};
9432
e281682b 9433struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 9434 u8 reserved_at_0[0x3];
e281682b 9435 u8 single_mac[0x1];
b4ff3a36 9436 u8 reserved_at_4[0x4];
e281682b
SM		 9437 u8 local_port[0x8];
9438 u8 mac_47_32[0x10];
9439
9440 u8 mac_31_0[0x20];
9441
b4ff3a36 9442 u8 reserved_at_40[0x40];
e281682b
SM		 9443};
9444
9445struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 9446 u8 reserved_at_0[0x8];
e281682b 9447 u8 local_port[0x8];
b4ff3a36 9448 u8 reserved_at_10[0x10];
e281682b
SM		 9449
9450 u8 max_mtu[0x10];
b4ff3a36 9451 u8 reserved_at_30[0x10];
e281682b
SM		 9452
9453 u8 admin_mtu[0x10];
b4ff3a36 9454 u8 reserved_at_50[0x10];
e281682b
SM		 9455
9456 u8 oper_mtu[0x10];
b4ff3a36 9457 u8 reserved_at_70[0x10];
e281682b
SM		 9458};
9459
9460struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 9461 u8 reserved_at_0[0x8];
e281682b 9462 u8 module[0x8];
b4ff3a36 9463 u8 reserved_at_10[0x10];
e281682b 9464
b4ff3a36 9465 u8 reserved_at_20[0x18];
e281682b
SM		 9466 u8 attenuation_5g[0x8];
9467
b4ff3a36 9468 u8 reserved_at_40[0x18];
e281682b
SM		 9469 u8 attenuation_7g[0x8];
9470
b4ff3a36 9471 u8 reserved_at_60[0x18];
e281682b
SM		 9472 u8 attenuation_12g[0x8];
9473};
9474
9475struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 9476 u8 reserved_at_0[0x8];
e281682b 9477 u8 module[0x8];
b4ff3a36 9478 u8 reserved_at_10[0xc];
e281682b
SM		 9479 u8 module_status[0x4];
9480
b4ff3a36 9481 u8 reserved_at_20[0x60];
e281682b
SM		 9482};
9483
9484struct mlx5_ifc_pmpc_reg_bits {
9485 u8 module_state_updated[32][0x8];
9486};
9487
9488struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 9489 u8 reserved_at_0[0x4];
e281682b
SM		 9490 u8 mlpn_status[0x4];
9491 u8 local_port[0x8];
b4ff3a36 9492 u8 reserved_at_10[0x10];
e281682b
SM		 9493
9494 u8 e[0x1];
b4ff3a36 9495 u8 reserved_at_21[0x1f];
e281682b
SM		 9496};
9497
9498struct mlx5_ifc_pmlp_reg_bits {
9499 u8 rxtx[0x1];
b4ff3a36 9500 u8 reserved_at_1[0x7];
e281682b 9501 u8 local_port[0x8];
b4ff3a36 9502 u8 reserved_at_10[0x8];
e281682b
SM		 9503 u8 width[0x8];
9504
9505 u8 lane0_module_mapping[0x20];
9506
9507 u8 lane1_module_mapping[0x20];
9508
9509 u8 lane2_module_mapping[0x20];
9510
9511 u8 lane3_module_mapping[0x20];
9512
b4ff3a36 9513 u8 reserved_at_a0[0x160];
e281682b
SM		 9514};
9515
9516struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 9517 u8 reserved_at_0[0x8];
e281682b 9518 u8 module[0x8];
b4ff3a36 9519 u8 reserved_at_10[0x4];
e281682b 9520 u8 admin_status[0x4];
b4ff3a36 9521 u8 reserved_at_18[0x4];
e281682b
SM		 9522 u8 oper_status[0x4];
9523
9524 u8 ase[0x1];
9525 u8 ee[0x1];
b4ff3a36 9526 u8 reserved_at_22[0x1c];
e281682b
SM		 9527 u8 e[0x2];
9528
b4ff3a36 9529 u8 reserved_at_40[0x40];
e281682b
SM		 9530};
9531
9532struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 9533 u8 reserved_at_0[0x4];
e281682b 9534 u8 profile_id[0xc];
b4ff3a36 9535 u8 reserved_at_10[0x4];
e281682b 9536 u8 proto_mask[0x4];
b4ff3a36 9537 u8 reserved_at_18[0x8];
e281682b 9538
b4ff3a36 9539 u8 reserved_at_20[0x10];
e281682b
SM		 9540 u8 lane_speed[0x10];
9541
b4ff3a36 9542 u8 reserved_at_40[0x17];
e281682b
SM		 9543 u8 lpbf[0x1];
9544 u8 fec_mode_policy[0x8];
9545
9546 u8 retransmission_capability[0x8];
9547 u8 fec_mode_capability[0x18];
9548
9549 u8 retransmission_support_admin[0x8];
9550 u8 fec_mode_support_admin[0x18];
9551
9552 u8 retransmission_request_admin[0x8];
9553 u8 fec_mode_request_admin[0x18];
9554
b4ff3a36 9555 u8 reserved_at_c0[0x80];
e281682b
SM		 9556};
9557
9558struct mlx5_ifc_plib_reg_bits {
b4ff3a36 9559 u8 reserved_at_0[0x8];
e281682b 9560 u8 local_port[0x8];
b4ff3a36 9561 u8 reserved_at_10[0x8];
e281682b
SM		 9562 u8 ib_port[0x8];
9563
b4ff3a36 9564 u8 reserved_at_20[0x60];
e281682b
SM		 9565};
9566
9567struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 9568 u8 reserved_at_0[0x8];
e281682b 9569 u8 local_port[0x8];
b4ff3a36 9570 u8 reserved_at_10[0xd];
e281682b
SM		 9571 u8 lbf_mode[0x3];
9572
b4ff3a36 9573 u8 reserved_at_20[0x20];
e281682b
SM		 9574};
9575
9576struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 9577 u8 reserved_at_0[0x8];
e281682b 9578 u8 local_port[0x8];
b4ff3a36 9579 u8 reserved_at_10[0x10];
e281682b
SM		 9580
9581 u8 dic[0x1];
b4ff3a36 9582 u8 reserved_at_21[0x19];
e281682b 9583 u8 ipg[0x4];
b4ff3a36 9584 u8 reserved_at_3e[0x2];
e281682b
SM		 9585};
9586
9587struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 9588 u8 reserved_at_0[0x8];
e281682b 9589 u8 local_port[0x8];
b4ff3a36 9590 u8 reserved_at_10[0x10];
e281682b 9591
b4ff3a36 9592 u8 reserved_at_20[0xe0];
e281682b
SM		 9593
9594 u8 port_filter[8][0x20];
9595
9596 u8 port_filter_update_en[8][0x20];
9597};
9598
9599struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 9600 u8 reserved_at_0[0x8];
e281682b 9601 u8 local_port[0x8];
2afa609f
IK		 9602 u8 reserved_at_10[0xb];
9603 u8 ppan_mask_n[0x1];
9604 u8 minor_stall_mask[0x1];
9605 u8 critical_stall_mask[0x1];
9606 u8 reserved_at_1e[0x2];
e281682b
SM		 9607
9608 u8 ppan[0x4];
b4ff3a36 9609 u8 reserved_at_24[0x4];
e281682b 9610 u8 prio_mask_tx[0x8];
b4ff3a36 9611 u8 reserved_at_30[0x8];
e281682b
SM		 9612 u8 prio_mask_rx[0x8];
9613
9614 u8 pptx[0x1];
9615 u8 aptx[0x1];
2afa609f
IK		 9616 u8 pptx_mask_n[0x1];
9617 u8 reserved_at_43[0x5];
e281682b 9618 u8 pfctx[0x8];
b4ff3a36 9619 u8 reserved_at_50[0x10];
e281682b
SM		 9620
9621 u8 pprx[0x1];
9622 u8 aprx[0x1];
2afa609f
IK		 9623 u8 pprx_mask_n[0x1];
9624 u8 reserved_at_63[0x5];
e281682b 9625 u8 pfcrx[0x8];
b4ff3a36 9626 u8 reserved_at_70[0x10];
e281682b 9627
2afa609f
IK		 9628 u8 device_stall_minor_watermark[0x10];
9629 u8 device_stall_critical_watermark[0x10];
9630
9631 u8 reserved_at_a0[0x60];
e281682b
SM		 9632};
9633
9634struct mlx5_ifc_pelc_reg_bits {
9635 u8 op[0x4];
b4ff3a36 9636 u8 reserved_at_4[0x4];
e281682b 9637 u8 local_port[0x8];
b4ff3a36 9638 u8 reserved_at_10[0x10];
e281682b
SM		 9639
9640 u8 op_admin[0x8];
9641 u8 op_capability[0x8];
9642 u8 op_request[0x8];
9643 u8 op_active[0x8];
9644
9645 u8 admin[0x40];
9646
9647 u8 capability[0x40];
9648
9649 u8 request[0x40];
9650
9651 u8 active[0x40];
9652
b4ff3a36 9653 u8 reserved_at_140[0x80];
e281682b
SM		 9654};
9655
9656struct mlx5_ifc_peir_reg_bits {
b4ff3a36 9657 u8 reserved_at_0[0x8];
e281682b 9658 u8 local_port[0x8];
b4ff3a36 9659 u8 reserved_at_10[0x10];
e281682b 9660
b4ff3a36 9661 u8 reserved_at_20[0xc];
e281682b 9662 u8 error_count[0x4];
b4ff3a36 9663 u8 reserved_at_30[0x10];
e281682b 9664
b4ff3a36 9665 u8 reserved_at_40[0xc];
e281682b 9666 u8 lane[0x4];
b4ff3a36 9667 u8 reserved_at_50[0x8];
e281682b
SM		 9668 u8 error_type[0x8];
9669};
9670
5e022dd3
EBE		 9671struct mlx5_ifc_mpegc_reg_bits {
9672 u8 reserved_at_0[0x30];
9673 u8 field_select[0x10];
9674
9675 u8 tx_overflow_sense[0x1];
9676 u8 mark_cqe[0x1];
9677 u8 mark_cnp[0x1];
9678 u8 reserved_at_43[0x1b];
9679 u8 tx_lossy_overflow_oper[0x2];
9680
9681 u8 reserved_at_60[0x100];
9682};
9683
ae02d415
EBE		 9684enum {
9685 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
9686 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
9687 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
9688};
9689
9690struct mlx5_ifc_mtutc_reg_bits {
9691 u8 reserved_at_0[0x1c];
9692 u8 operation[0x4];
9693
9694 u8 freq_adjustment[0x20];
9695
9696 u8 reserved_at_40[0x40];
9697
9698 u8 utc_sec[0x20];
9699
9700 u8 reserved_at_a0[0x2];
9701 u8 utc_nsec[0x1e];
9702
9703 u8 time_adjustment[0x20];
9704};
9705
cfdcbcea 9706struct mlx5_ifc_pcam_enhanced_features_bits {
a58837f5
AL		 9707 u8 reserved_at_0[0x68];
9708 u8 fec_50G_per_lane_in_pplm[0x1];
9709 u8 reserved_at_69[0x4];
0af5107c 9710 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 9711 u8 reserved_at_6e[0x4];
9712 u8 ptys_extended_ethernet[0x1];
9713 u8 reserved_at_73[0x3];
2fcb12df 9714 u8 pfcc_mask[0x1];
67daf118
SA		 9715 u8 reserved_at_77[0x3];
9716 u8 per_lane_error_counters[0x1];
2dba0797 9717 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 9718 u8 ptys_connector_type[0x1];
9719 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 9720 u8 ppcnt_discard_group[0x1];
9721 u8 ppcnt_statistical_group[0x1];
9722};
9723
df5f1361
HN		 9724struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9725 u8 port_access_reg_cap_mask_127_to_96[0x20];
9726 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 9727
9728 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9729 u8 pplm[0x1];
9730 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 9731
9732 u8 port_access_reg_cap_mask_31_to_13[0x13];
9733 u8 pbmc[0x1];
9734 u8 pptb[0x1];
75370eb0
ED		 9735 u8 port_access_reg_cap_mask_10_to_09[0x2];
9736 u8 ppcnt[0x1];
9737 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 9738};
9739
cfdcbcea
GP		 9740struct mlx5_ifc_pcam_reg_bits {
9741 u8 reserved_at_0[0x8];
9742 u8 feature_group[0x8];
9743 u8 reserved_at_10[0x8];
9744 u8 access_reg_group[0x8];
9745
9746 u8 reserved_at_20[0x20];
9747
9748 union {
df5f1361 9749 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 9750 u8 reserved_at_0[0x80];
9751 } port_access_reg_cap_mask;
9752
9753 u8 reserved_at_c0[0x80];
9754
9755 union {
9756 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9757 u8 reserved_at_0[0x80];
9758 } feature_cap_mask;
9759
9760 u8 reserved_at_1c0[0xc0];
9761};
9762
9763struct mlx5_ifc_mcam_enhanced_features_bits {
271907ee
GP		 9764 u8 reserved_at_0[0x5d];
9765 u8 mcia_32dwords[0x1];
9766 u8 reserved_at_5e[0xc];
72fb3b60 9767 u8 reset_state[0x1];
ae02d415
EBE		 9768 u8 ptpcyc2realtime_modify[0x1];
9769 u8 reserved_at_6c[0x2];
4039049b
AL		 9770 u8 pci_status_and_power[0x1];
9771 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 9772 u8 mark_tx_action_cnp[0x1];
9773 u8 mark_tx_action_cqe[0x1];
9774 u8 dynamic_tx_overflow[0x1];
9775 u8 reserved_at_77[0x4];
5405fa26 9776 u8 pcie_outbound_stalled[0x1];
efae7f78 9777 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 9778 u8 mtpps_enh_out_per_adj[0x1];
9779 u8 mtpps_fs[0x1];
cfdcbcea
GP		 9780 u8 pcie_performance_group[0x1];
9781};
9782
0ab87743
OG		 9783struct mlx5_ifc_mcam_access_reg_bits {
9784 u8 reserved_at_0[0x1c];
9785 u8 mcda[0x1];
9786 u8 mcc[0x1];
9787 u8 mcqi[0x1];
a82e0b5b 9788 u8 mcqs[0x1];
0ab87743 9789
5e022dd3
EBE		 9790 u8 regs_95_to_87[0x9];
9791 u8 mpegc[0x1];
ae02d415
EBE		 9792 u8 mtutc[0x1];
9793 u8 regs_84_to_68[0x11];
eff8ea8f
FD		 9794 u8 tracer_registers[0x4];
9795
502e82b9
AL		 9796 u8 regs_63_to_46[0x12];
9797 u8 mrtc[0x1];
9798 u8 regs_44_to_32[0xd];
9799
0ab87743
OG		 9800 u8 regs_31_to_0[0x20];
9801};
9802
f397464e
EBE		 9803struct mlx5_ifc_mcam_access_reg_bits1 {
9804 u8 regs_127_to_96[0x20];
9805
9806 u8 regs_95_to_64[0x20];
9807
9808 u8 regs_63_to_32[0x20];
9809
9810 u8 regs_31_to_0[0x20];
9811};
9812
9813struct mlx5_ifc_mcam_access_reg_bits2 {
9814 u8 regs_127_to_99[0x1d];
9815 u8 mirc[0x1];
9816 u8 regs_97_to_96[0x2];
9817
9818 u8 regs_95_to_64[0x20];
9819
9820 u8 regs_63_to_32[0x20];
9821
9822 u8 regs_31_to_0[0x20];
9823};
9824
cfdcbcea
GP		 9825struct mlx5_ifc_mcam_reg_bits {
9826 u8 reserved_at_0[0x8];
9827 u8 feature_group[0x8];
9828 u8 reserved_at_10[0x8];
9829 u8 access_reg_group[0x8];
9830
9831 u8 reserved_at_20[0x20];
9832
9833 union {
0ab87743 9834 struct mlx5_ifc_mcam_access_reg_bits access_regs;
f397464e
EBE		 9835 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9836 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
cfdcbcea
GP		 9837 u8 reserved_at_0[0x80];
9838 } mng_access_reg_cap_mask;
9839
9840 u8 reserved_at_c0[0x80];
9841
9842 union {
9843 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9844 u8 reserved_at_0[0x80];
9845 } mng_feature_cap_mask;
9846
9847 u8 reserved_at_1c0[0x80];
9848};
9849
c02762eb
HN		 9850struct mlx5_ifc_qcam_access_reg_cap_mask {
9851 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9852 u8 qpdpm[0x1];
9853 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9854 u8 qdpm[0x1];
9855 u8 qpts[0x1];
9856 u8 qcap[0x1];
9857 u8 qcam_access_reg_cap_mask_0[0x1];
9858};
9859
9860struct mlx5_ifc_qcam_qos_feature_cap_mask {
9861 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9862 u8 qpts_trust_both[0x1];
9863};
9864
9865struct mlx5_ifc_qcam_reg_bits {
9866 u8 reserved_at_0[0x8];
9867 u8 feature_group[0x8];
9868 u8 reserved_at_10[0x8];
9869 u8 access_reg_group[0x8];
9870 u8 reserved_at_20[0x20];
9871
9872 union {
9873 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9874 u8 reserved_at_0[0x80];
9875 } qos_access_reg_cap_mask;
9876
9877 u8 reserved_at_c0[0x80];
9878
9879 union {
9880 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9881 u8 reserved_at_0[0x80];
9882 } qos_feature_cap_mask;
9883
9884 u8 reserved_at_1c0[0x80];
9885};
9886
0b9055a1
MS		 9887struct mlx5_ifc_core_dump_reg_bits {
9888 u8 reserved_at_0[0x18];
9889 u8 core_dump_type[0x8];
9890
9891 u8 reserved_at_20[0x30];
9892 u8 vhca_id[0x10];
9893
9894 u8 reserved_at_60[0x8];
9895 u8 qpn[0x18];
9896 u8 reserved_at_80[0x180];
9897};
9898
e281682b 9899struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 9900 u8 reserved_at_0[0x8];
e281682b 9901 u8 local_port[0x8];
b4ff3a36 9902 u8 reserved_at_10[0x10];
e281682b
SM		 9903
9904 u8 port_capability_mask[4][0x20];
9905};
9906
9907struct mlx5_ifc_paos_reg_bits {
9908 u8 swid[0x8];
9909 u8 local_port[0x8];
b4ff3a36 9910 u8 reserved_at_10[0x4];
e281682b 9911 u8 admin_status[0x4];
b4ff3a36 9912 u8 reserved_at_18[0x4];
e281682b
SM		 9913 u8 oper_status[0x4];
9914
9915 u8 ase[0x1];
9916 u8 ee[0x1];
b4ff3a36 9917 u8 reserved_at_22[0x1c];
e281682b
SM		 9918 u8 e[0x2];
9919
b4ff3a36 9920 u8 reserved_at_40[0x40];
e281682b
SM		 9921};
9922
9923struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 9924 u8 reserved_at_0[0x8];
e281682b 9925 u8 opamp_group[0x8];
b4ff3a36 9926 u8 reserved_at_10[0xc];
e281682b
SM		 9927 u8 opamp_group_type[0x4];
9928
9929 u8 start_index[0x10];
b4ff3a36 9930 u8 reserved_at_30[0x4];
e281682b
SM		 9931 u8 num_of_indices[0xc];
9932
9933 u8 index_data[18][0x10];
9934};
9935
7d5e1423
SM		 9936struct mlx5_ifc_pcmr_reg_bits {
9937 u8 reserved_at_0[0x8];
9938 u8 local_port[0x8];
0dcaafc0 9939 u8 reserved_at_10[0x10];
0bc73ad4 9940
0dcaafc0
EB		 9941 u8 entropy_force_cap[0x1];
9942 u8 entropy_calc_cap[0x1];
9943 u8 entropy_gre_calc_cap[0x1];
0bc73ad4
AL		 9944 u8 reserved_at_23[0xf];
9945 u8 rx_ts_over_crc_cap[0x1];
9946 u8 reserved_at_33[0xb];
7d5e1423 9947 u8 fcs_cap[0x1];
0dcaafc0 9948 u8 reserved_at_3f[0x1];
0bc73ad4 9949
0dcaafc0
EB		 9950 u8 entropy_force[0x1];
9951 u8 entropy_calc[0x1];
9952 u8 entropy_gre_calc[0x1];
0bc73ad4
AL		 9953 u8 reserved_at_43[0xf];
9954 u8 rx_ts_over_crc[0x1];
9955 u8 reserved_at_53[0xb];
7d5e1423
SM		 9956 u8 fcs_chk[0x1];
9957 u8 reserved_at_5f[0x1];
9958};
9959
e281682b 9960struct mlx5_ifc_lane_2_module_mapping_bits {
fcb610a8
GP		 9961 u8 reserved_at_0[0x4];
9962 u8 rx_lane[0x4];
9963 u8 reserved_at_8[0x4];
9964 u8 tx_lane[0x4];
b4ff3a36 9965 u8 reserved_at_10[0x8];
e281682b
SM		 9966 u8 module[0x8];
9967};
9968
9969struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 9970 u8 reserved_at_0[0x6];
e281682b
SM		 9971 u8 lossy[0x1];
9972 u8 epsb[0x1];
ac77998b
MK		 9973 u8 reserved_at_8[0x8];
9974 u8 size[0x10];
e281682b
SM		 9975
9976 u8 xoff_threshold[0x10];
9977 u8 xon_threshold[0x10];
9978};
9979
9980struct mlx5_ifc_set_node_in_bits {
9981 u8 node_description[64][0x8];
9982};
9983
9984struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 9985 u8 reserved_at_0[0x18];
e281682b
SM		 9986 u8 power_settings_level[0x8];
9987
b4ff3a36 9988 u8 reserved_at_20[0x60];
e281682b
SM		 9989};
9990
9991struct mlx5_ifc_register_host_endianness_bits {
9992 u8 he[0x1];
b4ff3a36 9993 u8 reserved_at_1[0x1f];
e281682b 9994
b4ff3a36 9995 u8 reserved_at_20[0x60];
e281682b
SM		 9996};
9997
9998struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 9999 u8 reserved_at_0[0x20];
e281682b
SM		 10000
10001 u8 mkey[0x20];
10002
10003 u8 addressh_63_32[0x20];
10004
10005 u8 addressl_31_0[0x20];
10006};
10007
10008struct mlx5_ifc_ud_adrs_vector_bits {
10009 u8 dc_key[0x40];
10010
10011 u8 ext[0x1];
b4ff3a36 10012 u8 reserved_at_41[0x7];
e281682b
SM		 10013 u8 destination_qp_dct[0x18];
10014
10015 u8 static_rate[0x4];
10016 u8 sl_eth_prio[0x4];
10017 u8 fl[0x1];
10018 u8 mlid[0x7];
10019 u8 rlid_udp_sport[0x10];
10020
b4ff3a36 10021 u8 reserved_at_80[0x20];
e281682b
SM		 10022
10023 u8 rmac_47_16[0x20];
10024
10025 u8 rmac_15_0[0x10];
10026 u8 tclass[0x8];
10027 u8 hop_limit[0x8];
10028
b4ff3a36 10029 u8 reserved_at_e0[0x1];
e281682b 10030 u8 grh[0x1];
b4ff3a36 10031 u8 reserved_at_e2[0x2];
e281682b
SM		 10032 u8 src_addr_index[0x8];
10033 u8 flow_label[0x14];
10034
10035 u8 rgid_rip[16][0x8];
10036};
10037
10038struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 10039 u8 reserved_at_0[0x10];
e281682b
SM		 10040 u8 function_id[0x10];
10041
10042 u8 num_pages[0x20];
10043
b4ff3a36 10044 u8 reserved_at_40[0xa0];
e281682b
SM		 10045};
10046
10047struct mlx5_ifc_eqe_bits {
b4ff3a36 10048 u8 reserved_at_0[0x8];
e281682b 10049 u8 event_type[0x8];
b4ff3a36 10050 u8 reserved_at_10[0x8];
e281682b
SM		 10051 u8 event_sub_type[0x8];
10052
b4ff3a36 10053 u8 reserved_at_20[0xe0];
e281682b
SM		 10054
10055 union mlx5_ifc_event_auto_bits event_data;
10056
b4ff3a36 10057 u8 reserved_at_1e0[0x10];
e281682b 10058 u8 signature[0x8];
b4ff3a36 10059 u8 reserved_at_1f8[0x7];
e281682b
SM		 10060 u8 owner[0x1];
10061};
10062
10063enum {
10064 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10065};
10066
10067struct mlx5_ifc_cmd_queue_entry_bits {
10068 u8 type[0x8];
b4ff3a36 10069 u8 reserved_at_8[0x18];
e281682b
SM		 10070
10071 u8 input_length[0x20];
10072
10073 u8 input_mailbox_pointer_63_32[0x20];
10074
10075 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 10076 u8 reserved_at_77[0x9];
e281682b
SM		 10077
10078 u8 command_input_inline_data[16][0x8];
10079
10080 u8 command_output_inline_data[16][0x8];
10081
10082 u8 output_mailbox_pointer_63_32[0x20];
10083
10084 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 10085 u8 reserved_at_1b7[0x9];
e281682b
SM		 10086
10087 u8 output_length[0x20];
10088
10089 u8 token[0x8];
10090 u8 signature[0x8];
b4ff3a36 10091 u8 reserved_at_1f0[0x8];
e281682b
SM		 10092 u8 status[0x7];
10093 u8 ownership[0x1];
10094};
10095
10096struct mlx5_ifc_cmd_out_bits {
10097 u8 status[0x8];
b4ff3a36 10098 u8 reserved_at_8[0x18];
e281682b
SM		 10099
10100 u8 syndrome[0x20];
10101
10102 u8 command_output[0x20];
10103};
10104
10105struct mlx5_ifc_cmd_in_bits {
10106 u8 opcode[0x10];
b4ff3a36 10107 u8 reserved_at_10[0x10];
e281682b 10108
b4ff3a36 10109 u8 reserved_at_20[0x10];
e281682b
SM		 10110 u8 op_mod[0x10];
10111
b6ca09cb 10112 u8 command[][0x20];
e281682b
SM		 10113};
10114
10115struct mlx5_ifc_cmd_if_box_bits {
10116 u8 mailbox_data[512][0x8];
10117
b4ff3a36 10118 u8 reserved_at_1000[0x180];
e281682b
SM		 10119
10120 u8 next_pointer_63_32[0x20];
10121
10122 u8 next_pointer_31_10[0x16];
b4ff3a36 10123 u8 reserved_at_11b6[0xa];
e281682b
SM		 10124
10125 u8 block_number[0x20];
10126
b4ff3a36 10127 u8 reserved_at_11e0[0x8];
e281682b
SM		 10128 u8 token[0x8];
10129 u8 ctrl_signature[0x8];
10130 u8 signature[0x8];
10131};
10132
10133struct mlx5_ifc_mtt_bits {
10134 u8 ptag_63_32[0x20];
10135
10136 u8 ptag_31_8[0x18];
b4ff3a36 10137 u8 reserved_at_38[0x6];
e281682b
SM		 10138 u8 wr_en[0x1];
10139 u8 rd_en[0x1];
10140};
10141
928cfe87
TT		 10142struct mlx5_ifc_query_wol_rol_out_bits {
10143 u8 status[0x8];
10144 u8 reserved_at_8[0x18];
10145
10146 u8 syndrome[0x20];
10147
10148 u8 reserved_at_40[0x10];
10149 u8 rol_mode[0x8];
10150 u8 wol_mode[0x8];
10151
10152 u8 reserved_at_60[0x20];
10153};
10154
10155struct mlx5_ifc_query_wol_rol_in_bits {
10156 u8 opcode[0x10];
10157 u8 reserved_at_10[0x10];
10158
10159 u8 reserved_at_20[0x10];
10160 u8 op_mod[0x10];
10161
10162 u8 reserved_at_40[0x40];
10163};
10164
10165struct mlx5_ifc_set_wol_rol_out_bits {
10166 u8 status[0x8];
10167 u8 reserved_at_8[0x18];
10168
10169 u8 syndrome[0x20];
10170
10171 u8 reserved_at_40[0x40];
10172};
10173
10174struct mlx5_ifc_set_wol_rol_in_bits {
10175 u8 opcode[0x10];
10176 u8 reserved_at_10[0x10];
10177
10178 u8 reserved_at_20[0x10];
10179 u8 op_mod[0x10];
10180
10181 u8 rol_mode_valid[0x1];
10182 u8 wol_mode_valid[0x1];
10183 u8 reserved_at_42[0xe];
10184 u8 rol_mode[0x8];
10185 u8 wol_mode[0x8];
10186
10187 u8 reserved_at_60[0x20];
10188};
10189
e281682b
SM		 10190enum {
10191 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10192 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10193 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10194};
10195
10196enum {
10197 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10198 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10199 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10200};
10201
10202enum {
10203 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10204 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10205 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10206 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10207 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10208 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10209 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10210 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10211 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10212 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10213 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10214};
10215
10216struct mlx5_ifc_initial_seg_bits {
10217 u8 fw_rev_minor[0x10];
10218 u8 fw_rev_major[0x10];
10219
10220 u8 cmd_interface_rev[0x10];
10221 u8 fw_rev_subminor[0x10];
10222
b4ff3a36 10223 u8 reserved_at_40[0x40];
e281682b
SM		 10224
10225 u8 cmdq_phy_addr_63_32[0x20];
10226
10227 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 10228 u8 reserved_at_b4[0x2];
e281682b
SM		 10229 u8 nic_interface[0x2];
10230 u8 log_cmdq_size[0x4];
10231 u8 log_cmdq_stride[0x4];
10232
10233 u8 command_doorbell_vector[0x20];
10234
b4ff3a36 10235 u8 reserved_at_e0[0xf00];
e281682b
SM		 10236
10237 u8 initializing[0x1];
b4ff3a36 10238 u8 reserved_at_fe1[0x4];
e281682b 10239 u8 nic_interface_supported[0x3];
591905ba
BW		 10240 u8 embedded_cpu[0x1];
10241 u8 reserved_at_fe9[0x17];
e281682b
SM		 10242
10243 struct mlx5_ifc_health_buffer_bits health_buffer;
10244
10245 u8 no_dram_nic_offset[0x20];
10246
b4ff3a36 10247 u8 reserved_at_1220[0x6e40];
e281682b 10248
b4ff3a36 10249 u8 reserved_at_8060[0x1f];
e281682b
SM		 10250 u8 clear_int[0x1];
10251
10252 u8 health_syndrome[0x8];
10253 u8 health_counter[0x18];
10254
b4ff3a36 10255 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 10256};
10257
f9a1ef72
EE		 10258struct mlx5_ifc_mtpps_reg_bits {
10259 u8 reserved_at_0[0xc];
10260 u8 cap_number_of_pps_pins[0x4];
10261 u8 reserved_at_10[0x4];
10262 u8 cap_max_num_of_pps_in_pins[0x4];
10263 u8 reserved_at_18[0x4];
10264 u8 cap_max_num_of_pps_out_pins[0x4];
10265
10266 u8 reserved_at_20[0x24];
10267 u8 cap_pin_3_mode[0x4];
10268 u8 reserved_at_48[0x4];
10269 u8 cap_pin_2_mode[0x4];
10270 u8 reserved_at_50[0x4];
10271 u8 cap_pin_1_mode[0x4];
10272 u8 reserved_at_58[0x4];
10273 u8 cap_pin_0_mode[0x4];
10274
10275 u8 reserved_at_60[0x4];
10276 u8 cap_pin_7_mode[0x4];
10277 u8 reserved_at_68[0x4];
10278 u8 cap_pin_6_mode[0x4];
10279 u8 reserved_at_70[0x4];
10280 u8 cap_pin_5_mode[0x4];
10281 u8 reserved_at_78[0x4];
10282 u8 cap_pin_4_mode[0x4];
10283
fa367688
EE		 10284 u8 field_select[0x20];
10285 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 10286
10287 u8 enable[0x1];
10288 u8 reserved_at_101[0xb];
10289 u8 pattern[0x4];
10290 u8 reserved_at_110[0x4];
10291 u8 pin_mode[0x4];
10292 u8 pin[0x8];
10293
10294 u8 reserved_at_120[0x20];
10295
10296 u8 time_stamp[0x40];
10297
10298 u8 out_pulse_duration[0x10];
10299 u8 out_periodic_adjustment[0x10];
fa367688 10300 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 10301
fa367688 10302 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 10303};
10304
10305struct mlx5_ifc_mtppse_reg_bits {
10306 u8 reserved_at_0[0x18];
10307 u8 pin[0x8];
10308 u8 event_arm[0x1];
10309 u8 reserved_at_21[0x1b];
10310 u8 event_generation_mode[0x4];
10311 u8 reserved_at_40[0x40];
10312};
10313
a82e0b5b
SA		 10314struct mlx5_ifc_mcqs_reg_bits {
10315 u8 last_index_flag[0x1];
10316 u8 reserved_at_1[0x7];
10317 u8 fw_device[0x8];
10318 u8 component_index[0x10];
10319
10320 u8 reserved_at_20[0x10];
10321 u8 identifier[0x10];
10322
10323 u8 reserved_at_40[0x17];
10324 u8 component_status[0x5];
10325 u8 component_update_state[0x4];
10326
10327 u8 last_update_state_changer_type[0x4];
10328 u8 last_update_state_changer_host_id[0x4];
10329 u8 reserved_at_68[0x18];
10330};
10331
47176289
OG		 10332struct mlx5_ifc_mcqi_cap_bits {
10333 u8 supported_info_bitmask[0x20];
10334
10335 u8 component_size[0x20];
10336
10337 u8 max_component_size[0x20];
10338
10339 u8 log_mcda_word_size[0x4];
10340 u8 reserved_at_64[0xc];
10341 u8 mcda_max_write_size[0x10];
10342
10343 u8 rd_en[0x1];
10344 u8 reserved_at_81[0x1];
10345 u8 match_chip_id[0x1];
10346 u8 match_psid[0x1];
10347 u8 check_user_timestamp[0x1];
10348 u8 match_base_guid_mac[0x1];
10349 u8 reserved_at_86[0x1a];
10350};
10351
a82e0b5b
SA		 10352struct mlx5_ifc_mcqi_version_bits {
10353 u8 reserved_at_0[0x2];
10354 u8 build_time_valid[0x1];
10355 u8 user_defined_time_valid[0x1];
10356 u8 reserved_at_4[0x14];
10357 u8 version_string_length[0x8];
10358
10359 u8 version[0x20];
10360
10361 u8 build_time[0x40];
10362
10363 u8 user_defined_time[0x40];
10364
10365 u8 build_tool_version[0x20];
10366
10367 u8 reserved_at_e0[0x20];
10368
10369 u8 version_string[92][0x8];
10370};
10371
10372struct mlx5_ifc_mcqi_activation_method_bits {
10373 u8 pending_server_ac_power_cycle[0x1];
10374 u8 pending_server_dc_power_cycle[0x1];
10375 u8 pending_server_reboot[0x1];
10376 u8 pending_fw_reset[0x1];
10377 u8 auto_activate[0x1];
10378 u8 all_hosts_sync[0x1];
10379 u8 device_hw_reset[0x1];
10380 u8 reserved_at_7[0x19];
10381};
10382
10383union mlx5_ifc_mcqi_reg_data_bits {
10384 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
10385 struct mlx5_ifc_mcqi_version_bits mcqi_version;
10386 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10387};
10388
47176289
OG		 10389struct mlx5_ifc_mcqi_reg_bits {
10390 u8 read_pending_component[0x1];
10391 u8 reserved_at_1[0xf];
10392 u8 component_index[0x10];
10393
10394 u8 reserved_at_20[0x20];
10395
10396 u8 reserved_at_40[0x1b];
10397 u8 info_type[0x5];
10398
10399 u8 info_size[0x20];
10400
10401 u8 offset[0x20];
10402
10403 u8 reserved_at_a0[0x10];
10404 u8 data_size[0x10];
10405
b6ca09cb 10406 union mlx5_ifc_mcqi_reg_data_bits data[];
47176289
OG		 10407};
10408
10409struct mlx5_ifc_mcc_reg_bits {
10410 u8 reserved_at_0[0x4];
10411 u8 time_elapsed_since_last_cmd[0xc];
10412 u8 reserved_at_10[0x8];
10413 u8 instruction[0x8];
10414
10415 u8 reserved_at_20[0x10];
10416 u8 component_index[0x10];
10417
10418 u8 reserved_at_40[0x8];
10419 u8 update_handle[0x18];
10420
10421 u8 handle_owner_type[0x4];
10422 u8 handle_owner_host_id[0x4];
10423 u8 reserved_at_68[0x1];
10424 u8 control_progress[0x7];
10425 u8 error_code[0x8];
10426 u8 reserved_at_78[0x4];
10427 u8 control_state[0x4];
10428
10429 u8 component_size[0x20];
10430
10431 u8 reserved_at_a0[0x60];
10432};
10433
10434struct mlx5_ifc_mcda_reg_bits {
10435 u8 reserved_at_0[0x8];
10436 u8 update_handle[0x18];
10437
10438 u8 offset[0x20];
10439
10440 u8 reserved_at_40[0x10];
10441 u8 size[0x10];
10442
10443 u8 reserved_at_60[0x20];
10444
29056207 10445 u8 data[][0x20];
47176289
OG		 10446};
10447
72fb3b60
MS		 10448enum {
10449 MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10450 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10451 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10452 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10453 MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10454};
10455
06939536
MS		 10456enum {
10457 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10458 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10459};
10460
10461enum {
10462 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10463 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10464 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10465};
10466
10467struct mlx5_ifc_mfrl_reg_bits {
10468 u8 reserved_at_0[0x20];
10469
10470 u8 reserved_at_20[0x2];
10471 u8 pci_sync_for_fw_update_start[0x1];
10472 u8 pci_sync_for_fw_update_resp[0x2];
10473 u8 rst_type_sel[0x3];
72fb3b60
MS		 10474 u8 reserved_at_28[0x4];
10475 u8 reset_state[0x4];
06939536
MS		 10476 u8 reset_type[0x8];
10477 u8 reset_level[0x8];
10478};
10479
bab58ba1
EBE		 10480struct mlx5_ifc_mirc_reg_bits {
10481 u8 reserved_at_0[0x18];
10482 u8 status_code[0x8];
10483
10484 u8 reserved_at_20[0x20];
10485};
10486
36830159
MT		 10487struct mlx5_ifc_pddr_monitor_opcode_bits {
10488 u8 reserved_at_0[0x10];
10489 u8 monitor_opcode[0x10];
10490};
10491
10492union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10493 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10494 u8 reserved_at_0[0x20];
10495};
10496
10497enum {
10498 /* Monitor opcodes */
10499 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10500};
10501
10502struct mlx5_ifc_pddr_troubleshooting_page_bits {
10503 u8 reserved_at_0[0x10];
10504 u8 group_opcode[0x10];
10505
10506 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10507
10508 u8 reserved_at_40[0x20];
10509
10510 u8 status_message[59][0x20];
10511};
10512
10513union mlx5_ifc_pddr_reg_page_data_auto_bits {
10514 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10515 u8 reserved_at_0[0x7c0];
10516};
10517
10518enum {
10519 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
10520};
10521
10522struct mlx5_ifc_pddr_reg_bits {
10523 u8 reserved_at_0[0x8];
10524 u8 local_port[0x8];
10525 u8 pnat[0x2];
10526 u8 reserved_at_12[0xe];
10527
10528 u8 reserved_at_20[0x18];
10529 u8 page_select[0x8];
10530
10531 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10532};
10533
5a1023de
AL		 10534struct mlx5_ifc_mrtc_reg_bits {
10535 u8 time_synced[0x1];
10536 u8 reserved_at_1[0x1f];
10537
10538 u8 reserved_at_20[0x20];
10539
10540 u8 time_h[0x20];
10541
10542 u8 time_l[0x20];
10543};
10544
e281682b
SM		 10545union mlx5_ifc_ports_control_registers_document_bits {
10546 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10547 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10548 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10549 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10550 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10551 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10552 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 10553 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10554 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
e281682b
SM		 10555 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10556 struct mlx5_ifc_pamp_reg_bits pamp_reg;
10557 struct mlx5_ifc_paos_reg_bits paos_reg;
10558 struct mlx5_ifc_pcap_reg_bits pcap_reg;
36830159
MT		 10559 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10560 struct mlx5_ifc_pddr_reg_bits pddr_reg;
10561 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
e281682b
SM		 10562 struct mlx5_ifc_peir_reg_bits peir_reg;
10563 struct mlx5_ifc_pelc_reg_bits pelc_reg;
10564 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 10565 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 10566 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10567 struct mlx5_ifc_pifr_reg_bits pifr_reg;
10568 struct mlx5_ifc_pipg_reg_bits pipg_reg;
10569 struct mlx5_ifc_plbf_reg_bits plbf_reg;
10570 struct mlx5_ifc_plib_reg_bits plib_reg;
10571 struct mlx5_ifc_plpc_reg_bits plpc_reg;
10572 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10573 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10574 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10575 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10576 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10577 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10578 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10579 struct mlx5_ifc_ppad_reg_bits ppad_reg;
10580 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 10581 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 10582 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 10583 struct mlx5_ifc_pplm_reg_bits pplm_reg;
10584 struct mlx5_ifc_pplr_reg_bits pplr_reg;
10585 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10586 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10587 struct mlx5_ifc_pspa_reg_bits pspa_reg;
10588 struct mlx5_ifc_ptas_reg_bits ptas_reg;
10589 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 10590 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 10591 struct mlx5_ifc_pude_reg_bits pude_reg;
10592 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10593 struct mlx5_ifc_slrg_reg_bits slrg_reg;
10594 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 10595 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10596 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 10597 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 10598 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10599 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 10600 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10601 struct mlx5_ifc_mcc_reg_bits mcc_reg;
10602 struct mlx5_ifc_mcda_reg_bits mcda_reg;
bab58ba1 10603 struct mlx5_ifc_mirc_reg_bits mirc_reg;
06939536 10604 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
ae02d415 10605 struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
5a1023de 10606 struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
b4ff3a36 10607 u8 reserved_at_0[0x60e0];
e281682b
SM		 10608};
10609
10610union mlx5_ifc_debug_enhancements_document_bits {
10611 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 10612 u8 reserved_at_0[0x200];
e281682b
SM		 10613};
10614
10615union mlx5_ifc_uplink_pci_interface_document_bits {
10616 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 10617 u8 reserved_at_0[0x20060];
b775516b
EC		 10618};
10619
2cc43b49
MG		 10620struct mlx5_ifc_set_flow_table_root_out_bits {
10621 u8 status[0x8];
b4ff3a36 10622 u8 reserved_at_8[0x18];
2cc43b49
MG		 10623
10624 u8 syndrome[0x20];
10625
b4ff3a36 10626 u8 reserved_at_40[0x40];
2cc43b49
MG		 10627};
10628
10629struct mlx5_ifc_set_flow_table_root_in_bits {
10630 u8 opcode[0x10];
b4ff3a36 10631 u8 reserved_at_10[0x10];
2cc43b49 10632
b4ff3a36 10633 u8 reserved_at_20[0x10];
2cc43b49
MG		 10634 u8 op_mod[0x10];
10635
7d5e1423
SM		 10636 u8 other_vport[0x1];
10637 u8 reserved_at_41[0xf];
10638 u8 vport_number[0x10];
10639
10640 u8 reserved_at_60[0x20];
2cc43b49
MG		 10641
10642 u8 table_type[0x8];
c3e666f1
MB		 10643 u8 reserved_at_88[0x7];
10644 u8 table_of_other_vport[0x1];
10645 u8 table_vport_number[0x10];
2cc43b49 10646
b4ff3a36 10647 u8 reserved_at_a0[0x8];
2cc43b49
MG		 10648 u8 table_id[0x18];
10649
500a3d0d
ES		 10650 u8 reserved_at_c0[0x8];
10651 u8 underlay_qpn[0x18];
c3e666f1
MB		 10652 u8 table_eswitch_owner_vhca_id_valid[0x1];
10653 u8 reserved_at_e1[0xf];
10654 u8 table_eswitch_owner_vhca_id[0x10];
10655 u8 reserved_at_100[0x100];
2cc43b49
MG		 10656};
10657
34a40e68 10658enum {
84df61eb
AH		 10659 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
10660 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 10661};
10662
10663struct mlx5_ifc_modify_flow_table_out_bits {
10664 u8 status[0x8];
b4ff3a36 10665 u8 reserved_at_8[0x18];
34a40e68
MG		 10666
10667 u8 syndrome[0x20];
10668
b4ff3a36 10669 u8 reserved_at_40[0x40];
34a40e68
MG		 10670};
10671
10672struct mlx5_ifc_modify_flow_table_in_bits {
10673 u8 opcode[0x10];
b4ff3a36 10674 u8 reserved_at_10[0x10];
34a40e68 10675
b4ff3a36 10676 u8 reserved_at_20[0x10];
34a40e68
MG		 10677 u8 op_mod[0x10];
10678
7d5e1423
SM		 10679 u8 other_vport[0x1];
10680 u8 reserved_at_41[0xf];
10681 u8 vport_number[0x10];
34a40e68 10682
b4ff3a36 10683 u8 reserved_at_60[0x10];
34a40e68
MG		 10684 u8 modify_field_select[0x10];
10685
10686 u8 table_type[0x8];
b4ff3a36 10687 u8 reserved_at_88[0x18];
34a40e68 10688
b4ff3a36 10689 u8 reserved_at_a0[0x8];
34a40e68
MG		 10690 u8 table_id[0x18];
10691
0c90e9c6 10692 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 10693};
10694
4f3961ee
SM		 10695struct mlx5_ifc_ets_tcn_config_reg_bits {
10696 u8 g[0x1];
10697 u8 b[0x1];
10698 u8 r[0x1];
10699 u8 reserved_at_3[0x9];
10700 u8 group[0x4];
10701 u8 reserved_at_10[0x9];
10702 u8 bw_allocation[0x7];
10703
10704 u8 reserved_at_20[0xc];
10705 u8 max_bw_units[0x4];
10706 u8 reserved_at_30[0x8];
10707 u8 max_bw_value[0x8];
10708};
10709
10710struct mlx5_ifc_ets_global_config_reg_bits {
10711 u8 reserved_at_0[0x2];
10712 u8 r[0x1];
10713 u8 reserved_at_3[0x1d];
10714
10715 u8 reserved_at_20[0xc];
10716 u8 max_bw_units[0x4];
10717 u8 reserved_at_30[0x8];
10718 u8 max_bw_value[0x8];
10719};
10720
10721struct mlx5_ifc_qetc_reg_bits {
10722 u8 reserved_at_0[0x8];
10723 u8 port_number[0x8];
10724 u8 reserved_at_10[0x30];
10725
10726 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10727 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10728};
10729
415a64aa
HN		 10730struct mlx5_ifc_qpdpm_dscp_reg_bits {
10731 u8 e[0x1];
10732 u8 reserved_at_01[0x0b];
10733 u8 prio[0x04];
10734};
10735
10736struct mlx5_ifc_qpdpm_reg_bits {
10737 u8 reserved_at_0[0x8];
10738 u8 local_port[0x8];
10739 u8 reserved_at_10[0x10];
10740 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10741};
10742
10743struct mlx5_ifc_qpts_reg_bits {
10744 u8 reserved_at_0[0x8];
10745 u8 local_port[0x8];
10746 u8 reserved_at_10[0x2d];
10747 u8 trust_state[0x3];
10748};
10749
50b4a3c2
HN		 10750struct mlx5_ifc_pptb_reg_bits {
10751 u8 reserved_at_0[0x2];
10752 u8 mm[0x2];
10753 u8 reserved_at_4[0x4];
10754 u8 local_port[0x8];
10755 u8 reserved_at_10[0x6];
10756 u8 cm[0x1];
10757 u8 um[0x1];
10758 u8 pm[0x8];
10759
10760 u8 prio_x_buff[0x20];
10761
10762 u8 pm_msb[0x8];
10763 u8 reserved_at_48[0x10];
10764 u8 ctrl_buff[0x4];
10765 u8 untagged_buff[0x4];
10766};
10767
88b3d5c9
EBE		 10768struct mlx5_ifc_sbcam_reg_bits {
10769 u8 reserved_at_0[0x8];
10770 u8 feature_group[0x8];
10771 u8 reserved_at_10[0x8];
10772 u8 access_reg_group[0x8];
10773
10774 u8 reserved_at_20[0x20];
10775
10776 u8 sb_access_reg_cap_mask[4][0x20];
10777
10778 u8 reserved_at_c0[0x80];
10779
10780 u8 sb_feature_cap_mask[4][0x20];
10781
10782 u8 reserved_at_1c0[0x40];
10783
10784 u8 cap_total_buffer_size[0x20];
10785
10786 u8 cap_cell_size[0x10];
10787 u8 cap_max_pg_buffers[0x8];
10788 u8 cap_num_pool_supported[0x8];
10789
10790 u8 reserved_at_240[0x8];
10791 u8 cap_sbsr_stat_size[0x8];
10792 u8 cap_max_tclass_data[0x8];
10793 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10794};
10795
50b4a3c2
HN		 10796struct mlx5_ifc_pbmc_reg_bits {
10797 u8 reserved_at_0[0x8];
10798 u8 local_port[0x8];
10799 u8 reserved_at_10[0x10];
10800
10801 u8 xoff_timer_value[0x10];
10802 u8 xoff_refresh[0x10];
10803
10804 u8 reserved_at_40[0x9];
10805 u8 fullness_threshold[0x7];
10806 u8 port_buffer_size[0x10];
10807
10808 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10809
534b1204 10810 u8 reserved_at_2e0[0x80];
50b4a3c2
HN		 10811};
10812
4f3961ee
SM		 10813struct mlx5_ifc_qtct_reg_bits {
10814 u8 reserved_at_0[0x8];
10815 u8 port_number[0x8];
10816 u8 reserved_at_10[0xd];
10817 u8 prio[0x3];
10818
10819 u8 reserved_at_20[0x1d];
10820 u8 tclass[0x3];
10821};
10822
7d5e1423
SM		 10823struct mlx5_ifc_mcia_reg_bits {
10824 u8 l[0x1];
10825 u8 reserved_at_1[0x7];
10826 u8 module[0x8];
10827 u8 reserved_at_10[0x8];
10828 u8 status[0x8];
10829
10830 u8 i2c_device_address[0x8];
10831 u8 page_number[0x8];
10832 u8 device_address[0x10];
10833
10834 u8 reserved_at_40[0x10];
10835 u8 size[0x10];
10836
10837 u8 reserved_at_60[0x20];
10838
10839 u8 dword_0[0x20];
10840 u8 dword_1[0x20];
10841 u8 dword_2[0x20];
10842 u8 dword_3[0x20];
10843 u8 dword_4[0x20];
10844 u8 dword_5[0x20];
10845 u8 dword_6[0x20];
10846 u8 dword_7[0x20];
10847 u8 dword_8[0x20];
10848 u8 dword_9[0x20];
10849 u8 dword_10[0x20];
10850 u8 dword_11[0x20];
10851};
10852
7486216b
SM		 10853struct mlx5_ifc_dcbx_param_bits {
10854 u8 dcbx_cee_cap[0x1];
10855 u8 dcbx_ieee_cap[0x1];
10856 u8 dcbx_standby_cap[0x1];
c74d90c1 10857 u8 reserved_at_3[0x5];
7486216b
SM		 10858 u8 port_number[0x8];
10859 u8 reserved_at_10[0xa];
10860 u8 max_application_table_size[6];
10861 u8 reserved_at_20[0x15];
10862 u8 version_oper[0x3];
10863 u8 reserved_at_38[5];
10864 u8 version_admin[0x3];
10865 u8 willing_admin[0x1];
10866 u8 reserved_at_41[0x3];
10867 u8 pfc_cap_oper[0x4];
10868 u8 reserved_at_48[0x4];
10869 u8 pfc_cap_admin[0x4];
10870 u8 reserved_at_50[0x4];
10871 u8 num_of_tc_oper[0x4];
10872 u8 reserved_at_58[0x4];
10873 u8 num_of_tc_admin[0x4];
10874 u8 remote_willing[0x1];
10875 u8 reserved_at_61[3];
10876 u8 remote_pfc_cap[4];
10877 u8 reserved_at_68[0x14];
10878 u8 remote_num_of_tc[0x4];
10879 u8 reserved_at_80[0x18];
10880 u8 error[0x8];
10881 u8 reserved_at_a0[0x160];
10882};
84df61eb 10883
425a563a
MG		 10884enum {
10885 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
94db3317
EC		 10886 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
10887 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
425a563a
MG		 10888};
10889
84df61eb 10890struct mlx5_ifc_lagc_bits {
c3e666f1 10891 u8 fdb_selection_mode[0x1];
425a563a
MG		 10892 u8 reserved_at_1[0x14];
10893 u8 port_select_mode[0x3];
10894 u8 reserved_at_18[0x5];
84df61eb
AH		 10895 u8 lag_state[0x3];
10896
10897 u8 reserved_at_20[0x14];
10898 u8 tx_remap_affinity_2[0x4];
10899 u8 reserved_at_38[0x4];
10900 u8 tx_remap_affinity_1[0x4];
10901};
10902
10903struct mlx5_ifc_create_lag_out_bits {
10904 u8 status[0x8];
10905 u8 reserved_at_8[0x18];
10906
10907 u8 syndrome[0x20];
10908
10909 u8 reserved_at_40[0x40];
10910};
10911
10912struct mlx5_ifc_create_lag_in_bits {
10913 u8 opcode[0x10];
10914 u8 reserved_at_10[0x10];
10915
10916 u8 reserved_at_20[0x10];
10917 u8 op_mod[0x10];
10918
10919 struct mlx5_ifc_lagc_bits ctx;
10920};
10921
10922struct mlx5_ifc_modify_lag_out_bits {
10923 u8 status[0x8];
10924 u8 reserved_at_8[0x18];
10925
10926 u8 syndrome[0x20];
10927
10928 u8 reserved_at_40[0x40];
10929};
10930
10931struct mlx5_ifc_modify_lag_in_bits {
10932 u8 opcode[0x10];
10933 u8 reserved_at_10[0x10];
10934
10935 u8 reserved_at_20[0x10];
10936 u8 op_mod[0x10];
10937
10938 u8 reserved_at_40[0x20];
10939 u8 field_select[0x20];
10940
10941 struct mlx5_ifc_lagc_bits ctx;
10942};
10943
10944struct mlx5_ifc_query_lag_out_bits {
10945 u8 status[0x8];
10946 u8 reserved_at_8[0x18];
10947
10948 u8 syndrome[0x20];
10949
84df61eb
AH		 10950 struct mlx5_ifc_lagc_bits ctx;
10951};
10952
10953struct mlx5_ifc_query_lag_in_bits {
10954 u8 opcode[0x10];
10955 u8 reserved_at_10[0x10];
10956
10957 u8 reserved_at_20[0x10];
10958 u8 op_mod[0x10];
10959
10960 u8 reserved_at_40[0x40];
10961};
10962
10963struct mlx5_ifc_destroy_lag_out_bits {
10964 u8 status[0x8];
10965 u8 reserved_at_8[0x18];
10966
10967 u8 syndrome[0x20];
10968
10969 u8 reserved_at_40[0x40];
10970};
10971
10972struct mlx5_ifc_destroy_lag_in_bits {
10973 u8 opcode[0x10];
10974 u8 reserved_at_10[0x10];
10975
10976 u8 reserved_at_20[0x10];
10977 u8 op_mod[0x10];
10978
10979 u8 reserved_at_40[0x40];
10980};
10981
10982struct mlx5_ifc_create_vport_lag_out_bits {
10983 u8 status[0x8];
10984 u8 reserved_at_8[0x18];
10985
10986 u8 syndrome[0x20];
10987
10988 u8 reserved_at_40[0x40];
10989};
10990
10991struct mlx5_ifc_create_vport_lag_in_bits {
10992 u8 opcode[0x10];
10993 u8 reserved_at_10[0x10];
10994
10995 u8 reserved_at_20[0x10];
10996 u8 op_mod[0x10];
10997
10998 u8 reserved_at_40[0x40];
10999};
11000
11001struct mlx5_ifc_destroy_vport_lag_out_bits {
11002 u8 status[0x8];
11003 u8 reserved_at_8[0x18];
11004
11005 u8 syndrome[0x20];
11006
11007 u8 reserved_at_40[0x40];
11008};
11009
11010struct mlx5_ifc_destroy_vport_lag_in_bits {
11011 u8 opcode[0x10];
11012 u8 reserved_at_10[0x10];
11013
11014 u8 reserved_at_20[0x10];
11015 u8 op_mod[0x10];
11016
11017 u8 reserved_at_40[0x40];
11018};
11019
63f9c44b
MG		 11020enum {
11021 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11022 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11023};
11024
11025struct mlx5_ifc_modify_memic_in_bits {
11026 u8 opcode[0x10];
11027 u8 uid[0x10];
11028
11029 u8 reserved_at_20[0x10];
11030 u8 op_mod[0x10];
11031
11032 u8 reserved_at_40[0x20];
11033
11034 u8 reserved_at_60[0x18];
11035 u8 memic_operation_type[0x8];
11036
11037 u8 memic_start_addr[0x40];
11038
11039 u8 reserved_at_c0[0x140];
11040};
11041
11042struct mlx5_ifc_modify_memic_out_bits {
11043 u8 status[0x8];
11044 u8 reserved_at_8[0x18];
11045
11046 u8 syndrome[0x20];
11047
11048 u8 reserved_at_40[0x40];
11049
11050 u8 memic_operation_addr[0x40];
11051
11052 u8 reserved_at_c0[0x140];
11053};
11054
24da0016
AL		 11055struct mlx5_ifc_alloc_memic_in_bits {
11056 u8 opcode[0x10];
11057 u8 reserved_at_10[0x10];
11058
11059 u8 reserved_at_20[0x10];
11060 u8 op_mod[0x10];
11061
11062 u8 reserved_at_30[0x20];
11063
11064 u8 reserved_at_40[0x18];
11065 u8 log_memic_addr_alignment[0x8];
11066
11067 u8 range_start_addr[0x40];
11068
11069 u8 range_size[0x20];
11070
11071 u8 memic_size[0x20];
11072};
11073
11074struct mlx5_ifc_alloc_memic_out_bits {
11075 u8 status[0x8];
11076 u8 reserved_at_8[0x18];
11077
11078 u8 syndrome[0x20];
11079
11080 u8 memic_start_addr[0x40];
11081};
11082
11083struct mlx5_ifc_dealloc_memic_in_bits {
11084 u8 opcode[0x10];
11085 u8 reserved_at_10[0x10];
11086
11087 u8 reserved_at_20[0x10];
11088 u8 op_mod[0x10];
11089
11090 u8 reserved_at_40[0x40];
11091
11092 u8 memic_start_addr[0x40];
11093
11094 u8 memic_size[0x20];
11095
11096 u8 reserved_at_e0[0x20];
11097};
11098
11099struct mlx5_ifc_dealloc_memic_out_bits {
11100 u8 status[0x8];
11101 u8 reserved_at_8[0x18];
11102
11103 u8 syndrome[0x20];
11104
11105 u8 reserved_at_40[0x40];
11106};
11107
38b7ca92 11108struct mlx5_ifc_umem_bits {
6e3722ba 11109 u8 reserved_at_0[0x80];
38b7ca92 11110
6e3722ba 11111 u8 reserved_at_80[0x1b];
38b7ca92
YH		 11112 u8 log_page_size[0x5];
11113
11114 u8 page_offset[0x20];
11115
11116 u8 num_of_mtt[0x40];
11117
b6ca09cb 11118 struct mlx5_ifc_mtt_bits mtt[];
38b7ca92
YH		 11119};
11120
11121struct mlx5_ifc_uctx_bits {
9d43faac
YH		 11122 u8 cap[0x20];
11123
6e3722ba 11124 u8 reserved_at_20[0x160];
38b7ca92
YH		 11125};
11126
9fba2b9b
AL		 11127struct mlx5_ifc_sw_icm_bits {
11128 u8 modify_field_select[0x40];
11129
11130 u8 reserved_at_40[0x18];
11131 u8 log_sw_icm_size[0x8];
11132
11133 u8 reserved_at_60[0x20];
11134
11135 u8 sw_icm_start_addr[0x40];
11136
11137 u8 reserved_at_c0[0x140];
91a40a48 11138};
b169e64a
YK		 11139
11140struct mlx5_ifc_geneve_tlv_option_bits {
11141 u8 modify_field_select[0x40];
11142
11143 u8 reserved_at_40[0x18];
11144 u8 geneve_option_fte_index[0x8];
11145
11146 u8 option_class[0x10];
11147 u8 option_type[0x8];
11148 u8 reserved_at_78[0x3];
11149 u8 option_data_length[0x5];
11150
11151 u8 reserved_at_80[0x180];
9fba2b9b
AL		 11152};
11153
38b7ca92 11154struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 11155 u8 opcode[0x10];
11156 u8 uid[0x10];
11157
11158 u8 reserved_at_20[0x10];
11159 u8 op_mod[0x10];
11160
11161 u8 reserved_at_40[0x40];
11162
11163 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 11164};
11165
8a06a79b
EC		 11166struct mlx5_ifc_create_umem_out_bits {
11167 u8 status[0x8];
11168 u8 reserved_at_8[0x18];
11169
11170 u8 syndrome[0x20];
11171
11172 u8 reserved_at_40[0x8];
11173 u8 umem_id[0x18];
11174
11175 u8 reserved_at_60[0x20];
11176};
11177
11178struct mlx5_ifc_destroy_umem_in_bits {
11179 u8 opcode[0x10];
11180 u8 uid[0x10];
11181
11182 u8 reserved_at_20[0x10];
11183 u8 op_mod[0x10];
11184
11185 u8 reserved_at_40[0x8];
11186 u8 umem_id[0x18];
11187
11188 u8 reserved_at_60[0x20];
11189};
11190
11191struct mlx5_ifc_destroy_umem_out_bits {
11192 u8 status[0x8];
11193 u8 reserved_at_8[0x18];
11194
11195 u8 syndrome[0x20];
11196
11197 u8 reserved_at_40[0x40];
11198};
11199
38b7ca92 11200struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 11201 u8 opcode[0x10];
11202 u8 reserved_at_10[0x10];
11203
11204 u8 reserved_at_20[0x10];
11205 u8 op_mod[0x10];
11206
11207 u8 reserved_at_40[0x40];
11208
11209 struct mlx5_ifc_uctx_bits uctx;
11210};
11211
8a06a79b
EC		 11212struct mlx5_ifc_create_uctx_out_bits {
11213 u8 status[0x8];
11214 u8 reserved_at_8[0x18];
11215
11216 u8 syndrome[0x20];
11217
11218 u8 reserved_at_40[0x10];
11219 u8 uid[0x10];
11220
11221 u8 reserved_at_60[0x20];
11222};
11223
6e3722ba
YH		 11224struct mlx5_ifc_destroy_uctx_in_bits {
11225 u8 opcode[0x10];
11226 u8 reserved_at_10[0x10];
11227
11228 u8 reserved_at_20[0x10];
11229 u8 op_mod[0x10];
11230
11231 u8 reserved_at_40[0x10];
11232 u8 uid[0x10];
11233
11234 u8 reserved_at_60[0x20];
38b7ca92
YH		 11235};
11236
8a06a79b
EC		 11237struct mlx5_ifc_destroy_uctx_out_bits {
11238 u8 status[0x8];
11239 u8 reserved_at_8[0x18];
11240
11241 u8 syndrome[0x20];
11242
11243 u8 reserved_at_40[0x40];
11244};
11245
9fba2b9b
AL		 11246struct mlx5_ifc_create_sw_icm_in_bits {
11247 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11248 struct mlx5_ifc_sw_icm_bits sw_icm;
11249};
11250
b169e64a
YK		 11251struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11252 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11253 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
11254};
11255
eff8ea8f
FD		 11256struct mlx5_ifc_mtrc_string_db_param_bits {
11257 u8 string_db_base_address[0x20];
11258
11259 u8 reserved_at_20[0x8];
11260 u8 string_db_size[0x18];
11261};
11262
11263struct mlx5_ifc_mtrc_cap_bits {
11264 u8 trace_owner[0x1];
11265 u8 trace_to_memory[0x1];
11266 u8 reserved_at_2[0x4];
11267 u8 trc_ver[0x2];
11268 u8 reserved_at_8[0x14];
11269 u8 num_string_db[0x4];
11270
11271 u8 first_string_trace[0x8];
11272 u8 num_string_trace[0x8];
11273 u8 reserved_at_30[0x28];
11274
11275 u8 log_max_trace_buffer_size[0x8];
11276
11277 u8 reserved_at_60[0x20];
11278
11279 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11280
11281 u8 reserved_at_280[0x180];
11282};
11283
11284struct mlx5_ifc_mtrc_conf_bits {
11285 u8 reserved_at_0[0x1c];
11286 u8 trace_mode[0x4];
11287 u8 reserved_at_20[0x18];
11288 u8 log_trace_buffer_size[0x8];
11289 u8 trace_mkey[0x20];
11290 u8 reserved_at_60[0x3a0];
11291};
11292
11293struct mlx5_ifc_mtrc_stdb_bits {
11294 u8 string_db_index[0x4];
11295 u8 reserved_at_4[0x4];
11296 u8 read_size[0x18];
11297 u8 start_offset[0x20];
b6ca09cb 11298 u8 string_db_data[];
eff8ea8f
FD		 11299};
11300
11301struct mlx5_ifc_mtrc_ctrl_bits {
11302 u8 trace_status[0x2];
11303 u8 reserved_at_2[0x2];
11304 u8 arm_event[0x1];
11305 u8 reserved_at_5[0xb];
11306 u8 modify_field_select[0x10];
11307 u8 reserved_at_20[0x2b];
11308 u8 current_timestamp52_32[0x15];
11309 u8 current_timestamp31_0[0x20];
11310 u8 reserved_at_80[0x180];
11311};
11312
c3a4e9f1
BW		 11313struct mlx5_ifc_host_params_context_bits {
11314 u8 host_number[0x8];
5ccf2770
BW		 11315 u8 reserved_at_8[0x7];
11316 u8 host_pf_disabled[0x1];
c3a4e9f1
BW		 11317 u8 host_num_of_vfs[0x10];
11318
86eec50b 11319 u8 host_total_vfs[0x10];
c3a4e9f1
BW		 11320 u8 host_pci_bus[0x10];
11321
11322 u8 reserved_at_40[0x10];
11323 u8 host_pci_device[0x10];
11324
11325 u8 reserved_at_60[0x10];
11326 u8 host_pci_function[0x10];
11327
11328 u8 reserved_at_80[0x180];
11329};
11330
cd56f929 11331struct mlx5_ifc_query_esw_functions_in_bits {
c3a4e9f1
BW		 11332 u8 opcode[0x10];
11333 u8 reserved_at_10[0x10];
11334
11335 u8 reserved_at_20[0x10];
11336 u8 op_mod[0x10];
11337
11338 u8 reserved_at_40[0x40];
11339};
11340
cd56f929 11341struct mlx5_ifc_query_esw_functions_out_bits {
c3a4e9f1
BW		 11342 u8 status[0x8];
11343 u8 reserved_at_8[0x18];
11344
11345 u8 syndrome[0x20];
11346
11347 u8 reserved_at_40[0x40];
11348
11349 struct mlx5_ifc_host_params_context_bits host_params_context;
11350
11351 u8 reserved_at_280[0x180];
b6ca09cb 11352 u8 host_sf_enable[][0x40];
1759d322
PP		 11353};
11354
11355struct mlx5_ifc_sf_partition_bits {
11356 u8 reserved_at_0[0x10];
11357 u8 log_num_sf[0x8];
11358 u8 log_sf_bar_size[0x8];
11359};
11360
11361struct mlx5_ifc_query_sf_partitions_out_bits {
11362 u8 status[0x8];
11363 u8 reserved_at_8[0x18];
11364
11365 u8 syndrome[0x20];
11366
11367 u8 reserved_at_40[0x18];
11368 u8 num_sf_partitions[0x8];
11369
11370 u8 reserved_at_60[0x20];
11371
b6ca09cb 11372 struct mlx5_ifc_sf_partition_bits sf_partition[];
1759d322
PP		 11373};
11374
11375struct mlx5_ifc_query_sf_partitions_in_bits {
11376 u8 opcode[0x10];
11377 u8 reserved_at_10[0x10];
11378
11379 u8 reserved_at_20[0x10];
11380 u8 op_mod[0x10];
11381
11382 u8 reserved_at_40[0x40];
11383};
11384
11385struct mlx5_ifc_dealloc_sf_out_bits {
11386 u8 status[0x8];
11387 u8 reserved_at_8[0x18];
11388
11389 u8 syndrome[0x20];
11390
11391 u8 reserved_at_40[0x40];
11392};
11393
11394struct mlx5_ifc_dealloc_sf_in_bits {
11395 u8 opcode[0x10];
11396 u8 reserved_at_10[0x10];
11397
11398 u8 reserved_at_20[0x10];
11399 u8 op_mod[0x10];
11400
11401 u8 reserved_at_40[0x10];
11402 u8 function_id[0x10];
11403
11404 u8 reserved_at_60[0x20];
11405};
11406
11407struct mlx5_ifc_alloc_sf_out_bits {
11408 u8 status[0x8];
11409 u8 reserved_at_8[0x18];
11410
11411 u8 syndrome[0x20];
11412
11413 u8 reserved_at_40[0x40];
11414};
11415
11416struct mlx5_ifc_alloc_sf_in_bits {
11417 u8 opcode[0x10];
11418 u8 reserved_at_10[0x10];
11419
11420 u8 reserved_at_20[0x10];
11421 u8 op_mod[0x10];
11422
11423 u8 reserved_at_40[0x10];
11424 u8 function_id[0x10];
11425
11426 u8 reserved_at_60[0x20];
c3a4e9f1
BW		 11427};
11428
e4075c44
YH		 11429struct mlx5_ifc_affiliated_event_header_bits {
11430 u8 reserved_at_0[0x10];
11431 u8 obj_type[0x10];
11432
11433 u8 obj_id[0x20];
11434};
11435
a12ff35e 11436enum {
49e27134
PP		 11437 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11438 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11439 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
f5d23ee1 11440 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
a12ff35e
EBE		 11441};
11442
11443enum {
11444 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
2b58f6d9 11445 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
2a297089 11446 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
f5d23ee1 11447 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
2b58f6d9
RS		 11448};
11449
11450enum {
11451 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
2b58f6d9
RS		 11452};
11453
11454struct mlx5_ifc_ipsec_obj_bits {
11455 u8 modify_field_select[0x40];
11456 u8 full_offload[0x1];
11457 u8 reserved_at_41[0x1];
11458 u8 esn_en[0x1];
11459 u8 esn_overlap[0x1];
11460 u8 reserved_at_44[0x2];
11461 u8 icv_length[0x2];
11462 u8 reserved_at_48[0x4];
11463 u8 aso_return_reg[0x4];
11464 u8 reserved_at_50[0x10];
11465
11466 u8 esn_msb[0x20];
11467
11468 u8 reserved_at_80[0x8];
11469 u8 dekn[0x18];
11470
11471 u8 salt[0x20];
11472
11473 u8 implicit_iv[0x40];
11474
11475 u8 reserved_at_100[0x700];
11476};
11477
11478struct mlx5_ifc_create_ipsec_obj_in_bits {
11479 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11480 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11481};
11482
11483enum {
11484 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11485 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11486};
11487
11488struct mlx5_ifc_query_ipsec_obj_out_bits {
11489 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11490 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11491};
11492
11493struct mlx5_ifc_modify_ipsec_obj_in_bits {
11494 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11495 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
a12ff35e
EBE		 11496};
11497
11498struct mlx5_ifc_encryption_key_obj_bits {
11499 u8 modify_field_select[0x40];
11500
11501 u8 reserved_at_40[0x14];
11502 u8 key_size[0x4];
11503 u8 reserved_at_58[0x4];
11504 u8 key_type[0x4];
11505
11506 u8 reserved_at_60[0x8];
11507 u8 pd[0x18];
11508
11509 u8 reserved_at_80[0x180];
11510 u8 key[8][0x20];
11511
11512 u8 reserved_at_300[0x500];
11513};
11514
11515struct mlx5_ifc_create_encryption_key_in_bits {
11516 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11517 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11518};
11519
f5d23ee1
JL		 11520enum {
11521 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0,
11522 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1,
11523 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2,
11524 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3,
11525};
11526
11527struct mlx5_ifc_flow_meter_parameters_bits {
11528 u8 valid[0x1];
11529 u8 bucket_overflow[0x1];
11530 u8 start_color[0x2];
11531 u8 both_buckets_on_green[0x1];
11532 u8 reserved_at_5[0x1];
11533 u8 meter_mode[0x2];
11534 u8 reserved_at_8[0x18];
11535
11536 u8 reserved_at_20[0x20];
11537
11538 u8 reserved_at_40[0x3];
11539 u8 cbs_exponent[0x5];
11540 u8 cbs_mantissa[0x8];
11541 u8 reserved_at_50[0x3];
11542 u8 cir_exponent[0x5];
11543 u8 cir_mantissa[0x8];
11544
11545 u8 reserved_at_60[0x20];
11546
11547 u8 reserved_at_80[0x3];
11548 u8 ebs_exponent[0x5];
11549 u8 ebs_mantissa[0x8];
11550 u8 reserved_at_90[0x3];
11551 u8 eir_exponent[0x5];
11552 u8 eir_mantissa[0x8];
11553
11554 u8 reserved_at_a0[0x60];
11555};
11556
11557struct mlx5_ifc_flow_meter_aso_obj_bits {
11558 u8 modify_field_select[0x40];
11559
11560 u8 reserved_at_40[0x40];
11561
11562 u8 reserved_at_80[0x8];
11563 u8 meter_aso_access_pd[0x18];
11564
11565 u8 reserved_at_a0[0x160];
11566
11567 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
11568};
11569
11570struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
11571 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11572 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
11573};
11574
2a297089
CM		 11575struct mlx5_ifc_sampler_obj_bits {
11576 u8 modify_field_select[0x40];
11577
11578 u8 table_type[0x8];
11579 u8 level[0x8];
11580 u8 reserved_at_50[0xf];
11581 u8 ignore_flow_level[0x1];
11582
11583 u8 sample_ratio[0x20];
11584
11585 u8 reserved_at_80[0x8];
11586 u8 sample_table_id[0x18];
11587
11588 u8 reserved_at_a0[0x8];
11589 u8 default_table_id[0x18];
11590
11591 u8 sw_steering_icm_address_rx[0x40];
11592 u8 sw_steering_icm_address_tx[0x40];
11593
11594 u8 reserved_at_140[0xa0];
11595};
11596
11597struct mlx5_ifc_create_sampler_obj_in_bits {
11598 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11599 struct mlx5_ifc_sampler_obj_bits sampler_object;
11600};
11601
1ab6dc35
YK		 11602struct mlx5_ifc_query_sampler_obj_out_bits {
11603 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11604 struct mlx5_ifc_sampler_obj_bits sampler_object;
11605};
11606
a12ff35e
EBE		 11607enum {
11608 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11609 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11610};
11611
11612enum {
bd673da6
SM		 11613 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11614 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
a12ff35e
EBE		 11615};
11616
11617struct mlx5_ifc_tls_static_params_bits {
11618 u8 const_2[0x2];
11619 u8 tls_version[0x4];
11620 u8 const_1[0x2];
11621 u8 reserved_at_8[0x14];
11622 u8 encryption_standard[0x4];
11623
11624 u8 reserved_at_20[0x20];
11625
11626 u8 initial_record_number[0x40];
11627
11628 u8 resync_tcp_sn[0x20];
11629
11630 u8 gcm_iv[0x20];
11631
11632 u8 implicit_iv[0x40];
11633
11634 u8 reserved_at_100[0x8];
11635 u8 dek_index[0x18];
11636
11637 u8 reserved_at_120[0xe0];
11638};
11639
11640struct mlx5_ifc_tls_progress_params_bits {
a12ff35e
EBE		 11641 u8 next_record_tcp_sn[0x20];
11642
11643 u8 hw_resync_tcp_sn[0x20];
11644
11645 u8 record_tracker_state[0x2];
11646 u8 auth_state[0x2];
2d1b69ed 11647 u8 reserved_at_44[0x4];
a12ff35e
EBE		 11648 u8 hw_offset_record_number[0x18];
11649};
11650
1dcb6c36
EC		 11651enum {
11652 MLX5_MTT_PERM_READ = 1 << 0,
11653 MLX5_MTT_PERM_WRITE = 1 << 1,
11654 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11655};
11656
adfdaff3
YH		 11657enum {
11658 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
11659 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
11660};
11661
11662struct mlx5_ifc_suspend_vhca_in_bits {
11663 u8 opcode[0x10];
11664 u8 uid[0x10];
11665
11666 u8 reserved_at_20[0x10];
11667 u8 op_mod[0x10];
11668
11669 u8 reserved_at_40[0x10];
11670 u8 vhca_id[0x10];
11671
11672 u8 reserved_at_60[0x20];
11673};
11674
11675struct mlx5_ifc_suspend_vhca_out_bits {
11676 u8 status[0x8];
11677 u8 reserved_at_8[0x18];
11678
11679 u8 syndrome[0x20];
11680
11681 u8 reserved_at_40[0x40];
11682};
11683
11684enum {
11685 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
11686 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
11687};
11688
11689struct mlx5_ifc_resume_vhca_in_bits {
11690 u8 opcode[0x10];
11691 u8 uid[0x10];
11692
11693 u8 reserved_at_20[0x10];
11694 u8 op_mod[0x10];
11695
11696 u8 reserved_at_40[0x10];
11697 u8 vhca_id[0x10];
11698
11699 u8 reserved_at_60[0x20];
11700};
11701
11702struct mlx5_ifc_resume_vhca_out_bits {
11703 u8 status[0x8];
11704 u8 reserved_at_8[0x18];
11705
11706 u8 syndrome[0x20];
11707
11708 u8 reserved_at_40[0x40];
11709};
11710
11711struct mlx5_ifc_query_vhca_migration_state_in_bits {
11712 u8 opcode[0x10];
11713 u8 uid[0x10];
11714
11715 u8 reserved_at_20[0x10];
11716 u8 op_mod[0x10];
11717
11718 u8 reserved_at_40[0x10];
11719 u8 vhca_id[0x10];
11720
11721 u8 reserved_at_60[0x20];
11722};
11723
11724struct mlx5_ifc_query_vhca_migration_state_out_bits {
11725 u8 status[0x8];
11726 u8 reserved_at_8[0x18];
11727
11728 u8 syndrome[0x20];
11729
11730 u8 reserved_at_40[0x40];
11731
11732 u8 required_umem_size[0x20];
11733
11734 u8 reserved_at_a0[0x160];
11735};
11736
11737struct mlx5_ifc_save_vhca_state_in_bits {
11738 u8 opcode[0x10];
11739 u8 uid[0x10];
11740
11741 u8 reserved_at_20[0x10];
11742 u8 op_mod[0x10];
11743
11744 u8 reserved_at_40[0x10];
11745 u8 vhca_id[0x10];
11746
11747 u8 reserved_at_60[0x20];
11748
11749 u8 va[0x40];
11750
11751 u8 mkey[0x20];
11752
11753 u8 size[0x20];
11754};
11755
11756struct mlx5_ifc_save_vhca_state_out_bits {
11757 u8 status[0x8];
11758 u8 reserved_at_8[0x18];
11759
11760 u8 syndrome[0x20];
11761
11762 u8 actual_image_size[0x20];
11763
11764 u8 reserved_at_60[0x20];
11765};
11766
11767struct mlx5_ifc_load_vhca_state_in_bits {
11768 u8 opcode[0x10];
11769 u8 uid[0x10];
11770
11771 u8 reserved_at_20[0x10];
11772 u8 op_mod[0x10];
11773
11774 u8 reserved_at_40[0x10];
11775 u8 vhca_id[0x10];
11776
11777 u8 reserved_at_60[0x20];
11778
11779 u8 va[0x40];
11780
11781 u8 mkey[0x20];
11782
11783 u8 size[0x20];
11784};
11785
11786struct mlx5_ifc_load_vhca_state_out_bits {
11787 u8 status[0x8];
11788 u8 reserved_at_8[0x18];
11789
11790 u8 syndrome[0x20];
11791
11792 u8 reserved_at_40[0x40];
11793};
11794
d29b796a 11795#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)