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IB/mlx5: Verify DEVX general object type correctly
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
66enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71};
72
f91e6d89
EBE		 73enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89
EBE		 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77};
78
38b7ca92 79enum {
2acc7957 80 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 81};
82
9fba2b9b
AL		 83enum {
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
85};
86
87enum {
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89};
90
d29b796a
EC		 91enum {
92 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
93 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
94 MLX5_CMD_OP_INIT_HCA = 0x102,
95 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
96 MLX5_CMD_OP_ENABLE_HCA = 0x104,
97 MLX5_CMD_OP_DISABLE_HCA = 0x105,
98 MLX5_CMD_OP_QUERY_PAGES = 0x107,
99 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
100 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 101 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
102 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 103 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 104 MLX5_CMD_OP_CREATE_MKEY = 0x200,
105 MLX5_CMD_OP_QUERY_MKEY = 0x201,
106 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
107 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
108 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 109 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
110 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 111 MLX5_CMD_OP_CREATE_EQ = 0x301,
112 MLX5_CMD_OP_DESTROY_EQ = 0x302,
113 MLX5_CMD_OP_QUERY_EQ = 0x303,
114 MLX5_CMD_OP_GEN_EQE = 0x304,
115 MLX5_CMD_OP_CREATE_CQ = 0x400,
116 MLX5_CMD_OP_DESTROY_CQ = 0x401,
117 MLX5_CMD_OP_QUERY_CQ = 0x402,
118 MLX5_CMD_OP_MODIFY_CQ = 0x403,
119 MLX5_CMD_OP_CREATE_QP = 0x500,
120 MLX5_CMD_OP_DESTROY_QP = 0x501,
121 MLX5_CMD_OP_RST2INIT_QP = 0x502,
122 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
123 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
124 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
125 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
126 MLX5_CMD_OP_2ERR_QP = 0x507,
127 MLX5_CMD_OP_2RST_QP = 0x50a,
128 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 129 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 130 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
131 MLX5_CMD_OP_CREATE_PSV = 0x600,
132 MLX5_CMD_OP_DESTROY_PSV = 0x601,
133 MLX5_CMD_OP_CREATE_SRQ = 0x700,
134 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
135 MLX5_CMD_OP_QUERY_SRQ = 0x702,
136 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 137 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
138 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
139 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
140 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 141 MLX5_CMD_OP_CREATE_DCT = 0x710,
142 MLX5_CMD_OP_DESTROY_DCT = 0x711,
143 MLX5_CMD_OP_DRAIN_DCT = 0x712,
144 MLX5_CMD_OP_QUERY_DCT = 0x713,
145 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 146 MLX5_CMD_OP_CREATE_XRQ = 0x717,
147 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
148 MLX5_CMD_OP_QUERY_XRQ = 0x719,
149 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 150 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
151 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
152 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
c3a4e9f1 153 MLX5_CMD_OP_QUERY_HOST_PARAMS = 0x740,
d29b796a
EC		 154 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
155 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
156 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
157 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
158 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
159 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 160 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 161 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 162 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
163 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
164 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
165 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 166 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 167 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
168 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
169 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
170 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 171 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
172 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 173 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 174 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 175 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
176 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
177 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
178 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
179 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
180 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 181 MLX5_CMD_OP_ALLOC_PD = 0x800,
182 MLX5_CMD_OP_DEALLOC_PD = 0x801,
183 MLX5_CMD_OP_ALLOC_UAR = 0x802,
184 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
185 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
186 MLX5_CMD_OP_ACCESS_REG = 0x805,
187 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 188 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 189 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
190 MLX5_CMD_OP_MAD_IFC = 0x50d,
191 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
192 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
193 MLX5_CMD_OP_NOP = 0x80d,
194 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
195 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 196 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
197 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
198 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
199 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
200 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
201 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
202 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
203 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
204 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
205 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
206 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
207 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 208 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
209 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 210 MLX5_CMD_OP_CREATE_LAG = 0x840,
211 MLX5_CMD_OP_MODIFY_LAG = 0x841,
212 MLX5_CMD_OP_QUERY_LAG = 0x842,
213 MLX5_CMD_OP_DESTROY_LAG = 0x843,
214 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
215 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 216 MLX5_CMD_OP_CREATE_TIR = 0x900,
217 MLX5_CMD_OP_MODIFY_TIR = 0x901,
218 MLX5_CMD_OP_DESTROY_TIR = 0x902,
219 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 220 MLX5_CMD_OP_CREATE_SQ = 0x904,
221 MLX5_CMD_OP_MODIFY_SQ = 0x905,
222 MLX5_CMD_OP_DESTROY_SQ = 0x906,
223 MLX5_CMD_OP_QUERY_SQ = 0x907,
224 MLX5_CMD_OP_CREATE_RQ = 0x908,
225 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 226 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 227 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
228 MLX5_CMD_OP_QUERY_RQ = 0x90b,
229 MLX5_CMD_OP_CREATE_RMP = 0x90c,
230 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
231 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
232 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 233 MLX5_CMD_OP_CREATE_TIS = 0x912,
234 MLX5_CMD_OP_MODIFY_TIS = 0x913,
235 MLX5_CMD_OP_DESTROY_TIS = 0x914,
236 MLX5_CMD_OP_QUERY_TIS = 0x915,
237 MLX5_CMD_OP_CREATE_RQT = 0x916,
238 MLX5_CMD_OP_MODIFY_RQT = 0x917,
239 MLX5_CMD_OP_DESTROY_RQT = 0x918,
240 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 241 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 242 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
243 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
244 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
245 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
246 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
247 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
248 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
249 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 250 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 251 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
252 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
253 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 254 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 255 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
256 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 257 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 258 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
259 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 260 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 261 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
262 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
263 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
264 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
265 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 266 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 267 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
268 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 269 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 270 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
271 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
272 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
273 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
86d56a1a 274 MLX5_CMD_OP_MAX
e281682b
SM		 275};
276
719598c9
YH		 277/* Valid range for general commands that don't work over an object */
278enum {
279 MLX5_CMD_OP_GENERAL_START = 0xb00,
280 MLX5_CMD_OP_GENERAL_END = 0xd00,
281};
282
e281682b
SM		 283struct mlx5_ifc_flow_table_fields_supported_bits {
284 u8 outer_dmac[0x1];
285 u8 outer_smac[0x1];
286 u8 outer_ether_type[0x1];
19cc7524 287 u8 outer_ip_version[0x1];
e281682b
SM		 288 u8 outer_first_prio[0x1];
289 u8 outer_first_cfi[0x1];
290 u8 outer_first_vid[0x1];
a8ade55f 291 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 292 u8 outer_second_prio[0x1];
293 u8 outer_second_cfi[0x1];
294 u8 outer_second_vid[0x1];
b4ff3a36 295 u8 reserved_at_b[0x1];
e281682b
SM		 296 u8 outer_sip[0x1];
297 u8 outer_dip[0x1];
298 u8 outer_frag[0x1];
299 u8 outer_ip_protocol[0x1];
300 u8 outer_ip_ecn[0x1];
301 u8 outer_ip_dscp[0x1];
302 u8 outer_udp_sport[0x1];
303 u8 outer_udp_dport[0x1];
304 u8 outer_tcp_sport[0x1];
305 u8 outer_tcp_dport[0x1];
306 u8 outer_tcp_flags[0x1];
307 u8 outer_gre_protocol[0x1];
308 u8 outer_gre_key[0x1];
309 u8 outer_vxlan_vni[0x1];
b4ff3a36 310 u8 reserved_at_1a[0x5];
e281682b
SM		 311 u8 source_eswitch_port[0x1];
312
313 u8 inner_dmac[0x1];
314 u8 inner_smac[0x1];
315 u8 inner_ether_type[0x1];
19cc7524 316 u8 inner_ip_version[0x1];
e281682b
SM		 317 u8 inner_first_prio[0x1];
318 u8 inner_first_cfi[0x1];
319 u8 inner_first_vid[0x1];
b4ff3a36 320 u8 reserved_at_27[0x1];
e281682b
SM		 321 u8 inner_second_prio[0x1];
322 u8 inner_second_cfi[0x1];
323 u8 inner_second_vid[0x1];
b4ff3a36 324 u8 reserved_at_2b[0x1];
e281682b
SM		 325 u8 inner_sip[0x1];
326 u8 inner_dip[0x1];
327 u8 inner_frag[0x1];
328 u8 inner_ip_protocol[0x1];
329 u8 inner_ip_ecn[0x1];
330 u8 inner_ip_dscp[0x1];
331 u8 inner_udp_sport[0x1];
332 u8 inner_udp_dport[0x1];
333 u8 inner_tcp_sport[0x1];
334 u8 inner_tcp_dport[0x1];
335 u8 inner_tcp_flags[0x1];
b4ff3a36 336 u8 reserved_at_37[0x9];
71c6e863
AL		 337
338 u8 reserved_at_40[0x5];
339 u8 outer_first_mpls_over_udp[0x4];
340 u8 outer_first_mpls_over_gre[0x4];
341 u8 inner_first_mpls[0x4];
342 u8 outer_first_mpls[0x4];
343 u8 reserved_at_55[0x2];
3346c487 344 u8 outer_esp_spi[0x1];
71c6e863 345 u8 reserved_at_58[0x2];
a550ddfc 346 u8 bth_dst_qp[0x1];
e281682b 347
a550ddfc 348 u8 reserved_at_5b[0x25];
e281682b
SM		 349};
350
351struct mlx5_ifc_flow_table_prop_layout_bits {
352 u8 ft_support[0x1];
9dc0b289
AV		 353 u8 reserved_at_1[0x1];
354 u8 flow_counter[0x1];
26a81453 355 u8 flow_modify_en[0x1];
2cc43b49 356 u8 modify_root[0x1];
34a40e68
MG		 357 u8 identified_miss_table_mode[0x1];
358 u8 flow_table_modify[0x1];
60786f09 359 u8 reformat[0x1];
7adbde20 360 u8 decap[0x1];
0c06897a
OG		 361 u8 reserved_at_9[0x1];
362 u8 pop_vlan[0x1];
363 u8 push_vlan[0x1];
8da6fe2a
JL		 364 u8 reserved_at_c[0x1];
365 u8 pop_vlan_2[0x1];
366 u8 push_vlan_2[0x1];
bea4e1f6 367 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 368 u8 reserved_at_10[0x1];
369 u8 sw_owner[0x1];
bea4e1f6
MB		 370 u8 reformat_l3_tunnel_to_l2[0x1];
371 u8 reformat_l2_to_l3_tunnel[0x1];
372 u8 reformat_and_modify_action[0x1];
c74d90c1 373 u8 reserved_at_15[0xb];
b4ff3a36 374 u8 reserved_at_20[0x2];
e281682b 375 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 376 u8 log_max_modify_header_context[0x8];
377 u8 max_modify_header_actions[0x8];
e281682b
SM		 378 u8 max_ft_level[0x8];
379
b4ff3a36 380 u8 reserved_at_40[0x20];
e281682b 381
b4ff3a36 382 u8 reserved_at_60[0x18];
e281682b
SM		 383 u8 log_max_ft_num[0x8];
384
b4ff3a36 385 u8 reserved_at_80[0x18];
e281682b
SM		 386 u8 log_max_destination[0x8];
387
16f1c5bb
RS		 388 u8 log_max_flow_counter[0x8];
389 u8 reserved_at_a8[0x10];
e281682b
SM		 390 u8 log_max_flow[0x8];
391
b4ff3a36 392 u8 reserved_at_c0[0x40];
e281682b
SM		 393
394 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
395
396 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
397};
398
399struct mlx5_ifc_odp_per_transport_service_cap_bits {
400 u8 send[0x1];
401 u8 receive[0x1];
402 u8 write[0x1];
403 u8 read[0x1];
17d2f88f 404 u8 atomic[0x1];
e281682b 405 u8 srq_receive[0x1];
b4ff3a36 406 u8 reserved_at_6[0x1a];
e281682b
SM		 407};
408
409struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
410 u8 smac_47_16[0x20];
411
412 u8 smac_15_0[0x10];
413 u8 ethertype[0x10];
414
415 u8 dmac_47_16[0x20];
416
417 u8 dmac_15_0[0x10];
418 u8 first_prio[0x3];
419 u8 first_cfi[0x1];
420 u8 first_vid[0xc];
421
422 u8 ip_protocol[0x8];
423 u8 ip_dscp[0x6];
424 u8 ip_ecn[0x2];
10543365
MHY		 425 u8 cvlan_tag[0x1];
426 u8 svlan_tag[0x1];
e281682b 427 u8 frag[0x1];
19cc7524 428 u8 ip_version[0x4];
e281682b
SM		 429 u8 tcp_flags[0x9];
430
431 u8 tcp_sport[0x10];
432 u8 tcp_dport[0x10];
433
a8ade55f
OG		 434 u8 reserved_at_c0[0x18];
435 u8 ttl_hoplimit[0x8];
e281682b
SM		 436
437 u8 udp_sport[0x10];
438 u8 udp_dport[0x10];
439
b4d1f032 440 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 441
b4d1f032 442 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 443};
444
5886a96a
OS		 445struct mlx5_ifc_nvgre_key_bits {
446 u8 hi[0x18];
447 u8 lo[0x8];
448};
449
450union mlx5_ifc_gre_key_bits {
451 struct mlx5_ifc_nvgre_key_bits nvgre;
452 u8 key[0x20];
453};
454
e281682b 455struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 456 u8 reserved_at_0[0x8];
457 u8 source_sqn[0x18];
e281682b 458
3e99df87 459 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 460 u8 source_port[0x10];
461
462 u8 outer_second_prio[0x3];
463 u8 outer_second_cfi[0x1];
464 u8 outer_second_vid[0xc];
465 u8 inner_second_prio[0x3];
466 u8 inner_second_cfi[0x1];
467 u8 inner_second_vid[0xc];
468
10543365
MHY		 469 u8 outer_second_cvlan_tag[0x1];
470 u8 inner_second_cvlan_tag[0x1];
471 u8 outer_second_svlan_tag[0x1];
472 u8 inner_second_svlan_tag[0x1];
473 u8 reserved_at_64[0xc];
e281682b
SM		 474 u8 gre_protocol[0x10];
475
5886a96a 476 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 477
478 u8 vxlan_vni[0x18];
b4ff3a36 479 u8 reserved_at_b8[0x8];
e281682b 480
b4ff3a36 481 u8 reserved_at_c0[0x20];
e281682b 482
b4ff3a36 483 u8 reserved_at_e0[0xc];
e281682b
SM		 484 u8 outer_ipv6_flow_label[0x14];
485
b4ff3a36 486 u8 reserved_at_100[0xc];
e281682b
SM		 487 u8 inner_ipv6_flow_label[0x14];
488
a550ddfc
YH		 489 u8 reserved_at_120[0x28];
490 u8 bth_dst_qp[0x18];
3346c487
BP		 491 u8 reserved_at_160[0x20];
492 u8 outer_esp_spi[0x20];
493 u8 reserved_at_1a0[0x60];
e281682b
SM		 494};
495
71c6e863
AL		 496struct mlx5_ifc_fte_match_mpls_bits {
497 u8 mpls_label[0x14];
498 u8 mpls_exp[0x3];
499 u8 mpls_s_bos[0x1];
500 u8 mpls_ttl[0x8];
501};
502
503struct mlx5_ifc_fte_match_set_misc2_bits {
504 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
505
506 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
507
508 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
509
510 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
511
512 u8 reserved_at_80[0x100];
513
514 u8 metadata_reg_a[0x20];
515
516 u8 reserved_at_1a0[0x60];
517};
518
e281682b
SM		 519struct mlx5_ifc_cmd_pas_bits {
520 u8 pa_h[0x20];
521
522 u8 pa_l[0x14];
b4ff3a36 523 u8 reserved_at_34[0xc];
e281682b
SM		 524};
525
526struct mlx5_ifc_uint64_bits {
527 u8 hi[0x20];
528
529 u8 lo[0x20];
530};
531
532enum {
533 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
534 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
535 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
536 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
537 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
538 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
539 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
540 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
541 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
542 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
543};
544
545struct mlx5_ifc_ads_bits {
546 u8 fl[0x1];
547 u8 free_ar[0x1];
b4ff3a36 548 u8 reserved_at_2[0xe];
e281682b
SM		 549 u8 pkey_index[0x10];
550
b4ff3a36 551 u8 reserved_at_20[0x8];
e281682b
SM		 552 u8 grh[0x1];
553 u8 mlid[0x7];
554 u8 rlid[0x10];
555
556 u8 ack_timeout[0x5];
b4ff3a36 557 u8 reserved_at_45[0x3];
e281682b 558 u8 src_addr_index[0x8];
b4ff3a36 559 u8 reserved_at_50[0x4];
e281682b
SM		 560 u8 stat_rate[0x4];
561 u8 hop_limit[0x8];
562
b4ff3a36 563 u8 reserved_at_60[0x4];
e281682b
SM		 564 u8 tclass[0x8];
565 u8 flow_label[0x14];
566
567 u8 rgid_rip[16][0x8];
568
b4ff3a36 569 u8 reserved_at_100[0x4];
e281682b
SM		 570 u8 f_dscp[0x1];
571 u8 f_ecn[0x1];
b4ff3a36 572 u8 reserved_at_106[0x1];
e281682b
SM		 573 u8 f_eth_prio[0x1];
574 u8 ecn[0x2];
575 u8 dscp[0x6];
576 u8 udp_sport[0x10];
577
578 u8 dei_cfi[0x1];
579 u8 eth_prio[0x3];
580 u8 sl[0x4];
32f69e4b 581 u8 vhca_port_num[0x8];
e281682b
SM		 582 u8 rmac_47_32[0x10];
583
584 u8 rmac_31_0[0x20];
585};
586
587struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 588 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 589 u8 nic_rx_multi_path_tirs_fts[0x1];
590 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
bea4e1f6
MB		 591 u8 reserved_at_3[0x1d];
592 u8 encap_general_header[0x1];
593 u8 reserved_at_21[0xa];
594 u8 log_max_packet_reformat_context[0x5];
595 u8 reserved_at_30[0x6];
596 u8 max_encap_header_size[0xa];
597 u8 reserved_at_40[0x1c0];
e281682b
SM		 598
599 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
600
b4ff3a36 601 u8 reserved_at_400[0x200];
e281682b
SM		 602
603 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
604
605 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
606
b4ff3a36 607 u8 reserved_at_a00[0x200];
e281682b
SM		 608
609 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
610
b4ff3a36 611 u8 reserved_at_e00[0x7200];
e281682b
SM		 612};
613
495716b1 614struct mlx5_ifc_flow_table_eswitch_cap_bits {
663f146f 615 u8 reserved_at_0[0x1a];
b9aa0ba1 616 u8 multi_fdb_encap[0x1];
663f146f
VP		 617 u8 reserved_at_1b[0x1];
618 u8 fdb_multi_path_to_table[0x1];
619 u8 reserved_at_1d[0x3];
620
621 u8 reserved_at_20[0x1e0];
495716b1
SM		 622
623 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
624
625 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
626
627 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
628
b4ff3a36 629 u8 reserved_at_800[0x7800];
495716b1
SM		 630};
631
8bb957d2
SK		 632enum {
633 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
634 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
635};
636
d6666753
SM		 637struct mlx5_ifc_e_switch_cap_bits {
638 u8 vport_svlan_strip[0x1];
639 u8 vport_cvlan_strip[0x1];
640 u8 vport_svlan_insert[0x1];
641 u8 vport_cvlan_insert_if_not_exist[0x1];
642 u8 vport_cvlan_insert_overwrite[0x1];
81cd229c
BW		 643 u8 reserved_at_5[0x16];
644 u8 ecpf_vport_exists[0x1];
8bb957d2 645 u8 counter_eswitch_affinity[0x1];
a6d04569 646 u8 merged_eswitch[0x1];
23898c76
NO		 647 u8 nic_vport_node_guid_modify[0x1];
648 u8 nic_vport_port_guid_modify[0x1];
d6666753 649
7adbde20
HHZ		 650 u8 vxlan_encap_decap[0x1];
651 u8 nvgre_encap_decap[0x1];
1b115498
EB		 652 u8 reserved_at_22[0x1];
653 u8 log_max_fdb_encap_uplink[0x5];
654 u8 reserved_at_21[0x3];
60786f09 655 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 656 u8 reserved_2b[0x6];
657 u8 max_encap_header_size[0xa];
658
659 u8 reserved_40[0x7c0];
660
d6666753
SM		 661};
662
7486216b
SM		 663struct mlx5_ifc_qos_cap_bits {
664 u8 packet_pacing[0x1];
813f8540 665 u8 esw_scheduling[0x1];
c9497c98
MHY		 666 u8 esw_bw_share[0x1];
667 u8 esw_rate_limit[0x1];
05d3ac97
BW		 668 u8 reserved_at_4[0x1];
669 u8 packet_pacing_burst_bound[0x1];
670 u8 packet_pacing_typical_size[0x1];
671 u8 reserved_at_7[0x19];
813f8540
MHY		 672
673 u8 reserved_at_20[0x20];
674
7486216b 675 u8 packet_pacing_max_rate[0x20];
813f8540 676
7486216b 677 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 678
679 u8 reserved_at_80[0x10];
7486216b 680 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 681
682 u8 esw_element_type[0x10];
683 u8 esw_tsar_type[0x10];
684
685 u8 reserved_at_c0[0x10];
686 u8 max_qos_para_vport[0x10];
687
688 u8 max_tsar_bw_share[0x20];
689
690 u8 reserved_at_100[0x700];
7486216b
SM		 691};
692
2fcb12df
IK		 693struct mlx5_ifc_debug_cap_bits {
694 u8 reserved_at_0[0x20];
695
696 u8 reserved_at_20[0x2];
697 u8 stall_detect[0x1];
698 u8 reserved_at_23[0x1d];
699
700 u8 reserved_at_40[0x7c0];
701};
702
e281682b
SM		 703struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
704 u8 csum_cap[0x1];
705 u8 vlan_cap[0x1];
706 u8 lro_cap[0x1];
707 u8 lro_psh_flag[0x1];
708 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 709 u8 reserved_at_5[0x2];
710 u8 wqe_vlan_insert[0x1];
66189961 711 u8 self_lb_en_modifiable[0x1];
b4ff3a36 712 u8 reserved_at_9[0x2];
e281682b 713 u8 max_lso_cap[0x5];
c226dc22 714 u8 multi_pkt_send_wqe[0x2];
cff92d7c 715 u8 wqe_inline_mode[0x2];
e281682b 716 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 717 u8 reg_umr_sq[0x1];
718 u8 scatter_fcs[0x1];
050da902 719 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 720 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 721 u8 reserved_at_1c[0x2];
27299841 722 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 723 u8 tunnel_stateless_vxlan[0x1];
724
547eede0
IT		 725 u8 swp[0x1];
726 u8 swp_csum[0x1];
727 u8 swp_lso[0x1];
22a65aa8
GP		 728 u8 reserved_at_23[0xd];
729 u8 max_vxlan_udp_ports[0x8];
730 u8 reserved_at_38[0x6];
4d350f1f
MG		 731 u8 max_geneve_opt_len[0x1];
732 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 733
b4ff3a36 734 u8 reserved_at_40[0x10];
e281682b
SM		 735 u8 lro_min_mss_size[0x10];
736
b4ff3a36 737 u8 reserved_at_60[0x120];
e281682b
SM		 738
739 u8 lro_timer_supported_periods[4][0x20];
740
b4ff3a36 741 u8 reserved_at_200[0x600];
e281682b
SM		 742};
743
744struct mlx5_ifc_roce_cap_bits {
745 u8 roce_apm[0x1];
b4ff3a36 746 u8 reserved_at_1[0x1f];
e281682b 747
b4ff3a36 748 u8 reserved_at_20[0x60];
e281682b 749
b4ff3a36 750 u8 reserved_at_80[0xc];
e281682b 751 u8 l3_type[0x4];
b4ff3a36 752 u8 reserved_at_90[0x8];
e281682b
SM		 753 u8 roce_version[0x8];
754
b4ff3a36 755 u8 reserved_at_a0[0x10];
e281682b
SM		 756 u8 r_roce_dest_udp_port[0x10];
757
758 u8 r_roce_max_src_udp_port[0x10];
759 u8 r_roce_min_src_udp_port[0x10];
760
b4ff3a36 761 u8 reserved_at_e0[0x10];
e281682b
SM		 762 u8 roce_address_table_size[0x10];
763
b4ff3a36 764 u8 reserved_at_100[0x700];
e281682b
SM		 765};
766
e72bd817
AL		 767struct mlx5_ifc_device_mem_cap_bits {
768 u8 memic[0x1];
769 u8 reserved_at_1[0x1f];
770
771 u8 reserved_at_20[0xb];
772 u8 log_min_memic_alloc_size[0x5];
773 u8 reserved_at_30[0x8];
774 u8 log_max_memic_addr_alignment[0x8];
775
776 u8 memic_bar_start_addr[0x40];
777
778 u8 memic_bar_size[0x20];
779
780 u8 max_memic_size[0x20];
781
9fba2b9b
AL		 782 u8 steering_sw_icm_start_address[0x40];
783
784 u8 reserved_at_100[0x8];
785 u8 log_header_modify_sw_icm_size[0x8];
786 u8 reserved_at_110[0x2];
787 u8 log_sw_icm_alloc_granularity[0x6];
788 u8 log_steering_sw_icm_size[0x8];
789
790 u8 reserved_at_120[0x20];
791
792 u8 header_modify_sw_icm_start_address[0x40];
793
794 u8 reserved_at_180[0x680];
e72bd817
AL		 795};
796
e281682b
SM		 797enum {
798 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
799 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
800 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
801 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
802 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
803 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
804 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
805 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
806 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
807};
808
809enum {
810 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
811 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
812 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
813 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
814 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
815 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
816 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
817 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
818 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
819};
820
821struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 822 u8 reserved_at_0[0x40];
e281682b 823
bd10838a 824 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 825 u8 reserved_at_42[0x4];
bd10838a 826 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 827
b4ff3a36 828 u8 reserved_at_47[0x19];
e281682b 829
b4ff3a36 830 u8 reserved_at_60[0x20];
e281682b 831
b4ff3a36 832 u8 reserved_at_80[0x10];
f91e6d89 833 u8 atomic_operations[0x10];
e281682b 834
b4ff3a36 835 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 836 u8 atomic_size_qp[0x10];
837
b4ff3a36 838 u8 reserved_at_c0[0x10];
e281682b
SM		 839 u8 atomic_size_dc[0x10];
840
b4ff3a36 841 u8 reserved_at_e0[0x720];
e281682b
SM		 842};
843
844struct mlx5_ifc_odp_cap_bits {
b4ff3a36 845 u8 reserved_at_0[0x40];
e281682b
SM		 846
847 u8 sig[0x1];
b4ff3a36 848 u8 reserved_at_41[0x1f];
e281682b 849
b4ff3a36 850 u8 reserved_at_60[0x20];
e281682b
SM		 851
852 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
853
854 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
855
856 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
857
dda7a817
MS		 858 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
859
860 u8 reserved_at_100[0x700];
e281682b
SM		 861};
862
3f0393a5
SG		 863struct mlx5_ifc_calc_op {
864 u8 reserved_at_0[0x10];
865 u8 reserved_at_10[0x9];
866 u8 op_swap_endianness[0x1];
867 u8 op_min[0x1];
868 u8 op_xor[0x1];
869 u8 op_or[0x1];
870 u8 op_and[0x1];
871 u8 op_max[0x1];
872 u8 op_add[0x1];
873};
874
875struct mlx5_ifc_vector_calc_cap_bits {
876 u8 calc_matrix[0x1];
877 u8 reserved_at_1[0x1f];
878 u8 reserved_at_20[0x8];
879 u8 max_vec_count[0x8];
880 u8 reserved_at_30[0xd];
881 u8 max_chunk_size[0x3];
882 struct mlx5_ifc_calc_op calc0;
883 struct mlx5_ifc_calc_op calc1;
884 struct mlx5_ifc_calc_op calc2;
885 struct mlx5_ifc_calc_op calc3;
886
c74d90c1 887 u8 reserved_at_c0[0x720];
3f0393a5
SG		 888};
889
e281682b
SM		 890enum {
891 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
892 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 893 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 894 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 895};
896
897enum {
898 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
899 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
900};
901
902enum {
903 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
904 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
905 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
906 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
907 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
908};
909
910enum {
911 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
912 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
913 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
914 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
915 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
916 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
917};
918
919enum {
920 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
921 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
922};
923
924enum {
925 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
926 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
927 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
928};
929
930enum {
931 MLX5_CAP_PORT_TYPE_IB = 0x0,
932 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 933};
934
1410a90a
MG		 935enum {
936 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
937 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
938 MLX5_CAP_UMR_FENCE_NONE = 0x2,
939};
940
9d43faac
YH		 941enum {
942 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 943 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 944};
945
b775516b 946struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 947 u8 reserved_at_0[0x30];
948 u8 vhca_id[0x10];
949
950 u8 reserved_at_40[0x40];
b775516b
EC		 951
952 u8 log_max_srq_sz[0x8];
953 u8 log_max_qp_sz[0x8];
b4ff3a36 954 u8 reserved_at_90[0xb];
b775516b
EC		 955 u8 log_max_qp[0x5];
956
b4ff3a36 957 u8 reserved_at_a0[0xb];
e281682b 958 u8 log_max_srq[0x5];
b4ff3a36 959 u8 reserved_at_b0[0x10];
b775516b 960
b4ff3a36 961 u8 reserved_at_c0[0x8];
b775516b 962 u8 log_max_cq_sz[0x8];
b4ff3a36 963 u8 reserved_at_d0[0xb];
b775516b
EC		 964 u8 log_max_cq[0x5];
965
966 u8 log_max_eq_sz[0x8];
b4ff3a36 967 u8 reserved_at_e8[0x2];
b775516b 968 u8 log_max_mkey[0x6];
b183ee27
LR		 969 u8 reserved_at_f0[0x8];
970 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 971 u8 reserved_at_f9[0x2];
972 u8 fast_teardown[0x1];
b775516b
EC		 973 u8 log_max_eq[0x4];
974
975 u8 max_indirection[0x8];
bcda1aca 976 u8 fixed_buffer_size[0x1];
b775516b 977 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 978 u8 force_teardown[0x1];
979 u8 reserved_at_111[0x1];
b775516b 980 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 981 u8 umr_extended_translation_offset[0x1];
982 u8 null_mkey[0x1];
b775516b
EC		 983 u8 log_max_klm_list_size[0x6];
984
b4ff3a36 985 u8 reserved_at_120[0xa];
b775516b 986 u8 log_max_ra_req_dc[0x6];
b4ff3a36 987 u8 reserved_at_130[0xa];
b775516b
EC		 988 u8 log_max_ra_res_dc[0x6];
989
b4ff3a36 990 u8 reserved_at_140[0xa];
b775516b 991 u8 log_max_ra_req_qp[0x6];
b4ff3a36 992 u8 reserved_at_150[0xa];
b775516b
EC		 993 u8 log_max_ra_res_qp[0x6];
994
f32f5bd2 995 u8 end_pad[0x1];
b775516b
EC		 996 u8 cc_query_allowed[0x1];
997 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 998 u8 start_pad[0x1];
999 u8 cache_line_128byte[0x1];
c02762eb
HN		 1000 u8 reserved_at_165[0xa];
1001 u8 qcam_reg[0x1];
e281682b 1002 u8 gid_table_size[0x10];
b775516b 1003
e281682b
SM		 1004 u8 out_of_seq_cnt[0x1];
1005 u8 vport_counters[0x1];
7486216b 1006 u8 retransmission_q_counters[0x1];
2fcb12df 1007 u8 debug[0x1];
83b502a1 1008 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1009 u8 rq_delay_drop[0x1];
b775516b
EC		 1010 u8 max_qp_cnt[0xa];
1011 u8 pkey_table_size[0x10];
1012
e281682b
SM		 1013 u8 vport_group_manager[0x1];
1014 u8 vhca_group_manager[0x1];
1015 u8 ib_virt[0x1];
1016 u8 eth_virt[0x1];
61c5b5c9 1017 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1018 u8 ets[0x1];
1019 u8 nic_flow_table[0x1];
0efc8562 1020 u8 eswitch_manager[0x1];
e72bd817 1021 u8 device_memory[0x1];
cfdcbcea
GP		 1022 u8 mcam_reg[0x1];
1023 u8 pcam_reg[0x1];
b775516b 1024 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1025 u8 port_module_event[0x1];
58dcb60a 1026 u8 enhanced_error_q_counters[0x1];
7d5e1423 1027 u8 ports_check[0x1];
7b13558f 1028 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1029 u8 disable_link_up[0x1];
1030 u8 beacon_led[0x1];
e281682b 1031 u8 port_type[0x2];
b775516b
EC		 1032 u8 num_ports[0x8];
1033
f9a1ef72
EE		 1034 u8 reserved_at_1c0[0x1];
1035 u8 pps[0x1];
1036 u8 pps_modify[0x1];
b775516b 1037 u8 log_max_msg[0x5];
e1c9c62b 1038 u8 reserved_at_1c8[0x4];
4f3961ee 1039 u8 max_tc[0x4];
1865ea9a 1040 u8 temp_warn_event[0x1];
7486216b 1041 u8 dcbx[0x1];
246ac981
MG		 1042 u8 general_notification_event[0x1];
1043 u8 reserved_at_1d3[0x2];
e29341fb 1044 u8 fpga[0x1];
928cfe87
TT		 1045 u8 rol_s[0x1];
1046 u8 rol_g[0x1];
e1c9c62b 1047 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1048 u8 wol_s[0x1];
1049 u8 wol_g[0x1];
1050 u8 wol_a[0x1];
1051 u8 wol_b[0x1];
1052 u8 wol_m[0x1];
1053 u8 wol_u[0x1];
1054 u8 wol_p[0x1];
b775516b
EC		 1055
1056 u8 stat_rate_support[0x10];
e1c9c62b 1057 u8 reserved_at_1f0[0xc];
e281682b 1058 u8 cqe_version[0x4];
b775516b 1059
e281682b 1060 u8 compact_address_vector[0x1];
7d5e1423 1061 u8 striding_rq[0x1];
500a3d0d
ES		 1062 u8 reserved_at_202[0x1];
1063 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1064 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1065 u8 reserved_at_205[0x1];
1066 u8 repeated_block_disabled[0x1];
1067 u8 umr_modify_entity_size_disabled[0x1];
1068 u8 umr_modify_atomic_disabled[0x1];
1069 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1070 u8 umr_fence[0x2];
94a04d1d
YC		 1071 u8 dc_req_scat_data_cqe[0x1];
1072 u8 reserved_at_20d[0x2];
e281682b 1073 u8 drain_sigerr[0x1];
b775516b
EC		 1074 u8 cmdif_checksum[0x2];
1075 u8 sigerr_cqe[0x1];
e1c9c62b 1076 u8 reserved_at_213[0x1];
b775516b
EC		 1077 u8 wq_signature[0x1];
1078 u8 sctr_data_cqe[0x1];
e1c9c62b 1079 u8 reserved_at_216[0x1];
b775516b
EC		 1080 u8 sho[0x1];
1081 u8 tph[0x1];
1082 u8 rf[0x1];
e281682b 1083 u8 dct[0x1];
7486216b 1084 u8 qos[0x1];
e281682b 1085 u8 eth_net_offloads[0x1];
b775516b
EC		 1086 u8 roce[0x1];
1087 u8 atomic[0x1];
e1c9c62b 1088 u8 reserved_at_21f[0x1];
b775516b
EC		 1089
1090 u8 cq_oi[0x1];
1091 u8 cq_resize[0x1];
1092 u8 cq_moderation[0x1];
e1c9c62b 1093 u8 reserved_at_223[0x3];
e281682b 1094 u8 cq_eq_remap[0x1];
b775516b
EC		 1095 u8 pg[0x1];
1096 u8 block_lb_mc[0x1];
e1c9c62b 1097 u8 reserved_at_229[0x1];
e281682b 1098 u8 scqe_break_moderation[0x1];
7d5e1423 1099 u8 cq_period_start_from_cqe[0x1];
b775516b 1100 u8 cd[0x1];
e1c9c62b 1101 u8 reserved_at_22d[0x1];
b775516b 1102 u8 apm[0x1];
3f0393a5 1103 u8 vector_calc[0x1];
7d5e1423 1104 u8 umr_ptr_rlky[0x1];
d2370e0a 1105 u8 imaicl[0x1];
3fd3c80a
DG		 1106 u8 qp_packet_based[0x1];
1107 u8 reserved_at_233[0x3];
b775516b
EC		 1108 u8 qkv[0x1];
1109 u8 pkv[0x1];
b11a4f9c
HE		 1110 u8 set_deth_sqpn[0x1];
1111 u8 reserved_at_239[0x3];
b775516b
EC		 1112 u8 xrc[0x1];
1113 u8 ud[0x1];
1114 u8 uc[0x1];
1115 u8 rc[0x1];
1116
a6d51b68
EC		 1117 u8 uar_4k[0x1];
1118 u8 reserved_at_241[0x9];
b775516b 1119 u8 uar_sz[0x6];
e1c9c62b 1120 u8 reserved_at_250[0x8];
b775516b
EC		 1121 u8 log_pg_sz[0x8];
1122
1123 u8 bf[0x1];
0dbc6fe0 1124 u8 driver_version[0x1];
e281682b 1125 u8 pad_tx_eth_packet[0x1];
e1c9c62b 1126 u8 reserved_at_263[0x8];
b775516b 1127 u8 log_bf_reg_size[0x5];
84df61eb
AH		 1128
1129 u8 reserved_at_270[0xb];
1130 u8 lag_master[0x1];
1131 u8 num_lag_ports[0x4];
b775516b 1132
e1c9c62b 1133 u8 reserved_at_280[0x10];
b775516b
EC		 1134 u8 max_wqe_sz_sq[0x10];
1135
e1c9c62b 1136 u8 reserved_at_2a0[0x10];
b775516b
EC		 1137 u8 max_wqe_sz_rq[0x10];
1138
a8ffcc74 1139 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1140 u8 max_wqe_sz_sq_dc[0x10];
1141
e1c9c62b 1142 u8 reserved_at_2e0[0x7];
b775516b
EC		 1143 u8 max_qp_mcg[0x19];
1144
e1c9c62b 1145 u8 reserved_at_300[0x18];
b775516b
EC		 1146 u8 log_max_mcg[0x8];
1147
e1c9c62b 1148 u8 reserved_at_320[0x3];
e281682b 1149 u8 log_max_transport_domain[0x5];
e1c9c62b 1150 u8 reserved_at_328[0x3];
b775516b 1151 u8 log_max_pd[0x5];
e1c9c62b 1152 u8 reserved_at_330[0xb];
b775516b
EC		 1153 u8 log_max_xrcd[0x5];
1154
5c298143 1155 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1156 u8 receive_discard_vport_down[0x1];
1157 u8 transmit_discard_vport_down[0x1];
1158 u8 reserved_at_343[0x5];
a351a1b0 1159 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1160 u8 max_flow_counter_15_0[0x10];
a351a1b0 1161
b775516b 1162
e1c9c62b 1163 u8 reserved_at_360[0x3];
b775516b 1164 u8 log_max_rq[0x5];
e1c9c62b 1165 u8 reserved_at_368[0x3];
b775516b 1166 u8 log_max_sq[0x5];
e1c9c62b 1167 u8 reserved_at_370[0x3];
b775516b 1168 u8 log_max_tir[0x5];
e1c9c62b 1169 u8 reserved_at_378[0x3];
b775516b
EC		 1170 u8 log_max_tis[0x5];
1171
e281682b 1172 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1173 u8 reserved_at_381[0x2];
e281682b 1174 u8 log_max_rmp[0x5];
e1c9c62b 1175 u8 reserved_at_388[0x3];
e281682b 1176 u8 log_max_rqt[0x5];
e1c9c62b 1177 u8 reserved_at_390[0x3];
e281682b 1178 u8 log_max_rqt_size[0x5];
e1c9c62b 1179 u8 reserved_at_398[0x3];
b775516b
EC		 1180 u8 log_max_tis_per_sq[0x5];
1181
619a8f2a
TT		 1182 u8 ext_stride_num_range[0x1];
1183 u8 reserved_at_3a1[0x2];
e281682b 1184 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1185 u8 reserved_at_3a8[0x3];
e281682b 1186 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1187 u8 reserved_at_3b0[0x3];
e281682b 1188 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1189 u8 reserved_at_3b8[0x3];
e281682b
SM		 1190 u8 log_min_stride_sz_sq[0x5];
1191
40817cdb
OG		 1192 u8 hairpin[0x1];
1193 u8 reserved_at_3c1[0x2];
1194 u8 log_max_hairpin_queues[0x5];
1195 u8 reserved_at_3c8[0x3];
1196 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1197 u8 reserved_at_3d0[0x3];
1198 u8 log_max_hairpin_num_packets[0x5];
1199 u8 reserved_at_3d8[0x3];
e281682b
SM		 1200 u8 log_max_wq_sz[0x5];
1201
54f0a411 1202 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1203 u8 disable_local_lb_uc[0x1];
1204 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1205 u8 log_min_hairpin_wq_data_sz[0x5];
1206 u8 reserved_at_3e8[0x3];
54f0a411 1207 u8 log_max_vlan_list[0x5];
e1c9c62b 1208 u8 reserved_at_3f0[0x3];
54f0a411 1209 u8 log_max_current_mc_list[0x5];
e1c9c62b 1210 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1211 u8 log_max_current_uc_list[0x5];
1212
38b7ca92
YH		 1213 u8 general_obj_types[0x40];
1214
342ac844
DD		 1215 u8 reserved_at_440[0x20];
1216
6e3722ba
YH		 1217 u8 reserved_at_460[0x3];
1218 u8 log_max_uctx[0x5];
1219 u8 reserved_at_468[0x3];
1220 u8 log_max_umem[0x5];
342ac844 1221 u8 max_num_eqs[0x10];
54f0a411 1222
e1c9c62b 1223 u8 reserved_at_480[0x3];
e281682b 1224 u8 log_max_l2_table[0x5];
e1c9c62b 1225 u8 reserved_at_488[0x8];
b775516b
EC		 1226 u8 log_uar_page_sz[0x10];
1227
e1c9c62b 1228 u8 reserved_at_4a0[0x20];
048ccca8 1229 u8 device_frequency_mhz[0x20];
b0844444 1230 u8 device_frequency_khz[0x20];
e1c9c62b 1231
a6d51b68
EC		 1232 u8 reserved_at_500[0x20];
1233 u8 num_of_uars_per_page[0x20];
e1c9c62b 1234
e818e255
AL		 1235 u8 flex_parser_protocols[0x20];
1236 u8 reserved_at_560[0x20];
e1c9c62b 1237
ab741b2e
YC		 1238 u8 reserved_at_580[0x3c];
1239 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1240 u8 cqe_128_always[0x1];
1241 u8 cqe_compression_128[0x1];
7d5e1423 1242 u8 cqe_compression[0x1];
b775516b 1243
7d5e1423
SM		 1244 u8 cqe_compression_timeout[0x10];
1245 u8 cqe_compression_max_num[0x10];
b775516b 1246
7486216b
SM		 1247 u8 reserved_at_5e0[0x10];
1248 u8 tag_matching[0x1];
1249 u8 rndv_offload_rc[0x1];
1250 u8 rndv_offload_dc[0x1];
1251 u8 log_tag_matching_list_sz[0x5];
7b13558f 1252 u8 reserved_at_5f8[0x3];
7486216b
SM		 1253 u8 log_max_xrq[0x5];
1254
32f69e4b
DJ		 1255 u8 affiliate_nic_vport_criteria[0x8];
1256 u8 native_port_num[0x8];
1257 u8 num_vhca_ports[0x8];
1258 u8 reserved_at_618[0x6];
1259 u8 sw_owner_id[0x1];
9d43faac
YH		 1260 u8 reserved_at_61f[0x1];
1261
fd4572b3
ED		 1262 u8 max_num_of_monitor_counters[0x10];
1263 u8 num_ppcnt_monitor_counters[0x10];
1264
1265 u8 reserved_at_640[0x10];
1266 u8 num_q_monitor_counters[0x10];
1267
1268 u8 reserved_at_660[0x40];
9d43faac
YH		 1269
1270 u8 uctx_cap[0x20];
1271
1272 u8 reserved_at_6c0[0x140];
b775516b
EC		 1273};
1274
81848731
SM		 1275enum mlx5_flow_destination_type {
1276 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1277 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1278 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1279
5f418378 1280 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1281 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
664000b6 1282 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
e281682b 1283};
b775516b 1284
e281682b
SM		 1285struct mlx5_ifc_dest_format_struct_bits {
1286 u8 destination_type[0x8];
1287 u8 destination_id[0x18];
1b115498 1288
b17f7fc1 1289 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1290 u8 packet_reformat[0x1];
1291 u8 reserved_at_22[0xe];
b17f7fc1 1292 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1293};
1294
9dc0b289 1295struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1296 u8 flow_counter_id[0x20];
9dc0b289
AV		 1297
1298 u8 reserved_at_20[0x20];
1299};
1300
1b115498
EB		 1301struct mlx5_ifc_extended_dest_format_bits {
1302 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1303
1304 u8 packet_reformat_id[0x20];
1305
1306 u8 reserved_at_60[0x20];
1307};
1308
9dc0b289
AV		 1309union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1310 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1311 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1312 u8 reserved_at_0[0x40];
1313};
1314
e281682b
SM		 1315struct mlx5_ifc_fte_match_param_bits {
1316 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1317
1318 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1319
1320 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1321
71c6e863
AL		 1322 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1323
1324 u8 reserved_at_800[0x800];
b775516b
EC		 1325};
1326
e281682b
SM		 1327enum {
1328 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1329 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1330 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1331 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1332 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1333};
b775516b 1334
e281682b
SM		 1335struct mlx5_ifc_rx_hash_field_select_bits {
1336 u8 l3_prot_type[0x1];
1337 u8 l4_prot_type[0x1];
1338 u8 selected_fields[0x1e];
1339};
b775516b 1340
e281682b
SM		 1341enum {
1342 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1343 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1344};
1345
e281682b
SM		 1346enum {
1347 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1348 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1349};
1350
1351struct mlx5_ifc_wq_bits {
1352 u8 wq_type[0x4];
1353 u8 wq_signature[0x1];
1354 u8 end_padding_mode[0x2];
1355 u8 cd_slave[0x1];
b4ff3a36 1356 u8 reserved_at_8[0x18];
b775516b 1357
e281682b
SM		 1358 u8 hds_skip_first_sge[0x1];
1359 u8 log2_hds_buf_size[0x3];
b4ff3a36 1360 u8 reserved_at_24[0x7];
e281682b
SM		 1361 u8 page_offset[0x5];
1362 u8 lwm[0x10];
b775516b 1363
b4ff3a36 1364 u8 reserved_at_40[0x8];
e281682b
SM		 1365 u8 pd[0x18];
1366
b4ff3a36 1367 u8 reserved_at_60[0x8];
e281682b
SM		 1368 u8 uar_page[0x18];
1369
1370 u8 dbr_addr[0x40];
1371
1372 u8 hw_counter[0x20];
1373
1374 u8 sw_counter[0x20];
1375
b4ff3a36 1376 u8 reserved_at_100[0xc];
e281682b 1377 u8 log_wq_stride[0x4];
b4ff3a36 1378 u8 reserved_at_110[0x3];
e281682b 1379 u8 log_wq_pg_sz[0x5];
b4ff3a36 1380 u8 reserved_at_118[0x3];
e281682b
SM		 1381 u8 log_wq_sz[0x5];
1382
bd371975
LR		 1383 u8 dbr_umem_valid[0x1];
1384 u8 wq_umem_valid[0x1];
1385 u8 reserved_at_122[0x1];
4d533e0f
OG		 1386 u8 log_hairpin_num_packets[0x5];
1387 u8 reserved_at_128[0x3];
40817cdb 1388 u8 log_hairpin_data_sz[0x5];
40817cdb 1389
619a8f2a
TT		 1390 u8 reserved_at_130[0x4];
1391 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1392 u8 two_byte_shift_en[0x1];
1393 u8 reserved_at_139[0x4];
1394 u8 log_wqe_stride_size[0x3];
1395
1396 u8 reserved_at_140[0x4c0];
b775516b 1397
e281682b 1398 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1399};
1400
e281682b 1401struct mlx5_ifc_rq_num_bits {
b4ff3a36 1402 u8 reserved_at_0[0x8];
e281682b
SM		 1403 u8 rq_num[0x18];
1404};
b775516b 1405
e281682b 1406struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1407 u8 reserved_at_0[0x10];
e281682b 1408 u8 mac_addr_47_32[0x10];
b775516b 1409
e281682b
SM		 1410 u8 mac_addr_31_0[0x20];
1411};
1412
c0046cf7 1413struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1414 u8 reserved_at_0[0x14];
c0046cf7
SM		 1415 u8 vlan[0x0c];
1416
b4ff3a36 1417 u8 reserved_at_20[0x20];
c0046cf7
SM		 1418};
1419
e281682b 1420struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1421 u8 reserved_at_0[0xa0];
e281682b
SM		 1422
1423 u8 min_time_between_cnps[0x20];
1424
b4ff3a36 1425 u8 reserved_at_c0[0x12];
e281682b 1426 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1427 u8 reserved_at_d8[0x4];
1428 u8 cnp_prio_mode[0x1];
e281682b
SM		 1429 u8 cnp_802p_prio[0x3];
1430
b4ff3a36 1431 u8 reserved_at_e0[0x720];
e281682b
SM		 1432};
1433
1434struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1435 u8 reserved_at_0[0x60];
e281682b 1436
b4ff3a36 1437 u8 reserved_at_60[0x4];
e281682b 1438 u8 clamp_tgt_rate[0x1];
b4ff3a36 1439 u8 reserved_at_65[0x3];
e281682b 1440 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1441 u8 reserved_at_69[0x17];
e281682b 1442
b4ff3a36 1443 u8 reserved_at_80[0x20];
e281682b
SM		 1444
1445 u8 rpg_time_reset[0x20];
1446
1447 u8 rpg_byte_reset[0x20];
1448
1449 u8 rpg_threshold[0x20];
1450
1451 u8 rpg_max_rate[0x20];
1452
1453 u8 rpg_ai_rate[0x20];
1454
1455 u8 rpg_hai_rate[0x20];
1456
1457 u8 rpg_gd[0x20];
1458
1459 u8 rpg_min_dec_fac[0x20];
1460
1461 u8 rpg_min_rate[0x20];
1462
b4ff3a36 1463 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1464
1465 u8 rate_to_set_on_first_cnp[0x20];
1466
1467 u8 dce_tcp_g[0x20];
1468
1469 u8 dce_tcp_rtt[0x20];
1470
1471 u8 rate_reduce_monitor_period[0x20];
1472
b4ff3a36 1473 u8 reserved_at_320[0x20];
e281682b
SM		 1474
1475 u8 initial_alpha_value[0x20];
1476
b4ff3a36 1477 u8 reserved_at_360[0x4a0];
e281682b
SM		 1478};
1479
1480struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1481 u8 reserved_at_0[0x80];
e281682b
SM		 1482
1483 u8 rppp_max_rps[0x20];
1484
1485 u8 rpg_time_reset[0x20];
1486
1487 u8 rpg_byte_reset[0x20];
1488
1489 u8 rpg_threshold[0x20];
1490
1491 u8 rpg_max_rate[0x20];
1492
1493 u8 rpg_ai_rate[0x20];
1494
1495 u8 rpg_hai_rate[0x20];
1496
1497 u8 rpg_gd[0x20];
1498
1499 u8 rpg_min_dec_fac[0x20];
1500
1501 u8 rpg_min_rate[0x20];
1502
b4ff3a36 1503 u8 reserved_at_1c0[0x640];
e281682b
SM		 1504};
1505
1506enum {
1507 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1508 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1509 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1510};
1511
1512struct mlx5_ifc_resize_field_select_bits {
1513 u8 resize_field_select[0x20];
1514};
1515
1516enum {
1517 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1518 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1519 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1520 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1521};
1522
1523struct mlx5_ifc_modify_field_select_bits {
1524 u8 modify_field_select[0x20];
1525};
1526
1527struct mlx5_ifc_field_select_r_roce_np_bits {
1528 u8 field_select_r_roce_np[0x20];
1529};
1530
1531struct mlx5_ifc_field_select_r_roce_rp_bits {
1532 u8 field_select_r_roce_rp[0x20];
1533};
1534
1535enum {
1536 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1537 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1538 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1539 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1540 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1541 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1542 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1543 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1544 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1545 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1546};
1547
1548struct mlx5_ifc_field_select_802_1qau_rp_bits {
1549 u8 field_select_8021qaurp[0x20];
1550};
1551
1552struct mlx5_ifc_phys_layer_cntrs_bits {
1553 u8 time_since_last_clear_high[0x20];
1554
1555 u8 time_since_last_clear_low[0x20];
1556
1557 u8 symbol_errors_high[0x20];
1558
1559 u8 symbol_errors_low[0x20];
1560
1561 u8 sync_headers_errors_high[0x20];
1562
1563 u8 sync_headers_errors_low[0x20];
1564
1565 u8 edpl_bip_errors_lane0_high[0x20];
1566
1567 u8 edpl_bip_errors_lane0_low[0x20];
1568
1569 u8 edpl_bip_errors_lane1_high[0x20];
1570
1571 u8 edpl_bip_errors_lane1_low[0x20];
1572
1573 u8 edpl_bip_errors_lane2_high[0x20];
1574
1575 u8 edpl_bip_errors_lane2_low[0x20];
1576
1577 u8 edpl_bip_errors_lane3_high[0x20];
1578
1579 u8 edpl_bip_errors_lane3_low[0x20];
1580
1581 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1582
1583 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1584
1585 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1586
1587 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1588
1589 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1590
1591 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1592
1593 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1594
1595 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1596
1597 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1598
1599 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1600
1601 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1602
1603 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1604
1605 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1606
1607 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1608
1609 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1610
1611 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1612
1613 u8 rs_fec_corrected_blocks_high[0x20];
1614
1615 u8 rs_fec_corrected_blocks_low[0x20];
1616
1617 u8 rs_fec_uncorrectable_blocks_high[0x20];
1618
1619 u8 rs_fec_uncorrectable_blocks_low[0x20];
1620
1621 u8 rs_fec_no_errors_blocks_high[0x20];
1622
1623 u8 rs_fec_no_errors_blocks_low[0x20];
1624
1625 u8 rs_fec_single_error_blocks_high[0x20];
1626
1627 u8 rs_fec_single_error_blocks_low[0x20];
1628
1629 u8 rs_fec_corrected_symbols_total_high[0x20];
1630
1631 u8 rs_fec_corrected_symbols_total_low[0x20];
1632
1633 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1634
1635 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1636
1637 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1638
1639 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1640
1641 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1642
1643 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1644
1645 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1646
1647 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1648
1649 u8 link_down_events[0x20];
1650
1651 u8 successful_recovery_events[0x20];
1652
b4ff3a36 1653 u8 reserved_at_640[0x180];
e281682b
SM		 1654};
1655
d8dc0508
GP		 1656struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1657 u8 time_since_last_clear_high[0x20];
1658
1659 u8 time_since_last_clear_low[0x20];
1660
1661 u8 phy_received_bits_high[0x20];
1662
1663 u8 phy_received_bits_low[0x20];
1664
1665 u8 phy_symbol_errors_high[0x20];
1666
1667 u8 phy_symbol_errors_low[0x20];
1668
1669 u8 phy_corrected_bits_high[0x20];
1670
1671 u8 phy_corrected_bits_low[0x20];
1672
1673 u8 phy_corrected_bits_lane0_high[0x20];
1674
1675 u8 phy_corrected_bits_lane0_low[0x20];
1676
1677 u8 phy_corrected_bits_lane1_high[0x20];
1678
1679 u8 phy_corrected_bits_lane1_low[0x20];
1680
1681 u8 phy_corrected_bits_lane2_high[0x20];
1682
1683 u8 phy_corrected_bits_lane2_low[0x20];
1684
1685 u8 phy_corrected_bits_lane3_high[0x20];
1686
1687 u8 phy_corrected_bits_lane3_low[0x20];
1688
1689 u8 reserved_at_200[0x5c0];
1690};
1691
1c64bf6f
MY		 1692struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1693 u8 symbol_error_counter[0x10];
1694
1695 u8 link_error_recovery_counter[0x8];
1696
1697 u8 link_downed_counter[0x8];
1698
1699 u8 port_rcv_errors[0x10];
1700
1701 u8 port_rcv_remote_physical_errors[0x10];
1702
1703 u8 port_rcv_switch_relay_errors[0x10];
1704
1705 u8 port_xmit_discards[0x10];
1706
1707 u8 port_xmit_constraint_errors[0x8];
1708
1709 u8 port_rcv_constraint_errors[0x8];
1710
1711 u8 reserved_at_70[0x8];
1712
1713 u8 link_overrun_errors[0x8];
1714
1715 u8 reserved_at_80[0x10];
1716
1717 u8 vl_15_dropped[0x10];
1718
133bea04
TW		 1719 u8 reserved_at_a0[0x80];
1720
1721 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1722};
1723
e281682b
SM		 1724struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1725 u8 transmit_queue_high[0x20];
1726
1727 u8 transmit_queue_low[0x20];
1728
b4ff3a36 1729 u8 reserved_at_40[0x780];
e281682b
SM		 1730};
1731
1732struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1733 u8 rx_octets_high[0x20];
1734
1735 u8 rx_octets_low[0x20];
1736
b4ff3a36 1737 u8 reserved_at_40[0xc0];
e281682b
SM		 1738
1739 u8 rx_frames_high[0x20];
1740
1741 u8 rx_frames_low[0x20];
1742
1743 u8 tx_octets_high[0x20];
1744
1745 u8 tx_octets_low[0x20];
1746
b4ff3a36 1747 u8 reserved_at_180[0xc0];
e281682b
SM		 1748
1749 u8 tx_frames_high[0x20];
1750
1751 u8 tx_frames_low[0x20];
1752
1753 u8 rx_pause_high[0x20];
1754
1755 u8 rx_pause_low[0x20];
1756
1757 u8 rx_pause_duration_high[0x20];
1758
1759 u8 rx_pause_duration_low[0x20];
1760
1761 u8 tx_pause_high[0x20];
1762
1763 u8 tx_pause_low[0x20];
1764
1765 u8 tx_pause_duration_high[0x20];
1766
1767 u8 tx_pause_duration_low[0x20];
1768
1769 u8 rx_pause_transition_high[0x20];
1770
1771 u8 rx_pause_transition_low[0x20];
1772
2fcb12df
IK		 1773 u8 reserved_at_3c0[0x40];
1774
1775 u8 device_stall_minor_watermark_cnt_high[0x20];
1776
1777 u8 device_stall_minor_watermark_cnt_low[0x20];
1778
1779 u8 device_stall_critical_watermark_cnt_high[0x20];
1780
1781 u8 device_stall_critical_watermark_cnt_low[0x20];
1782
1783 u8 reserved_at_480[0x340];
e281682b
SM		 1784};
1785
1786struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1787 u8 port_transmit_wait_high[0x20];
1788
1789 u8 port_transmit_wait_low[0x20];
1790
2dba0797
GP		 1791 u8 reserved_at_40[0x100];
1792
1793 u8 rx_buffer_almost_full_high[0x20];
1794
1795 u8 rx_buffer_almost_full_low[0x20];
1796
1797 u8 rx_buffer_full_high[0x20];
1798
1799 u8 rx_buffer_full_low[0x20];
1800
0af5107c
TB		 1801 u8 rx_icrc_encapsulated_high[0x20];
1802
1803 u8 rx_icrc_encapsulated_low[0x20];
1804
1805 u8 reserved_at_200[0x5c0];
e281682b
SM		 1806};
1807
1808struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1809 u8 dot3stats_alignment_errors_high[0x20];
1810
1811 u8 dot3stats_alignment_errors_low[0x20];
1812
1813 u8 dot3stats_fcs_errors_high[0x20];
1814
1815 u8 dot3stats_fcs_errors_low[0x20];
1816
1817 u8 dot3stats_single_collision_frames_high[0x20];
1818
1819 u8 dot3stats_single_collision_frames_low[0x20];
1820
1821 u8 dot3stats_multiple_collision_frames_high[0x20];
1822
1823 u8 dot3stats_multiple_collision_frames_low[0x20];
1824
1825 u8 dot3stats_sqe_test_errors_high[0x20];
1826
1827 u8 dot3stats_sqe_test_errors_low[0x20];
1828
1829 u8 dot3stats_deferred_transmissions_high[0x20];
1830
1831 u8 dot3stats_deferred_transmissions_low[0x20];
1832
1833 u8 dot3stats_late_collisions_high[0x20];
1834
1835 u8 dot3stats_late_collisions_low[0x20];
1836
1837 u8 dot3stats_excessive_collisions_high[0x20];
1838
1839 u8 dot3stats_excessive_collisions_low[0x20];
1840
1841 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1842
1843 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1844
1845 u8 dot3stats_carrier_sense_errors_high[0x20];
1846
1847 u8 dot3stats_carrier_sense_errors_low[0x20];
1848
1849 u8 dot3stats_frame_too_longs_high[0x20];
1850
1851 u8 dot3stats_frame_too_longs_low[0x20];
1852
1853 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1854
1855 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1856
1857 u8 dot3stats_symbol_errors_high[0x20];
1858
1859 u8 dot3stats_symbol_errors_low[0x20];
1860
1861 u8 dot3control_in_unknown_opcodes_high[0x20];
1862
1863 u8 dot3control_in_unknown_opcodes_low[0x20];
1864
1865 u8 dot3in_pause_frames_high[0x20];
1866
1867 u8 dot3in_pause_frames_low[0x20];
1868
1869 u8 dot3out_pause_frames_high[0x20];
1870
1871 u8 dot3out_pause_frames_low[0x20];
1872
b4ff3a36 1873 u8 reserved_at_400[0x3c0];
e281682b
SM		 1874};
1875
1876struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1877 u8 ether_stats_drop_events_high[0x20];
1878
1879 u8 ether_stats_drop_events_low[0x20];
1880
1881 u8 ether_stats_octets_high[0x20];
1882
1883 u8 ether_stats_octets_low[0x20];
1884
1885 u8 ether_stats_pkts_high[0x20];
1886
1887 u8 ether_stats_pkts_low[0x20];
1888
1889 u8 ether_stats_broadcast_pkts_high[0x20];
1890
1891 u8 ether_stats_broadcast_pkts_low[0x20];
1892
1893 u8 ether_stats_multicast_pkts_high[0x20];
1894
1895 u8 ether_stats_multicast_pkts_low[0x20];
1896
1897 u8 ether_stats_crc_align_errors_high[0x20];
1898
1899 u8 ether_stats_crc_align_errors_low[0x20];
1900
1901 u8 ether_stats_undersize_pkts_high[0x20];
1902
1903 u8 ether_stats_undersize_pkts_low[0x20];
1904
1905 u8 ether_stats_oversize_pkts_high[0x20];
1906
1907 u8 ether_stats_oversize_pkts_low[0x20];
1908
1909 u8 ether_stats_fragments_high[0x20];
1910
1911 u8 ether_stats_fragments_low[0x20];
1912
1913 u8 ether_stats_jabbers_high[0x20];
1914
1915 u8 ether_stats_jabbers_low[0x20];
1916
1917 u8 ether_stats_collisions_high[0x20];
1918
1919 u8 ether_stats_collisions_low[0x20];
1920
1921 u8 ether_stats_pkts64octets_high[0x20];
1922
1923 u8 ether_stats_pkts64octets_low[0x20];
1924
1925 u8 ether_stats_pkts65to127octets_high[0x20];
1926
1927 u8 ether_stats_pkts65to127octets_low[0x20];
1928
1929 u8 ether_stats_pkts128to255octets_high[0x20];
1930
1931 u8 ether_stats_pkts128to255octets_low[0x20];
1932
1933 u8 ether_stats_pkts256to511octets_high[0x20];
1934
1935 u8 ether_stats_pkts256to511octets_low[0x20];
1936
1937 u8 ether_stats_pkts512to1023octets_high[0x20];
1938
1939 u8 ether_stats_pkts512to1023octets_low[0x20];
1940
1941 u8 ether_stats_pkts1024to1518octets_high[0x20];
1942
1943 u8 ether_stats_pkts1024to1518octets_low[0x20];
1944
1945 u8 ether_stats_pkts1519to2047octets_high[0x20];
1946
1947 u8 ether_stats_pkts1519to2047octets_low[0x20];
1948
1949 u8 ether_stats_pkts2048to4095octets_high[0x20];
1950
1951 u8 ether_stats_pkts2048to4095octets_low[0x20];
1952
1953 u8 ether_stats_pkts4096to8191octets_high[0x20];
1954
1955 u8 ether_stats_pkts4096to8191octets_low[0x20];
1956
1957 u8 ether_stats_pkts8192to10239octets_high[0x20];
1958
1959 u8 ether_stats_pkts8192to10239octets_low[0x20];
1960
b4ff3a36 1961 u8 reserved_at_540[0x280];
e281682b
SM		 1962};
1963
1964struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1965 u8 if_in_octets_high[0x20];
1966
1967 u8 if_in_octets_low[0x20];
1968
1969 u8 if_in_ucast_pkts_high[0x20];
1970
1971 u8 if_in_ucast_pkts_low[0x20];
1972
1973 u8 if_in_discards_high[0x20];
1974
1975 u8 if_in_discards_low[0x20];
1976
1977 u8 if_in_errors_high[0x20];
1978
1979 u8 if_in_errors_low[0x20];
1980
1981 u8 if_in_unknown_protos_high[0x20];
1982
1983 u8 if_in_unknown_protos_low[0x20];
1984
1985 u8 if_out_octets_high[0x20];
1986
1987 u8 if_out_octets_low[0x20];
1988
1989 u8 if_out_ucast_pkts_high[0x20];
1990
1991 u8 if_out_ucast_pkts_low[0x20];
1992
1993 u8 if_out_discards_high[0x20];
1994
1995 u8 if_out_discards_low[0x20];
1996
1997 u8 if_out_errors_high[0x20];
1998
1999 u8 if_out_errors_low[0x20];
2000
2001 u8 if_in_multicast_pkts_high[0x20];
2002
2003 u8 if_in_multicast_pkts_low[0x20];
2004
2005 u8 if_in_broadcast_pkts_high[0x20];
2006
2007 u8 if_in_broadcast_pkts_low[0x20];
2008
2009 u8 if_out_multicast_pkts_high[0x20];
2010
2011 u8 if_out_multicast_pkts_low[0x20];
2012
2013 u8 if_out_broadcast_pkts_high[0x20];
2014
2015 u8 if_out_broadcast_pkts_low[0x20];
2016
b4ff3a36 2017 u8 reserved_at_340[0x480];
e281682b
SM		 2018};
2019
2020struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2021 u8 a_frames_transmitted_ok_high[0x20];
2022
2023 u8 a_frames_transmitted_ok_low[0x20];
2024
2025 u8 a_frames_received_ok_high[0x20];
2026
2027 u8 a_frames_received_ok_low[0x20];
2028
2029 u8 a_frame_check_sequence_errors_high[0x20];
2030
2031 u8 a_frame_check_sequence_errors_low[0x20];
2032
2033 u8 a_alignment_errors_high[0x20];
2034
2035 u8 a_alignment_errors_low[0x20];
2036
2037 u8 a_octets_transmitted_ok_high[0x20];
2038
2039 u8 a_octets_transmitted_ok_low[0x20];
2040
2041 u8 a_octets_received_ok_high[0x20];
2042
2043 u8 a_octets_received_ok_low[0x20];
2044
2045 u8 a_multicast_frames_xmitted_ok_high[0x20];
2046
2047 u8 a_multicast_frames_xmitted_ok_low[0x20];
2048
2049 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2050
2051 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2052
2053 u8 a_multicast_frames_received_ok_high[0x20];
2054
2055 u8 a_multicast_frames_received_ok_low[0x20];
2056
2057 u8 a_broadcast_frames_received_ok_high[0x20];
2058
2059 u8 a_broadcast_frames_received_ok_low[0x20];
2060
2061 u8 a_in_range_length_errors_high[0x20];
2062
2063 u8 a_in_range_length_errors_low[0x20];
2064
2065 u8 a_out_of_range_length_field_high[0x20];
2066
2067 u8 a_out_of_range_length_field_low[0x20];
2068
2069 u8 a_frame_too_long_errors_high[0x20];
2070
2071 u8 a_frame_too_long_errors_low[0x20];
2072
2073 u8 a_symbol_error_during_carrier_high[0x20];
2074
2075 u8 a_symbol_error_during_carrier_low[0x20];
2076
2077 u8 a_mac_control_frames_transmitted_high[0x20];
2078
2079 u8 a_mac_control_frames_transmitted_low[0x20];
2080
2081 u8 a_mac_control_frames_received_high[0x20];
2082
2083 u8 a_mac_control_frames_received_low[0x20];
2084
2085 u8 a_unsupported_opcodes_received_high[0x20];
2086
2087 u8 a_unsupported_opcodes_received_low[0x20];
2088
2089 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2090
2091 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2092
2093 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2094
2095 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2096
b4ff3a36 2097 u8 reserved_at_4c0[0x300];
e281682b
SM		 2098};
2099
8ed1a630
GP		 2100struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2101 u8 life_time_counter_high[0x20];
2102
2103 u8 life_time_counter_low[0x20];
2104
2105 u8 rx_errors[0x20];
2106
2107 u8 tx_errors[0x20];
2108
2109 u8 l0_to_recovery_eieos[0x20];
2110
2111 u8 l0_to_recovery_ts[0x20];
2112
2113 u8 l0_to_recovery_framing[0x20];
2114
2115 u8 l0_to_recovery_retrain[0x20];
2116
2117 u8 crc_error_dllp[0x20];
2118
2119 u8 crc_error_tlp[0x20];
2120
efae7f78
EBE		 2121 u8 tx_overflow_buffer_pkt_high[0x20];
2122
2123 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2124
2125 u8 outbound_stalled_reads[0x20];
2126
2127 u8 outbound_stalled_writes[0x20];
2128
2129 u8 outbound_stalled_reads_events[0x20];
2130
2131 u8 outbound_stalled_writes_events[0x20];
2132
2133 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2134};
2135
e281682b
SM		 2136struct mlx5_ifc_cmd_inter_comp_event_bits {
2137 u8 command_completion_vector[0x20];
2138
b4ff3a36 2139 u8 reserved_at_20[0xc0];
e281682b
SM		 2140};
2141
2142struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2143 u8 reserved_at_0[0x18];
e281682b 2144 u8 port_num[0x1];
b4ff3a36 2145 u8 reserved_at_19[0x3];
e281682b
SM		 2146 u8 vl[0x4];
2147
b4ff3a36 2148 u8 reserved_at_20[0xa0];
e281682b
SM		 2149};
2150
2151struct mlx5_ifc_db_bf_congestion_event_bits {
2152 u8 event_subtype[0x8];
b4ff3a36 2153 u8 reserved_at_8[0x8];
e281682b 2154 u8 congestion_level[0x8];
b4ff3a36 2155 u8 reserved_at_18[0x8];
e281682b 2156
b4ff3a36 2157 u8 reserved_at_20[0xa0];
e281682b
SM		 2158};
2159
2160struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2161 u8 reserved_at_0[0x60];
e281682b
SM		 2162
2163 u8 gpio_event_hi[0x20];
2164
2165 u8 gpio_event_lo[0x20];
2166
b4ff3a36 2167 u8 reserved_at_a0[0x40];
e281682b
SM		 2168};
2169
2170struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2171 u8 reserved_at_0[0x40];
e281682b
SM		 2172
2173 u8 port_num[0x4];
b4ff3a36 2174 u8 reserved_at_44[0x1c];
e281682b 2175
b4ff3a36 2176 u8 reserved_at_60[0x80];
e281682b
SM		 2177};
2178
2179struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2180 u8 reserved_at_0[0xe0];
e281682b
SM		 2181};
2182
2183enum {
2184 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2185 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2186};
2187
2188struct mlx5_ifc_cq_error_bits {
b4ff3a36 2189 u8 reserved_at_0[0x8];
e281682b
SM		 2190 u8 cqn[0x18];
2191
b4ff3a36 2192 u8 reserved_at_20[0x20];
e281682b 2193
b4ff3a36 2194 u8 reserved_at_40[0x18];
e281682b
SM		 2195 u8 syndrome[0x8];
2196
b4ff3a36 2197 u8 reserved_at_60[0x80];
e281682b
SM		 2198};
2199
2200struct mlx5_ifc_rdma_page_fault_event_bits {
2201 u8 bytes_committed[0x20];
2202
2203 u8 r_key[0x20];
2204
b4ff3a36 2205 u8 reserved_at_40[0x10];
e281682b
SM		 2206 u8 packet_len[0x10];
2207
2208 u8 rdma_op_len[0x20];
2209
2210 u8 rdma_va[0x40];
2211
b4ff3a36 2212 u8 reserved_at_c0[0x5];
e281682b
SM		 2213 u8 rdma[0x1];
2214 u8 write[0x1];
2215 u8 requestor[0x1];
2216 u8 qp_number[0x18];
2217};
2218
2219struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2220 u8 bytes_committed[0x20];
2221
b4ff3a36 2222 u8 reserved_at_20[0x10];
e281682b
SM		 2223 u8 wqe_index[0x10];
2224
b4ff3a36 2225 u8 reserved_at_40[0x10];
e281682b
SM		 2226 u8 len[0x10];
2227
b4ff3a36 2228 u8 reserved_at_60[0x60];
e281682b 2229
b4ff3a36 2230 u8 reserved_at_c0[0x5];
e281682b
SM		 2231 u8 rdma[0x1];
2232 u8 write_read[0x1];
2233 u8 requestor[0x1];
2234 u8 qpn[0x18];
2235};
2236
2237struct mlx5_ifc_qp_events_bits {
b4ff3a36 2238 u8 reserved_at_0[0xa0];
e281682b
SM		 2239
2240 u8 type[0x8];
b4ff3a36 2241 u8 reserved_at_a8[0x18];
e281682b 2242
b4ff3a36 2243 u8 reserved_at_c0[0x8];
e281682b
SM		 2244 u8 qpn_rqn_sqn[0x18];
2245};
2246
2247struct mlx5_ifc_dct_events_bits {
b4ff3a36 2248 u8 reserved_at_0[0xc0];
e281682b 2249
b4ff3a36 2250 u8 reserved_at_c0[0x8];
e281682b
SM		 2251 u8 dct_number[0x18];
2252};
2253
2254struct mlx5_ifc_comp_event_bits {
b4ff3a36 2255 u8 reserved_at_0[0xc0];
e281682b 2256
b4ff3a36 2257 u8 reserved_at_c0[0x8];
e281682b
SM		 2258 u8 cq_number[0x18];
2259};
2260
2261enum {
2262 MLX5_QPC_STATE_RST = 0x0,
2263 MLX5_QPC_STATE_INIT = 0x1,
2264 MLX5_QPC_STATE_RTR = 0x2,
2265 MLX5_QPC_STATE_RTS = 0x3,
2266 MLX5_QPC_STATE_SQER = 0x4,
2267 MLX5_QPC_STATE_ERR = 0x6,
2268 MLX5_QPC_STATE_SQD = 0x7,
2269 MLX5_QPC_STATE_SUSPENDED = 0x9,
2270};
2271
2272enum {
2273 MLX5_QPC_ST_RC = 0x0,
2274 MLX5_QPC_ST_UC = 0x1,
2275 MLX5_QPC_ST_UD = 0x2,
2276 MLX5_QPC_ST_XRC = 0x3,
2277 MLX5_QPC_ST_DCI = 0x5,
2278 MLX5_QPC_ST_QP0 = 0x7,
2279 MLX5_QPC_ST_QP1 = 0x8,
2280 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2281 MLX5_QPC_ST_REG_UMR = 0xc,
2282};
2283
2284enum {
2285 MLX5_QPC_PM_STATE_ARMED = 0x0,
2286 MLX5_QPC_PM_STATE_REARM = 0x1,
2287 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2288 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2289};
2290
6e44636a
AK		 2291enum {
2292 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2293};
2294
e281682b
SM		 2295enum {
2296 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2297 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2298};
2299
2300enum {
2301 MLX5_QPC_MTU_256_BYTES = 0x1,
2302 MLX5_QPC_MTU_512_BYTES = 0x2,
2303 MLX5_QPC_MTU_1K_BYTES = 0x3,
2304 MLX5_QPC_MTU_2K_BYTES = 0x4,
2305 MLX5_QPC_MTU_4K_BYTES = 0x5,
2306 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2307};
2308
2309enum {
2310 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2311 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2312 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2313 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2314 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2315 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2316 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2317 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2318};
2319
2320enum {
2321 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2322 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2323 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2324};
2325
2326enum {
2327 MLX5_QPC_CS_RES_DISABLE = 0x0,
2328 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2329 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2330};
2331
2332struct mlx5_ifc_qpc_bits {
2333 u8 state[0x4];
84df61eb 2334 u8 lag_tx_port_affinity[0x4];
e281682b 2335 u8 st[0x8];
b4ff3a36 2336 u8 reserved_at_10[0x3];
e281682b 2337 u8 pm_state[0x2];
3fd3c80a
DG		 2338 u8 reserved_at_15[0x1];
2339 u8 req_e2e_credit_mode[0x2];
6e44636a 2340 u8 offload_type[0x4];
e281682b 2341 u8 end_padding_mode[0x2];
b4ff3a36 2342 u8 reserved_at_1e[0x2];
e281682b
SM		 2343
2344 u8 wq_signature[0x1];
2345 u8 block_lb_mc[0x1];
2346 u8 atomic_like_write_en[0x1];
2347 u8 latency_sensitive[0x1];
b4ff3a36 2348 u8 reserved_at_24[0x1];
e281682b 2349 u8 drain_sigerr[0x1];
b4ff3a36 2350 u8 reserved_at_26[0x2];
e281682b
SM		 2351 u8 pd[0x18];
2352
2353 u8 mtu[0x3];
2354 u8 log_msg_max[0x5];
b4ff3a36 2355 u8 reserved_at_48[0x1];
e281682b
SM		 2356 u8 log_rq_size[0x4];
2357 u8 log_rq_stride[0x3];
2358 u8 no_sq[0x1];
2359 u8 log_sq_size[0x4];
b4ff3a36 2360 u8 reserved_at_55[0x6];
e281682b 2361 u8 rlky[0x1];
1015c2e8 2362 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2363
2364 u8 counter_set_id[0x8];
2365 u8 uar_page[0x18];
2366
b4ff3a36 2367 u8 reserved_at_80[0x8];
e281682b
SM		 2368 u8 user_index[0x18];
2369
b4ff3a36 2370 u8 reserved_at_a0[0x3];
e281682b
SM		 2371 u8 log_page_size[0x5];
2372 u8 remote_qpn[0x18];
2373
2374 struct mlx5_ifc_ads_bits primary_address_path;
2375
2376 struct mlx5_ifc_ads_bits secondary_address_path;
2377
2378 u8 log_ack_req_freq[0x4];
b4ff3a36 2379 u8 reserved_at_384[0x4];
e281682b 2380 u8 log_sra_max[0x3];
b4ff3a36 2381 u8 reserved_at_38b[0x2];
e281682b
SM		 2382 u8 retry_count[0x3];
2383 u8 rnr_retry[0x3];
b4ff3a36 2384 u8 reserved_at_393[0x1];
e281682b
SM		 2385 u8 fre[0x1];
2386 u8 cur_rnr_retry[0x3];
2387 u8 cur_retry_count[0x3];
b4ff3a36 2388 u8 reserved_at_39b[0x5];
e281682b 2389
b4ff3a36 2390 u8 reserved_at_3a0[0x20];
e281682b 2391
b4ff3a36 2392 u8 reserved_at_3c0[0x8];
e281682b
SM		 2393 u8 next_send_psn[0x18];
2394
b4ff3a36 2395 u8 reserved_at_3e0[0x8];
e281682b
SM		 2396 u8 cqn_snd[0x18];
2397
09a7d9ec
SM		 2398 u8 reserved_at_400[0x8];
2399 u8 deth_sqpn[0x18];
2400
2401 u8 reserved_at_420[0x20];
e281682b 2402
b4ff3a36 2403 u8 reserved_at_440[0x8];
e281682b
SM		 2404 u8 last_acked_psn[0x18];
2405
b4ff3a36 2406 u8 reserved_at_460[0x8];
e281682b
SM		 2407 u8 ssn[0x18];
2408
b4ff3a36 2409 u8 reserved_at_480[0x8];
e281682b 2410 u8 log_rra_max[0x3];
b4ff3a36 2411 u8 reserved_at_48b[0x1];
e281682b
SM		 2412 u8 atomic_mode[0x4];
2413 u8 rre[0x1];
2414 u8 rwe[0x1];
2415 u8 rae[0x1];
b4ff3a36 2416 u8 reserved_at_493[0x1];
e281682b 2417 u8 page_offset[0x6];
b4ff3a36 2418 u8 reserved_at_49a[0x3];
e281682b
SM		 2419 u8 cd_slave_receive[0x1];
2420 u8 cd_slave_send[0x1];
2421 u8 cd_master[0x1];
2422
b4ff3a36 2423 u8 reserved_at_4a0[0x3];
e281682b
SM		 2424 u8 min_rnr_nak[0x5];
2425 u8 next_rcv_psn[0x18];
2426
b4ff3a36 2427 u8 reserved_at_4c0[0x8];
e281682b
SM		 2428 u8 xrcd[0x18];
2429
b4ff3a36 2430 u8 reserved_at_4e0[0x8];
e281682b
SM		 2431 u8 cqn_rcv[0x18];
2432
2433 u8 dbr_addr[0x40];
2434
2435 u8 q_key[0x20];
2436
b4ff3a36 2437 u8 reserved_at_560[0x5];
e281682b 2438 u8 rq_type[0x3];
7486216b 2439 u8 srqn_rmpn_xrqn[0x18];
e281682b 2440
b4ff3a36 2441 u8 reserved_at_580[0x8];
e281682b
SM		 2442 u8 rmsn[0x18];
2443
2444 u8 hw_sq_wqebb_counter[0x10];
2445 u8 sw_sq_wqebb_counter[0x10];
2446
2447 u8 hw_rq_counter[0x20];
2448
2449 u8 sw_rq_counter[0x20];
2450
b4ff3a36 2451 u8 reserved_at_600[0x20];
e281682b 2452
b4ff3a36 2453 u8 reserved_at_620[0xf];
e281682b
SM		 2454 u8 cgs[0x1];
2455 u8 cs_req[0x8];
2456 u8 cs_res[0x8];
2457
2458 u8 dc_access_key[0x40];
2459
bd371975
LR		 2460 u8 reserved_at_680[0x3];
2461 u8 dbr_umem_valid[0x1];
2462
2463 u8 reserved_at_684[0xbc];
e281682b
SM		 2464};
2465
2466struct mlx5_ifc_roce_addr_layout_bits {
2467 u8 source_l3_address[16][0x8];
2468
b4ff3a36 2469 u8 reserved_at_80[0x3];
e281682b
SM		 2470 u8 vlan_valid[0x1];
2471 u8 vlan_id[0xc];
2472 u8 source_mac_47_32[0x10];
2473
2474 u8 source_mac_31_0[0x20];
2475
b4ff3a36 2476 u8 reserved_at_c0[0x14];
e281682b
SM		 2477 u8 roce_l3_type[0x4];
2478 u8 roce_version[0x8];
2479
b4ff3a36 2480 u8 reserved_at_e0[0x20];
e281682b
SM		 2481};
2482
2483union mlx5_ifc_hca_cap_union_bits {
2484 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2485 struct mlx5_ifc_odp_cap_bits odp_cap;
2486 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2487 struct mlx5_ifc_roce_cap_bits roce_cap;
2488 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2489 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2490 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2491 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2492 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2493 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2494 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2495 u8 reserved_at_0[0x8000];
e281682b
SM		 2496};
2497
2498enum {
2499 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2500 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2501 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2502 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 2503 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 2504 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2505 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2506 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2507 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 2508 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2509 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
0c06897a
OG		 2510};
2511
2512struct mlx5_ifc_vlan_bits {
2513 u8 ethtype[0x10];
2514 u8 prio[0x3];
2515 u8 cfi[0x1];
2516 u8 vid[0xc];
e281682b
SM		 2517};
2518
2519struct mlx5_ifc_flow_context_bits {
0c06897a 2520 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2521
2522 u8 group_id[0x20];
2523
b4ff3a36 2524 u8 reserved_at_40[0x8];
e281682b
SM		 2525 u8 flow_tag[0x18];
2526
b4ff3a36 2527 u8 reserved_at_60[0x10];
e281682b
SM		 2528 u8 action[0x10];
2529
1b115498
EB		 2530 u8 extended_destination[0x1];
2531 u8 reserved_at_80[0x7];
e281682b
SM		 2532 u8 destination_list_size[0x18];
2533
9dc0b289
AV		 2534 u8 reserved_at_a0[0x8];
2535 u8 flow_counter_list_size[0x18];
2536
60786f09 2537 u8 packet_reformat_id[0x20];
7adbde20 2538
2a69cb9f
OG		 2539 u8 modify_header_id[0x20];
2540
8da6fe2a
JL		 2541 struct mlx5_ifc_vlan_bits push_vlan_2;
2542
2543 u8 reserved_at_120[0xe0];
e281682b
SM		 2544
2545 struct mlx5_ifc_fte_match_param_bits match_value;
2546
b4ff3a36 2547 u8 reserved_at_1200[0x600];
e281682b 2548
9dc0b289 2549 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2550};
2551
2552enum {
2553 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2554 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2555};
2556
2557struct mlx5_ifc_xrc_srqc_bits {
2558 u8 state[0x4];
2559 u8 log_xrc_srq_size[0x4];
b4ff3a36 2560 u8 reserved_at_8[0x18];
e281682b
SM		 2561
2562 u8 wq_signature[0x1];
2563 u8 cont_srq[0x1];
99b77fef 2564 u8 reserved_at_22[0x1];
e281682b
SM		 2565 u8 rlky[0x1];
2566 u8 basic_cyclic_rcv_wqe[0x1];
2567 u8 log_rq_stride[0x3];
2568 u8 xrcd[0x18];
2569
2570 u8 page_offset[0x6];
99b77fef
YH		 2571 u8 reserved_at_46[0x1];
2572 u8 dbr_umem_valid[0x1];
e281682b
SM		 2573 u8 cqn[0x18];
2574
b4ff3a36 2575 u8 reserved_at_60[0x20];
e281682b
SM		 2576
2577 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2578 u8 reserved_at_81[0x1];
e281682b
SM		 2579 u8 log_page_size[0x6];
2580 u8 user_index[0x18];
2581
b4ff3a36 2582 u8 reserved_at_a0[0x20];
e281682b 2583
b4ff3a36 2584 u8 reserved_at_c0[0x8];
e281682b
SM		 2585 u8 pd[0x18];
2586
2587 u8 lwm[0x10];
2588 u8 wqe_cnt[0x10];
2589
b4ff3a36 2590 u8 reserved_at_100[0x40];
e281682b
SM		 2591
2592 u8 db_record_addr_h[0x20];
2593
2594 u8 db_record_addr_l[0x1e];
b4ff3a36 2595 u8 reserved_at_17e[0x2];
e281682b 2596
b4ff3a36 2597 u8 reserved_at_180[0x80];
e281682b
SM		 2598};
2599
61c5b5c9
MS		 2600struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2601 u8 counter_error_queues[0x20];
2602
2603 u8 total_error_queues[0x20];
2604
2605 u8 send_queue_priority_update_flow[0x20];
2606
2607 u8 reserved_at_60[0x20];
2608
2609 u8 nic_receive_steering_discard[0x40];
2610
2611 u8 receive_discard_vport_down[0x40];
2612
2613 u8 transmit_discard_vport_down[0x40];
2614
2615 u8 reserved_at_140[0xec0];
2616};
2617
e281682b
SM		 2618struct mlx5_ifc_traffic_counter_bits {
2619 u8 packets[0x40];
2620
2621 u8 octets[0x40];
2622};
2623
2624struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2625 u8 strict_lag_tx_port_affinity[0x1];
2626 u8 reserved_at_1[0x3];
2627 u8 lag_tx_port_affinity[0x04];
2628
2629 u8 reserved_at_8[0x4];
e281682b 2630 u8 prio[0x4];
b4ff3a36 2631 u8 reserved_at_10[0x10];
e281682b 2632
b4ff3a36 2633 u8 reserved_at_20[0x100];
e281682b 2634
b4ff3a36 2635 u8 reserved_at_120[0x8];
e281682b
SM		 2636 u8 transport_domain[0x18];
2637
500a3d0d
ES		 2638 u8 reserved_at_140[0x8];
2639 u8 underlay_qpn[0x18];
2640 u8 reserved_at_160[0x3a0];
e281682b
SM		 2641};
2642
2643enum {
2644 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2645 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2646};
2647
2648enum {
2649 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2650 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2651};
2652
2653enum {
2be6967c
SM		 2654 MLX5_RX_HASH_FN_NONE = 0x0,
2655 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2656 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2657};
2658
2659enum {
5d773ff4
MB		 2660 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2661 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 2662};
2663
2664struct mlx5_ifc_tirc_bits {
b4ff3a36 2665 u8 reserved_at_0[0x20];
e281682b
SM		 2666
2667 u8 disp_type[0x4];
b4ff3a36 2668 u8 reserved_at_24[0x1c];
e281682b 2669
b4ff3a36 2670 u8 reserved_at_40[0x40];
e281682b 2671
b4ff3a36 2672 u8 reserved_at_80[0x4];
e281682b
SM		 2673 u8 lro_timeout_period_usecs[0x10];
2674 u8 lro_enable_mask[0x4];
2675 u8 lro_max_ip_payload_size[0x8];
2676
b4ff3a36 2677 u8 reserved_at_a0[0x40];
e281682b 2678
b4ff3a36 2679 u8 reserved_at_e0[0x8];
e281682b
SM		 2680 u8 inline_rqn[0x18];
2681
2682 u8 rx_hash_symmetric[0x1];
b4ff3a36 2683 u8 reserved_at_101[0x1];
e281682b 2684 u8 tunneled_offload_en[0x1];
b4ff3a36 2685 u8 reserved_at_103[0x5];
e281682b
SM		 2686 u8 indirect_table[0x18];
2687
2688 u8 rx_hash_fn[0x4];
b4ff3a36 2689 u8 reserved_at_124[0x2];
e281682b
SM		 2690 u8 self_lb_block[0x2];
2691 u8 transport_domain[0x18];
2692
2693 u8 rx_hash_toeplitz_key[10][0x20];
2694
2695 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2696
2697 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2698
b4ff3a36 2699 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2700};
2701
2702enum {
2703 MLX5_SRQC_STATE_GOOD = 0x0,
2704 MLX5_SRQC_STATE_ERROR = 0x1,
2705};
2706
2707struct mlx5_ifc_srqc_bits {
2708 u8 state[0x4];
2709 u8 log_srq_size[0x4];
b4ff3a36 2710 u8 reserved_at_8[0x18];
e281682b
SM		 2711
2712 u8 wq_signature[0x1];
2713 u8 cont_srq[0x1];
b4ff3a36 2714 u8 reserved_at_22[0x1];
e281682b 2715 u8 rlky[0x1];
b4ff3a36 2716 u8 reserved_at_24[0x1];
e281682b
SM		 2717 u8 log_rq_stride[0x3];
2718 u8 xrcd[0x18];
2719
2720 u8 page_offset[0x6];
b4ff3a36 2721 u8 reserved_at_46[0x2];
e281682b
SM		 2722 u8 cqn[0x18];
2723
b4ff3a36 2724 u8 reserved_at_60[0x20];
e281682b 2725
b4ff3a36 2726 u8 reserved_at_80[0x2];
e281682b 2727 u8 log_page_size[0x6];
b4ff3a36 2728 u8 reserved_at_88[0x18];
e281682b 2729
b4ff3a36 2730 u8 reserved_at_a0[0x20];
e281682b 2731
b4ff3a36 2732 u8 reserved_at_c0[0x8];
e281682b
SM		 2733 u8 pd[0x18];
2734
2735 u8 lwm[0x10];
2736 u8 wqe_cnt[0x10];
2737
b4ff3a36 2738 u8 reserved_at_100[0x40];
e281682b 2739
01949d01 2740 u8 dbr_addr[0x40];
e281682b 2741
b4ff3a36 2742 u8 reserved_at_180[0x80];
e281682b
SM		 2743};
2744
2745enum {
2746 MLX5_SQC_STATE_RST = 0x0,
2747 MLX5_SQC_STATE_RDY = 0x1,
2748 MLX5_SQC_STATE_ERR = 0x3,
2749};
2750
2751struct mlx5_ifc_sqc_bits {
2752 u8 rlky[0x1];
2753 u8 cd_master[0x1];
2754 u8 fre[0x1];
2755 u8 flush_in_error_en[0x1];
795b609c 2756 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2757 u8 min_wqe_inline_mode[0x3];
e281682b 2758 u8 state[0x4];
7d5e1423 2759 u8 reg_umr[0x1];
547eede0 2760 u8 allow_swp[0x1];
40817cdb
OG		 2761 u8 hairpin[0x1];
2762 u8 reserved_at_f[0x11];
e281682b 2763
b4ff3a36 2764 u8 reserved_at_20[0x8];
e281682b
SM		 2765 u8 user_index[0x18];
2766
b4ff3a36 2767 u8 reserved_at_40[0x8];
e281682b
SM		 2768 u8 cqn[0x18];
2769
40817cdb
OG		 2770 u8 reserved_at_60[0x8];
2771 u8 hairpin_peer_rq[0x18];
2772
2773 u8 reserved_at_80[0x10];
2774 u8 hairpin_peer_vhca[0x10];
2775
2776 u8 reserved_at_a0[0x50];
e281682b 2777
7486216b 2778 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2779 u8 tis_lst_sz[0x10];
b4ff3a36 2780 u8 reserved_at_110[0x10];
e281682b 2781
b4ff3a36 2782 u8 reserved_at_120[0x40];
e281682b 2783
b4ff3a36 2784 u8 reserved_at_160[0x8];
e281682b
SM		 2785 u8 tis_num_0[0x18];
2786
2787 struct mlx5_ifc_wq_bits wq;
2788};
2789
813f8540
MHY		 2790enum {
2791 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2792 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2793 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2794 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2795};
2796
2797struct mlx5_ifc_scheduling_context_bits {
2798 u8 element_type[0x8];
2799 u8 reserved_at_8[0x18];
2800
2801 u8 element_attributes[0x20];
2802
2803 u8 parent_element_id[0x20];
2804
2805 u8 reserved_at_60[0x40];
2806
2807 u8 bw_share[0x20];
2808
2809 u8 max_average_bw[0x20];
2810
2811 u8 reserved_at_e0[0x120];
2812};
2813
e281682b 2814struct mlx5_ifc_rqtc_bits {
b4ff3a36 2815 u8 reserved_at_0[0xa0];
e281682b 2816
b4ff3a36 2817 u8 reserved_at_a0[0x10];
e281682b
SM		 2818 u8 rqt_max_size[0x10];
2819
b4ff3a36 2820 u8 reserved_at_c0[0x10];
e281682b
SM		 2821 u8 rqt_actual_size[0x10];
2822
b4ff3a36 2823 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2824
2825 struct mlx5_ifc_rq_num_bits rq_num[0];
2826};
2827
2828enum {
2829 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2830 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2831};
2832
2833enum {
2834 MLX5_RQC_STATE_RST = 0x0,
2835 MLX5_RQC_STATE_RDY = 0x1,
2836 MLX5_RQC_STATE_ERR = 0x3,
2837};
2838
2839struct mlx5_ifc_rqc_bits {
2840 u8 rlky[0x1];
03404e8a 2841 u8 delay_drop_en[0x1];
7d5e1423 2842 u8 scatter_fcs[0x1];
e281682b
SM		 2843 u8 vsd[0x1];
2844 u8 mem_rq_type[0x4];
2845 u8 state[0x4];
b4ff3a36 2846 u8 reserved_at_c[0x1];
e281682b 2847 u8 flush_in_error_en[0x1];
40817cdb
OG		 2848 u8 hairpin[0x1];
2849 u8 reserved_at_f[0x11];
e281682b 2850
b4ff3a36 2851 u8 reserved_at_20[0x8];
e281682b
SM		 2852 u8 user_index[0x18];
2853
b4ff3a36 2854 u8 reserved_at_40[0x8];
e281682b
SM		 2855 u8 cqn[0x18];
2856
2857 u8 counter_set_id[0x8];
b4ff3a36 2858 u8 reserved_at_68[0x18];
e281682b 2859
b4ff3a36 2860 u8 reserved_at_80[0x8];
e281682b
SM		 2861 u8 rmpn[0x18];
2862
40817cdb
OG		 2863 u8 reserved_at_a0[0x8];
2864 u8 hairpin_peer_sq[0x18];
2865
2866 u8 reserved_at_c0[0x10];
2867 u8 hairpin_peer_vhca[0x10];
2868
2869 u8 reserved_at_e0[0xa0];
e281682b
SM		 2870
2871 struct mlx5_ifc_wq_bits wq;
2872};
2873
2874enum {
2875 MLX5_RMPC_STATE_RDY = 0x1,
2876 MLX5_RMPC_STATE_ERR = 0x3,
2877};
2878
2879struct mlx5_ifc_rmpc_bits {
b4ff3a36 2880 u8 reserved_at_0[0x8];
e281682b 2881 u8 state[0x4];
b4ff3a36 2882 u8 reserved_at_c[0x14];
e281682b
SM		 2883
2884 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2885 u8 reserved_at_21[0x1f];
e281682b 2886
b4ff3a36 2887 u8 reserved_at_40[0x140];
e281682b
SM		 2888
2889 struct mlx5_ifc_wq_bits wq;
2890};
2891
e281682b 2892struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2893 u8 reserved_at_0[0x5];
2894 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2895 u8 reserved_at_8[0x15];
2896 u8 disable_mc_local_lb[0x1];
2897 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2898 u8 roce_en[0x1];
2899
d82b7318 2900 u8 arm_change_event[0x1];
b4ff3a36 2901 u8 reserved_at_21[0x1a];
d82b7318
SM		 2902 u8 event_on_mtu[0x1];
2903 u8 event_on_promisc_change[0x1];
2904 u8 event_on_vlan_change[0x1];
2905 u8 event_on_mc_address_change[0x1];
2906 u8 event_on_uc_address_change[0x1];
e281682b 2907
32f69e4b
DJ		 2908 u8 reserved_at_40[0xc];
2909
2910 u8 affiliation_criteria[0x4];
2911 u8 affiliated_vhca_id[0x10];
2912
2913 u8 reserved_at_60[0xd0];
d82b7318
SM		 2914
2915 u8 mtu[0x10];
2916
9efa7525
AS		 2917 u8 system_image_guid[0x40];
2918 u8 port_guid[0x40];
2919 u8 node_guid[0x40];
2920
b4ff3a36 2921 u8 reserved_at_200[0x140];
9efa7525 2922 u8 qkey_violation_counter[0x10];
b4ff3a36 2923 u8 reserved_at_350[0x430];
d82b7318
SM		 2924
2925 u8 promisc_uc[0x1];
2926 u8 promisc_mc[0x1];
2927 u8 promisc_all[0x1];
b4ff3a36 2928 u8 reserved_at_783[0x2];
e281682b 2929 u8 allowed_list_type[0x3];
b4ff3a36 2930 u8 reserved_at_788[0xc];
e281682b
SM		 2931 u8 allowed_list_size[0xc];
2932
2933 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2934
b4ff3a36 2935 u8 reserved_at_7e0[0x20];
e281682b
SM		 2936
2937 u8 current_uc_mac_address[0][0x40];
2938};
2939
2940enum {
2941 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2942 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2943 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2944 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 2945 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 2946 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 2947};
2948
2949struct mlx5_ifc_mkc_bits {
b4ff3a36 2950 u8 reserved_at_0[0x1];
e281682b 2951 u8 free[0x1];
cdbd0d2b
AL		 2952 u8 reserved_at_2[0x1];
2953 u8 access_mode_4_2[0x3];
2954 u8 reserved_at_6[0x7];
2955 u8 relaxed_ordering_write[0x1];
2956 u8 reserved_at_e[0x1];
e281682b
SM		 2957 u8 small_fence_on_rdma_read_response[0x1];
2958 u8 umr_en[0x1];
2959 u8 a[0x1];
2960 u8 rw[0x1];
2961 u8 rr[0x1];
2962 u8 lw[0x1];
2963 u8 lr[0x1];
cdbd0d2b 2964 u8 access_mode_1_0[0x2];
b4ff3a36 2965 u8 reserved_at_18[0x8];
e281682b
SM		 2966
2967 u8 qpn[0x18];
2968 u8 mkey_7_0[0x8];
2969
b4ff3a36 2970 u8 reserved_at_40[0x20];
e281682b
SM		 2971
2972 u8 length64[0x1];
2973 u8 bsf_en[0x1];
2974 u8 sync_umr[0x1];
b4ff3a36 2975 u8 reserved_at_63[0x2];
e281682b 2976 u8 expected_sigerr_count[0x1];
b4ff3a36 2977 u8 reserved_at_66[0x1];
e281682b
SM		 2978 u8 en_rinval[0x1];
2979 u8 pd[0x18];
2980
2981 u8 start_addr[0x40];
2982
2983 u8 len[0x40];
2984
2985 u8 bsf_octword_size[0x20];
2986
b4ff3a36 2987 u8 reserved_at_120[0x80];
e281682b
SM		 2988
2989 u8 translations_octword_size[0x20];
2990
b4ff3a36 2991 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2992 u8 log_page_size[0x5];
2993
b4ff3a36 2994 u8 reserved_at_1e0[0x20];
e281682b
SM		 2995};
2996
2997struct mlx5_ifc_pkey_bits {
b4ff3a36 2998 u8 reserved_at_0[0x10];
e281682b
SM		 2999 u8 pkey[0x10];
3000};
3001
3002struct mlx5_ifc_array128_auto_bits {
3003 u8 array128_auto[16][0x8];
3004};
3005
3006struct mlx5_ifc_hca_vport_context_bits {
3007 u8 field_select[0x20];
3008
b4ff3a36 3009 u8 reserved_at_20[0xe0];
e281682b
SM		 3010
3011 u8 sm_virt_aware[0x1];
3012 u8 has_smi[0x1];
3013 u8 has_raw[0x1];
3014 u8 grh_required[0x1];
b4ff3a36 3015 u8 reserved_at_104[0xc];
707c4602
MD		 3016 u8 port_physical_state[0x4];
3017 u8 vport_state_policy[0x4];
3018 u8 port_state[0x4];
e281682b
SM		 3019 u8 vport_state[0x4];
3020
b4ff3a36 3021 u8 reserved_at_120[0x20];
707c4602
MD		 3022
3023 u8 system_image_guid[0x40];
e281682b
SM		 3024
3025 u8 port_guid[0x40];
3026
3027 u8 node_guid[0x40];
3028
3029 u8 cap_mask1[0x20];
3030
3031 u8 cap_mask1_field_select[0x20];
3032
3033 u8 cap_mask2[0x20];
3034
3035 u8 cap_mask2_field_select[0x20];
3036
b4ff3a36 3037 u8 reserved_at_280[0x80];
e281682b
SM		 3038
3039 u8 lid[0x10];
b4ff3a36 3040 u8 reserved_at_310[0x4];
e281682b
SM		 3041 u8 init_type_reply[0x4];
3042 u8 lmc[0x3];
3043 u8 subnet_timeout[0x5];
3044
3045 u8 sm_lid[0x10];
3046 u8 sm_sl[0x4];
b4ff3a36 3047 u8 reserved_at_334[0xc];
e281682b
SM		 3048
3049 u8 qkey_violation_counter[0x10];
3050 u8 pkey_violation_counter[0x10];
3051
b4ff3a36 3052 u8 reserved_at_360[0xca0];
e281682b
SM		 3053};
3054
d6666753 3055struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 3056 u8 reserved_at_0[0x3];
d6666753
SM		 3057 u8 vport_svlan_strip[0x1];
3058 u8 vport_cvlan_strip[0x1];
3059 u8 vport_svlan_insert[0x1];
3060 u8 vport_cvlan_insert[0x2];
b4ff3a36 3061 u8 reserved_at_8[0x18];
d6666753 3062
b4ff3a36 3063 u8 reserved_at_20[0x20];
d6666753
SM		 3064
3065 u8 svlan_cfi[0x1];
3066 u8 svlan_pcp[0x3];
3067 u8 svlan_id[0xc];
3068 u8 cvlan_cfi[0x1];
3069 u8 cvlan_pcp[0x3];
3070 u8 cvlan_id[0xc];
3071
b4ff3a36 3072 u8 reserved_at_60[0x7a0];
d6666753
SM		 3073};
3074
e281682b
SM		 3075enum {
3076 MLX5_EQC_STATUS_OK = 0x0,
3077 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3078};
3079
3080enum {
3081 MLX5_EQC_ST_ARMED = 0x9,
3082 MLX5_EQC_ST_FIRED = 0xa,
3083};
3084
3085struct mlx5_ifc_eqc_bits {
3086 u8 status[0x4];
b4ff3a36 3087 u8 reserved_at_4[0x9];
e281682b
SM		 3088 u8 ec[0x1];
3089 u8 oi[0x1];
b4ff3a36 3090 u8 reserved_at_f[0x5];
e281682b 3091 u8 st[0x4];
b4ff3a36 3092 u8 reserved_at_18[0x8];
e281682b 3093
b4ff3a36 3094 u8 reserved_at_20[0x20];
e281682b 3095
b4ff3a36 3096 u8 reserved_at_40[0x14];
e281682b 3097 u8 page_offset[0x6];
b4ff3a36 3098 u8 reserved_at_5a[0x6];
e281682b 3099
b4ff3a36 3100 u8 reserved_at_60[0x3];
e281682b
SM		 3101 u8 log_eq_size[0x5];
3102 u8 uar_page[0x18];
3103
b4ff3a36 3104 u8 reserved_at_80[0x20];
e281682b 3105
b4ff3a36 3106 u8 reserved_at_a0[0x18];
e281682b
SM		 3107 u8 intr[0x8];
3108
b4ff3a36 3109 u8 reserved_at_c0[0x3];
e281682b 3110 u8 log_page_size[0x5];
b4ff3a36 3111 u8 reserved_at_c8[0x18];
e281682b 3112
b4ff3a36 3113 u8 reserved_at_e0[0x60];
e281682b 3114
b4ff3a36 3115 u8 reserved_at_140[0x8];
e281682b
SM		 3116 u8 consumer_counter[0x18];
3117
b4ff3a36 3118 u8 reserved_at_160[0x8];
e281682b
SM		 3119 u8 producer_counter[0x18];
3120
b4ff3a36 3121 u8 reserved_at_180[0x80];
e281682b
SM		 3122};
3123
3124enum {
3125 MLX5_DCTC_STATE_ACTIVE = 0x0,
3126 MLX5_DCTC_STATE_DRAINING = 0x1,
3127 MLX5_DCTC_STATE_DRAINED = 0x2,
3128};
3129
3130enum {
3131 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3132 MLX5_DCTC_CS_RES_NA = 0x1,
3133 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3134};
3135
3136enum {
3137 MLX5_DCTC_MTU_256_BYTES = 0x1,
3138 MLX5_DCTC_MTU_512_BYTES = 0x2,
3139 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3140 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3141 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3142};
3143
3144struct mlx5_ifc_dctc_bits {
b4ff3a36 3145 u8 reserved_at_0[0x4];
e281682b 3146 u8 state[0x4];
b4ff3a36 3147 u8 reserved_at_8[0x18];
e281682b 3148
b4ff3a36 3149 u8 reserved_at_20[0x8];
e281682b
SM		 3150 u8 user_index[0x18];
3151
b4ff3a36 3152 u8 reserved_at_40[0x8];
e281682b
SM		 3153 u8 cqn[0x18];
3154
3155 u8 counter_set_id[0x8];
3156 u8 atomic_mode[0x4];
3157 u8 rre[0x1];
3158 u8 rwe[0x1];
3159 u8 rae[0x1];
3160 u8 atomic_like_write_en[0x1];
3161 u8 latency_sensitive[0x1];
3162 u8 rlky[0x1];
3163 u8 free_ar[0x1];
b4ff3a36 3164 u8 reserved_at_73[0xd];
e281682b 3165
b4ff3a36 3166 u8 reserved_at_80[0x8];
e281682b 3167 u8 cs_res[0x8];
b4ff3a36 3168 u8 reserved_at_90[0x3];
e281682b 3169 u8 min_rnr_nak[0x5];
b4ff3a36 3170 u8 reserved_at_98[0x8];
e281682b 3171
b4ff3a36 3172 u8 reserved_at_a0[0x8];
7486216b 3173 u8 srqn_xrqn[0x18];
e281682b 3174
b4ff3a36 3175 u8 reserved_at_c0[0x8];
e281682b
SM		 3176 u8 pd[0x18];
3177
3178 u8 tclass[0x8];
b4ff3a36 3179 u8 reserved_at_e8[0x4];
e281682b
SM		 3180 u8 flow_label[0x14];
3181
3182 u8 dc_access_key[0x40];
3183
b4ff3a36 3184 u8 reserved_at_140[0x5];
e281682b
SM		 3185 u8 mtu[0x3];
3186 u8 port[0x8];
3187 u8 pkey_index[0x10];
3188
b4ff3a36 3189 u8 reserved_at_160[0x8];
e281682b 3190 u8 my_addr_index[0x8];
b4ff3a36 3191 u8 reserved_at_170[0x8];
e281682b
SM		 3192 u8 hop_limit[0x8];
3193
3194 u8 dc_access_key_violation_count[0x20];
3195
b4ff3a36 3196 u8 reserved_at_1a0[0x14];
e281682b
SM		 3197 u8 dei_cfi[0x1];
3198 u8 eth_prio[0x3];
3199 u8 ecn[0x2];
3200 u8 dscp[0x6];
3201
b4ff3a36 3202 u8 reserved_at_1c0[0x40];
e281682b
SM		 3203};
3204
3205enum {
3206 MLX5_CQC_STATUS_OK = 0x0,
3207 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3208 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3209};
3210
3211enum {
3212 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3213 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3214};
3215
3216enum {
3217 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3218 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3219 MLX5_CQC_ST_FIRED = 0xa,
3220};
3221
7d5e1423
SM		 3222enum {
3223 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3224 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3225 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3226};
3227
e281682b
SM		 3228struct mlx5_ifc_cqc_bits {
3229 u8 status[0x4];
bd371975
LR		 3230 u8 reserved_at_4[0x2];
3231 u8 dbr_umem_valid[0x1];
3232 u8 reserved_at_7[0x1];
e281682b
SM		 3233 u8 cqe_sz[0x3];
3234 u8 cc[0x1];
b4ff3a36 3235 u8 reserved_at_c[0x1];
e281682b
SM		 3236 u8 scqe_break_moderation_en[0x1];
3237 u8 oi[0x1];
7d5e1423
SM		 3238 u8 cq_period_mode[0x2];
3239 u8 cqe_comp_en[0x1];
e281682b
SM		 3240 u8 mini_cqe_res_format[0x2];
3241 u8 st[0x4];
b4ff3a36 3242 u8 reserved_at_18[0x8];
e281682b 3243
b4ff3a36 3244 u8 reserved_at_20[0x20];
e281682b 3245
b4ff3a36 3246 u8 reserved_at_40[0x14];
e281682b 3247 u8 page_offset[0x6];
b4ff3a36 3248 u8 reserved_at_5a[0x6];
e281682b 3249
b4ff3a36 3250 u8 reserved_at_60[0x3];
e281682b
SM		 3251 u8 log_cq_size[0x5];
3252 u8 uar_page[0x18];
3253
b4ff3a36 3254 u8 reserved_at_80[0x4];
e281682b
SM		 3255 u8 cq_period[0xc];
3256 u8 cq_max_count[0x10];
3257
b4ff3a36 3258 u8 reserved_at_a0[0x18];
e281682b
SM		 3259 u8 c_eqn[0x8];
3260
b4ff3a36 3261 u8 reserved_at_c0[0x3];
e281682b 3262 u8 log_page_size[0x5];
b4ff3a36 3263 u8 reserved_at_c8[0x18];
e281682b 3264
b4ff3a36 3265 u8 reserved_at_e0[0x20];
e281682b 3266
b4ff3a36 3267 u8 reserved_at_100[0x8];
e281682b
SM		 3268 u8 last_notified_index[0x18];
3269
b4ff3a36 3270 u8 reserved_at_120[0x8];
e281682b
SM		 3271 u8 last_solicit_index[0x18];
3272
b4ff3a36 3273 u8 reserved_at_140[0x8];
e281682b
SM		 3274 u8 consumer_counter[0x18];
3275
b4ff3a36 3276 u8 reserved_at_160[0x8];
e281682b
SM		 3277 u8 producer_counter[0x18];
3278
b4ff3a36 3279 u8 reserved_at_180[0x40];
e281682b
SM		 3280
3281 u8 dbr_addr[0x40];
3282};
3283
3284union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3285 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3286 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3287 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3288 u8 reserved_at_0[0x800];
e281682b
SM		 3289};
3290
3291struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3292 u8 reserved_at_0[0xc0];
e281682b 3293
b4ff3a36 3294 u8 reserved_at_c0[0x8];
211e6c80
MD		 3295 u8 ieee_vendor_id[0x18];
3296
b4ff3a36 3297 u8 reserved_at_e0[0x10];
e281682b
SM		 3298 u8 vsd_vendor_id[0x10];
3299
3300 u8 vsd[208][0x8];
3301
3302 u8 vsd_contd_psid[16][0x8];
3303};
3304
7486216b
SM		 3305enum {
3306 MLX5_XRQC_STATE_GOOD = 0x0,
3307 MLX5_XRQC_STATE_ERROR = 0x1,
3308};
3309
3310enum {
3311 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3312 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3313};
3314
3315enum {
3316 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3317};
3318
3319struct mlx5_ifc_tag_matching_topology_context_bits {
3320 u8 log_matching_list_sz[0x4];
3321 u8 reserved_at_4[0xc];
3322 u8 append_next_index[0x10];
3323
3324 u8 sw_phase_cnt[0x10];
3325 u8 hw_phase_cnt[0x10];
3326
3327 u8 reserved_at_40[0x40];
3328};
3329
3330struct mlx5_ifc_xrqc_bits {
3331 u8 state[0x4];
3332 u8 rlkey[0x1];
3333 u8 reserved_at_5[0xf];
3334 u8 topology[0x4];
3335 u8 reserved_at_18[0x4];
3336 u8 offload[0x4];
3337
3338 u8 reserved_at_20[0x8];
3339 u8 user_index[0x18];
3340
3341 u8 reserved_at_40[0x8];
3342 u8 cqn[0x18];
3343
3344 u8 reserved_at_60[0xa0];
3345
3346 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3347
6e44636a 3348 u8 reserved_at_180[0x280];
7486216b
SM		 3349
3350 struct mlx5_ifc_wq_bits wq;
3351};
3352
e281682b
SM		 3353union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3354 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3355 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3356 u8 reserved_at_0[0x20];
e281682b
SM		 3357};
3358
3359union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3360 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3361 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3362 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3363 u8 reserved_at_0[0x20];
e281682b
SM		 3364};
3365
3366union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3367 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3368 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3369 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3370 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3371 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3372 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3373 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3374 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3375 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3376 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3377 u8 reserved_at_0[0x7c0];
e281682b
SM		 3378};
3379
8ed1a630
GP		 3380union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3381 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3382 u8 reserved_at_0[0x7c0];
3383};
3384
e281682b
SM		 3385union mlx5_ifc_event_auto_bits {
3386 struct mlx5_ifc_comp_event_bits comp_event;
3387 struct mlx5_ifc_dct_events_bits dct_events;
3388 struct mlx5_ifc_qp_events_bits qp_events;
3389 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3390 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3391 struct mlx5_ifc_cq_error_bits cq_error;
3392 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3393 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3394 struct mlx5_ifc_gpio_event_bits gpio_event;
3395 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3396 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3397 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3398 u8 reserved_at_0[0xe0];
e281682b
SM		 3399};
3400
3401struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3402 u8 reserved_at_0[0x100];
e281682b
SM		 3403
3404 u8 assert_existptr[0x20];
3405
3406 u8 assert_callra[0x20];
3407
b4ff3a36 3408 u8 reserved_at_140[0x40];
e281682b
SM		 3409
3410 u8 fw_version[0x20];
3411
3412 u8 hw_id[0x20];
3413
b4ff3a36 3414 u8 reserved_at_1c0[0x20];
e281682b
SM		 3415
3416 u8 irisc_index[0x8];
3417 u8 synd[0x8];
3418 u8 ext_synd[0x10];
3419};
3420
3421struct mlx5_ifc_register_loopback_control_bits {
3422 u8 no_lb[0x1];
b4ff3a36 3423 u8 reserved_at_1[0x7];
e281682b 3424 u8 port[0x8];
b4ff3a36 3425 u8 reserved_at_10[0x10];
e281682b 3426
b4ff3a36 3427 u8 reserved_at_20[0x60];
e281682b
SM		 3428};
3429
813f8540
MHY		 3430struct mlx5_ifc_vport_tc_element_bits {
3431 u8 traffic_class[0x4];
3432 u8 reserved_at_4[0xc];
3433 u8 vport_number[0x10];
3434};
3435
3436struct mlx5_ifc_vport_element_bits {
3437 u8 reserved_at_0[0x10];
3438 u8 vport_number[0x10];
3439};
3440
3441enum {
3442 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3443 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3444 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3445};
3446
3447struct mlx5_ifc_tsar_element_bits {
3448 u8 reserved_at_0[0x8];
3449 u8 tsar_type[0x8];
3450 u8 reserved_at_10[0x10];
3451};
3452
8812c24d
MD		 3453enum {
3454 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3455 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3456};
3457
e281682b
SM		 3458struct mlx5_ifc_teardown_hca_out_bits {
3459 u8 status[0x8];
b4ff3a36 3460 u8 reserved_at_8[0x18];
e281682b
SM		 3461
3462 u8 syndrome[0x20];
3463
8812c24d
MD		 3464 u8 reserved_at_40[0x3f];
3465
fcd29ad1 3466 u8 state[0x1];
e281682b
SM		 3467};
3468
3469enum {
3470 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3471 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 3472 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 3473};
3474
3475struct mlx5_ifc_teardown_hca_in_bits {
3476 u8 opcode[0x10];
b4ff3a36 3477 u8 reserved_at_10[0x10];
e281682b 3478
b4ff3a36 3479 u8 reserved_at_20[0x10];
e281682b
SM		 3480 u8 op_mod[0x10];
3481
b4ff3a36 3482 u8 reserved_at_40[0x10];
e281682b
SM		 3483 u8 profile[0x10];
3484
b4ff3a36 3485 u8 reserved_at_60[0x20];
e281682b
SM		 3486};
3487
3488struct mlx5_ifc_sqerr2rts_qp_out_bits {
3489 u8 status[0x8];
b4ff3a36 3490 u8 reserved_at_8[0x18];
e281682b
SM		 3491
3492 u8 syndrome[0x20];
3493
b4ff3a36 3494 u8 reserved_at_40[0x40];
e281682b
SM		 3495};
3496
3497struct mlx5_ifc_sqerr2rts_qp_in_bits {
3498 u8 opcode[0x10];
4ac63ec7 3499 u8 uid[0x10];
e281682b 3500
b4ff3a36 3501 u8 reserved_at_20[0x10];
e281682b
SM		 3502 u8 op_mod[0x10];
3503
b4ff3a36 3504 u8 reserved_at_40[0x8];
e281682b
SM		 3505 u8 qpn[0x18];
3506
b4ff3a36 3507 u8 reserved_at_60[0x20];
e281682b
SM		 3508
3509 u8 opt_param_mask[0x20];
3510
b4ff3a36 3511 u8 reserved_at_a0[0x20];
e281682b
SM		 3512
3513 struct mlx5_ifc_qpc_bits qpc;
3514
b4ff3a36 3515 u8 reserved_at_800[0x80];
e281682b
SM		 3516};
3517
3518struct mlx5_ifc_sqd2rts_qp_out_bits {
3519 u8 status[0x8];
b4ff3a36 3520 u8 reserved_at_8[0x18];
e281682b
SM		 3521
3522 u8 syndrome[0x20];
3523
b4ff3a36 3524 u8 reserved_at_40[0x40];
e281682b
SM		 3525};
3526
3527struct mlx5_ifc_sqd2rts_qp_in_bits {
3528 u8 opcode[0x10];
4ac63ec7 3529 u8 uid[0x10];
e281682b 3530
b4ff3a36 3531 u8 reserved_at_20[0x10];
e281682b
SM		 3532 u8 op_mod[0x10];
3533
b4ff3a36 3534 u8 reserved_at_40[0x8];
e281682b
SM		 3535 u8 qpn[0x18];
3536
b4ff3a36 3537 u8 reserved_at_60[0x20];
e281682b
SM		 3538
3539 u8 opt_param_mask[0x20];
3540
b4ff3a36 3541 u8 reserved_at_a0[0x20];
e281682b
SM		 3542
3543 struct mlx5_ifc_qpc_bits qpc;
3544
b4ff3a36 3545 u8 reserved_at_800[0x80];
e281682b
SM		 3546};
3547
3548struct mlx5_ifc_set_roce_address_out_bits {
3549 u8 status[0x8];
b4ff3a36 3550 u8 reserved_at_8[0x18];
e281682b
SM		 3551
3552 u8 syndrome[0x20];
3553
b4ff3a36 3554 u8 reserved_at_40[0x40];
e281682b
SM		 3555};
3556
3557struct mlx5_ifc_set_roce_address_in_bits {
3558 u8 opcode[0x10];
b4ff3a36 3559 u8 reserved_at_10[0x10];
e281682b 3560
b4ff3a36 3561 u8 reserved_at_20[0x10];
e281682b
SM		 3562 u8 op_mod[0x10];
3563
3564 u8 roce_address_index[0x10];
32f69e4b
DJ		 3565 u8 reserved_at_50[0xc];
3566 u8 vhca_port_num[0x4];
e281682b 3567
b4ff3a36 3568 u8 reserved_at_60[0x20];
e281682b
SM		 3569
3570 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3571};
3572
3573struct mlx5_ifc_set_mad_demux_out_bits {
3574 u8 status[0x8];
b4ff3a36 3575 u8 reserved_at_8[0x18];
e281682b
SM		 3576
3577 u8 syndrome[0x20];
3578
b4ff3a36 3579 u8 reserved_at_40[0x40];
e281682b
SM		 3580};
3581
3582enum {
3583 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3584 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3585};
3586
3587struct mlx5_ifc_set_mad_demux_in_bits {
3588 u8 opcode[0x10];
b4ff3a36 3589 u8 reserved_at_10[0x10];
e281682b 3590
b4ff3a36 3591 u8 reserved_at_20[0x10];
e281682b
SM		 3592 u8 op_mod[0x10];
3593
b4ff3a36 3594 u8 reserved_at_40[0x20];
e281682b 3595
b4ff3a36 3596 u8 reserved_at_60[0x6];
e281682b 3597 u8 demux_mode[0x2];
b4ff3a36 3598 u8 reserved_at_68[0x18];
e281682b
SM		 3599};
3600
3601struct mlx5_ifc_set_l2_table_entry_out_bits {
3602 u8 status[0x8];
b4ff3a36 3603 u8 reserved_at_8[0x18];
e281682b
SM		 3604
3605 u8 syndrome[0x20];
3606
b4ff3a36 3607 u8 reserved_at_40[0x40];
e281682b
SM		 3608};
3609
3610struct mlx5_ifc_set_l2_table_entry_in_bits {
3611 u8 opcode[0x10];
b4ff3a36 3612 u8 reserved_at_10[0x10];
e281682b 3613
b4ff3a36 3614 u8 reserved_at_20[0x10];
e281682b
SM		 3615 u8 op_mod[0x10];
3616
b4ff3a36 3617 u8 reserved_at_40[0x60];
e281682b 3618
b4ff3a36 3619 u8 reserved_at_a0[0x8];
e281682b
SM		 3620 u8 table_index[0x18];
3621
b4ff3a36 3622 u8 reserved_at_c0[0x20];
e281682b 3623
b4ff3a36 3624 u8 reserved_at_e0[0x13];
e281682b
SM		 3625 u8 vlan_valid[0x1];
3626 u8 vlan[0xc];
3627
3628 struct mlx5_ifc_mac_address_layout_bits mac_address;
3629
b4ff3a36 3630 u8 reserved_at_140[0xc0];
e281682b
SM		 3631};
3632
3633struct mlx5_ifc_set_issi_out_bits {
3634 u8 status[0x8];
b4ff3a36 3635 u8 reserved_at_8[0x18];
e281682b
SM		 3636
3637 u8 syndrome[0x20];
3638
b4ff3a36 3639 u8 reserved_at_40[0x40];
e281682b
SM		 3640};
3641
3642struct mlx5_ifc_set_issi_in_bits {
3643 u8 opcode[0x10];
b4ff3a36 3644 u8 reserved_at_10[0x10];
e281682b 3645
b4ff3a36 3646 u8 reserved_at_20[0x10];
e281682b
SM		 3647 u8 op_mod[0x10];
3648
b4ff3a36 3649 u8 reserved_at_40[0x10];
e281682b
SM		 3650 u8 current_issi[0x10];
3651
b4ff3a36 3652 u8 reserved_at_60[0x20];
e281682b
SM		 3653};
3654
3655struct mlx5_ifc_set_hca_cap_out_bits {
3656 u8 status[0x8];
b4ff3a36 3657 u8 reserved_at_8[0x18];
e281682b
SM		 3658
3659 u8 syndrome[0x20];
3660
b4ff3a36 3661 u8 reserved_at_40[0x40];
e281682b
SM		 3662};
3663
3664struct mlx5_ifc_set_hca_cap_in_bits {
3665 u8 opcode[0x10];
b4ff3a36 3666 u8 reserved_at_10[0x10];
e281682b 3667
b4ff3a36 3668 u8 reserved_at_20[0x10];
e281682b
SM		 3669 u8 op_mod[0x10];
3670
b4ff3a36 3671 u8 reserved_at_40[0x40];
e281682b
SM		 3672
3673 union mlx5_ifc_hca_cap_union_bits capability;
3674};
3675
26a81453
MG		 3676enum {
3677 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3678 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3679 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3680 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3681};
3682
e281682b
SM		 3683struct mlx5_ifc_set_fte_out_bits {
3684 u8 status[0x8];
b4ff3a36 3685 u8 reserved_at_8[0x18];
e281682b
SM		 3686
3687 u8 syndrome[0x20];
3688
b4ff3a36 3689 u8 reserved_at_40[0x40];
e281682b
SM		 3690};
3691
3692struct mlx5_ifc_set_fte_in_bits {
3693 u8 opcode[0x10];
b4ff3a36 3694 u8 reserved_at_10[0x10];
e281682b 3695
b4ff3a36 3696 u8 reserved_at_20[0x10];
e281682b
SM		 3697 u8 op_mod[0x10];
3698
7d5e1423
SM		 3699 u8 other_vport[0x1];
3700 u8 reserved_at_41[0xf];
3701 u8 vport_number[0x10];
3702
3703 u8 reserved_at_60[0x20];
e281682b
SM		 3704
3705 u8 table_type[0x8];
b4ff3a36 3706 u8 reserved_at_88[0x18];
e281682b 3707
b4ff3a36 3708 u8 reserved_at_a0[0x8];
e281682b
SM		 3709 u8 table_id[0x18];
3710
b4ff3a36 3711 u8 reserved_at_c0[0x18];
26a81453
MG		 3712 u8 modify_enable_mask[0x8];
3713
b4ff3a36 3714 u8 reserved_at_e0[0x20];
e281682b
SM		 3715
3716 u8 flow_index[0x20];
3717
b4ff3a36 3718 u8 reserved_at_120[0xe0];
e281682b
SM		 3719
3720 struct mlx5_ifc_flow_context_bits flow_context;
3721};
3722
3723struct mlx5_ifc_rts2rts_qp_out_bits {
3724 u8 status[0x8];
b4ff3a36 3725 u8 reserved_at_8[0x18];
e281682b
SM		 3726
3727 u8 syndrome[0x20];
3728
b4ff3a36 3729 u8 reserved_at_40[0x40];
e281682b
SM		 3730};
3731
3732struct mlx5_ifc_rts2rts_qp_in_bits {
3733 u8 opcode[0x10];
4ac63ec7 3734 u8 uid[0x10];
e281682b 3735
b4ff3a36 3736 u8 reserved_at_20[0x10];
e281682b
SM		 3737 u8 op_mod[0x10];
3738
b4ff3a36 3739 u8 reserved_at_40[0x8];
e281682b
SM		 3740 u8 qpn[0x18];
3741
b4ff3a36 3742 u8 reserved_at_60[0x20];
e281682b
SM		 3743
3744 u8 opt_param_mask[0x20];
3745
b4ff3a36 3746 u8 reserved_at_a0[0x20];
e281682b
SM		 3747
3748 struct mlx5_ifc_qpc_bits qpc;
3749
b4ff3a36 3750 u8 reserved_at_800[0x80];
e281682b
SM		 3751};
3752
3753struct mlx5_ifc_rtr2rts_qp_out_bits {
3754 u8 status[0x8];
b4ff3a36 3755 u8 reserved_at_8[0x18];
e281682b
SM		 3756
3757 u8 syndrome[0x20];
3758
b4ff3a36 3759 u8 reserved_at_40[0x40];
e281682b
SM		 3760};
3761
3762struct mlx5_ifc_rtr2rts_qp_in_bits {
3763 u8 opcode[0x10];
4ac63ec7 3764 u8 uid[0x10];
e281682b 3765
b4ff3a36 3766 u8 reserved_at_20[0x10];
e281682b
SM		 3767 u8 op_mod[0x10];
3768
b4ff3a36 3769 u8 reserved_at_40[0x8];
e281682b
SM		 3770 u8 qpn[0x18];
3771
b4ff3a36 3772 u8 reserved_at_60[0x20];
e281682b
SM		 3773
3774 u8 opt_param_mask[0x20];
3775
b4ff3a36 3776 u8 reserved_at_a0[0x20];
e281682b
SM		 3777
3778 struct mlx5_ifc_qpc_bits qpc;
3779
b4ff3a36 3780 u8 reserved_at_800[0x80];
e281682b
SM		 3781};
3782
3783struct mlx5_ifc_rst2init_qp_out_bits {
3784 u8 status[0x8];
b4ff3a36 3785 u8 reserved_at_8[0x18];
e281682b
SM		 3786
3787 u8 syndrome[0x20];
3788
b4ff3a36 3789 u8 reserved_at_40[0x40];
e281682b
SM		 3790};
3791
3792struct mlx5_ifc_rst2init_qp_in_bits {
3793 u8 opcode[0x10];
4ac63ec7 3794 u8 uid[0x10];
e281682b 3795
b4ff3a36 3796 u8 reserved_at_20[0x10];
e281682b
SM		 3797 u8 op_mod[0x10];
3798
b4ff3a36 3799 u8 reserved_at_40[0x8];
e281682b
SM		 3800 u8 qpn[0x18];
3801
b4ff3a36 3802 u8 reserved_at_60[0x20];
e281682b
SM		 3803
3804 u8 opt_param_mask[0x20];
3805
b4ff3a36 3806 u8 reserved_at_a0[0x20];
e281682b
SM		 3807
3808 struct mlx5_ifc_qpc_bits qpc;
3809
b4ff3a36 3810 u8 reserved_at_800[0x80];
e281682b
SM		 3811};
3812
7486216b
SM		 3813struct mlx5_ifc_query_xrq_out_bits {
3814 u8 status[0x8];
3815 u8 reserved_at_8[0x18];
3816
3817 u8 syndrome[0x20];
3818
3819 u8 reserved_at_40[0x40];
3820
3821 struct mlx5_ifc_xrqc_bits xrq_context;
3822};
3823
3824struct mlx5_ifc_query_xrq_in_bits {
3825 u8 opcode[0x10];
3826 u8 reserved_at_10[0x10];
3827
3828 u8 reserved_at_20[0x10];
3829 u8 op_mod[0x10];
3830
3831 u8 reserved_at_40[0x8];
3832 u8 xrqn[0x18];
3833
3834 u8 reserved_at_60[0x20];
3835};
3836
e281682b
SM		 3837struct mlx5_ifc_query_xrc_srq_out_bits {
3838 u8 status[0x8];
b4ff3a36 3839 u8 reserved_at_8[0x18];
e281682b
SM		 3840
3841 u8 syndrome[0x20];
3842
b4ff3a36 3843 u8 reserved_at_40[0x40];
e281682b
SM		 3844
3845 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3846
b4ff3a36 3847 u8 reserved_at_280[0x600];
e281682b
SM		 3848
3849 u8 pas[0][0x40];
3850};
3851
3852struct mlx5_ifc_query_xrc_srq_in_bits {
3853 u8 opcode[0x10];
b4ff3a36 3854 u8 reserved_at_10[0x10];
e281682b 3855
b4ff3a36 3856 u8 reserved_at_20[0x10];
e281682b
SM		 3857 u8 op_mod[0x10];
3858
b4ff3a36 3859 u8 reserved_at_40[0x8];
e281682b
SM		 3860 u8 xrc_srqn[0x18];
3861
b4ff3a36 3862 u8 reserved_at_60[0x20];
e281682b
SM		 3863};
3864
3865enum {
3866 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3867 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3868};
3869
3870struct mlx5_ifc_query_vport_state_out_bits {
3871 u8 status[0x8];
b4ff3a36 3872 u8 reserved_at_8[0x18];
e281682b
SM		 3873
3874 u8 syndrome[0x20];
3875
b4ff3a36 3876 u8 reserved_at_40[0x20];
e281682b 3877
b4ff3a36 3878 u8 reserved_at_60[0x18];
e281682b
SM		 3879 u8 admin_state[0x4];
3880 u8 state[0x4];
3881};
3882
3883enum {
cc9c82a8
EBE		 3884 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
3885 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3886};
3887
fd4572b3
ED		 3888struct mlx5_ifc_arm_monitor_counter_in_bits {
3889 u8 opcode[0x10];
3890 u8 uid[0x10];
3891
3892 u8 reserved_at_20[0x10];
3893 u8 op_mod[0x10];
3894
3895 u8 reserved_at_40[0x20];
3896
3897 u8 reserved_at_60[0x20];
3898};
3899
3900struct mlx5_ifc_arm_monitor_counter_out_bits {
3901 u8 status[0x8];
3902 u8 reserved_at_8[0x18];
3903
3904 u8 syndrome[0x20];
3905
3906 u8 reserved_at_40[0x40];
3907};
3908
3909enum {
3910 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
3911 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
3912};
3913
3914enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 3915 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
3916 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
3917 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
3918 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
3919 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
3920 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 3921};
3922
3923enum {
4c8b8518 3924 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 3925};
3926
3927struct mlx5_ifc_monitor_counter_output_bits {
3928 u8 reserved_at_0[0x4];
3929 u8 type[0x4];
3930 u8 reserved_at_8[0x8];
3931 u8 counter[0x10];
3932
3933 u8 counter_group_id[0x20];
3934};
3935
3936#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
3937#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
3938#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
3939 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
3940
3941struct mlx5_ifc_set_monitor_counter_in_bits {
3942 u8 opcode[0x10];
3943 u8 uid[0x10];
3944
3945 u8 reserved_at_20[0x10];
3946 u8 op_mod[0x10];
3947
3948 u8 reserved_at_40[0x10];
3949 u8 num_of_counters[0x10];
3950
3951 u8 reserved_at_60[0x20];
3952
3953 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
3954};
3955
3956struct mlx5_ifc_set_monitor_counter_out_bits {
3957 u8 status[0x8];
3958 u8 reserved_at_8[0x18];
3959
3960 u8 syndrome[0x20];
3961
3962 u8 reserved_at_40[0x40];
3963};
3964
e281682b
SM		 3965struct mlx5_ifc_query_vport_state_in_bits {
3966 u8 opcode[0x10];
b4ff3a36 3967 u8 reserved_at_10[0x10];
e281682b 3968
b4ff3a36 3969 u8 reserved_at_20[0x10];
e281682b
SM		 3970 u8 op_mod[0x10];
3971
3972 u8 other_vport[0x1];
b4ff3a36 3973 u8 reserved_at_41[0xf];
e281682b
SM		 3974 u8 vport_number[0x10];
3975
b4ff3a36 3976 u8 reserved_at_60[0x20];
e281682b
SM		 3977};
3978
61c5b5c9
MS		 3979struct mlx5_ifc_query_vnic_env_out_bits {
3980 u8 status[0x8];
3981 u8 reserved_at_8[0x18];
3982
3983 u8 syndrome[0x20];
3984
3985 u8 reserved_at_40[0x40];
3986
3987 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3988};
3989
3990enum {
3991 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3992};
3993
3994struct mlx5_ifc_query_vnic_env_in_bits {
3995 u8 opcode[0x10];
3996 u8 reserved_at_10[0x10];
3997
3998 u8 reserved_at_20[0x10];
3999 u8 op_mod[0x10];
4000
4001 u8 other_vport[0x1];
4002 u8 reserved_at_41[0xf];
4003 u8 vport_number[0x10];
4004
4005 u8 reserved_at_60[0x20];
4006};
4007
e281682b
SM		 4008struct mlx5_ifc_query_vport_counter_out_bits {
4009 u8 status[0x8];
b4ff3a36 4010 u8 reserved_at_8[0x18];
e281682b
SM		 4011
4012 u8 syndrome[0x20];
4013
b4ff3a36 4014 u8 reserved_at_40[0x40];
e281682b
SM		 4015
4016 struct mlx5_ifc_traffic_counter_bits received_errors;
4017
4018 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4019
4020 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4021
4022 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4023
4024 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4025
4026 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4027
4028 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4029
4030 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4031
4032 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4033
4034 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4035
4036 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4037
4038 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4039
b4ff3a36 4040 u8 reserved_at_680[0xa00];
e281682b
SM		 4041};
4042
4043enum {
4044 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4045};
4046
4047struct mlx5_ifc_query_vport_counter_in_bits {
4048 u8 opcode[0x10];
b4ff3a36 4049 u8 reserved_at_10[0x10];
e281682b 4050
b4ff3a36 4051 u8 reserved_at_20[0x10];
e281682b
SM		 4052 u8 op_mod[0x10];
4053
4054 u8 other_vport[0x1];
b54ba277
MY		 4055 u8 reserved_at_41[0xb];
4056 u8 port_num[0x4];
e281682b
SM		 4057 u8 vport_number[0x10];
4058
b4ff3a36 4059 u8 reserved_at_60[0x60];
e281682b
SM		 4060
4061 u8 clear[0x1];
b4ff3a36 4062 u8 reserved_at_c1[0x1f];
e281682b 4063
b4ff3a36 4064 u8 reserved_at_e0[0x20];
e281682b
SM		 4065};
4066
4067struct mlx5_ifc_query_tis_out_bits {
4068 u8 status[0x8];
b4ff3a36 4069 u8 reserved_at_8[0x18];
e281682b
SM		 4070
4071 u8 syndrome[0x20];
4072
b4ff3a36 4073 u8 reserved_at_40[0x40];
e281682b
SM		 4074
4075 struct mlx5_ifc_tisc_bits tis_context;
4076};
4077
4078struct mlx5_ifc_query_tis_in_bits {
4079 u8 opcode[0x10];
b4ff3a36 4080 u8 reserved_at_10[0x10];
e281682b 4081
b4ff3a36 4082 u8 reserved_at_20[0x10];
e281682b
SM		 4083 u8 op_mod[0x10];
4084
b4ff3a36 4085 u8 reserved_at_40[0x8];
e281682b
SM		 4086 u8 tisn[0x18];
4087
b4ff3a36 4088 u8 reserved_at_60[0x20];
e281682b
SM		 4089};
4090
4091struct mlx5_ifc_query_tir_out_bits {
4092 u8 status[0x8];
b4ff3a36 4093 u8 reserved_at_8[0x18];
e281682b
SM		 4094
4095 u8 syndrome[0x20];
4096
b4ff3a36 4097 u8 reserved_at_40[0xc0];
e281682b
SM		 4098
4099 struct mlx5_ifc_tirc_bits tir_context;
4100};
4101
4102struct mlx5_ifc_query_tir_in_bits {
4103 u8 opcode[0x10];
b4ff3a36 4104 u8 reserved_at_10[0x10];
e281682b 4105
b4ff3a36 4106 u8 reserved_at_20[0x10];
e281682b
SM		 4107 u8 op_mod[0x10];
4108
b4ff3a36 4109 u8 reserved_at_40[0x8];
e281682b
SM		 4110 u8 tirn[0x18];
4111
b4ff3a36 4112 u8 reserved_at_60[0x20];
e281682b
SM		 4113};
4114
4115struct mlx5_ifc_query_srq_out_bits {
4116 u8 status[0x8];
b4ff3a36 4117 u8 reserved_at_8[0x18];
e281682b
SM		 4118
4119 u8 syndrome[0x20];
4120
b4ff3a36 4121 u8 reserved_at_40[0x40];
e281682b
SM		 4122
4123 struct mlx5_ifc_srqc_bits srq_context_entry;
4124
b4ff3a36 4125 u8 reserved_at_280[0x600];
e281682b
SM		 4126
4127 u8 pas[0][0x40];
4128};
4129
4130struct mlx5_ifc_query_srq_in_bits {
4131 u8 opcode[0x10];
b4ff3a36 4132 u8 reserved_at_10[0x10];
e281682b 4133
b4ff3a36 4134 u8 reserved_at_20[0x10];
e281682b
SM		 4135 u8 op_mod[0x10];
4136
b4ff3a36 4137 u8 reserved_at_40[0x8];
e281682b
SM		 4138 u8 srqn[0x18];
4139
b4ff3a36 4140 u8 reserved_at_60[0x20];
e281682b
SM		 4141};
4142
4143struct mlx5_ifc_query_sq_out_bits {
4144 u8 status[0x8];
b4ff3a36 4145 u8 reserved_at_8[0x18];
e281682b
SM		 4146
4147 u8 syndrome[0x20];
4148
b4ff3a36 4149 u8 reserved_at_40[0xc0];
e281682b
SM		 4150
4151 struct mlx5_ifc_sqc_bits sq_context;
4152};
4153
4154struct mlx5_ifc_query_sq_in_bits {
4155 u8 opcode[0x10];
b4ff3a36 4156 u8 reserved_at_10[0x10];
e281682b 4157
b4ff3a36 4158 u8 reserved_at_20[0x10];
e281682b
SM		 4159 u8 op_mod[0x10];
4160
b4ff3a36 4161 u8 reserved_at_40[0x8];
e281682b
SM		 4162 u8 sqn[0x18];
4163
b4ff3a36 4164 u8 reserved_at_60[0x20];
e281682b
SM		 4165};
4166
4167struct mlx5_ifc_query_special_contexts_out_bits {
4168 u8 status[0x8];
b4ff3a36 4169 u8 reserved_at_8[0x18];
e281682b
SM		 4170
4171 u8 syndrome[0x20];
4172
ec22eb53 4173 u8 dump_fill_mkey[0x20];
e281682b
SM		 4174
4175 u8 resd_lkey[0x20];
bcda1aca
AK		 4176
4177 u8 null_mkey[0x20];
4178
4179 u8 reserved_at_a0[0x60];
e281682b
SM		 4180};
4181
4182struct mlx5_ifc_query_special_contexts_in_bits {
4183 u8 opcode[0x10];
b4ff3a36 4184 u8 reserved_at_10[0x10];
e281682b 4185
b4ff3a36 4186 u8 reserved_at_20[0x10];
e281682b
SM		 4187 u8 op_mod[0x10];
4188
b4ff3a36 4189 u8 reserved_at_40[0x40];
e281682b
SM		 4190};
4191
813f8540
MHY		 4192struct mlx5_ifc_query_scheduling_element_out_bits {
4193 u8 opcode[0x10];
4194 u8 reserved_at_10[0x10];
4195
4196 u8 reserved_at_20[0x10];
4197 u8 op_mod[0x10];
4198
4199 u8 reserved_at_40[0xc0];
4200
4201 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4202
4203 u8 reserved_at_300[0x100];
4204};
4205
4206enum {
4207 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4208};
4209
4210struct mlx5_ifc_query_scheduling_element_in_bits {
4211 u8 opcode[0x10];
4212 u8 reserved_at_10[0x10];
4213
4214 u8 reserved_at_20[0x10];
4215 u8 op_mod[0x10];
4216
4217 u8 scheduling_hierarchy[0x8];
4218 u8 reserved_at_48[0x18];
4219
4220 u8 scheduling_element_id[0x20];
4221
4222 u8 reserved_at_80[0x180];
4223};
4224
e281682b
SM		 4225struct mlx5_ifc_query_rqt_out_bits {
4226 u8 status[0x8];
b4ff3a36 4227 u8 reserved_at_8[0x18];
e281682b
SM		 4228
4229 u8 syndrome[0x20];
4230
b4ff3a36 4231 u8 reserved_at_40[0xc0];
e281682b
SM		 4232
4233 struct mlx5_ifc_rqtc_bits rqt_context;
4234};
4235
4236struct mlx5_ifc_query_rqt_in_bits {
4237 u8 opcode[0x10];
b4ff3a36 4238 u8 reserved_at_10[0x10];
e281682b 4239
b4ff3a36 4240 u8 reserved_at_20[0x10];
e281682b
SM		 4241 u8 op_mod[0x10];
4242
b4ff3a36 4243 u8 reserved_at_40[0x8];
e281682b
SM		 4244 u8 rqtn[0x18];
4245
b4ff3a36 4246 u8 reserved_at_60[0x20];
e281682b
SM		 4247};
4248
4249struct mlx5_ifc_query_rq_out_bits {
4250 u8 status[0x8];
b4ff3a36 4251 u8 reserved_at_8[0x18];
e281682b
SM		 4252
4253 u8 syndrome[0x20];
4254
b4ff3a36 4255 u8 reserved_at_40[0xc0];
e281682b
SM		 4256
4257 struct mlx5_ifc_rqc_bits rq_context;
4258};
4259
4260struct mlx5_ifc_query_rq_in_bits {
4261 u8 opcode[0x10];
b4ff3a36 4262 u8 reserved_at_10[0x10];
e281682b 4263
b4ff3a36 4264 u8 reserved_at_20[0x10];
e281682b
SM		 4265 u8 op_mod[0x10];
4266
b4ff3a36 4267 u8 reserved_at_40[0x8];
e281682b
SM		 4268 u8 rqn[0x18];
4269
b4ff3a36 4270 u8 reserved_at_60[0x20];
e281682b
SM		 4271};
4272
4273struct mlx5_ifc_query_roce_address_out_bits {
4274 u8 status[0x8];
b4ff3a36 4275 u8 reserved_at_8[0x18];
e281682b
SM		 4276
4277 u8 syndrome[0x20];
4278
b4ff3a36 4279 u8 reserved_at_40[0x40];
e281682b
SM		 4280
4281 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4282};
4283
4284struct mlx5_ifc_query_roce_address_in_bits {
4285 u8 opcode[0x10];
b4ff3a36 4286 u8 reserved_at_10[0x10];
e281682b 4287
b4ff3a36 4288 u8 reserved_at_20[0x10];
e281682b
SM		 4289 u8 op_mod[0x10];
4290
4291 u8 roce_address_index[0x10];
32f69e4b
DJ		 4292 u8 reserved_at_50[0xc];
4293 u8 vhca_port_num[0x4];
e281682b 4294
b4ff3a36 4295 u8 reserved_at_60[0x20];
e281682b
SM		 4296};
4297
4298struct mlx5_ifc_query_rmp_out_bits {
4299 u8 status[0x8];
b4ff3a36 4300 u8 reserved_at_8[0x18];
e281682b
SM		 4301
4302 u8 syndrome[0x20];
4303
b4ff3a36 4304 u8 reserved_at_40[0xc0];
e281682b
SM		 4305
4306 struct mlx5_ifc_rmpc_bits rmp_context;
4307};
4308
4309struct mlx5_ifc_query_rmp_in_bits {
4310 u8 opcode[0x10];
b4ff3a36 4311 u8 reserved_at_10[0x10];
e281682b 4312
b4ff3a36 4313 u8 reserved_at_20[0x10];
e281682b
SM		 4314 u8 op_mod[0x10];
4315
b4ff3a36 4316 u8 reserved_at_40[0x8];
e281682b
SM		 4317 u8 rmpn[0x18];
4318
b4ff3a36 4319 u8 reserved_at_60[0x20];
e281682b
SM		 4320};
4321
4322struct mlx5_ifc_query_qp_out_bits {
4323 u8 status[0x8];
b4ff3a36 4324 u8 reserved_at_8[0x18];
e281682b
SM		 4325
4326 u8 syndrome[0x20];
4327
b4ff3a36 4328 u8 reserved_at_40[0x40];
e281682b
SM		 4329
4330 u8 opt_param_mask[0x20];
4331
b4ff3a36 4332 u8 reserved_at_a0[0x20];
e281682b
SM		 4333
4334 struct mlx5_ifc_qpc_bits qpc;
4335
b4ff3a36 4336 u8 reserved_at_800[0x80];
e281682b
SM		 4337
4338 u8 pas[0][0x40];
4339};
4340
4341struct mlx5_ifc_query_qp_in_bits {
4342 u8 opcode[0x10];
b4ff3a36 4343 u8 reserved_at_10[0x10];
e281682b 4344
b4ff3a36 4345 u8 reserved_at_20[0x10];
e281682b
SM		 4346 u8 op_mod[0x10];
4347
b4ff3a36 4348 u8 reserved_at_40[0x8];
e281682b
SM		 4349 u8 qpn[0x18];
4350
b4ff3a36 4351 u8 reserved_at_60[0x20];
e281682b
SM		 4352};
4353
4354struct mlx5_ifc_query_q_counter_out_bits {
4355 u8 status[0x8];
b4ff3a36 4356 u8 reserved_at_8[0x18];
e281682b
SM		 4357
4358 u8 syndrome[0x20];
4359
b4ff3a36 4360 u8 reserved_at_40[0x40];
e281682b
SM		 4361
4362 u8 rx_write_requests[0x20];
4363
b4ff3a36 4364 u8 reserved_at_a0[0x20];
e281682b
SM		 4365
4366 u8 rx_read_requests[0x20];
4367
b4ff3a36 4368 u8 reserved_at_e0[0x20];
e281682b
SM		 4369
4370 u8 rx_atomic_requests[0x20];
4371
b4ff3a36 4372 u8 reserved_at_120[0x20];
e281682b
SM		 4373
4374 u8 rx_dct_connect[0x20];
4375
b4ff3a36 4376 u8 reserved_at_160[0x20];
e281682b
SM		 4377
4378 u8 out_of_buffer[0x20];
4379
b4ff3a36 4380 u8 reserved_at_1a0[0x20];
e281682b
SM		 4381
4382 u8 out_of_sequence[0x20];
4383
7486216b
SM		 4384 u8 reserved_at_1e0[0x20];
4385
4386 u8 duplicate_request[0x20];
4387
4388 u8 reserved_at_220[0x20];
4389
4390 u8 rnr_nak_retry_err[0x20];
4391
4392 u8 reserved_at_260[0x20];
4393
4394 u8 packet_seq_err[0x20];
4395
4396 u8 reserved_at_2a0[0x20];
4397
4398 u8 implied_nak_seq_err[0x20];
4399
4400 u8 reserved_at_2e0[0x20];
4401
4402 u8 local_ack_timeout_err[0x20];
4403
58dcb60a
PP		 4404 u8 reserved_at_320[0xa0];
4405
4406 u8 resp_local_length_error[0x20];
4407
4408 u8 req_local_length_error[0x20];
4409
4410 u8 resp_local_qp_error[0x20];
4411
4412 u8 local_operation_error[0x20];
4413
4414 u8 resp_local_protection[0x20];
4415
4416 u8 req_local_protection[0x20];
4417
4418 u8 resp_cqe_error[0x20];
4419
4420 u8 req_cqe_error[0x20];
4421
4422 u8 req_mw_binding[0x20];
4423
4424 u8 req_bad_response[0x20];
4425
4426 u8 req_remote_invalid_request[0x20];
4427
4428 u8 resp_remote_invalid_request[0x20];
4429
4430 u8 req_remote_access_errors[0x20];
4431
4432 u8 resp_remote_access_errors[0x20];
4433
4434 u8 req_remote_operation_errors[0x20];
4435
4436 u8 req_transport_retries_exceeded[0x20];
4437
4438 u8 cq_overflow[0x20];
4439
4440 u8 resp_cqe_flush_error[0x20];
4441
4442 u8 req_cqe_flush_error[0x20];
4443
4444 u8 reserved_at_620[0x1e0];
e281682b
SM		 4445};
4446
4447struct mlx5_ifc_query_q_counter_in_bits {
4448 u8 opcode[0x10];
b4ff3a36 4449 u8 reserved_at_10[0x10];
e281682b 4450
b4ff3a36 4451 u8 reserved_at_20[0x10];
e281682b
SM		 4452 u8 op_mod[0x10];
4453
b4ff3a36 4454 u8 reserved_at_40[0x80];
e281682b
SM		 4455
4456 u8 clear[0x1];
b4ff3a36 4457 u8 reserved_at_c1[0x1f];
e281682b 4458
b4ff3a36 4459 u8 reserved_at_e0[0x18];
e281682b
SM		 4460 u8 counter_set_id[0x8];
4461};
4462
4463struct mlx5_ifc_query_pages_out_bits {
4464 u8 status[0x8];
b4ff3a36 4465 u8 reserved_at_8[0x18];
e281682b
SM		 4466
4467 u8 syndrome[0x20];
4468
591905ba
BW		 4469 u8 embedded_cpu_function[0x1];
4470 u8 reserved_at_41[0xf];
e281682b
SM		 4471 u8 function_id[0x10];
4472
4473 u8 num_pages[0x20];
4474};
4475
4476enum {
4477 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4478 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4479 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4480};
4481
4482struct mlx5_ifc_query_pages_in_bits {
4483 u8 opcode[0x10];
b4ff3a36 4484 u8 reserved_at_10[0x10];
e281682b 4485
b4ff3a36 4486 u8 reserved_at_20[0x10];
e281682b
SM		 4487 u8 op_mod[0x10];
4488
591905ba
BW		 4489 u8 embedded_cpu_function[0x1];
4490 u8 reserved_at_41[0xf];
e281682b
SM		 4491 u8 function_id[0x10];
4492
b4ff3a36 4493 u8 reserved_at_60[0x20];
e281682b
SM		 4494};
4495
4496struct mlx5_ifc_query_nic_vport_context_out_bits {
4497 u8 status[0x8];
b4ff3a36 4498 u8 reserved_at_8[0x18];
e281682b
SM		 4499
4500 u8 syndrome[0x20];
4501
b4ff3a36 4502 u8 reserved_at_40[0x40];
e281682b
SM		 4503
4504 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4505};
4506
4507struct mlx5_ifc_query_nic_vport_context_in_bits {
4508 u8 opcode[0x10];
b4ff3a36 4509 u8 reserved_at_10[0x10];
e281682b 4510
b4ff3a36 4511 u8 reserved_at_20[0x10];
e281682b
SM		 4512 u8 op_mod[0x10];
4513
4514 u8 other_vport[0x1];
b4ff3a36 4515 u8 reserved_at_41[0xf];
e281682b
SM		 4516 u8 vport_number[0x10];
4517
b4ff3a36 4518 u8 reserved_at_60[0x5];
e281682b 4519 u8 allowed_list_type[0x3];
b4ff3a36 4520 u8 reserved_at_68[0x18];
e281682b
SM		 4521};
4522
4523struct mlx5_ifc_query_mkey_out_bits {
4524 u8 status[0x8];
b4ff3a36 4525 u8 reserved_at_8[0x18];
e281682b
SM		 4526
4527 u8 syndrome[0x20];
4528
b4ff3a36 4529 u8 reserved_at_40[0x40];
e281682b
SM		 4530
4531 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4532
b4ff3a36 4533 u8 reserved_at_280[0x600];
e281682b
SM		 4534
4535 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4536
4537 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4538};
4539
4540struct mlx5_ifc_query_mkey_in_bits {
4541 u8 opcode[0x10];
b4ff3a36 4542 u8 reserved_at_10[0x10];
e281682b 4543
b4ff3a36 4544 u8 reserved_at_20[0x10];
e281682b
SM		 4545 u8 op_mod[0x10];
4546
b4ff3a36 4547 u8 reserved_at_40[0x8];
e281682b
SM		 4548 u8 mkey_index[0x18];
4549
4550 u8 pg_access[0x1];
b4ff3a36 4551 u8 reserved_at_61[0x1f];
e281682b
SM		 4552};
4553
4554struct mlx5_ifc_query_mad_demux_out_bits {
4555 u8 status[0x8];
b4ff3a36 4556 u8 reserved_at_8[0x18];
e281682b
SM		 4557
4558 u8 syndrome[0x20];
4559
b4ff3a36 4560 u8 reserved_at_40[0x40];
e281682b
SM		 4561
4562 u8 mad_dumux_parameters_block[0x20];
4563};
4564
4565struct mlx5_ifc_query_mad_demux_in_bits {
4566 u8 opcode[0x10];
b4ff3a36 4567 u8 reserved_at_10[0x10];
e281682b 4568
b4ff3a36 4569 u8 reserved_at_20[0x10];
e281682b
SM		 4570 u8 op_mod[0x10];
4571
b4ff3a36 4572 u8 reserved_at_40[0x40];
e281682b
SM		 4573};
4574
4575struct mlx5_ifc_query_l2_table_entry_out_bits {
4576 u8 status[0x8];
b4ff3a36 4577 u8 reserved_at_8[0x18];
e281682b
SM		 4578
4579 u8 syndrome[0x20];
4580
b4ff3a36 4581 u8 reserved_at_40[0xa0];
e281682b 4582
b4ff3a36 4583 u8 reserved_at_e0[0x13];
e281682b
SM		 4584 u8 vlan_valid[0x1];
4585 u8 vlan[0xc];
4586
4587 struct mlx5_ifc_mac_address_layout_bits mac_address;
4588
b4ff3a36 4589 u8 reserved_at_140[0xc0];
e281682b
SM		 4590};
4591
4592struct mlx5_ifc_query_l2_table_entry_in_bits {
4593 u8 opcode[0x10];
b4ff3a36 4594 u8 reserved_at_10[0x10];
e281682b 4595
b4ff3a36 4596 u8 reserved_at_20[0x10];
e281682b
SM		 4597 u8 op_mod[0x10];
4598
b4ff3a36 4599 u8 reserved_at_40[0x60];
e281682b 4600
b4ff3a36 4601 u8 reserved_at_a0[0x8];
e281682b
SM		 4602 u8 table_index[0x18];
4603
b4ff3a36 4604 u8 reserved_at_c0[0x140];
e281682b
SM		 4605};
4606
4607struct mlx5_ifc_query_issi_out_bits {
4608 u8 status[0x8];
b4ff3a36 4609 u8 reserved_at_8[0x18];
e281682b
SM		 4610
4611 u8 syndrome[0x20];
4612
b4ff3a36 4613 u8 reserved_at_40[0x10];
e281682b
SM		 4614 u8 current_issi[0x10];
4615
b4ff3a36 4616 u8 reserved_at_60[0xa0];
e281682b 4617
b4ff3a36 4618 u8 reserved_at_100[76][0x8];
e281682b
SM		 4619 u8 supported_issi_dw0[0x20];
4620};
4621
4622struct mlx5_ifc_query_issi_in_bits {
4623 u8 opcode[0x10];
b4ff3a36 4624 u8 reserved_at_10[0x10];
e281682b 4625
b4ff3a36 4626 u8 reserved_at_20[0x10];
e281682b
SM		 4627 u8 op_mod[0x10];
4628
b4ff3a36 4629 u8 reserved_at_40[0x40];
e281682b
SM		 4630};
4631
0dbc6fe0
SM		 4632struct mlx5_ifc_set_driver_version_out_bits {
4633 u8 status[0x8];
4634 u8 reserved_0[0x18];
4635
4636 u8 syndrome[0x20];
4637 u8 reserved_1[0x40];
4638};
4639
4640struct mlx5_ifc_set_driver_version_in_bits {
4641 u8 opcode[0x10];
4642 u8 reserved_0[0x10];
4643
4644 u8 reserved_1[0x10];
4645 u8 op_mod[0x10];
4646
4647 u8 reserved_2[0x40];
4648 u8 driver_version[64][0x8];
4649};
4650
e281682b
SM		 4651struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4652 u8 status[0x8];
b4ff3a36 4653 u8 reserved_at_8[0x18];
e281682b
SM		 4654
4655 u8 syndrome[0x20];
4656
b4ff3a36 4657 u8 reserved_at_40[0x40];
e281682b
SM		 4658
4659 struct mlx5_ifc_pkey_bits pkey[0];
4660};
4661
4662struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4663 u8 opcode[0x10];
b4ff3a36 4664 u8 reserved_at_10[0x10];
e281682b 4665
b4ff3a36 4666 u8 reserved_at_20[0x10];
e281682b
SM		 4667 u8 op_mod[0x10];
4668
4669 u8 other_vport[0x1];
b4ff3a36 4670 u8 reserved_at_41[0xb];
707c4602 4671 u8 port_num[0x4];
e281682b
SM		 4672 u8 vport_number[0x10];
4673
b4ff3a36 4674 u8 reserved_at_60[0x10];
e281682b
SM		 4675 u8 pkey_index[0x10];
4676};
4677
eff901d3
EC		 4678enum {
4679 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4680 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4681 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4682};
4683
e281682b
SM		 4684struct mlx5_ifc_query_hca_vport_gid_out_bits {
4685 u8 status[0x8];
b4ff3a36 4686 u8 reserved_at_8[0x18];
e281682b
SM		 4687
4688 u8 syndrome[0x20];
4689
b4ff3a36 4690 u8 reserved_at_40[0x20];
e281682b
SM		 4691
4692 u8 gids_num[0x10];
b4ff3a36 4693 u8 reserved_at_70[0x10];
e281682b
SM		 4694
4695 struct mlx5_ifc_array128_auto_bits gid[0];
4696};
4697
4698struct mlx5_ifc_query_hca_vport_gid_in_bits {
4699 u8 opcode[0x10];
b4ff3a36 4700 u8 reserved_at_10[0x10];
e281682b 4701
b4ff3a36 4702 u8 reserved_at_20[0x10];
e281682b
SM		 4703 u8 op_mod[0x10];
4704
4705 u8 other_vport[0x1];
b4ff3a36 4706 u8 reserved_at_41[0xb];
707c4602 4707 u8 port_num[0x4];
e281682b
SM		 4708 u8 vport_number[0x10];
4709
b4ff3a36 4710 u8 reserved_at_60[0x10];
e281682b
SM		 4711 u8 gid_index[0x10];
4712};
4713
4714struct mlx5_ifc_query_hca_vport_context_out_bits {
4715 u8 status[0x8];
b4ff3a36 4716 u8 reserved_at_8[0x18];
e281682b
SM		 4717
4718 u8 syndrome[0x20];
4719
b4ff3a36 4720 u8 reserved_at_40[0x40];
e281682b
SM		 4721
4722 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4723};
4724
4725struct mlx5_ifc_query_hca_vport_context_in_bits {
4726 u8 opcode[0x10];
b4ff3a36 4727 u8 reserved_at_10[0x10];
e281682b 4728
b4ff3a36 4729 u8 reserved_at_20[0x10];
e281682b
SM		 4730 u8 op_mod[0x10];
4731
4732 u8 other_vport[0x1];
b4ff3a36 4733 u8 reserved_at_41[0xb];
707c4602 4734 u8 port_num[0x4];
e281682b
SM		 4735 u8 vport_number[0x10];
4736
b4ff3a36 4737 u8 reserved_at_60[0x20];
e281682b
SM		 4738};
4739
4740struct mlx5_ifc_query_hca_cap_out_bits {
4741 u8 status[0x8];
b4ff3a36 4742 u8 reserved_at_8[0x18];
e281682b
SM		 4743
4744 u8 syndrome[0x20];
4745
b4ff3a36 4746 u8 reserved_at_40[0x40];
e281682b
SM		 4747
4748 union mlx5_ifc_hca_cap_union_bits capability;
4749};
4750
4751struct mlx5_ifc_query_hca_cap_in_bits {
4752 u8 opcode[0x10];
b4ff3a36 4753 u8 reserved_at_10[0x10];
e281682b 4754
b4ff3a36 4755 u8 reserved_at_20[0x10];
e281682b
SM		 4756 u8 op_mod[0x10];
4757
b4ff3a36 4758 u8 reserved_at_40[0x40];
e281682b
SM		 4759};
4760
4761struct mlx5_ifc_query_flow_table_out_bits {
4762 u8 status[0x8];
b4ff3a36 4763 u8 reserved_at_8[0x18];
e281682b
SM		 4764
4765 u8 syndrome[0x20];
4766
b4ff3a36 4767 u8 reserved_at_40[0x80];
e281682b 4768
b4ff3a36 4769 u8 reserved_at_c0[0x8];
e281682b 4770 u8 level[0x8];
b4ff3a36 4771 u8 reserved_at_d0[0x8];
e281682b
SM		 4772 u8 log_size[0x8];
4773
b4ff3a36 4774 u8 reserved_at_e0[0x120];
e281682b
SM		 4775};
4776
4777struct mlx5_ifc_query_flow_table_in_bits {
4778 u8 opcode[0x10];
b4ff3a36 4779 u8 reserved_at_10[0x10];
e281682b 4780
b4ff3a36 4781 u8 reserved_at_20[0x10];
e281682b
SM		 4782 u8 op_mod[0x10];
4783
b4ff3a36 4784 u8 reserved_at_40[0x40];
e281682b
SM		 4785
4786 u8 table_type[0x8];
b4ff3a36 4787 u8 reserved_at_88[0x18];
e281682b 4788
b4ff3a36 4789 u8 reserved_at_a0[0x8];
e281682b
SM		 4790 u8 table_id[0x18];
4791
b4ff3a36 4792 u8 reserved_at_c0[0x140];
e281682b
SM		 4793};
4794
4795struct mlx5_ifc_query_fte_out_bits {
4796 u8 status[0x8];
b4ff3a36 4797 u8 reserved_at_8[0x18];
e281682b
SM		 4798
4799 u8 syndrome[0x20];
4800
b4ff3a36 4801 u8 reserved_at_40[0x1c0];
e281682b
SM		 4802
4803 struct mlx5_ifc_flow_context_bits flow_context;
4804};
4805
4806struct mlx5_ifc_query_fte_in_bits {
4807 u8 opcode[0x10];
b4ff3a36 4808 u8 reserved_at_10[0x10];
e281682b 4809
b4ff3a36 4810 u8 reserved_at_20[0x10];
e281682b
SM		 4811 u8 op_mod[0x10];
4812
b4ff3a36 4813 u8 reserved_at_40[0x40];
e281682b
SM		 4814
4815 u8 table_type[0x8];
b4ff3a36 4816 u8 reserved_at_88[0x18];
e281682b 4817
b4ff3a36 4818 u8 reserved_at_a0[0x8];
e281682b
SM		 4819 u8 table_id[0x18];
4820
b4ff3a36 4821 u8 reserved_at_c0[0x40];
e281682b
SM		 4822
4823 u8 flow_index[0x20];
4824
b4ff3a36 4825 u8 reserved_at_120[0xe0];
e281682b
SM		 4826};
4827
4828enum {
4829 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4830 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4831 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 4832 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 4833};
4834
4835struct mlx5_ifc_query_flow_group_out_bits {
4836 u8 status[0x8];
b4ff3a36 4837 u8 reserved_at_8[0x18];
e281682b
SM		 4838
4839 u8 syndrome[0x20];
4840
b4ff3a36 4841 u8 reserved_at_40[0xa0];
e281682b
SM		 4842
4843 u8 start_flow_index[0x20];
4844
b4ff3a36 4845 u8 reserved_at_100[0x20];
e281682b
SM		 4846
4847 u8 end_flow_index[0x20];
4848
b4ff3a36 4849 u8 reserved_at_140[0xa0];
e281682b 4850
b4ff3a36 4851 u8 reserved_at_1e0[0x18];
e281682b
SM		 4852 u8 match_criteria_enable[0x8];
4853
4854 struct mlx5_ifc_fte_match_param_bits match_criteria;
4855
b4ff3a36 4856 u8 reserved_at_1200[0xe00];
e281682b
SM		 4857};
4858
4859struct mlx5_ifc_query_flow_group_in_bits {
4860 u8 opcode[0x10];
b4ff3a36 4861 u8 reserved_at_10[0x10];
e281682b 4862
b4ff3a36 4863 u8 reserved_at_20[0x10];
e281682b
SM		 4864 u8 op_mod[0x10];
4865
b4ff3a36 4866 u8 reserved_at_40[0x40];
e281682b
SM		 4867
4868 u8 table_type[0x8];
b4ff3a36 4869 u8 reserved_at_88[0x18];
e281682b 4870
b4ff3a36 4871 u8 reserved_at_a0[0x8];
e281682b
SM		 4872 u8 table_id[0x18];
4873
4874 u8 group_id[0x20];
4875
b4ff3a36 4876 u8 reserved_at_e0[0x120];
e281682b
SM		 4877};
4878
9dc0b289
AV		 4879struct mlx5_ifc_query_flow_counter_out_bits {
4880 u8 status[0x8];
4881 u8 reserved_at_8[0x18];
4882
4883 u8 syndrome[0x20];
4884
4885 u8 reserved_at_40[0x40];
4886
4887 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4888};
4889
4890struct mlx5_ifc_query_flow_counter_in_bits {
4891 u8 opcode[0x10];
4892 u8 reserved_at_10[0x10];
4893
4894 u8 reserved_at_20[0x10];
4895 u8 op_mod[0x10];
4896
4897 u8 reserved_at_40[0x80];
4898
4899 u8 clear[0x1];
4900 u8 reserved_at_c1[0xf];
4901 u8 num_of_counters[0x10];
4902
a8ffcc74 4903 u8 flow_counter_id[0x20];
9dc0b289
AV		 4904};
4905
d6666753
SM		 4906struct mlx5_ifc_query_esw_vport_context_out_bits {
4907 u8 status[0x8];
b4ff3a36 4908 u8 reserved_at_8[0x18];
d6666753
SM		 4909
4910 u8 syndrome[0x20];
4911
b4ff3a36 4912 u8 reserved_at_40[0x40];
d6666753
SM		 4913
4914 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4915};
4916
4917struct mlx5_ifc_query_esw_vport_context_in_bits {
4918 u8 opcode[0x10];
b4ff3a36 4919 u8 reserved_at_10[0x10];
d6666753 4920
b4ff3a36 4921 u8 reserved_at_20[0x10];
d6666753
SM		 4922 u8 op_mod[0x10];
4923
4924 u8 other_vport[0x1];
b4ff3a36 4925 u8 reserved_at_41[0xf];
d6666753
SM		 4926 u8 vport_number[0x10];
4927
b4ff3a36 4928 u8 reserved_at_60[0x20];
d6666753
SM		 4929};
4930
4931struct mlx5_ifc_modify_esw_vport_context_out_bits {
4932 u8 status[0x8];
b4ff3a36 4933 u8 reserved_at_8[0x18];
d6666753
SM		 4934
4935 u8 syndrome[0x20];
4936
b4ff3a36 4937 u8 reserved_at_40[0x40];
d6666753
SM		 4938};
4939
4940struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4941 u8 reserved_at_0[0x1c];
d6666753
SM		 4942 u8 vport_cvlan_insert[0x1];
4943 u8 vport_svlan_insert[0x1];
4944 u8 vport_cvlan_strip[0x1];
4945 u8 vport_svlan_strip[0x1];
4946};
4947
4948struct mlx5_ifc_modify_esw_vport_context_in_bits {
4949 u8 opcode[0x10];
b4ff3a36 4950 u8 reserved_at_10[0x10];
d6666753 4951
b4ff3a36 4952 u8 reserved_at_20[0x10];
d6666753
SM		 4953 u8 op_mod[0x10];
4954
4955 u8 other_vport[0x1];
b4ff3a36 4956 u8 reserved_at_41[0xf];
d6666753
SM		 4957 u8 vport_number[0x10];
4958
4959 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4960
4961 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4962};
4963
e281682b
SM		 4964struct mlx5_ifc_query_eq_out_bits {
4965 u8 status[0x8];
b4ff3a36 4966 u8 reserved_at_8[0x18];
e281682b
SM		 4967
4968 u8 syndrome[0x20];
4969
b4ff3a36 4970 u8 reserved_at_40[0x40];
e281682b
SM		 4971
4972 struct mlx5_ifc_eqc_bits eq_context_entry;
4973
b4ff3a36 4974 u8 reserved_at_280[0x40];
e281682b
SM		 4975
4976 u8 event_bitmask[0x40];
4977
b4ff3a36 4978 u8 reserved_at_300[0x580];
e281682b
SM		 4979
4980 u8 pas[0][0x40];
4981};
4982
4983struct mlx5_ifc_query_eq_in_bits {
4984 u8 opcode[0x10];
b4ff3a36 4985 u8 reserved_at_10[0x10];
e281682b 4986
b4ff3a36 4987 u8 reserved_at_20[0x10];
e281682b
SM		 4988 u8 op_mod[0x10];
4989
b4ff3a36 4990 u8 reserved_at_40[0x18];
e281682b
SM		 4991 u8 eq_number[0x8];
4992
b4ff3a36 4993 u8 reserved_at_60[0x20];
e281682b
SM		 4994};
4995
60786f09 4996struct mlx5_ifc_packet_reformat_context_in_bits {
7adbde20 4997 u8 reserved_at_0[0x5];
60786f09 4998 u8 reformat_type[0x3];
7adbde20 4999 u8 reserved_at_8[0xe];
60786f09 5000 u8 reformat_data_size[0xa];
7adbde20
HHZ		 5001
5002 u8 reserved_at_20[0x10];
60786f09 5003 u8 reformat_data[2][0x8];
7adbde20 5004
60786f09 5005 u8 more_reformat_data[0][0x8];
7adbde20
HHZ		 5006};
5007
60786f09 5008struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 5009 u8 status[0x8];
5010 u8 reserved_at_8[0x18];
5011
5012 u8 syndrome[0x20];
5013
5014 u8 reserved_at_40[0xa0];
5015
60786f09 5016 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
7adbde20
HHZ		 5017};
5018
60786f09 5019struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 5020 u8 opcode[0x10];
5021 u8 reserved_at_10[0x10];
5022
5023 u8 reserved_at_20[0x10];
5024 u8 op_mod[0x10];
5025
60786f09 5026 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5027
5028 u8 reserved_at_60[0xa0];
5029};
5030
60786f09 5031struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5032 u8 status[0x8];
5033 u8 reserved_at_8[0x18];
5034
5035 u8 syndrome[0x20];
5036
60786f09 5037 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5038
5039 u8 reserved_at_60[0x20];
5040};
5041
e0e7a386 5042enum {
60786f09
MB		 5043 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5044 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 5045 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5046 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5047 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
e0e7a386
MB		 5048};
5049
60786f09 5050struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5051 u8 opcode[0x10];
5052 u8 reserved_at_10[0x10];
5053
5054 u8 reserved_at_20[0x10];
5055 u8 op_mod[0x10];
5056
5057 u8 reserved_at_40[0xa0];
5058
60786f09 5059 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 5060};
5061
60786f09 5062struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5063 u8 status[0x8];
5064 u8 reserved_at_8[0x18];
5065
5066 u8 syndrome[0x20];
5067
5068 u8 reserved_at_40[0x40];
5069};
5070
60786f09 5071struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5072 u8 opcode[0x10];
5073 u8 reserved_at_10[0x10];
5074
5075 u8 reserved_20[0x10];
5076 u8 op_mod[0x10];
5077
60786f09 5078 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5079
5080 u8 reserved_60[0x20];
5081};
5082
2a69cb9f
OG		 5083struct mlx5_ifc_set_action_in_bits {
5084 u8 action_type[0x4];
5085 u8 field[0xc];
5086 u8 reserved_at_10[0x3];
5087 u8 offset[0x5];
5088 u8 reserved_at_18[0x3];
5089 u8 length[0x5];
5090
5091 u8 data[0x20];
5092};
5093
5094struct mlx5_ifc_add_action_in_bits {
5095 u8 action_type[0x4];
5096 u8 field[0xc];
5097 u8 reserved_at_10[0x10];
5098
5099 u8 data[0x20];
5100};
5101
5102union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5103 struct mlx5_ifc_set_action_in_bits set_action_in;
5104 struct mlx5_ifc_add_action_in_bits add_action_in;
5105 u8 reserved_at_0[0x40];
5106};
5107
5108enum {
5109 MLX5_ACTION_TYPE_SET = 0x1,
5110 MLX5_ACTION_TYPE_ADD = 0x2,
5111};
5112
5113enum {
5114 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5115 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5116 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5117 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5118 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5119 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5120 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5121 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5122 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5123 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5124 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5125 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5126 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5127 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5128 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5129 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5130 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5131 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5132 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5133 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5134 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5135 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 5136 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 5137};
5138
5139struct mlx5_ifc_alloc_modify_header_context_out_bits {
5140 u8 status[0x8];
5141 u8 reserved_at_8[0x18];
5142
5143 u8 syndrome[0x20];
5144
5145 u8 modify_header_id[0x20];
5146
5147 u8 reserved_at_60[0x20];
5148};
5149
5150struct mlx5_ifc_alloc_modify_header_context_in_bits {
5151 u8 opcode[0x10];
5152 u8 reserved_at_10[0x10];
5153
5154 u8 reserved_at_20[0x10];
5155 u8 op_mod[0x10];
5156
5157 u8 reserved_at_40[0x20];
5158
5159 u8 table_type[0x8];
5160 u8 reserved_at_68[0x10];
5161 u8 num_of_actions[0x8];
5162
5163 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5164};
5165
5166struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5167 u8 status[0x8];
5168 u8 reserved_at_8[0x18];
5169
5170 u8 syndrome[0x20];
5171
5172 u8 reserved_at_40[0x40];
5173};
5174
5175struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5176 u8 opcode[0x10];
5177 u8 reserved_at_10[0x10];
5178
5179 u8 reserved_at_20[0x10];
5180 u8 op_mod[0x10];
5181
5182 u8 modify_header_id[0x20];
5183
5184 u8 reserved_at_60[0x20];
5185};
5186
e281682b
SM		 5187struct mlx5_ifc_query_dct_out_bits {
5188 u8 status[0x8];
b4ff3a36 5189 u8 reserved_at_8[0x18];
e281682b
SM		 5190
5191 u8 syndrome[0x20];
5192
b4ff3a36 5193 u8 reserved_at_40[0x40];
e281682b
SM		 5194
5195 struct mlx5_ifc_dctc_bits dct_context_entry;
5196
b4ff3a36 5197 u8 reserved_at_280[0x180];
e281682b
SM		 5198};
5199
5200struct mlx5_ifc_query_dct_in_bits {
5201 u8 opcode[0x10];
b4ff3a36 5202 u8 reserved_at_10[0x10];
e281682b 5203
b4ff3a36 5204 u8 reserved_at_20[0x10];
e281682b
SM		 5205 u8 op_mod[0x10];
5206
b4ff3a36 5207 u8 reserved_at_40[0x8];
e281682b
SM		 5208 u8 dctn[0x18];
5209
b4ff3a36 5210 u8 reserved_at_60[0x20];
e281682b
SM		 5211};
5212
5213struct mlx5_ifc_query_cq_out_bits {
5214 u8 status[0x8];
b4ff3a36 5215 u8 reserved_at_8[0x18];
e281682b
SM		 5216
5217 u8 syndrome[0x20];
5218
b4ff3a36 5219 u8 reserved_at_40[0x40];
e281682b
SM		 5220
5221 struct mlx5_ifc_cqc_bits cq_context;
5222
b4ff3a36 5223 u8 reserved_at_280[0x600];
e281682b
SM		 5224
5225 u8 pas[0][0x40];
5226};
5227
5228struct mlx5_ifc_query_cq_in_bits {
5229 u8 opcode[0x10];
b4ff3a36 5230 u8 reserved_at_10[0x10];
e281682b 5231
b4ff3a36 5232 u8 reserved_at_20[0x10];
e281682b
SM		 5233 u8 op_mod[0x10];
5234
b4ff3a36 5235 u8 reserved_at_40[0x8];
e281682b
SM		 5236 u8 cqn[0x18];
5237
b4ff3a36 5238 u8 reserved_at_60[0x20];
e281682b
SM		 5239};
5240
5241struct mlx5_ifc_query_cong_status_out_bits {
5242 u8 status[0x8];
b4ff3a36 5243 u8 reserved_at_8[0x18];
e281682b
SM		 5244
5245 u8 syndrome[0x20];
5246
b4ff3a36 5247 u8 reserved_at_40[0x20];
e281682b
SM		 5248
5249 u8 enable[0x1];
5250 u8 tag_enable[0x1];
b4ff3a36 5251 u8 reserved_at_62[0x1e];
e281682b
SM		 5252};
5253
5254struct mlx5_ifc_query_cong_status_in_bits {
5255 u8 opcode[0x10];
b4ff3a36 5256 u8 reserved_at_10[0x10];
e281682b 5257
b4ff3a36 5258 u8 reserved_at_20[0x10];
e281682b
SM		 5259 u8 op_mod[0x10];
5260
b4ff3a36 5261 u8 reserved_at_40[0x18];
e281682b
SM		 5262 u8 priority[0x4];
5263 u8 cong_protocol[0x4];
5264
b4ff3a36 5265 u8 reserved_at_60[0x20];
e281682b
SM		 5266};
5267
5268struct mlx5_ifc_query_cong_statistics_out_bits {
5269 u8 status[0x8];
b4ff3a36 5270 u8 reserved_at_8[0x18];
e281682b
SM		 5271
5272 u8 syndrome[0x20];
5273
b4ff3a36 5274 u8 reserved_at_40[0x40];
e281682b 5275
e1f24a79 5276 u8 rp_cur_flows[0x20];
e281682b
SM		 5277
5278 u8 sum_flows[0x20];
5279
e1f24a79 5280 u8 rp_cnp_ignored_high[0x20];
e281682b 5281
e1f24a79 5282 u8 rp_cnp_ignored_low[0x20];
e281682b 5283
e1f24a79 5284 u8 rp_cnp_handled_high[0x20];
e281682b 5285
e1f24a79 5286 u8 rp_cnp_handled_low[0x20];
e281682b 5287
b4ff3a36 5288 u8 reserved_at_140[0x100];
e281682b
SM		 5289
5290 u8 time_stamp_high[0x20];
5291
5292 u8 time_stamp_low[0x20];
5293
5294 u8 accumulators_period[0x20];
5295
e1f24a79 5296 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5297
e1f24a79 5298 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5299
e1f24a79 5300 u8 np_cnp_sent_high[0x20];
e281682b 5301
e1f24a79 5302 u8 np_cnp_sent_low[0x20];
e281682b 5303
b4ff3a36 5304 u8 reserved_at_320[0x560];
e281682b
SM		 5305};
5306
5307struct mlx5_ifc_query_cong_statistics_in_bits {
5308 u8 opcode[0x10];
b4ff3a36 5309 u8 reserved_at_10[0x10];
e281682b 5310
b4ff3a36 5311 u8 reserved_at_20[0x10];
e281682b
SM		 5312 u8 op_mod[0x10];
5313
5314 u8 clear[0x1];
b4ff3a36 5315 u8 reserved_at_41[0x1f];
e281682b 5316
b4ff3a36 5317 u8 reserved_at_60[0x20];
e281682b
SM		 5318};
5319
5320struct mlx5_ifc_query_cong_params_out_bits {
5321 u8 status[0x8];
b4ff3a36 5322 u8 reserved_at_8[0x18];
e281682b
SM		 5323
5324 u8 syndrome[0x20];
5325
b4ff3a36 5326 u8 reserved_at_40[0x40];
e281682b
SM		 5327
5328 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5329};
5330
5331struct mlx5_ifc_query_cong_params_in_bits {
5332 u8 opcode[0x10];
b4ff3a36 5333 u8 reserved_at_10[0x10];
e281682b 5334
b4ff3a36 5335 u8 reserved_at_20[0x10];
e281682b
SM		 5336 u8 op_mod[0x10];
5337
b4ff3a36 5338 u8 reserved_at_40[0x1c];
e281682b
SM		 5339 u8 cong_protocol[0x4];
5340
b4ff3a36 5341 u8 reserved_at_60[0x20];
e281682b
SM		 5342};
5343
5344struct mlx5_ifc_query_adapter_out_bits {
5345 u8 status[0x8];
b4ff3a36 5346 u8 reserved_at_8[0x18];
e281682b
SM		 5347
5348 u8 syndrome[0x20];
5349
b4ff3a36 5350 u8 reserved_at_40[0x40];
e281682b
SM		 5351
5352 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5353};
5354
5355struct mlx5_ifc_query_adapter_in_bits {
5356 u8 opcode[0x10];
b4ff3a36 5357 u8 reserved_at_10[0x10];
e281682b 5358
b4ff3a36 5359 u8 reserved_at_20[0x10];
e281682b
SM		 5360 u8 op_mod[0x10];
5361
b4ff3a36 5362 u8 reserved_at_40[0x40];
e281682b
SM		 5363};
5364
5365struct mlx5_ifc_qp_2rst_out_bits {
5366 u8 status[0x8];
b4ff3a36 5367 u8 reserved_at_8[0x18];
e281682b
SM		 5368
5369 u8 syndrome[0x20];
5370
b4ff3a36 5371 u8 reserved_at_40[0x40];
e281682b
SM		 5372};
5373
5374struct mlx5_ifc_qp_2rst_in_bits {
5375 u8 opcode[0x10];
4ac63ec7 5376 u8 uid[0x10];
e281682b 5377
b4ff3a36 5378 u8 reserved_at_20[0x10];
e281682b
SM		 5379 u8 op_mod[0x10];
5380
b4ff3a36 5381 u8 reserved_at_40[0x8];
e281682b
SM		 5382 u8 qpn[0x18];
5383
b4ff3a36 5384 u8 reserved_at_60[0x20];
e281682b
SM		 5385};
5386
5387struct mlx5_ifc_qp_2err_out_bits {
5388 u8 status[0x8];
b4ff3a36 5389 u8 reserved_at_8[0x18];
e281682b
SM		 5390
5391 u8 syndrome[0x20];
5392
b4ff3a36 5393 u8 reserved_at_40[0x40];
e281682b
SM		 5394};
5395
5396struct mlx5_ifc_qp_2err_in_bits {
5397 u8 opcode[0x10];
4ac63ec7 5398 u8 uid[0x10];
e281682b 5399
b4ff3a36 5400 u8 reserved_at_20[0x10];
e281682b
SM		 5401 u8 op_mod[0x10];
5402
b4ff3a36 5403 u8 reserved_at_40[0x8];
e281682b
SM		 5404 u8 qpn[0x18];
5405
b4ff3a36 5406 u8 reserved_at_60[0x20];
e281682b
SM		 5407};
5408
5409struct mlx5_ifc_page_fault_resume_out_bits {
5410 u8 status[0x8];
b4ff3a36 5411 u8 reserved_at_8[0x18];
e281682b
SM		 5412
5413 u8 syndrome[0x20];
5414
b4ff3a36 5415 u8 reserved_at_40[0x40];
e281682b
SM		 5416};
5417
5418struct mlx5_ifc_page_fault_resume_in_bits {
5419 u8 opcode[0x10];
b4ff3a36 5420 u8 reserved_at_10[0x10];
e281682b 5421
b4ff3a36 5422 u8 reserved_at_20[0x10];
e281682b
SM		 5423 u8 op_mod[0x10];
5424
5425 u8 error[0x1];
b4ff3a36 5426 u8 reserved_at_41[0x4];
223cdc72
AK		 5427 u8 page_fault_type[0x3];
5428 u8 wq_number[0x18];
e281682b 5429
223cdc72
AK		 5430 u8 reserved_at_60[0x8];
5431 u8 token[0x18];
e281682b
SM		 5432};
5433
5434struct mlx5_ifc_nop_out_bits {
5435 u8 status[0x8];
b4ff3a36 5436 u8 reserved_at_8[0x18];
e281682b
SM		 5437
5438 u8 syndrome[0x20];
5439
b4ff3a36 5440 u8 reserved_at_40[0x40];
e281682b
SM		 5441};
5442
5443struct mlx5_ifc_nop_in_bits {
5444 u8 opcode[0x10];
b4ff3a36 5445 u8 reserved_at_10[0x10];
e281682b 5446
b4ff3a36 5447 u8 reserved_at_20[0x10];
e281682b
SM		 5448 u8 op_mod[0x10];
5449
b4ff3a36 5450 u8 reserved_at_40[0x40];
e281682b
SM		 5451};
5452
5453struct mlx5_ifc_modify_vport_state_out_bits {
5454 u8 status[0x8];
b4ff3a36 5455 u8 reserved_at_8[0x18];
e281682b
SM		 5456
5457 u8 syndrome[0x20];
5458
b4ff3a36 5459 u8 reserved_at_40[0x40];
e281682b
SM		 5460};
5461
5462struct mlx5_ifc_modify_vport_state_in_bits {
5463 u8 opcode[0x10];
b4ff3a36 5464 u8 reserved_at_10[0x10];
e281682b 5465
b4ff3a36 5466 u8 reserved_at_20[0x10];
e281682b
SM		 5467 u8 op_mod[0x10];
5468
5469 u8 other_vport[0x1];
b4ff3a36 5470 u8 reserved_at_41[0xf];
e281682b
SM		 5471 u8 vport_number[0x10];
5472
b4ff3a36 5473 u8 reserved_at_60[0x18];
e281682b 5474 u8 admin_state[0x4];
b4ff3a36 5475 u8 reserved_at_7c[0x4];
e281682b
SM		 5476};
5477
5478struct mlx5_ifc_modify_tis_out_bits {
5479 u8 status[0x8];
b4ff3a36 5480 u8 reserved_at_8[0x18];
e281682b
SM		 5481
5482 u8 syndrome[0x20];
5483
b4ff3a36 5484 u8 reserved_at_40[0x40];
e281682b
SM		 5485};
5486
75850d0b 5487struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5488 u8 reserved_at_0[0x20];
75850d0b 5489
84df61eb
AH		 5490 u8 reserved_at_20[0x1d];
5491 u8 lag_tx_port_affinity[0x1];
5492 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5493 u8 prio[0x1];
5494};
5495
e281682b
SM		 5496struct mlx5_ifc_modify_tis_in_bits {
5497 u8 opcode[0x10];
bd371975 5498 u8 uid[0x10];
e281682b 5499
b4ff3a36 5500 u8 reserved_at_20[0x10];
e281682b
SM		 5501 u8 op_mod[0x10];
5502
b4ff3a36 5503 u8 reserved_at_40[0x8];
e281682b
SM		 5504 u8 tisn[0x18];
5505
b4ff3a36 5506 u8 reserved_at_60[0x20];
e281682b 5507
75850d0b 5508 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5509
b4ff3a36 5510 u8 reserved_at_c0[0x40];
e281682b
SM		 5511
5512 struct mlx5_ifc_tisc_bits ctx;
5513};
5514
d9eea403 5515struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5516 u8 reserved_at_0[0x20];
d9eea403 5517
b4ff3a36 5518 u8 reserved_at_20[0x1b];
66189961 5519 u8 self_lb_en[0x1];
bdfc028d
TT		 5520 u8 reserved_at_3c[0x1];
5521 u8 hash[0x1];
5522 u8 reserved_at_3e[0x1];
d9eea403
AS		 5523 u8 lro[0x1];
5524};
5525
e281682b
SM		 5526struct mlx5_ifc_modify_tir_out_bits {
5527 u8 status[0x8];
b4ff3a36 5528 u8 reserved_at_8[0x18];
e281682b
SM		 5529
5530 u8 syndrome[0x20];
5531
b4ff3a36 5532 u8 reserved_at_40[0x40];
e281682b
SM		 5533};
5534
5535struct mlx5_ifc_modify_tir_in_bits {
5536 u8 opcode[0x10];
bd371975 5537 u8 uid[0x10];
e281682b 5538
b4ff3a36 5539 u8 reserved_at_20[0x10];
e281682b
SM		 5540 u8 op_mod[0x10];
5541
b4ff3a36 5542 u8 reserved_at_40[0x8];
e281682b
SM		 5543 u8 tirn[0x18];
5544
b4ff3a36 5545 u8 reserved_at_60[0x20];
e281682b 5546
d9eea403 5547 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5548
b4ff3a36 5549 u8 reserved_at_c0[0x40];
e281682b
SM		 5550
5551 struct mlx5_ifc_tirc_bits ctx;
5552};
5553
5554struct mlx5_ifc_modify_sq_out_bits {
5555 u8 status[0x8];
b4ff3a36 5556 u8 reserved_at_8[0x18];
e281682b
SM		 5557
5558 u8 syndrome[0x20];
5559
b4ff3a36 5560 u8 reserved_at_40[0x40];
e281682b
SM		 5561};
5562
5563struct mlx5_ifc_modify_sq_in_bits {
5564 u8 opcode[0x10];
430ae0d5 5565 u8 uid[0x10];
e281682b 5566
b4ff3a36 5567 u8 reserved_at_20[0x10];
e281682b
SM		 5568 u8 op_mod[0x10];
5569
5570 u8 sq_state[0x4];
b4ff3a36 5571 u8 reserved_at_44[0x4];
e281682b
SM		 5572 u8 sqn[0x18];
5573
b4ff3a36 5574 u8 reserved_at_60[0x20];
e281682b
SM		 5575
5576 u8 modify_bitmask[0x40];
5577
b4ff3a36 5578 u8 reserved_at_c0[0x40];
e281682b
SM		 5579
5580 struct mlx5_ifc_sqc_bits ctx;
5581};
5582
813f8540
MHY		 5583struct mlx5_ifc_modify_scheduling_element_out_bits {
5584 u8 status[0x8];
5585 u8 reserved_at_8[0x18];
5586
5587 u8 syndrome[0x20];
5588
5589 u8 reserved_at_40[0x1c0];
5590};
5591
5592enum {
5593 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5594 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5595};
5596
5597struct mlx5_ifc_modify_scheduling_element_in_bits {
5598 u8 opcode[0x10];
5599 u8 reserved_at_10[0x10];
5600
5601 u8 reserved_at_20[0x10];
5602 u8 op_mod[0x10];
5603
5604 u8 scheduling_hierarchy[0x8];
5605 u8 reserved_at_48[0x18];
5606
5607 u8 scheduling_element_id[0x20];
5608
5609 u8 reserved_at_80[0x20];
5610
5611 u8 modify_bitmask[0x20];
5612
5613 u8 reserved_at_c0[0x40];
5614
5615 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5616
5617 u8 reserved_at_300[0x100];
5618};
5619
e281682b
SM		 5620struct mlx5_ifc_modify_rqt_out_bits {
5621 u8 status[0x8];
b4ff3a36 5622 u8 reserved_at_8[0x18];
e281682b
SM		 5623
5624 u8 syndrome[0x20];
5625
b4ff3a36 5626 u8 reserved_at_40[0x40];
e281682b
SM		 5627};
5628
5c50368f 5629struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5630 u8 reserved_at_0[0x20];
5c50368f 5631
b4ff3a36 5632 u8 reserved_at_20[0x1f];
5c50368f
AS		 5633 u8 rqn_list[0x1];
5634};
5635
e281682b
SM		 5636struct mlx5_ifc_modify_rqt_in_bits {
5637 u8 opcode[0x10];
bd371975 5638 u8 uid[0x10];
e281682b 5639
b4ff3a36 5640 u8 reserved_at_20[0x10];
e281682b
SM		 5641 u8 op_mod[0x10];
5642
b4ff3a36 5643 u8 reserved_at_40[0x8];
e281682b
SM		 5644 u8 rqtn[0x18];
5645
b4ff3a36 5646 u8 reserved_at_60[0x20];
e281682b 5647
5c50368f 5648 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5649
b4ff3a36 5650 u8 reserved_at_c0[0x40];
e281682b
SM		 5651
5652 struct mlx5_ifc_rqtc_bits ctx;
5653};
5654
5655struct mlx5_ifc_modify_rq_out_bits {
5656 u8 status[0x8];
b4ff3a36 5657 u8 reserved_at_8[0x18];
e281682b
SM		 5658
5659 u8 syndrome[0x20];
5660
b4ff3a36 5661 u8 reserved_at_40[0x40];
e281682b
SM		 5662};
5663
83b502a1
AV		 5664enum {
5665 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5666 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5667 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5668};
5669
e281682b
SM		 5670struct mlx5_ifc_modify_rq_in_bits {
5671 u8 opcode[0x10];
d269b3af 5672 u8 uid[0x10];
e281682b 5673
b4ff3a36 5674 u8 reserved_at_20[0x10];
e281682b
SM		 5675 u8 op_mod[0x10];
5676
5677 u8 rq_state[0x4];
b4ff3a36 5678 u8 reserved_at_44[0x4];
e281682b
SM		 5679 u8 rqn[0x18];
5680
b4ff3a36 5681 u8 reserved_at_60[0x20];
e281682b
SM		 5682
5683 u8 modify_bitmask[0x40];
5684
b4ff3a36 5685 u8 reserved_at_c0[0x40];
e281682b
SM		 5686
5687 struct mlx5_ifc_rqc_bits ctx;
5688};
5689
5690struct mlx5_ifc_modify_rmp_out_bits {
5691 u8 status[0x8];
b4ff3a36 5692 u8 reserved_at_8[0x18];
e281682b
SM		 5693
5694 u8 syndrome[0x20];
5695
b4ff3a36 5696 u8 reserved_at_40[0x40];
e281682b
SM		 5697};
5698
01949d01 5699struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5700 u8 reserved_at_0[0x20];
01949d01 5701
b4ff3a36 5702 u8 reserved_at_20[0x1f];
01949d01
HA		 5703 u8 lwm[0x1];
5704};
5705
e281682b
SM		 5706struct mlx5_ifc_modify_rmp_in_bits {
5707 u8 opcode[0x10];
a0d8c054 5708 u8 uid[0x10];
e281682b 5709
b4ff3a36 5710 u8 reserved_at_20[0x10];
e281682b
SM		 5711 u8 op_mod[0x10];
5712
5713 u8 rmp_state[0x4];
b4ff3a36 5714 u8 reserved_at_44[0x4];
e281682b
SM		 5715 u8 rmpn[0x18];
5716
b4ff3a36 5717 u8 reserved_at_60[0x20];
e281682b 5718
01949d01 5719 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5720
b4ff3a36 5721 u8 reserved_at_c0[0x40];
e281682b
SM		 5722
5723 struct mlx5_ifc_rmpc_bits ctx;
5724};
5725
5726struct mlx5_ifc_modify_nic_vport_context_out_bits {
5727 u8 status[0x8];
b4ff3a36 5728 u8 reserved_at_8[0x18];
e281682b
SM		 5729
5730 u8 syndrome[0x20];
5731
b4ff3a36 5732 u8 reserved_at_40[0x40];
e281682b
SM		 5733};
5734
5735struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5736 u8 reserved_at_0[0x12];
5737 u8 affiliation[0x1];
c74d90c1 5738 u8 reserved_at_13[0x1];
bded747b
HN		 5739 u8 disable_uc_local_lb[0x1];
5740 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5741 u8 node_guid[0x1];
5742 u8 port_guid[0x1];
9def7121 5743 u8 min_inline[0x1];
d82b7318
SM		 5744 u8 mtu[0x1];
5745 u8 change_event[0x1];
5746 u8 promisc[0x1];
e281682b
SM		 5747 u8 permanent_address[0x1];
5748 u8 addresses_list[0x1];
5749 u8 roce_en[0x1];
b4ff3a36 5750 u8 reserved_at_1f[0x1];
e281682b
SM		 5751};
5752
5753struct mlx5_ifc_modify_nic_vport_context_in_bits {
5754 u8 opcode[0x10];
b4ff3a36 5755 u8 reserved_at_10[0x10];
e281682b 5756
b4ff3a36 5757 u8 reserved_at_20[0x10];
e281682b
SM		 5758 u8 op_mod[0x10];
5759
5760 u8 other_vport[0x1];
b4ff3a36 5761 u8 reserved_at_41[0xf];
e281682b
SM		 5762 u8 vport_number[0x10];
5763
5764 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5765
b4ff3a36 5766 u8 reserved_at_80[0x780];
e281682b
SM		 5767
5768 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5769};
5770
5771struct mlx5_ifc_modify_hca_vport_context_out_bits {
5772 u8 status[0x8];
b4ff3a36 5773 u8 reserved_at_8[0x18];
e281682b
SM		 5774
5775 u8 syndrome[0x20];
5776
b4ff3a36 5777 u8 reserved_at_40[0x40];
e281682b
SM		 5778};
5779
5780struct mlx5_ifc_modify_hca_vport_context_in_bits {
5781 u8 opcode[0x10];
b4ff3a36 5782 u8 reserved_at_10[0x10];
e281682b 5783
b4ff3a36 5784 u8 reserved_at_20[0x10];
e281682b
SM		 5785 u8 op_mod[0x10];
5786
5787 u8 other_vport[0x1];
b4ff3a36 5788 u8 reserved_at_41[0xb];
707c4602 5789 u8 port_num[0x4];
e281682b
SM		 5790 u8 vport_number[0x10];
5791
b4ff3a36 5792 u8 reserved_at_60[0x20];
e281682b
SM		 5793
5794 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5795};
5796
5797struct mlx5_ifc_modify_cq_out_bits {
5798 u8 status[0x8];
b4ff3a36 5799 u8 reserved_at_8[0x18];
e281682b
SM		 5800
5801 u8 syndrome[0x20];
5802
b4ff3a36 5803 u8 reserved_at_40[0x40];
e281682b
SM		 5804};
5805
5806enum {
5807 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5808 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5809};
5810
5811struct mlx5_ifc_modify_cq_in_bits {
5812 u8 opcode[0x10];
9ba481e2 5813 u8 uid[0x10];
e281682b 5814
b4ff3a36 5815 u8 reserved_at_20[0x10];
e281682b
SM		 5816 u8 op_mod[0x10];
5817
b4ff3a36 5818 u8 reserved_at_40[0x8];
e281682b
SM		 5819 u8 cqn[0x18];
5820
5821 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5822
5823 struct mlx5_ifc_cqc_bits cq_context;
5824
bd371975
LR		 5825 u8 reserved_at_280[0x40];
5826
5827 u8 cq_umem_valid[0x1];
5828 u8 reserved_at_2c1[0x5bf];
e281682b
SM		 5829
5830 u8 pas[0][0x40];
5831};
5832
5833struct mlx5_ifc_modify_cong_status_out_bits {
5834 u8 status[0x8];
b4ff3a36 5835 u8 reserved_at_8[0x18];
e281682b
SM		 5836
5837 u8 syndrome[0x20];
5838
b4ff3a36 5839 u8 reserved_at_40[0x40];
e281682b
SM		 5840};
5841
5842struct mlx5_ifc_modify_cong_status_in_bits {
5843 u8 opcode[0x10];
b4ff3a36 5844 u8 reserved_at_10[0x10];
e281682b 5845
b4ff3a36 5846 u8 reserved_at_20[0x10];
e281682b
SM		 5847 u8 op_mod[0x10];
5848
b4ff3a36 5849 u8 reserved_at_40[0x18];
e281682b
SM		 5850 u8 priority[0x4];
5851 u8 cong_protocol[0x4];
5852
5853 u8 enable[0x1];
5854 u8 tag_enable[0x1];
b4ff3a36 5855 u8 reserved_at_62[0x1e];
e281682b
SM		 5856};
5857
5858struct mlx5_ifc_modify_cong_params_out_bits {
5859 u8 status[0x8];
b4ff3a36 5860 u8 reserved_at_8[0x18];
e281682b
SM		 5861
5862 u8 syndrome[0x20];
5863
b4ff3a36 5864 u8 reserved_at_40[0x40];
e281682b
SM		 5865};
5866
5867struct mlx5_ifc_modify_cong_params_in_bits {
5868 u8 opcode[0x10];
b4ff3a36 5869 u8 reserved_at_10[0x10];
e281682b 5870
b4ff3a36 5871 u8 reserved_at_20[0x10];
e281682b
SM		 5872 u8 op_mod[0x10];
5873
b4ff3a36 5874 u8 reserved_at_40[0x1c];
e281682b
SM		 5875 u8 cong_protocol[0x4];
5876
5877 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5878
b4ff3a36 5879 u8 reserved_at_80[0x80];
e281682b
SM		 5880
5881 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5882};
5883
5884struct mlx5_ifc_manage_pages_out_bits {
5885 u8 status[0x8];
b4ff3a36 5886 u8 reserved_at_8[0x18];
e281682b
SM		 5887
5888 u8 syndrome[0x20];
5889
5890 u8 output_num_entries[0x20];
5891
b4ff3a36 5892 u8 reserved_at_60[0x20];
e281682b
SM		 5893
5894 u8 pas[0][0x40];
5895};
5896
5897enum {
5898 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5899 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5900 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5901};
5902
5903struct mlx5_ifc_manage_pages_in_bits {
5904 u8 opcode[0x10];
b4ff3a36 5905 u8 reserved_at_10[0x10];
e281682b 5906
b4ff3a36 5907 u8 reserved_at_20[0x10];
e281682b
SM		 5908 u8 op_mod[0x10];
5909
591905ba
BW		 5910 u8 embedded_cpu_function[0x1];
5911 u8 reserved_at_41[0xf];
e281682b
SM		 5912 u8 function_id[0x10];
5913
5914 u8 input_num_entries[0x20];
5915
5916 u8 pas[0][0x40];
5917};
5918
5919struct mlx5_ifc_mad_ifc_out_bits {
5920 u8 status[0x8];
b4ff3a36 5921 u8 reserved_at_8[0x18];
e281682b
SM		 5922
5923 u8 syndrome[0x20];
5924
b4ff3a36 5925 u8 reserved_at_40[0x40];
e281682b
SM		 5926
5927 u8 response_mad_packet[256][0x8];
5928};
5929
5930struct mlx5_ifc_mad_ifc_in_bits {
5931 u8 opcode[0x10];
b4ff3a36 5932 u8 reserved_at_10[0x10];
e281682b 5933
b4ff3a36 5934 u8 reserved_at_20[0x10];
e281682b
SM		 5935 u8 op_mod[0x10];
5936
5937 u8 remote_lid[0x10];
b4ff3a36 5938 u8 reserved_at_50[0x8];
e281682b
SM		 5939 u8 port[0x8];
5940
b4ff3a36 5941 u8 reserved_at_60[0x20];
e281682b
SM		 5942
5943 u8 mad[256][0x8];
5944};
5945
5946struct mlx5_ifc_init_hca_out_bits {
5947 u8 status[0x8];
b4ff3a36 5948 u8 reserved_at_8[0x18];
e281682b
SM		 5949
5950 u8 syndrome[0x20];
5951
b4ff3a36 5952 u8 reserved_at_40[0x40];
e281682b
SM		 5953};
5954
5955struct mlx5_ifc_init_hca_in_bits {
5956 u8 opcode[0x10];
b4ff3a36 5957 u8 reserved_at_10[0x10];
e281682b 5958
b4ff3a36 5959 u8 reserved_at_20[0x10];
e281682b
SM		 5960 u8 op_mod[0x10];
5961
b4ff3a36 5962 u8 reserved_at_40[0x40];
8737f818 5963 u8 sw_owner_id[4][0x20];
e281682b
SM		 5964};
5965
5966struct mlx5_ifc_init2rtr_qp_out_bits {
5967 u8 status[0x8];
b4ff3a36 5968 u8 reserved_at_8[0x18];
e281682b
SM		 5969
5970 u8 syndrome[0x20];
5971
b4ff3a36 5972 u8 reserved_at_40[0x40];
e281682b
SM		 5973};
5974
5975struct mlx5_ifc_init2rtr_qp_in_bits {
5976 u8 opcode[0x10];
4ac63ec7 5977 u8 uid[0x10];
e281682b 5978
b4ff3a36 5979 u8 reserved_at_20[0x10];
e281682b
SM		 5980 u8 op_mod[0x10];
5981
b4ff3a36 5982 u8 reserved_at_40[0x8];
e281682b
SM		 5983 u8 qpn[0x18];
5984
b4ff3a36 5985 u8 reserved_at_60[0x20];
e281682b
SM		 5986
5987 u8 opt_param_mask[0x20];
5988
b4ff3a36 5989 u8 reserved_at_a0[0x20];
e281682b
SM		 5990
5991 struct mlx5_ifc_qpc_bits qpc;
5992
b4ff3a36 5993 u8 reserved_at_800[0x80];
e281682b
SM		 5994};
5995
5996struct mlx5_ifc_init2init_qp_out_bits {
5997 u8 status[0x8];
b4ff3a36 5998 u8 reserved_at_8[0x18];
e281682b
SM		 5999
6000 u8 syndrome[0x20];
6001
b4ff3a36 6002 u8 reserved_at_40[0x40];
e281682b
SM		 6003};
6004
6005struct mlx5_ifc_init2init_qp_in_bits {
6006 u8 opcode[0x10];
4ac63ec7 6007 u8 uid[0x10];
e281682b 6008
b4ff3a36 6009 u8 reserved_at_20[0x10];
e281682b
SM		 6010 u8 op_mod[0x10];
6011
b4ff3a36 6012 u8 reserved_at_40[0x8];
e281682b
SM		 6013 u8 qpn[0x18];
6014
b4ff3a36 6015 u8 reserved_at_60[0x20];
e281682b
SM		 6016
6017 u8 opt_param_mask[0x20];
6018
b4ff3a36 6019 u8 reserved_at_a0[0x20];
e281682b
SM		 6020
6021 struct mlx5_ifc_qpc_bits qpc;
6022
b4ff3a36 6023 u8 reserved_at_800[0x80];
e281682b
SM		 6024};
6025
6026struct mlx5_ifc_get_dropped_packet_log_out_bits {
6027 u8 status[0x8];
b4ff3a36 6028 u8 reserved_at_8[0x18];
e281682b
SM		 6029
6030 u8 syndrome[0x20];
6031
b4ff3a36 6032 u8 reserved_at_40[0x40];
e281682b
SM		 6033
6034 u8 packet_headers_log[128][0x8];
6035
6036 u8 packet_syndrome[64][0x8];
6037};
6038
6039struct mlx5_ifc_get_dropped_packet_log_in_bits {
6040 u8 opcode[0x10];
b4ff3a36 6041 u8 reserved_at_10[0x10];
e281682b 6042
b4ff3a36 6043 u8 reserved_at_20[0x10];
e281682b
SM		 6044 u8 op_mod[0x10];
6045
b4ff3a36 6046 u8 reserved_at_40[0x40];
e281682b
SM		 6047};
6048
6049struct mlx5_ifc_gen_eqe_in_bits {
6050 u8 opcode[0x10];
b4ff3a36 6051 u8 reserved_at_10[0x10];
e281682b 6052
b4ff3a36 6053 u8 reserved_at_20[0x10];
e281682b
SM		 6054 u8 op_mod[0x10];
6055
b4ff3a36 6056 u8 reserved_at_40[0x18];
e281682b
SM		 6057 u8 eq_number[0x8];
6058
b4ff3a36 6059 u8 reserved_at_60[0x20];
e281682b
SM		 6060
6061 u8 eqe[64][0x8];
6062};
6063
6064struct mlx5_ifc_gen_eq_out_bits {
6065 u8 status[0x8];
b4ff3a36 6066 u8 reserved_at_8[0x18];
e281682b
SM		 6067
6068 u8 syndrome[0x20];
6069
b4ff3a36 6070 u8 reserved_at_40[0x40];
e281682b
SM		 6071};
6072
6073struct mlx5_ifc_enable_hca_out_bits {
6074 u8 status[0x8];
b4ff3a36 6075 u8 reserved_at_8[0x18];
e281682b
SM		 6076
6077 u8 syndrome[0x20];
6078
b4ff3a36 6079 u8 reserved_at_40[0x20];
e281682b
SM		 6080};
6081
6082struct mlx5_ifc_enable_hca_in_bits {
6083 u8 opcode[0x10];
b4ff3a36 6084 u8 reserved_at_10[0x10];
e281682b 6085
b4ff3a36 6086 u8 reserved_at_20[0x10];
e281682b
SM		 6087 u8 op_mod[0x10];
6088
22e939a9
BW		 6089 u8 embedded_cpu_function[0x1];
6090 u8 reserved_at_41[0xf];
e281682b
SM		 6091 u8 function_id[0x10];
6092
b4ff3a36 6093 u8 reserved_at_60[0x20];
e281682b
SM		 6094};
6095
6096struct mlx5_ifc_drain_dct_out_bits {
6097 u8 status[0x8];
b4ff3a36 6098 u8 reserved_at_8[0x18];
e281682b
SM		 6099
6100 u8 syndrome[0x20];
6101
b4ff3a36 6102 u8 reserved_at_40[0x40];
e281682b
SM		 6103};
6104
6105struct mlx5_ifc_drain_dct_in_bits {
6106 u8 opcode[0x10];
774ea6ee 6107 u8 uid[0x10];
e281682b 6108
b4ff3a36 6109 u8 reserved_at_20[0x10];
e281682b
SM		 6110 u8 op_mod[0x10];
6111
b4ff3a36 6112 u8 reserved_at_40[0x8];
e281682b
SM		 6113 u8 dctn[0x18];
6114
b4ff3a36 6115 u8 reserved_at_60[0x20];
e281682b
SM		 6116};
6117
6118struct mlx5_ifc_disable_hca_out_bits {
6119 u8 status[0x8];
b4ff3a36 6120 u8 reserved_at_8[0x18];
e281682b
SM		 6121
6122 u8 syndrome[0x20];
6123
b4ff3a36 6124 u8 reserved_at_40[0x20];
e281682b
SM		 6125};
6126
6127struct mlx5_ifc_disable_hca_in_bits {
6128 u8 opcode[0x10];
b4ff3a36 6129 u8 reserved_at_10[0x10];
e281682b 6130
b4ff3a36 6131 u8 reserved_at_20[0x10];
e281682b
SM		 6132 u8 op_mod[0x10];
6133
22e939a9
BW		 6134 u8 embedded_cpu_function[0x1];
6135 u8 reserved_at_41[0xf];
e281682b
SM		 6136 u8 function_id[0x10];
6137
b4ff3a36 6138 u8 reserved_at_60[0x20];
e281682b
SM		 6139};
6140
6141struct mlx5_ifc_detach_from_mcg_out_bits {
6142 u8 status[0x8];
b4ff3a36 6143 u8 reserved_at_8[0x18];
e281682b
SM		 6144
6145 u8 syndrome[0x20];
6146
b4ff3a36 6147 u8 reserved_at_40[0x40];
e281682b
SM		 6148};
6149
6150struct mlx5_ifc_detach_from_mcg_in_bits {
6151 u8 opcode[0x10];
bd371975 6152 u8 uid[0x10];
e281682b 6153
b4ff3a36 6154 u8 reserved_at_20[0x10];
e281682b
SM		 6155 u8 op_mod[0x10];
6156
b4ff3a36 6157 u8 reserved_at_40[0x8];
e281682b
SM		 6158 u8 qpn[0x18];
6159
b4ff3a36 6160 u8 reserved_at_60[0x20];
e281682b
SM		 6161
6162 u8 multicast_gid[16][0x8];
6163};
6164
7486216b
SM		 6165struct mlx5_ifc_destroy_xrq_out_bits {
6166 u8 status[0x8];
6167 u8 reserved_at_8[0x18];
6168
6169 u8 syndrome[0x20];
6170
6171 u8 reserved_at_40[0x40];
6172};
6173
6174struct mlx5_ifc_destroy_xrq_in_bits {
6175 u8 opcode[0x10];
a0d8c054 6176 u8 uid[0x10];
7486216b
SM		 6177
6178 u8 reserved_at_20[0x10];
6179 u8 op_mod[0x10];
6180
6181 u8 reserved_at_40[0x8];
6182 u8 xrqn[0x18];
6183
6184 u8 reserved_at_60[0x20];
6185};
6186
e281682b
SM		 6187struct mlx5_ifc_destroy_xrc_srq_out_bits {
6188 u8 status[0x8];
b4ff3a36 6189 u8 reserved_at_8[0x18];
e281682b
SM		 6190
6191 u8 syndrome[0x20];
6192
b4ff3a36 6193 u8 reserved_at_40[0x40];
e281682b
SM		 6194};
6195
6196struct mlx5_ifc_destroy_xrc_srq_in_bits {
6197 u8 opcode[0x10];
a0d8c054 6198 u8 uid[0x10];
e281682b 6199
b4ff3a36 6200 u8 reserved_at_20[0x10];
e281682b
SM		 6201 u8 op_mod[0x10];
6202
b4ff3a36 6203 u8 reserved_at_40[0x8];
e281682b
SM		 6204 u8 xrc_srqn[0x18];
6205
b4ff3a36 6206 u8 reserved_at_60[0x20];
e281682b
SM		 6207};
6208
6209struct mlx5_ifc_destroy_tis_out_bits {
6210 u8 status[0x8];
b4ff3a36 6211 u8 reserved_at_8[0x18];
e281682b
SM		 6212
6213 u8 syndrome[0x20];
6214
b4ff3a36 6215 u8 reserved_at_40[0x40];
e281682b
SM		 6216};
6217
6218struct mlx5_ifc_destroy_tis_in_bits {
6219 u8 opcode[0x10];
bd371975 6220 u8 uid[0x10];
e281682b 6221
b4ff3a36 6222 u8 reserved_at_20[0x10];
e281682b
SM		 6223 u8 op_mod[0x10];
6224
b4ff3a36 6225 u8 reserved_at_40[0x8];
e281682b
SM		 6226 u8 tisn[0x18];
6227
b4ff3a36 6228 u8 reserved_at_60[0x20];
e281682b
SM		 6229};
6230
6231struct mlx5_ifc_destroy_tir_out_bits {
6232 u8 status[0x8];
b4ff3a36 6233 u8 reserved_at_8[0x18];
e281682b
SM		 6234
6235 u8 syndrome[0x20];
6236
b4ff3a36 6237 u8 reserved_at_40[0x40];
e281682b
SM		 6238};
6239
6240struct mlx5_ifc_destroy_tir_in_bits {
6241 u8 opcode[0x10];
bd371975 6242 u8 uid[0x10];
e281682b 6243
b4ff3a36 6244 u8 reserved_at_20[0x10];
e281682b
SM		 6245 u8 op_mod[0x10];
6246
b4ff3a36 6247 u8 reserved_at_40[0x8];
e281682b
SM		 6248 u8 tirn[0x18];
6249
b4ff3a36 6250 u8 reserved_at_60[0x20];
e281682b
SM		 6251};
6252
6253struct mlx5_ifc_destroy_srq_out_bits {
6254 u8 status[0x8];
b4ff3a36 6255 u8 reserved_at_8[0x18];
e281682b
SM		 6256
6257 u8 syndrome[0x20];
6258
b4ff3a36 6259 u8 reserved_at_40[0x40];
e281682b
SM		 6260};
6261
6262struct mlx5_ifc_destroy_srq_in_bits {
6263 u8 opcode[0x10];
a0d8c054 6264 u8 uid[0x10];
e281682b 6265
b4ff3a36 6266 u8 reserved_at_20[0x10];
e281682b
SM		 6267 u8 op_mod[0x10];
6268
b4ff3a36 6269 u8 reserved_at_40[0x8];
e281682b
SM		 6270 u8 srqn[0x18];
6271
b4ff3a36 6272 u8 reserved_at_60[0x20];
e281682b
SM		 6273};
6274
6275struct mlx5_ifc_destroy_sq_out_bits {
6276 u8 status[0x8];
b4ff3a36 6277 u8 reserved_at_8[0x18];
e281682b
SM		 6278
6279 u8 syndrome[0x20];
6280
b4ff3a36 6281 u8 reserved_at_40[0x40];
e281682b
SM		 6282};
6283
6284struct mlx5_ifc_destroy_sq_in_bits {
6285 u8 opcode[0x10];
430ae0d5 6286 u8 uid[0x10];
e281682b 6287
b4ff3a36 6288 u8 reserved_at_20[0x10];
e281682b
SM		 6289 u8 op_mod[0x10];
6290
b4ff3a36 6291 u8 reserved_at_40[0x8];
e281682b
SM		 6292 u8 sqn[0x18];
6293
b4ff3a36 6294 u8 reserved_at_60[0x20];
e281682b
SM		 6295};
6296
813f8540
MHY		 6297struct mlx5_ifc_destroy_scheduling_element_out_bits {
6298 u8 status[0x8];
6299 u8 reserved_at_8[0x18];
6300
6301 u8 syndrome[0x20];
6302
6303 u8 reserved_at_40[0x1c0];
6304};
6305
6306struct mlx5_ifc_destroy_scheduling_element_in_bits {
6307 u8 opcode[0x10];
6308 u8 reserved_at_10[0x10];
6309
6310 u8 reserved_at_20[0x10];
6311 u8 op_mod[0x10];
6312
6313 u8 scheduling_hierarchy[0x8];
6314 u8 reserved_at_48[0x18];
6315
6316 u8 scheduling_element_id[0x20];
6317
6318 u8 reserved_at_80[0x180];
6319};
6320
e281682b
SM		 6321struct mlx5_ifc_destroy_rqt_out_bits {
6322 u8 status[0x8];
b4ff3a36 6323 u8 reserved_at_8[0x18];
e281682b
SM		 6324
6325 u8 syndrome[0x20];
6326
b4ff3a36 6327 u8 reserved_at_40[0x40];
e281682b
SM		 6328};
6329
6330struct mlx5_ifc_destroy_rqt_in_bits {
6331 u8 opcode[0x10];
bd371975 6332 u8 uid[0x10];
e281682b 6333
b4ff3a36 6334 u8 reserved_at_20[0x10];
e281682b
SM		 6335 u8 op_mod[0x10];
6336
b4ff3a36 6337 u8 reserved_at_40[0x8];
e281682b
SM		 6338 u8 rqtn[0x18];
6339
b4ff3a36 6340 u8 reserved_at_60[0x20];
e281682b
SM		 6341};
6342
6343struct mlx5_ifc_destroy_rq_out_bits {
6344 u8 status[0x8];
b4ff3a36 6345 u8 reserved_at_8[0x18];
e281682b
SM		 6346
6347 u8 syndrome[0x20];
6348
b4ff3a36 6349 u8 reserved_at_40[0x40];
e281682b
SM		 6350};
6351
6352struct mlx5_ifc_destroy_rq_in_bits {
6353 u8 opcode[0x10];
d269b3af 6354 u8 uid[0x10];
e281682b 6355
b4ff3a36 6356 u8 reserved_at_20[0x10];
e281682b
SM		 6357 u8 op_mod[0x10];
6358
b4ff3a36 6359 u8 reserved_at_40[0x8];
e281682b
SM		 6360 u8 rqn[0x18];
6361
b4ff3a36 6362 u8 reserved_at_60[0x20];
e281682b
SM		 6363};
6364
c1e0bfc1
MG		 6365struct mlx5_ifc_set_delay_drop_params_in_bits {
6366 u8 opcode[0x10];
6367 u8 reserved_at_10[0x10];
6368
6369 u8 reserved_at_20[0x10];
6370 u8 op_mod[0x10];
6371
6372 u8 reserved_at_40[0x20];
6373
6374 u8 reserved_at_60[0x10];
6375 u8 delay_drop_timeout[0x10];
6376};
6377
6378struct mlx5_ifc_set_delay_drop_params_out_bits {
6379 u8 status[0x8];
6380 u8 reserved_at_8[0x18];
6381
6382 u8 syndrome[0x20];
6383
6384 u8 reserved_at_40[0x40];
6385};
6386
e281682b
SM		 6387struct mlx5_ifc_destroy_rmp_out_bits {
6388 u8 status[0x8];
b4ff3a36 6389 u8 reserved_at_8[0x18];
e281682b
SM		 6390
6391 u8 syndrome[0x20];
6392
b4ff3a36 6393 u8 reserved_at_40[0x40];
e281682b
SM		 6394};
6395
6396struct mlx5_ifc_destroy_rmp_in_bits {
6397 u8 opcode[0x10];
a0d8c054 6398 u8 uid[0x10];
e281682b 6399
b4ff3a36 6400 u8 reserved_at_20[0x10];
e281682b
SM		 6401 u8 op_mod[0x10];
6402
b4ff3a36 6403 u8 reserved_at_40[0x8];
e281682b
SM		 6404 u8 rmpn[0x18];
6405
b4ff3a36 6406 u8 reserved_at_60[0x20];
e281682b
SM		 6407};
6408
6409struct mlx5_ifc_destroy_qp_out_bits {
6410 u8 status[0x8];
b4ff3a36 6411 u8 reserved_at_8[0x18];
e281682b
SM		 6412
6413 u8 syndrome[0x20];
6414
b4ff3a36 6415 u8 reserved_at_40[0x40];
e281682b
SM		 6416};
6417
6418struct mlx5_ifc_destroy_qp_in_bits {
6419 u8 opcode[0x10];
4ac63ec7 6420 u8 uid[0x10];
e281682b 6421
b4ff3a36 6422 u8 reserved_at_20[0x10];
e281682b
SM		 6423 u8 op_mod[0x10];
6424
b4ff3a36 6425 u8 reserved_at_40[0x8];
e281682b
SM		 6426 u8 qpn[0x18];
6427
b4ff3a36 6428 u8 reserved_at_60[0x20];
e281682b
SM		 6429};
6430
6431struct mlx5_ifc_destroy_psv_out_bits {
6432 u8 status[0x8];
b4ff3a36 6433 u8 reserved_at_8[0x18];
e281682b
SM		 6434
6435 u8 syndrome[0x20];
6436
b4ff3a36 6437 u8 reserved_at_40[0x40];
e281682b
SM		 6438};
6439
6440struct mlx5_ifc_destroy_psv_in_bits {
6441 u8 opcode[0x10];
b4ff3a36 6442 u8 reserved_at_10[0x10];
e281682b 6443
b4ff3a36 6444 u8 reserved_at_20[0x10];
e281682b
SM		 6445 u8 op_mod[0x10];
6446
b4ff3a36 6447 u8 reserved_at_40[0x8];
e281682b
SM		 6448 u8 psvn[0x18];
6449
b4ff3a36 6450 u8 reserved_at_60[0x20];
e281682b
SM		 6451};
6452
6453struct mlx5_ifc_destroy_mkey_out_bits {
6454 u8 status[0x8];
b4ff3a36 6455 u8 reserved_at_8[0x18];
e281682b
SM		 6456
6457 u8 syndrome[0x20];
6458
b4ff3a36 6459 u8 reserved_at_40[0x40];
e281682b
SM		 6460};
6461
6462struct mlx5_ifc_destroy_mkey_in_bits {
6463 u8 opcode[0x10];
b4ff3a36 6464 u8 reserved_at_10[0x10];
e281682b 6465
b4ff3a36 6466 u8 reserved_at_20[0x10];
e281682b
SM		 6467 u8 op_mod[0x10];
6468
b4ff3a36 6469 u8 reserved_at_40[0x8];
e281682b
SM		 6470 u8 mkey_index[0x18];
6471
b4ff3a36 6472 u8 reserved_at_60[0x20];
e281682b
SM		 6473};
6474
6475struct mlx5_ifc_destroy_flow_table_out_bits {
6476 u8 status[0x8];
b4ff3a36 6477 u8 reserved_at_8[0x18];
e281682b
SM		 6478
6479 u8 syndrome[0x20];
6480
b4ff3a36 6481 u8 reserved_at_40[0x40];
e281682b
SM		 6482};
6483
6484struct mlx5_ifc_destroy_flow_table_in_bits {
6485 u8 opcode[0x10];
b4ff3a36 6486 u8 reserved_at_10[0x10];
e281682b 6487
b4ff3a36 6488 u8 reserved_at_20[0x10];
e281682b
SM		 6489 u8 op_mod[0x10];
6490
7d5e1423
SM		 6491 u8 other_vport[0x1];
6492 u8 reserved_at_41[0xf];
6493 u8 vport_number[0x10];
6494
6495 u8 reserved_at_60[0x20];
e281682b
SM		 6496
6497 u8 table_type[0x8];
b4ff3a36 6498 u8 reserved_at_88[0x18];
e281682b 6499
b4ff3a36 6500 u8 reserved_at_a0[0x8];
e281682b
SM		 6501 u8 table_id[0x18];
6502
b4ff3a36 6503 u8 reserved_at_c0[0x140];
e281682b
SM		 6504};
6505
6506struct mlx5_ifc_destroy_flow_group_out_bits {
6507 u8 status[0x8];
b4ff3a36 6508 u8 reserved_at_8[0x18];
e281682b
SM		 6509
6510 u8 syndrome[0x20];
6511
b4ff3a36 6512 u8 reserved_at_40[0x40];
e281682b
SM		 6513};
6514
6515struct mlx5_ifc_destroy_flow_group_in_bits {
6516 u8 opcode[0x10];
b4ff3a36 6517 u8 reserved_at_10[0x10];
e281682b 6518
b4ff3a36 6519 u8 reserved_at_20[0x10];
e281682b
SM		 6520 u8 op_mod[0x10];
6521
7d5e1423
SM		 6522 u8 other_vport[0x1];
6523 u8 reserved_at_41[0xf];
6524 u8 vport_number[0x10];
6525
6526 u8 reserved_at_60[0x20];
e281682b
SM		 6527
6528 u8 table_type[0x8];
b4ff3a36 6529 u8 reserved_at_88[0x18];
e281682b 6530
b4ff3a36 6531 u8 reserved_at_a0[0x8];
e281682b
SM		 6532 u8 table_id[0x18];
6533
6534 u8 group_id[0x20];
6535
b4ff3a36 6536 u8 reserved_at_e0[0x120];
e281682b
SM		 6537};
6538
6539struct mlx5_ifc_destroy_eq_out_bits {
6540 u8 status[0x8];
b4ff3a36 6541 u8 reserved_at_8[0x18];
e281682b
SM		 6542
6543 u8 syndrome[0x20];
6544
b4ff3a36 6545 u8 reserved_at_40[0x40];
e281682b
SM		 6546};
6547
6548struct mlx5_ifc_destroy_eq_in_bits {
6549 u8 opcode[0x10];
b4ff3a36 6550 u8 reserved_at_10[0x10];
e281682b 6551
b4ff3a36 6552 u8 reserved_at_20[0x10];
e281682b
SM		 6553 u8 op_mod[0x10];
6554
b4ff3a36 6555 u8 reserved_at_40[0x18];
e281682b
SM		 6556 u8 eq_number[0x8];
6557
b4ff3a36 6558 u8 reserved_at_60[0x20];
e281682b
SM		 6559};
6560
6561struct mlx5_ifc_destroy_dct_out_bits {
6562 u8 status[0x8];
b4ff3a36 6563 u8 reserved_at_8[0x18];
e281682b
SM		 6564
6565 u8 syndrome[0x20];
6566
b4ff3a36 6567 u8 reserved_at_40[0x40];
e281682b
SM		 6568};
6569
6570struct mlx5_ifc_destroy_dct_in_bits {
6571 u8 opcode[0x10];
774ea6ee 6572 u8 uid[0x10];
e281682b 6573
b4ff3a36 6574 u8 reserved_at_20[0x10];
e281682b
SM		 6575 u8 op_mod[0x10];
6576
b4ff3a36 6577 u8 reserved_at_40[0x8];
e281682b
SM		 6578 u8 dctn[0x18];
6579
b4ff3a36 6580 u8 reserved_at_60[0x20];
e281682b
SM		 6581};
6582
6583struct mlx5_ifc_destroy_cq_out_bits {
6584 u8 status[0x8];
b4ff3a36 6585 u8 reserved_at_8[0x18];
e281682b
SM		 6586
6587 u8 syndrome[0x20];
6588
b4ff3a36 6589 u8 reserved_at_40[0x40];
e281682b
SM		 6590};
6591
6592struct mlx5_ifc_destroy_cq_in_bits {
6593 u8 opcode[0x10];
9ba481e2 6594 u8 uid[0x10];
e281682b 6595
b4ff3a36 6596 u8 reserved_at_20[0x10];
e281682b
SM		 6597 u8 op_mod[0x10];
6598
b4ff3a36 6599 u8 reserved_at_40[0x8];
e281682b
SM		 6600 u8 cqn[0x18];
6601
b4ff3a36 6602 u8 reserved_at_60[0x20];
e281682b
SM		 6603};
6604
6605struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6606 u8 status[0x8];
b4ff3a36 6607 u8 reserved_at_8[0x18];
e281682b
SM		 6608
6609 u8 syndrome[0x20];
6610
b4ff3a36 6611 u8 reserved_at_40[0x40];
e281682b
SM		 6612};
6613
6614struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6615 u8 opcode[0x10];
b4ff3a36 6616 u8 reserved_at_10[0x10];
e281682b 6617
b4ff3a36 6618 u8 reserved_at_20[0x10];
e281682b
SM		 6619 u8 op_mod[0x10];
6620
b4ff3a36 6621 u8 reserved_at_40[0x20];
e281682b 6622
b4ff3a36 6623 u8 reserved_at_60[0x10];
e281682b
SM		 6624 u8 vxlan_udp_port[0x10];
6625};
6626
6627struct mlx5_ifc_delete_l2_table_entry_out_bits {
6628 u8 status[0x8];
b4ff3a36 6629 u8 reserved_at_8[0x18];
e281682b
SM		 6630
6631 u8 syndrome[0x20];
6632
b4ff3a36 6633 u8 reserved_at_40[0x40];
e281682b
SM		 6634};
6635
6636struct mlx5_ifc_delete_l2_table_entry_in_bits {
6637 u8 opcode[0x10];
b4ff3a36 6638 u8 reserved_at_10[0x10];
e281682b 6639
b4ff3a36 6640 u8 reserved_at_20[0x10];
e281682b
SM		 6641 u8 op_mod[0x10];
6642
b4ff3a36 6643 u8 reserved_at_40[0x60];
e281682b 6644
b4ff3a36 6645 u8 reserved_at_a0[0x8];
e281682b
SM		 6646 u8 table_index[0x18];
6647
b4ff3a36 6648 u8 reserved_at_c0[0x140];
e281682b
SM		 6649};
6650
6651struct mlx5_ifc_delete_fte_out_bits {
6652 u8 status[0x8];
b4ff3a36 6653 u8 reserved_at_8[0x18];
e281682b
SM		 6654
6655 u8 syndrome[0x20];
6656
b4ff3a36 6657 u8 reserved_at_40[0x40];
e281682b
SM		 6658};
6659
6660struct mlx5_ifc_delete_fte_in_bits {
6661 u8 opcode[0x10];
b4ff3a36 6662 u8 reserved_at_10[0x10];
e281682b 6663
b4ff3a36 6664 u8 reserved_at_20[0x10];
e281682b
SM		 6665 u8 op_mod[0x10];
6666
7d5e1423
SM		 6667 u8 other_vport[0x1];
6668 u8 reserved_at_41[0xf];
6669 u8 vport_number[0x10];
6670
6671 u8 reserved_at_60[0x20];
e281682b
SM		 6672
6673 u8 table_type[0x8];
b4ff3a36 6674 u8 reserved_at_88[0x18];
e281682b 6675
b4ff3a36 6676 u8 reserved_at_a0[0x8];
e281682b
SM		 6677 u8 table_id[0x18];
6678
b4ff3a36 6679 u8 reserved_at_c0[0x40];
e281682b
SM		 6680
6681 u8 flow_index[0x20];
6682
b4ff3a36 6683 u8 reserved_at_120[0xe0];
e281682b
SM		 6684};
6685
6686struct mlx5_ifc_dealloc_xrcd_out_bits {
6687 u8 status[0x8];
b4ff3a36 6688 u8 reserved_at_8[0x18];
e281682b
SM		 6689
6690 u8 syndrome[0x20];
6691
b4ff3a36 6692 u8 reserved_at_40[0x40];
e281682b
SM		 6693};
6694
6695struct mlx5_ifc_dealloc_xrcd_in_bits {
6696 u8 opcode[0x10];
bd371975 6697 u8 uid[0x10];
e281682b 6698
b4ff3a36 6699 u8 reserved_at_20[0x10];
e281682b
SM		 6700 u8 op_mod[0x10];
6701
b4ff3a36 6702 u8 reserved_at_40[0x8];
e281682b
SM		 6703 u8 xrcd[0x18];
6704
b4ff3a36 6705 u8 reserved_at_60[0x20];
e281682b
SM		 6706};
6707
6708struct mlx5_ifc_dealloc_uar_out_bits {
6709 u8 status[0x8];
b4ff3a36 6710 u8 reserved_at_8[0x18];
e281682b
SM		 6711
6712 u8 syndrome[0x20];
6713
b4ff3a36 6714 u8 reserved_at_40[0x40];
e281682b
SM		 6715};
6716
6717struct mlx5_ifc_dealloc_uar_in_bits {
6718 u8 opcode[0x10];
b4ff3a36 6719 u8 reserved_at_10[0x10];
e281682b 6720
b4ff3a36 6721 u8 reserved_at_20[0x10];
e281682b
SM		 6722 u8 op_mod[0x10];
6723
b4ff3a36 6724 u8 reserved_at_40[0x8];
e281682b
SM		 6725 u8 uar[0x18];
6726
b4ff3a36 6727 u8 reserved_at_60[0x20];
e281682b
SM		 6728};
6729
6730struct mlx5_ifc_dealloc_transport_domain_out_bits {
6731 u8 status[0x8];
b4ff3a36 6732 u8 reserved_at_8[0x18];
e281682b
SM		 6733
6734 u8 syndrome[0x20];
6735
b4ff3a36 6736 u8 reserved_at_40[0x40];
e281682b
SM		 6737};
6738
6739struct mlx5_ifc_dealloc_transport_domain_in_bits {
6740 u8 opcode[0x10];
71bef2fd 6741 u8 uid[0x10];
e281682b 6742
b4ff3a36 6743 u8 reserved_at_20[0x10];
e281682b
SM		 6744 u8 op_mod[0x10];
6745
b4ff3a36 6746 u8 reserved_at_40[0x8];
e281682b
SM		 6747 u8 transport_domain[0x18];
6748
b4ff3a36 6749 u8 reserved_at_60[0x20];
e281682b
SM		 6750};
6751
6752struct mlx5_ifc_dealloc_q_counter_out_bits {
6753 u8 status[0x8];
b4ff3a36 6754 u8 reserved_at_8[0x18];
e281682b
SM		 6755
6756 u8 syndrome[0x20];
6757
b4ff3a36 6758 u8 reserved_at_40[0x40];
e281682b
SM		 6759};
6760
6761struct mlx5_ifc_dealloc_q_counter_in_bits {
6762 u8 opcode[0x10];
b4ff3a36 6763 u8 reserved_at_10[0x10];
e281682b 6764
b4ff3a36 6765 u8 reserved_at_20[0x10];
e281682b
SM		 6766 u8 op_mod[0x10];
6767
b4ff3a36 6768 u8 reserved_at_40[0x18];
e281682b
SM		 6769 u8 counter_set_id[0x8];
6770
b4ff3a36 6771 u8 reserved_at_60[0x20];
e281682b
SM		 6772};
6773
6774struct mlx5_ifc_dealloc_pd_out_bits {
6775 u8 status[0x8];
b4ff3a36 6776 u8 reserved_at_8[0x18];
e281682b
SM		 6777
6778 u8 syndrome[0x20];
6779
b4ff3a36 6780 u8 reserved_at_40[0x40];
e281682b
SM		 6781};
6782
6783struct mlx5_ifc_dealloc_pd_in_bits {
6784 u8 opcode[0x10];
bd371975 6785 u8 uid[0x10];
e281682b 6786
b4ff3a36 6787 u8 reserved_at_20[0x10];
e281682b
SM		 6788 u8 op_mod[0x10];
6789
b4ff3a36 6790 u8 reserved_at_40[0x8];
e281682b
SM		 6791 u8 pd[0x18];
6792
b4ff3a36 6793 u8 reserved_at_60[0x20];
e281682b
SM		 6794};
6795
9dc0b289
AV		 6796struct mlx5_ifc_dealloc_flow_counter_out_bits {
6797 u8 status[0x8];
6798 u8 reserved_at_8[0x18];
6799
6800 u8 syndrome[0x20];
6801
6802 u8 reserved_at_40[0x40];
6803};
6804
6805struct mlx5_ifc_dealloc_flow_counter_in_bits {
6806 u8 opcode[0x10];
6807 u8 reserved_at_10[0x10];
6808
6809 u8 reserved_at_20[0x10];
6810 u8 op_mod[0x10];
6811
a8ffcc74 6812 u8 flow_counter_id[0x20];
9dc0b289
AV		 6813
6814 u8 reserved_at_60[0x20];
6815};
6816
7486216b
SM		 6817struct mlx5_ifc_create_xrq_out_bits {
6818 u8 status[0x8];
6819 u8 reserved_at_8[0x18];
6820
6821 u8 syndrome[0x20];
6822
6823 u8 reserved_at_40[0x8];
6824 u8 xrqn[0x18];
6825
6826 u8 reserved_at_60[0x20];
6827};
6828
6829struct mlx5_ifc_create_xrq_in_bits {
6830 u8 opcode[0x10];
a0d8c054 6831 u8 uid[0x10];
7486216b
SM		 6832
6833 u8 reserved_at_20[0x10];
6834 u8 op_mod[0x10];
6835
6836 u8 reserved_at_40[0x40];
6837
6838 struct mlx5_ifc_xrqc_bits xrq_context;
6839};
6840
e281682b
SM		 6841struct mlx5_ifc_create_xrc_srq_out_bits {
6842 u8 status[0x8];
b4ff3a36 6843 u8 reserved_at_8[0x18];
e281682b
SM		 6844
6845 u8 syndrome[0x20];
6846
b4ff3a36 6847 u8 reserved_at_40[0x8];
e281682b
SM		 6848 u8 xrc_srqn[0x18];
6849
b4ff3a36 6850 u8 reserved_at_60[0x20];
e281682b
SM		 6851};
6852
6853struct mlx5_ifc_create_xrc_srq_in_bits {
6854 u8 opcode[0x10];
a0d8c054 6855 u8 uid[0x10];
e281682b 6856
b4ff3a36 6857 u8 reserved_at_20[0x10];
e281682b
SM		 6858 u8 op_mod[0x10];
6859
b4ff3a36 6860 u8 reserved_at_40[0x40];
e281682b
SM		 6861
6862 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6863
99b77fef
YH		 6864 u8 reserved_at_280[0x60];
6865
bd371975 6866 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 6867 u8 reserved_at_2e1[0x1f];
6868
6869 u8 reserved_at_300[0x580];
e281682b
SM		 6870
6871 u8 pas[0][0x40];
6872};
6873
6874struct mlx5_ifc_create_tis_out_bits {
6875 u8 status[0x8];
b4ff3a36 6876 u8 reserved_at_8[0x18];
e281682b
SM		 6877
6878 u8 syndrome[0x20];
6879
b4ff3a36 6880 u8 reserved_at_40[0x8];
e281682b
SM		 6881 u8 tisn[0x18];
6882
b4ff3a36 6883 u8 reserved_at_60[0x20];
e281682b
SM		 6884};
6885
6886struct mlx5_ifc_create_tis_in_bits {
6887 u8 opcode[0x10];
bd371975 6888 u8 uid[0x10];
e281682b 6889
b4ff3a36 6890 u8 reserved_at_20[0x10];
e281682b
SM		 6891 u8 op_mod[0x10];
6892
b4ff3a36 6893 u8 reserved_at_40[0xc0];
e281682b
SM		 6894
6895 struct mlx5_ifc_tisc_bits ctx;
6896};
6897
6898struct mlx5_ifc_create_tir_out_bits {
6899 u8 status[0x8];
3e070470 6900 u8 icm_address_63_40[0x18];
e281682b
SM		 6901
6902 u8 syndrome[0x20];
6903
3e070470 6904 u8 icm_address_39_32[0x8];
e281682b
SM		 6905 u8 tirn[0x18];
6906
3e070470 6907 u8 icm_address_31_0[0x20];
e281682b
SM		 6908};
6909
6910struct mlx5_ifc_create_tir_in_bits {
6911 u8 opcode[0x10];
bd371975 6912 u8 uid[0x10];
e281682b 6913
b4ff3a36 6914 u8 reserved_at_20[0x10];
e281682b
SM		 6915 u8 op_mod[0x10];
6916
b4ff3a36 6917 u8 reserved_at_40[0xc0];
e281682b
SM		 6918
6919 struct mlx5_ifc_tirc_bits ctx;
6920};
6921
6922struct mlx5_ifc_create_srq_out_bits {
6923 u8 status[0x8];
b4ff3a36 6924 u8 reserved_at_8[0x18];
e281682b
SM		 6925
6926 u8 syndrome[0x20];
6927
b4ff3a36 6928 u8 reserved_at_40[0x8];
e281682b
SM		 6929 u8 srqn[0x18];
6930
b4ff3a36 6931 u8 reserved_at_60[0x20];
e281682b
SM		 6932};
6933
6934struct mlx5_ifc_create_srq_in_bits {
6935 u8 opcode[0x10];
a0d8c054 6936 u8 uid[0x10];
e281682b 6937
b4ff3a36 6938 u8 reserved_at_20[0x10];
e281682b
SM		 6939 u8 op_mod[0x10];
6940
b4ff3a36 6941 u8 reserved_at_40[0x40];
e281682b
SM		 6942
6943 struct mlx5_ifc_srqc_bits srq_context_entry;
6944
b4ff3a36 6945 u8 reserved_at_280[0x600];
e281682b
SM		 6946
6947 u8 pas[0][0x40];
6948};
6949
6950struct mlx5_ifc_create_sq_out_bits {
6951 u8 status[0x8];
b4ff3a36 6952 u8 reserved_at_8[0x18];
e281682b
SM		 6953
6954 u8 syndrome[0x20];
6955
b4ff3a36 6956 u8 reserved_at_40[0x8];
e281682b
SM		 6957 u8 sqn[0x18];
6958
b4ff3a36 6959 u8 reserved_at_60[0x20];
e281682b
SM		 6960};
6961
6962struct mlx5_ifc_create_sq_in_bits {
6963 u8 opcode[0x10];
430ae0d5 6964 u8 uid[0x10];
e281682b 6965
b4ff3a36 6966 u8 reserved_at_20[0x10];
e281682b
SM		 6967 u8 op_mod[0x10];
6968
b4ff3a36 6969 u8 reserved_at_40[0xc0];
e281682b
SM		 6970
6971 struct mlx5_ifc_sqc_bits ctx;
6972};
6973
813f8540
MHY		 6974struct mlx5_ifc_create_scheduling_element_out_bits {
6975 u8 status[0x8];
6976 u8 reserved_at_8[0x18];
6977
6978 u8 syndrome[0x20];
6979
6980 u8 reserved_at_40[0x40];
6981
6982 u8 scheduling_element_id[0x20];
6983
6984 u8 reserved_at_a0[0x160];
6985};
6986
6987struct mlx5_ifc_create_scheduling_element_in_bits {
6988 u8 opcode[0x10];
6989 u8 reserved_at_10[0x10];
6990
6991 u8 reserved_at_20[0x10];
6992 u8 op_mod[0x10];
6993
6994 u8 scheduling_hierarchy[0x8];
6995 u8 reserved_at_48[0x18];
6996
6997 u8 reserved_at_60[0xa0];
6998
6999 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7000
7001 u8 reserved_at_300[0x100];
7002};
7003
e281682b
SM		 7004struct mlx5_ifc_create_rqt_out_bits {
7005 u8 status[0x8];
b4ff3a36 7006 u8 reserved_at_8[0x18];
e281682b
SM		 7007
7008 u8 syndrome[0x20];
7009
b4ff3a36 7010 u8 reserved_at_40[0x8];
e281682b
SM		 7011 u8 rqtn[0x18];
7012
b4ff3a36 7013 u8 reserved_at_60[0x20];
e281682b
SM		 7014};
7015
7016struct mlx5_ifc_create_rqt_in_bits {
7017 u8 opcode[0x10];
bd371975 7018 u8 uid[0x10];
e281682b 7019
b4ff3a36 7020 u8 reserved_at_20[0x10];
e281682b
SM		 7021 u8 op_mod[0x10];
7022
b4ff3a36 7023 u8 reserved_at_40[0xc0];
e281682b
SM		 7024
7025 struct mlx5_ifc_rqtc_bits rqt_context;
7026};
7027
7028struct mlx5_ifc_create_rq_out_bits {
7029 u8 status[0x8];
b4ff3a36 7030 u8 reserved_at_8[0x18];
e281682b
SM		 7031
7032 u8 syndrome[0x20];
7033
b4ff3a36 7034 u8 reserved_at_40[0x8];
e281682b
SM		 7035 u8 rqn[0x18];
7036
b4ff3a36 7037 u8 reserved_at_60[0x20];
e281682b
SM		 7038};
7039
7040struct mlx5_ifc_create_rq_in_bits {
7041 u8 opcode[0x10];
d269b3af 7042 u8 uid[0x10];
e281682b 7043
b4ff3a36 7044 u8 reserved_at_20[0x10];
e281682b
SM		 7045 u8 op_mod[0x10];
7046
b4ff3a36 7047 u8 reserved_at_40[0xc0];
e281682b
SM		 7048
7049 struct mlx5_ifc_rqc_bits ctx;
7050};
7051
7052struct mlx5_ifc_create_rmp_out_bits {
7053 u8 status[0x8];
b4ff3a36 7054 u8 reserved_at_8[0x18];
e281682b
SM		 7055
7056 u8 syndrome[0x20];
7057
b4ff3a36 7058 u8 reserved_at_40[0x8];
e281682b
SM		 7059 u8 rmpn[0x18];
7060
b4ff3a36 7061 u8 reserved_at_60[0x20];
e281682b
SM		 7062};
7063
7064struct mlx5_ifc_create_rmp_in_bits {
7065 u8 opcode[0x10];
a0d8c054 7066 u8 uid[0x10];
e281682b 7067
b4ff3a36 7068 u8 reserved_at_20[0x10];
e281682b
SM		 7069 u8 op_mod[0x10];
7070
b4ff3a36 7071 u8 reserved_at_40[0xc0];
e281682b
SM		 7072
7073 struct mlx5_ifc_rmpc_bits ctx;
7074};
7075
7076struct mlx5_ifc_create_qp_out_bits {
7077 u8 status[0x8];
b4ff3a36 7078 u8 reserved_at_8[0x18];
e281682b
SM		 7079
7080 u8 syndrome[0x20];
7081
b4ff3a36 7082 u8 reserved_at_40[0x8];
e281682b
SM		 7083 u8 qpn[0x18];
7084
b4ff3a36 7085 u8 reserved_at_60[0x20];
e281682b
SM		 7086};
7087
7088struct mlx5_ifc_create_qp_in_bits {
7089 u8 opcode[0x10];
4ac63ec7 7090 u8 uid[0x10];
e281682b 7091
b4ff3a36 7092 u8 reserved_at_20[0x10];
e281682b
SM		 7093 u8 op_mod[0x10];
7094
b4ff3a36 7095 u8 reserved_at_40[0x40];
e281682b
SM		 7096
7097 u8 opt_param_mask[0x20];
7098
b4ff3a36 7099 u8 reserved_at_a0[0x20];
e281682b
SM		 7100
7101 struct mlx5_ifc_qpc_bits qpc;
7102
bd371975
LR		 7103 u8 reserved_at_800[0x60];
7104
7105 u8 wq_umem_valid[0x1];
7106 u8 reserved_at_861[0x1f];
e281682b
SM		 7107
7108 u8 pas[0][0x40];
7109};
7110
7111struct mlx5_ifc_create_psv_out_bits {
7112 u8 status[0x8];
b4ff3a36 7113 u8 reserved_at_8[0x18];
e281682b
SM		 7114
7115 u8 syndrome[0x20];
7116
b4ff3a36 7117 u8 reserved_at_40[0x40];
e281682b 7118
b4ff3a36 7119 u8 reserved_at_80[0x8];
e281682b
SM		 7120 u8 psv0_index[0x18];
7121
b4ff3a36 7122 u8 reserved_at_a0[0x8];
e281682b
SM		 7123 u8 psv1_index[0x18];
7124
b4ff3a36 7125 u8 reserved_at_c0[0x8];
e281682b
SM		 7126 u8 psv2_index[0x18];
7127
b4ff3a36 7128 u8 reserved_at_e0[0x8];
e281682b
SM		 7129 u8 psv3_index[0x18];
7130};
7131
7132struct mlx5_ifc_create_psv_in_bits {
7133 u8 opcode[0x10];
b4ff3a36 7134 u8 reserved_at_10[0x10];
e281682b 7135
b4ff3a36 7136 u8 reserved_at_20[0x10];
e281682b
SM		 7137 u8 op_mod[0x10];
7138
7139 u8 num_psv[0x4];
b4ff3a36 7140 u8 reserved_at_44[0x4];
e281682b
SM		 7141 u8 pd[0x18];
7142
b4ff3a36 7143 u8 reserved_at_60[0x20];
e281682b
SM		 7144};
7145
7146struct mlx5_ifc_create_mkey_out_bits {
7147 u8 status[0x8];
b4ff3a36 7148 u8 reserved_at_8[0x18];
e281682b
SM		 7149
7150 u8 syndrome[0x20];
7151
b4ff3a36 7152 u8 reserved_at_40[0x8];
e281682b
SM		 7153 u8 mkey_index[0x18];
7154
b4ff3a36 7155 u8 reserved_at_60[0x20];
e281682b
SM		 7156};
7157
7158struct mlx5_ifc_create_mkey_in_bits {
7159 u8 opcode[0x10];
b4ff3a36 7160 u8 reserved_at_10[0x10];
e281682b 7161
b4ff3a36 7162 u8 reserved_at_20[0x10];
e281682b
SM		 7163 u8 op_mod[0x10];
7164
b4ff3a36 7165 u8 reserved_at_40[0x20];
e281682b
SM		 7166
7167 u8 pg_access[0x1];
bd371975
LR		 7168 u8 mkey_umem_valid[0x1];
7169 u8 reserved_at_62[0x1e];
e281682b
SM		 7170
7171 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7172
b4ff3a36 7173 u8 reserved_at_280[0x80];
e281682b
SM		 7174
7175 u8 translations_octword_actual_size[0x20];
7176
b4ff3a36 7177 u8 reserved_at_320[0x560];
e281682b
SM		 7178
7179 u8 klm_pas_mtt[0][0x20];
7180};
7181
7182struct mlx5_ifc_create_flow_table_out_bits {
7183 u8 status[0x8];
b4ff3a36 7184 u8 reserved_at_8[0x18];
e281682b
SM		 7185
7186 u8 syndrome[0x20];
7187
b4ff3a36 7188 u8 reserved_at_40[0x8];
e281682b
SM		 7189 u8 table_id[0x18];
7190
b4ff3a36 7191 u8 reserved_at_60[0x20];
e281682b
SM		 7192};
7193
0c90e9c6 7194struct mlx5_ifc_flow_table_context_bits {
60786f09 7195 u8 reformat_en[0x1];
0c90e9c6
MG		 7196 u8 decap_en[0x1];
7197 u8 reserved_at_2[0x2];
7198 u8 table_miss_action[0x4];
7199 u8 level[0x8];
7200 u8 reserved_at_10[0x8];
7201 u8 log_size[0x8];
7202
7203 u8 reserved_at_20[0x8];
7204 u8 table_miss_id[0x18];
7205
7206 u8 reserved_at_40[0x8];
7207 u8 lag_master_next_table_id[0x18];
7208
7209 u8 reserved_at_60[0xe0];
7210};
7211
e281682b
SM		 7212struct mlx5_ifc_create_flow_table_in_bits {
7213 u8 opcode[0x10];
b4ff3a36 7214 u8 reserved_at_10[0x10];
e281682b 7215
b4ff3a36 7216 u8 reserved_at_20[0x10];
e281682b
SM		 7217 u8 op_mod[0x10];
7218
7d5e1423
SM		 7219 u8 other_vport[0x1];
7220 u8 reserved_at_41[0xf];
7221 u8 vport_number[0x10];
7222
7223 u8 reserved_at_60[0x20];
e281682b
SM		 7224
7225 u8 table_type[0x8];
b4ff3a36 7226 u8 reserved_at_88[0x18];
e281682b 7227
b4ff3a36 7228 u8 reserved_at_a0[0x20];
e281682b 7229
0c90e9c6 7230 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 7231};
7232
7233struct mlx5_ifc_create_flow_group_out_bits {
7234 u8 status[0x8];
b4ff3a36 7235 u8 reserved_at_8[0x18];
e281682b
SM		 7236
7237 u8 syndrome[0x20];
7238
b4ff3a36 7239 u8 reserved_at_40[0x8];
e281682b
SM		 7240 u8 group_id[0x18];
7241
b4ff3a36 7242 u8 reserved_at_60[0x20];
e281682b
SM		 7243};
7244
7245enum {
71c6e863
AL		 7246 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7247 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7248 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7249 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 7250};
7251
7252struct mlx5_ifc_create_flow_group_in_bits {
7253 u8 opcode[0x10];
b4ff3a36 7254 u8 reserved_at_10[0x10];
e281682b 7255
b4ff3a36 7256 u8 reserved_at_20[0x10];
e281682b
SM		 7257 u8 op_mod[0x10];
7258
7d5e1423
SM		 7259 u8 other_vport[0x1];
7260 u8 reserved_at_41[0xf];
7261 u8 vport_number[0x10];
7262
7263 u8 reserved_at_60[0x20];
e281682b
SM		 7264
7265 u8 table_type[0x8];
b4ff3a36 7266 u8 reserved_at_88[0x18];
e281682b 7267
b4ff3a36 7268 u8 reserved_at_a0[0x8];
e281682b
SM		 7269 u8 table_id[0x18];
7270
3e99df87
SK		 7271 u8 source_eswitch_owner_vhca_id_valid[0x1];
7272
7273 u8 reserved_at_c1[0x1f];
e281682b
SM		 7274
7275 u8 start_flow_index[0x20];
7276
b4ff3a36 7277 u8 reserved_at_100[0x20];
e281682b
SM		 7278
7279 u8 end_flow_index[0x20];
7280
b4ff3a36 7281 u8 reserved_at_140[0xa0];
e281682b 7282
b4ff3a36 7283 u8 reserved_at_1e0[0x18];
e281682b
SM		 7284 u8 match_criteria_enable[0x8];
7285
7286 struct mlx5_ifc_fte_match_param_bits match_criteria;
7287
b4ff3a36 7288 u8 reserved_at_1200[0xe00];
e281682b
SM		 7289};
7290
7291struct mlx5_ifc_create_eq_out_bits {
7292 u8 status[0x8];
b4ff3a36 7293 u8 reserved_at_8[0x18];
e281682b
SM		 7294
7295 u8 syndrome[0x20];
7296
b4ff3a36 7297 u8 reserved_at_40[0x18];
e281682b
SM		 7298 u8 eq_number[0x8];
7299
b4ff3a36 7300 u8 reserved_at_60[0x20];
e281682b
SM		 7301};
7302
7303struct mlx5_ifc_create_eq_in_bits {
7304 u8 opcode[0x10];
b4ff3a36 7305 u8 reserved_at_10[0x10];
e281682b 7306
b4ff3a36 7307 u8 reserved_at_20[0x10];
e281682b
SM		 7308 u8 op_mod[0x10];
7309
b4ff3a36 7310 u8 reserved_at_40[0x40];
e281682b
SM		 7311
7312 struct mlx5_ifc_eqc_bits eq_context_entry;
7313
b4ff3a36 7314 u8 reserved_at_280[0x40];
e281682b
SM		 7315
7316 u8 event_bitmask[0x40];
7317
b4ff3a36 7318 u8 reserved_at_300[0x580];
e281682b
SM		 7319
7320 u8 pas[0][0x40];
7321};
7322
7323struct mlx5_ifc_create_dct_out_bits {
7324 u8 status[0x8];
b4ff3a36 7325 u8 reserved_at_8[0x18];
e281682b
SM		 7326
7327 u8 syndrome[0x20];
7328
b4ff3a36 7329 u8 reserved_at_40[0x8];
e281682b
SM		 7330 u8 dctn[0x18];
7331
b4ff3a36 7332 u8 reserved_at_60[0x20];
e281682b
SM		 7333};
7334
7335struct mlx5_ifc_create_dct_in_bits {
7336 u8 opcode[0x10];
774ea6ee 7337 u8 uid[0x10];
e281682b 7338
b4ff3a36 7339 u8 reserved_at_20[0x10];
e281682b
SM		 7340 u8 op_mod[0x10];
7341
b4ff3a36 7342 u8 reserved_at_40[0x40];
e281682b
SM		 7343
7344 struct mlx5_ifc_dctc_bits dct_context_entry;
7345
b4ff3a36 7346 u8 reserved_at_280[0x180];
e281682b
SM		 7347};
7348
7349struct mlx5_ifc_create_cq_out_bits {
7350 u8 status[0x8];
b4ff3a36 7351 u8 reserved_at_8[0x18];
e281682b
SM		 7352
7353 u8 syndrome[0x20];
7354
b4ff3a36 7355 u8 reserved_at_40[0x8];
e281682b
SM		 7356 u8 cqn[0x18];
7357
b4ff3a36 7358 u8 reserved_at_60[0x20];
e281682b
SM		 7359};
7360
7361struct mlx5_ifc_create_cq_in_bits {
7362 u8 opcode[0x10];
9ba481e2 7363 u8 uid[0x10];
e281682b 7364
b4ff3a36 7365 u8 reserved_at_20[0x10];
e281682b
SM		 7366 u8 op_mod[0x10];
7367
b4ff3a36 7368 u8 reserved_at_40[0x40];
e281682b
SM		 7369
7370 struct mlx5_ifc_cqc_bits cq_context;
7371
bd371975
LR		 7372 u8 reserved_at_280[0x60];
7373
7374 u8 cq_umem_valid[0x1];
7375 u8 reserved_at_2e1[0x59f];
e281682b
SM		 7376
7377 u8 pas[0][0x40];
7378};
7379
7380struct mlx5_ifc_config_int_moderation_out_bits {
7381 u8 status[0x8];
b4ff3a36 7382 u8 reserved_at_8[0x18];
e281682b
SM		 7383
7384 u8 syndrome[0x20];
7385
b4ff3a36 7386 u8 reserved_at_40[0x4];
e281682b
SM		 7387 u8 min_delay[0xc];
7388 u8 int_vector[0x10];
7389
b4ff3a36 7390 u8 reserved_at_60[0x20];
e281682b
SM		 7391};
7392
7393enum {
7394 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7395 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7396};
7397
7398struct mlx5_ifc_config_int_moderation_in_bits {
7399 u8 opcode[0x10];
b4ff3a36 7400 u8 reserved_at_10[0x10];
e281682b 7401
b4ff3a36 7402 u8 reserved_at_20[0x10];
e281682b
SM		 7403 u8 op_mod[0x10];
7404
b4ff3a36 7405 u8 reserved_at_40[0x4];
e281682b
SM		 7406 u8 min_delay[0xc];
7407 u8 int_vector[0x10];
7408
b4ff3a36 7409 u8 reserved_at_60[0x20];
e281682b
SM		 7410};
7411
7412struct mlx5_ifc_attach_to_mcg_out_bits {
7413 u8 status[0x8];
b4ff3a36 7414 u8 reserved_at_8[0x18];
e281682b
SM		 7415
7416 u8 syndrome[0x20];
7417
b4ff3a36 7418 u8 reserved_at_40[0x40];
e281682b
SM		 7419};
7420
7421struct mlx5_ifc_attach_to_mcg_in_bits {
7422 u8 opcode[0x10];
bd371975 7423 u8 uid[0x10];
e281682b 7424
b4ff3a36 7425 u8 reserved_at_20[0x10];
e281682b
SM		 7426 u8 op_mod[0x10];
7427
b4ff3a36 7428 u8 reserved_at_40[0x8];
e281682b
SM		 7429 u8 qpn[0x18];
7430
b4ff3a36 7431 u8 reserved_at_60[0x20];
e281682b
SM		 7432
7433 u8 multicast_gid[16][0x8];
7434};
7435
7486216b
SM		 7436struct mlx5_ifc_arm_xrq_out_bits {
7437 u8 status[0x8];
7438 u8 reserved_at_8[0x18];
7439
7440 u8 syndrome[0x20];
7441
7442 u8 reserved_at_40[0x40];
7443};
7444
7445struct mlx5_ifc_arm_xrq_in_bits {
7446 u8 opcode[0x10];
7447 u8 reserved_at_10[0x10];
7448
7449 u8 reserved_at_20[0x10];
7450 u8 op_mod[0x10];
7451
7452 u8 reserved_at_40[0x8];
7453 u8 xrqn[0x18];
7454
7455 u8 reserved_at_60[0x10];
7456 u8 lwm[0x10];
7457};
7458
e281682b
SM		 7459struct mlx5_ifc_arm_xrc_srq_out_bits {
7460 u8 status[0x8];
b4ff3a36 7461 u8 reserved_at_8[0x18];
e281682b
SM		 7462
7463 u8 syndrome[0x20];
7464
b4ff3a36 7465 u8 reserved_at_40[0x40];
e281682b
SM		 7466};
7467
7468enum {
7469 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7470};
7471
7472struct mlx5_ifc_arm_xrc_srq_in_bits {
7473 u8 opcode[0x10];
a0d8c054 7474 u8 uid[0x10];
e281682b 7475
b4ff3a36 7476 u8 reserved_at_20[0x10];
e281682b
SM		 7477 u8 op_mod[0x10];
7478
b4ff3a36 7479 u8 reserved_at_40[0x8];
e281682b
SM		 7480 u8 xrc_srqn[0x18];
7481
b4ff3a36 7482 u8 reserved_at_60[0x10];
e281682b
SM		 7483 u8 lwm[0x10];
7484};
7485
7486struct mlx5_ifc_arm_rq_out_bits {
7487 u8 status[0x8];
b4ff3a36 7488 u8 reserved_at_8[0x18];
e281682b
SM		 7489
7490 u8 syndrome[0x20];
7491
b4ff3a36 7492 u8 reserved_at_40[0x40];
e281682b
SM		 7493};
7494
7495enum {
7486216b
SM		 7496 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7497 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7498};
7499
7500struct mlx5_ifc_arm_rq_in_bits {
7501 u8 opcode[0x10];
a0d8c054 7502 u8 uid[0x10];
e281682b 7503
b4ff3a36 7504 u8 reserved_at_20[0x10];
e281682b
SM		 7505 u8 op_mod[0x10];
7506
b4ff3a36 7507 u8 reserved_at_40[0x8];
e281682b
SM		 7508 u8 srq_number[0x18];
7509
b4ff3a36 7510 u8 reserved_at_60[0x10];
e281682b
SM		 7511 u8 lwm[0x10];
7512};
7513
7514struct mlx5_ifc_arm_dct_out_bits {
7515 u8 status[0x8];
b4ff3a36 7516 u8 reserved_at_8[0x18];
e281682b
SM		 7517
7518 u8 syndrome[0x20];
7519
b4ff3a36 7520 u8 reserved_at_40[0x40];
e281682b
SM		 7521};
7522
7523struct mlx5_ifc_arm_dct_in_bits {
7524 u8 opcode[0x10];
b4ff3a36 7525 u8 reserved_at_10[0x10];
e281682b 7526
b4ff3a36 7527 u8 reserved_at_20[0x10];
e281682b
SM		 7528 u8 op_mod[0x10];
7529
b4ff3a36 7530 u8 reserved_at_40[0x8];
e281682b
SM		 7531 u8 dct_number[0x18];
7532
b4ff3a36 7533 u8 reserved_at_60[0x20];
e281682b
SM		 7534};
7535
7536struct mlx5_ifc_alloc_xrcd_out_bits {
7537 u8 status[0x8];
b4ff3a36 7538 u8 reserved_at_8[0x18];
e281682b
SM		 7539
7540 u8 syndrome[0x20];
7541
b4ff3a36 7542 u8 reserved_at_40[0x8];
e281682b
SM		 7543 u8 xrcd[0x18];
7544
b4ff3a36 7545 u8 reserved_at_60[0x20];
e281682b
SM		 7546};
7547
7548struct mlx5_ifc_alloc_xrcd_in_bits {
7549 u8 opcode[0x10];
bd371975 7550 u8 uid[0x10];
e281682b 7551
b4ff3a36 7552 u8 reserved_at_20[0x10];
e281682b
SM		 7553 u8 op_mod[0x10];
7554
b4ff3a36 7555 u8 reserved_at_40[0x40];
e281682b
SM		 7556};
7557
7558struct mlx5_ifc_alloc_uar_out_bits {
7559 u8 status[0x8];
b4ff3a36 7560 u8 reserved_at_8[0x18];
e281682b
SM		 7561
7562 u8 syndrome[0x20];
7563
b4ff3a36 7564 u8 reserved_at_40[0x8];
e281682b
SM		 7565 u8 uar[0x18];
7566
b4ff3a36 7567 u8 reserved_at_60[0x20];
e281682b
SM		 7568};
7569
7570struct mlx5_ifc_alloc_uar_in_bits {
7571 u8 opcode[0x10];
b4ff3a36 7572 u8 reserved_at_10[0x10];
e281682b 7573
b4ff3a36 7574 u8 reserved_at_20[0x10];
e281682b
SM		 7575 u8 op_mod[0x10];
7576
b4ff3a36 7577 u8 reserved_at_40[0x40];
e281682b
SM		 7578};
7579
7580struct mlx5_ifc_alloc_transport_domain_out_bits {
7581 u8 status[0x8];
b4ff3a36 7582 u8 reserved_at_8[0x18];
e281682b
SM		 7583
7584 u8 syndrome[0x20];
7585
b4ff3a36 7586 u8 reserved_at_40[0x8];
e281682b
SM		 7587 u8 transport_domain[0x18];
7588
b4ff3a36 7589 u8 reserved_at_60[0x20];
e281682b
SM		 7590};
7591
7592struct mlx5_ifc_alloc_transport_domain_in_bits {
7593 u8 opcode[0x10];
71bef2fd 7594 u8 uid[0x10];
e281682b 7595
b4ff3a36 7596 u8 reserved_at_20[0x10];
e281682b
SM		 7597 u8 op_mod[0x10];
7598
b4ff3a36 7599 u8 reserved_at_40[0x40];
e281682b
SM		 7600};
7601
7602struct mlx5_ifc_alloc_q_counter_out_bits {
7603 u8 status[0x8];
b4ff3a36 7604 u8 reserved_at_8[0x18];
e281682b
SM		 7605
7606 u8 syndrome[0x20];
7607
b4ff3a36 7608 u8 reserved_at_40[0x18];
e281682b
SM		 7609 u8 counter_set_id[0x8];
7610
b4ff3a36 7611 u8 reserved_at_60[0x20];
e281682b
SM		 7612};
7613
7614struct mlx5_ifc_alloc_q_counter_in_bits {
7615 u8 opcode[0x10];
2acc7957 7616 u8 uid[0x10];
e281682b 7617
b4ff3a36 7618 u8 reserved_at_20[0x10];
e281682b
SM		 7619 u8 op_mod[0x10];
7620
b4ff3a36 7621 u8 reserved_at_40[0x40];
e281682b
SM		 7622};
7623
7624struct mlx5_ifc_alloc_pd_out_bits {
7625 u8 status[0x8];
b4ff3a36 7626 u8 reserved_at_8[0x18];
e281682b
SM		 7627
7628 u8 syndrome[0x20];
7629
b4ff3a36 7630 u8 reserved_at_40[0x8];
e281682b
SM		 7631 u8 pd[0x18];
7632
b4ff3a36 7633 u8 reserved_at_60[0x20];
e281682b
SM		 7634};
7635
7636struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 7637 u8 opcode[0x10];
bd371975 7638 u8 uid[0x10];
9dc0b289
AV		 7639
7640 u8 reserved_at_20[0x10];
7641 u8 op_mod[0x10];
7642
7643 u8 reserved_at_40[0x40];
7644};
7645
7646struct mlx5_ifc_alloc_flow_counter_out_bits {
7647 u8 status[0x8];
7648 u8 reserved_at_8[0x18];
7649
7650 u8 syndrome[0x20];
7651
a8ffcc74 7652 u8 flow_counter_id[0x20];
9dc0b289
AV		 7653
7654 u8 reserved_at_60[0x20];
7655};
7656
7657struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7658 u8 opcode[0x10];
b4ff3a36 7659 u8 reserved_at_10[0x10];
e281682b 7660
b4ff3a36 7661 u8 reserved_at_20[0x10];
e281682b
SM		 7662 u8 op_mod[0x10];
7663
b4ff3a36 7664 u8 reserved_at_40[0x40];
e281682b
SM		 7665};
7666
7667struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7668 u8 status[0x8];
b4ff3a36 7669 u8 reserved_at_8[0x18];
e281682b
SM		 7670
7671 u8 syndrome[0x20];
7672
b4ff3a36 7673 u8 reserved_at_40[0x40];
e281682b
SM		 7674};
7675
7676struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7677 u8 opcode[0x10];
b4ff3a36 7678 u8 reserved_at_10[0x10];
e281682b 7679
b4ff3a36 7680 u8 reserved_at_20[0x10];
e281682b
SM		 7681 u8 op_mod[0x10];
7682
b4ff3a36 7683 u8 reserved_at_40[0x20];
e281682b 7684
b4ff3a36 7685 u8 reserved_at_60[0x10];
e281682b
SM		 7686 u8 vxlan_udp_port[0x10];
7687};
7688
37e92a9d 7689struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7690 u8 status[0x8];
7691 u8 reserved_at_8[0x18];
7692
7693 u8 syndrome[0x20];
7694
7695 u8 reserved_at_40[0x40];
7696};
7697
37e92a9d 7698struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7699 u8 opcode[0x10];
7700 u8 reserved_at_10[0x10];
7701
7702 u8 reserved_at_20[0x10];
7703 u8 op_mod[0x10];
7704
7705 u8 reserved_at_40[0x10];
7706 u8 rate_limit_index[0x10];
7707
7708 u8 reserved_at_60[0x20];
7709
7710 u8 rate_limit[0x20];
37e92a9d 7711
05d3ac97
BW		 7712 u8 burst_upper_bound[0x20];
7713
7714 u8 reserved_at_c0[0x10];
7715 u8 typical_packet_size[0x10];
7716
7717 u8 reserved_at_e0[0x120];
7486216b
SM		 7718};
7719
e281682b
SM		 7720struct mlx5_ifc_access_register_out_bits {
7721 u8 status[0x8];
b4ff3a36 7722 u8 reserved_at_8[0x18];
e281682b
SM		 7723
7724 u8 syndrome[0x20];
7725
b4ff3a36 7726 u8 reserved_at_40[0x40];
e281682b
SM		 7727
7728 u8 register_data[0][0x20];
7729};
7730
7731enum {
7732 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7733 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7734};
7735
7736struct mlx5_ifc_access_register_in_bits {
7737 u8 opcode[0x10];
b4ff3a36 7738 u8 reserved_at_10[0x10];
e281682b 7739
b4ff3a36 7740 u8 reserved_at_20[0x10];
e281682b
SM		 7741 u8 op_mod[0x10];
7742
b4ff3a36 7743 u8 reserved_at_40[0x10];
e281682b
SM		 7744 u8 register_id[0x10];
7745
7746 u8 argument[0x20];
7747
7748 u8 register_data[0][0x20];
7749};
7750
7751struct mlx5_ifc_sltp_reg_bits {
7752 u8 status[0x4];
7753 u8 version[0x4];
7754 u8 local_port[0x8];
7755 u8 pnat[0x2];
b4ff3a36 7756 u8 reserved_at_12[0x2];
e281682b 7757 u8 lane[0x4];
b4ff3a36 7758 u8 reserved_at_18[0x8];
e281682b 7759
b4ff3a36 7760 u8 reserved_at_20[0x20];
e281682b 7761
b4ff3a36 7762 u8 reserved_at_40[0x7];
e281682b
SM		 7763 u8 polarity[0x1];
7764 u8 ob_tap0[0x8];
7765 u8 ob_tap1[0x8];
7766 u8 ob_tap2[0x8];
7767
b4ff3a36 7768 u8 reserved_at_60[0xc];
e281682b
SM		 7769 u8 ob_preemp_mode[0x4];
7770 u8 ob_reg[0x8];
7771 u8 ob_bias[0x8];
7772
b4ff3a36 7773 u8 reserved_at_80[0x20];
e281682b
SM		 7774};
7775
7776struct mlx5_ifc_slrg_reg_bits {
7777 u8 status[0x4];
7778 u8 version[0x4];
7779 u8 local_port[0x8];
7780 u8 pnat[0x2];
b4ff3a36 7781 u8 reserved_at_12[0x2];
e281682b 7782 u8 lane[0x4];
b4ff3a36 7783 u8 reserved_at_18[0x8];
e281682b
SM		 7784
7785 u8 time_to_link_up[0x10];
b4ff3a36 7786 u8 reserved_at_30[0xc];
e281682b
SM		 7787 u8 grade_lane_speed[0x4];
7788
7789 u8 grade_version[0x8];
7790 u8 grade[0x18];
7791
b4ff3a36 7792 u8 reserved_at_60[0x4];
e281682b
SM		 7793 u8 height_grade_type[0x4];
7794 u8 height_grade[0x18];
7795
7796 u8 height_dz[0x10];
7797 u8 height_dv[0x10];
7798
b4ff3a36 7799 u8 reserved_at_a0[0x10];
e281682b
SM		 7800 u8 height_sigma[0x10];
7801
b4ff3a36 7802 u8 reserved_at_c0[0x20];
e281682b 7803
b4ff3a36 7804 u8 reserved_at_e0[0x4];
e281682b
SM		 7805 u8 phase_grade_type[0x4];
7806 u8 phase_grade[0x18];
7807
b4ff3a36 7808 u8 reserved_at_100[0x8];
e281682b 7809 u8 phase_eo_pos[0x8];
b4ff3a36 7810 u8 reserved_at_110[0x8];
e281682b
SM		 7811 u8 phase_eo_neg[0x8];
7812
7813 u8 ffe_set_tested[0x10];
7814 u8 test_errors_per_lane[0x10];
7815};
7816
7817struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7818 u8 reserved_at_0[0x8];
e281682b 7819 u8 local_port[0x8];
b4ff3a36 7820 u8 reserved_at_10[0x10];
e281682b 7821
b4ff3a36 7822 u8 reserved_at_20[0x1c];
e281682b
SM		 7823 u8 vl_hw_cap[0x4];
7824
b4ff3a36 7825 u8 reserved_at_40[0x1c];
e281682b
SM		 7826 u8 vl_admin[0x4];
7827
b4ff3a36 7828 u8 reserved_at_60[0x1c];
e281682b
SM		 7829 u8 vl_operational[0x4];
7830};
7831
7832struct mlx5_ifc_pude_reg_bits {
7833 u8 swid[0x8];
7834 u8 local_port[0x8];
b4ff3a36 7835 u8 reserved_at_10[0x4];
e281682b 7836 u8 admin_status[0x4];
b4ff3a36 7837 u8 reserved_at_18[0x4];
e281682b
SM		 7838 u8 oper_status[0x4];
7839
b4ff3a36 7840 u8 reserved_at_20[0x60];
e281682b
SM		 7841};
7842
7843struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7844 u8 reserved_at_0[0x1];
7486216b 7845 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7846 u8 an_disable_cap[0x1];
7847 u8 reserved_at_3[0x5];
e281682b 7848 u8 local_port[0x8];
b4ff3a36 7849 u8 reserved_at_10[0xd];
e281682b
SM		 7850 u8 proto_mask[0x3];
7851
7486216b 7852 u8 an_status[0x4];
a0a89989
AL		 7853 u8 reserved_at_24[0x1c];
7854
7855 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 7856
7857 u8 eth_proto_capability[0x20];
7858
7859 u8 ib_link_width_capability[0x10];
7860 u8 ib_proto_capability[0x10];
7861
a0a89989 7862 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 7863
7864 u8 eth_proto_admin[0x20];
7865
7866 u8 ib_link_width_admin[0x10];
7867 u8 ib_proto_admin[0x10];
7868
a0a89989 7869 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 7870
7871 u8 eth_proto_oper[0x20];
7872
7873 u8 ib_link_width_oper[0x10];
7874 u8 ib_proto_oper[0x10];
7875
5b4793f8
EBE		 7876 u8 reserved_at_160[0x1c];
7877 u8 connector_type[0x4];
e281682b
SM		 7878
7879 u8 eth_proto_lp_advertise[0x20];
7880
b4ff3a36 7881 u8 reserved_at_1a0[0x60];
e281682b
SM		 7882};
7883
7d5e1423
SM		 7884struct mlx5_ifc_mlcr_reg_bits {
7885 u8 reserved_at_0[0x8];
7886 u8 local_port[0x8];
7887 u8 reserved_at_10[0x20];
7888
7889 u8 beacon_duration[0x10];
7890 u8 reserved_at_40[0x10];
7891
7892 u8 beacon_remain[0x10];
7893};
7894
e281682b 7895struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7896 u8 reserved_at_0[0x20];
e281682b
SM		 7897
7898 u8 algorithm_options[0x10];
b4ff3a36 7899 u8 reserved_at_30[0x4];
e281682b
SM		 7900 u8 repetitions_mode[0x4];
7901 u8 num_of_repetitions[0x8];
7902
7903 u8 grade_version[0x8];
7904 u8 height_grade_type[0x4];
7905 u8 phase_grade_type[0x4];
7906 u8 height_grade_weight[0x8];
7907 u8 phase_grade_weight[0x8];
7908
7909 u8 gisim_measure_bits[0x10];
7910 u8 adaptive_tap_measure_bits[0x10];
7911
7912 u8 ber_bath_high_error_threshold[0x10];
7913 u8 ber_bath_mid_error_threshold[0x10];
7914
7915 u8 ber_bath_low_error_threshold[0x10];
7916 u8 one_ratio_high_threshold[0x10];
7917
7918 u8 one_ratio_high_mid_threshold[0x10];
7919 u8 one_ratio_low_mid_threshold[0x10];
7920
7921 u8 one_ratio_low_threshold[0x10];
7922 u8 ndeo_error_threshold[0x10];
7923
7924 u8 mixer_offset_step_size[0x10];
b4ff3a36 7925 u8 reserved_at_110[0x8];
e281682b
SM		 7926 u8 mix90_phase_for_voltage_bath[0x8];
7927
7928 u8 mixer_offset_start[0x10];
7929 u8 mixer_offset_end[0x10];
7930
b4ff3a36 7931 u8 reserved_at_140[0x15];
e281682b
SM		 7932 u8 ber_test_time[0xb];
7933};
7934
7935struct mlx5_ifc_pspa_reg_bits {
7936 u8 swid[0x8];
7937 u8 local_port[0x8];
7938 u8 sub_port[0x8];
b4ff3a36 7939 u8 reserved_at_18[0x8];
e281682b 7940
b4ff3a36 7941 u8 reserved_at_20[0x20];
e281682b
SM		 7942};
7943
7944struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7945 u8 reserved_at_0[0x8];
e281682b 7946 u8 local_port[0x8];
b4ff3a36 7947 u8 reserved_at_10[0x5];
e281682b 7948 u8 prio[0x3];
b4ff3a36 7949 u8 reserved_at_18[0x6];
e281682b
SM		 7950 u8 mode[0x2];
7951
b4ff3a36 7952 u8 reserved_at_20[0x20];
e281682b 7953
b4ff3a36 7954 u8 reserved_at_40[0x10];
e281682b
SM		 7955 u8 min_threshold[0x10];
7956
b4ff3a36 7957 u8 reserved_at_60[0x10];
e281682b
SM		 7958 u8 max_threshold[0x10];
7959
b4ff3a36 7960 u8 reserved_at_80[0x10];
e281682b
SM		 7961 u8 mark_probability_denominator[0x10];
7962
b4ff3a36 7963 u8 reserved_at_a0[0x60];
e281682b
SM		 7964};
7965
7966struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7967 u8 reserved_at_0[0x8];
e281682b 7968 u8 local_port[0x8];
b4ff3a36 7969 u8 reserved_at_10[0x10];
e281682b 7970
b4ff3a36 7971 u8 reserved_at_20[0x60];
e281682b 7972
b4ff3a36 7973 u8 reserved_at_80[0x1c];
e281682b
SM		 7974 u8 wrps_admin[0x4];
7975
b4ff3a36 7976 u8 reserved_at_a0[0x1c];
e281682b
SM		 7977 u8 wrps_status[0x4];
7978
b4ff3a36 7979 u8 reserved_at_c0[0x8];
e281682b 7980 u8 up_threshold[0x8];
b4ff3a36 7981 u8 reserved_at_d0[0x8];
e281682b
SM		 7982 u8 down_threshold[0x8];
7983
b4ff3a36 7984 u8 reserved_at_e0[0x20];
e281682b 7985
b4ff3a36 7986 u8 reserved_at_100[0x1c];
e281682b
SM		 7987 u8 srps_admin[0x4];
7988
b4ff3a36 7989 u8 reserved_at_120[0x1c];
e281682b
SM		 7990 u8 srps_status[0x4];
7991
b4ff3a36 7992 u8 reserved_at_140[0x40];
e281682b
SM		 7993};
7994
7995struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7996 u8 reserved_at_0[0x8];
e281682b 7997 u8 local_port[0x8];
b4ff3a36 7998 u8 reserved_at_10[0x10];
e281682b 7999
b4ff3a36 8000 u8 reserved_at_20[0x8];
e281682b 8001 u8 lb_cap[0x8];
b4ff3a36 8002 u8 reserved_at_30[0x8];
e281682b
SM		 8003 u8 lb_en[0x8];
8004};
8005
8006struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 8007 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 8008 u8 local_port[0x8];
8009 u8 reserved_at_10[0x10];
e281682b 8010
4b5b9c7d 8011 u8 reserved_at_20[0x20];
e281682b 8012
4b5b9c7d
SA		 8013 u8 port_profile_mode[0x8];
8014 u8 static_port_profile[0x8];
8015 u8 active_port_profile[0x8];
8016 u8 reserved_at_58[0x8];
e281682b 8017
4b5b9c7d
SA		 8018 u8 retransmission_active[0x8];
8019 u8 fec_mode_active[0x18];
e281682b 8020
4b5b9c7d
SA		 8021 u8 rs_fec_correction_bypass_cap[0x4];
8022 u8 reserved_at_84[0x8];
8023 u8 fec_override_cap_56g[0x4];
8024 u8 fec_override_cap_100g[0x4];
8025 u8 fec_override_cap_50g[0x4];
8026 u8 fec_override_cap_25g[0x4];
8027 u8 fec_override_cap_10g_40g[0x4];
8028
8029 u8 rs_fec_correction_bypass_admin[0x4];
8030 u8 reserved_at_a4[0x8];
8031 u8 fec_override_admin_56g[0x4];
8032 u8 fec_override_admin_100g[0x4];
8033 u8 fec_override_admin_50g[0x4];
8034 u8 fec_override_admin_25g[0x4];
8035 u8 fec_override_admin_10g_40g[0x4];
e281682b
SM		 8036};
8037
8038struct mlx5_ifc_ppcnt_reg_bits {
8039 u8 swid[0x8];
8040 u8 local_port[0x8];
8041 u8 pnat[0x2];
b4ff3a36 8042 u8 reserved_at_12[0x8];
e281682b
SM		 8043 u8 grp[0x6];
8044
8045 u8 clr[0x1];
b4ff3a36 8046 u8 reserved_at_21[0x1c];
e281682b
SM		 8047 u8 prio_tc[0x3];
8048
8049 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8050};
8051
4039049b
AL		 8052struct mlx5_ifc_mpein_reg_bits {
8053 u8 reserved_at_0[0x2];
8054 u8 depth[0x6];
8055 u8 pcie_index[0x8];
8056 u8 node[0x8];
8057 u8 reserved_at_18[0x8];
8058
8059 u8 capability_mask[0x20];
8060
8061 u8 reserved_at_40[0x8];
8062 u8 link_width_enabled[0x8];
8063 u8 link_speed_enabled[0x10];
8064
8065 u8 lane0_physical_position[0x8];
8066 u8 link_width_active[0x8];
8067 u8 link_speed_active[0x10];
8068
8069 u8 num_of_pfs[0x10];
8070 u8 num_of_vfs[0x10];
8071
8072 u8 bdf0[0x10];
8073 u8 reserved_at_b0[0x10];
8074
8075 u8 max_read_request_size[0x4];
8076 u8 max_payload_size[0x4];
8077 u8 reserved_at_c8[0x5];
8078 u8 pwr_status[0x3];
8079 u8 port_type[0x4];
8080 u8 reserved_at_d4[0xb];
8081 u8 lane_reversal[0x1];
8082
8083 u8 reserved_at_e0[0x14];
8084 u8 pci_power[0xc];
8085
8086 u8 reserved_at_100[0x20];
8087
8088 u8 device_status[0x10];
8089 u8 port_state[0x8];
8090 u8 reserved_at_138[0x8];
8091
8092 u8 reserved_at_140[0x10];
8093 u8 receiver_detect_result[0x10];
8094
8095 u8 reserved_at_160[0x20];
8096};
8097
8ed1a630
GP		 8098struct mlx5_ifc_mpcnt_reg_bits {
8099 u8 reserved_at_0[0x8];
8100 u8 pcie_index[0x8];
8101 u8 reserved_at_10[0xa];
8102 u8 grp[0x6];
8103
8104 u8 clr[0x1];
8105 u8 reserved_at_21[0x1f];
8106
8107 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8108};
8109
e281682b 8110struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 8111 u8 reserved_at_0[0x3];
e281682b 8112 u8 single_mac[0x1];
b4ff3a36 8113 u8 reserved_at_4[0x4];
e281682b
SM		 8114 u8 local_port[0x8];
8115 u8 mac_47_32[0x10];
8116
8117 u8 mac_31_0[0x20];
8118
b4ff3a36 8119 u8 reserved_at_40[0x40];
e281682b
SM		 8120};
8121
8122struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 8123 u8 reserved_at_0[0x8];
e281682b 8124 u8 local_port[0x8];
b4ff3a36 8125 u8 reserved_at_10[0x10];
e281682b
SM		 8126
8127 u8 max_mtu[0x10];
b4ff3a36 8128 u8 reserved_at_30[0x10];
e281682b
SM		 8129
8130 u8 admin_mtu[0x10];
b4ff3a36 8131 u8 reserved_at_50[0x10];
e281682b
SM		 8132
8133 u8 oper_mtu[0x10];
b4ff3a36 8134 u8 reserved_at_70[0x10];
e281682b
SM		 8135};
8136
8137struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 8138 u8 reserved_at_0[0x8];
e281682b 8139 u8 module[0x8];
b4ff3a36 8140 u8 reserved_at_10[0x10];
e281682b 8141
b4ff3a36 8142 u8 reserved_at_20[0x18];
e281682b
SM		 8143 u8 attenuation_5g[0x8];
8144
b4ff3a36 8145 u8 reserved_at_40[0x18];
e281682b
SM		 8146 u8 attenuation_7g[0x8];
8147
b4ff3a36 8148 u8 reserved_at_60[0x18];
e281682b
SM		 8149 u8 attenuation_12g[0x8];
8150};
8151
8152struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 8153 u8 reserved_at_0[0x8];
e281682b 8154 u8 module[0x8];
b4ff3a36 8155 u8 reserved_at_10[0xc];
e281682b
SM		 8156 u8 module_status[0x4];
8157
b4ff3a36 8158 u8 reserved_at_20[0x60];
e281682b
SM		 8159};
8160
8161struct mlx5_ifc_pmpc_reg_bits {
8162 u8 module_state_updated[32][0x8];
8163};
8164
8165struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 8166 u8 reserved_at_0[0x4];
e281682b
SM		 8167 u8 mlpn_status[0x4];
8168 u8 local_port[0x8];
b4ff3a36 8169 u8 reserved_at_10[0x10];
e281682b
SM		 8170
8171 u8 e[0x1];
b4ff3a36 8172 u8 reserved_at_21[0x1f];
e281682b
SM		 8173};
8174
8175struct mlx5_ifc_pmlp_reg_bits {
8176 u8 rxtx[0x1];
b4ff3a36 8177 u8 reserved_at_1[0x7];
e281682b 8178 u8 local_port[0x8];
b4ff3a36 8179 u8 reserved_at_10[0x8];
e281682b
SM		 8180 u8 width[0x8];
8181
8182 u8 lane0_module_mapping[0x20];
8183
8184 u8 lane1_module_mapping[0x20];
8185
8186 u8 lane2_module_mapping[0x20];
8187
8188 u8 lane3_module_mapping[0x20];
8189
b4ff3a36 8190 u8 reserved_at_a0[0x160];
e281682b
SM		 8191};
8192
8193struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 8194 u8 reserved_at_0[0x8];
e281682b 8195 u8 module[0x8];
b4ff3a36 8196 u8 reserved_at_10[0x4];
e281682b 8197 u8 admin_status[0x4];
b4ff3a36 8198 u8 reserved_at_18[0x4];
e281682b
SM		 8199 u8 oper_status[0x4];
8200
8201 u8 ase[0x1];
8202 u8 ee[0x1];
b4ff3a36 8203 u8 reserved_at_22[0x1c];
e281682b
SM		 8204 u8 e[0x2];
8205
b4ff3a36 8206 u8 reserved_at_40[0x40];
e281682b
SM		 8207};
8208
8209struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 8210 u8 reserved_at_0[0x4];
e281682b 8211 u8 profile_id[0xc];
b4ff3a36 8212 u8 reserved_at_10[0x4];
e281682b 8213 u8 proto_mask[0x4];
b4ff3a36 8214 u8 reserved_at_18[0x8];
e281682b 8215
b4ff3a36 8216 u8 reserved_at_20[0x10];
e281682b
SM		 8217 u8 lane_speed[0x10];
8218
b4ff3a36 8219 u8 reserved_at_40[0x17];
e281682b
SM		 8220 u8 lpbf[0x1];
8221 u8 fec_mode_policy[0x8];
8222
8223 u8 retransmission_capability[0x8];
8224 u8 fec_mode_capability[0x18];
8225
8226 u8 retransmission_support_admin[0x8];
8227 u8 fec_mode_support_admin[0x18];
8228
8229 u8 retransmission_request_admin[0x8];
8230 u8 fec_mode_request_admin[0x18];
8231
b4ff3a36 8232 u8 reserved_at_c0[0x80];
e281682b
SM		 8233};
8234
8235struct mlx5_ifc_plib_reg_bits {
b4ff3a36 8236 u8 reserved_at_0[0x8];
e281682b 8237 u8 local_port[0x8];
b4ff3a36 8238 u8 reserved_at_10[0x8];
e281682b
SM		 8239 u8 ib_port[0x8];
8240
b4ff3a36 8241 u8 reserved_at_20[0x60];
e281682b
SM		 8242};
8243
8244struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 8245 u8 reserved_at_0[0x8];
e281682b 8246 u8 local_port[0x8];
b4ff3a36 8247 u8 reserved_at_10[0xd];
e281682b
SM		 8248 u8 lbf_mode[0x3];
8249
b4ff3a36 8250 u8 reserved_at_20[0x20];
e281682b
SM		 8251};
8252
8253struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 8254 u8 reserved_at_0[0x8];
e281682b 8255 u8 local_port[0x8];
b4ff3a36 8256 u8 reserved_at_10[0x10];
e281682b
SM		 8257
8258 u8 dic[0x1];
b4ff3a36 8259 u8 reserved_at_21[0x19];
e281682b 8260 u8 ipg[0x4];
b4ff3a36 8261 u8 reserved_at_3e[0x2];
e281682b
SM		 8262};
8263
8264struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 8265 u8 reserved_at_0[0x8];
e281682b 8266 u8 local_port[0x8];
b4ff3a36 8267 u8 reserved_at_10[0x10];
e281682b 8268
b4ff3a36 8269 u8 reserved_at_20[0xe0];
e281682b
SM		 8270
8271 u8 port_filter[8][0x20];
8272
8273 u8 port_filter_update_en[8][0x20];
8274};
8275
8276struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 8277 u8 reserved_at_0[0x8];
e281682b 8278 u8 local_port[0x8];
2afa609f
IK		 8279 u8 reserved_at_10[0xb];
8280 u8 ppan_mask_n[0x1];
8281 u8 minor_stall_mask[0x1];
8282 u8 critical_stall_mask[0x1];
8283 u8 reserved_at_1e[0x2];
e281682b
SM		 8284
8285 u8 ppan[0x4];
b4ff3a36 8286 u8 reserved_at_24[0x4];
e281682b 8287 u8 prio_mask_tx[0x8];
b4ff3a36 8288 u8 reserved_at_30[0x8];
e281682b
SM		 8289 u8 prio_mask_rx[0x8];
8290
8291 u8 pptx[0x1];
8292 u8 aptx[0x1];
2afa609f
IK		 8293 u8 pptx_mask_n[0x1];
8294 u8 reserved_at_43[0x5];
e281682b 8295 u8 pfctx[0x8];
b4ff3a36 8296 u8 reserved_at_50[0x10];
e281682b
SM		 8297
8298 u8 pprx[0x1];
8299 u8 aprx[0x1];
2afa609f
IK		 8300 u8 pprx_mask_n[0x1];
8301 u8 reserved_at_63[0x5];
e281682b 8302 u8 pfcrx[0x8];
b4ff3a36 8303 u8 reserved_at_70[0x10];
e281682b 8304
2afa609f
IK		 8305 u8 device_stall_minor_watermark[0x10];
8306 u8 device_stall_critical_watermark[0x10];
8307
8308 u8 reserved_at_a0[0x60];
e281682b
SM		 8309};
8310
8311struct mlx5_ifc_pelc_reg_bits {
8312 u8 op[0x4];
b4ff3a36 8313 u8 reserved_at_4[0x4];
e281682b 8314 u8 local_port[0x8];
b4ff3a36 8315 u8 reserved_at_10[0x10];
e281682b
SM		 8316
8317 u8 op_admin[0x8];
8318 u8 op_capability[0x8];
8319 u8 op_request[0x8];
8320 u8 op_active[0x8];
8321
8322 u8 admin[0x40];
8323
8324 u8 capability[0x40];
8325
8326 u8 request[0x40];
8327
8328 u8 active[0x40];
8329
b4ff3a36 8330 u8 reserved_at_140[0x80];
e281682b
SM		 8331};
8332
8333struct mlx5_ifc_peir_reg_bits {
b4ff3a36 8334 u8 reserved_at_0[0x8];
e281682b 8335 u8 local_port[0x8];
b4ff3a36 8336 u8 reserved_at_10[0x10];
e281682b 8337
b4ff3a36 8338 u8 reserved_at_20[0xc];
e281682b 8339 u8 error_count[0x4];
b4ff3a36 8340 u8 reserved_at_30[0x10];
e281682b 8341
b4ff3a36 8342 u8 reserved_at_40[0xc];
e281682b 8343 u8 lane[0x4];
b4ff3a36 8344 u8 reserved_at_50[0x8];
e281682b
SM		 8345 u8 error_type[0x8];
8346};
8347
5e022dd3
EBE		 8348struct mlx5_ifc_mpegc_reg_bits {
8349 u8 reserved_at_0[0x30];
8350 u8 field_select[0x10];
8351
8352 u8 tx_overflow_sense[0x1];
8353 u8 mark_cqe[0x1];
8354 u8 mark_cnp[0x1];
8355 u8 reserved_at_43[0x1b];
8356 u8 tx_lossy_overflow_oper[0x2];
8357
8358 u8 reserved_at_60[0x100];
8359};
8360
cfdcbcea 8361struct mlx5_ifc_pcam_enhanced_features_bits {
0af5107c
TB		 8362 u8 reserved_at_0[0x6d];
8363 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 8364 u8 reserved_at_6e[0x4];
8365 u8 ptys_extended_ethernet[0x1];
8366 u8 reserved_at_73[0x3];
2fcb12df 8367 u8 pfcc_mask[0x1];
67daf118
SA		 8368 u8 reserved_at_77[0x3];
8369 u8 per_lane_error_counters[0x1];
2dba0797 8370 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8371 u8 ptys_connector_type[0x1];
8372 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8373 u8 ppcnt_discard_group[0x1];
8374 u8 ppcnt_statistical_group[0x1];
8375};
8376
df5f1361
HN		 8377struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8378 u8 port_access_reg_cap_mask_127_to_96[0x20];
8379 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 8380
8381 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8382 u8 pplm[0x1];
8383 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 8384
8385 u8 port_access_reg_cap_mask_31_to_13[0x13];
8386 u8 pbmc[0x1];
8387 u8 pptb[0x1];
75370eb0
ED		 8388 u8 port_access_reg_cap_mask_10_to_09[0x2];
8389 u8 ppcnt[0x1];
8390 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 8391};
8392
cfdcbcea
GP		 8393struct mlx5_ifc_pcam_reg_bits {
8394 u8 reserved_at_0[0x8];
8395 u8 feature_group[0x8];
8396 u8 reserved_at_10[0x8];
8397 u8 access_reg_group[0x8];
8398
8399 u8 reserved_at_20[0x20];
8400
8401 union {
df5f1361 8402 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 8403 u8 reserved_at_0[0x80];
8404 } port_access_reg_cap_mask;
8405
8406 u8 reserved_at_c0[0x80];
8407
8408 union {
8409 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8410 u8 reserved_at_0[0x80];
8411 } feature_cap_mask;
8412
8413 u8 reserved_at_1c0[0xc0];
8414};
8415
8416struct mlx5_ifc_mcam_enhanced_features_bits {
4039049b
AL		 8417 u8 reserved_at_0[0x6e];
8418 u8 pci_status_and_power[0x1];
8419 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 8420 u8 mark_tx_action_cnp[0x1];
8421 u8 mark_tx_action_cqe[0x1];
8422 u8 dynamic_tx_overflow[0x1];
8423 u8 reserved_at_77[0x4];
5405fa26 8424 u8 pcie_outbound_stalled[0x1];
efae7f78 8425 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8426 u8 mtpps_enh_out_per_adj[0x1];
8427 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8428 u8 pcie_performance_group[0x1];
8429};
8430
0ab87743
OG		 8431struct mlx5_ifc_mcam_access_reg_bits {
8432 u8 reserved_at_0[0x1c];
8433 u8 mcda[0x1];
8434 u8 mcc[0x1];
8435 u8 mcqi[0x1];
8436 u8 reserved_at_1f[0x1];
8437
5e022dd3
EBE		 8438 u8 regs_95_to_87[0x9];
8439 u8 mpegc[0x1];
8440 u8 regs_85_to_68[0x12];
eff8ea8f
FD		 8441 u8 tracer_registers[0x4];
8442
0ab87743
OG		 8443 u8 regs_63_to_32[0x20];
8444 u8 regs_31_to_0[0x20];
8445};
8446
cfdcbcea
GP		 8447struct mlx5_ifc_mcam_reg_bits {
8448 u8 reserved_at_0[0x8];
8449 u8 feature_group[0x8];
8450 u8 reserved_at_10[0x8];
8451 u8 access_reg_group[0x8];
8452
8453 u8 reserved_at_20[0x20];
8454
8455 union {
0ab87743 8456 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8457 u8 reserved_at_0[0x80];
8458 } mng_access_reg_cap_mask;
8459
8460 u8 reserved_at_c0[0x80];
8461
8462 union {
8463 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8464 u8 reserved_at_0[0x80];
8465 } mng_feature_cap_mask;
8466
8467 u8 reserved_at_1c0[0x80];
8468};
8469
c02762eb
HN		 8470struct mlx5_ifc_qcam_access_reg_cap_mask {
8471 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8472 u8 qpdpm[0x1];
8473 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8474 u8 qdpm[0x1];
8475 u8 qpts[0x1];
8476 u8 qcap[0x1];
8477 u8 qcam_access_reg_cap_mask_0[0x1];
8478};
8479
8480struct mlx5_ifc_qcam_qos_feature_cap_mask {
8481 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8482 u8 qpts_trust_both[0x1];
8483};
8484
8485struct mlx5_ifc_qcam_reg_bits {
8486 u8 reserved_at_0[0x8];
8487 u8 feature_group[0x8];
8488 u8 reserved_at_10[0x8];
8489 u8 access_reg_group[0x8];
8490 u8 reserved_at_20[0x20];
8491
8492 union {
8493 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8494 u8 reserved_at_0[0x80];
8495 } qos_access_reg_cap_mask;
8496
8497 u8 reserved_at_c0[0x80];
8498
8499 union {
8500 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8501 u8 reserved_at_0[0x80];
8502 } qos_feature_cap_mask;
8503
8504 u8 reserved_at_1c0[0x80];
8505};
8506
e281682b 8507struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8508 u8 reserved_at_0[0x8];
e281682b 8509 u8 local_port[0x8];
b4ff3a36 8510 u8 reserved_at_10[0x10];
e281682b
SM		 8511
8512 u8 port_capability_mask[4][0x20];
8513};
8514
8515struct mlx5_ifc_paos_reg_bits {
8516 u8 swid[0x8];
8517 u8 local_port[0x8];
b4ff3a36 8518 u8 reserved_at_10[0x4];
e281682b 8519 u8 admin_status[0x4];
b4ff3a36 8520 u8 reserved_at_18[0x4];
e281682b
SM		 8521 u8 oper_status[0x4];
8522
8523 u8 ase[0x1];
8524 u8 ee[0x1];
b4ff3a36 8525 u8 reserved_at_22[0x1c];
e281682b
SM		 8526 u8 e[0x2];
8527
b4ff3a36 8528 u8 reserved_at_40[0x40];
e281682b
SM		 8529};
8530
8531struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8532 u8 reserved_at_0[0x8];
e281682b 8533 u8 opamp_group[0x8];
b4ff3a36 8534 u8 reserved_at_10[0xc];
e281682b
SM		 8535 u8 opamp_group_type[0x4];
8536
8537 u8 start_index[0x10];
b4ff3a36 8538 u8 reserved_at_30[0x4];
e281682b
SM		 8539 u8 num_of_indices[0xc];
8540
8541 u8 index_data[18][0x10];
8542};
8543
7d5e1423
SM		 8544struct mlx5_ifc_pcmr_reg_bits {
8545 u8 reserved_at_0[0x8];
8546 u8 local_port[0x8];
0dcaafc0
EB		 8547 u8 reserved_at_10[0x10];
8548 u8 entropy_force_cap[0x1];
8549 u8 entropy_calc_cap[0x1];
8550 u8 entropy_gre_calc_cap[0x1];
8551 u8 reserved_at_23[0x1b];
7d5e1423 8552 u8 fcs_cap[0x1];
0dcaafc0
EB		 8553 u8 reserved_at_3f[0x1];
8554 u8 entropy_force[0x1];
8555 u8 entropy_calc[0x1];
8556 u8 entropy_gre_calc[0x1];
8557 u8 reserved_at_43[0x1b];
7d5e1423
SM		 8558 u8 fcs_chk[0x1];
8559 u8 reserved_at_5f[0x1];
8560};
8561
e281682b 8562struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8563 u8 reserved_at_0[0x6];
e281682b 8564 u8 rx_lane[0x2];
b4ff3a36 8565 u8 reserved_at_8[0x6];
e281682b 8566 u8 tx_lane[0x2];
b4ff3a36 8567 u8 reserved_at_10[0x8];
e281682b
SM		 8568 u8 module[0x8];
8569};
8570
8571struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8572 u8 reserved_at_0[0x6];
e281682b
SM		 8573 u8 lossy[0x1];
8574 u8 epsb[0x1];
b4ff3a36 8575 u8 reserved_at_8[0xc];
e281682b
SM		 8576 u8 size[0xc];
8577
8578 u8 xoff_threshold[0x10];
8579 u8 xon_threshold[0x10];
8580};
8581
8582struct mlx5_ifc_set_node_in_bits {
8583 u8 node_description[64][0x8];
8584};
8585
8586struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8587 u8 reserved_at_0[0x18];
e281682b
SM		 8588 u8 power_settings_level[0x8];
8589
b4ff3a36 8590 u8 reserved_at_20[0x60];
e281682b
SM		 8591};
8592
8593struct mlx5_ifc_register_host_endianness_bits {
8594 u8 he[0x1];
b4ff3a36 8595 u8 reserved_at_1[0x1f];
e281682b 8596
b4ff3a36 8597 u8 reserved_at_20[0x60];
e281682b
SM		 8598};
8599
8600struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8601 u8 reserved_at_0[0x20];
e281682b
SM		 8602
8603 u8 mkey[0x20];
8604
8605 u8 addressh_63_32[0x20];
8606
8607 u8 addressl_31_0[0x20];
8608};
8609
8610struct mlx5_ifc_ud_adrs_vector_bits {
8611 u8 dc_key[0x40];
8612
8613 u8 ext[0x1];
b4ff3a36 8614 u8 reserved_at_41[0x7];
e281682b
SM		 8615 u8 destination_qp_dct[0x18];
8616
8617 u8 static_rate[0x4];
8618 u8 sl_eth_prio[0x4];
8619 u8 fl[0x1];
8620 u8 mlid[0x7];
8621 u8 rlid_udp_sport[0x10];
8622
b4ff3a36 8623 u8 reserved_at_80[0x20];
e281682b
SM		 8624
8625 u8 rmac_47_16[0x20];
8626
8627 u8 rmac_15_0[0x10];
8628 u8 tclass[0x8];
8629 u8 hop_limit[0x8];
8630
b4ff3a36 8631 u8 reserved_at_e0[0x1];
e281682b 8632 u8 grh[0x1];
b4ff3a36 8633 u8 reserved_at_e2[0x2];
e281682b
SM		 8634 u8 src_addr_index[0x8];
8635 u8 flow_label[0x14];
8636
8637 u8 rgid_rip[16][0x8];
8638};
8639
8640struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8641 u8 reserved_at_0[0x10];
e281682b
SM		 8642 u8 function_id[0x10];
8643
8644 u8 num_pages[0x20];
8645
b4ff3a36 8646 u8 reserved_at_40[0xa0];
e281682b
SM		 8647};
8648
8649struct mlx5_ifc_eqe_bits {
b4ff3a36 8650 u8 reserved_at_0[0x8];
e281682b 8651 u8 event_type[0x8];
b4ff3a36 8652 u8 reserved_at_10[0x8];
e281682b
SM		 8653 u8 event_sub_type[0x8];
8654
b4ff3a36 8655 u8 reserved_at_20[0xe0];
e281682b
SM		 8656
8657 union mlx5_ifc_event_auto_bits event_data;
8658
b4ff3a36 8659 u8 reserved_at_1e0[0x10];
e281682b 8660 u8 signature[0x8];
b4ff3a36 8661 u8 reserved_at_1f8[0x7];
e281682b
SM		 8662 u8 owner[0x1];
8663};
8664
8665enum {
8666 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8667};
8668
8669struct mlx5_ifc_cmd_queue_entry_bits {
8670 u8 type[0x8];
b4ff3a36 8671 u8 reserved_at_8[0x18];
e281682b
SM		 8672
8673 u8 input_length[0x20];
8674
8675 u8 input_mailbox_pointer_63_32[0x20];
8676
8677 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8678 u8 reserved_at_77[0x9];
e281682b
SM		 8679
8680 u8 command_input_inline_data[16][0x8];
8681
8682 u8 command_output_inline_data[16][0x8];
8683
8684 u8 output_mailbox_pointer_63_32[0x20];
8685
8686 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8687 u8 reserved_at_1b7[0x9];
e281682b
SM		 8688
8689 u8 output_length[0x20];
8690
8691 u8 token[0x8];
8692 u8 signature[0x8];
b4ff3a36 8693 u8 reserved_at_1f0[0x8];
e281682b
SM		 8694 u8 status[0x7];
8695 u8 ownership[0x1];
8696};
8697
8698struct mlx5_ifc_cmd_out_bits {
8699 u8 status[0x8];
b4ff3a36 8700 u8 reserved_at_8[0x18];
e281682b
SM		 8701
8702 u8 syndrome[0x20];
8703
8704 u8 command_output[0x20];
8705};
8706
8707struct mlx5_ifc_cmd_in_bits {
8708 u8 opcode[0x10];
b4ff3a36 8709 u8 reserved_at_10[0x10];
e281682b 8710
b4ff3a36 8711 u8 reserved_at_20[0x10];
e281682b
SM		 8712 u8 op_mod[0x10];
8713
8714 u8 command[0][0x20];
8715};
8716
8717struct mlx5_ifc_cmd_if_box_bits {
8718 u8 mailbox_data[512][0x8];
8719
b4ff3a36 8720 u8 reserved_at_1000[0x180];
e281682b
SM		 8721
8722 u8 next_pointer_63_32[0x20];
8723
8724 u8 next_pointer_31_10[0x16];
b4ff3a36 8725 u8 reserved_at_11b6[0xa];
e281682b
SM		 8726
8727 u8 block_number[0x20];
8728
b4ff3a36 8729 u8 reserved_at_11e0[0x8];
e281682b
SM		 8730 u8 token[0x8];
8731 u8 ctrl_signature[0x8];
8732 u8 signature[0x8];
8733};
8734
8735struct mlx5_ifc_mtt_bits {
8736 u8 ptag_63_32[0x20];
8737
8738 u8 ptag_31_8[0x18];
b4ff3a36 8739 u8 reserved_at_38[0x6];
e281682b
SM		 8740 u8 wr_en[0x1];
8741 u8 rd_en[0x1];
8742};
8743
928cfe87
TT		 8744struct mlx5_ifc_query_wol_rol_out_bits {
8745 u8 status[0x8];
8746 u8 reserved_at_8[0x18];
8747
8748 u8 syndrome[0x20];
8749
8750 u8 reserved_at_40[0x10];
8751 u8 rol_mode[0x8];
8752 u8 wol_mode[0x8];
8753
8754 u8 reserved_at_60[0x20];
8755};
8756
8757struct mlx5_ifc_query_wol_rol_in_bits {
8758 u8 opcode[0x10];
8759 u8 reserved_at_10[0x10];
8760
8761 u8 reserved_at_20[0x10];
8762 u8 op_mod[0x10];
8763
8764 u8 reserved_at_40[0x40];
8765};
8766
8767struct mlx5_ifc_set_wol_rol_out_bits {
8768 u8 status[0x8];
8769 u8 reserved_at_8[0x18];
8770
8771 u8 syndrome[0x20];
8772
8773 u8 reserved_at_40[0x40];
8774};
8775
8776struct mlx5_ifc_set_wol_rol_in_bits {
8777 u8 opcode[0x10];
8778 u8 reserved_at_10[0x10];
8779
8780 u8 reserved_at_20[0x10];
8781 u8 op_mod[0x10];
8782
8783 u8 rol_mode_valid[0x1];
8784 u8 wol_mode_valid[0x1];
8785 u8 reserved_at_42[0xe];
8786 u8 rol_mode[0x8];
8787 u8 wol_mode[0x8];
8788
8789 u8 reserved_at_60[0x20];
8790};
8791
e281682b
SM		 8792enum {
8793 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8794 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8795 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8796};
8797
8798enum {
8799 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8800 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8801 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8802};
8803
8804enum {
8805 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8806 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8807 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8808 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8809 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8810 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8811 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8812 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8813 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8814 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8815 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8816};
8817
8818struct mlx5_ifc_initial_seg_bits {
8819 u8 fw_rev_minor[0x10];
8820 u8 fw_rev_major[0x10];
8821
8822 u8 cmd_interface_rev[0x10];
8823 u8 fw_rev_subminor[0x10];
8824
b4ff3a36 8825 u8 reserved_at_40[0x40];
e281682b
SM		 8826
8827 u8 cmdq_phy_addr_63_32[0x20];
8828
8829 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8830 u8 reserved_at_b4[0x2];
e281682b
SM		 8831 u8 nic_interface[0x2];
8832 u8 log_cmdq_size[0x4];
8833 u8 log_cmdq_stride[0x4];
8834
8835 u8 command_doorbell_vector[0x20];
8836
b4ff3a36 8837 u8 reserved_at_e0[0xf00];
e281682b
SM		 8838
8839 u8 initializing[0x1];
b4ff3a36 8840 u8 reserved_at_fe1[0x4];
e281682b 8841 u8 nic_interface_supported[0x3];
591905ba
BW		 8842 u8 embedded_cpu[0x1];
8843 u8 reserved_at_fe9[0x17];
e281682b
SM		 8844
8845 struct mlx5_ifc_health_buffer_bits health_buffer;
8846
8847 u8 no_dram_nic_offset[0x20];
8848
b4ff3a36 8849 u8 reserved_at_1220[0x6e40];
e281682b 8850
b4ff3a36 8851 u8 reserved_at_8060[0x1f];
e281682b
SM		 8852 u8 clear_int[0x1];
8853
8854 u8 health_syndrome[0x8];
8855 u8 health_counter[0x18];
8856
b4ff3a36 8857 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8858};
8859
f9a1ef72
EE		 8860struct mlx5_ifc_mtpps_reg_bits {
8861 u8 reserved_at_0[0xc];
8862 u8 cap_number_of_pps_pins[0x4];
8863 u8 reserved_at_10[0x4];
8864 u8 cap_max_num_of_pps_in_pins[0x4];
8865 u8 reserved_at_18[0x4];
8866 u8 cap_max_num_of_pps_out_pins[0x4];
8867
8868 u8 reserved_at_20[0x24];
8869 u8 cap_pin_3_mode[0x4];
8870 u8 reserved_at_48[0x4];
8871 u8 cap_pin_2_mode[0x4];
8872 u8 reserved_at_50[0x4];
8873 u8 cap_pin_1_mode[0x4];
8874 u8 reserved_at_58[0x4];
8875 u8 cap_pin_0_mode[0x4];
8876
8877 u8 reserved_at_60[0x4];
8878 u8 cap_pin_7_mode[0x4];
8879 u8 reserved_at_68[0x4];
8880 u8 cap_pin_6_mode[0x4];
8881 u8 reserved_at_70[0x4];
8882 u8 cap_pin_5_mode[0x4];
8883 u8 reserved_at_78[0x4];
8884 u8 cap_pin_4_mode[0x4];
8885
fa367688
EE		 8886 u8 field_select[0x20];
8887 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8888
8889 u8 enable[0x1];
8890 u8 reserved_at_101[0xb];
8891 u8 pattern[0x4];
8892 u8 reserved_at_110[0x4];
8893 u8 pin_mode[0x4];
8894 u8 pin[0x8];
8895
8896 u8 reserved_at_120[0x20];
8897
8898 u8 time_stamp[0x40];
8899
8900 u8 out_pulse_duration[0x10];
8901 u8 out_periodic_adjustment[0x10];
fa367688 8902 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8903
fa367688 8904 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8905};
8906
8907struct mlx5_ifc_mtppse_reg_bits {
8908 u8 reserved_at_0[0x18];
8909 u8 pin[0x8];
8910 u8 event_arm[0x1];
8911 u8 reserved_at_21[0x1b];
8912 u8 event_generation_mode[0x4];
8913 u8 reserved_at_40[0x40];
8914};
8915
47176289
OG		 8916struct mlx5_ifc_mcqi_cap_bits {
8917 u8 supported_info_bitmask[0x20];
8918
8919 u8 component_size[0x20];
8920
8921 u8 max_component_size[0x20];
8922
8923 u8 log_mcda_word_size[0x4];
8924 u8 reserved_at_64[0xc];
8925 u8 mcda_max_write_size[0x10];
8926
8927 u8 rd_en[0x1];
8928 u8 reserved_at_81[0x1];
8929 u8 match_chip_id[0x1];
8930 u8 match_psid[0x1];
8931 u8 check_user_timestamp[0x1];
8932 u8 match_base_guid_mac[0x1];
8933 u8 reserved_at_86[0x1a];
8934};
8935
8936struct mlx5_ifc_mcqi_reg_bits {
8937 u8 read_pending_component[0x1];
8938 u8 reserved_at_1[0xf];
8939 u8 component_index[0x10];
8940
8941 u8 reserved_at_20[0x20];
8942
8943 u8 reserved_at_40[0x1b];
8944 u8 info_type[0x5];
8945
8946 u8 info_size[0x20];
8947
8948 u8 offset[0x20];
8949
8950 u8 reserved_at_a0[0x10];
8951 u8 data_size[0x10];
8952
8953 u8 data[0][0x20];
8954};
8955
8956struct mlx5_ifc_mcc_reg_bits {
8957 u8 reserved_at_0[0x4];
8958 u8 time_elapsed_since_last_cmd[0xc];
8959 u8 reserved_at_10[0x8];
8960 u8 instruction[0x8];
8961
8962 u8 reserved_at_20[0x10];
8963 u8 component_index[0x10];
8964
8965 u8 reserved_at_40[0x8];
8966 u8 update_handle[0x18];
8967
8968 u8 handle_owner_type[0x4];
8969 u8 handle_owner_host_id[0x4];
8970 u8 reserved_at_68[0x1];
8971 u8 control_progress[0x7];
8972 u8 error_code[0x8];
8973 u8 reserved_at_78[0x4];
8974 u8 control_state[0x4];
8975
8976 u8 component_size[0x20];
8977
8978 u8 reserved_at_a0[0x60];
8979};
8980
8981struct mlx5_ifc_mcda_reg_bits {
8982 u8 reserved_at_0[0x8];
8983 u8 update_handle[0x18];
8984
8985 u8 offset[0x20];
8986
8987 u8 reserved_at_40[0x10];
8988 u8 size[0x10];
8989
8990 u8 reserved_at_60[0x20];
8991
8992 u8 data[0][0x20];
8993};
8994
e281682b
SM		 8995union mlx5_ifc_ports_control_registers_document_bits {
8996 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8997 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8998 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8999 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9000 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9001 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9002 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9003 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9004 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9005 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9006 struct mlx5_ifc_paos_reg_bits paos_reg;
9007 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9008 struct mlx5_ifc_peir_reg_bits peir_reg;
9009 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9010 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 9011 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 9012 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9013 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9014 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9015 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9016 struct mlx5_ifc_plib_reg_bits plib_reg;
9017 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9018 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9019 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9020 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9021 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9022 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9023 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9024 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9025 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9026 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 9027 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 9028 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 9029 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9030 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9031 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9032 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9033 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9034 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9035 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 9036 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 9037 struct mlx5_ifc_pude_reg_bits pude_reg;
9038 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9039 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9040 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 9041 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9042 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 9043 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 9044 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9045 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 9046 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9047 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9048 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 9049 u8 reserved_at_0[0x60e0];
e281682b
SM		 9050};
9051
9052union mlx5_ifc_debug_enhancements_document_bits {
9053 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 9054 u8 reserved_at_0[0x200];
e281682b
SM		 9055};
9056
9057union mlx5_ifc_uplink_pci_interface_document_bits {
9058 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 9059 u8 reserved_at_0[0x20060];
b775516b
EC		 9060};
9061
2cc43b49
MG		 9062struct mlx5_ifc_set_flow_table_root_out_bits {
9063 u8 status[0x8];
b4ff3a36 9064 u8 reserved_at_8[0x18];
2cc43b49
MG		 9065
9066 u8 syndrome[0x20];
9067
b4ff3a36 9068 u8 reserved_at_40[0x40];
2cc43b49
MG		 9069};
9070
9071struct mlx5_ifc_set_flow_table_root_in_bits {
9072 u8 opcode[0x10];
b4ff3a36 9073 u8 reserved_at_10[0x10];
2cc43b49 9074
b4ff3a36 9075 u8 reserved_at_20[0x10];
2cc43b49
MG		 9076 u8 op_mod[0x10];
9077
7d5e1423
SM		 9078 u8 other_vport[0x1];
9079 u8 reserved_at_41[0xf];
9080 u8 vport_number[0x10];
9081
9082 u8 reserved_at_60[0x20];
2cc43b49
MG		 9083
9084 u8 table_type[0x8];
b4ff3a36 9085 u8 reserved_at_88[0x18];
2cc43b49 9086
b4ff3a36 9087 u8 reserved_at_a0[0x8];
2cc43b49
MG		 9088 u8 table_id[0x18];
9089
500a3d0d
ES		 9090 u8 reserved_at_c0[0x8];
9091 u8 underlay_qpn[0x18];
9092 u8 reserved_at_e0[0x120];
2cc43b49
MG		 9093};
9094
34a40e68 9095enum {
84df61eb
AH		 9096 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9097 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 9098};
9099
9100struct mlx5_ifc_modify_flow_table_out_bits {
9101 u8 status[0x8];
b4ff3a36 9102 u8 reserved_at_8[0x18];
34a40e68
MG		 9103
9104 u8 syndrome[0x20];
9105
b4ff3a36 9106 u8 reserved_at_40[0x40];
34a40e68
MG		 9107};
9108
9109struct mlx5_ifc_modify_flow_table_in_bits {
9110 u8 opcode[0x10];
b4ff3a36 9111 u8 reserved_at_10[0x10];
34a40e68 9112
b4ff3a36 9113 u8 reserved_at_20[0x10];
34a40e68
MG		 9114 u8 op_mod[0x10];
9115
7d5e1423
SM		 9116 u8 other_vport[0x1];
9117 u8 reserved_at_41[0xf];
9118 u8 vport_number[0x10];
34a40e68 9119
b4ff3a36 9120 u8 reserved_at_60[0x10];
34a40e68
MG		 9121 u8 modify_field_select[0x10];
9122
9123 u8 table_type[0x8];
b4ff3a36 9124 u8 reserved_at_88[0x18];
34a40e68 9125
b4ff3a36 9126 u8 reserved_at_a0[0x8];
34a40e68
MG		 9127 u8 table_id[0x18];
9128
0c90e9c6 9129 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 9130};
9131
4f3961ee
SM		 9132struct mlx5_ifc_ets_tcn_config_reg_bits {
9133 u8 g[0x1];
9134 u8 b[0x1];
9135 u8 r[0x1];
9136 u8 reserved_at_3[0x9];
9137 u8 group[0x4];
9138 u8 reserved_at_10[0x9];
9139 u8 bw_allocation[0x7];
9140
9141 u8 reserved_at_20[0xc];
9142 u8 max_bw_units[0x4];
9143 u8 reserved_at_30[0x8];
9144 u8 max_bw_value[0x8];
9145};
9146
9147struct mlx5_ifc_ets_global_config_reg_bits {
9148 u8 reserved_at_0[0x2];
9149 u8 r[0x1];
9150 u8 reserved_at_3[0x1d];
9151
9152 u8 reserved_at_20[0xc];
9153 u8 max_bw_units[0x4];
9154 u8 reserved_at_30[0x8];
9155 u8 max_bw_value[0x8];
9156};
9157
9158struct mlx5_ifc_qetc_reg_bits {
9159 u8 reserved_at_0[0x8];
9160 u8 port_number[0x8];
9161 u8 reserved_at_10[0x30];
9162
9163 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9164 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9165};
9166
415a64aa
HN		 9167struct mlx5_ifc_qpdpm_dscp_reg_bits {
9168 u8 e[0x1];
9169 u8 reserved_at_01[0x0b];
9170 u8 prio[0x04];
9171};
9172
9173struct mlx5_ifc_qpdpm_reg_bits {
9174 u8 reserved_at_0[0x8];
9175 u8 local_port[0x8];
9176 u8 reserved_at_10[0x10];
9177 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9178};
9179
9180struct mlx5_ifc_qpts_reg_bits {
9181 u8 reserved_at_0[0x8];
9182 u8 local_port[0x8];
9183 u8 reserved_at_10[0x2d];
9184 u8 trust_state[0x3];
9185};
9186
50b4a3c2
HN		 9187struct mlx5_ifc_pptb_reg_bits {
9188 u8 reserved_at_0[0x2];
9189 u8 mm[0x2];
9190 u8 reserved_at_4[0x4];
9191 u8 local_port[0x8];
9192 u8 reserved_at_10[0x6];
9193 u8 cm[0x1];
9194 u8 um[0x1];
9195 u8 pm[0x8];
9196
9197 u8 prio_x_buff[0x20];
9198
9199 u8 pm_msb[0x8];
9200 u8 reserved_at_48[0x10];
9201 u8 ctrl_buff[0x4];
9202 u8 untagged_buff[0x4];
9203};
9204
9205struct mlx5_ifc_pbmc_reg_bits {
9206 u8 reserved_at_0[0x8];
9207 u8 local_port[0x8];
9208 u8 reserved_at_10[0x10];
9209
9210 u8 xoff_timer_value[0x10];
9211 u8 xoff_refresh[0x10];
9212
9213 u8 reserved_at_40[0x9];
9214 u8 fullness_threshold[0x7];
9215 u8 port_buffer_size[0x10];
9216
9217 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9218
9219 u8 reserved_at_2e0[0x40];
9220};
9221
4f3961ee
SM		 9222struct mlx5_ifc_qtct_reg_bits {
9223 u8 reserved_at_0[0x8];
9224 u8 port_number[0x8];
9225 u8 reserved_at_10[0xd];
9226 u8 prio[0x3];
9227
9228 u8 reserved_at_20[0x1d];
9229 u8 tclass[0x3];
9230};
9231
7d5e1423
SM		 9232struct mlx5_ifc_mcia_reg_bits {
9233 u8 l[0x1];
9234 u8 reserved_at_1[0x7];
9235 u8 module[0x8];
9236 u8 reserved_at_10[0x8];
9237 u8 status[0x8];
9238
9239 u8 i2c_device_address[0x8];
9240 u8 page_number[0x8];
9241 u8 device_address[0x10];
9242
9243 u8 reserved_at_40[0x10];
9244 u8 size[0x10];
9245
9246 u8 reserved_at_60[0x20];
9247
9248 u8 dword_0[0x20];
9249 u8 dword_1[0x20];
9250 u8 dword_2[0x20];
9251 u8 dword_3[0x20];
9252 u8 dword_4[0x20];
9253 u8 dword_5[0x20];
9254 u8 dword_6[0x20];
9255 u8 dword_7[0x20];
9256 u8 dword_8[0x20];
9257 u8 dword_9[0x20];
9258 u8 dword_10[0x20];
9259 u8 dword_11[0x20];
9260};
9261
7486216b
SM		 9262struct mlx5_ifc_dcbx_param_bits {
9263 u8 dcbx_cee_cap[0x1];
9264 u8 dcbx_ieee_cap[0x1];
9265 u8 dcbx_standby_cap[0x1];
c74d90c1 9266 u8 reserved_at_3[0x5];
7486216b
SM		 9267 u8 port_number[0x8];
9268 u8 reserved_at_10[0xa];
9269 u8 max_application_table_size[6];
9270 u8 reserved_at_20[0x15];
9271 u8 version_oper[0x3];
9272 u8 reserved_at_38[5];
9273 u8 version_admin[0x3];
9274 u8 willing_admin[0x1];
9275 u8 reserved_at_41[0x3];
9276 u8 pfc_cap_oper[0x4];
9277 u8 reserved_at_48[0x4];
9278 u8 pfc_cap_admin[0x4];
9279 u8 reserved_at_50[0x4];
9280 u8 num_of_tc_oper[0x4];
9281 u8 reserved_at_58[0x4];
9282 u8 num_of_tc_admin[0x4];
9283 u8 remote_willing[0x1];
9284 u8 reserved_at_61[3];
9285 u8 remote_pfc_cap[4];
9286 u8 reserved_at_68[0x14];
9287 u8 remote_num_of_tc[0x4];
9288 u8 reserved_at_80[0x18];
9289 u8 error[0x8];
9290 u8 reserved_at_a0[0x160];
9291};
84df61eb
AH		 9292
9293struct mlx5_ifc_lagc_bits {
9294 u8 reserved_at_0[0x1d];
9295 u8 lag_state[0x3];
9296
9297 u8 reserved_at_20[0x14];
9298 u8 tx_remap_affinity_2[0x4];
9299 u8 reserved_at_38[0x4];
9300 u8 tx_remap_affinity_1[0x4];
9301};
9302
9303struct mlx5_ifc_create_lag_out_bits {
9304 u8 status[0x8];
9305 u8 reserved_at_8[0x18];
9306
9307 u8 syndrome[0x20];
9308
9309 u8 reserved_at_40[0x40];
9310};
9311
9312struct mlx5_ifc_create_lag_in_bits {
9313 u8 opcode[0x10];
9314 u8 reserved_at_10[0x10];
9315
9316 u8 reserved_at_20[0x10];
9317 u8 op_mod[0x10];
9318
9319 struct mlx5_ifc_lagc_bits ctx;
9320};
9321
9322struct mlx5_ifc_modify_lag_out_bits {
9323 u8 status[0x8];
9324 u8 reserved_at_8[0x18];
9325
9326 u8 syndrome[0x20];
9327
9328 u8 reserved_at_40[0x40];
9329};
9330
9331struct mlx5_ifc_modify_lag_in_bits {
9332 u8 opcode[0x10];
9333 u8 reserved_at_10[0x10];
9334
9335 u8 reserved_at_20[0x10];
9336 u8 op_mod[0x10];
9337
9338 u8 reserved_at_40[0x20];
9339 u8 field_select[0x20];
9340
9341 struct mlx5_ifc_lagc_bits ctx;
9342};
9343
9344struct mlx5_ifc_query_lag_out_bits {
9345 u8 status[0x8];
9346 u8 reserved_at_8[0x18];
9347
9348 u8 syndrome[0x20];
9349
9350 u8 reserved_at_40[0x40];
9351
9352 struct mlx5_ifc_lagc_bits ctx;
9353};
9354
9355struct mlx5_ifc_query_lag_in_bits {
9356 u8 opcode[0x10];
9357 u8 reserved_at_10[0x10];
9358
9359 u8 reserved_at_20[0x10];
9360 u8 op_mod[0x10];
9361
9362 u8 reserved_at_40[0x40];
9363};
9364
9365struct mlx5_ifc_destroy_lag_out_bits {
9366 u8 status[0x8];
9367 u8 reserved_at_8[0x18];
9368
9369 u8 syndrome[0x20];
9370
9371 u8 reserved_at_40[0x40];
9372};
9373
9374struct mlx5_ifc_destroy_lag_in_bits {
9375 u8 opcode[0x10];
9376 u8 reserved_at_10[0x10];
9377
9378 u8 reserved_at_20[0x10];
9379 u8 op_mod[0x10];
9380
9381 u8 reserved_at_40[0x40];
9382};
9383
9384struct mlx5_ifc_create_vport_lag_out_bits {
9385 u8 status[0x8];
9386 u8 reserved_at_8[0x18];
9387
9388 u8 syndrome[0x20];
9389
9390 u8 reserved_at_40[0x40];
9391};
9392
9393struct mlx5_ifc_create_vport_lag_in_bits {
9394 u8 opcode[0x10];
9395 u8 reserved_at_10[0x10];
9396
9397 u8 reserved_at_20[0x10];
9398 u8 op_mod[0x10];
9399
9400 u8 reserved_at_40[0x40];
9401};
9402
9403struct mlx5_ifc_destroy_vport_lag_out_bits {
9404 u8 status[0x8];
9405 u8 reserved_at_8[0x18];
9406
9407 u8 syndrome[0x20];
9408
9409 u8 reserved_at_40[0x40];
9410};
9411
9412struct mlx5_ifc_destroy_vport_lag_in_bits {
9413 u8 opcode[0x10];
9414 u8 reserved_at_10[0x10];
9415
9416 u8 reserved_at_20[0x10];
9417 u8 op_mod[0x10];
9418
9419 u8 reserved_at_40[0x40];
9420};
9421
24da0016
AL		 9422struct mlx5_ifc_alloc_memic_in_bits {
9423 u8 opcode[0x10];
9424 u8 reserved_at_10[0x10];
9425
9426 u8 reserved_at_20[0x10];
9427 u8 op_mod[0x10];
9428
9429 u8 reserved_at_30[0x20];
9430
9431 u8 reserved_at_40[0x18];
9432 u8 log_memic_addr_alignment[0x8];
9433
9434 u8 range_start_addr[0x40];
9435
9436 u8 range_size[0x20];
9437
9438 u8 memic_size[0x20];
9439};
9440
9441struct mlx5_ifc_alloc_memic_out_bits {
9442 u8 status[0x8];
9443 u8 reserved_at_8[0x18];
9444
9445 u8 syndrome[0x20];
9446
9447 u8 memic_start_addr[0x40];
9448};
9449
9450struct mlx5_ifc_dealloc_memic_in_bits {
9451 u8 opcode[0x10];
9452 u8 reserved_at_10[0x10];
9453
9454 u8 reserved_at_20[0x10];
9455 u8 op_mod[0x10];
9456
9457 u8 reserved_at_40[0x40];
9458
9459 u8 memic_start_addr[0x40];
9460
9461 u8 memic_size[0x20];
9462
9463 u8 reserved_at_e0[0x20];
9464};
9465
9466struct mlx5_ifc_dealloc_memic_out_bits {
9467 u8 status[0x8];
9468 u8 reserved_at_8[0x18];
9469
9470 u8 syndrome[0x20];
9471
9472 u8 reserved_at_40[0x40];
9473};
9474
38b7ca92
YH		 9475struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9476 u8 opcode[0x10];
9477 u8 uid[0x10];
9478
9479 u8 reserved_at_20[0x10];
9480 u8 obj_type[0x10];
9481
9482 u8 obj_id[0x20];
9483
9484 u8 reserved_at_60[0x20];
9485};
9486
9487struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9488 u8 status[0x8];
9489 u8 reserved_at_8[0x18];
9490
9491 u8 syndrome[0x20];
9492
9493 u8 obj_id[0x20];
9494
9495 u8 reserved_at_60[0x20];
9496};
9497
9498struct mlx5_ifc_umem_bits {
6e3722ba 9499 u8 reserved_at_0[0x80];
38b7ca92 9500
6e3722ba 9501 u8 reserved_at_80[0x1b];
38b7ca92
YH		 9502 u8 log_page_size[0x5];
9503
9504 u8 page_offset[0x20];
9505
9506 u8 num_of_mtt[0x40];
9507
9508 struct mlx5_ifc_mtt_bits mtt[0];
9509};
9510
9511struct mlx5_ifc_uctx_bits {
9d43faac
YH		 9512 u8 cap[0x20];
9513
6e3722ba 9514 u8 reserved_at_20[0x160];
38b7ca92
YH		 9515};
9516
9fba2b9b
AL		 9517struct mlx5_ifc_sw_icm_bits {
9518 u8 modify_field_select[0x40];
9519
9520 u8 reserved_at_40[0x18];
9521 u8 log_sw_icm_size[0x8];
9522
9523 u8 reserved_at_60[0x20];
9524
9525 u8 sw_icm_start_addr[0x40];
9526
9527 u8 reserved_at_c0[0x140];
9528};
9529
38b7ca92 9530struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 9531 u8 opcode[0x10];
9532 u8 uid[0x10];
9533
9534 u8 reserved_at_20[0x10];
9535 u8 op_mod[0x10];
9536
9537 u8 reserved_at_40[0x40];
9538
9539 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 9540};
9541
9542struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 9543 u8 opcode[0x10];
9544 u8 reserved_at_10[0x10];
9545
9546 u8 reserved_at_20[0x10];
9547 u8 op_mod[0x10];
9548
9549 u8 reserved_at_40[0x40];
9550
9551 struct mlx5_ifc_uctx_bits uctx;
9552};
9553
9554struct mlx5_ifc_destroy_uctx_in_bits {
9555 u8 opcode[0x10];
9556 u8 reserved_at_10[0x10];
9557
9558 u8 reserved_at_20[0x10];
9559 u8 op_mod[0x10];
9560
9561 u8 reserved_at_40[0x10];
9562 u8 uid[0x10];
9563
9564 u8 reserved_at_60[0x20];
38b7ca92
YH		 9565};
9566
9fba2b9b
AL		 9567struct mlx5_ifc_create_sw_icm_in_bits {
9568 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9569 struct mlx5_ifc_sw_icm_bits sw_icm;
9570};
9571
eff8ea8f
FD		 9572struct mlx5_ifc_mtrc_string_db_param_bits {
9573 u8 string_db_base_address[0x20];
9574
9575 u8 reserved_at_20[0x8];
9576 u8 string_db_size[0x18];
9577};
9578
9579struct mlx5_ifc_mtrc_cap_bits {
9580 u8 trace_owner[0x1];
9581 u8 trace_to_memory[0x1];
9582 u8 reserved_at_2[0x4];
9583 u8 trc_ver[0x2];
9584 u8 reserved_at_8[0x14];
9585 u8 num_string_db[0x4];
9586
9587 u8 first_string_trace[0x8];
9588 u8 num_string_trace[0x8];
9589 u8 reserved_at_30[0x28];
9590
9591 u8 log_max_trace_buffer_size[0x8];
9592
9593 u8 reserved_at_60[0x20];
9594
9595 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9596
9597 u8 reserved_at_280[0x180];
9598};
9599
9600struct mlx5_ifc_mtrc_conf_bits {
9601 u8 reserved_at_0[0x1c];
9602 u8 trace_mode[0x4];
9603 u8 reserved_at_20[0x18];
9604 u8 log_trace_buffer_size[0x8];
9605 u8 trace_mkey[0x20];
9606 u8 reserved_at_60[0x3a0];
9607};
9608
9609struct mlx5_ifc_mtrc_stdb_bits {
9610 u8 string_db_index[0x4];
9611 u8 reserved_at_4[0x4];
9612 u8 read_size[0x18];
9613 u8 start_offset[0x20];
9614 u8 string_db_data[0];
9615};
9616
9617struct mlx5_ifc_mtrc_ctrl_bits {
9618 u8 trace_status[0x2];
9619 u8 reserved_at_2[0x2];
9620 u8 arm_event[0x1];
9621 u8 reserved_at_5[0xb];
9622 u8 modify_field_select[0x10];
9623 u8 reserved_at_20[0x2b];
9624 u8 current_timestamp52_32[0x15];
9625 u8 current_timestamp31_0[0x20];
9626 u8 reserved_at_80[0x180];
9627};
9628
c3a4e9f1
BW		 9629struct mlx5_ifc_host_params_context_bits {
9630 u8 host_number[0x8];
9631 u8 reserved_at_8[0x8];
9632 u8 host_num_of_vfs[0x10];
9633
9634 u8 reserved_at_20[0x10];
9635 u8 host_pci_bus[0x10];
9636
9637 u8 reserved_at_40[0x10];
9638 u8 host_pci_device[0x10];
9639
9640 u8 reserved_at_60[0x10];
9641 u8 host_pci_function[0x10];
9642
9643 u8 reserved_at_80[0x180];
9644};
9645
9646struct mlx5_ifc_query_host_params_in_bits {
9647 u8 opcode[0x10];
9648 u8 reserved_at_10[0x10];
9649
9650 u8 reserved_at_20[0x10];
9651 u8 op_mod[0x10];
9652
9653 u8 reserved_at_40[0x40];
9654};
9655
9656struct mlx5_ifc_query_host_params_out_bits {
9657 u8 status[0x8];
9658 u8 reserved_at_8[0x18];
9659
9660 u8 syndrome[0x20];
9661
9662 u8 reserved_at_40[0x40];
9663
9664 struct mlx5_ifc_host_params_context_bits host_params_context;
9665
9666 u8 reserved_at_280[0x180];
9667};
9668
d29b796a 9669#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)