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net/mlx5: Expose IP-in-IP capability bit
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
66enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71};
72
f91e6d89
EBE		 73enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89
EBE		 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77};
78
38b7ca92 79enum {
2acc7957 80 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 81};
82
9fba2b9b
AL		 83enum {
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
85};
86
87enum {
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
b169e64a
YK		 89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90};
91
92enum {
93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
e4075c44
YH		 94 MLX5_OBJ_TYPE_MKEY = 0xff01,
95 MLX5_OBJ_TYPE_QP = 0xff02,
96 MLX5_OBJ_TYPE_PSV = 0xff03,
97 MLX5_OBJ_TYPE_RMP = 0xff04,
98 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99 MLX5_OBJ_TYPE_RQ = 0xff06,
100 MLX5_OBJ_TYPE_SQ = 0xff07,
101 MLX5_OBJ_TYPE_TIR = 0xff08,
102 MLX5_OBJ_TYPE_TIS = 0xff09,
103 MLX5_OBJ_TYPE_DCT = 0xff0a,
104 MLX5_OBJ_TYPE_XRQ = 0xff0b,
105 MLX5_OBJ_TYPE_RQT = 0xff0e,
106 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107 MLX5_OBJ_TYPE_CQ = 0xff10,
9fba2b9b
AL		 108};
109
d29b796a
EC		 110enum {
111 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
112 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
113 MLX5_CMD_OP_INIT_HCA = 0x102,
114 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
115 MLX5_CMD_OP_ENABLE_HCA = 0x104,
116 MLX5_CMD_OP_DISABLE_HCA = 0x105,
117 MLX5_CMD_OP_QUERY_PAGES = 0x107,
118 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
119 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 120 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
121 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
1759d322
PP		 123 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
124 MLX5_CMD_OP_ALLOC_SF = 0x113,
125 MLX5_CMD_OP_DEALLOC_SF = 0x114,
d29b796a
EC		 126 MLX5_CMD_OP_CREATE_MKEY = 0x200,
127 MLX5_CMD_OP_QUERY_MKEY = 0x201,
128 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
129 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
130 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 131 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
132 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 133 MLX5_CMD_OP_CREATE_EQ = 0x301,
134 MLX5_CMD_OP_DESTROY_EQ = 0x302,
135 MLX5_CMD_OP_QUERY_EQ = 0x303,
136 MLX5_CMD_OP_GEN_EQE = 0x304,
137 MLX5_CMD_OP_CREATE_CQ = 0x400,
138 MLX5_CMD_OP_DESTROY_CQ = 0x401,
139 MLX5_CMD_OP_QUERY_CQ = 0x402,
140 MLX5_CMD_OP_MODIFY_CQ = 0x403,
141 MLX5_CMD_OP_CREATE_QP = 0x500,
142 MLX5_CMD_OP_DESTROY_QP = 0x501,
143 MLX5_CMD_OP_RST2INIT_QP = 0x502,
144 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
145 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
146 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
147 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
148 MLX5_CMD_OP_2ERR_QP = 0x507,
149 MLX5_CMD_OP_2RST_QP = 0x50a,
150 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 151 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 152 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
153 MLX5_CMD_OP_CREATE_PSV = 0x600,
154 MLX5_CMD_OP_DESTROY_PSV = 0x601,
155 MLX5_CMD_OP_CREATE_SRQ = 0x700,
156 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
157 MLX5_CMD_OP_QUERY_SRQ = 0x702,
158 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 159 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
160 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
161 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
162 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 163 MLX5_CMD_OP_CREATE_DCT = 0x710,
164 MLX5_CMD_OP_DESTROY_DCT = 0x711,
165 MLX5_CMD_OP_DRAIN_DCT = 0x712,
166 MLX5_CMD_OP_QUERY_DCT = 0x713,
167 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 168 MLX5_CMD_OP_CREATE_XRQ = 0x717,
169 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
170 MLX5_CMD_OP_QUERY_XRQ = 0x719,
171 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 172 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
173 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
174 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
b1635ee6
YH		 175 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
176 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
cd56f929 177 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
d29b796a
EC		 178 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
179 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
180 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
181 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
182 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
183 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 184 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 185 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 186 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
187 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
188 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 190 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 191 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
192 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
193 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
194 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 195 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
196 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 197 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 198 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 199 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
200 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
201 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
202 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
203 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
204 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 205 MLX5_CMD_OP_ALLOC_PD = 0x800,
206 MLX5_CMD_OP_DEALLOC_PD = 0x801,
207 MLX5_CMD_OP_ALLOC_UAR = 0x802,
208 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
209 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
210 MLX5_CMD_OP_ACCESS_REG = 0x805,
211 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 212 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 213 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
214 MLX5_CMD_OP_MAD_IFC = 0x50d,
215 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
216 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
217 MLX5_CMD_OP_NOP = 0x80d,
218 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
219 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 220 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
221 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
222 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
223 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
224 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
225 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
226 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
227 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
228 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
229 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
230 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
231 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 232 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
233 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 234 MLX5_CMD_OP_CREATE_LAG = 0x840,
235 MLX5_CMD_OP_MODIFY_LAG = 0x841,
236 MLX5_CMD_OP_QUERY_LAG = 0x842,
237 MLX5_CMD_OP_DESTROY_LAG = 0x843,
238 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
239 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 240 MLX5_CMD_OP_CREATE_TIR = 0x900,
241 MLX5_CMD_OP_MODIFY_TIR = 0x901,
242 MLX5_CMD_OP_DESTROY_TIR = 0x902,
243 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 244 MLX5_CMD_OP_CREATE_SQ = 0x904,
245 MLX5_CMD_OP_MODIFY_SQ = 0x905,
246 MLX5_CMD_OP_DESTROY_SQ = 0x906,
247 MLX5_CMD_OP_QUERY_SQ = 0x907,
248 MLX5_CMD_OP_CREATE_RQ = 0x908,
249 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 250 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 251 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
252 MLX5_CMD_OP_QUERY_RQ = 0x90b,
253 MLX5_CMD_OP_CREATE_RMP = 0x90c,
254 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
255 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
256 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 257 MLX5_CMD_OP_CREATE_TIS = 0x912,
258 MLX5_CMD_OP_MODIFY_TIS = 0x913,
259 MLX5_CMD_OP_DESTROY_TIS = 0x914,
260 MLX5_CMD_OP_QUERY_TIS = 0x915,
261 MLX5_CMD_OP_CREATE_RQT = 0x916,
262 MLX5_CMD_OP_MODIFY_RQT = 0x917,
263 MLX5_CMD_OP_DESTROY_RQT = 0x918,
264 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 265 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 266 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
267 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
268 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
269 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
270 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
271 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
272 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
273 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 274 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 275 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
276 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
277 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 278 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 279 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
280 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 281 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 285 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
286 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
287 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
288 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
289 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 290 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 291 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
292 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 293 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 294 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
295 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
296 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
297 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
86d56a1a 298 MLX5_CMD_OP_MAX
e281682b
SM		 299};
300
719598c9
YH		 301/* Valid range for general commands that don't work over an object */
302enum {
303 MLX5_CMD_OP_GENERAL_START = 0xb00,
304 MLX5_CMD_OP_GENERAL_END = 0xd00,
305};
306
e281682b
SM		 307struct mlx5_ifc_flow_table_fields_supported_bits {
308 u8 outer_dmac[0x1];
309 u8 outer_smac[0x1];
310 u8 outer_ether_type[0x1];
19cc7524 311 u8 outer_ip_version[0x1];
e281682b
SM		 312 u8 outer_first_prio[0x1];
313 u8 outer_first_cfi[0x1];
314 u8 outer_first_vid[0x1];
a8ade55f 315 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 316 u8 outer_second_prio[0x1];
317 u8 outer_second_cfi[0x1];
318 u8 outer_second_vid[0x1];
b4ff3a36 319 u8 reserved_at_b[0x1];
e281682b
SM		 320 u8 outer_sip[0x1];
321 u8 outer_dip[0x1];
322 u8 outer_frag[0x1];
323 u8 outer_ip_protocol[0x1];
324 u8 outer_ip_ecn[0x1];
325 u8 outer_ip_dscp[0x1];
326 u8 outer_udp_sport[0x1];
327 u8 outer_udp_dport[0x1];
328 u8 outer_tcp_sport[0x1];
329 u8 outer_tcp_dport[0x1];
330 u8 outer_tcp_flags[0x1];
331 u8 outer_gre_protocol[0x1];
332 u8 outer_gre_key[0x1];
333 u8 outer_vxlan_vni[0x1];
75d90e7d
YK		 334 u8 outer_geneve_vni[0x1];
335 u8 outer_geneve_oam[0x1];
336 u8 outer_geneve_protocol_type[0x1];
337 u8 outer_geneve_opt_len[0x1];
338 u8 reserved_at_1e[0x1];
e281682b
SM		 339 u8 source_eswitch_port[0x1];
340
341 u8 inner_dmac[0x1];
342 u8 inner_smac[0x1];
343 u8 inner_ether_type[0x1];
19cc7524 344 u8 inner_ip_version[0x1];
e281682b
SM		 345 u8 inner_first_prio[0x1];
346 u8 inner_first_cfi[0x1];
347 u8 inner_first_vid[0x1];
b4ff3a36 348 u8 reserved_at_27[0x1];
e281682b
SM		 349 u8 inner_second_prio[0x1];
350 u8 inner_second_cfi[0x1];
351 u8 inner_second_vid[0x1];
b4ff3a36 352 u8 reserved_at_2b[0x1];
e281682b
SM		 353 u8 inner_sip[0x1];
354 u8 inner_dip[0x1];
355 u8 inner_frag[0x1];
356 u8 inner_ip_protocol[0x1];
357 u8 inner_ip_ecn[0x1];
358 u8 inner_ip_dscp[0x1];
359 u8 inner_udp_sport[0x1];
360 u8 inner_udp_dport[0x1];
361 u8 inner_tcp_sport[0x1];
362 u8 inner_tcp_dport[0x1];
363 u8 inner_tcp_flags[0x1];
b4ff3a36 364 u8 reserved_at_37[0x9];
71c6e863 365
b169e64a
YK		 366 u8 geneve_tlv_option_0_data[0x1];
367 u8 reserved_at_41[0x4];
71c6e863
AL		 368 u8 outer_first_mpls_over_udp[0x4];
369 u8 outer_first_mpls_over_gre[0x4];
370 u8 inner_first_mpls[0x4];
371 u8 outer_first_mpls[0x4];
372 u8 reserved_at_55[0x2];
3346c487 373 u8 outer_esp_spi[0x1];
71c6e863 374 u8 reserved_at_58[0x2];
a550ddfc 375 u8 bth_dst_qp[0x1];
e281682b 376
a550ddfc 377 u8 reserved_at_5b[0x25];
e281682b
SM		 378};
379
380struct mlx5_ifc_flow_table_prop_layout_bits {
381 u8 ft_support[0x1];
9dc0b289
AV		 382 u8 reserved_at_1[0x1];
383 u8 flow_counter[0x1];
26a81453 384 u8 flow_modify_en[0x1];
2cc43b49 385 u8 modify_root[0x1];
34a40e68
MG		 386 u8 identified_miss_table_mode[0x1];
387 u8 flow_table_modify[0x1];
60786f09 388 u8 reformat[0x1];
7adbde20 389 u8 decap[0x1];
0c06897a
OG		 390 u8 reserved_at_9[0x1];
391 u8 pop_vlan[0x1];
392 u8 push_vlan[0x1];
8da6fe2a
JL		 393 u8 reserved_at_c[0x1];
394 u8 pop_vlan_2[0x1];
395 u8 push_vlan_2[0x1];
bea4e1f6 396 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 397 u8 reserved_at_10[0x1];
398 u8 sw_owner[0x1];
bea4e1f6
MB		 399 u8 reformat_l3_tunnel_to_l2[0x1];
400 u8 reformat_l2_to_l3_tunnel[0x1];
401 u8 reformat_and_modify_action[0x1];
f6f7d6b5
MG		 402 u8 reserved_at_15[0x2];
403 u8 table_miss_action_domain[0x1];
c6d4e45d
EB		 404 u8 termination_table[0x1];
405 u8 reserved_at_19[0x7];
b4ff3a36 406 u8 reserved_at_20[0x2];
e281682b 407 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 408 u8 log_max_modify_header_context[0x8];
409 u8 max_modify_header_actions[0x8];
e281682b
SM		 410 u8 max_ft_level[0x8];
411
b4ff3a36 412 u8 reserved_at_40[0x20];
e281682b 413
b4ff3a36 414 u8 reserved_at_60[0x18];
e281682b
SM		 415 u8 log_max_ft_num[0x8];
416
b4ff3a36 417 u8 reserved_at_80[0x18];
e281682b
SM		 418 u8 log_max_destination[0x8];
419
16f1c5bb
RS		 420 u8 log_max_flow_counter[0x8];
421 u8 reserved_at_a8[0x10];
e281682b
SM		 422 u8 log_max_flow[0x8];
423
b4ff3a36 424 u8 reserved_at_c0[0x40];
e281682b
SM		 425
426 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
427
428 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
429};
430
431struct mlx5_ifc_odp_per_transport_service_cap_bits {
432 u8 send[0x1];
433 u8 receive[0x1];
434 u8 write[0x1];
435 u8 read[0x1];
17d2f88f 436 u8 atomic[0x1];
e281682b 437 u8 srq_receive[0x1];
b4ff3a36 438 u8 reserved_at_6[0x1a];
e281682b
SM		 439};
440
441struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
442 u8 smac_47_16[0x20];
443
444 u8 smac_15_0[0x10];
445 u8 ethertype[0x10];
446
447 u8 dmac_47_16[0x20];
448
449 u8 dmac_15_0[0x10];
450 u8 first_prio[0x3];
451 u8 first_cfi[0x1];
452 u8 first_vid[0xc];
453
454 u8 ip_protocol[0x8];
455 u8 ip_dscp[0x6];
456 u8 ip_ecn[0x2];
10543365
MHY		 457 u8 cvlan_tag[0x1];
458 u8 svlan_tag[0x1];
e281682b 459 u8 frag[0x1];
19cc7524 460 u8 ip_version[0x4];
e281682b
SM		 461 u8 tcp_flags[0x9];
462
463 u8 tcp_sport[0x10];
464 u8 tcp_dport[0x10];
465
a8ade55f
OG		 466 u8 reserved_at_c0[0x18];
467 u8 ttl_hoplimit[0x8];
e281682b
SM		 468
469 u8 udp_sport[0x10];
470 u8 udp_dport[0x10];
471
b4d1f032 472 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 473
b4d1f032 474 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 475};
476
5886a96a
OS		 477struct mlx5_ifc_nvgre_key_bits {
478 u8 hi[0x18];
479 u8 lo[0x8];
480};
481
482union mlx5_ifc_gre_key_bits {
483 struct mlx5_ifc_nvgre_key_bits nvgre;
484 u8 key[0x20];
485};
486
e281682b 487struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 488 u8 reserved_at_0[0x8];
489 u8 source_sqn[0x18];
e281682b 490
3e99df87 491 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 492 u8 source_port[0x10];
493
494 u8 outer_second_prio[0x3];
495 u8 outer_second_cfi[0x1];
496 u8 outer_second_vid[0xc];
497 u8 inner_second_prio[0x3];
498 u8 inner_second_cfi[0x1];
499 u8 inner_second_vid[0xc];
500
10543365
MHY		 501 u8 outer_second_cvlan_tag[0x1];
502 u8 inner_second_cvlan_tag[0x1];
503 u8 outer_second_svlan_tag[0x1];
504 u8 inner_second_svlan_tag[0x1];
505 u8 reserved_at_64[0xc];
e281682b
SM		 506 u8 gre_protocol[0x10];
507
5886a96a 508 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 509
510 u8 vxlan_vni[0x18];
b4ff3a36 511 u8 reserved_at_b8[0x8];
e281682b 512
75d90e7d
YK		 513 u8 geneve_vni[0x18];
514 u8 reserved_at_d8[0x7];
515 u8 geneve_oam[0x1];
e281682b 516
b4ff3a36 517 u8 reserved_at_e0[0xc];
e281682b
SM		 518 u8 outer_ipv6_flow_label[0x14];
519
b4ff3a36 520 u8 reserved_at_100[0xc];
e281682b
SM		 521 u8 inner_ipv6_flow_label[0x14];
522
75d90e7d
YK		 523 u8 reserved_at_120[0xa];
524 u8 geneve_opt_len[0x6];
525 u8 geneve_protocol_type[0x10];
526
527 u8 reserved_at_140[0x8];
a550ddfc 528 u8 bth_dst_qp[0x18];
3346c487
BP		 529 u8 reserved_at_160[0x20];
530 u8 outer_esp_spi[0x20];
531 u8 reserved_at_1a0[0x60];
e281682b
SM		 532};
533
71c6e863
AL		 534struct mlx5_ifc_fte_match_mpls_bits {
535 u8 mpls_label[0x14];
536 u8 mpls_exp[0x3];
537 u8 mpls_s_bos[0x1];
538 u8 mpls_ttl[0x8];
539};
540
541struct mlx5_ifc_fte_match_set_misc2_bits {
542 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
543
544 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
545
546 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
547
548 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
549
65c0f2c1
JL		 550 u8 metadata_reg_c_7[0x20];
551
552 u8 metadata_reg_c_6[0x20];
553
554 u8 metadata_reg_c_5[0x20];
555
556 u8 metadata_reg_c_4[0x20];
557
558 u8 metadata_reg_c_3[0x20];
559
560 u8 metadata_reg_c_2[0x20];
561
562 u8 metadata_reg_c_1[0x20];
563
564 u8 metadata_reg_c_0[0x20];
71c6e863
AL		 565
566 u8 metadata_reg_a[0x20];
567
568 u8 reserved_at_1a0[0x60];
569};
570
b169e64a
YK		 571struct mlx5_ifc_fte_match_set_misc3_bits {
572 u8 reserved_at_0[0x120];
573 u8 geneve_tlv_option_0_data[0x20];
574 u8 reserved_at_140[0xc0];
575};
576
e281682b
SM		 577struct mlx5_ifc_cmd_pas_bits {
578 u8 pa_h[0x20];
579
580 u8 pa_l[0x14];
b4ff3a36 581 u8 reserved_at_34[0xc];
e281682b
SM		 582};
583
584struct mlx5_ifc_uint64_bits {
585 u8 hi[0x20];
586
587 u8 lo[0x20];
588};
589
590enum {
591 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
592 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
593 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
594 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
595 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
596 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
597 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
598 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
599 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
600 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
601};
602
603struct mlx5_ifc_ads_bits {
604 u8 fl[0x1];
605 u8 free_ar[0x1];
b4ff3a36 606 u8 reserved_at_2[0xe];
e281682b
SM		 607 u8 pkey_index[0x10];
608
b4ff3a36 609 u8 reserved_at_20[0x8];
e281682b
SM		 610 u8 grh[0x1];
611 u8 mlid[0x7];
612 u8 rlid[0x10];
613
614 u8 ack_timeout[0x5];
b4ff3a36 615 u8 reserved_at_45[0x3];
e281682b 616 u8 src_addr_index[0x8];
b4ff3a36 617 u8 reserved_at_50[0x4];
e281682b
SM		 618 u8 stat_rate[0x4];
619 u8 hop_limit[0x8];
620
b4ff3a36 621 u8 reserved_at_60[0x4];
e281682b
SM		 622 u8 tclass[0x8];
623 u8 flow_label[0x14];
624
625 u8 rgid_rip[16][0x8];
626
b4ff3a36 627 u8 reserved_at_100[0x4];
e281682b
SM		 628 u8 f_dscp[0x1];
629 u8 f_ecn[0x1];
b4ff3a36 630 u8 reserved_at_106[0x1];
e281682b
SM		 631 u8 f_eth_prio[0x1];
632 u8 ecn[0x2];
633 u8 dscp[0x6];
634 u8 udp_sport[0x10];
635
636 u8 dei_cfi[0x1];
637 u8 eth_prio[0x3];
638 u8 sl[0x4];
32f69e4b 639 u8 vhca_port_num[0x8];
e281682b
SM		 640 u8 rmac_47_32[0x10];
641
642 u8 rmac_31_0[0x20];
643};
644
645struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 646 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 647 u8 nic_rx_multi_path_tirs_fts[0x1];
648 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
bea4e1f6
MB		 649 u8 reserved_at_3[0x1d];
650 u8 encap_general_header[0x1];
651 u8 reserved_at_21[0xa];
652 u8 log_max_packet_reformat_context[0x5];
653 u8 reserved_at_30[0x6];
654 u8 max_encap_header_size[0xa];
655 u8 reserved_at_40[0x1c0];
e281682b
SM		 656
657 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
658
d83eb50e 659 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
e281682b
SM		 660
661 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
662
663 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
664
b4ff3a36 665 u8 reserved_at_a00[0x200];
e281682b
SM		 666
667 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
668
b4ff3a36 669 u8 reserved_at_e00[0x7200];
e281682b
SM		 670};
671
65c0f2c1
JL		 672enum {
673 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
674 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
675 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
676 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
677 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
678 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
679 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
680 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
681};
682
495716b1 683struct mlx5_ifc_flow_table_eswitch_cap_bits {
65c0f2c1
JL		 684 u8 fdb_to_vport_reg_c_id[0x8];
685 u8 reserved_at_8[0xf];
686 u8 flow_source[0x1];
687 u8 reserved_at_18[0x2];
b9aa0ba1 688 u8 multi_fdb_encap[0x1];
663f146f
VP		 689 u8 reserved_at_1b[0x1];
690 u8 fdb_multi_path_to_table[0x1];
691 u8 reserved_at_1d[0x3];
692
693 u8 reserved_at_20[0x1e0];
495716b1
SM		 694
695 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
696
697 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
698
699 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
700
b4ff3a36 701 u8 reserved_at_800[0x7800];
495716b1
SM		 702};
703
8bb957d2
SK		 704enum {
705 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
706 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
707};
708
d6666753
SM		 709struct mlx5_ifc_e_switch_cap_bits {
710 u8 vport_svlan_strip[0x1];
711 u8 vport_cvlan_strip[0x1];
712 u8 vport_svlan_insert[0x1];
713 u8 vport_cvlan_insert_if_not_exist[0x1];
714 u8 vport_cvlan_insert_overwrite[0x1];
65c0f2c1
JL		 715 u8 reserved_at_5[0x3];
716 u8 esw_uplink_ingress_acl[0x1];
717 u8 reserved_at_9[0x10];
6706a3b9
VP		 718 u8 esw_functions_changed[0x1];
719 u8 reserved_at_1a[0x1];
81cd229c 720 u8 ecpf_vport_exists[0x1];
8bb957d2 721 u8 counter_eswitch_affinity[0x1];
a6d04569 722 u8 merged_eswitch[0x1];
23898c76
NO		 723 u8 nic_vport_node_guid_modify[0x1];
724 u8 nic_vport_port_guid_modify[0x1];
d6666753 725
7adbde20
HHZ		 726 u8 vxlan_encap_decap[0x1];
727 u8 nvgre_encap_decap[0x1];
1b115498
EB		 728 u8 reserved_at_22[0x1];
729 u8 log_max_fdb_encap_uplink[0x5];
730 u8 reserved_at_21[0x3];
60786f09 731 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 732 u8 reserved_2b[0x6];
733 u8 max_encap_header_size[0xa];
734
1759d322
PP		 735 u8 reserved_at_40[0xb];
736 u8 log_max_esw_sf[0x5];
737 u8 esw_sf_base_id[0x10];
738
739 u8 reserved_at_60[0x7a0];
7adbde20 740
d6666753
SM		 741};
742
7486216b
SM		 743struct mlx5_ifc_qos_cap_bits {
744 u8 packet_pacing[0x1];
813f8540 745 u8 esw_scheduling[0x1];
c9497c98
MHY		 746 u8 esw_bw_share[0x1];
747 u8 esw_rate_limit[0x1];
05d3ac97
BW		 748 u8 reserved_at_4[0x1];
749 u8 packet_pacing_burst_bound[0x1];
750 u8 packet_pacing_typical_size[0x1];
751 u8 reserved_at_7[0x19];
813f8540
MHY		 752
753 u8 reserved_at_20[0x20];
754
7486216b 755 u8 packet_pacing_max_rate[0x20];
813f8540 756
7486216b 757 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 758
759 u8 reserved_at_80[0x10];
7486216b 760 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 761
762 u8 esw_element_type[0x10];
763 u8 esw_tsar_type[0x10];
764
765 u8 reserved_at_c0[0x10];
766 u8 max_qos_para_vport[0x10];
767
768 u8 max_tsar_bw_share[0x20];
769
770 u8 reserved_at_100[0x700];
7486216b
SM		 771};
772
2fcb12df 773struct mlx5_ifc_debug_cap_bits {
0b9055a1
MS		 774 u8 core_dump_general[0x1];
775 u8 core_dump_qp[0x1];
776 u8 reserved_at_2[0x1e];
2fcb12df
IK		 777
778 u8 reserved_at_20[0x2];
779 u8 stall_detect[0x1];
780 u8 reserved_at_23[0x1d];
781
782 u8 reserved_at_40[0x7c0];
783};
784
e281682b
SM		 785struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
786 u8 csum_cap[0x1];
787 u8 vlan_cap[0x1];
788 u8 lro_cap[0x1];
789 u8 lro_psh_flag[0x1];
790 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 791 u8 reserved_at_5[0x2];
792 u8 wqe_vlan_insert[0x1];
66189961 793 u8 self_lb_en_modifiable[0x1];
b4ff3a36 794 u8 reserved_at_9[0x2];
e281682b 795 u8 max_lso_cap[0x5];
c226dc22 796 u8 multi_pkt_send_wqe[0x2];
cff92d7c 797 u8 wqe_inline_mode[0x2];
e281682b 798 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 799 u8 reg_umr_sq[0x1];
800 u8 scatter_fcs[0x1];
050da902 801 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 802 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 803 u8 reserved_at_1c[0x2];
27299841 804 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 805 u8 tunnel_stateless_vxlan[0x1];
806
547eede0
IT		 807 u8 swp[0x1];
808 u8 swp_csum[0x1];
809 u8 swp_lso[0x1];
db849faa 810 u8 cqe_checksum_full[0x1];
caa18547
AL		 811 u8 reserved_at_24[0x5];
812 u8 tunnel_stateless_ip_over_ip[0x1];
813 u8 reserved_at_2a[0x6];
22a65aa8
GP		 814 u8 max_vxlan_udp_ports[0x8];
815 u8 reserved_at_38[0x6];
4d350f1f
MG		 816 u8 max_geneve_opt_len[0x1];
817 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 818
b4ff3a36 819 u8 reserved_at_40[0x10];
e281682b
SM		 820 u8 lro_min_mss_size[0x10];
821
b4ff3a36 822 u8 reserved_at_60[0x120];
e281682b
SM		 823
824 u8 lro_timer_supported_periods[4][0x20];
825
b4ff3a36 826 u8 reserved_at_200[0x600];
e281682b
SM		 827};
828
829struct mlx5_ifc_roce_cap_bits {
830 u8 roce_apm[0x1];
b4ff3a36 831 u8 reserved_at_1[0x1f];
e281682b 832
b4ff3a36 833 u8 reserved_at_20[0x60];
e281682b 834
b4ff3a36 835 u8 reserved_at_80[0xc];
e281682b 836 u8 l3_type[0x4];
b4ff3a36 837 u8 reserved_at_90[0x8];
e281682b
SM		 838 u8 roce_version[0x8];
839
b4ff3a36 840 u8 reserved_at_a0[0x10];
e281682b
SM		 841 u8 r_roce_dest_udp_port[0x10];
842
843 u8 r_roce_max_src_udp_port[0x10];
844 u8 r_roce_min_src_udp_port[0x10];
845
b4ff3a36 846 u8 reserved_at_e0[0x10];
e281682b
SM		 847 u8 roce_address_table_size[0x10];
848
b4ff3a36 849 u8 reserved_at_100[0x700];
e281682b
SM		 850};
851
e72bd817
AL		 852struct mlx5_ifc_device_mem_cap_bits {
853 u8 memic[0x1];
854 u8 reserved_at_1[0x1f];
855
856 u8 reserved_at_20[0xb];
857 u8 log_min_memic_alloc_size[0x5];
858 u8 reserved_at_30[0x8];
859 u8 log_max_memic_addr_alignment[0x8];
860
861 u8 memic_bar_start_addr[0x40];
862
863 u8 memic_bar_size[0x20];
864
865 u8 max_memic_size[0x20];
866
9fba2b9b
AL		 867 u8 steering_sw_icm_start_address[0x40];
868
869 u8 reserved_at_100[0x8];
870 u8 log_header_modify_sw_icm_size[0x8];
871 u8 reserved_at_110[0x2];
872 u8 log_sw_icm_alloc_granularity[0x6];
873 u8 log_steering_sw_icm_size[0x8];
874
875 u8 reserved_at_120[0x20];
876
877 u8 header_modify_sw_icm_start_address[0x40];
878
879 u8 reserved_at_180[0x680];
e72bd817
AL		 880};
881
b9a7ba55
YH		 882struct mlx5_ifc_device_event_cap_bits {
883 u8 user_affiliated_events[4][0x40];
884
885 u8 user_unaffiliated_events[4][0x40];
886};
887
e281682b
SM		 888enum {
889 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
890 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
891 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
892 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
893 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
894 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
895 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
896 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
897 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
898};
899
900enum {
901 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
902 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
903 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
904 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
905 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
906 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
907 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
908 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
909 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
910};
911
912struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 913 u8 reserved_at_0[0x40];
e281682b 914
bd10838a 915 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 916 u8 reserved_at_42[0x4];
bd10838a 917 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 918
b4ff3a36 919 u8 reserved_at_47[0x19];
e281682b 920
b4ff3a36 921 u8 reserved_at_60[0x20];
e281682b 922
b4ff3a36 923 u8 reserved_at_80[0x10];
f91e6d89 924 u8 atomic_operations[0x10];
e281682b 925
b4ff3a36 926 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 927 u8 atomic_size_qp[0x10];
928
b4ff3a36 929 u8 reserved_at_c0[0x10];
e281682b
SM		 930 u8 atomic_size_dc[0x10];
931
b4ff3a36 932 u8 reserved_at_e0[0x720];
e281682b
SM		 933};
934
935struct mlx5_ifc_odp_cap_bits {
b4ff3a36 936 u8 reserved_at_0[0x40];
e281682b
SM		 937
938 u8 sig[0x1];
b4ff3a36 939 u8 reserved_at_41[0x1f];
e281682b 940
b4ff3a36 941 u8 reserved_at_60[0x20];
e281682b
SM		 942
943 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
944
945 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
946
947 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
948
dda7a817
MS		 949 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
950
951 u8 reserved_at_100[0x700];
e281682b
SM		 952};
953
3f0393a5
SG		 954struct mlx5_ifc_calc_op {
955 u8 reserved_at_0[0x10];
956 u8 reserved_at_10[0x9];
957 u8 op_swap_endianness[0x1];
958 u8 op_min[0x1];
959 u8 op_xor[0x1];
960 u8 op_or[0x1];
961 u8 op_and[0x1];
962 u8 op_max[0x1];
963 u8 op_add[0x1];
964};
965
966struct mlx5_ifc_vector_calc_cap_bits {
967 u8 calc_matrix[0x1];
968 u8 reserved_at_1[0x1f];
969 u8 reserved_at_20[0x8];
970 u8 max_vec_count[0x8];
971 u8 reserved_at_30[0xd];
972 u8 max_chunk_size[0x3];
973 struct mlx5_ifc_calc_op calc0;
974 struct mlx5_ifc_calc_op calc1;
975 struct mlx5_ifc_calc_op calc2;
976 struct mlx5_ifc_calc_op calc3;
977
c74d90c1 978 u8 reserved_at_c0[0x720];
3f0393a5
SG		 979};
980
a12ff35e
EBE		 981struct mlx5_ifc_tls_cap_bits {
982 u8 tls_1_2_aes_gcm_128[0x1];
983 u8 tls_1_3_aes_gcm_128[0x1];
984 u8 tls_1_2_aes_gcm_256[0x1];
985 u8 tls_1_3_aes_gcm_256[0x1];
986 u8 reserved_at_4[0x1c];
987
988 u8 reserved_at_20[0x7e0];
989};
990
e281682b
SM		 991enum {
992 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
993 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 994 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 995 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 996};
997
998enum {
999 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1000 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1001};
1002
1003enum {
1004 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1005 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1006 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1007 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1008 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1009};
1010
1011enum {
1012 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1013 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1014 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1015 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1016 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1017 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1018};
1019
1020enum {
1021 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1022 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1023};
1024
1025enum {
1026 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1027 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1028 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1029};
1030
1031enum {
1032 MLX5_CAP_PORT_TYPE_IB = 0x0,
1033 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 1034};
1035
1410a90a
MG		 1036enum {
1037 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1038 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1039 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1040};
1041
9d43faac
YH		 1042enum {
1043 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 1044 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 1045};
1046
8536a6bf
GT		 1047#define MLX5_FC_BULK_SIZE_FACTOR 128
1048
1049enum mlx5_fc_bulk_alloc_bitmask {
1050 MLX5_FC_BULK_128 = (1 << 0),
1051 MLX5_FC_BULK_256 = (1 << 1),
1052 MLX5_FC_BULK_512 = (1 << 2),
1053 MLX5_FC_BULK_1024 = (1 << 3),
1054 MLX5_FC_BULK_2048 = (1 << 4),
1055 MLX5_FC_BULK_4096 = (1 << 5),
1056 MLX5_FC_BULK_8192 = (1 << 6),
1057 MLX5_FC_BULK_16384 = (1 << 7),
1058};
1059
1060#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1061
b775516b 1062struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 1063 u8 reserved_at_0[0x30];
1064 u8 vhca_id[0x10];
1065
1066 u8 reserved_at_40[0x40];
b775516b
EC		 1067
1068 u8 log_max_srq_sz[0x8];
1069 u8 log_max_qp_sz[0x8];
b9a7ba55
YH		 1070 u8 event_cap[0x1];
1071 u8 reserved_at_91[0x7];
316793fb
EB		 1072 u8 prio_tag_required[0x1];
1073 u8 reserved_at_99[0x2];
b775516b
EC		 1074 u8 log_max_qp[0x5];
1075
b4ff3a36 1076 u8 reserved_at_a0[0xb];
e281682b 1077 u8 log_max_srq[0x5];
b4ff3a36 1078 u8 reserved_at_b0[0x10];
b775516b 1079
b4ff3a36 1080 u8 reserved_at_c0[0x8];
b775516b 1081 u8 log_max_cq_sz[0x8];
b4ff3a36 1082 u8 reserved_at_d0[0xb];
b775516b
EC		 1083 u8 log_max_cq[0x5];
1084
1085 u8 log_max_eq_sz[0x8];
b4ff3a36 1086 u8 reserved_at_e8[0x2];
b775516b 1087 u8 log_max_mkey[0x6];
b183ee27
LR		 1088 u8 reserved_at_f0[0x8];
1089 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 1090 u8 reserved_at_f9[0x2];
1091 u8 fast_teardown[0x1];
b775516b
EC		 1092 u8 log_max_eq[0x4];
1093
1094 u8 max_indirection[0x8];
bcda1aca 1095 u8 fixed_buffer_size[0x1];
b775516b 1096 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 1097 u8 force_teardown[0x1];
1098 u8 reserved_at_111[0x1];
b775516b 1099 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 1100 u8 umr_extended_translation_offset[0x1];
1101 u8 null_mkey[0x1];
b775516b
EC		 1102 u8 log_max_klm_list_size[0x6];
1103
b4ff3a36 1104 u8 reserved_at_120[0xa];
b775516b 1105 u8 log_max_ra_req_dc[0x6];
b4ff3a36 1106 u8 reserved_at_130[0xa];
b775516b
EC		 1107 u8 log_max_ra_res_dc[0x6];
1108
b4ff3a36 1109 u8 reserved_at_140[0xa];
b775516b 1110 u8 log_max_ra_req_qp[0x6];
b4ff3a36 1111 u8 reserved_at_150[0xa];
b775516b
EC		 1112 u8 log_max_ra_res_qp[0x6];
1113
f32f5bd2 1114 u8 end_pad[0x1];
b775516b
EC		 1115 u8 cc_query_allowed[0x1];
1116 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 1117 u8 start_pad[0x1];
1118 u8 cache_line_128byte[0x1];
f8efee08
MZ		 1119 u8 reserved_at_165[0x4];
1120 u8 rts2rts_qp_counters_set_id[0x1];
30b10e89
MS		 1121 u8 reserved_at_16a[0x2];
1122 u8 vnic_env_int_rq_oob[0x1];
1123 u8 reserved_at_16d[0x2];
c02762eb 1124 u8 qcam_reg[0x1];
e281682b 1125 u8 gid_table_size[0x10];
b775516b 1126
e281682b
SM		 1127 u8 out_of_seq_cnt[0x1];
1128 u8 vport_counters[0x1];
7486216b 1129 u8 retransmission_q_counters[0x1];
2fcb12df 1130 u8 debug[0x1];
83b502a1 1131 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1132 u8 rq_delay_drop[0x1];
b775516b
EC		 1133 u8 max_qp_cnt[0xa];
1134 u8 pkey_table_size[0x10];
1135
e281682b
SM		 1136 u8 vport_group_manager[0x1];
1137 u8 vhca_group_manager[0x1];
1138 u8 ib_virt[0x1];
1139 u8 eth_virt[0x1];
61c5b5c9 1140 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1141 u8 ets[0x1];
1142 u8 nic_flow_table[0x1];
0efc8562 1143 u8 eswitch_manager[0x1];
e72bd817 1144 u8 device_memory[0x1];
cfdcbcea
GP		 1145 u8 mcam_reg[0x1];
1146 u8 pcam_reg[0x1];
b775516b 1147 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1148 u8 port_module_event[0x1];
58dcb60a 1149 u8 enhanced_error_q_counters[0x1];
7d5e1423 1150 u8 ports_check[0x1];
7b13558f 1151 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1152 u8 disable_link_up[0x1];
1153 u8 beacon_led[0x1];
e281682b 1154 u8 port_type[0x2];
b775516b
EC		 1155 u8 num_ports[0x8];
1156
f9a1ef72
EE		 1157 u8 reserved_at_1c0[0x1];
1158 u8 pps[0x1];
1159 u8 pps_modify[0x1];
b775516b 1160 u8 log_max_msg[0x5];
e1c9c62b 1161 u8 reserved_at_1c8[0x4];
4f3961ee 1162 u8 max_tc[0x4];
1865ea9a 1163 u8 temp_warn_event[0x1];
7486216b 1164 u8 dcbx[0x1];
246ac981
MG		 1165 u8 general_notification_event[0x1];
1166 u8 reserved_at_1d3[0x2];
e29341fb 1167 u8 fpga[0x1];
928cfe87
TT		 1168 u8 rol_s[0x1];
1169 u8 rol_g[0x1];
e1c9c62b 1170 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1171 u8 wol_s[0x1];
1172 u8 wol_g[0x1];
1173 u8 wol_a[0x1];
1174 u8 wol_b[0x1];
1175 u8 wol_m[0x1];
1176 u8 wol_u[0x1];
1177 u8 wol_p[0x1];
b775516b
EC		 1178
1179 u8 stat_rate_support[0x10];
e1c9c62b 1180 u8 reserved_at_1f0[0xc];
e281682b 1181 u8 cqe_version[0x4];
b775516b 1182
e281682b 1183 u8 compact_address_vector[0x1];
7d5e1423 1184 u8 striding_rq[0x1];
500a3d0d
ES		 1185 u8 reserved_at_202[0x1];
1186 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1187 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1188 u8 reserved_at_205[0x1];
1189 u8 repeated_block_disabled[0x1];
1190 u8 umr_modify_entity_size_disabled[0x1];
1191 u8 umr_modify_atomic_disabled[0x1];
1192 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1193 u8 umr_fence[0x2];
94a04d1d
YC		 1194 u8 dc_req_scat_data_cqe[0x1];
1195 u8 reserved_at_20d[0x2];
e281682b 1196 u8 drain_sigerr[0x1];
b775516b
EC		 1197 u8 cmdif_checksum[0x2];
1198 u8 sigerr_cqe[0x1];
e1c9c62b 1199 u8 reserved_at_213[0x1];
b775516b
EC		 1200 u8 wq_signature[0x1];
1201 u8 sctr_data_cqe[0x1];
e1c9c62b 1202 u8 reserved_at_216[0x1];
b775516b
EC		 1203 u8 sho[0x1];
1204 u8 tph[0x1];
1205 u8 rf[0x1];
e281682b 1206 u8 dct[0x1];
7486216b 1207 u8 qos[0x1];
e281682b 1208 u8 eth_net_offloads[0x1];
b775516b
EC		 1209 u8 roce[0x1];
1210 u8 atomic[0x1];
e1c9c62b 1211 u8 reserved_at_21f[0x1];
b775516b
EC		 1212
1213 u8 cq_oi[0x1];
1214 u8 cq_resize[0x1];
1215 u8 cq_moderation[0x1];
e1c9c62b 1216 u8 reserved_at_223[0x3];
e281682b 1217 u8 cq_eq_remap[0x1];
b775516b
EC		 1218 u8 pg[0x1];
1219 u8 block_lb_mc[0x1];
e1c9c62b 1220 u8 reserved_at_229[0x1];
e281682b 1221 u8 scqe_break_moderation[0x1];
7d5e1423 1222 u8 cq_period_start_from_cqe[0x1];
b775516b 1223 u8 cd[0x1];
e1c9c62b 1224 u8 reserved_at_22d[0x1];
b775516b 1225 u8 apm[0x1];
3f0393a5 1226 u8 vector_calc[0x1];
7d5e1423 1227 u8 umr_ptr_rlky[0x1];
d2370e0a 1228 u8 imaicl[0x1];
3fd3c80a
DG		 1229 u8 qp_packet_based[0x1];
1230 u8 reserved_at_233[0x3];
b775516b
EC		 1231 u8 qkv[0x1];
1232 u8 pkv[0x1];
b11a4f9c
HE		 1233 u8 set_deth_sqpn[0x1];
1234 u8 reserved_at_239[0x3];
b775516b
EC		 1235 u8 xrc[0x1];
1236 u8 ud[0x1];
1237 u8 uc[0x1];
1238 u8 rc[0x1];
1239
a6d51b68
EC		 1240 u8 uar_4k[0x1];
1241 u8 reserved_at_241[0x9];
b775516b 1242 u8 uar_sz[0x6];
e1c9c62b 1243 u8 reserved_at_250[0x8];
b775516b
EC		 1244 u8 log_pg_sz[0x8];
1245
1246 u8 bf[0x1];
0dbc6fe0 1247 u8 driver_version[0x1];
e281682b 1248 u8 pad_tx_eth_packet[0x1];
e1c9c62b 1249 u8 reserved_at_263[0x8];
b775516b 1250 u8 log_bf_reg_size[0x5];
84df61eb
AH		 1251
1252 u8 reserved_at_270[0xb];
1253 u8 lag_master[0x1];
1254 u8 num_lag_ports[0x4];
b775516b 1255
e1c9c62b 1256 u8 reserved_at_280[0x10];
b775516b
EC		 1257 u8 max_wqe_sz_sq[0x10];
1258
e1c9c62b 1259 u8 reserved_at_2a0[0x10];
b775516b
EC		 1260 u8 max_wqe_sz_rq[0x10];
1261
a8ffcc74 1262 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1263 u8 max_wqe_sz_sq_dc[0x10];
1264
e1c9c62b 1265 u8 reserved_at_2e0[0x7];
b775516b
EC		 1266 u8 max_qp_mcg[0x19];
1267
8536a6bf
GT		 1268 u8 reserved_at_300[0x10];
1269 u8 flow_counter_bulk_alloc[0x8];
b775516b
EC		 1270 u8 log_max_mcg[0x8];
1271
e1c9c62b 1272 u8 reserved_at_320[0x3];
e281682b 1273 u8 log_max_transport_domain[0x5];
e1c9c62b 1274 u8 reserved_at_328[0x3];
b775516b 1275 u8 log_max_pd[0x5];
e1c9c62b 1276 u8 reserved_at_330[0xb];
b775516b
EC		 1277 u8 log_max_xrcd[0x5];
1278
5c298143 1279 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1280 u8 receive_discard_vport_down[0x1];
1281 u8 transmit_discard_vport_down[0x1];
1282 u8 reserved_at_343[0x5];
a351a1b0 1283 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1284 u8 max_flow_counter_15_0[0x10];
a351a1b0 1285
b775516b 1286
e1c9c62b 1287 u8 reserved_at_360[0x3];
b775516b 1288 u8 log_max_rq[0x5];
e1c9c62b 1289 u8 reserved_at_368[0x3];
b775516b 1290 u8 log_max_sq[0x5];
e1c9c62b 1291 u8 reserved_at_370[0x3];
b775516b 1292 u8 log_max_tir[0x5];
e1c9c62b 1293 u8 reserved_at_378[0x3];
b775516b
EC		 1294 u8 log_max_tis[0x5];
1295
e281682b 1296 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1297 u8 reserved_at_381[0x2];
e281682b 1298 u8 log_max_rmp[0x5];
e1c9c62b 1299 u8 reserved_at_388[0x3];
e281682b 1300 u8 log_max_rqt[0x5];
e1c9c62b 1301 u8 reserved_at_390[0x3];
e281682b 1302 u8 log_max_rqt_size[0x5];
e1c9c62b 1303 u8 reserved_at_398[0x3];
b775516b
EC		 1304 u8 log_max_tis_per_sq[0x5];
1305
619a8f2a
TT		 1306 u8 ext_stride_num_range[0x1];
1307 u8 reserved_at_3a1[0x2];
e281682b 1308 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1309 u8 reserved_at_3a8[0x3];
e281682b 1310 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1311 u8 reserved_at_3b0[0x3];
e281682b 1312 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1313 u8 reserved_at_3b8[0x3];
e281682b
SM		 1314 u8 log_min_stride_sz_sq[0x5];
1315
40817cdb
OG		 1316 u8 hairpin[0x1];
1317 u8 reserved_at_3c1[0x2];
1318 u8 log_max_hairpin_queues[0x5];
1319 u8 reserved_at_3c8[0x3];
1320 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1321 u8 reserved_at_3d0[0x3];
1322 u8 log_max_hairpin_num_packets[0x5];
1323 u8 reserved_at_3d8[0x3];
e281682b
SM		 1324 u8 log_max_wq_sz[0x5];
1325
54f0a411 1326 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1327 u8 disable_local_lb_uc[0x1];
1328 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1329 u8 log_min_hairpin_wq_data_sz[0x5];
1330 u8 reserved_at_3e8[0x3];
54f0a411 1331 u8 log_max_vlan_list[0x5];
e1c9c62b 1332 u8 reserved_at_3f0[0x3];
54f0a411 1333 u8 log_max_current_mc_list[0x5];
e1c9c62b 1334 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1335 u8 log_max_current_uc_list[0x5];
1336
38b7ca92
YH		 1337 u8 general_obj_types[0x40];
1338
342ac844
DD		 1339 u8 reserved_at_440[0x20];
1340
a12ff35e
EBE		 1341 u8 tls[0x1];
1342 u8 reserved_at_461[0x2];
6e3722ba
YH		 1343 u8 log_max_uctx[0x5];
1344 u8 reserved_at_468[0x3];
1345 u8 log_max_umem[0x5];
342ac844 1346 u8 max_num_eqs[0x10];
54f0a411 1347
e1c9c62b 1348 u8 reserved_at_480[0x3];
e281682b 1349 u8 log_max_l2_table[0x5];
e1c9c62b 1350 u8 reserved_at_488[0x8];
b775516b
EC		 1351 u8 log_uar_page_sz[0x10];
1352
e1c9c62b 1353 u8 reserved_at_4a0[0x20];
048ccca8 1354 u8 device_frequency_mhz[0x20];
b0844444 1355 u8 device_frequency_khz[0x20];
e1c9c62b 1356
a6d51b68
EC		 1357 u8 reserved_at_500[0x20];
1358 u8 num_of_uars_per_page[0x20];
e1c9c62b 1359
e818e255 1360 u8 flex_parser_protocols[0x20];
e1c9c62b 1361
b169e64a
YK		 1362 u8 max_geneve_tlv_options[0x8];
1363 u8 reserved_at_568[0x3];
1364 u8 max_geneve_tlv_option_data_len[0x5];
1365 u8 reserved_at_570[0x10];
e1c9c62b 1366
a12ff35e
EBE		 1367 u8 reserved_at_580[0x33];
1368 u8 log_max_dek[0x5];
1369 u8 reserved_at_5b8[0x4];
ab741b2e 1370 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1371 u8 cqe_128_always[0x1];
1372 u8 cqe_compression_128[0x1];
7d5e1423 1373 u8 cqe_compression[0x1];
b775516b 1374
7d5e1423
SM		 1375 u8 cqe_compression_timeout[0x10];
1376 u8 cqe_compression_max_num[0x10];
b775516b 1377
7486216b
SM		 1378 u8 reserved_at_5e0[0x10];
1379 u8 tag_matching[0x1];
1380 u8 rndv_offload_rc[0x1];
1381 u8 rndv_offload_dc[0x1];
1382 u8 log_tag_matching_list_sz[0x5];
7b13558f 1383 u8 reserved_at_5f8[0x3];
7486216b
SM		 1384 u8 log_max_xrq[0x5];
1385
32f69e4b
DJ		 1386 u8 affiliate_nic_vport_criteria[0x8];
1387 u8 native_port_num[0x8];
1388 u8 num_vhca_ports[0x8];
1389 u8 reserved_at_618[0x6];
1390 u8 sw_owner_id[0x1];
9d43faac
YH		 1391 u8 reserved_at_61f[0x1];
1392
fd4572b3
ED		 1393 u8 max_num_of_monitor_counters[0x10];
1394 u8 num_ppcnt_monitor_counters[0x10];
1395
1396 u8 reserved_at_640[0x10];
1397 u8 num_q_monitor_counters[0x10];
1398
1759d322
PP		 1399 u8 reserved_at_660[0x20];
1400
1401 u8 sf[0x1];
1402 u8 sf_set_partition[0x1];
1403 u8 reserved_at_682[0x1];
1404 u8 log_max_sf[0x5];
1405 u8 reserved_at_688[0x8];
1406 u8 log_min_sf_size[0x8];
1407 u8 max_num_sf_partitions[0x8];
9d43faac
YH		 1408
1409 u8 uctx_cap[0x20];
1410
b169e64a
YK		 1411 u8 reserved_at_6c0[0x4];
1412 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1759d322
PP		 1413 u8 reserved_at_6c8[0x28];
1414 u8 sf_base_id[0x10];
1415
1dd7382b
MG		 1416 u8 reserved_at_700[0x80];
1417 u8 vhca_tunnel_commands[0x40];
1418 u8 reserved_at_7c0[0x40];
b775516b
EC		 1419};
1420
81848731
SM		 1421enum mlx5_flow_destination_type {
1422 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1423 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1424 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1425
5f418378 1426 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1427 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
664000b6 1428 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
e281682b 1429};
b775516b 1430
f6f7d6b5
MG		 1431enum mlx5_flow_table_miss_action {
1432 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1433 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1434 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1435};
1436
e281682b
SM		 1437struct mlx5_ifc_dest_format_struct_bits {
1438 u8 destination_type[0x8];
1439 u8 destination_id[0x18];
1b115498 1440
b17f7fc1 1441 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1442 u8 packet_reformat[0x1];
1443 u8 reserved_at_22[0xe];
b17f7fc1 1444 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1445};
1446
9dc0b289 1447struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1448 u8 flow_counter_id[0x20];
9dc0b289
AV		 1449
1450 u8 reserved_at_20[0x20];
1451};
1452
1b115498
EB		 1453struct mlx5_ifc_extended_dest_format_bits {
1454 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1455
1456 u8 packet_reformat_id[0x20];
1457
1458 u8 reserved_at_60[0x20];
1459};
1460
9dc0b289
AV		 1461union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1462 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1463 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1464 u8 reserved_at_0[0x40];
1465};
1466
e281682b
SM		 1467struct mlx5_ifc_fte_match_param_bits {
1468 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1469
1470 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1471
1472 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1473
71c6e863
AL		 1474 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1475
b169e64a
YK		 1476 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1477
1478 u8 reserved_at_a00[0x600];
b775516b
EC		 1479};
1480
e281682b
SM		 1481enum {
1482 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1483 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1484 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1485 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1486 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1487};
b775516b 1488
e281682b
SM		 1489struct mlx5_ifc_rx_hash_field_select_bits {
1490 u8 l3_prot_type[0x1];
1491 u8 l4_prot_type[0x1];
1492 u8 selected_fields[0x1e];
1493};
b775516b 1494
e281682b
SM		 1495enum {
1496 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1497 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1498};
1499
e281682b
SM		 1500enum {
1501 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1502 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1503};
1504
1505struct mlx5_ifc_wq_bits {
1506 u8 wq_type[0x4];
1507 u8 wq_signature[0x1];
1508 u8 end_padding_mode[0x2];
1509 u8 cd_slave[0x1];
b4ff3a36 1510 u8 reserved_at_8[0x18];
b775516b 1511
e281682b
SM		 1512 u8 hds_skip_first_sge[0x1];
1513 u8 log2_hds_buf_size[0x3];
b4ff3a36 1514 u8 reserved_at_24[0x7];
e281682b
SM		 1515 u8 page_offset[0x5];
1516 u8 lwm[0x10];
b775516b 1517
b4ff3a36 1518 u8 reserved_at_40[0x8];
e281682b
SM		 1519 u8 pd[0x18];
1520
b4ff3a36 1521 u8 reserved_at_60[0x8];
e281682b
SM		 1522 u8 uar_page[0x18];
1523
1524 u8 dbr_addr[0x40];
1525
1526 u8 hw_counter[0x20];
1527
1528 u8 sw_counter[0x20];
1529
b4ff3a36 1530 u8 reserved_at_100[0xc];
e281682b 1531 u8 log_wq_stride[0x4];
b4ff3a36 1532 u8 reserved_at_110[0x3];
e281682b 1533 u8 log_wq_pg_sz[0x5];
b4ff3a36 1534 u8 reserved_at_118[0x3];
e281682b
SM		 1535 u8 log_wq_sz[0x5];
1536
bd371975
LR		 1537 u8 dbr_umem_valid[0x1];
1538 u8 wq_umem_valid[0x1];
1539 u8 reserved_at_122[0x1];
4d533e0f
OG		 1540 u8 log_hairpin_num_packets[0x5];
1541 u8 reserved_at_128[0x3];
40817cdb 1542 u8 log_hairpin_data_sz[0x5];
40817cdb 1543
619a8f2a
TT		 1544 u8 reserved_at_130[0x4];
1545 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1546 u8 two_byte_shift_en[0x1];
1547 u8 reserved_at_139[0x4];
1548 u8 log_wqe_stride_size[0x3];
1549
1550 u8 reserved_at_140[0x4c0];
b775516b 1551
e281682b 1552 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1553};
1554
e281682b 1555struct mlx5_ifc_rq_num_bits {
b4ff3a36 1556 u8 reserved_at_0[0x8];
e281682b
SM		 1557 u8 rq_num[0x18];
1558};
b775516b 1559
e281682b 1560struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1561 u8 reserved_at_0[0x10];
e281682b 1562 u8 mac_addr_47_32[0x10];
b775516b 1563
e281682b
SM		 1564 u8 mac_addr_31_0[0x20];
1565};
1566
c0046cf7 1567struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1568 u8 reserved_at_0[0x14];
c0046cf7
SM		 1569 u8 vlan[0x0c];
1570
b4ff3a36 1571 u8 reserved_at_20[0x20];
c0046cf7
SM		 1572};
1573
e281682b 1574struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1575 u8 reserved_at_0[0xa0];
e281682b
SM		 1576
1577 u8 min_time_between_cnps[0x20];
1578
b4ff3a36 1579 u8 reserved_at_c0[0x12];
e281682b 1580 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1581 u8 reserved_at_d8[0x4];
1582 u8 cnp_prio_mode[0x1];
e281682b
SM		 1583 u8 cnp_802p_prio[0x3];
1584
b4ff3a36 1585 u8 reserved_at_e0[0x720];
e281682b
SM		 1586};
1587
1588struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1589 u8 reserved_at_0[0x60];
e281682b 1590
b4ff3a36 1591 u8 reserved_at_60[0x4];
e281682b 1592 u8 clamp_tgt_rate[0x1];
b4ff3a36 1593 u8 reserved_at_65[0x3];
e281682b 1594 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1595 u8 reserved_at_69[0x17];
e281682b 1596
b4ff3a36 1597 u8 reserved_at_80[0x20];
e281682b
SM		 1598
1599 u8 rpg_time_reset[0x20];
1600
1601 u8 rpg_byte_reset[0x20];
1602
1603 u8 rpg_threshold[0x20];
1604
1605 u8 rpg_max_rate[0x20];
1606
1607 u8 rpg_ai_rate[0x20];
1608
1609 u8 rpg_hai_rate[0x20];
1610
1611 u8 rpg_gd[0x20];
1612
1613 u8 rpg_min_dec_fac[0x20];
1614
1615 u8 rpg_min_rate[0x20];
1616
b4ff3a36 1617 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1618
1619 u8 rate_to_set_on_first_cnp[0x20];
1620
1621 u8 dce_tcp_g[0x20];
1622
1623 u8 dce_tcp_rtt[0x20];
1624
1625 u8 rate_reduce_monitor_period[0x20];
1626
b4ff3a36 1627 u8 reserved_at_320[0x20];
e281682b
SM		 1628
1629 u8 initial_alpha_value[0x20];
1630
b4ff3a36 1631 u8 reserved_at_360[0x4a0];
e281682b
SM		 1632};
1633
1634struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1635 u8 reserved_at_0[0x80];
e281682b
SM		 1636
1637 u8 rppp_max_rps[0x20];
1638
1639 u8 rpg_time_reset[0x20];
1640
1641 u8 rpg_byte_reset[0x20];
1642
1643 u8 rpg_threshold[0x20];
1644
1645 u8 rpg_max_rate[0x20];
1646
1647 u8 rpg_ai_rate[0x20];
1648
1649 u8 rpg_hai_rate[0x20];
1650
1651 u8 rpg_gd[0x20];
1652
1653 u8 rpg_min_dec_fac[0x20];
1654
1655 u8 rpg_min_rate[0x20];
1656
b4ff3a36 1657 u8 reserved_at_1c0[0x640];
e281682b
SM		 1658};
1659
1660enum {
1661 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1662 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1663 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1664};
1665
1666struct mlx5_ifc_resize_field_select_bits {
1667 u8 resize_field_select[0x20];
1668};
1669
1670enum {
1671 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1672 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1673 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1674 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1675};
1676
1677struct mlx5_ifc_modify_field_select_bits {
1678 u8 modify_field_select[0x20];
1679};
1680
1681struct mlx5_ifc_field_select_r_roce_np_bits {
1682 u8 field_select_r_roce_np[0x20];
1683};
1684
1685struct mlx5_ifc_field_select_r_roce_rp_bits {
1686 u8 field_select_r_roce_rp[0x20];
1687};
1688
1689enum {
1690 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1691 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1692 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1693 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1694 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1695 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1696 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1697 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1698 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1699 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1700};
1701
1702struct mlx5_ifc_field_select_802_1qau_rp_bits {
1703 u8 field_select_8021qaurp[0x20];
1704};
1705
1706struct mlx5_ifc_phys_layer_cntrs_bits {
1707 u8 time_since_last_clear_high[0x20];
1708
1709 u8 time_since_last_clear_low[0x20];
1710
1711 u8 symbol_errors_high[0x20];
1712
1713 u8 symbol_errors_low[0x20];
1714
1715 u8 sync_headers_errors_high[0x20];
1716
1717 u8 sync_headers_errors_low[0x20];
1718
1719 u8 edpl_bip_errors_lane0_high[0x20];
1720
1721 u8 edpl_bip_errors_lane0_low[0x20];
1722
1723 u8 edpl_bip_errors_lane1_high[0x20];
1724
1725 u8 edpl_bip_errors_lane1_low[0x20];
1726
1727 u8 edpl_bip_errors_lane2_high[0x20];
1728
1729 u8 edpl_bip_errors_lane2_low[0x20];
1730
1731 u8 edpl_bip_errors_lane3_high[0x20];
1732
1733 u8 edpl_bip_errors_lane3_low[0x20];
1734
1735 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1736
1737 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1738
1739 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1740
1741 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1742
1743 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1744
1745 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1746
1747 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1748
1749 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1750
1751 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1752
1753 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1754
1755 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1756
1757 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1758
1759 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1760
1761 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1762
1763 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1764
1765 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1766
1767 u8 rs_fec_corrected_blocks_high[0x20];
1768
1769 u8 rs_fec_corrected_blocks_low[0x20];
1770
1771 u8 rs_fec_uncorrectable_blocks_high[0x20];
1772
1773 u8 rs_fec_uncorrectable_blocks_low[0x20];
1774
1775 u8 rs_fec_no_errors_blocks_high[0x20];
1776
1777 u8 rs_fec_no_errors_blocks_low[0x20];
1778
1779 u8 rs_fec_single_error_blocks_high[0x20];
1780
1781 u8 rs_fec_single_error_blocks_low[0x20];
1782
1783 u8 rs_fec_corrected_symbols_total_high[0x20];
1784
1785 u8 rs_fec_corrected_symbols_total_low[0x20];
1786
1787 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1788
1789 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1790
1791 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1792
1793 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1794
1795 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1796
1797 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1798
1799 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1800
1801 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1802
1803 u8 link_down_events[0x20];
1804
1805 u8 successful_recovery_events[0x20];
1806
b4ff3a36 1807 u8 reserved_at_640[0x180];
e281682b
SM		 1808};
1809
d8dc0508
GP		 1810struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1811 u8 time_since_last_clear_high[0x20];
1812
1813 u8 time_since_last_clear_low[0x20];
1814
1815 u8 phy_received_bits_high[0x20];
1816
1817 u8 phy_received_bits_low[0x20];
1818
1819 u8 phy_symbol_errors_high[0x20];
1820
1821 u8 phy_symbol_errors_low[0x20];
1822
1823 u8 phy_corrected_bits_high[0x20];
1824
1825 u8 phy_corrected_bits_low[0x20];
1826
1827 u8 phy_corrected_bits_lane0_high[0x20];
1828
1829 u8 phy_corrected_bits_lane0_low[0x20];
1830
1831 u8 phy_corrected_bits_lane1_high[0x20];
1832
1833 u8 phy_corrected_bits_lane1_low[0x20];
1834
1835 u8 phy_corrected_bits_lane2_high[0x20];
1836
1837 u8 phy_corrected_bits_lane2_low[0x20];
1838
1839 u8 phy_corrected_bits_lane3_high[0x20];
1840
1841 u8 phy_corrected_bits_lane3_low[0x20];
1842
1843 u8 reserved_at_200[0x5c0];
1844};
1845
1c64bf6f
MY		 1846struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1847 u8 symbol_error_counter[0x10];
1848
1849 u8 link_error_recovery_counter[0x8];
1850
1851 u8 link_downed_counter[0x8];
1852
1853 u8 port_rcv_errors[0x10];
1854
1855 u8 port_rcv_remote_physical_errors[0x10];
1856
1857 u8 port_rcv_switch_relay_errors[0x10];
1858
1859 u8 port_xmit_discards[0x10];
1860
1861 u8 port_xmit_constraint_errors[0x8];
1862
1863 u8 port_rcv_constraint_errors[0x8];
1864
1865 u8 reserved_at_70[0x8];
1866
1867 u8 link_overrun_errors[0x8];
1868
1869 u8 reserved_at_80[0x10];
1870
1871 u8 vl_15_dropped[0x10];
1872
133bea04
TW		 1873 u8 reserved_at_a0[0x80];
1874
1875 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1876};
1877
e281682b
SM		 1878struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1879 u8 transmit_queue_high[0x20];
1880
1881 u8 transmit_queue_low[0x20];
1882
b4ff3a36 1883 u8 reserved_at_40[0x780];
e281682b
SM		 1884};
1885
1886struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1887 u8 rx_octets_high[0x20];
1888
1889 u8 rx_octets_low[0x20];
1890
b4ff3a36 1891 u8 reserved_at_40[0xc0];
e281682b
SM		 1892
1893 u8 rx_frames_high[0x20];
1894
1895 u8 rx_frames_low[0x20];
1896
1897 u8 tx_octets_high[0x20];
1898
1899 u8 tx_octets_low[0x20];
1900
b4ff3a36 1901 u8 reserved_at_180[0xc0];
e281682b
SM		 1902
1903 u8 tx_frames_high[0x20];
1904
1905 u8 tx_frames_low[0x20];
1906
1907 u8 rx_pause_high[0x20];
1908
1909 u8 rx_pause_low[0x20];
1910
1911 u8 rx_pause_duration_high[0x20];
1912
1913 u8 rx_pause_duration_low[0x20];
1914
1915 u8 tx_pause_high[0x20];
1916
1917 u8 tx_pause_low[0x20];
1918
1919 u8 tx_pause_duration_high[0x20];
1920
1921 u8 tx_pause_duration_low[0x20];
1922
1923 u8 rx_pause_transition_high[0x20];
1924
1925 u8 rx_pause_transition_low[0x20];
1926
2fcb12df
IK		 1927 u8 reserved_at_3c0[0x40];
1928
1929 u8 device_stall_minor_watermark_cnt_high[0x20];
1930
1931 u8 device_stall_minor_watermark_cnt_low[0x20];
1932
1933 u8 device_stall_critical_watermark_cnt_high[0x20];
1934
1935 u8 device_stall_critical_watermark_cnt_low[0x20];
1936
1937 u8 reserved_at_480[0x340];
e281682b
SM		 1938};
1939
1940struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1941 u8 port_transmit_wait_high[0x20];
1942
1943 u8 port_transmit_wait_low[0x20];
1944
2dba0797
GP		 1945 u8 reserved_at_40[0x100];
1946
1947 u8 rx_buffer_almost_full_high[0x20];
1948
1949 u8 rx_buffer_almost_full_low[0x20];
1950
1951 u8 rx_buffer_full_high[0x20];
1952
1953 u8 rx_buffer_full_low[0x20];
1954
0af5107c
TB		 1955 u8 rx_icrc_encapsulated_high[0x20];
1956
1957 u8 rx_icrc_encapsulated_low[0x20];
1958
1959 u8 reserved_at_200[0x5c0];
e281682b
SM		 1960};
1961
1962struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1963 u8 dot3stats_alignment_errors_high[0x20];
1964
1965 u8 dot3stats_alignment_errors_low[0x20];
1966
1967 u8 dot3stats_fcs_errors_high[0x20];
1968
1969 u8 dot3stats_fcs_errors_low[0x20];
1970
1971 u8 dot3stats_single_collision_frames_high[0x20];
1972
1973 u8 dot3stats_single_collision_frames_low[0x20];
1974
1975 u8 dot3stats_multiple_collision_frames_high[0x20];
1976
1977 u8 dot3stats_multiple_collision_frames_low[0x20];
1978
1979 u8 dot3stats_sqe_test_errors_high[0x20];
1980
1981 u8 dot3stats_sqe_test_errors_low[0x20];
1982
1983 u8 dot3stats_deferred_transmissions_high[0x20];
1984
1985 u8 dot3stats_deferred_transmissions_low[0x20];
1986
1987 u8 dot3stats_late_collisions_high[0x20];
1988
1989 u8 dot3stats_late_collisions_low[0x20];
1990
1991 u8 dot3stats_excessive_collisions_high[0x20];
1992
1993 u8 dot3stats_excessive_collisions_low[0x20];
1994
1995 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1996
1997 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1998
1999 u8 dot3stats_carrier_sense_errors_high[0x20];
2000
2001 u8 dot3stats_carrier_sense_errors_low[0x20];
2002
2003 u8 dot3stats_frame_too_longs_high[0x20];
2004
2005 u8 dot3stats_frame_too_longs_low[0x20];
2006
2007 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2008
2009 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2010
2011 u8 dot3stats_symbol_errors_high[0x20];
2012
2013 u8 dot3stats_symbol_errors_low[0x20];
2014
2015 u8 dot3control_in_unknown_opcodes_high[0x20];
2016
2017 u8 dot3control_in_unknown_opcodes_low[0x20];
2018
2019 u8 dot3in_pause_frames_high[0x20];
2020
2021 u8 dot3in_pause_frames_low[0x20];
2022
2023 u8 dot3out_pause_frames_high[0x20];
2024
2025 u8 dot3out_pause_frames_low[0x20];
2026
b4ff3a36 2027 u8 reserved_at_400[0x3c0];
e281682b
SM		 2028};
2029
2030struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2031 u8 ether_stats_drop_events_high[0x20];
2032
2033 u8 ether_stats_drop_events_low[0x20];
2034
2035 u8 ether_stats_octets_high[0x20];
2036
2037 u8 ether_stats_octets_low[0x20];
2038
2039 u8 ether_stats_pkts_high[0x20];
2040
2041 u8 ether_stats_pkts_low[0x20];
2042
2043 u8 ether_stats_broadcast_pkts_high[0x20];
2044
2045 u8 ether_stats_broadcast_pkts_low[0x20];
2046
2047 u8 ether_stats_multicast_pkts_high[0x20];
2048
2049 u8 ether_stats_multicast_pkts_low[0x20];
2050
2051 u8 ether_stats_crc_align_errors_high[0x20];
2052
2053 u8 ether_stats_crc_align_errors_low[0x20];
2054
2055 u8 ether_stats_undersize_pkts_high[0x20];
2056
2057 u8 ether_stats_undersize_pkts_low[0x20];
2058
2059 u8 ether_stats_oversize_pkts_high[0x20];
2060
2061 u8 ether_stats_oversize_pkts_low[0x20];
2062
2063 u8 ether_stats_fragments_high[0x20];
2064
2065 u8 ether_stats_fragments_low[0x20];
2066
2067 u8 ether_stats_jabbers_high[0x20];
2068
2069 u8 ether_stats_jabbers_low[0x20];
2070
2071 u8 ether_stats_collisions_high[0x20];
2072
2073 u8 ether_stats_collisions_low[0x20];
2074
2075 u8 ether_stats_pkts64octets_high[0x20];
2076
2077 u8 ether_stats_pkts64octets_low[0x20];
2078
2079 u8 ether_stats_pkts65to127octets_high[0x20];
2080
2081 u8 ether_stats_pkts65to127octets_low[0x20];
2082
2083 u8 ether_stats_pkts128to255octets_high[0x20];
2084
2085 u8 ether_stats_pkts128to255octets_low[0x20];
2086
2087 u8 ether_stats_pkts256to511octets_high[0x20];
2088
2089 u8 ether_stats_pkts256to511octets_low[0x20];
2090
2091 u8 ether_stats_pkts512to1023octets_high[0x20];
2092
2093 u8 ether_stats_pkts512to1023octets_low[0x20];
2094
2095 u8 ether_stats_pkts1024to1518octets_high[0x20];
2096
2097 u8 ether_stats_pkts1024to1518octets_low[0x20];
2098
2099 u8 ether_stats_pkts1519to2047octets_high[0x20];
2100
2101 u8 ether_stats_pkts1519to2047octets_low[0x20];
2102
2103 u8 ether_stats_pkts2048to4095octets_high[0x20];
2104
2105 u8 ether_stats_pkts2048to4095octets_low[0x20];
2106
2107 u8 ether_stats_pkts4096to8191octets_high[0x20];
2108
2109 u8 ether_stats_pkts4096to8191octets_low[0x20];
2110
2111 u8 ether_stats_pkts8192to10239octets_high[0x20];
2112
2113 u8 ether_stats_pkts8192to10239octets_low[0x20];
2114
b4ff3a36 2115 u8 reserved_at_540[0x280];
e281682b
SM		 2116};
2117
2118struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2119 u8 if_in_octets_high[0x20];
2120
2121 u8 if_in_octets_low[0x20];
2122
2123 u8 if_in_ucast_pkts_high[0x20];
2124
2125 u8 if_in_ucast_pkts_low[0x20];
2126
2127 u8 if_in_discards_high[0x20];
2128
2129 u8 if_in_discards_low[0x20];
2130
2131 u8 if_in_errors_high[0x20];
2132
2133 u8 if_in_errors_low[0x20];
2134
2135 u8 if_in_unknown_protos_high[0x20];
2136
2137 u8 if_in_unknown_protos_low[0x20];
2138
2139 u8 if_out_octets_high[0x20];
2140
2141 u8 if_out_octets_low[0x20];
2142
2143 u8 if_out_ucast_pkts_high[0x20];
2144
2145 u8 if_out_ucast_pkts_low[0x20];
2146
2147 u8 if_out_discards_high[0x20];
2148
2149 u8 if_out_discards_low[0x20];
2150
2151 u8 if_out_errors_high[0x20];
2152
2153 u8 if_out_errors_low[0x20];
2154
2155 u8 if_in_multicast_pkts_high[0x20];
2156
2157 u8 if_in_multicast_pkts_low[0x20];
2158
2159 u8 if_in_broadcast_pkts_high[0x20];
2160
2161 u8 if_in_broadcast_pkts_low[0x20];
2162
2163 u8 if_out_multicast_pkts_high[0x20];
2164
2165 u8 if_out_multicast_pkts_low[0x20];
2166
2167 u8 if_out_broadcast_pkts_high[0x20];
2168
2169 u8 if_out_broadcast_pkts_low[0x20];
2170
b4ff3a36 2171 u8 reserved_at_340[0x480];
e281682b
SM		 2172};
2173
2174struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2175 u8 a_frames_transmitted_ok_high[0x20];
2176
2177 u8 a_frames_transmitted_ok_low[0x20];
2178
2179 u8 a_frames_received_ok_high[0x20];
2180
2181 u8 a_frames_received_ok_low[0x20];
2182
2183 u8 a_frame_check_sequence_errors_high[0x20];
2184
2185 u8 a_frame_check_sequence_errors_low[0x20];
2186
2187 u8 a_alignment_errors_high[0x20];
2188
2189 u8 a_alignment_errors_low[0x20];
2190
2191 u8 a_octets_transmitted_ok_high[0x20];
2192
2193 u8 a_octets_transmitted_ok_low[0x20];
2194
2195 u8 a_octets_received_ok_high[0x20];
2196
2197 u8 a_octets_received_ok_low[0x20];
2198
2199 u8 a_multicast_frames_xmitted_ok_high[0x20];
2200
2201 u8 a_multicast_frames_xmitted_ok_low[0x20];
2202
2203 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2204
2205 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2206
2207 u8 a_multicast_frames_received_ok_high[0x20];
2208
2209 u8 a_multicast_frames_received_ok_low[0x20];
2210
2211 u8 a_broadcast_frames_received_ok_high[0x20];
2212
2213 u8 a_broadcast_frames_received_ok_low[0x20];
2214
2215 u8 a_in_range_length_errors_high[0x20];
2216
2217 u8 a_in_range_length_errors_low[0x20];
2218
2219 u8 a_out_of_range_length_field_high[0x20];
2220
2221 u8 a_out_of_range_length_field_low[0x20];
2222
2223 u8 a_frame_too_long_errors_high[0x20];
2224
2225 u8 a_frame_too_long_errors_low[0x20];
2226
2227 u8 a_symbol_error_during_carrier_high[0x20];
2228
2229 u8 a_symbol_error_during_carrier_low[0x20];
2230
2231 u8 a_mac_control_frames_transmitted_high[0x20];
2232
2233 u8 a_mac_control_frames_transmitted_low[0x20];
2234
2235 u8 a_mac_control_frames_received_high[0x20];
2236
2237 u8 a_mac_control_frames_received_low[0x20];
2238
2239 u8 a_unsupported_opcodes_received_high[0x20];
2240
2241 u8 a_unsupported_opcodes_received_low[0x20];
2242
2243 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2244
2245 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2246
2247 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2248
2249 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2250
b4ff3a36 2251 u8 reserved_at_4c0[0x300];
e281682b
SM		 2252};
2253
8ed1a630
GP		 2254struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2255 u8 life_time_counter_high[0x20];
2256
2257 u8 life_time_counter_low[0x20];
2258
2259 u8 rx_errors[0x20];
2260
2261 u8 tx_errors[0x20];
2262
2263 u8 l0_to_recovery_eieos[0x20];
2264
2265 u8 l0_to_recovery_ts[0x20];
2266
2267 u8 l0_to_recovery_framing[0x20];
2268
2269 u8 l0_to_recovery_retrain[0x20];
2270
2271 u8 crc_error_dllp[0x20];
2272
2273 u8 crc_error_tlp[0x20];
2274
efae7f78
EBE		 2275 u8 tx_overflow_buffer_pkt_high[0x20];
2276
2277 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2278
2279 u8 outbound_stalled_reads[0x20];
2280
2281 u8 outbound_stalled_writes[0x20];
2282
2283 u8 outbound_stalled_reads_events[0x20];
2284
2285 u8 outbound_stalled_writes_events[0x20];
2286
2287 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2288};
2289
e281682b
SM		 2290struct mlx5_ifc_cmd_inter_comp_event_bits {
2291 u8 command_completion_vector[0x20];
2292
b4ff3a36 2293 u8 reserved_at_20[0xc0];
e281682b
SM		 2294};
2295
2296struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2297 u8 reserved_at_0[0x18];
e281682b 2298 u8 port_num[0x1];
b4ff3a36 2299 u8 reserved_at_19[0x3];
e281682b
SM		 2300 u8 vl[0x4];
2301
b4ff3a36 2302 u8 reserved_at_20[0xa0];
e281682b
SM		 2303};
2304
2305struct mlx5_ifc_db_bf_congestion_event_bits {
2306 u8 event_subtype[0x8];
b4ff3a36 2307 u8 reserved_at_8[0x8];
e281682b 2308 u8 congestion_level[0x8];
b4ff3a36 2309 u8 reserved_at_18[0x8];
e281682b 2310
b4ff3a36 2311 u8 reserved_at_20[0xa0];
e281682b
SM		 2312};
2313
2314struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2315 u8 reserved_at_0[0x60];
e281682b
SM		 2316
2317 u8 gpio_event_hi[0x20];
2318
2319 u8 gpio_event_lo[0x20];
2320
b4ff3a36 2321 u8 reserved_at_a0[0x40];
e281682b
SM		 2322};
2323
2324struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2325 u8 reserved_at_0[0x40];
e281682b
SM		 2326
2327 u8 port_num[0x4];
b4ff3a36 2328 u8 reserved_at_44[0x1c];
e281682b 2329
b4ff3a36 2330 u8 reserved_at_60[0x80];
e281682b
SM		 2331};
2332
2333struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2334 u8 reserved_at_0[0xe0];
e281682b
SM		 2335};
2336
2337enum {
2338 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2339 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2340};
2341
2342struct mlx5_ifc_cq_error_bits {
b4ff3a36 2343 u8 reserved_at_0[0x8];
e281682b
SM		 2344 u8 cqn[0x18];
2345
b4ff3a36 2346 u8 reserved_at_20[0x20];
e281682b 2347
b4ff3a36 2348 u8 reserved_at_40[0x18];
e281682b
SM		 2349 u8 syndrome[0x8];
2350
b4ff3a36 2351 u8 reserved_at_60[0x80];
e281682b
SM		 2352};
2353
2354struct mlx5_ifc_rdma_page_fault_event_bits {
2355 u8 bytes_committed[0x20];
2356
2357 u8 r_key[0x20];
2358
b4ff3a36 2359 u8 reserved_at_40[0x10];
e281682b
SM		 2360 u8 packet_len[0x10];
2361
2362 u8 rdma_op_len[0x20];
2363
2364 u8 rdma_va[0x40];
2365
b4ff3a36 2366 u8 reserved_at_c0[0x5];
e281682b
SM		 2367 u8 rdma[0x1];
2368 u8 write[0x1];
2369 u8 requestor[0x1];
2370 u8 qp_number[0x18];
2371};
2372
2373struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2374 u8 bytes_committed[0x20];
2375
b4ff3a36 2376 u8 reserved_at_20[0x10];
e281682b
SM		 2377 u8 wqe_index[0x10];
2378
b4ff3a36 2379 u8 reserved_at_40[0x10];
e281682b
SM		 2380 u8 len[0x10];
2381
b4ff3a36 2382 u8 reserved_at_60[0x60];
e281682b 2383
b4ff3a36 2384 u8 reserved_at_c0[0x5];
e281682b
SM		 2385 u8 rdma[0x1];
2386 u8 write_read[0x1];
2387 u8 requestor[0x1];
2388 u8 qpn[0x18];
2389};
2390
2391struct mlx5_ifc_qp_events_bits {
b4ff3a36 2392 u8 reserved_at_0[0xa0];
e281682b
SM		 2393
2394 u8 type[0x8];
b4ff3a36 2395 u8 reserved_at_a8[0x18];
e281682b 2396
b4ff3a36 2397 u8 reserved_at_c0[0x8];
e281682b
SM		 2398 u8 qpn_rqn_sqn[0x18];
2399};
2400
2401struct mlx5_ifc_dct_events_bits {
b4ff3a36 2402 u8 reserved_at_0[0xc0];
e281682b 2403
b4ff3a36 2404 u8 reserved_at_c0[0x8];
e281682b
SM		 2405 u8 dct_number[0x18];
2406};
2407
2408struct mlx5_ifc_comp_event_bits {
b4ff3a36 2409 u8 reserved_at_0[0xc0];
e281682b 2410
b4ff3a36 2411 u8 reserved_at_c0[0x8];
e281682b
SM		 2412 u8 cq_number[0x18];
2413};
2414
2415enum {
2416 MLX5_QPC_STATE_RST = 0x0,
2417 MLX5_QPC_STATE_INIT = 0x1,
2418 MLX5_QPC_STATE_RTR = 0x2,
2419 MLX5_QPC_STATE_RTS = 0x3,
2420 MLX5_QPC_STATE_SQER = 0x4,
2421 MLX5_QPC_STATE_ERR = 0x6,
2422 MLX5_QPC_STATE_SQD = 0x7,
2423 MLX5_QPC_STATE_SUSPENDED = 0x9,
2424};
2425
2426enum {
2427 MLX5_QPC_ST_RC = 0x0,
2428 MLX5_QPC_ST_UC = 0x1,
2429 MLX5_QPC_ST_UD = 0x2,
2430 MLX5_QPC_ST_XRC = 0x3,
2431 MLX5_QPC_ST_DCI = 0x5,
2432 MLX5_QPC_ST_QP0 = 0x7,
2433 MLX5_QPC_ST_QP1 = 0x8,
2434 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2435 MLX5_QPC_ST_REG_UMR = 0xc,
2436};
2437
2438enum {
2439 MLX5_QPC_PM_STATE_ARMED = 0x0,
2440 MLX5_QPC_PM_STATE_REARM = 0x1,
2441 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2442 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2443};
2444
6e44636a
AK		 2445enum {
2446 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2447};
2448
e281682b
SM		 2449enum {
2450 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2451 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2452};
2453
2454enum {
2455 MLX5_QPC_MTU_256_BYTES = 0x1,
2456 MLX5_QPC_MTU_512_BYTES = 0x2,
2457 MLX5_QPC_MTU_1K_BYTES = 0x3,
2458 MLX5_QPC_MTU_2K_BYTES = 0x4,
2459 MLX5_QPC_MTU_4K_BYTES = 0x5,
2460 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2461};
2462
2463enum {
2464 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2465 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2466 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2467 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2468 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2469 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2470 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2471 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2472};
2473
2474enum {
2475 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2476 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2477 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2478};
2479
2480enum {
2481 MLX5_QPC_CS_RES_DISABLE = 0x0,
2482 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2483 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2484};
2485
2486struct mlx5_ifc_qpc_bits {
2487 u8 state[0x4];
84df61eb 2488 u8 lag_tx_port_affinity[0x4];
e281682b 2489 u8 st[0x8];
b4ff3a36 2490 u8 reserved_at_10[0x3];
e281682b 2491 u8 pm_state[0x2];
3fd3c80a
DG		 2492 u8 reserved_at_15[0x1];
2493 u8 req_e2e_credit_mode[0x2];
6e44636a 2494 u8 offload_type[0x4];
e281682b 2495 u8 end_padding_mode[0x2];
b4ff3a36 2496 u8 reserved_at_1e[0x2];
e281682b
SM		 2497
2498 u8 wq_signature[0x1];
2499 u8 block_lb_mc[0x1];
2500 u8 atomic_like_write_en[0x1];
2501 u8 latency_sensitive[0x1];
b4ff3a36 2502 u8 reserved_at_24[0x1];
e281682b 2503 u8 drain_sigerr[0x1];
b4ff3a36 2504 u8 reserved_at_26[0x2];
e281682b
SM		 2505 u8 pd[0x18];
2506
2507 u8 mtu[0x3];
2508 u8 log_msg_max[0x5];
b4ff3a36 2509 u8 reserved_at_48[0x1];
e281682b
SM		 2510 u8 log_rq_size[0x4];
2511 u8 log_rq_stride[0x3];
2512 u8 no_sq[0x1];
2513 u8 log_sq_size[0x4];
b4ff3a36 2514 u8 reserved_at_55[0x6];
e281682b 2515 u8 rlky[0x1];
1015c2e8 2516 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2517
2518 u8 counter_set_id[0x8];
2519 u8 uar_page[0x18];
2520
b4ff3a36 2521 u8 reserved_at_80[0x8];
e281682b
SM		 2522 u8 user_index[0x18];
2523
b4ff3a36 2524 u8 reserved_at_a0[0x3];
e281682b
SM		 2525 u8 log_page_size[0x5];
2526 u8 remote_qpn[0x18];
2527
2528 struct mlx5_ifc_ads_bits primary_address_path;
2529
2530 struct mlx5_ifc_ads_bits secondary_address_path;
2531
2532 u8 log_ack_req_freq[0x4];
b4ff3a36 2533 u8 reserved_at_384[0x4];
e281682b 2534 u8 log_sra_max[0x3];
b4ff3a36 2535 u8 reserved_at_38b[0x2];
e281682b
SM		 2536 u8 retry_count[0x3];
2537 u8 rnr_retry[0x3];
b4ff3a36 2538 u8 reserved_at_393[0x1];
e281682b
SM		 2539 u8 fre[0x1];
2540 u8 cur_rnr_retry[0x3];
2541 u8 cur_retry_count[0x3];
b4ff3a36 2542 u8 reserved_at_39b[0x5];
e281682b 2543
b4ff3a36 2544 u8 reserved_at_3a0[0x20];
e281682b 2545
b4ff3a36 2546 u8 reserved_at_3c0[0x8];
e281682b
SM		 2547 u8 next_send_psn[0x18];
2548
b4ff3a36 2549 u8 reserved_at_3e0[0x8];
e281682b
SM		 2550 u8 cqn_snd[0x18];
2551
09a7d9ec
SM		 2552 u8 reserved_at_400[0x8];
2553 u8 deth_sqpn[0x18];
2554
2555 u8 reserved_at_420[0x20];
e281682b 2556
b4ff3a36 2557 u8 reserved_at_440[0x8];
e281682b
SM		 2558 u8 last_acked_psn[0x18];
2559
b4ff3a36 2560 u8 reserved_at_460[0x8];
e281682b
SM		 2561 u8 ssn[0x18];
2562
b4ff3a36 2563 u8 reserved_at_480[0x8];
e281682b 2564 u8 log_rra_max[0x3];
b4ff3a36 2565 u8 reserved_at_48b[0x1];
e281682b
SM		 2566 u8 atomic_mode[0x4];
2567 u8 rre[0x1];
2568 u8 rwe[0x1];
2569 u8 rae[0x1];
b4ff3a36 2570 u8 reserved_at_493[0x1];
e281682b 2571 u8 page_offset[0x6];
b4ff3a36 2572 u8 reserved_at_49a[0x3];
e281682b
SM		 2573 u8 cd_slave_receive[0x1];
2574 u8 cd_slave_send[0x1];
2575 u8 cd_master[0x1];
2576
b4ff3a36 2577 u8 reserved_at_4a0[0x3];
e281682b
SM		 2578 u8 min_rnr_nak[0x5];
2579 u8 next_rcv_psn[0x18];
2580
b4ff3a36 2581 u8 reserved_at_4c0[0x8];
e281682b
SM		 2582 u8 xrcd[0x18];
2583
b4ff3a36 2584 u8 reserved_at_4e0[0x8];
e281682b
SM		 2585 u8 cqn_rcv[0x18];
2586
2587 u8 dbr_addr[0x40];
2588
2589 u8 q_key[0x20];
2590
b4ff3a36 2591 u8 reserved_at_560[0x5];
e281682b 2592 u8 rq_type[0x3];
7486216b 2593 u8 srqn_rmpn_xrqn[0x18];
e281682b 2594
b4ff3a36 2595 u8 reserved_at_580[0x8];
e281682b
SM		 2596 u8 rmsn[0x18];
2597
2598 u8 hw_sq_wqebb_counter[0x10];
2599 u8 sw_sq_wqebb_counter[0x10];
2600
2601 u8 hw_rq_counter[0x20];
2602
2603 u8 sw_rq_counter[0x20];
2604
b4ff3a36 2605 u8 reserved_at_600[0x20];
e281682b 2606
b4ff3a36 2607 u8 reserved_at_620[0xf];
e281682b
SM		 2608 u8 cgs[0x1];
2609 u8 cs_req[0x8];
2610 u8 cs_res[0x8];
2611
2612 u8 dc_access_key[0x40];
2613
bd371975
LR		 2614 u8 reserved_at_680[0x3];
2615 u8 dbr_umem_valid[0x1];
2616
2617 u8 reserved_at_684[0xbc];
e281682b
SM		 2618};
2619
2620struct mlx5_ifc_roce_addr_layout_bits {
2621 u8 source_l3_address[16][0x8];
2622
b4ff3a36 2623 u8 reserved_at_80[0x3];
e281682b
SM		 2624 u8 vlan_valid[0x1];
2625 u8 vlan_id[0xc];
2626 u8 source_mac_47_32[0x10];
2627
2628 u8 source_mac_31_0[0x20];
2629
b4ff3a36 2630 u8 reserved_at_c0[0x14];
e281682b
SM		 2631 u8 roce_l3_type[0x4];
2632 u8 roce_version[0x8];
2633
b4ff3a36 2634 u8 reserved_at_e0[0x20];
e281682b
SM		 2635};
2636
2637union mlx5_ifc_hca_cap_union_bits {
2638 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2639 struct mlx5_ifc_odp_cap_bits odp_cap;
2640 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2641 struct mlx5_ifc_roce_cap_bits roce_cap;
2642 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2643 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2644 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2645 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2646 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2647 struct mlx5_ifc_qos_cap_bits qos_cap;
0b9055a1 2648 struct mlx5_ifc_debug_cap_bits debug_cap;
e29341fb 2649 struct mlx5_ifc_fpga_cap_bits fpga_cap;
a12ff35e 2650 struct mlx5_ifc_tls_cap_bits tls_cap;
b4ff3a36 2651 u8 reserved_at_0[0x8000];
e281682b
SM		 2652};
2653
2654enum {
2655 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2656 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2657 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2658 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 2659 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 2660 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2661 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2662 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2663 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 2664 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2665 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
0c06897a
OG		 2666};
2667
65c0f2c1
JL		 2668enum {
2669 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
2670 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
2671 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2672};
2673
0c06897a
OG		 2674struct mlx5_ifc_vlan_bits {
2675 u8 ethtype[0x10];
2676 u8 prio[0x3];
2677 u8 cfi[0x1];
2678 u8 vid[0xc];
e281682b
SM		 2679};
2680
2681struct mlx5_ifc_flow_context_bits {
0c06897a 2682 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2683
2684 u8 group_id[0x20];
2685
b4ff3a36 2686 u8 reserved_at_40[0x8];
e281682b
SM		 2687 u8 flow_tag[0x18];
2688
b4ff3a36 2689 u8 reserved_at_60[0x10];
e281682b
SM		 2690 u8 action[0x10];
2691
1b115498 2692 u8 extended_destination[0x1];
65c0f2c1
JL		 2693 u8 reserved_at_81[0x1];
2694 u8 flow_source[0x2];
2695 u8 reserved_at_84[0x4];
e281682b
SM		 2696 u8 destination_list_size[0x18];
2697
9dc0b289
AV		 2698 u8 reserved_at_a0[0x8];
2699 u8 flow_counter_list_size[0x18];
2700
60786f09 2701 u8 packet_reformat_id[0x20];
7adbde20 2702
2a69cb9f
OG		 2703 u8 modify_header_id[0x20];
2704
8da6fe2a
JL		 2705 struct mlx5_ifc_vlan_bits push_vlan_2;
2706
2707 u8 reserved_at_120[0xe0];
e281682b
SM		 2708
2709 struct mlx5_ifc_fte_match_param_bits match_value;
2710
b4ff3a36 2711 u8 reserved_at_1200[0x600];
e281682b 2712
9dc0b289 2713 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2714};
2715
2716enum {
2717 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2718 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2719};
2720
2721struct mlx5_ifc_xrc_srqc_bits {
2722 u8 state[0x4];
2723 u8 log_xrc_srq_size[0x4];
b4ff3a36 2724 u8 reserved_at_8[0x18];
e281682b
SM		 2725
2726 u8 wq_signature[0x1];
2727 u8 cont_srq[0x1];
99b77fef 2728 u8 reserved_at_22[0x1];
e281682b
SM		 2729 u8 rlky[0x1];
2730 u8 basic_cyclic_rcv_wqe[0x1];
2731 u8 log_rq_stride[0x3];
2732 u8 xrcd[0x18];
2733
2734 u8 page_offset[0x6];
99b77fef
YH		 2735 u8 reserved_at_46[0x1];
2736 u8 dbr_umem_valid[0x1];
e281682b
SM		 2737 u8 cqn[0x18];
2738
b4ff3a36 2739 u8 reserved_at_60[0x20];
e281682b
SM		 2740
2741 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2742 u8 reserved_at_81[0x1];
e281682b
SM		 2743 u8 log_page_size[0x6];
2744 u8 user_index[0x18];
2745
b4ff3a36 2746 u8 reserved_at_a0[0x20];
e281682b 2747
b4ff3a36 2748 u8 reserved_at_c0[0x8];
e281682b
SM		 2749 u8 pd[0x18];
2750
2751 u8 lwm[0x10];
2752 u8 wqe_cnt[0x10];
2753
b4ff3a36 2754 u8 reserved_at_100[0x40];
e281682b
SM		 2755
2756 u8 db_record_addr_h[0x20];
2757
2758 u8 db_record_addr_l[0x1e];
b4ff3a36 2759 u8 reserved_at_17e[0x2];
e281682b 2760
b4ff3a36 2761 u8 reserved_at_180[0x80];
e281682b
SM		 2762};
2763
61c5b5c9
MS		 2764struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2765 u8 counter_error_queues[0x20];
2766
2767 u8 total_error_queues[0x20];
2768
2769 u8 send_queue_priority_update_flow[0x20];
2770
2771 u8 reserved_at_60[0x20];
2772
2773 u8 nic_receive_steering_discard[0x40];
2774
2775 u8 receive_discard_vport_down[0x40];
2776
2777 u8 transmit_discard_vport_down[0x40];
2778
30b10e89
MS		 2779 u8 reserved_at_140[0xa0];
2780
2781 u8 internal_rq_out_of_buffer[0x20];
2782
2783 u8 reserved_at_200[0xe00];
61c5b5c9
MS		 2784};
2785
e281682b
SM		 2786struct mlx5_ifc_traffic_counter_bits {
2787 u8 packets[0x40];
2788
2789 u8 octets[0x40];
2790};
2791
2792struct mlx5_ifc_tisc_bits {
84df61eb 2793 u8 strict_lag_tx_port_affinity[0x1];
a12ff35e 2794 u8 tls_en[0x1];
7761f9ee 2795 u8 reserved_at_2[0x2];
84df61eb
AH		 2796 u8 lag_tx_port_affinity[0x04];
2797
2798 u8 reserved_at_8[0x4];
e281682b 2799 u8 prio[0x4];
b4ff3a36 2800 u8 reserved_at_10[0x10];
e281682b 2801
b4ff3a36 2802 u8 reserved_at_20[0x100];
e281682b 2803
b4ff3a36 2804 u8 reserved_at_120[0x8];
e281682b
SM		 2805 u8 transport_domain[0x18];
2806
500a3d0d
ES		 2807 u8 reserved_at_140[0x8];
2808 u8 underlay_qpn[0x18];
a12ff35e
EBE		 2809
2810 u8 reserved_at_160[0x8];
2811 u8 pd[0x18];
2812
2813 u8 reserved_at_180[0x380];
e281682b
SM		 2814};
2815
2816enum {
2817 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2818 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2819};
2820
2821enum {
2822 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2823 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2824};
2825
2826enum {
2be6967c
SM		 2827 MLX5_RX_HASH_FN_NONE = 0x0,
2828 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2829 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2830};
2831
2832enum {
5d773ff4
MB		 2833 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2834 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 2835};
2836
2837struct mlx5_ifc_tirc_bits {
b4ff3a36 2838 u8 reserved_at_0[0x20];
e281682b
SM		 2839
2840 u8 disp_type[0x4];
b4ff3a36 2841 u8 reserved_at_24[0x1c];
e281682b 2842
b4ff3a36 2843 u8 reserved_at_40[0x40];
e281682b 2844
b4ff3a36 2845 u8 reserved_at_80[0x4];
e281682b
SM		 2846 u8 lro_timeout_period_usecs[0x10];
2847 u8 lro_enable_mask[0x4];
2848 u8 lro_max_ip_payload_size[0x8];
2849
b4ff3a36 2850 u8 reserved_at_a0[0x40];
e281682b 2851
b4ff3a36 2852 u8 reserved_at_e0[0x8];
e281682b
SM		 2853 u8 inline_rqn[0x18];
2854
2855 u8 rx_hash_symmetric[0x1];
b4ff3a36 2856 u8 reserved_at_101[0x1];
e281682b 2857 u8 tunneled_offload_en[0x1];
b4ff3a36 2858 u8 reserved_at_103[0x5];
e281682b
SM		 2859 u8 indirect_table[0x18];
2860
2861 u8 rx_hash_fn[0x4];
b4ff3a36 2862 u8 reserved_at_124[0x2];
e281682b
SM		 2863 u8 self_lb_block[0x2];
2864 u8 transport_domain[0x18];
2865
2866 u8 rx_hash_toeplitz_key[10][0x20];
2867
2868 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2869
2870 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2871
b4ff3a36 2872 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2873};
2874
2875enum {
2876 MLX5_SRQC_STATE_GOOD = 0x0,
2877 MLX5_SRQC_STATE_ERROR = 0x1,
2878};
2879
2880struct mlx5_ifc_srqc_bits {
2881 u8 state[0x4];
2882 u8 log_srq_size[0x4];
b4ff3a36 2883 u8 reserved_at_8[0x18];
e281682b
SM		 2884
2885 u8 wq_signature[0x1];
2886 u8 cont_srq[0x1];
b4ff3a36 2887 u8 reserved_at_22[0x1];
e281682b 2888 u8 rlky[0x1];
b4ff3a36 2889 u8 reserved_at_24[0x1];
e281682b
SM		 2890 u8 log_rq_stride[0x3];
2891 u8 xrcd[0x18];
2892
2893 u8 page_offset[0x6];
b4ff3a36 2894 u8 reserved_at_46[0x2];
e281682b
SM		 2895 u8 cqn[0x18];
2896
b4ff3a36 2897 u8 reserved_at_60[0x20];
e281682b 2898
b4ff3a36 2899 u8 reserved_at_80[0x2];
e281682b 2900 u8 log_page_size[0x6];
b4ff3a36 2901 u8 reserved_at_88[0x18];
e281682b 2902
b4ff3a36 2903 u8 reserved_at_a0[0x20];
e281682b 2904
b4ff3a36 2905 u8 reserved_at_c0[0x8];
e281682b
SM		 2906 u8 pd[0x18];
2907
2908 u8 lwm[0x10];
2909 u8 wqe_cnt[0x10];
2910
b4ff3a36 2911 u8 reserved_at_100[0x40];
e281682b 2912
01949d01 2913 u8 dbr_addr[0x40];
e281682b 2914
b4ff3a36 2915 u8 reserved_at_180[0x80];
e281682b
SM		 2916};
2917
2918enum {
2919 MLX5_SQC_STATE_RST = 0x0,
2920 MLX5_SQC_STATE_RDY = 0x1,
2921 MLX5_SQC_STATE_ERR = 0x3,
2922};
2923
2924struct mlx5_ifc_sqc_bits {
2925 u8 rlky[0x1];
2926 u8 cd_master[0x1];
2927 u8 fre[0x1];
2928 u8 flush_in_error_en[0x1];
795b609c 2929 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2930 u8 min_wqe_inline_mode[0x3];
e281682b 2931 u8 state[0x4];
7d5e1423 2932 u8 reg_umr[0x1];
547eede0 2933 u8 allow_swp[0x1];
40817cdb
OG		 2934 u8 hairpin[0x1];
2935 u8 reserved_at_f[0x11];
e281682b 2936
b4ff3a36 2937 u8 reserved_at_20[0x8];
e281682b
SM		 2938 u8 user_index[0x18];
2939
b4ff3a36 2940 u8 reserved_at_40[0x8];
e281682b
SM		 2941 u8 cqn[0x18];
2942
40817cdb
OG		 2943 u8 reserved_at_60[0x8];
2944 u8 hairpin_peer_rq[0x18];
2945
2946 u8 reserved_at_80[0x10];
2947 u8 hairpin_peer_vhca[0x10];
2948
2949 u8 reserved_at_a0[0x50];
e281682b 2950
7486216b 2951 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2952 u8 tis_lst_sz[0x10];
b4ff3a36 2953 u8 reserved_at_110[0x10];
e281682b 2954
b4ff3a36 2955 u8 reserved_at_120[0x40];
e281682b 2956
b4ff3a36 2957 u8 reserved_at_160[0x8];
e281682b
SM		 2958 u8 tis_num_0[0x18];
2959
2960 struct mlx5_ifc_wq_bits wq;
2961};
2962
813f8540
MHY		 2963enum {
2964 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2965 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2966 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2967 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2968};
2969
6cedde45
EC		 2970enum {
2971 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
2972 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
2973 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
2974 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
2975};
2976
813f8540
MHY		 2977struct mlx5_ifc_scheduling_context_bits {
2978 u8 element_type[0x8];
2979 u8 reserved_at_8[0x18];
2980
2981 u8 element_attributes[0x20];
2982
2983 u8 parent_element_id[0x20];
2984
2985 u8 reserved_at_60[0x40];
2986
2987 u8 bw_share[0x20];
2988
2989 u8 max_average_bw[0x20];
2990
2991 u8 reserved_at_e0[0x120];
2992};
2993
e281682b 2994struct mlx5_ifc_rqtc_bits {
b4ff3a36 2995 u8 reserved_at_0[0xa0];
e281682b 2996
b4ff3a36 2997 u8 reserved_at_a0[0x10];
e281682b
SM		 2998 u8 rqt_max_size[0x10];
2999
b4ff3a36 3000 u8 reserved_at_c0[0x10];
e281682b
SM		 3001 u8 rqt_actual_size[0x10];
3002
b4ff3a36 3003 u8 reserved_at_e0[0x6a0];
e281682b
SM		 3004
3005 struct mlx5_ifc_rq_num_bits rq_num[0];
3006};
3007
3008enum {
3009 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3010 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3011};
3012
3013enum {
3014 MLX5_RQC_STATE_RST = 0x0,
3015 MLX5_RQC_STATE_RDY = 0x1,
3016 MLX5_RQC_STATE_ERR = 0x3,
3017};
3018
3019struct mlx5_ifc_rqc_bits {
3020 u8 rlky[0x1];
03404e8a 3021 u8 delay_drop_en[0x1];
7d5e1423 3022 u8 scatter_fcs[0x1];
e281682b
SM		 3023 u8 vsd[0x1];
3024 u8 mem_rq_type[0x4];
3025 u8 state[0x4];
b4ff3a36 3026 u8 reserved_at_c[0x1];
e281682b 3027 u8 flush_in_error_en[0x1];
40817cdb
OG		 3028 u8 hairpin[0x1];
3029 u8 reserved_at_f[0x11];
e281682b 3030
b4ff3a36 3031 u8 reserved_at_20[0x8];
e281682b
SM		 3032 u8 user_index[0x18];
3033
b4ff3a36 3034 u8 reserved_at_40[0x8];
e281682b
SM		 3035 u8 cqn[0x18];
3036
3037 u8 counter_set_id[0x8];
b4ff3a36 3038 u8 reserved_at_68[0x18];
e281682b 3039
b4ff3a36 3040 u8 reserved_at_80[0x8];
e281682b
SM		 3041 u8 rmpn[0x18];
3042
40817cdb
OG		 3043 u8 reserved_at_a0[0x8];
3044 u8 hairpin_peer_sq[0x18];
3045
3046 u8 reserved_at_c0[0x10];
3047 u8 hairpin_peer_vhca[0x10];
3048
3049 u8 reserved_at_e0[0xa0];
e281682b
SM		 3050
3051 struct mlx5_ifc_wq_bits wq;
3052};
3053
3054enum {
3055 MLX5_RMPC_STATE_RDY = 0x1,
3056 MLX5_RMPC_STATE_ERR = 0x3,
3057};
3058
3059struct mlx5_ifc_rmpc_bits {
b4ff3a36 3060 u8 reserved_at_0[0x8];
e281682b 3061 u8 state[0x4];
b4ff3a36 3062 u8 reserved_at_c[0x14];
e281682b
SM		 3063
3064 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 3065 u8 reserved_at_21[0x1f];
e281682b 3066
b4ff3a36 3067 u8 reserved_at_40[0x140];
e281682b
SM		 3068
3069 struct mlx5_ifc_wq_bits wq;
3070};
3071
e281682b 3072struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 3073 u8 reserved_at_0[0x5];
3074 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 3075 u8 reserved_at_8[0x15];
3076 u8 disable_mc_local_lb[0x1];
3077 u8 disable_uc_local_lb[0x1];
e281682b
SM		 3078 u8 roce_en[0x1];
3079
d82b7318 3080 u8 arm_change_event[0x1];
b4ff3a36 3081 u8 reserved_at_21[0x1a];
d82b7318
SM		 3082 u8 event_on_mtu[0x1];
3083 u8 event_on_promisc_change[0x1];
3084 u8 event_on_vlan_change[0x1];
3085 u8 event_on_mc_address_change[0x1];
3086 u8 event_on_uc_address_change[0x1];
e281682b 3087
32f69e4b
DJ		 3088 u8 reserved_at_40[0xc];
3089
3090 u8 affiliation_criteria[0x4];
3091 u8 affiliated_vhca_id[0x10];
3092
3093 u8 reserved_at_60[0xd0];
d82b7318
SM		 3094
3095 u8 mtu[0x10];
3096
9efa7525
AS		 3097 u8 system_image_guid[0x40];
3098 u8 port_guid[0x40];
3099 u8 node_guid[0x40];
3100
b4ff3a36 3101 u8 reserved_at_200[0x140];
9efa7525 3102 u8 qkey_violation_counter[0x10];
b4ff3a36 3103 u8 reserved_at_350[0x430];
d82b7318
SM		 3104
3105 u8 promisc_uc[0x1];
3106 u8 promisc_mc[0x1];
3107 u8 promisc_all[0x1];
b4ff3a36 3108 u8 reserved_at_783[0x2];
e281682b 3109 u8 allowed_list_type[0x3];
b4ff3a36 3110 u8 reserved_at_788[0xc];
e281682b
SM		 3111 u8 allowed_list_size[0xc];
3112
3113 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3114
b4ff3a36 3115 u8 reserved_at_7e0[0x20];
e281682b
SM		 3116
3117 u8 current_uc_mac_address[0][0x40];
3118};
3119
3120enum {
3121 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3122 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3123 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 3124 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 3125 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 3126 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 3127};
3128
3129struct mlx5_ifc_mkc_bits {
b4ff3a36 3130 u8 reserved_at_0[0x1];
e281682b 3131 u8 free[0x1];
cdbd0d2b
AL		 3132 u8 reserved_at_2[0x1];
3133 u8 access_mode_4_2[0x3];
3134 u8 reserved_at_6[0x7];
3135 u8 relaxed_ordering_write[0x1];
3136 u8 reserved_at_e[0x1];
e281682b
SM		 3137 u8 small_fence_on_rdma_read_response[0x1];
3138 u8 umr_en[0x1];
3139 u8 a[0x1];
3140 u8 rw[0x1];
3141 u8 rr[0x1];
3142 u8 lw[0x1];
3143 u8 lr[0x1];
cdbd0d2b 3144 u8 access_mode_1_0[0x2];
b4ff3a36 3145 u8 reserved_at_18[0x8];
e281682b
SM		 3146
3147 u8 qpn[0x18];
3148 u8 mkey_7_0[0x8];
3149
b4ff3a36 3150 u8 reserved_at_40[0x20];
e281682b
SM		 3151
3152 u8 length64[0x1];
3153 u8 bsf_en[0x1];
3154 u8 sync_umr[0x1];
b4ff3a36 3155 u8 reserved_at_63[0x2];
e281682b 3156 u8 expected_sigerr_count[0x1];
b4ff3a36 3157 u8 reserved_at_66[0x1];
e281682b
SM		 3158 u8 en_rinval[0x1];
3159 u8 pd[0x18];
3160
3161 u8 start_addr[0x40];
3162
3163 u8 len[0x40];
3164
3165 u8 bsf_octword_size[0x20];
3166
b4ff3a36 3167 u8 reserved_at_120[0x80];
e281682b
SM		 3168
3169 u8 translations_octword_size[0x20];
3170
b4ff3a36 3171 u8 reserved_at_1c0[0x1b];
e281682b
SM		 3172 u8 log_page_size[0x5];
3173
b4ff3a36 3174 u8 reserved_at_1e0[0x20];
e281682b
SM		 3175};
3176
3177struct mlx5_ifc_pkey_bits {
b4ff3a36 3178 u8 reserved_at_0[0x10];
e281682b
SM		 3179 u8 pkey[0x10];
3180};
3181
3182struct mlx5_ifc_array128_auto_bits {
3183 u8 array128_auto[16][0x8];
3184};
3185
3186struct mlx5_ifc_hca_vport_context_bits {
3187 u8 field_select[0x20];
3188
b4ff3a36 3189 u8 reserved_at_20[0xe0];
e281682b
SM		 3190
3191 u8 sm_virt_aware[0x1];
3192 u8 has_smi[0x1];
3193 u8 has_raw[0x1];
3194 u8 grh_required[0x1];
b4ff3a36 3195 u8 reserved_at_104[0xc];
707c4602
MD		 3196 u8 port_physical_state[0x4];
3197 u8 vport_state_policy[0x4];
3198 u8 port_state[0x4];
e281682b
SM		 3199 u8 vport_state[0x4];
3200
b4ff3a36 3201 u8 reserved_at_120[0x20];
707c4602
MD		 3202
3203 u8 system_image_guid[0x40];
e281682b
SM		 3204
3205 u8 port_guid[0x40];
3206
3207 u8 node_guid[0x40];
3208
3209 u8 cap_mask1[0x20];
3210
3211 u8 cap_mask1_field_select[0x20];
3212
3213 u8 cap_mask2[0x20];
3214
3215 u8 cap_mask2_field_select[0x20];
3216
b4ff3a36 3217 u8 reserved_at_280[0x80];
e281682b
SM		 3218
3219 u8 lid[0x10];
b4ff3a36 3220 u8 reserved_at_310[0x4];
e281682b
SM		 3221 u8 init_type_reply[0x4];
3222 u8 lmc[0x3];
3223 u8 subnet_timeout[0x5];
3224
3225 u8 sm_lid[0x10];
3226 u8 sm_sl[0x4];
b4ff3a36 3227 u8 reserved_at_334[0xc];
e281682b
SM		 3228
3229 u8 qkey_violation_counter[0x10];
3230 u8 pkey_violation_counter[0x10];
3231
b4ff3a36 3232 u8 reserved_at_360[0xca0];
e281682b
SM		 3233};
3234
d6666753 3235struct mlx5_ifc_esw_vport_context_bits {
65c0f2c1
JL		 3236 u8 fdb_to_vport_reg_c[0x1];
3237 u8 reserved_at_1[0x2];
d6666753
SM		 3238 u8 vport_svlan_strip[0x1];
3239 u8 vport_cvlan_strip[0x1];
3240 u8 vport_svlan_insert[0x1];
3241 u8 vport_cvlan_insert[0x2];
65c0f2c1
JL		 3242 u8 fdb_to_vport_reg_c_id[0x8];
3243 u8 reserved_at_10[0x10];
d6666753 3244
b4ff3a36 3245 u8 reserved_at_20[0x20];
d6666753
SM		 3246
3247 u8 svlan_cfi[0x1];
3248 u8 svlan_pcp[0x3];
3249 u8 svlan_id[0xc];
3250 u8 cvlan_cfi[0x1];
3251 u8 cvlan_pcp[0x3];
3252 u8 cvlan_id[0xc];
3253
b4ff3a36 3254 u8 reserved_at_60[0x7a0];
d6666753
SM		 3255};
3256
e281682b
SM		 3257enum {
3258 MLX5_EQC_STATUS_OK = 0x0,
3259 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3260};
3261
3262enum {
3263 MLX5_EQC_ST_ARMED = 0x9,
3264 MLX5_EQC_ST_FIRED = 0xa,
3265};
3266
3267struct mlx5_ifc_eqc_bits {
3268 u8 status[0x4];
b4ff3a36 3269 u8 reserved_at_4[0x9];
e281682b
SM		 3270 u8 ec[0x1];
3271 u8 oi[0x1];
b4ff3a36 3272 u8 reserved_at_f[0x5];
e281682b 3273 u8 st[0x4];
b4ff3a36 3274 u8 reserved_at_18[0x8];
e281682b 3275
b4ff3a36 3276 u8 reserved_at_20[0x20];
e281682b 3277
b4ff3a36 3278 u8 reserved_at_40[0x14];
e281682b 3279 u8 page_offset[0x6];
b4ff3a36 3280 u8 reserved_at_5a[0x6];
e281682b 3281
b4ff3a36 3282 u8 reserved_at_60[0x3];
e281682b
SM		 3283 u8 log_eq_size[0x5];
3284 u8 uar_page[0x18];
3285
b4ff3a36 3286 u8 reserved_at_80[0x20];
e281682b 3287
b4ff3a36 3288 u8 reserved_at_a0[0x18];
e281682b
SM		 3289 u8 intr[0x8];
3290
b4ff3a36 3291 u8 reserved_at_c0[0x3];
e281682b 3292 u8 log_page_size[0x5];
b4ff3a36 3293 u8 reserved_at_c8[0x18];
e281682b 3294
b4ff3a36 3295 u8 reserved_at_e0[0x60];
e281682b 3296
b4ff3a36 3297 u8 reserved_at_140[0x8];
e281682b
SM		 3298 u8 consumer_counter[0x18];
3299
b4ff3a36 3300 u8 reserved_at_160[0x8];
e281682b
SM		 3301 u8 producer_counter[0x18];
3302
b4ff3a36 3303 u8 reserved_at_180[0x80];
e281682b
SM		 3304};
3305
3306enum {
3307 MLX5_DCTC_STATE_ACTIVE = 0x0,
3308 MLX5_DCTC_STATE_DRAINING = 0x1,
3309 MLX5_DCTC_STATE_DRAINED = 0x2,
3310};
3311
3312enum {
3313 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3314 MLX5_DCTC_CS_RES_NA = 0x1,
3315 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3316};
3317
3318enum {
3319 MLX5_DCTC_MTU_256_BYTES = 0x1,
3320 MLX5_DCTC_MTU_512_BYTES = 0x2,
3321 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3322 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3323 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3324};
3325
3326struct mlx5_ifc_dctc_bits {
b4ff3a36 3327 u8 reserved_at_0[0x4];
e281682b 3328 u8 state[0x4];
b4ff3a36 3329 u8 reserved_at_8[0x18];
e281682b 3330
b4ff3a36 3331 u8 reserved_at_20[0x8];
e281682b
SM		 3332 u8 user_index[0x18];
3333
b4ff3a36 3334 u8 reserved_at_40[0x8];
e281682b
SM		 3335 u8 cqn[0x18];
3336
3337 u8 counter_set_id[0x8];
3338 u8 atomic_mode[0x4];
3339 u8 rre[0x1];
3340 u8 rwe[0x1];
3341 u8 rae[0x1];
3342 u8 atomic_like_write_en[0x1];
3343 u8 latency_sensitive[0x1];
3344 u8 rlky[0x1];
3345 u8 free_ar[0x1];
b4ff3a36 3346 u8 reserved_at_73[0xd];
e281682b 3347
b4ff3a36 3348 u8 reserved_at_80[0x8];
e281682b 3349 u8 cs_res[0x8];
b4ff3a36 3350 u8 reserved_at_90[0x3];
e281682b 3351 u8 min_rnr_nak[0x5];
b4ff3a36 3352 u8 reserved_at_98[0x8];
e281682b 3353
b4ff3a36 3354 u8 reserved_at_a0[0x8];
7486216b 3355 u8 srqn_xrqn[0x18];
e281682b 3356
b4ff3a36 3357 u8 reserved_at_c0[0x8];
e281682b
SM		 3358 u8 pd[0x18];
3359
3360 u8 tclass[0x8];
b4ff3a36 3361 u8 reserved_at_e8[0x4];
e281682b
SM		 3362 u8 flow_label[0x14];
3363
3364 u8 dc_access_key[0x40];
3365
b4ff3a36 3366 u8 reserved_at_140[0x5];
e281682b
SM		 3367 u8 mtu[0x3];
3368 u8 port[0x8];
3369 u8 pkey_index[0x10];
3370
b4ff3a36 3371 u8 reserved_at_160[0x8];
e281682b 3372 u8 my_addr_index[0x8];
b4ff3a36 3373 u8 reserved_at_170[0x8];
e281682b
SM		 3374 u8 hop_limit[0x8];
3375
3376 u8 dc_access_key_violation_count[0x20];
3377
b4ff3a36 3378 u8 reserved_at_1a0[0x14];
e281682b
SM		 3379 u8 dei_cfi[0x1];
3380 u8 eth_prio[0x3];
3381 u8 ecn[0x2];
3382 u8 dscp[0x6];
3383
b4ff3a36 3384 u8 reserved_at_1c0[0x40];
e281682b
SM		 3385};
3386
3387enum {
3388 MLX5_CQC_STATUS_OK = 0x0,
3389 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3390 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3391};
3392
3393enum {
3394 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3395 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3396};
3397
3398enum {
3399 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3400 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3401 MLX5_CQC_ST_FIRED = 0xa,
3402};
3403
7d5e1423
SM		 3404enum {
3405 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3406 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3407 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3408};
3409
e281682b
SM		 3410struct mlx5_ifc_cqc_bits {
3411 u8 status[0x4];
bd371975
LR		 3412 u8 reserved_at_4[0x2];
3413 u8 dbr_umem_valid[0x1];
3414 u8 reserved_at_7[0x1];
e281682b
SM		 3415 u8 cqe_sz[0x3];
3416 u8 cc[0x1];
b4ff3a36 3417 u8 reserved_at_c[0x1];
e281682b
SM		 3418 u8 scqe_break_moderation_en[0x1];
3419 u8 oi[0x1];
7d5e1423
SM		 3420 u8 cq_period_mode[0x2];
3421 u8 cqe_comp_en[0x1];
e281682b
SM		 3422 u8 mini_cqe_res_format[0x2];
3423 u8 st[0x4];
b4ff3a36 3424 u8 reserved_at_18[0x8];
e281682b 3425
b4ff3a36 3426 u8 reserved_at_20[0x20];
e281682b 3427
b4ff3a36 3428 u8 reserved_at_40[0x14];
e281682b 3429 u8 page_offset[0x6];
b4ff3a36 3430 u8 reserved_at_5a[0x6];
e281682b 3431
b4ff3a36 3432 u8 reserved_at_60[0x3];
e281682b
SM		 3433 u8 log_cq_size[0x5];
3434 u8 uar_page[0x18];
3435
b4ff3a36 3436 u8 reserved_at_80[0x4];
e281682b
SM		 3437 u8 cq_period[0xc];
3438 u8 cq_max_count[0x10];
3439
b4ff3a36 3440 u8 reserved_at_a0[0x18];
e281682b
SM		 3441 u8 c_eqn[0x8];
3442
b4ff3a36 3443 u8 reserved_at_c0[0x3];
e281682b 3444 u8 log_page_size[0x5];
b4ff3a36 3445 u8 reserved_at_c8[0x18];
e281682b 3446
b4ff3a36 3447 u8 reserved_at_e0[0x20];
e281682b 3448
b4ff3a36 3449 u8 reserved_at_100[0x8];
e281682b
SM		 3450 u8 last_notified_index[0x18];
3451
b4ff3a36 3452 u8 reserved_at_120[0x8];
e281682b
SM		 3453 u8 last_solicit_index[0x18];
3454
b4ff3a36 3455 u8 reserved_at_140[0x8];
e281682b
SM		 3456 u8 consumer_counter[0x18];
3457
b4ff3a36 3458 u8 reserved_at_160[0x8];
e281682b
SM		 3459 u8 producer_counter[0x18];
3460
b4ff3a36 3461 u8 reserved_at_180[0x40];
e281682b
SM		 3462
3463 u8 dbr_addr[0x40];
3464};
3465
3466union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3467 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3468 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3469 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3470 u8 reserved_at_0[0x800];
e281682b
SM		 3471};
3472
3473struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3474 u8 reserved_at_0[0xc0];
e281682b 3475
b4ff3a36 3476 u8 reserved_at_c0[0x8];
211e6c80
MD		 3477 u8 ieee_vendor_id[0x18];
3478
b4ff3a36 3479 u8 reserved_at_e0[0x10];
e281682b
SM		 3480 u8 vsd_vendor_id[0x10];
3481
3482 u8 vsd[208][0x8];
3483
3484 u8 vsd_contd_psid[16][0x8];
3485};
3486
7486216b
SM		 3487enum {
3488 MLX5_XRQC_STATE_GOOD = 0x0,
3489 MLX5_XRQC_STATE_ERROR = 0x1,
3490};
3491
3492enum {
3493 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3494 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3495};
3496
3497enum {
3498 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3499};
3500
3501struct mlx5_ifc_tag_matching_topology_context_bits {
3502 u8 log_matching_list_sz[0x4];
3503 u8 reserved_at_4[0xc];
3504 u8 append_next_index[0x10];
3505
3506 u8 sw_phase_cnt[0x10];
3507 u8 hw_phase_cnt[0x10];
3508
3509 u8 reserved_at_40[0x40];
3510};
3511
3512struct mlx5_ifc_xrqc_bits {
3513 u8 state[0x4];
3514 u8 rlkey[0x1];
3515 u8 reserved_at_5[0xf];
3516 u8 topology[0x4];
3517 u8 reserved_at_18[0x4];
3518 u8 offload[0x4];
3519
3520 u8 reserved_at_20[0x8];
3521 u8 user_index[0x18];
3522
3523 u8 reserved_at_40[0x8];
3524 u8 cqn[0x18];
3525
3526 u8 reserved_at_60[0xa0];
3527
3528 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3529
6e44636a 3530 u8 reserved_at_180[0x280];
7486216b
SM		 3531
3532 struct mlx5_ifc_wq_bits wq;
3533};
3534
e281682b
SM		 3535union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3536 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3537 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3538 u8 reserved_at_0[0x20];
e281682b
SM		 3539};
3540
3541union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3542 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3543 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3544 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3545 u8 reserved_at_0[0x20];
e281682b
SM		 3546};
3547
3548union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3549 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3550 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3551 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3552 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3553 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3554 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3555 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3556 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3557 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3558 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3559 u8 reserved_at_0[0x7c0];
e281682b
SM		 3560};
3561
8ed1a630
GP		 3562union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3563 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3564 u8 reserved_at_0[0x7c0];
3565};
3566
e281682b
SM		 3567union mlx5_ifc_event_auto_bits {
3568 struct mlx5_ifc_comp_event_bits comp_event;
3569 struct mlx5_ifc_dct_events_bits dct_events;
3570 struct mlx5_ifc_qp_events_bits qp_events;
3571 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3572 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3573 struct mlx5_ifc_cq_error_bits cq_error;
3574 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3575 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3576 struct mlx5_ifc_gpio_event_bits gpio_event;
3577 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3578 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3579 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3580 u8 reserved_at_0[0xe0];
e281682b
SM		 3581};
3582
3583struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3584 u8 reserved_at_0[0x100];
e281682b
SM		 3585
3586 u8 assert_existptr[0x20];
3587
3588 u8 assert_callra[0x20];
3589
b4ff3a36 3590 u8 reserved_at_140[0x40];
e281682b
SM		 3591
3592 u8 fw_version[0x20];
3593
3594 u8 hw_id[0x20];
3595
b4ff3a36 3596 u8 reserved_at_1c0[0x20];
e281682b
SM		 3597
3598 u8 irisc_index[0x8];
3599 u8 synd[0x8];
3600 u8 ext_synd[0x10];
3601};
3602
3603struct mlx5_ifc_register_loopback_control_bits {
3604 u8 no_lb[0x1];
b4ff3a36 3605 u8 reserved_at_1[0x7];
e281682b 3606 u8 port[0x8];
b4ff3a36 3607 u8 reserved_at_10[0x10];
e281682b 3608
b4ff3a36 3609 u8 reserved_at_20[0x60];
e281682b
SM		 3610};
3611
813f8540
MHY		 3612struct mlx5_ifc_vport_tc_element_bits {
3613 u8 traffic_class[0x4];
3614 u8 reserved_at_4[0xc];
3615 u8 vport_number[0x10];
3616};
3617
3618struct mlx5_ifc_vport_element_bits {
3619 u8 reserved_at_0[0x10];
3620 u8 vport_number[0x10];
3621};
3622
3623enum {
3624 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3625 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3626 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3627};
3628
3629struct mlx5_ifc_tsar_element_bits {
3630 u8 reserved_at_0[0x8];
3631 u8 tsar_type[0x8];
3632 u8 reserved_at_10[0x10];
3633};
3634
8812c24d
MD		 3635enum {
3636 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3637 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3638};
3639
e281682b
SM		 3640struct mlx5_ifc_teardown_hca_out_bits {
3641 u8 status[0x8];
b4ff3a36 3642 u8 reserved_at_8[0x18];
e281682b
SM		 3643
3644 u8 syndrome[0x20];
3645
8812c24d
MD		 3646 u8 reserved_at_40[0x3f];
3647
fcd29ad1 3648 u8 state[0x1];
e281682b
SM		 3649};
3650
3651enum {
3652 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3653 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 3654 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 3655};
3656
3657struct mlx5_ifc_teardown_hca_in_bits {
3658 u8 opcode[0x10];
b4ff3a36 3659 u8 reserved_at_10[0x10];
e281682b 3660
b4ff3a36 3661 u8 reserved_at_20[0x10];
e281682b
SM		 3662 u8 op_mod[0x10];
3663
b4ff3a36 3664 u8 reserved_at_40[0x10];
e281682b
SM		 3665 u8 profile[0x10];
3666
b4ff3a36 3667 u8 reserved_at_60[0x20];
e281682b
SM		 3668};
3669
3670struct mlx5_ifc_sqerr2rts_qp_out_bits {
3671 u8 status[0x8];
b4ff3a36 3672 u8 reserved_at_8[0x18];
e281682b
SM		 3673
3674 u8 syndrome[0x20];
3675
b4ff3a36 3676 u8 reserved_at_40[0x40];
e281682b
SM		 3677};
3678
3679struct mlx5_ifc_sqerr2rts_qp_in_bits {
3680 u8 opcode[0x10];
4ac63ec7 3681 u8 uid[0x10];
e281682b 3682
b4ff3a36 3683 u8 reserved_at_20[0x10];
e281682b
SM		 3684 u8 op_mod[0x10];
3685
b4ff3a36 3686 u8 reserved_at_40[0x8];
e281682b
SM		 3687 u8 qpn[0x18];
3688
b4ff3a36 3689 u8 reserved_at_60[0x20];
e281682b
SM		 3690
3691 u8 opt_param_mask[0x20];
3692
b4ff3a36 3693 u8 reserved_at_a0[0x20];
e281682b
SM		 3694
3695 struct mlx5_ifc_qpc_bits qpc;
3696
b4ff3a36 3697 u8 reserved_at_800[0x80];
e281682b
SM		 3698};
3699
3700struct mlx5_ifc_sqd2rts_qp_out_bits {
3701 u8 status[0x8];
b4ff3a36 3702 u8 reserved_at_8[0x18];
e281682b
SM		 3703
3704 u8 syndrome[0x20];
3705
b4ff3a36 3706 u8 reserved_at_40[0x40];
e281682b
SM		 3707};
3708
3709struct mlx5_ifc_sqd2rts_qp_in_bits {
3710 u8 opcode[0x10];
4ac63ec7 3711 u8 uid[0x10];
e281682b 3712
b4ff3a36 3713 u8 reserved_at_20[0x10];
e281682b
SM		 3714 u8 op_mod[0x10];
3715
b4ff3a36 3716 u8 reserved_at_40[0x8];
e281682b
SM		 3717 u8 qpn[0x18];
3718
b4ff3a36 3719 u8 reserved_at_60[0x20];
e281682b
SM		 3720
3721 u8 opt_param_mask[0x20];
3722
b4ff3a36 3723 u8 reserved_at_a0[0x20];
e281682b
SM		 3724
3725 struct mlx5_ifc_qpc_bits qpc;
3726
b4ff3a36 3727 u8 reserved_at_800[0x80];
e281682b
SM		 3728};
3729
3730struct mlx5_ifc_set_roce_address_out_bits {
3731 u8 status[0x8];
b4ff3a36 3732 u8 reserved_at_8[0x18];
e281682b
SM		 3733
3734 u8 syndrome[0x20];
3735
b4ff3a36 3736 u8 reserved_at_40[0x40];
e281682b
SM		 3737};
3738
3739struct mlx5_ifc_set_roce_address_in_bits {
3740 u8 opcode[0x10];
b4ff3a36 3741 u8 reserved_at_10[0x10];
e281682b 3742
b4ff3a36 3743 u8 reserved_at_20[0x10];
e281682b
SM		 3744 u8 op_mod[0x10];
3745
3746 u8 roce_address_index[0x10];
32f69e4b
DJ		 3747 u8 reserved_at_50[0xc];
3748 u8 vhca_port_num[0x4];
e281682b 3749
b4ff3a36 3750 u8 reserved_at_60[0x20];
e281682b
SM		 3751
3752 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3753};
3754
3755struct mlx5_ifc_set_mad_demux_out_bits {
3756 u8 status[0x8];
b4ff3a36 3757 u8 reserved_at_8[0x18];
e281682b
SM		 3758
3759 u8 syndrome[0x20];
3760
b4ff3a36 3761 u8 reserved_at_40[0x40];
e281682b
SM		 3762};
3763
3764enum {
3765 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3766 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3767};
3768
3769struct mlx5_ifc_set_mad_demux_in_bits {
3770 u8 opcode[0x10];
b4ff3a36 3771 u8 reserved_at_10[0x10];
e281682b 3772
b4ff3a36 3773 u8 reserved_at_20[0x10];
e281682b
SM		 3774 u8 op_mod[0x10];
3775
b4ff3a36 3776 u8 reserved_at_40[0x20];
e281682b 3777
b4ff3a36 3778 u8 reserved_at_60[0x6];
e281682b 3779 u8 demux_mode[0x2];
b4ff3a36 3780 u8 reserved_at_68[0x18];
e281682b
SM		 3781};
3782
3783struct mlx5_ifc_set_l2_table_entry_out_bits {
3784 u8 status[0x8];
b4ff3a36 3785 u8 reserved_at_8[0x18];
e281682b
SM		 3786
3787 u8 syndrome[0x20];
3788
b4ff3a36 3789 u8 reserved_at_40[0x40];
e281682b
SM		 3790};
3791
3792struct mlx5_ifc_set_l2_table_entry_in_bits {
3793 u8 opcode[0x10];
b4ff3a36 3794 u8 reserved_at_10[0x10];
e281682b 3795
b4ff3a36 3796 u8 reserved_at_20[0x10];
e281682b
SM		 3797 u8 op_mod[0x10];
3798
b4ff3a36 3799 u8 reserved_at_40[0x60];
e281682b 3800
b4ff3a36 3801 u8 reserved_at_a0[0x8];
e281682b
SM		 3802 u8 table_index[0x18];
3803
b4ff3a36 3804 u8 reserved_at_c0[0x20];
e281682b 3805
b4ff3a36 3806 u8 reserved_at_e0[0x13];
e281682b
SM		 3807 u8 vlan_valid[0x1];
3808 u8 vlan[0xc];
3809
3810 struct mlx5_ifc_mac_address_layout_bits mac_address;
3811
b4ff3a36 3812 u8 reserved_at_140[0xc0];
e281682b
SM		 3813};
3814
3815struct mlx5_ifc_set_issi_out_bits {
3816 u8 status[0x8];
b4ff3a36 3817 u8 reserved_at_8[0x18];
e281682b
SM		 3818
3819 u8 syndrome[0x20];
3820
b4ff3a36 3821 u8 reserved_at_40[0x40];
e281682b
SM		 3822};
3823
3824struct mlx5_ifc_set_issi_in_bits {
3825 u8 opcode[0x10];
b4ff3a36 3826 u8 reserved_at_10[0x10];
e281682b 3827
b4ff3a36 3828 u8 reserved_at_20[0x10];
e281682b
SM		 3829 u8 op_mod[0x10];
3830
b4ff3a36 3831 u8 reserved_at_40[0x10];
e281682b
SM		 3832 u8 current_issi[0x10];
3833
b4ff3a36 3834 u8 reserved_at_60[0x20];
e281682b
SM		 3835};
3836
3837struct mlx5_ifc_set_hca_cap_out_bits {
3838 u8 status[0x8];
b4ff3a36 3839 u8 reserved_at_8[0x18];
e281682b
SM		 3840
3841 u8 syndrome[0x20];
3842
b4ff3a36 3843 u8 reserved_at_40[0x40];
e281682b
SM		 3844};
3845
3846struct mlx5_ifc_set_hca_cap_in_bits {
3847 u8 opcode[0x10];
b4ff3a36 3848 u8 reserved_at_10[0x10];
e281682b 3849
b4ff3a36 3850 u8 reserved_at_20[0x10];
e281682b
SM		 3851 u8 op_mod[0x10];
3852
b4ff3a36 3853 u8 reserved_at_40[0x40];
e281682b
SM		 3854
3855 union mlx5_ifc_hca_cap_union_bits capability;
3856};
3857
26a81453
MG		 3858enum {
3859 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3860 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3861 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3862 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3863};
3864
e281682b
SM		 3865struct mlx5_ifc_set_fte_out_bits {
3866 u8 status[0x8];
b4ff3a36 3867 u8 reserved_at_8[0x18];
e281682b
SM		 3868
3869 u8 syndrome[0x20];
3870
b4ff3a36 3871 u8 reserved_at_40[0x40];
e281682b
SM		 3872};
3873
3874struct mlx5_ifc_set_fte_in_bits {
3875 u8 opcode[0x10];
b4ff3a36 3876 u8 reserved_at_10[0x10];
e281682b 3877
b4ff3a36 3878 u8 reserved_at_20[0x10];
e281682b
SM		 3879 u8 op_mod[0x10];
3880
7d5e1423
SM		 3881 u8 other_vport[0x1];
3882 u8 reserved_at_41[0xf];
3883 u8 vport_number[0x10];
3884
3885 u8 reserved_at_60[0x20];
e281682b
SM		 3886
3887 u8 table_type[0x8];
b4ff3a36 3888 u8 reserved_at_88[0x18];
e281682b 3889
b4ff3a36 3890 u8 reserved_at_a0[0x8];
e281682b
SM		 3891 u8 table_id[0x18];
3892
b4ff3a36 3893 u8 reserved_at_c0[0x18];
26a81453
MG		 3894 u8 modify_enable_mask[0x8];
3895
b4ff3a36 3896 u8 reserved_at_e0[0x20];
e281682b
SM		 3897
3898 u8 flow_index[0x20];
3899
b4ff3a36 3900 u8 reserved_at_120[0xe0];
e281682b
SM		 3901
3902 struct mlx5_ifc_flow_context_bits flow_context;
3903};
3904
3905struct mlx5_ifc_rts2rts_qp_out_bits {
3906 u8 status[0x8];
b4ff3a36 3907 u8 reserved_at_8[0x18];
e281682b
SM		 3908
3909 u8 syndrome[0x20];
3910
b4ff3a36 3911 u8 reserved_at_40[0x40];
e281682b
SM		 3912};
3913
3914struct mlx5_ifc_rts2rts_qp_in_bits {
3915 u8 opcode[0x10];
4ac63ec7 3916 u8 uid[0x10];
e281682b 3917
b4ff3a36 3918 u8 reserved_at_20[0x10];
e281682b
SM		 3919 u8 op_mod[0x10];
3920
b4ff3a36 3921 u8 reserved_at_40[0x8];
e281682b
SM		 3922 u8 qpn[0x18];
3923
b4ff3a36 3924 u8 reserved_at_60[0x20];
e281682b
SM		 3925
3926 u8 opt_param_mask[0x20];
3927
b4ff3a36 3928 u8 reserved_at_a0[0x20];
e281682b
SM		 3929
3930 struct mlx5_ifc_qpc_bits qpc;
3931
b4ff3a36 3932 u8 reserved_at_800[0x80];
e281682b
SM		 3933};
3934
3935struct mlx5_ifc_rtr2rts_qp_out_bits {
3936 u8 status[0x8];
b4ff3a36 3937 u8 reserved_at_8[0x18];
e281682b
SM		 3938
3939 u8 syndrome[0x20];
3940
b4ff3a36 3941 u8 reserved_at_40[0x40];
e281682b
SM		 3942};
3943
3944struct mlx5_ifc_rtr2rts_qp_in_bits {
3945 u8 opcode[0x10];
4ac63ec7 3946 u8 uid[0x10];
e281682b 3947
b4ff3a36 3948 u8 reserved_at_20[0x10];
e281682b
SM		 3949 u8 op_mod[0x10];
3950
b4ff3a36 3951 u8 reserved_at_40[0x8];
e281682b
SM		 3952 u8 qpn[0x18];
3953
b4ff3a36 3954 u8 reserved_at_60[0x20];
e281682b
SM		 3955
3956 u8 opt_param_mask[0x20];
3957
b4ff3a36 3958 u8 reserved_at_a0[0x20];
e281682b
SM		 3959
3960 struct mlx5_ifc_qpc_bits qpc;
3961
b4ff3a36 3962 u8 reserved_at_800[0x80];
e281682b
SM		 3963};
3964
3965struct mlx5_ifc_rst2init_qp_out_bits {
3966 u8 status[0x8];
b4ff3a36 3967 u8 reserved_at_8[0x18];
e281682b
SM		 3968
3969 u8 syndrome[0x20];
3970
b4ff3a36 3971 u8 reserved_at_40[0x40];
e281682b
SM		 3972};
3973
3974struct mlx5_ifc_rst2init_qp_in_bits {
3975 u8 opcode[0x10];
4ac63ec7 3976 u8 uid[0x10];
e281682b 3977
b4ff3a36 3978 u8 reserved_at_20[0x10];
e281682b
SM		 3979 u8 op_mod[0x10];
3980
b4ff3a36 3981 u8 reserved_at_40[0x8];
e281682b
SM		 3982 u8 qpn[0x18];
3983
b4ff3a36 3984 u8 reserved_at_60[0x20];
e281682b
SM		 3985
3986 u8 opt_param_mask[0x20];
3987
b4ff3a36 3988 u8 reserved_at_a0[0x20];
e281682b
SM		 3989
3990 struct mlx5_ifc_qpc_bits qpc;
3991
b4ff3a36 3992 u8 reserved_at_800[0x80];
e281682b
SM		 3993};
3994
7486216b
SM		 3995struct mlx5_ifc_query_xrq_out_bits {
3996 u8 status[0x8];
3997 u8 reserved_at_8[0x18];
3998
3999 u8 syndrome[0x20];
4000
4001 u8 reserved_at_40[0x40];
4002
4003 struct mlx5_ifc_xrqc_bits xrq_context;
4004};
4005
4006struct mlx5_ifc_query_xrq_in_bits {
4007 u8 opcode[0x10];
4008 u8 reserved_at_10[0x10];
4009
4010 u8 reserved_at_20[0x10];
4011 u8 op_mod[0x10];
4012
4013 u8 reserved_at_40[0x8];
4014 u8 xrqn[0x18];
4015
4016 u8 reserved_at_60[0x20];
4017};
4018
e281682b
SM		 4019struct mlx5_ifc_query_xrc_srq_out_bits {
4020 u8 status[0x8];
b4ff3a36 4021 u8 reserved_at_8[0x18];
e281682b
SM		 4022
4023 u8 syndrome[0x20];
4024
b4ff3a36 4025 u8 reserved_at_40[0x40];
e281682b
SM		 4026
4027 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4028
b4ff3a36 4029 u8 reserved_at_280[0x600];
e281682b
SM		 4030
4031 u8 pas[0][0x40];
4032};
4033
4034struct mlx5_ifc_query_xrc_srq_in_bits {
4035 u8 opcode[0x10];
b4ff3a36 4036 u8 reserved_at_10[0x10];
e281682b 4037
b4ff3a36 4038 u8 reserved_at_20[0x10];
e281682b
SM		 4039 u8 op_mod[0x10];
4040
b4ff3a36 4041 u8 reserved_at_40[0x8];
e281682b
SM		 4042 u8 xrc_srqn[0x18];
4043
b4ff3a36 4044 u8 reserved_at_60[0x20];
e281682b
SM		 4045};
4046
4047enum {
4048 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4049 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4050};
4051
4052struct mlx5_ifc_query_vport_state_out_bits {
4053 u8 status[0x8];
b4ff3a36 4054 u8 reserved_at_8[0x18];
e281682b
SM		 4055
4056 u8 syndrome[0x20];
4057
b4ff3a36 4058 u8 reserved_at_40[0x20];
e281682b 4059
b4ff3a36 4060 u8 reserved_at_60[0x18];
e281682b
SM		 4061 u8 admin_state[0x4];
4062 u8 state[0x4];
4063};
4064
4065enum {
cc9c82a8
EBE		 4066 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4067 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 4068};
4069
fd4572b3
ED		 4070struct mlx5_ifc_arm_monitor_counter_in_bits {
4071 u8 opcode[0x10];
4072 u8 uid[0x10];
4073
4074 u8 reserved_at_20[0x10];
4075 u8 op_mod[0x10];
4076
4077 u8 reserved_at_40[0x20];
4078
4079 u8 reserved_at_60[0x20];
4080};
4081
4082struct mlx5_ifc_arm_monitor_counter_out_bits {
4083 u8 status[0x8];
4084 u8 reserved_at_8[0x18];
4085
4086 u8 syndrome[0x20];
4087
4088 u8 reserved_at_40[0x40];
4089};
4090
4091enum {
4092 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4093 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4094};
4095
4096enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 4097 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4098 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4099 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4100 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4101 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4102 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 4103};
4104
4105enum {
4c8b8518 4106 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 4107};
4108
4109struct mlx5_ifc_monitor_counter_output_bits {
4110 u8 reserved_at_0[0x4];
4111 u8 type[0x4];
4112 u8 reserved_at_8[0x8];
4113 u8 counter[0x10];
4114
4115 u8 counter_group_id[0x20];
4116};
4117
4118#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4119#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4120#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4121 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4122
4123struct mlx5_ifc_set_monitor_counter_in_bits {
4124 u8 opcode[0x10];
4125 u8 uid[0x10];
4126
4127 u8 reserved_at_20[0x10];
4128 u8 op_mod[0x10];
4129
4130 u8 reserved_at_40[0x10];
4131 u8 num_of_counters[0x10];
4132
4133 u8 reserved_at_60[0x20];
4134
4135 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4136};
4137
4138struct mlx5_ifc_set_monitor_counter_out_bits {
4139 u8 status[0x8];
4140 u8 reserved_at_8[0x18];
4141
4142 u8 syndrome[0x20];
4143
4144 u8 reserved_at_40[0x40];
4145};
4146
e281682b
SM		 4147struct mlx5_ifc_query_vport_state_in_bits {
4148 u8 opcode[0x10];
b4ff3a36 4149 u8 reserved_at_10[0x10];
e281682b 4150
b4ff3a36 4151 u8 reserved_at_20[0x10];
e281682b
SM		 4152 u8 op_mod[0x10];
4153
4154 u8 other_vport[0x1];
b4ff3a36 4155 u8 reserved_at_41[0xf];
e281682b
SM		 4156 u8 vport_number[0x10];
4157
b4ff3a36 4158 u8 reserved_at_60[0x20];
e281682b
SM		 4159};
4160
61c5b5c9
MS		 4161struct mlx5_ifc_query_vnic_env_out_bits {
4162 u8 status[0x8];
4163 u8 reserved_at_8[0x18];
4164
4165 u8 syndrome[0x20];
4166
4167 u8 reserved_at_40[0x40];
4168
4169 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4170};
4171
4172enum {
4173 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4174};
4175
4176struct mlx5_ifc_query_vnic_env_in_bits {
4177 u8 opcode[0x10];
4178 u8 reserved_at_10[0x10];
4179
4180 u8 reserved_at_20[0x10];
4181 u8 op_mod[0x10];
4182
4183 u8 other_vport[0x1];
4184 u8 reserved_at_41[0xf];
4185 u8 vport_number[0x10];
4186
4187 u8 reserved_at_60[0x20];
4188};
4189
e281682b
SM		 4190struct mlx5_ifc_query_vport_counter_out_bits {
4191 u8 status[0x8];
b4ff3a36 4192 u8 reserved_at_8[0x18];
e281682b
SM		 4193
4194 u8 syndrome[0x20];
4195
b4ff3a36 4196 u8 reserved_at_40[0x40];
e281682b
SM		 4197
4198 struct mlx5_ifc_traffic_counter_bits received_errors;
4199
4200 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4201
4202 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4203
4204 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4205
4206 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4207
4208 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4209
4210 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4211
4212 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4213
4214 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4215
4216 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4217
4218 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4219
4220 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4221
b4ff3a36 4222 u8 reserved_at_680[0xa00];
e281682b
SM		 4223};
4224
4225enum {
4226 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4227};
4228
4229struct mlx5_ifc_query_vport_counter_in_bits {
4230 u8 opcode[0x10];
b4ff3a36 4231 u8 reserved_at_10[0x10];
e281682b 4232
b4ff3a36 4233 u8 reserved_at_20[0x10];
e281682b
SM		 4234 u8 op_mod[0x10];
4235
4236 u8 other_vport[0x1];
b54ba277
MY		 4237 u8 reserved_at_41[0xb];
4238 u8 port_num[0x4];
e281682b
SM		 4239 u8 vport_number[0x10];
4240
b4ff3a36 4241 u8 reserved_at_60[0x60];
e281682b
SM		 4242
4243 u8 clear[0x1];
b4ff3a36 4244 u8 reserved_at_c1[0x1f];
e281682b 4245
b4ff3a36 4246 u8 reserved_at_e0[0x20];
e281682b
SM		 4247};
4248
4249struct mlx5_ifc_query_tis_out_bits {
4250 u8 status[0x8];
b4ff3a36 4251 u8 reserved_at_8[0x18];
e281682b
SM		 4252
4253 u8 syndrome[0x20];
4254
b4ff3a36 4255 u8 reserved_at_40[0x40];
e281682b
SM		 4256
4257 struct mlx5_ifc_tisc_bits tis_context;
4258};
4259
4260struct mlx5_ifc_query_tis_in_bits {
4261 u8 opcode[0x10];
b4ff3a36 4262 u8 reserved_at_10[0x10];
e281682b 4263
b4ff3a36 4264 u8 reserved_at_20[0x10];
e281682b
SM		 4265 u8 op_mod[0x10];
4266
b4ff3a36 4267 u8 reserved_at_40[0x8];
e281682b
SM		 4268 u8 tisn[0x18];
4269
b4ff3a36 4270 u8 reserved_at_60[0x20];
e281682b
SM		 4271};
4272
4273struct mlx5_ifc_query_tir_out_bits {
4274 u8 status[0x8];
b4ff3a36 4275 u8 reserved_at_8[0x18];
e281682b
SM		 4276
4277 u8 syndrome[0x20];
4278
b4ff3a36 4279 u8 reserved_at_40[0xc0];
e281682b
SM		 4280
4281 struct mlx5_ifc_tirc_bits tir_context;
4282};
4283
4284struct mlx5_ifc_query_tir_in_bits {
4285 u8 opcode[0x10];
b4ff3a36 4286 u8 reserved_at_10[0x10];
e281682b 4287
b4ff3a36 4288 u8 reserved_at_20[0x10];
e281682b
SM		 4289 u8 op_mod[0x10];
4290
b4ff3a36 4291 u8 reserved_at_40[0x8];
e281682b
SM		 4292 u8 tirn[0x18];
4293
b4ff3a36 4294 u8 reserved_at_60[0x20];
e281682b
SM		 4295};
4296
4297struct mlx5_ifc_query_srq_out_bits {
4298 u8 status[0x8];
b4ff3a36 4299 u8 reserved_at_8[0x18];
e281682b
SM		 4300
4301 u8 syndrome[0x20];
4302
b4ff3a36 4303 u8 reserved_at_40[0x40];
e281682b
SM		 4304
4305 struct mlx5_ifc_srqc_bits srq_context_entry;
4306
b4ff3a36 4307 u8 reserved_at_280[0x600];
e281682b
SM		 4308
4309 u8 pas[0][0x40];
4310};
4311
4312struct mlx5_ifc_query_srq_in_bits {
4313 u8 opcode[0x10];
b4ff3a36 4314 u8 reserved_at_10[0x10];
e281682b 4315
b4ff3a36 4316 u8 reserved_at_20[0x10];
e281682b
SM		 4317 u8 op_mod[0x10];
4318
b4ff3a36 4319 u8 reserved_at_40[0x8];
e281682b
SM		 4320 u8 srqn[0x18];
4321
b4ff3a36 4322 u8 reserved_at_60[0x20];
e281682b
SM		 4323};
4324
4325struct mlx5_ifc_query_sq_out_bits {
4326 u8 status[0x8];
b4ff3a36 4327 u8 reserved_at_8[0x18];
e281682b
SM		 4328
4329 u8 syndrome[0x20];
4330
b4ff3a36 4331 u8 reserved_at_40[0xc0];
e281682b
SM		 4332
4333 struct mlx5_ifc_sqc_bits sq_context;
4334};
4335
4336struct mlx5_ifc_query_sq_in_bits {
4337 u8 opcode[0x10];
b4ff3a36 4338 u8 reserved_at_10[0x10];
e281682b 4339
b4ff3a36 4340 u8 reserved_at_20[0x10];
e281682b
SM		 4341 u8 op_mod[0x10];
4342
b4ff3a36 4343 u8 reserved_at_40[0x8];
e281682b
SM		 4344 u8 sqn[0x18];
4345
b4ff3a36 4346 u8 reserved_at_60[0x20];
e281682b
SM		 4347};
4348
4349struct mlx5_ifc_query_special_contexts_out_bits {
4350 u8 status[0x8];
b4ff3a36 4351 u8 reserved_at_8[0x18];
e281682b
SM		 4352
4353 u8 syndrome[0x20];
4354
ec22eb53 4355 u8 dump_fill_mkey[0x20];
e281682b
SM		 4356
4357 u8 resd_lkey[0x20];
bcda1aca
AK		 4358
4359 u8 null_mkey[0x20];
4360
4361 u8 reserved_at_a0[0x60];
e281682b
SM		 4362};
4363
4364struct mlx5_ifc_query_special_contexts_in_bits {
4365 u8 opcode[0x10];
b4ff3a36 4366 u8 reserved_at_10[0x10];
e281682b 4367
b4ff3a36 4368 u8 reserved_at_20[0x10];
e281682b
SM		 4369 u8 op_mod[0x10];
4370
b4ff3a36 4371 u8 reserved_at_40[0x40];
e281682b
SM		 4372};
4373
813f8540
MHY		 4374struct mlx5_ifc_query_scheduling_element_out_bits {
4375 u8 opcode[0x10];
4376 u8 reserved_at_10[0x10];
4377
4378 u8 reserved_at_20[0x10];
4379 u8 op_mod[0x10];
4380
4381 u8 reserved_at_40[0xc0];
4382
4383 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4384
4385 u8 reserved_at_300[0x100];
4386};
4387
4388enum {
4389 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4390};
4391
4392struct mlx5_ifc_query_scheduling_element_in_bits {
4393 u8 opcode[0x10];
4394 u8 reserved_at_10[0x10];
4395
4396 u8 reserved_at_20[0x10];
4397 u8 op_mod[0x10];
4398
4399 u8 scheduling_hierarchy[0x8];
4400 u8 reserved_at_48[0x18];
4401
4402 u8 scheduling_element_id[0x20];
4403
4404 u8 reserved_at_80[0x180];
4405};
4406
e281682b
SM		 4407struct mlx5_ifc_query_rqt_out_bits {
4408 u8 status[0x8];
b4ff3a36 4409 u8 reserved_at_8[0x18];
e281682b
SM		 4410
4411 u8 syndrome[0x20];
4412
b4ff3a36 4413 u8 reserved_at_40[0xc0];
e281682b
SM		 4414
4415 struct mlx5_ifc_rqtc_bits rqt_context;
4416};
4417
4418struct mlx5_ifc_query_rqt_in_bits {
4419 u8 opcode[0x10];
b4ff3a36 4420 u8 reserved_at_10[0x10];
e281682b 4421
b4ff3a36 4422 u8 reserved_at_20[0x10];
e281682b
SM		 4423 u8 op_mod[0x10];
4424
b4ff3a36 4425 u8 reserved_at_40[0x8];
e281682b
SM		 4426 u8 rqtn[0x18];
4427
b4ff3a36 4428 u8 reserved_at_60[0x20];
e281682b
SM		 4429};
4430
4431struct mlx5_ifc_query_rq_out_bits {
4432 u8 status[0x8];
b4ff3a36 4433 u8 reserved_at_8[0x18];
e281682b
SM		 4434
4435 u8 syndrome[0x20];
4436
b4ff3a36 4437 u8 reserved_at_40[0xc0];
e281682b
SM		 4438
4439 struct mlx5_ifc_rqc_bits rq_context;
4440};
4441
4442struct mlx5_ifc_query_rq_in_bits {
4443 u8 opcode[0x10];
b4ff3a36 4444 u8 reserved_at_10[0x10];
e281682b 4445
b4ff3a36 4446 u8 reserved_at_20[0x10];
e281682b
SM		 4447 u8 op_mod[0x10];
4448
b4ff3a36 4449 u8 reserved_at_40[0x8];
e281682b
SM		 4450 u8 rqn[0x18];
4451
b4ff3a36 4452 u8 reserved_at_60[0x20];
e281682b
SM		 4453};
4454
4455struct mlx5_ifc_query_roce_address_out_bits {
4456 u8 status[0x8];
b4ff3a36 4457 u8 reserved_at_8[0x18];
e281682b
SM		 4458
4459 u8 syndrome[0x20];
4460
b4ff3a36 4461 u8 reserved_at_40[0x40];
e281682b
SM		 4462
4463 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4464};
4465
4466struct mlx5_ifc_query_roce_address_in_bits {
4467 u8 opcode[0x10];
b4ff3a36 4468 u8 reserved_at_10[0x10];
e281682b 4469
b4ff3a36 4470 u8 reserved_at_20[0x10];
e281682b
SM		 4471 u8 op_mod[0x10];
4472
4473 u8 roce_address_index[0x10];
32f69e4b
DJ		 4474 u8 reserved_at_50[0xc];
4475 u8 vhca_port_num[0x4];
e281682b 4476
b4ff3a36 4477 u8 reserved_at_60[0x20];
e281682b
SM		 4478};
4479
4480struct mlx5_ifc_query_rmp_out_bits {
4481 u8 status[0x8];
b4ff3a36 4482 u8 reserved_at_8[0x18];
e281682b
SM		 4483
4484 u8 syndrome[0x20];
4485
b4ff3a36 4486 u8 reserved_at_40[0xc0];
e281682b
SM		 4487
4488 struct mlx5_ifc_rmpc_bits rmp_context;
4489};
4490
4491struct mlx5_ifc_query_rmp_in_bits {
4492 u8 opcode[0x10];
b4ff3a36 4493 u8 reserved_at_10[0x10];
e281682b 4494
b4ff3a36 4495 u8 reserved_at_20[0x10];
e281682b
SM		 4496 u8 op_mod[0x10];
4497
b4ff3a36 4498 u8 reserved_at_40[0x8];
e281682b
SM		 4499 u8 rmpn[0x18];
4500
b4ff3a36 4501 u8 reserved_at_60[0x20];
e281682b
SM		 4502};
4503
4504struct mlx5_ifc_query_qp_out_bits {
4505 u8 status[0x8];
b4ff3a36 4506 u8 reserved_at_8[0x18];
e281682b
SM		 4507
4508 u8 syndrome[0x20];
4509
b4ff3a36 4510 u8 reserved_at_40[0x40];
e281682b
SM		 4511
4512 u8 opt_param_mask[0x20];
4513
b4ff3a36 4514 u8 reserved_at_a0[0x20];
e281682b
SM		 4515
4516 struct mlx5_ifc_qpc_bits qpc;
4517
b4ff3a36 4518 u8 reserved_at_800[0x80];
e281682b
SM		 4519
4520 u8 pas[0][0x40];
4521};
4522
4523struct mlx5_ifc_query_qp_in_bits {
4524 u8 opcode[0x10];
b4ff3a36 4525 u8 reserved_at_10[0x10];
e281682b 4526
b4ff3a36 4527 u8 reserved_at_20[0x10];
e281682b
SM		 4528 u8 op_mod[0x10];
4529
b4ff3a36 4530 u8 reserved_at_40[0x8];
e281682b
SM		 4531 u8 qpn[0x18];
4532
b4ff3a36 4533 u8 reserved_at_60[0x20];
e281682b
SM		 4534};
4535
4536struct mlx5_ifc_query_q_counter_out_bits {
4537 u8 status[0x8];
b4ff3a36 4538 u8 reserved_at_8[0x18];
e281682b
SM		 4539
4540 u8 syndrome[0x20];
4541
b4ff3a36 4542 u8 reserved_at_40[0x40];
e281682b
SM		 4543
4544 u8 rx_write_requests[0x20];
4545
b4ff3a36 4546 u8 reserved_at_a0[0x20];
e281682b
SM		 4547
4548 u8 rx_read_requests[0x20];
4549
b4ff3a36 4550 u8 reserved_at_e0[0x20];
e281682b
SM		 4551
4552 u8 rx_atomic_requests[0x20];
4553
b4ff3a36 4554 u8 reserved_at_120[0x20];
e281682b
SM		 4555
4556 u8 rx_dct_connect[0x20];
4557
b4ff3a36 4558 u8 reserved_at_160[0x20];
e281682b
SM		 4559
4560 u8 out_of_buffer[0x20];
4561
b4ff3a36 4562 u8 reserved_at_1a0[0x20];
e281682b
SM		 4563
4564 u8 out_of_sequence[0x20];
4565
7486216b
SM		 4566 u8 reserved_at_1e0[0x20];
4567
4568 u8 duplicate_request[0x20];
4569
4570 u8 reserved_at_220[0x20];
4571
4572 u8 rnr_nak_retry_err[0x20];
4573
4574 u8 reserved_at_260[0x20];
4575
4576 u8 packet_seq_err[0x20];
4577
4578 u8 reserved_at_2a0[0x20];
4579
4580 u8 implied_nak_seq_err[0x20];
4581
4582 u8 reserved_at_2e0[0x20];
4583
4584 u8 local_ack_timeout_err[0x20];
4585
58dcb60a
PP		 4586 u8 reserved_at_320[0xa0];
4587
4588 u8 resp_local_length_error[0x20];
4589
4590 u8 req_local_length_error[0x20];
4591
4592 u8 resp_local_qp_error[0x20];
4593
4594 u8 local_operation_error[0x20];
4595
4596 u8 resp_local_protection[0x20];
4597
4598 u8 req_local_protection[0x20];
4599
4600 u8 resp_cqe_error[0x20];
4601
4602 u8 req_cqe_error[0x20];
4603
4604 u8 req_mw_binding[0x20];
4605
4606 u8 req_bad_response[0x20];
4607
4608 u8 req_remote_invalid_request[0x20];
4609
4610 u8 resp_remote_invalid_request[0x20];
4611
4612 u8 req_remote_access_errors[0x20];
4613
4614 u8 resp_remote_access_errors[0x20];
4615
4616 u8 req_remote_operation_errors[0x20];
4617
4618 u8 req_transport_retries_exceeded[0x20];
4619
4620 u8 cq_overflow[0x20];
4621
4622 u8 resp_cqe_flush_error[0x20];
4623
4624 u8 req_cqe_flush_error[0x20];
4625
4626 u8 reserved_at_620[0x1e0];
e281682b
SM		 4627};
4628
4629struct mlx5_ifc_query_q_counter_in_bits {
4630 u8 opcode[0x10];
b4ff3a36 4631 u8 reserved_at_10[0x10];
e281682b 4632
b4ff3a36 4633 u8 reserved_at_20[0x10];
e281682b
SM		 4634 u8 op_mod[0x10];
4635
b4ff3a36 4636 u8 reserved_at_40[0x80];
e281682b
SM		 4637
4638 u8 clear[0x1];
b4ff3a36 4639 u8 reserved_at_c1[0x1f];
e281682b 4640
b4ff3a36 4641 u8 reserved_at_e0[0x18];
e281682b
SM		 4642 u8 counter_set_id[0x8];
4643};
4644
4645struct mlx5_ifc_query_pages_out_bits {
4646 u8 status[0x8];
b4ff3a36 4647 u8 reserved_at_8[0x18];
e281682b
SM		 4648
4649 u8 syndrome[0x20];
4650
591905ba
BW		 4651 u8 embedded_cpu_function[0x1];
4652 u8 reserved_at_41[0xf];
e281682b
SM		 4653 u8 function_id[0x10];
4654
4655 u8 num_pages[0x20];
4656};
4657
4658enum {
4659 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4660 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4661 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4662};
4663
4664struct mlx5_ifc_query_pages_in_bits {
4665 u8 opcode[0x10];
b4ff3a36 4666 u8 reserved_at_10[0x10];
e281682b 4667
b4ff3a36 4668 u8 reserved_at_20[0x10];
e281682b
SM		 4669 u8 op_mod[0x10];
4670
591905ba
BW		 4671 u8 embedded_cpu_function[0x1];
4672 u8 reserved_at_41[0xf];
e281682b
SM		 4673 u8 function_id[0x10];
4674
b4ff3a36 4675 u8 reserved_at_60[0x20];
e281682b
SM		 4676};
4677
4678struct mlx5_ifc_query_nic_vport_context_out_bits {
4679 u8 status[0x8];
b4ff3a36 4680 u8 reserved_at_8[0x18];
e281682b
SM		 4681
4682 u8 syndrome[0x20];
4683
b4ff3a36 4684 u8 reserved_at_40[0x40];
e281682b
SM		 4685
4686 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4687};
4688
4689struct mlx5_ifc_query_nic_vport_context_in_bits {
4690 u8 opcode[0x10];
b4ff3a36 4691 u8 reserved_at_10[0x10];
e281682b 4692
b4ff3a36 4693 u8 reserved_at_20[0x10];
e281682b
SM		 4694 u8 op_mod[0x10];
4695
4696 u8 other_vport[0x1];
b4ff3a36 4697 u8 reserved_at_41[0xf];
e281682b
SM		 4698 u8 vport_number[0x10];
4699
b4ff3a36 4700 u8 reserved_at_60[0x5];
e281682b 4701 u8 allowed_list_type[0x3];
b4ff3a36 4702 u8 reserved_at_68[0x18];
e281682b
SM		 4703};
4704
4705struct mlx5_ifc_query_mkey_out_bits {
4706 u8 status[0x8];
b4ff3a36 4707 u8 reserved_at_8[0x18];
e281682b
SM		 4708
4709 u8 syndrome[0x20];
4710
b4ff3a36 4711 u8 reserved_at_40[0x40];
e281682b
SM		 4712
4713 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4714
b4ff3a36 4715 u8 reserved_at_280[0x600];
e281682b
SM		 4716
4717 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4718
4719 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4720};
4721
4722struct mlx5_ifc_query_mkey_in_bits {
4723 u8 opcode[0x10];
b4ff3a36 4724 u8 reserved_at_10[0x10];
e281682b 4725
b4ff3a36 4726 u8 reserved_at_20[0x10];
e281682b
SM		 4727 u8 op_mod[0x10];
4728
b4ff3a36 4729 u8 reserved_at_40[0x8];
e281682b
SM		 4730 u8 mkey_index[0x18];
4731
4732 u8 pg_access[0x1];
b4ff3a36 4733 u8 reserved_at_61[0x1f];
e281682b
SM		 4734};
4735
4736struct mlx5_ifc_query_mad_demux_out_bits {
4737 u8 status[0x8];
b4ff3a36 4738 u8 reserved_at_8[0x18];
e281682b
SM		 4739
4740 u8 syndrome[0x20];
4741
b4ff3a36 4742 u8 reserved_at_40[0x40];
e281682b
SM		 4743
4744 u8 mad_dumux_parameters_block[0x20];
4745};
4746
4747struct mlx5_ifc_query_mad_demux_in_bits {
4748 u8 opcode[0x10];
b4ff3a36 4749 u8 reserved_at_10[0x10];
e281682b 4750
b4ff3a36 4751 u8 reserved_at_20[0x10];
e281682b
SM		 4752 u8 op_mod[0x10];
4753
b4ff3a36 4754 u8 reserved_at_40[0x40];
e281682b
SM		 4755};
4756
4757struct mlx5_ifc_query_l2_table_entry_out_bits {
4758 u8 status[0x8];
b4ff3a36 4759 u8 reserved_at_8[0x18];
e281682b
SM		 4760
4761 u8 syndrome[0x20];
4762
b4ff3a36 4763 u8 reserved_at_40[0xa0];
e281682b 4764
b4ff3a36 4765 u8 reserved_at_e0[0x13];
e281682b
SM		 4766 u8 vlan_valid[0x1];
4767 u8 vlan[0xc];
4768
4769 struct mlx5_ifc_mac_address_layout_bits mac_address;
4770
b4ff3a36 4771 u8 reserved_at_140[0xc0];
e281682b
SM		 4772};
4773
4774struct mlx5_ifc_query_l2_table_entry_in_bits {
4775 u8 opcode[0x10];
b4ff3a36 4776 u8 reserved_at_10[0x10];
e281682b 4777
b4ff3a36 4778 u8 reserved_at_20[0x10];
e281682b
SM		 4779 u8 op_mod[0x10];
4780
b4ff3a36 4781 u8 reserved_at_40[0x60];
e281682b 4782
b4ff3a36 4783 u8 reserved_at_a0[0x8];
e281682b
SM		 4784 u8 table_index[0x18];
4785
b4ff3a36 4786 u8 reserved_at_c0[0x140];
e281682b
SM		 4787};
4788
4789struct mlx5_ifc_query_issi_out_bits {
4790 u8 status[0x8];
b4ff3a36 4791 u8 reserved_at_8[0x18];
e281682b
SM		 4792
4793 u8 syndrome[0x20];
4794
b4ff3a36 4795 u8 reserved_at_40[0x10];
e281682b
SM		 4796 u8 current_issi[0x10];
4797
b4ff3a36 4798 u8 reserved_at_60[0xa0];
e281682b 4799
b4ff3a36 4800 u8 reserved_at_100[76][0x8];
e281682b
SM		 4801 u8 supported_issi_dw0[0x20];
4802};
4803
4804struct mlx5_ifc_query_issi_in_bits {
4805 u8 opcode[0x10];
b4ff3a36 4806 u8 reserved_at_10[0x10];
e281682b 4807
b4ff3a36 4808 u8 reserved_at_20[0x10];
e281682b
SM		 4809 u8 op_mod[0x10];
4810
b4ff3a36 4811 u8 reserved_at_40[0x40];
e281682b
SM		 4812};
4813
0dbc6fe0
SM		 4814struct mlx5_ifc_set_driver_version_out_bits {
4815 u8 status[0x8];
4816 u8 reserved_0[0x18];
4817
4818 u8 syndrome[0x20];
4819 u8 reserved_1[0x40];
4820};
4821
4822struct mlx5_ifc_set_driver_version_in_bits {
4823 u8 opcode[0x10];
4824 u8 reserved_0[0x10];
4825
4826 u8 reserved_1[0x10];
4827 u8 op_mod[0x10];
4828
4829 u8 reserved_2[0x40];
4830 u8 driver_version[64][0x8];
4831};
4832
e281682b
SM		 4833struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4834 u8 status[0x8];
b4ff3a36 4835 u8 reserved_at_8[0x18];
e281682b
SM		 4836
4837 u8 syndrome[0x20];
4838
b4ff3a36 4839 u8 reserved_at_40[0x40];
e281682b
SM		 4840
4841 struct mlx5_ifc_pkey_bits pkey[0];
4842};
4843
4844struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4845 u8 opcode[0x10];
b4ff3a36 4846 u8 reserved_at_10[0x10];
e281682b 4847
b4ff3a36 4848 u8 reserved_at_20[0x10];
e281682b
SM		 4849 u8 op_mod[0x10];
4850
4851 u8 other_vport[0x1];
b4ff3a36 4852 u8 reserved_at_41[0xb];
707c4602 4853 u8 port_num[0x4];
e281682b
SM		 4854 u8 vport_number[0x10];
4855
b4ff3a36 4856 u8 reserved_at_60[0x10];
e281682b
SM		 4857 u8 pkey_index[0x10];
4858};
4859
eff901d3
EC		 4860enum {
4861 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4862 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4863 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4864};
4865
e281682b
SM		 4866struct mlx5_ifc_query_hca_vport_gid_out_bits {
4867 u8 status[0x8];
b4ff3a36 4868 u8 reserved_at_8[0x18];
e281682b
SM		 4869
4870 u8 syndrome[0x20];
4871
b4ff3a36 4872 u8 reserved_at_40[0x20];
e281682b
SM		 4873
4874 u8 gids_num[0x10];
b4ff3a36 4875 u8 reserved_at_70[0x10];
e281682b
SM		 4876
4877 struct mlx5_ifc_array128_auto_bits gid[0];
4878};
4879
4880struct mlx5_ifc_query_hca_vport_gid_in_bits {
4881 u8 opcode[0x10];
b4ff3a36 4882 u8 reserved_at_10[0x10];
e281682b 4883
b4ff3a36 4884 u8 reserved_at_20[0x10];
e281682b
SM		 4885 u8 op_mod[0x10];
4886
4887 u8 other_vport[0x1];
b4ff3a36 4888 u8 reserved_at_41[0xb];
707c4602 4889 u8 port_num[0x4];
e281682b
SM		 4890 u8 vport_number[0x10];
4891
b4ff3a36 4892 u8 reserved_at_60[0x10];
e281682b
SM		 4893 u8 gid_index[0x10];
4894};
4895
4896struct mlx5_ifc_query_hca_vport_context_out_bits {
4897 u8 status[0x8];
b4ff3a36 4898 u8 reserved_at_8[0x18];
e281682b
SM		 4899
4900 u8 syndrome[0x20];
4901
b4ff3a36 4902 u8 reserved_at_40[0x40];
e281682b
SM		 4903
4904 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4905};
4906
4907struct mlx5_ifc_query_hca_vport_context_in_bits {
4908 u8 opcode[0x10];
b4ff3a36 4909 u8 reserved_at_10[0x10];
e281682b 4910
b4ff3a36 4911 u8 reserved_at_20[0x10];
e281682b
SM		 4912 u8 op_mod[0x10];
4913
4914 u8 other_vport[0x1];
b4ff3a36 4915 u8 reserved_at_41[0xb];
707c4602 4916 u8 port_num[0x4];
e281682b
SM		 4917 u8 vport_number[0x10];
4918
b4ff3a36 4919 u8 reserved_at_60[0x20];
e281682b
SM		 4920};
4921
4922struct mlx5_ifc_query_hca_cap_out_bits {
4923 u8 status[0x8];
b4ff3a36 4924 u8 reserved_at_8[0x18];
e281682b
SM		 4925
4926 u8 syndrome[0x20];
4927
b4ff3a36 4928 u8 reserved_at_40[0x40];
e281682b
SM		 4929
4930 union mlx5_ifc_hca_cap_union_bits capability;
4931};
4932
4933struct mlx5_ifc_query_hca_cap_in_bits {
4934 u8 opcode[0x10];
b4ff3a36 4935 u8 reserved_at_10[0x10];
e281682b 4936
b4ff3a36 4937 u8 reserved_at_20[0x10];
e281682b
SM		 4938 u8 op_mod[0x10];
4939
b4ff3a36 4940 u8 reserved_at_40[0x40];
e281682b
SM		 4941};
4942
4943struct mlx5_ifc_query_flow_table_out_bits {
4944 u8 status[0x8];
b4ff3a36 4945 u8 reserved_at_8[0x18];
e281682b
SM		 4946
4947 u8 syndrome[0x20];
4948
b4ff3a36 4949 u8 reserved_at_40[0x80];
e281682b 4950
b4ff3a36 4951 u8 reserved_at_c0[0x8];
e281682b 4952 u8 level[0x8];
b4ff3a36 4953 u8 reserved_at_d0[0x8];
e281682b
SM		 4954 u8 log_size[0x8];
4955
b4ff3a36 4956 u8 reserved_at_e0[0x120];
e281682b
SM		 4957};
4958
4959struct mlx5_ifc_query_flow_table_in_bits {
4960 u8 opcode[0x10];
b4ff3a36 4961 u8 reserved_at_10[0x10];
e281682b 4962
b4ff3a36 4963 u8 reserved_at_20[0x10];
e281682b
SM		 4964 u8 op_mod[0x10];
4965
b4ff3a36 4966 u8 reserved_at_40[0x40];
e281682b
SM		 4967
4968 u8 table_type[0x8];
b4ff3a36 4969 u8 reserved_at_88[0x18];
e281682b 4970
b4ff3a36 4971 u8 reserved_at_a0[0x8];
e281682b
SM		 4972 u8 table_id[0x18];
4973
b4ff3a36 4974 u8 reserved_at_c0[0x140];
e281682b
SM		 4975};
4976
4977struct mlx5_ifc_query_fte_out_bits {
4978 u8 status[0x8];
b4ff3a36 4979 u8 reserved_at_8[0x18];
e281682b
SM		 4980
4981 u8 syndrome[0x20];
4982
b4ff3a36 4983 u8 reserved_at_40[0x1c0];
e281682b
SM		 4984
4985 struct mlx5_ifc_flow_context_bits flow_context;
4986};
4987
4988struct mlx5_ifc_query_fte_in_bits {
4989 u8 opcode[0x10];
b4ff3a36 4990 u8 reserved_at_10[0x10];
e281682b 4991
b4ff3a36 4992 u8 reserved_at_20[0x10];
e281682b
SM		 4993 u8 op_mod[0x10];
4994
b4ff3a36 4995 u8 reserved_at_40[0x40];
e281682b
SM		 4996
4997 u8 table_type[0x8];
b4ff3a36 4998 u8 reserved_at_88[0x18];
e281682b 4999
b4ff3a36 5000 u8 reserved_at_a0[0x8];
e281682b
SM		 5001 u8 table_id[0x18];
5002
b4ff3a36 5003 u8 reserved_at_c0[0x40];
e281682b
SM		 5004
5005 u8 flow_index[0x20];
5006
b4ff3a36 5007 u8 reserved_at_120[0xe0];
e281682b
SM		 5008};
5009
5010enum {
5011 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5012 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5013 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 5014 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
b169e64a 5015 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
e281682b
SM		 5016};
5017
5018struct mlx5_ifc_query_flow_group_out_bits {
5019 u8 status[0x8];
b4ff3a36 5020 u8 reserved_at_8[0x18];
e281682b
SM		 5021
5022 u8 syndrome[0x20];
5023
b4ff3a36 5024 u8 reserved_at_40[0xa0];
e281682b
SM		 5025
5026 u8 start_flow_index[0x20];
5027
b4ff3a36 5028 u8 reserved_at_100[0x20];
e281682b
SM		 5029
5030 u8 end_flow_index[0x20];
5031
b4ff3a36 5032 u8 reserved_at_140[0xa0];
e281682b 5033
b4ff3a36 5034 u8 reserved_at_1e0[0x18];
e281682b
SM		 5035 u8 match_criteria_enable[0x8];
5036
5037 struct mlx5_ifc_fte_match_param_bits match_criteria;
5038
b4ff3a36 5039 u8 reserved_at_1200[0xe00];
e281682b
SM		 5040};
5041
5042struct mlx5_ifc_query_flow_group_in_bits {
5043 u8 opcode[0x10];
b4ff3a36 5044 u8 reserved_at_10[0x10];
e281682b 5045
b4ff3a36 5046 u8 reserved_at_20[0x10];
e281682b
SM		 5047 u8 op_mod[0x10];
5048
b4ff3a36 5049 u8 reserved_at_40[0x40];
e281682b
SM		 5050
5051 u8 table_type[0x8];
b4ff3a36 5052 u8 reserved_at_88[0x18];
e281682b 5053
b4ff3a36 5054 u8 reserved_at_a0[0x8];
e281682b
SM		 5055 u8 table_id[0x18];
5056
5057 u8 group_id[0x20];
5058
b4ff3a36 5059 u8 reserved_at_e0[0x120];
e281682b
SM		 5060};
5061
9dc0b289
AV		 5062struct mlx5_ifc_query_flow_counter_out_bits {
5063 u8 status[0x8];
5064 u8 reserved_at_8[0x18];
5065
5066 u8 syndrome[0x20];
5067
5068 u8 reserved_at_40[0x40];
5069
5070 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5071};
5072
5073struct mlx5_ifc_query_flow_counter_in_bits {
5074 u8 opcode[0x10];
5075 u8 reserved_at_10[0x10];
5076
5077 u8 reserved_at_20[0x10];
5078 u8 op_mod[0x10];
5079
5080 u8 reserved_at_40[0x80];
5081
5082 u8 clear[0x1];
5083 u8 reserved_at_c1[0xf];
5084 u8 num_of_counters[0x10];
5085
a8ffcc74 5086 u8 flow_counter_id[0x20];
9dc0b289
AV		 5087};
5088
d6666753
SM		 5089struct mlx5_ifc_query_esw_vport_context_out_bits {
5090 u8 status[0x8];
b4ff3a36 5091 u8 reserved_at_8[0x18];
d6666753
SM		 5092
5093 u8 syndrome[0x20];
5094
b4ff3a36 5095 u8 reserved_at_40[0x40];
d6666753
SM		 5096
5097 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5098};
5099
5100struct mlx5_ifc_query_esw_vport_context_in_bits {
5101 u8 opcode[0x10];
b4ff3a36 5102 u8 reserved_at_10[0x10];
d6666753 5103
b4ff3a36 5104 u8 reserved_at_20[0x10];
d6666753
SM		 5105 u8 op_mod[0x10];
5106
5107 u8 other_vport[0x1];
b4ff3a36 5108 u8 reserved_at_41[0xf];
d6666753
SM		 5109 u8 vport_number[0x10];
5110
b4ff3a36 5111 u8 reserved_at_60[0x20];
d6666753
SM		 5112};
5113
5114struct mlx5_ifc_modify_esw_vport_context_out_bits {
5115 u8 status[0x8];
b4ff3a36 5116 u8 reserved_at_8[0x18];
d6666753
SM		 5117
5118 u8 syndrome[0x20];
5119
b4ff3a36 5120 u8 reserved_at_40[0x40];
d6666753
SM		 5121};
5122
5123struct mlx5_ifc_esw_vport_context_fields_select_bits {
65c0f2c1
JL		 5124 u8 reserved_at_0[0x1b];
5125 u8 fdb_to_vport_reg_c_id[0x1];
d6666753
SM		 5126 u8 vport_cvlan_insert[0x1];
5127 u8 vport_svlan_insert[0x1];
5128 u8 vport_cvlan_strip[0x1];
5129 u8 vport_svlan_strip[0x1];
5130};
5131
5132struct mlx5_ifc_modify_esw_vport_context_in_bits {
5133 u8 opcode[0x10];
b4ff3a36 5134 u8 reserved_at_10[0x10];
d6666753 5135
b4ff3a36 5136 u8 reserved_at_20[0x10];
d6666753
SM		 5137 u8 op_mod[0x10];
5138
5139 u8 other_vport[0x1];
b4ff3a36 5140 u8 reserved_at_41[0xf];
d6666753
SM		 5141 u8 vport_number[0x10];
5142
5143 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5144
5145 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5146};
5147
e281682b
SM		 5148struct mlx5_ifc_query_eq_out_bits {
5149 u8 status[0x8];
b4ff3a36 5150 u8 reserved_at_8[0x18];
e281682b
SM		 5151
5152 u8 syndrome[0x20];
5153
b4ff3a36 5154 u8 reserved_at_40[0x40];
e281682b
SM		 5155
5156 struct mlx5_ifc_eqc_bits eq_context_entry;
5157
b4ff3a36 5158 u8 reserved_at_280[0x40];
e281682b
SM		 5159
5160 u8 event_bitmask[0x40];
5161
b4ff3a36 5162 u8 reserved_at_300[0x580];
e281682b
SM		 5163
5164 u8 pas[0][0x40];
5165};
5166
5167struct mlx5_ifc_query_eq_in_bits {
5168 u8 opcode[0x10];
b4ff3a36 5169 u8 reserved_at_10[0x10];
e281682b 5170
b4ff3a36 5171 u8 reserved_at_20[0x10];
e281682b
SM		 5172 u8 op_mod[0x10];
5173
b4ff3a36 5174 u8 reserved_at_40[0x18];
e281682b
SM		 5175 u8 eq_number[0x8];
5176
b4ff3a36 5177 u8 reserved_at_60[0x20];
e281682b
SM		 5178};
5179
60786f09 5180struct mlx5_ifc_packet_reformat_context_in_bits {
7adbde20 5181 u8 reserved_at_0[0x5];
60786f09 5182 u8 reformat_type[0x3];
7adbde20 5183 u8 reserved_at_8[0xe];
60786f09 5184 u8 reformat_data_size[0xa];
7adbde20
HHZ		 5185
5186 u8 reserved_at_20[0x10];
60786f09 5187 u8 reformat_data[2][0x8];
7adbde20 5188
60786f09 5189 u8 more_reformat_data[0][0x8];
7adbde20
HHZ		 5190};
5191
60786f09 5192struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 5193 u8 status[0x8];
5194 u8 reserved_at_8[0x18];
5195
5196 u8 syndrome[0x20];
5197
5198 u8 reserved_at_40[0xa0];
5199
60786f09 5200 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
7adbde20
HHZ		 5201};
5202
60786f09 5203struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 5204 u8 opcode[0x10];
5205 u8 reserved_at_10[0x10];
5206
5207 u8 reserved_at_20[0x10];
5208 u8 op_mod[0x10];
5209
60786f09 5210 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5211
5212 u8 reserved_at_60[0xa0];
5213};
5214
60786f09 5215struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5216 u8 status[0x8];
5217 u8 reserved_at_8[0x18];
5218
5219 u8 syndrome[0x20];
5220
60786f09 5221 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5222
5223 u8 reserved_at_60[0x20];
5224};
5225
e0e7a386 5226enum {
60786f09
MB		 5227 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5228 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 5229 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5230 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5231 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
e0e7a386
MB		 5232};
5233
60786f09 5234struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5235 u8 opcode[0x10];
5236 u8 reserved_at_10[0x10];
5237
5238 u8 reserved_at_20[0x10];
5239 u8 op_mod[0x10];
5240
5241 u8 reserved_at_40[0xa0];
5242
60786f09 5243 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 5244};
5245
60786f09 5246struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5247 u8 status[0x8];
5248 u8 reserved_at_8[0x18];
5249
5250 u8 syndrome[0x20];
5251
5252 u8 reserved_at_40[0x40];
5253};
5254
60786f09 5255struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5256 u8 opcode[0x10];
5257 u8 reserved_at_10[0x10];
5258
5259 u8 reserved_20[0x10];
5260 u8 op_mod[0x10];
5261
60786f09 5262 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5263
5264 u8 reserved_60[0x20];
5265};
5266
2a69cb9f
OG		 5267struct mlx5_ifc_set_action_in_bits {
5268 u8 action_type[0x4];
5269 u8 field[0xc];
5270 u8 reserved_at_10[0x3];
5271 u8 offset[0x5];
5272 u8 reserved_at_18[0x3];
5273 u8 length[0x5];
5274
5275 u8 data[0x20];
5276};
5277
5278struct mlx5_ifc_add_action_in_bits {
5279 u8 action_type[0x4];
5280 u8 field[0xc];
5281 u8 reserved_at_10[0x10];
5282
5283 u8 data[0x20];
5284};
5285
5286union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5287 struct mlx5_ifc_set_action_in_bits set_action_in;
5288 struct mlx5_ifc_add_action_in_bits add_action_in;
5289 u8 reserved_at_0[0x40];
5290};
5291
5292enum {
5293 MLX5_ACTION_TYPE_SET = 0x1,
5294 MLX5_ACTION_TYPE_ADD = 0x2,
5295};
5296
5297enum {
5298 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5299 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5300 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5301 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5302 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5303 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5304 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5305 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5306 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5307 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5308 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5309 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5310 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5311 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5312 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5313 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5314 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5315 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5316 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5317 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5318 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5319 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0eb69bb9 5320 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
0c0316f5 5321 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
65c0f2c1 5322 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
2a69cb9f
OG		 5323};
5324
5325struct mlx5_ifc_alloc_modify_header_context_out_bits {
5326 u8 status[0x8];
5327 u8 reserved_at_8[0x18];
5328
5329 u8 syndrome[0x20];
5330
5331 u8 modify_header_id[0x20];
5332
5333 u8 reserved_at_60[0x20];
5334};
5335
5336struct mlx5_ifc_alloc_modify_header_context_in_bits {
5337 u8 opcode[0x10];
5338 u8 reserved_at_10[0x10];
5339
5340 u8 reserved_at_20[0x10];
5341 u8 op_mod[0x10];
5342
5343 u8 reserved_at_40[0x20];
5344
5345 u8 table_type[0x8];
5346 u8 reserved_at_68[0x10];
5347 u8 num_of_actions[0x8];
5348
5349 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5350};
5351
5352struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5353 u8 status[0x8];
5354 u8 reserved_at_8[0x18];
5355
5356 u8 syndrome[0x20];
5357
5358 u8 reserved_at_40[0x40];
5359};
5360
5361struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5362 u8 opcode[0x10];
5363 u8 reserved_at_10[0x10];
5364
5365 u8 reserved_at_20[0x10];
5366 u8 op_mod[0x10];
5367
5368 u8 modify_header_id[0x20];
5369
5370 u8 reserved_at_60[0x20];
5371};
5372
e281682b
SM		 5373struct mlx5_ifc_query_dct_out_bits {
5374 u8 status[0x8];
b4ff3a36 5375 u8 reserved_at_8[0x18];
e281682b
SM		 5376
5377 u8 syndrome[0x20];
5378
b4ff3a36 5379 u8 reserved_at_40[0x40];
e281682b
SM		 5380
5381 struct mlx5_ifc_dctc_bits dct_context_entry;
5382
b4ff3a36 5383 u8 reserved_at_280[0x180];
e281682b
SM		 5384};
5385
5386struct mlx5_ifc_query_dct_in_bits {
5387 u8 opcode[0x10];
b4ff3a36 5388 u8 reserved_at_10[0x10];
e281682b 5389
b4ff3a36 5390 u8 reserved_at_20[0x10];
e281682b
SM		 5391 u8 op_mod[0x10];
5392
b4ff3a36 5393 u8 reserved_at_40[0x8];
e281682b
SM		 5394 u8 dctn[0x18];
5395
b4ff3a36 5396 u8 reserved_at_60[0x20];
e281682b
SM		 5397};
5398
5399struct mlx5_ifc_query_cq_out_bits {
5400 u8 status[0x8];
b4ff3a36 5401 u8 reserved_at_8[0x18];
e281682b
SM		 5402
5403 u8 syndrome[0x20];
5404
b4ff3a36 5405 u8 reserved_at_40[0x40];
e281682b
SM		 5406
5407 struct mlx5_ifc_cqc_bits cq_context;
5408
b4ff3a36 5409 u8 reserved_at_280[0x600];
e281682b
SM		 5410
5411 u8 pas[0][0x40];
5412};
5413
5414struct mlx5_ifc_query_cq_in_bits {
5415 u8 opcode[0x10];
b4ff3a36 5416 u8 reserved_at_10[0x10];
e281682b 5417
b4ff3a36 5418 u8 reserved_at_20[0x10];
e281682b
SM		 5419 u8 op_mod[0x10];
5420
b4ff3a36 5421 u8 reserved_at_40[0x8];
e281682b
SM		 5422 u8 cqn[0x18];
5423
b4ff3a36 5424 u8 reserved_at_60[0x20];
e281682b
SM		 5425};
5426
5427struct mlx5_ifc_query_cong_status_out_bits {
5428 u8 status[0x8];
b4ff3a36 5429 u8 reserved_at_8[0x18];
e281682b
SM		 5430
5431 u8 syndrome[0x20];
5432
b4ff3a36 5433 u8 reserved_at_40[0x20];
e281682b
SM		 5434
5435 u8 enable[0x1];
5436 u8 tag_enable[0x1];
b4ff3a36 5437 u8 reserved_at_62[0x1e];
e281682b
SM		 5438};
5439
5440struct mlx5_ifc_query_cong_status_in_bits {
5441 u8 opcode[0x10];
b4ff3a36 5442 u8 reserved_at_10[0x10];
e281682b 5443
b4ff3a36 5444 u8 reserved_at_20[0x10];
e281682b
SM		 5445 u8 op_mod[0x10];
5446
b4ff3a36 5447 u8 reserved_at_40[0x18];
e281682b
SM		 5448 u8 priority[0x4];
5449 u8 cong_protocol[0x4];
5450
b4ff3a36 5451 u8 reserved_at_60[0x20];
e281682b
SM		 5452};
5453
5454struct mlx5_ifc_query_cong_statistics_out_bits {
5455 u8 status[0x8];
b4ff3a36 5456 u8 reserved_at_8[0x18];
e281682b
SM		 5457
5458 u8 syndrome[0x20];
5459
b4ff3a36 5460 u8 reserved_at_40[0x40];
e281682b 5461
e1f24a79 5462 u8 rp_cur_flows[0x20];
e281682b
SM		 5463
5464 u8 sum_flows[0x20];
5465
e1f24a79 5466 u8 rp_cnp_ignored_high[0x20];
e281682b 5467
e1f24a79 5468 u8 rp_cnp_ignored_low[0x20];
e281682b 5469
e1f24a79 5470 u8 rp_cnp_handled_high[0x20];
e281682b 5471
e1f24a79 5472 u8 rp_cnp_handled_low[0x20];
e281682b 5473
b4ff3a36 5474 u8 reserved_at_140[0x100];
e281682b
SM		 5475
5476 u8 time_stamp_high[0x20];
5477
5478 u8 time_stamp_low[0x20];
5479
5480 u8 accumulators_period[0x20];
5481
e1f24a79 5482 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5483
e1f24a79 5484 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5485
e1f24a79 5486 u8 np_cnp_sent_high[0x20];
e281682b 5487
e1f24a79 5488 u8 np_cnp_sent_low[0x20];
e281682b 5489
b4ff3a36 5490 u8 reserved_at_320[0x560];
e281682b
SM		 5491};
5492
5493struct mlx5_ifc_query_cong_statistics_in_bits {
5494 u8 opcode[0x10];
b4ff3a36 5495 u8 reserved_at_10[0x10];
e281682b 5496
b4ff3a36 5497 u8 reserved_at_20[0x10];
e281682b
SM		 5498 u8 op_mod[0x10];
5499
5500 u8 clear[0x1];
b4ff3a36 5501 u8 reserved_at_41[0x1f];
e281682b 5502
b4ff3a36 5503 u8 reserved_at_60[0x20];
e281682b
SM		 5504};
5505
5506struct mlx5_ifc_query_cong_params_out_bits {
5507 u8 status[0x8];
b4ff3a36 5508 u8 reserved_at_8[0x18];
e281682b
SM		 5509
5510 u8 syndrome[0x20];
5511
b4ff3a36 5512 u8 reserved_at_40[0x40];
e281682b
SM		 5513
5514 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5515};
5516
5517struct mlx5_ifc_query_cong_params_in_bits {
5518 u8 opcode[0x10];
b4ff3a36 5519 u8 reserved_at_10[0x10];
e281682b 5520
b4ff3a36 5521 u8 reserved_at_20[0x10];
e281682b
SM		 5522 u8 op_mod[0x10];
5523
b4ff3a36 5524 u8 reserved_at_40[0x1c];
e281682b
SM		 5525 u8 cong_protocol[0x4];
5526
b4ff3a36 5527 u8 reserved_at_60[0x20];
e281682b
SM		 5528};
5529
5530struct mlx5_ifc_query_adapter_out_bits {
5531 u8 status[0x8];
b4ff3a36 5532 u8 reserved_at_8[0x18];
e281682b
SM		 5533
5534 u8 syndrome[0x20];
5535
b4ff3a36 5536 u8 reserved_at_40[0x40];
e281682b
SM		 5537
5538 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5539};
5540
5541struct mlx5_ifc_query_adapter_in_bits {
5542 u8 opcode[0x10];
b4ff3a36 5543 u8 reserved_at_10[0x10];
e281682b 5544
b4ff3a36 5545 u8 reserved_at_20[0x10];
e281682b
SM		 5546 u8 op_mod[0x10];
5547
b4ff3a36 5548 u8 reserved_at_40[0x40];
e281682b
SM		 5549};
5550
5551struct mlx5_ifc_qp_2rst_out_bits {
5552 u8 status[0x8];
b4ff3a36 5553 u8 reserved_at_8[0x18];
e281682b
SM		 5554
5555 u8 syndrome[0x20];
5556
b4ff3a36 5557 u8 reserved_at_40[0x40];
e281682b
SM		 5558};
5559
5560struct mlx5_ifc_qp_2rst_in_bits {
5561 u8 opcode[0x10];
4ac63ec7 5562 u8 uid[0x10];
e281682b 5563
b4ff3a36 5564 u8 reserved_at_20[0x10];
e281682b
SM		 5565 u8 op_mod[0x10];
5566
b4ff3a36 5567 u8 reserved_at_40[0x8];
e281682b
SM		 5568 u8 qpn[0x18];
5569
b4ff3a36 5570 u8 reserved_at_60[0x20];
e281682b
SM		 5571};
5572
5573struct mlx5_ifc_qp_2err_out_bits {
5574 u8 status[0x8];
b4ff3a36 5575 u8 reserved_at_8[0x18];
e281682b
SM		 5576
5577 u8 syndrome[0x20];
5578
b4ff3a36 5579 u8 reserved_at_40[0x40];
e281682b
SM		 5580};
5581
5582struct mlx5_ifc_qp_2err_in_bits {
5583 u8 opcode[0x10];
4ac63ec7 5584 u8 uid[0x10];
e281682b 5585
b4ff3a36 5586 u8 reserved_at_20[0x10];
e281682b
SM		 5587 u8 op_mod[0x10];
5588
b4ff3a36 5589 u8 reserved_at_40[0x8];
e281682b
SM		 5590 u8 qpn[0x18];
5591
b4ff3a36 5592 u8 reserved_at_60[0x20];
e281682b
SM		 5593};
5594
5595struct mlx5_ifc_page_fault_resume_out_bits {
5596 u8 status[0x8];
b4ff3a36 5597 u8 reserved_at_8[0x18];
e281682b
SM		 5598
5599 u8 syndrome[0x20];
5600
b4ff3a36 5601 u8 reserved_at_40[0x40];
e281682b
SM		 5602};
5603
5604struct mlx5_ifc_page_fault_resume_in_bits {
5605 u8 opcode[0x10];
b4ff3a36 5606 u8 reserved_at_10[0x10];
e281682b 5607
b4ff3a36 5608 u8 reserved_at_20[0x10];
e281682b
SM		 5609 u8 op_mod[0x10];
5610
5611 u8 error[0x1];
b4ff3a36 5612 u8 reserved_at_41[0x4];
223cdc72
AK		 5613 u8 page_fault_type[0x3];
5614 u8 wq_number[0x18];
e281682b 5615
223cdc72
AK		 5616 u8 reserved_at_60[0x8];
5617 u8 token[0x18];
e281682b
SM		 5618};
5619
5620struct mlx5_ifc_nop_out_bits {
5621 u8 status[0x8];
b4ff3a36 5622 u8 reserved_at_8[0x18];
e281682b
SM		 5623
5624 u8 syndrome[0x20];
5625
b4ff3a36 5626 u8 reserved_at_40[0x40];
e281682b
SM		 5627};
5628
5629struct mlx5_ifc_nop_in_bits {
5630 u8 opcode[0x10];
b4ff3a36 5631 u8 reserved_at_10[0x10];
e281682b 5632
b4ff3a36 5633 u8 reserved_at_20[0x10];
e281682b
SM		 5634 u8 op_mod[0x10];
5635
b4ff3a36 5636 u8 reserved_at_40[0x40];
e281682b
SM		 5637};
5638
5639struct mlx5_ifc_modify_vport_state_out_bits {
5640 u8 status[0x8];
b4ff3a36 5641 u8 reserved_at_8[0x18];
e281682b
SM		 5642
5643 u8 syndrome[0x20];
5644
b4ff3a36 5645 u8 reserved_at_40[0x40];
e281682b
SM		 5646};
5647
5648struct mlx5_ifc_modify_vport_state_in_bits {
5649 u8 opcode[0x10];
b4ff3a36 5650 u8 reserved_at_10[0x10];
e281682b 5651
b4ff3a36 5652 u8 reserved_at_20[0x10];
e281682b
SM		 5653 u8 op_mod[0x10];
5654
5655 u8 other_vport[0x1];
b4ff3a36 5656 u8 reserved_at_41[0xf];
e281682b
SM		 5657 u8 vport_number[0x10];
5658
b4ff3a36 5659 u8 reserved_at_60[0x18];
e281682b 5660 u8 admin_state[0x4];
b4ff3a36 5661 u8 reserved_at_7c[0x4];
e281682b
SM		 5662};
5663
5664struct mlx5_ifc_modify_tis_out_bits {
5665 u8 status[0x8];
b4ff3a36 5666 u8 reserved_at_8[0x18];
e281682b
SM		 5667
5668 u8 syndrome[0x20];
5669
b4ff3a36 5670 u8 reserved_at_40[0x40];
e281682b
SM		 5671};
5672
75850d0b 5673struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5674 u8 reserved_at_0[0x20];
75850d0b 5675
84df61eb
AH		 5676 u8 reserved_at_20[0x1d];
5677 u8 lag_tx_port_affinity[0x1];
5678 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5679 u8 prio[0x1];
5680};
5681
e281682b
SM		 5682struct mlx5_ifc_modify_tis_in_bits {
5683 u8 opcode[0x10];
bd371975 5684 u8 uid[0x10];
e281682b 5685
b4ff3a36 5686 u8 reserved_at_20[0x10];
e281682b
SM		 5687 u8 op_mod[0x10];
5688
b4ff3a36 5689 u8 reserved_at_40[0x8];
e281682b
SM		 5690 u8 tisn[0x18];
5691
b4ff3a36 5692 u8 reserved_at_60[0x20];
e281682b 5693
75850d0b 5694 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5695
b4ff3a36 5696 u8 reserved_at_c0[0x40];
e281682b
SM		 5697
5698 struct mlx5_ifc_tisc_bits ctx;
5699};
5700
d9eea403 5701struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5702 u8 reserved_at_0[0x20];
d9eea403 5703
b4ff3a36 5704 u8 reserved_at_20[0x1b];
66189961 5705 u8 self_lb_en[0x1];
bdfc028d
TT		 5706 u8 reserved_at_3c[0x1];
5707 u8 hash[0x1];
5708 u8 reserved_at_3e[0x1];
d9eea403
AS		 5709 u8 lro[0x1];
5710};
5711
e281682b
SM		 5712struct mlx5_ifc_modify_tir_out_bits {
5713 u8 status[0x8];
b4ff3a36 5714 u8 reserved_at_8[0x18];
e281682b
SM		 5715
5716 u8 syndrome[0x20];
5717
b4ff3a36 5718 u8 reserved_at_40[0x40];
e281682b
SM		 5719};
5720
5721struct mlx5_ifc_modify_tir_in_bits {
5722 u8 opcode[0x10];
bd371975 5723 u8 uid[0x10];
e281682b 5724
b4ff3a36 5725 u8 reserved_at_20[0x10];
e281682b
SM		 5726 u8 op_mod[0x10];
5727
b4ff3a36 5728 u8 reserved_at_40[0x8];
e281682b
SM		 5729 u8 tirn[0x18];
5730
b4ff3a36 5731 u8 reserved_at_60[0x20];
e281682b 5732
d9eea403 5733 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5734
b4ff3a36 5735 u8 reserved_at_c0[0x40];
e281682b
SM		 5736
5737 struct mlx5_ifc_tirc_bits ctx;
5738};
5739
5740struct mlx5_ifc_modify_sq_out_bits {
5741 u8 status[0x8];
b4ff3a36 5742 u8 reserved_at_8[0x18];
e281682b
SM		 5743
5744 u8 syndrome[0x20];
5745
b4ff3a36 5746 u8 reserved_at_40[0x40];
e281682b
SM		 5747};
5748
5749struct mlx5_ifc_modify_sq_in_bits {
5750 u8 opcode[0x10];
430ae0d5 5751 u8 uid[0x10];
e281682b 5752
b4ff3a36 5753 u8 reserved_at_20[0x10];
e281682b
SM		 5754 u8 op_mod[0x10];
5755
5756 u8 sq_state[0x4];
b4ff3a36 5757 u8 reserved_at_44[0x4];
e281682b
SM		 5758 u8 sqn[0x18];
5759
b4ff3a36 5760 u8 reserved_at_60[0x20];
e281682b
SM		 5761
5762 u8 modify_bitmask[0x40];
5763
b4ff3a36 5764 u8 reserved_at_c0[0x40];
e281682b
SM		 5765
5766 struct mlx5_ifc_sqc_bits ctx;
5767};
5768
813f8540
MHY		 5769struct mlx5_ifc_modify_scheduling_element_out_bits {
5770 u8 status[0x8];
5771 u8 reserved_at_8[0x18];
5772
5773 u8 syndrome[0x20];
5774
5775 u8 reserved_at_40[0x1c0];
5776};
5777
5778enum {
5779 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5780 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5781};
5782
5783struct mlx5_ifc_modify_scheduling_element_in_bits {
5784 u8 opcode[0x10];
5785 u8 reserved_at_10[0x10];
5786
5787 u8 reserved_at_20[0x10];
5788 u8 op_mod[0x10];
5789
5790 u8 scheduling_hierarchy[0x8];
5791 u8 reserved_at_48[0x18];
5792
5793 u8 scheduling_element_id[0x20];
5794
5795 u8 reserved_at_80[0x20];
5796
5797 u8 modify_bitmask[0x20];
5798
5799 u8 reserved_at_c0[0x40];
5800
5801 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5802
5803 u8 reserved_at_300[0x100];
5804};
5805
e281682b
SM		 5806struct mlx5_ifc_modify_rqt_out_bits {
5807 u8 status[0x8];
b4ff3a36 5808 u8 reserved_at_8[0x18];
e281682b
SM		 5809
5810 u8 syndrome[0x20];
5811
b4ff3a36 5812 u8 reserved_at_40[0x40];
e281682b
SM		 5813};
5814
5c50368f 5815struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5816 u8 reserved_at_0[0x20];
5c50368f 5817
b4ff3a36 5818 u8 reserved_at_20[0x1f];
5c50368f
AS		 5819 u8 rqn_list[0x1];
5820};
5821
e281682b
SM		 5822struct mlx5_ifc_modify_rqt_in_bits {
5823 u8 opcode[0x10];
bd371975 5824 u8 uid[0x10];
e281682b 5825
b4ff3a36 5826 u8 reserved_at_20[0x10];
e281682b
SM		 5827 u8 op_mod[0x10];
5828
b4ff3a36 5829 u8 reserved_at_40[0x8];
e281682b
SM		 5830 u8 rqtn[0x18];
5831
b4ff3a36 5832 u8 reserved_at_60[0x20];
e281682b 5833
5c50368f 5834 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5835
b4ff3a36 5836 u8 reserved_at_c0[0x40];
e281682b
SM		 5837
5838 struct mlx5_ifc_rqtc_bits ctx;
5839};
5840
5841struct mlx5_ifc_modify_rq_out_bits {
5842 u8 status[0x8];
b4ff3a36 5843 u8 reserved_at_8[0x18];
e281682b
SM		 5844
5845 u8 syndrome[0x20];
5846
b4ff3a36 5847 u8 reserved_at_40[0x40];
e281682b
SM		 5848};
5849
83b502a1
AV		 5850enum {
5851 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5852 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5853 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5854};
5855
e281682b
SM		 5856struct mlx5_ifc_modify_rq_in_bits {
5857 u8 opcode[0x10];
d269b3af 5858 u8 uid[0x10];
e281682b 5859
b4ff3a36 5860 u8 reserved_at_20[0x10];
e281682b
SM		 5861 u8 op_mod[0x10];
5862
5863 u8 rq_state[0x4];
b4ff3a36 5864 u8 reserved_at_44[0x4];
e281682b
SM		 5865 u8 rqn[0x18];
5866
b4ff3a36 5867 u8 reserved_at_60[0x20];
e281682b
SM		 5868
5869 u8 modify_bitmask[0x40];
5870
b4ff3a36 5871 u8 reserved_at_c0[0x40];
e281682b
SM		 5872
5873 struct mlx5_ifc_rqc_bits ctx;
5874};
5875
5876struct mlx5_ifc_modify_rmp_out_bits {
5877 u8 status[0x8];
b4ff3a36 5878 u8 reserved_at_8[0x18];
e281682b
SM		 5879
5880 u8 syndrome[0x20];
5881
b4ff3a36 5882 u8 reserved_at_40[0x40];
e281682b
SM		 5883};
5884
01949d01 5885struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5886 u8 reserved_at_0[0x20];
01949d01 5887
b4ff3a36 5888 u8 reserved_at_20[0x1f];
01949d01
HA		 5889 u8 lwm[0x1];
5890};
5891
e281682b
SM		 5892struct mlx5_ifc_modify_rmp_in_bits {
5893 u8 opcode[0x10];
a0d8c054 5894 u8 uid[0x10];
e281682b 5895
b4ff3a36 5896 u8 reserved_at_20[0x10];
e281682b
SM		 5897 u8 op_mod[0x10];
5898
5899 u8 rmp_state[0x4];
b4ff3a36 5900 u8 reserved_at_44[0x4];
e281682b
SM		 5901 u8 rmpn[0x18];
5902
b4ff3a36 5903 u8 reserved_at_60[0x20];
e281682b 5904
01949d01 5905 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5906
b4ff3a36 5907 u8 reserved_at_c0[0x40];
e281682b
SM		 5908
5909 struct mlx5_ifc_rmpc_bits ctx;
5910};
5911
5912struct mlx5_ifc_modify_nic_vport_context_out_bits {
5913 u8 status[0x8];
b4ff3a36 5914 u8 reserved_at_8[0x18];
e281682b
SM		 5915
5916 u8 syndrome[0x20];
5917
b4ff3a36 5918 u8 reserved_at_40[0x40];
e281682b
SM		 5919};
5920
5921struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5922 u8 reserved_at_0[0x12];
5923 u8 affiliation[0x1];
c74d90c1 5924 u8 reserved_at_13[0x1];
bded747b
HN		 5925 u8 disable_uc_local_lb[0x1];
5926 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5927 u8 node_guid[0x1];
5928 u8 port_guid[0x1];
9def7121 5929 u8 min_inline[0x1];
d82b7318
SM		 5930 u8 mtu[0x1];
5931 u8 change_event[0x1];
5932 u8 promisc[0x1];
e281682b
SM		 5933 u8 permanent_address[0x1];
5934 u8 addresses_list[0x1];
5935 u8 roce_en[0x1];
b4ff3a36 5936 u8 reserved_at_1f[0x1];
e281682b
SM		 5937};
5938
5939struct mlx5_ifc_modify_nic_vport_context_in_bits {
5940 u8 opcode[0x10];
b4ff3a36 5941 u8 reserved_at_10[0x10];
e281682b 5942
b4ff3a36 5943 u8 reserved_at_20[0x10];
e281682b
SM		 5944 u8 op_mod[0x10];
5945
5946 u8 other_vport[0x1];
b4ff3a36 5947 u8 reserved_at_41[0xf];
e281682b
SM		 5948 u8 vport_number[0x10];
5949
5950 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5951
b4ff3a36 5952 u8 reserved_at_80[0x780];
e281682b
SM		 5953
5954 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5955};
5956
5957struct mlx5_ifc_modify_hca_vport_context_out_bits {
5958 u8 status[0x8];
b4ff3a36 5959 u8 reserved_at_8[0x18];
e281682b
SM		 5960
5961 u8 syndrome[0x20];
5962
b4ff3a36 5963 u8 reserved_at_40[0x40];
e281682b
SM		 5964};
5965
5966struct mlx5_ifc_modify_hca_vport_context_in_bits {
5967 u8 opcode[0x10];
b4ff3a36 5968 u8 reserved_at_10[0x10];
e281682b 5969
b4ff3a36 5970 u8 reserved_at_20[0x10];
e281682b
SM		 5971 u8 op_mod[0x10];
5972
5973 u8 other_vport[0x1];
b4ff3a36 5974 u8 reserved_at_41[0xb];
707c4602 5975 u8 port_num[0x4];
e281682b
SM		 5976 u8 vport_number[0x10];
5977
b4ff3a36 5978 u8 reserved_at_60[0x20];
e281682b
SM		 5979
5980 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5981};
5982
5983struct mlx5_ifc_modify_cq_out_bits {
5984 u8 status[0x8];
b4ff3a36 5985 u8 reserved_at_8[0x18];
e281682b
SM		 5986
5987 u8 syndrome[0x20];
5988
b4ff3a36 5989 u8 reserved_at_40[0x40];
e281682b
SM		 5990};
5991
5992enum {
5993 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5994 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5995};
5996
5997struct mlx5_ifc_modify_cq_in_bits {
5998 u8 opcode[0x10];
9ba481e2 5999 u8 uid[0x10];
e281682b 6000
b4ff3a36 6001 u8 reserved_at_20[0x10];
e281682b
SM		 6002 u8 op_mod[0x10];
6003
b4ff3a36 6004 u8 reserved_at_40[0x8];
e281682b
SM		 6005 u8 cqn[0x18];
6006
6007 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6008
6009 struct mlx5_ifc_cqc_bits cq_context;
6010
bd371975
LR		 6011 u8 reserved_at_280[0x40];
6012
6013 u8 cq_umem_valid[0x1];
6014 u8 reserved_at_2c1[0x5bf];
e281682b
SM		 6015
6016 u8 pas[0][0x40];
6017};
6018
6019struct mlx5_ifc_modify_cong_status_out_bits {
6020 u8 status[0x8];
b4ff3a36 6021 u8 reserved_at_8[0x18];
e281682b
SM		 6022
6023 u8 syndrome[0x20];
6024
b4ff3a36 6025 u8 reserved_at_40[0x40];
e281682b
SM		 6026};
6027
6028struct mlx5_ifc_modify_cong_status_in_bits {
6029 u8 opcode[0x10];
b4ff3a36 6030 u8 reserved_at_10[0x10];
e281682b 6031
b4ff3a36 6032 u8 reserved_at_20[0x10];
e281682b
SM		 6033 u8 op_mod[0x10];
6034
b4ff3a36 6035 u8 reserved_at_40[0x18];
e281682b
SM		 6036 u8 priority[0x4];
6037 u8 cong_protocol[0x4];
6038
6039 u8 enable[0x1];
6040 u8 tag_enable[0x1];
b4ff3a36 6041 u8 reserved_at_62[0x1e];
e281682b
SM		 6042};
6043
6044struct mlx5_ifc_modify_cong_params_out_bits {
6045 u8 status[0x8];
b4ff3a36 6046 u8 reserved_at_8[0x18];
e281682b
SM		 6047
6048 u8 syndrome[0x20];
6049
b4ff3a36 6050 u8 reserved_at_40[0x40];
e281682b
SM		 6051};
6052
6053struct mlx5_ifc_modify_cong_params_in_bits {
6054 u8 opcode[0x10];
b4ff3a36 6055 u8 reserved_at_10[0x10];
e281682b 6056
b4ff3a36 6057 u8 reserved_at_20[0x10];
e281682b
SM		 6058 u8 op_mod[0x10];
6059
b4ff3a36 6060 u8 reserved_at_40[0x1c];
e281682b
SM		 6061 u8 cong_protocol[0x4];
6062
6063 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6064
b4ff3a36 6065 u8 reserved_at_80[0x80];
e281682b
SM		 6066
6067 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6068};
6069
6070struct mlx5_ifc_manage_pages_out_bits {
6071 u8 status[0x8];
b4ff3a36 6072 u8 reserved_at_8[0x18];
e281682b
SM		 6073
6074 u8 syndrome[0x20];
6075
6076 u8 output_num_entries[0x20];
6077
b4ff3a36 6078 u8 reserved_at_60[0x20];
e281682b
SM		 6079
6080 u8 pas[0][0x40];
6081};
6082
6083enum {
6084 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6085 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6086 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6087};
6088
6089struct mlx5_ifc_manage_pages_in_bits {
6090 u8 opcode[0x10];
b4ff3a36 6091 u8 reserved_at_10[0x10];
e281682b 6092
b4ff3a36 6093 u8 reserved_at_20[0x10];
e281682b
SM		 6094 u8 op_mod[0x10];
6095
591905ba
BW		 6096 u8 embedded_cpu_function[0x1];
6097 u8 reserved_at_41[0xf];
e281682b
SM		 6098 u8 function_id[0x10];
6099
6100 u8 input_num_entries[0x20];
6101
6102 u8 pas[0][0x40];
6103};
6104
6105struct mlx5_ifc_mad_ifc_out_bits {
6106 u8 status[0x8];
b4ff3a36 6107 u8 reserved_at_8[0x18];
e281682b
SM		 6108
6109 u8 syndrome[0x20];
6110
b4ff3a36 6111 u8 reserved_at_40[0x40];
e281682b
SM		 6112
6113 u8 response_mad_packet[256][0x8];
6114};
6115
6116struct mlx5_ifc_mad_ifc_in_bits {
6117 u8 opcode[0x10];
b4ff3a36 6118 u8 reserved_at_10[0x10];
e281682b 6119
b4ff3a36 6120 u8 reserved_at_20[0x10];
e281682b
SM		 6121 u8 op_mod[0x10];
6122
6123 u8 remote_lid[0x10];
b4ff3a36 6124 u8 reserved_at_50[0x8];
e281682b
SM		 6125 u8 port[0x8];
6126
b4ff3a36 6127 u8 reserved_at_60[0x20];
e281682b
SM		 6128
6129 u8 mad[256][0x8];
6130};
6131
6132struct mlx5_ifc_init_hca_out_bits {
6133 u8 status[0x8];
b4ff3a36 6134 u8 reserved_at_8[0x18];
e281682b
SM		 6135
6136 u8 syndrome[0x20];
6137
b4ff3a36 6138 u8 reserved_at_40[0x40];
e281682b
SM		 6139};
6140
6141struct mlx5_ifc_init_hca_in_bits {
6142 u8 opcode[0x10];
b4ff3a36 6143 u8 reserved_at_10[0x10];
e281682b 6144
b4ff3a36 6145 u8 reserved_at_20[0x10];
e281682b
SM		 6146 u8 op_mod[0x10];
6147
b4ff3a36 6148 u8 reserved_at_40[0x40];
8737f818 6149 u8 sw_owner_id[4][0x20];
e281682b
SM		 6150};
6151
6152struct mlx5_ifc_init2rtr_qp_out_bits {
6153 u8 status[0x8];
b4ff3a36 6154 u8 reserved_at_8[0x18];
e281682b
SM		 6155
6156 u8 syndrome[0x20];
6157
b4ff3a36 6158 u8 reserved_at_40[0x40];
e281682b
SM		 6159};
6160
6161struct mlx5_ifc_init2rtr_qp_in_bits {
6162 u8 opcode[0x10];
4ac63ec7 6163 u8 uid[0x10];
e281682b 6164
b4ff3a36 6165 u8 reserved_at_20[0x10];
e281682b
SM		 6166 u8 op_mod[0x10];
6167
b4ff3a36 6168 u8 reserved_at_40[0x8];
e281682b
SM		 6169 u8 qpn[0x18];
6170
b4ff3a36 6171 u8 reserved_at_60[0x20];
e281682b
SM		 6172
6173 u8 opt_param_mask[0x20];
6174
b4ff3a36 6175 u8 reserved_at_a0[0x20];
e281682b
SM		 6176
6177 struct mlx5_ifc_qpc_bits qpc;
6178
b4ff3a36 6179 u8 reserved_at_800[0x80];
e281682b
SM		 6180};
6181
6182struct mlx5_ifc_init2init_qp_out_bits {
6183 u8 status[0x8];
b4ff3a36 6184 u8 reserved_at_8[0x18];
e281682b
SM		 6185
6186 u8 syndrome[0x20];
6187
b4ff3a36 6188 u8 reserved_at_40[0x40];
e281682b
SM		 6189};
6190
6191struct mlx5_ifc_init2init_qp_in_bits {
6192 u8 opcode[0x10];
4ac63ec7 6193 u8 uid[0x10];
e281682b 6194
b4ff3a36 6195 u8 reserved_at_20[0x10];
e281682b
SM		 6196 u8 op_mod[0x10];
6197
b4ff3a36 6198 u8 reserved_at_40[0x8];
e281682b
SM		 6199 u8 qpn[0x18];
6200
b4ff3a36 6201 u8 reserved_at_60[0x20];
e281682b
SM		 6202
6203 u8 opt_param_mask[0x20];
6204
b4ff3a36 6205 u8 reserved_at_a0[0x20];
e281682b
SM		 6206
6207 struct mlx5_ifc_qpc_bits qpc;
6208
b4ff3a36 6209 u8 reserved_at_800[0x80];
e281682b
SM		 6210};
6211
6212struct mlx5_ifc_get_dropped_packet_log_out_bits {
6213 u8 status[0x8];
b4ff3a36 6214 u8 reserved_at_8[0x18];
e281682b
SM		 6215
6216 u8 syndrome[0x20];
6217
b4ff3a36 6218 u8 reserved_at_40[0x40];
e281682b
SM		 6219
6220 u8 packet_headers_log[128][0x8];
6221
6222 u8 packet_syndrome[64][0x8];
6223};
6224
6225struct mlx5_ifc_get_dropped_packet_log_in_bits {
6226 u8 opcode[0x10];
b4ff3a36 6227 u8 reserved_at_10[0x10];
e281682b 6228
b4ff3a36 6229 u8 reserved_at_20[0x10];
e281682b
SM		 6230 u8 op_mod[0x10];
6231
b4ff3a36 6232 u8 reserved_at_40[0x40];
e281682b
SM		 6233};
6234
6235struct mlx5_ifc_gen_eqe_in_bits {
6236 u8 opcode[0x10];
b4ff3a36 6237 u8 reserved_at_10[0x10];
e281682b 6238
b4ff3a36 6239 u8 reserved_at_20[0x10];
e281682b
SM		 6240 u8 op_mod[0x10];
6241
b4ff3a36 6242 u8 reserved_at_40[0x18];
e281682b
SM		 6243 u8 eq_number[0x8];
6244
b4ff3a36 6245 u8 reserved_at_60[0x20];
e281682b
SM		 6246
6247 u8 eqe[64][0x8];
6248};
6249
6250struct mlx5_ifc_gen_eq_out_bits {
6251 u8 status[0x8];
b4ff3a36 6252 u8 reserved_at_8[0x18];
e281682b
SM		 6253
6254 u8 syndrome[0x20];
6255
b4ff3a36 6256 u8 reserved_at_40[0x40];
e281682b
SM		 6257};
6258
6259struct mlx5_ifc_enable_hca_out_bits {
6260 u8 status[0x8];
b4ff3a36 6261 u8 reserved_at_8[0x18];
e281682b
SM		 6262
6263 u8 syndrome[0x20];
6264
b4ff3a36 6265 u8 reserved_at_40[0x20];
e281682b
SM		 6266};
6267
6268struct mlx5_ifc_enable_hca_in_bits {
6269 u8 opcode[0x10];
b4ff3a36 6270 u8 reserved_at_10[0x10];
e281682b 6271
b4ff3a36 6272 u8 reserved_at_20[0x10];
e281682b
SM		 6273 u8 op_mod[0x10];
6274
22e939a9
BW		 6275 u8 embedded_cpu_function[0x1];
6276 u8 reserved_at_41[0xf];
e281682b
SM		 6277 u8 function_id[0x10];
6278
b4ff3a36 6279 u8 reserved_at_60[0x20];
e281682b
SM		 6280};
6281
6282struct mlx5_ifc_drain_dct_out_bits {
6283 u8 status[0x8];
b4ff3a36 6284 u8 reserved_at_8[0x18];
e281682b
SM		 6285
6286 u8 syndrome[0x20];
6287
b4ff3a36 6288 u8 reserved_at_40[0x40];
e281682b
SM		 6289};
6290
6291struct mlx5_ifc_drain_dct_in_bits {
6292 u8 opcode[0x10];
774ea6ee 6293 u8 uid[0x10];
e281682b 6294
b4ff3a36 6295 u8 reserved_at_20[0x10];
e281682b
SM		 6296 u8 op_mod[0x10];
6297
b4ff3a36 6298 u8 reserved_at_40[0x8];
e281682b
SM		 6299 u8 dctn[0x18];
6300
b4ff3a36 6301 u8 reserved_at_60[0x20];
e281682b
SM		 6302};
6303
6304struct mlx5_ifc_disable_hca_out_bits {
6305 u8 status[0x8];
b4ff3a36 6306 u8 reserved_at_8[0x18];
e281682b
SM		 6307
6308 u8 syndrome[0x20];
6309
b4ff3a36 6310 u8 reserved_at_40[0x20];
e281682b
SM		 6311};
6312
6313struct mlx5_ifc_disable_hca_in_bits {
6314 u8 opcode[0x10];
b4ff3a36 6315 u8 reserved_at_10[0x10];
e281682b 6316
b4ff3a36 6317 u8 reserved_at_20[0x10];
e281682b
SM		 6318 u8 op_mod[0x10];
6319
22e939a9
BW		 6320 u8 embedded_cpu_function[0x1];
6321 u8 reserved_at_41[0xf];
e281682b
SM		 6322 u8 function_id[0x10];
6323
b4ff3a36 6324 u8 reserved_at_60[0x20];
e281682b
SM		 6325};
6326
6327struct mlx5_ifc_detach_from_mcg_out_bits {
6328 u8 status[0x8];
b4ff3a36 6329 u8 reserved_at_8[0x18];
e281682b
SM		 6330
6331 u8 syndrome[0x20];
6332
b4ff3a36 6333 u8 reserved_at_40[0x40];
e281682b
SM		 6334};
6335
6336struct mlx5_ifc_detach_from_mcg_in_bits {
6337 u8 opcode[0x10];
bd371975 6338 u8 uid[0x10];
e281682b 6339
b4ff3a36 6340 u8 reserved_at_20[0x10];
e281682b
SM		 6341 u8 op_mod[0x10];
6342
b4ff3a36 6343 u8 reserved_at_40[0x8];
e281682b
SM		 6344 u8 qpn[0x18];
6345
b4ff3a36 6346 u8 reserved_at_60[0x20];
e281682b
SM		 6347
6348 u8 multicast_gid[16][0x8];
6349};
6350
7486216b
SM		 6351struct mlx5_ifc_destroy_xrq_out_bits {
6352 u8 status[0x8];
6353 u8 reserved_at_8[0x18];
6354
6355 u8 syndrome[0x20];
6356
6357 u8 reserved_at_40[0x40];
6358};
6359
6360struct mlx5_ifc_destroy_xrq_in_bits {
6361 u8 opcode[0x10];
a0d8c054 6362 u8 uid[0x10];
7486216b
SM		 6363
6364 u8 reserved_at_20[0x10];
6365 u8 op_mod[0x10];
6366
6367 u8 reserved_at_40[0x8];
6368 u8 xrqn[0x18];
6369
6370 u8 reserved_at_60[0x20];
6371};
6372
e281682b
SM		 6373struct mlx5_ifc_destroy_xrc_srq_out_bits {
6374 u8 status[0x8];
b4ff3a36 6375 u8 reserved_at_8[0x18];
e281682b
SM		 6376
6377 u8 syndrome[0x20];
6378
b4ff3a36 6379 u8 reserved_at_40[0x40];
e281682b
SM		 6380};
6381
6382struct mlx5_ifc_destroy_xrc_srq_in_bits {
6383 u8 opcode[0x10];
a0d8c054 6384 u8 uid[0x10];
e281682b 6385
b4ff3a36 6386 u8 reserved_at_20[0x10];
e281682b
SM		 6387 u8 op_mod[0x10];
6388
b4ff3a36 6389 u8 reserved_at_40[0x8];
e281682b
SM		 6390 u8 xrc_srqn[0x18];
6391
b4ff3a36 6392 u8 reserved_at_60[0x20];
e281682b
SM		 6393};
6394
6395struct mlx5_ifc_destroy_tis_out_bits {
6396 u8 status[0x8];
b4ff3a36 6397 u8 reserved_at_8[0x18];
e281682b
SM		 6398
6399 u8 syndrome[0x20];
6400
b4ff3a36 6401 u8 reserved_at_40[0x40];
e281682b
SM		 6402};
6403
6404struct mlx5_ifc_destroy_tis_in_bits {
6405 u8 opcode[0x10];
bd371975 6406 u8 uid[0x10];
e281682b 6407
b4ff3a36 6408 u8 reserved_at_20[0x10];
e281682b
SM		 6409 u8 op_mod[0x10];
6410
b4ff3a36 6411 u8 reserved_at_40[0x8];
e281682b
SM		 6412 u8 tisn[0x18];
6413
b4ff3a36 6414 u8 reserved_at_60[0x20];
e281682b
SM		 6415};
6416
6417struct mlx5_ifc_destroy_tir_out_bits {
6418 u8 status[0x8];
b4ff3a36 6419 u8 reserved_at_8[0x18];
e281682b
SM		 6420
6421 u8 syndrome[0x20];
6422
b4ff3a36 6423 u8 reserved_at_40[0x40];
e281682b
SM		 6424};
6425
6426struct mlx5_ifc_destroy_tir_in_bits {
6427 u8 opcode[0x10];
bd371975 6428 u8 uid[0x10];
e281682b 6429
b4ff3a36 6430 u8 reserved_at_20[0x10];
e281682b
SM		 6431 u8 op_mod[0x10];
6432
b4ff3a36 6433 u8 reserved_at_40[0x8];
e281682b
SM		 6434 u8 tirn[0x18];
6435
b4ff3a36 6436 u8 reserved_at_60[0x20];
e281682b
SM		 6437};
6438
6439struct mlx5_ifc_destroy_srq_out_bits {
6440 u8 status[0x8];
b4ff3a36 6441 u8 reserved_at_8[0x18];
e281682b
SM		 6442
6443 u8 syndrome[0x20];
6444
b4ff3a36 6445 u8 reserved_at_40[0x40];
e281682b
SM		 6446};
6447
6448struct mlx5_ifc_destroy_srq_in_bits {
6449 u8 opcode[0x10];
a0d8c054 6450 u8 uid[0x10];
e281682b 6451
b4ff3a36 6452 u8 reserved_at_20[0x10];
e281682b
SM		 6453 u8 op_mod[0x10];
6454
b4ff3a36 6455 u8 reserved_at_40[0x8];
e281682b
SM		 6456 u8 srqn[0x18];
6457
b4ff3a36 6458 u8 reserved_at_60[0x20];
e281682b
SM		 6459};
6460
6461struct mlx5_ifc_destroy_sq_out_bits {
6462 u8 status[0x8];
b4ff3a36 6463 u8 reserved_at_8[0x18];
e281682b
SM		 6464
6465 u8 syndrome[0x20];
6466
b4ff3a36 6467 u8 reserved_at_40[0x40];
e281682b
SM		 6468};
6469
6470struct mlx5_ifc_destroy_sq_in_bits {
6471 u8 opcode[0x10];
430ae0d5 6472 u8 uid[0x10];
e281682b 6473
b4ff3a36 6474 u8 reserved_at_20[0x10];
e281682b
SM		 6475 u8 op_mod[0x10];
6476
b4ff3a36 6477 u8 reserved_at_40[0x8];
e281682b
SM		 6478 u8 sqn[0x18];
6479
b4ff3a36 6480 u8 reserved_at_60[0x20];
e281682b
SM		 6481};
6482
813f8540
MHY		 6483struct mlx5_ifc_destroy_scheduling_element_out_bits {
6484 u8 status[0x8];
6485 u8 reserved_at_8[0x18];
6486
6487 u8 syndrome[0x20];
6488
6489 u8 reserved_at_40[0x1c0];
6490};
6491
6492struct mlx5_ifc_destroy_scheduling_element_in_bits {
6493 u8 opcode[0x10];
6494 u8 reserved_at_10[0x10];
6495
6496 u8 reserved_at_20[0x10];
6497 u8 op_mod[0x10];
6498
6499 u8 scheduling_hierarchy[0x8];
6500 u8 reserved_at_48[0x18];
6501
6502 u8 scheduling_element_id[0x20];
6503
6504 u8 reserved_at_80[0x180];
6505};
6506
e281682b
SM		 6507struct mlx5_ifc_destroy_rqt_out_bits {
6508 u8 status[0x8];
b4ff3a36 6509 u8 reserved_at_8[0x18];
e281682b
SM		 6510
6511 u8 syndrome[0x20];
6512
b4ff3a36 6513 u8 reserved_at_40[0x40];
e281682b
SM		 6514};
6515
6516struct mlx5_ifc_destroy_rqt_in_bits {
6517 u8 opcode[0x10];
bd371975 6518 u8 uid[0x10];
e281682b 6519
b4ff3a36 6520 u8 reserved_at_20[0x10];
e281682b
SM		 6521 u8 op_mod[0x10];
6522
b4ff3a36 6523 u8 reserved_at_40[0x8];
e281682b
SM		 6524 u8 rqtn[0x18];
6525
b4ff3a36 6526 u8 reserved_at_60[0x20];
e281682b
SM		 6527};
6528
6529struct mlx5_ifc_destroy_rq_out_bits {
6530 u8 status[0x8];
b4ff3a36 6531 u8 reserved_at_8[0x18];
e281682b
SM		 6532
6533 u8 syndrome[0x20];
6534
b4ff3a36 6535 u8 reserved_at_40[0x40];
e281682b
SM		 6536};
6537
6538struct mlx5_ifc_destroy_rq_in_bits {
6539 u8 opcode[0x10];
d269b3af 6540 u8 uid[0x10];
e281682b 6541
b4ff3a36 6542 u8 reserved_at_20[0x10];
e281682b
SM		 6543 u8 op_mod[0x10];
6544
b4ff3a36 6545 u8 reserved_at_40[0x8];
e281682b
SM		 6546 u8 rqn[0x18];
6547
b4ff3a36 6548 u8 reserved_at_60[0x20];
e281682b
SM		 6549};
6550
c1e0bfc1
MG		 6551struct mlx5_ifc_set_delay_drop_params_in_bits {
6552 u8 opcode[0x10];
6553 u8 reserved_at_10[0x10];
6554
6555 u8 reserved_at_20[0x10];
6556 u8 op_mod[0x10];
6557
6558 u8 reserved_at_40[0x20];
6559
6560 u8 reserved_at_60[0x10];
6561 u8 delay_drop_timeout[0x10];
6562};
6563
6564struct mlx5_ifc_set_delay_drop_params_out_bits {
6565 u8 status[0x8];
6566 u8 reserved_at_8[0x18];
6567
6568 u8 syndrome[0x20];
6569
6570 u8 reserved_at_40[0x40];
6571};
6572
e281682b
SM		 6573struct mlx5_ifc_destroy_rmp_out_bits {
6574 u8 status[0x8];
b4ff3a36 6575 u8 reserved_at_8[0x18];
e281682b
SM		 6576
6577 u8 syndrome[0x20];
6578
b4ff3a36 6579 u8 reserved_at_40[0x40];
e281682b
SM		 6580};
6581
6582struct mlx5_ifc_destroy_rmp_in_bits {
6583 u8 opcode[0x10];
a0d8c054 6584 u8 uid[0x10];
e281682b 6585
b4ff3a36 6586 u8 reserved_at_20[0x10];
e281682b
SM		 6587 u8 op_mod[0x10];
6588
b4ff3a36 6589 u8 reserved_at_40[0x8];
e281682b
SM		 6590 u8 rmpn[0x18];
6591
b4ff3a36 6592 u8 reserved_at_60[0x20];
e281682b
SM		 6593};
6594
6595struct mlx5_ifc_destroy_qp_out_bits {
6596 u8 status[0x8];
b4ff3a36 6597 u8 reserved_at_8[0x18];
e281682b
SM		 6598
6599 u8 syndrome[0x20];
6600
b4ff3a36 6601 u8 reserved_at_40[0x40];
e281682b
SM		 6602};
6603
6604struct mlx5_ifc_destroy_qp_in_bits {
6605 u8 opcode[0x10];
4ac63ec7 6606 u8 uid[0x10];
e281682b 6607
b4ff3a36 6608 u8 reserved_at_20[0x10];
e281682b
SM		 6609 u8 op_mod[0x10];
6610
b4ff3a36 6611 u8 reserved_at_40[0x8];
e281682b
SM		 6612 u8 qpn[0x18];
6613
b4ff3a36 6614 u8 reserved_at_60[0x20];
e281682b
SM		 6615};
6616
6617struct mlx5_ifc_destroy_psv_out_bits {
6618 u8 status[0x8];
b4ff3a36 6619 u8 reserved_at_8[0x18];
e281682b
SM		 6620
6621 u8 syndrome[0x20];
6622
b4ff3a36 6623 u8 reserved_at_40[0x40];
e281682b
SM		 6624};
6625
6626struct mlx5_ifc_destroy_psv_in_bits {
6627 u8 opcode[0x10];
b4ff3a36 6628 u8 reserved_at_10[0x10];
e281682b 6629
b4ff3a36 6630 u8 reserved_at_20[0x10];
e281682b
SM		 6631 u8 op_mod[0x10];
6632
b4ff3a36 6633 u8 reserved_at_40[0x8];
e281682b
SM		 6634 u8 psvn[0x18];
6635
b4ff3a36 6636 u8 reserved_at_60[0x20];
e281682b
SM		 6637};
6638
6639struct mlx5_ifc_destroy_mkey_out_bits {
6640 u8 status[0x8];
b4ff3a36 6641 u8 reserved_at_8[0x18];
e281682b
SM		 6642
6643 u8 syndrome[0x20];
6644
b4ff3a36 6645 u8 reserved_at_40[0x40];
e281682b
SM		 6646};
6647
6648struct mlx5_ifc_destroy_mkey_in_bits {
6649 u8 opcode[0x10];
b4ff3a36 6650 u8 reserved_at_10[0x10];
e281682b 6651
b4ff3a36 6652 u8 reserved_at_20[0x10];
e281682b
SM		 6653 u8 op_mod[0x10];
6654
b4ff3a36 6655 u8 reserved_at_40[0x8];
e281682b
SM		 6656 u8 mkey_index[0x18];
6657
b4ff3a36 6658 u8 reserved_at_60[0x20];
e281682b
SM		 6659};
6660
6661struct mlx5_ifc_destroy_flow_table_out_bits {
6662 u8 status[0x8];
b4ff3a36 6663 u8 reserved_at_8[0x18];
e281682b
SM		 6664
6665 u8 syndrome[0x20];
6666
b4ff3a36 6667 u8 reserved_at_40[0x40];
e281682b
SM		 6668};
6669
6670struct mlx5_ifc_destroy_flow_table_in_bits {
6671 u8 opcode[0x10];
b4ff3a36 6672 u8 reserved_at_10[0x10];
e281682b 6673
b4ff3a36 6674 u8 reserved_at_20[0x10];
e281682b
SM		 6675 u8 op_mod[0x10];
6676
7d5e1423
SM		 6677 u8 other_vport[0x1];
6678 u8 reserved_at_41[0xf];
6679 u8 vport_number[0x10];
6680
6681 u8 reserved_at_60[0x20];
e281682b
SM		 6682
6683 u8 table_type[0x8];
b4ff3a36 6684 u8 reserved_at_88[0x18];
e281682b 6685
b4ff3a36 6686 u8 reserved_at_a0[0x8];
e281682b
SM		 6687 u8 table_id[0x18];
6688
b4ff3a36 6689 u8 reserved_at_c0[0x140];
e281682b
SM		 6690};
6691
6692struct mlx5_ifc_destroy_flow_group_out_bits {
6693 u8 status[0x8];
b4ff3a36 6694 u8 reserved_at_8[0x18];
e281682b
SM		 6695
6696 u8 syndrome[0x20];
6697
b4ff3a36 6698 u8 reserved_at_40[0x40];
e281682b
SM		 6699};
6700
6701struct mlx5_ifc_destroy_flow_group_in_bits {
6702 u8 opcode[0x10];
b4ff3a36 6703 u8 reserved_at_10[0x10];
e281682b 6704
b4ff3a36 6705 u8 reserved_at_20[0x10];
e281682b
SM		 6706 u8 op_mod[0x10];
6707
7d5e1423
SM		 6708 u8 other_vport[0x1];
6709 u8 reserved_at_41[0xf];
6710 u8 vport_number[0x10];
6711
6712 u8 reserved_at_60[0x20];
e281682b
SM		 6713
6714 u8 table_type[0x8];
b4ff3a36 6715 u8 reserved_at_88[0x18];
e281682b 6716
b4ff3a36 6717 u8 reserved_at_a0[0x8];
e281682b
SM		 6718 u8 table_id[0x18];
6719
6720 u8 group_id[0x20];
6721
b4ff3a36 6722 u8 reserved_at_e0[0x120];
e281682b
SM		 6723};
6724
6725struct mlx5_ifc_destroy_eq_out_bits {
6726 u8 status[0x8];
b4ff3a36 6727 u8 reserved_at_8[0x18];
e281682b
SM		 6728
6729 u8 syndrome[0x20];
6730
b4ff3a36 6731 u8 reserved_at_40[0x40];
e281682b
SM		 6732};
6733
6734struct mlx5_ifc_destroy_eq_in_bits {
6735 u8 opcode[0x10];
b4ff3a36 6736 u8 reserved_at_10[0x10];
e281682b 6737
b4ff3a36 6738 u8 reserved_at_20[0x10];
e281682b
SM		 6739 u8 op_mod[0x10];
6740
b4ff3a36 6741 u8 reserved_at_40[0x18];
e281682b
SM		 6742 u8 eq_number[0x8];
6743
b4ff3a36 6744 u8 reserved_at_60[0x20];
e281682b
SM		 6745};
6746
6747struct mlx5_ifc_destroy_dct_out_bits {
6748 u8 status[0x8];
b4ff3a36 6749 u8 reserved_at_8[0x18];
e281682b
SM		 6750
6751 u8 syndrome[0x20];
6752
b4ff3a36 6753 u8 reserved_at_40[0x40];
e281682b
SM		 6754};
6755
6756struct mlx5_ifc_destroy_dct_in_bits {
6757 u8 opcode[0x10];
774ea6ee 6758 u8 uid[0x10];
e281682b 6759
b4ff3a36 6760 u8 reserved_at_20[0x10];
e281682b
SM		 6761 u8 op_mod[0x10];
6762
b4ff3a36 6763 u8 reserved_at_40[0x8];
e281682b
SM		 6764 u8 dctn[0x18];
6765
b4ff3a36 6766 u8 reserved_at_60[0x20];
e281682b
SM		 6767};
6768
6769struct mlx5_ifc_destroy_cq_out_bits {
6770 u8 status[0x8];
b4ff3a36 6771 u8 reserved_at_8[0x18];
e281682b
SM		 6772
6773 u8 syndrome[0x20];
6774
b4ff3a36 6775 u8 reserved_at_40[0x40];
e281682b
SM		 6776};
6777
6778struct mlx5_ifc_destroy_cq_in_bits {
6779 u8 opcode[0x10];
9ba481e2 6780 u8 uid[0x10];
e281682b 6781
b4ff3a36 6782 u8 reserved_at_20[0x10];
e281682b
SM		 6783 u8 op_mod[0x10];
6784
b4ff3a36 6785 u8 reserved_at_40[0x8];
e281682b
SM		 6786 u8 cqn[0x18];
6787
b4ff3a36 6788 u8 reserved_at_60[0x20];
e281682b
SM		 6789};
6790
6791struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6792 u8 status[0x8];
b4ff3a36 6793 u8 reserved_at_8[0x18];
e281682b
SM		 6794
6795 u8 syndrome[0x20];
6796
b4ff3a36 6797 u8 reserved_at_40[0x40];
e281682b
SM		 6798};
6799
6800struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6801 u8 opcode[0x10];
b4ff3a36 6802 u8 reserved_at_10[0x10];
e281682b 6803
b4ff3a36 6804 u8 reserved_at_20[0x10];
e281682b
SM		 6805 u8 op_mod[0x10];
6806
b4ff3a36 6807 u8 reserved_at_40[0x20];
e281682b 6808
b4ff3a36 6809 u8 reserved_at_60[0x10];
e281682b
SM		 6810 u8 vxlan_udp_port[0x10];
6811};
6812
6813struct mlx5_ifc_delete_l2_table_entry_out_bits {
6814 u8 status[0x8];
b4ff3a36 6815 u8 reserved_at_8[0x18];
e281682b
SM		 6816
6817 u8 syndrome[0x20];
6818
b4ff3a36 6819 u8 reserved_at_40[0x40];
e281682b
SM		 6820};
6821
6822struct mlx5_ifc_delete_l2_table_entry_in_bits {
6823 u8 opcode[0x10];
b4ff3a36 6824 u8 reserved_at_10[0x10];
e281682b 6825
b4ff3a36 6826 u8 reserved_at_20[0x10];
e281682b
SM		 6827 u8 op_mod[0x10];
6828
b4ff3a36 6829 u8 reserved_at_40[0x60];
e281682b 6830
b4ff3a36 6831 u8 reserved_at_a0[0x8];
e281682b
SM		 6832 u8 table_index[0x18];
6833
b4ff3a36 6834 u8 reserved_at_c0[0x140];
e281682b
SM		 6835};
6836
6837struct mlx5_ifc_delete_fte_out_bits {
6838 u8 status[0x8];
b4ff3a36 6839 u8 reserved_at_8[0x18];
e281682b
SM		 6840
6841 u8 syndrome[0x20];
6842
b4ff3a36 6843 u8 reserved_at_40[0x40];
e281682b
SM		 6844};
6845
6846struct mlx5_ifc_delete_fte_in_bits {
6847 u8 opcode[0x10];
b4ff3a36 6848 u8 reserved_at_10[0x10];
e281682b 6849
b4ff3a36 6850 u8 reserved_at_20[0x10];
e281682b
SM		 6851 u8 op_mod[0x10];
6852
7d5e1423
SM		 6853 u8 other_vport[0x1];
6854 u8 reserved_at_41[0xf];
6855 u8 vport_number[0x10];
6856
6857 u8 reserved_at_60[0x20];
e281682b
SM		 6858
6859 u8 table_type[0x8];
b4ff3a36 6860 u8 reserved_at_88[0x18];
e281682b 6861
b4ff3a36 6862 u8 reserved_at_a0[0x8];
e281682b
SM		 6863 u8 table_id[0x18];
6864
b4ff3a36 6865 u8 reserved_at_c0[0x40];
e281682b
SM		 6866
6867 u8 flow_index[0x20];
6868
b4ff3a36 6869 u8 reserved_at_120[0xe0];
e281682b
SM		 6870};
6871
6872struct mlx5_ifc_dealloc_xrcd_out_bits {
6873 u8 status[0x8];
b4ff3a36 6874 u8 reserved_at_8[0x18];
e281682b
SM		 6875
6876 u8 syndrome[0x20];
6877
b4ff3a36 6878 u8 reserved_at_40[0x40];
e281682b
SM		 6879};
6880
6881struct mlx5_ifc_dealloc_xrcd_in_bits {
6882 u8 opcode[0x10];
bd371975 6883 u8 uid[0x10];
e281682b 6884
b4ff3a36 6885 u8 reserved_at_20[0x10];
e281682b
SM		 6886 u8 op_mod[0x10];
6887
b4ff3a36 6888 u8 reserved_at_40[0x8];
e281682b
SM		 6889 u8 xrcd[0x18];
6890
b4ff3a36 6891 u8 reserved_at_60[0x20];
e281682b
SM		 6892};
6893
6894struct mlx5_ifc_dealloc_uar_out_bits {
6895 u8 status[0x8];
b4ff3a36 6896 u8 reserved_at_8[0x18];
e281682b
SM		 6897
6898 u8 syndrome[0x20];
6899
b4ff3a36 6900 u8 reserved_at_40[0x40];
e281682b
SM		 6901};
6902
6903struct mlx5_ifc_dealloc_uar_in_bits {
6904 u8 opcode[0x10];
b4ff3a36 6905 u8 reserved_at_10[0x10];
e281682b 6906
b4ff3a36 6907 u8 reserved_at_20[0x10];
e281682b
SM		 6908 u8 op_mod[0x10];
6909
b4ff3a36 6910 u8 reserved_at_40[0x8];
e281682b
SM		 6911 u8 uar[0x18];
6912
b4ff3a36 6913 u8 reserved_at_60[0x20];
e281682b
SM		 6914};
6915
6916struct mlx5_ifc_dealloc_transport_domain_out_bits {
6917 u8 status[0x8];
b4ff3a36 6918 u8 reserved_at_8[0x18];
e281682b
SM		 6919
6920 u8 syndrome[0x20];
6921
b4ff3a36 6922 u8 reserved_at_40[0x40];
e281682b
SM		 6923};
6924
6925struct mlx5_ifc_dealloc_transport_domain_in_bits {
6926 u8 opcode[0x10];
71bef2fd 6927 u8 uid[0x10];
e281682b 6928
b4ff3a36 6929 u8 reserved_at_20[0x10];
e281682b
SM		 6930 u8 op_mod[0x10];
6931
b4ff3a36 6932 u8 reserved_at_40[0x8];
e281682b
SM		 6933 u8 transport_domain[0x18];
6934
b4ff3a36 6935 u8 reserved_at_60[0x20];
e281682b
SM		 6936};
6937
6938struct mlx5_ifc_dealloc_q_counter_out_bits {
6939 u8 status[0x8];
b4ff3a36 6940 u8 reserved_at_8[0x18];
e281682b
SM		 6941
6942 u8 syndrome[0x20];
6943
b4ff3a36 6944 u8 reserved_at_40[0x40];
e281682b
SM		 6945};
6946
6947struct mlx5_ifc_dealloc_q_counter_in_bits {
6948 u8 opcode[0x10];
b4ff3a36 6949 u8 reserved_at_10[0x10];
e281682b 6950
b4ff3a36 6951 u8 reserved_at_20[0x10];
e281682b
SM		 6952 u8 op_mod[0x10];
6953
b4ff3a36 6954 u8 reserved_at_40[0x18];
e281682b
SM		 6955 u8 counter_set_id[0x8];
6956
b4ff3a36 6957 u8 reserved_at_60[0x20];
e281682b
SM		 6958};
6959
6960struct mlx5_ifc_dealloc_pd_out_bits {
6961 u8 status[0x8];
b4ff3a36 6962 u8 reserved_at_8[0x18];
e281682b
SM		 6963
6964 u8 syndrome[0x20];
6965
b4ff3a36 6966 u8 reserved_at_40[0x40];
e281682b
SM		 6967};
6968
6969struct mlx5_ifc_dealloc_pd_in_bits {
6970 u8 opcode[0x10];
bd371975 6971 u8 uid[0x10];
e281682b 6972
b4ff3a36 6973 u8 reserved_at_20[0x10];
e281682b
SM		 6974 u8 op_mod[0x10];
6975
b4ff3a36 6976 u8 reserved_at_40[0x8];
e281682b
SM		 6977 u8 pd[0x18];
6978
b4ff3a36 6979 u8 reserved_at_60[0x20];
e281682b
SM		 6980};
6981
9dc0b289
AV		 6982struct mlx5_ifc_dealloc_flow_counter_out_bits {
6983 u8 status[0x8];
6984 u8 reserved_at_8[0x18];
6985
6986 u8 syndrome[0x20];
6987
6988 u8 reserved_at_40[0x40];
6989};
6990
6991struct mlx5_ifc_dealloc_flow_counter_in_bits {
6992 u8 opcode[0x10];
6993 u8 reserved_at_10[0x10];
6994
6995 u8 reserved_at_20[0x10];
6996 u8 op_mod[0x10];
6997
a8ffcc74 6998 u8 flow_counter_id[0x20];
9dc0b289
AV		 6999
7000 u8 reserved_at_60[0x20];
7001};
7002
7486216b
SM		 7003struct mlx5_ifc_create_xrq_out_bits {
7004 u8 status[0x8];
7005 u8 reserved_at_8[0x18];
7006
7007 u8 syndrome[0x20];
7008
7009 u8 reserved_at_40[0x8];
7010 u8 xrqn[0x18];
7011
7012 u8 reserved_at_60[0x20];
7013};
7014
7015struct mlx5_ifc_create_xrq_in_bits {
7016 u8 opcode[0x10];
a0d8c054 7017 u8 uid[0x10];
7486216b
SM		 7018
7019 u8 reserved_at_20[0x10];
7020 u8 op_mod[0x10];
7021
7022 u8 reserved_at_40[0x40];
7023
7024 struct mlx5_ifc_xrqc_bits xrq_context;
7025};
7026
e281682b
SM		 7027struct mlx5_ifc_create_xrc_srq_out_bits {
7028 u8 status[0x8];
b4ff3a36 7029 u8 reserved_at_8[0x18];
e281682b
SM		 7030
7031 u8 syndrome[0x20];
7032
b4ff3a36 7033 u8 reserved_at_40[0x8];
e281682b
SM		 7034 u8 xrc_srqn[0x18];
7035
b4ff3a36 7036 u8 reserved_at_60[0x20];
e281682b
SM		 7037};
7038
7039struct mlx5_ifc_create_xrc_srq_in_bits {
7040 u8 opcode[0x10];
a0d8c054 7041 u8 uid[0x10];
e281682b 7042
b4ff3a36 7043 u8 reserved_at_20[0x10];
e281682b
SM		 7044 u8 op_mod[0x10];
7045
b4ff3a36 7046 u8 reserved_at_40[0x40];
e281682b
SM		 7047
7048 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7049
99b77fef
YH		 7050 u8 reserved_at_280[0x60];
7051
bd371975 7052 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 7053 u8 reserved_at_2e1[0x1f];
7054
7055 u8 reserved_at_300[0x580];
e281682b
SM		 7056
7057 u8 pas[0][0x40];
7058};
7059
7060struct mlx5_ifc_create_tis_out_bits {
7061 u8 status[0x8];
b4ff3a36 7062 u8 reserved_at_8[0x18];
e281682b
SM		 7063
7064 u8 syndrome[0x20];
7065
b4ff3a36 7066 u8 reserved_at_40[0x8];
e281682b
SM		 7067 u8 tisn[0x18];
7068
b4ff3a36 7069 u8 reserved_at_60[0x20];
e281682b
SM		 7070};
7071
7072struct mlx5_ifc_create_tis_in_bits {
7073 u8 opcode[0x10];
bd371975 7074 u8 uid[0x10];
e281682b 7075
b4ff3a36 7076 u8 reserved_at_20[0x10];
e281682b
SM		 7077 u8 op_mod[0x10];
7078
b4ff3a36 7079 u8 reserved_at_40[0xc0];
e281682b
SM		 7080
7081 struct mlx5_ifc_tisc_bits ctx;
7082};
7083
7084struct mlx5_ifc_create_tir_out_bits {
7085 u8 status[0x8];
3e070470 7086 u8 icm_address_63_40[0x18];
e281682b
SM		 7087
7088 u8 syndrome[0x20];
7089
3e070470 7090 u8 icm_address_39_32[0x8];
e281682b
SM		 7091 u8 tirn[0x18];
7092
3e070470 7093 u8 icm_address_31_0[0x20];
e281682b
SM		 7094};
7095
7096struct mlx5_ifc_create_tir_in_bits {
7097 u8 opcode[0x10];
bd371975 7098 u8 uid[0x10];
e281682b 7099
b4ff3a36 7100 u8 reserved_at_20[0x10];
e281682b
SM		 7101 u8 op_mod[0x10];
7102
b4ff3a36 7103 u8 reserved_at_40[0xc0];
e281682b
SM		 7104
7105 struct mlx5_ifc_tirc_bits ctx;
7106};
7107
7108struct mlx5_ifc_create_srq_out_bits {
7109 u8 status[0x8];
b4ff3a36 7110 u8 reserved_at_8[0x18];
e281682b
SM		 7111
7112 u8 syndrome[0x20];
7113
b4ff3a36 7114 u8 reserved_at_40[0x8];
e281682b
SM		 7115 u8 srqn[0x18];
7116
b4ff3a36 7117 u8 reserved_at_60[0x20];
e281682b
SM		 7118};
7119
7120struct mlx5_ifc_create_srq_in_bits {
7121 u8 opcode[0x10];
a0d8c054 7122 u8 uid[0x10];
e281682b 7123
b4ff3a36 7124 u8 reserved_at_20[0x10];
e281682b
SM		 7125 u8 op_mod[0x10];
7126
b4ff3a36 7127 u8 reserved_at_40[0x40];
e281682b
SM		 7128
7129 struct mlx5_ifc_srqc_bits srq_context_entry;
7130
b4ff3a36 7131 u8 reserved_at_280[0x600];
e281682b
SM		 7132
7133 u8 pas[0][0x40];
7134};
7135
7136struct mlx5_ifc_create_sq_out_bits {
7137 u8 status[0x8];
b4ff3a36 7138 u8 reserved_at_8[0x18];
e281682b
SM		 7139
7140 u8 syndrome[0x20];
7141
b4ff3a36 7142 u8 reserved_at_40[0x8];
e281682b
SM		 7143 u8 sqn[0x18];
7144
b4ff3a36 7145 u8 reserved_at_60[0x20];
e281682b
SM		 7146};
7147
7148struct mlx5_ifc_create_sq_in_bits {
7149 u8 opcode[0x10];
430ae0d5 7150 u8 uid[0x10];
e281682b 7151
b4ff3a36 7152 u8 reserved_at_20[0x10];
e281682b
SM		 7153 u8 op_mod[0x10];
7154
b4ff3a36 7155 u8 reserved_at_40[0xc0];
e281682b
SM		 7156
7157 struct mlx5_ifc_sqc_bits ctx;
7158};
7159
813f8540
MHY		 7160struct mlx5_ifc_create_scheduling_element_out_bits {
7161 u8 status[0x8];
7162 u8 reserved_at_8[0x18];
7163
7164 u8 syndrome[0x20];
7165
7166 u8 reserved_at_40[0x40];
7167
7168 u8 scheduling_element_id[0x20];
7169
7170 u8 reserved_at_a0[0x160];
7171};
7172
7173struct mlx5_ifc_create_scheduling_element_in_bits {
7174 u8 opcode[0x10];
7175 u8 reserved_at_10[0x10];
7176
7177 u8 reserved_at_20[0x10];
7178 u8 op_mod[0x10];
7179
7180 u8 scheduling_hierarchy[0x8];
7181 u8 reserved_at_48[0x18];
7182
7183 u8 reserved_at_60[0xa0];
7184
7185 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7186
7187 u8 reserved_at_300[0x100];
7188};
7189
e281682b
SM		 7190struct mlx5_ifc_create_rqt_out_bits {
7191 u8 status[0x8];
b4ff3a36 7192 u8 reserved_at_8[0x18];
e281682b
SM		 7193
7194 u8 syndrome[0x20];
7195
b4ff3a36 7196 u8 reserved_at_40[0x8];
e281682b
SM		 7197 u8 rqtn[0x18];
7198
b4ff3a36 7199 u8 reserved_at_60[0x20];
e281682b
SM		 7200};
7201
7202struct mlx5_ifc_create_rqt_in_bits {
7203 u8 opcode[0x10];
bd371975 7204 u8 uid[0x10];
e281682b 7205
b4ff3a36 7206 u8 reserved_at_20[0x10];
e281682b
SM		 7207 u8 op_mod[0x10];
7208
b4ff3a36 7209 u8 reserved_at_40[0xc0];
e281682b
SM		 7210
7211 struct mlx5_ifc_rqtc_bits rqt_context;
7212};
7213
7214struct mlx5_ifc_create_rq_out_bits {
7215 u8 status[0x8];
b4ff3a36 7216 u8 reserved_at_8[0x18];
e281682b
SM		 7217
7218 u8 syndrome[0x20];
7219
b4ff3a36 7220 u8 reserved_at_40[0x8];
e281682b
SM		 7221 u8 rqn[0x18];
7222
b4ff3a36 7223 u8 reserved_at_60[0x20];
e281682b
SM		 7224};
7225
7226struct mlx5_ifc_create_rq_in_bits {
7227 u8 opcode[0x10];
d269b3af 7228 u8 uid[0x10];
e281682b 7229
b4ff3a36 7230 u8 reserved_at_20[0x10];
e281682b
SM		 7231 u8 op_mod[0x10];
7232
b4ff3a36 7233 u8 reserved_at_40[0xc0];
e281682b
SM		 7234
7235 struct mlx5_ifc_rqc_bits ctx;
7236};
7237
7238struct mlx5_ifc_create_rmp_out_bits {
7239 u8 status[0x8];
b4ff3a36 7240 u8 reserved_at_8[0x18];
e281682b
SM		 7241
7242 u8 syndrome[0x20];
7243
b4ff3a36 7244 u8 reserved_at_40[0x8];
e281682b
SM		 7245 u8 rmpn[0x18];
7246
b4ff3a36 7247 u8 reserved_at_60[0x20];
e281682b
SM		 7248};
7249
7250struct mlx5_ifc_create_rmp_in_bits {
7251 u8 opcode[0x10];
a0d8c054 7252 u8 uid[0x10];
e281682b 7253
b4ff3a36 7254 u8 reserved_at_20[0x10];
e281682b
SM		 7255 u8 op_mod[0x10];
7256
b4ff3a36 7257 u8 reserved_at_40[0xc0];
e281682b
SM		 7258
7259 struct mlx5_ifc_rmpc_bits ctx;
7260};
7261
7262struct mlx5_ifc_create_qp_out_bits {
7263 u8 status[0x8];
b4ff3a36 7264 u8 reserved_at_8[0x18];
e281682b
SM		 7265
7266 u8 syndrome[0x20];
7267
b4ff3a36 7268 u8 reserved_at_40[0x8];
e281682b
SM		 7269 u8 qpn[0x18];
7270
b4ff3a36 7271 u8 reserved_at_60[0x20];
e281682b
SM		 7272};
7273
7274struct mlx5_ifc_create_qp_in_bits {
7275 u8 opcode[0x10];
4ac63ec7 7276 u8 uid[0x10];
e281682b 7277
b4ff3a36 7278 u8 reserved_at_20[0x10];
e281682b
SM		 7279 u8 op_mod[0x10];
7280
b4ff3a36 7281 u8 reserved_at_40[0x40];
e281682b
SM		 7282
7283 u8 opt_param_mask[0x20];
7284
b4ff3a36 7285 u8 reserved_at_a0[0x20];
e281682b
SM		 7286
7287 struct mlx5_ifc_qpc_bits qpc;
7288
bd371975
LR		 7289 u8 reserved_at_800[0x60];
7290
7291 u8 wq_umem_valid[0x1];
7292 u8 reserved_at_861[0x1f];
e281682b
SM		 7293
7294 u8 pas[0][0x40];
7295};
7296
7297struct mlx5_ifc_create_psv_out_bits {
7298 u8 status[0x8];
b4ff3a36 7299 u8 reserved_at_8[0x18];
e281682b
SM		 7300
7301 u8 syndrome[0x20];
7302
b4ff3a36 7303 u8 reserved_at_40[0x40];
e281682b 7304
b4ff3a36 7305 u8 reserved_at_80[0x8];
e281682b
SM		 7306 u8 psv0_index[0x18];
7307
b4ff3a36 7308 u8 reserved_at_a0[0x8];
e281682b
SM		 7309 u8 psv1_index[0x18];
7310
b4ff3a36 7311 u8 reserved_at_c0[0x8];
e281682b
SM		 7312 u8 psv2_index[0x18];
7313
b4ff3a36 7314 u8 reserved_at_e0[0x8];
e281682b
SM		 7315 u8 psv3_index[0x18];
7316};
7317
7318struct mlx5_ifc_create_psv_in_bits {
7319 u8 opcode[0x10];
b4ff3a36 7320 u8 reserved_at_10[0x10];
e281682b 7321
b4ff3a36 7322 u8 reserved_at_20[0x10];
e281682b
SM		 7323 u8 op_mod[0x10];
7324
7325 u8 num_psv[0x4];
b4ff3a36 7326 u8 reserved_at_44[0x4];
e281682b
SM		 7327 u8 pd[0x18];
7328
b4ff3a36 7329 u8 reserved_at_60[0x20];
e281682b
SM		 7330};
7331
7332struct mlx5_ifc_create_mkey_out_bits {
7333 u8 status[0x8];
b4ff3a36 7334 u8 reserved_at_8[0x18];
e281682b
SM		 7335
7336 u8 syndrome[0x20];
7337
b4ff3a36 7338 u8 reserved_at_40[0x8];
e281682b
SM		 7339 u8 mkey_index[0x18];
7340
b4ff3a36 7341 u8 reserved_at_60[0x20];
e281682b
SM		 7342};
7343
7344struct mlx5_ifc_create_mkey_in_bits {
7345 u8 opcode[0x10];
b4ff3a36 7346 u8 reserved_at_10[0x10];
e281682b 7347
b4ff3a36 7348 u8 reserved_at_20[0x10];
e281682b
SM		 7349 u8 op_mod[0x10];
7350
b4ff3a36 7351 u8 reserved_at_40[0x20];
e281682b
SM		 7352
7353 u8 pg_access[0x1];
bd371975
LR		 7354 u8 mkey_umem_valid[0x1];
7355 u8 reserved_at_62[0x1e];
e281682b
SM		 7356
7357 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7358
b4ff3a36 7359 u8 reserved_at_280[0x80];
e281682b
SM		 7360
7361 u8 translations_octword_actual_size[0x20];
7362
b4ff3a36 7363 u8 reserved_at_320[0x560];
e281682b
SM		 7364
7365 u8 klm_pas_mtt[0][0x20];
7366};
7367
7368struct mlx5_ifc_create_flow_table_out_bits {
7369 u8 status[0x8];
b4ff3a36 7370 u8 reserved_at_8[0x18];
e281682b
SM		 7371
7372 u8 syndrome[0x20];
7373
b4ff3a36 7374 u8 reserved_at_40[0x8];
e281682b
SM		 7375 u8 table_id[0x18];
7376
b4ff3a36 7377 u8 reserved_at_60[0x20];
e281682b
SM		 7378};
7379
0c90e9c6 7380struct mlx5_ifc_flow_table_context_bits {
60786f09 7381 u8 reformat_en[0x1];
0c90e9c6 7382 u8 decap_en[0x1];
c6d4e45d
EB		 7383 u8 reserved_at_2[0x1];
7384 u8 termination_table[0x1];
0c90e9c6
MG		 7385 u8 table_miss_action[0x4];
7386 u8 level[0x8];
7387 u8 reserved_at_10[0x8];
7388 u8 log_size[0x8];
7389
7390 u8 reserved_at_20[0x8];
7391 u8 table_miss_id[0x18];
7392
7393 u8 reserved_at_40[0x8];
7394 u8 lag_master_next_table_id[0x18];
7395
7396 u8 reserved_at_60[0xe0];
7397};
7398
e281682b
SM		 7399struct mlx5_ifc_create_flow_table_in_bits {
7400 u8 opcode[0x10];
b4ff3a36 7401 u8 reserved_at_10[0x10];
e281682b 7402
b4ff3a36 7403 u8 reserved_at_20[0x10];
e281682b
SM		 7404 u8 op_mod[0x10];
7405
7d5e1423
SM		 7406 u8 other_vport[0x1];
7407 u8 reserved_at_41[0xf];
7408 u8 vport_number[0x10];
7409
7410 u8 reserved_at_60[0x20];
e281682b
SM		 7411
7412 u8 table_type[0x8];
b4ff3a36 7413 u8 reserved_at_88[0x18];
e281682b 7414
b4ff3a36 7415 u8 reserved_at_a0[0x20];
e281682b 7416
0c90e9c6 7417 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 7418};
7419
7420struct mlx5_ifc_create_flow_group_out_bits {
7421 u8 status[0x8];
b4ff3a36 7422 u8 reserved_at_8[0x18];
e281682b
SM		 7423
7424 u8 syndrome[0x20];
7425
b4ff3a36 7426 u8 reserved_at_40[0x8];
e281682b
SM		 7427 u8 group_id[0x18];
7428
b4ff3a36 7429 u8 reserved_at_60[0x20];
e281682b
SM		 7430};
7431
7432enum {
71c6e863
AL		 7433 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7434 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7435 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7436 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 7437};
7438
7439struct mlx5_ifc_create_flow_group_in_bits {
7440 u8 opcode[0x10];
b4ff3a36 7441 u8 reserved_at_10[0x10];
e281682b 7442
b4ff3a36 7443 u8 reserved_at_20[0x10];
e281682b
SM		 7444 u8 op_mod[0x10];
7445
7d5e1423
SM		 7446 u8 other_vport[0x1];
7447 u8 reserved_at_41[0xf];
7448 u8 vport_number[0x10];
7449
7450 u8 reserved_at_60[0x20];
e281682b
SM		 7451
7452 u8 table_type[0x8];
b4ff3a36 7453 u8 reserved_at_88[0x18];
e281682b 7454
b4ff3a36 7455 u8 reserved_at_a0[0x8];
e281682b
SM		 7456 u8 table_id[0x18];
7457
3e99df87
SK		 7458 u8 source_eswitch_owner_vhca_id_valid[0x1];
7459
7460 u8 reserved_at_c1[0x1f];
e281682b
SM		 7461
7462 u8 start_flow_index[0x20];
7463
b4ff3a36 7464 u8 reserved_at_100[0x20];
e281682b
SM		 7465
7466 u8 end_flow_index[0x20];
7467
b4ff3a36 7468 u8 reserved_at_140[0xa0];
e281682b 7469
b4ff3a36 7470 u8 reserved_at_1e0[0x18];
e281682b
SM		 7471 u8 match_criteria_enable[0x8];
7472
7473 struct mlx5_ifc_fte_match_param_bits match_criteria;
7474
b4ff3a36 7475 u8 reserved_at_1200[0xe00];
e281682b
SM		 7476};
7477
7478struct mlx5_ifc_create_eq_out_bits {
7479 u8 status[0x8];
b4ff3a36 7480 u8 reserved_at_8[0x18];
e281682b
SM		 7481
7482 u8 syndrome[0x20];
7483
b4ff3a36 7484 u8 reserved_at_40[0x18];
e281682b
SM		 7485 u8 eq_number[0x8];
7486
b4ff3a36 7487 u8 reserved_at_60[0x20];
e281682b
SM		 7488};
7489
7490struct mlx5_ifc_create_eq_in_bits {
7491 u8 opcode[0x10];
c191f934 7492 u8 uid[0x10];
e281682b 7493
b4ff3a36 7494 u8 reserved_at_20[0x10];
e281682b
SM		 7495 u8 op_mod[0x10];
7496
b4ff3a36 7497 u8 reserved_at_40[0x40];
e281682b
SM		 7498
7499 struct mlx5_ifc_eqc_bits eq_context_entry;
7500
b4ff3a36 7501 u8 reserved_at_280[0x40];
e281682b 7502
b9a7ba55 7503 u8 event_bitmask[4][0x40];
e281682b 7504
b9a7ba55 7505 u8 reserved_at_3c0[0x4c0];
e281682b
SM		 7506
7507 u8 pas[0][0x40];
7508};
7509
7510struct mlx5_ifc_create_dct_out_bits {
7511 u8 status[0x8];
b4ff3a36 7512 u8 reserved_at_8[0x18];
e281682b
SM		 7513
7514 u8 syndrome[0x20];
7515
b4ff3a36 7516 u8 reserved_at_40[0x8];
e281682b
SM		 7517 u8 dctn[0x18];
7518
b4ff3a36 7519 u8 reserved_at_60[0x20];
e281682b
SM		 7520};
7521
7522struct mlx5_ifc_create_dct_in_bits {
7523 u8 opcode[0x10];
774ea6ee 7524 u8 uid[0x10];
e281682b 7525
b4ff3a36 7526 u8 reserved_at_20[0x10];
e281682b
SM		 7527 u8 op_mod[0x10];
7528
b4ff3a36 7529 u8 reserved_at_40[0x40];
e281682b
SM		 7530
7531 struct mlx5_ifc_dctc_bits dct_context_entry;
7532
b4ff3a36 7533 u8 reserved_at_280[0x180];
e281682b
SM		 7534};
7535
7536struct mlx5_ifc_create_cq_out_bits {
7537 u8 status[0x8];
b4ff3a36 7538 u8 reserved_at_8[0x18];
e281682b
SM		 7539
7540 u8 syndrome[0x20];
7541
b4ff3a36 7542 u8 reserved_at_40[0x8];
e281682b
SM		 7543 u8 cqn[0x18];
7544
b4ff3a36 7545 u8 reserved_at_60[0x20];
e281682b
SM		 7546};
7547
7548struct mlx5_ifc_create_cq_in_bits {
7549 u8 opcode[0x10];
9ba481e2 7550 u8 uid[0x10];
e281682b 7551
b4ff3a36 7552 u8 reserved_at_20[0x10];
e281682b
SM		 7553 u8 op_mod[0x10];
7554
b4ff3a36 7555 u8 reserved_at_40[0x40];
e281682b
SM		 7556
7557 struct mlx5_ifc_cqc_bits cq_context;
7558
bd371975
LR		 7559 u8 reserved_at_280[0x60];
7560
7561 u8 cq_umem_valid[0x1];
7562 u8 reserved_at_2e1[0x59f];
e281682b
SM		 7563
7564 u8 pas[0][0x40];
7565};
7566
7567struct mlx5_ifc_config_int_moderation_out_bits {
7568 u8 status[0x8];
b4ff3a36 7569 u8 reserved_at_8[0x18];
e281682b
SM		 7570
7571 u8 syndrome[0x20];
7572
b4ff3a36 7573 u8 reserved_at_40[0x4];
e281682b
SM		 7574 u8 min_delay[0xc];
7575 u8 int_vector[0x10];
7576
b4ff3a36 7577 u8 reserved_at_60[0x20];
e281682b
SM		 7578};
7579
7580enum {
7581 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7582 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7583};
7584
7585struct mlx5_ifc_config_int_moderation_in_bits {
7586 u8 opcode[0x10];
b4ff3a36 7587 u8 reserved_at_10[0x10];
e281682b 7588
b4ff3a36 7589 u8 reserved_at_20[0x10];
e281682b
SM		 7590 u8 op_mod[0x10];
7591
b4ff3a36 7592 u8 reserved_at_40[0x4];
e281682b
SM		 7593 u8 min_delay[0xc];
7594 u8 int_vector[0x10];
7595
b4ff3a36 7596 u8 reserved_at_60[0x20];
e281682b
SM		 7597};
7598
7599struct mlx5_ifc_attach_to_mcg_out_bits {
7600 u8 status[0x8];
b4ff3a36 7601 u8 reserved_at_8[0x18];
e281682b
SM		 7602
7603 u8 syndrome[0x20];
7604
b4ff3a36 7605 u8 reserved_at_40[0x40];
e281682b
SM		 7606};
7607
7608struct mlx5_ifc_attach_to_mcg_in_bits {
7609 u8 opcode[0x10];
bd371975 7610 u8 uid[0x10];
e281682b 7611
b4ff3a36 7612 u8 reserved_at_20[0x10];
e281682b
SM		 7613 u8 op_mod[0x10];
7614
b4ff3a36 7615 u8 reserved_at_40[0x8];
e281682b
SM		 7616 u8 qpn[0x18];
7617
b4ff3a36 7618 u8 reserved_at_60[0x20];
e281682b
SM		 7619
7620 u8 multicast_gid[16][0x8];
7621};
7622
7486216b
SM		 7623struct mlx5_ifc_arm_xrq_out_bits {
7624 u8 status[0x8];
7625 u8 reserved_at_8[0x18];
7626
7627 u8 syndrome[0x20];
7628
7629 u8 reserved_at_40[0x40];
7630};
7631
7632struct mlx5_ifc_arm_xrq_in_bits {
7633 u8 opcode[0x10];
7634 u8 reserved_at_10[0x10];
7635
7636 u8 reserved_at_20[0x10];
7637 u8 op_mod[0x10];
7638
7639 u8 reserved_at_40[0x8];
7640 u8 xrqn[0x18];
7641
7642 u8 reserved_at_60[0x10];
7643 u8 lwm[0x10];
7644};
7645
e281682b
SM		 7646struct mlx5_ifc_arm_xrc_srq_out_bits {
7647 u8 status[0x8];
b4ff3a36 7648 u8 reserved_at_8[0x18];
e281682b
SM		 7649
7650 u8 syndrome[0x20];
7651
b4ff3a36 7652 u8 reserved_at_40[0x40];
e281682b
SM		 7653};
7654
7655enum {
7656 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7657};
7658
7659struct mlx5_ifc_arm_xrc_srq_in_bits {
7660 u8 opcode[0x10];
a0d8c054 7661 u8 uid[0x10];
e281682b 7662
b4ff3a36 7663 u8 reserved_at_20[0x10];
e281682b
SM		 7664 u8 op_mod[0x10];
7665
b4ff3a36 7666 u8 reserved_at_40[0x8];
e281682b
SM		 7667 u8 xrc_srqn[0x18];
7668
b4ff3a36 7669 u8 reserved_at_60[0x10];
e281682b
SM		 7670 u8 lwm[0x10];
7671};
7672
7673struct mlx5_ifc_arm_rq_out_bits {
7674 u8 status[0x8];
b4ff3a36 7675 u8 reserved_at_8[0x18];
e281682b
SM		 7676
7677 u8 syndrome[0x20];
7678
b4ff3a36 7679 u8 reserved_at_40[0x40];
e281682b
SM		 7680};
7681
7682enum {
7486216b
SM		 7683 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7684 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7685};
7686
7687struct mlx5_ifc_arm_rq_in_bits {
7688 u8 opcode[0x10];
a0d8c054 7689 u8 uid[0x10];
e281682b 7690
b4ff3a36 7691 u8 reserved_at_20[0x10];
e281682b
SM		 7692 u8 op_mod[0x10];
7693
b4ff3a36 7694 u8 reserved_at_40[0x8];
e281682b
SM		 7695 u8 srq_number[0x18];
7696
b4ff3a36 7697 u8 reserved_at_60[0x10];
e281682b
SM		 7698 u8 lwm[0x10];
7699};
7700
7701struct mlx5_ifc_arm_dct_out_bits {
7702 u8 status[0x8];
b4ff3a36 7703 u8 reserved_at_8[0x18];
e281682b
SM		 7704
7705 u8 syndrome[0x20];
7706
b4ff3a36 7707 u8 reserved_at_40[0x40];
e281682b
SM		 7708};
7709
7710struct mlx5_ifc_arm_dct_in_bits {
7711 u8 opcode[0x10];
b4ff3a36 7712 u8 reserved_at_10[0x10];
e281682b 7713
b4ff3a36 7714 u8 reserved_at_20[0x10];
e281682b
SM		 7715 u8 op_mod[0x10];
7716
b4ff3a36 7717 u8 reserved_at_40[0x8];
e281682b
SM		 7718 u8 dct_number[0x18];
7719
b4ff3a36 7720 u8 reserved_at_60[0x20];
e281682b
SM		 7721};
7722
7723struct mlx5_ifc_alloc_xrcd_out_bits {
7724 u8 status[0x8];
b4ff3a36 7725 u8 reserved_at_8[0x18];
e281682b
SM		 7726
7727 u8 syndrome[0x20];
7728
b4ff3a36 7729 u8 reserved_at_40[0x8];
e281682b
SM		 7730 u8 xrcd[0x18];
7731
b4ff3a36 7732 u8 reserved_at_60[0x20];
e281682b
SM		 7733};
7734
7735struct mlx5_ifc_alloc_xrcd_in_bits {
7736 u8 opcode[0x10];
bd371975 7737 u8 uid[0x10];
e281682b 7738
b4ff3a36 7739 u8 reserved_at_20[0x10];
e281682b
SM		 7740 u8 op_mod[0x10];
7741
b4ff3a36 7742 u8 reserved_at_40[0x40];
e281682b
SM		 7743};
7744
7745struct mlx5_ifc_alloc_uar_out_bits {
7746 u8 status[0x8];
b4ff3a36 7747 u8 reserved_at_8[0x18];
e281682b
SM		 7748
7749 u8 syndrome[0x20];
7750
b4ff3a36 7751 u8 reserved_at_40[0x8];
e281682b
SM		 7752 u8 uar[0x18];
7753
b4ff3a36 7754 u8 reserved_at_60[0x20];
e281682b
SM		 7755};
7756
7757struct mlx5_ifc_alloc_uar_in_bits {
7758 u8 opcode[0x10];
b4ff3a36 7759 u8 reserved_at_10[0x10];
e281682b 7760
b4ff3a36 7761 u8 reserved_at_20[0x10];
e281682b
SM		 7762 u8 op_mod[0x10];
7763
b4ff3a36 7764 u8 reserved_at_40[0x40];
e281682b
SM		 7765};
7766
7767struct mlx5_ifc_alloc_transport_domain_out_bits {
7768 u8 status[0x8];
b4ff3a36 7769 u8 reserved_at_8[0x18];
e281682b
SM		 7770
7771 u8 syndrome[0x20];
7772
b4ff3a36 7773 u8 reserved_at_40[0x8];
e281682b
SM		 7774 u8 transport_domain[0x18];
7775
b4ff3a36 7776 u8 reserved_at_60[0x20];
e281682b
SM		 7777};
7778
7779struct mlx5_ifc_alloc_transport_domain_in_bits {
7780 u8 opcode[0x10];
71bef2fd 7781 u8 uid[0x10];
e281682b 7782
b4ff3a36 7783 u8 reserved_at_20[0x10];
e281682b
SM		 7784 u8 op_mod[0x10];
7785
b4ff3a36 7786 u8 reserved_at_40[0x40];
e281682b
SM		 7787};
7788
7789struct mlx5_ifc_alloc_q_counter_out_bits {
7790 u8 status[0x8];
b4ff3a36 7791 u8 reserved_at_8[0x18];
e281682b
SM		 7792
7793 u8 syndrome[0x20];
7794
b4ff3a36 7795 u8 reserved_at_40[0x18];
e281682b
SM		 7796 u8 counter_set_id[0x8];
7797
b4ff3a36 7798 u8 reserved_at_60[0x20];
e281682b
SM		 7799};
7800
7801struct mlx5_ifc_alloc_q_counter_in_bits {
7802 u8 opcode[0x10];
2acc7957 7803 u8 uid[0x10];
e281682b 7804
b4ff3a36 7805 u8 reserved_at_20[0x10];
e281682b
SM		 7806 u8 op_mod[0x10];
7807
b4ff3a36 7808 u8 reserved_at_40[0x40];
e281682b
SM		 7809};
7810
7811struct mlx5_ifc_alloc_pd_out_bits {
7812 u8 status[0x8];
b4ff3a36 7813 u8 reserved_at_8[0x18];
e281682b
SM		 7814
7815 u8 syndrome[0x20];
7816
b4ff3a36 7817 u8 reserved_at_40[0x8];
e281682b
SM		 7818 u8 pd[0x18];
7819
b4ff3a36 7820 u8 reserved_at_60[0x20];
e281682b
SM		 7821};
7822
7823struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 7824 u8 opcode[0x10];
bd371975 7825 u8 uid[0x10];
9dc0b289
AV		 7826
7827 u8 reserved_at_20[0x10];
7828 u8 op_mod[0x10];
7829
7830 u8 reserved_at_40[0x40];
7831};
7832
7833struct mlx5_ifc_alloc_flow_counter_out_bits {
7834 u8 status[0x8];
7835 u8 reserved_at_8[0x18];
7836
7837 u8 syndrome[0x20];
7838
a8ffcc74 7839 u8 flow_counter_id[0x20];
9dc0b289
AV		 7840
7841 u8 reserved_at_60[0x20];
7842};
7843
7844struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7845 u8 opcode[0x10];
b4ff3a36 7846 u8 reserved_at_10[0x10];
e281682b 7847
b4ff3a36 7848 u8 reserved_at_20[0x10];
e281682b
SM		 7849 u8 op_mod[0x10];
7850
8536a6bf
GT		 7851 u8 reserved_at_40[0x38];
7852 u8 flow_counter_bulk[0x8];
e281682b
SM		 7853};
7854
7855struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7856 u8 status[0x8];
b4ff3a36 7857 u8 reserved_at_8[0x18];
e281682b
SM		 7858
7859 u8 syndrome[0x20];
7860
b4ff3a36 7861 u8 reserved_at_40[0x40];
e281682b
SM		 7862};
7863
7864struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7865 u8 opcode[0x10];
b4ff3a36 7866 u8 reserved_at_10[0x10];
e281682b 7867
b4ff3a36 7868 u8 reserved_at_20[0x10];
e281682b
SM		 7869 u8 op_mod[0x10];
7870
b4ff3a36 7871 u8 reserved_at_40[0x20];
e281682b 7872
b4ff3a36 7873 u8 reserved_at_60[0x10];
e281682b
SM		 7874 u8 vxlan_udp_port[0x10];
7875};
7876
37e92a9d 7877struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7878 u8 status[0x8];
7879 u8 reserved_at_8[0x18];
7880
7881 u8 syndrome[0x20];
7882
7883 u8 reserved_at_40[0x40];
7884};
7885
37e92a9d 7886struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7887 u8 opcode[0x10];
7888 u8 reserved_at_10[0x10];
7889
7890 u8 reserved_at_20[0x10];
7891 u8 op_mod[0x10];
7892
7893 u8 reserved_at_40[0x10];
7894 u8 rate_limit_index[0x10];
7895
7896 u8 reserved_at_60[0x20];
7897
7898 u8 rate_limit[0x20];
37e92a9d 7899
05d3ac97
BW		 7900 u8 burst_upper_bound[0x20];
7901
7902 u8 reserved_at_c0[0x10];
7903 u8 typical_packet_size[0x10];
7904
7905 u8 reserved_at_e0[0x120];
7486216b
SM		 7906};
7907
e281682b
SM		 7908struct mlx5_ifc_access_register_out_bits {
7909 u8 status[0x8];
b4ff3a36 7910 u8 reserved_at_8[0x18];
e281682b
SM		 7911
7912 u8 syndrome[0x20];
7913
b4ff3a36 7914 u8 reserved_at_40[0x40];
e281682b
SM		 7915
7916 u8 register_data[0][0x20];
7917};
7918
7919enum {
7920 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7921 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7922};
7923
7924struct mlx5_ifc_access_register_in_bits {
7925 u8 opcode[0x10];
b4ff3a36 7926 u8 reserved_at_10[0x10];
e281682b 7927
b4ff3a36 7928 u8 reserved_at_20[0x10];
e281682b
SM		 7929 u8 op_mod[0x10];
7930
b4ff3a36 7931 u8 reserved_at_40[0x10];
e281682b
SM		 7932 u8 register_id[0x10];
7933
7934 u8 argument[0x20];
7935
7936 u8 register_data[0][0x20];
7937};
7938
7939struct mlx5_ifc_sltp_reg_bits {
7940 u8 status[0x4];
7941 u8 version[0x4];
7942 u8 local_port[0x8];
7943 u8 pnat[0x2];
b4ff3a36 7944 u8 reserved_at_12[0x2];
e281682b 7945 u8 lane[0x4];
b4ff3a36 7946 u8 reserved_at_18[0x8];
e281682b 7947
b4ff3a36 7948 u8 reserved_at_20[0x20];
e281682b 7949
b4ff3a36 7950 u8 reserved_at_40[0x7];
e281682b
SM		 7951 u8 polarity[0x1];
7952 u8 ob_tap0[0x8];
7953 u8 ob_tap1[0x8];
7954 u8 ob_tap2[0x8];
7955
b4ff3a36 7956 u8 reserved_at_60[0xc];
e281682b
SM		 7957 u8 ob_preemp_mode[0x4];
7958 u8 ob_reg[0x8];
7959 u8 ob_bias[0x8];
7960
b4ff3a36 7961 u8 reserved_at_80[0x20];
e281682b
SM		 7962};
7963
7964struct mlx5_ifc_slrg_reg_bits {
7965 u8 status[0x4];
7966 u8 version[0x4];
7967 u8 local_port[0x8];
7968 u8 pnat[0x2];
b4ff3a36 7969 u8 reserved_at_12[0x2];
e281682b 7970 u8 lane[0x4];
b4ff3a36 7971 u8 reserved_at_18[0x8];
e281682b
SM		 7972
7973 u8 time_to_link_up[0x10];
b4ff3a36 7974 u8 reserved_at_30[0xc];
e281682b
SM		 7975 u8 grade_lane_speed[0x4];
7976
7977 u8 grade_version[0x8];
7978 u8 grade[0x18];
7979
b4ff3a36 7980 u8 reserved_at_60[0x4];
e281682b
SM		 7981 u8 height_grade_type[0x4];
7982 u8 height_grade[0x18];
7983
7984 u8 height_dz[0x10];
7985 u8 height_dv[0x10];
7986
b4ff3a36 7987 u8 reserved_at_a0[0x10];
e281682b
SM		 7988 u8 height_sigma[0x10];
7989
b4ff3a36 7990 u8 reserved_at_c0[0x20];
e281682b 7991
b4ff3a36 7992 u8 reserved_at_e0[0x4];
e281682b
SM		 7993 u8 phase_grade_type[0x4];
7994 u8 phase_grade[0x18];
7995
b4ff3a36 7996 u8 reserved_at_100[0x8];
e281682b 7997 u8 phase_eo_pos[0x8];
b4ff3a36 7998 u8 reserved_at_110[0x8];
e281682b
SM		 7999 u8 phase_eo_neg[0x8];
8000
8001 u8 ffe_set_tested[0x10];
8002 u8 test_errors_per_lane[0x10];
8003};
8004
8005struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 8006 u8 reserved_at_0[0x8];
e281682b 8007 u8 local_port[0x8];
b4ff3a36 8008 u8 reserved_at_10[0x10];
e281682b 8009
b4ff3a36 8010 u8 reserved_at_20[0x1c];
e281682b
SM		 8011 u8 vl_hw_cap[0x4];
8012
b4ff3a36 8013 u8 reserved_at_40[0x1c];
e281682b
SM		 8014 u8 vl_admin[0x4];
8015
b4ff3a36 8016 u8 reserved_at_60[0x1c];
e281682b
SM		 8017 u8 vl_operational[0x4];
8018};
8019
8020struct mlx5_ifc_pude_reg_bits {
8021 u8 swid[0x8];
8022 u8 local_port[0x8];
b4ff3a36 8023 u8 reserved_at_10[0x4];
e281682b 8024 u8 admin_status[0x4];
b4ff3a36 8025 u8 reserved_at_18[0x4];
e281682b
SM		 8026 u8 oper_status[0x4];
8027
b4ff3a36 8028 u8 reserved_at_20[0x60];
e281682b
SM		 8029};
8030
8031struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 8032 u8 reserved_at_0[0x1];
7486216b 8033 u8 an_disable_admin[0x1];
e7e31ca4
BW		 8034 u8 an_disable_cap[0x1];
8035 u8 reserved_at_3[0x5];
e281682b 8036 u8 local_port[0x8];
b4ff3a36 8037 u8 reserved_at_10[0xd];
e281682b
SM		 8038 u8 proto_mask[0x3];
8039
7486216b 8040 u8 an_status[0x4];
a0a89989
AL		 8041 u8 reserved_at_24[0x1c];
8042
8043 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 8044
8045 u8 eth_proto_capability[0x20];
8046
8047 u8 ib_link_width_capability[0x10];
8048 u8 ib_proto_capability[0x10];
8049
a0a89989 8050 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 8051
8052 u8 eth_proto_admin[0x20];
8053
8054 u8 ib_link_width_admin[0x10];
8055 u8 ib_proto_admin[0x10];
8056
a0a89989 8057 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 8058
8059 u8 eth_proto_oper[0x20];
8060
8061 u8 ib_link_width_oper[0x10];
8062 u8 ib_proto_oper[0x10];
8063
5b4793f8
EBE		 8064 u8 reserved_at_160[0x1c];
8065 u8 connector_type[0x4];
e281682b
SM		 8066
8067 u8 eth_proto_lp_advertise[0x20];
8068
b4ff3a36 8069 u8 reserved_at_1a0[0x60];
e281682b
SM		 8070};
8071
7d5e1423
SM		 8072struct mlx5_ifc_mlcr_reg_bits {
8073 u8 reserved_at_0[0x8];
8074 u8 local_port[0x8];
8075 u8 reserved_at_10[0x20];
8076
8077 u8 beacon_duration[0x10];
8078 u8 reserved_at_40[0x10];
8079
8080 u8 beacon_remain[0x10];
8081};
8082
e281682b 8083struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 8084 u8 reserved_at_0[0x20];
e281682b
SM		 8085
8086 u8 algorithm_options[0x10];
b4ff3a36 8087 u8 reserved_at_30[0x4];
e281682b
SM		 8088 u8 repetitions_mode[0x4];
8089 u8 num_of_repetitions[0x8];
8090
8091 u8 grade_version[0x8];
8092 u8 height_grade_type[0x4];
8093 u8 phase_grade_type[0x4];
8094 u8 height_grade_weight[0x8];
8095 u8 phase_grade_weight[0x8];
8096
8097 u8 gisim_measure_bits[0x10];
8098 u8 adaptive_tap_measure_bits[0x10];
8099
8100 u8 ber_bath_high_error_threshold[0x10];
8101 u8 ber_bath_mid_error_threshold[0x10];
8102
8103 u8 ber_bath_low_error_threshold[0x10];
8104 u8 one_ratio_high_threshold[0x10];
8105
8106 u8 one_ratio_high_mid_threshold[0x10];
8107 u8 one_ratio_low_mid_threshold[0x10];
8108
8109 u8 one_ratio_low_threshold[0x10];
8110 u8 ndeo_error_threshold[0x10];
8111
8112 u8 mixer_offset_step_size[0x10];
b4ff3a36 8113 u8 reserved_at_110[0x8];
e281682b
SM		 8114 u8 mix90_phase_for_voltage_bath[0x8];
8115
8116 u8 mixer_offset_start[0x10];
8117 u8 mixer_offset_end[0x10];
8118
b4ff3a36 8119 u8 reserved_at_140[0x15];
e281682b
SM		 8120 u8 ber_test_time[0xb];
8121};
8122
8123struct mlx5_ifc_pspa_reg_bits {
8124 u8 swid[0x8];
8125 u8 local_port[0x8];
8126 u8 sub_port[0x8];
b4ff3a36 8127 u8 reserved_at_18[0x8];
e281682b 8128
b4ff3a36 8129 u8 reserved_at_20[0x20];
e281682b
SM		 8130};
8131
8132struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 8133 u8 reserved_at_0[0x8];
e281682b 8134 u8 local_port[0x8];
b4ff3a36 8135 u8 reserved_at_10[0x5];
e281682b 8136 u8 prio[0x3];
b4ff3a36 8137 u8 reserved_at_18[0x6];
e281682b
SM		 8138 u8 mode[0x2];
8139
b4ff3a36 8140 u8 reserved_at_20[0x20];
e281682b 8141
b4ff3a36 8142 u8 reserved_at_40[0x10];
e281682b
SM		 8143 u8 min_threshold[0x10];
8144
b4ff3a36 8145 u8 reserved_at_60[0x10];
e281682b
SM		 8146 u8 max_threshold[0x10];
8147
b4ff3a36 8148 u8 reserved_at_80[0x10];
e281682b
SM		 8149 u8 mark_probability_denominator[0x10];
8150
b4ff3a36 8151 u8 reserved_at_a0[0x60];
e281682b
SM		 8152};
8153
8154struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 8155 u8 reserved_at_0[0x8];
e281682b 8156 u8 local_port[0x8];
b4ff3a36 8157 u8 reserved_at_10[0x10];
e281682b 8158
b4ff3a36 8159 u8 reserved_at_20[0x60];
e281682b 8160
b4ff3a36 8161 u8 reserved_at_80[0x1c];
e281682b
SM		 8162 u8 wrps_admin[0x4];
8163
b4ff3a36 8164 u8 reserved_at_a0[0x1c];
e281682b
SM		 8165 u8 wrps_status[0x4];
8166
b4ff3a36 8167 u8 reserved_at_c0[0x8];
e281682b 8168 u8 up_threshold[0x8];
b4ff3a36 8169 u8 reserved_at_d0[0x8];
e281682b
SM		 8170 u8 down_threshold[0x8];
8171
b4ff3a36 8172 u8 reserved_at_e0[0x20];
e281682b 8173
b4ff3a36 8174 u8 reserved_at_100[0x1c];
e281682b
SM		 8175 u8 srps_admin[0x4];
8176
b4ff3a36 8177 u8 reserved_at_120[0x1c];
e281682b
SM		 8178 u8 srps_status[0x4];
8179
b4ff3a36 8180 u8 reserved_at_140[0x40];
e281682b
SM		 8181};
8182
8183struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 8184 u8 reserved_at_0[0x8];
e281682b 8185 u8 local_port[0x8];
b4ff3a36 8186 u8 reserved_at_10[0x10];
e281682b 8187
b4ff3a36 8188 u8 reserved_at_20[0x8];
e281682b 8189 u8 lb_cap[0x8];
b4ff3a36 8190 u8 reserved_at_30[0x8];
e281682b
SM		 8191 u8 lb_en[0x8];
8192};
8193
8194struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 8195 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 8196 u8 local_port[0x8];
8197 u8 reserved_at_10[0x10];
e281682b 8198
4b5b9c7d 8199 u8 reserved_at_20[0x20];
e281682b 8200
4b5b9c7d
SA		 8201 u8 port_profile_mode[0x8];
8202 u8 static_port_profile[0x8];
8203 u8 active_port_profile[0x8];
8204 u8 reserved_at_58[0x8];
e281682b 8205
4b5b9c7d
SA		 8206 u8 retransmission_active[0x8];
8207 u8 fec_mode_active[0x18];
e281682b 8208
4b5b9c7d
SA		 8209 u8 rs_fec_correction_bypass_cap[0x4];
8210 u8 reserved_at_84[0x8];
8211 u8 fec_override_cap_56g[0x4];
8212 u8 fec_override_cap_100g[0x4];
8213 u8 fec_override_cap_50g[0x4];
8214 u8 fec_override_cap_25g[0x4];
8215 u8 fec_override_cap_10g_40g[0x4];
8216
8217 u8 rs_fec_correction_bypass_admin[0x4];
8218 u8 reserved_at_a4[0x8];
8219 u8 fec_override_admin_56g[0x4];
8220 u8 fec_override_admin_100g[0x4];
8221 u8 fec_override_admin_50g[0x4];
8222 u8 fec_override_admin_25g[0x4];
8223 u8 fec_override_admin_10g_40g[0x4];
e281682b
SM		 8224};
8225
8226struct mlx5_ifc_ppcnt_reg_bits {
8227 u8 swid[0x8];
8228 u8 local_port[0x8];
8229 u8 pnat[0x2];
b4ff3a36 8230 u8 reserved_at_12[0x8];
e281682b
SM		 8231 u8 grp[0x6];
8232
8233 u8 clr[0x1];
b4ff3a36 8234 u8 reserved_at_21[0x1c];
e281682b
SM		 8235 u8 prio_tc[0x3];
8236
8237 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8238};
8239
4039049b
AL		 8240struct mlx5_ifc_mpein_reg_bits {
8241 u8 reserved_at_0[0x2];
8242 u8 depth[0x6];
8243 u8 pcie_index[0x8];
8244 u8 node[0x8];
8245 u8 reserved_at_18[0x8];
8246
8247 u8 capability_mask[0x20];
8248
8249 u8 reserved_at_40[0x8];
8250 u8 link_width_enabled[0x8];
8251 u8 link_speed_enabled[0x10];
8252
8253 u8 lane0_physical_position[0x8];
8254 u8 link_width_active[0x8];
8255 u8 link_speed_active[0x10];
8256
8257 u8 num_of_pfs[0x10];
8258 u8 num_of_vfs[0x10];
8259
8260 u8 bdf0[0x10];
8261 u8 reserved_at_b0[0x10];
8262
8263 u8 max_read_request_size[0x4];
8264 u8 max_payload_size[0x4];
8265 u8 reserved_at_c8[0x5];
8266 u8 pwr_status[0x3];
8267 u8 port_type[0x4];
8268 u8 reserved_at_d4[0xb];
8269 u8 lane_reversal[0x1];
8270
8271 u8 reserved_at_e0[0x14];
8272 u8 pci_power[0xc];
8273
8274 u8 reserved_at_100[0x20];
8275
8276 u8 device_status[0x10];
8277 u8 port_state[0x8];
8278 u8 reserved_at_138[0x8];
8279
8280 u8 reserved_at_140[0x10];
8281 u8 receiver_detect_result[0x10];
8282
8283 u8 reserved_at_160[0x20];
8284};
8285
8ed1a630
GP		 8286struct mlx5_ifc_mpcnt_reg_bits {
8287 u8 reserved_at_0[0x8];
8288 u8 pcie_index[0x8];
8289 u8 reserved_at_10[0xa];
8290 u8 grp[0x6];
8291
8292 u8 clr[0x1];
8293 u8 reserved_at_21[0x1f];
8294
8295 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8296};
8297
e281682b 8298struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 8299 u8 reserved_at_0[0x3];
e281682b 8300 u8 single_mac[0x1];
b4ff3a36 8301 u8 reserved_at_4[0x4];
e281682b
SM		 8302 u8 local_port[0x8];
8303 u8 mac_47_32[0x10];
8304
8305 u8 mac_31_0[0x20];
8306
b4ff3a36 8307 u8 reserved_at_40[0x40];
e281682b
SM		 8308};
8309
8310struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 8311 u8 reserved_at_0[0x8];
e281682b 8312 u8 local_port[0x8];
b4ff3a36 8313 u8 reserved_at_10[0x10];
e281682b
SM		 8314
8315 u8 max_mtu[0x10];
b4ff3a36 8316 u8 reserved_at_30[0x10];
e281682b
SM		 8317
8318 u8 admin_mtu[0x10];
b4ff3a36 8319 u8 reserved_at_50[0x10];
e281682b
SM		 8320
8321 u8 oper_mtu[0x10];
b4ff3a36 8322 u8 reserved_at_70[0x10];
e281682b
SM		 8323};
8324
8325struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 8326 u8 reserved_at_0[0x8];
e281682b 8327 u8 module[0x8];
b4ff3a36 8328 u8 reserved_at_10[0x10];
e281682b 8329
b4ff3a36 8330 u8 reserved_at_20[0x18];
e281682b
SM		 8331 u8 attenuation_5g[0x8];
8332
b4ff3a36 8333 u8 reserved_at_40[0x18];
e281682b
SM		 8334 u8 attenuation_7g[0x8];
8335
b4ff3a36 8336 u8 reserved_at_60[0x18];
e281682b
SM		 8337 u8 attenuation_12g[0x8];
8338};
8339
8340struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 8341 u8 reserved_at_0[0x8];
e281682b 8342 u8 module[0x8];
b4ff3a36 8343 u8 reserved_at_10[0xc];
e281682b
SM		 8344 u8 module_status[0x4];
8345
b4ff3a36 8346 u8 reserved_at_20[0x60];
e281682b
SM		 8347};
8348
8349struct mlx5_ifc_pmpc_reg_bits {
8350 u8 module_state_updated[32][0x8];
8351};
8352
8353struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 8354 u8 reserved_at_0[0x4];
e281682b
SM		 8355 u8 mlpn_status[0x4];
8356 u8 local_port[0x8];
b4ff3a36 8357 u8 reserved_at_10[0x10];
e281682b
SM		 8358
8359 u8 e[0x1];
b4ff3a36 8360 u8 reserved_at_21[0x1f];
e281682b
SM		 8361};
8362
8363struct mlx5_ifc_pmlp_reg_bits {
8364 u8 rxtx[0x1];
b4ff3a36 8365 u8 reserved_at_1[0x7];
e281682b 8366 u8 local_port[0x8];
b4ff3a36 8367 u8 reserved_at_10[0x8];
e281682b
SM		 8368 u8 width[0x8];
8369
8370 u8 lane0_module_mapping[0x20];
8371
8372 u8 lane1_module_mapping[0x20];
8373
8374 u8 lane2_module_mapping[0x20];
8375
8376 u8 lane3_module_mapping[0x20];
8377
b4ff3a36 8378 u8 reserved_at_a0[0x160];
e281682b
SM		 8379};
8380
8381struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 8382 u8 reserved_at_0[0x8];
e281682b 8383 u8 module[0x8];
b4ff3a36 8384 u8 reserved_at_10[0x4];
e281682b 8385 u8 admin_status[0x4];
b4ff3a36 8386 u8 reserved_at_18[0x4];
e281682b
SM		 8387 u8 oper_status[0x4];
8388
8389 u8 ase[0x1];
8390 u8 ee[0x1];
b4ff3a36 8391 u8 reserved_at_22[0x1c];
e281682b
SM		 8392 u8 e[0x2];
8393
b4ff3a36 8394 u8 reserved_at_40[0x40];
e281682b
SM		 8395};
8396
8397struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 8398 u8 reserved_at_0[0x4];
e281682b 8399 u8 profile_id[0xc];
b4ff3a36 8400 u8 reserved_at_10[0x4];
e281682b 8401 u8 proto_mask[0x4];
b4ff3a36 8402 u8 reserved_at_18[0x8];
e281682b 8403
b4ff3a36 8404 u8 reserved_at_20[0x10];
e281682b
SM		 8405 u8 lane_speed[0x10];
8406
b4ff3a36 8407 u8 reserved_at_40[0x17];
e281682b
SM		 8408 u8 lpbf[0x1];
8409 u8 fec_mode_policy[0x8];
8410
8411 u8 retransmission_capability[0x8];
8412 u8 fec_mode_capability[0x18];
8413
8414 u8 retransmission_support_admin[0x8];
8415 u8 fec_mode_support_admin[0x18];
8416
8417 u8 retransmission_request_admin[0x8];
8418 u8 fec_mode_request_admin[0x18];
8419
b4ff3a36 8420 u8 reserved_at_c0[0x80];
e281682b
SM		 8421};
8422
8423struct mlx5_ifc_plib_reg_bits {
b4ff3a36 8424 u8 reserved_at_0[0x8];
e281682b 8425 u8 local_port[0x8];
b4ff3a36 8426 u8 reserved_at_10[0x8];
e281682b
SM		 8427 u8 ib_port[0x8];
8428
b4ff3a36 8429 u8 reserved_at_20[0x60];
e281682b
SM		 8430};
8431
8432struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 8433 u8 reserved_at_0[0x8];
e281682b 8434 u8 local_port[0x8];
b4ff3a36 8435 u8 reserved_at_10[0xd];
e281682b
SM		 8436 u8 lbf_mode[0x3];
8437
b4ff3a36 8438 u8 reserved_at_20[0x20];
e281682b
SM		 8439};
8440
8441struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 8442 u8 reserved_at_0[0x8];
e281682b 8443 u8 local_port[0x8];
b4ff3a36 8444 u8 reserved_at_10[0x10];
e281682b
SM		 8445
8446 u8 dic[0x1];
b4ff3a36 8447 u8 reserved_at_21[0x19];
e281682b 8448 u8 ipg[0x4];
b4ff3a36 8449 u8 reserved_at_3e[0x2];
e281682b
SM		 8450};
8451
8452struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 8453 u8 reserved_at_0[0x8];
e281682b 8454 u8 local_port[0x8];
b4ff3a36 8455 u8 reserved_at_10[0x10];
e281682b 8456
b4ff3a36 8457 u8 reserved_at_20[0xe0];
e281682b
SM		 8458
8459 u8 port_filter[8][0x20];
8460
8461 u8 port_filter_update_en[8][0x20];
8462};
8463
8464struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 8465 u8 reserved_at_0[0x8];
e281682b 8466 u8 local_port[0x8];
2afa609f
IK		 8467 u8 reserved_at_10[0xb];
8468 u8 ppan_mask_n[0x1];
8469 u8 minor_stall_mask[0x1];
8470 u8 critical_stall_mask[0x1];
8471 u8 reserved_at_1e[0x2];
e281682b
SM		 8472
8473 u8 ppan[0x4];
b4ff3a36 8474 u8 reserved_at_24[0x4];
e281682b 8475 u8 prio_mask_tx[0x8];
b4ff3a36 8476 u8 reserved_at_30[0x8];
e281682b
SM		 8477 u8 prio_mask_rx[0x8];
8478
8479 u8 pptx[0x1];
8480 u8 aptx[0x1];
2afa609f
IK		 8481 u8 pptx_mask_n[0x1];
8482 u8 reserved_at_43[0x5];
e281682b 8483 u8 pfctx[0x8];
b4ff3a36 8484 u8 reserved_at_50[0x10];
e281682b
SM		 8485
8486 u8 pprx[0x1];
8487 u8 aprx[0x1];
2afa609f
IK		 8488 u8 pprx_mask_n[0x1];
8489 u8 reserved_at_63[0x5];
e281682b 8490 u8 pfcrx[0x8];
b4ff3a36 8491 u8 reserved_at_70[0x10];
e281682b 8492
2afa609f
IK		 8493 u8 device_stall_minor_watermark[0x10];
8494 u8 device_stall_critical_watermark[0x10];
8495
8496 u8 reserved_at_a0[0x60];
e281682b
SM		 8497};
8498
8499struct mlx5_ifc_pelc_reg_bits {
8500 u8 op[0x4];
b4ff3a36 8501 u8 reserved_at_4[0x4];
e281682b 8502 u8 local_port[0x8];
b4ff3a36 8503 u8 reserved_at_10[0x10];
e281682b
SM		 8504
8505 u8 op_admin[0x8];
8506 u8 op_capability[0x8];
8507 u8 op_request[0x8];
8508 u8 op_active[0x8];
8509
8510 u8 admin[0x40];
8511
8512 u8 capability[0x40];
8513
8514 u8 request[0x40];
8515
8516 u8 active[0x40];
8517
b4ff3a36 8518 u8 reserved_at_140[0x80];
e281682b
SM		 8519};
8520
8521struct mlx5_ifc_peir_reg_bits {
b4ff3a36 8522 u8 reserved_at_0[0x8];
e281682b 8523 u8 local_port[0x8];
b4ff3a36 8524 u8 reserved_at_10[0x10];
e281682b 8525
b4ff3a36 8526 u8 reserved_at_20[0xc];
e281682b 8527 u8 error_count[0x4];
b4ff3a36 8528 u8 reserved_at_30[0x10];
e281682b 8529
b4ff3a36 8530 u8 reserved_at_40[0xc];
e281682b 8531 u8 lane[0x4];
b4ff3a36 8532 u8 reserved_at_50[0x8];
e281682b
SM		 8533 u8 error_type[0x8];
8534};
8535
5e022dd3
EBE		 8536struct mlx5_ifc_mpegc_reg_bits {
8537 u8 reserved_at_0[0x30];
8538 u8 field_select[0x10];
8539
8540 u8 tx_overflow_sense[0x1];
8541 u8 mark_cqe[0x1];
8542 u8 mark_cnp[0x1];
8543 u8 reserved_at_43[0x1b];
8544 u8 tx_lossy_overflow_oper[0x2];
8545
8546 u8 reserved_at_60[0x100];
8547};
8548
cfdcbcea 8549struct mlx5_ifc_pcam_enhanced_features_bits {
0af5107c
TB		 8550 u8 reserved_at_0[0x6d];
8551 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 8552 u8 reserved_at_6e[0x4];
8553 u8 ptys_extended_ethernet[0x1];
8554 u8 reserved_at_73[0x3];
2fcb12df 8555 u8 pfcc_mask[0x1];
67daf118
SA		 8556 u8 reserved_at_77[0x3];
8557 u8 per_lane_error_counters[0x1];
2dba0797 8558 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8559 u8 ptys_connector_type[0x1];
8560 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8561 u8 ppcnt_discard_group[0x1];
8562 u8 ppcnt_statistical_group[0x1];
8563};
8564
df5f1361
HN		 8565struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8566 u8 port_access_reg_cap_mask_127_to_96[0x20];
8567 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 8568
8569 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8570 u8 pplm[0x1];
8571 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 8572
8573 u8 port_access_reg_cap_mask_31_to_13[0x13];
8574 u8 pbmc[0x1];
8575 u8 pptb[0x1];
75370eb0
ED		 8576 u8 port_access_reg_cap_mask_10_to_09[0x2];
8577 u8 ppcnt[0x1];
8578 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 8579};
8580
cfdcbcea
GP		 8581struct mlx5_ifc_pcam_reg_bits {
8582 u8 reserved_at_0[0x8];
8583 u8 feature_group[0x8];
8584 u8 reserved_at_10[0x8];
8585 u8 access_reg_group[0x8];
8586
8587 u8 reserved_at_20[0x20];
8588
8589 union {
df5f1361 8590 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 8591 u8 reserved_at_0[0x80];
8592 } port_access_reg_cap_mask;
8593
8594 u8 reserved_at_c0[0x80];
8595
8596 union {
8597 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8598 u8 reserved_at_0[0x80];
8599 } feature_cap_mask;
8600
8601 u8 reserved_at_1c0[0xc0];
8602};
8603
8604struct mlx5_ifc_mcam_enhanced_features_bits {
4039049b
AL		 8605 u8 reserved_at_0[0x6e];
8606 u8 pci_status_and_power[0x1];
8607 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 8608 u8 mark_tx_action_cnp[0x1];
8609 u8 mark_tx_action_cqe[0x1];
8610 u8 dynamic_tx_overflow[0x1];
8611 u8 reserved_at_77[0x4];
5405fa26 8612 u8 pcie_outbound_stalled[0x1];
efae7f78 8613 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8614 u8 mtpps_enh_out_per_adj[0x1];
8615 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8616 u8 pcie_performance_group[0x1];
8617};
8618
0ab87743
OG		 8619struct mlx5_ifc_mcam_access_reg_bits {
8620 u8 reserved_at_0[0x1c];
8621 u8 mcda[0x1];
8622 u8 mcc[0x1];
8623 u8 mcqi[0x1];
a82e0b5b 8624 u8 mcqs[0x1];
0ab87743 8625
5e022dd3
EBE		 8626 u8 regs_95_to_87[0x9];
8627 u8 mpegc[0x1];
8628 u8 regs_85_to_68[0x12];
eff8ea8f
FD		 8629 u8 tracer_registers[0x4];
8630
0ab87743
OG		 8631 u8 regs_63_to_32[0x20];
8632 u8 regs_31_to_0[0x20];
8633};
8634
cfdcbcea
GP		 8635struct mlx5_ifc_mcam_reg_bits {
8636 u8 reserved_at_0[0x8];
8637 u8 feature_group[0x8];
8638 u8 reserved_at_10[0x8];
8639 u8 access_reg_group[0x8];
8640
8641 u8 reserved_at_20[0x20];
8642
8643 union {
0ab87743 8644 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8645 u8 reserved_at_0[0x80];
8646 } mng_access_reg_cap_mask;
8647
8648 u8 reserved_at_c0[0x80];
8649
8650 union {
8651 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8652 u8 reserved_at_0[0x80];
8653 } mng_feature_cap_mask;
8654
8655 u8 reserved_at_1c0[0x80];
8656};
8657
c02762eb
HN		 8658struct mlx5_ifc_qcam_access_reg_cap_mask {
8659 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8660 u8 qpdpm[0x1];
8661 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8662 u8 qdpm[0x1];
8663 u8 qpts[0x1];
8664 u8 qcap[0x1];
8665 u8 qcam_access_reg_cap_mask_0[0x1];
8666};
8667
8668struct mlx5_ifc_qcam_qos_feature_cap_mask {
8669 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8670 u8 qpts_trust_both[0x1];
8671};
8672
8673struct mlx5_ifc_qcam_reg_bits {
8674 u8 reserved_at_0[0x8];
8675 u8 feature_group[0x8];
8676 u8 reserved_at_10[0x8];
8677 u8 access_reg_group[0x8];
8678 u8 reserved_at_20[0x20];
8679
8680 union {
8681 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8682 u8 reserved_at_0[0x80];
8683 } qos_access_reg_cap_mask;
8684
8685 u8 reserved_at_c0[0x80];
8686
8687 union {
8688 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8689 u8 reserved_at_0[0x80];
8690 } qos_feature_cap_mask;
8691
8692 u8 reserved_at_1c0[0x80];
8693};
8694
0b9055a1
MS		 8695struct mlx5_ifc_core_dump_reg_bits {
8696 u8 reserved_at_0[0x18];
8697 u8 core_dump_type[0x8];
8698
8699 u8 reserved_at_20[0x30];
8700 u8 vhca_id[0x10];
8701
8702 u8 reserved_at_60[0x8];
8703 u8 qpn[0x18];
8704 u8 reserved_at_80[0x180];
8705};
8706
e281682b 8707struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8708 u8 reserved_at_0[0x8];
e281682b 8709 u8 local_port[0x8];
b4ff3a36 8710 u8 reserved_at_10[0x10];
e281682b
SM		 8711
8712 u8 port_capability_mask[4][0x20];
8713};
8714
8715struct mlx5_ifc_paos_reg_bits {
8716 u8 swid[0x8];
8717 u8 local_port[0x8];
b4ff3a36 8718 u8 reserved_at_10[0x4];
e281682b 8719 u8 admin_status[0x4];
b4ff3a36 8720 u8 reserved_at_18[0x4];
e281682b
SM		 8721 u8 oper_status[0x4];
8722
8723 u8 ase[0x1];
8724 u8 ee[0x1];
b4ff3a36 8725 u8 reserved_at_22[0x1c];
e281682b
SM		 8726 u8 e[0x2];
8727
b4ff3a36 8728 u8 reserved_at_40[0x40];
e281682b
SM		 8729};
8730
8731struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8732 u8 reserved_at_0[0x8];
e281682b 8733 u8 opamp_group[0x8];
b4ff3a36 8734 u8 reserved_at_10[0xc];
e281682b
SM		 8735 u8 opamp_group_type[0x4];
8736
8737 u8 start_index[0x10];
b4ff3a36 8738 u8 reserved_at_30[0x4];
e281682b
SM		 8739 u8 num_of_indices[0xc];
8740
8741 u8 index_data[18][0x10];
8742};
8743
7d5e1423
SM		 8744struct mlx5_ifc_pcmr_reg_bits {
8745 u8 reserved_at_0[0x8];
8746 u8 local_port[0x8];
0dcaafc0
EB		 8747 u8 reserved_at_10[0x10];
8748 u8 entropy_force_cap[0x1];
8749 u8 entropy_calc_cap[0x1];
8750 u8 entropy_gre_calc_cap[0x1];
8751 u8 reserved_at_23[0x1b];
7d5e1423 8752 u8 fcs_cap[0x1];
0dcaafc0
EB		 8753 u8 reserved_at_3f[0x1];
8754 u8 entropy_force[0x1];
8755 u8 entropy_calc[0x1];
8756 u8 entropy_gre_calc[0x1];
8757 u8 reserved_at_43[0x1b];
7d5e1423
SM		 8758 u8 fcs_chk[0x1];
8759 u8 reserved_at_5f[0x1];
8760};
8761
e281682b 8762struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8763 u8 reserved_at_0[0x6];
e281682b 8764 u8 rx_lane[0x2];
b4ff3a36 8765 u8 reserved_at_8[0x6];
e281682b 8766 u8 tx_lane[0x2];
b4ff3a36 8767 u8 reserved_at_10[0x8];
e281682b
SM		 8768 u8 module[0x8];
8769};
8770
8771struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8772 u8 reserved_at_0[0x6];
e281682b
SM		 8773 u8 lossy[0x1];
8774 u8 epsb[0x1];
b4ff3a36 8775 u8 reserved_at_8[0xc];
e281682b
SM		 8776 u8 size[0xc];
8777
8778 u8 xoff_threshold[0x10];
8779 u8 xon_threshold[0x10];
8780};
8781
8782struct mlx5_ifc_set_node_in_bits {
8783 u8 node_description[64][0x8];
8784};
8785
8786struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8787 u8 reserved_at_0[0x18];
e281682b
SM		 8788 u8 power_settings_level[0x8];
8789
b4ff3a36 8790 u8 reserved_at_20[0x60];
e281682b
SM		 8791};
8792
8793struct mlx5_ifc_register_host_endianness_bits {
8794 u8 he[0x1];
b4ff3a36 8795 u8 reserved_at_1[0x1f];
e281682b 8796
b4ff3a36 8797 u8 reserved_at_20[0x60];
e281682b
SM		 8798};
8799
8800struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8801 u8 reserved_at_0[0x20];
e281682b
SM		 8802
8803 u8 mkey[0x20];
8804
8805 u8 addressh_63_32[0x20];
8806
8807 u8 addressl_31_0[0x20];
8808};
8809
8810struct mlx5_ifc_ud_adrs_vector_bits {
8811 u8 dc_key[0x40];
8812
8813 u8 ext[0x1];
b4ff3a36 8814 u8 reserved_at_41[0x7];
e281682b
SM		 8815 u8 destination_qp_dct[0x18];
8816
8817 u8 static_rate[0x4];
8818 u8 sl_eth_prio[0x4];
8819 u8 fl[0x1];
8820 u8 mlid[0x7];
8821 u8 rlid_udp_sport[0x10];
8822
b4ff3a36 8823 u8 reserved_at_80[0x20];
e281682b
SM		 8824
8825 u8 rmac_47_16[0x20];
8826
8827 u8 rmac_15_0[0x10];
8828 u8 tclass[0x8];
8829 u8 hop_limit[0x8];
8830
b4ff3a36 8831 u8 reserved_at_e0[0x1];
e281682b 8832 u8 grh[0x1];
b4ff3a36 8833 u8 reserved_at_e2[0x2];
e281682b
SM		 8834 u8 src_addr_index[0x8];
8835 u8 flow_label[0x14];
8836
8837 u8 rgid_rip[16][0x8];
8838};
8839
8840struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8841 u8 reserved_at_0[0x10];
e281682b
SM		 8842 u8 function_id[0x10];
8843
8844 u8 num_pages[0x20];
8845
b4ff3a36 8846 u8 reserved_at_40[0xa0];
e281682b
SM		 8847};
8848
8849struct mlx5_ifc_eqe_bits {
b4ff3a36 8850 u8 reserved_at_0[0x8];
e281682b 8851 u8 event_type[0x8];
b4ff3a36 8852 u8 reserved_at_10[0x8];
e281682b
SM		 8853 u8 event_sub_type[0x8];
8854
b4ff3a36 8855 u8 reserved_at_20[0xe0];
e281682b
SM		 8856
8857 union mlx5_ifc_event_auto_bits event_data;
8858
b4ff3a36 8859 u8 reserved_at_1e0[0x10];
e281682b 8860 u8 signature[0x8];
b4ff3a36 8861 u8 reserved_at_1f8[0x7];
e281682b
SM		 8862 u8 owner[0x1];
8863};
8864
8865enum {
8866 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8867};
8868
8869struct mlx5_ifc_cmd_queue_entry_bits {
8870 u8 type[0x8];
b4ff3a36 8871 u8 reserved_at_8[0x18];
e281682b
SM		 8872
8873 u8 input_length[0x20];
8874
8875 u8 input_mailbox_pointer_63_32[0x20];
8876
8877 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8878 u8 reserved_at_77[0x9];
e281682b
SM		 8879
8880 u8 command_input_inline_data[16][0x8];
8881
8882 u8 command_output_inline_data[16][0x8];
8883
8884 u8 output_mailbox_pointer_63_32[0x20];
8885
8886 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8887 u8 reserved_at_1b7[0x9];
e281682b
SM		 8888
8889 u8 output_length[0x20];
8890
8891 u8 token[0x8];
8892 u8 signature[0x8];
b4ff3a36 8893 u8 reserved_at_1f0[0x8];
e281682b
SM		 8894 u8 status[0x7];
8895 u8 ownership[0x1];
8896};
8897
8898struct mlx5_ifc_cmd_out_bits {
8899 u8 status[0x8];
b4ff3a36 8900 u8 reserved_at_8[0x18];
e281682b
SM		 8901
8902 u8 syndrome[0x20];
8903
8904 u8 command_output[0x20];
8905};
8906
8907struct mlx5_ifc_cmd_in_bits {
8908 u8 opcode[0x10];
b4ff3a36 8909 u8 reserved_at_10[0x10];
e281682b 8910
b4ff3a36 8911 u8 reserved_at_20[0x10];
e281682b
SM		 8912 u8 op_mod[0x10];
8913
8914 u8 command[0][0x20];
8915};
8916
8917struct mlx5_ifc_cmd_if_box_bits {
8918 u8 mailbox_data[512][0x8];
8919
b4ff3a36 8920 u8 reserved_at_1000[0x180];
e281682b
SM		 8921
8922 u8 next_pointer_63_32[0x20];
8923
8924 u8 next_pointer_31_10[0x16];
b4ff3a36 8925 u8 reserved_at_11b6[0xa];
e281682b
SM		 8926
8927 u8 block_number[0x20];
8928
b4ff3a36 8929 u8 reserved_at_11e0[0x8];
e281682b
SM		 8930 u8 token[0x8];
8931 u8 ctrl_signature[0x8];
8932 u8 signature[0x8];
8933};
8934
8935struct mlx5_ifc_mtt_bits {
8936 u8 ptag_63_32[0x20];
8937
8938 u8 ptag_31_8[0x18];
b4ff3a36 8939 u8 reserved_at_38[0x6];
e281682b
SM		 8940 u8 wr_en[0x1];
8941 u8 rd_en[0x1];
8942};
8943
928cfe87
TT		 8944struct mlx5_ifc_query_wol_rol_out_bits {
8945 u8 status[0x8];
8946 u8 reserved_at_8[0x18];
8947
8948 u8 syndrome[0x20];
8949
8950 u8 reserved_at_40[0x10];
8951 u8 rol_mode[0x8];
8952 u8 wol_mode[0x8];
8953
8954 u8 reserved_at_60[0x20];
8955};
8956
8957struct mlx5_ifc_query_wol_rol_in_bits {
8958 u8 opcode[0x10];
8959 u8 reserved_at_10[0x10];
8960
8961 u8 reserved_at_20[0x10];
8962 u8 op_mod[0x10];
8963
8964 u8 reserved_at_40[0x40];
8965};
8966
8967struct mlx5_ifc_set_wol_rol_out_bits {
8968 u8 status[0x8];
8969 u8 reserved_at_8[0x18];
8970
8971 u8 syndrome[0x20];
8972
8973 u8 reserved_at_40[0x40];
8974};
8975
8976struct mlx5_ifc_set_wol_rol_in_bits {
8977 u8 opcode[0x10];
8978 u8 reserved_at_10[0x10];
8979
8980 u8 reserved_at_20[0x10];
8981 u8 op_mod[0x10];
8982
8983 u8 rol_mode_valid[0x1];
8984 u8 wol_mode_valid[0x1];
8985 u8 reserved_at_42[0xe];
8986 u8 rol_mode[0x8];
8987 u8 wol_mode[0x8];
8988
8989 u8 reserved_at_60[0x20];
8990};
8991
e281682b
SM		 8992enum {
8993 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8994 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8995 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8996};
8997
8998enum {
8999 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9000 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9001 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9002};
9003
9004enum {
9005 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9006 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9007 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9008 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9009 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9010 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9011 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9012 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9013 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9014 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9015 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9016};
9017
9018struct mlx5_ifc_initial_seg_bits {
9019 u8 fw_rev_minor[0x10];
9020 u8 fw_rev_major[0x10];
9021
9022 u8 cmd_interface_rev[0x10];
9023 u8 fw_rev_subminor[0x10];
9024
b4ff3a36 9025 u8 reserved_at_40[0x40];
e281682b
SM		 9026
9027 u8 cmdq_phy_addr_63_32[0x20];
9028
9029 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 9030 u8 reserved_at_b4[0x2];
e281682b
SM		 9031 u8 nic_interface[0x2];
9032 u8 log_cmdq_size[0x4];
9033 u8 log_cmdq_stride[0x4];
9034
9035 u8 command_doorbell_vector[0x20];
9036
b4ff3a36 9037 u8 reserved_at_e0[0xf00];
e281682b
SM		 9038
9039 u8 initializing[0x1];
b4ff3a36 9040 u8 reserved_at_fe1[0x4];
e281682b 9041 u8 nic_interface_supported[0x3];
591905ba
BW		 9042 u8 embedded_cpu[0x1];
9043 u8 reserved_at_fe9[0x17];
e281682b
SM		 9044
9045 struct mlx5_ifc_health_buffer_bits health_buffer;
9046
9047 u8 no_dram_nic_offset[0x20];
9048
b4ff3a36 9049 u8 reserved_at_1220[0x6e40];
e281682b 9050
b4ff3a36 9051 u8 reserved_at_8060[0x1f];
e281682b
SM		 9052 u8 clear_int[0x1];
9053
9054 u8 health_syndrome[0x8];
9055 u8 health_counter[0x18];
9056
b4ff3a36 9057 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 9058};
9059
f9a1ef72
EE		 9060struct mlx5_ifc_mtpps_reg_bits {
9061 u8 reserved_at_0[0xc];
9062 u8 cap_number_of_pps_pins[0x4];
9063 u8 reserved_at_10[0x4];
9064 u8 cap_max_num_of_pps_in_pins[0x4];
9065 u8 reserved_at_18[0x4];
9066 u8 cap_max_num_of_pps_out_pins[0x4];
9067
9068 u8 reserved_at_20[0x24];
9069 u8 cap_pin_3_mode[0x4];
9070 u8 reserved_at_48[0x4];
9071 u8 cap_pin_2_mode[0x4];
9072 u8 reserved_at_50[0x4];
9073 u8 cap_pin_1_mode[0x4];
9074 u8 reserved_at_58[0x4];
9075 u8 cap_pin_0_mode[0x4];
9076
9077 u8 reserved_at_60[0x4];
9078 u8 cap_pin_7_mode[0x4];
9079 u8 reserved_at_68[0x4];
9080 u8 cap_pin_6_mode[0x4];
9081 u8 reserved_at_70[0x4];
9082 u8 cap_pin_5_mode[0x4];
9083 u8 reserved_at_78[0x4];
9084 u8 cap_pin_4_mode[0x4];
9085
fa367688
EE		 9086 u8 field_select[0x20];
9087 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 9088
9089 u8 enable[0x1];
9090 u8 reserved_at_101[0xb];
9091 u8 pattern[0x4];
9092 u8 reserved_at_110[0x4];
9093 u8 pin_mode[0x4];
9094 u8 pin[0x8];
9095
9096 u8 reserved_at_120[0x20];
9097
9098 u8 time_stamp[0x40];
9099
9100 u8 out_pulse_duration[0x10];
9101 u8 out_periodic_adjustment[0x10];
fa367688 9102 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 9103
fa367688 9104 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 9105};
9106
9107struct mlx5_ifc_mtppse_reg_bits {
9108 u8 reserved_at_0[0x18];
9109 u8 pin[0x8];
9110 u8 event_arm[0x1];
9111 u8 reserved_at_21[0x1b];
9112 u8 event_generation_mode[0x4];
9113 u8 reserved_at_40[0x40];
9114};
9115
a82e0b5b
SA		 9116struct mlx5_ifc_mcqs_reg_bits {
9117 u8 last_index_flag[0x1];
9118 u8 reserved_at_1[0x7];
9119 u8 fw_device[0x8];
9120 u8 component_index[0x10];
9121
9122 u8 reserved_at_20[0x10];
9123 u8 identifier[0x10];
9124
9125 u8 reserved_at_40[0x17];
9126 u8 component_status[0x5];
9127 u8 component_update_state[0x4];
9128
9129 u8 last_update_state_changer_type[0x4];
9130 u8 last_update_state_changer_host_id[0x4];
9131 u8 reserved_at_68[0x18];
9132};
9133
47176289
OG		 9134struct mlx5_ifc_mcqi_cap_bits {
9135 u8 supported_info_bitmask[0x20];
9136
9137 u8 component_size[0x20];
9138
9139 u8 max_component_size[0x20];
9140
9141 u8 log_mcda_word_size[0x4];
9142 u8 reserved_at_64[0xc];
9143 u8 mcda_max_write_size[0x10];
9144
9145 u8 rd_en[0x1];
9146 u8 reserved_at_81[0x1];
9147 u8 match_chip_id[0x1];
9148 u8 match_psid[0x1];
9149 u8 check_user_timestamp[0x1];
9150 u8 match_base_guid_mac[0x1];
9151 u8 reserved_at_86[0x1a];
9152};
9153
a82e0b5b
SA		 9154struct mlx5_ifc_mcqi_version_bits {
9155 u8 reserved_at_0[0x2];
9156 u8 build_time_valid[0x1];
9157 u8 user_defined_time_valid[0x1];
9158 u8 reserved_at_4[0x14];
9159 u8 version_string_length[0x8];
9160
9161 u8 version[0x20];
9162
9163 u8 build_time[0x40];
9164
9165 u8 user_defined_time[0x40];
9166
9167 u8 build_tool_version[0x20];
9168
9169 u8 reserved_at_e0[0x20];
9170
9171 u8 version_string[92][0x8];
9172};
9173
9174struct mlx5_ifc_mcqi_activation_method_bits {
9175 u8 pending_server_ac_power_cycle[0x1];
9176 u8 pending_server_dc_power_cycle[0x1];
9177 u8 pending_server_reboot[0x1];
9178 u8 pending_fw_reset[0x1];
9179 u8 auto_activate[0x1];
9180 u8 all_hosts_sync[0x1];
9181 u8 device_hw_reset[0x1];
9182 u8 reserved_at_7[0x19];
9183};
9184
9185union mlx5_ifc_mcqi_reg_data_bits {
9186 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9187 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9188 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9189};
9190
47176289
OG		 9191struct mlx5_ifc_mcqi_reg_bits {
9192 u8 read_pending_component[0x1];
9193 u8 reserved_at_1[0xf];
9194 u8 component_index[0x10];
9195
9196 u8 reserved_at_20[0x20];
9197
9198 u8 reserved_at_40[0x1b];
9199 u8 info_type[0x5];
9200
9201 u8 info_size[0x20];
9202
9203 u8 offset[0x20];
9204
9205 u8 reserved_at_a0[0x10];
9206 u8 data_size[0x10];
9207
a82e0b5b 9208 union mlx5_ifc_mcqi_reg_data_bits data[0];
47176289
OG		 9209};
9210
9211struct mlx5_ifc_mcc_reg_bits {
9212 u8 reserved_at_0[0x4];
9213 u8 time_elapsed_since_last_cmd[0xc];
9214 u8 reserved_at_10[0x8];
9215 u8 instruction[0x8];
9216
9217 u8 reserved_at_20[0x10];
9218 u8 component_index[0x10];
9219
9220 u8 reserved_at_40[0x8];
9221 u8 update_handle[0x18];
9222
9223 u8 handle_owner_type[0x4];
9224 u8 handle_owner_host_id[0x4];
9225 u8 reserved_at_68[0x1];
9226 u8 control_progress[0x7];
9227 u8 error_code[0x8];
9228 u8 reserved_at_78[0x4];
9229 u8 control_state[0x4];
9230
9231 u8 component_size[0x20];
9232
9233 u8 reserved_at_a0[0x60];
9234};
9235
9236struct mlx5_ifc_mcda_reg_bits {
9237 u8 reserved_at_0[0x8];
9238 u8 update_handle[0x18];
9239
9240 u8 offset[0x20];
9241
9242 u8 reserved_at_40[0x10];
9243 u8 size[0x10];
9244
9245 u8 reserved_at_60[0x20];
9246
9247 u8 data[0][0x20];
9248};
9249
e281682b
SM		 9250union mlx5_ifc_ports_control_registers_document_bits {
9251 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9252 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9253 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9254 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9255 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9256 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9257 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9258 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9259 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9260 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9261 struct mlx5_ifc_paos_reg_bits paos_reg;
9262 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9263 struct mlx5_ifc_peir_reg_bits peir_reg;
9264 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9265 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 9266 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 9267 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9268 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9269 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9270 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9271 struct mlx5_ifc_plib_reg_bits plib_reg;
9272 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9273 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9274 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9275 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9276 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9277 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9278 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9279 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9280 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9281 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 9282 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 9283 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 9284 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9285 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9286 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9287 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9288 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9289 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9290 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 9291 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 9292 struct mlx5_ifc_pude_reg_bits pude_reg;
9293 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9294 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9295 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 9296 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9297 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 9298 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 9299 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9300 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 9301 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9302 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9303 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 9304 u8 reserved_at_0[0x60e0];
e281682b
SM		 9305};
9306
9307union mlx5_ifc_debug_enhancements_document_bits {
9308 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 9309 u8 reserved_at_0[0x200];
e281682b
SM		 9310};
9311
9312union mlx5_ifc_uplink_pci_interface_document_bits {
9313 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 9314 u8 reserved_at_0[0x20060];
b775516b
EC		 9315};
9316
2cc43b49
MG		 9317struct mlx5_ifc_set_flow_table_root_out_bits {
9318 u8 status[0x8];
b4ff3a36 9319 u8 reserved_at_8[0x18];
2cc43b49
MG		 9320
9321 u8 syndrome[0x20];
9322
b4ff3a36 9323 u8 reserved_at_40[0x40];
2cc43b49
MG		 9324};
9325
9326struct mlx5_ifc_set_flow_table_root_in_bits {
9327 u8 opcode[0x10];
b4ff3a36 9328 u8 reserved_at_10[0x10];
2cc43b49 9329
b4ff3a36 9330 u8 reserved_at_20[0x10];
2cc43b49
MG		 9331 u8 op_mod[0x10];
9332
7d5e1423
SM		 9333 u8 other_vport[0x1];
9334 u8 reserved_at_41[0xf];
9335 u8 vport_number[0x10];
9336
9337 u8 reserved_at_60[0x20];
2cc43b49
MG		 9338
9339 u8 table_type[0x8];
b4ff3a36 9340 u8 reserved_at_88[0x18];
2cc43b49 9341
b4ff3a36 9342 u8 reserved_at_a0[0x8];
2cc43b49
MG		 9343 u8 table_id[0x18];
9344
500a3d0d
ES		 9345 u8 reserved_at_c0[0x8];
9346 u8 underlay_qpn[0x18];
9347 u8 reserved_at_e0[0x120];
2cc43b49
MG		 9348};
9349
34a40e68 9350enum {
84df61eb
AH		 9351 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9352 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 9353};
9354
9355struct mlx5_ifc_modify_flow_table_out_bits {
9356 u8 status[0x8];
b4ff3a36 9357 u8 reserved_at_8[0x18];
34a40e68
MG		 9358
9359 u8 syndrome[0x20];
9360
b4ff3a36 9361 u8 reserved_at_40[0x40];
34a40e68
MG		 9362};
9363
9364struct mlx5_ifc_modify_flow_table_in_bits {
9365 u8 opcode[0x10];
b4ff3a36 9366 u8 reserved_at_10[0x10];
34a40e68 9367
b4ff3a36 9368 u8 reserved_at_20[0x10];
34a40e68
MG		 9369 u8 op_mod[0x10];
9370
7d5e1423
SM		 9371 u8 other_vport[0x1];
9372 u8 reserved_at_41[0xf];
9373 u8 vport_number[0x10];
34a40e68 9374
b4ff3a36 9375 u8 reserved_at_60[0x10];
34a40e68
MG		 9376 u8 modify_field_select[0x10];
9377
9378 u8 table_type[0x8];
b4ff3a36 9379 u8 reserved_at_88[0x18];
34a40e68 9380
b4ff3a36 9381 u8 reserved_at_a0[0x8];
34a40e68
MG		 9382 u8 table_id[0x18];
9383
0c90e9c6 9384 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 9385};
9386
4f3961ee
SM		 9387struct mlx5_ifc_ets_tcn_config_reg_bits {
9388 u8 g[0x1];
9389 u8 b[0x1];
9390 u8 r[0x1];
9391 u8 reserved_at_3[0x9];
9392 u8 group[0x4];
9393 u8 reserved_at_10[0x9];
9394 u8 bw_allocation[0x7];
9395
9396 u8 reserved_at_20[0xc];
9397 u8 max_bw_units[0x4];
9398 u8 reserved_at_30[0x8];
9399 u8 max_bw_value[0x8];
9400};
9401
9402struct mlx5_ifc_ets_global_config_reg_bits {
9403 u8 reserved_at_0[0x2];
9404 u8 r[0x1];
9405 u8 reserved_at_3[0x1d];
9406
9407 u8 reserved_at_20[0xc];
9408 u8 max_bw_units[0x4];
9409 u8 reserved_at_30[0x8];
9410 u8 max_bw_value[0x8];
9411};
9412
9413struct mlx5_ifc_qetc_reg_bits {
9414 u8 reserved_at_0[0x8];
9415 u8 port_number[0x8];
9416 u8 reserved_at_10[0x30];
9417
9418 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9419 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9420};
9421
415a64aa
HN		 9422struct mlx5_ifc_qpdpm_dscp_reg_bits {
9423 u8 e[0x1];
9424 u8 reserved_at_01[0x0b];
9425 u8 prio[0x04];
9426};
9427
9428struct mlx5_ifc_qpdpm_reg_bits {
9429 u8 reserved_at_0[0x8];
9430 u8 local_port[0x8];
9431 u8 reserved_at_10[0x10];
9432 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9433};
9434
9435struct mlx5_ifc_qpts_reg_bits {
9436 u8 reserved_at_0[0x8];
9437 u8 local_port[0x8];
9438 u8 reserved_at_10[0x2d];
9439 u8 trust_state[0x3];
9440};
9441
50b4a3c2
HN		 9442struct mlx5_ifc_pptb_reg_bits {
9443 u8 reserved_at_0[0x2];
9444 u8 mm[0x2];
9445 u8 reserved_at_4[0x4];
9446 u8 local_port[0x8];
9447 u8 reserved_at_10[0x6];
9448 u8 cm[0x1];
9449 u8 um[0x1];
9450 u8 pm[0x8];
9451
9452 u8 prio_x_buff[0x20];
9453
9454 u8 pm_msb[0x8];
9455 u8 reserved_at_48[0x10];
9456 u8 ctrl_buff[0x4];
9457 u8 untagged_buff[0x4];
9458};
9459
9460struct mlx5_ifc_pbmc_reg_bits {
9461 u8 reserved_at_0[0x8];
9462 u8 local_port[0x8];
9463 u8 reserved_at_10[0x10];
9464
9465 u8 xoff_timer_value[0x10];
9466 u8 xoff_refresh[0x10];
9467
9468 u8 reserved_at_40[0x9];
9469 u8 fullness_threshold[0x7];
9470 u8 port_buffer_size[0x10];
9471
9472 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9473
9474 u8 reserved_at_2e0[0x40];
9475};
9476
4f3961ee
SM		 9477struct mlx5_ifc_qtct_reg_bits {
9478 u8 reserved_at_0[0x8];
9479 u8 port_number[0x8];
9480 u8 reserved_at_10[0xd];
9481 u8 prio[0x3];
9482
9483 u8 reserved_at_20[0x1d];
9484 u8 tclass[0x3];
9485};
9486
7d5e1423
SM		 9487struct mlx5_ifc_mcia_reg_bits {
9488 u8 l[0x1];
9489 u8 reserved_at_1[0x7];
9490 u8 module[0x8];
9491 u8 reserved_at_10[0x8];
9492 u8 status[0x8];
9493
9494 u8 i2c_device_address[0x8];
9495 u8 page_number[0x8];
9496 u8 device_address[0x10];
9497
9498 u8 reserved_at_40[0x10];
9499 u8 size[0x10];
9500
9501 u8 reserved_at_60[0x20];
9502
9503 u8 dword_0[0x20];
9504 u8 dword_1[0x20];
9505 u8 dword_2[0x20];
9506 u8 dword_3[0x20];
9507 u8 dword_4[0x20];
9508 u8 dword_5[0x20];
9509 u8 dword_6[0x20];
9510 u8 dword_7[0x20];
9511 u8 dword_8[0x20];
9512 u8 dword_9[0x20];
9513 u8 dword_10[0x20];
9514 u8 dword_11[0x20];
9515};
9516
7486216b
SM		 9517struct mlx5_ifc_dcbx_param_bits {
9518 u8 dcbx_cee_cap[0x1];
9519 u8 dcbx_ieee_cap[0x1];
9520 u8 dcbx_standby_cap[0x1];
c74d90c1 9521 u8 reserved_at_3[0x5];
7486216b
SM		 9522 u8 port_number[0x8];
9523 u8 reserved_at_10[0xa];
9524 u8 max_application_table_size[6];
9525 u8 reserved_at_20[0x15];
9526 u8 version_oper[0x3];
9527 u8 reserved_at_38[5];
9528 u8 version_admin[0x3];
9529 u8 willing_admin[0x1];
9530 u8 reserved_at_41[0x3];
9531 u8 pfc_cap_oper[0x4];
9532 u8 reserved_at_48[0x4];
9533 u8 pfc_cap_admin[0x4];
9534 u8 reserved_at_50[0x4];
9535 u8 num_of_tc_oper[0x4];
9536 u8 reserved_at_58[0x4];
9537 u8 num_of_tc_admin[0x4];
9538 u8 remote_willing[0x1];
9539 u8 reserved_at_61[3];
9540 u8 remote_pfc_cap[4];
9541 u8 reserved_at_68[0x14];
9542 u8 remote_num_of_tc[0x4];
9543 u8 reserved_at_80[0x18];
9544 u8 error[0x8];
9545 u8 reserved_at_a0[0x160];
9546};
84df61eb
AH		 9547
9548struct mlx5_ifc_lagc_bits {
9549 u8 reserved_at_0[0x1d];
9550 u8 lag_state[0x3];
9551
9552 u8 reserved_at_20[0x14];
9553 u8 tx_remap_affinity_2[0x4];
9554 u8 reserved_at_38[0x4];
9555 u8 tx_remap_affinity_1[0x4];
9556};
9557
9558struct mlx5_ifc_create_lag_out_bits {
9559 u8 status[0x8];
9560 u8 reserved_at_8[0x18];
9561
9562 u8 syndrome[0x20];
9563
9564 u8 reserved_at_40[0x40];
9565};
9566
9567struct mlx5_ifc_create_lag_in_bits {
9568 u8 opcode[0x10];
9569 u8 reserved_at_10[0x10];
9570
9571 u8 reserved_at_20[0x10];
9572 u8 op_mod[0x10];
9573
9574 struct mlx5_ifc_lagc_bits ctx;
9575};
9576
9577struct mlx5_ifc_modify_lag_out_bits {
9578 u8 status[0x8];
9579 u8 reserved_at_8[0x18];
9580
9581 u8 syndrome[0x20];
9582
9583 u8 reserved_at_40[0x40];
9584};
9585
9586struct mlx5_ifc_modify_lag_in_bits {
9587 u8 opcode[0x10];
9588 u8 reserved_at_10[0x10];
9589
9590 u8 reserved_at_20[0x10];
9591 u8 op_mod[0x10];
9592
9593 u8 reserved_at_40[0x20];
9594 u8 field_select[0x20];
9595
9596 struct mlx5_ifc_lagc_bits ctx;
9597};
9598
9599struct mlx5_ifc_query_lag_out_bits {
9600 u8 status[0x8];
9601 u8 reserved_at_8[0x18];
9602
9603 u8 syndrome[0x20];
9604
84df61eb
AH		 9605 struct mlx5_ifc_lagc_bits ctx;
9606};
9607
9608struct mlx5_ifc_query_lag_in_bits {
9609 u8 opcode[0x10];
9610 u8 reserved_at_10[0x10];
9611
9612 u8 reserved_at_20[0x10];
9613 u8 op_mod[0x10];
9614
9615 u8 reserved_at_40[0x40];
9616};
9617
9618struct mlx5_ifc_destroy_lag_out_bits {
9619 u8 status[0x8];
9620 u8 reserved_at_8[0x18];
9621
9622 u8 syndrome[0x20];
9623
9624 u8 reserved_at_40[0x40];
9625};
9626
9627struct mlx5_ifc_destroy_lag_in_bits {
9628 u8 opcode[0x10];
9629 u8 reserved_at_10[0x10];
9630
9631 u8 reserved_at_20[0x10];
9632 u8 op_mod[0x10];
9633
9634 u8 reserved_at_40[0x40];
9635};
9636
9637struct mlx5_ifc_create_vport_lag_out_bits {
9638 u8 status[0x8];
9639 u8 reserved_at_8[0x18];
9640
9641 u8 syndrome[0x20];
9642
9643 u8 reserved_at_40[0x40];
9644};
9645
9646struct mlx5_ifc_create_vport_lag_in_bits {
9647 u8 opcode[0x10];
9648 u8 reserved_at_10[0x10];
9649
9650 u8 reserved_at_20[0x10];
9651 u8 op_mod[0x10];
9652
9653 u8 reserved_at_40[0x40];
9654};
9655
9656struct mlx5_ifc_destroy_vport_lag_out_bits {
9657 u8 status[0x8];
9658 u8 reserved_at_8[0x18];
9659
9660 u8 syndrome[0x20];
9661
9662 u8 reserved_at_40[0x40];
9663};
9664
9665struct mlx5_ifc_destroy_vport_lag_in_bits {
9666 u8 opcode[0x10];
9667 u8 reserved_at_10[0x10];
9668
9669 u8 reserved_at_20[0x10];
9670 u8 op_mod[0x10];
9671
9672 u8 reserved_at_40[0x40];
9673};
9674
24da0016
AL		 9675struct mlx5_ifc_alloc_memic_in_bits {
9676 u8 opcode[0x10];
9677 u8 reserved_at_10[0x10];
9678
9679 u8 reserved_at_20[0x10];
9680 u8 op_mod[0x10];
9681
9682 u8 reserved_at_30[0x20];
9683
9684 u8 reserved_at_40[0x18];
9685 u8 log_memic_addr_alignment[0x8];
9686
9687 u8 range_start_addr[0x40];
9688
9689 u8 range_size[0x20];
9690
9691 u8 memic_size[0x20];
9692};
9693
9694struct mlx5_ifc_alloc_memic_out_bits {
9695 u8 status[0x8];
9696 u8 reserved_at_8[0x18];
9697
9698 u8 syndrome[0x20];
9699
9700 u8 memic_start_addr[0x40];
9701};
9702
9703struct mlx5_ifc_dealloc_memic_in_bits {
9704 u8 opcode[0x10];
9705 u8 reserved_at_10[0x10];
9706
9707 u8 reserved_at_20[0x10];
9708 u8 op_mod[0x10];
9709
9710 u8 reserved_at_40[0x40];
9711
9712 u8 memic_start_addr[0x40];
9713
9714 u8 memic_size[0x20];
9715
9716 u8 reserved_at_e0[0x20];
9717};
9718
9719struct mlx5_ifc_dealloc_memic_out_bits {
9720 u8 status[0x8];
9721 u8 reserved_at_8[0x18];
9722
9723 u8 syndrome[0x20];
9724
9725 u8 reserved_at_40[0x40];
9726};
9727
38b7ca92
YH		 9728struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9729 u8 opcode[0x10];
9730 u8 uid[0x10];
9731
1dd7382b 9732 u8 vhca_tunnel_id[0x10];
38b7ca92
YH		 9733 u8 obj_type[0x10];
9734
9735 u8 obj_id[0x20];
9736
9737 u8 reserved_at_60[0x20];
9738};
9739
9740struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9741 u8 status[0x8];
9742 u8 reserved_at_8[0x18];
9743
9744 u8 syndrome[0x20];
9745
9746 u8 obj_id[0x20];
9747
9748 u8 reserved_at_60[0x20];
9749};
9750
9751struct mlx5_ifc_umem_bits {
6e3722ba 9752 u8 reserved_at_0[0x80];
38b7ca92 9753
6e3722ba 9754 u8 reserved_at_80[0x1b];
38b7ca92
YH		 9755 u8 log_page_size[0x5];
9756
9757 u8 page_offset[0x20];
9758
9759 u8 num_of_mtt[0x40];
9760
9761 struct mlx5_ifc_mtt_bits mtt[0];
9762};
9763
9764struct mlx5_ifc_uctx_bits {
9d43faac
YH		 9765 u8 cap[0x20];
9766
6e3722ba 9767 u8 reserved_at_20[0x160];
38b7ca92
YH		 9768};
9769
9fba2b9b
AL		 9770struct mlx5_ifc_sw_icm_bits {
9771 u8 modify_field_select[0x40];
9772
9773 u8 reserved_at_40[0x18];
9774 u8 log_sw_icm_size[0x8];
9775
9776 u8 reserved_at_60[0x20];
9777
9778 u8 sw_icm_start_addr[0x40];
9779
9780 u8 reserved_at_c0[0x140];
91a40a48 9781};
b169e64a
YK		 9782
9783struct mlx5_ifc_geneve_tlv_option_bits {
9784 u8 modify_field_select[0x40];
9785
9786 u8 reserved_at_40[0x18];
9787 u8 geneve_option_fte_index[0x8];
9788
9789 u8 option_class[0x10];
9790 u8 option_type[0x8];
9791 u8 reserved_at_78[0x3];
9792 u8 option_data_length[0x5];
9793
9794 u8 reserved_at_80[0x180];
9fba2b9b
AL		 9795};
9796
38b7ca92 9797struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 9798 u8 opcode[0x10];
9799 u8 uid[0x10];
9800
9801 u8 reserved_at_20[0x10];
9802 u8 op_mod[0x10];
9803
9804 u8 reserved_at_40[0x40];
9805
9806 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 9807};
9808
9809struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 9810 u8 opcode[0x10];
9811 u8 reserved_at_10[0x10];
9812
9813 u8 reserved_at_20[0x10];
9814 u8 op_mod[0x10];
9815
9816 u8 reserved_at_40[0x40];
9817
9818 struct mlx5_ifc_uctx_bits uctx;
9819};
9820
9821struct mlx5_ifc_destroy_uctx_in_bits {
9822 u8 opcode[0x10];
9823 u8 reserved_at_10[0x10];
9824
9825 u8 reserved_at_20[0x10];
9826 u8 op_mod[0x10];
9827
9828 u8 reserved_at_40[0x10];
9829 u8 uid[0x10];
9830
9831 u8 reserved_at_60[0x20];
38b7ca92
YH		 9832};
9833
9fba2b9b
AL		 9834struct mlx5_ifc_create_sw_icm_in_bits {
9835 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9836 struct mlx5_ifc_sw_icm_bits sw_icm;
9837};
9838
b169e64a
YK		 9839struct mlx5_ifc_create_geneve_tlv_option_in_bits {
9840 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9841 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
9842};
9843
eff8ea8f
FD		 9844struct mlx5_ifc_mtrc_string_db_param_bits {
9845 u8 string_db_base_address[0x20];
9846
9847 u8 reserved_at_20[0x8];
9848 u8 string_db_size[0x18];
9849};
9850
9851struct mlx5_ifc_mtrc_cap_bits {
9852 u8 trace_owner[0x1];
9853 u8 trace_to_memory[0x1];
9854 u8 reserved_at_2[0x4];
9855 u8 trc_ver[0x2];
9856 u8 reserved_at_8[0x14];
9857 u8 num_string_db[0x4];
9858
9859 u8 first_string_trace[0x8];
9860 u8 num_string_trace[0x8];
9861 u8 reserved_at_30[0x28];
9862
9863 u8 log_max_trace_buffer_size[0x8];
9864
9865 u8 reserved_at_60[0x20];
9866
9867 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9868
9869 u8 reserved_at_280[0x180];
9870};
9871
9872struct mlx5_ifc_mtrc_conf_bits {
9873 u8 reserved_at_0[0x1c];
9874 u8 trace_mode[0x4];
9875 u8 reserved_at_20[0x18];
9876 u8 log_trace_buffer_size[0x8];
9877 u8 trace_mkey[0x20];
9878 u8 reserved_at_60[0x3a0];
9879};
9880
9881struct mlx5_ifc_mtrc_stdb_bits {
9882 u8 string_db_index[0x4];
9883 u8 reserved_at_4[0x4];
9884 u8 read_size[0x18];
9885 u8 start_offset[0x20];
9886 u8 string_db_data[0];
9887};
9888
9889struct mlx5_ifc_mtrc_ctrl_bits {
9890 u8 trace_status[0x2];
9891 u8 reserved_at_2[0x2];
9892 u8 arm_event[0x1];
9893 u8 reserved_at_5[0xb];
9894 u8 modify_field_select[0x10];
9895 u8 reserved_at_20[0x2b];
9896 u8 current_timestamp52_32[0x15];
9897 u8 current_timestamp31_0[0x20];
9898 u8 reserved_at_80[0x180];
9899};
9900
c3a4e9f1
BW		 9901struct mlx5_ifc_host_params_context_bits {
9902 u8 host_number[0x8];
5ccf2770
BW		 9903 u8 reserved_at_8[0x7];
9904 u8 host_pf_disabled[0x1];
c3a4e9f1
BW		 9905 u8 host_num_of_vfs[0x10];
9906
86eec50b 9907 u8 host_total_vfs[0x10];
c3a4e9f1
BW		 9908 u8 host_pci_bus[0x10];
9909
9910 u8 reserved_at_40[0x10];
9911 u8 host_pci_device[0x10];
9912
9913 u8 reserved_at_60[0x10];
9914 u8 host_pci_function[0x10];
9915
9916 u8 reserved_at_80[0x180];
9917};
9918
cd56f929 9919struct mlx5_ifc_query_esw_functions_in_bits {
c3a4e9f1
BW		 9920 u8 opcode[0x10];
9921 u8 reserved_at_10[0x10];
9922
9923 u8 reserved_at_20[0x10];
9924 u8 op_mod[0x10];
9925
9926 u8 reserved_at_40[0x40];
9927};
9928
cd56f929 9929struct mlx5_ifc_query_esw_functions_out_bits {
c3a4e9f1
BW		 9930 u8 status[0x8];
9931 u8 reserved_at_8[0x18];
9932
9933 u8 syndrome[0x20];
9934
9935 u8 reserved_at_40[0x40];
9936
9937 struct mlx5_ifc_host_params_context_bits host_params_context;
9938
9939 u8 reserved_at_280[0x180];
1759d322
PP		 9940 u8 host_sf_enable[0][0x40];
9941};
9942
9943struct mlx5_ifc_sf_partition_bits {
9944 u8 reserved_at_0[0x10];
9945 u8 log_num_sf[0x8];
9946 u8 log_sf_bar_size[0x8];
9947};
9948
9949struct mlx5_ifc_query_sf_partitions_out_bits {
9950 u8 status[0x8];
9951 u8 reserved_at_8[0x18];
9952
9953 u8 syndrome[0x20];
9954
9955 u8 reserved_at_40[0x18];
9956 u8 num_sf_partitions[0x8];
9957
9958 u8 reserved_at_60[0x20];
9959
9960 struct mlx5_ifc_sf_partition_bits sf_partition[0];
9961};
9962
9963struct mlx5_ifc_query_sf_partitions_in_bits {
9964 u8 opcode[0x10];
9965 u8 reserved_at_10[0x10];
9966
9967 u8 reserved_at_20[0x10];
9968 u8 op_mod[0x10];
9969
9970 u8 reserved_at_40[0x40];
9971};
9972
9973struct mlx5_ifc_dealloc_sf_out_bits {
9974 u8 status[0x8];
9975 u8 reserved_at_8[0x18];
9976
9977 u8 syndrome[0x20];
9978
9979 u8 reserved_at_40[0x40];
9980};
9981
9982struct mlx5_ifc_dealloc_sf_in_bits {
9983 u8 opcode[0x10];
9984 u8 reserved_at_10[0x10];
9985
9986 u8 reserved_at_20[0x10];
9987 u8 op_mod[0x10];
9988
9989 u8 reserved_at_40[0x10];
9990 u8 function_id[0x10];
9991
9992 u8 reserved_at_60[0x20];
9993};
9994
9995struct mlx5_ifc_alloc_sf_out_bits {
9996 u8 status[0x8];
9997 u8 reserved_at_8[0x18];
9998
9999 u8 syndrome[0x20];
10000
10001 u8 reserved_at_40[0x40];
10002};
10003
10004struct mlx5_ifc_alloc_sf_in_bits {
10005 u8 opcode[0x10];
10006 u8 reserved_at_10[0x10];
10007
10008 u8 reserved_at_20[0x10];
10009 u8 op_mod[0x10];
10010
10011 u8 reserved_at_40[0x10];
10012 u8 function_id[0x10];
10013
10014 u8 reserved_at_60[0x20];
c3a4e9f1
BW		 10015};
10016
e4075c44
YH		 10017struct mlx5_ifc_affiliated_event_header_bits {
10018 u8 reserved_at_0[0x10];
10019 u8 obj_type[0x10];
10020
10021 u8 obj_id[0x20];
10022};
10023
a12ff35e
EBE		 10024enum {
10025 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10026};
10027
10028enum {
10029 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10030};
10031
10032struct mlx5_ifc_encryption_key_obj_bits {
10033 u8 modify_field_select[0x40];
10034
10035 u8 reserved_at_40[0x14];
10036 u8 key_size[0x4];
10037 u8 reserved_at_58[0x4];
10038 u8 key_type[0x4];
10039
10040 u8 reserved_at_60[0x8];
10041 u8 pd[0x18];
10042
10043 u8 reserved_at_80[0x180];
10044 u8 key[8][0x20];
10045
10046 u8 reserved_at_300[0x500];
10047};
10048
10049struct mlx5_ifc_create_encryption_key_in_bits {
10050 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10051 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10052};
10053
10054enum {
10055 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10056 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10057};
10058
10059enum {
10060 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10061};
10062
10063struct mlx5_ifc_tls_static_params_bits {
10064 u8 const_2[0x2];
10065 u8 tls_version[0x4];
10066 u8 const_1[0x2];
10067 u8 reserved_at_8[0x14];
10068 u8 encryption_standard[0x4];
10069
10070 u8 reserved_at_20[0x20];
10071
10072 u8 initial_record_number[0x40];
10073
10074 u8 resync_tcp_sn[0x20];
10075
10076 u8 gcm_iv[0x20];
10077
10078 u8 implicit_iv[0x40];
10079
10080 u8 reserved_at_100[0x8];
10081 u8 dek_index[0x18];
10082
10083 u8 reserved_at_120[0xe0];
10084};
10085
10086struct mlx5_ifc_tls_progress_params_bits {
10087 u8 valid[0x1];
10088 u8 reserved_at_1[0x7];
10089 u8 pd[0x18];
10090
10091 u8 next_record_tcp_sn[0x20];
10092
10093 u8 hw_resync_tcp_sn[0x20];
10094
10095 u8 record_tracker_state[0x2];
10096 u8 auth_state[0x2];
10097 u8 reserved_at_64[0x4];
10098 u8 hw_offset_record_number[0x18];
10099};
10100
d29b796a 10101#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)