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net/mlx5: Exposing a new mini-CQE format
[linux-2.6-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 95 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
96 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 97 MLX5_CMD_OP_CREATE_EQ = 0x301,
98 MLX5_CMD_OP_DESTROY_EQ = 0x302,
99 MLX5_CMD_OP_QUERY_EQ = 0x303,
100 MLX5_CMD_OP_GEN_EQE = 0x304,
101 MLX5_CMD_OP_CREATE_CQ = 0x400,
102 MLX5_CMD_OP_DESTROY_CQ = 0x401,
103 MLX5_CMD_OP_QUERY_CQ = 0x402,
104 MLX5_CMD_OP_MODIFY_CQ = 0x403,
105 MLX5_CMD_OP_CREATE_QP = 0x500,
106 MLX5_CMD_OP_DESTROY_QP = 0x501,
107 MLX5_CMD_OP_RST2INIT_QP = 0x502,
108 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
109 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
110 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
112 MLX5_CMD_OP_2ERR_QP = 0x507,
113 MLX5_CMD_OP_2RST_QP = 0x50a,
114 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
117 MLX5_CMD_OP_CREATE_PSV = 0x600,
118 MLX5_CMD_OP_DESTROY_PSV = 0x601,
119 MLX5_CMD_OP_CREATE_SRQ = 0x700,
120 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
121 MLX5_CMD_OP_QUERY_SRQ = 0x702,
122 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 127 MLX5_CMD_OP_CREATE_DCT = 0x710,
128 MLX5_CMD_OP_DESTROY_DCT = 0x711,
129 MLX5_CMD_OP_DRAIN_DCT = 0x712,
130 MLX5_CMD_OP_QUERY_DCT = 0x713,
131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 132 MLX5_CMD_OP_CREATE_XRQ = 0x717,
133 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
134 MLX5_CMD_OP_QUERY_XRQ = 0x719,
135 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 136 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
137 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 143 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 148 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 149 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
150 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
151 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
152 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
37e92a9d 153 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 154 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 155 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
156 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
157 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
158 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
159 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
160 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 161 MLX5_CMD_OP_ALLOC_PD = 0x800,
162 MLX5_CMD_OP_DEALLOC_PD = 0x801,
163 MLX5_CMD_OP_ALLOC_UAR = 0x802,
164 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
165 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
166 MLX5_CMD_OP_ACCESS_REG = 0x805,
167 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 168 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 169 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
170 MLX5_CMD_OP_MAD_IFC = 0x50d,
171 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
172 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
173 MLX5_CMD_OP_NOP = 0x80d,
174 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
175 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 176 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
177 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
178 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
179 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
180 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
181 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
182 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
183 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
184 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
185 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
186 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
187 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 188 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
189 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 190 MLX5_CMD_OP_CREATE_LAG = 0x840,
191 MLX5_CMD_OP_MODIFY_LAG = 0x841,
192 MLX5_CMD_OP_QUERY_LAG = 0x842,
193 MLX5_CMD_OP_DESTROY_LAG = 0x843,
194 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
195 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 196 MLX5_CMD_OP_CREATE_TIR = 0x900,
197 MLX5_CMD_OP_MODIFY_TIR = 0x901,
198 MLX5_CMD_OP_DESTROY_TIR = 0x902,
199 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 200 MLX5_CMD_OP_CREATE_SQ = 0x904,
201 MLX5_CMD_OP_MODIFY_SQ = 0x905,
202 MLX5_CMD_OP_DESTROY_SQ = 0x906,
203 MLX5_CMD_OP_QUERY_SQ = 0x907,
204 MLX5_CMD_OP_CREATE_RQ = 0x908,
205 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 206 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 207 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
208 MLX5_CMD_OP_QUERY_RQ = 0x90b,
209 MLX5_CMD_OP_CREATE_RMP = 0x90c,
210 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
211 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
212 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 213 MLX5_CMD_OP_CREATE_TIS = 0x912,
214 MLX5_CMD_OP_MODIFY_TIS = 0x913,
215 MLX5_CMD_OP_DESTROY_TIS = 0x914,
216 MLX5_CMD_OP_QUERY_TIS = 0x915,
217 MLX5_CMD_OP_CREATE_RQT = 0x916,
218 MLX5_CMD_OP_MODIFY_RQT = 0x917,
219 MLX5_CMD_OP_DESTROY_RQT = 0x918,
220 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 221 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 222 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
223 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
224 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
225 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
226 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
227 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
228 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
229 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 230 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 231 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
232 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
233 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 234 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 235 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
236 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 237 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
238 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 239 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
240 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
241 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
242 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
243 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 244 MLX5_CMD_OP_MAX
e281682b
SM		 245};
246
247struct mlx5_ifc_flow_table_fields_supported_bits {
248 u8 outer_dmac[0x1];
249 u8 outer_smac[0x1];
250 u8 outer_ether_type[0x1];
19cc7524 251 u8 outer_ip_version[0x1];
e281682b
SM		 252 u8 outer_first_prio[0x1];
253 u8 outer_first_cfi[0x1];
254 u8 outer_first_vid[0x1];
a8ade55f 255 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 256 u8 outer_second_prio[0x1];
257 u8 outer_second_cfi[0x1];
258 u8 outer_second_vid[0x1];
b4ff3a36 259 u8 reserved_at_b[0x1];
e281682b
SM		 260 u8 outer_sip[0x1];
261 u8 outer_dip[0x1];
262 u8 outer_frag[0x1];
263 u8 outer_ip_protocol[0x1];
264 u8 outer_ip_ecn[0x1];
265 u8 outer_ip_dscp[0x1];
266 u8 outer_udp_sport[0x1];
267 u8 outer_udp_dport[0x1];
268 u8 outer_tcp_sport[0x1];
269 u8 outer_tcp_dport[0x1];
270 u8 outer_tcp_flags[0x1];
271 u8 outer_gre_protocol[0x1];
272 u8 outer_gre_key[0x1];
273 u8 outer_vxlan_vni[0x1];
b4ff3a36 274 u8 reserved_at_1a[0x5];
e281682b
SM		 275 u8 source_eswitch_port[0x1];
276
277 u8 inner_dmac[0x1];
278 u8 inner_smac[0x1];
279 u8 inner_ether_type[0x1];
19cc7524 280 u8 inner_ip_version[0x1];
e281682b
SM		 281 u8 inner_first_prio[0x1];
282 u8 inner_first_cfi[0x1];
283 u8 inner_first_vid[0x1];
b4ff3a36 284 u8 reserved_at_27[0x1];
e281682b
SM		 285 u8 inner_second_prio[0x1];
286 u8 inner_second_cfi[0x1];
287 u8 inner_second_vid[0x1];
b4ff3a36 288 u8 reserved_at_2b[0x1];
e281682b
SM		 289 u8 inner_sip[0x1];
290 u8 inner_dip[0x1];
291 u8 inner_frag[0x1];
292 u8 inner_ip_protocol[0x1];
293 u8 inner_ip_ecn[0x1];
294 u8 inner_ip_dscp[0x1];
295 u8 inner_udp_sport[0x1];
296 u8 inner_udp_dport[0x1];
297 u8 inner_tcp_sport[0x1];
298 u8 inner_tcp_dport[0x1];
299 u8 inner_tcp_flags[0x1];
b4ff3a36 300 u8 reserved_at_37[0x9];
3346c487
BP		 301 u8 reserved_at_40[0x17];
302 u8 outer_esp_spi[0x1];
303 u8 reserved_at_58[0x2];
a550ddfc 304 u8 bth_dst_qp[0x1];
e281682b 305
a550ddfc 306 u8 reserved_at_5b[0x25];
e281682b
SM		 307};
308
309struct mlx5_ifc_flow_table_prop_layout_bits {
310 u8 ft_support[0x1];
9dc0b289
AV		 311 u8 reserved_at_1[0x1];
312 u8 flow_counter[0x1];
26a81453 313 u8 flow_modify_en[0x1];
2cc43b49 314 u8 modify_root[0x1];
34a40e68
MG		 315 u8 identified_miss_table_mode[0x1];
316 u8 flow_table_modify[0x1];
7adbde20
HHZ		 317 u8 encap[0x1];
318 u8 decap[0x1];
0c06897a
OG		 319 u8 reserved_at_9[0x1];
320 u8 pop_vlan[0x1];
321 u8 push_vlan[0x1];
322 u8 reserved_at_c[0x14];
e281682b 323
b4ff3a36 324 u8 reserved_at_20[0x2];
e281682b 325 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 326 u8 log_max_modify_header_context[0x8];
327 u8 max_modify_header_actions[0x8];
e281682b
SM		 328 u8 max_ft_level[0x8];
329
b4ff3a36 330 u8 reserved_at_40[0x20];
e281682b 331
b4ff3a36 332 u8 reserved_at_60[0x18];
e281682b
SM		 333 u8 log_max_ft_num[0x8];
334
b4ff3a36 335 u8 reserved_at_80[0x18];
e281682b
SM		 336 u8 log_max_destination[0x8];
337
16f1c5bb
RS		 338 u8 log_max_flow_counter[0x8];
339 u8 reserved_at_a8[0x10];
e281682b
SM		 340 u8 log_max_flow[0x8];
341
b4ff3a36 342 u8 reserved_at_c0[0x40];
e281682b
SM		 343
344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
345
346 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
347};
348
349struct mlx5_ifc_odp_per_transport_service_cap_bits {
350 u8 send[0x1];
351 u8 receive[0x1];
352 u8 write[0x1];
353 u8 read[0x1];
17d2f88f 354 u8 atomic[0x1];
e281682b 355 u8 srq_receive[0x1];
b4ff3a36 356 u8 reserved_at_6[0x1a];
e281682b
SM		 357};
358
b4d1f032 359struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 360 u8 reserved_at_0[0x60];
b4d1f032
MG		 361
362 u8 ipv4[0x20];
363};
364
365struct mlx5_ifc_ipv6_layout_bits {
366 u8 ipv6[16][0x8];
367};
368
369union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
370 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
371 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 372 u8 reserved_at_0[0x80];
b4d1f032
MG		 373};
374
e281682b
SM		 375struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
376 u8 smac_47_16[0x20];
377
378 u8 smac_15_0[0x10];
379 u8 ethertype[0x10];
380
381 u8 dmac_47_16[0x20];
382
383 u8 dmac_15_0[0x10];
384 u8 first_prio[0x3];
385 u8 first_cfi[0x1];
386 u8 first_vid[0xc];
387
388 u8 ip_protocol[0x8];
389 u8 ip_dscp[0x6];
390 u8 ip_ecn[0x2];
10543365
MHY		 391 u8 cvlan_tag[0x1];
392 u8 svlan_tag[0x1];
e281682b 393 u8 frag[0x1];
19cc7524 394 u8 ip_version[0x4];
e281682b
SM		 395 u8 tcp_flags[0x9];
396
397 u8 tcp_sport[0x10];
398 u8 tcp_dport[0x10];
399
a8ade55f
OG		 400 u8 reserved_at_c0[0x18];
401 u8 ttl_hoplimit[0x8];
e281682b
SM		 402
403 u8 udp_sport[0x10];
404 u8 udp_dport[0x10];
405
b4d1f032 406 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 407
b4d1f032 408 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 409};
410
411struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 412 u8 reserved_at_0[0x8];
413 u8 source_sqn[0x18];
e281682b 414
3e99df87 415 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 416 u8 source_port[0x10];
417
418 u8 outer_second_prio[0x3];
419 u8 outer_second_cfi[0x1];
420 u8 outer_second_vid[0xc];
421 u8 inner_second_prio[0x3];
422 u8 inner_second_cfi[0x1];
423 u8 inner_second_vid[0xc];
424
10543365
MHY		 425 u8 outer_second_cvlan_tag[0x1];
426 u8 inner_second_cvlan_tag[0x1];
427 u8 outer_second_svlan_tag[0x1];
428 u8 inner_second_svlan_tag[0x1];
429 u8 reserved_at_64[0xc];
e281682b
SM		 430 u8 gre_protocol[0x10];
431
432 u8 gre_key_h[0x18];
433 u8 gre_key_l[0x8];
434
435 u8 vxlan_vni[0x18];
b4ff3a36 436 u8 reserved_at_b8[0x8];
e281682b 437
b4ff3a36 438 u8 reserved_at_c0[0x20];
e281682b 439
b4ff3a36 440 u8 reserved_at_e0[0xc];
e281682b
SM		 441 u8 outer_ipv6_flow_label[0x14];
442
b4ff3a36 443 u8 reserved_at_100[0xc];
e281682b
SM		 444 u8 inner_ipv6_flow_label[0x14];
445
a550ddfc
YH		 446 u8 reserved_at_120[0x28];
447 u8 bth_dst_qp[0x18];
3346c487
BP		 448 u8 reserved_at_160[0x20];
449 u8 outer_esp_spi[0x20];
450 u8 reserved_at_1a0[0x60];
e281682b
SM		 451};
452
453struct mlx5_ifc_cmd_pas_bits {
454 u8 pa_h[0x20];
455
456 u8 pa_l[0x14];
b4ff3a36 457 u8 reserved_at_34[0xc];
e281682b
SM		 458};
459
460struct mlx5_ifc_uint64_bits {
461 u8 hi[0x20];
462
463 u8 lo[0x20];
464};
465
466enum {
467 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
468 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
469 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
470 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
471 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
472 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
473 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
474 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
475 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
476 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
477};
478
479struct mlx5_ifc_ads_bits {
480 u8 fl[0x1];
481 u8 free_ar[0x1];
b4ff3a36 482 u8 reserved_at_2[0xe];
e281682b
SM		 483 u8 pkey_index[0x10];
484
b4ff3a36 485 u8 reserved_at_20[0x8];
e281682b
SM		 486 u8 grh[0x1];
487 u8 mlid[0x7];
488 u8 rlid[0x10];
489
490 u8 ack_timeout[0x5];
b4ff3a36 491 u8 reserved_at_45[0x3];
e281682b 492 u8 src_addr_index[0x8];
b4ff3a36 493 u8 reserved_at_50[0x4];
e281682b
SM		 494 u8 stat_rate[0x4];
495 u8 hop_limit[0x8];
496
b4ff3a36 497 u8 reserved_at_60[0x4];
e281682b
SM		 498 u8 tclass[0x8];
499 u8 flow_label[0x14];
500
501 u8 rgid_rip[16][0x8];
502
b4ff3a36 503 u8 reserved_at_100[0x4];
e281682b
SM		 504 u8 f_dscp[0x1];
505 u8 f_ecn[0x1];
b4ff3a36 506 u8 reserved_at_106[0x1];
e281682b
SM		 507 u8 f_eth_prio[0x1];
508 u8 ecn[0x2];
509 u8 dscp[0x6];
510 u8 udp_sport[0x10];
511
512 u8 dei_cfi[0x1];
513 u8 eth_prio[0x3];
514 u8 sl[0x4];
32f69e4b 515 u8 vhca_port_num[0x8];
e281682b
SM		 516 u8 rmac_47_32[0x10];
517
518 u8 rmac_31_0[0x20];
519};
520
521struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 522 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 523 u8 nic_rx_multi_path_tirs_fts[0x1];
524 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
525 u8 reserved_at_3[0x1fd];
e281682b
SM		 526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
528
b4ff3a36 529 u8 reserved_at_400[0x200];
e281682b
SM		 530
531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
532
533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
534
b4ff3a36 535 u8 reserved_at_a00[0x200];
e281682b
SM		 536
537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
538
b4ff3a36 539 u8 reserved_at_e00[0x7200];
e281682b
SM		 540};
541
495716b1 542struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 543 u8 reserved_at_0[0x200];
495716b1
SM		 544
545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
546
547 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
548
549 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
550
b4ff3a36 551 u8 reserved_at_800[0x7800];
495716b1
SM		 552};
553
d6666753
SM		 554struct mlx5_ifc_e_switch_cap_bits {
555 u8 vport_svlan_strip[0x1];
556 u8 vport_cvlan_strip[0x1];
557 u8 vport_svlan_insert[0x1];
558 u8 vport_cvlan_insert_if_not_exist[0x1];
559 u8 vport_cvlan_insert_overwrite[0x1];
a6d04569
RD		 560 u8 reserved_at_5[0x18];
561 u8 merged_eswitch[0x1];
23898c76
NO		 562 u8 nic_vport_node_guid_modify[0x1];
563 u8 nic_vport_port_guid_modify[0x1];
d6666753 564
7adbde20
HHZ		 565 u8 vxlan_encap_decap[0x1];
566 u8 nvgre_encap_decap[0x1];
567 u8 reserved_at_22[0x9];
568 u8 log_max_encap_headers[0x5];
569 u8 reserved_2b[0x6];
570 u8 max_encap_header_size[0xa];
571
572 u8 reserved_40[0x7c0];
573
d6666753
SM		 574};
575
7486216b
SM		 576struct mlx5_ifc_qos_cap_bits {
577 u8 packet_pacing[0x1];
813f8540 578 u8 esw_scheduling[0x1];
c9497c98
MHY		 579 u8 esw_bw_share[0x1];
580 u8 esw_rate_limit[0x1];
05d3ac97
BW		 581 u8 reserved_at_4[0x1];
582 u8 packet_pacing_burst_bound[0x1];
583 u8 packet_pacing_typical_size[0x1];
584 u8 reserved_at_7[0x19];
813f8540
MHY		 585
586 u8 reserved_at_20[0x20];
587
7486216b 588 u8 packet_pacing_max_rate[0x20];
813f8540 589
7486216b 590 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 591
592 u8 reserved_at_80[0x10];
7486216b 593 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 594
595 u8 esw_element_type[0x10];
596 u8 esw_tsar_type[0x10];
597
598 u8 reserved_at_c0[0x10];
599 u8 max_qos_para_vport[0x10];
600
601 u8 max_tsar_bw_share[0x20];
602
603 u8 reserved_at_100[0x700];
7486216b
SM		 604};
605
2fcb12df
IK		 606struct mlx5_ifc_debug_cap_bits {
607 u8 reserved_at_0[0x20];
608
609 u8 reserved_at_20[0x2];
610 u8 stall_detect[0x1];
611 u8 reserved_at_23[0x1d];
612
613 u8 reserved_at_40[0x7c0];
614};
615
e281682b
SM		 616struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
617 u8 csum_cap[0x1];
618 u8 vlan_cap[0x1];
619 u8 lro_cap[0x1];
620 u8 lro_psh_flag[0x1];
621 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 622 u8 reserved_at_5[0x2];
623 u8 wqe_vlan_insert[0x1];
66189961 624 u8 self_lb_en_modifiable[0x1];
b4ff3a36 625 u8 reserved_at_9[0x2];
e281682b 626 u8 max_lso_cap[0x5];
c226dc22 627 u8 multi_pkt_send_wqe[0x2];
cff92d7c 628 u8 wqe_inline_mode[0x2];
e281682b 629 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 630 u8 reg_umr_sq[0x1];
631 u8 scatter_fcs[0x1];
050da902 632 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 633 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 634 u8 reserved_at_1c[0x2];
27299841 635 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 636 u8 tunnel_stateless_vxlan[0x1];
637
547eede0
IT		 638 u8 swp[0x1];
639 u8 swp_csum[0x1];
640 u8 swp_lso[0x1];
4d350f1f
MG		 641 u8 reserved_at_23[0x1b];
642 u8 max_geneve_opt_len[0x1];
643 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 644
b4ff3a36 645 u8 reserved_at_40[0x10];
e281682b
SM		 646 u8 lro_min_mss_size[0x10];
647
b4ff3a36 648 u8 reserved_at_60[0x120];
e281682b
SM		 649
650 u8 lro_timer_supported_periods[4][0x20];
651
b4ff3a36 652 u8 reserved_at_200[0x600];
e281682b
SM		 653};
654
655struct mlx5_ifc_roce_cap_bits {
656 u8 roce_apm[0x1];
b4ff3a36 657 u8 reserved_at_1[0x1f];
e281682b 658
b4ff3a36 659 u8 reserved_at_20[0x60];
e281682b 660
b4ff3a36 661 u8 reserved_at_80[0xc];
e281682b 662 u8 l3_type[0x4];
b4ff3a36 663 u8 reserved_at_90[0x8];
e281682b
SM		 664 u8 roce_version[0x8];
665
b4ff3a36 666 u8 reserved_at_a0[0x10];
e281682b
SM		 667 u8 r_roce_dest_udp_port[0x10];
668
669 u8 r_roce_max_src_udp_port[0x10];
670 u8 r_roce_min_src_udp_port[0x10];
671
b4ff3a36 672 u8 reserved_at_e0[0x10];
e281682b
SM		 673 u8 roce_address_table_size[0x10];
674
b4ff3a36 675 u8 reserved_at_100[0x700];
e281682b
SM		 676};
677
e72bd817
AL		 678struct mlx5_ifc_device_mem_cap_bits {
679 u8 memic[0x1];
680 u8 reserved_at_1[0x1f];
681
682 u8 reserved_at_20[0xb];
683 u8 log_min_memic_alloc_size[0x5];
684 u8 reserved_at_30[0x8];
685 u8 log_max_memic_addr_alignment[0x8];
686
687 u8 memic_bar_start_addr[0x40];
688
689 u8 memic_bar_size[0x20];
690
691 u8 max_memic_size[0x20];
692
693 u8 reserved_at_c0[0x740];
694};
695
e281682b
SM		 696enum {
697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
702 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
703 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
704 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
705 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
706};
707
708enum {
709 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
710 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
711 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
712 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
713 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
714 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
715 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
716 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
717 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
718};
719
720struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 721 u8 reserved_at_0[0x40];
e281682b 722
bd10838a 723 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 724 u8 reserved_at_42[0x4];
bd10838a 725 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 726
b4ff3a36 727 u8 reserved_at_47[0x19];
e281682b 728
b4ff3a36 729 u8 reserved_at_60[0x20];
e281682b 730
b4ff3a36 731 u8 reserved_at_80[0x10];
f91e6d89 732 u8 atomic_operations[0x10];
e281682b 733
b4ff3a36 734 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 735 u8 atomic_size_qp[0x10];
736
b4ff3a36 737 u8 reserved_at_c0[0x10];
e281682b
SM		 738 u8 atomic_size_dc[0x10];
739
b4ff3a36 740 u8 reserved_at_e0[0x720];
e281682b
SM		 741};
742
743struct mlx5_ifc_odp_cap_bits {
b4ff3a36 744 u8 reserved_at_0[0x40];
e281682b
SM		 745
746 u8 sig[0x1];
b4ff3a36 747 u8 reserved_at_41[0x1f];
e281682b 748
b4ff3a36 749 u8 reserved_at_60[0x20];
e281682b
SM		 750
751 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
752
753 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
754
755 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
756
b4ff3a36 757 u8 reserved_at_e0[0x720];
e281682b
SM		 758};
759
3f0393a5
SG		 760struct mlx5_ifc_calc_op {
761 u8 reserved_at_0[0x10];
762 u8 reserved_at_10[0x9];
763 u8 op_swap_endianness[0x1];
764 u8 op_min[0x1];
765 u8 op_xor[0x1];
766 u8 op_or[0x1];
767 u8 op_and[0x1];
768 u8 op_max[0x1];
769 u8 op_add[0x1];
770};
771
772struct mlx5_ifc_vector_calc_cap_bits {
773 u8 calc_matrix[0x1];
774 u8 reserved_at_1[0x1f];
775 u8 reserved_at_20[0x8];
776 u8 max_vec_count[0x8];
777 u8 reserved_at_30[0xd];
778 u8 max_chunk_size[0x3];
779 struct mlx5_ifc_calc_op calc0;
780 struct mlx5_ifc_calc_op calc1;
781 struct mlx5_ifc_calc_op calc2;
782 struct mlx5_ifc_calc_op calc3;
783
784 u8 reserved_at_e0[0x720];
785};
786
e281682b
SM		 787enum {
788 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
789 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 790 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 791 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 792};
793
794enum {
795 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
796 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
797};
798
799enum {
800 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
801 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
802 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
803 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
804 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
805};
806
807enum {
808 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
809 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
810 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
811 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
812 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
813 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
814};
815
816enum {
817 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
818 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
819};
820
821enum {
822 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
823 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
824 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
825};
826
827enum {
828 MLX5_CAP_PORT_TYPE_IB = 0x0,
829 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 830};
831
1410a90a
MG		 832enum {
833 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
834 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
835 MLX5_CAP_UMR_FENCE_NONE = 0x2,
836};
837
b775516b 838struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 839 u8 reserved_at_0[0x30];
840 u8 vhca_id[0x10];
841
842 u8 reserved_at_40[0x40];
b775516b
EC		 843
844 u8 log_max_srq_sz[0x8];
845 u8 log_max_qp_sz[0x8];
b4ff3a36 846 u8 reserved_at_90[0xb];
b775516b
EC		 847 u8 log_max_qp[0x5];
848
b4ff3a36 849 u8 reserved_at_a0[0xb];
e281682b 850 u8 log_max_srq[0x5];
b4ff3a36 851 u8 reserved_at_b0[0x10];
b775516b 852
b4ff3a36 853 u8 reserved_at_c0[0x8];
b775516b 854 u8 log_max_cq_sz[0x8];
b4ff3a36 855 u8 reserved_at_d0[0xb];
b775516b
EC		 856 u8 log_max_cq[0x5];
857
858 u8 log_max_eq_sz[0x8];
b4ff3a36 859 u8 reserved_at_e8[0x2];
b775516b 860 u8 log_max_mkey[0x6];
b4ff3a36 861 u8 reserved_at_f0[0xc];
b775516b
EC		 862 u8 log_max_eq[0x4];
863
864 u8 max_indirection[0x8];
bcda1aca 865 u8 fixed_buffer_size[0x1];
b775516b 866 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 867 u8 force_teardown[0x1];
868 u8 reserved_at_111[0x1];
b775516b 869 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 870 u8 umr_extended_translation_offset[0x1];
871 u8 null_mkey[0x1];
b775516b
EC		 872 u8 log_max_klm_list_size[0x6];
873
b4ff3a36 874 u8 reserved_at_120[0xa];
b775516b 875 u8 log_max_ra_req_dc[0x6];
b4ff3a36 876 u8 reserved_at_130[0xa];
b775516b
EC		 877 u8 log_max_ra_res_dc[0x6];
878
b4ff3a36 879 u8 reserved_at_140[0xa];
b775516b 880 u8 log_max_ra_req_qp[0x6];
b4ff3a36 881 u8 reserved_at_150[0xa];
b775516b
EC		 882 u8 log_max_ra_res_qp[0x6];
883
f32f5bd2 884 u8 end_pad[0x1];
b775516b
EC		 885 u8 cc_query_allowed[0x1];
886 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 887 u8 start_pad[0x1];
888 u8 cache_line_128byte[0x1];
c02762eb
HN		 889 u8 reserved_at_165[0xa];
890 u8 qcam_reg[0x1];
e281682b 891 u8 gid_table_size[0x10];
b775516b 892
e281682b
SM		 893 u8 out_of_seq_cnt[0x1];
894 u8 vport_counters[0x1];
7486216b 895 u8 retransmission_q_counters[0x1];
2fcb12df 896 u8 debug[0x1];
83b502a1 897 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 898 u8 rq_delay_drop[0x1];
b775516b
EC		 899 u8 max_qp_cnt[0xa];
900 u8 pkey_table_size[0x10];
901
e281682b
SM		 902 u8 vport_group_manager[0x1];
903 u8 vhca_group_manager[0x1];
904 u8 ib_virt[0x1];
905 u8 eth_virt[0x1];
61c5b5c9 906 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 907 u8 ets[0x1];
908 u8 nic_flow_table[0x1];
54f0a411 909 u8 eswitch_flow_table[0x1];
e72bd817 910 u8 device_memory[0x1];
cfdcbcea
GP		 911 u8 mcam_reg[0x1];
912 u8 pcam_reg[0x1];
b775516b 913 u8 local_ca_ack_delay[0x5];
4ce3bf2f 914 u8 port_module_event[0x1];
58dcb60a 915 u8 enhanced_error_q_counters[0x1];
7d5e1423 916 u8 ports_check[0x1];
7b13558f 917 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 918 u8 disable_link_up[0x1];
919 u8 beacon_led[0x1];
e281682b 920 u8 port_type[0x2];
b775516b
EC		 921 u8 num_ports[0x8];
922
f9a1ef72
EE		 923 u8 reserved_at_1c0[0x1];
924 u8 pps[0x1];
925 u8 pps_modify[0x1];
b775516b 926 u8 log_max_msg[0x5];
e1c9c62b 927 u8 reserved_at_1c8[0x4];
4f3961ee 928 u8 max_tc[0x4];
7486216b
SM		 929 u8 reserved_at_1d0[0x1];
930 u8 dcbx[0x1];
246ac981
MG		 931 u8 general_notification_event[0x1];
932 u8 reserved_at_1d3[0x2];
e29341fb 933 u8 fpga[0x1];
928cfe87
TT		 934 u8 rol_s[0x1];
935 u8 rol_g[0x1];
e1c9c62b 936 u8 reserved_at_1d8[0x1];
928cfe87
TT		 937 u8 wol_s[0x1];
938 u8 wol_g[0x1];
939 u8 wol_a[0x1];
940 u8 wol_b[0x1];
941 u8 wol_m[0x1];
942 u8 wol_u[0x1];
943 u8 wol_p[0x1];
b775516b
EC		 944
945 u8 stat_rate_support[0x10];
e1c9c62b 946 u8 reserved_at_1f0[0xc];
e281682b 947 u8 cqe_version[0x4];
b775516b 948
e281682b 949 u8 compact_address_vector[0x1];
7d5e1423 950 u8 striding_rq[0x1];
500a3d0d
ES		 951 u8 reserved_at_202[0x1];
952 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 953 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 954 u8 reserved_at_205[0x1];
955 u8 repeated_block_disabled[0x1];
956 u8 umr_modify_entity_size_disabled[0x1];
957 u8 umr_modify_atomic_disabled[0x1];
958 u8 umr_indirect_mkey_disabled[0x1];
1410a90a
MG		 959 u8 umr_fence[0x2];
960 u8 reserved_at_20c[0x3];
e281682b 961 u8 drain_sigerr[0x1];
b775516b
EC		 962 u8 cmdif_checksum[0x2];
963 u8 sigerr_cqe[0x1];
e1c9c62b 964 u8 reserved_at_213[0x1];
b775516b
EC		 965 u8 wq_signature[0x1];
966 u8 sctr_data_cqe[0x1];
e1c9c62b 967 u8 reserved_at_216[0x1];
b775516b
EC		 968 u8 sho[0x1];
969 u8 tph[0x1];
970 u8 rf[0x1];
e281682b 971 u8 dct[0x1];
7486216b 972 u8 qos[0x1];
e281682b 973 u8 eth_net_offloads[0x1];
b775516b
EC		 974 u8 roce[0x1];
975 u8 atomic[0x1];
e1c9c62b 976 u8 reserved_at_21f[0x1];
b775516b
EC		 977
978 u8 cq_oi[0x1];
979 u8 cq_resize[0x1];
980 u8 cq_moderation[0x1];
e1c9c62b 981 u8 reserved_at_223[0x3];
e281682b 982 u8 cq_eq_remap[0x1];
b775516b
EC		 983 u8 pg[0x1];
984 u8 block_lb_mc[0x1];
e1c9c62b 985 u8 reserved_at_229[0x1];
e281682b 986 u8 scqe_break_moderation[0x1];
7d5e1423 987 u8 cq_period_start_from_cqe[0x1];
b775516b 988 u8 cd[0x1];
e1c9c62b 989 u8 reserved_at_22d[0x1];
b775516b 990 u8 apm[0x1];
3f0393a5 991 u8 vector_calc[0x1];
7d5e1423 992 u8 umr_ptr_rlky[0x1];
d2370e0a 993 u8 imaicl[0x1];
e1c9c62b 994 u8 reserved_at_232[0x4];
b775516b
EC		 995 u8 qkv[0x1];
996 u8 pkv[0x1];
b11a4f9c
HE		 997 u8 set_deth_sqpn[0x1];
998 u8 reserved_at_239[0x3];
b775516b
EC		 999 u8 xrc[0x1];
1000 u8 ud[0x1];
1001 u8 uc[0x1];
1002 u8 rc[0x1];
1003
a6d51b68
EC		 1004 u8 uar_4k[0x1];
1005 u8 reserved_at_241[0x9];
b775516b 1006 u8 uar_sz[0x6];
e1c9c62b 1007 u8 reserved_at_250[0x8];
b775516b
EC		 1008 u8 log_pg_sz[0x8];
1009
1010 u8 bf[0x1];
0dbc6fe0 1011 u8 driver_version[0x1];
e281682b 1012 u8 pad_tx_eth_packet[0x1];
e1c9c62b 1013 u8 reserved_at_263[0x8];
b775516b 1014 u8 log_bf_reg_size[0x5];
84df61eb
AH		 1015
1016 u8 reserved_at_270[0xb];
1017 u8 lag_master[0x1];
1018 u8 num_lag_ports[0x4];
b775516b 1019
e1c9c62b 1020 u8 reserved_at_280[0x10];
b775516b
EC		 1021 u8 max_wqe_sz_sq[0x10];
1022
e1c9c62b 1023 u8 reserved_at_2a0[0x10];
b775516b
EC		 1024 u8 max_wqe_sz_rq[0x10];
1025
a8ffcc74 1026 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1027 u8 max_wqe_sz_sq_dc[0x10];
1028
e1c9c62b 1029 u8 reserved_at_2e0[0x7];
b775516b
EC		 1030 u8 max_qp_mcg[0x19];
1031
e1c9c62b 1032 u8 reserved_at_300[0x18];
b775516b
EC		 1033 u8 log_max_mcg[0x8];
1034
e1c9c62b 1035 u8 reserved_at_320[0x3];
e281682b 1036 u8 log_max_transport_domain[0x5];
e1c9c62b 1037 u8 reserved_at_328[0x3];
b775516b 1038 u8 log_max_pd[0x5];
e1c9c62b 1039 u8 reserved_at_330[0xb];
b775516b
EC		 1040 u8 log_max_xrcd[0x5];
1041
5c298143 1042 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1043 u8 receive_discard_vport_down[0x1];
1044 u8 transmit_discard_vport_down[0x1];
1045 u8 reserved_at_343[0x5];
a351a1b0 1046 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1047 u8 max_flow_counter_15_0[0x10];
a351a1b0 1048
b775516b 1049
e1c9c62b 1050 u8 reserved_at_360[0x3];
b775516b 1051 u8 log_max_rq[0x5];
e1c9c62b 1052 u8 reserved_at_368[0x3];
b775516b 1053 u8 log_max_sq[0x5];
e1c9c62b 1054 u8 reserved_at_370[0x3];
b775516b 1055 u8 log_max_tir[0x5];
e1c9c62b 1056 u8 reserved_at_378[0x3];
b775516b
EC		 1057 u8 log_max_tis[0x5];
1058
e281682b 1059 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1060 u8 reserved_at_381[0x2];
e281682b 1061 u8 log_max_rmp[0x5];
e1c9c62b 1062 u8 reserved_at_388[0x3];
e281682b 1063 u8 log_max_rqt[0x5];
e1c9c62b 1064 u8 reserved_at_390[0x3];
e281682b 1065 u8 log_max_rqt_size[0x5];
e1c9c62b 1066 u8 reserved_at_398[0x3];
b775516b
EC		 1067 u8 log_max_tis_per_sq[0x5];
1068
619a8f2a
TT		 1069 u8 ext_stride_num_range[0x1];
1070 u8 reserved_at_3a1[0x2];
e281682b 1071 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1072 u8 reserved_at_3a8[0x3];
e281682b 1073 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1074 u8 reserved_at_3b0[0x3];
e281682b 1075 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1076 u8 reserved_at_3b8[0x3];
e281682b
SM		 1077 u8 log_min_stride_sz_sq[0x5];
1078
40817cdb
OG		 1079 u8 hairpin[0x1];
1080 u8 reserved_at_3c1[0x2];
1081 u8 log_max_hairpin_queues[0x5];
1082 u8 reserved_at_3c8[0x3];
1083 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1084 u8 reserved_at_3d0[0x3];
1085 u8 log_max_hairpin_num_packets[0x5];
1086 u8 reserved_at_3d8[0x3];
e281682b
SM		 1087 u8 log_max_wq_sz[0x5];
1088
54f0a411 1089 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1090 u8 disable_local_lb_uc[0x1];
1091 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1092 u8 log_min_hairpin_wq_data_sz[0x5];
1093 u8 reserved_at_3e8[0x3];
54f0a411 1094 u8 log_max_vlan_list[0x5];
e1c9c62b 1095 u8 reserved_at_3f0[0x3];
54f0a411 1096 u8 log_max_current_mc_list[0x5];
e1c9c62b 1097 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1098 u8 log_max_current_uc_list[0x5];
1099
e1c9c62b 1100 u8 reserved_at_400[0x80];
54f0a411 1101
e1c9c62b 1102 u8 reserved_at_480[0x3];
e281682b 1103 u8 log_max_l2_table[0x5];
e1c9c62b 1104 u8 reserved_at_488[0x8];
b775516b
EC		 1105 u8 log_uar_page_sz[0x10];
1106
e1c9c62b 1107 u8 reserved_at_4a0[0x20];
048ccca8 1108 u8 device_frequency_mhz[0x20];
b0844444 1109 u8 device_frequency_khz[0x20];
e1c9c62b 1110
a6d51b68
EC		 1111 u8 reserved_at_500[0x20];
1112 u8 num_of_uars_per_page[0x20];
1113 u8 reserved_at_540[0x40];
e1c9c62b 1114
ab741b2e
YC		 1115 u8 reserved_at_580[0x3c];
1116 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1117 u8 cqe_128_always[0x1];
1118 u8 cqe_compression_128[0x1];
7d5e1423 1119 u8 cqe_compression[0x1];
b775516b 1120
7d5e1423
SM		 1121 u8 cqe_compression_timeout[0x10];
1122 u8 cqe_compression_max_num[0x10];
b775516b 1123
7486216b
SM		 1124 u8 reserved_at_5e0[0x10];
1125 u8 tag_matching[0x1];
1126 u8 rndv_offload_rc[0x1];
1127 u8 rndv_offload_dc[0x1];
1128 u8 log_tag_matching_list_sz[0x5];
7b13558f 1129 u8 reserved_at_5f8[0x3];
7486216b
SM		 1130 u8 log_max_xrq[0x5];
1131
32f69e4b
DJ		 1132 u8 affiliate_nic_vport_criteria[0x8];
1133 u8 native_port_num[0x8];
1134 u8 num_vhca_ports[0x8];
1135 u8 reserved_at_618[0x6];
1136 u8 sw_owner_id[0x1];
8737f818 1137 u8 reserved_at_61f[0x1e1];
b775516b
EC		 1138};
1139
81848731
SM		 1140enum mlx5_flow_destination_type {
1141 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1142 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1143 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1144
5f418378 1145 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1146 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1147};
b775516b 1148
e281682b
SM		 1149struct mlx5_ifc_dest_format_struct_bits {
1150 u8 destination_type[0x8];
1151 u8 destination_id[0x18];
b17f7fc1
SK		 1152 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1153 u8 reserved_at_21[0xf];
1154 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1155};
1156
9dc0b289 1157struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1158 u8 flow_counter_id[0x20];
9dc0b289
AV		 1159
1160 u8 reserved_at_20[0x20];
1161};
1162
1163union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1164 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1165 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1166 u8 reserved_at_0[0x40];
1167};
1168
e281682b
SM		 1169struct mlx5_ifc_fte_match_param_bits {
1170 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1171
1172 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1173
1174 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1175
b4ff3a36 1176 u8 reserved_at_600[0xa00];
b775516b
EC		 1177};
1178
e281682b
SM		 1179enum {
1180 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1181 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1182 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1183 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1184 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1185};
b775516b 1186
e281682b
SM		 1187struct mlx5_ifc_rx_hash_field_select_bits {
1188 u8 l3_prot_type[0x1];
1189 u8 l4_prot_type[0x1];
1190 u8 selected_fields[0x1e];
1191};
b775516b 1192
e281682b
SM		 1193enum {
1194 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1195 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1196};
1197
e281682b
SM		 1198enum {
1199 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1200 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1201};
1202
1203struct mlx5_ifc_wq_bits {
1204 u8 wq_type[0x4];
1205 u8 wq_signature[0x1];
1206 u8 end_padding_mode[0x2];
1207 u8 cd_slave[0x1];
b4ff3a36 1208 u8 reserved_at_8[0x18];
b775516b 1209
e281682b
SM		 1210 u8 hds_skip_first_sge[0x1];
1211 u8 log2_hds_buf_size[0x3];
b4ff3a36 1212 u8 reserved_at_24[0x7];
e281682b
SM		 1213 u8 page_offset[0x5];
1214 u8 lwm[0x10];
b775516b 1215
b4ff3a36 1216 u8 reserved_at_40[0x8];
e281682b
SM		 1217 u8 pd[0x18];
1218
b4ff3a36 1219 u8 reserved_at_60[0x8];
e281682b
SM		 1220 u8 uar_page[0x18];
1221
1222 u8 dbr_addr[0x40];
1223
1224 u8 hw_counter[0x20];
1225
1226 u8 sw_counter[0x20];
1227
b4ff3a36 1228 u8 reserved_at_100[0xc];
e281682b 1229 u8 log_wq_stride[0x4];
b4ff3a36 1230 u8 reserved_at_110[0x3];
e281682b 1231 u8 log_wq_pg_sz[0x5];
b4ff3a36 1232 u8 reserved_at_118[0x3];
e281682b
SM		 1233 u8 log_wq_sz[0x5];
1234
4d533e0f
OG		 1235 u8 reserved_at_120[0x3];
1236 u8 log_hairpin_num_packets[0x5];
1237 u8 reserved_at_128[0x3];
40817cdb 1238 u8 log_hairpin_data_sz[0x5];
40817cdb 1239
619a8f2a
TT		 1240 u8 reserved_at_130[0x4];
1241 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1242 u8 two_byte_shift_en[0x1];
1243 u8 reserved_at_139[0x4];
1244 u8 log_wqe_stride_size[0x3];
1245
1246 u8 reserved_at_140[0x4c0];
b775516b 1247
e281682b 1248 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1249};
1250
e281682b 1251struct mlx5_ifc_rq_num_bits {
b4ff3a36 1252 u8 reserved_at_0[0x8];
e281682b
SM		 1253 u8 rq_num[0x18];
1254};
b775516b 1255
e281682b 1256struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1257 u8 reserved_at_0[0x10];
e281682b 1258 u8 mac_addr_47_32[0x10];
b775516b 1259
e281682b
SM		 1260 u8 mac_addr_31_0[0x20];
1261};
1262
c0046cf7 1263struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1264 u8 reserved_at_0[0x14];
c0046cf7
SM		 1265 u8 vlan[0x0c];
1266
b4ff3a36 1267 u8 reserved_at_20[0x20];
c0046cf7
SM		 1268};
1269
e281682b 1270struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1271 u8 reserved_at_0[0xa0];
e281682b
SM		 1272
1273 u8 min_time_between_cnps[0x20];
1274
b4ff3a36 1275 u8 reserved_at_c0[0x12];
e281682b 1276 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1277 u8 reserved_at_d8[0x4];
1278 u8 cnp_prio_mode[0x1];
e281682b
SM		 1279 u8 cnp_802p_prio[0x3];
1280
b4ff3a36 1281 u8 reserved_at_e0[0x720];
e281682b
SM		 1282};
1283
1284struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1285 u8 reserved_at_0[0x60];
e281682b 1286
b4ff3a36 1287 u8 reserved_at_60[0x4];
e281682b 1288 u8 clamp_tgt_rate[0x1];
b4ff3a36 1289 u8 reserved_at_65[0x3];
e281682b 1290 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1291 u8 reserved_at_69[0x17];
e281682b 1292
b4ff3a36 1293 u8 reserved_at_80[0x20];
e281682b
SM		 1294
1295 u8 rpg_time_reset[0x20];
1296
1297 u8 rpg_byte_reset[0x20];
1298
1299 u8 rpg_threshold[0x20];
1300
1301 u8 rpg_max_rate[0x20];
1302
1303 u8 rpg_ai_rate[0x20];
1304
1305 u8 rpg_hai_rate[0x20];
1306
1307 u8 rpg_gd[0x20];
1308
1309 u8 rpg_min_dec_fac[0x20];
1310
1311 u8 rpg_min_rate[0x20];
1312
b4ff3a36 1313 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1314
1315 u8 rate_to_set_on_first_cnp[0x20];
1316
1317 u8 dce_tcp_g[0x20];
1318
1319 u8 dce_tcp_rtt[0x20];
1320
1321 u8 rate_reduce_monitor_period[0x20];
1322
b4ff3a36 1323 u8 reserved_at_320[0x20];
e281682b
SM		 1324
1325 u8 initial_alpha_value[0x20];
1326
b4ff3a36 1327 u8 reserved_at_360[0x4a0];
e281682b
SM		 1328};
1329
1330struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1331 u8 reserved_at_0[0x80];
e281682b
SM		 1332
1333 u8 rppp_max_rps[0x20];
1334
1335 u8 rpg_time_reset[0x20];
1336
1337 u8 rpg_byte_reset[0x20];
1338
1339 u8 rpg_threshold[0x20];
1340
1341 u8 rpg_max_rate[0x20];
1342
1343 u8 rpg_ai_rate[0x20];
1344
1345 u8 rpg_hai_rate[0x20];
1346
1347 u8 rpg_gd[0x20];
1348
1349 u8 rpg_min_dec_fac[0x20];
1350
1351 u8 rpg_min_rate[0x20];
1352
b4ff3a36 1353 u8 reserved_at_1c0[0x640];
e281682b
SM		 1354};
1355
1356enum {
1357 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1358 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1359 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1360};
1361
1362struct mlx5_ifc_resize_field_select_bits {
1363 u8 resize_field_select[0x20];
1364};
1365
1366enum {
1367 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1368 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1369 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1370 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1371};
1372
1373struct mlx5_ifc_modify_field_select_bits {
1374 u8 modify_field_select[0x20];
1375};
1376
1377struct mlx5_ifc_field_select_r_roce_np_bits {
1378 u8 field_select_r_roce_np[0x20];
1379};
1380
1381struct mlx5_ifc_field_select_r_roce_rp_bits {
1382 u8 field_select_r_roce_rp[0x20];
1383};
1384
1385enum {
1386 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1387 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1388 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1389 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1390 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1391 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1392 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1393 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1394 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1395 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1396};
1397
1398struct mlx5_ifc_field_select_802_1qau_rp_bits {
1399 u8 field_select_8021qaurp[0x20];
1400};
1401
1402struct mlx5_ifc_phys_layer_cntrs_bits {
1403 u8 time_since_last_clear_high[0x20];
1404
1405 u8 time_since_last_clear_low[0x20];
1406
1407 u8 symbol_errors_high[0x20];
1408
1409 u8 symbol_errors_low[0x20];
1410
1411 u8 sync_headers_errors_high[0x20];
1412
1413 u8 sync_headers_errors_low[0x20];
1414
1415 u8 edpl_bip_errors_lane0_high[0x20];
1416
1417 u8 edpl_bip_errors_lane0_low[0x20];
1418
1419 u8 edpl_bip_errors_lane1_high[0x20];
1420
1421 u8 edpl_bip_errors_lane1_low[0x20];
1422
1423 u8 edpl_bip_errors_lane2_high[0x20];
1424
1425 u8 edpl_bip_errors_lane2_low[0x20];
1426
1427 u8 edpl_bip_errors_lane3_high[0x20];
1428
1429 u8 edpl_bip_errors_lane3_low[0x20];
1430
1431 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1432
1433 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1434
1435 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1436
1437 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1438
1439 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1440
1441 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1442
1443 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1444
1445 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1446
1447 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1448
1449 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1450
1451 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1452
1453 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1454
1455 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1456
1457 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1458
1459 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1460
1461 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1462
1463 u8 rs_fec_corrected_blocks_high[0x20];
1464
1465 u8 rs_fec_corrected_blocks_low[0x20];
1466
1467 u8 rs_fec_uncorrectable_blocks_high[0x20];
1468
1469 u8 rs_fec_uncorrectable_blocks_low[0x20];
1470
1471 u8 rs_fec_no_errors_blocks_high[0x20];
1472
1473 u8 rs_fec_no_errors_blocks_low[0x20];
1474
1475 u8 rs_fec_single_error_blocks_high[0x20];
1476
1477 u8 rs_fec_single_error_blocks_low[0x20];
1478
1479 u8 rs_fec_corrected_symbols_total_high[0x20];
1480
1481 u8 rs_fec_corrected_symbols_total_low[0x20];
1482
1483 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1484
1485 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1486
1487 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1488
1489 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1490
1491 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1492
1493 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1494
1495 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1496
1497 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1498
1499 u8 link_down_events[0x20];
1500
1501 u8 successful_recovery_events[0x20];
1502
b4ff3a36 1503 u8 reserved_at_640[0x180];
e281682b
SM		 1504};
1505
d8dc0508
GP		 1506struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1507 u8 time_since_last_clear_high[0x20];
1508
1509 u8 time_since_last_clear_low[0x20];
1510
1511 u8 phy_received_bits_high[0x20];
1512
1513 u8 phy_received_bits_low[0x20];
1514
1515 u8 phy_symbol_errors_high[0x20];
1516
1517 u8 phy_symbol_errors_low[0x20];
1518
1519 u8 phy_corrected_bits_high[0x20];
1520
1521 u8 phy_corrected_bits_low[0x20];
1522
1523 u8 phy_corrected_bits_lane0_high[0x20];
1524
1525 u8 phy_corrected_bits_lane0_low[0x20];
1526
1527 u8 phy_corrected_bits_lane1_high[0x20];
1528
1529 u8 phy_corrected_bits_lane1_low[0x20];
1530
1531 u8 phy_corrected_bits_lane2_high[0x20];
1532
1533 u8 phy_corrected_bits_lane2_low[0x20];
1534
1535 u8 phy_corrected_bits_lane3_high[0x20];
1536
1537 u8 phy_corrected_bits_lane3_low[0x20];
1538
1539 u8 reserved_at_200[0x5c0];
1540};
1541
1c64bf6f
MY		 1542struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1543 u8 symbol_error_counter[0x10];
1544
1545 u8 link_error_recovery_counter[0x8];
1546
1547 u8 link_downed_counter[0x8];
1548
1549 u8 port_rcv_errors[0x10];
1550
1551 u8 port_rcv_remote_physical_errors[0x10];
1552
1553 u8 port_rcv_switch_relay_errors[0x10];
1554
1555 u8 port_xmit_discards[0x10];
1556
1557 u8 port_xmit_constraint_errors[0x8];
1558
1559 u8 port_rcv_constraint_errors[0x8];
1560
1561 u8 reserved_at_70[0x8];
1562
1563 u8 link_overrun_errors[0x8];
1564
1565 u8 reserved_at_80[0x10];
1566
1567 u8 vl_15_dropped[0x10];
1568
133bea04
TW		 1569 u8 reserved_at_a0[0x80];
1570
1571 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1572};
1573
e281682b
SM		 1574struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1575 u8 transmit_queue_high[0x20];
1576
1577 u8 transmit_queue_low[0x20];
1578
b4ff3a36 1579 u8 reserved_at_40[0x780];
e281682b
SM		 1580};
1581
1582struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1583 u8 rx_octets_high[0x20];
1584
1585 u8 rx_octets_low[0x20];
1586
b4ff3a36 1587 u8 reserved_at_40[0xc0];
e281682b
SM		 1588
1589 u8 rx_frames_high[0x20];
1590
1591 u8 rx_frames_low[0x20];
1592
1593 u8 tx_octets_high[0x20];
1594
1595 u8 tx_octets_low[0x20];
1596
b4ff3a36 1597 u8 reserved_at_180[0xc0];
e281682b
SM		 1598
1599 u8 tx_frames_high[0x20];
1600
1601 u8 tx_frames_low[0x20];
1602
1603 u8 rx_pause_high[0x20];
1604
1605 u8 rx_pause_low[0x20];
1606
1607 u8 rx_pause_duration_high[0x20];
1608
1609 u8 rx_pause_duration_low[0x20];
1610
1611 u8 tx_pause_high[0x20];
1612
1613 u8 tx_pause_low[0x20];
1614
1615 u8 tx_pause_duration_high[0x20];
1616
1617 u8 tx_pause_duration_low[0x20];
1618
1619 u8 rx_pause_transition_high[0x20];
1620
1621 u8 rx_pause_transition_low[0x20];
1622
2fcb12df
IK		 1623 u8 reserved_at_3c0[0x40];
1624
1625 u8 device_stall_minor_watermark_cnt_high[0x20];
1626
1627 u8 device_stall_minor_watermark_cnt_low[0x20];
1628
1629 u8 device_stall_critical_watermark_cnt_high[0x20];
1630
1631 u8 device_stall_critical_watermark_cnt_low[0x20];
1632
1633 u8 reserved_at_480[0x340];
e281682b
SM		 1634};
1635
1636struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1637 u8 port_transmit_wait_high[0x20];
1638
1639 u8 port_transmit_wait_low[0x20];
1640
2dba0797
GP		 1641 u8 reserved_at_40[0x100];
1642
1643 u8 rx_buffer_almost_full_high[0x20];
1644
1645 u8 rx_buffer_almost_full_low[0x20];
1646
1647 u8 rx_buffer_full_high[0x20];
1648
1649 u8 rx_buffer_full_low[0x20];
1650
1651 u8 reserved_at_1c0[0x600];
e281682b
SM		 1652};
1653
1654struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1655 u8 dot3stats_alignment_errors_high[0x20];
1656
1657 u8 dot3stats_alignment_errors_low[0x20];
1658
1659 u8 dot3stats_fcs_errors_high[0x20];
1660
1661 u8 dot3stats_fcs_errors_low[0x20];
1662
1663 u8 dot3stats_single_collision_frames_high[0x20];
1664
1665 u8 dot3stats_single_collision_frames_low[0x20];
1666
1667 u8 dot3stats_multiple_collision_frames_high[0x20];
1668
1669 u8 dot3stats_multiple_collision_frames_low[0x20];
1670
1671 u8 dot3stats_sqe_test_errors_high[0x20];
1672
1673 u8 dot3stats_sqe_test_errors_low[0x20];
1674
1675 u8 dot3stats_deferred_transmissions_high[0x20];
1676
1677 u8 dot3stats_deferred_transmissions_low[0x20];
1678
1679 u8 dot3stats_late_collisions_high[0x20];
1680
1681 u8 dot3stats_late_collisions_low[0x20];
1682
1683 u8 dot3stats_excessive_collisions_high[0x20];
1684
1685 u8 dot3stats_excessive_collisions_low[0x20];
1686
1687 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1688
1689 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1690
1691 u8 dot3stats_carrier_sense_errors_high[0x20];
1692
1693 u8 dot3stats_carrier_sense_errors_low[0x20];
1694
1695 u8 dot3stats_frame_too_longs_high[0x20];
1696
1697 u8 dot3stats_frame_too_longs_low[0x20];
1698
1699 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1700
1701 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1702
1703 u8 dot3stats_symbol_errors_high[0x20];
1704
1705 u8 dot3stats_symbol_errors_low[0x20];
1706
1707 u8 dot3control_in_unknown_opcodes_high[0x20];
1708
1709 u8 dot3control_in_unknown_opcodes_low[0x20];
1710
1711 u8 dot3in_pause_frames_high[0x20];
1712
1713 u8 dot3in_pause_frames_low[0x20];
1714
1715 u8 dot3out_pause_frames_high[0x20];
1716
1717 u8 dot3out_pause_frames_low[0x20];
1718
b4ff3a36 1719 u8 reserved_at_400[0x3c0];
e281682b
SM		 1720};
1721
1722struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1723 u8 ether_stats_drop_events_high[0x20];
1724
1725 u8 ether_stats_drop_events_low[0x20];
1726
1727 u8 ether_stats_octets_high[0x20];
1728
1729 u8 ether_stats_octets_low[0x20];
1730
1731 u8 ether_stats_pkts_high[0x20];
1732
1733 u8 ether_stats_pkts_low[0x20];
1734
1735 u8 ether_stats_broadcast_pkts_high[0x20];
1736
1737 u8 ether_stats_broadcast_pkts_low[0x20];
1738
1739 u8 ether_stats_multicast_pkts_high[0x20];
1740
1741 u8 ether_stats_multicast_pkts_low[0x20];
1742
1743 u8 ether_stats_crc_align_errors_high[0x20];
1744
1745 u8 ether_stats_crc_align_errors_low[0x20];
1746
1747 u8 ether_stats_undersize_pkts_high[0x20];
1748
1749 u8 ether_stats_undersize_pkts_low[0x20];
1750
1751 u8 ether_stats_oversize_pkts_high[0x20];
1752
1753 u8 ether_stats_oversize_pkts_low[0x20];
1754
1755 u8 ether_stats_fragments_high[0x20];
1756
1757 u8 ether_stats_fragments_low[0x20];
1758
1759 u8 ether_stats_jabbers_high[0x20];
1760
1761 u8 ether_stats_jabbers_low[0x20];
1762
1763 u8 ether_stats_collisions_high[0x20];
1764
1765 u8 ether_stats_collisions_low[0x20];
1766
1767 u8 ether_stats_pkts64octets_high[0x20];
1768
1769 u8 ether_stats_pkts64octets_low[0x20];
1770
1771 u8 ether_stats_pkts65to127octets_high[0x20];
1772
1773 u8 ether_stats_pkts65to127octets_low[0x20];
1774
1775 u8 ether_stats_pkts128to255octets_high[0x20];
1776
1777 u8 ether_stats_pkts128to255octets_low[0x20];
1778
1779 u8 ether_stats_pkts256to511octets_high[0x20];
1780
1781 u8 ether_stats_pkts256to511octets_low[0x20];
1782
1783 u8 ether_stats_pkts512to1023octets_high[0x20];
1784
1785 u8 ether_stats_pkts512to1023octets_low[0x20];
1786
1787 u8 ether_stats_pkts1024to1518octets_high[0x20];
1788
1789 u8 ether_stats_pkts1024to1518octets_low[0x20];
1790
1791 u8 ether_stats_pkts1519to2047octets_high[0x20];
1792
1793 u8 ether_stats_pkts1519to2047octets_low[0x20];
1794
1795 u8 ether_stats_pkts2048to4095octets_high[0x20];
1796
1797 u8 ether_stats_pkts2048to4095octets_low[0x20];
1798
1799 u8 ether_stats_pkts4096to8191octets_high[0x20];
1800
1801 u8 ether_stats_pkts4096to8191octets_low[0x20];
1802
1803 u8 ether_stats_pkts8192to10239octets_high[0x20];
1804
1805 u8 ether_stats_pkts8192to10239octets_low[0x20];
1806
b4ff3a36 1807 u8 reserved_at_540[0x280];
e281682b
SM		 1808};
1809
1810struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1811 u8 if_in_octets_high[0x20];
1812
1813 u8 if_in_octets_low[0x20];
1814
1815 u8 if_in_ucast_pkts_high[0x20];
1816
1817 u8 if_in_ucast_pkts_low[0x20];
1818
1819 u8 if_in_discards_high[0x20];
1820
1821 u8 if_in_discards_low[0x20];
1822
1823 u8 if_in_errors_high[0x20];
1824
1825 u8 if_in_errors_low[0x20];
1826
1827 u8 if_in_unknown_protos_high[0x20];
1828
1829 u8 if_in_unknown_protos_low[0x20];
1830
1831 u8 if_out_octets_high[0x20];
1832
1833 u8 if_out_octets_low[0x20];
1834
1835 u8 if_out_ucast_pkts_high[0x20];
1836
1837 u8 if_out_ucast_pkts_low[0x20];
1838
1839 u8 if_out_discards_high[0x20];
1840
1841 u8 if_out_discards_low[0x20];
1842
1843 u8 if_out_errors_high[0x20];
1844
1845 u8 if_out_errors_low[0x20];
1846
1847 u8 if_in_multicast_pkts_high[0x20];
1848
1849 u8 if_in_multicast_pkts_low[0x20];
1850
1851 u8 if_in_broadcast_pkts_high[0x20];
1852
1853 u8 if_in_broadcast_pkts_low[0x20];
1854
1855 u8 if_out_multicast_pkts_high[0x20];
1856
1857 u8 if_out_multicast_pkts_low[0x20];
1858
1859 u8 if_out_broadcast_pkts_high[0x20];
1860
1861 u8 if_out_broadcast_pkts_low[0x20];
1862
b4ff3a36 1863 u8 reserved_at_340[0x480];
e281682b
SM		 1864};
1865
1866struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1867 u8 a_frames_transmitted_ok_high[0x20];
1868
1869 u8 a_frames_transmitted_ok_low[0x20];
1870
1871 u8 a_frames_received_ok_high[0x20];
1872
1873 u8 a_frames_received_ok_low[0x20];
1874
1875 u8 a_frame_check_sequence_errors_high[0x20];
1876
1877 u8 a_frame_check_sequence_errors_low[0x20];
1878
1879 u8 a_alignment_errors_high[0x20];
1880
1881 u8 a_alignment_errors_low[0x20];
1882
1883 u8 a_octets_transmitted_ok_high[0x20];
1884
1885 u8 a_octets_transmitted_ok_low[0x20];
1886
1887 u8 a_octets_received_ok_high[0x20];
1888
1889 u8 a_octets_received_ok_low[0x20];
1890
1891 u8 a_multicast_frames_xmitted_ok_high[0x20];
1892
1893 u8 a_multicast_frames_xmitted_ok_low[0x20];
1894
1895 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1896
1897 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1898
1899 u8 a_multicast_frames_received_ok_high[0x20];
1900
1901 u8 a_multicast_frames_received_ok_low[0x20];
1902
1903 u8 a_broadcast_frames_received_ok_high[0x20];
1904
1905 u8 a_broadcast_frames_received_ok_low[0x20];
1906
1907 u8 a_in_range_length_errors_high[0x20];
1908
1909 u8 a_in_range_length_errors_low[0x20];
1910
1911 u8 a_out_of_range_length_field_high[0x20];
1912
1913 u8 a_out_of_range_length_field_low[0x20];
1914
1915 u8 a_frame_too_long_errors_high[0x20];
1916
1917 u8 a_frame_too_long_errors_low[0x20];
1918
1919 u8 a_symbol_error_during_carrier_high[0x20];
1920
1921 u8 a_symbol_error_during_carrier_low[0x20];
1922
1923 u8 a_mac_control_frames_transmitted_high[0x20];
1924
1925 u8 a_mac_control_frames_transmitted_low[0x20];
1926
1927 u8 a_mac_control_frames_received_high[0x20];
1928
1929 u8 a_mac_control_frames_received_low[0x20];
1930
1931 u8 a_unsupported_opcodes_received_high[0x20];
1932
1933 u8 a_unsupported_opcodes_received_low[0x20];
1934
1935 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1936
1937 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1938
1939 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1940
1941 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1942
b4ff3a36 1943 u8 reserved_at_4c0[0x300];
e281682b
SM		 1944};
1945
8ed1a630
GP		 1946struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1947 u8 life_time_counter_high[0x20];
1948
1949 u8 life_time_counter_low[0x20];
1950
1951 u8 rx_errors[0x20];
1952
1953 u8 tx_errors[0x20];
1954
1955 u8 l0_to_recovery_eieos[0x20];
1956
1957 u8 l0_to_recovery_ts[0x20];
1958
1959 u8 l0_to_recovery_framing[0x20];
1960
1961 u8 l0_to_recovery_retrain[0x20];
1962
1963 u8 crc_error_dllp[0x20];
1964
1965 u8 crc_error_tlp[0x20];
1966
efae7f78
EBE		 1967 u8 tx_overflow_buffer_pkt_high[0x20];
1968
1969 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 1970
1971 u8 outbound_stalled_reads[0x20];
1972
1973 u8 outbound_stalled_writes[0x20];
1974
1975 u8 outbound_stalled_reads_events[0x20];
1976
1977 u8 outbound_stalled_writes_events[0x20];
1978
1979 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 1980};
1981
e281682b
SM		 1982struct mlx5_ifc_cmd_inter_comp_event_bits {
1983 u8 command_completion_vector[0x20];
1984
b4ff3a36 1985 u8 reserved_at_20[0xc0];
e281682b
SM		 1986};
1987
1988struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1989 u8 reserved_at_0[0x18];
e281682b 1990 u8 port_num[0x1];
b4ff3a36 1991 u8 reserved_at_19[0x3];
e281682b
SM		 1992 u8 vl[0x4];
1993
b4ff3a36 1994 u8 reserved_at_20[0xa0];
e281682b
SM		 1995};
1996
1997struct mlx5_ifc_db_bf_congestion_event_bits {
1998 u8 event_subtype[0x8];
b4ff3a36 1999 u8 reserved_at_8[0x8];
e281682b 2000 u8 congestion_level[0x8];
b4ff3a36 2001 u8 reserved_at_18[0x8];
e281682b 2002
b4ff3a36 2003 u8 reserved_at_20[0xa0];
e281682b
SM		 2004};
2005
2006struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2007 u8 reserved_at_0[0x60];
e281682b
SM		 2008
2009 u8 gpio_event_hi[0x20];
2010
2011 u8 gpio_event_lo[0x20];
2012
b4ff3a36 2013 u8 reserved_at_a0[0x40];
e281682b
SM		 2014};
2015
2016struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2017 u8 reserved_at_0[0x40];
e281682b
SM		 2018
2019 u8 port_num[0x4];
b4ff3a36 2020 u8 reserved_at_44[0x1c];
e281682b 2021
b4ff3a36 2022 u8 reserved_at_60[0x80];
e281682b
SM		 2023};
2024
2025struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2026 u8 reserved_at_0[0xe0];
e281682b
SM		 2027};
2028
2029enum {
2030 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2031 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2032};
2033
2034struct mlx5_ifc_cq_error_bits {
b4ff3a36 2035 u8 reserved_at_0[0x8];
e281682b
SM		 2036 u8 cqn[0x18];
2037
b4ff3a36 2038 u8 reserved_at_20[0x20];
e281682b 2039
b4ff3a36 2040 u8 reserved_at_40[0x18];
e281682b
SM		 2041 u8 syndrome[0x8];
2042
b4ff3a36 2043 u8 reserved_at_60[0x80];
e281682b
SM		 2044};
2045
2046struct mlx5_ifc_rdma_page_fault_event_bits {
2047 u8 bytes_committed[0x20];
2048
2049 u8 r_key[0x20];
2050
b4ff3a36 2051 u8 reserved_at_40[0x10];
e281682b
SM		 2052 u8 packet_len[0x10];
2053
2054 u8 rdma_op_len[0x20];
2055
2056 u8 rdma_va[0x40];
2057
b4ff3a36 2058 u8 reserved_at_c0[0x5];
e281682b
SM		 2059 u8 rdma[0x1];
2060 u8 write[0x1];
2061 u8 requestor[0x1];
2062 u8 qp_number[0x18];
2063};
2064
2065struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2066 u8 bytes_committed[0x20];
2067
b4ff3a36 2068 u8 reserved_at_20[0x10];
e281682b
SM		 2069 u8 wqe_index[0x10];
2070
b4ff3a36 2071 u8 reserved_at_40[0x10];
e281682b
SM		 2072 u8 len[0x10];
2073
b4ff3a36 2074 u8 reserved_at_60[0x60];
e281682b 2075
b4ff3a36 2076 u8 reserved_at_c0[0x5];
e281682b
SM		 2077 u8 rdma[0x1];
2078 u8 write_read[0x1];
2079 u8 requestor[0x1];
2080 u8 qpn[0x18];
2081};
2082
2083struct mlx5_ifc_qp_events_bits {
b4ff3a36 2084 u8 reserved_at_0[0xa0];
e281682b
SM		 2085
2086 u8 type[0x8];
b4ff3a36 2087 u8 reserved_at_a8[0x18];
e281682b 2088
b4ff3a36 2089 u8 reserved_at_c0[0x8];
e281682b
SM		 2090 u8 qpn_rqn_sqn[0x18];
2091};
2092
2093struct mlx5_ifc_dct_events_bits {
b4ff3a36 2094 u8 reserved_at_0[0xc0];
e281682b 2095
b4ff3a36 2096 u8 reserved_at_c0[0x8];
e281682b
SM		 2097 u8 dct_number[0x18];
2098};
2099
2100struct mlx5_ifc_comp_event_bits {
b4ff3a36 2101 u8 reserved_at_0[0xc0];
e281682b 2102
b4ff3a36 2103 u8 reserved_at_c0[0x8];
e281682b
SM		 2104 u8 cq_number[0x18];
2105};
2106
2107enum {
2108 MLX5_QPC_STATE_RST = 0x0,
2109 MLX5_QPC_STATE_INIT = 0x1,
2110 MLX5_QPC_STATE_RTR = 0x2,
2111 MLX5_QPC_STATE_RTS = 0x3,
2112 MLX5_QPC_STATE_SQER = 0x4,
2113 MLX5_QPC_STATE_ERR = 0x6,
2114 MLX5_QPC_STATE_SQD = 0x7,
2115 MLX5_QPC_STATE_SUSPENDED = 0x9,
2116};
2117
2118enum {
2119 MLX5_QPC_ST_RC = 0x0,
2120 MLX5_QPC_ST_UC = 0x1,
2121 MLX5_QPC_ST_UD = 0x2,
2122 MLX5_QPC_ST_XRC = 0x3,
2123 MLX5_QPC_ST_DCI = 0x5,
2124 MLX5_QPC_ST_QP0 = 0x7,
2125 MLX5_QPC_ST_QP1 = 0x8,
2126 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2127 MLX5_QPC_ST_REG_UMR = 0xc,
2128};
2129
2130enum {
2131 MLX5_QPC_PM_STATE_ARMED = 0x0,
2132 MLX5_QPC_PM_STATE_REARM = 0x1,
2133 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2134 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2135};
2136
6e44636a
AK		 2137enum {
2138 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2139};
2140
e281682b
SM		 2141enum {
2142 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2143 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2144};
2145
2146enum {
2147 MLX5_QPC_MTU_256_BYTES = 0x1,
2148 MLX5_QPC_MTU_512_BYTES = 0x2,
2149 MLX5_QPC_MTU_1K_BYTES = 0x3,
2150 MLX5_QPC_MTU_2K_BYTES = 0x4,
2151 MLX5_QPC_MTU_4K_BYTES = 0x5,
2152 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2153};
2154
2155enum {
2156 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2157 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2158 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2159 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2160 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2161 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2162 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2163 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2164};
2165
2166enum {
2167 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2168 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2169 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2170};
2171
2172enum {
2173 MLX5_QPC_CS_RES_DISABLE = 0x0,
2174 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2175 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2176};
2177
2178struct mlx5_ifc_qpc_bits {
2179 u8 state[0x4];
84df61eb 2180 u8 lag_tx_port_affinity[0x4];
e281682b 2181 u8 st[0x8];
b4ff3a36 2182 u8 reserved_at_10[0x3];
e281682b 2183 u8 pm_state[0x2];
6e44636a
AK		 2184 u8 reserved_at_15[0x3];
2185 u8 offload_type[0x4];
e281682b 2186 u8 end_padding_mode[0x2];
b4ff3a36 2187 u8 reserved_at_1e[0x2];
e281682b
SM		 2188
2189 u8 wq_signature[0x1];
2190 u8 block_lb_mc[0x1];
2191 u8 atomic_like_write_en[0x1];
2192 u8 latency_sensitive[0x1];
b4ff3a36 2193 u8 reserved_at_24[0x1];
e281682b 2194 u8 drain_sigerr[0x1];
b4ff3a36 2195 u8 reserved_at_26[0x2];
e281682b
SM		 2196 u8 pd[0x18];
2197
2198 u8 mtu[0x3];
2199 u8 log_msg_max[0x5];
b4ff3a36 2200 u8 reserved_at_48[0x1];
e281682b
SM		 2201 u8 log_rq_size[0x4];
2202 u8 log_rq_stride[0x3];
2203 u8 no_sq[0x1];
2204 u8 log_sq_size[0x4];
b4ff3a36 2205 u8 reserved_at_55[0x6];
e281682b 2206 u8 rlky[0x1];
1015c2e8 2207 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2208
2209 u8 counter_set_id[0x8];
2210 u8 uar_page[0x18];
2211
b4ff3a36 2212 u8 reserved_at_80[0x8];
e281682b
SM		 2213 u8 user_index[0x18];
2214
b4ff3a36 2215 u8 reserved_at_a0[0x3];
e281682b
SM		 2216 u8 log_page_size[0x5];
2217 u8 remote_qpn[0x18];
2218
2219 struct mlx5_ifc_ads_bits primary_address_path;
2220
2221 struct mlx5_ifc_ads_bits secondary_address_path;
2222
2223 u8 log_ack_req_freq[0x4];
b4ff3a36 2224 u8 reserved_at_384[0x4];
e281682b 2225 u8 log_sra_max[0x3];
b4ff3a36 2226 u8 reserved_at_38b[0x2];
e281682b
SM		 2227 u8 retry_count[0x3];
2228 u8 rnr_retry[0x3];
b4ff3a36 2229 u8 reserved_at_393[0x1];
e281682b
SM		 2230 u8 fre[0x1];
2231 u8 cur_rnr_retry[0x3];
2232 u8 cur_retry_count[0x3];
b4ff3a36 2233 u8 reserved_at_39b[0x5];
e281682b 2234
b4ff3a36 2235 u8 reserved_at_3a0[0x20];
e281682b 2236
b4ff3a36 2237 u8 reserved_at_3c0[0x8];
e281682b
SM		 2238 u8 next_send_psn[0x18];
2239
b4ff3a36 2240 u8 reserved_at_3e0[0x8];
e281682b
SM		 2241 u8 cqn_snd[0x18];
2242
09a7d9ec
SM		 2243 u8 reserved_at_400[0x8];
2244 u8 deth_sqpn[0x18];
2245
2246 u8 reserved_at_420[0x20];
e281682b 2247
b4ff3a36 2248 u8 reserved_at_440[0x8];
e281682b
SM		 2249 u8 last_acked_psn[0x18];
2250
b4ff3a36 2251 u8 reserved_at_460[0x8];
e281682b
SM		 2252 u8 ssn[0x18];
2253
b4ff3a36 2254 u8 reserved_at_480[0x8];
e281682b 2255 u8 log_rra_max[0x3];
b4ff3a36 2256 u8 reserved_at_48b[0x1];
e281682b
SM		 2257 u8 atomic_mode[0x4];
2258 u8 rre[0x1];
2259 u8 rwe[0x1];
2260 u8 rae[0x1];
b4ff3a36 2261 u8 reserved_at_493[0x1];
e281682b 2262 u8 page_offset[0x6];
b4ff3a36 2263 u8 reserved_at_49a[0x3];
e281682b
SM		 2264 u8 cd_slave_receive[0x1];
2265 u8 cd_slave_send[0x1];
2266 u8 cd_master[0x1];
2267
b4ff3a36 2268 u8 reserved_at_4a0[0x3];
e281682b
SM		 2269 u8 min_rnr_nak[0x5];
2270 u8 next_rcv_psn[0x18];
2271
b4ff3a36 2272 u8 reserved_at_4c0[0x8];
e281682b
SM		 2273 u8 xrcd[0x18];
2274
b4ff3a36 2275 u8 reserved_at_4e0[0x8];
e281682b
SM		 2276 u8 cqn_rcv[0x18];
2277
2278 u8 dbr_addr[0x40];
2279
2280 u8 q_key[0x20];
2281
b4ff3a36 2282 u8 reserved_at_560[0x5];
e281682b 2283 u8 rq_type[0x3];
7486216b 2284 u8 srqn_rmpn_xrqn[0x18];
e281682b 2285
b4ff3a36 2286 u8 reserved_at_580[0x8];
e281682b
SM		 2287 u8 rmsn[0x18];
2288
2289 u8 hw_sq_wqebb_counter[0x10];
2290 u8 sw_sq_wqebb_counter[0x10];
2291
2292 u8 hw_rq_counter[0x20];
2293
2294 u8 sw_rq_counter[0x20];
2295
b4ff3a36 2296 u8 reserved_at_600[0x20];
e281682b 2297
b4ff3a36 2298 u8 reserved_at_620[0xf];
e281682b
SM		 2299 u8 cgs[0x1];
2300 u8 cs_req[0x8];
2301 u8 cs_res[0x8];
2302
2303 u8 dc_access_key[0x40];
2304
b4ff3a36 2305 u8 reserved_at_680[0xc0];
e281682b
SM		 2306};
2307
2308struct mlx5_ifc_roce_addr_layout_bits {
2309 u8 source_l3_address[16][0x8];
2310
b4ff3a36 2311 u8 reserved_at_80[0x3];
e281682b
SM		 2312 u8 vlan_valid[0x1];
2313 u8 vlan_id[0xc];
2314 u8 source_mac_47_32[0x10];
2315
2316 u8 source_mac_31_0[0x20];
2317
b4ff3a36 2318 u8 reserved_at_c0[0x14];
e281682b
SM		 2319 u8 roce_l3_type[0x4];
2320 u8 roce_version[0x8];
2321
b4ff3a36 2322 u8 reserved_at_e0[0x20];
e281682b
SM		 2323};
2324
2325union mlx5_ifc_hca_cap_union_bits {
2326 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2327 struct mlx5_ifc_odp_cap_bits odp_cap;
2328 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2329 struct mlx5_ifc_roce_cap_bits roce_cap;
2330 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2331 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2332 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2333 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2334 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2335 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2336 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2337 u8 reserved_at_0[0x8000];
e281682b
SM		 2338};
2339
2340enum {
2341 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2342 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2343 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2344 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2345 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2346 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2347 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2348 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2349 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2350};
2351
2352struct mlx5_ifc_vlan_bits {
2353 u8 ethtype[0x10];
2354 u8 prio[0x3];
2355 u8 cfi[0x1];
2356 u8 vid[0xc];
e281682b
SM		 2357};
2358
2359struct mlx5_ifc_flow_context_bits {
0c06897a 2360 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2361
2362 u8 group_id[0x20];
2363
b4ff3a36 2364 u8 reserved_at_40[0x8];
e281682b
SM		 2365 u8 flow_tag[0x18];
2366
b4ff3a36 2367 u8 reserved_at_60[0x10];
e281682b
SM		 2368 u8 action[0x10];
2369
b4ff3a36 2370 u8 reserved_at_80[0x8];
e281682b
SM		 2371 u8 destination_list_size[0x18];
2372
9dc0b289
AV		 2373 u8 reserved_at_a0[0x8];
2374 u8 flow_counter_list_size[0x18];
2375
7adbde20
HHZ		 2376 u8 encap_id[0x20];
2377
2a69cb9f
OG		 2378 u8 modify_header_id[0x20];
2379
2380 u8 reserved_at_100[0x100];
e281682b
SM		 2381
2382 struct mlx5_ifc_fte_match_param_bits match_value;
2383
b4ff3a36 2384 u8 reserved_at_1200[0x600];
e281682b 2385
9dc0b289 2386 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2387};
2388
2389enum {
2390 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2391 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2392};
2393
2394struct mlx5_ifc_xrc_srqc_bits {
2395 u8 state[0x4];
2396 u8 log_xrc_srq_size[0x4];
b4ff3a36 2397 u8 reserved_at_8[0x18];
e281682b
SM		 2398
2399 u8 wq_signature[0x1];
2400 u8 cont_srq[0x1];
b4ff3a36 2401 u8 reserved_at_22[0x1];
e281682b
SM		 2402 u8 rlky[0x1];
2403 u8 basic_cyclic_rcv_wqe[0x1];
2404 u8 log_rq_stride[0x3];
2405 u8 xrcd[0x18];
2406
2407 u8 page_offset[0x6];
b4ff3a36 2408 u8 reserved_at_46[0x2];
e281682b
SM		 2409 u8 cqn[0x18];
2410
b4ff3a36 2411 u8 reserved_at_60[0x20];
e281682b
SM		 2412
2413 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2414 u8 reserved_at_81[0x1];
e281682b
SM		 2415 u8 log_page_size[0x6];
2416 u8 user_index[0x18];
2417
b4ff3a36 2418 u8 reserved_at_a0[0x20];
e281682b 2419
b4ff3a36 2420 u8 reserved_at_c0[0x8];
e281682b
SM		 2421 u8 pd[0x18];
2422
2423 u8 lwm[0x10];
2424 u8 wqe_cnt[0x10];
2425
b4ff3a36 2426 u8 reserved_at_100[0x40];
e281682b
SM		 2427
2428 u8 db_record_addr_h[0x20];
2429
2430 u8 db_record_addr_l[0x1e];
b4ff3a36 2431 u8 reserved_at_17e[0x2];
e281682b 2432
b4ff3a36 2433 u8 reserved_at_180[0x80];
e281682b
SM		 2434};
2435
61c5b5c9
MS		 2436struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2437 u8 counter_error_queues[0x20];
2438
2439 u8 total_error_queues[0x20];
2440
2441 u8 send_queue_priority_update_flow[0x20];
2442
2443 u8 reserved_at_60[0x20];
2444
2445 u8 nic_receive_steering_discard[0x40];
2446
2447 u8 receive_discard_vport_down[0x40];
2448
2449 u8 transmit_discard_vport_down[0x40];
2450
2451 u8 reserved_at_140[0xec0];
2452};
2453
e281682b
SM		 2454struct mlx5_ifc_traffic_counter_bits {
2455 u8 packets[0x40];
2456
2457 u8 octets[0x40];
2458};
2459
2460struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2461 u8 strict_lag_tx_port_affinity[0x1];
2462 u8 reserved_at_1[0x3];
2463 u8 lag_tx_port_affinity[0x04];
2464
2465 u8 reserved_at_8[0x4];
e281682b 2466 u8 prio[0x4];
b4ff3a36 2467 u8 reserved_at_10[0x10];
e281682b 2468
b4ff3a36 2469 u8 reserved_at_20[0x100];
e281682b 2470
b4ff3a36 2471 u8 reserved_at_120[0x8];
e281682b
SM		 2472 u8 transport_domain[0x18];
2473
500a3d0d
ES		 2474 u8 reserved_at_140[0x8];
2475 u8 underlay_qpn[0x18];
2476 u8 reserved_at_160[0x3a0];
e281682b
SM		 2477};
2478
2479enum {
2480 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2481 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2482};
2483
2484enum {
2485 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2486 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2487};
2488
2489enum {
2be6967c
SM		 2490 MLX5_RX_HASH_FN_NONE = 0x0,
2491 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2492 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2493};
2494
2495enum {
2496 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2497 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2498};
2499
2500struct mlx5_ifc_tirc_bits {
b4ff3a36 2501 u8 reserved_at_0[0x20];
e281682b
SM		 2502
2503 u8 disp_type[0x4];
b4ff3a36 2504 u8 reserved_at_24[0x1c];
e281682b 2505
b4ff3a36 2506 u8 reserved_at_40[0x40];
e281682b 2507
b4ff3a36 2508 u8 reserved_at_80[0x4];
e281682b
SM		 2509 u8 lro_timeout_period_usecs[0x10];
2510 u8 lro_enable_mask[0x4];
2511 u8 lro_max_ip_payload_size[0x8];
2512
b4ff3a36 2513 u8 reserved_at_a0[0x40];
e281682b 2514
b4ff3a36 2515 u8 reserved_at_e0[0x8];
e281682b
SM		 2516 u8 inline_rqn[0x18];
2517
2518 u8 rx_hash_symmetric[0x1];
b4ff3a36 2519 u8 reserved_at_101[0x1];
e281682b 2520 u8 tunneled_offload_en[0x1];
b4ff3a36 2521 u8 reserved_at_103[0x5];
e281682b
SM		 2522 u8 indirect_table[0x18];
2523
2524 u8 rx_hash_fn[0x4];
b4ff3a36 2525 u8 reserved_at_124[0x2];
e281682b
SM		 2526 u8 self_lb_block[0x2];
2527 u8 transport_domain[0x18];
2528
2529 u8 rx_hash_toeplitz_key[10][0x20];
2530
2531 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2532
2533 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2534
b4ff3a36 2535 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2536};
2537
2538enum {
2539 MLX5_SRQC_STATE_GOOD = 0x0,
2540 MLX5_SRQC_STATE_ERROR = 0x1,
2541};
2542
2543struct mlx5_ifc_srqc_bits {
2544 u8 state[0x4];
2545 u8 log_srq_size[0x4];
b4ff3a36 2546 u8 reserved_at_8[0x18];
e281682b
SM		 2547
2548 u8 wq_signature[0x1];
2549 u8 cont_srq[0x1];
b4ff3a36 2550 u8 reserved_at_22[0x1];
e281682b 2551 u8 rlky[0x1];
b4ff3a36 2552 u8 reserved_at_24[0x1];
e281682b
SM		 2553 u8 log_rq_stride[0x3];
2554 u8 xrcd[0x18];
2555
2556 u8 page_offset[0x6];
b4ff3a36 2557 u8 reserved_at_46[0x2];
e281682b
SM		 2558 u8 cqn[0x18];
2559
b4ff3a36 2560 u8 reserved_at_60[0x20];
e281682b 2561
b4ff3a36 2562 u8 reserved_at_80[0x2];
e281682b 2563 u8 log_page_size[0x6];
b4ff3a36 2564 u8 reserved_at_88[0x18];
e281682b 2565
b4ff3a36 2566 u8 reserved_at_a0[0x20];
e281682b 2567
b4ff3a36 2568 u8 reserved_at_c0[0x8];
e281682b
SM		 2569 u8 pd[0x18];
2570
2571 u8 lwm[0x10];
2572 u8 wqe_cnt[0x10];
2573
b4ff3a36 2574 u8 reserved_at_100[0x40];
e281682b 2575
01949d01 2576 u8 dbr_addr[0x40];
e281682b 2577
b4ff3a36 2578 u8 reserved_at_180[0x80];
e281682b
SM		 2579};
2580
2581enum {
2582 MLX5_SQC_STATE_RST = 0x0,
2583 MLX5_SQC_STATE_RDY = 0x1,
2584 MLX5_SQC_STATE_ERR = 0x3,
2585};
2586
2587struct mlx5_ifc_sqc_bits {
2588 u8 rlky[0x1];
2589 u8 cd_master[0x1];
2590 u8 fre[0x1];
2591 u8 flush_in_error_en[0x1];
795b609c 2592 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2593 u8 min_wqe_inline_mode[0x3];
e281682b 2594 u8 state[0x4];
7d5e1423 2595 u8 reg_umr[0x1];
547eede0 2596 u8 allow_swp[0x1];
40817cdb
OG		 2597 u8 hairpin[0x1];
2598 u8 reserved_at_f[0x11];
e281682b 2599
b4ff3a36 2600 u8 reserved_at_20[0x8];
e281682b
SM		 2601 u8 user_index[0x18];
2602
b4ff3a36 2603 u8 reserved_at_40[0x8];
e281682b
SM		 2604 u8 cqn[0x18];
2605
40817cdb
OG		 2606 u8 reserved_at_60[0x8];
2607 u8 hairpin_peer_rq[0x18];
2608
2609 u8 reserved_at_80[0x10];
2610 u8 hairpin_peer_vhca[0x10];
2611
2612 u8 reserved_at_a0[0x50];
e281682b 2613
7486216b 2614 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2615 u8 tis_lst_sz[0x10];
b4ff3a36 2616 u8 reserved_at_110[0x10];
e281682b 2617
b4ff3a36 2618 u8 reserved_at_120[0x40];
e281682b 2619
b4ff3a36 2620 u8 reserved_at_160[0x8];
e281682b
SM		 2621 u8 tis_num_0[0x18];
2622
2623 struct mlx5_ifc_wq_bits wq;
2624};
2625
813f8540
MHY		 2626enum {
2627 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2628 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2629 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2630 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2631};
2632
2633struct mlx5_ifc_scheduling_context_bits {
2634 u8 element_type[0x8];
2635 u8 reserved_at_8[0x18];
2636
2637 u8 element_attributes[0x20];
2638
2639 u8 parent_element_id[0x20];
2640
2641 u8 reserved_at_60[0x40];
2642
2643 u8 bw_share[0x20];
2644
2645 u8 max_average_bw[0x20];
2646
2647 u8 reserved_at_e0[0x120];
2648};
2649
e281682b 2650struct mlx5_ifc_rqtc_bits {
b4ff3a36 2651 u8 reserved_at_0[0xa0];
e281682b 2652
b4ff3a36 2653 u8 reserved_at_a0[0x10];
e281682b
SM		 2654 u8 rqt_max_size[0x10];
2655
b4ff3a36 2656 u8 reserved_at_c0[0x10];
e281682b
SM		 2657 u8 rqt_actual_size[0x10];
2658
b4ff3a36 2659 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2660
2661 struct mlx5_ifc_rq_num_bits rq_num[0];
2662};
2663
2664enum {
2665 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2666 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2667};
2668
2669enum {
2670 MLX5_RQC_STATE_RST = 0x0,
2671 MLX5_RQC_STATE_RDY = 0x1,
2672 MLX5_RQC_STATE_ERR = 0x3,
2673};
2674
2675struct mlx5_ifc_rqc_bits {
2676 u8 rlky[0x1];
03404e8a 2677 u8 delay_drop_en[0x1];
7d5e1423 2678 u8 scatter_fcs[0x1];
e281682b
SM		 2679 u8 vsd[0x1];
2680 u8 mem_rq_type[0x4];
2681 u8 state[0x4];
b4ff3a36 2682 u8 reserved_at_c[0x1];
e281682b 2683 u8 flush_in_error_en[0x1];
40817cdb
OG		 2684 u8 hairpin[0x1];
2685 u8 reserved_at_f[0x11];
e281682b 2686
b4ff3a36 2687 u8 reserved_at_20[0x8];
e281682b
SM		 2688 u8 user_index[0x18];
2689
b4ff3a36 2690 u8 reserved_at_40[0x8];
e281682b
SM		 2691 u8 cqn[0x18];
2692
2693 u8 counter_set_id[0x8];
b4ff3a36 2694 u8 reserved_at_68[0x18];
e281682b 2695
b4ff3a36 2696 u8 reserved_at_80[0x8];
e281682b
SM		 2697 u8 rmpn[0x18];
2698
40817cdb
OG		 2699 u8 reserved_at_a0[0x8];
2700 u8 hairpin_peer_sq[0x18];
2701
2702 u8 reserved_at_c0[0x10];
2703 u8 hairpin_peer_vhca[0x10];
2704
2705 u8 reserved_at_e0[0xa0];
e281682b
SM		 2706
2707 struct mlx5_ifc_wq_bits wq;
2708};
2709
2710enum {
2711 MLX5_RMPC_STATE_RDY = 0x1,
2712 MLX5_RMPC_STATE_ERR = 0x3,
2713};
2714
2715struct mlx5_ifc_rmpc_bits {
b4ff3a36 2716 u8 reserved_at_0[0x8];
e281682b 2717 u8 state[0x4];
b4ff3a36 2718 u8 reserved_at_c[0x14];
e281682b
SM		 2719
2720 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2721 u8 reserved_at_21[0x1f];
e281682b 2722
b4ff3a36 2723 u8 reserved_at_40[0x140];
e281682b
SM		 2724
2725 struct mlx5_ifc_wq_bits wq;
2726};
2727
e281682b 2728struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2729 u8 reserved_at_0[0x5];
2730 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2731 u8 reserved_at_8[0x15];
2732 u8 disable_mc_local_lb[0x1];
2733 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2734 u8 roce_en[0x1];
2735
d82b7318 2736 u8 arm_change_event[0x1];
b4ff3a36 2737 u8 reserved_at_21[0x1a];
d82b7318
SM		 2738 u8 event_on_mtu[0x1];
2739 u8 event_on_promisc_change[0x1];
2740 u8 event_on_vlan_change[0x1];
2741 u8 event_on_mc_address_change[0x1];
2742 u8 event_on_uc_address_change[0x1];
e281682b 2743
32f69e4b
DJ		 2744 u8 reserved_at_40[0xc];
2745
2746 u8 affiliation_criteria[0x4];
2747 u8 affiliated_vhca_id[0x10];
2748
2749 u8 reserved_at_60[0xd0];
d82b7318
SM		 2750
2751 u8 mtu[0x10];
2752
9efa7525
AS		 2753 u8 system_image_guid[0x40];
2754 u8 port_guid[0x40];
2755 u8 node_guid[0x40];
2756
b4ff3a36 2757 u8 reserved_at_200[0x140];
9efa7525 2758 u8 qkey_violation_counter[0x10];
b4ff3a36 2759 u8 reserved_at_350[0x430];
d82b7318
SM		 2760
2761 u8 promisc_uc[0x1];
2762 u8 promisc_mc[0x1];
2763 u8 promisc_all[0x1];
b4ff3a36 2764 u8 reserved_at_783[0x2];
e281682b 2765 u8 allowed_list_type[0x3];
b4ff3a36 2766 u8 reserved_at_788[0xc];
e281682b
SM		 2767 u8 allowed_list_size[0xc];
2768
2769 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2770
b4ff3a36 2771 u8 reserved_at_7e0[0x20];
e281682b
SM		 2772
2773 u8 current_uc_mac_address[0][0x40];
2774};
2775
2776enum {
2777 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2778 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2779 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2780 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
cdbd0d2b 2781 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 2782};
2783
2784struct mlx5_ifc_mkc_bits {
b4ff3a36 2785 u8 reserved_at_0[0x1];
e281682b 2786 u8 free[0x1];
cdbd0d2b
AL		 2787 u8 reserved_at_2[0x1];
2788 u8 access_mode_4_2[0x3];
2789 u8 reserved_at_6[0x7];
2790 u8 relaxed_ordering_write[0x1];
2791 u8 reserved_at_e[0x1];
e281682b
SM		 2792 u8 small_fence_on_rdma_read_response[0x1];
2793 u8 umr_en[0x1];
2794 u8 a[0x1];
2795 u8 rw[0x1];
2796 u8 rr[0x1];
2797 u8 lw[0x1];
2798 u8 lr[0x1];
cdbd0d2b 2799 u8 access_mode_1_0[0x2];
b4ff3a36 2800 u8 reserved_at_18[0x8];
e281682b
SM		 2801
2802 u8 qpn[0x18];
2803 u8 mkey_7_0[0x8];
2804
b4ff3a36 2805 u8 reserved_at_40[0x20];
e281682b
SM		 2806
2807 u8 length64[0x1];
2808 u8 bsf_en[0x1];
2809 u8 sync_umr[0x1];
b4ff3a36 2810 u8 reserved_at_63[0x2];
e281682b 2811 u8 expected_sigerr_count[0x1];
b4ff3a36 2812 u8 reserved_at_66[0x1];
e281682b
SM		 2813 u8 en_rinval[0x1];
2814 u8 pd[0x18];
2815
2816 u8 start_addr[0x40];
2817
2818 u8 len[0x40];
2819
2820 u8 bsf_octword_size[0x20];
2821
b4ff3a36 2822 u8 reserved_at_120[0x80];
e281682b
SM		 2823
2824 u8 translations_octword_size[0x20];
2825
b4ff3a36 2826 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2827 u8 log_page_size[0x5];
2828
b4ff3a36 2829 u8 reserved_at_1e0[0x20];
e281682b
SM		 2830};
2831
2832struct mlx5_ifc_pkey_bits {
b4ff3a36 2833 u8 reserved_at_0[0x10];
e281682b
SM		 2834 u8 pkey[0x10];
2835};
2836
2837struct mlx5_ifc_array128_auto_bits {
2838 u8 array128_auto[16][0x8];
2839};
2840
2841struct mlx5_ifc_hca_vport_context_bits {
2842 u8 field_select[0x20];
2843
b4ff3a36 2844 u8 reserved_at_20[0xe0];
e281682b
SM		 2845
2846 u8 sm_virt_aware[0x1];
2847 u8 has_smi[0x1];
2848 u8 has_raw[0x1];
2849 u8 grh_required[0x1];
b4ff3a36 2850 u8 reserved_at_104[0xc];
707c4602
MD		 2851 u8 port_physical_state[0x4];
2852 u8 vport_state_policy[0x4];
2853 u8 port_state[0x4];
e281682b
SM		 2854 u8 vport_state[0x4];
2855
b4ff3a36 2856 u8 reserved_at_120[0x20];
707c4602
MD		 2857
2858 u8 system_image_guid[0x40];
e281682b
SM		 2859
2860 u8 port_guid[0x40];
2861
2862 u8 node_guid[0x40];
2863
2864 u8 cap_mask1[0x20];
2865
2866 u8 cap_mask1_field_select[0x20];
2867
2868 u8 cap_mask2[0x20];
2869
2870 u8 cap_mask2_field_select[0x20];
2871
b4ff3a36 2872 u8 reserved_at_280[0x80];
e281682b
SM		 2873
2874 u8 lid[0x10];
b4ff3a36 2875 u8 reserved_at_310[0x4];
e281682b
SM		 2876 u8 init_type_reply[0x4];
2877 u8 lmc[0x3];
2878 u8 subnet_timeout[0x5];
2879
2880 u8 sm_lid[0x10];
2881 u8 sm_sl[0x4];
b4ff3a36 2882 u8 reserved_at_334[0xc];
e281682b
SM		 2883
2884 u8 qkey_violation_counter[0x10];
2885 u8 pkey_violation_counter[0x10];
2886
b4ff3a36 2887 u8 reserved_at_360[0xca0];
e281682b
SM		 2888};
2889
d6666753 2890struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2891 u8 reserved_at_0[0x3];
d6666753
SM		 2892 u8 vport_svlan_strip[0x1];
2893 u8 vport_cvlan_strip[0x1];
2894 u8 vport_svlan_insert[0x1];
2895 u8 vport_cvlan_insert[0x2];
b4ff3a36 2896 u8 reserved_at_8[0x18];
d6666753 2897
b4ff3a36 2898 u8 reserved_at_20[0x20];
d6666753
SM		 2899
2900 u8 svlan_cfi[0x1];
2901 u8 svlan_pcp[0x3];
2902 u8 svlan_id[0xc];
2903 u8 cvlan_cfi[0x1];
2904 u8 cvlan_pcp[0x3];
2905 u8 cvlan_id[0xc];
2906
b4ff3a36 2907 u8 reserved_at_60[0x7a0];
d6666753
SM		 2908};
2909
e281682b
SM		 2910enum {
2911 MLX5_EQC_STATUS_OK = 0x0,
2912 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2913};
2914
2915enum {
2916 MLX5_EQC_ST_ARMED = 0x9,
2917 MLX5_EQC_ST_FIRED = 0xa,
2918};
2919
2920struct mlx5_ifc_eqc_bits {
2921 u8 status[0x4];
b4ff3a36 2922 u8 reserved_at_4[0x9];
e281682b
SM		 2923 u8 ec[0x1];
2924 u8 oi[0x1];
b4ff3a36 2925 u8 reserved_at_f[0x5];
e281682b 2926 u8 st[0x4];
b4ff3a36 2927 u8 reserved_at_18[0x8];
e281682b 2928
b4ff3a36 2929 u8 reserved_at_20[0x20];
e281682b 2930
b4ff3a36 2931 u8 reserved_at_40[0x14];
e281682b 2932 u8 page_offset[0x6];
b4ff3a36 2933 u8 reserved_at_5a[0x6];
e281682b 2934
b4ff3a36 2935 u8 reserved_at_60[0x3];
e281682b
SM		 2936 u8 log_eq_size[0x5];
2937 u8 uar_page[0x18];
2938
b4ff3a36 2939 u8 reserved_at_80[0x20];
e281682b 2940
b4ff3a36 2941 u8 reserved_at_a0[0x18];
e281682b
SM		 2942 u8 intr[0x8];
2943
b4ff3a36 2944 u8 reserved_at_c0[0x3];
e281682b 2945 u8 log_page_size[0x5];
b4ff3a36 2946 u8 reserved_at_c8[0x18];
e281682b 2947
b4ff3a36 2948 u8 reserved_at_e0[0x60];
e281682b 2949
b4ff3a36 2950 u8 reserved_at_140[0x8];
e281682b
SM		 2951 u8 consumer_counter[0x18];
2952
b4ff3a36 2953 u8 reserved_at_160[0x8];
e281682b
SM		 2954 u8 producer_counter[0x18];
2955
b4ff3a36 2956 u8 reserved_at_180[0x80];
e281682b
SM		 2957};
2958
2959enum {
2960 MLX5_DCTC_STATE_ACTIVE = 0x0,
2961 MLX5_DCTC_STATE_DRAINING = 0x1,
2962 MLX5_DCTC_STATE_DRAINED = 0x2,
2963};
2964
2965enum {
2966 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2967 MLX5_DCTC_CS_RES_NA = 0x1,
2968 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2969};
2970
2971enum {
2972 MLX5_DCTC_MTU_256_BYTES = 0x1,
2973 MLX5_DCTC_MTU_512_BYTES = 0x2,
2974 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2975 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2976 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2977};
2978
2979struct mlx5_ifc_dctc_bits {
b4ff3a36 2980 u8 reserved_at_0[0x4];
e281682b 2981 u8 state[0x4];
b4ff3a36 2982 u8 reserved_at_8[0x18];
e281682b 2983
b4ff3a36 2984 u8 reserved_at_20[0x8];
e281682b
SM		 2985 u8 user_index[0x18];
2986
b4ff3a36 2987 u8 reserved_at_40[0x8];
e281682b
SM		 2988 u8 cqn[0x18];
2989
2990 u8 counter_set_id[0x8];
2991 u8 atomic_mode[0x4];
2992 u8 rre[0x1];
2993 u8 rwe[0x1];
2994 u8 rae[0x1];
2995 u8 atomic_like_write_en[0x1];
2996 u8 latency_sensitive[0x1];
2997 u8 rlky[0x1];
2998 u8 free_ar[0x1];
b4ff3a36 2999 u8 reserved_at_73[0xd];
e281682b 3000
b4ff3a36 3001 u8 reserved_at_80[0x8];
e281682b 3002 u8 cs_res[0x8];
b4ff3a36 3003 u8 reserved_at_90[0x3];
e281682b 3004 u8 min_rnr_nak[0x5];
b4ff3a36 3005 u8 reserved_at_98[0x8];
e281682b 3006
b4ff3a36 3007 u8 reserved_at_a0[0x8];
7486216b 3008 u8 srqn_xrqn[0x18];
e281682b 3009
b4ff3a36 3010 u8 reserved_at_c0[0x8];
e281682b
SM		 3011 u8 pd[0x18];
3012
3013 u8 tclass[0x8];
b4ff3a36 3014 u8 reserved_at_e8[0x4];
e281682b
SM		 3015 u8 flow_label[0x14];
3016
3017 u8 dc_access_key[0x40];
3018
b4ff3a36 3019 u8 reserved_at_140[0x5];
e281682b
SM		 3020 u8 mtu[0x3];
3021 u8 port[0x8];
3022 u8 pkey_index[0x10];
3023
b4ff3a36 3024 u8 reserved_at_160[0x8];
e281682b 3025 u8 my_addr_index[0x8];
b4ff3a36 3026 u8 reserved_at_170[0x8];
e281682b
SM		 3027 u8 hop_limit[0x8];
3028
3029 u8 dc_access_key_violation_count[0x20];
3030
b4ff3a36 3031 u8 reserved_at_1a0[0x14];
e281682b
SM		 3032 u8 dei_cfi[0x1];
3033 u8 eth_prio[0x3];
3034 u8 ecn[0x2];
3035 u8 dscp[0x6];
3036
b4ff3a36 3037 u8 reserved_at_1c0[0x40];
e281682b
SM		 3038};
3039
3040enum {
3041 MLX5_CQC_STATUS_OK = 0x0,
3042 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3043 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3044};
3045
3046enum {
3047 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3048 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3049};
3050
3051enum {
3052 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3053 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3054 MLX5_CQC_ST_FIRED = 0xa,
3055};
3056
7d5e1423
SM		 3057enum {
3058 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3059 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3060 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3061};
3062
e281682b
SM		 3063struct mlx5_ifc_cqc_bits {
3064 u8 status[0x4];
b4ff3a36 3065 u8 reserved_at_4[0x4];
e281682b
SM		 3066 u8 cqe_sz[0x3];
3067 u8 cc[0x1];
b4ff3a36 3068 u8 reserved_at_c[0x1];
e281682b
SM		 3069 u8 scqe_break_moderation_en[0x1];
3070 u8 oi[0x1];
7d5e1423
SM		 3071 u8 cq_period_mode[0x2];
3072 u8 cqe_comp_en[0x1];
e281682b
SM		 3073 u8 mini_cqe_res_format[0x2];
3074 u8 st[0x4];
b4ff3a36 3075 u8 reserved_at_18[0x8];
e281682b 3076
b4ff3a36 3077 u8 reserved_at_20[0x20];
e281682b 3078
b4ff3a36 3079 u8 reserved_at_40[0x14];
e281682b 3080 u8 page_offset[0x6];
b4ff3a36 3081 u8 reserved_at_5a[0x6];
e281682b 3082
b4ff3a36 3083 u8 reserved_at_60[0x3];
e281682b
SM		 3084 u8 log_cq_size[0x5];
3085 u8 uar_page[0x18];
3086
b4ff3a36 3087 u8 reserved_at_80[0x4];
e281682b
SM		 3088 u8 cq_period[0xc];
3089 u8 cq_max_count[0x10];
3090
b4ff3a36 3091 u8 reserved_at_a0[0x18];
e281682b
SM		 3092 u8 c_eqn[0x8];
3093
b4ff3a36 3094 u8 reserved_at_c0[0x3];
e281682b 3095 u8 log_page_size[0x5];
b4ff3a36 3096 u8 reserved_at_c8[0x18];
e281682b 3097
b4ff3a36 3098 u8 reserved_at_e0[0x20];
e281682b 3099
b4ff3a36 3100 u8 reserved_at_100[0x8];
e281682b
SM		 3101 u8 last_notified_index[0x18];
3102
b4ff3a36 3103 u8 reserved_at_120[0x8];
e281682b
SM		 3104 u8 last_solicit_index[0x18];
3105
b4ff3a36 3106 u8 reserved_at_140[0x8];
e281682b
SM		 3107 u8 consumer_counter[0x18];
3108
b4ff3a36 3109 u8 reserved_at_160[0x8];
e281682b
SM		 3110 u8 producer_counter[0x18];
3111
b4ff3a36 3112 u8 reserved_at_180[0x40];
e281682b
SM		 3113
3114 u8 dbr_addr[0x40];
3115};
3116
3117union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3118 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3119 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3120 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3121 u8 reserved_at_0[0x800];
e281682b
SM		 3122};
3123
3124struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3125 u8 reserved_at_0[0xc0];
e281682b 3126
b4ff3a36 3127 u8 reserved_at_c0[0x8];
211e6c80
MD		 3128 u8 ieee_vendor_id[0x18];
3129
b4ff3a36 3130 u8 reserved_at_e0[0x10];
e281682b
SM		 3131 u8 vsd_vendor_id[0x10];
3132
3133 u8 vsd[208][0x8];
3134
3135 u8 vsd_contd_psid[16][0x8];
3136};
3137
7486216b
SM		 3138enum {
3139 MLX5_XRQC_STATE_GOOD = 0x0,
3140 MLX5_XRQC_STATE_ERROR = 0x1,
3141};
3142
3143enum {
3144 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3145 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3146};
3147
3148enum {
3149 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3150};
3151
3152struct mlx5_ifc_tag_matching_topology_context_bits {
3153 u8 log_matching_list_sz[0x4];
3154 u8 reserved_at_4[0xc];
3155 u8 append_next_index[0x10];
3156
3157 u8 sw_phase_cnt[0x10];
3158 u8 hw_phase_cnt[0x10];
3159
3160 u8 reserved_at_40[0x40];
3161};
3162
3163struct mlx5_ifc_xrqc_bits {
3164 u8 state[0x4];
3165 u8 rlkey[0x1];
3166 u8 reserved_at_5[0xf];
3167 u8 topology[0x4];
3168 u8 reserved_at_18[0x4];
3169 u8 offload[0x4];
3170
3171 u8 reserved_at_20[0x8];
3172 u8 user_index[0x18];
3173
3174 u8 reserved_at_40[0x8];
3175 u8 cqn[0x18];
3176
3177 u8 reserved_at_60[0xa0];
3178
3179 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3180
6e44636a 3181 u8 reserved_at_180[0x280];
7486216b
SM		 3182
3183 struct mlx5_ifc_wq_bits wq;
3184};
3185
e281682b
SM		 3186union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3187 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3188 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3189 u8 reserved_at_0[0x20];
e281682b
SM		 3190};
3191
3192union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3193 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3194 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3195 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3196 u8 reserved_at_0[0x20];
e281682b
SM		 3197};
3198
3199union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3200 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3201 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3202 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3203 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3204 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3205 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3206 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3207 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3208 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3209 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3210 u8 reserved_at_0[0x7c0];
e281682b
SM		 3211};
3212
8ed1a630
GP		 3213union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3214 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3215 u8 reserved_at_0[0x7c0];
3216};
3217
e281682b
SM		 3218union mlx5_ifc_event_auto_bits {
3219 struct mlx5_ifc_comp_event_bits comp_event;
3220 struct mlx5_ifc_dct_events_bits dct_events;
3221 struct mlx5_ifc_qp_events_bits qp_events;
3222 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3223 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3224 struct mlx5_ifc_cq_error_bits cq_error;
3225 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3226 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3227 struct mlx5_ifc_gpio_event_bits gpio_event;
3228 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3229 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3230 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3231 u8 reserved_at_0[0xe0];
e281682b
SM		 3232};
3233
3234struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3235 u8 reserved_at_0[0x100];
e281682b
SM		 3236
3237 u8 assert_existptr[0x20];
3238
3239 u8 assert_callra[0x20];
3240
b4ff3a36 3241 u8 reserved_at_140[0x40];
e281682b
SM		 3242
3243 u8 fw_version[0x20];
3244
3245 u8 hw_id[0x20];
3246
b4ff3a36 3247 u8 reserved_at_1c0[0x20];
e281682b
SM		 3248
3249 u8 irisc_index[0x8];
3250 u8 synd[0x8];
3251 u8 ext_synd[0x10];
3252};
3253
3254struct mlx5_ifc_register_loopback_control_bits {
3255 u8 no_lb[0x1];
b4ff3a36 3256 u8 reserved_at_1[0x7];
e281682b 3257 u8 port[0x8];
b4ff3a36 3258 u8 reserved_at_10[0x10];
e281682b 3259
b4ff3a36 3260 u8 reserved_at_20[0x60];
e281682b
SM		 3261};
3262
813f8540
MHY		 3263struct mlx5_ifc_vport_tc_element_bits {
3264 u8 traffic_class[0x4];
3265 u8 reserved_at_4[0xc];
3266 u8 vport_number[0x10];
3267};
3268
3269struct mlx5_ifc_vport_element_bits {
3270 u8 reserved_at_0[0x10];
3271 u8 vport_number[0x10];
3272};
3273
3274enum {
3275 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3276 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3277 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3278};
3279
3280struct mlx5_ifc_tsar_element_bits {
3281 u8 reserved_at_0[0x8];
3282 u8 tsar_type[0x8];
3283 u8 reserved_at_10[0x10];
3284};
3285
8812c24d
MD		 3286enum {
3287 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3288 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3289};
3290
e281682b
SM		 3291struct mlx5_ifc_teardown_hca_out_bits {
3292 u8 status[0x8];
b4ff3a36 3293 u8 reserved_at_8[0x18];
e281682b
SM		 3294
3295 u8 syndrome[0x20];
3296
8812c24d
MD		 3297 u8 reserved_at_40[0x3f];
3298
3299 u8 force_state[0x1];
e281682b
SM		 3300};
3301
3302enum {
3303 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3304 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3305};
3306
3307struct mlx5_ifc_teardown_hca_in_bits {
3308 u8 opcode[0x10];
b4ff3a36 3309 u8 reserved_at_10[0x10];
e281682b 3310
b4ff3a36 3311 u8 reserved_at_20[0x10];
e281682b
SM		 3312 u8 op_mod[0x10];
3313
b4ff3a36 3314 u8 reserved_at_40[0x10];
e281682b
SM		 3315 u8 profile[0x10];
3316
b4ff3a36 3317 u8 reserved_at_60[0x20];
e281682b
SM		 3318};
3319
3320struct mlx5_ifc_sqerr2rts_qp_out_bits {
3321 u8 status[0x8];
b4ff3a36 3322 u8 reserved_at_8[0x18];
e281682b
SM		 3323
3324 u8 syndrome[0x20];
3325
b4ff3a36 3326 u8 reserved_at_40[0x40];
e281682b
SM		 3327};
3328
3329struct mlx5_ifc_sqerr2rts_qp_in_bits {
3330 u8 opcode[0x10];
b4ff3a36 3331 u8 reserved_at_10[0x10];
e281682b 3332
b4ff3a36 3333 u8 reserved_at_20[0x10];
e281682b
SM		 3334 u8 op_mod[0x10];
3335
b4ff3a36 3336 u8 reserved_at_40[0x8];
e281682b
SM		 3337 u8 qpn[0x18];
3338
b4ff3a36 3339 u8 reserved_at_60[0x20];
e281682b
SM		 3340
3341 u8 opt_param_mask[0x20];
3342
b4ff3a36 3343 u8 reserved_at_a0[0x20];
e281682b
SM		 3344
3345 struct mlx5_ifc_qpc_bits qpc;
3346
b4ff3a36 3347 u8 reserved_at_800[0x80];
e281682b
SM		 3348};
3349
3350struct mlx5_ifc_sqd2rts_qp_out_bits {
3351 u8 status[0x8];
b4ff3a36 3352 u8 reserved_at_8[0x18];
e281682b
SM		 3353
3354 u8 syndrome[0x20];
3355
b4ff3a36 3356 u8 reserved_at_40[0x40];
e281682b
SM		 3357};
3358
3359struct mlx5_ifc_sqd2rts_qp_in_bits {
3360 u8 opcode[0x10];
b4ff3a36 3361 u8 reserved_at_10[0x10];
e281682b 3362
b4ff3a36 3363 u8 reserved_at_20[0x10];
e281682b
SM		 3364 u8 op_mod[0x10];
3365
b4ff3a36 3366 u8 reserved_at_40[0x8];
e281682b
SM		 3367 u8 qpn[0x18];
3368
b4ff3a36 3369 u8 reserved_at_60[0x20];
e281682b
SM		 3370
3371 u8 opt_param_mask[0x20];
3372
b4ff3a36 3373 u8 reserved_at_a0[0x20];
e281682b
SM		 3374
3375 struct mlx5_ifc_qpc_bits qpc;
3376
b4ff3a36 3377 u8 reserved_at_800[0x80];
e281682b
SM		 3378};
3379
3380struct mlx5_ifc_set_roce_address_out_bits {
3381 u8 status[0x8];
b4ff3a36 3382 u8 reserved_at_8[0x18];
e281682b
SM		 3383
3384 u8 syndrome[0x20];
3385
b4ff3a36 3386 u8 reserved_at_40[0x40];
e281682b
SM		 3387};
3388
3389struct mlx5_ifc_set_roce_address_in_bits {
3390 u8 opcode[0x10];
b4ff3a36 3391 u8 reserved_at_10[0x10];
e281682b 3392
b4ff3a36 3393 u8 reserved_at_20[0x10];
e281682b
SM		 3394 u8 op_mod[0x10];
3395
3396 u8 roce_address_index[0x10];
32f69e4b
DJ		 3397 u8 reserved_at_50[0xc];
3398 u8 vhca_port_num[0x4];
e281682b 3399
b4ff3a36 3400 u8 reserved_at_60[0x20];
e281682b
SM		 3401
3402 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3403};
3404
3405struct mlx5_ifc_set_mad_demux_out_bits {
3406 u8 status[0x8];
b4ff3a36 3407 u8 reserved_at_8[0x18];
e281682b
SM		 3408
3409 u8 syndrome[0x20];
3410
b4ff3a36 3411 u8 reserved_at_40[0x40];
e281682b
SM		 3412};
3413
3414enum {
3415 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3416 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3417};
3418
3419struct mlx5_ifc_set_mad_demux_in_bits {
3420 u8 opcode[0x10];
b4ff3a36 3421 u8 reserved_at_10[0x10];
e281682b 3422
b4ff3a36 3423 u8 reserved_at_20[0x10];
e281682b
SM		 3424 u8 op_mod[0x10];
3425
b4ff3a36 3426 u8 reserved_at_40[0x20];
e281682b 3427
b4ff3a36 3428 u8 reserved_at_60[0x6];
e281682b 3429 u8 demux_mode[0x2];
b4ff3a36 3430 u8 reserved_at_68[0x18];
e281682b
SM		 3431};
3432
3433struct mlx5_ifc_set_l2_table_entry_out_bits {
3434 u8 status[0x8];
b4ff3a36 3435 u8 reserved_at_8[0x18];
e281682b
SM		 3436
3437 u8 syndrome[0x20];
3438
b4ff3a36 3439 u8 reserved_at_40[0x40];
e281682b
SM		 3440};
3441
3442struct mlx5_ifc_set_l2_table_entry_in_bits {
3443 u8 opcode[0x10];
b4ff3a36 3444 u8 reserved_at_10[0x10];
e281682b 3445
b4ff3a36 3446 u8 reserved_at_20[0x10];
e281682b
SM		 3447 u8 op_mod[0x10];
3448
b4ff3a36 3449 u8 reserved_at_40[0x60];
e281682b 3450
b4ff3a36 3451 u8 reserved_at_a0[0x8];
e281682b
SM		 3452 u8 table_index[0x18];
3453
b4ff3a36 3454 u8 reserved_at_c0[0x20];
e281682b 3455
b4ff3a36 3456 u8 reserved_at_e0[0x13];
e281682b
SM		 3457 u8 vlan_valid[0x1];
3458 u8 vlan[0xc];
3459
3460 struct mlx5_ifc_mac_address_layout_bits mac_address;
3461
b4ff3a36 3462 u8 reserved_at_140[0xc0];
e281682b
SM		 3463};
3464
3465struct mlx5_ifc_set_issi_out_bits {
3466 u8 status[0x8];
b4ff3a36 3467 u8 reserved_at_8[0x18];
e281682b
SM		 3468
3469 u8 syndrome[0x20];
3470
b4ff3a36 3471 u8 reserved_at_40[0x40];
e281682b
SM		 3472};
3473
3474struct mlx5_ifc_set_issi_in_bits {
3475 u8 opcode[0x10];
b4ff3a36 3476 u8 reserved_at_10[0x10];
e281682b 3477
b4ff3a36 3478 u8 reserved_at_20[0x10];
e281682b
SM		 3479 u8 op_mod[0x10];
3480
b4ff3a36 3481 u8 reserved_at_40[0x10];
e281682b
SM		 3482 u8 current_issi[0x10];
3483
b4ff3a36 3484 u8 reserved_at_60[0x20];
e281682b
SM		 3485};
3486
3487struct mlx5_ifc_set_hca_cap_out_bits {
3488 u8 status[0x8];
b4ff3a36 3489 u8 reserved_at_8[0x18];
e281682b
SM		 3490
3491 u8 syndrome[0x20];
3492
b4ff3a36 3493 u8 reserved_at_40[0x40];
e281682b
SM		 3494};
3495
3496struct mlx5_ifc_set_hca_cap_in_bits {
3497 u8 opcode[0x10];
b4ff3a36 3498 u8 reserved_at_10[0x10];
e281682b 3499
b4ff3a36 3500 u8 reserved_at_20[0x10];
e281682b
SM		 3501 u8 op_mod[0x10];
3502
b4ff3a36 3503 u8 reserved_at_40[0x40];
e281682b
SM		 3504
3505 union mlx5_ifc_hca_cap_union_bits capability;
3506};
3507
26a81453
MG		 3508enum {
3509 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3510 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3511 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3512 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3513};
3514
e281682b
SM		 3515struct mlx5_ifc_set_fte_out_bits {
3516 u8 status[0x8];
b4ff3a36 3517 u8 reserved_at_8[0x18];
e281682b
SM		 3518
3519 u8 syndrome[0x20];
3520
b4ff3a36 3521 u8 reserved_at_40[0x40];
e281682b
SM		 3522};
3523
3524struct mlx5_ifc_set_fte_in_bits {
3525 u8 opcode[0x10];
b4ff3a36 3526 u8 reserved_at_10[0x10];
e281682b 3527
b4ff3a36 3528 u8 reserved_at_20[0x10];
e281682b
SM		 3529 u8 op_mod[0x10];
3530
7d5e1423
SM		 3531 u8 other_vport[0x1];
3532 u8 reserved_at_41[0xf];
3533 u8 vport_number[0x10];
3534
3535 u8 reserved_at_60[0x20];
e281682b
SM		 3536
3537 u8 table_type[0x8];
b4ff3a36 3538 u8 reserved_at_88[0x18];
e281682b 3539
b4ff3a36 3540 u8 reserved_at_a0[0x8];
e281682b
SM		 3541 u8 table_id[0x18];
3542
b4ff3a36 3543 u8 reserved_at_c0[0x18];
26a81453
MG		 3544 u8 modify_enable_mask[0x8];
3545
b4ff3a36 3546 u8 reserved_at_e0[0x20];
e281682b
SM		 3547
3548 u8 flow_index[0x20];
3549
b4ff3a36 3550 u8 reserved_at_120[0xe0];
e281682b
SM		 3551
3552 struct mlx5_ifc_flow_context_bits flow_context;
3553};
3554
3555struct mlx5_ifc_rts2rts_qp_out_bits {
3556 u8 status[0x8];
b4ff3a36 3557 u8 reserved_at_8[0x18];
e281682b
SM		 3558
3559 u8 syndrome[0x20];
3560
b4ff3a36 3561 u8 reserved_at_40[0x40];
e281682b
SM		 3562};
3563
3564struct mlx5_ifc_rts2rts_qp_in_bits {
3565 u8 opcode[0x10];
b4ff3a36 3566 u8 reserved_at_10[0x10];
e281682b 3567
b4ff3a36 3568 u8 reserved_at_20[0x10];
e281682b
SM		 3569 u8 op_mod[0x10];
3570
b4ff3a36 3571 u8 reserved_at_40[0x8];
e281682b
SM		 3572 u8 qpn[0x18];
3573
b4ff3a36 3574 u8 reserved_at_60[0x20];
e281682b
SM		 3575
3576 u8 opt_param_mask[0x20];
3577
b4ff3a36 3578 u8 reserved_at_a0[0x20];
e281682b
SM		 3579
3580 struct mlx5_ifc_qpc_bits qpc;
3581
b4ff3a36 3582 u8 reserved_at_800[0x80];
e281682b
SM		 3583};
3584
3585struct mlx5_ifc_rtr2rts_qp_out_bits {
3586 u8 status[0x8];
b4ff3a36 3587 u8 reserved_at_8[0x18];
e281682b
SM		 3588
3589 u8 syndrome[0x20];
3590
b4ff3a36 3591 u8 reserved_at_40[0x40];
e281682b
SM		 3592};
3593
3594struct mlx5_ifc_rtr2rts_qp_in_bits {
3595 u8 opcode[0x10];
b4ff3a36 3596 u8 reserved_at_10[0x10];
e281682b 3597
b4ff3a36 3598 u8 reserved_at_20[0x10];
e281682b
SM		 3599 u8 op_mod[0x10];
3600
b4ff3a36 3601 u8 reserved_at_40[0x8];
e281682b
SM		 3602 u8 qpn[0x18];
3603
b4ff3a36 3604 u8 reserved_at_60[0x20];
e281682b
SM		 3605
3606 u8 opt_param_mask[0x20];
3607
b4ff3a36 3608 u8 reserved_at_a0[0x20];
e281682b
SM		 3609
3610 struct mlx5_ifc_qpc_bits qpc;
3611
b4ff3a36 3612 u8 reserved_at_800[0x80];
e281682b
SM		 3613};
3614
3615struct mlx5_ifc_rst2init_qp_out_bits {
3616 u8 status[0x8];
b4ff3a36 3617 u8 reserved_at_8[0x18];
e281682b
SM		 3618
3619 u8 syndrome[0x20];
3620
b4ff3a36 3621 u8 reserved_at_40[0x40];
e281682b
SM		 3622};
3623
3624struct mlx5_ifc_rst2init_qp_in_bits {
3625 u8 opcode[0x10];
b4ff3a36 3626 u8 reserved_at_10[0x10];
e281682b 3627
b4ff3a36 3628 u8 reserved_at_20[0x10];
e281682b
SM		 3629 u8 op_mod[0x10];
3630
b4ff3a36 3631 u8 reserved_at_40[0x8];
e281682b
SM		 3632 u8 qpn[0x18];
3633
b4ff3a36 3634 u8 reserved_at_60[0x20];
e281682b
SM		 3635
3636 u8 opt_param_mask[0x20];
3637
b4ff3a36 3638 u8 reserved_at_a0[0x20];
e281682b
SM		 3639
3640 struct mlx5_ifc_qpc_bits qpc;
3641
b4ff3a36 3642 u8 reserved_at_800[0x80];
e281682b
SM		 3643};
3644
7486216b
SM		 3645struct mlx5_ifc_query_xrq_out_bits {
3646 u8 status[0x8];
3647 u8 reserved_at_8[0x18];
3648
3649 u8 syndrome[0x20];
3650
3651 u8 reserved_at_40[0x40];
3652
3653 struct mlx5_ifc_xrqc_bits xrq_context;
3654};
3655
3656struct mlx5_ifc_query_xrq_in_bits {
3657 u8 opcode[0x10];
3658 u8 reserved_at_10[0x10];
3659
3660 u8 reserved_at_20[0x10];
3661 u8 op_mod[0x10];
3662
3663 u8 reserved_at_40[0x8];
3664 u8 xrqn[0x18];
3665
3666 u8 reserved_at_60[0x20];
3667};
3668
e281682b
SM		 3669struct mlx5_ifc_query_xrc_srq_out_bits {
3670 u8 status[0x8];
b4ff3a36 3671 u8 reserved_at_8[0x18];
e281682b
SM		 3672
3673 u8 syndrome[0x20];
3674
b4ff3a36 3675 u8 reserved_at_40[0x40];
e281682b
SM		 3676
3677 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3678
b4ff3a36 3679 u8 reserved_at_280[0x600];
e281682b
SM		 3680
3681 u8 pas[0][0x40];
3682};
3683
3684struct mlx5_ifc_query_xrc_srq_in_bits {
3685 u8 opcode[0x10];
b4ff3a36 3686 u8 reserved_at_10[0x10];
e281682b 3687
b4ff3a36 3688 u8 reserved_at_20[0x10];
e281682b
SM		 3689 u8 op_mod[0x10];
3690
b4ff3a36 3691 u8 reserved_at_40[0x8];
e281682b
SM		 3692 u8 xrc_srqn[0x18];
3693
b4ff3a36 3694 u8 reserved_at_60[0x20];
e281682b
SM		 3695};
3696
3697enum {
3698 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3699 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3700};
3701
3702struct mlx5_ifc_query_vport_state_out_bits {
3703 u8 status[0x8];
b4ff3a36 3704 u8 reserved_at_8[0x18];
e281682b
SM		 3705
3706 u8 syndrome[0x20];
3707
b4ff3a36 3708 u8 reserved_at_40[0x20];
e281682b 3709
b4ff3a36 3710 u8 reserved_at_60[0x18];
e281682b
SM		 3711 u8 admin_state[0x4];
3712 u8 state[0x4];
3713};
3714
3715enum {
3716 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3717 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3718};
3719
3720struct mlx5_ifc_query_vport_state_in_bits {
3721 u8 opcode[0x10];
b4ff3a36 3722 u8 reserved_at_10[0x10];
e281682b 3723
b4ff3a36 3724 u8 reserved_at_20[0x10];
e281682b
SM		 3725 u8 op_mod[0x10];
3726
3727 u8 other_vport[0x1];
b4ff3a36 3728 u8 reserved_at_41[0xf];
e281682b
SM		 3729 u8 vport_number[0x10];
3730
b4ff3a36 3731 u8 reserved_at_60[0x20];
e281682b
SM		 3732};
3733
61c5b5c9
MS		 3734struct mlx5_ifc_query_vnic_env_out_bits {
3735 u8 status[0x8];
3736 u8 reserved_at_8[0x18];
3737
3738 u8 syndrome[0x20];
3739
3740 u8 reserved_at_40[0x40];
3741
3742 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3743};
3744
3745enum {
3746 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3747};
3748
3749struct mlx5_ifc_query_vnic_env_in_bits {
3750 u8 opcode[0x10];
3751 u8 reserved_at_10[0x10];
3752
3753 u8 reserved_at_20[0x10];
3754 u8 op_mod[0x10];
3755
3756 u8 other_vport[0x1];
3757 u8 reserved_at_41[0xf];
3758 u8 vport_number[0x10];
3759
3760 u8 reserved_at_60[0x20];
3761};
3762
e281682b
SM		 3763struct mlx5_ifc_query_vport_counter_out_bits {
3764 u8 status[0x8];
b4ff3a36 3765 u8 reserved_at_8[0x18];
e281682b
SM		 3766
3767 u8 syndrome[0x20];
3768
b4ff3a36 3769 u8 reserved_at_40[0x40];
e281682b
SM		 3770
3771 struct mlx5_ifc_traffic_counter_bits received_errors;
3772
3773 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3774
3775 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3776
3777 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3778
3779 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3780
3781 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3782
3783 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3784
3785 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3786
3787 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3788
3789 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3790
3791 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3792
3793 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3794
b4ff3a36 3795 u8 reserved_at_680[0xa00];
e281682b
SM		 3796};
3797
3798enum {
3799 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3800};
3801
3802struct mlx5_ifc_query_vport_counter_in_bits {
3803 u8 opcode[0x10];
b4ff3a36 3804 u8 reserved_at_10[0x10];
e281682b 3805
b4ff3a36 3806 u8 reserved_at_20[0x10];
e281682b
SM		 3807 u8 op_mod[0x10];
3808
3809 u8 other_vport[0x1];
b54ba277
MY		 3810 u8 reserved_at_41[0xb];
3811 u8 port_num[0x4];
e281682b
SM		 3812 u8 vport_number[0x10];
3813
b4ff3a36 3814 u8 reserved_at_60[0x60];
e281682b
SM		 3815
3816 u8 clear[0x1];
b4ff3a36 3817 u8 reserved_at_c1[0x1f];
e281682b 3818
b4ff3a36 3819 u8 reserved_at_e0[0x20];
e281682b
SM		 3820};
3821
3822struct mlx5_ifc_query_tis_out_bits {
3823 u8 status[0x8];
b4ff3a36 3824 u8 reserved_at_8[0x18];
e281682b
SM		 3825
3826 u8 syndrome[0x20];
3827
b4ff3a36 3828 u8 reserved_at_40[0x40];
e281682b
SM		 3829
3830 struct mlx5_ifc_tisc_bits tis_context;
3831};
3832
3833struct mlx5_ifc_query_tis_in_bits {
3834 u8 opcode[0x10];
b4ff3a36 3835 u8 reserved_at_10[0x10];
e281682b 3836
b4ff3a36 3837 u8 reserved_at_20[0x10];
e281682b
SM		 3838 u8 op_mod[0x10];
3839
b4ff3a36 3840 u8 reserved_at_40[0x8];
e281682b
SM		 3841 u8 tisn[0x18];
3842
b4ff3a36 3843 u8 reserved_at_60[0x20];
e281682b
SM		 3844};
3845
3846struct mlx5_ifc_query_tir_out_bits {
3847 u8 status[0x8];
b4ff3a36 3848 u8 reserved_at_8[0x18];
e281682b
SM		 3849
3850 u8 syndrome[0x20];
3851
b4ff3a36 3852 u8 reserved_at_40[0xc0];
e281682b
SM		 3853
3854 struct mlx5_ifc_tirc_bits tir_context;
3855};
3856
3857struct mlx5_ifc_query_tir_in_bits {
3858 u8 opcode[0x10];
b4ff3a36 3859 u8 reserved_at_10[0x10];
e281682b 3860
b4ff3a36 3861 u8 reserved_at_20[0x10];
e281682b
SM		 3862 u8 op_mod[0x10];
3863
b4ff3a36 3864 u8 reserved_at_40[0x8];
e281682b
SM		 3865 u8 tirn[0x18];
3866
b4ff3a36 3867 u8 reserved_at_60[0x20];
e281682b
SM		 3868};
3869
3870struct mlx5_ifc_query_srq_out_bits {
3871 u8 status[0x8];
b4ff3a36 3872 u8 reserved_at_8[0x18];
e281682b
SM		 3873
3874 u8 syndrome[0x20];
3875
b4ff3a36 3876 u8 reserved_at_40[0x40];
e281682b
SM		 3877
3878 struct mlx5_ifc_srqc_bits srq_context_entry;
3879
b4ff3a36 3880 u8 reserved_at_280[0x600];
e281682b
SM		 3881
3882 u8 pas[0][0x40];
3883};
3884
3885struct mlx5_ifc_query_srq_in_bits {
3886 u8 opcode[0x10];
b4ff3a36 3887 u8 reserved_at_10[0x10];
e281682b 3888
b4ff3a36 3889 u8 reserved_at_20[0x10];
e281682b
SM		 3890 u8 op_mod[0x10];
3891
b4ff3a36 3892 u8 reserved_at_40[0x8];
e281682b
SM		 3893 u8 srqn[0x18];
3894
b4ff3a36 3895 u8 reserved_at_60[0x20];
e281682b
SM		 3896};
3897
3898struct mlx5_ifc_query_sq_out_bits {
3899 u8 status[0x8];
b4ff3a36 3900 u8 reserved_at_8[0x18];
e281682b
SM		 3901
3902 u8 syndrome[0x20];
3903
b4ff3a36 3904 u8 reserved_at_40[0xc0];
e281682b
SM		 3905
3906 struct mlx5_ifc_sqc_bits sq_context;
3907};
3908
3909struct mlx5_ifc_query_sq_in_bits {
3910 u8 opcode[0x10];
b4ff3a36 3911 u8 reserved_at_10[0x10];
e281682b 3912
b4ff3a36 3913 u8 reserved_at_20[0x10];
e281682b
SM		 3914 u8 op_mod[0x10];
3915
b4ff3a36 3916 u8 reserved_at_40[0x8];
e281682b
SM		 3917 u8 sqn[0x18];
3918
b4ff3a36 3919 u8 reserved_at_60[0x20];
e281682b
SM		 3920};
3921
3922struct mlx5_ifc_query_special_contexts_out_bits {
3923 u8 status[0x8];
b4ff3a36 3924 u8 reserved_at_8[0x18];
e281682b
SM		 3925
3926 u8 syndrome[0x20];
3927
ec22eb53 3928 u8 dump_fill_mkey[0x20];
e281682b
SM		 3929
3930 u8 resd_lkey[0x20];
bcda1aca
AK		 3931
3932 u8 null_mkey[0x20];
3933
3934 u8 reserved_at_a0[0x60];
e281682b
SM		 3935};
3936
3937struct mlx5_ifc_query_special_contexts_in_bits {
3938 u8 opcode[0x10];
b4ff3a36 3939 u8 reserved_at_10[0x10];
e281682b 3940
b4ff3a36 3941 u8 reserved_at_20[0x10];
e281682b
SM		 3942 u8 op_mod[0x10];
3943
b4ff3a36 3944 u8 reserved_at_40[0x40];
e281682b
SM		 3945};
3946
813f8540
MHY		 3947struct mlx5_ifc_query_scheduling_element_out_bits {
3948 u8 opcode[0x10];
3949 u8 reserved_at_10[0x10];
3950
3951 u8 reserved_at_20[0x10];
3952 u8 op_mod[0x10];
3953
3954 u8 reserved_at_40[0xc0];
3955
3956 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3957
3958 u8 reserved_at_300[0x100];
3959};
3960
3961enum {
3962 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3963};
3964
3965struct mlx5_ifc_query_scheduling_element_in_bits {
3966 u8 opcode[0x10];
3967 u8 reserved_at_10[0x10];
3968
3969 u8 reserved_at_20[0x10];
3970 u8 op_mod[0x10];
3971
3972 u8 scheduling_hierarchy[0x8];
3973 u8 reserved_at_48[0x18];
3974
3975 u8 scheduling_element_id[0x20];
3976
3977 u8 reserved_at_80[0x180];
3978};
3979
e281682b
SM		 3980struct mlx5_ifc_query_rqt_out_bits {
3981 u8 status[0x8];
b4ff3a36 3982 u8 reserved_at_8[0x18];
e281682b
SM		 3983
3984 u8 syndrome[0x20];
3985
b4ff3a36 3986 u8 reserved_at_40[0xc0];
e281682b
SM		 3987
3988 struct mlx5_ifc_rqtc_bits rqt_context;
3989};
3990
3991struct mlx5_ifc_query_rqt_in_bits {
3992 u8 opcode[0x10];
b4ff3a36 3993 u8 reserved_at_10[0x10];
e281682b 3994
b4ff3a36 3995 u8 reserved_at_20[0x10];
e281682b
SM		 3996 u8 op_mod[0x10];
3997
b4ff3a36 3998 u8 reserved_at_40[0x8];
e281682b
SM		 3999 u8 rqtn[0x18];
4000
b4ff3a36 4001 u8 reserved_at_60[0x20];
e281682b
SM		 4002};
4003
4004struct mlx5_ifc_query_rq_out_bits {
4005 u8 status[0x8];
b4ff3a36 4006 u8 reserved_at_8[0x18];
e281682b
SM		 4007
4008 u8 syndrome[0x20];
4009
b4ff3a36 4010 u8 reserved_at_40[0xc0];
e281682b
SM		 4011
4012 struct mlx5_ifc_rqc_bits rq_context;
4013};
4014
4015struct mlx5_ifc_query_rq_in_bits {
4016 u8 opcode[0x10];
b4ff3a36 4017 u8 reserved_at_10[0x10];
e281682b 4018
b4ff3a36 4019 u8 reserved_at_20[0x10];
e281682b
SM		 4020 u8 op_mod[0x10];
4021
b4ff3a36 4022 u8 reserved_at_40[0x8];
e281682b
SM		 4023 u8 rqn[0x18];
4024
b4ff3a36 4025 u8 reserved_at_60[0x20];
e281682b
SM		 4026};
4027
4028struct mlx5_ifc_query_roce_address_out_bits {
4029 u8 status[0x8];
b4ff3a36 4030 u8 reserved_at_8[0x18];
e281682b
SM		 4031
4032 u8 syndrome[0x20];
4033
b4ff3a36 4034 u8 reserved_at_40[0x40];
e281682b
SM		 4035
4036 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4037};
4038
4039struct mlx5_ifc_query_roce_address_in_bits {
4040 u8 opcode[0x10];
b4ff3a36 4041 u8 reserved_at_10[0x10];
e281682b 4042
b4ff3a36 4043 u8 reserved_at_20[0x10];
e281682b
SM		 4044 u8 op_mod[0x10];
4045
4046 u8 roce_address_index[0x10];
32f69e4b
DJ		 4047 u8 reserved_at_50[0xc];
4048 u8 vhca_port_num[0x4];
e281682b 4049
b4ff3a36 4050 u8 reserved_at_60[0x20];
e281682b
SM		 4051};
4052
4053struct mlx5_ifc_query_rmp_out_bits {
4054 u8 status[0x8];
b4ff3a36 4055 u8 reserved_at_8[0x18];
e281682b
SM		 4056
4057 u8 syndrome[0x20];
4058
b4ff3a36 4059 u8 reserved_at_40[0xc0];
e281682b
SM		 4060
4061 struct mlx5_ifc_rmpc_bits rmp_context;
4062};
4063
4064struct mlx5_ifc_query_rmp_in_bits {
4065 u8 opcode[0x10];
b4ff3a36 4066 u8 reserved_at_10[0x10];
e281682b 4067
b4ff3a36 4068 u8 reserved_at_20[0x10];
e281682b
SM		 4069 u8 op_mod[0x10];
4070
b4ff3a36 4071 u8 reserved_at_40[0x8];
e281682b
SM		 4072 u8 rmpn[0x18];
4073
b4ff3a36 4074 u8 reserved_at_60[0x20];
e281682b
SM		 4075};
4076
4077struct mlx5_ifc_query_qp_out_bits {
4078 u8 status[0x8];
b4ff3a36 4079 u8 reserved_at_8[0x18];
e281682b
SM		 4080
4081 u8 syndrome[0x20];
4082
b4ff3a36 4083 u8 reserved_at_40[0x40];
e281682b
SM		 4084
4085 u8 opt_param_mask[0x20];
4086
b4ff3a36 4087 u8 reserved_at_a0[0x20];
e281682b
SM		 4088
4089 struct mlx5_ifc_qpc_bits qpc;
4090
b4ff3a36 4091 u8 reserved_at_800[0x80];
e281682b
SM		 4092
4093 u8 pas[0][0x40];
4094};
4095
4096struct mlx5_ifc_query_qp_in_bits {
4097 u8 opcode[0x10];
b4ff3a36 4098 u8 reserved_at_10[0x10];
e281682b 4099
b4ff3a36 4100 u8 reserved_at_20[0x10];
e281682b
SM		 4101 u8 op_mod[0x10];
4102
b4ff3a36 4103 u8 reserved_at_40[0x8];
e281682b
SM		 4104 u8 qpn[0x18];
4105
b4ff3a36 4106 u8 reserved_at_60[0x20];
e281682b
SM		 4107};
4108
4109struct mlx5_ifc_query_q_counter_out_bits {
4110 u8 status[0x8];
b4ff3a36 4111 u8 reserved_at_8[0x18];
e281682b
SM		 4112
4113 u8 syndrome[0x20];
4114
b4ff3a36 4115 u8 reserved_at_40[0x40];
e281682b
SM		 4116
4117 u8 rx_write_requests[0x20];
4118
b4ff3a36 4119 u8 reserved_at_a0[0x20];
e281682b
SM		 4120
4121 u8 rx_read_requests[0x20];
4122
b4ff3a36 4123 u8 reserved_at_e0[0x20];
e281682b
SM		 4124
4125 u8 rx_atomic_requests[0x20];
4126
b4ff3a36 4127 u8 reserved_at_120[0x20];
e281682b
SM		 4128
4129 u8 rx_dct_connect[0x20];
4130
b4ff3a36 4131 u8 reserved_at_160[0x20];
e281682b
SM		 4132
4133 u8 out_of_buffer[0x20];
4134
b4ff3a36 4135 u8 reserved_at_1a0[0x20];
e281682b
SM		 4136
4137 u8 out_of_sequence[0x20];
4138
7486216b
SM		 4139 u8 reserved_at_1e0[0x20];
4140
4141 u8 duplicate_request[0x20];
4142
4143 u8 reserved_at_220[0x20];
4144
4145 u8 rnr_nak_retry_err[0x20];
4146
4147 u8 reserved_at_260[0x20];
4148
4149 u8 packet_seq_err[0x20];
4150
4151 u8 reserved_at_2a0[0x20];
4152
4153 u8 implied_nak_seq_err[0x20];
4154
4155 u8 reserved_at_2e0[0x20];
4156
4157 u8 local_ack_timeout_err[0x20];
4158
58dcb60a
PP		 4159 u8 reserved_at_320[0xa0];
4160
4161 u8 resp_local_length_error[0x20];
4162
4163 u8 req_local_length_error[0x20];
4164
4165 u8 resp_local_qp_error[0x20];
4166
4167 u8 local_operation_error[0x20];
4168
4169 u8 resp_local_protection[0x20];
4170
4171 u8 req_local_protection[0x20];
4172
4173 u8 resp_cqe_error[0x20];
4174
4175 u8 req_cqe_error[0x20];
4176
4177 u8 req_mw_binding[0x20];
4178
4179 u8 req_bad_response[0x20];
4180
4181 u8 req_remote_invalid_request[0x20];
4182
4183 u8 resp_remote_invalid_request[0x20];
4184
4185 u8 req_remote_access_errors[0x20];
4186
4187 u8 resp_remote_access_errors[0x20];
4188
4189 u8 req_remote_operation_errors[0x20];
4190
4191 u8 req_transport_retries_exceeded[0x20];
4192
4193 u8 cq_overflow[0x20];
4194
4195 u8 resp_cqe_flush_error[0x20];
4196
4197 u8 req_cqe_flush_error[0x20];
4198
4199 u8 reserved_at_620[0x1e0];
e281682b
SM		 4200};
4201
4202struct mlx5_ifc_query_q_counter_in_bits {
4203 u8 opcode[0x10];
b4ff3a36 4204 u8 reserved_at_10[0x10];
e281682b 4205
b4ff3a36 4206 u8 reserved_at_20[0x10];
e281682b
SM		 4207 u8 op_mod[0x10];
4208
b4ff3a36 4209 u8 reserved_at_40[0x80];
e281682b
SM		 4210
4211 u8 clear[0x1];
b4ff3a36 4212 u8 reserved_at_c1[0x1f];
e281682b 4213
b4ff3a36 4214 u8 reserved_at_e0[0x18];
e281682b
SM		 4215 u8 counter_set_id[0x8];
4216};
4217
4218struct mlx5_ifc_query_pages_out_bits {
4219 u8 status[0x8];
b4ff3a36 4220 u8 reserved_at_8[0x18];
e281682b
SM		 4221
4222 u8 syndrome[0x20];
4223
b4ff3a36 4224 u8 reserved_at_40[0x10];
e281682b
SM		 4225 u8 function_id[0x10];
4226
4227 u8 num_pages[0x20];
4228};
4229
4230enum {
4231 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4232 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4233 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4234};
4235
4236struct mlx5_ifc_query_pages_in_bits {
4237 u8 opcode[0x10];
b4ff3a36 4238 u8 reserved_at_10[0x10];
e281682b 4239
b4ff3a36 4240 u8 reserved_at_20[0x10];
e281682b
SM		 4241 u8 op_mod[0x10];
4242
b4ff3a36 4243 u8 reserved_at_40[0x10];
e281682b
SM		 4244 u8 function_id[0x10];
4245
b4ff3a36 4246 u8 reserved_at_60[0x20];
e281682b
SM		 4247};
4248
4249struct mlx5_ifc_query_nic_vport_context_out_bits {
4250 u8 status[0x8];
b4ff3a36 4251 u8 reserved_at_8[0x18];
e281682b
SM		 4252
4253 u8 syndrome[0x20];
4254
b4ff3a36 4255 u8 reserved_at_40[0x40];
e281682b
SM		 4256
4257 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4258};
4259
4260struct mlx5_ifc_query_nic_vport_context_in_bits {
4261 u8 opcode[0x10];
b4ff3a36 4262 u8 reserved_at_10[0x10];
e281682b 4263
b4ff3a36 4264 u8 reserved_at_20[0x10];
e281682b
SM		 4265 u8 op_mod[0x10];
4266
4267 u8 other_vport[0x1];
b4ff3a36 4268 u8 reserved_at_41[0xf];
e281682b
SM		 4269 u8 vport_number[0x10];
4270
b4ff3a36 4271 u8 reserved_at_60[0x5];
e281682b 4272 u8 allowed_list_type[0x3];
b4ff3a36 4273 u8 reserved_at_68[0x18];
e281682b
SM		 4274};
4275
4276struct mlx5_ifc_query_mkey_out_bits {
4277 u8 status[0x8];
b4ff3a36 4278 u8 reserved_at_8[0x18];
e281682b
SM		 4279
4280 u8 syndrome[0x20];
4281
b4ff3a36 4282 u8 reserved_at_40[0x40];
e281682b
SM		 4283
4284 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4285
b4ff3a36 4286 u8 reserved_at_280[0x600];
e281682b
SM		 4287
4288 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4289
4290 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4291};
4292
4293struct mlx5_ifc_query_mkey_in_bits {
4294 u8 opcode[0x10];
b4ff3a36 4295 u8 reserved_at_10[0x10];
e281682b 4296
b4ff3a36 4297 u8 reserved_at_20[0x10];
e281682b
SM		 4298 u8 op_mod[0x10];
4299
b4ff3a36 4300 u8 reserved_at_40[0x8];
e281682b
SM		 4301 u8 mkey_index[0x18];
4302
4303 u8 pg_access[0x1];
b4ff3a36 4304 u8 reserved_at_61[0x1f];
e281682b
SM		 4305};
4306
4307struct mlx5_ifc_query_mad_demux_out_bits {
4308 u8 status[0x8];
b4ff3a36 4309 u8 reserved_at_8[0x18];
e281682b
SM		 4310
4311 u8 syndrome[0x20];
4312
b4ff3a36 4313 u8 reserved_at_40[0x40];
e281682b
SM		 4314
4315 u8 mad_dumux_parameters_block[0x20];
4316};
4317
4318struct mlx5_ifc_query_mad_demux_in_bits {
4319 u8 opcode[0x10];
b4ff3a36 4320 u8 reserved_at_10[0x10];
e281682b 4321
b4ff3a36 4322 u8 reserved_at_20[0x10];
e281682b
SM		 4323 u8 op_mod[0x10];
4324
b4ff3a36 4325 u8 reserved_at_40[0x40];
e281682b
SM		 4326};
4327
4328struct mlx5_ifc_query_l2_table_entry_out_bits {
4329 u8 status[0x8];
b4ff3a36 4330 u8 reserved_at_8[0x18];
e281682b
SM		 4331
4332 u8 syndrome[0x20];
4333
b4ff3a36 4334 u8 reserved_at_40[0xa0];
e281682b 4335
b4ff3a36 4336 u8 reserved_at_e0[0x13];
e281682b
SM		 4337 u8 vlan_valid[0x1];
4338 u8 vlan[0xc];
4339
4340 struct mlx5_ifc_mac_address_layout_bits mac_address;
4341
b4ff3a36 4342 u8 reserved_at_140[0xc0];
e281682b
SM		 4343};
4344
4345struct mlx5_ifc_query_l2_table_entry_in_bits {
4346 u8 opcode[0x10];
b4ff3a36 4347 u8 reserved_at_10[0x10];
e281682b 4348
b4ff3a36 4349 u8 reserved_at_20[0x10];
e281682b
SM		 4350 u8 op_mod[0x10];
4351
b4ff3a36 4352 u8 reserved_at_40[0x60];
e281682b 4353
b4ff3a36 4354 u8 reserved_at_a0[0x8];
e281682b
SM		 4355 u8 table_index[0x18];
4356
b4ff3a36 4357 u8 reserved_at_c0[0x140];
e281682b
SM		 4358};
4359
4360struct mlx5_ifc_query_issi_out_bits {
4361 u8 status[0x8];
b4ff3a36 4362 u8 reserved_at_8[0x18];
e281682b
SM		 4363
4364 u8 syndrome[0x20];
4365
b4ff3a36 4366 u8 reserved_at_40[0x10];
e281682b
SM		 4367 u8 current_issi[0x10];
4368
b4ff3a36 4369 u8 reserved_at_60[0xa0];
e281682b 4370
b4ff3a36 4371 u8 reserved_at_100[76][0x8];
e281682b
SM		 4372 u8 supported_issi_dw0[0x20];
4373};
4374
4375struct mlx5_ifc_query_issi_in_bits {
4376 u8 opcode[0x10];
b4ff3a36 4377 u8 reserved_at_10[0x10];
e281682b 4378
b4ff3a36 4379 u8 reserved_at_20[0x10];
e281682b
SM		 4380 u8 op_mod[0x10];
4381
b4ff3a36 4382 u8 reserved_at_40[0x40];
e281682b
SM		 4383};
4384
0dbc6fe0
SM		 4385struct mlx5_ifc_set_driver_version_out_bits {
4386 u8 status[0x8];
4387 u8 reserved_0[0x18];
4388
4389 u8 syndrome[0x20];
4390 u8 reserved_1[0x40];
4391};
4392
4393struct mlx5_ifc_set_driver_version_in_bits {
4394 u8 opcode[0x10];
4395 u8 reserved_0[0x10];
4396
4397 u8 reserved_1[0x10];
4398 u8 op_mod[0x10];
4399
4400 u8 reserved_2[0x40];
4401 u8 driver_version[64][0x8];
4402};
4403
e281682b
SM		 4404struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4405 u8 status[0x8];
b4ff3a36 4406 u8 reserved_at_8[0x18];
e281682b
SM		 4407
4408 u8 syndrome[0x20];
4409
b4ff3a36 4410 u8 reserved_at_40[0x40];
e281682b
SM		 4411
4412 struct mlx5_ifc_pkey_bits pkey[0];
4413};
4414
4415struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4416 u8 opcode[0x10];
b4ff3a36 4417 u8 reserved_at_10[0x10];
e281682b 4418
b4ff3a36 4419 u8 reserved_at_20[0x10];
e281682b
SM		 4420 u8 op_mod[0x10];
4421
4422 u8 other_vport[0x1];
b4ff3a36 4423 u8 reserved_at_41[0xb];
707c4602 4424 u8 port_num[0x4];
e281682b
SM		 4425 u8 vport_number[0x10];
4426
b4ff3a36 4427 u8 reserved_at_60[0x10];
e281682b
SM		 4428 u8 pkey_index[0x10];
4429};
4430
eff901d3
EC		 4431enum {
4432 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4433 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4434 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4435};
4436
e281682b
SM		 4437struct mlx5_ifc_query_hca_vport_gid_out_bits {
4438 u8 status[0x8];
b4ff3a36 4439 u8 reserved_at_8[0x18];
e281682b
SM		 4440
4441 u8 syndrome[0x20];
4442
b4ff3a36 4443 u8 reserved_at_40[0x20];
e281682b
SM		 4444
4445 u8 gids_num[0x10];
b4ff3a36 4446 u8 reserved_at_70[0x10];
e281682b
SM		 4447
4448 struct mlx5_ifc_array128_auto_bits gid[0];
4449};
4450
4451struct mlx5_ifc_query_hca_vport_gid_in_bits {
4452 u8 opcode[0x10];
b4ff3a36 4453 u8 reserved_at_10[0x10];
e281682b 4454
b4ff3a36 4455 u8 reserved_at_20[0x10];
e281682b
SM		 4456 u8 op_mod[0x10];
4457
4458 u8 other_vport[0x1];
b4ff3a36 4459 u8 reserved_at_41[0xb];
707c4602 4460 u8 port_num[0x4];
e281682b
SM		 4461 u8 vport_number[0x10];
4462
b4ff3a36 4463 u8 reserved_at_60[0x10];
e281682b
SM		 4464 u8 gid_index[0x10];
4465};
4466
4467struct mlx5_ifc_query_hca_vport_context_out_bits {
4468 u8 status[0x8];
b4ff3a36 4469 u8 reserved_at_8[0x18];
e281682b
SM		 4470
4471 u8 syndrome[0x20];
4472
b4ff3a36 4473 u8 reserved_at_40[0x40];
e281682b
SM		 4474
4475 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4476};
4477
4478struct mlx5_ifc_query_hca_vport_context_in_bits {
4479 u8 opcode[0x10];
b4ff3a36 4480 u8 reserved_at_10[0x10];
e281682b 4481
b4ff3a36 4482 u8 reserved_at_20[0x10];
e281682b
SM		 4483 u8 op_mod[0x10];
4484
4485 u8 other_vport[0x1];
b4ff3a36 4486 u8 reserved_at_41[0xb];
707c4602 4487 u8 port_num[0x4];
e281682b
SM		 4488 u8 vport_number[0x10];
4489
b4ff3a36 4490 u8 reserved_at_60[0x20];
e281682b
SM		 4491};
4492
4493struct mlx5_ifc_query_hca_cap_out_bits {
4494 u8 status[0x8];
b4ff3a36 4495 u8 reserved_at_8[0x18];
e281682b
SM		 4496
4497 u8 syndrome[0x20];
4498
b4ff3a36 4499 u8 reserved_at_40[0x40];
e281682b
SM		 4500
4501 union mlx5_ifc_hca_cap_union_bits capability;
4502};
4503
4504struct mlx5_ifc_query_hca_cap_in_bits {
4505 u8 opcode[0x10];
b4ff3a36 4506 u8 reserved_at_10[0x10];
e281682b 4507
b4ff3a36 4508 u8 reserved_at_20[0x10];
e281682b
SM		 4509 u8 op_mod[0x10];
4510
b4ff3a36 4511 u8 reserved_at_40[0x40];
e281682b
SM		 4512};
4513
4514struct mlx5_ifc_query_flow_table_out_bits {
4515 u8 status[0x8];
b4ff3a36 4516 u8 reserved_at_8[0x18];
e281682b
SM		 4517
4518 u8 syndrome[0x20];
4519
b4ff3a36 4520 u8 reserved_at_40[0x80];
e281682b 4521
b4ff3a36 4522 u8 reserved_at_c0[0x8];
e281682b 4523 u8 level[0x8];
b4ff3a36 4524 u8 reserved_at_d0[0x8];
e281682b
SM		 4525 u8 log_size[0x8];
4526
b4ff3a36 4527 u8 reserved_at_e0[0x120];
e281682b
SM		 4528};
4529
4530struct mlx5_ifc_query_flow_table_in_bits {
4531 u8 opcode[0x10];
b4ff3a36 4532 u8 reserved_at_10[0x10];
e281682b 4533
b4ff3a36 4534 u8 reserved_at_20[0x10];
e281682b
SM		 4535 u8 op_mod[0x10];
4536
b4ff3a36 4537 u8 reserved_at_40[0x40];
e281682b
SM		 4538
4539 u8 table_type[0x8];
b4ff3a36 4540 u8 reserved_at_88[0x18];
e281682b 4541
b4ff3a36 4542 u8 reserved_at_a0[0x8];
e281682b
SM		 4543 u8 table_id[0x18];
4544
b4ff3a36 4545 u8 reserved_at_c0[0x140];
e281682b
SM		 4546};
4547
4548struct mlx5_ifc_query_fte_out_bits {
4549 u8 status[0x8];
b4ff3a36 4550 u8 reserved_at_8[0x18];
e281682b
SM		 4551
4552 u8 syndrome[0x20];
4553
b4ff3a36 4554 u8 reserved_at_40[0x1c0];
e281682b
SM		 4555
4556 struct mlx5_ifc_flow_context_bits flow_context;
4557};
4558
4559struct mlx5_ifc_query_fte_in_bits {
4560 u8 opcode[0x10];
b4ff3a36 4561 u8 reserved_at_10[0x10];
e281682b 4562
b4ff3a36 4563 u8 reserved_at_20[0x10];
e281682b
SM		 4564 u8 op_mod[0x10];
4565
b4ff3a36 4566 u8 reserved_at_40[0x40];
e281682b
SM		 4567
4568 u8 table_type[0x8];
b4ff3a36 4569 u8 reserved_at_88[0x18];
e281682b 4570
b4ff3a36 4571 u8 reserved_at_a0[0x8];
e281682b
SM		 4572 u8 table_id[0x18];
4573
b4ff3a36 4574 u8 reserved_at_c0[0x40];
e281682b
SM		 4575
4576 u8 flow_index[0x20];
4577
b4ff3a36 4578 u8 reserved_at_120[0xe0];
e281682b
SM		 4579};
4580
4581enum {
4582 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4583 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4584 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4585};
4586
4587struct mlx5_ifc_query_flow_group_out_bits {
4588 u8 status[0x8];
b4ff3a36 4589 u8 reserved_at_8[0x18];
e281682b
SM		 4590
4591 u8 syndrome[0x20];
4592
b4ff3a36 4593 u8 reserved_at_40[0xa0];
e281682b
SM		 4594
4595 u8 start_flow_index[0x20];
4596
b4ff3a36 4597 u8 reserved_at_100[0x20];
e281682b
SM		 4598
4599 u8 end_flow_index[0x20];
4600
b4ff3a36 4601 u8 reserved_at_140[0xa0];
e281682b 4602
b4ff3a36 4603 u8 reserved_at_1e0[0x18];
e281682b
SM		 4604 u8 match_criteria_enable[0x8];
4605
4606 struct mlx5_ifc_fte_match_param_bits match_criteria;
4607
b4ff3a36 4608 u8 reserved_at_1200[0xe00];
e281682b
SM		 4609};
4610
4611struct mlx5_ifc_query_flow_group_in_bits {
4612 u8 opcode[0x10];
b4ff3a36 4613 u8 reserved_at_10[0x10];
e281682b 4614
b4ff3a36 4615 u8 reserved_at_20[0x10];
e281682b
SM		 4616 u8 op_mod[0x10];
4617
b4ff3a36 4618 u8 reserved_at_40[0x40];
e281682b
SM		 4619
4620 u8 table_type[0x8];
b4ff3a36 4621 u8 reserved_at_88[0x18];
e281682b 4622
b4ff3a36 4623 u8 reserved_at_a0[0x8];
e281682b
SM		 4624 u8 table_id[0x18];
4625
4626 u8 group_id[0x20];
4627
b4ff3a36 4628 u8 reserved_at_e0[0x120];
e281682b
SM		 4629};
4630
9dc0b289
AV		 4631struct mlx5_ifc_query_flow_counter_out_bits {
4632 u8 status[0x8];
4633 u8 reserved_at_8[0x18];
4634
4635 u8 syndrome[0x20];
4636
4637 u8 reserved_at_40[0x40];
4638
4639 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4640};
4641
4642struct mlx5_ifc_query_flow_counter_in_bits {
4643 u8 opcode[0x10];
4644 u8 reserved_at_10[0x10];
4645
4646 u8 reserved_at_20[0x10];
4647 u8 op_mod[0x10];
4648
4649 u8 reserved_at_40[0x80];
4650
4651 u8 clear[0x1];
4652 u8 reserved_at_c1[0xf];
4653 u8 num_of_counters[0x10];
4654
a8ffcc74 4655 u8 flow_counter_id[0x20];
9dc0b289
AV		 4656};
4657
d6666753
SM		 4658struct mlx5_ifc_query_esw_vport_context_out_bits {
4659 u8 status[0x8];
b4ff3a36 4660 u8 reserved_at_8[0x18];
d6666753
SM		 4661
4662 u8 syndrome[0x20];
4663
b4ff3a36 4664 u8 reserved_at_40[0x40];
d6666753
SM		 4665
4666 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4667};
4668
4669struct mlx5_ifc_query_esw_vport_context_in_bits {
4670 u8 opcode[0x10];
b4ff3a36 4671 u8 reserved_at_10[0x10];
d6666753 4672
b4ff3a36 4673 u8 reserved_at_20[0x10];
d6666753
SM		 4674 u8 op_mod[0x10];
4675
4676 u8 other_vport[0x1];
b4ff3a36 4677 u8 reserved_at_41[0xf];
d6666753
SM		 4678 u8 vport_number[0x10];
4679
b4ff3a36 4680 u8 reserved_at_60[0x20];
d6666753
SM		 4681};
4682
4683struct mlx5_ifc_modify_esw_vport_context_out_bits {
4684 u8 status[0x8];
b4ff3a36 4685 u8 reserved_at_8[0x18];
d6666753
SM		 4686
4687 u8 syndrome[0x20];
4688
b4ff3a36 4689 u8 reserved_at_40[0x40];
d6666753
SM		 4690};
4691
4692struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4693 u8 reserved_at_0[0x1c];
d6666753
SM		 4694 u8 vport_cvlan_insert[0x1];
4695 u8 vport_svlan_insert[0x1];
4696 u8 vport_cvlan_strip[0x1];
4697 u8 vport_svlan_strip[0x1];
4698};
4699
4700struct mlx5_ifc_modify_esw_vport_context_in_bits {
4701 u8 opcode[0x10];
b4ff3a36 4702 u8 reserved_at_10[0x10];
d6666753 4703
b4ff3a36 4704 u8 reserved_at_20[0x10];
d6666753
SM		 4705 u8 op_mod[0x10];
4706
4707 u8 other_vport[0x1];
b4ff3a36 4708 u8 reserved_at_41[0xf];
d6666753
SM		 4709 u8 vport_number[0x10];
4710
4711 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4712
4713 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4714};
4715
e281682b
SM		 4716struct mlx5_ifc_query_eq_out_bits {
4717 u8 status[0x8];
b4ff3a36 4718 u8 reserved_at_8[0x18];
e281682b
SM		 4719
4720 u8 syndrome[0x20];
4721
b4ff3a36 4722 u8 reserved_at_40[0x40];
e281682b
SM		 4723
4724 struct mlx5_ifc_eqc_bits eq_context_entry;
4725
b4ff3a36 4726 u8 reserved_at_280[0x40];
e281682b
SM		 4727
4728 u8 event_bitmask[0x40];
4729
b4ff3a36 4730 u8 reserved_at_300[0x580];
e281682b
SM		 4731
4732 u8 pas[0][0x40];
4733};
4734
4735struct mlx5_ifc_query_eq_in_bits {
4736 u8 opcode[0x10];
b4ff3a36 4737 u8 reserved_at_10[0x10];
e281682b 4738
b4ff3a36 4739 u8 reserved_at_20[0x10];
e281682b
SM		 4740 u8 op_mod[0x10];
4741
b4ff3a36 4742 u8 reserved_at_40[0x18];
e281682b
SM		 4743 u8 eq_number[0x8];
4744
b4ff3a36 4745 u8 reserved_at_60[0x20];
e281682b
SM		 4746};
4747
7adbde20
HHZ		 4748struct mlx5_ifc_encap_header_in_bits {
4749 u8 reserved_at_0[0x5];
4750 u8 header_type[0x3];
4751 u8 reserved_at_8[0xe];
4752 u8 encap_header_size[0xa];
4753
4754 u8 reserved_at_20[0x10];
4755 u8 encap_header[2][0x8];
4756
4757 u8 more_encap_header[0][0x8];
4758};
4759
4760struct mlx5_ifc_query_encap_header_out_bits {
4761 u8 status[0x8];
4762 u8 reserved_at_8[0x18];
4763
4764 u8 syndrome[0x20];
4765
4766 u8 reserved_at_40[0xa0];
4767
4768 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4769};
4770
4771struct mlx5_ifc_query_encap_header_in_bits {
4772 u8 opcode[0x10];
4773 u8 reserved_at_10[0x10];
4774
4775 u8 reserved_at_20[0x10];
4776 u8 op_mod[0x10];
4777
4778 u8 encap_id[0x20];
4779
4780 u8 reserved_at_60[0xa0];
4781};
4782
4783struct mlx5_ifc_alloc_encap_header_out_bits {
4784 u8 status[0x8];
4785 u8 reserved_at_8[0x18];
4786
4787 u8 syndrome[0x20];
4788
4789 u8 encap_id[0x20];
4790
4791 u8 reserved_at_60[0x20];
4792};
4793
4794struct mlx5_ifc_alloc_encap_header_in_bits {
4795 u8 opcode[0x10];
4796 u8 reserved_at_10[0x10];
4797
4798 u8 reserved_at_20[0x10];
4799 u8 op_mod[0x10];
4800
4801 u8 reserved_at_40[0xa0];
4802
4803 struct mlx5_ifc_encap_header_in_bits encap_header;
4804};
4805
4806struct mlx5_ifc_dealloc_encap_header_out_bits {
4807 u8 status[0x8];
4808 u8 reserved_at_8[0x18];
4809
4810 u8 syndrome[0x20];
4811
4812 u8 reserved_at_40[0x40];
4813};
4814
4815struct mlx5_ifc_dealloc_encap_header_in_bits {
4816 u8 opcode[0x10];
4817 u8 reserved_at_10[0x10];
4818
4819 u8 reserved_20[0x10];
4820 u8 op_mod[0x10];
4821
4822 u8 encap_id[0x20];
4823
4824 u8 reserved_60[0x20];
4825};
4826
2a69cb9f
OG		 4827struct mlx5_ifc_set_action_in_bits {
4828 u8 action_type[0x4];
4829 u8 field[0xc];
4830 u8 reserved_at_10[0x3];
4831 u8 offset[0x5];
4832 u8 reserved_at_18[0x3];
4833 u8 length[0x5];
4834
4835 u8 data[0x20];
4836};
4837
4838struct mlx5_ifc_add_action_in_bits {
4839 u8 action_type[0x4];
4840 u8 field[0xc];
4841 u8 reserved_at_10[0x10];
4842
4843 u8 data[0x20];
4844};
4845
4846union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4847 struct mlx5_ifc_set_action_in_bits set_action_in;
4848 struct mlx5_ifc_add_action_in_bits add_action_in;
4849 u8 reserved_at_0[0x40];
4850};
4851
4852enum {
4853 MLX5_ACTION_TYPE_SET = 0x1,
4854 MLX5_ACTION_TYPE_ADD = 0x2,
4855};
4856
4857enum {
4858 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4859 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4860 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4861 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4862 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4863 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4864 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4865 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4866 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4867 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4868 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4869 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4870 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4871 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4872 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4873 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4874 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4875 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4876 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4877 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4878 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4879 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4880 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4881};
4882
4883struct mlx5_ifc_alloc_modify_header_context_out_bits {
4884 u8 status[0x8];
4885 u8 reserved_at_8[0x18];
4886
4887 u8 syndrome[0x20];
4888
4889 u8 modify_header_id[0x20];
4890
4891 u8 reserved_at_60[0x20];
4892};
4893
4894struct mlx5_ifc_alloc_modify_header_context_in_bits {
4895 u8 opcode[0x10];
4896 u8 reserved_at_10[0x10];
4897
4898 u8 reserved_at_20[0x10];
4899 u8 op_mod[0x10];
4900
4901 u8 reserved_at_40[0x20];
4902
4903 u8 table_type[0x8];
4904 u8 reserved_at_68[0x10];
4905 u8 num_of_actions[0x8];
4906
4907 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4908};
4909
4910struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4911 u8 status[0x8];
4912 u8 reserved_at_8[0x18];
4913
4914 u8 syndrome[0x20];
4915
4916 u8 reserved_at_40[0x40];
4917};
4918
4919struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4920 u8 opcode[0x10];
4921 u8 reserved_at_10[0x10];
4922
4923 u8 reserved_at_20[0x10];
4924 u8 op_mod[0x10];
4925
4926 u8 modify_header_id[0x20];
4927
4928 u8 reserved_at_60[0x20];
4929};
4930
e281682b
SM		 4931struct mlx5_ifc_query_dct_out_bits {
4932 u8 status[0x8];
b4ff3a36 4933 u8 reserved_at_8[0x18];
e281682b
SM		 4934
4935 u8 syndrome[0x20];
4936
b4ff3a36 4937 u8 reserved_at_40[0x40];
e281682b
SM		 4938
4939 struct mlx5_ifc_dctc_bits dct_context_entry;
4940
b4ff3a36 4941 u8 reserved_at_280[0x180];
e281682b
SM		 4942};
4943
4944struct mlx5_ifc_query_dct_in_bits {
4945 u8 opcode[0x10];
b4ff3a36 4946 u8 reserved_at_10[0x10];
e281682b 4947
b4ff3a36 4948 u8 reserved_at_20[0x10];
e281682b
SM		 4949 u8 op_mod[0x10];
4950
b4ff3a36 4951 u8 reserved_at_40[0x8];
e281682b
SM		 4952 u8 dctn[0x18];
4953
b4ff3a36 4954 u8 reserved_at_60[0x20];
e281682b
SM		 4955};
4956
4957struct mlx5_ifc_query_cq_out_bits {
4958 u8 status[0x8];
b4ff3a36 4959 u8 reserved_at_8[0x18];
e281682b
SM		 4960
4961 u8 syndrome[0x20];
4962
b4ff3a36 4963 u8 reserved_at_40[0x40];
e281682b
SM		 4964
4965 struct mlx5_ifc_cqc_bits cq_context;
4966
b4ff3a36 4967 u8 reserved_at_280[0x600];
e281682b
SM		 4968
4969 u8 pas[0][0x40];
4970};
4971
4972struct mlx5_ifc_query_cq_in_bits {
4973 u8 opcode[0x10];
b4ff3a36 4974 u8 reserved_at_10[0x10];
e281682b 4975
b4ff3a36 4976 u8 reserved_at_20[0x10];
e281682b
SM		 4977 u8 op_mod[0x10];
4978
b4ff3a36 4979 u8 reserved_at_40[0x8];
e281682b
SM		 4980 u8 cqn[0x18];
4981
b4ff3a36 4982 u8 reserved_at_60[0x20];
e281682b
SM		 4983};
4984
4985struct mlx5_ifc_query_cong_status_out_bits {
4986 u8 status[0x8];
b4ff3a36 4987 u8 reserved_at_8[0x18];
e281682b
SM		 4988
4989 u8 syndrome[0x20];
4990
b4ff3a36 4991 u8 reserved_at_40[0x20];
e281682b
SM		 4992
4993 u8 enable[0x1];
4994 u8 tag_enable[0x1];
b4ff3a36 4995 u8 reserved_at_62[0x1e];
e281682b
SM		 4996};
4997
4998struct mlx5_ifc_query_cong_status_in_bits {
4999 u8 opcode[0x10];
b4ff3a36 5000 u8 reserved_at_10[0x10];
e281682b 5001
b4ff3a36 5002 u8 reserved_at_20[0x10];
e281682b
SM		 5003 u8 op_mod[0x10];
5004
b4ff3a36 5005 u8 reserved_at_40[0x18];
e281682b
SM		 5006 u8 priority[0x4];
5007 u8 cong_protocol[0x4];
5008
b4ff3a36 5009 u8 reserved_at_60[0x20];
e281682b
SM		 5010};
5011
5012struct mlx5_ifc_query_cong_statistics_out_bits {
5013 u8 status[0x8];
b4ff3a36 5014 u8 reserved_at_8[0x18];
e281682b
SM		 5015
5016 u8 syndrome[0x20];
5017
b4ff3a36 5018 u8 reserved_at_40[0x40];
e281682b 5019
e1f24a79 5020 u8 rp_cur_flows[0x20];
e281682b
SM		 5021
5022 u8 sum_flows[0x20];
5023
e1f24a79 5024 u8 rp_cnp_ignored_high[0x20];
e281682b 5025
e1f24a79 5026 u8 rp_cnp_ignored_low[0x20];
e281682b 5027
e1f24a79 5028 u8 rp_cnp_handled_high[0x20];
e281682b 5029
e1f24a79 5030 u8 rp_cnp_handled_low[0x20];
e281682b 5031
b4ff3a36 5032 u8 reserved_at_140[0x100];
e281682b
SM		 5033
5034 u8 time_stamp_high[0x20];
5035
5036 u8 time_stamp_low[0x20];
5037
5038 u8 accumulators_period[0x20];
5039
e1f24a79 5040 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5041
e1f24a79 5042 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5043
e1f24a79 5044 u8 np_cnp_sent_high[0x20];
e281682b 5045
e1f24a79 5046 u8 np_cnp_sent_low[0x20];
e281682b 5047
b4ff3a36 5048 u8 reserved_at_320[0x560];
e281682b
SM		 5049};
5050
5051struct mlx5_ifc_query_cong_statistics_in_bits {
5052 u8 opcode[0x10];
b4ff3a36 5053 u8 reserved_at_10[0x10];
e281682b 5054
b4ff3a36 5055 u8 reserved_at_20[0x10];
e281682b
SM		 5056 u8 op_mod[0x10];
5057
5058 u8 clear[0x1];
b4ff3a36 5059 u8 reserved_at_41[0x1f];
e281682b 5060
b4ff3a36 5061 u8 reserved_at_60[0x20];
e281682b
SM		 5062};
5063
5064struct mlx5_ifc_query_cong_params_out_bits {
5065 u8 status[0x8];
b4ff3a36 5066 u8 reserved_at_8[0x18];
e281682b
SM		 5067
5068 u8 syndrome[0x20];
5069
b4ff3a36 5070 u8 reserved_at_40[0x40];
e281682b
SM		 5071
5072 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5073};
5074
5075struct mlx5_ifc_query_cong_params_in_bits {
5076 u8 opcode[0x10];
b4ff3a36 5077 u8 reserved_at_10[0x10];
e281682b 5078
b4ff3a36 5079 u8 reserved_at_20[0x10];
e281682b
SM		 5080 u8 op_mod[0x10];
5081
b4ff3a36 5082 u8 reserved_at_40[0x1c];
e281682b
SM		 5083 u8 cong_protocol[0x4];
5084
b4ff3a36 5085 u8 reserved_at_60[0x20];
e281682b
SM		 5086};
5087
5088struct mlx5_ifc_query_adapter_out_bits {
5089 u8 status[0x8];
b4ff3a36 5090 u8 reserved_at_8[0x18];
e281682b
SM		 5091
5092 u8 syndrome[0x20];
5093
b4ff3a36 5094 u8 reserved_at_40[0x40];
e281682b
SM		 5095
5096 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5097};
5098
5099struct mlx5_ifc_query_adapter_in_bits {
5100 u8 opcode[0x10];
b4ff3a36 5101 u8 reserved_at_10[0x10];
e281682b 5102
b4ff3a36 5103 u8 reserved_at_20[0x10];
e281682b
SM		 5104 u8 op_mod[0x10];
5105
b4ff3a36 5106 u8 reserved_at_40[0x40];
e281682b
SM		 5107};
5108
5109struct mlx5_ifc_qp_2rst_out_bits {
5110 u8 status[0x8];
b4ff3a36 5111 u8 reserved_at_8[0x18];
e281682b
SM		 5112
5113 u8 syndrome[0x20];
5114
b4ff3a36 5115 u8 reserved_at_40[0x40];
e281682b
SM		 5116};
5117
5118struct mlx5_ifc_qp_2rst_in_bits {
5119 u8 opcode[0x10];
b4ff3a36 5120 u8 reserved_at_10[0x10];
e281682b 5121
b4ff3a36 5122 u8 reserved_at_20[0x10];
e281682b
SM		 5123 u8 op_mod[0x10];
5124
b4ff3a36 5125 u8 reserved_at_40[0x8];
e281682b
SM		 5126 u8 qpn[0x18];
5127
b4ff3a36 5128 u8 reserved_at_60[0x20];
e281682b
SM		 5129};
5130
5131struct mlx5_ifc_qp_2err_out_bits {
5132 u8 status[0x8];
b4ff3a36 5133 u8 reserved_at_8[0x18];
e281682b
SM		 5134
5135 u8 syndrome[0x20];
5136
b4ff3a36 5137 u8 reserved_at_40[0x40];
e281682b
SM		 5138};
5139
5140struct mlx5_ifc_qp_2err_in_bits {
5141 u8 opcode[0x10];
b4ff3a36 5142 u8 reserved_at_10[0x10];
e281682b 5143
b4ff3a36 5144 u8 reserved_at_20[0x10];
e281682b
SM		 5145 u8 op_mod[0x10];
5146
b4ff3a36 5147 u8 reserved_at_40[0x8];
e281682b
SM		 5148 u8 qpn[0x18];
5149
b4ff3a36 5150 u8 reserved_at_60[0x20];
e281682b
SM		 5151};
5152
5153struct mlx5_ifc_page_fault_resume_out_bits {
5154 u8 status[0x8];
b4ff3a36 5155 u8 reserved_at_8[0x18];
e281682b
SM		 5156
5157 u8 syndrome[0x20];
5158
b4ff3a36 5159 u8 reserved_at_40[0x40];
e281682b
SM		 5160};
5161
5162struct mlx5_ifc_page_fault_resume_in_bits {
5163 u8 opcode[0x10];
b4ff3a36 5164 u8 reserved_at_10[0x10];
e281682b 5165
b4ff3a36 5166 u8 reserved_at_20[0x10];
e281682b
SM		 5167 u8 op_mod[0x10];
5168
5169 u8 error[0x1];
b4ff3a36 5170 u8 reserved_at_41[0x4];
223cdc72
AK		 5171 u8 page_fault_type[0x3];
5172 u8 wq_number[0x18];
e281682b 5173
223cdc72
AK		 5174 u8 reserved_at_60[0x8];
5175 u8 token[0x18];
e281682b
SM		 5176};
5177
5178struct mlx5_ifc_nop_out_bits {
5179 u8 status[0x8];
b4ff3a36 5180 u8 reserved_at_8[0x18];
e281682b
SM		 5181
5182 u8 syndrome[0x20];
5183
b4ff3a36 5184 u8 reserved_at_40[0x40];
e281682b
SM		 5185};
5186
5187struct mlx5_ifc_nop_in_bits {
5188 u8 opcode[0x10];
b4ff3a36 5189 u8 reserved_at_10[0x10];
e281682b 5190
b4ff3a36 5191 u8 reserved_at_20[0x10];
e281682b
SM		 5192 u8 op_mod[0x10];
5193
b4ff3a36 5194 u8 reserved_at_40[0x40];
e281682b
SM		 5195};
5196
5197struct mlx5_ifc_modify_vport_state_out_bits {
5198 u8 status[0x8];
b4ff3a36 5199 u8 reserved_at_8[0x18];
e281682b
SM		 5200
5201 u8 syndrome[0x20];
5202
b4ff3a36 5203 u8 reserved_at_40[0x40];
e281682b
SM		 5204};
5205
5206struct mlx5_ifc_modify_vport_state_in_bits {
5207 u8 opcode[0x10];
b4ff3a36 5208 u8 reserved_at_10[0x10];
e281682b 5209
b4ff3a36 5210 u8 reserved_at_20[0x10];
e281682b
SM		 5211 u8 op_mod[0x10];
5212
5213 u8 other_vport[0x1];
b4ff3a36 5214 u8 reserved_at_41[0xf];
e281682b
SM		 5215 u8 vport_number[0x10];
5216
b4ff3a36 5217 u8 reserved_at_60[0x18];
e281682b 5218 u8 admin_state[0x4];
b4ff3a36 5219 u8 reserved_at_7c[0x4];
e281682b
SM		 5220};
5221
5222struct mlx5_ifc_modify_tis_out_bits {
5223 u8 status[0x8];
b4ff3a36 5224 u8 reserved_at_8[0x18];
e281682b
SM		 5225
5226 u8 syndrome[0x20];
5227
b4ff3a36 5228 u8 reserved_at_40[0x40];
e281682b
SM		 5229};
5230
75850d0b 5231struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5232 u8 reserved_at_0[0x20];
75850d0b 5233
84df61eb
AH		 5234 u8 reserved_at_20[0x1d];
5235 u8 lag_tx_port_affinity[0x1];
5236 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5237 u8 prio[0x1];
5238};
5239
e281682b
SM		 5240struct mlx5_ifc_modify_tis_in_bits {
5241 u8 opcode[0x10];
b4ff3a36 5242 u8 reserved_at_10[0x10];
e281682b 5243
b4ff3a36 5244 u8 reserved_at_20[0x10];
e281682b
SM		 5245 u8 op_mod[0x10];
5246
b4ff3a36 5247 u8 reserved_at_40[0x8];
e281682b
SM		 5248 u8 tisn[0x18];
5249
b4ff3a36 5250 u8 reserved_at_60[0x20];
e281682b 5251
75850d0b 5252 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5253
b4ff3a36 5254 u8 reserved_at_c0[0x40];
e281682b
SM		 5255
5256 struct mlx5_ifc_tisc_bits ctx;
5257};
5258
d9eea403 5259struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5260 u8 reserved_at_0[0x20];
d9eea403 5261
b4ff3a36 5262 u8 reserved_at_20[0x1b];
66189961 5263 u8 self_lb_en[0x1];
bdfc028d
TT		 5264 u8 reserved_at_3c[0x1];
5265 u8 hash[0x1];
5266 u8 reserved_at_3e[0x1];
d9eea403
AS		 5267 u8 lro[0x1];
5268};
5269
e281682b
SM		 5270struct mlx5_ifc_modify_tir_out_bits {
5271 u8 status[0x8];
b4ff3a36 5272 u8 reserved_at_8[0x18];
e281682b
SM		 5273
5274 u8 syndrome[0x20];
5275
b4ff3a36 5276 u8 reserved_at_40[0x40];
e281682b
SM		 5277};
5278
5279struct mlx5_ifc_modify_tir_in_bits {
5280 u8 opcode[0x10];
b4ff3a36 5281 u8 reserved_at_10[0x10];
e281682b 5282
b4ff3a36 5283 u8 reserved_at_20[0x10];
e281682b
SM		 5284 u8 op_mod[0x10];
5285
b4ff3a36 5286 u8 reserved_at_40[0x8];
e281682b
SM		 5287 u8 tirn[0x18];
5288
b4ff3a36 5289 u8 reserved_at_60[0x20];
e281682b 5290
d9eea403 5291 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5292
b4ff3a36 5293 u8 reserved_at_c0[0x40];
e281682b
SM		 5294
5295 struct mlx5_ifc_tirc_bits ctx;
5296};
5297
5298struct mlx5_ifc_modify_sq_out_bits {
5299 u8 status[0x8];
b4ff3a36 5300 u8 reserved_at_8[0x18];
e281682b
SM		 5301
5302 u8 syndrome[0x20];
5303
b4ff3a36 5304 u8 reserved_at_40[0x40];
e281682b
SM		 5305};
5306
5307struct mlx5_ifc_modify_sq_in_bits {
5308 u8 opcode[0x10];
b4ff3a36 5309 u8 reserved_at_10[0x10];
e281682b 5310
b4ff3a36 5311 u8 reserved_at_20[0x10];
e281682b
SM		 5312 u8 op_mod[0x10];
5313
5314 u8 sq_state[0x4];
b4ff3a36 5315 u8 reserved_at_44[0x4];
e281682b
SM		 5316 u8 sqn[0x18];
5317
b4ff3a36 5318 u8 reserved_at_60[0x20];
e281682b
SM		 5319
5320 u8 modify_bitmask[0x40];
5321
b4ff3a36 5322 u8 reserved_at_c0[0x40];
e281682b
SM		 5323
5324 struct mlx5_ifc_sqc_bits ctx;
5325};
5326
813f8540
MHY		 5327struct mlx5_ifc_modify_scheduling_element_out_bits {
5328 u8 status[0x8];
5329 u8 reserved_at_8[0x18];
5330
5331 u8 syndrome[0x20];
5332
5333 u8 reserved_at_40[0x1c0];
5334};
5335
5336enum {
5337 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5338 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5339};
5340
5341struct mlx5_ifc_modify_scheduling_element_in_bits {
5342 u8 opcode[0x10];
5343 u8 reserved_at_10[0x10];
5344
5345 u8 reserved_at_20[0x10];
5346 u8 op_mod[0x10];
5347
5348 u8 scheduling_hierarchy[0x8];
5349 u8 reserved_at_48[0x18];
5350
5351 u8 scheduling_element_id[0x20];
5352
5353 u8 reserved_at_80[0x20];
5354
5355 u8 modify_bitmask[0x20];
5356
5357 u8 reserved_at_c0[0x40];
5358
5359 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5360
5361 u8 reserved_at_300[0x100];
5362};
5363
e281682b
SM		 5364struct mlx5_ifc_modify_rqt_out_bits {
5365 u8 status[0x8];
b4ff3a36 5366 u8 reserved_at_8[0x18];
e281682b
SM		 5367
5368 u8 syndrome[0x20];
5369
b4ff3a36 5370 u8 reserved_at_40[0x40];
e281682b
SM		 5371};
5372
5c50368f 5373struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5374 u8 reserved_at_0[0x20];
5c50368f 5375
b4ff3a36 5376 u8 reserved_at_20[0x1f];
5c50368f
AS		 5377 u8 rqn_list[0x1];
5378};
5379
e281682b
SM		 5380struct mlx5_ifc_modify_rqt_in_bits {
5381 u8 opcode[0x10];
b4ff3a36 5382 u8 reserved_at_10[0x10];
e281682b 5383
b4ff3a36 5384 u8 reserved_at_20[0x10];
e281682b
SM		 5385 u8 op_mod[0x10];
5386
b4ff3a36 5387 u8 reserved_at_40[0x8];
e281682b
SM		 5388 u8 rqtn[0x18];
5389
b4ff3a36 5390 u8 reserved_at_60[0x20];
e281682b 5391
5c50368f 5392 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5393
b4ff3a36 5394 u8 reserved_at_c0[0x40];
e281682b
SM		 5395
5396 struct mlx5_ifc_rqtc_bits ctx;
5397};
5398
5399struct mlx5_ifc_modify_rq_out_bits {
5400 u8 status[0x8];
b4ff3a36 5401 u8 reserved_at_8[0x18];
e281682b
SM		 5402
5403 u8 syndrome[0x20];
5404
b4ff3a36 5405 u8 reserved_at_40[0x40];
e281682b
SM		 5406};
5407
83b502a1
AV		 5408enum {
5409 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5410 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5411 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5412};
5413
e281682b
SM		 5414struct mlx5_ifc_modify_rq_in_bits {
5415 u8 opcode[0x10];
b4ff3a36 5416 u8 reserved_at_10[0x10];
e281682b 5417
b4ff3a36 5418 u8 reserved_at_20[0x10];
e281682b
SM		 5419 u8 op_mod[0x10];
5420
5421 u8 rq_state[0x4];
b4ff3a36 5422 u8 reserved_at_44[0x4];
e281682b
SM		 5423 u8 rqn[0x18];
5424
b4ff3a36 5425 u8 reserved_at_60[0x20];
e281682b
SM		 5426
5427 u8 modify_bitmask[0x40];
5428
b4ff3a36 5429 u8 reserved_at_c0[0x40];
e281682b
SM		 5430
5431 struct mlx5_ifc_rqc_bits ctx;
5432};
5433
5434struct mlx5_ifc_modify_rmp_out_bits {
5435 u8 status[0x8];
b4ff3a36 5436 u8 reserved_at_8[0x18];
e281682b
SM		 5437
5438 u8 syndrome[0x20];
5439
b4ff3a36 5440 u8 reserved_at_40[0x40];
e281682b
SM		 5441};
5442
01949d01 5443struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5444 u8 reserved_at_0[0x20];
01949d01 5445
b4ff3a36 5446 u8 reserved_at_20[0x1f];
01949d01
HA		 5447 u8 lwm[0x1];
5448};
5449
e281682b
SM		 5450struct mlx5_ifc_modify_rmp_in_bits {
5451 u8 opcode[0x10];
b4ff3a36 5452 u8 reserved_at_10[0x10];
e281682b 5453
b4ff3a36 5454 u8 reserved_at_20[0x10];
e281682b
SM		 5455 u8 op_mod[0x10];
5456
5457 u8 rmp_state[0x4];
b4ff3a36 5458 u8 reserved_at_44[0x4];
e281682b
SM		 5459 u8 rmpn[0x18];
5460
b4ff3a36 5461 u8 reserved_at_60[0x20];
e281682b 5462
01949d01 5463 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5464
b4ff3a36 5465 u8 reserved_at_c0[0x40];
e281682b
SM		 5466
5467 struct mlx5_ifc_rmpc_bits ctx;
5468};
5469
5470struct mlx5_ifc_modify_nic_vport_context_out_bits {
5471 u8 status[0x8];
b4ff3a36 5472 u8 reserved_at_8[0x18];
e281682b
SM		 5473
5474 u8 syndrome[0x20];
5475
b4ff3a36 5476 u8 reserved_at_40[0x40];
e281682b
SM		 5477};
5478
5479struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5480 u8 reserved_at_0[0x12];
5481 u8 affiliation[0x1];
5482 u8 reserved_at_e[0x1];
bded747b
HN		 5483 u8 disable_uc_local_lb[0x1];
5484 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5485 u8 node_guid[0x1];
5486 u8 port_guid[0x1];
9def7121 5487 u8 min_inline[0x1];
d82b7318
SM		 5488 u8 mtu[0x1];
5489 u8 change_event[0x1];
5490 u8 promisc[0x1];
e281682b
SM		 5491 u8 permanent_address[0x1];
5492 u8 addresses_list[0x1];
5493 u8 roce_en[0x1];
b4ff3a36 5494 u8 reserved_at_1f[0x1];
e281682b
SM		 5495};
5496
5497struct mlx5_ifc_modify_nic_vport_context_in_bits {
5498 u8 opcode[0x10];
b4ff3a36 5499 u8 reserved_at_10[0x10];
e281682b 5500
b4ff3a36 5501 u8 reserved_at_20[0x10];
e281682b
SM		 5502 u8 op_mod[0x10];
5503
5504 u8 other_vport[0x1];
b4ff3a36 5505 u8 reserved_at_41[0xf];
e281682b
SM		 5506 u8 vport_number[0x10];
5507
5508 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5509
b4ff3a36 5510 u8 reserved_at_80[0x780];
e281682b
SM		 5511
5512 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5513};
5514
5515struct mlx5_ifc_modify_hca_vport_context_out_bits {
5516 u8 status[0x8];
b4ff3a36 5517 u8 reserved_at_8[0x18];
e281682b
SM		 5518
5519 u8 syndrome[0x20];
5520
b4ff3a36 5521 u8 reserved_at_40[0x40];
e281682b
SM		 5522};
5523
5524struct mlx5_ifc_modify_hca_vport_context_in_bits {
5525 u8 opcode[0x10];
b4ff3a36 5526 u8 reserved_at_10[0x10];
e281682b 5527
b4ff3a36 5528 u8 reserved_at_20[0x10];
e281682b
SM		 5529 u8 op_mod[0x10];
5530
5531 u8 other_vport[0x1];
b4ff3a36 5532 u8 reserved_at_41[0xb];
707c4602 5533 u8 port_num[0x4];
e281682b
SM		 5534 u8 vport_number[0x10];
5535
b4ff3a36 5536 u8 reserved_at_60[0x20];
e281682b
SM		 5537
5538 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5539};
5540
5541struct mlx5_ifc_modify_cq_out_bits {
5542 u8 status[0x8];
b4ff3a36 5543 u8 reserved_at_8[0x18];
e281682b
SM		 5544
5545 u8 syndrome[0x20];
5546
b4ff3a36 5547 u8 reserved_at_40[0x40];
e281682b
SM		 5548};
5549
5550enum {
5551 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5552 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5553};
5554
5555struct mlx5_ifc_modify_cq_in_bits {
5556 u8 opcode[0x10];
b4ff3a36 5557 u8 reserved_at_10[0x10];
e281682b 5558
b4ff3a36 5559 u8 reserved_at_20[0x10];
e281682b
SM		 5560 u8 op_mod[0x10];
5561
b4ff3a36 5562 u8 reserved_at_40[0x8];
e281682b
SM		 5563 u8 cqn[0x18];
5564
5565 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5566
5567 struct mlx5_ifc_cqc_bits cq_context;
5568
b4ff3a36 5569 u8 reserved_at_280[0x600];
e281682b
SM		 5570
5571 u8 pas[0][0x40];
5572};
5573
5574struct mlx5_ifc_modify_cong_status_out_bits {
5575 u8 status[0x8];
b4ff3a36 5576 u8 reserved_at_8[0x18];
e281682b
SM		 5577
5578 u8 syndrome[0x20];
5579
b4ff3a36 5580 u8 reserved_at_40[0x40];
e281682b
SM		 5581};
5582
5583struct mlx5_ifc_modify_cong_status_in_bits {
5584 u8 opcode[0x10];
b4ff3a36 5585 u8 reserved_at_10[0x10];
e281682b 5586
b4ff3a36 5587 u8 reserved_at_20[0x10];
e281682b
SM		 5588 u8 op_mod[0x10];
5589
b4ff3a36 5590 u8 reserved_at_40[0x18];
e281682b
SM		 5591 u8 priority[0x4];
5592 u8 cong_protocol[0x4];
5593
5594 u8 enable[0x1];
5595 u8 tag_enable[0x1];
b4ff3a36 5596 u8 reserved_at_62[0x1e];
e281682b
SM		 5597};
5598
5599struct mlx5_ifc_modify_cong_params_out_bits {
5600 u8 status[0x8];
b4ff3a36 5601 u8 reserved_at_8[0x18];
e281682b
SM		 5602
5603 u8 syndrome[0x20];
5604
b4ff3a36 5605 u8 reserved_at_40[0x40];
e281682b
SM		 5606};
5607
5608struct mlx5_ifc_modify_cong_params_in_bits {
5609 u8 opcode[0x10];
b4ff3a36 5610 u8 reserved_at_10[0x10];
e281682b 5611
b4ff3a36 5612 u8 reserved_at_20[0x10];
e281682b
SM		 5613 u8 op_mod[0x10];
5614
b4ff3a36 5615 u8 reserved_at_40[0x1c];
e281682b
SM		 5616 u8 cong_protocol[0x4];
5617
5618 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5619
b4ff3a36 5620 u8 reserved_at_80[0x80];
e281682b
SM		 5621
5622 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5623};
5624
5625struct mlx5_ifc_manage_pages_out_bits {
5626 u8 status[0x8];
b4ff3a36 5627 u8 reserved_at_8[0x18];
e281682b
SM		 5628
5629 u8 syndrome[0x20];
5630
5631 u8 output_num_entries[0x20];
5632
b4ff3a36 5633 u8 reserved_at_60[0x20];
e281682b
SM		 5634
5635 u8 pas[0][0x40];
5636};
5637
5638enum {
5639 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5640 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5641 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5642};
5643
5644struct mlx5_ifc_manage_pages_in_bits {
5645 u8 opcode[0x10];
b4ff3a36 5646 u8 reserved_at_10[0x10];
e281682b 5647
b4ff3a36 5648 u8 reserved_at_20[0x10];
e281682b
SM		 5649 u8 op_mod[0x10];
5650
b4ff3a36 5651 u8 reserved_at_40[0x10];
e281682b
SM		 5652 u8 function_id[0x10];
5653
5654 u8 input_num_entries[0x20];
5655
5656 u8 pas[0][0x40];
5657};
5658
5659struct mlx5_ifc_mad_ifc_out_bits {
5660 u8 status[0x8];
b4ff3a36 5661 u8 reserved_at_8[0x18];
e281682b
SM		 5662
5663 u8 syndrome[0x20];
5664
b4ff3a36 5665 u8 reserved_at_40[0x40];
e281682b
SM		 5666
5667 u8 response_mad_packet[256][0x8];
5668};
5669
5670struct mlx5_ifc_mad_ifc_in_bits {
5671 u8 opcode[0x10];
b4ff3a36 5672 u8 reserved_at_10[0x10];
e281682b 5673
b4ff3a36 5674 u8 reserved_at_20[0x10];
e281682b
SM		 5675 u8 op_mod[0x10];
5676
5677 u8 remote_lid[0x10];
b4ff3a36 5678 u8 reserved_at_50[0x8];
e281682b
SM		 5679 u8 port[0x8];
5680
b4ff3a36 5681 u8 reserved_at_60[0x20];
e281682b
SM		 5682
5683 u8 mad[256][0x8];
5684};
5685
5686struct mlx5_ifc_init_hca_out_bits {
5687 u8 status[0x8];
b4ff3a36 5688 u8 reserved_at_8[0x18];
e281682b
SM		 5689
5690 u8 syndrome[0x20];
5691
b4ff3a36 5692 u8 reserved_at_40[0x40];
e281682b
SM		 5693};
5694
5695struct mlx5_ifc_init_hca_in_bits {
5696 u8 opcode[0x10];
b4ff3a36 5697 u8 reserved_at_10[0x10];
e281682b 5698
b4ff3a36 5699 u8 reserved_at_20[0x10];
e281682b
SM		 5700 u8 op_mod[0x10];
5701
b4ff3a36 5702 u8 reserved_at_40[0x40];
8737f818 5703 u8 sw_owner_id[4][0x20];
e281682b
SM		 5704};
5705
5706struct mlx5_ifc_init2rtr_qp_out_bits {
5707 u8 status[0x8];
b4ff3a36 5708 u8 reserved_at_8[0x18];
e281682b
SM		 5709
5710 u8 syndrome[0x20];
5711
b4ff3a36 5712 u8 reserved_at_40[0x40];
e281682b
SM		 5713};
5714
5715struct mlx5_ifc_init2rtr_qp_in_bits {
5716 u8 opcode[0x10];
b4ff3a36 5717 u8 reserved_at_10[0x10];
e281682b 5718
b4ff3a36 5719 u8 reserved_at_20[0x10];
e281682b
SM		 5720 u8 op_mod[0x10];
5721
b4ff3a36 5722 u8 reserved_at_40[0x8];
e281682b
SM		 5723 u8 qpn[0x18];
5724
b4ff3a36 5725 u8 reserved_at_60[0x20];
e281682b
SM		 5726
5727 u8 opt_param_mask[0x20];
5728
b4ff3a36 5729 u8 reserved_at_a0[0x20];
e281682b
SM		 5730
5731 struct mlx5_ifc_qpc_bits qpc;
5732
b4ff3a36 5733 u8 reserved_at_800[0x80];
e281682b
SM		 5734};
5735
5736struct mlx5_ifc_init2init_qp_out_bits {
5737 u8 status[0x8];
b4ff3a36 5738 u8 reserved_at_8[0x18];
e281682b
SM		 5739
5740 u8 syndrome[0x20];
5741
b4ff3a36 5742 u8 reserved_at_40[0x40];
e281682b
SM		 5743};
5744
5745struct mlx5_ifc_init2init_qp_in_bits {
5746 u8 opcode[0x10];
b4ff3a36 5747 u8 reserved_at_10[0x10];
e281682b 5748
b4ff3a36 5749 u8 reserved_at_20[0x10];
e281682b
SM		 5750 u8 op_mod[0x10];
5751
b4ff3a36 5752 u8 reserved_at_40[0x8];
e281682b
SM		 5753 u8 qpn[0x18];
5754
b4ff3a36 5755 u8 reserved_at_60[0x20];
e281682b
SM		 5756
5757 u8 opt_param_mask[0x20];
5758
b4ff3a36 5759 u8 reserved_at_a0[0x20];
e281682b
SM		 5760
5761 struct mlx5_ifc_qpc_bits qpc;
5762
b4ff3a36 5763 u8 reserved_at_800[0x80];
e281682b
SM		 5764};
5765
5766struct mlx5_ifc_get_dropped_packet_log_out_bits {
5767 u8 status[0x8];
b4ff3a36 5768 u8 reserved_at_8[0x18];
e281682b
SM		 5769
5770 u8 syndrome[0x20];
5771
b4ff3a36 5772 u8 reserved_at_40[0x40];
e281682b
SM		 5773
5774 u8 packet_headers_log[128][0x8];
5775
5776 u8 packet_syndrome[64][0x8];
5777};
5778
5779struct mlx5_ifc_get_dropped_packet_log_in_bits {
5780 u8 opcode[0x10];
b4ff3a36 5781 u8 reserved_at_10[0x10];
e281682b 5782
b4ff3a36 5783 u8 reserved_at_20[0x10];
e281682b
SM		 5784 u8 op_mod[0x10];
5785
b4ff3a36 5786 u8 reserved_at_40[0x40];
e281682b
SM		 5787};
5788
5789struct mlx5_ifc_gen_eqe_in_bits {
5790 u8 opcode[0x10];
b4ff3a36 5791 u8 reserved_at_10[0x10];
e281682b 5792
b4ff3a36 5793 u8 reserved_at_20[0x10];
e281682b
SM		 5794 u8 op_mod[0x10];
5795
b4ff3a36 5796 u8 reserved_at_40[0x18];
e281682b
SM		 5797 u8 eq_number[0x8];
5798
b4ff3a36 5799 u8 reserved_at_60[0x20];
e281682b
SM		 5800
5801 u8 eqe[64][0x8];
5802};
5803
5804struct mlx5_ifc_gen_eq_out_bits {
5805 u8 status[0x8];
b4ff3a36 5806 u8 reserved_at_8[0x18];
e281682b
SM		 5807
5808 u8 syndrome[0x20];
5809
b4ff3a36 5810 u8 reserved_at_40[0x40];
e281682b
SM		 5811};
5812
5813struct mlx5_ifc_enable_hca_out_bits {
5814 u8 status[0x8];
b4ff3a36 5815 u8 reserved_at_8[0x18];
e281682b
SM		 5816
5817 u8 syndrome[0x20];
5818
b4ff3a36 5819 u8 reserved_at_40[0x20];
e281682b
SM		 5820};
5821
5822struct mlx5_ifc_enable_hca_in_bits {
5823 u8 opcode[0x10];
b4ff3a36 5824 u8 reserved_at_10[0x10];
e281682b 5825
b4ff3a36 5826 u8 reserved_at_20[0x10];
e281682b
SM		 5827 u8 op_mod[0x10];
5828
b4ff3a36 5829 u8 reserved_at_40[0x10];
e281682b
SM		 5830 u8 function_id[0x10];
5831
b4ff3a36 5832 u8 reserved_at_60[0x20];
e281682b
SM		 5833};
5834
5835struct mlx5_ifc_drain_dct_out_bits {
5836 u8 status[0x8];
b4ff3a36 5837 u8 reserved_at_8[0x18];
e281682b
SM		 5838
5839 u8 syndrome[0x20];
5840
b4ff3a36 5841 u8 reserved_at_40[0x40];
e281682b
SM		 5842};
5843
5844struct mlx5_ifc_drain_dct_in_bits {
5845 u8 opcode[0x10];
b4ff3a36 5846 u8 reserved_at_10[0x10];
e281682b 5847
b4ff3a36 5848 u8 reserved_at_20[0x10];
e281682b
SM		 5849 u8 op_mod[0x10];
5850
b4ff3a36 5851 u8 reserved_at_40[0x8];
e281682b
SM		 5852 u8 dctn[0x18];
5853
b4ff3a36 5854 u8 reserved_at_60[0x20];
e281682b
SM		 5855};
5856
5857struct mlx5_ifc_disable_hca_out_bits {
5858 u8 status[0x8];
b4ff3a36 5859 u8 reserved_at_8[0x18];
e281682b
SM		 5860
5861 u8 syndrome[0x20];
5862
b4ff3a36 5863 u8 reserved_at_40[0x20];
e281682b
SM		 5864};
5865
5866struct mlx5_ifc_disable_hca_in_bits {
5867 u8 opcode[0x10];
b4ff3a36 5868 u8 reserved_at_10[0x10];
e281682b 5869
b4ff3a36 5870 u8 reserved_at_20[0x10];
e281682b
SM		 5871 u8 op_mod[0x10];
5872
b4ff3a36 5873 u8 reserved_at_40[0x10];
e281682b
SM		 5874 u8 function_id[0x10];
5875
b4ff3a36 5876 u8 reserved_at_60[0x20];
e281682b
SM		 5877};
5878
5879struct mlx5_ifc_detach_from_mcg_out_bits {
5880 u8 status[0x8];
b4ff3a36 5881 u8 reserved_at_8[0x18];
e281682b
SM		 5882
5883 u8 syndrome[0x20];
5884
b4ff3a36 5885 u8 reserved_at_40[0x40];
e281682b
SM		 5886};
5887
5888struct mlx5_ifc_detach_from_mcg_in_bits {
5889 u8 opcode[0x10];
b4ff3a36 5890 u8 reserved_at_10[0x10];
e281682b 5891
b4ff3a36 5892 u8 reserved_at_20[0x10];
e281682b
SM		 5893 u8 op_mod[0x10];
5894
b4ff3a36 5895 u8 reserved_at_40[0x8];
e281682b
SM		 5896 u8 qpn[0x18];
5897
b4ff3a36 5898 u8 reserved_at_60[0x20];
e281682b
SM		 5899
5900 u8 multicast_gid[16][0x8];
5901};
5902
7486216b
SM		 5903struct mlx5_ifc_destroy_xrq_out_bits {
5904 u8 status[0x8];
5905 u8 reserved_at_8[0x18];
5906
5907 u8 syndrome[0x20];
5908
5909 u8 reserved_at_40[0x40];
5910};
5911
5912struct mlx5_ifc_destroy_xrq_in_bits {
5913 u8 opcode[0x10];
5914 u8 reserved_at_10[0x10];
5915
5916 u8 reserved_at_20[0x10];
5917 u8 op_mod[0x10];
5918
5919 u8 reserved_at_40[0x8];
5920 u8 xrqn[0x18];
5921
5922 u8 reserved_at_60[0x20];
5923};
5924
e281682b
SM		 5925struct mlx5_ifc_destroy_xrc_srq_out_bits {
5926 u8 status[0x8];
b4ff3a36 5927 u8 reserved_at_8[0x18];
e281682b
SM		 5928
5929 u8 syndrome[0x20];
5930
b4ff3a36 5931 u8 reserved_at_40[0x40];
e281682b
SM		 5932};
5933
5934struct mlx5_ifc_destroy_xrc_srq_in_bits {
5935 u8 opcode[0x10];
b4ff3a36 5936 u8 reserved_at_10[0x10];
e281682b 5937
b4ff3a36 5938 u8 reserved_at_20[0x10];
e281682b
SM		 5939 u8 op_mod[0x10];
5940
b4ff3a36 5941 u8 reserved_at_40[0x8];
e281682b
SM		 5942 u8 xrc_srqn[0x18];
5943
b4ff3a36 5944 u8 reserved_at_60[0x20];
e281682b
SM		 5945};
5946
5947struct mlx5_ifc_destroy_tis_out_bits {
5948 u8 status[0x8];
b4ff3a36 5949 u8 reserved_at_8[0x18];
e281682b
SM		 5950
5951 u8 syndrome[0x20];
5952
b4ff3a36 5953 u8 reserved_at_40[0x40];
e281682b
SM		 5954};
5955
5956struct mlx5_ifc_destroy_tis_in_bits {
5957 u8 opcode[0x10];
b4ff3a36 5958 u8 reserved_at_10[0x10];
e281682b 5959
b4ff3a36 5960 u8 reserved_at_20[0x10];
e281682b
SM		 5961 u8 op_mod[0x10];
5962
b4ff3a36 5963 u8 reserved_at_40[0x8];
e281682b
SM		 5964 u8 tisn[0x18];
5965
b4ff3a36 5966 u8 reserved_at_60[0x20];
e281682b
SM		 5967};
5968
5969struct mlx5_ifc_destroy_tir_out_bits {
5970 u8 status[0x8];
b4ff3a36 5971 u8 reserved_at_8[0x18];
e281682b
SM		 5972
5973 u8 syndrome[0x20];
5974
b4ff3a36 5975 u8 reserved_at_40[0x40];
e281682b
SM		 5976};
5977
5978struct mlx5_ifc_destroy_tir_in_bits {
5979 u8 opcode[0x10];
b4ff3a36 5980 u8 reserved_at_10[0x10];
e281682b 5981
b4ff3a36 5982 u8 reserved_at_20[0x10];
e281682b
SM		 5983 u8 op_mod[0x10];
5984
b4ff3a36 5985 u8 reserved_at_40[0x8];
e281682b
SM		 5986 u8 tirn[0x18];
5987
b4ff3a36 5988 u8 reserved_at_60[0x20];
e281682b
SM		 5989};
5990
5991struct mlx5_ifc_destroy_srq_out_bits {
5992 u8 status[0x8];
b4ff3a36 5993 u8 reserved_at_8[0x18];
e281682b
SM		 5994
5995 u8 syndrome[0x20];
5996
b4ff3a36 5997 u8 reserved_at_40[0x40];
e281682b
SM		 5998};
5999
6000struct mlx5_ifc_destroy_srq_in_bits {
6001 u8 opcode[0x10];
b4ff3a36 6002 u8 reserved_at_10[0x10];
e281682b 6003
b4ff3a36 6004 u8 reserved_at_20[0x10];
e281682b
SM		 6005 u8 op_mod[0x10];
6006
b4ff3a36 6007 u8 reserved_at_40[0x8];
e281682b
SM		 6008 u8 srqn[0x18];
6009
b4ff3a36 6010 u8 reserved_at_60[0x20];
e281682b
SM		 6011};
6012
6013struct mlx5_ifc_destroy_sq_out_bits {
6014 u8 status[0x8];
b4ff3a36 6015 u8 reserved_at_8[0x18];
e281682b
SM		 6016
6017 u8 syndrome[0x20];
6018
b4ff3a36 6019 u8 reserved_at_40[0x40];
e281682b
SM		 6020};
6021
6022struct mlx5_ifc_destroy_sq_in_bits {
6023 u8 opcode[0x10];
b4ff3a36 6024 u8 reserved_at_10[0x10];
e281682b 6025
b4ff3a36 6026 u8 reserved_at_20[0x10];
e281682b
SM		 6027 u8 op_mod[0x10];
6028
b4ff3a36 6029 u8 reserved_at_40[0x8];
e281682b
SM		 6030 u8 sqn[0x18];
6031
b4ff3a36 6032 u8 reserved_at_60[0x20];
e281682b
SM		 6033};
6034
813f8540
MHY		 6035struct mlx5_ifc_destroy_scheduling_element_out_bits {
6036 u8 status[0x8];
6037 u8 reserved_at_8[0x18];
6038
6039 u8 syndrome[0x20];
6040
6041 u8 reserved_at_40[0x1c0];
6042};
6043
6044struct mlx5_ifc_destroy_scheduling_element_in_bits {
6045 u8 opcode[0x10];
6046 u8 reserved_at_10[0x10];
6047
6048 u8 reserved_at_20[0x10];
6049 u8 op_mod[0x10];
6050
6051 u8 scheduling_hierarchy[0x8];
6052 u8 reserved_at_48[0x18];
6053
6054 u8 scheduling_element_id[0x20];
6055
6056 u8 reserved_at_80[0x180];
6057};
6058
e281682b
SM		 6059struct mlx5_ifc_destroy_rqt_out_bits {
6060 u8 status[0x8];
b4ff3a36 6061 u8 reserved_at_8[0x18];
e281682b
SM		 6062
6063 u8 syndrome[0x20];
6064
b4ff3a36 6065 u8 reserved_at_40[0x40];
e281682b
SM		 6066};
6067
6068struct mlx5_ifc_destroy_rqt_in_bits {
6069 u8 opcode[0x10];
b4ff3a36 6070 u8 reserved_at_10[0x10];
e281682b 6071
b4ff3a36 6072 u8 reserved_at_20[0x10];
e281682b
SM		 6073 u8 op_mod[0x10];
6074
b4ff3a36 6075 u8 reserved_at_40[0x8];
e281682b
SM		 6076 u8 rqtn[0x18];
6077
b4ff3a36 6078 u8 reserved_at_60[0x20];
e281682b
SM		 6079};
6080
6081struct mlx5_ifc_destroy_rq_out_bits {
6082 u8 status[0x8];
b4ff3a36 6083 u8 reserved_at_8[0x18];
e281682b
SM		 6084
6085 u8 syndrome[0x20];
6086
b4ff3a36 6087 u8 reserved_at_40[0x40];
e281682b
SM		 6088};
6089
6090struct mlx5_ifc_destroy_rq_in_bits {
6091 u8 opcode[0x10];
b4ff3a36 6092 u8 reserved_at_10[0x10];
e281682b 6093
b4ff3a36 6094 u8 reserved_at_20[0x10];
e281682b
SM		 6095 u8 op_mod[0x10];
6096
b4ff3a36 6097 u8 reserved_at_40[0x8];
e281682b
SM		 6098 u8 rqn[0x18];
6099
b4ff3a36 6100 u8 reserved_at_60[0x20];
e281682b
SM		 6101};
6102
c1e0bfc1
MG		 6103struct mlx5_ifc_set_delay_drop_params_in_bits {
6104 u8 opcode[0x10];
6105 u8 reserved_at_10[0x10];
6106
6107 u8 reserved_at_20[0x10];
6108 u8 op_mod[0x10];
6109
6110 u8 reserved_at_40[0x20];
6111
6112 u8 reserved_at_60[0x10];
6113 u8 delay_drop_timeout[0x10];
6114};
6115
6116struct mlx5_ifc_set_delay_drop_params_out_bits {
6117 u8 status[0x8];
6118 u8 reserved_at_8[0x18];
6119
6120 u8 syndrome[0x20];
6121
6122 u8 reserved_at_40[0x40];
6123};
6124
e281682b
SM		 6125struct mlx5_ifc_destroy_rmp_out_bits {
6126 u8 status[0x8];
b4ff3a36 6127 u8 reserved_at_8[0x18];
e281682b
SM		 6128
6129 u8 syndrome[0x20];
6130
b4ff3a36 6131 u8 reserved_at_40[0x40];
e281682b
SM		 6132};
6133
6134struct mlx5_ifc_destroy_rmp_in_bits {
6135 u8 opcode[0x10];
b4ff3a36 6136 u8 reserved_at_10[0x10];
e281682b 6137
b4ff3a36 6138 u8 reserved_at_20[0x10];
e281682b
SM		 6139 u8 op_mod[0x10];
6140
b4ff3a36 6141 u8 reserved_at_40[0x8];
e281682b
SM		 6142 u8 rmpn[0x18];
6143
b4ff3a36 6144 u8 reserved_at_60[0x20];
e281682b
SM		 6145};
6146
6147struct mlx5_ifc_destroy_qp_out_bits {
6148 u8 status[0x8];
b4ff3a36 6149 u8 reserved_at_8[0x18];
e281682b
SM		 6150
6151 u8 syndrome[0x20];
6152
b4ff3a36 6153 u8 reserved_at_40[0x40];
e281682b
SM		 6154};
6155
6156struct mlx5_ifc_destroy_qp_in_bits {
6157 u8 opcode[0x10];
b4ff3a36 6158 u8 reserved_at_10[0x10];
e281682b 6159
b4ff3a36 6160 u8 reserved_at_20[0x10];
e281682b
SM		 6161 u8 op_mod[0x10];
6162
b4ff3a36 6163 u8 reserved_at_40[0x8];
e281682b
SM		 6164 u8 qpn[0x18];
6165
b4ff3a36 6166 u8 reserved_at_60[0x20];
e281682b
SM		 6167};
6168
6169struct mlx5_ifc_destroy_psv_out_bits {
6170 u8 status[0x8];
b4ff3a36 6171 u8 reserved_at_8[0x18];
e281682b
SM		 6172
6173 u8 syndrome[0x20];
6174
b4ff3a36 6175 u8 reserved_at_40[0x40];
e281682b
SM		 6176};
6177
6178struct mlx5_ifc_destroy_psv_in_bits {
6179 u8 opcode[0x10];
b4ff3a36 6180 u8 reserved_at_10[0x10];
e281682b 6181
b4ff3a36 6182 u8 reserved_at_20[0x10];
e281682b
SM		 6183 u8 op_mod[0x10];
6184
b4ff3a36 6185 u8 reserved_at_40[0x8];
e281682b
SM		 6186 u8 psvn[0x18];
6187
b4ff3a36 6188 u8 reserved_at_60[0x20];
e281682b
SM		 6189};
6190
6191struct mlx5_ifc_destroy_mkey_out_bits {
6192 u8 status[0x8];
b4ff3a36 6193 u8 reserved_at_8[0x18];
e281682b
SM		 6194
6195 u8 syndrome[0x20];
6196
b4ff3a36 6197 u8 reserved_at_40[0x40];
e281682b
SM		 6198};
6199
6200struct mlx5_ifc_destroy_mkey_in_bits {
6201 u8 opcode[0x10];
b4ff3a36 6202 u8 reserved_at_10[0x10];
e281682b 6203
b4ff3a36 6204 u8 reserved_at_20[0x10];
e281682b
SM		 6205 u8 op_mod[0x10];
6206
b4ff3a36 6207 u8 reserved_at_40[0x8];
e281682b
SM		 6208 u8 mkey_index[0x18];
6209
b4ff3a36 6210 u8 reserved_at_60[0x20];
e281682b
SM		 6211};
6212
6213struct mlx5_ifc_destroy_flow_table_out_bits {
6214 u8 status[0x8];
b4ff3a36 6215 u8 reserved_at_8[0x18];
e281682b
SM		 6216
6217 u8 syndrome[0x20];
6218
b4ff3a36 6219 u8 reserved_at_40[0x40];
e281682b
SM		 6220};
6221
6222struct mlx5_ifc_destroy_flow_table_in_bits {
6223 u8 opcode[0x10];
b4ff3a36 6224 u8 reserved_at_10[0x10];
e281682b 6225
b4ff3a36 6226 u8 reserved_at_20[0x10];
e281682b
SM		 6227 u8 op_mod[0x10];
6228
7d5e1423
SM		 6229 u8 other_vport[0x1];
6230 u8 reserved_at_41[0xf];
6231 u8 vport_number[0x10];
6232
6233 u8 reserved_at_60[0x20];
e281682b
SM		 6234
6235 u8 table_type[0x8];
b4ff3a36 6236 u8 reserved_at_88[0x18];
e281682b 6237
b4ff3a36 6238 u8 reserved_at_a0[0x8];
e281682b
SM		 6239 u8 table_id[0x18];
6240
b4ff3a36 6241 u8 reserved_at_c0[0x140];
e281682b
SM		 6242};
6243
6244struct mlx5_ifc_destroy_flow_group_out_bits {
6245 u8 status[0x8];
b4ff3a36 6246 u8 reserved_at_8[0x18];
e281682b
SM		 6247
6248 u8 syndrome[0x20];
6249
b4ff3a36 6250 u8 reserved_at_40[0x40];
e281682b
SM		 6251};
6252
6253struct mlx5_ifc_destroy_flow_group_in_bits {
6254 u8 opcode[0x10];
b4ff3a36 6255 u8 reserved_at_10[0x10];
e281682b 6256
b4ff3a36 6257 u8 reserved_at_20[0x10];
e281682b
SM		 6258 u8 op_mod[0x10];
6259
7d5e1423
SM		 6260 u8 other_vport[0x1];
6261 u8 reserved_at_41[0xf];
6262 u8 vport_number[0x10];
6263
6264 u8 reserved_at_60[0x20];
e281682b
SM		 6265
6266 u8 table_type[0x8];
b4ff3a36 6267 u8 reserved_at_88[0x18];
e281682b 6268
b4ff3a36 6269 u8 reserved_at_a0[0x8];
e281682b
SM		 6270 u8 table_id[0x18];
6271
6272 u8 group_id[0x20];
6273
b4ff3a36 6274 u8 reserved_at_e0[0x120];
e281682b
SM		 6275};
6276
6277struct mlx5_ifc_destroy_eq_out_bits {
6278 u8 status[0x8];
b4ff3a36 6279 u8 reserved_at_8[0x18];
e281682b
SM		 6280
6281 u8 syndrome[0x20];
6282
b4ff3a36 6283 u8 reserved_at_40[0x40];
e281682b
SM		 6284};
6285
6286struct mlx5_ifc_destroy_eq_in_bits {
6287 u8 opcode[0x10];
b4ff3a36 6288 u8 reserved_at_10[0x10];
e281682b 6289
b4ff3a36 6290 u8 reserved_at_20[0x10];
e281682b
SM		 6291 u8 op_mod[0x10];
6292
b4ff3a36 6293 u8 reserved_at_40[0x18];
e281682b
SM		 6294 u8 eq_number[0x8];
6295
b4ff3a36 6296 u8 reserved_at_60[0x20];
e281682b
SM		 6297};
6298
6299struct mlx5_ifc_destroy_dct_out_bits {
6300 u8 status[0x8];
b4ff3a36 6301 u8 reserved_at_8[0x18];
e281682b
SM		 6302
6303 u8 syndrome[0x20];
6304
b4ff3a36 6305 u8 reserved_at_40[0x40];
e281682b
SM		 6306};
6307
6308struct mlx5_ifc_destroy_dct_in_bits {
6309 u8 opcode[0x10];
b4ff3a36 6310 u8 reserved_at_10[0x10];
e281682b 6311
b4ff3a36 6312 u8 reserved_at_20[0x10];
e281682b
SM		 6313 u8 op_mod[0x10];
6314
b4ff3a36 6315 u8 reserved_at_40[0x8];
e281682b
SM		 6316 u8 dctn[0x18];
6317
b4ff3a36 6318 u8 reserved_at_60[0x20];
e281682b
SM		 6319};
6320
6321struct mlx5_ifc_destroy_cq_out_bits {
6322 u8 status[0x8];
b4ff3a36 6323 u8 reserved_at_8[0x18];
e281682b
SM		 6324
6325 u8 syndrome[0x20];
6326
b4ff3a36 6327 u8 reserved_at_40[0x40];
e281682b
SM		 6328};
6329
6330struct mlx5_ifc_destroy_cq_in_bits {
6331 u8 opcode[0x10];
b4ff3a36 6332 u8 reserved_at_10[0x10];
e281682b 6333
b4ff3a36 6334 u8 reserved_at_20[0x10];
e281682b
SM		 6335 u8 op_mod[0x10];
6336
b4ff3a36 6337 u8 reserved_at_40[0x8];
e281682b
SM		 6338 u8 cqn[0x18];
6339
b4ff3a36 6340 u8 reserved_at_60[0x20];
e281682b
SM		 6341};
6342
6343struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6344 u8 status[0x8];
b4ff3a36 6345 u8 reserved_at_8[0x18];
e281682b
SM		 6346
6347 u8 syndrome[0x20];
6348
b4ff3a36 6349 u8 reserved_at_40[0x40];
e281682b
SM		 6350};
6351
6352struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6353 u8 opcode[0x10];
b4ff3a36 6354 u8 reserved_at_10[0x10];
e281682b 6355
b4ff3a36 6356 u8 reserved_at_20[0x10];
e281682b
SM		 6357 u8 op_mod[0x10];
6358
b4ff3a36 6359 u8 reserved_at_40[0x20];
e281682b 6360
b4ff3a36 6361 u8 reserved_at_60[0x10];
e281682b
SM		 6362 u8 vxlan_udp_port[0x10];
6363};
6364
6365struct mlx5_ifc_delete_l2_table_entry_out_bits {
6366 u8 status[0x8];
b4ff3a36 6367 u8 reserved_at_8[0x18];
e281682b
SM		 6368
6369 u8 syndrome[0x20];
6370
b4ff3a36 6371 u8 reserved_at_40[0x40];
e281682b
SM		 6372};
6373
6374struct mlx5_ifc_delete_l2_table_entry_in_bits {
6375 u8 opcode[0x10];
b4ff3a36 6376 u8 reserved_at_10[0x10];
e281682b 6377
b4ff3a36 6378 u8 reserved_at_20[0x10];
e281682b
SM		 6379 u8 op_mod[0x10];
6380
b4ff3a36 6381 u8 reserved_at_40[0x60];
e281682b 6382
b4ff3a36 6383 u8 reserved_at_a0[0x8];
e281682b
SM		 6384 u8 table_index[0x18];
6385
b4ff3a36 6386 u8 reserved_at_c0[0x140];
e281682b
SM		 6387};
6388
6389struct mlx5_ifc_delete_fte_out_bits {
6390 u8 status[0x8];
b4ff3a36 6391 u8 reserved_at_8[0x18];
e281682b
SM		 6392
6393 u8 syndrome[0x20];
6394
b4ff3a36 6395 u8 reserved_at_40[0x40];
e281682b
SM		 6396};
6397
6398struct mlx5_ifc_delete_fte_in_bits {
6399 u8 opcode[0x10];
b4ff3a36 6400 u8 reserved_at_10[0x10];
e281682b 6401
b4ff3a36 6402 u8 reserved_at_20[0x10];
e281682b
SM		 6403 u8 op_mod[0x10];
6404
7d5e1423
SM		 6405 u8 other_vport[0x1];
6406 u8 reserved_at_41[0xf];
6407 u8 vport_number[0x10];
6408
6409 u8 reserved_at_60[0x20];
e281682b
SM		 6410
6411 u8 table_type[0x8];
b4ff3a36 6412 u8 reserved_at_88[0x18];
e281682b 6413
b4ff3a36 6414 u8 reserved_at_a0[0x8];
e281682b
SM		 6415 u8 table_id[0x18];
6416
b4ff3a36 6417 u8 reserved_at_c0[0x40];
e281682b
SM		 6418
6419 u8 flow_index[0x20];
6420
b4ff3a36 6421 u8 reserved_at_120[0xe0];
e281682b
SM		 6422};
6423
6424struct mlx5_ifc_dealloc_xrcd_out_bits {
6425 u8 status[0x8];
b4ff3a36 6426 u8 reserved_at_8[0x18];
e281682b
SM		 6427
6428 u8 syndrome[0x20];
6429
b4ff3a36 6430 u8 reserved_at_40[0x40];
e281682b
SM		 6431};
6432
6433struct mlx5_ifc_dealloc_xrcd_in_bits {
6434 u8 opcode[0x10];
b4ff3a36 6435 u8 reserved_at_10[0x10];
e281682b 6436
b4ff3a36 6437 u8 reserved_at_20[0x10];
e281682b
SM		 6438 u8 op_mod[0x10];
6439
b4ff3a36 6440 u8 reserved_at_40[0x8];
e281682b
SM		 6441 u8 xrcd[0x18];
6442
b4ff3a36 6443 u8 reserved_at_60[0x20];
e281682b
SM		 6444};
6445
6446struct mlx5_ifc_dealloc_uar_out_bits {
6447 u8 status[0x8];
b4ff3a36 6448 u8 reserved_at_8[0x18];
e281682b
SM		 6449
6450 u8 syndrome[0x20];
6451
b4ff3a36 6452 u8 reserved_at_40[0x40];
e281682b
SM		 6453};
6454
6455struct mlx5_ifc_dealloc_uar_in_bits {
6456 u8 opcode[0x10];
b4ff3a36 6457 u8 reserved_at_10[0x10];
e281682b 6458
b4ff3a36 6459 u8 reserved_at_20[0x10];
e281682b
SM		 6460 u8 op_mod[0x10];
6461
b4ff3a36 6462 u8 reserved_at_40[0x8];
e281682b
SM		 6463 u8 uar[0x18];
6464
b4ff3a36 6465 u8 reserved_at_60[0x20];
e281682b
SM		 6466};
6467
6468struct mlx5_ifc_dealloc_transport_domain_out_bits {
6469 u8 status[0x8];
b4ff3a36 6470 u8 reserved_at_8[0x18];
e281682b
SM		 6471
6472 u8 syndrome[0x20];
6473
b4ff3a36 6474 u8 reserved_at_40[0x40];
e281682b
SM		 6475};
6476
6477struct mlx5_ifc_dealloc_transport_domain_in_bits {
6478 u8 opcode[0x10];
b4ff3a36 6479 u8 reserved_at_10[0x10];
e281682b 6480
b4ff3a36 6481 u8 reserved_at_20[0x10];
e281682b
SM		 6482 u8 op_mod[0x10];
6483
b4ff3a36 6484 u8 reserved_at_40[0x8];
e281682b
SM		 6485 u8 transport_domain[0x18];
6486
b4ff3a36 6487 u8 reserved_at_60[0x20];
e281682b
SM		 6488};
6489
6490struct mlx5_ifc_dealloc_q_counter_out_bits {
6491 u8 status[0x8];
b4ff3a36 6492 u8 reserved_at_8[0x18];
e281682b
SM		 6493
6494 u8 syndrome[0x20];
6495
b4ff3a36 6496 u8 reserved_at_40[0x40];
e281682b
SM		 6497};
6498
6499struct mlx5_ifc_dealloc_q_counter_in_bits {
6500 u8 opcode[0x10];
b4ff3a36 6501 u8 reserved_at_10[0x10];
e281682b 6502
b4ff3a36 6503 u8 reserved_at_20[0x10];
e281682b
SM		 6504 u8 op_mod[0x10];
6505
b4ff3a36 6506 u8 reserved_at_40[0x18];
e281682b
SM		 6507 u8 counter_set_id[0x8];
6508
b4ff3a36 6509 u8 reserved_at_60[0x20];
e281682b
SM		 6510};
6511
6512struct mlx5_ifc_dealloc_pd_out_bits {
6513 u8 status[0x8];
b4ff3a36 6514 u8 reserved_at_8[0x18];
e281682b
SM		 6515
6516 u8 syndrome[0x20];
6517
b4ff3a36 6518 u8 reserved_at_40[0x40];
e281682b
SM		 6519};
6520
6521struct mlx5_ifc_dealloc_pd_in_bits {
6522 u8 opcode[0x10];
b4ff3a36 6523 u8 reserved_at_10[0x10];
e281682b 6524
b4ff3a36 6525 u8 reserved_at_20[0x10];
e281682b
SM		 6526 u8 op_mod[0x10];
6527
b4ff3a36 6528 u8 reserved_at_40[0x8];
e281682b
SM		 6529 u8 pd[0x18];
6530
b4ff3a36 6531 u8 reserved_at_60[0x20];
e281682b
SM		 6532};
6533
9dc0b289
AV		 6534struct mlx5_ifc_dealloc_flow_counter_out_bits {
6535 u8 status[0x8];
6536 u8 reserved_at_8[0x18];
6537
6538 u8 syndrome[0x20];
6539
6540 u8 reserved_at_40[0x40];
6541};
6542
6543struct mlx5_ifc_dealloc_flow_counter_in_bits {
6544 u8 opcode[0x10];
6545 u8 reserved_at_10[0x10];
6546
6547 u8 reserved_at_20[0x10];
6548 u8 op_mod[0x10];
6549
a8ffcc74 6550 u8 flow_counter_id[0x20];
9dc0b289
AV		 6551
6552 u8 reserved_at_60[0x20];
6553};
6554
7486216b
SM		 6555struct mlx5_ifc_create_xrq_out_bits {
6556 u8 status[0x8];
6557 u8 reserved_at_8[0x18];
6558
6559 u8 syndrome[0x20];
6560
6561 u8 reserved_at_40[0x8];
6562 u8 xrqn[0x18];
6563
6564 u8 reserved_at_60[0x20];
6565};
6566
6567struct mlx5_ifc_create_xrq_in_bits {
6568 u8 opcode[0x10];
6569 u8 reserved_at_10[0x10];
6570
6571 u8 reserved_at_20[0x10];
6572 u8 op_mod[0x10];
6573
6574 u8 reserved_at_40[0x40];
6575
6576 struct mlx5_ifc_xrqc_bits xrq_context;
6577};
6578
e281682b
SM		 6579struct mlx5_ifc_create_xrc_srq_out_bits {
6580 u8 status[0x8];
b4ff3a36 6581 u8 reserved_at_8[0x18];
e281682b
SM		 6582
6583 u8 syndrome[0x20];
6584
b4ff3a36 6585 u8 reserved_at_40[0x8];
e281682b
SM		 6586 u8 xrc_srqn[0x18];
6587
b4ff3a36 6588 u8 reserved_at_60[0x20];
e281682b
SM		 6589};
6590
6591struct mlx5_ifc_create_xrc_srq_in_bits {
6592 u8 opcode[0x10];
b4ff3a36 6593 u8 reserved_at_10[0x10];
e281682b 6594
b4ff3a36 6595 u8 reserved_at_20[0x10];
e281682b
SM		 6596 u8 op_mod[0x10];
6597
b4ff3a36 6598 u8 reserved_at_40[0x40];
e281682b
SM		 6599
6600 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6601
b4ff3a36 6602 u8 reserved_at_280[0x600];
e281682b
SM		 6603
6604 u8 pas[0][0x40];
6605};
6606
6607struct mlx5_ifc_create_tis_out_bits {
6608 u8 status[0x8];
b4ff3a36 6609 u8 reserved_at_8[0x18];
e281682b
SM		 6610
6611 u8 syndrome[0x20];
6612
b4ff3a36 6613 u8 reserved_at_40[0x8];
e281682b
SM		 6614 u8 tisn[0x18];
6615
b4ff3a36 6616 u8 reserved_at_60[0x20];
e281682b
SM		 6617};
6618
6619struct mlx5_ifc_create_tis_in_bits {
6620 u8 opcode[0x10];
b4ff3a36 6621 u8 reserved_at_10[0x10];
e281682b 6622
b4ff3a36 6623 u8 reserved_at_20[0x10];
e281682b
SM		 6624 u8 op_mod[0x10];
6625
b4ff3a36 6626 u8 reserved_at_40[0xc0];
e281682b
SM		 6627
6628 struct mlx5_ifc_tisc_bits ctx;
6629};
6630
6631struct mlx5_ifc_create_tir_out_bits {
6632 u8 status[0x8];
b4ff3a36 6633 u8 reserved_at_8[0x18];
e281682b
SM		 6634
6635 u8 syndrome[0x20];
6636
b4ff3a36 6637 u8 reserved_at_40[0x8];
e281682b
SM		 6638 u8 tirn[0x18];
6639
b4ff3a36 6640 u8 reserved_at_60[0x20];
e281682b
SM		 6641};
6642
6643struct mlx5_ifc_create_tir_in_bits {
6644 u8 opcode[0x10];
b4ff3a36 6645 u8 reserved_at_10[0x10];
e281682b 6646
b4ff3a36 6647 u8 reserved_at_20[0x10];
e281682b
SM		 6648 u8 op_mod[0x10];
6649
b4ff3a36 6650 u8 reserved_at_40[0xc0];
e281682b
SM		 6651
6652 struct mlx5_ifc_tirc_bits ctx;
6653};
6654
6655struct mlx5_ifc_create_srq_out_bits {
6656 u8 status[0x8];
b4ff3a36 6657 u8 reserved_at_8[0x18];
e281682b
SM		 6658
6659 u8 syndrome[0x20];
6660
b4ff3a36 6661 u8 reserved_at_40[0x8];
e281682b
SM		 6662 u8 srqn[0x18];
6663
b4ff3a36 6664 u8 reserved_at_60[0x20];
e281682b
SM		 6665};
6666
6667struct mlx5_ifc_create_srq_in_bits {
6668 u8 opcode[0x10];
b4ff3a36 6669 u8 reserved_at_10[0x10];
e281682b 6670
b4ff3a36 6671 u8 reserved_at_20[0x10];
e281682b
SM		 6672 u8 op_mod[0x10];
6673
b4ff3a36 6674 u8 reserved_at_40[0x40];
e281682b
SM		 6675
6676 struct mlx5_ifc_srqc_bits srq_context_entry;
6677
b4ff3a36 6678 u8 reserved_at_280[0x600];
e281682b
SM		 6679
6680 u8 pas[0][0x40];
6681};
6682
6683struct mlx5_ifc_create_sq_out_bits {
6684 u8 status[0x8];
b4ff3a36 6685 u8 reserved_at_8[0x18];
e281682b
SM		 6686
6687 u8 syndrome[0x20];
6688
b4ff3a36 6689 u8 reserved_at_40[0x8];
e281682b
SM		 6690 u8 sqn[0x18];
6691
b4ff3a36 6692 u8 reserved_at_60[0x20];
e281682b
SM		 6693};
6694
6695struct mlx5_ifc_create_sq_in_bits {
6696 u8 opcode[0x10];
b4ff3a36 6697 u8 reserved_at_10[0x10];
e281682b 6698
b4ff3a36 6699 u8 reserved_at_20[0x10];
e281682b
SM		 6700 u8 op_mod[0x10];
6701
b4ff3a36 6702 u8 reserved_at_40[0xc0];
e281682b
SM		 6703
6704 struct mlx5_ifc_sqc_bits ctx;
6705};
6706
813f8540
MHY		 6707struct mlx5_ifc_create_scheduling_element_out_bits {
6708 u8 status[0x8];
6709 u8 reserved_at_8[0x18];
6710
6711 u8 syndrome[0x20];
6712
6713 u8 reserved_at_40[0x40];
6714
6715 u8 scheduling_element_id[0x20];
6716
6717 u8 reserved_at_a0[0x160];
6718};
6719
6720struct mlx5_ifc_create_scheduling_element_in_bits {
6721 u8 opcode[0x10];
6722 u8 reserved_at_10[0x10];
6723
6724 u8 reserved_at_20[0x10];
6725 u8 op_mod[0x10];
6726
6727 u8 scheduling_hierarchy[0x8];
6728 u8 reserved_at_48[0x18];
6729
6730 u8 reserved_at_60[0xa0];
6731
6732 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6733
6734 u8 reserved_at_300[0x100];
6735};
6736
e281682b
SM		 6737struct mlx5_ifc_create_rqt_out_bits {
6738 u8 status[0x8];
b4ff3a36 6739 u8 reserved_at_8[0x18];
e281682b
SM		 6740
6741 u8 syndrome[0x20];
6742
b4ff3a36 6743 u8 reserved_at_40[0x8];
e281682b
SM		 6744 u8 rqtn[0x18];
6745
b4ff3a36 6746 u8 reserved_at_60[0x20];
e281682b
SM		 6747};
6748
6749struct mlx5_ifc_create_rqt_in_bits {
6750 u8 opcode[0x10];
b4ff3a36 6751 u8 reserved_at_10[0x10];
e281682b 6752
b4ff3a36 6753 u8 reserved_at_20[0x10];
e281682b
SM		 6754 u8 op_mod[0x10];
6755
b4ff3a36 6756 u8 reserved_at_40[0xc0];
e281682b
SM		 6757
6758 struct mlx5_ifc_rqtc_bits rqt_context;
6759};
6760
6761struct mlx5_ifc_create_rq_out_bits {
6762 u8 status[0x8];
b4ff3a36 6763 u8 reserved_at_8[0x18];
e281682b
SM		 6764
6765 u8 syndrome[0x20];
6766
b4ff3a36 6767 u8 reserved_at_40[0x8];
e281682b
SM		 6768 u8 rqn[0x18];
6769
b4ff3a36 6770 u8 reserved_at_60[0x20];
e281682b
SM		 6771};
6772
6773struct mlx5_ifc_create_rq_in_bits {
6774 u8 opcode[0x10];
b4ff3a36 6775 u8 reserved_at_10[0x10];
e281682b 6776
b4ff3a36 6777 u8 reserved_at_20[0x10];
e281682b
SM		 6778 u8 op_mod[0x10];
6779
b4ff3a36 6780 u8 reserved_at_40[0xc0];
e281682b
SM		 6781
6782 struct mlx5_ifc_rqc_bits ctx;
6783};
6784
6785struct mlx5_ifc_create_rmp_out_bits {
6786 u8 status[0x8];
b4ff3a36 6787 u8 reserved_at_8[0x18];
e281682b
SM		 6788
6789 u8 syndrome[0x20];
6790
b4ff3a36 6791 u8 reserved_at_40[0x8];
e281682b
SM		 6792 u8 rmpn[0x18];
6793
b4ff3a36 6794 u8 reserved_at_60[0x20];
e281682b
SM		 6795};
6796
6797struct mlx5_ifc_create_rmp_in_bits {
6798 u8 opcode[0x10];
b4ff3a36 6799 u8 reserved_at_10[0x10];
e281682b 6800
b4ff3a36 6801 u8 reserved_at_20[0x10];
e281682b
SM		 6802 u8 op_mod[0x10];
6803
b4ff3a36 6804 u8 reserved_at_40[0xc0];
e281682b
SM		 6805
6806 struct mlx5_ifc_rmpc_bits ctx;
6807};
6808
6809struct mlx5_ifc_create_qp_out_bits {
6810 u8 status[0x8];
b4ff3a36 6811 u8 reserved_at_8[0x18];
e281682b
SM		 6812
6813 u8 syndrome[0x20];
6814
b4ff3a36 6815 u8 reserved_at_40[0x8];
e281682b
SM		 6816 u8 qpn[0x18];
6817
b4ff3a36 6818 u8 reserved_at_60[0x20];
e281682b
SM		 6819};
6820
6821struct mlx5_ifc_create_qp_in_bits {
6822 u8 opcode[0x10];
b4ff3a36 6823 u8 reserved_at_10[0x10];
e281682b 6824
b4ff3a36 6825 u8 reserved_at_20[0x10];
e281682b
SM		 6826 u8 op_mod[0x10];
6827
b4ff3a36 6828 u8 reserved_at_40[0x40];
e281682b
SM		 6829
6830 u8 opt_param_mask[0x20];
6831
b4ff3a36 6832 u8 reserved_at_a0[0x20];
e281682b
SM		 6833
6834 struct mlx5_ifc_qpc_bits qpc;
6835
b4ff3a36 6836 u8 reserved_at_800[0x80];
e281682b
SM		 6837
6838 u8 pas[0][0x40];
6839};
6840
6841struct mlx5_ifc_create_psv_out_bits {
6842 u8 status[0x8];
b4ff3a36 6843 u8 reserved_at_8[0x18];
e281682b
SM		 6844
6845 u8 syndrome[0x20];
6846
b4ff3a36 6847 u8 reserved_at_40[0x40];
e281682b 6848
b4ff3a36 6849 u8 reserved_at_80[0x8];
e281682b
SM		 6850 u8 psv0_index[0x18];
6851
b4ff3a36 6852 u8 reserved_at_a0[0x8];
e281682b
SM		 6853 u8 psv1_index[0x18];
6854
b4ff3a36 6855 u8 reserved_at_c0[0x8];
e281682b
SM		 6856 u8 psv2_index[0x18];
6857
b4ff3a36 6858 u8 reserved_at_e0[0x8];
e281682b
SM		 6859 u8 psv3_index[0x18];
6860};
6861
6862struct mlx5_ifc_create_psv_in_bits {
6863 u8 opcode[0x10];
b4ff3a36 6864 u8 reserved_at_10[0x10];
e281682b 6865
b4ff3a36 6866 u8 reserved_at_20[0x10];
e281682b
SM		 6867 u8 op_mod[0x10];
6868
6869 u8 num_psv[0x4];
b4ff3a36 6870 u8 reserved_at_44[0x4];
e281682b
SM		 6871 u8 pd[0x18];
6872
b4ff3a36 6873 u8 reserved_at_60[0x20];
e281682b
SM		 6874};
6875
6876struct mlx5_ifc_create_mkey_out_bits {
6877 u8 status[0x8];
b4ff3a36 6878 u8 reserved_at_8[0x18];
e281682b
SM		 6879
6880 u8 syndrome[0x20];
6881
b4ff3a36 6882 u8 reserved_at_40[0x8];
e281682b
SM		 6883 u8 mkey_index[0x18];
6884
b4ff3a36 6885 u8 reserved_at_60[0x20];
e281682b
SM		 6886};
6887
6888struct mlx5_ifc_create_mkey_in_bits {
6889 u8 opcode[0x10];
b4ff3a36 6890 u8 reserved_at_10[0x10];
e281682b 6891
b4ff3a36 6892 u8 reserved_at_20[0x10];
e281682b
SM		 6893 u8 op_mod[0x10];
6894
b4ff3a36 6895 u8 reserved_at_40[0x20];
e281682b
SM		 6896
6897 u8 pg_access[0x1];
b4ff3a36 6898 u8 reserved_at_61[0x1f];
e281682b
SM		 6899
6900 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6901
b4ff3a36 6902 u8 reserved_at_280[0x80];
e281682b
SM		 6903
6904 u8 translations_octword_actual_size[0x20];
6905
b4ff3a36 6906 u8 reserved_at_320[0x560];
e281682b
SM		 6907
6908 u8 klm_pas_mtt[0][0x20];
6909};
6910
6911struct mlx5_ifc_create_flow_table_out_bits {
6912 u8 status[0x8];
b4ff3a36 6913 u8 reserved_at_8[0x18];
e281682b
SM		 6914
6915 u8 syndrome[0x20];
6916
b4ff3a36 6917 u8 reserved_at_40[0x8];
e281682b
SM		 6918 u8 table_id[0x18];
6919
b4ff3a36 6920 u8 reserved_at_60[0x20];
e281682b
SM		 6921};
6922
0c90e9c6
MG		 6923struct mlx5_ifc_flow_table_context_bits {
6924 u8 encap_en[0x1];
6925 u8 decap_en[0x1];
6926 u8 reserved_at_2[0x2];
6927 u8 table_miss_action[0x4];
6928 u8 level[0x8];
6929 u8 reserved_at_10[0x8];
6930 u8 log_size[0x8];
6931
6932 u8 reserved_at_20[0x8];
6933 u8 table_miss_id[0x18];
6934
6935 u8 reserved_at_40[0x8];
6936 u8 lag_master_next_table_id[0x18];
6937
6938 u8 reserved_at_60[0xe0];
6939};
6940
e281682b
SM		 6941struct mlx5_ifc_create_flow_table_in_bits {
6942 u8 opcode[0x10];
b4ff3a36 6943 u8 reserved_at_10[0x10];
e281682b 6944
b4ff3a36 6945 u8 reserved_at_20[0x10];
e281682b
SM		 6946 u8 op_mod[0x10];
6947
7d5e1423
SM		 6948 u8 other_vport[0x1];
6949 u8 reserved_at_41[0xf];
6950 u8 vport_number[0x10];
6951
6952 u8 reserved_at_60[0x20];
e281682b
SM		 6953
6954 u8 table_type[0x8];
b4ff3a36 6955 u8 reserved_at_88[0x18];
e281682b 6956
b4ff3a36 6957 u8 reserved_at_a0[0x20];
e281682b 6958
0c90e9c6 6959 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6960};
6961
6962struct mlx5_ifc_create_flow_group_out_bits {
6963 u8 status[0x8];
b4ff3a36 6964 u8 reserved_at_8[0x18];
e281682b
SM		 6965
6966 u8 syndrome[0x20];
6967
b4ff3a36 6968 u8 reserved_at_40[0x8];
e281682b
SM		 6969 u8 group_id[0x18];
6970
b4ff3a36 6971 u8 reserved_at_60[0x20];
e281682b
SM		 6972};
6973
6974enum {
6975 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6976 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6977 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6978};
6979
6980struct mlx5_ifc_create_flow_group_in_bits {
6981 u8 opcode[0x10];
b4ff3a36 6982 u8 reserved_at_10[0x10];
e281682b 6983
b4ff3a36 6984 u8 reserved_at_20[0x10];
e281682b
SM		 6985 u8 op_mod[0x10];
6986
7d5e1423
SM		 6987 u8 other_vport[0x1];
6988 u8 reserved_at_41[0xf];
6989 u8 vport_number[0x10];
6990
6991 u8 reserved_at_60[0x20];
e281682b
SM		 6992
6993 u8 table_type[0x8];
b4ff3a36 6994 u8 reserved_at_88[0x18];
e281682b 6995
b4ff3a36 6996 u8 reserved_at_a0[0x8];
e281682b
SM		 6997 u8 table_id[0x18];
6998
3e99df87
SK		 6999 u8 source_eswitch_owner_vhca_id_valid[0x1];
7000
7001 u8 reserved_at_c1[0x1f];
e281682b
SM		 7002
7003 u8 start_flow_index[0x20];
7004
b4ff3a36 7005 u8 reserved_at_100[0x20];
e281682b
SM		 7006
7007 u8 end_flow_index[0x20];
7008
b4ff3a36 7009 u8 reserved_at_140[0xa0];
e281682b 7010
b4ff3a36 7011 u8 reserved_at_1e0[0x18];
e281682b
SM		 7012 u8 match_criteria_enable[0x8];
7013
7014 struct mlx5_ifc_fte_match_param_bits match_criteria;
7015
b4ff3a36 7016 u8 reserved_at_1200[0xe00];
e281682b
SM		 7017};
7018
7019struct mlx5_ifc_create_eq_out_bits {
7020 u8 status[0x8];
b4ff3a36 7021 u8 reserved_at_8[0x18];
e281682b
SM		 7022
7023 u8 syndrome[0x20];
7024
b4ff3a36 7025 u8 reserved_at_40[0x18];
e281682b
SM		 7026 u8 eq_number[0x8];
7027
b4ff3a36 7028 u8 reserved_at_60[0x20];
e281682b
SM		 7029};
7030
7031struct mlx5_ifc_create_eq_in_bits {
7032 u8 opcode[0x10];
b4ff3a36 7033 u8 reserved_at_10[0x10];
e281682b 7034
b4ff3a36 7035 u8 reserved_at_20[0x10];
e281682b
SM		 7036 u8 op_mod[0x10];
7037
b4ff3a36 7038 u8 reserved_at_40[0x40];
e281682b
SM		 7039
7040 struct mlx5_ifc_eqc_bits eq_context_entry;
7041
b4ff3a36 7042 u8 reserved_at_280[0x40];
e281682b
SM		 7043
7044 u8 event_bitmask[0x40];
7045
b4ff3a36 7046 u8 reserved_at_300[0x580];
e281682b
SM		 7047
7048 u8 pas[0][0x40];
7049};
7050
7051struct mlx5_ifc_create_dct_out_bits {
7052 u8 status[0x8];
b4ff3a36 7053 u8 reserved_at_8[0x18];
e281682b
SM		 7054
7055 u8 syndrome[0x20];
7056
b4ff3a36 7057 u8 reserved_at_40[0x8];
e281682b
SM		 7058 u8 dctn[0x18];
7059
b4ff3a36 7060 u8 reserved_at_60[0x20];
e281682b
SM		 7061};
7062
7063struct mlx5_ifc_create_dct_in_bits {
7064 u8 opcode[0x10];
b4ff3a36 7065 u8 reserved_at_10[0x10];
e281682b 7066
b4ff3a36 7067 u8 reserved_at_20[0x10];
e281682b
SM		 7068 u8 op_mod[0x10];
7069
b4ff3a36 7070 u8 reserved_at_40[0x40];
e281682b
SM		 7071
7072 struct mlx5_ifc_dctc_bits dct_context_entry;
7073
b4ff3a36 7074 u8 reserved_at_280[0x180];
e281682b
SM		 7075};
7076
7077struct mlx5_ifc_create_cq_out_bits {
7078 u8 status[0x8];
b4ff3a36 7079 u8 reserved_at_8[0x18];
e281682b
SM		 7080
7081 u8 syndrome[0x20];
7082
b4ff3a36 7083 u8 reserved_at_40[0x8];
e281682b
SM		 7084 u8 cqn[0x18];
7085
b4ff3a36 7086 u8 reserved_at_60[0x20];
e281682b
SM		 7087};
7088
7089struct mlx5_ifc_create_cq_in_bits {
7090 u8 opcode[0x10];
b4ff3a36 7091 u8 reserved_at_10[0x10];
e281682b 7092
b4ff3a36 7093 u8 reserved_at_20[0x10];
e281682b
SM		 7094 u8 op_mod[0x10];
7095
b4ff3a36 7096 u8 reserved_at_40[0x40];
e281682b
SM		 7097
7098 struct mlx5_ifc_cqc_bits cq_context;
7099
b4ff3a36 7100 u8 reserved_at_280[0x600];
e281682b
SM		 7101
7102 u8 pas[0][0x40];
7103};
7104
7105struct mlx5_ifc_config_int_moderation_out_bits {
7106 u8 status[0x8];
b4ff3a36 7107 u8 reserved_at_8[0x18];
e281682b
SM		 7108
7109 u8 syndrome[0x20];
7110
b4ff3a36 7111 u8 reserved_at_40[0x4];
e281682b
SM		 7112 u8 min_delay[0xc];
7113 u8 int_vector[0x10];
7114
b4ff3a36 7115 u8 reserved_at_60[0x20];
e281682b
SM		 7116};
7117
7118enum {
7119 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7120 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7121};
7122
7123struct mlx5_ifc_config_int_moderation_in_bits {
7124 u8 opcode[0x10];
b4ff3a36 7125 u8 reserved_at_10[0x10];
e281682b 7126
b4ff3a36 7127 u8 reserved_at_20[0x10];
e281682b
SM		 7128 u8 op_mod[0x10];
7129
b4ff3a36 7130 u8 reserved_at_40[0x4];
e281682b
SM		 7131 u8 min_delay[0xc];
7132 u8 int_vector[0x10];
7133
b4ff3a36 7134 u8 reserved_at_60[0x20];
e281682b
SM		 7135};
7136
7137struct mlx5_ifc_attach_to_mcg_out_bits {
7138 u8 status[0x8];
b4ff3a36 7139 u8 reserved_at_8[0x18];
e281682b
SM		 7140
7141 u8 syndrome[0x20];
7142
b4ff3a36 7143 u8 reserved_at_40[0x40];
e281682b
SM		 7144};
7145
7146struct mlx5_ifc_attach_to_mcg_in_bits {
7147 u8 opcode[0x10];
b4ff3a36 7148 u8 reserved_at_10[0x10];
e281682b 7149
b4ff3a36 7150 u8 reserved_at_20[0x10];
e281682b
SM		 7151 u8 op_mod[0x10];
7152
b4ff3a36 7153 u8 reserved_at_40[0x8];
e281682b
SM		 7154 u8 qpn[0x18];
7155
b4ff3a36 7156 u8 reserved_at_60[0x20];
e281682b
SM		 7157
7158 u8 multicast_gid[16][0x8];
7159};
7160
7486216b
SM		 7161struct mlx5_ifc_arm_xrq_out_bits {
7162 u8 status[0x8];
7163 u8 reserved_at_8[0x18];
7164
7165 u8 syndrome[0x20];
7166
7167 u8 reserved_at_40[0x40];
7168};
7169
7170struct mlx5_ifc_arm_xrq_in_bits {
7171 u8 opcode[0x10];
7172 u8 reserved_at_10[0x10];
7173
7174 u8 reserved_at_20[0x10];
7175 u8 op_mod[0x10];
7176
7177 u8 reserved_at_40[0x8];
7178 u8 xrqn[0x18];
7179
7180 u8 reserved_at_60[0x10];
7181 u8 lwm[0x10];
7182};
7183
e281682b
SM		 7184struct mlx5_ifc_arm_xrc_srq_out_bits {
7185 u8 status[0x8];
b4ff3a36 7186 u8 reserved_at_8[0x18];
e281682b
SM		 7187
7188 u8 syndrome[0x20];
7189
b4ff3a36 7190 u8 reserved_at_40[0x40];
e281682b
SM		 7191};
7192
7193enum {
7194 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7195};
7196
7197struct mlx5_ifc_arm_xrc_srq_in_bits {
7198 u8 opcode[0x10];
b4ff3a36 7199 u8 reserved_at_10[0x10];
e281682b 7200
b4ff3a36 7201 u8 reserved_at_20[0x10];
e281682b
SM		 7202 u8 op_mod[0x10];
7203
b4ff3a36 7204 u8 reserved_at_40[0x8];
e281682b
SM		 7205 u8 xrc_srqn[0x18];
7206
b4ff3a36 7207 u8 reserved_at_60[0x10];
e281682b
SM		 7208 u8 lwm[0x10];
7209};
7210
7211struct mlx5_ifc_arm_rq_out_bits {
7212 u8 status[0x8];
b4ff3a36 7213 u8 reserved_at_8[0x18];
e281682b
SM		 7214
7215 u8 syndrome[0x20];
7216
b4ff3a36 7217 u8 reserved_at_40[0x40];
e281682b
SM		 7218};
7219
7220enum {
7486216b
SM		 7221 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7222 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7223};
7224
7225struct mlx5_ifc_arm_rq_in_bits {
7226 u8 opcode[0x10];
b4ff3a36 7227 u8 reserved_at_10[0x10];
e281682b 7228
b4ff3a36 7229 u8 reserved_at_20[0x10];
e281682b
SM		 7230 u8 op_mod[0x10];
7231
b4ff3a36 7232 u8 reserved_at_40[0x8];
e281682b
SM		 7233 u8 srq_number[0x18];
7234
b4ff3a36 7235 u8 reserved_at_60[0x10];
e281682b
SM		 7236 u8 lwm[0x10];
7237};
7238
7239struct mlx5_ifc_arm_dct_out_bits {
7240 u8 status[0x8];
b4ff3a36 7241 u8 reserved_at_8[0x18];
e281682b
SM		 7242
7243 u8 syndrome[0x20];
7244
b4ff3a36 7245 u8 reserved_at_40[0x40];
e281682b
SM		 7246};
7247
7248struct mlx5_ifc_arm_dct_in_bits {
7249 u8 opcode[0x10];
b4ff3a36 7250 u8 reserved_at_10[0x10];
e281682b 7251
b4ff3a36 7252 u8 reserved_at_20[0x10];
e281682b
SM		 7253 u8 op_mod[0x10];
7254
b4ff3a36 7255 u8 reserved_at_40[0x8];
e281682b
SM		 7256 u8 dct_number[0x18];
7257
b4ff3a36 7258 u8 reserved_at_60[0x20];
e281682b
SM		 7259};
7260
7261struct mlx5_ifc_alloc_xrcd_out_bits {
7262 u8 status[0x8];
b4ff3a36 7263 u8 reserved_at_8[0x18];
e281682b
SM		 7264
7265 u8 syndrome[0x20];
7266
b4ff3a36 7267 u8 reserved_at_40[0x8];
e281682b
SM		 7268 u8 xrcd[0x18];
7269
b4ff3a36 7270 u8 reserved_at_60[0x20];
e281682b
SM		 7271};
7272
7273struct mlx5_ifc_alloc_xrcd_in_bits {
7274 u8 opcode[0x10];
b4ff3a36 7275 u8 reserved_at_10[0x10];
e281682b 7276
b4ff3a36 7277 u8 reserved_at_20[0x10];
e281682b
SM		 7278 u8 op_mod[0x10];
7279
b4ff3a36 7280 u8 reserved_at_40[0x40];
e281682b
SM		 7281};
7282
7283struct mlx5_ifc_alloc_uar_out_bits {
7284 u8 status[0x8];
b4ff3a36 7285 u8 reserved_at_8[0x18];
e281682b
SM		 7286
7287 u8 syndrome[0x20];
7288
b4ff3a36 7289 u8 reserved_at_40[0x8];
e281682b
SM		 7290 u8 uar[0x18];
7291
b4ff3a36 7292 u8 reserved_at_60[0x20];
e281682b
SM		 7293};
7294
7295struct mlx5_ifc_alloc_uar_in_bits {
7296 u8 opcode[0x10];
b4ff3a36 7297 u8 reserved_at_10[0x10];
e281682b 7298
b4ff3a36 7299 u8 reserved_at_20[0x10];
e281682b
SM		 7300 u8 op_mod[0x10];
7301
b4ff3a36 7302 u8 reserved_at_40[0x40];
e281682b
SM		 7303};
7304
7305struct mlx5_ifc_alloc_transport_domain_out_bits {
7306 u8 status[0x8];
b4ff3a36 7307 u8 reserved_at_8[0x18];
e281682b
SM		 7308
7309 u8 syndrome[0x20];
7310
b4ff3a36 7311 u8 reserved_at_40[0x8];
e281682b
SM		 7312 u8 transport_domain[0x18];
7313
b4ff3a36 7314 u8 reserved_at_60[0x20];
e281682b
SM		 7315};
7316
7317struct mlx5_ifc_alloc_transport_domain_in_bits {
7318 u8 opcode[0x10];
b4ff3a36 7319 u8 reserved_at_10[0x10];
e281682b 7320
b4ff3a36 7321 u8 reserved_at_20[0x10];
e281682b
SM		 7322 u8 op_mod[0x10];
7323
b4ff3a36 7324 u8 reserved_at_40[0x40];
e281682b
SM		 7325};
7326
7327struct mlx5_ifc_alloc_q_counter_out_bits {
7328 u8 status[0x8];
b4ff3a36 7329 u8 reserved_at_8[0x18];
e281682b
SM		 7330
7331 u8 syndrome[0x20];
7332
b4ff3a36 7333 u8 reserved_at_40[0x18];
e281682b
SM		 7334 u8 counter_set_id[0x8];
7335
b4ff3a36 7336 u8 reserved_at_60[0x20];
e281682b
SM		 7337};
7338
7339struct mlx5_ifc_alloc_q_counter_in_bits {
7340 u8 opcode[0x10];
b4ff3a36 7341 u8 reserved_at_10[0x10];
e281682b 7342
b4ff3a36 7343 u8 reserved_at_20[0x10];
e281682b
SM		 7344 u8 op_mod[0x10];
7345
b4ff3a36 7346 u8 reserved_at_40[0x40];
e281682b
SM		 7347};
7348
7349struct mlx5_ifc_alloc_pd_out_bits {
7350 u8 status[0x8];
b4ff3a36 7351 u8 reserved_at_8[0x18];
e281682b
SM		 7352
7353 u8 syndrome[0x20];
7354
b4ff3a36 7355 u8 reserved_at_40[0x8];
e281682b
SM		 7356 u8 pd[0x18];
7357
b4ff3a36 7358 u8 reserved_at_60[0x20];
e281682b
SM		 7359};
7360
7361struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7362 u8 opcode[0x10];
7363 u8 reserved_at_10[0x10];
7364
7365 u8 reserved_at_20[0x10];
7366 u8 op_mod[0x10];
7367
7368 u8 reserved_at_40[0x40];
7369};
7370
7371struct mlx5_ifc_alloc_flow_counter_out_bits {
7372 u8 status[0x8];
7373 u8 reserved_at_8[0x18];
7374
7375 u8 syndrome[0x20];
7376
a8ffcc74 7377 u8 flow_counter_id[0x20];
9dc0b289
AV		 7378
7379 u8 reserved_at_60[0x20];
7380};
7381
7382struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7383 u8 opcode[0x10];
b4ff3a36 7384 u8 reserved_at_10[0x10];
e281682b 7385
b4ff3a36 7386 u8 reserved_at_20[0x10];
e281682b
SM		 7387 u8 op_mod[0x10];
7388
b4ff3a36 7389 u8 reserved_at_40[0x40];
e281682b
SM		 7390};
7391
7392struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7393 u8 status[0x8];
b4ff3a36 7394 u8 reserved_at_8[0x18];
e281682b
SM		 7395
7396 u8 syndrome[0x20];
7397
b4ff3a36 7398 u8 reserved_at_40[0x40];
e281682b
SM		 7399};
7400
7401struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7402 u8 opcode[0x10];
b4ff3a36 7403 u8 reserved_at_10[0x10];
e281682b 7404
b4ff3a36 7405 u8 reserved_at_20[0x10];
e281682b
SM		 7406 u8 op_mod[0x10];
7407
b4ff3a36 7408 u8 reserved_at_40[0x20];
e281682b 7409
b4ff3a36 7410 u8 reserved_at_60[0x10];
e281682b
SM		 7411 u8 vxlan_udp_port[0x10];
7412};
7413
37e92a9d 7414struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7415 u8 status[0x8];
7416 u8 reserved_at_8[0x18];
7417
7418 u8 syndrome[0x20];
7419
7420 u8 reserved_at_40[0x40];
7421};
7422
37e92a9d 7423struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7424 u8 opcode[0x10];
7425 u8 reserved_at_10[0x10];
7426
7427 u8 reserved_at_20[0x10];
7428 u8 op_mod[0x10];
7429
7430 u8 reserved_at_40[0x10];
7431 u8 rate_limit_index[0x10];
7432
7433 u8 reserved_at_60[0x20];
7434
7435 u8 rate_limit[0x20];
37e92a9d 7436
05d3ac97
BW		 7437 u8 burst_upper_bound[0x20];
7438
7439 u8 reserved_at_c0[0x10];
7440 u8 typical_packet_size[0x10];
7441
7442 u8 reserved_at_e0[0x120];
7486216b
SM		 7443};
7444
e281682b
SM		 7445struct mlx5_ifc_access_register_out_bits {
7446 u8 status[0x8];
b4ff3a36 7447 u8 reserved_at_8[0x18];
e281682b
SM		 7448
7449 u8 syndrome[0x20];
7450
b4ff3a36 7451 u8 reserved_at_40[0x40];
e281682b
SM		 7452
7453 u8 register_data[0][0x20];
7454};
7455
7456enum {
7457 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7458 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7459};
7460
7461struct mlx5_ifc_access_register_in_bits {
7462 u8 opcode[0x10];
b4ff3a36 7463 u8 reserved_at_10[0x10];
e281682b 7464
b4ff3a36 7465 u8 reserved_at_20[0x10];
e281682b
SM		 7466 u8 op_mod[0x10];
7467
b4ff3a36 7468 u8 reserved_at_40[0x10];
e281682b
SM		 7469 u8 register_id[0x10];
7470
7471 u8 argument[0x20];
7472
7473 u8 register_data[0][0x20];
7474};
7475
7476struct mlx5_ifc_sltp_reg_bits {
7477 u8 status[0x4];
7478 u8 version[0x4];
7479 u8 local_port[0x8];
7480 u8 pnat[0x2];
b4ff3a36 7481 u8 reserved_at_12[0x2];
e281682b 7482 u8 lane[0x4];
b4ff3a36 7483 u8 reserved_at_18[0x8];
e281682b 7484
b4ff3a36 7485 u8 reserved_at_20[0x20];
e281682b 7486
b4ff3a36 7487 u8 reserved_at_40[0x7];
e281682b
SM		 7488 u8 polarity[0x1];
7489 u8 ob_tap0[0x8];
7490 u8 ob_tap1[0x8];
7491 u8 ob_tap2[0x8];
7492
b4ff3a36 7493 u8 reserved_at_60[0xc];
e281682b
SM		 7494 u8 ob_preemp_mode[0x4];
7495 u8 ob_reg[0x8];
7496 u8 ob_bias[0x8];
7497
b4ff3a36 7498 u8 reserved_at_80[0x20];
e281682b
SM		 7499};
7500
7501struct mlx5_ifc_slrg_reg_bits {
7502 u8 status[0x4];
7503 u8 version[0x4];
7504 u8 local_port[0x8];
7505 u8 pnat[0x2];
b4ff3a36 7506 u8 reserved_at_12[0x2];
e281682b 7507 u8 lane[0x4];
b4ff3a36 7508 u8 reserved_at_18[0x8];
e281682b
SM		 7509
7510 u8 time_to_link_up[0x10];
b4ff3a36 7511 u8 reserved_at_30[0xc];
e281682b
SM		 7512 u8 grade_lane_speed[0x4];
7513
7514 u8 grade_version[0x8];
7515 u8 grade[0x18];
7516
b4ff3a36 7517 u8 reserved_at_60[0x4];
e281682b
SM		 7518 u8 height_grade_type[0x4];
7519 u8 height_grade[0x18];
7520
7521 u8 height_dz[0x10];
7522 u8 height_dv[0x10];
7523
b4ff3a36 7524 u8 reserved_at_a0[0x10];
e281682b
SM		 7525 u8 height_sigma[0x10];
7526
b4ff3a36 7527 u8 reserved_at_c0[0x20];
e281682b 7528
b4ff3a36 7529 u8 reserved_at_e0[0x4];
e281682b
SM		 7530 u8 phase_grade_type[0x4];
7531 u8 phase_grade[0x18];
7532
b4ff3a36 7533 u8 reserved_at_100[0x8];
e281682b 7534 u8 phase_eo_pos[0x8];
b4ff3a36 7535 u8 reserved_at_110[0x8];
e281682b
SM		 7536 u8 phase_eo_neg[0x8];
7537
7538 u8 ffe_set_tested[0x10];
7539 u8 test_errors_per_lane[0x10];
7540};
7541
7542struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7543 u8 reserved_at_0[0x8];
e281682b 7544 u8 local_port[0x8];
b4ff3a36 7545 u8 reserved_at_10[0x10];
e281682b 7546
b4ff3a36 7547 u8 reserved_at_20[0x1c];
e281682b
SM		 7548 u8 vl_hw_cap[0x4];
7549
b4ff3a36 7550 u8 reserved_at_40[0x1c];
e281682b
SM		 7551 u8 vl_admin[0x4];
7552
b4ff3a36 7553 u8 reserved_at_60[0x1c];
e281682b
SM		 7554 u8 vl_operational[0x4];
7555};
7556
7557struct mlx5_ifc_pude_reg_bits {
7558 u8 swid[0x8];
7559 u8 local_port[0x8];
b4ff3a36 7560 u8 reserved_at_10[0x4];
e281682b 7561 u8 admin_status[0x4];
b4ff3a36 7562 u8 reserved_at_18[0x4];
e281682b
SM		 7563 u8 oper_status[0x4];
7564
b4ff3a36 7565 u8 reserved_at_20[0x60];
e281682b
SM		 7566};
7567
7568struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7569 u8 reserved_at_0[0x1];
7486216b 7570 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7571 u8 an_disable_cap[0x1];
7572 u8 reserved_at_3[0x5];
e281682b 7573 u8 local_port[0x8];
b4ff3a36 7574 u8 reserved_at_10[0xd];
e281682b
SM		 7575 u8 proto_mask[0x3];
7576
7486216b
SM		 7577 u8 an_status[0x4];
7578 u8 reserved_at_24[0x3c];
e281682b
SM		 7579
7580 u8 eth_proto_capability[0x20];
7581
7582 u8 ib_link_width_capability[0x10];
7583 u8 ib_proto_capability[0x10];
7584
b4ff3a36 7585 u8 reserved_at_a0[0x20];
e281682b
SM		 7586
7587 u8 eth_proto_admin[0x20];
7588
7589 u8 ib_link_width_admin[0x10];
7590 u8 ib_proto_admin[0x10];
7591
b4ff3a36 7592 u8 reserved_at_100[0x20];
e281682b
SM		 7593
7594 u8 eth_proto_oper[0x20];
7595
7596 u8 ib_link_width_oper[0x10];
7597 u8 ib_proto_oper[0x10];
7598
5b4793f8
EBE		 7599 u8 reserved_at_160[0x1c];
7600 u8 connector_type[0x4];
e281682b
SM		 7601
7602 u8 eth_proto_lp_advertise[0x20];
7603
b4ff3a36 7604 u8 reserved_at_1a0[0x60];
e281682b
SM		 7605};
7606
7d5e1423
SM		 7607struct mlx5_ifc_mlcr_reg_bits {
7608 u8 reserved_at_0[0x8];
7609 u8 local_port[0x8];
7610 u8 reserved_at_10[0x20];
7611
7612 u8 beacon_duration[0x10];
7613 u8 reserved_at_40[0x10];
7614
7615 u8 beacon_remain[0x10];
7616};
7617
e281682b 7618struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7619 u8 reserved_at_0[0x20];
e281682b
SM		 7620
7621 u8 algorithm_options[0x10];
b4ff3a36 7622 u8 reserved_at_30[0x4];
e281682b
SM		 7623 u8 repetitions_mode[0x4];
7624 u8 num_of_repetitions[0x8];
7625
7626 u8 grade_version[0x8];
7627 u8 height_grade_type[0x4];
7628 u8 phase_grade_type[0x4];
7629 u8 height_grade_weight[0x8];
7630 u8 phase_grade_weight[0x8];
7631
7632 u8 gisim_measure_bits[0x10];
7633 u8 adaptive_tap_measure_bits[0x10];
7634
7635 u8 ber_bath_high_error_threshold[0x10];
7636 u8 ber_bath_mid_error_threshold[0x10];
7637
7638 u8 ber_bath_low_error_threshold[0x10];
7639 u8 one_ratio_high_threshold[0x10];
7640
7641 u8 one_ratio_high_mid_threshold[0x10];
7642 u8 one_ratio_low_mid_threshold[0x10];
7643
7644 u8 one_ratio_low_threshold[0x10];
7645 u8 ndeo_error_threshold[0x10];
7646
7647 u8 mixer_offset_step_size[0x10];
b4ff3a36 7648 u8 reserved_at_110[0x8];
e281682b
SM		 7649 u8 mix90_phase_for_voltage_bath[0x8];
7650
7651 u8 mixer_offset_start[0x10];
7652 u8 mixer_offset_end[0x10];
7653
b4ff3a36 7654 u8 reserved_at_140[0x15];
e281682b
SM		 7655 u8 ber_test_time[0xb];
7656};
7657
7658struct mlx5_ifc_pspa_reg_bits {
7659 u8 swid[0x8];
7660 u8 local_port[0x8];
7661 u8 sub_port[0x8];
b4ff3a36 7662 u8 reserved_at_18[0x8];
e281682b 7663
b4ff3a36 7664 u8 reserved_at_20[0x20];
e281682b
SM		 7665};
7666
7667struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7668 u8 reserved_at_0[0x8];
e281682b 7669 u8 local_port[0x8];
b4ff3a36 7670 u8 reserved_at_10[0x5];
e281682b 7671 u8 prio[0x3];
b4ff3a36 7672 u8 reserved_at_18[0x6];
e281682b
SM		 7673 u8 mode[0x2];
7674
b4ff3a36 7675 u8 reserved_at_20[0x20];
e281682b 7676
b4ff3a36 7677 u8 reserved_at_40[0x10];
e281682b
SM		 7678 u8 min_threshold[0x10];
7679
b4ff3a36 7680 u8 reserved_at_60[0x10];
e281682b
SM		 7681 u8 max_threshold[0x10];
7682
b4ff3a36 7683 u8 reserved_at_80[0x10];
e281682b
SM		 7684 u8 mark_probability_denominator[0x10];
7685
b4ff3a36 7686 u8 reserved_at_a0[0x60];
e281682b
SM		 7687};
7688
7689struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7690 u8 reserved_at_0[0x8];
e281682b 7691 u8 local_port[0x8];
b4ff3a36 7692 u8 reserved_at_10[0x10];
e281682b 7693
b4ff3a36 7694 u8 reserved_at_20[0x60];
e281682b 7695
b4ff3a36 7696 u8 reserved_at_80[0x1c];
e281682b
SM		 7697 u8 wrps_admin[0x4];
7698
b4ff3a36 7699 u8 reserved_at_a0[0x1c];
e281682b
SM		 7700 u8 wrps_status[0x4];
7701
b4ff3a36 7702 u8 reserved_at_c0[0x8];
e281682b 7703 u8 up_threshold[0x8];
b4ff3a36 7704 u8 reserved_at_d0[0x8];
e281682b
SM		 7705 u8 down_threshold[0x8];
7706
b4ff3a36 7707 u8 reserved_at_e0[0x20];
e281682b 7708
b4ff3a36 7709 u8 reserved_at_100[0x1c];
e281682b
SM		 7710 u8 srps_admin[0x4];
7711
b4ff3a36 7712 u8 reserved_at_120[0x1c];
e281682b
SM		 7713 u8 srps_status[0x4];
7714
b4ff3a36 7715 u8 reserved_at_140[0x40];
e281682b
SM		 7716};
7717
7718struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7719 u8 reserved_at_0[0x8];
e281682b 7720 u8 local_port[0x8];
b4ff3a36 7721 u8 reserved_at_10[0x10];
e281682b 7722
b4ff3a36 7723 u8 reserved_at_20[0x8];
e281682b 7724 u8 lb_cap[0x8];
b4ff3a36 7725 u8 reserved_at_30[0x8];
e281682b
SM		 7726 u8 lb_en[0x8];
7727};
7728
7729struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7730 u8 reserved_at_0[0x8];
e281682b 7731 u8 local_port[0x8];
b4ff3a36 7732 u8 reserved_at_10[0x10];
e281682b 7733
b4ff3a36 7734 u8 reserved_at_20[0x20];
e281682b
SM		 7735
7736 u8 port_profile_mode[0x8];
7737 u8 static_port_profile[0x8];
7738 u8 active_port_profile[0x8];
b4ff3a36 7739 u8 reserved_at_58[0x8];
e281682b
SM		 7740
7741 u8 retransmission_active[0x8];
7742 u8 fec_mode_active[0x18];
7743
b4ff3a36 7744 u8 reserved_at_80[0x20];
e281682b
SM		 7745};
7746
7747struct mlx5_ifc_ppcnt_reg_bits {
7748 u8 swid[0x8];
7749 u8 local_port[0x8];
7750 u8 pnat[0x2];
b4ff3a36 7751 u8 reserved_at_12[0x8];
e281682b
SM		 7752 u8 grp[0x6];
7753
7754 u8 clr[0x1];
b4ff3a36 7755 u8 reserved_at_21[0x1c];
e281682b
SM		 7756 u8 prio_tc[0x3];
7757
7758 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7759};
7760
8ed1a630
GP		 7761struct mlx5_ifc_mpcnt_reg_bits {
7762 u8 reserved_at_0[0x8];
7763 u8 pcie_index[0x8];
7764 u8 reserved_at_10[0xa];
7765 u8 grp[0x6];
7766
7767 u8 clr[0x1];
7768 u8 reserved_at_21[0x1f];
7769
7770 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7771};
7772
e281682b 7773struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7774 u8 reserved_at_0[0x3];
e281682b 7775 u8 single_mac[0x1];
b4ff3a36 7776 u8 reserved_at_4[0x4];
e281682b
SM		 7777 u8 local_port[0x8];
7778 u8 mac_47_32[0x10];
7779
7780 u8 mac_31_0[0x20];
7781
b4ff3a36 7782 u8 reserved_at_40[0x40];
e281682b
SM		 7783};
7784
7785struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7786 u8 reserved_at_0[0x8];
e281682b 7787 u8 local_port[0x8];
b4ff3a36 7788 u8 reserved_at_10[0x10];
e281682b
SM		 7789
7790 u8 max_mtu[0x10];
b4ff3a36 7791 u8 reserved_at_30[0x10];
e281682b
SM		 7792
7793 u8 admin_mtu[0x10];
b4ff3a36 7794 u8 reserved_at_50[0x10];
e281682b
SM		 7795
7796 u8 oper_mtu[0x10];
b4ff3a36 7797 u8 reserved_at_70[0x10];
e281682b
SM		 7798};
7799
7800struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7801 u8 reserved_at_0[0x8];
e281682b 7802 u8 module[0x8];
b4ff3a36 7803 u8 reserved_at_10[0x10];
e281682b 7804
b4ff3a36 7805 u8 reserved_at_20[0x18];
e281682b
SM		 7806 u8 attenuation_5g[0x8];
7807
b4ff3a36 7808 u8 reserved_at_40[0x18];
e281682b
SM		 7809 u8 attenuation_7g[0x8];
7810
b4ff3a36 7811 u8 reserved_at_60[0x18];
e281682b
SM		 7812 u8 attenuation_12g[0x8];
7813};
7814
7815struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7816 u8 reserved_at_0[0x8];
e281682b 7817 u8 module[0x8];
b4ff3a36 7818 u8 reserved_at_10[0xc];
e281682b
SM		 7819 u8 module_status[0x4];
7820
b4ff3a36 7821 u8 reserved_at_20[0x60];
e281682b
SM		 7822};
7823
7824struct mlx5_ifc_pmpc_reg_bits {
7825 u8 module_state_updated[32][0x8];
7826};
7827
7828struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7829 u8 reserved_at_0[0x4];
e281682b
SM		 7830 u8 mlpn_status[0x4];
7831 u8 local_port[0x8];
b4ff3a36 7832 u8 reserved_at_10[0x10];
e281682b
SM		 7833
7834 u8 e[0x1];
b4ff3a36 7835 u8 reserved_at_21[0x1f];
e281682b
SM		 7836};
7837
7838struct mlx5_ifc_pmlp_reg_bits {
7839 u8 rxtx[0x1];
b4ff3a36 7840 u8 reserved_at_1[0x7];
e281682b 7841 u8 local_port[0x8];
b4ff3a36 7842 u8 reserved_at_10[0x8];
e281682b
SM		 7843 u8 width[0x8];
7844
7845 u8 lane0_module_mapping[0x20];
7846
7847 u8 lane1_module_mapping[0x20];
7848
7849 u8 lane2_module_mapping[0x20];
7850
7851 u8 lane3_module_mapping[0x20];
7852
b4ff3a36 7853 u8 reserved_at_a0[0x160];
e281682b
SM		 7854};
7855
7856struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7857 u8 reserved_at_0[0x8];
e281682b 7858 u8 module[0x8];
b4ff3a36 7859 u8 reserved_at_10[0x4];
e281682b 7860 u8 admin_status[0x4];
b4ff3a36 7861 u8 reserved_at_18[0x4];
e281682b
SM		 7862 u8 oper_status[0x4];
7863
7864 u8 ase[0x1];
7865 u8 ee[0x1];
b4ff3a36 7866 u8 reserved_at_22[0x1c];
e281682b
SM		 7867 u8 e[0x2];
7868
b4ff3a36 7869 u8 reserved_at_40[0x40];
e281682b
SM		 7870};
7871
7872struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7873 u8 reserved_at_0[0x4];
e281682b 7874 u8 profile_id[0xc];
b4ff3a36 7875 u8 reserved_at_10[0x4];
e281682b 7876 u8 proto_mask[0x4];
b4ff3a36 7877 u8 reserved_at_18[0x8];
e281682b 7878
b4ff3a36 7879 u8 reserved_at_20[0x10];
e281682b
SM		 7880 u8 lane_speed[0x10];
7881
b4ff3a36 7882 u8 reserved_at_40[0x17];
e281682b
SM		 7883 u8 lpbf[0x1];
7884 u8 fec_mode_policy[0x8];
7885
7886 u8 retransmission_capability[0x8];
7887 u8 fec_mode_capability[0x18];
7888
7889 u8 retransmission_support_admin[0x8];
7890 u8 fec_mode_support_admin[0x18];
7891
7892 u8 retransmission_request_admin[0x8];
7893 u8 fec_mode_request_admin[0x18];
7894
b4ff3a36 7895 u8 reserved_at_c0[0x80];
e281682b
SM		 7896};
7897
7898struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7899 u8 reserved_at_0[0x8];
e281682b 7900 u8 local_port[0x8];
b4ff3a36 7901 u8 reserved_at_10[0x8];
e281682b
SM		 7902 u8 ib_port[0x8];
7903
b4ff3a36 7904 u8 reserved_at_20[0x60];
e281682b
SM		 7905};
7906
7907struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7908 u8 reserved_at_0[0x8];
e281682b 7909 u8 local_port[0x8];
b4ff3a36 7910 u8 reserved_at_10[0xd];
e281682b
SM		 7911 u8 lbf_mode[0x3];
7912
b4ff3a36 7913 u8 reserved_at_20[0x20];
e281682b
SM		 7914};
7915
7916struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7917 u8 reserved_at_0[0x8];
e281682b 7918 u8 local_port[0x8];
b4ff3a36 7919 u8 reserved_at_10[0x10];
e281682b
SM		 7920
7921 u8 dic[0x1];
b4ff3a36 7922 u8 reserved_at_21[0x19];
e281682b 7923 u8 ipg[0x4];
b4ff3a36 7924 u8 reserved_at_3e[0x2];
e281682b
SM		 7925};
7926
7927struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7928 u8 reserved_at_0[0x8];
e281682b 7929 u8 local_port[0x8];
b4ff3a36 7930 u8 reserved_at_10[0x10];
e281682b 7931
b4ff3a36 7932 u8 reserved_at_20[0xe0];
e281682b
SM		 7933
7934 u8 port_filter[8][0x20];
7935
7936 u8 port_filter_update_en[8][0x20];
7937};
7938
7939struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7940 u8 reserved_at_0[0x8];
e281682b 7941 u8 local_port[0x8];
2afa609f
IK		 7942 u8 reserved_at_10[0xb];
7943 u8 ppan_mask_n[0x1];
7944 u8 minor_stall_mask[0x1];
7945 u8 critical_stall_mask[0x1];
7946 u8 reserved_at_1e[0x2];
e281682b
SM		 7947
7948 u8 ppan[0x4];
b4ff3a36 7949 u8 reserved_at_24[0x4];
e281682b 7950 u8 prio_mask_tx[0x8];
b4ff3a36 7951 u8 reserved_at_30[0x8];
e281682b
SM		 7952 u8 prio_mask_rx[0x8];
7953
7954 u8 pptx[0x1];
7955 u8 aptx[0x1];
2afa609f
IK		 7956 u8 pptx_mask_n[0x1];
7957 u8 reserved_at_43[0x5];
e281682b 7958 u8 pfctx[0x8];
b4ff3a36 7959 u8 reserved_at_50[0x10];
e281682b
SM		 7960
7961 u8 pprx[0x1];
7962 u8 aprx[0x1];
2afa609f
IK		 7963 u8 pprx_mask_n[0x1];
7964 u8 reserved_at_63[0x5];
e281682b 7965 u8 pfcrx[0x8];
b4ff3a36 7966 u8 reserved_at_70[0x10];
e281682b 7967
2afa609f
IK		 7968 u8 device_stall_minor_watermark[0x10];
7969 u8 device_stall_critical_watermark[0x10];
7970
7971 u8 reserved_at_a0[0x60];
e281682b
SM		 7972};
7973
7974struct mlx5_ifc_pelc_reg_bits {
7975 u8 op[0x4];
b4ff3a36 7976 u8 reserved_at_4[0x4];
e281682b 7977 u8 local_port[0x8];
b4ff3a36 7978 u8 reserved_at_10[0x10];
e281682b
SM		 7979
7980 u8 op_admin[0x8];
7981 u8 op_capability[0x8];
7982 u8 op_request[0x8];
7983 u8 op_active[0x8];
7984
7985 u8 admin[0x40];
7986
7987 u8 capability[0x40];
7988
7989 u8 request[0x40];
7990
7991 u8 active[0x40];
7992
b4ff3a36 7993 u8 reserved_at_140[0x80];
e281682b
SM		 7994};
7995
7996struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7997 u8 reserved_at_0[0x8];
e281682b 7998 u8 local_port[0x8];
b4ff3a36 7999 u8 reserved_at_10[0x10];
e281682b 8000
b4ff3a36 8001 u8 reserved_at_20[0xc];
e281682b 8002 u8 error_count[0x4];
b4ff3a36 8003 u8 reserved_at_30[0x10];
e281682b 8004
b4ff3a36 8005 u8 reserved_at_40[0xc];
e281682b 8006 u8 lane[0x4];
b4ff3a36 8007 u8 reserved_at_50[0x8];
e281682b
SM		 8008 u8 error_type[0x8];
8009};
8010
cfdcbcea 8011struct mlx5_ifc_pcam_enhanced_features_bits {
2fcb12df 8012 u8 reserved_at_0[0x76];
cfdcbcea 8013
2fcb12df
IK		 8014 u8 pfcc_mask[0x1];
8015 u8 reserved_at_77[0x4];
2dba0797 8016 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8017 u8 ptys_connector_type[0x1];
8018 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8019 u8 ppcnt_discard_group[0x1];
8020 u8 ppcnt_statistical_group[0x1];
8021};
8022
8023struct mlx5_ifc_pcam_reg_bits {
8024 u8 reserved_at_0[0x8];
8025 u8 feature_group[0x8];
8026 u8 reserved_at_10[0x8];
8027 u8 access_reg_group[0x8];
8028
8029 u8 reserved_at_20[0x20];
8030
8031 union {
8032 u8 reserved_at_0[0x80];
8033 } port_access_reg_cap_mask;
8034
8035 u8 reserved_at_c0[0x80];
8036
8037 union {
8038 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8039 u8 reserved_at_0[0x80];
8040 } feature_cap_mask;
8041
8042 u8 reserved_at_1c0[0xc0];
8043};
8044
8045struct mlx5_ifc_mcam_enhanced_features_bits {
5405fa26
GP		 8046 u8 reserved_at_0[0x7b];
8047 u8 pcie_outbound_stalled[0x1];
efae7f78 8048 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8049 u8 mtpps_enh_out_per_adj[0x1];
8050 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8051 u8 pcie_performance_group[0x1];
8052};
8053
0ab87743
OG		 8054struct mlx5_ifc_mcam_access_reg_bits {
8055 u8 reserved_at_0[0x1c];
8056 u8 mcda[0x1];
8057 u8 mcc[0x1];
8058 u8 mcqi[0x1];
8059 u8 reserved_at_1f[0x1];
8060
8061 u8 regs_95_to_64[0x20];
8062 u8 regs_63_to_32[0x20];
8063 u8 regs_31_to_0[0x20];
8064};
8065
cfdcbcea
GP		 8066struct mlx5_ifc_mcam_reg_bits {
8067 u8 reserved_at_0[0x8];
8068 u8 feature_group[0x8];
8069 u8 reserved_at_10[0x8];
8070 u8 access_reg_group[0x8];
8071
8072 u8 reserved_at_20[0x20];
8073
8074 union {
0ab87743 8075 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8076 u8 reserved_at_0[0x80];
8077 } mng_access_reg_cap_mask;
8078
8079 u8 reserved_at_c0[0x80];
8080
8081 union {
8082 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8083 u8 reserved_at_0[0x80];
8084 } mng_feature_cap_mask;
8085
8086 u8 reserved_at_1c0[0x80];
8087};
8088
c02762eb
HN		 8089struct mlx5_ifc_qcam_access_reg_cap_mask {
8090 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8091 u8 qpdpm[0x1];
8092 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8093 u8 qdpm[0x1];
8094 u8 qpts[0x1];
8095 u8 qcap[0x1];
8096 u8 qcam_access_reg_cap_mask_0[0x1];
8097};
8098
8099struct mlx5_ifc_qcam_qos_feature_cap_mask {
8100 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8101 u8 qpts_trust_both[0x1];
8102};
8103
8104struct mlx5_ifc_qcam_reg_bits {
8105 u8 reserved_at_0[0x8];
8106 u8 feature_group[0x8];
8107 u8 reserved_at_10[0x8];
8108 u8 access_reg_group[0x8];
8109 u8 reserved_at_20[0x20];
8110
8111 union {
8112 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8113 u8 reserved_at_0[0x80];
8114 } qos_access_reg_cap_mask;
8115
8116 u8 reserved_at_c0[0x80];
8117
8118 union {
8119 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8120 u8 reserved_at_0[0x80];
8121 } qos_feature_cap_mask;
8122
8123 u8 reserved_at_1c0[0x80];
8124};
8125
e281682b 8126struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8127 u8 reserved_at_0[0x8];
e281682b 8128 u8 local_port[0x8];
b4ff3a36 8129 u8 reserved_at_10[0x10];
e281682b
SM		 8130
8131 u8 port_capability_mask[4][0x20];
8132};
8133
8134struct mlx5_ifc_paos_reg_bits {
8135 u8 swid[0x8];
8136 u8 local_port[0x8];
b4ff3a36 8137 u8 reserved_at_10[0x4];
e281682b 8138 u8 admin_status[0x4];
b4ff3a36 8139 u8 reserved_at_18[0x4];
e281682b
SM		 8140 u8 oper_status[0x4];
8141
8142 u8 ase[0x1];
8143 u8 ee[0x1];
b4ff3a36 8144 u8 reserved_at_22[0x1c];
e281682b
SM		 8145 u8 e[0x2];
8146
b4ff3a36 8147 u8 reserved_at_40[0x40];
e281682b
SM		 8148};
8149
8150struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8151 u8 reserved_at_0[0x8];
e281682b 8152 u8 opamp_group[0x8];
b4ff3a36 8153 u8 reserved_at_10[0xc];
e281682b
SM		 8154 u8 opamp_group_type[0x4];
8155
8156 u8 start_index[0x10];
b4ff3a36 8157 u8 reserved_at_30[0x4];
e281682b
SM		 8158 u8 num_of_indices[0xc];
8159
8160 u8 index_data[18][0x10];
8161};
8162
7d5e1423
SM		 8163struct mlx5_ifc_pcmr_reg_bits {
8164 u8 reserved_at_0[0x8];
8165 u8 local_port[0x8];
8166 u8 reserved_at_10[0x2e];
8167 u8 fcs_cap[0x1];
8168 u8 reserved_at_3f[0x1f];
8169 u8 fcs_chk[0x1];
8170 u8 reserved_at_5f[0x1];
8171};
8172
e281682b 8173struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8174 u8 reserved_at_0[0x6];
e281682b 8175 u8 rx_lane[0x2];
b4ff3a36 8176 u8 reserved_at_8[0x6];
e281682b 8177 u8 tx_lane[0x2];
b4ff3a36 8178 u8 reserved_at_10[0x8];
e281682b
SM		 8179 u8 module[0x8];
8180};
8181
8182struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8183 u8 reserved_at_0[0x6];
e281682b
SM		 8184 u8 lossy[0x1];
8185 u8 epsb[0x1];
b4ff3a36 8186 u8 reserved_at_8[0xc];
e281682b
SM		 8187 u8 size[0xc];
8188
8189 u8 xoff_threshold[0x10];
8190 u8 xon_threshold[0x10];
8191};
8192
8193struct mlx5_ifc_set_node_in_bits {
8194 u8 node_description[64][0x8];
8195};
8196
8197struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8198 u8 reserved_at_0[0x18];
e281682b
SM		 8199 u8 power_settings_level[0x8];
8200
b4ff3a36 8201 u8 reserved_at_20[0x60];
e281682b
SM		 8202};
8203
8204struct mlx5_ifc_register_host_endianness_bits {
8205 u8 he[0x1];
b4ff3a36 8206 u8 reserved_at_1[0x1f];
e281682b 8207
b4ff3a36 8208 u8 reserved_at_20[0x60];
e281682b
SM		 8209};
8210
8211struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8212 u8 reserved_at_0[0x20];
e281682b
SM		 8213
8214 u8 mkey[0x20];
8215
8216 u8 addressh_63_32[0x20];
8217
8218 u8 addressl_31_0[0x20];
8219};
8220
8221struct mlx5_ifc_ud_adrs_vector_bits {
8222 u8 dc_key[0x40];
8223
8224 u8 ext[0x1];
b4ff3a36 8225 u8 reserved_at_41[0x7];
e281682b
SM		 8226 u8 destination_qp_dct[0x18];
8227
8228 u8 static_rate[0x4];
8229 u8 sl_eth_prio[0x4];
8230 u8 fl[0x1];
8231 u8 mlid[0x7];
8232 u8 rlid_udp_sport[0x10];
8233
b4ff3a36 8234 u8 reserved_at_80[0x20];
e281682b
SM		 8235
8236 u8 rmac_47_16[0x20];
8237
8238 u8 rmac_15_0[0x10];
8239 u8 tclass[0x8];
8240 u8 hop_limit[0x8];
8241
b4ff3a36 8242 u8 reserved_at_e0[0x1];
e281682b 8243 u8 grh[0x1];
b4ff3a36 8244 u8 reserved_at_e2[0x2];
e281682b
SM		 8245 u8 src_addr_index[0x8];
8246 u8 flow_label[0x14];
8247
8248 u8 rgid_rip[16][0x8];
8249};
8250
8251struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8252 u8 reserved_at_0[0x10];
e281682b
SM		 8253 u8 function_id[0x10];
8254
8255 u8 num_pages[0x20];
8256
b4ff3a36 8257 u8 reserved_at_40[0xa0];
e281682b
SM		 8258};
8259
8260struct mlx5_ifc_eqe_bits {
b4ff3a36 8261 u8 reserved_at_0[0x8];
e281682b 8262 u8 event_type[0x8];
b4ff3a36 8263 u8 reserved_at_10[0x8];
e281682b
SM		 8264 u8 event_sub_type[0x8];
8265
b4ff3a36 8266 u8 reserved_at_20[0xe0];
e281682b
SM		 8267
8268 union mlx5_ifc_event_auto_bits event_data;
8269
b4ff3a36 8270 u8 reserved_at_1e0[0x10];
e281682b 8271 u8 signature[0x8];
b4ff3a36 8272 u8 reserved_at_1f8[0x7];
e281682b
SM		 8273 u8 owner[0x1];
8274};
8275
8276enum {
8277 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8278};
8279
8280struct mlx5_ifc_cmd_queue_entry_bits {
8281 u8 type[0x8];
b4ff3a36 8282 u8 reserved_at_8[0x18];
e281682b
SM		 8283
8284 u8 input_length[0x20];
8285
8286 u8 input_mailbox_pointer_63_32[0x20];
8287
8288 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8289 u8 reserved_at_77[0x9];
e281682b
SM		 8290
8291 u8 command_input_inline_data[16][0x8];
8292
8293 u8 command_output_inline_data[16][0x8];
8294
8295 u8 output_mailbox_pointer_63_32[0x20];
8296
8297 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8298 u8 reserved_at_1b7[0x9];
e281682b
SM		 8299
8300 u8 output_length[0x20];
8301
8302 u8 token[0x8];
8303 u8 signature[0x8];
b4ff3a36 8304 u8 reserved_at_1f0[0x8];
e281682b
SM		 8305 u8 status[0x7];
8306 u8 ownership[0x1];
8307};
8308
8309struct mlx5_ifc_cmd_out_bits {
8310 u8 status[0x8];
b4ff3a36 8311 u8 reserved_at_8[0x18];
e281682b
SM		 8312
8313 u8 syndrome[0x20];
8314
8315 u8 command_output[0x20];
8316};
8317
8318struct mlx5_ifc_cmd_in_bits {
8319 u8 opcode[0x10];
b4ff3a36 8320 u8 reserved_at_10[0x10];
e281682b 8321
b4ff3a36 8322 u8 reserved_at_20[0x10];
e281682b
SM		 8323 u8 op_mod[0x10];
8324
8325 u8 command[0][0x20];
8326};
8327
8328struct mlx5_ifc_cmd_if_box_bits {
8329 u8 mailbox_data[512][0x8];
8330
b4ff3a36 8331 u8 reserved_at_1000[0x180];
e281682b
SM		 8332
8333 u8 next_pointer_63_32[0x20];
8334
8335 u8 next_pointer_31_10[0x16];
b4ff3a36 8336 u8 reserved_at_11b6[0xa];
e281682b
SM		 8337
8338 u8 block_number[0x20];
8339
b4ff3a36 8340 u8 reserved_at_11e0[0x8];
e281682b
SM		 8341 u8 token[0x8];
8342 u8 ctrl_signature[0x8];
8343 u8 signature[0x8];
8344};
8345
8346struct mlx5_ifc_mtt_bits {
8347 u8 ptag_63_32[0x20];
8348
8349 u8 ptag_31_8[0x18];
b4ff3a36 8350 u8 reserved_at_38[0x6];
e281682b
SM		 8351 u8 wr_en[0x1];
8352 u8 rd_en[0x1];
8353};
8354
928cfe87
TT		 8355struct mlx5_ifc_query_wol_rol_out_bits {
8356 u8 status[0x8];
8357 u8 reserved_at_8[0x18];
8358
8359 u8 syndrome[0x20];
8360
8361 u8 reserved_at_40[0x10];
8362 u8 rol_mode[0x8];
8363 u8 wol_mode[0x8];
8364
8365 u8 reserved_at_60[0x20];
8366};
8367
8368struct mlx5_ifc_query_wol_rol_in_bits {
8369 u8 opcode[0x10];
8370 u8 reserved_at_10[0x10];
8371
8372 u8 reserved_at_20[0x10];
8373 u8 op_mod[0x10];
8374
8375 u8 reserved_at_40[0x40];
8376};
8377
8378struct mlx5_ifc_set_wol_rol_out_bits {
8379 u8 status[0x8];
8380 u8 reserved_at_8[0x18];
8381
8382 u8 syndrome[0x20];
8383
8384 u8 reserved_at_40[0x40];
8385};
8386
8387struct mlx5_ifc_set_wol_rol_in_bits {
8388 u8 opcode[0x10];
8389 u8 reserved_at_10[0x10];
8390
8391 u8 reserved_at_20[0x10];
8392 u8 op_mod[0x10];
8393
8394 u8 rol_mode_valid[0x1];
8395 u8 wol_mode_valid[0x1];
8396 u8 reserved_at_42[0xe];
8397 u8 rol_mode[0x8];
8398 u8 wol_mode[0x8];
8399
8400 u8 reserved_at_60[0x20];
8401};
8402
e281682b
SM		 8403enum {
8404 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8405 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8406 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8407};
8408
8409enum {
8410 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8411 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8412 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8413};
8414
8415enum {
8416 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8417 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8426 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8427};
8428
8429struct mlx5_ifc_initial_seg_bits {
8430 u8 fw_rev_minor[0x10];
8431 u8 fw_rev_major[0x10];
8432
8433 u8 cmd_interface_rev[0x10];
8434 u8 fw_rev_subminor[0x10];
8435
b4ff3a36 8436 u8 reserved_at_40[0x40];
e281682b
SM		 8437
8438 u8 cmdq_phy_addr_63_32[0x20];
8439
8440 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8441 u8 reserved_at_b4[0x2];
e281682b
SM		 8442 u8 nic_interface[0x2];
8443 u8 log_cmdq_size[0x4];
8444 u8 log_cmdq_stride[0x4];
8445
8446 u8 command_doorbell_vector[0x20];
8447
b4ff3a36 8448 u8 reserved_at_e0[0xf00];
e281682b
SM		 8449
8450 u8 initializing[0x1];
b4ff3a36 8451 u8 reserved_at_fe1[0x4];
e281682b 8452 u8 nic_interface_supported[0x3];
b4ff3a36 8453 u8 reserved_at_fe8[0x18];
e281682b
SM		 8454
8455 struct mlx5_ifc_health_buffer_bits health_buffer;
8456
8457 u8 no_dram_nic_offset[0x20];
8458
b4ff3a36 8459 u8 reserved_at_1220[0x6e40];
e281682b 8460
b4ff3a36 8461 u8 reserved_at_8060[0x1f];
e281682b
SM		 8462 u8 clear_int[0x1];
8463
8464 u8 health_syndrome[0x8];
8465 u8 health_counter[0x18];
8466
b4ff3a36 8467 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8468};
8469
f9a1ef72
EE		 8470struct mlx5_ifc_mtpps_reg_bits {
8471 u8 reserved_at_0[0xc];
8472 u8 cap_number_of_pps_pins[0x4];
8473 u8 reserved_at_10[0x4];
8474 u8 cap_max_num_of_pps_in_pins[0x4];
8475 u8 reserved_at_18[0x4];
8476 u8 cap_max_num_of_pps_out_pins[0x4];
8477
8478 u8 reserved_at_20[0x24];
8479 u8 cap_pin_3_mode[0x4];
8480 u8 reserved_at_48[0x4];
8481 u8 cap_pin_2_mode[0x4];
8482 u8 reserved_at_50[0x4];
8483 u8 cap_pin_1_mode[0x4];
8484 u8 reserved_at_58[0x4];
8485 u8 cap_pin_0_mode[0x4];
8486
8487 u8 reserved_at_60[0x4];
8488 u8 cap_pin_7_mode[0x4];
8489 u8 reserved_at_68[0x4];
8490 u8 cap_pin_6_mode[0x4];
8491 u8 reserved_at_70[0x4];
8492 u8 cap_pin_5_mode[0x4];
8493 u8 reserved_at_78[0x4];
8494 u8 cap_pin_4_mode[0x4];
8495
fa367688
EE		 8496 u8 field_select[0x20];
8497 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8498
8499 u8 enable[0x1];
8500 u8 reserved_at_101[0xb];
8501 u8 pattern[0x4];
8502 u8 reserved_at_110[0x4];
8503 u8 pin_mode[0x4];
8504 u8 pin[0x8];
8505
8506 u8 reserved_at_120[0x20];
8507
8508 u8 time_stamp[0x40];
8509
8510 u8 out_pulse_duration[0x10];
8511 u8 out_periodic_adjustment[0x10];
fa367688 8512 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8513
fa367688 8514 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8515};
8516
8517struct mlx5_ifc_mtppse_reg_bits {
8518 u8 reserved_at_0[0x18];
8519 u8 pin[0x8];
8520 u8 event_arm[0x1];
8521 u8 reserved_at_21[0x1b];
8522 u8 event_generation_mode[0x4];
8523 u8 reserved_at_40[0x40];
8524};
8525
47176289
OG		 8526struct mlx5_ifc_mcqi_cap_bits {
8527 u8 supported_info_bitmask[0x20];
8528
8529 u8 component_size[0x20];
8530
8531 u8 max_component_size[0x20];
8532
8533 u8 log_mcda_word_size[0x4];
8534 u8 reserved_at_64[0xc];
8535 u8 mcda_max_write_size[0x10];
8536
8537 u8 rd_en[0x1];
8538 u8 reserved_at_81[0x1];
8539 u8 match_chip_id[0x1];
8540 u8 match_psid[0x1];
8541 u8 check_user_timestamp[0x1];
8542 u8 match_base_guid_mac[0x1];
8543 u8 reserved_at_86[0x1a];
8544};
8545
8546struct mlx5_ifc_mcqi_reg_bits {
8547 u8 read_pending_component[0x1];
8548 u8 reserved_at_1[0xf];
8549 u8 component_index[0x10];
8550
8551 u8 reserved_at_20[0x20];
8552
8553 u8 reserved_at_40[0x1b];
8554 u8 info_type[0x5];
8555
8556 u8 info_size[0x20];
8557
8558 u8 offset[0x20];
8559
8560 u8 reserved_at_a0[0x10];
8561 u8 data_size[0x10];
8562
8563 u8 data[0][0x20];
8564};
8565
8566struct mlx5_ifc_mcc_reg_bits {
8567 u8 reserved_at_0[0x4];
8568 u8 time_elapsed_since_last_cmd[0xc];
8569 u8 reserved_at_10[0x8];
8570 u8 instruction[0x8];
8571
8572 u8 reserved_at_20[0x10];
8573 u8 component_index[0x10];
8574
8575 u8 reserved_at_40[0x8];
8576 u8 update_handle[0x18];
8577
8578 u8 handle_owner_type[0x4];
8579 u8 handle_owner_host_id[0x4];
8580 u8 reserved_at_68[0x1];
8581 u8 control_progress[0x7];
8582 u8 error_code[0x8];
8583 u8 reserved_at_78[0x4];
8584 u8 control_state[0x4];
8585
8586 u8 component_size[0x20];
8587
8588 u8 reserved_at_a0[0x60];
8589};
8590
8591struct mlx5_ifc_mcda_reg_bits {
8592 u8 reserved_at_0[0x8];
8593 u8 update_handle[0x18];
8594
8595 u8 offset[0x20];
8596
8597 u8 reserved_at_40[0x10];
8598 u8 size[0x10];
8599
8600 u8 reserved_at_60[0x20];
8601
8602 u8 data[0][0x20];
8603};
8604
e281682b
SM		 8605union mlx5_ifc_ports_control_registers_document_bits {
8606 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8607 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8608 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8609 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8610 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8611 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8612 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8613 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8614 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8615 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8616 struct mlx5_ifc_paos_reg_bits paos_reg;
8617 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8618 struct mlx5_ifc_peir_reg_bits peir_reg;
8619 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8620 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8621 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8622 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8623 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8624 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8625 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8626 struct mlx5_ifc_plib_reg_bits plib_reg;
8627 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8628 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8629 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8630 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8631 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8632 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8633 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8634 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8635 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8636 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8637 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8638 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8639 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8640 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8641 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8642 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8643 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8644 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8645 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8646 struct mlx5_ifc_pude_reg_bits pude_reg;
8647 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8648 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8649 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8650 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8651 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8652 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8653 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8654 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8655 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8656 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8657 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8658 u8 reserved_at_0[0x60e0];
e281682b
SM		 8659};
8660
8661union mlx5_ifc_debug_enhancements_document_bits {
8662 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8663 u8 reserved_at_0[0x200];
e281682b
SM		 8664};
8665
8666union mlx5_ifc_uplink_pci_interface_document_bits {
8667 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8668 u8 reserved_at_0[0x20060];
b775516b
EC		 8669};
8670
2cc43b49
MG		 8671struct mlx5_ifc_set_flow_table_root_out_bits {
8672 u8 status[0x8];
b4ff3a36 8673 u8 reserved_at_8[0x18];
2cc43b49
MG		 8674
8675 u8 syndrome[0x20];
8676
b4ff3a36 8677 u8 reserved_at_40[0x40];
2cc43b49
MG		 8678};
8679
8680struct mlx5_ifc_set_flow_table_root_in_bits {
8681 u8 opcode[0x10];
b4ff3a36 8682 u8 reserved_at_10[0x10];
2cc43b49 8683
b4ff3a36 8684 u8 reserved_at_20[0x10];
2cc43b49
MG		 8685 u8 op_mod[0x10];
8686
7d5e1423
SM		 8687 u8 other_vport[0x1];
8688 u8 reserved_at_41[0xf];
8689 u8 vport_number[0x10];
8690
8691 u8 reserved_at_60[0x20];
2cc43b49
MG		 8692
8693 u8 table_type[0x8];
b4ff3a36 8694 u8 reserved_at_88[0x18];
2cc43b49 8695
b4ff3a36 8696 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8697 u8 table_id[0x18];
8698
500a3d0d
ES		 8699 u8 reserved_at_c0[0x8];
8700 u8 underlay_qpn[0x18];
8701 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8702};
8703
34a40e68 8704enum {
84df61eb
AH		 8705 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8706 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8707};
8708
8709struct mlx5_ifc_modify_flow_table_out_bits {
8710 u8 status[0x8];
b4ff3a36 8711 u8 reserved_at_8[0x18];
34a40e68
MG		 8712
8713 u8 syndrome[0x20];
8714
b4ff3a36 8715 u8 reserved_at_40[0x40];
34a40e68
MG		 8716};
8717
8718struct mlx5_ifc_modify_flow_table_in_bits {
8719 u8 opcode[0x10];
b4ff3a36 8720 u8 reserved_at_10[0x10];
34a40e68 8721
b4ff3a36 8722 u8 reserved_at_20[0x10];
34a40e68
MG		 8723 u8 op_mod[0x10];
8724
7d5e1423
SM		 8725 u8 other_vport[0x1];
8726 u8 reserved_at_41[0xf];
8727 u8 vport_number[0x10];
34a40e68 8728
b4ff3a36 8729 u8 reserved_at_60[0x10];
34a40e68
MG		 8730 u8 modify_field_select[0x10];
8731
8732 u8 table_type[0x8];
b4ff3a36 8733 u8 reserved_at_88[0x18];
34a40e68 8734
b4ff3a36 8735 u8 reserved_at_a0[0x8];
34a40e68
MG		 8736 u8 table_id[0x18];
8737
0c90e9c6 8738 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8739};
8740
4f3961ee
SM		 8741struct mlx5_ifc_ets_tcn_config_reg_bits {
8742 u8 g[0x1];
8743 u8 b[0x1];
8744 u8 r[0x1];
8745 u8 reserved_at_3[0x9];
8746 u8 group[0x4];
8747 u8 reserved_at_10[0x9];
8748 u8 bw_allocation[0x7];
8749
8750 u8 reserved_at_20[0xc];
8751 u8 max_bw_units[0x4];
8752 u8 reserved_at_30[0x8];
8753 u8 max_bw_value[0x8];
8754};
8755
8756struct mlx5_ifc_ets_global_config_reg_bits {
8757 u8 reserved_at_0[0x2];
8758 u8 r[0x1];
8759 u8 reserved_at_3[0x1d];
8760
8761 u8 reserved_at_20[0xc];
8762 u8 max_bw_units[0x4];
8763 u8 reserved_at_30[0x8];
8764 u8 max_bw_value[0x8];
8765};
8766
8767struct mlx5_ifc_qetc_reg_bits {
8768 u8 reserved_at_0[0x8];
8769 u8 port_number[0x8];
8770 u8 reserved_at_10[0x30];
8771
8772 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8773 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8774};
8775
415a64aa
HN		 8776struct mlx5_ifc_qpdpm_dscp_reg_bits {
8777 u8 e[0x1];
8778 u8 reserved_at_01[0x0b];
8779 u8 prio[0x04];
8780};
8781
8782struct mlx5_ifc_qpdpm_reg_bits {
8783 u8 reserved_at_0[0x8];
8784 u8 local_port[0x8];
8785 u8 reserved_at_10[0x10];
8786 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8787};
8788
8789struct mlx5_ifc_qpts_reg_bits {
8790 u8 reserved_at_0[0x8];
8791 u8 local_port[0x8];
8792 u8 reserved_at_10[0x2d];
8793 u8 trust_state[0x3];
8794};
8795
4f3961ee
SM		 8796struct mlx5_ifc_qtct_reg_bits {
8797 u8 reserved_at_0[0x8];
8798 u8 port_number[0x8];
8799 u8 reserved_at_10[0xd];
8800 u8 prio[0x3];
8801
8802 u8 reserved_at_20[0x1d];
8803 u8 tclass[0x3];
8804};
8805
7d5e1423
SM		 8806struct mlx5_ifc_mcia_reg_bits {
8807 u8 l[0x1];
8808 u8 reserved_at_1[0x7];
8809 u8 module[0x8];
8810 u8 reserved_at_10[0x8];
8811 u8 status[0x8];
8812
8813 u8 i2c_device_address[0x8];
8814 u8 page_number[0x8];
8815 u8 device_address[0x10];
8816
8817 u8 reserved_at_40[0x10];
8818 u8 size[0x10];
8819
8820 u8 reserved_at_60[0x20];
8821
8822 u8 dword_0[0x20];
8823 u8 dword_1[0x20];
8824 u8 dword_2[0x20];
8825 u8 dword_3[0x20];
8826 u8 dword_4[0x20];
8827 u8 dword_5[0x20];
8828 u8 dword_6[0x20];
8829 u8 dword_7[0x20];
8830 u8 dword_8[0x20];
8831 u8 dword_9[0x20];
8832 u8 dword_10[0x20];
8833 u8 dword_11[0x20];
8834};
8835
7486216b
SM		 8836struct mlx5_ifc_dcbx_param_bits {
8837 u8 dcbx_cee_cap[0x1];
8838 u8 dcbx_ieee_cap[0x1];
8839 u8 dcbx_standby_cap[0x1];
8840 u8 reserved_at_0[0x5];
8841 u8 port_number[0x8];
8842 u8 reserved_at_10[0xa];
8843 u8 max_application_table_size[6];
8844 u8 reserved_at_20[0x15];
8845 u8 version_oper[0x3];
8846 u8 reserved_at_38[5];
8847 u8 version_admin[0x3];
8848 u8 willing_admin[0x1];
8849 u8 reserved_at_41[0x3];
8850 u8 pfc_cap_oper[0x4];
8851 u8 reserved_at_48[0x4];
8852 u8 pfc_cap_admin[0x4];
8853 u8 reserved_at_50[0x4];
8854 u8 num_of_tc_oper[0x4];
8855 u8 reserved_at_58[0x4];
8856 u8 num_of_tc_admin[0x4];
8857 u8 remote_willing[0x1];
8858 u8 reserved_at_61[3];
8859 u8 remote_pfc_cap[4];
8860 u8 reserved_at_68[0x14];
8861 u8 remote_num_of_tc[0x4];
8862 u8 reserved_at_80[0x18];
8863 u8 error[0x8];
8864 u8 reserved_at_a0[0x160];
8865};
84df61eb
AH		 8866
8867struct mlx5_ifc_lagc_bits {
8868 u8 reserved_at_0[0x1d];
8869 u8 lag_state[0x3];
8870
8871 u8 reserved_at_20[0x14];
8872 u8 tx_remap_affinity_2[0x4];
8873 u8 reserved_at_38[0x4];
8874 u8 tx_remap_affinity_1[0x4];
8875};
8876
8877struct mlx5_ifc_create_lag_out_bits {
8878 u8 status[0x8];
8879 u8 reserved_at_8[0x18];
8880
8881 u8 syndrome[0x20];
8882
8883 u8 reserved_at_40[0x40];
8884};
8885
8886struct mlx5_ifc_create_lag_in_bits {
8887 u8 opcode[0x10];
8888 u8 reserved_at_10[0x10];
8889
8890 u8 reserved_at_20[0x10];
8891 u8 op_mod[0x10];
8892
8893 struct mlx5_ifc_lagc_bits ctx;
8894};
8895
8896struct mlx5_ifc_modify_lag_out_bits {
8897 u8 status[0x8];
8898 u8 reserved_at_8[0x18];
8899
8900 u8 syndrome[0x20];
8901
8902 u8 reserved_at_40[0x40];
8903};
8904
8905struct mlx5_ifc_modify_lag_in_bits {
8906 u8 opcode[0x10];
8907 u8 reserved_at_10[0x10];
8908
8909 u8 reserved_at_20[0x10];
8910 u8 op_mod[0x10];
8911
8912 u8 reserved_at_40[0x20];
8913 u8 field_select[0x20];
8914
8915 struct mlx5_ifc_lagc_bits ctx;
8916};
8917
8918struct mlx5_ifc_query_lag_out_bits {
8919 u8 status[0x8];
8920 u8 reserved_at_8[0x18];
8921
8922 u8 syndrome[0x20];
8923
8924 u8 reserved_at_40[0x40];
8925
8926 struct mlx5_ifc_lagc_bits ctx;
8927};
8928
8929struct mlx5_ifc_query_lag_in_bits {
8930 u8 opcode[0x10];
8931 u8 reserved_at_10[0x10];
8932
8933 u8 reserved_at_20[0x10];
8934 u8 op_mod[0x10];
8935
8936 u8 reserved_at_40[0x40];
8937};
8938
8939struct mlx5_ifc_destroy_lag_out_bits {
8940 u8 status[0x8];
8941 u8 reserved_at_8[0x18];
8942
8943 u8 syndrome[0x20];
8944
8945 u8 reserved_at_40[0x40];
8946};
8947
8948struct mlx5_ifc_destroy_lag_in_bits {
8949 u8 opcode[0x10];
8950 u8 reserved_at_10[0x10];
8951
8952 u8 reserved_at_20[0x10];
8953 u8 op_mod[0x10];
8954
8955 u8 reserved_at_40[0x40];
8956};
8957
8958struct mlx5_ifc_create_vport_lag_out_bits {
8959 u8 status[0x8];
8960 u8 reserved_at_8[0x18];
8961
8962 u8 syndrome[0x20];
8963
8964 u8 reserved_at_40[0x40];
8965};
8966
8967struct mlx5_ifc_create_vport_lag_in_bits {
8968 u8 opcode[0x10];
8969 u8 reserved_at_10[0x10];
8970
8971 u8 reserved_at_20[0x10];
8972 u8 op_mod[0x10];
8973
8974 u8 reserved_at_40[0x40];
8975};
8976
8977struct mlx5_ifc_destroy_vport_lag_out_bits {
8978 u8 status[0x8];
8979 u8 reserved_at_8[0x18];
8980
8981 u8 syndrome[0x20];
8982
8983 u8 reserved_at_40[0x40];
8984};
8985
8986struct mlx5_ifc_destroy_vport_lag_in_bits {
8987 u8 opcode[0x10];
8988 u8 reserved_at_10[0x10];
8989
8990 u8 reserved_at_20[0x10];
8991 u8 op_mod[0x10];
8992
8993 u8 reserved_at_40[0x40];
8994};
8995
24da0016
AL		 8996struct mlx5_ifc_alloc_memic_in_bits {
8997 u8 opcode[0x10];
8998 u8 reserved_at_10[0x10];
8999
9000 u8 reserved_at_20[0x10];
9001 u8 op_mod[0x10];
9002
9003 u8 reserved_at_30[0x20];
9004
9005 u8 reserved_at_40[0x18];
9006 u8 log_memic_addr_alignment[0x8];
9007
9008 u8 range_start_addr[0x40];
9009
9010 u8 range_size[0x20];
9011
9012 u8 memic_size[0x20];
9013};
9014
9015struct mlx5_ifc_alloc_memic_out_bits {
9016 u8 status[0x8];
9017 u8 reserved_at_8[0x18];
9018
9019 u8 syndrome[0x20];
9020
9021 u8 memic_start_addr[0x40];
9022};
9023
9024struct mlx5_ifc_dealloc_memic_in_bits {
9025 u8 opcode[0x10];
9026 u8 reserved_at_10[0x10];
9027
9028 u8 reserved_at_20[0x10];
9029 u8 op_mod[0x10];
9030
9031 u8 reserved_at_40[0x40];
9032
9033 u8 memic_start_addr[0x40];
9034
9035 u8 memic_size[0x20];
9036
9037 u8 reserved_at_e0[0x20];
9038};
9039
9040struct mlx5_ifc_dealloc_memic_out_bits {
9041 u8 status[0x8];
9042 u8 reserved_at_8[0x18];
9043
9044 u8 syndrome[0x20];
9045
9046 u8 reserved_at_40[0x40];
9047};
9048
d29b796a 9049#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)