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net/mlx5: Remove unused argument
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
f91e6d89
EBE		 66enum {
67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
59e9e8e4 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
f91e6d89
EBE		 71};
72
38b7ca92 73enum {
2acc7957 74 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 75};
76
9fba2b9b
AL		 77enum {
78 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
79};
80
81enum {
82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
b169e64a 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90fbca59 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
b169e64a
YK		 85};
86
87enum {
88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
8a06a79b 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
e7e2519e 90 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
e4075c44
YH		 91 MLX5_OBJ_TYPE_MKEY = 0xff01,
92 MLX5_OBJ_TYPE_QP = 0xff02,
93 MLX5_OBJ_TYPE_PSV = 0xff03,
94 MLX5_OBJ_TYPE_RMP = 0xff04,
95 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
96 MLX5_OBJ_TYPE_RQ = 0xff06,
97 MLX5_OBJ_TYPE_SQ = 0xff07,
98 MLX5_OBJ_TYPE_TIR = 0xff08,
99 MLX5_OBJ_TYPE_TIS = 0xff09,
100 MLX5_OBJ_TYPE_DCT = 0xff0a,
101 MLX5_OBJ_TYPE_XRQ = 0xff0b,
102 MLX5_OBJ_TYPE_RQT = 0xff0e,
103 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
104 MLX5_OBJ_TYPE_CQ = 0xff10,
9fba2b9b
AL		 105};
106
d29b796a
EC		 107enum {
108 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
109 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
110 MLX5_CMD_OP_INIT_HCA = 0x102,
111 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
112 MLX5_CMD_OP_ENABLE_HCA = 0x104,
113 MLX5_CMD_OP_DISABLE_HCA = 0x105,
114 MLX5_CMD_OP_QUERY_PAGES = 0x107,
115 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
116 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 117 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
118 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 119 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
1759d322
PP		 120 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
121 MLX5_CMD_OP_ALLOC_SF = 0x113,
122 MLX5_CMD_OP_DEALLOC_SF = 0x114,
adfdaff3
YH		 123 MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
124 MLX5_CMD_OP_RESUME_VHCA = 0x116,
125 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
126 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
127 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
d29b796a
EC		 128 MLX5_CMD_OP_CREATE_MKEY = 0x200,
129 MLX5_CMD_OP_QUERY_MKEY = 0x201,
130 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
131 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
132 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 133 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
134 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
63f9c44b 135 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
d29b796a
EC		 136 MLX5_CMD_OP_CREATE_EQ = 0x301,
137 MLX5_CMD_OP_DESTROY_EQ = 0x302,
138 MLX5_CMD_OP_QUERY_EQ = 0x303,
139 MLX5_CMD_OP_GEN_EQE = 0x304,
140 MLX5_CMD_OP_CREATE_CQ = 0x400,
141 MLX5_CMD_OP_DESTROY_CQ = 0x401,
142 MLX5_CMD_OP_QUERY_CQ = 0x402,
143 MLX5_CMD_OP_MODIFY_CQ = 0x403,
144 MLX5_CMD_OP_CREATE_QP = 0x500,
145 MLX5_CMD_OP_DESTROY_QP = 0x501,
146 MLX5_CMD_OP_RST2INIT_QP = 0x502,
147 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
148 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
149 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
151 MLX5_CMD_OP_2ERR_QP = 0x507,
152 MLX5_CMD_OP_2RST_QP = 0x50a,
153 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
156 MLX5_CMD_OP_CREATE_PSV = 0x600,
157 MLX5_CMD_OP_DESTROY_PSV = 0x601,
158 MLX5_CMD_OP_CREATE_SRQ = 0x700,
159 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
160 MLX5_CMD_OP_QUERY_SRQ = 0x702,
161 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 166 MLX5_CMD_OP_CREATE_DCT = 0x710,
167 MLX5_CMD_OP_DESTROY_DCT = 0x711,
168 MLX5_CMD_OP_DRAIN_DCT = 0x712,
169 MLX5_CMD_OP_QUERY_DCT = 0x713,
170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 171 MLX5_CMD_OP_CREATE_XRQ = 0x717,
172 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
173 MLX5_CMD_OP_QUERY_XRQ = 0x719,
174 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
b1635ee6
YH		 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
cd56f929 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
d29b796a
EC		 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 208 MLX5_CMD_OP_ALLOC_PD = 0x800,
209 MLX5_CMD_OP_DEALLOC_PD = 0x801,
210 MLX5_CMD_OP_ALLOC_UAR = 0x802,
211 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
213 MLX5_CMD_OP_ACCESS_REG = 0x805,
214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
217 MLX5_CMD_OP_MAD_IFC = 0x50d,
218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
220 MLX5_CMD_OP_NOP = 0x80d,
221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 237 MLX5_CMD_OP_CREATE_LAG = 0x840,
238 MLX5_CMD_OP_MODIFY_LAG = 0x841,
239 MLX5_CMD_OP_QUERY_LAG = 0x842,
240 MLX5_CMD_OP_DESTROY_LAG = 0x843,
241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 243 MLX5_CMD_OP_CREATE_TIR = 0x900,
244 MLX5_CMD_OP_MODIFY_TIR = 0x901,
245 MLX5_CMD_OP_DESTROY_TIR = 0x902,
246 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 247 MLX5_CMD_OP_CREATE_SQ = 0x904,
248 MLX5_CMD_OP_MODIFY_SQ = 0x905,
249 MLX5_CMD_OP_DESTROY_SQ = 0x906,
250 MLX5_CMD_OP_QUERY_SQ = 0x907,
251 MLX5_CMD_OP_CREATE_RQ = 0x908,
252 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
255 MLX5_CMD_OP_QUERY_RQ = 0x90b,
256 MLX5_CMD_OP_CREATE_RMP = 0x90c,
257 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
258 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
259 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 260 MLX5_CMD_OP_CREATE_TIS = 0x912,
261 MLX5_CMD_OP_MODIFY_TIS = 0x913,
262 MLX5_CMD_OP_DESTROY_TIS = 0x914,
263 MLX5_CMD_OP_QUERY_TIS = 0x915,
264 MLX5_CMD_OP_CREATE_RQT = 0x916,
265 MLX5_CMD_OP_MODIFY_RQT = 0x917,
266 MLX5_CMD_OP_DESTROY_RQT = 0x918,
267 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
d32d7c52 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
349125ba
PP		 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
86d56a1a 304 MLX5_CMD_OP_MAX
e281682b
SM		 305};
306
719598c9
YH		 307/* Valid range for general commands that don't work over an object */
308enum {
309 MLX5_CMD_OP_GENERAL_START = 0xb00,
310 MLX5_CMD_OP_GENERAL_END = 0xd00,
311};
312
e281682b
SM		 313struct mlx5_ifc_flow_table_fields_supported_bits {
314 u8 outer_dmac[0x1];
315 u8 outer_smac[0x1];
316 u8 outer_ether_type[0x1];
19cc7524 317 u8 outer_ip_version[0x1];
e281682b
SM		 318 u8 outer_first_prio[0x1];
319 u8 outer_first_cfi[0x1];
320 u8 outer_first_vid[0x1];
a8ade55f 321 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 322 u8 outer_second_prio[0x1];
323 u8 outer_second_cfi[0x1];
324 u8 outer_second_vid[0x1];
b4ff3a36 325 u8 reserved_at_b[0x1];
e281682b
SM		 326 u8 outer_sip[0x1];
327 u8 outer_dip[0x1];
328 u8 outer_frag[0x1];
329 u8 outer_ip_protocol[0x1];
330 u8 outer_ip_ecn[0x1];
331 u8 outer_ip_dscp[0x1];
332 u8 outer_udp_sport[0x1];
333 u8 outer_udp_dport[0x1];
334 u8 outer_tcp_sport[0x1];
335 u8 outer_tcp_dport[0x1];
336 u8 outer_tcp_flags[0x1];
337 u8 outer_gre_protocol[0x1];
338 u8 outer_gre_key[0x1];
339 u8 outer_vxlan_vni[0x1];
75d90e7d
YK		 340 u8 outer_geneve_vni[0x1];
341 u8 outer_geneve_oam[0x1];
342 u8 outer_geneve_protocol_type[0x1];
343 u8 outer_geneve_opt_len[0x1];
8208461d 344 u8 source_vhca_port[0x1];
e281682b
SM		 345 u8 source_eswitch_port[0x1];
346
347 u8 inner_dmac[0x1];
348 u8 inner_smac[0x1];
349 u8 inner_ether_type[0x1];
19cc7524 350 u8 inner_ip_version[0x1];
e281682b
SM		 351 u8 inner_first_prio[0x1];
352 u8 inner_first_cfi[0x1];
353 u8 inner_first_vid[0x1];
b4ff3a36 354 u8 reserved_at_27[0x1];
e281682b
SM		 355 u8 inner_second_prio[0x1];
356 u8 inner_second_cfi[0x1];
357 u8 inner_second_vid[0x1];
b4ff3a36 358 u8 reserved_at_2b[0x1];
e281682b
SM		 359 u8 inner_sip[0x1];
360 u8 inner_dip[0x1];
361 u8 inner_frag[0x1];
362 u8 inner_ip_protocol[0x1];
363 u8 inner_ip_ecn[0x1];
364 u8 inner_ip_dscp[0x1];
365 u8 inner_udp_sport[0x1];
366 u8 inner_udp_dport[0x1];
367 u8 inner_tcp_sport[0x1];
368 u8 inner_tcp_dport[0x1];
369 u8 inner_tcp_flags[0x1];
b4ff3a36 370 u8 reserved_at_37[0x9];
71c6e863 371
b169e64a 372 u8 geneve_tlv_option_0_data[0x1];
f59464e2
YK		 373 u8 geneve_tlv_option_0_exist[0x1];
374 u8 reserved_at_42[0x3];
71c6e863
AL		 375 u8 outer_first_mpls_over_udp[0x4];
376 u8 outer_first_mpls_over_gre[0x4];
377 u8 inner_first_mpls[0x4];
378 u8 outer_first_mpls[0x4];
379 u8 reserved_at_55[0x2];
3346c487 380 u8 outer_esp_spi[0x1];
71c6e863 381 u8 reserved_at_58[0x2];
a550ddfc 382 u8 bth_dst_qp[0x1];
822e114b 383 u8 reserved_at_5b[0x5];
e281682b 384
822e114b
PB		 385 u8 reserved_at_60[0x18];
386 u8 metadata_reg_c_7[0x1];
387 u8 metadata_reg_c_6[0x1];
388 u8 metadata_reg_c_5[0x1];
389 u8 metadata_reg_c_4[0x1];
390 u8 metadata_reg_c_3[0x1];
391 u8 metadata_reg_c_2[0x1];
392 u8 metadata_reg_c_1[0x1];
393 u8 metadata_reg_c_0[0x1];
e281682b
SM		 394};
395
8208461d
AL		 396struct mlx5_ifc_flow_table_fields_supported_2_bits {
397 u8 reserved_at_0[0xe];
398 u8 bth_opcode[0x1];
399 u8 reserved_at_f[0x11];
400
401 u8 reserved_at_20[0x60];
402};
403
e281682b
SM		 404struct mlx5_ifc_flow_table_prop_layout_bits {
405 u8 ft_support[0x1];
9dc0b289
AV		 406 u8 reserved_at_1[0x1];
407 u8 flow_counter[0x1];
26a81453 408 u8 flow_modify_en[0x1];
2cc43b49 409 u8 modify_root[0x1];
34a40e68
MG		 410 u8 identified_miss_table_mode[0x1];
411 u8 flow_table_modify[0x1];
60786f09 412 u8 reformat[0x1];
7adbde20 413 u8 decap[0x1];
0c06897a
OG		 414 u8 reserved_at_9[0x1];
415 u8 pop_vlan[0x1];
416 u8 push_vlan[0x1];
8da6fe2a
JL		 417 u8 reserved_at_c[0x1];
418 u8 pop_vlan_2[0x1];
419 u8 push_vlan_2[0x1];
bea4e1f6 420 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 421 u8 reserved_at_10[0x1];
422 u8 sw_owner[0x1];
bea4e1f6
MB		 423 u8 reformat_l3_tunnel_to_l2[0x1];
424 u8 reformat_l2_to_l3_tunnel[0x1];
425 u8 reformat_and_modify_action[0x1];
822e114b
PB		 426 u8 ignore_flow_level[0x1];
427 u8 reserved_at_16[0x1];
f6f7d6b5 428 u8 table_miss_action_domain[0x1];
c6d4e45d 429 u8 termination_table[0x1];
e0ebd8eb 430 u8 reformat_and_fwd_to_table[0x1];
78fb6122
HN		 431 u8 reserved_at_1a[0x2];
432 u8 ipsec_encrypt[0x1];
433 u8 ipsec_decrypt[0x1];
9d8feb46
AV		 434 u8 sw_owner_v2[0x1];
435 u8 reserved_at_1f[0x1];
78fb6122 436
613f53fe
EC		 437 u8 termination_table_raw_traffic[0x1];
438 u8 reserved_at_21[0x1];
e281682b 439 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 440 u8 log_max_modify_header_context[0x8];
441 u8 max_modify_header_actions[0x8];
e281682b
SM		 442 u8 max_ft_level[0x8];
443
b4ff3a36 444 u8 reserved_at_40[0x20];
e281682b 445
67133eaa
YK		 446 u8 reserved_at_60[0x2];
447 u8 reformat_insert[0x1];
448 u8 reformat_remove[0x1];
449 u8 reserver_at_64[0x14];
e281682b
SM		 450 u8 log_max_ft_num[0x8];
451
a14587df
RS		 452 u8 reserved_at_80[0x10];
453 u8 log_max_flow_counter[0x8];
e281682b
SM		 454 u8 log_max_destination[0x8];
455
a14587df 456 u8 reserved_at_a0[0x18];
e281682b
SM		 457 u8 log_max_flow[0x8];
458
b4ff3a36 459 u8 reserved_at_c0[0x40];
e281682b
SM		 460
461 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
462
463 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
464};
465
466struct mlx5_ifc_odp_per_transport_service_cap_bits {
467 u8 send[0x1];
468 u8 receive[0x1];
469 u8 write[0x1];
470 u8 read[0x1];
17d2f88f 471 u8 atomic[0x1];
e281682b 472 u8 srq_receive[0x1];
b4ff3a36 473 u8 reserved_at_6[0x1a];
e281682b
SM		 474};
475
476struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
477 u8 smac_47_16[0x20];
478
479 u8 smac_15_0[0x10];
480 u8 ethertype[0x10];
481
482 u8 dmac_47_16[0x20];
483
484 u8 dmac_15_0[0x10];
485 u8 first_prio[0x3];
486 u8 first_cfi[0x1];
487 u8 first_vid[0xc];
488
489 u8 ip_protocol[0x8];
490 u8 ip_dscp[0x6];
491 u8 ip_ecn[0x2];
10543365
MHY		 492 u8 cvlan_tag[0x1];
493 u8 svlan_tag[0x1];
e281682b 494 u8 frag[0x1];
19cc7524 495 u8 ip_version[0x4];
e281682b
SM		 496 u8 tcp_flags[0x9];
497
498 u8 tcp_sport[0x10];
499 u8 tcp_dport[0x10];
500
5c422bfa
YK		 501 u8 reserved_at_c0[0x10];
502 u8 ipv4_ihl[0x4];
503 u8 reserved_at_c4[0x4];
504
a8ade55f 505 u8 ttl_hoplimit[0x8];
e281682b
SM		 506
507 u8 udp_sport[0x10];
508 u8 udp_dport[0x10];
509
b4d1f032 510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 511
b4d1f032 512 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 513};
514
5886a96a
OS		 515struct mlx5_ifc_nvgre_key_bits {
516 u8 hi[0x18];
517 u8 lo[0x8];
518};
519
520union mlx5_ifc_gre_key_bits {
521 struct mlx5_ifc_nvgre_key_bits nvgre;
522 u8 key[0x20];
523};
524
e281682b 525struct mlx5_ifc_fte_match_set_misc_bits {
97b5484e 526 u8 gre_c_present[0x1];
d32d7c52 527 u8 reserved_at_1[0x1];
97b5484e
AV		 528 u8 gre_k_present[0x1];
529 u8 gre_s_present[0x1];
530 u8 source_vhca_port[0x4];
7486216b 531 u8 source_sqn[0x18];
e281682b 532
3e99df87 533 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 534 u8 source_port[0x10];
535
536 u8 outer_second_prio[0x3];
537 u8 outer_second_cfi[0x1];
538 u8 outer_second_vid[0xc];
539 u8 inner_second_prio[0x3];
540 u8 inner_second_cfi[0x1];
541 u8 inner_second_vid[0xc];
542
10543365
MHY		 543 u8 outer_second_cvlan_tag[0x1];
544 u8 inner_second_cvlan_tag[0x1];
545 u8 outer_second_svlan_tag[0x1];
546 u8 inner_second_svlan_tag[0x1];
547 u8 reserved_at_64[0xc];
e281682b
SM		 548 u8 gre_protocol[0x10];
549
5886a96a 550 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 551
552 u8 vxlan_vni[0x18];
8208461d 553 u8 bth_opcode[0x8];
e281682b 554
75d90e7d 555 u8 geneve_vni[0x18];
f59464e2
YK		 556 u8 reserved_at_d8[0x6];
557 u8 geneve_tlv_option_0_exist[0x1];
75d90e7d 558 u8 geneve_oam[0x1];
e281682b 559
b4ff3a36 560 u8 reserved_at_e0[0xc];
e281682b
SM		 561 u8 outer_ipv6_flow_label[0x14];
562
b4ff3a36 563 u8 reserved_at_100[0xc];
e281682b
SM		 564 u8 inner_ipv6_flow_label[0x14];
565
75d90e7d
YK		 566 u8 reserved_at_120[0xa];
567 u8 geneve_opt_len[0x6];
568 u8 geneve_protocol_type[0x10];
569
570 u8 reserved_at_140[0x8];
a550ddfc 571 u8 bth_dst_qp[0x18];
3346c487
BP		 572 u8 reserved_at_160[0x20];
573 u8 outer_esp_spi[0x20];
574 u8 reserved_at_1a0[0x60];
e281682b
SM		 575};
576
71c6e863
AL		 577struct mlx5_ifc_fte_match_mpls_bits {
578 u8 mpls_label[0x14];
579 u8 mpls_exp[0x3];
580 u8 mpls_s_bos[0x1];
581 u8 mpls_ttl[0x8];
582};
583
584struct mlx5_ifc_fte_match_set_misc2_bits {
585 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
586
587 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
588
589 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
590
591 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
592
65c0f2c1
JL		 593 u8 metadata_reg_c_7[0x20];
594
595 u8 metadata_reg_c_6[0x20];
596
597 u8 metadata_reg_c_5[0x20];
598
599 u8 metadata_reg_c_4[0x20];
600
601 u8 metadata_reg_c_3[0x20];
602
603 u8 metadata_reg_c_2[0x20];
604
605 u8 metadata_reg_c_1[0x20];
606
607 u8 metadata_reg_c_0[0x20];
71c6e863
AL		 608
609 u8 metadata_reg_a[0x20];
610
356d411c 611 u8 reserved_at_1a0[0x60];
71c6e863
AL		 612};
613
b169e64a 614struct mlx5_ifc_fte_match_set_misc3_bits {
97b5484e
AV		 615 u8 inner_tcp_seq_num[0x20];
616
617 u8 outer_tcp_seq_num[0x20];
618
619 u8 inner_tcp_ack_num[0x20];
620
621 u8 outer_tcp_ack_num[0x20];
622
623 u8 reserved_at_80[0x8];
624 u8 outer_vxlan_gpe_vni[0x18];
625
626 u8 outer_vxlan_gpe_next_protocol[0x8];
627 u8 outer_vxlan_gpe_flags[0x8];
628 u8 reserved_at_b0[0x10];
629
630 u8 icmp_header_data[0x20];
631
632 u8 icmpv6_header_data[0x20];
633
634 u8 icmp_type[0x8];
635 u8 icmp_code[0x8];
636 u8 icmpv6_type[0x8];
637 u8 icmpv6_code[0x8];
638
b169e64a 639 u8 geneve_tlv_option_0_data[0x20];
97b5484e 640
704cfecd
YK		 641 u8 gtpu_teid[0x20];
642
643 u8 gtpu_msg_type[0x8];
644 u8 gtpu_msg_flags[0x8];
645 u8 reserved_at_170[0x10];
646
647 u8 gtpu_dw_2[0x20];
648
649 u8 gtpu_first_ext_dw_0[0x20];
650
651 u8 gtpu_dw_0[0x20];
652
653 u8 reserved_at_1e0[0x20];
b169e64a
YK		 654};
655
7da3ad6c
MS		 656struct mlx5_ifc_fte_match_set_misc4_bits {
657 u8 prog_sample_field_value_0[0x20];
658
659 u8 prog_sample_field_id_0[0x20];
660
661 u8 prog_sample_field_value_1[0x20];
662
663 u8 prog_sample_field_id_1[0x20];
664
665 u8 prog_sample_field_value_2[0x20];
666
667 u8 prog_sample_field_id_2[0x20];
668
669 u8 prog_sample_field_value_3[0x20];
670
671 u8 prog_sample_field_id_3[0x20];
672
673 u8 reserved_at_100[0x100];
674};
675
0f2a6c3b
MS		 676struct mlx5_ifc_fte_match_set_misc5_bits {
677 u8 macsec_tag_0[0x20];
678
679 u8 macsec_tag_1[0x20];
680
681 u8 macsec_tag_2[0x20];
682
683 u8 macsec_tag_3[0x20];
684
685 u8 tunnel_header_0[0x20];
686
687 u8 tunnel_header_1[0x20];
688
689 u8 tunnel_header_2[0x20];
690
691 u8 tunnel_header_3[0x20];
692
693 u8 reserved_at_100[0x100];
694};
695
e281682b
SM		 696struct mlx5_ifc_cmd_pas_bits {
697 u8 pa_h[0x20];
698
699 u8 pa_l[0x14];
b4ff3a36 700 u8 reserved_at_34[0xc];
e281682b
SM		 701};
702
703struct mlx5_ifc_uint64_bits {
704 u8 hi[0x20];
705
706 u8 lo[0x20];
707};
708
709enum {
710 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
711 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
712 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
713 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
714 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
715 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
716 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
717 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
718 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
719 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
720};
721
722struct mlx5_ifc_ads_bits {
723 u8 fl[0x1];
724 u8 free_ar[0x1];
b4ff3a36 725 u8 reserved_at_2[0xe];
e281682b
SM		 726 u8 pkey_index[0x10];
727
b4ff3a36 728 u8 reserved_at_20[0x8];
e281682b
SM		 729 u8 grh[0x1];
730 u8 mlid[0x7];
731 u8 rlid[0x10];
732
733 u8 ack_timeout[0x5];
b4ff3a36 734 u8 reserved_at_45[0x3];
e281682b 735 u8 src_addr_index[0x8];
b4ff3a36 736 u8 reserved_at_50[0x4];
e281682b
SM		 737 u8 stat_rate[0x4];
738 u8 hop_limit[0x8];
739
b4ff3a36 740 u8 reserved_at_60[0x4];
e281682b
SM		 741 u8 tclass[0x8];
742 u8 flow_label[0x14];
743
744 u8 rgid_rip[16][0x8];
745
b4ff3a36 746 u8 reserved_at_100[0x4];
e281682b
SM		 747 u8 f_dscp[0x1];
748 u8 f_ecn[0x1];
b4ff3a36 749 u8 reserved_at_106[0x1];
e281682b
SM		 750 u8 f_eth_prio[0x1];
751 u8 ecn[0x2];
752 u8 dscp[0x6];
753 u8 udp_sport[0x10];
754
755 u8 dei_cfi[0x1];
756 u8 eth_prio[0x3];
757 u8 sl[0x4];
32f69e4b 758 u8 vhca_port_num[0x8];
e281682b
SM		 759 u8 rmac_47_32[0x10];
760
761 u8 rmac_31_0[0x20];
762};
763
764struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 765 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 766 u8 nic_rx_multi_path_tirs_fts[0x1];
767 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
13a7e459
ES		 768 u8 reserved_at_3[0x4];
769 u8 sw_owner_reformat_supported[0x1];
770 u8 reserved_at_8[0x18];
771
bea4e1f6
MB		 772 u8 encap_general_header[0x1];
773 u8 reserved_at_21[0xa];
774 u8 log_max_packet_reformat_context[0x5];
775 u8 reserved_at_30[0x6];
776 u8 max_encap_header_size[0xa];
777 u8 reserved_at_40[0x1c0];
e281682b
SM		 778
779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
780
d83eb50e 781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
e281682b
SM		 782
783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
784
785 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
786
24670b1a 787 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
e281682b
SM		 788
789 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
790
8208461d
AL		 791 u8 reserved_at_e00[0x700];
792
793 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
794
795 u8 reserved_at_1580[0x280];
796
797 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
798
799 u8 reserved_at_1880[0x780];
97b5484e
AV		 800
801 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
802
803 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
804
805 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
806
807 u8 reserved_at_20c0[0x5f40];
e281682b
SM		 808};
809
425a563a
MG		 810struct mlx5_ifc_port_selection_cap_bits {
811 u8 reserved_at_0[0x10];
812 u8 port_select_flow_table[0x1];
813 u8 reserved_at_11[0xf];
814
815 u8 reserved_at_20[0x1e0];
816
817 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
818
819 u8 reserved_at_400[0x7c00];
820};
821
65c0f2c1
JL		 822enum {
823 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
824 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
825 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
826 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
827 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
828 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
829 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
830 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
831};
832
495716b1 833struct mlx5_ifc_flow_table_eswitch_cap_bits {
65c0f2c1 834 u8 fdb_to_vport_reg_c_id[0x8];
822e114b
PB		 835 u8 reserved_at_8[0xd];
836 u8 fdb_modify_header_fwd_to_table[0x1];
4ff725e1 837 u8 fdb_ipv4_ttl_modify[0x1];
65c0f2c1
JL		 838 u8 flow_source[0x1];
839 u8 reserved_at_18[0x2];
b9aa0ba1 840 u8 multi_fdb_encap[0x1];
86f5d0f3 841 u8 egress_acl_forward_to_vport[0x1];
663f146f
VP		 842 u8 fdb_multi_path_to_table[0x1];
843 u8 reserved_at_1d[0x3];
844
845 u8 reserved_at_20[0x1e0];
495716b1
SM		 846
847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
848
849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
850
851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
852
97b5484e
AV		 853 u8 reserved_at_800[0x1000];
854
855 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
856
857 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
858
859 u8 sw_steering_uplink_icm_address_rx[0x40];
860
861 u8 sw_steering_uplink_icm_address_tx[0x40];
862
863 u8 reserved_at_1900[0x6700];
495716b1
SM		 864};
865
8bb957d2
SK		 866enum {
867 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
868 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
869};
870
d6666753
SM		 871struct mlx5_ifc_e_switch_cap_bits {
872 u8 vport_svlan_strip[0x1];
873 u8 vport_cvlan_strip[0x1];
874 u8 vport_svlan_insert[0x1];
875 u8 vport_cvlan_insert_if_not_exist[0x1];
876 u8 vport_cvlan_insert_overwrite[0x1];
c3e666f1
MB		 877 u8 reserved_at_5[0x2];
878 u8 esw_shared_ingress_acl[0x1];
65c0f2c1 879 u8 esw_uplink_ingress_acl[0x1];
c3e666f1
MB		 880 u8 root_ft_on_other_esw[0x1];
881 u8 reserved_at_a[0xf];
6706a3b9
VP		 882 u8 esw_functions_changed[0x1];
883 u8 reserved_at_1a[0x1];
81cd229c 884 u8 ecpf_vport_exists[0x1];
8bb957d2 885 u8 counter_eswitch_affinity[0x1];
a6d04569 886 u8 merged_eswitch[0x1];
23898c76
NO		 887 u8 nic_vport_node_guid_modify[0x1];
888 u8 nic_vport_port_guid_modify[0x1];
d6666753 889
7adbde20
HHZ		 890 u8 vxlan_encap_decap[0x1];
891 u8 nvgre_encap_decap[0x1];
1b115498
EB		 892 u8 reserved_at_22[0x1];
893 u8 log_max_fdb_encap_uplink[0x5];
894 u8 reserved_at_21[0x3];
60786f09 895 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 896 u8 reserved_2b[0x6];
897 u8 max_encap_header_size[0xa];
898
1759d322
PP		 899 u8 reserved_at_40[0xb];
900 u8 log_max_esw_sf[0x5];
901 u8 esw_sf_base_id[0x10];
902
903 u8 reserved_at_60[0x7a0];
7adbde20 904
d6666753
SM		 905};
906
7486216b
SM		 907struct mlx5_ifc_qos_cap_bits {
908 u8 packet_pacing[0x1];
813f8540 909 u8 esw_scheduling[0x1];
c9497c98
MHY		 910 u8 esw_bw_share[0x1];
911 u8 esw_rate_limit[0x1];
05d3ac97
BW		 912 u8 reserved_at_4[0x1];
913 u8 packet_pacing_burst_bound[0x1];
914 u8 packet_pacing_typical_size[0x1];
214baf22
MM		 915 u8 reserved_at_7[0x1];
916 u8 nic_sq_scheduling[0x1];
917 u8 nic_bw_share[0x1];
918 u8 nic_rate_limit[0x1];
1326034b 919 u8 packet_pacing_uid[0x1];
1ae258f8
DL		 920 u8 log_esw_max_sched_depth[0x4];
921 u8 reserved_at_10[0x10];
813f8540 922
214baf22
MM		 923 u8 reserved_at_20[0xb];
924 u8 log_max_qos_nic_queue_group[0x5];
925 u8 reserved_at_30[0x10];
813f8540 926
7486216b 927 u8 packet_pacing_max_rate[0x20];
813f8540 928
7486216b 929 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 930
931 u8 reserved_at_80[0x10];
7486216b 932 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 933
934 u8 esw_element_type[0x10];
935 u8 esw_tsar_type[0x10];
936
937 u8 reserved_at_c0[0x10];
938 u8 max_qos_para_vport[0x10];
939
940 u8 max_tsar_bw_share[0x20];
941
942 u8 reserved_at_100[0x700];
7486216b
SM		 943};
944
2fcb12df 945struct mlx5_ifc_debug_cap_bits {
0b9055a1
MS		 946 u8 core_dump_general[0x1];
947 u8 core_dump_qp[0x1];
609b8272
AL		 948 u8 reserved_at_2[0x7];
949 u8 resource_dump[0x1];
950 u8 reserved_at_a[0x16];
2fcb12df
IK		 951
952 u8 reserved_at_20[0x2];
953 u8 stall_detect[0x1];
954 u8 reserved_at_23[0x1d];
955
956 u8 reserved_at_40[0x7c0];
957};
958
e281682b
SM		 959struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
960 u8 csum_cap[0x1];
961 u8 vlan_cap[0x1];
962 u8 lro_cap[0x1];
963 u8 lro_psh_flag[0x1];
964 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 965 u8 reserved_at_5[0x2];
966 u8 wqe_vlan_insert[0x1];
66189961 967 u8 self_lb_en_modifiable[0x1];
b4ff3a36 968 u8 reserved_at_9[0x2];
e281682b 969 u8 max_lso_cap[0x5];
c226dc22 970 u8 multi_pkt_send_wqe[0x2];
cff92d7c 971 u8 wqe_inline_mode[0x2];
e281682b 972 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 973 u8 reg_umr_sq[0x1];
974 u8 scatter_fcs[0x1];
050da902 975 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 976 u8 tunnel_lso_const_out_ip_id[0x1];
26ab7b38
MM		 977 u8 tunnel_lro_gre[0x1];
978 u8 tunnel_lro_vxlan[0x1];
27299841 979 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 980 u8 tunnel_stateless_vxlan[0x1];
981
547eede0
IT		 982 u8 swp[0x1];
983 u8 swp_csum[0x1];
984 u8 swp_lso[0x1];
db849faa 985 u8 cqe_checksum_full[0x1];
41e684ef
AV		 986 u8 tunnel_stateless_geneve_tx[0x1];
987 u8 tunnel_stateless_mpls_over_udp[0x1];
988 u8 tunnel_stateless_mpls_over_gre[0x1];
989 u8 tunnel_stateless_vxlan_gpe[0x1];
990 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
caa18547 991 u8 tunnel_stateless_ip_over_ip[0x1];
2b58f6d9 992 u8 insert_trailer[0x1];
21adf05d
AL		 993 u8 reserved_at_2b[0x1];
994 u8 tunnel_stateless_ip_over_ip_rx[0x1];
995 u8 tunnel_stateless_ip_over_ip_tx[0x1];
996 u8 reserved_at_2e[0x2];
22a65aa8
GP		 997 u8 max_vxlan_udp_ports[0x8];
998 u8 reserved_at_38[0x6];
4d350f1f
MG		 999 u8 max_geneve_opt_len[0x1];
1000 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 1001
b4ff3a36 1002 u8 reserved_at_40[0x10];
e281682b
SM		 1003 u8 lro_min_mss_size[0x10];
1004
b4ff3a36 1005 u8 reserved_at_60[0x120];
e281682b
SM		 1006
1007 u8 lro_timer_supported_periods[4][0x20];
1008
b4ff3a36 1009 u8 reserved_at_200[0x600];
e281682b
SM		 1010};
1011
a6a217dd 1012enum {
9a1ac95a
AL		 1013 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1014 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1015 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
a6a217dd
AL		 1016};
1017
e281682b
SM		 1018struct mlx5_ifc_roce_cap_bits {
1019 u8 roce_apm[0x1];
59e9e8e4
MZ		 1020 u8 reserved_at_1[0x3];
1021 u8 sw_r_roce_src_udp_port[0x1];
7304d603
YK		 1022 u8 fl_rc_qp_when_roce_disabled[0x1];
1023 u8 fl_rc_qp_when_roce_enabled[0x1];
1024 u8 reserved_at_7[0x17];
a6a217dd 1025 u8 qp_ts_format[0x2];
e281682b 1026
b4ff3a36 1027 u8 reserved_at_20[0x60];
e281682b 1028
b4ff3a36 1029 u8 reserved_at_80[0xc];
e281682b 1030 u8 l3_type[0x4];
b4ff3a36 1031 u8 reserved_at_90[0x8];
e281682b
SM		 1032 u8 roce_version[0x8];
1033
b4ff3a36 1034 u8 reserved_at_a0[0x10];
e281682b
SM		 1035 u8 r_roce_dest_udp_port[0x10];
1036
1037 u8 r_roce_max_src_udp_port[0x10];
1038 u8 r_roce_min_src_udp_port[0x10];
1039
b4ff3a36 1040 u8 reserved_at_e0[0x10];
e281682b
SM		 1041 u8 roce_address_table_size[0x10];
1042
b4ff3a36 1043 u8 reserved_at_100[0x700];
e281682b
SM		 1044};
1045
97b5484e
AV		 1046struct mlx5_ifc_sync_steering_in_bits {
1047 u8 opcode[0x10];
1048 u8 uid[0x10];
1049
1050 u8 reserved_at_20[0x10];
1051 u8 op_mod[0x10];
1052
1053 u8 reserved_at_40[0xc0];
1054};
1055
1056struct mlx5_ifc_sync_steering_out_bits {
1057 u8 status[0x8];
1058 u8 reserved_at_8[0x18];
1059
1060 u8 syndrome[0x20];
1061
1062 u8 reserved_at_40[0x40];
1063};
1064
e72bd817
AL		 1065struct mlx5_ifc_device_mem_cap_bits {
1066 u8 memic[0x1];
1067 u8 reserved_at_1[0x1f];
1068
1069 u8 reserved_at_20[0xb];
1070 u8 log_min_memic_alloc_size[0x5];
1071 u8 reserved_at_30[0x8];
1072 u8 log_max_memic_addr_alignment[0x8];
1073
1074 u8 memic_bar_start_addr[0x40];
1075
1076 u8 memic_bar_size[0x20];
1077
1078 u8 max_memic_size[0x20];
1079
9fba2b9b
AL		 1080 u8 steering_sw_icm_start_address[0x40];
1081
1082 u8 reserved_at_100[0x8];
1083 u8 log_header_modify_sw_icm_size[0x8];
1084 u8 reserved_at_110[0x2];
1085 u8 log_sw_icm_alloc_granularity[0x6];
1086 u8 log_steering_sw_icm_size[0x8];
1087
1088 u8 reserved_at_120[0x20];
1089
1090 u8 header_modify_sw_icm_start_address[0x40];
1091
63f9c44b
MG		 1092 u8 reserved_at_180[0x80];
1093
1094 u8 memic_operations[0x20];
1095
1096 u8 reserved_at_220[0x5e0];
e72bd817
AL		 1097};
1098
b9a7ba55
YH		 1099struct mlx5_ifc_device_event_cap_bits {
1100 u8 user_affiliated_events[4][0x40];
1101
1102 u8 user_unaffiliated_events[4][0x40];
1103};
1104
8a06a79b
EC		 1105struct mlx5_ifc_virtio_emulation_cap_bits {
1106 u8 desc_tunnel_offload_type[0x1];
1107 u8 eth_frame_offload_type[0x1];
1108 u8 virtio_version_1_0[0x1];
1109 u8 device_features_bits_mask[0xd];
1110 u8 event_mode[0x8];
1111 u8 virtio_queue_type[0x8];
90fbca59 1112
8a06a79b
EC		 1113 u8 max_tunnel_desc[0x10];
1114 u8 reserved_at_30[0x3];
90fbca59
YH		 1115 u8 log_doorbell_stride[0x5];
1116 u8 reserved_at_38[0x3];
1117 u8 log_doorbell_bar_size[0x5];
1118
1119 u8 doorbell_bar_offset[0x40];
1120
8a06a79b
EC		 1121 u8 max_emulated_devices[0x8];
1122 u8 max_num_virtio_queues[0x18];
1123
1124 u8 reserved_at_a0[0x60];
1125
1126 u8 umem_1_buffer_param_a[0x20];
1127
1128 u8 umem_1_buffer_param_b[0x20];
1129
1130 u8 umem_2_buffer_param_a[0x20];
1131
1132 u8 umem_2_buffer_param_b[0x20];
1133
1134 u8 umem_3_buffer_param_a[0x20];
1135
1136 u8 umem_3_buffer_param_b[0x20];
1137
1138 u8 reserved_at_1c0[0x640];
90fbca59
YH		 1139};
1140
e281682b
SM		 1141enum {
1142 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1143 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1144 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1145 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1146 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1147 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1148 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1149 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1150 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1151};
1152
1153enum {
1154 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1155 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1156 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1157 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1163};
1164
1165struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 1166 u8 reserved_at_0[0x40];
e281682b 1167
bd10838a 1168 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 1169 u8 reserved_at_42[0x4];
bd10838a 1170 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 1171
b4ff3a36 1172 u8 reserved_at_47[0x19];
e281682b 1173
b4ff3a36 1174 u8 reserved_at_60[0x20];
e281682b 1175
b4ff3a36 1176 u8 reserved_at_80[0x10];
f91e6d89 1177 u8 atomic_operations[0x10];
e281682b 1178
b4ff3a36 1179 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 1180 u8 atomic_size_qp[0x10];
1181
b4ff3a36 1182 u8 reserved_at_c0[0x10];
e281682b
SM		 1183 u8 atomic_size_dc[0x10];
1184
b4ff3a36 1185 u8 reserved_at_e0[0x720];
e281682b
SM		 1186};
1187
1188struct mlx5_ifc_odp_cap_bits {
b4ff3a36 1189 u8 reserved_at_0[0x40];
e281682b
SM		 1190
1191 u8 sig[0x1];
b4ff3a36 1192 u8 reserved_at_41[0x1f];
e281682b 1193
b4ff3a36 1194 u8 reserved_at_60[0x20];
e281682b
SM		 1195
1196 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1197
1198 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1199
1200 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1201
dda7a817
MS		 1202 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1203
00679b63
MG		 1204 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1205
1206 u8 reserved_at_120[0x6E0];
e281682b
SM		 1207};
1208
3f0393a5
SG		 1209struct mlx5_ifc_calc_op {
1210 u8 reserved_at_0[0x10];
1211 u8 reserved_at_10[0x9];
1212 u8 op_swap_endianness[0x1];
1213 u8 op_min[0x1];
1214 u8 op_xor[0x1];
1215 u8 op_or[0x1];
1216 u8 op_and[0x1];
1217 u8 op_max[0x1];
1218 u8 op_add[0x1];
1219};
1220
1221struct mlx5_ifc_vector_calc_cap_bits {
1222 u8 calc_matrix[0x1];
1223 u8 reserved_at_1[0x1f];
1224 u8 reserved_at_20[0x8];
1225 u8 max_vec_count[0x8];
1226 u8 reserved_at_30[0xd];
1227 u8 max_chunk_size[0x3];
1228 struct mlx5_ifc_calc_op calc0;
1229 struct mlx5_ifc_calc_op calc1;
1230 struct mlx5_ifc_calc_op calc2;
1231 struct mlx5_ifc_calc_op calc3;
1232
c74d90c1 1233 u8 reserved_at_c0[0x720];
3f0393a5
SG		 1234};
1235
a12ff35e
EBE		 1236struct mlx5_ifc_tls_cap_bits {
1237 u8 tls_1_2_aes_gcm_128[0x1];
1238 u8 tls_1_3_aes_gcm_128[0x1];
1239 u8 tls_1_2_aes_gcm_256[0x1];
1240 u8 tls_1_3_aes_gcm_256[0x1];
1241 u8 reserved_at_4[0x1c];
1242
1243 u8 reserved_at_20[0x7e0];
1244};
1245
2b58f6d9
RS		 1246struct mlx5_ifc_ipsec_cap_bits {
1247 u8 ipsec_full_offload[0x1];
1248 u8 ipsec_crypto_offload[0x1];
1249 u8 ipsec_esn[0x1];
1250 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1251 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1252 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1253 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1254 u8 reserved_at_7[0x4];
1255 u8 log_max_ipsec_offload[0x5];
1256 u8 reserved_at_10[0x10];
1257
1258 u8 min_log_ipsec_full_replay_window[0x8];
1259 u8 max_log_ipsec_full_replay_window[0x8];
1260 u8 reserved_at_30[0x7d0];
1261};
1262
e281682b
SM		 1263enum {
1264 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1265 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 1266 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 1267 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 1268};
1269
1270enum {
1271 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1272 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1273};
1274
1275enum {
1276 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1277 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1278 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1279 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1280 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1281};
1282
1283enum {
1284 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1285 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1286 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1287 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1288 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1289 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1290};
1291
1292enum {
1293 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1294 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1295};
1296
1297enum {
1298 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1299 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1300 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1301};
1302
1303enum {
1304 MLX5_CAP_PORT_TYPE_IB = 0x0,
1305 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 1306};
1307
1410a90a
MG		 1308enum {
1309 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1310 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1311 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1312};
1313
97b5484e 1314enum {
a18fab48 1315 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
704cfecd 1316 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
c3fb0e28 1317 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
97b5484e
AV		 1318 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1319 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1320 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
704cfecd
YK		 1321 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1322 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1323 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1324 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1325 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1326 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
97b5484e
AV		 1327};
1328
9d43faac
YH		 1329enum {
1330 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 1331 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 1332};
1333
8536a6bf
GT		 1334#define MLX5_FC_BULK_SIZE_FACTOR 128
1335
1336enum mlx5_fc_bulk_alloc_bitmask {
1337 MLX5_FC_BULK_128 = (1 << 0),
1338 MLX5_FC_BULK_256 = (1 << 1),
1339 MLX5_FC_BULK_512 = (1 << 2),
1340 MLX5_FC_BULK_1024 = (1 << 3),
1341 MLX5_FC_BULK_2048 = (1 << 4),
1342 MLX5_FC_BULK_4096 = (1 << 5),
1343 MLX5_FC_BULK_8192 = (1 << 6),
1344 MLX5_FC_BULK_16384 = (1 << 7),
1345};
1346
1347#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1348
216214c6
YK		 1349#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1350
d421e466
YK		 1351enum {
1352 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1353 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
6862c787 1354 MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
d421e466
YK		 1355};
1356
b775516b 1357struct mlx5_ifc_cmd_hca_cap_bits {
959af556
YH		 1358 u8 reserved_at_0[0x1f];
1359 u8 vhca_resource_manager[0x1];
349125ba 1360
67133eaa 1361 u8 hca_cap_2[0x1];
4b2c5fa9
AT		 1362 u8 reserved_at_21[0x1];
1363 u8 dtor[0x1];
349125ba
PP		 1364 u8 event_on_vhca_state_teardown_request[0x1];
1365 u8 event_on_vhca_state_in_use[0x1];
1366 u8 event_on_vhca_state_active[0x1];
1367 u8 event_on_vhca_state_allocated[0x1];
1368 u8 event_on_vhca_state_invalid[0x1];
1369 u8 reserved_at_28[0x8];
32f69e4b
DJ		 1370 u8 vhca_id[0x10];
1371
1372 u8 reserved_at_40[0x40];
b775516b
EC		 1373
1374 u8 log_max_srq_sz[0x8];
1375 u8 log_max_qp_sz[0x8];
b9a7ba55 1376 u8 event_cap[0x1];
aeacb52a
YK		 1377 u8 reserved_at_91[0x2];
1378 u8 isolate_vl_tc_new[0x1];
1379 u8 reserved_at_94[0x4];
316793fb
EB		 1380 u8 prio_tag_required[0x1];
1381 u8 reserved_at_99[0x2];
b775516b
EC		 1382 u8 log_max_qp[0x5];
1383
6b646a7e
LR		 1384 u8 reserved_at_a0[0x3];
1385 u8 ece_support[0x1];
838b00a2
PB		 1386 u8 reserved_at_a4[0x5];
1387 u8 reg_c_preserve[0x1];
1388 u8 reserved_at_aa[0x1];
e281682b 1389 u8 log_max_srq[0x5];
9c9be85f
AL		 1390 u8 reserved_at_b0[0x1];
1391 u8 uplink_follow[0x1];
59d2ae1d 1392 u8 ts_cqe_to_dest_cqn[0x1];
7025329d
BBI		 1393 u8 reserved_at_b3[0x7];
1394 u8 shampo[0x1];
1395 u8 reserved_at_bb[0x5];
b775516b 1396
7d47433c 1397 u8 max_sgl_for_optimized_performance[0x8];
b775516b 1398 u8 log_max_cq_sz[0x8];
042dd05b
ML		 1399 u8 relaxed_ordering_write_umr[0x1];
1400 u8 relaxed_ordering_read_umr[0x1];
1401 u8 reserved_at_d2[0x7];
8a06a79b
EC		 1402 u8 virtio_net_device_emualtion_manager[0x1];
1403 u8 virtio_blk_device_emualtion_manager[0x1];
b775516b
EC		 1404 u8 log_max_cq[0x5];
1405
1406 u8 log_max_eq_sz[0x8];
a880a6dd
MG		 1407 u8 relaxed_ordering_write[0x1];
1408 u8 relaxed_ordering_read[0x1];
b775516b 1409 u8 log_max_mkey[0x6];
b183ee27
LR		 1410 u8 reserved_at_f0[0x8];
1411 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 1412 u8 reserved_at_f9[0x2];
1413 u8 fast_teardown[0x1];
b775516b
EC		 1414 u8 log_max_eq[0x4];
1415
1416 u8 max_indirection[0x8];
bcda1aca 1417 u8 fixed_buffer_size[0x1];
b775516b 1418 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 1419 u8 force_teardown[0x1];
1420 u8 reserved_at_111[0x1];
b775516b 1421 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 1422 u8 umr_extended_translation_offset[0x1];
1423 u8 null_mkey[0x1];
b775516b
EC		 1424 u8 log_max_klm_list_size[0x6];
1425
b4ff3a36 1426 u8 reserved_at_120[0xa];
b775516b 1427 u8 log_max_ra_req_dc[0x6];
b4ff3a36 1428 u8 reserved_at_130[0xa];
b775516b
EC		 1429 u8 log_max_ra_res_dc[0x6];
1430
d2cb8dda 1431 u8 reserved_at_140[0x5];
0e1533bb 1432 u8 release_all_pages[0x1];
d2cb8dda 1433 u8 must_not_use[0x1];
0e1533bb 1434 u8 reserved_at_147[0x2];
8fd5b75d 1435 u8 roce_accl[0x1];
b775516b 1436 u8 log_max_ra_req_qp[0x6];
b4ff3a36 1437 u8 reserved_at_150[0xa];
b775516b
EC		 1438 u8 log_max_ra_res_qp[0x6];
1439
f32f5bd2 1440 u8 end_pad[0x1];
b775516b
EC		 1441 u8 cc_query_allowed[0x1];
1442 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 1443 u8 start_pad[0x1];
1444 u8 cache_line_128byte[0x1];
f8efee08
MZ		 1445 u8 reserved_at_165[0x4];
1446 u8 rts2rts_qp_counters_set_id[0x1];
30b10e89
MS		 1447 u8 reserved_at_16a[0x2];
1448 u8 vnic_env_int_rq_oob[0x1];
948d3f90
AL		 1449 u8 sbcam_reg[0x1];
1450 u8 reserved_at_16e[0x1];
c02762eb 1451 u8 qcam_reg[0x1];
e281682b 1452 u8 gid_table_size[0x10];
b775516b 1453
e281682b
SM		 1454 u8 out_of_seq_cnt[0x1];
1455 u8 vport_counters[0x1];
7486216b 1456 u8 retransmission_q_counters[0x1];
2fcb12df 1457 u8 debug[0x1];
83b502a1 1458 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1459 u8 rq_delay_drop[0x1];
b775516b
EC		 1460 u8 max_qp_cnt[0xa];
1461 u8 pkey_table_size[0x10];
1462
e281682b
SM		 1463 u8 vport_group_manager[0x1];
1464 u8 vhca_group_manager[0x1];
1465 u8 ib_virt[0x1];
1466 u8 eth_virt[0x1];
61c5b5c9 1467 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1468 u8 ets[0x1];
1469 u8 nic_flow_table[0x1];
0efc8562 1470 u8 eswitch_manager[0x1];
e72bd817 1471 u8 device_memory[0x1];
cfdcbcea
GP		 1472 u8 mcam_reg[0x1];
1473 u8 pcam_reg[0x1];
b775516b 1474 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1475 u8 port_module_event[0x1];
58dcb60a 1476 u8 enhanced_error_q_counters[0x1];
7d5e1423 1477 u8 ports_check[0x1];
7b13558f 1478 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1479 u8 disable_link_up[0x1];
1480 u8 beacon_led[0x1];
e281682b 1481 u8 port_type[0x2];
b775516b
EC		 1482 u8 num_ports[0x8];
1483
f9a1ef72
EE		 1484 u8 reserved_at_1c0[0x1];
1485 u8 pps[0x1];
1486 u8 pps_modify[0x1];
b775516b 1487 u8 log_max_msg[0x5];
e1c9c62b 1488 u8 reserved_at_1c8[0x4];
4f3961ee 1489 u8 max_tc[0x4];
1865ea9a 1490 u8 temp_warn_event[0x1];
7486216b 1491 u8 dcbx[0x1];
246ac981
MG		 1492 u8 general_notification_event[0x1];
1493 u8 reserved_at_1d3[0x2];
e29341fb 1494 u8 fpga[0x1];
928cfe87
TT		 1495 u8 rol_s[0x1];
1496 u8 rol_g[0x1];
e1c9c62b 1497 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1498 u8 wol_s[0x1];
1499 u8 wol_g[0x1];
1500 u8 wol_a[0x1];
1501 u8 wol_b[0x1];
1502 u8 wol_m[0x1];
1503 u8 wol_u[0x1];
1504 u8 wol_p[0x1];
b775516b
EC		 1505
1506 u8 stat_rate_support[0x10];
3df01077
MS		 1507 u8 reserved_at_1f0[0x1];
1508 u8 pci_sync_for_fw_update_event[0x1];
cfc1a89e
MG		 1509 u8 reserved_at_1f2[0x6];
1510 u8 init2_lag_tx_port_affinity[0x1];
1511 u8 reserved_at_1fa[0x3];
e281682b 1512 u8 cqe_version[0x4];
b775516b 1513
e281682b 1514 u8 compact_address_vector[0x1];
7d5e1423 1515 u8 striding_rq[0x1];
500a3d0d
ES		 1516 u8 reserved_at_202[0x1];
1517 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1518 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1519 u8 reserved_at_205[0x1];
1520 u8 repeated_block_disabled[0x1];
1521 u8 umr_modify_entity_size_disabled[0x1];
1522 u8 umr_modify_atomic_disabled[0x1];
1523 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1524 u8 umr_fence[0x2];
94a04d1d
YC		 1525 u8 dc_req_scat_data_cqe[0x1];
1526 u8 reserved_at_20d[0x2];
e281682b 1527 u8 drain_sigerr[0x1];
b775516b
EC		 1528 u8 cmdif_checksum[0x2];
1529 u8 sigerr_cqe[0x1];
e1c9c62b 1530 u8 reserved_at_213[0x1];
b775516b
EC		 1531 u8 wq_signature[0x1];
1532 u8 sctr_data_cqe[0x1];
e1c9c62b 1533 u8 reserved_at_216[0x1];
b775516b
EC		 1534 u8 sho[0x1];
1535 u8 tph[0x1];
1536 u8 rf[0x1];
e281682b 1537 u8 dct[0x1];
7486216b 1538 u8 qos[0x1];
e281682b 1539 u8 eth_net_offloads[0x1];
b775516b
EC		 1540 u8 roce[0x1];
1541 u8 atomic[0x1];
e1c9c62b 1542 u8 reserved_at_21f[0x1];
b775516b
EC		 1543
1544 u8 cq_oi[0x1];
1545 u8 cq_resize[0x1];
1546 u8 cq_moderation[0x1];
e1c9c62b 1547 u8 reserved_at_223[0x3];
e281682b 1548 u8 cq_eq_remap[0x1];
b775516b
EC		 1549 u8 pg[0x1];
1550 u8 block_lb_mc[0x1];
e1c9c62b 1551 u8 reserved_at_229[0x1];
e281682b 1552 u8 scqe_break_moderation[0x1];
7d5e1423 1553 u8 cq_period_start_from_cqe[0x1];
b775516b 1554 u8 cd[0x1];
e1c9c62b 1555 u8 reserved_at_22d[0x1];
b775516b 1556 u8 apm[0x1];
3f0393a5 1557 u8 vector_calc[0x1];
7d5e1423 1558 u8 umr_ptr_rlky[0x1];
d2370e0a 1559 u8 imaicl[0x1];
3fd3c80a
DG		 1560 u8 qp_packet_based[0x1];
1561 u8 reserved_at_233[0x3];
b775516b
EC		 1562 u8 qkv[0x1];
1563 u8 pkv[0x1];
b11a4f9c
HE		 1564 u8 set_deth_sqpn[0x1];
1565 u8 reserved_at_239[0x3];
b775516b
EC		 1566 u8 xrc[0x1];
1567 u8 ud[0x1];
1568 u8 uc[0x1];
1569 u8 rc[0x1];
1570
a6d51b68
EC		 1571 u8 uar_4k[0x1];
1572 u8 reserved_at_241[0x9];
b775516b 1573 u8 uar_sz[0x6];
425a563a
MG		 1574 u8 port_selection_cap[0x1];
1575 u8 reserved_at_248[0x1];
e13cd45d
EC		 1576 u8 umem_uid_0[0x1];
1577 u8 reserved_at_250[0x5];
b775516b
EC		 1578 u8 log_pg_sz[0x8];
1579
1580 u8 bf[0x1];
0dbc6fe0 1581 u8 driver_version[0x1];
e281682b 1582 u8 pad_tx_eth_packet[0x1];
4dca6509
MG		 1583 u8 reserved_at_263[0x3];
1584 u8 mkey_by_name[0x1];
1585 u8 reserved_at_267[0x4];
1586
b775516b 1587 u8 log_bf_reg_size[0x5];
84df61eb 1588
7c4b1ab9
MZ		 1589 u8 reserved_at_270[0x6];
1590 u8 lag_dct[0x2];
1eba383f 1591 u8 lag_tx_port_affinity[0x1];
c3e666f1
MB		 1592 u8 lag_native_fdb_selection[0x1];
1593 u8 reserved_at_27a[0x1];
84df61eb
AH		 1594 u8 lag_master[0x1];
1595 u8 num_lag_ports[0x4];
b775516b 1596
e1c9c62b 1597 u8 reserved_at_280[0x10];
b775516b
EC		 1598 u8 max_wqe_sz_sq[0x10];
1599
e1c9c62b 1600 u8 reserved_at_2a0[0x10];
b775516b
EC		 1601 u8 max_wqe_sz_rq[0x10];
1602
a8ffcc74 1603 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1604 u8 max_wqe_sz_sq_dc[0x10];
1605
e1c9c62b 1606 u8 reserved_at_2e0[0x7];
b775516b
EC		 1607 u8 max_qp_mcg[0x19];
1608
8536a6bf
GT		 1609 u8 reserved_at_300[0x10];
1610 u8 flow_counter_bulk_alloc[0x8];
b775516b
EC		 1611 u8 log_max_mcg[0x8];
1612
e1c9c62b 1613 u8 reserved_at_320[0x3];
e281682b 1614 u8 log_max_transport_domain[0x5];
e1c9c62b 1615 u8 reserved_at_328[0x3];
b775516b 1616 u8 log_max_pd[0x5];
e1c9c62b 1617 u8 reserved_at_330[0xb];
b775516b
EC		 1618 u8 log_max_xrcd[0x5];
1619
5c298143 1620 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1621 u8 receive_discard_vport_down[0x1];
1622 u8 transmit_discard_vport_down[0x1];
1623 u8 reserved_at_343[0x5];
a351a1b0 1624 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1625 u8 max_flow_counter_15_0[0x10];
a351a1b0 1626
b775516b 1627
e1c9c62b 1628 u8 reserved_at_360[0x3];
b775516b 1629 u8 log_max_rq[0x5];
e1c9c62b 1630 u8 reserved_at_368[0x3];
b775516b 1631 u8 log_max_sq[0x5];
e1c9c62b 1632 u8 reserved_at_370[0x3];
b775516b 1633 u8 log_max_tir[0x5];
e1c9c62b 1634 u8 reserved_at_378[0x3];
b775516b
EC		 1635 u8 log_max_tis[0x5];
1636
e281682b 1637 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1638 u8 reserved_at_381[0x2];
e281682b 1639 u8 log_max_rmp[0x5];
e1c9c62b 1640 u8 reserved_at_388[0x3];
e281682b 1641 u8 log_max_rqt[0x5];
e1c9c62b 1642 u8 reserved_at_390[0x3];
e281682b 1643 u8 log_max_rqt_size[0x5];
e1c9c62b 1644 u8 reserved_at_398[0x3];
b775516b
EC		 1645 u8 log_max_tis_per_sq[0x5];
1646
619a8f2a 1647 u8 ext_stride_num_range[0x1];
fbfa97b4 1648 u8 roce_rw_supported[0x1];
685b1afd 1649 u8 log_max_current_uc_list_wr_supported[0x1];
e281682b 1650 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1651 u8 reserved_at_3a8[0x3];
e281682b 1652 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1653 u8 reserved_at_3b0[0x3];
e281682b 1654 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1655 u8 reserved_at_3b8[0x3];
e281682b
SM		 1656 u8 log_min_stride_sz_sq[0x5];
1657
40817cdb
OG		 1658 u8 hairpin[0x1];
1659 u8 reserved_at_3c1[0x2];
1660 u8 log_max_hairpin_queues[0x5];
1661 u8 reserved_at_3c8[0x3];
1662 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1663 u8 reserved_at_3d0[0x3];
1664 u8 log_max_hairpin_num_packets[0x5];
1665 u8 reserved_at_3d8[0x3];
e281682b
SM		 1666 u8 log_max_wq_sz[0x5];
1667
54f0a411 1668 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1669 u8 disable_local_lb_uc[0x1];
1670 u8 disable_local_lb_mc[0x1];
40817cdb 1671 u8 log_min_hairpin_wq_data_sz[0x5];
349125ba
PP		 1672 u8 reserved_at_3e8[0x2];
1673 u8 vhca_state[0x1];
54f0a411 1674 u8 log_max_vlan_list[0x5];
e1c9c62b 1675 u8 reserved_at_3f0[0x3];
54f0a411 1676 u8 log_max_current_mc_list[0x5];
e1c9c62b 1677 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1678 u8 log_max_current_uc_list[0x5];
1679
38b7ca92
YH		 1680 u8 general_obj_types[0x40];
1681
a6a217dd
AL		 1682 u8 sq_ts_format[0x2];
1683 u8 rq_ts_format[0x2];
d421e466
YK		 1684 u8 steering_format_version[0x4];
1685 u8 create_qp_start_hint[0x18];
342ac844 1686
61c00cca 1687 u8 reserved_at_460[0x3];
6e3722ba 1688 u8 log_max_uctx[0x5];
2b58f6d9
RS		 1689 u8 reserved_at_468[0x2];
1690 u8 ipsec_offload[0x1];
6e3722ba 1691 u8 log_max_umem[0x5];
342ac844 1692 u8 max_num_eqs[0x10];
54f0a411 1693
61c00cca
TT		 1694 u8 reserved_at_480[0x1];
1695 u8 tls_tx[0x1];
ee5cdf7a 1696 u8 tls_rx[0x1];
e281682b 1697 u8 log_max_l2_table[0x5];
e1c9c62b 1698 u8 reserved_at_488[0x8];
b775516b
EC		 1699 u8 log_uar_page_sz[0x10];
1700
e1c9c62b 1701 u8 reserved_at_4a0[0x20];
048ccca8 1702 u8 device_frequency_mhz[0x20];
b0844444 1703 u8 device_frequency_khz[0x20];
e1c9c62b 1704
a6d51b68
EC		 1705 u8 reserved_at_500[0x20];
1706 u8 num_of_uars_per_page[0x20];
e1c9c62b 1707
e818e255 1708 u8 flex_parser_protocols[0x20];
e1c9c62b 1709
b169e64a
YK		 1710 u8 max_geneve_tlv_options[0x8];
1711 u8 reserved_at_568[0x3];
1712 u8 max_geneve_tlv_option_data_len[0x5];
1713 u8 reserved_at_570[0x10];
e1c9c62b 1714
96cd2dd6
LN		 1715 u8 reserved_at_580[0xb];
1716 u8 log_max_dci_stream_channels[0x5];
1717 u8 reserved_at_590[0x3];
1718 u8 log_max_dci_errored_streams[0x5];
1719 u8 reserved_at_598[0x8];
1720
1721 u8 reserved_at_5a0[0x13];
a12ff35e
EBE		 1722 u8 log_max_dek[0x5];
1723 u8 reserved_at_5b8[0x4];
ab741b2e 1724 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1725 u8 cqe_128_always[0x1];
1726 u8 cqe_compression_128[0x1];
7d5e1423 1727 u8 cqe_compression[0x1];
b775516b 1728
7d5e1423
SM		 1729 u8 cqe_compression_timeout[0x10];
1730 u8 cqe_compression_max_num[0x10];
b775516b 1731
704cfecd
YK		 1732 u8 reserved_at_5e0[0x8];
1733 u8 flex_parser_id_gtpu_dw_0[0x4];
1734 u8 reserved_at_5ec[0x4];
7486216b
SM		 1735 u8 tag_matching[0x1];
1736 u8 rndv_offload_rc[0x1];
1737 u8 rndv_offload_dc[0x1];
1738 u8 log_tag_matching_list_sz[0x5];
7b13558f 1739 u8 reserved_at_5f8[0x3];
7486216b
SM		 1740 u8 log_max_xrq[0x5];
1741
32f69e4b
DJ		 1742 u8 affiliate_nic_vport_criteria[0x8];
1743 u8 native_port_num[0x8];
1744 u8 num_vhca_ports[0x8];
704cfecd
YK		 1745 u8 flex_parser_id_gtpu_teid[0x4];
1746 u8 reserved_at_61c[0x2];
32f69e4b 1747 u8 sw_owner_id[0x1];
9d43faac
YH		 1748 u8 reserved_at_61f[0x1];
1749
fd4572b3
ED		 1750 u8 max_num_of_monitor_counters[0x10];
1751 u8 num_ppcnt_monitor_counters[0x10];
1752
349125ba 1753 u8 max_num_sf[0x10];
fd4572b3
ED		 1754 u8 num_q_monitor_counters[0x10];
1755
1759d322
PP		 1756 u8 reserved_at_660[0x20];
1757
1758 u8 sf[0x1];
1759 u8 sf_set_partition[0x1];
1760 u8 reserved_at_682[0x1];
1761 u8 log_max_sf[0x5];
7232c132 1762 u8 apu[0x1];
adfdaff3
YH		 1763 u8 reserved_at_689[0x4];
1764 u8 migration[0x1];
1765 u8 reserved_at_68e[0x2];
1759d322
PP		 1766 u8 log_min_sf_size[0x8];
1767 u8 max_num_sf_partitions[0x8];
9d43faac
YH		 1768
1769 u8 uctx_cap[0x20];
1770
b169e64a
YK		 1771 u8 reserved_at_6c0[0x4];
1772 u8 flex_parser_id_geneve_tlv_option_0[0x4];
97b5484e
AV		 1773 u8 flex_parser_id_icmp_dw1[0x4];
1774 u8 flex_parser_id_icmp_dw0[0x4];
1775 u8 flex_parser_id_icmpv6_dw1[0x4];
1776 u8 flex_parser_id_icmpv6_dw0[0x4];
1777 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1778 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1779
e7e2519e 1780 u8 max_num_match_definer[0x10];
1759d322
PP		 1781 u8 sf_base_id[0x10];
1782
704cfecd
YK		 1783 u8 flex_parser_id_gtpu_dw_2[0x4];
1784 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
0b989c1e
LR		 1785 u8 num_total_dynamic_vf_msix[0x18];
1786 u8 reserved_at_720[0x14];
1787 u8 dynamic_msix_table_size[0xc];
1788 u8 reserved_at_740[0xc];
1789 u8 min_dynamic_vf_msix_table_size[0x4];
1790 u8 reserved_at_750[0x4];
1791 u8 max_dynamic_vf_msix_table_size[0xc];
1792
1793 u8 reserved_at_760[0x20];
1dd7382b 1794 u8 vhca_tunnel_commands[0x40];
e7e2519e 1795 u8 match_definer_format_supported[0x40];
b775516b
EC		 1796};
1797
67133eaa
YK		 1798struct mlx5_ifc_cmd_hca_cap_2_bits {
1799 u8 reserved_at_0[0xa0];
1800
1801 u8 max_reformat_insert_size[0x8];
1802 u8 max_reformat_insert_offset[0x8];
1803 u8 max_reformat_remove_size[0x8];
1804 u8 max_reformat_remove_offset[0x8];
1805
1806 u8 reserved_at_c0[0x740];
1807};
1808
d639af62
MB		 1809enum mlx5_ifc_flow_destination_type {
1810 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1811 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1812 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
1813 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1814 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
e281682b 1815};
b775516b 1816
f6f7d6b5
MG		 1817enum mlx5_flow_table_miss_action {
1818 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1819 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1820 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1821};
1822
e281682b
SM		 1823struct mlx5_ifc_dest_format_struct_bits {
1824 u8 destination_type[0x8];
1825 u8 destination_id[0x18];
1b115498 1826
b17f7fc1 1827 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1828 u8 packet_reformat[0x1];
1829 u8 reserved_at_22[0xe];
b17f7fc1 1830 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1831};
1832
9dc0b289 1833struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1834 u8 flow_counter_id[0x20];
9dc0b289
AV		 1835
1836 u8 reserved_at_20[0x20];
1837};
1838
1b115498
EB		 1839struct mlx5_ifc_extended_dest_format_bits {
1840 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1841
1842 u8 packet_reformat_id[0x20];
1843
1844 u8 reserved_at_60[0x20];
1845};
1846
9dc0b289 1847union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
6dfef396 1848 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
9dc0b289 1849 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
9dc0b289
AV		 1850};
1851
e281682b
SM		 1852struct mlx5_ifc_fte_match_param_bits {
1853 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1854
1855 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1856
1857 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1858
71c6e863
AL		 1859 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1860
b169e64a
YK		 1861 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1862
7da3ad6c
MS		 1863 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1864
0f2a6c3b
MS		 1865 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1866
1867 u8 reserved_at_e00[0x200];
b775516b
EC		 1868};
1869
e281682b
SM		 1870enum {
1871 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1872 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1873 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1874 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1875 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1876};
b775516b 1877
e281682b
SM		 1878struct mlx5_ifc_rx_hash_field_select_bits {
1879 u8 l3_prot_type[0x1];
1880 u8 l4_prot_type[0x1];
1881 u8 selected_fields[0x1e];
1882};
b775516b 1883
e281682b
SM		 1884enum {
1885 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1886 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1887};
1888
e281682b
SM		 1889enum {
1890 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1891 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1892};
1893
1894struct mlx5_ifc_wq_bits {
1895 u8 wq_type[0x4];
1896 u8 wq_signature[0x1];
1897 u8 end_padding_mode[0x2];
1898 u8 cd_slave[0x1];
b4ff3a36 1899 u8 reserved_at_8[0x18];
b775516b 1900
e281682b
SM		 1901 u8 hds_skip_first_sge[0x1];
1902 u8 log2_hds_buf_size[0x3];
b4ff3a36 1903 u8 reserved_at_24[0x7];
e281682b
SM		 1904 u8 page_offset[0x5];
1905 u8 lwm[0x10];
b775516b 1906
b4ff3a36 1907 u8 reserved_at_40[0x8];
e281682b
SM		 1908 u8 pd[0x18];
1909
b4ff3a36 1910 u8 reserved_at_60[0x8];
e281682b
SM		 1911 u8 uar_page[0x18];
1912
1913 u8 dbr_addr[0x40];
1914
1915 u8 hw_counter[0x20];
1916
1917 u8 sw_counter[0x20];
1918
b4ff3a36 1919 u8 reserved_at_100[0xc];
e281682b 1920 u8 log_wq_stride[0x4];
b4ff3a36 1921 u8 reserved_at_110[0x3];
e281682b 1922 u8 log_wq_pg_sz[0x5];
b4ff3a36 1923 u8 reserved_at_118[0x3];
e281682b
SM		 1924 u8 log_wq_sz[0x5];
1925
bd371975
LR		 1926 u8 dbr_umem_valid[0x1];
1927 u8 wq_umem_valid[0x1];
1928 u8 reserved_at_122[0x1];
4d533e0f
OG		 1929 u8 log_hairpin_num_packets[0x5];
1930 u8 reserved_at_128[0x3];
40817cdb 1931 u8 log_hairpin_data_sz[0x5];
40817cdb 1932
619a8f2a
TT		 1933 u8 reserved_at_130[0x4];
1934 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1935 u8 two_byte_shift_en[0x1];
1936 u8 reserved_at_139[0x4];
1937 u8 log_wqe_stride_size[0x3];
1938
7025329d
BBI		 1939 u8 reserved_at_140[0x80];
1940
1941 u8 headers_mkey[0x20];
1942
1943 u8 shampo_enable[0x1];
1944 u8 reserved_at_1e1[0x4];
1945 u8 log_reservation_size[0x3];
1946 u8 reserved_at_1e8[0x5];
1947 u8 log_max_num_of_packets_per_reservation[0x3];
1948 u8 reserved_at_1f0[0x6];
1949 u8 log_headers_entry_size[0x2];
1950 u8 reserved_at_1f8[0x4];
1951 u8 log_headers_buffer_entry_num[0x4];
1952
1953 u8 reserved_at_200[0x400];
b775516b 1954
b6ca09cb 1955 struct mlx5_ifc_cmd_pas_bits pas[];
b775516b
EC		 1956};
1957
e281682b 1958struct mlx5_ifc_rq_num_bits {
b4ff3a36 1959 u8 reserved_at_0[0x8];
e281682b
SM		 1960 u8 rq_num[0x18];
1961};
b775516b 1962
e281682b 1963struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1964 u8 reserved_at_0[0x10];
e281682b 1965 u8 mac_addr_47_32[0x10];
b775516b 1966
e281682b
SM		 1967 u8 mac_addr_31_0[0x20];
1968};
1969
c0046cf7 1970struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1971 u8 reserved_at_0[0x14];
c0046cf7
SM		 1972 u8 vlan[0x0c];
1973
b4ff3a36 1974 u8 reserved_at_20[0x20];
c0046cf7
SM		 1975};
1976
e281682b 1977struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1978 u8 reserved_at_0[0xa0];
e281682b
SM		 1979
1980 u8 min_time_between_cnps[0x20];
1981
b4ff3a36 1982 u8 reserved_at_c0[0x12];
e281682b 1983 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1984 u8 reserved_at_d8[0x4];
1985 u8 cnp_prio_mode[0x1];
e281682b
SM		 1986 u8 cnp_802p_prio[0x3];
1987
b4ff3a36 1988 u8 reserved_at_e0[0x720];
e281682b
SM		 1989};
1990
1991struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1992 u8 reserved_at_0[0x60];
e281682b 1993
b4ff3a36 1994 u8 reserved_at_60[0x4];
e281682b 1995 u8 clamp_tgt_rate[0x1];
b4ff3a36 1996 u8 reserved_at_65[0x3];
e281682b 1997 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1998 u8 reserved_at_69[0x17];
e281682b 1999
b4ff3a36 2000 u8 reserved_at_80[0x20];
e281682b
SM		 2001
2002 u8 rpg_time_reset[0x20];
2003
2004 u8 rpg_byte_reset[0x20];
2005
2006 u8 rpg_threshold[0x20];
2007
2008 u8 rpg_max_rate[0x20];
2009
2010 u8 rpg_ai_rate[0x20];
2011
2012 u8 rpg_hai_rate[0x20];
2013
2014 u8 rpg_gd[0x20];
2015
2016 u8 rpg_min_dec_fac[0x20];
2017
2018 u8 rpg_min_rate[0x20];
2019
b4ff3a36 2020 u8 reserved_at_1c0[0xe0];
e281682b
SM		 2021
2022 u8 rate_to_set_on_first_cnp[0x20];
2023
2024 u8 dce_tcp_g[0x20];
2025
2026 u8 dce_tcp_rtt[0x20];
2027
2028 u8 rate_reduce_monitor_period[0x20];
2029
b4ff3a36 2030 u8 reserved_at_320[0x20];
e281682b
SM		 2031
2032 u8 initial_alpha_value[0x20];
2033
b4ff3a36 2034 u8 reserved_at_360[0x4a0];
e281682b
SM		 2035};
2036
2037struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 2038 u8 reserved_at_0[0x80];
e281682b
SM		 2039
2040 u8 rppp_max_rps[0x20];
2041
2042 u8 rpg_time_reset[0x20];
2043
2044 u8 rpg_byte_reset[0x20];
2045
2046 u8 rpg_threshold[0x20];
2047
2048 u8 rpg_max_rate[0x20];
2049
2050 u8 rpg_ai_rate[0x20];
2051
2052 u8 rpg_hai_rate[0x20];
2053
2054 u8 rpg_gd[0x20];
2055
2056 u8 rpg_min_dec_fac[0x20];
2057
2058 u8 rpg_min_rate[0x20];
2059
b4ff3a36 2060 u8 reserved_at_1c0[0x640];
e281682b
SM		 2061};
2062
2063enum {
2064 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2065 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2066 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2067};
2068
2069struct mlx5_ifc_resize_field_select_bits {
2070 u8 resize_field_select[0x20];
2071};
2072
609b8272
AL		 2073struct mlx5_ifc_resource_dump_bits {
2074 u8 more_dump[0x1];
2075 u8 inline_dump[0x1];
2076 u8 reserved_at_2[0xa];
2077 u8 seq_num[0x4];
2078 u8 segment_type[0x10];
2079
2080 u8 reserved_at_20[0x10];
2081 u8 vhca_id[0x10];
2082
2083 u8 index1[0x20];
2084
2085 u8 index2[0x20];
2086
2087 u8 num_of_obj1[0x10];
2088 u8 num_of_obj2[0x10];
2089
2090 u8 reserved_at_a0[0x20];
2091
2092 u8 device_opaque[0x40];
2093
2094 u8 mkey[0x20];
2095
2096 u8 size[0x20];
2097
2098 u8 address[0x40];
2099
2100 u8 inline_data[52][0x20];
2101};
2102
2103struct mlx5_ifc_resource_dump_menu_record_bits {
2104 u8 reserved_at_0[0x4];
2105 u8 num_of_obj2_supports_active[0x1];
2106 u8 num_of_obj2_supports_all[0x1];
2107 u8 must_have_num_of_obj2[0x1];
2108 u8 support_num_of_obj2[0x1];
2109 u8 num_of_obj1_supports_active[0x1];
2110 u8 num_of_obj1_supports_all[0x1];
2111 u8 must_have_num_of_obj1[0x1];
2112 u8 support_num_of_obj1[0x1];
2113 u8 must_have_index2[0x1];
2114 u8 support_index2[0x1];
2115 u8 must_have_index1[0x1];
2116 u8 support_index1[0x1];
2117 u8 segment_type[0x10];
2118
2119 u8 segment_name[4][0x20];
2120
2121 u8 index1_name[4][0x20];
2122
2123 u8 index2_name[4][0x20];
2124};
2125
2126struct mlx5_ifc_resource_dump_segment_header_bits {
2127 u8 length_dw[0x10];
2128 u8 segment_type[0x10];
2129};
2130
2131struct mlx5_ifc_resource_dump_command_segment_bits {
2132 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2133
2134 u8 segment_called[0x10];
2135 u8 vhca_id[0x10];
2136
2137 u8 index1[0x20];
2138
2139 u8 index2[0x20];
2140
2141 u8 num_of_obj1[0x10];
2142 u8 num_of_obj2[0x10];
2143};
2144
2145struct mlx5_ifc_resource_dump_error_segment_bits {
2146 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2147
2148 u8 reserved_at_20[0x10];
2149 u8 syndrome_id[0x10];
2150
2151 u8 reserved_at_40[0x40];
2152
2153 u8 error[8][0x20];
2154};
2155
2156struct mlx5_ifc_resource_dump_info_segment_bits {
2157 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2158
2159 u8 reserved_at_20[0x18];
2160 u8 dump_version[0x8];
2161
2162 u8 hw_version[0x20];
2163
2164 u8 fw_version[0x20];
2165};
2166
2167struct mlx5_ifc_resource_dump_menu_segment_bits {
2168 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2169
2170 u8 reserved_at_20[0x10];
2171 u8 num_of_records[0x10];
2172
b6ca09cb 2173 struct mlx5_ifc_resource_dump_menu_record_bits record[];
609b8272
AL		 2174};
2175
2176struct mlx5_ifc_resource_dump_resource_segment_bits {
2177 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2178
2179 u8 reserved_at_20[0x20];
2180
2181 u8 index1[0x20];
2182
2183 u8 index2[0x20];
2184
b6ca09cb 2185 u8 payload[][0x20];
609b8272
AL		 2186};
2187
2188struct mlx5_ifc_resource_dump_terminate_segment_bits {
2189 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2190};
2191
2192struct mlx5_ifc_menu_resource_dump_response_bits {
2193 struct mlx5_ifc_resource_dump_info_segment_bits info;
2194 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2195 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2196 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2197};
2198
e281682b
SM		 2199enum {
2200 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2201 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2202 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2203 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2204};
2205
2206struct mlx5_ifc_modify_field_select_bits {
2207 u8 modify_field_select[0x20];
2208};
2209
2210struct mlx5_ifc_field_select_r_roce_np_bits {
2211 u8 field_select_r_roce_np[0x20];
2212};
2213
2214struct mlx5_ifc_field_select_r_roce_rp_bits {
2215 u8 field_select_r_roce_rp[0x20];
2216};
2217
2218enum {
2219 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2220 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2221 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2222 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2223 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2224 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2225 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2226 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2227 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2228 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2229};
2230
2231struct mlx5_ifc_field_select_802_1qau_rp_bits {
2232 u8 field_select_8021qaurp[0x20];
2233};
2234
2235struct mlx5_ifc_phys_layer_cntrs_bits {
2236 u8 time_since_last_clear_high[0x20];
2237
2238 u8 time_since_last_clear_low[0x20];
2239
2240 u8 symbol_errors_high[0x20];
2241
2242 u8 symbol_errors_low[0x20];
2243
2244 u8 sync_headers_errors_high[0x20];
2245
2246 u8 sync_headers_errors_low[0x20];
2247
2248 u8 edpl_bip_errors_lane0_high[0x20];
2249
2250 u8 edpl_bip_errors_lane0_low[0x20];
2251
2252 u8 edpl_bip_errors_lane1_high[0x20];
2253
2254 u8 edpl_bip_errors_lane1_low[0x20];
2255
2256 u8 edpl_bip_errors_lane2_high[0x20];
2257
2258 u8 edpl_bip_errors_lane2_low[0x20];
2259
2260 u8 edpl_bip_errors_lane3_high[0x20];
2261
2262 u8 edpl_bip_errors_lane3_low[0x20];
2263
2264 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2265
2266 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2267
2268 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2269
2270 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2271
2272 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2273
2274 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2275
2276 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2277
2278 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2279
2280 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2281
2282 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2283
2284 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2285
2286 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2287
2288 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2289
2290 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2291
2292 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2293
2294 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2295
2296 u8 rs_fec_corrected_blocks_high[0x20];
2297
2298 u8 rs_fec_corrected_blocks_low[0x20];
2299
2300 u8 rs_fec_uncorrectable_blocks_high[0x20];
2301
2302 u8 rs_fec_uncorrectable_blocks_low[0x20];
2303
2304 u8 rs_fec_no_errors_blocks_high[0x20];
2305
2306 u8 rs_fec_no_errors_blocks_low[0x20];
2307
2308 u8 rs_fec_single_error_blocks_high[0x20];
2309
2310 u8 rs_fec_single_error_blocks_low[0x20];
2311
2312 u8 rs_fec_corrected_symbols_total_high[0x20];
2313
2314 u8 rs_fec_corrected_symbols_total_low[0x20];
2315
2316 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2317
2318 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2319
2320 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2321
2322 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2323
2324 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2325
2326 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2327
2328 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2329
2330 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2331
2332 u8 link_down_events[0x20];
2333
2334 u8 successful_recovery_events[0x20];
2335
b4ff3a36 2336 u8 reserved_at_640[0x180];
e281682b
SM		 2337};
2338
d8dc0508
GP		 2339struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2340 u8 time_since_last_clear_high[0x20];
2341
2342 u8 time_since_last_clear_low[0x20];
2343
2344 u8 phy_received_bits_high[0x20];
2345
2346 u8 phy_received_bits_low[0x20];
2347
2348 u8 phy_symbol_errors_high[0x20];
2349
2350 u8 phy_symbol_errors_low[0x20];
2351
2352 u8 phy_corrected_bits_high[0x20];
2353
2354 u8 phy_corrected_bits_low[0x20];
2355
2356 u8 phy_corrected_bits_lane0_high[0x20];
2357
2358 u8 phy_corrected_bits_lane0_low[0x20];
2359
2360 u8 phy_corrected_bits_lane1_high[0x20];
2361
2362 u8 phy_corrected_bits_lane1_low[0x20];
2363
2364 u8 phy_corrected_bits_lane2_high[0x20];
2365
2366 u8 phy_corrected_bits_lane2_low[0x20];
2367
2368 u8 phy_corrected_bits_lane3_high[0x20];
2369
2370 u8 phy_corrected_bits_lane3_low[0x20];
2371
2372 u8 reserved_at_200[0x5c0];
2373};
2374
1c64bf6f
MY		 2375struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2376 u8 symbol_error_counter[0x10];
2377
2378 u8 link_error_recovery_counter[0x8];
2379
2380 u8 link_downed_counter[0x8];
2381
2382 u8 port_rcv_errors[0x10];
2383
2384 u8 port_rcv_remote_physical_errors[0x10];
2385
2386 u8 port_rcv_switch_relay_errors[0x10];
2387
2388 u8 port_xmit_discards[0x10];
2389
2390 u8 port_xmit_constraint_errors[0x8];
2391
2392 u8 port_rcv_constraint_errors[0x8];
2393
2394 u8 reserved_at_70[0x8];
2395
2396 u8 link_overrun_errors[0x8];
2397
2398 u8 reserved_at_80[0x10];
2399
2400 u8 vl_15_dropped[0x10];
2401
133bea04
TW		 2402 u8 reserved_at_a0[0x80];
2403
2404 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 2405};
2406
948d3f90 2407struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
e281682b
SM		 2408 u8 transmit_queue_high[0x20];
2409
2410 u8 transmit_queue_low[0x20];
2411
948d3f90
AL		 2412 u8 no_buffer_discard_uc_high[0x20];
2413
2414 u8 no_buffer_discard_uc_low[0x20];
2415
2416 u8 reserved_at_80[0x740];
2417};
2418
2419struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2420 u8 wred_discard_high[0x20];
2421
2422 u8 wred_discard_low[0x20];
2423
2424 u8 ecn_marked_tc_high[0x20];
2425
2426 u8 ecn_marked_tc_low[0x20];
2427
2428 u8 reserved_at_80[0x740];
e281682b
SM		 2429};
2430
2431struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2432 u8 rx_octets_high[0x20];
2433
2434 u8 rx_octets_low[0x20];
2435
b4ff3a36 2436 u8 reserved_at_40[0xc0];
e281682b
SM		 2437
2438 u8 rx_frames_high[0x20];
2439
2440 u8 rx_frames_low[0x20];
2441
2442 u8 tx_octets_high[0x20];
2443
2444 u8 tx_octets_low[0x20];
2445
b4ff3a36 2446 u8 reserved_at_180[0xc0];
e281682b
SM		 2447
2448 u8 tx_frames_high[0x20];
2449
2450 u8 tx_frames_low[0x20];
2451
2452 u8 rx_pause_high[0x20];
2453
2454 u8 rx_pause_low[0x20];
2455
2456 u8 rx_pause_duration_high[0x20];
2457
2458 u8 rx_pause_duration_low[0x20];
2459
2460 u8 tx_pause_high[0x20];
2461
2462 u8 tx_pause_low[0x20];
2463
2464 u8 tx_pause_duration_high[0x20];
2465
2466 u8 tx_pause_duration_low[0x20];
2467
2468 u8 rx_pause_transition_high[0x20];
2469
2470 u8 rx_pause_transition_low[0x20];
2471
827a8cb2
AL		 2472 u8 rx_discards_high[0x20];
2473
2474 u8 rx_discards_low[0x20];
2fcb12df
IK		 2475
2476 u8 device_stall_minor_watermark_cnt_high[0x20];
2477
2478 u8 device_stall_minor_watermark_cnt_low[0x20];
2479
2480 u8 device_stall_critical_watermark_cnt_high[0x20];
2481
2482 u8 device_stall_critical_watermark_cnt_low[0x20];
2483
2484 u8 reserved_at_480[0x340];
e281682b
SM		 2485};
2486
2487struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2488 u8 port_transmit_wait_high[0x20];
2489
2490 u8 port_transmit_wait_low[0x20];
2491
2dba0797
GP		 2492 u8 reserved_at_40[0x100];
2493
2494 u8 rx_buffer_almost_full_high[0x20];
2495
2496 u8 rx_buffer_almost_full_low[0x20];
2497
2498 u8 rx_buffer_full_high[0x20];
2499
2500 u8 rx_buffer_full_low[0x20];
2501
0af5107c
TB		 2502 u8 rx_icrc_encapsulated_high[0x20];
2503
2504 u8 rx_icrc_encapsulated_low[0x20];
2505
2506 u8 reserved_at_200[0x5c0];
e281682b
SM		 2507};
2508
2509struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2510 u8 dot3stats_alignment_errors_high[0x20];
2511
2512 u8 dot3stats_alignment_errors_low[0x20];
2513
2514 u8 dot3stats_fcs_errors_high[0x20];
2515
2516 u8 dot3stats_fcs_errors_low[0x20];
2517
2518 u8 dot3stats_single_collision_frames_high[0x20];
2519
2520 u8 dot3stats_single_collision_frames_low[0x20];
2521
2522 u8 dot3stats_multiple_collision_frames_high[0x20];
2523
2524 u8 dot3stats_multiple_collision_frames_low[0x20];
2525
2526 u8 dot3stats_sqe_test_errors_high[0x20];
2527
2528 u8 dot3stats_sqe_test_errors_low[0x20];
2529
2530 u8 dot3stats_deferred_transmissions_high[0x20];
2531
2532 u8 dot3stats_deferred_transmissions_low[0x20];
2533
2534 u8 dot3stats_late_collisions_high[0x20];
2535
2536 u8 dot3stats_late_collisions_low[0x20];
2537
2538 u8 dot3stats_excessive_collisions_high[0x20];
2539
2540 u8 dot3stats_excessive_collisions_low[0x20];
2541
2542 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2543
2544 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2545
2546 u8 dot3stats_carrier_sense_errors_high[0x20];
2547
2548 u8 dot3stats_carrier_sense_errors_low[0x20];
2549
2550 u8 dot3stats_frame_too_longs_high[0x20];
2551
2552 u8 dot3stats_frame_too_longs_low[0x20];
2553
2554 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2555
2556 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2557
2558 u8 dot3stats_symbol_errors_high[0x20];
2559
2560 u8 dot3stats_symbol_errors_low[0x20];
2561
2562 u8 dot3control_in_unknown_opcodes_high[0x20];
2563
2564 u8 dot3control_in_unknown_opcodes_low[0x20];
2565
2566 u8 dot3in_pause_frames_high[0x20];
2567
2568 u8 dot3in_pause_frames_low[0x20];
2569
2570 u8 dot3out_pause_frames_high[0x20];
2571
2572 u8 dot3out_pause_frames_low[0x20];
2573
b4ff3a36 2574 u8 reserved_at_400[0x3c0];
e281682b
SM		 2575};
2576
2577struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2578 u8 ether_stats_drop_events_high[0x20];
2579
2580 u8 ether_stats_drop_events_low[0x20];
2581
2582 u8 ether_stats_octets_high[0x20];
2583
2584 u8 ether_stats_octets_low[0x20];
2585
2586 u8 ether_stats_pkts_high[0x20];
2587
2588 u8 ether_stats_pkts_low[0x20];
2589
2590 u8 ether_stats_broadcast_pkts_high[0x20];
2591
2592 u8 ether_stats_broadcast_pkts_low[0x20];
2593
2594 u8 ether_stats_multicast_pkts_high[0x20];
2595
2596 u8 ether_stats_multicast_pkts_low[0x20];
2597
2598 u8 ether_stats_crc_align_errors_high[0x20];
2599
2600 u8 ether_stats_crc_align_errors_low[0x20];
2601
2602 u8 ether_stats_undersize_pkts_high[0x20];
2603
2604 u8 ether_stats_undersize_pkts_low[0x20];
2605
2606 u8 ether_stats_oversize_pkts_high[0x20];
2607
2608 u8 ether_stats_oversize_pkts_low[0x20];
2609
2610 u8 ether_stats_fragments_high[0x20];
2611
2612 u8 ether_stats_fragments_low[0x20];
2613
2614 u8 ether_stats_jabbers_high[0x20];
2615
2616 u8 ether_stats_jabbers_low[0x20];
2617
2618 u8 ether_stats_collisions_high[0x20];
2619
2620 u8 ether_stats_collisions_low[0x20];
2621
2622 u8 ether_stats_pkts64octets_high[0x20];
2623
2624 u8 ether_stats_pkts64octets_low[0x20];
2625
2626 u8 ether_stats_pkts65to127octets_high[0x20];
2627
2628 u8 ether_stats_pkts65to127octets_low[0x20];
2629
2630 u8 ether_stats_pkts128to255octets_high[0x20];
2631
2632 u8 ether_stats_pkts128to255octets_low[0x20];
2633
2634 u8 ether_stats_pkts256to511octets_high[0x20];
2635
2636 u8 ether_stats_pkts256to511octets_low[0x20];
2637
2638 u8 ether_stats_pkts512to1023octets_high[0x20];
2639
2640 u8 ether_stats_pkts512to1023octets_low[0x20];
2641
2642 u8 ether_stats_pkts1024to1518octets_high[0x20];
2643
2644 u8 ether_stats_pkts1024to1518octets_low[0x20];
2645
2646 u8 ether_stats_pkts1519to2047octets_high[0x20];
2647
2648 u8 ether_stats_pkts1519to2047octets_low[0x20];
2649
2650 u8 ether_stats_pkts2048to4095octets_high[0x20];
2651
2652 u8 ether_stats_pkts2048to4095octets_low[0x20];
2653
2654 u8 ether_stats_pkts4096to8191octets_high[0x20];
2655
2656 u8 ether_stats_pkts4096to8191octets_low[0x20];
2657
2658 u8 ether_stats_pkts8192to10239octets_high[0x20];
2659
2660 u8 ether_stats_pkts8192to10239octets_low[0x20];
2661
b4ff3a36 2662 u8 reserved_at_540[0x280];
e281682b
SM		 2663};
2664
2665struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2666 u8 if_in_octets_high[0x20];
2667
2668 u8 if_in_octets_low[0x20];
2669
2670 u8 if_in_ucast_pkts_high[0x20];
2671
2672 u8 if_in_ucast_pkts_low[0x20];
2673
2674 u8 if_in_discards_high[0x20];
2675
2676 u8 if_in_discards_low[0x20];
2677
2678 u8 if_in_errors_high[0x20];
2679
2680 u8 if_in_errors_low[0x20];
2681
2682 u8 if_in_unknown_protos_high[0x20];
2683
2684 u8 if_in_unknown_protos_low[0x20];
2685
2686 u8 if_out_octets_high[0x20];
2687
2688 u8 if_out_octets_low[0x20];
2689
2690 u8 if_out_ucast_pkts_high[0x20];
2691
2692 u8 if_out_ucast_pkts_low[0x20];
2693
2694 u8 if_out_discards_high[0x20];
2695
2696 u8 if_out_discards_low[0x20];
2697
2698 u8 if_out_errors_high[0x20];
2699
2700 u8 if_out_errors_low[0x20];
2701
2702 u8 if_in_multicast_pkts_high[0x20];
2703
2704 u8 if_in_multicast_pkts_low[0x20];
2705
2706 u8 if_in_broadcast_pkts_high[0x20];
2707
2708 u8 if_in_broadcast_pkts_low[0x20];
2709
2710 u8 if_out_multicast_pkts_high[0x20];
2711
2712 u8 if_out_multicast_pkts_low[0x20];
2713
2714 u8 if_out_broadcast_pkts_high[0x20];
2715
2716 u8 if_out_broadcast_pkts_low[0x20];
2717
b4ff3a36 2718 u8 reserved_at_340[0x480];
e281682b
SM		 2719};
2720
2721struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2722 u8 a_frames_transmitted_ok_high[0x20];
2723
2724 u8 a_frames_transmitted_ok_low[0x20];
2725
2726 u8 a_frames_received_ok_high[0x20];
2727
2728 u8 a_frames_received_ok_low[0x20];
2729
2730 u8 a_frame_check_sequence_errors_high[0x20];
2731
2732 u8 a_frame_check_sequence_errors_low[0x20];
2733
2734 u8 a_alignment_errors_high[0x20];
2735
2736 u8 a_alignment_errors_low[0x20];
2737
2738 u8 a_octets_transmitted_ok_high[0x20];
2739
2740 u8 a_octets_transmitted_ok_low[0x20];
2741
2742 u8 a_octets_received_ok_high[0x20];
2743
2744 u8 a_octets_received_ok_low[0x20];
2745
2746 u8 a_multicast_frames_xmitted_ok_high[0x20];
2747
2748 u8 a_multicast_frames_xmitted_ok_low[0x20];
2749
2750 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2751
2752 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2753
2754 u8 a_multicast_frames_received_ok_high[0x20];
2755
2756 u8 a_multicast_frames_received_ok_low[0x20];
2757
2758 u8 a_broadcast_frames_received_ok_high[0x20];
2759
2760 u8 a_broadcast_frames_received_ok_low[0x20];
2761
2762 u8 a_in_range_length_errors_high[0x20];
2763
2764 u8 a_in_range_length_errors_low[0x20];
2765
2766 u8 a_out_of_range_length_field_high[0x20];
2767
2768 u8 a_out_of_range_length_field_low[0x20];
2769
2770 u8 a_frame_too_long_errors_high[0x20];
2771
2772 u8 a_frame_too_long_errors_low[0x20];
2773
2774 u8 a_symbol_error_during_carrier_high[0x20];
2775
2776 u8 a_symbol_error_during_carrier_low[0x20];
2777
2778 u8 a_mac_control_frames_transmitted_high[0x20];
2779
2780 u8 a_mac_control_frames_transmitted_low[0x20];
2781
2782 u8 a_mac_control_frames_received_high[0x20];
2783
2784 u8 a_mac_control_frames_received_low[0x20];
2785
2786 u8 a_unsupported_opcodes_received_high[0x20];
2787
2788 u8 a_unsupported_opcodes_received_low[0x20];
2789
2790 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2791
2792 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2793
2794 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2795
2796 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2797
b4ff3a36 2798 u8 reserved_at_4c0[0x300];
e281682b
SM		 2799};
2800
8ed1a630
GP		 2801struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2802 u8 life_time_counter_high[0x20];
2803
2804 u8 life_time_counter_low[0x20];
2805
2806 u8 rx_errors[0x20];
2807
2808 u8 tx_errors[0x20];
2809
2810 u8 l0_to_recovery_eieos[0x20];
2811
2812 u8 l0_to_recovery_ts[0x20];
2813
2814 u8 l0_to_recovery_framing[0x20];
2815
2816 u8 l0_to_recovery_retrain[0x20];
2817
2818 u8 crc_error_dllp[0x20];
2819
2820 u8 crc_error_tlp[0x20];
2821
efae7f78
EBE		 2822 u8 tx_overflow_buffer_pkt_high[0x20];
2823
2824 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2825
2826 u8 outbound_stalled_reads[0x20];
2827
2828 u8 outbound_stalled_writes[0x20];
2829
2830 u8 outbound_stalled_reads_events[0x20];
2831
2832 u8 outbound_stalled_writes_events[0x20];
2833
2834 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2835};
2836
e281682b
SM		 2837struct mlx5_ifc_cmd_inter_comp_event_bits {
2838 u8 command_completion_vector[0x20];
2839
b4ff3a36 2840 u8 reserved_at_20[0xc0];
e281682b
SM		 2841};
2842
2843struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2844 u8 reserved_at_0[0x18];
e281682b 2845 u8 port_num[0x1];
b4ff3a36 2846 u8 reserved_at_19[0x3];
e281682b
SM		 2847 u8 vl[0x4];
2848
b4ff3a36 2849 u8 reserved_at_20[0xa0];
e281682b
SM		 2850};
2851
2852struct mlx5_ifc_db_bf_congestion_event_bits {
2853 u8 event_subtype[0x8];
b4ff3a36 2854 u8 reserved_at_8[0x8];
e281682b 2855 u8 congestion_level[0x8];
b4ff3a36 2856 u8 reserved_at_18[0x8];
e281682b 2857
b4ff3a36 2858 u8 reserved_at_20[0xa0];
e281682b
SM		 2859};
2860
2861struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2862 u8 reserved_at_0[0x60];
e281682b
SM		 2863
2864 u8 gpio_event_hi[0x20];
2865
2866 u8 gpio_event_lo[0x20];
2867
b4ff3a36 2868 u8 reserved_at_a0[0x40];
e281682b
SM		 2869};
2870
2871struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2872 u8 reserved_at_0[0x40];
e281682b
SM		 2873
2874 u8 port_num[0x4];
b4ff3a36 2875 u8 reserved_at_44[0x1c];
e281682b 2876
b4ff3a36 2877 u8 reserved_at_60[0x80];
e281682b
SM		 2878};
2879
2880struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2881 u8 reserved_at_0[0xe0];
e281682b
SM		 2882};
2883
4b2c5fa9
AT		 2884struct mlx5_ifc_default_timeout_bits {
2885 u8 to_multiplier[0x3];
2886 u8 reserved_at_3[0x9];
2887 u8 to_value[0x14];
2888};
2889
2890struct mlx5_ifc_dtor_reg_bits {
2891 u8 reserved_at_0[0x20];
2892
2893 struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2894
2895 u8 reserved_at_40[0x60];
2896
2897 struct mlx5_ifc_default_timeout_bits health_poll_to;
2898
2899 struct mlx5_ifc_default_timeout_bits full_crdump_to;
2900
2901 struct mlx5_ifc_default_timeout_bits fw_reset_to;
2902
2903 struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2904
2905 struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2906
2907 struct mlx5_ifc_default_timeout_bits tear_down_to;
2908
2909 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2910
2911 struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2912
2913 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
2914
2915 u8 reserved_at_1c0[0x40];
2916};
2917
e281682b
SM		 2918enum {
2919 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2920 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2921};
2922
2923struct mlx5_ifc_cq_error_bits {
b4ff3a36 2924 u8 reserved_at_0[0x8];
e281682b
SM		 2925 u8 cqn[0x18];
2926
b4ff3a36 2927 u8 reserved_at_20[0x20];
e281682b 2928
b4ff3a36 2929 u8 reserved_at_40[0x18];
e281682b
SM		 2930 u8 syndrome[0x8];
2931
b4ff3a36 2932 u8 reserved_at_60[0x80];
e281682b
SM		 2933};
2934
2935struct mlx5_ifc_rdma_page_fault_event_bits {
2936 u8 bytes_committed[0x20];
2937
2938 u8 r_key[0x20];
2939
b4ff3a36 2940 u8 reserved_at_40[0x10];
e281682b
SM		 2941 u8 packet_len[0x10];
2942
2943 u8 rdma_op_len[0x20];
2944
2945 u8 rdma_va[0x40];
2946
b4ff3a36 2947 u8 reserved_at_c0[0x5];
e281682b
SM		 2948 u8 rdma[0x1];
2949 u8 write[0x1];
2950 u8 requestor[0x1];
2951 u8 qp_number[0x18];
2952};
2953
2954struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2955 u8 bytes_committed[0x20];
2956
b4ff3a36 2957 u8 reserved_at_20[0x10];
e281682b
SM		 2958 u8 wqe_index[0x10];
2959
b4ff3a36 2960 u8 reserved_at_40[0x10];
e281682b
SM		 2961 u8 len[0x10];
2962
b4ff3a36 2963 u8 reserved_at_60[0x60];
e281682b 2964
b4ff3a36 2965 u8 reserved_at_c0[0x5];
e281682b
SM		 2966 u8 rdma[0x1];
2967 u8 write_read[0x1];
2968 u8 requestor[0x1];
2969 u8 qpn[0x18];
2970};
2971
2972struct mlx5_ifc_qp_events_bits {
b4ff3a36 2973 u8 reserved_at_0[0xa0];
e281682b
SM		 2974
2975 u8 type[0x8];
b4ff3a36 2976 u8 reserved_at_a8[0x18];
e281682b 2977
b4ff3a36 2978 u8 reserved_at_c0[0x8];
e281682b
SM		 2979 u8 qpn_rqn_sqn[0x18];
2980};
2981
2982struct mlx5_ifc_dct_events_bits {
b4ff3a36 2983 u8 reserved_at_0[0xc0];
e281682b 2984
b4ff3a36 2985 u8 reserved_at_c0[0x8];
e281682b
SM		 2986 u8 dct_number[0x18];
2987};
2988
2989struct mlx5_ifc_comp_event_bits {
b4ff3a36 2990 u8 reserved_at_0[0xc0];
e281682b 2991
b4ff3a36 2992 u8 reserved_at_c0[0x8];
e281682b
SM		 2993 u8 cq_number[0x18];
2994};
2995
2996enum {
2997 MLX5_QPC_STATE_RST = 0x0,
2998 MLX5_QPC_STATE_INIT = 0x1,
2999 MLX5_QPC_STATE_RTR = 0x2,
3000 MLX5_QPC_STATE_RTS = 0x3,
3001 MLX5_QPC_STATE_SQER = 0x4,
3002 MLX5_QPC_STATE_ERR = 0x6,
3003 MLX5_QPC_STATE_SQD = 0x7,
3004 MLX5_QPC_STATE_SUSPENDED = 0x9,
3005};
3006
3007enum {
3008 MLX5_QPC_ST_RC = 0x0,
3009 MLX5_QPC_ST_UC = 0x1,
3010 MLX5_QPC_ST_UD = 0x2,
3011 MLX5_QPC_ST_XRC = 0x3,
3012 MLX5_QPC_ST_DCI = 0x5,
3013 MLX5_QPC_ST_QP0 = 0x7,
3014 MLX5_QPC_ST_QP1 = 0x8,
3015 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3016 MLX5_QPC_ST_REG_UMR = 0xc,
3017};
3018
3019enum {
3020 MLX5_QPC_PM_STATE_ARMED = 0x0,
3021 MLX5_QPC_PM_STATE_REARM = 0x1,
3022 MLX5_QPC_PM_STATE_RESERVED = 0x2,
3023 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3024};
3025
6e44636a
AK		 3026enum {
3027 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3028};
3029
e281682b
SM		 3030enum {
3031 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3032 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3033};
3034
3035enum {
3036 MLX5_QPC_MTU_256_BYTES = 0x1,
3037 MLX5_QPC_MTU_512_BYTES = 0x2,
3038 MLX5_QPC_MTU_1K_BYTES = 0x3,
3039 MLX5_QPC_MTU_2K_BYTES = 0x4,
3040 MLX5_QPC_MTU_4K_BYTES = 0x5,
3041 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3042};
3043
3044enum {
3045 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3046 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3047 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3048 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3049 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3050 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3051 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3052 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3053};
3054
3055enum {
3056 MLX5_QPC_CS_REQ_DISABLE = 0x0,
3057 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3058 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3059};
3060
3061enum {
3062 MLX5_QPC_CS_RES_DISABLE = 0x0,
3063 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3064 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3065};
3066
a6a217dd 3067enum {
9a1ac95a
AL		 3068 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3069 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3070 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
a6a217dd
AL		 3071};
3072
e281682b
SM		 3073struct mlx5_ifc_qpc_bits {
3074 u8 state[0x4];
84df61eb 3075 u8 lag_tx_port_affinity[0x4];
e281682b 3076 u8 st[0x8];
7304d603
YK		 3077 u8 reserved_at_10[0x2];
3078 u8 isolate_vl_tc[0x1];
e281682b 3079 u8 pm_state[0x2];
3fd3c80a
DG		 3080 u8 reserved_at_15[0x1];
3081 u8 req_e2e_credit_mode[0x2];
6e44636a 3082 u8 offload_type[0x4];
e281682b 3083 u8 end_padding_mode[0x2];
b4ff3a36 3084 u8 reserved_at_1e[0x2];
e281682b
SM		 3085
3086 u8 wq_signature[0x1];
3087 u8 block_lb_mc[0x1];
3088 u8 atomic_like_write_en[0x1];
3089 u8 latency_sensitive[0x1];
b4ff3a36 3090 u8 reserved_at_24[0x1];
e281682b 3091 u8 drain_sigerr[0x1];
b4ff3a36 3092 u8 reserved_at_26[0x2];
e281682b
SM		 3093 u8 pd[0x18];
3094
3095 u8 mtu[0x3];
3096 u8 log_msg_max[0x5];
b4ff3a36 3097 u8 reserved_at_48[0x1];
e281682b
SM		 3098 u8 log_rq_size[0x4];
3099 u8 log_rq_stride[0x3];
3100 u8 no_sq[0x1];
3101 u8 log_sq_size[0x4];
a6a217dd
AL		 3102 u8 reserved_at_55[0x3];
3103 u8 ts_format[0x2];
3104 u8 reserved_at_5a[0x1];
e281682b 3105 u8 rlky[0x1];
1015c2e8 3106 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 3107
3108 u8 counter_set_id[0x8];
3109 u8 uar_page[0x18];
3110
b4ff3a36 3111 u8 reserved_at_80[0x8];
e281682b
SM		 3112 u8 user_index[0x18];
3113
b4ff3a36 3114 u8 reserved_at_a0[0x3];
e281682b
SM		 3115 u8 log_page_size[0x5];
3116 u8 remote_qpn[0x18];
3117
3118 struct mlx5_ifc_ads_bits primary_address_path;
3119
3120 struct mlx5_ifc_ads_bits secondary_address_path;
3121
3122 u8 log_ack_req_freq[0x4];
b4ff3a36 3123 u8 reserved_at_384[0x4];
e281682b 3124 u8 log_sra_max[0x3];
b4ff3a36 3125 u8 reserved_at_38b[0x2];
e281682b
SM		 3126 u8 retry_count[0x3];
3127 u8 rnr_retry[0x3];
b4ff3a36 3128 u8 reserved_at_393[0x1];
e281682b
SM		 3129 u8 fre[0x1];
3130 u8 cur_rnr_retry[0x3];
3131 u8 cur_retry_count[0x3];
b4ff3a36 3132 u8 reserved_at_39b[0x5];
e281682b 3133
b4ff3a36 3134 u8 reserved_at_3a0[0x20];
e281682b 3135
b4ff3a36 3136 u8 reserved_at_3c0[0x8];
e281682b
SM		 3137 u8 next_send_psn[0x18];
3138
96cd2dd6
LN		 3139 u8 reserved_at_3e0[0x3];
3140 u8 log_num_dci_stream_channels[0x5];
e281682b
SM		 3141 u8 cqn_snd[0x18];
3142
96cd2dd6
LN		 3143 u8 reserved_at_400[0x3];
3144 u8 log_num_dci_errored_streams[0x5];
09a7d9ec
SM		 3145 u8 deth_sqpn[0x18];
3146
3147 u8 reserved_at_420[0x20];
e281682b 3148
b4ff3a36 3149 u8 reserved_at_440[0x8];
e281682b
SM		 3150 u8 last_acked_psn[0x18];
3151
b4ff3a36 3152 u8 reserved_at_460[0x8];
e281682b
SM		 3153 u8 ssn[0x18];
3154
b4ff3a36 3155 u8 reserved_at_480[0x8];
e281682b 3156 u8 log_rra_max[0x3];
b4ff3a36 3157 u8 reserved_at_48b[0x1];
e281682b
SM		 3158 u8 atomic_mode[0x4];
3159 u8 rre[0x1];
3160 u8 rwe[0x1];
3161 u8 rae[0x1];
b4ff3a36 3162 u8 reserved_at_493[0x1];
e281682b 3163 u8 page_offset[0x6];
b4ff3a36 3164 u8 reserved_at_49a[0x3];
e281682b
SM		 3165 u8 cd_slave_receive[0x1];
3166 u8 cd_slave_send[0x1];
3167 u8 cd_master[0x1];
3168
b4ff3a36 3169 u8 reserved_at_4a0[0x3];
e281682b
SM		 3170 u8 min_rnr_nak[0x5];
3171 u8 next_rcv_psn[0x18];
3172
b4ff3a36 3173 u8 reserved_at_4c0[0x8];
e281682b
SM		 3174 u8 xrcd[0x18];
3175
b4ff3a36 3176 u8 reserved_at_4e0[0x8];
e281682b
SM		 3177 u8 cqn_rcv[0x18];
3178
3179 u8 dbr_addr[0x40];
3180
3181 u8 q_key[0x20];
3182
b4ff3a36 3183 u8 reserved_at_560[0x5];
e281682b 3184 u8 rq_type[0x3];
7486216b 3185 u8 srqn_rmpn_xrqn[0x18];
e281682b 3186
b4ff3a36 3187 u8 reserved_at_580[0x8];
e281682b
SM		 3188 u8 rmsn[0x18];
3189
3190 u8 hw_sq_wqebb_counter[0x10];
3191 u8 sw_sq_wqebb_counter[0x10];
3192
3193 u8 hw_rq_counter[0x20];
3194
3195 u8 sw_rq_counter[0x20];
3196
b4ff3a36 3197 u8 reserved_at_600[0x20];
e281682b 3198
b4ff3a36 3199 u8 reserved_at_620[0xf];
e281682b
SM		 3200 u8 cgs[0x1];
3201 u8 cs_req[0x8];
3202 u8 cs_res[0x8];
3203
3204 u8 dc_access_key[0x40];
3205
bd371975
LR		 3206 u8 reserved_at_680[0x3];
3207 u8 dbr_umem_valid[0x1];
3208
3209 u8 reserved_at_684[0xbc];
e281682b
SM		 3210};
3211
3212struct mlx5_ifc_roce_addr_layout_bits {
3213 u8 source_l3_address[16][0x8];
3214
b4ff3a36 3215 u8 reserved_at_80[0x3];
e281682b
SM		 3216 u8 vlan_valid[0x1];
3217 u8 vlan_id[0xc];
3218 u8 source_mac_47_32[0x10];
3219
3220 u8 source_mac_31_0[0x20];
3221
b4ff3a36 3222 u8 reserved_at_c0[0x14];
e281682b
SM		 3223 u8 roce_l3_type[0x4];
3224 u8 roce_version[0x8];
3225
b4ff3a36 3226 u8 reserved_at_e0[0x20];
e281682b
SM		 3227};
3228
7025329d
BBI		 3229struct mlx5_ifc_shampo_cap_bits {
3230 u8 reserved_at_0[0x3];
3231 u8 shampo_log_max_reservation_size[0x5];
3232 u8 reserved_at_8[0x3];
3233 u8 shampo_log_min_reservation_size[0x5];
3234 u8 shampo_min_mss_size[0x10];
3235
3236 u8 reserved_at_20[0x3];
3237 u8 shampo_max_log_headers_entry_size[0x5];
3238 u8 reserved_at_28[0x18];
3239
3240 u8 reserved_at_40[0x7c0];
3241};
3242
e281682b
SM		 3243union mlx5_ifc_hca_cap_union_bits {
3244 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
67133eaa 3245 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
e281682b
SM		 3246 struct mlx5_ifc_odp_cap_bits odp_cap;
3247 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3248 struct mlx5_ifc_roce_cap_bits roce_cap;
3249 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3250 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 3251 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 3252 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
425a563a 3253 struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3f0393a5 3254 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 3255 struct mlx5_ifc_qos_cap_bits qos_cap;
0b9055a1 3256 struct mlx5_ifc_debug_cap_bits debug_cap;
e29341fb 3257 struct mlx5_ifc_fpga_cap_bits fpga_cap;
a12ff35e 3258 struct mlx5_ifc_tls_cap_bits tls_cap;
97b5484e 3259 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
8a06a79b 3260 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
7025329d 3261 struct mlx5_ifc_shampo_cap_bits shampo_cap;
b4ff3a36 3262 u8 reserved_at_0[0x8000];
e281682b
SM		 3263};
3264
3265enum {
3266 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3267 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3268 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 3269 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 3270 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 3271 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 3272 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 3273 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3274 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 3275 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3276 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
78fb6122
HN		 3277 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3278 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
0c06897a
OG		 3279};
3280
65c0f2c1
JL		 3281enum {
3282 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3283 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3284 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3285};
3286
0c06897a
OG		 3287struct mlx5_ifc_vlan_bits {
3288 u8 ethtype[0x10];
3289 u8 prio[0x3];
3290 u8 cfi[0x1];
3291 u8 vid[0xc];
e281682b
SM		 3292};
3293
3294struct mlx5_ifc_flow_context_bits {
0c06897a 3295 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 3296
3297 u8 group_id[0x20];
3298
b4ff3a36 3299 u8 reserved_at_40[0x8];
e281682b
SM		 3300 u8 flow_tag[0x18];
3301
b4ff3a36 3302 u8 reserved_at_60[0x10];
e281682b
SM		 3303 u8 action[0x10];
3304
1b115498 3305 u8 extended_destination[0x1];
65c0f2c1
JL		 3306 u8 reserved_at_81[0x1];
3307 u8 flow_source[0x2];
3308 u8 reserved_at_84[0x4];
e281682b
SM		 3309 u8 destination_list_size[0x18];
3310
9dc0b289
AV		 3311 u8 reserved_at_a0[0x8];
3312 u8 flow_counter_list_size[0x18];
3313
60786f09 3314 u8 packet_reformat_id[0x20];
7adbde20 3315
2a69cb9f
OG		 3316 u8 modify_header_id[0x20];
3317
8da6fe2a
JL		 3318 struct mlx5_ifc_vlan_bits push_vlan_2;
3319
78fb6122
HN		 3320 u8 ipsec_obj_id[0x20];
3321 u8 reserved_at_140[0xc0];
e281682b
SM		 3322
3323 struct mlx5_ifc_fte_match_param_bits match_value;
3324
b4ff3a36 3325 u8 reserved_at_1200[0x600];
e281682b 3326
b6ca09cb 3327 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
e281682b
SM		 3328};
3329
3330enum {
3331 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3332 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3333};
3334
3335struct mlx5_ifc_xrc_srqc_bits {
3336 u8 state[0x4];
3337 u8 log_xrc_srq_size[0x4];
b4ff3a36 3338 u8 reserved_at_8[0x18];
e281682b
SM		 3339
3340 u8 wq_signature[0x1];
3341 u8 cont_srq[0x1];
99b77fef 3342 u8 reserved_at_22[0x1];
e281682b
SM		 3343 u8 rlky[0x1];
3344 u8 basic_cyclic_rcv_wqe[0x1];
3345 u8 log_rq_stride[0x3];
3346 u8 xrcd[0x18];
3347
3348 u8 page_offset[0x6];
99b77fef
YH		 3349 u8 reserved_at_46[0x1];
3350 u8 dbr_umem_valid[0x1];
e281682b
SM		 3351 u8 cqn[0x18];
3352
b4ff3a36 3353 u8 reserved_at_60[0x20];
e281682b
SM		 3354
3355 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 3356 u8 reserved_at_81[0x1];
e281682b
SM		 3357 u8 log_page_size[0x6];
3358 u8 user_index[0x18];
3359
b4ff3a36 3360 u8 reserved_at_a0[0x20];
e281682b 3361
b4ff3a36 3362 u8 reserved_at_c0[0x8];
e281682b
SM		 3363 u8 pd[0x18];
3364
3365 u8 lwm[0x10];
3366 u8 wqe_cnt[0x10];
3367
b4ff3a36 3368 u8 reserved_at_100[0x40];
e281682b
SM		 3369
3370 u8 db_record_addr_h[0x20];
3371
3372 u8 db_record_addr_l[0x1e];
b4ff3a36 3373 u8 reserved_at_17e[0x2];
e281682b 3374
b4ff3a36 3375 u8 reserved_at_180[0x80];
e281682b
SM		 3376};
3377
61c5b5c9
MS		 3378struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3379 u8 counter_error_queues[0x20];
3380
3381 u8 total_error_queues[0x20];
3382
3383 u8 send_queue_priority_update_flow[0x20];
3384
3385 u8 reserved_at_60[0x20];
3386
3387 u8 nic_receive_steering_discard[0x40];
3388
3389 u8 receive_discard_vport_down[0x40];
3390
3391 u8 transmit_discard_vport_down[0x40];
3392
30b10e89
MS		 3393 u8 reserved_at_140[0xa0];
3394
3395 u8 internal_rq_out_of_buffer[0x20];
3396
3397 u8 reserved_at_200[0xe00];
61c5b5c9
MS		 3398};
3399
e281682b
SM		 3400struct mlx5_ifc_traffic_counter_bits {
3401 u8 packets[0x40];
3402
3403 u8 octets[0x40];
3404};
3405
3406struct mlx5_ifc_tisc_bits {
84df61eb 3407 u8 strict_lag_tx_port_affinity[0x1];
a12ff35e 3408 u8 tls_en[0x1];
7761f9ee 3409 u8 reserved_at_2[0x2];
84df61eb
AH		 3410 u8 lag_tx_port_affinity[0x04];
3411
3412 u8 reserved_at_8[0x4];
e281682b 3413 u8 prio[0x4];
b4ff3a36 3414 u8 reserved_at_10[0x10];
e281682b 3415
b4ff3a36 3416 u8 reserved_at_20[0x100];
e281682b 3417
b4ff3a36 3418 u8 reserved_at_120[0x8];
e281682b
SM		 3419 u8 transport_domain[0x18];
3420
500a3d0d
ES		 3421 u8 reserved_at_140[0x8];
3422 u8 underlay_qpn[0x18];
a12ff35e
EBE		 3423
3424 u8 reserved_at_160[0x8];
3425 u8 pd[0x18];
3426
3427 u8 reserved_at_180[0x380];
e281682b
SM		 3428};
3429
3430enum {
3431 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3432 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3433};
3434
3435enum {
50f477fe
BBI		 3436 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3437 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
e281682b
SM		 3438};
3439
3440enum {
2be6967c
SM		 3441 MLX5_RX_HASH_FN_NONE = 0x0,
3442 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3443 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 3444};
3445
3446enum {
5d773ff4
MB		 3447 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3448 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 3449};
3450
3451struct mlx5_ifc_tirc_bits {
b4ff3a36 3452 u8 reserved_at_0[0x20];
e281682b
SM		 3453
3454 u8 disp_type[0x4];
ee5cdf7a
TT		 3455 u8 tls_en[0x1];
3456 u8 reserved_at_25[0x1b];
e281682b 3457
b4ff3a36 3458 u8 reserved_at_40[0x40];
e281682b 3459
b4ff3a36 3460 u8 reserved_at_80[0x4];
e281682b 3461 u8 lro_timeout_period_usecs[0x10];
50f477fe 3462 u8 packet_merge_mask[0x4];
e281682b
SM		 3463 u8 lro_max_ip_payload_size[0x8];
3464
b4ff3a36 3465 u8 reserved_at_a0[0x40];
e281682b 3466
b4ff3a36 3467 u8 reserved_at_e0[0x8];
e281682b
SM		 3468 u8 inline_rqn[0x18];
3469
3470 u8 rx_hash_symmetric[0x1];
b4ff3a36 3471 u8 reserved_at_101[0x1];
e281682b 3472 u8 tunneled_offload_en[0x1];
b4ff3a36 3473 u8 reserved_at_103[0x5];
e281682b
SM		 3474 u8 indirect_table[0x18];
3475
3476 u8 rx_hash_fn[0x4];
b4ff3a36 3477 u8 reserved_at_124[0x2];
e281682b
SM		 3478 u8 self_lb_block[0x2];
3479 u8 transport_domain[0x18];
3480
3481 u8 rx_hash_toeplitz_key[10][0x20];
3482
3483 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3484
3485 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3486
b4ff3a36 3487 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 3488};
3489
3490enum {
3491 MLX5_SRQC_STATE_GOOD = 0x0,
3492 MLX5_SRQC_STATE_ERROR = 0x1,
3493};
3494
3495struct mlx5_ifc_srqc_bits {
3496 u8 state[0x4];
3497 u8 log_srq_size[0x4];
b4ff3a36 3498 u8 reserved_at_8[0x18];
e281682b
SM		 3499
3500 u8 wq_signature[0x1];
3501 u8 cont_srq[0x1];
b4ff3a36 3502 u8 reserved_at_22[0x1];
e281682b 3503 u8 rlky[0x1];
b4ff3a36 3504 u8 reserved_at_24[0x1];
e281682b
SM		 3505 u8 log_rq_stride[0x3];
3506 u8 xrcd[0x18];
3507
3508 u8 page_offset[0x6];
b4ff3a36 3509 u8 reserved_at_46[0x2];
e281682b
SM		 3510 u8 cqn[0x18];
3511
b4ff3a36 3512 u8 reserved_at_60[0x20];
e281682b 3513
b4ff3a36 3514 u8 reserved_at_80[0x2];
e281682b 3515 u8 log_page_size[0x6];
b4ff3a36 3516 u8 reserved_at_88[0x18];
e281682b 3517
b4ff3a36 3518 u8 reserved_at_a0[0x20];
e281682b 3519
b4ff3a36 3520 u8 reserved_at_c0[0x8];
e281682b
SM		 3521 u8 pd[0x18];
3522
3523 u8 lwm[0x10];
3524 u8 wqe_cnt[0x10];
3525
b4ff3a36 3526 u8 reserved_at_100[0x40];
e281682b 3527
01949d01 3528 u8 dbr_addr[0x40];
e281682b 3529
b4ff3a36 3530 u8 reserved_at_180[0x80];
e281682b
SM		 3531};
3532
3533enum {
3534 MLX5_SQC_STATE_RST = 0x0,
3535 MLX5_SQC_STATE_RDY = 0x1,
3536 MLX5_SQC_STATE_ERR = 0x3,
3537};
3538
3539struct mlx5_ifc_sqc_bits {
3540 u8 rlky[0x1];
3541 u8 cd_master[0x1];
3542 u8 fre[0x1];
3543 u8 flush_in_error_en[0x1];
795b609c 3544 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 3545 u8 min_wqe_inline_mode[0x3];
e281682b 3546 u8 state[0x4];
7d5e1423 3547 u8 reg_umr[0x1];
547eede0 3548 u8 allow_swp[0x1];
40817cdb 3549 u8 hairpin[0x1];
a6a217dd
AL		 3550 u8 reserved_at_f[0xb];
3551 u8 ts_format[0x2];
3552 u8 reserved_at_1c[0x4];
e281682b 3553
b4ff3a36 3554 u8 reserved_at_20[0x8];
e281682b
SM		 3555 u8 user_index[0x18];
3556
b4ff3a36 3557 u8 reserved_at_40[0x8];
e281682b
SM		 3558 u8 cqn[0x18];
3559
40817cdb
OG		 3560 u8 reserved_at_60[0x8];
3561 u8 hairpin_peer_rq[0x18];
3562
3563 u8 reserved_at_80[0x10];
3564 u8 hairpin_peer_vhca[0x10];
3565
59d2ae1d 3566 u8 reserved_at_a0[0x20];
e281682b 3567
59d2ae1d
EBE		 3568 u8 reserved_at_c0[0x8];
3569 u8 ts_cqe_to_dest_cqn[0x18];
e281682b 3570
59d2ae1d 3571 u8 reserved_at_e0[0x10];
7486216b 3572 u8 packet_pacing_rate_limit_index[0x10];
e281682b 3573 u8 tis_lst_sz[0x10];
214baf22 3574 u8 qos_queue_group_id[0x10];
e281682b 3575
b4ff3a36 3576 u8 reserved_at_120[0x40];
e281682b 3577
b4ff3a36 3578 u8 reserved_at_160[0x8];
e281682b
SM		 3579 u8 tis_num_0[0x18];
3580
3581 struct mlx5_ifc_wq_bits wq;
3582};
3583
813f8540
MHY		 3584enum {
3585 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3586 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3587 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3588 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
214baf22 3589 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
813f8540
MHY		 3590};
3591
6cedde45
EC		 3592enum {
3593 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3594 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3595 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3596 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3597};
3598
813f8540
MHY		 3599struct mlx5_ifc_scheduling_context_bits {
3600 u8 element_type[0x8];
3601 u8 reserved_at_8[0x18];
3602
3603 u8 element_attributes[0x20];
3604
3605 u8 parent_element_id[0x20];
3606
3607 u8 reserved_at_60[0x40];
3608
3609 u8 bw_share[0x20];
3610
3611 u8 max_average_bw[0x20];
3612
3613 u8 reserved_at_e0[0x120];
3614};
3615
e281682b 3616struct mlx5_ifc_rqtc_bits {
8a06a79b 3617 u8 reserved_at_0[0xa0];
e281682b 3618
8a06a79b
EC		 3619 u8 reserved_at_a0[0x5];
3620 u8 list_q_type[0x3];
3621 u8 reserved_at_a8[0x8];
3622 u8 rqt_max_size[0x10];
e281682b 3623
8a06a79b
EC		 3624 u8 rq_vhca_id_format[0x1];
3625 u8 reserved_at_c1[0xf];
3626 u8 rqt_actual_size[0x10];
e281682b 3627
8a06a79b 3628 u8 reserved_at_e0[0x6a0];
e281682b 3629
b6ca09cb 3630 struct mlx5_ifc_rq_num_bits rq_num[];
e281682b
SM		 3631};
3632
3633enum {
3634 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3635 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3636};
3637
3638enum {
3639 MLX5_RQC_STATE_RST = 0x0,
3640 MLX5_RQC_STATE_RDY = 0x1,
3641 MLX5_RQC_STATE_ERR = 0x3,
3642};
3643
7025329d
BBI		 3644enum {
3645 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3646 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3647 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3648};
3649
3650enum {
3651 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3652 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3653 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3654};
3655
e281682b
SM		 3656struct mlx5_ifc_rqc_bits {
3657 u8 rlky[0x1];
03404e8a 3658 u8 delay_drop_en[0x1];
7d5e1423 3659 u8 scatter_fcs[0x1];
e281682b
SM		 3660 u8 vsd[0x1];
3661 u8 mem_rq_type[0x4];
3662 u8 state[0x4];
b4ff3a36 3663 u8 reserved_at_c[0x1];
e281682b 3664 u8 flush_in_error_en[0x1];
40817cdb 3665 u8 hairpin[0x1];
a6a217dd
AL		 3666 u8 reserved_at_f[0xb];
3667 u8 ts_format[0x2];
3668 u8 reserved_at_1c[0x4];
e281682b 3669
b4ff3a36 3670 u8 reserved_at_20[0x8];
e281682b
SM		 3671 u8 user_index[0x18];
3672
b4ff3a36 3673 u8 reserved_at_40[0x8];
e281682b
SM		 3674 u8 cqn[0x18];
3675
3676 u8 counter_set_id[0x8];
b4ff3a36 3677 u8 reserved_at_68[0x18];
e281682b 3678
b4ff3a36 3679 u8 reserved_at_80[0x8];
e281682b
SM		 3680 u8 rmpn[0x18];
3681
40817cdb
OG		 3682 u8 reserved_at_a0[0x8];
3683 u8 hairpin_peer_sq[0x18];
3684
3685 u8 reserved_at_c0[0x10];
3686 u8 hairpin_peer_vhca[0x10];
3687
7025329d
BBI		 3688 u8 reserved_at_e0[0x46];
3689 u8 shampo_no_match_alignment_granularity[0x2];
3690 u8 reserved_at_128[0x6];
3691 u8 shampo_match_criteria_type[0x2];
3692 u8 reservation_timeout[0x10];
3693
3694 u8 reserved_at_140[0x40];
e281682b
SM		 3695
3696 struct mlx5_ifc_wq_bits wq;
3697};
3698
3699enum {
3700 MLX5_RMPC_STATE_RDY = 0x1,
3701 MLX5_RMPC_STATE_ERR = 0x3,
3702};
3703
3704struct mlx5_ifc_rmpc_bits {
b4ff3a36 3705 u8 reserved_at_0[0x8];
e281682b 3706 u8 state[0x4];
b4ff3a36 3707 u8 reserved_at_c[0x14];
e281682b
SM		 3708
3709 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 3710 u8 reserved_at_21[0x1f];
e281682b 3711
b4ff3a36 3712 u8 reserved_at_40[0x140];
e281682b
SM		 3713
3714 struct mlx5_ifc_wq_bits wq;
3715};
3716
e281682b 3717struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 3718 u8 reserved_at_0[0x5];
3719 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 3720 u8 reserved_at_8[0x15];
3721 u8 disable_mc_local_lb[0x1];
3722 u8 disable_uc_local_lb[0x1];
e281682b
SM		 3723 u8 roce_en[0x1];
3724
d82b7318 3725 u8 arm_change_event[0x1];
b4ff3a36 3726 u8 reserved_at_21[0x1a];
d82b7318
SM		 3727 u8 event_on_mtu[0x1];
3728 u8 event_on_promisc_change[0x1];
3729 u8 event_on_vlan_change[0x1];
3730 u8 event_on_mc_address_change[0x1];
3731 u8 event_on_uc_address_change[0x1];
e281682b 3732
32f69e4b
DJ		 3733 u8 reserved_at_40[0xc];
3734
3735 u8 affiliation_criteria[0x4];
3736 u8 affiliated_vhca_id[0x10];
3737
3738 u8 reserved_at_60[0xd0];
d82b7318
SM		 3739
3740 u8 mtu[0x10];
3741
9efa7525
AS		 3742 u8 system_image_guid[0x40];
3743 u8 port_guid[0x40];
3744 u8 node_guid[0x40];
3745
b4ff3a36 3746 u8 reserved_at_200[0x140];
9efa7525 3747 u8 qkey_violation_counter[0x10];
b4ff3a36 3748 u8 reserved_at_350[0x430];
d82b7318
SM		 3749
3750 u8 promisc_uc[0x1];
3751 u8 promisc_mc[0x1];
3752 u8 promisc_all[0x1];
b4ff3a36 3753 u8 reserved_at_783[0x2];
e281682b 3754 u8 allowed_list_type[0x3];
b4ff3a36 3755 u8 reserved_at_788[0xc];
e281682b
SM		 3756 u8 allowed_list_size[0xc];
3757
3758 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3759
b4ff3a36 3760 u8 reserved_at_7e0[0x20];
e281682b 3761
b6ca09cb 3762 u8 current_uc_mac_address[][0x40];
e281682b
SM		 3763};
3764
3765enum {
3766 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3767 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3768 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 3769 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 3770 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 3771 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 3772};
3773
3774struct mlx5_ifc_mkc_bits {
b4ff3a36 3775 u8 reserved_at_0[0x1];
e281682b 3776 u8 free[0x1];
cdbd0d2b
AL		 3777 u8 reserved_at_2[0x1];
3778 u8 access_mode_4_2[0x3];
3779 u8 reserved_at_6[0x7];
3780 u8 relaxed_ordering_write[0x1];
3781 u8 reserved_at_e[0x1];
e281682b
SM		 3782 u8 small_fence_on_rdma_read_response[0x1];
3783 u8 umr_en[0x1];
3784 u8 a[0x1];
3785 u8 rw[0x1];
3786 u8 rr[0x1];
3787 u8 lw[0x1];
3788 u8 lr[0x1];
cdbd0d2b 3789 u8 access_mode_1_0[0x2];
b4ff3a36 3790 u8 reserved_at_18[0x8];
e281682b
SM		 3791
3792 u8 qpn[0x18];
3793 u8 mkey_7_0[0x8];
3794
b4ff3a36 3795 u8 reserved_at_40[0x20];
e281682b
SM		 3796
3797 u8 length64[0x1];
3798 u8 bsf_en[0x1];
3799 u8 sync_umr[0x1];
b4ff3a36 3800 u8 reserved_at_63[0x2];
e281682b 3801 u8 expected_sigerr_count[0x1];
b4ff3a36 3802 u8 reserved_at_66[0x1];
e281682b
SM		 3803 u8 en_rinval[0x1];
3804 u8 pd[0x18];
3805
3806 u8 start_addr[0x40];
3807
3808 u8 len[0x40];
3809
3810 u8 bsf_octword_size[0x20];
3811
b4ff3a36 3812 u8 reserved_at_120[0x80];
e281682b
SM		 3813
3814 u8 translations_octword_size[0x20];
3815
a880a6dd
MG		 3816 u8 reserved_at_1c0[0x19];
3817 u8 relaxed_ordering_read[0x1];
3818 u8 reserved_at_1d9[0x1];
e281682b
SM		 3819 u8 log_page_size[0x5];
3820
b4ff3a36 3821 u8 reserved_at_1e0[0x20];
e281682b
SM		 3822};
3823
3824struct mlx5_ifc_pkey_bits {
b4ff3a36 3825 u8 reserved_at_0[0x10];
e281682b
SM		 3826 u8 pkey[0x10];
3827};
3828
3829struct mlx5_ifc_array128_auto_bits {
3830 u8 array128_auto[16][0x8];
3831};
3832
3833struct mlx5_ifc_hca_vport_context_bits {
3834 u8 field_select[0x20];
3835
b4ff3a36 3836 u8 reserved_at_20[0xe0];
e281682b
SM		 3837
3838 u8 sm_virt_aware[0x1];
3839 u8 has_smi[0x1];
3840 u8 has_raw[0x1];
3841 u8 grh_required[0x1];
b4ff3a36 3842 u8 reserved_at_104[0xc];
707c4602
MD		 3843 u8 port_physical_state[0x4];
3844 u8 vport_state_policy[0x4];
3845 u8 port_state[0x4];
e281682b
SM		 3846 u8 vport_state[0x4];
3847
b4ff3a36 3848 u8 reserved_at_120[0x20];
707c4602
MD		 3849
3850 u8 system_image_guid[0x40];
e281682b
SM		 3851
3852 u8 port_guid[0x40];
3853
3854 u8 node_guid[0x40];
3855
3856 u8 cap_mask1[0x20];
3857
3858 u8 cap_mask1_field_select[0x20];
3859
3860 u8 cap_mask2[0x20];
3861
3862 u8 cap_mask2_field_select[0x20];
3863
b4ff3a36 3864 u8 reserved_at_280[0x80];
e281682b
SM		 3865
3866 u8 lid[0x10];
b4ff3a36 3867 u8 reserved_at_310[0x4];
e281682b
SM		 3868 u8 init_type_reply[0x4];
3869 u8 lmc[0x3];
3870 u8 subnet_timeout[0x5];
3871
3872 u8 sm_lid[0x10];
3873 u8 sm_sl[0x4];
b4ff3a36 3874 u8 reserved_at_334[0xc];
e281682b
SM		 3875
3876 u8 qkey_violation_counter[0x10];
3877 u8 pkey_violation_counter[0x10];
3878
b4ff3a36 3879 u8 reserved_at_360[0xca0];
e281682b
SM		 3880};
3881
d6666753 3882struct mlx5_ifc_esw_vport_context_bits {
65c0f2c1
JL		 3883 u8 fdb_to_vport_reg_c[0x1];
3884 u8 reserved_at_1[0x2];
d6666753
SM		 3885 u8 vport_svlan_strip[0x1];
3886 u8 vport_cvlan_strip[0x1];
3887 u8 vport_svlan_insert[0x1];
3888 u8 vport_cvlan_insert[0x2];
65c0f2c1
JL		 3889 u8 fdb_to_vport_reg_c_id[0x8];
3890 u8 reserved_at_10[0x10];
d6666753 3891
b4ff3a36 3892 u8 reserved_at_20[0x20];
d6666753
SM		 3893
3894 u8 svlan_cfi[0x1];
3895 u8 svlan_pcp[0x3];
3896 u8 svlan_id[0xc];
3897 u8 cvlan_cfi[0x1];
3898 u8 cvlan_pcp[0x3];
3899 u8 cvlan_id[0xc];
3900
97b5484e
AV		 3901 u8 reserved_at_60[0x720];
3902
3903 u8 sw_steering_vport_icm_address_rx[0x40];
3904
3905 u8 sw_steering_vport_icm_address_tx[0x40];
d6666753
SM		 3906};
3907
e281682b
SM		 3908enum {
3909 MLX5_EQC_STATUS_OK = 0x0,
3910 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3911};
3912
3913enum {
3914 MLX5_EQC_ST_ARMED = 0x9,
3915 MLX5_EQC_ST_FIRED = 0xa,
3916};
3917
3918struct mlx5_ifc_eqc_bits {
3919 u8 status[0x4];
b4ff3a36 3920 u8 reserved_at_4[0x9];
e281682b
SM		 3921 u8 ec[0x1];
3922 u8 oi[0x1];
b4ff3a36 3923 u8 reserved_at_f[0x5];
e281682b 3924 u8 st[0x4];
b4ff3a36 3925 u8 reserved_at_18[0x8];
e281682b 3926
b4ff3a36 3927 u8 reserved_at_20[0x20];
e281682b 3928
b4ff3a36 3929 u8 reserved_at_40[0x14];
e281682b 3930 u8 page_offset[0x6];
b4ff3a36 3931 u8 reserved_at_5a[0x6];
e281682b 3932
b4ff3a36 3933 u8 reserved_at_60[0x3];
e281682b
SM		 3934 u8 log_eq_size[0x5];
3935 u8 uar_page[0x18];
3936
b4ff3a36 3937 u8 reserved_at_80[0x20];
e281682b 3938
3af26495
SD		 3939 u8 reserved_at_a0[0x14];
3940 u8 intr[0xc];
e281682b 3941
b4ff3a36 3942 u8 reserved_at_c0[0x3];
e281682b 3943 u8 log_page_size[0x5];
b4ff3a36 3944 u8 reserved_at_c8[0x18];
e281682b 3945
b4ff3a36 3946 u8 reserved_at_e0[0x60];
e281682b 3947
b4ff3a36 3948 u8 reserved_at_140[0x8];
e281682b
SM		 3949 u8 consumer_counter[0x18];
3950
b4ff3a36 3951 u8 reserved_at_160[0x8];
e281682b
SM		 3952 u8 producer_counter[0x18];
3953
b4ff3a36 3954 u8 reserved_at_180[0x80];
e281682b
SM		 3955};
3956
3957enum {
3958 MLX5_DCTC_STATE_ACTIVE = 0x0,
3959 MLX5_DCTC_STATE_DRAINING = 0x1,
3960 MLX5_DCTC_STATE_DRAINED = 0x2,
3961};
3962
3963enum {
3964 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3965 MLX5_DCTC_CS_RES_NA = 0x1,
3966 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3967};
3968
3969enum {
3970 MLX5_DCTC_MTU_256_BYTES = 0x1,
3971 MLX5_DCTC_MTU_512_BYTES = 0x2,
3972 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3973 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3974 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3975};
3976
3977struct mlx5_ifc_dctc_bits {
b4ff3a36 3978 u8 reserved_at_0[0x4];
e281682b 3979 u8 state[0x4];
b4ff3a36 3980 u8 reserved_at_8[0x18];
e281682b 3981
b4ff3a36 3982 u8 reserved_at_20[0x8];
e281682b
SM		 3983 u8 user_index[0x18];
3984
b4ff3a36 3985 u8 reserved_at_40[0x8];
e281682b
SM		 3986 u8 cqn[0x18];
3987
3988 u8 counter_set_id[0x8];
3989 u8 atomic_mode[0x4];
3990 u8 rre[0x1];
3991 u8 rwe[0x1];
3992 u8 rae[0x1];
3993 u8 atomic_like_write_en[0x1];
3994 u8 latency_sensitive[0x1];
3995 u8 rlky[0x1];
3996 u8 free_ar[0x1];
b4ff3a36 3997 u8 reserved_at_73[0xd];
e281682b 3998
b4ff3a36 3999 u8 reserved_at_80[0x8];
e281682b 4000 u8 cs_res[0x8];
b4ff3a36 4001 u8 reserved_at_90[0x3];
e281682b 4002 u8 min_rnr_nak[0x5];
b4ff3a36 4003 u8 reserved_at_98[0x8];
e281682b 4004
b4ff3a36 4005 u8 reserved_at_a0[0x8];
7486216b 4006 u8 srqn_xrqn[0x18];
e281682b 4007
b4ff3a36 4008 u8 reserved_at_c0[0x8];
e281682b
SM		 4009 u8 pd[0x18];
4010
4011 u8 tclass[0x8];
b4ff3a36 4012 u8 reserved_at_e8[0x4];
e281682b
SM		 4013 u8 flow_label[0x14];
4014
4015 u8 dc_access_key[0x40];
4016
b4ff3a36 4017 u8 reserved_at_140[0x5];
e281682b
SM		 4018 u8 mtu[0x3];
4019 u8 port[0x8];
4020 u8 pkey_index[0x10];
4021
b4ff3a36 4022 u8 reserved_at_160[0x8];
e281682b 4023 u8 my_addr_index[0x8];
b4ff3a36 4024 u8 reserved_at_170[0x8];
e281682b
SM		 4025 u8 hop_limit[0x8];
4026
4027 u8 dc_access_key_violation_count[0x20];
4028
b4ff3a36 4029 u8 reserved_at_1a0[0x14];
e281682b
SM		 4030 u8 dei_cfi[0x1];
4031 u8 eth_prio[0x3];
4032 u8 ecn[0x2];
4033 u8 dscp[0x6];
4034
a645a89d
LR		 4035 u8 reserved_at_1c0[0x20];
4036 u8 ece[0x20];
e281682b
SM		 4037};
4038
4039enum {
4040 MLX5_CQC_STATUS_OK = 0x0,
4041 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4042 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4043};
4044
4045enum {
4046 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4047 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4048};
4049
4050enum {
4051 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4052 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4053 MLX5_CQC_ST_FIRED = 0xa,
4054};
4055
7d5e1423
SM		 4056enum {
4057 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4058 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 4059 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 4060};
4061
e281682b
SM		 4062struct mlx5_ifc_cqc_bits {
4063 u8 status[0x4];
bd371975
LR		 4064 u8 reserved_at_4[0x2];
4065 u8 dbr_umem_valid[0x1];
616d5769 4066 u8 apu_cq[0x1];
e281682b
SM		 4067 u8 cqe_sz[0x3];
4068 u8 cc[0x1];
b4ff3a36 4069 u8 reserved_at_c[0x1];
e281682b
SM		 4070 u8 scqe_break_moderation_en[0x1];
4071 u8 oi[0x1];
7d5e1423
SM		 4072 u8 cq_period_mode[0x2];
4073 u8 cqe_comp_en[0x1];
e281682b
SM		 4074 u8 mini_cqe_res_format[0x2];
4075 u8 st[0x4];
b4ff3a36 4076 u8 reserved_at_18[0x8];
e281682b 4077
b4ff3a36 4078 u8 reserved_at_20[0x20];
e281682b 4079
b4ff3a36 4080 u8 reserved_at_40[0x14];
e281682b 4081 u8 page_offset[0x6];
b4ff3a36 4082 u8 reserved_at_5a[0x6];
e281682b 4083
b4ff3a36 4084 u8 reserved_at_60[0x3];
e281682b
SM		 4085 u8 log_cq_size[0x5];
4086 u8 uar_page[0x18];
4087
b4ff3a36 4088 u8 reserved_at_80[0x4];
e281682b
SM		 4089 u8 cq_period[0xc];
4090 u8 cq_max_count[0x10];
4091
616d5769 4092 u8 c_eqn_or_apu_element[0x20];
e281682b 4093
b4ff3a36 4094 u8 reserved_at_c0[0x3];
e281682b 4095 u8 log_page_size[0x5];
b4ff3a36 4096 u8 reserved_at_c8[0x18];
e281682b 4097
b4ff3a36 4098 u8 reserved_at_e0[0x20];
e281682b 4099
b4ff3a36 4100 u8 reserved_at_100[0x8];
e281682b
SM		 4101 u8 last_notified_index[0x18];
4102
b4ff3a36 4103 u8 reserved_at_120[0x8];
e281682b
SM		 4104 u8 last_solicit_index[0x18];
4105
b4ff3a36 4106 u8 reserved_at_140[0x8];
e281682b
SM		 4107 u8 consumer_counter[0x18];
4108
b4ff3a36 4109 u8 reserved_at_160[0x8];
e281682b
SM		 4110 u8 producer_counter[0x18];
4111
b4ff3a36 4112 u8 reserved_at_180[0x40];
e281682b
SM		 4113
4114 u8 dbr_addr[0x40];
4115};
4116
4117union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4118 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4119 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4120 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 4121 u8 reserved_at_0[0x800];
e281682b
SM		 4122};
4123
4124struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 4125 u8 reserved_at_0[0xc0];
e281682b 4126
b4ff3a36 4127 u8 reserved_at_c0[0x8];
211e6c80
MD		 4128 u8 ieee_vendor_id[0x18];
4129
b4ff3a36 4130 u8 reserved_at_e0[0x10];
e281682b
SM		 4131 u8 vsd_vendor_id[0x10];
4132
4133 u8 vsd[208][0x8];
4134
4135 u8 vsd_contd_psid[16][0x8];
4136};
4137
7486216b
SM		 4138enum {
4139 MLX5_XRQC_STATE_GOOD = 0x0,
4140 MLX5_XRQC_STATE_ERROR = 0x1,
4141};
4142
4143enum {
4144 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4145 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4146};
4147
4148enum {
4149 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4150};
4151
4152struct mlx5_ifc_tag_matching_topology_context_bits {
4153 u8 log_matching_list_sz[0x4];
4154 u8 reserved_at_4[0xc];
4155 u8 append_next_index[0x10];
4156
4157 u8 sw_phase_cnt[0x10];
4158 u8 hw_phase_cnt[0x10];
4159
4160 u8 reserved_at_40[0x40];
4161};
4162
4163struct mlx5_ifc_xrqc_bits {
4164 u8 state[0x4];
4165 u8 rlkey[0x1];
4166 u8 reserved_at_5[0xf];
4167 u8 topology[0x4];
4168 u8 reserved_at_18[0x4];
4169 u8 offload[0x4];
4170
4171 u8 reserved_at_20[0x8];
4172 u8 user_index[0x18];
4173
4174 u8 reserved_at_40[0x8];
4175 u8 cqn[0x18];
4176
4177 u8 reserved_at_60[0xa0];
4178
4179 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4180
6e44636a 4181 u8 reserved_at_180[0x280];
7486216b
SM		 4182
4183 struct mlx5_ifc_wq_bits wq;
4184};
4185
e281682b
SM		 4186union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4187 struct mlx5_ifc_modify_field_select_bits modify_field_select;
4188 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 4189 u8 reserved_at_0[0x20];
e281682b
SM		 4190};
4191
4192union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4193 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4194 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4195 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 4196 u8 reserved_at_0[0x20];
e281682b
SM		 4197};
4198
4199union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4200 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4201 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4202 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4203 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4204 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4205 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 4206 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4207 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
1c64bf6f 4208 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 4209 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 4210 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 4211 u8 reserved_at_0[0x7c0];
e281682b
SM		 4212};
4213
8ed1a630
GP		 4214union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4215 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4216 u8 reserved_at_0[0x7c0];
4217};
4218
e281682b
SM		 4219union mlx5_ifc_event_auto_bits {
4220 struct mlx5_ifc_comp_event_bits comp_event;
4221 struct mlx5_ifc_dct_events_bits dct_events;
4222 struct mlx5_ifc_qp_events_bits qp_events;
4223 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4224 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4225 struct mlx5_ifc_cq_error_bits cq_error;
4226 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4227 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4228 struct mlx5_ifc_gpio_event_bits gpio_event;
4229 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4230 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4231 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 4232 u8 reserved_at_0[0xe0];
e281682b
SM		 4233};
4234
4235struct mlx5_ifc_health_buffer_bits {
b4ff3a36 4236 u8 reserved_at_0[0x100];
e281682b
SM		 4237
4238 u8 assert_existptr[0x20];
4239
4240 u8 assert_callra[0x20];
4241
cb464ba5
AL		 4242 u8 reserved_at_140[0x20];
4243
4244 u8 time[0x20];
e281682b
SM		 4245
4246 u8 fw_version[0x20];
4247
4248 u8 hw_id[0x20];
4249
cb464ba5
AL		 4250 u8 rfr[0x1];
4251 u8 reserved_at_1c1[0x3];
4252 u8 valid[0x1];
4253 u8 severity[0x3];
4254 u8 reserved_at_1c8[0x18];
e281682b
SM		 4255
4256 u8 irisc_index[0x8];
4257 u8 synd[0x8];
4258 u8 ext_synd[0x10];
4259};
4260
4261struct mlx5_ifc_register_loopback_control_bits {
4262 u8 no_lb[0x1];
b4ff3a36 4263 u8 reserved_at_1[0x7];
e281682b 4264 u8 port[0x8];
b4ff3a36 4265 u8 reserved_at_10[0x10];
e281682b 4266
b4ff3a36 4267 u8 reserved_at_20[0x60];
e281682b
SM		 4268};
4269
813f8540
MHY		 4270struct mlx5_ifc_vport_tc_element_bits {
4271 u8 traffic_class[0x4];
4272 u8 reserved_at_4[0xc];
4273 u8 vport_number[0x10];
4274};
4275
4276struct mlx5_ifc_vport_element_bits {
4277 u8 reserved_at_0[0x10];
4278 u8 vport_number[0x10];
4279};
4280
4281enum {
4282 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4283 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4284 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4285};
4286
4287struct mlx5_ifc_tsar_element_bits {
4288 u8 reserved_at_0[0x8];
4289 u8 tsar_type[0x8];
4290 u8 reserved_at_10[0x10];
4291};
4292
8812c24d
MD		 4293enum {
4294 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4295 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4296};
4297
e281682b
SM		 4298struct mlx5_ifc_teardown_hca_out_bits {
4299 u8 status[0x8];
b4ff3a36 4300 u8 reserved_at_8[0x18];
e281682b
SM		 4301
4302 u8 syndrome[0x20];
4303
8812c24d
MD		 4304 u8 reserved_at_40[0x3f];
4305
fcd29ad1 4306 u8 state[0x1];
e281682b
SM		 4307};
4308
4309enum {
4310 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 4311 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 4312 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 4313};
4314
4315struct mlx5_ifc_teardown_hca_in_bits {
4316 u8 opcode[0x10];
b4ff3a36 4317 u8 reserved_at_10[0x10];
e281682b 4318
b4ff3a36 4319 u8 reserved_at_20[0x10];
e281682b
SM		 4320 u8 op_mod[0x10];
4321
b4ff3a36 4322 u8 reserved_at_40[0x10];
e281682b
SM		 4323 u8 profile[0x10];
4324
b4ff3a36 4325 u8 reserved_at_60[0x20];
e281682b
SM		 4326};
4327
4328struct mlx5_ifc_sqerr2rts_qp_out_bits {
4329 u8 status[0x8];
b4ff3a36 4330 u8 reserved_at_8[0x18];
e281682b
SM		 4331
4332 u8 syndrome[0x20];
4333
b4ff3a36 4334 u8 reserved_at_40[0x40];
e281682b
SM		 4335};
4336
4337struct mlx5_ifc_sqerr2rts_qp_in_bits {
4338 u8 opcode[0x10];
4ac63ec7 4339 u8 uid[0x10];
e281682b 4340
b4ff3a36 4341 u8 reserved_at_20[0x10];
e281682b
SM		 4342 u8 op_mod[0x10];
4343
b4ff3a36 4344 u8 reserved_at_40[0x8];
e281682b
SM		 4345 u8 qpn[0x18];
4346
b4ff3a36 4347 u8 reserved_at_60[0x20];
e281682b
SM		 4348
4349 u8 opt_param_mask[0x20];
4350
b4ff3a36 4351 u8 reserved_at_a0[0x20];
e281682b
SM		 4352
4353 struct mlx5_ifc_qpc_bits qpc;
4354
b4ff3a36 4355 u8 reserved_at_800[0x80];
e281682b
SM		 4356};
4357
4358struct mlx5_ifc_sqd2rts_qp_out_bits {
4359 u8 status[0x8];
b4ff3a36 4360 u8 reserved_at_8[0x18];
e281682b
SM		 4361
4362 u8 syndrome[0x20];
4363
b4ff3a36 4364 u8 reserved_at_40[0x40];
e281682b
SM		 4365};
4366
4367struct mlx5_ifc_sqd2rts_qp_in_bits {
4368 u8 opcode[0x10];
4ac63ec7 4369 u8 uid[0x10];
e281682b 4370
b4ff3a36 4371 u8 reserved_at_20[0x10];
e281682b
SM		 4372 u8 op_mod[0x10];
4373
b4ff3a36 4374 u8 reserved_at_40[0x8];
e281682b
SM		 4375 u8 qpn[0x18];
4376
b4ff3a36 4377 u8 reserved_at_60[0x20];
e281682b
SM		 4378
4379 u8 opt_param_mask[0x20];
4380
b4ff3a36 4381 u8 reserved_at_a0[0x20];
e281682b
SM		 4382
4383 struct mlx5_ifc_qpc_bits qpc;
4384
b4ff3a36 4385 u8 reserved_at_800[0x80];
e281682b
SM		 4386};
4387
4388struct mlx5_ifc_set_roce_address_out_bits {
4389 u8 status[0x8];
b4ff3a36 4390 u8 reserved_at_8[0x18];
e281682b
SM		 4391
4392 u8 syndrome[0x20];
4393
b4ff3a36 4394 u8 reserved_at_40[0x40];
e281682b
SM		 4395};
4396
4397struct mlx5_ifc_set_roce_address_in_bits {
4398 u8 opcode[0x10];
b4ff3a36 4399 u8 reserved_at_10[0x10];
e281682b 4400
b4ff3a36 4401 u8 reserved_at_20[0x10];
e281682b
SM		 4402 u8 op_mod[0x10];
4403
4404 u8 roce_address_index[0x10];
32f69e4b
DJ		 4405 u8 reserved_at_50[0xc];
4406 u8 vhca_port_num[0x4];
e281682b 4407
b4ff3a36 4408 u8 reserved_at_60[0x20];
e281682b
SM		 4409
4410 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4411};
4412
4413struct mlx5_ifc_set_mad_demux_out_bits {
4414 u8 status[0x8];
b4ff3a36 4415 u8 reserved_at_8[0x18];
e281682b
SM		 4416
4417 u8 syndrome[0x20];
4418
b4ff3a36 4419 u8 reserved_at_40[0x40];
e281682b
SM		 4420};
4421
4422enum {
4423 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4424 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4425};
4426
4427struct mlx5_ifc_set_mad_demux_in_bits {
4428 u8 opcode[0x10];
b4ff3a36 4429 u8 reserved_at_10[0x10];
e281682b 4430
b4ff3a36 4431 u8 reserved_at_20[0x10];
e281682b
SM		 4432 u8 op_mod[0x10];
4433
b4ff3a36 4434 u8 reserved_at_40[0x20];
e281682b 4435
b4ff3a36 4436 u8 reserved_at_60[0x6];
e281682b 4437 u8 demux_mode[0x2];
b4ff3a36 4438 u8 reserved_at_68[0x18];
e281682b
SM		 4439};
4440
4441struct mlx5_ifc_set_l2_table_entry_out_bits {
4442 u8 status[0x8];
b4ff3a36 4443 u8 reserved_at_8[0x18];
e281682b
SM		 4444
4445 u8 syndrome[0x20];
4446
b4ff3a36 4447 u8 reserved_at_40[0x40];
e281682b
SM		 4448};
4449
4450struct mlx5_ifc_set_l2_table_entry_in_bits {
4451 u8 opcode[0x10];
b4ff3a36 4452 u8 reserved_at_10[0x10];
e281682b 4453
b4ff3a36 4454 u8 reserved_at_20[0x10];
e281682b
SM		 4455 u8 op_mod[0x10];
4456
b4ff3a36 4457 u8 reserved_at_40[0x60];
e281682b 4458
b4ff3a36 4459 u8 reserved_at_a0[0x8];
e281682b
SM		 4460 u8 table_index[0x18];
4461
b4ff3a36 4462 u8 reserved_at_c0[0x20];
e281682b 4463
b4ff3a36 4464 u8 reserved_at_e0[0x13];
e281682b
SM		 4465 u8 vlan_valid[0x1];
4466 u8 vlan[0xc];
4467
4468 struct mlx5_ifc_mac_address_layout_bits mac_address;
4469
b4ff3a36 4470 u8 reserved_at_140[0xc0];
e281682b
SM		 4471};
4472
4473struct mlx5_ifc_set_issi_out_bits {
4474 u8 status[0x8];
b4ff3a36 4475 u8 reserved_at_8[0x18];
e281682b
SM		 4476
4477 u8 syndrome[0x20];
4478
b4ff3a36 4479 u8 reserved_at_40[0x40];
e281682b
SM		 4480};
4481
4482struct mlx5_ifc_set_issi_in_bits {
4483 u8 opcode[0x10];
b4ff3a36 4484 u8 reserved_at_10[0x10];
e281682b 4485
b4ff3a36 4486 u8 reserved_at_20[0x10];
e281682b
SM		 4487 u8 op_mod[0x10];
4488
b4ff3a36 4489 u8 reserved_at_40[0x10];
e281682b
SM		 4490 u8 current_issi[0x10];
4491
b4ff3a36 4492 u8 reserved_at_60[0x20];
e281682b
SM		 4493};
4494
4495struct mlx5_ifc_set_hca_cap_out_bits {
4496 u8 status[0x8];
b4ff3a36 4497 u8 reserved_at_8[0x18];
e281682b
SM		 4498
4499 u8 syndrome[0x20];
4500
b4ff3a36 4501 u8 reserved_at_40[0x40];
e281682b
SM		 4502};
4503
4504struct mlx5_ifc_set_hca_cap_in_bits {
4505 u8 opcode[0x10];
b4ff3a36 4506 u8 reserved_at_10[0x10];
e281682b 4507
b4ff3a36 4508 u8 reserved_at_20[0x10];
e281682b
SM		 4509 u8 op_mod[0x10];
4510
959af556
YH		 4511 u8 other_function[0x1];
4512 u8 reserved_at_41[0xf];
4513 u8 function_id[0x10];
4514
4515 u8 reserved_at_60[0x20];
e281682b
SM		 4516
4517 union mlx5_ifc_hca_cap_union_bits capability;
4518};
4519
26a81453
MG		 4520enum {
4521 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4522 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4523 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2b58f6d9
RS		 4524 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4525 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
26a81453
MG		 4526};
4527
e281682b
SM		 4528struct mlx5_ifc_set_fte_out_bits {
4529 u8 status[0x8];
b4ff3a36 4530 u8 reserved_at_8[0x18];
e281682b
SM		 4531
4532 u8 syndrome[0x20];
4533
b4ff3a36 4534 u8 reserved_at_40[0x40];
e281682b
SM		 4535};
4536
4537struct mlx5_ifc_set_fte_in_bits {
4538 u8 opcode[0x10];
b4ff3a36 4539 u8 reserved_at_10[0x10];
e281682b 4540
b4ff3a36 4541 u8 reserved_at_20[0x10];
e281682b
SM		 4542 u8 op_mod[0x10];
4543
7d5e1423
SM		 4544 u8 other_vport[0x1];
4545 u8 reserved_at_41[0xf];
4546 u8 vport_number[0x10];
4547
4548 u8 reserved_at_60[0x20];
e281682b
SM		 4549
4550 u8 table_type[0x8];
b4ff3a36 4551 u8 reserved_at_88[0x18];
e281682b 4552
b4ff3a36 4553 u8 reserved_at_a0[0x8];
e281682b
SM		 4554 u8 table_id[0x18];
4555
822e114b
PB		 4556 u8 ignore_flow_level[0x1];
4557 u8 reserved_at_c1[0x17];
26a81453
MG		 4558 u8 modify_enable_mask[0x8];
4559
b4ff3a36 4560 u8 reserved_at_e0[0x20];
e281682b
SM		 4561
4562 u8 flow_index[0x20];
4563
b4ff3a36 4564 u8 reserved_at_120[0xe0];
e281682b
SM		 4565
4566 struct mlx5_ifc_flow_context_bits flow_context;
4567};
4568
4569struct mlx5_ifc_rts2rts_qp_out_bits {
4570 u8 status[0x8];
b4ff3a36 4571 u8 reserved_at_8[0x18];
e281682b
SM		 4572
4573 u8 syndrome[0x20];
4574
6b646a7e
LR		 4575 u8 reserved_at_40[0x20];
4576 u8 ece[0x20];
e281682b
SM		 4577};
4578
4579struct mlx5_ifc_rts2rts_qp_in_bits {
4580 u8 opcode[0x10];
4ac63ec7 4581 u8 uid[0x10];
e281682b 4582
b4ff3a36 4583 u8 reserved_at_20[0x10];
e281682b
SM		 4584 u8 op_mod[0x10];
4585
b4ff3a36 4586 u8 reserved_at_40[0x8];
e281682b
SM		 4587 u8 qpn[0x18];
4588
b4ff3a36 4589 u8 reserved_at_60[0x20];
e281682b
SM		 4590
4591 u8 opt_param_mask[0x20];
4592
6b646a7e 4593 u8 ece[0x20];
e281682b
SM		 4594
4595 struct mlx5_ifc_qpc_bits qpc;
4596
b4ff3a36 4597 u8 reserved_at_800[0x80];
e281682b
SM		 4598};
4599
4600struct mlx5_ifc_rtr2rts_qp_out_bits {
4601 u8 status[0x8];
b4ff3a36 4602 u8 reserved_at_8[0x18];
e281682b
SM		 4603
4604 u8 syndrome[0x20];
4605
6b646a7e
LR		 4606 u8 reserved_at_40[0x20];
4607 u8 ece[0x20];
e281682b
SM		 4608};
4609
4610struct mlx5_ifc_rtr2rts_qp_in_bits {
4611 u8 opcode[0x10];
4ac63ec7 4612 u8 uid[0x10];
e281682b 4613
b4ff3a36 4614 u8 reserved_at_20[0x10];
e281682b
SM		 4615 u8 op_mod[0x10];
4616
b4ff3a36 4617 u8 reserved_at_40[0x8];
e281682b
SM		 4618 u8 qpn[0x18];
4619
b4ff3a36 4620 u8 reserved_at_60[0x20];
e281682b
SM		 4621
4622 u8 opt_param_mask[0x20];
4623
6b646a7e 4624 u8 ece[0x20];
e281682b
SM		 4625
4626 struct mlx5_ifc_qpc_bits qpc;
4627
b4ff3a36 4628 u8 reserved_at_800[0x80];
e281682b
SM		 4629};
4630
4631struct mlx5_ifc_rst2init_qp_out_bits {
4632 u8 status[0x8];
b4ff3a36 4633 u8 reserved_at_8[0x18];
e281682b
SM		 4634
4635 u8 syndrome[0x20];
4636
ab183d46
LR		 4637 u8 reserved_at_40[0x20];
4638 u8 ece[0x20];
e281682b
SM		 4639};
4640
4641struct mlx5_ifc_rst2init_qp_in_bits {
4642 u8 opcode[0x10];
4ac63ec7 4643 u8 uid[0x10];
e281682b 4644
b4ff3a36 4645 u8 reserved_at_20[0x10];
e281682b
SM		 4646 u8 op_mod[0x10];
4647
b4ff3a36 4648 u8 reserved_at_40[0x8];
e281682b
SM		 4649 u8 qpn[0x18];
4650
b4ff3a36 4651 u8 reserved_at_60[0x20];
e281682b
SM		 4652
4653 u8 opt_param_mask[0x20];
4654
ab183d46 4655 u8 ece[0x20];
e281682b
SM		 4656
4657 struct mlx5_ifc_qpc_bits qpc;
4658
b4ff3a36 4659 u8 reserved_at_800[0x80];
e281682b
SM		 4660};
4661
7486216b
SM		 4662struct mlx5_ifc_query_xrq_out_bits {
4663 u8 status[0x8];
4664 u8 reserved_at_8[0x18];
4665
4666 u8 syndrome[0x20];
4667
4668 u8 reserved_at_40[0x40];
4669
4670 struct mlx5_ifc_xrqc_bits xrq_context;
4671};
4672
4673struct mlx5_ifc_query_xrq_in_bits {
4674 u8 opcode[0x10];
4675 u8 reserved_at_10[0x10];
4676
4677 u8 reserved_at_20[0x10];
4678 u8 op_mod[0x10];
4679
4680 u8 reserved_at_40[0x8];
4681 u8 xrqn[0x18];
4682
4683 u8 reserved_at_60[0x20];
4684};
4685
e281682b
SM		 4686struct mlx5_ifc_query_xrc_srq_out_bits {
4687 u8 status[0x8];
b4ff3a36 4688 u8 reserved_at_8[0x18];
e281682b
SM		 4689
4690 u8 syndrome[0x20];
4691
b4ff3a36 4692 u8 reserved_at_40[0x40];
e281682b
SM		 4693
4694 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4695
b4ff3a36 4696 u8 reserved_at_280[0x600];
e281682b 4697
b6ca09cb 4698 u8 pas[][0x40];
e281682b
SM		 4699};
4700
4701struct mlx5_ifc_query_xrc_srq_in_bits {
4702 u8 opcode[0x10];
b4ff3a36 4703 u8 reserved_at_10[0x10];
e281682b 4704
b4ff3a36 4705 u8 reserved_at_20[0x10];
e281682b
SM		 4706 u8 op_mod[0x10];
4707
b4ff3a36 4708 u8 reserved_at_40[0x8];
e281682b
SM		 4709 u8 xrc_srqn[0x18];
4710
b4ff3a36 4711 u8 reserved_at_60[0x20];
e281682b
SM		 4712};
4713
4714enum {
4715 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4716 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4717};
4718
4719struct mlx5_ifc_query_vport_state_out_bits {
4720 u8 status[0x8];
b4ff3a36 4721 u8 reserved_at_8[0x18];
e281682b
SM		 4722
4723 u8 syndrome[0x20];
4724
b4ff3a36 4725 u8 reserved_at_40[0x20];
e281682b 4726
b4ff3a36 4727 u8 reserved_at_60[0x18];
e281682b
SM		 4728 u8 admin_state[0x4];
4729 u8 state[0x4];
4730};
4731
4732enum {
cc9c82a8
EBE		 4733 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4734 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
7d0314b1 4735 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
e281682b
SM		 4736};
4737
fd4572b3
ED		 4738struct mlx5_ifc_arm_monitor_counter_in_bits {
4739 u8 opcode[0x10];
4740 u8 uid[0x10];
4741
4742 u8 reserved_at_20[0x10];
4743 u8 op_mod[0x10];
4744
4745 u8 reserved_at_40[0x20];
4746
4747 u8 reserved_at_60[0x20];
4748};
4749
4750struct mlx5_ifc_arm_monitor_counter_out_bits {
4751 u8 status[0x8];
4752 u8 reserved_at_8[0x18];
4753
4754 u8 syndrome[0x20];
4755
4756 u8 reserved_at_40[0x40];
4757};
4758
4759enum {
4760 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4761 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4762};
4763
4764enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 4765 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4766 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4767 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4768 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4769 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4770 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 4771};
4772
4773enum {
4c8b8518 4774 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 4775};
4776
4777struct mlx5_ifc_monitor_counter_output_bits {
4778 u8 reserved_at_0[0x4];
4779 u8 type[0x4];
4780 u8 reserved_at_8[0x8];
4781 u8 counter[0x10];
4782
4783 u8 counter_group_id[0x20];
4784};
4785
4786#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4787#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4788#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4789 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4790
4791struct mlx5_ifc_set_monitor_counter_in_bits {
4792 u8 opcode[0x10];
4793 u8 uid[0x10];
4794
4795 u8 reserved_at_20[0x10];
4796 u8 op_mod[0x10];
4797
4798 u8 reserved_at_40[0x10];
4799 u8 num_of_counters[0x10];
4800
4801 u8 reserved_at_60[0x20];
4802
4803 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4804};
4805
4806struct mlx5_ifc_set_monitor_counter_out_bits {
4807 u8 status[0x8];
4808 u8 reserved_at_8[0x18];
4809
4810 u8 syndrome[0x20];
4811
4812 u8 reserved_at_40[0x40];
4813};
4814
e281682b
SM		 4815struct mlx5_ifc_query_vport_state_in_bits {
4816 u8 opcode[0x10];
b4ff3a36 4817 u8 reserved_at_10[0x10];
e281682b 4818
b4ff3a36 4819 u8 reserved_at_20[0x10];
e281682b
SM		 4820 u8 op_mod[0x10];
4821
4822 u8 other_vport[0x1];
b4ff3a36 4823 u8 reserved_at_41[0xf];
e281682b
SM		 4824 u8 vport_number[0x10];
4825
b4ff3a36 4826 u8 reserved_at_60[0x20];
e281682b
SM		 4827};
4828
61c5b5c9
MS		 4829struct mlx5_ifc_query_vnic_env_out_bits {
4830 u8 status[0x8];
4831 u8 reserved_at_8[0x18];
4832
4833 u8 syndrome[0x20];
4834
4835 u8 reserved_at_40[0x40];
4836
4837 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4838};
4839
4840enum {
4841 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4842};
4843
4844struct mlx5_ifc_query_vnic_env_in_bits {
4845 u8 opcode[0x10];
4846 u8 reserved_at_10[0x10];
4847
4848 u8 reserved_at_20[0x10];
4849 u8 op_mod[0x10];
4850
4851 u8 other_vport[0x1];
4852 u8 reserved_at_41[0xf];
4853 u8 vport_number[0x10];
4854
4855 u8 reserved_at_60[0x20];
4856};
4857
e281682b
SM		 4858struct mlx5_ifc_query_vport_counter_out_bits {
4859 u8 status[0x8];
b4ff3a36 4860 u8 reserved_at_8[0x18];
e281682b
SM		 4861
4862 u8 syndrome[0x20];
4863
b4ff3a36 4864 u8 reserved_at_40[0x40];
e281682b
SM		 4865
4866 struct mlx5_ifc_traffic_counter_bits received_errors;
4867
4868 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4869
4870 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4871
4872 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4873
4874 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4875
4876 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4877
4878 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4879
4880 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4881
4882 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4883
4884 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4885
4886 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4887
4888 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4889
b4ff3a36 4890 u8 reserved_at_680[0xa00];
e281682b
SM		 4891};
4892
4893enum {
4894 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4895};
4896
4897struct mlx5_ifc_query_vport_counter_in_bits {
4898 u8 opcode[0x10];
b4ff3a36 4899 u8 reserved_at_10[0x10];
e281682b 4900
b4ff3a36 4901 u8 reserved_at_20[0x10];
e281682b
SM		 4902 u8 op_mod[0x10];
4903
4904 u8 other_vport[0x1];
b54ba277
MY		 4905 u8 reserved_at_41[0xb];
4906 u8 port_num[0x4];
e281682b
SM		 4907 u8 vport_number[0x10];
4908
b4ff3a36 4909 u8 reserved_at_60[0x60];
e281682b
SM		 4910
4911 u8 clear[0x1];
b4ff3a36 4912 u8 reserved_at_c1[0x1f];
e281682b 4913
b4ff3a36 4914 u8 reserved_at_e0[0x20];
e281682b
SM		 4915};
4916
4917struct mlx5_ifc_query_tis_out_bits {
4918 u8 status[0x8];
b4ff3a36 4919 u8 reserved_at_8[0x18];
e281682b
SM		 4920
4921 u8 syndrome[0x20];
4922
b4ff3a36 4923 u8 reserved_at_40[0x40];
e281682b
SM		 4924
4925 struct mlx5_ifc_tisc_bits tis_context;
4926};
4927
4928struct mlx5_ifc_query_tis_in_bits {
4929 u8 opcode[0x10];
b4ff3a36 4930 u8 reserved_at_10[0x10];
e281682b 4931
b4ff3a36 4932 u8 reserved_at_20[0x10];
e281682b
SM		 4933 u8 op_mod[0x10];
4934
b4ff3a36 4935 u8 reserved_at_40[0x8];
e281682b
SM		 4936 u8 tisn[0x18];
4937
b4ff3a36 4938 u8 reserved_at_60[0x20];
e281682b
SM		 4939};
4940
4941struct mlx5_ifc_query_tir_out_bits {
4942 u8 status[0x8];
b4ff3a36 4943 u8 reserved_at_8[0x18];
e281682b
SM		 4944
4945 u8 syndrome[0x20];
4946
b4ff3a36 4947 u8 reserved_at_40[0xc0];
e281682b
SM		 4948
4949 struct mlx5_ifc_tirc_bits tir_context;
4950};
4951
4952struct mlx5_ifc_query_tir_in_bits {
4953 u8 opcode[0x10];
b4ff3a36 4954 u8 reserved_at_10[0x10];
e281682b 4955
b4ff3a36 4956 u8 reserved_at_20[0x10];
e281682b
SM		 4957 u8 op_mod[0x10];
4958
b4ff3a36 4959 u8 reserved_at_40[0x8];
e281682b
SM		 4960 u8 tirn[0x18];
4961
b4ff3a36 4962 u8 reserved_at_60[0x20];
e281682b
SM		 4963};
4964
4965struct mlx5_ifc_query_srq_out_bits {
4966 u8 status[0x8];
b4ff3a36 4967 u8 reserved_at_8[0x18];
e281682b
SM		 4968
4969 u8 syndrome[0x20];
4970
b4ff3a36 4971 u8 reserved_at_40[0x40];
e281682b
SM		 4972
4973 struct mlx5_ifc_srqc_bits srq_context_entry;
4974
b4ff3a36 4975 u8 reserved_at_280[0x600];
e281682b 4976
b6ca09cb 4977 u8 pas[][0x40];
e281682b
SM		 4978};
4979
4980struct mlx5_ifc_query_srq_in_bits {
4981 u8 opcode[0x10];
b4ff3a36 4982 u8 reserved_at_10[0x10];
e281682b 4983
b4ff3a36 4984 u8 reserved_at_20[0x10];
e281682b
SM		 4985 u8 op_mod[0x10];
4986
b4ff3a36 4987 u8 reserved_at_40[0x8];
e281682b
SM		 4988 u8 srqn[0x18];
4989
b4ff3a36 4990 u8 reserved_at_60[0x20];
e281682b
SM		 4991};
4992
4993struct mlx5_ifc_query_sq_out_bits {
4994 u8 status[0x8];
b4ff3a36 4995 u8 reserved_at_8[0x18];
e281682b
SM		 4996
4997 u8 syndrome[0x20];
4998
b4ff3a36 4999 u8 reserved_at_40[0xc0];
e281682b
SM		 5000
5001 struct mlx5_ifc_sqc_bits sq_context;
5002};
5003
5004struct mlx5_ifc_query_sq_in_bits {
5005 u8 opcode[0x10];
b4ff3a36 5006 u8 reserved_at_10[0x10];
e281682b 5007
b4ff3a36 5008 u8 reserved_at_20[0x10];
e281682b
SM		 5009 u8 op_mod[0x10];
5010
b4ff3a36 5011 u8 reserved_at_40[0x8];
e281682b
SM		 5012 u8 sqn[0x18];
5013
b4ff3a36 5014 u8 reserved_at_60[0x20];
e281682b
SM		 5015};
5016
5017struct mlx5_ifc_query_special_contexts_out_bits {
5018 u8 status[0x8];
b4ff3a36 5019 u8 reserved_at_8[0x18];
e281682b
SM		 5020
5021 u8 syndrome[0x20];
5022
ec22eb53 5023 u8 dump_fill_mkey[0x20];
e281682b
SM		 5024
5025 u8 resd_lkey[0x20];
bcda1aca
AK		 5026
5027 u8 null_mkey[0x20];
5028
5029 u8 reserved_at_a0[0x60];
e281682b
SM		 5030};
5031
5032struct mlx5_ifc_query_special_contexts_in_bits {
5033 u8 opcode[0x10];
b4ff3a36 5034 u8 reserved_at_10[0x10];
e281682b 5035
b4ff3a36 5036 u8 reserved_at_20[0x10];
e281682b
SM		 5037 u8 op_mod[0x10];
5038
b4ff3a36 5039 u8 reserved_at_40[0x40];
e281682b
SM		 5040};
5041
813f8540
MHY		 5042struct mlx5_ifc_query_scheduling_element_out_bits {
5043 u8 opcode[0x10];
5044 u8 reserved_at_10[0x10];
5045
5046 u8 reserved_at_20[0x10];
5047 u8 op_mod[0x10];
5048
5049 u8 reserved_at_40[0xc0];
5050
5051 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5052
5053 u8 reserved_at_300[0x100];
5054};
5055
5056enum {
5057 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
214baf22 5058 SCHEDULING_HIERARCHY_NIC = 0x3,
813f8540
MHY		 5059};
5060
5061struct mlx5_ifc_query_scheduling_element_in_bits {
5062 u8 opcode[0x10];
5063 u8 reserved_at_10[0x10];
5064
5065 u8 reserved_at_20[0x10];
5066 u8 op_mod[0x10];
5067
5068 u8 scheduling_hierarchy[0x8];
5069 u8 reserved_at_48[0x18];
5070
5071 u8 scheduling_element_id[0x20];
5072
5073 u8 reserved_at_80[0x180];
5074};
5075
e281682b
SM		 5076struct mlx5_ifc_query_rqt_out_bits {
5077 u8 status[0x8];
b4ff3a36 5078 u8 reserved_at_8[0x18];
e281682b
SM		 5079
5080 u8 syndrome[0x20];
5081
b4ff3a36 5082 u8 reserved_at_40[0xc0];
e281682b
SM		 5083
5084 struct mlx5_ifc_rqtc_bits rqt_context;
5085};
5086
5087struct mlx5_ifc_query_rqt_in_bits {
5088 u8 opcode[0x10];
b4ff3a36 5089 u8 reserved_at_10[0x10];
e281682b 5090
b4ff3a36 5091 u8 reserved_at_20[0x10];
e281682b
SM		 5092 u8 op_mod[0x10];
5093
b4ff3a36 5094 u8 reserved_at_40[0x8];
e281682b
SM		 5095 u8 rqtn[0x18];
5096
b4ff3a36 5097 u8 reserved_at_60[0x20];
e281682b
SM		 5098};
5099
5100struct mlx5_ifc_query_rq_out_bits {
5101 u8 status[0x8];
b4ff3a36 5102 u8 reserved_at_8[0x18];
e281682b
SM		 5103
5104 u8 syndrome[0x20];
5105
b4ff3a36 5106 u8 reserved_at_40[0xc0];
e281682b
SM		 5107
5108 struct mlx5_ifc_rqc_bits rq_context;
5109};
5110
5111struct mlx5_ifc_query_rq_in_bits {
5112 u8 opcode[0x10];
b4ff3a36 5113 u8 reserved_at_10[0x10];
e281682b 5114
b4ff3a36 5115 u8 reserved_at_20[0x10];
e281682b
SM		 5116 u8 op_mod[0x10];
5117
b4ff3a36 5118 u8 reserved_at_40[0x8];
e281682b
SM		 5119 u8 rqn[0x18];
5120
b4ff3a36 5121 u8 reserved_at_60[0x20];
e281682b
SM		 5122};
5123
5124struct mlx5_ifc_query_roce_address_out_bits {
5125 u8 status[0x8];
b4ff3a36 5126 u8 reserved_at_8[0x18];
e281682b
SM		 5127
5128 u8 syndrome[0x20];
5129
b4ff3a36 5130 u8 reserved_at_40[0x40];
e281682b
SM		 5131
5132 struct mlx5_ifc_roce_addr_layout_bits roce_address;
5133};
5134
5135struct mlx5_ifc_query_roce_address_in_bits {
5136 u8 opcode[0x10];
b4ff3a36 5137 u8 reserved_at_10[0x10];
e281682b 5138
b4ff3a36 5139 u8 reserved_at_20[0x10];
e281682b
SM		 5140 u8 op_mod[0x10];
5141
5142 u8 roce_address_index[0x10];
32f69e4b
DJ		 5143 u8 reserved_at_50[0xc];
5144 u8 vhca_port_num[0x4];
e281682b 5145
b4ff3a36 5146 u8 reserved_at_60[0x20];
e281682b
SM		 5147};
5148
5149struct mlx5_ifc_query_rmp_out_bits {
5150 u8 status[0x8];
b4ff3a36 5151 u8 reserved_at_8[0x18];
e281682b
SM		 5152
5153 u8 syndrome[0x20];
5154
b4ff3a36 5155 u8 reserved_at_40[0xc0];
e281682b
SM		 5156
5157 struct mlx5_ifc_rmpc_bits rmp_context;
5158};
5159
5160struct mlx5_ifc_query_rmp_in_bits {
5161 u8 opcode[0x10];
b4ff3a36 5162 u8 reserved_at_10[0x10];
e281682b 5163
b4ff3a36 5164 u8 reserved_at_20[0x10];
e281682b
SM		 5165 u8 op_mod[0x10];
5166
b4ff3a36 5167 u8 reserved_at_40[0x8];
e281682b
SM		 5168 u8 rmpn[0x18];
5169
b4ff3a36 5170 u8 reserved_at_60[0x20];
e281682b
SM		 5171};
5172
5173struct mlx5_ifc_query_qp_out_bits {
5174 u8 status[0x8];
b4ff3a36 5175 u8 reserved_at_8[0x18];
e281682b
SM		 5176
5177 u8 syndrome[0x20];
5178
6b646a7e
LR		 5179 u8 reserved_at_40[0x20];
5180 u8 ece[0x20];
e281682b
SM		 5181
5182 u8 opt_param_mask[0x20];
5183
b4ff3a36 5184 u8 reserved_at_a0[0x20];
e281682b
SM		 5185
5186 struct mlx5_ifc_qpc_bits qpc;
5187
b4ff3a36 5188 u8 reserved_at_800[0x80];
e281682b 5189
b6ca09cb 5190 u8 pas[][0x40];
e281682b
SM		 5191};
5192
5193struct mlx5_ifc_query_qp_in_bits {
5194 u8 opcode[0x10];
b4ff3a36 5195 u8 reserved_at_10[0x10];
e281682b 5196
b4ff3a36 5197 u8 reserved_at_20[0x10];
e281682b
SM		 5198 u8 op_mod[0x10];
5199
b4ff3a36 5200 u8 reserved_at_40[0x8];
e281682b
SM		 5201 u8 qpn[0x18];
5202
b4ff3a36 5203 u8 reserved_at_60[0x20];
e281682b
SM		 5204};
5205
5206struct mlx5_ifc_query_q_counter_out_bits {
5207 u8 status[0x8];
b4ff3a36 5208 u8 reserved_at_8[0x18];
e281682b
SM		 5209
5210 u8 syndrome[0x20];
5211
b4ff3a36 5212 u8 reserved_at_40[0x40];
e281682b
SM		 5213
5214 u8 rx_write_requests[0x20];
5215
b4ff3a36 5216 u8 reserved_at_a0[0x20];
e281682b
SM		 5217
5218 u8 rx_read_requests[0x20];
5219
b4ff3a36 5220 u8 reserved_at_e0[0x20];
e281682b
SM		 5221
5222 u8 rx_atomic_requests[0x20];
5223
b4ff3a36 5224 u8 reserved_at_120[0x20];
e281682b
SM		 5225
5226 u8 rx_dct_connect[0x20];
5227
b4ff3a36 5228 u8 reserved_at_160[0x20];
e281682b
SM		 5229
5230 u8 out_of_buffer[0x20];
5231
b4ff3a36 5232 u8 reserved_at_1a0[0x20];
e281682b
SM		 5233
5234 u8 out_of_sequence[0x20];
5235
7486216b
SM		 5236 u8 reserved_at_1e0[0x20];
5237
5238 u8 duplicate_request[0x20];
5239
5240 u8 reserved_at_220[0x20];
5241
5242 u8 rnr_nak_retry_err[0x20];
5243
5244 u8 reserved_at_260[0x20];
5245
5246 u8 packet_seq_err[0x20];
5247
5248 u8 reserved_at_2a0[0x20];
5249
5250 u8 implied_nak_seq_err[0x20];
5251
5252 u8 reserved_at_2e0[0x20];
5253
5254 u8 local_ack_timeout_err[0x20];
5255
58dcb60a
PP		 5256 u8 reserved_at_320[0xa0];
5257
5258 u8 resp_local_length_error[0x20];
5259
5260 u8 req_local_length_error[0x20];
5261
5262 u8 resp_local_qp_error[0x20];
5263
5264 u8 local_operation_error[0x20];
5265
5266 u8 resp_local_protection[0x20];
5267
5268 u8 req_local_protection[0x20];
5269
5270 u8 resp_cqe_error[0x20];
5271
5272 u8 req_cqe_error[0x20];
5273
5274 u8 req_mw_binding[0x20];
5275
5276 u8 req_bad_response[0x20];
5277
5278 u8 req_remote_invalid_request[0x20];
5279
5280 u8 resp_remote_invalid_request[0x20];
5281
5282 u8 req_remote_access_errors[0x20];
5283
5284 u8 resp_remote_access_errors[0x20];
5285
5286 u8 req_remote_operation_errors[0x20];
5287
5288 u8 req_transport_retries_exceeded[0x20];
5289
5290 u8 cq_overflow[0x20];
5291
5292 u8 resp_cqe_flush_error[0x20];
5293
5294 u8 req_cqe_flush_error[0x20];
5295
8fd5b75d
LR		 5296 u8 reserved_at_620[0x20];
5297
5298 u8 roce_adp_retrans[0x20];
5299
5300 u8 roce_adp_retrans_to[0x20];
5301
5302 u8 roce_slow_restart[0x20];
5303
5304 u8 roce_slow_restart_cnps[0x20];
5305
5306 u8 roce_slow_restart_trans[0x20];
5307
5308 u8 reserved_at_6e0[0x120];
e281682b
SM		 5309};
5310
5311struct mlx5_ifc_query_q_counter_in_bits {
5312 u8 opcode[0x10];
b4ff3a36 5313 u8 reserved_at_10[0x10];
e281682b 5314
b4ff3a36 5315 u8 reserved_at_20[0x10];
e281682b
SM		 5316 u8 op_mod[0x10];
5317
b4ff3a36 5318 u8 reserved_at_40[0x80];
e281682b
SM		 5319
5320 u8 clear[0x1];
b4ff3a36 5321 u8 reserved_at_c1[0x1f];
e281682b 5322
b4ff3a36 5323 u8 reserved_at_e0[0x18];
e281682b
SM		 5324 u8 counter_set_id[0x8];
5325};
5326
5327struct mlx5_ifc_query_pages_out_bits {
5328 u8 status[0x8];
b4ff3a36 5329 u8 reserved_at_8[0x18];
e281682b
SM		 5330
5331 u8 syndrome[0x20];
5332
591905ba
BW		 5333 u8 embedded_cpu_function[0x1];
5334 u8 reserved_at_41[0xf];
e281682b
SM		 5335 u8 function_id[0x10];
5336
5337 u8 num_pages[0x20];
5338};
5339
5340enum {
5341 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5342 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5343 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5344};
5345
5346struct mlx5_ifc_query_pages_in_bits {
5347 u8 opcode[0x10];
b4ff3a36 5348 u8 reserved_at_10[0x10];
e281682b 5349
b4ff3a36 5350 u8 reserved_at_20[0x10];
e281682b
SM		 5351 u8 op_mod[0x10];
5352
591905ba
BW		 5353 u8 embedded_cpu_function[0x1];
5354 u8 reserved_at_41[0xf];
e281682b
SM		 5355 u8 function_id[0x10];
5356
b4ff3a36 5357 u8 reserved_at_60[0x20];
e281682b
SM		 5358};
5359
5360struct mlx5_ifc_query_nic_vport_context_out_bits {
5361 u8 status[0x8];
b4ff3a36 5362 u8 reserved_at_8[0x18];
e281682b
SM		 5363
5364 u8 syndrome[0x20];
5365
b4ff3a36 5366 u8 reserved_at_40[0x40];
e281682b
SM		 5367
5368 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5369};
5370
5371struct mlx5_ifc_query_nic_vport_context_in_bits {
5372 u8 opcode[0x10];
b4ff3a36 5373 u8 reserved_at_10[0x10];
e281682b 5374
b4ff3a36 5375 u8 reserved_at_20[0x10];
e281682b
SM		 5376 u8 op_mod[0x10];
5377
5378 u8 other_vport[0x1];
b4ff3a36 5379 u8 reserved_at_41[0xf];
e281682b
SM		 5380 u8 vport_number[0x10];
5381
b4ff3a36 5382 u8 reserved_at_60[0x5];
e281682b 5383 u8 allowed_list_type[0x3];
b4ff3a36 5384 u8 reserved_at_68[0x18];
e281682b
SM		 5385};
5386
5387struct mlx5_ifc_query_mkey_out_bits {
5388 u8 status[0x8];
b4ff3a36 5389 u8 reserved_at_8[0x18];
e281682b
SM		 5390
5391 u8 syndrome[0x20];
5392
b4ff3a36 5393 u8 reserved_at_40[0x40];
e281682b
SM		 5394
5395 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5396
b4ff3a36 5397 u8 reserved_at_280[0x600];
e281682b
SM		 5398
5399 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5400
5401 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5402};
5403
5404struct mlx5_ifc_query_mkey_in_bits {
5405 u8 opcode[0x10];
b4ff3a36 5406 u8 reserved_at_10[0x10];
e281682b 5407
b4ff3a36 5408 u8 reserved_at_20[0x10];
e281682b
SM		 5409 u8 op_mod[0x10];
5410
b4ff3a36 5411 u8 reserved_at_40[0x8];
e281682b
SM		 5412 u8 mkey_index[0x18];
5413
5414 u8 pg_access[0x1];
b4ff3a36 5415 u8 reserved_at_61[0x1f];
e281682b
SM		 5416};
5417
5418struct mlx5_ifc_query_mad_demux_out_bits {
5419 u8 status[0x8];
b4ff3a36 5420 u8 reserved_at_8[0x18];
e281682b
SM		 5421
5422 u8 syndrome[0x20];
5423
b4ff3a36 5424 u8 reserved_at_40[0x40];
e281682b
SM		 5425
5426 u8 mad_dumux_parameters_block[0x20];
5427};
5428
5429struct mlx5_ifc_query_mad_demux_in_bits {
5430 u8 opcode[0x10];
b4ff3a36 5431 u8 reserved_at_10[0x10];
e281682b 5432
b4ff3a36 5433 u8 reserved_at_20[0x10];
e281682b
SM		 5434 u8 op_mod[0x10];
5435
b4ff3a36 5436 u8 reserved_at_40[0x40];
e281682b
SM		 5437};
5438
5439struct mlx5_ifc_query_l2_table_entry_out_bits {
5440 u8 status[0x8];
b4ff3a36 5441 u8 reserved_at_8[0x18];
e281682b
SM		 5442
5443 u8 syndrome[0x20];
5444
b4ff3a36 5445 u8 reserved_at_40[0xa0];
e281682b 5446
b4ff3a36 5447 u8 reserved_at_e0[0x13];
e281682b
SM		 5448 u8 vlan_valid[0x1];
5449 u8 vlan[0xc];
5450
5451 struct mlx5_ifc_mac_address_layout_bits mac_address;
5452
b4ff3a36 5453 u8 reserved_at_140[0xc0];
e281682b
SM		 5454};
5455
5456struct mlx5_ifc_query_l2_table_entry_in_bits {
5457 u8 opcode[0x10];
b4ff3a36 5458 u8 reserved_at_10[0x10];
e281682b 5459
b4ff3a36 5460 u8 reserved_at_20[0x10];
e281682b
SM		 5461 u8 op_mod[0x10];
5462
b4ff3a36 5463 u8 reserved_at_40[0x60];
e281682b 5464
b4ff3a36 5465 u8 reserved_at_a0[0x8];
e281682b
SM		 5466 u8 table_index[0x18];
5467
b4ff3a36 5468 u8 reserved_at_c0[0x140];
e281682b
SM		 5469};
5470
5471struct mlx5_ifc_query_issi_out_bits {
5472 u8 status[0x8];
b4ff3a36 5473 u8 reserved_at_8[0x18];
e281682b
SM		 5474
5475 u8 syndrome[0x20];
5476
b4ff3a36 5477 u8 reserved_at_40[0x10];
e281682b
SM		 5478 u8 current_issi[0x10];
5479
b4ff3a36 5480 u8 reserved_at_60[0xa0];
e281682b 5481
b4ff3a36 5482 u8 reserved_at_100[76][0x8];
e281682b
SM		 5483 u8 supported_issi_dw0[0x20];
5484};
5485
5486struct mlx5_ifc_query_issi_in_bits {
5487 u8 opcode[0x10];
b4ff3a36 5488 u8 reserved_at_10[0x10];
e281682b 5489
b4ff3a36 5490 u8 reserved_at_20[0x10];
e281682b
SM		 5491 u8 op_mod[0x10];
5492
b4ff3a36 5493 u8 reserved_at_40[0x40];
e281682b
SM		 5494};
5495
0dbc6fe0
SM		 5496struct mlx5_ifc_set_driver_version_out_bits {
5497 u8 status[0x8];
5498 u8 reserved_0[0x18];
5499
5500 u8 syndrome[0x20];
5501 u8 reserved_1[0x40];
5502};
5503
5504struct mlx5_ifc_set_driver_version_in_bits {
5505 u8 opcode[0x10];
5506 u8 reserved_0[0x10];
5507
5508 u8 reserved_1[0x10];
5509 u8 op_mod[0x10];
5510
5511 u8 reserved_2[0x40];
5512 u8 driver_version[64][0x8];
5513};
5514
e281682b
SM		 5515struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5516 u8 status[0x8];
b4ff3a36 5517 u8 reserved_at_8[0x18];
e281682b
SM		 5518
5519 u8 syndrome[0x20];
5520
b4ff3a36 5521 u8 reserved_at_40[0x40];
e281682b 5522
b6ca09cb 5523 struct mlx5_ifc_pkey_bits pkey[];
e281682b
SM		 5524};
5525
5526struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5527 u8 opcode[0x10];
b4ff3a36 5528 u8 reserved_at_10[0x10];
e281682b 5529
b4ff3a36 5530 u8 reserved_at_20[0x10];
e281682b
SM		 5531 u8 op_mod[0x10];
5532
5533 u8 other_vport[0x1];
b4ff3a36 5534 u8 reserved_at_41[0xb];
707c4602 5535 u8 port_num[0x4];
e281682b
SM		 5536 u8 vport_number[0x10];
5537
b4ff3a36 5538 u8 reserved_at_60[0x10];
e281682b
SM		 5539 u8 pkey_index[0x10];
5540};
5541
eff901d3
EC		 5542enum {
5543 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5544 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5545 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5546};
5547
e281682b
SM		 5548struct mlx5_ifc_query_hca_vport_gid_out_bits {
5549 u8 status[0x8];
b4ff3a36 5550 u8 reserved_at_8[0x18];
e281682b
SM		 5551
5552 u8 syndrome[0x20];
5553
b4ff3a36 5554 u8 reserved_at_40[0x20];
e281682b
SM		 5555
5556 u8 gids_num[0x10];
b4ff3a36 5557 u8 reserved_at_70[0x10];
e281682b 5558
b6ca09cb 5559 struct mlx5_ifc_array128_auto_bits gid[];
e281682b
SM		 5560};
5561
5562struct mlx5_ifc_query_hca_vport_gid_in_bits {
5563 u8 opcode[0x10];
b4ff3a36 5564 u8 reserved_at_10[0x10];
e281682b 5565
b4ff3a36 5566 u8 reserved_at_20[0x10];
e281682b
SM		 5567 u8 op_mod[0x10];
5568
5569 u8 other_vport[0x1];
b4ff3a36 5570 u8 reserved_at_41[0xb];
707c4602 5571 u8 port_num[0x4];
e281682b
SM		 5572 u8 vport_number[0x10];
5573
b4ff3a36 5574 u8 reserved_at_60[0x10];
e281682b
SM		 5575 u8 gid_index[0x10];
5576};
5577
5578struct mlx5_ifc_query_hca_vport_context_out_bits {
5579 u8 status[0x8];
b4ff3a36 5580 u8 reserved_at_8[0x18];
e281682b
SM		 5581
5582 u8 syndrome[0x20];
5583
b4ff3a36 5584 u8 reserved_at_40[0x40];
e281682b
SM		 5585
5586 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5587};
5588
5589struct mlx5_ifc_query_hca_vport_context_in_bits {
5590 u8 opcode[0x10];
b4ff3a36 5591 u8 reserved_at_10[0x10];
e281682b 5592
b4ff3a36 5593 u8 reserved_at_20[0x10];
e281682b
SM		 5594 u8 op_mod[0x10];
5595
5596 u8 other_vport[0x1];
b4ff3a36 5597 u8 reserved_at_41[0xb];
707c4602 5598 u8 port_num[0x4];
e281682b
SM		 5599 u8 vport_number[0x10];
5600
b4ff3a36 5601 u8 reserved_at_60[0x20];
e281682b
SM		 5602};
5603
5604struct mlx5_ifc_query_hca_cap_out_bits {
5605 u8 status[0x8];
b4ff3a36 5606 u8 reserved_at_8[0x18];
e281682b
SM		 5607
5608 u8 syndrome[0x20];
5609
b4ff3a36 5610 u8 reserved_at_40[0x40];
e281682b
SM		 5611
5612 union mlx5_ifc_hca_cap_union_bits capability;
5613};
5614
5615struct mlx5_ifc_query_hca_cap_in_bits {
5616 u8 opcode[0x10];
b4ff3a36 5617 u8 reserved_at_10[0x10];
e281682b 5618
b4ff3a36 5619 u8 reserved_at_20[0x10];
e281682b
SM		 5620 u8 op_mod[0x10];
5621
97b5484e
AV		 5622 u8 other_function[0x1];
5623 u8 reserved_at_41[0xf];
5624 u8 function_id[0x10];
5625
5626 u8 reserved_at_60[0x20];
e281682b
SM		 5627};
5628
97b5484e
AV		 5629struct mlx5_ifc_other_hca_cap_bits {
5630 u8 roce[0x1];
d32d7c52 5631 u8 reserved_at_1[0x27f];
97b5484e
AV		 5632};
5633
5634struct mlx5_ifc_query_other_hca_cap_out_bits {
e281682b 5635 u8 status[0x8];
d32d7c52 5636 u8 reserved_at_8[0x18];
e281682b
SM		 5637
5638 u8 syndrome[0x20];
5639
d32d7c52 5640 u8 reserved_at_40[0x40];
e281682b 5641
97b5484e
AV		 5642 struct mlx5_ifc_other_hca_cap_bits other_capability;
5643};
5644
5645struct mlx5_ifc_query_other_hca_cap_in_bits {
5646 u8 opcode[0x10];
d32d7c52 5647 u8 reserved_at_10[0x10];
97b5484e 5648
d32d7c52 5649 u8 reserved_at_20[0x10];
97b5484e
AV		 5650 u8 op_mod[0x10];
5651
d32d7c52 5652 u8 reserved_at_40[0x10];
97b5484e
AV		 5653 u8 function_id[0x10];
5654
d32d7c52 5655 u8 reserved_at_60[0x20];
97b5484e
AV		 5656};
5657
5658struct mlx5_ifc_modify_other_hca_cap_out_bits {
5659 u8 status[0x8];
d32d7c52 5660 u8 reserved_at_8[0x18];
97b5484e
AV		 5661
5662 u8 syndrome[0x20];
5663
d32d7c52 5664 u8 reserved_at_40[0x40];
97b5484e
AV		 5665};
5666
5667struct mlx5_ifc_modify_other_hca_cap_in_bits {
5668 u8 opcode[0x10];
d32d7c52 5669 u8 reserved_at_10[0x10];
97b5484e 5670
d32d7c52 5671 u8 reserved_at_20[0x10];
97b5484e
AV		 5672 u8 op_mod[0x10];
5673
d32d7c52 5674 u8 reserved_at_40[0x10];
97b5484e
AV		 5675 u8 function_id[0x10];
5676 u8 field_select[0x20];
5677
5678 struct mlx5_ifc_other_hca_cap_bits other_capability;
5679};
5680
5681struct mlx5_ifc_flow_table_context_bits {
5682 u8 reformat_en[0x1];
5683 u8 decap_en[0x1];
5684 u8 sw_owner[0x1];
5685 u8 termination_table[0x1];
5686 u8 table_miss_action[0x4];
e281682b 5687 u8 level[0x8];
97b5484e 5688 u8 reserved_at_10[0x8];
e281682b
SM		 5689 u8 log_size[0x8];
5690
97b5484e
AV		 5691 u8 reserved_at_20[0x8];
5692 u8 table_miss_id[0x18];
5693
5694 u8 reserved_at_40[0x8];
5695 u8 lag_master_next_table_id[0x18];
5696
5697 u8 reserved_at_60[0x60];
5698
5699 u8 sw_owner_icm_root_1[0x40];
5700
5701 u8 sw_owner_icm_root_0[0x40];
5702
5703};
5704
5705struct mlx5_ifc_query_flow_table_out_bits {
5706 u8 status[0x8];
5707 u8 reserved_at_8[0x18];
5708
5709 u8 syndrome[0x20];
5710
5711 u8 reserved_at_40[0x80];
5712
5713 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 5714};
5715
5716struct mlx5_ifc_query_flow_table_in_bits {
5717 u8 opcode[0x10];
b4ff3a36 5718 u8 reserved_at_10[0x10];
e281682b 5719
b4ff3a36 5720 u8 reserved_at_20[0x10];
e281682b
SM		 5721 u8 op_mod[0x10];
5722
b4ff3a36 5723 u8 reserved_at_40[0x40];
e281682b
SM		 5724
5725 u8 table_type[0x8];
b4ff3a36 5726 u8 reserved_at_88[0x18];
e281682b 5727
b4ff3a36 5728 u8 reserved_at_a0[0x8];
e281682b
SM		 5729 u8 table_id[0x18];
5730
b4ff3a36 5731 u8 reserved_at_c0[0x140];
e281682b
SM		 5732};
5733
5734struct mlx5_ifc_query_fte_out_bits {
5735 u8 status[0x8];
b4ff3a36 5736 u8 reserved_at_8[0x18];
e281682b
SM		 5737
5738 u8 syndrome[0x20];
5739
b4ff3a36 5740 u8 reserved_at_40[0x1c0];
e281682b
SM		 5741
5742 struct mlx5_ifc_flow_context_bits flow_context;
5743};
5744
5745struct mlx5_ifc_query_fte_in_bits {
5746 u8 opcode[0x10];
b4ff3a36 5747 u8 reserved_at_10[0x10];
e281682b 5748
b4ff3a36 5749 u8 reserved_at_20[0x10];
e281682b
SM		 5750 u8 op_mod[0x10];
5751
b4ff3a36 5752 u8 reserved_at_40[0x40];
e281682b
SM		 5753
5754 u8 table_type[0x8];
b4ff3a36 5755 u8 reserved_at_88[0x18];
e281682b 5756
b4ff3a36 5757 u8 reserved_at_a0[0x8];
e281682b
SM		 5758 u8 table_id[0x18];
5759
b4ff3a36 5760 u8 reserved_at_c0[0x40];
e281682b
SM		 5761
5762 u8 flow_index[0x20];
5763
b4ff3a36 5764 u8 reserved_at_120[0xe0];
e281682b
SM		 5765};
5766
e7e2519e
MG		 5767struct mlx5_ifc_match_definer_format_0_bits {
5768 u8 reserved_at_0[0x100];
5769
5770 u8 metadata_reg_c_0[0x20];
5771
5772 u8 metadata_reg_c_1[0x20];
5773
5774 u8 outer_dmac_47_16[0x20];
5775
5776 u8 outer_dmac_15_0[0x10];
5777 u8 outer_ethertype[0x10];
5778
5779 u8 reserved_at_180[0x1];
5780 u8 sx_sniffer[0x1];
5781 u8 functional_lb[0x1];
5782 u8 outer_ip_frag[0x1];
5783 u8 outer_qp_type[0x2];
5784 u8 outer_encap_type[0x2];
5785 u8 port_number[0x2];
5786 u8 outer_l3_type[0x2];
5787 u8 outer_l4_type[0x2];
5788 u8 outer_first_vlan_type[0x2];
5789 u8 outer_first_vlan_prio[0x3];
5790 u8 outer_first_vlan_cfi[0x1];
5791 u8 outer_first_vlan_vid[0xc];
5792
5793 u8 outer_l4_type_ext[0x4];
5794 u8 reserved_at_1a4[0x2];
5795 u8 outer_ipsec_layer[0x2];
5796 u8 outer_l2_type[0x2];
5797 u8 force_lb[0x1];
5798 u8 outer_l2_ok[0x1];
5799 u8 outer_l3_ok[0x1];
5800 u8 outer_l4_ok[0x1];
5801 u8 outer_second_vlan_type[0x2];
5802 u8 outer_second_vlan_prio[0x3];
5803 u8 outer_second_vlan_cfi[0x1];
5804 u8 outer_second_vlan_vid[0xc];
5805
5806 u8 outer_smac_47_16[0x20];
5807
5808 u8 outer_smac_15_0[0x10];
5809 u8 inner_ipv4_checksum_ok[0x1];
5810 u8 inner_l4_checksum_ok[0x1];
5811 u8 outer_ipv4_checksum_ok[0x1];
5812 u8 outer_l4_checksum_ok[0x1];
5813 u8 inner_l3_ok[0x1];
5814 u8 inner_l4_ok[0x1];
5815 u8 outer_l3_ok_duplicate[0x1];
5816 u8 outer_l4_ok_duplicate[0x1];
5817 u8 outer_tcp_cwr[0x1];
5818 u8 outer_tcp_ece[0x1];
5819 u8 outer_tcp_urg[0x1];
5820 u8 outer_tcp_ack[0x1];
5821 u8 outer_tcp_psh[0x1];
5822 u8 outer_tcp_rst[0x1];
5823 u8 outer_tcp_syn[0x1];
5824 u8 outer_tcp_fin[0x1];
5825};
5826
5827struct mlx5_ifc_match_definer_format_22_bits {
5828 u8 reserved_at_0[0x100];
5829
5830 u8 outer_ip_src_addr[0x20];
5831
5832 u8 outer_ip_dest_addr[0x20];
5833
5834 u8 outer_l4_sport[0x10];
5835 u8 outer_l4_dport[0x10];
5836
5837 u8 reserved_at_160[0x1];
5838 u8 sx_sniffer[0x1];
5839 u8 functional_lb[0x1];
5840 u8 outer_ip_frag[0x1];
5841 u8 outer_qp_type[0x2];
5842 u8 outer_encap_type[0x2];
5843 u8 port_number[0x2];
5844 u8 outer_l3_type[0x2];
5845 u8 outer_l4_type[0x2];
5846 u8 outer_first_vlan_type[0x2];
5847 u8 outer_first_vlan_prio[0x3];
5848 u8 outer_first_vlan_cfi[0x1];
5849 u8 outer_first_vlan_vid[0xc];
5850
5851 u8 metadata_reg_c_0[0x20];
5852
5853 u8 outer_dmac_47_16[0x20];
5854
5855 u8 outer_smac_47_16[0x20];
5856
5857 u8 outer_smac_15_0[0x10];
5858 u8 outer_dmac_15_0[0x10];
5859};
5860
5861struct mlx5_ifc_match_definer_format_23_bits {
5862 u8 reserved_at_0[0x100];
5863
5864 u8 inner_ip_src_addr[0x20];
5865
5866 u8 inner_ip_dest_addr[0x20];
5867
5868 u8 inner_l4_sport[0x10];
5869 u8 inner_l4_dport[0x10];
5870
5871 u8 reserved_at_160[0x1];
5872 u8 sx_sniffer[0x1];
5873 u8 functional_lb[0x1];
5874 u8 inner_ip_frag[0x1];
5875 u8 inner_qp_type[0x2];
5876 u8 inner_encap_type[0x2];
5877 u8 port_number[0x2];
5878 u8 inner_l3_type[0x2];
5879 u8 inner_l4_type[0x2];
5880 u8 inner_first_vlan_type[0x2];
5881 u8 inner_first_vlan_prio[0x3];
5882 u8 inner_first_vlan_cfi[0x1];
5883 u8 inner_first_vlan_vid[0xc];
5884
5885 u8 tunnel_header_0[0x20];
5886
5887 u8 inner_dmac_47_16[0x20];
5888
5889 u8 inner_smac_47_16[0x20];
5890
5891 u8 inner_smac_15_0[0x10];
5892 u8 inner_dmac_15_0[0x10];
5893};
5894
5895struct mlx5_ifc_match_definer_format_29_bits {
5896 u8 reserved_at_0[0xc0];
5897
5898 u8 outer_ip_dest_addr[0x80];
5899
5900 u8 outer_ip_src_addr[0x80];
5901
5902 u8 outer_l4_sport[0x10];
5903 u8 outer_l4_dport[0x10];
5904
5905 u8 reserved_at_1e0[0x20];
5906};
5907
5908struct mlx5_ifc_match_definer_format_30_bits {
5909 u8 reserved_at_0[0xa0];
5910
5911 u8 outer_ip_dest_addr[0x80];
5912
5913 u8 outer_ip_src_addr[0x80];
5914
5915 u8 outer_dmac_47_16[0x20];
5916
5917 u8 outer_smac_47_16[0x20];
5918
5919 u8 outer_smac_15_0[0x10];
5920 u8 outer_dmac_15_0[0x10];
5921};
5922
5923struct mlx5_ifc_match_definer_format_31_bits {
5924 u8 reserved_at_0[0xc0];
5925
5926 u8 inner_ip_dest_addr[0x80];
5927
5928 u8 inner_ip_src_addr[0x80];
5929
5930 u8 inner_l4_sport[0x10];
5931 u8 inner_l4_dport[0x10];
5932
5933 u8 reserved_at_1e0[0x20];
5934};
5935
5936struct mlx5_ifc_match_definer_format_32_bits {
5937 u8 reserved_at_0[0xa0];
5938
5939 u8 inner_ip_dest_addr[0x80];
5940
5941 u8 inner_ip_src_addr[0x80];
5942
5943 u8 inner_dmac_47_16[0x20];
5944
5945 u8 inner_smac_47_16[0x20];
5946
5947 u8 inner_smac_15_0[0x10];
5948 u8 inner_dmac_15_0[0x10];
5949};
5950
5951struct mlx5_ifc_match_definer_bits {
5952 u8 modify_field_select[0x40];
5953
5954 u8 reserved_at_40[0x40];
5955
5956 u8 reserved_at_80[0x10];
5957 u8 format_id[0x10];
5958
5959 u8 reserved_at_a0[0x160];
5960
5961 u8 match_mask[16][0x20];
5962};
5963
5964struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
5965 u8 opcode[0x10];
5966 u8 uid[0x10];
5967
5968 u8 vhca_tunnel_id[0x10];
5969 u8 obj_type[0x10];
5970
5971 u8 obj_id[0x20];
5972
5973 u8 reserved_at_60[0x20];
5974};
5975
5976struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
5977 u8 status[0x8];
5978 u8 reserved_at_8[0x18];
5979
5980 u8 syndrome[0x20];
5981
5982 u8 obj_id[0x20];
5983
5984 u8 reserved_at_60[0x20];
5985};
5986
5987struct mlx5_ifc_create_match_definer_in_bits {
5988 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
5989
5990 struct mlx5_ifc_match_definer_bits obj_context;
5991};
5992
5993struct mlx5_ifc_create_match_definer_out_bits {
5994 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
5995};
5996
e281682b
SM		 5997enum {
5998 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5999 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6000 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 6001 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
b169e64a 6002 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
7da3ad6c 6003 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
0f2a6c3b 6004 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
e281682b
SM		 6005};
6006
6007struct mlx5_ifc_query_flow_group_out_bits {
6008 u8 status[0x8];
b4ff3a36 6009 u8 reserved_at_8[0x18];
e281682b
SM		 6010
6011 u8 syndrome[0x20];
6012
b4ff3a36 6013 u8 reserved_at_40[0xa0];
e281682b
SM		 6014
6015 u8 start_flow_index[0x20];
6016
b4ff3a36 6017 u8 reserved_at_100[0x20];
e281682b
SM		 6018
6019 u8 end_flow_index[0x20];
6020
b4ff3a36 6021 u8 reserved_at_140[0xa0];
e281682b 6022
b4ff3a36 6023 u8 reserved_at_1e0[0x18];
e281682b
SM		 6024 u8 match_criteria_enable[0x8];
6025
6026 struct mlx5_ifc_fte_match_param_bits match_criteria;
6027
b4ff3a36 6028 u8 reserved_at_1200[0xe00];
e281682b
SM		 6029};
6030
6031struct mlx5_ifc_query_flow_group_in_bits {
6032 u8 opcode[0x10];
b4ff3a36 6033 u8 reserved_at_10[0x10];
e281682b 6034
b4ff3a36 6035 u8 reserved_at_20[0x10];
e281682b
SM		 6036 u8 op_mod[0x10];
6037
b4ff3a36 6038 u8 reserved_at_40[0x40];
e281682b
SM		 6039
6040 u8 table_type[0x8];
b4ff3a36 6041 u8 reserved_at_88[0x18];
e281682b 6042
b4ff3a36 6043 u8 reserved_at_a0[0x8];
e281682b
SM		 6044 u8 table_id[0x18];
6045
6046 u8 group_id[0x20];
6047
b4ff3a36 6048 u8 reserved_at_e0[0x120];
e281682b
SM		 6049};
6050
9dc0b289
AV		 6051struct mlx5_ifc_query_flow_counter_out_bits {
6052 u8 status[0x8];
6053 u8 reserved_at_8[0x18];
6054
6055 u8 syndrome[0x20];
6056
6057 u8 reserved_at_40[0x40];
6058
b6ca09cb 6059 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
9dc0b289
AV		 6060};
6061
6062struct mlx5_ifc_query_flow_counter_in_bits {
6063 u8 opcode[0x10];
6064 u8 reserved_at_10[0x10];
6065
6066 u8 reserved_at_20[0x10];
6067 u8 op_mod[0x10];
6068
6069 u8 reserved_at_40[0x80];
6070
6071 u8 clear[0x1];
6072 u8 reserved_at_c1[0xf];
6073 u8 num_of_counters[0x10];
6074
a8ffcc74 6075 u8 flow_counter_id[0x20];
9dc0b289
AV		 6076};
6077
d6666753
SM		 6078struct mlx5_ifc_query_esw_vport_context_out_bits {
6079 u8 status[0x8];
b4ff3a36 6080 u8 reserved_at_8[0x18];
d6666753
SM		 6081
6082 u8 syndrome[0x20];
6083
b4ff3a36 6084 u8 reserved_at_40[0x40];
d6666753
SM		 6085
6086 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6087};
6088
6089struct mlx5_ifc_query_esw_vport_context_in_bits {
6090 u8 opcode[0x10];
b4ff3a36 6091 u8 reserved_at_10[0x10];
d6666753 6092
b4ff3a36 6093 u8 reserved_at_20[0x10];
d6666753
SM		 6094 u8 op_mod[0x10];
6095
6096 u8 other_vport[0x1];
b4ff3a36 6097 u8 reserved_at_41[0xf];
d6666753
SM		 6098 u8 vport_number[0x10];
6099
b4ff3a36 6100 u8 reserved_at_60[0x20];
d6666753
SM		 6101};
6102
6103struct mlx5_ifc_modify_esw_vport_context_out_bits {
6104 u8 status[0x8];
b4ff3a36 6105 u8 reserved_at_8[0x18];
d6666753
SM		 6106
6107 u8 syndrome[0x20];
6108
b4ff3a36 6109 u8 reserved_at_40[0x40];
d6666753
SM		 6110};
6111
6112struct mlx5_ifc_esw_vport_context_fields_select_bits {
65c0f2c1
JL		 6113 u8 reserved_at_0[0x1b];
6114 u8 fdb_to_vport_reg_c_id[0x1];
d6666753
SM		 6115 u8 vport_cvlan_insert[0x1];
6116 u8 vport_svlan_insert[0x1];
6117 u8 vport_cvlan_strip[0x1];
6118 u8 vport_svlan_strip[0x1];
6119};
6120
6121struct mlx5_ifc_modify_esw_vport_context_in_bits {
6122 u8 opcode[0x10];
b4ff3a36 6123 u8 reserved_at_10[0x10];
d6666753 6124
b4ff3a36 6125 u8 reserved_at_20[0x10];
d6666753
SM		 6126 u8 op_mod[0x10];
6127
6128 u8 other_vport[0x1];
b4ff3a36 6129 u8 reserved_at_41[0xf];
d6666753
SM		 6130 u8 vport_number[0x10];
6131
6132 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6133
6134 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6135};
6136
e281682b
SM		 6137struct mlx5_ifc_query_eq_out_bits {
6138 u8 status[0x8];
b4ff3a36 6139 u8 reserved_at_8[0x18];
e281682b
SM		 6140
6141 u8 syndrome[0x20];
6142
b4ff3a36 6143 u8 reserved_at_40[0x40];
e281682b
SM		 6144
6145 struct mlx5_ifc_eqc_bits eq_context_entry;
6146
b4ff3a36 6147 u8 reserved_at_280[0x40];
e281682b
SM		 6148
6149 u8 event_bitmask[0x40];
6150
b4ff3a36 6151 u8 reserved_at_300[0x580];
e281682b 6152
b6ca09cb 6153 u8 pas[][0x40];
e281682b
SM		 6154};
6155
6156struct mlx5_ifc_query_eq_in_bits {
6157 u8 opcode[0x10];
b4ff3a36 6158 u8 reserved_at_10[0x10];
e281682b 6159
b4ff3a36 6160 u8 reserved_at_20[0x10];
e281682b
SM		 6161 u8 op_mod[0x10];
6162
b4ff3a36 6163 u8 reserved_at_40[0x18];
e281682b
SM		 6164 u8 eq_number[0x8];
6165
b4ff3a36 6166 u8 reserved_at_60[0x20];
e281682b
SM		 6167};
6168
60786f09 6169struct mlx5_ifc_packet_reformat_context_in_bits {
67133eaa
YK		 6170 u8 reformat_type[0x8];
6171 u8 reserved_at_8[0x4];
6172 u8 reformat_param_0[0x4];
6173 u8 reserved_at_10[0x6];
60786f09 6174 u8 reformat_data_size[0xa];
7adbde20 6175
67133eaa
YK		 6176 u8 reformat_param_1[0x8];
6177 u8 reserved_at_28[0x8];
60786f09 6178 u8 reformat_data[2][0x8];
7adbde20 6179
b6ca09cb 6180 u8 more_reformat_data[][0x8];
7adbde20
HHZ		 6181};
6182
60786f09 6183struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 6184 u8 status[0x8];
6185 u8 reserved_at_8[0x18];
6186
6187 u8 syndrome[0x20];
6188
6189 u8 reserved_at_40[0xa0];
6190
b6ca09cb 6191 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7adbde20
HHZ		 6192};
6193
60786f09 6194struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 6195 u8 opcode[0x10];
6196 u8 reserved_at_10[0x10];
6197
6198 u8 reserved_at_20[0x10];
6199 u8 op_mod[0x10];
6200
60786f09 6201 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6202
6203 u8 reserved_at_60[0xa0];
6204};
6205
60786f09 6206struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 6207 u8 status[0x8];
6208 u8 reserved_at_8[0x18];
6209
6210 u8 syndrome[0x20];
6211
60786f09 6212 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6213
6214 u8 reserved_at_60[0x20];
6215};
6216
67133eaa
YK		 6217enum {
6218 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6219 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6220 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6221};
6222
97b5484e 6223enum mlx5_reformat_ctx_type {
60786f09
MB		 6224 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6225 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 6226 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6227 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6228 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
67133eaa
YK		 6229 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6230 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
e0e7a386
MB		 6231};
6232
60786f09 6233struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 6234 u8 opcode[0x10];
6235 u8 reserved_at_10[0x10];
6236
6237 u8 reserved_at_20[0x10];
6238 u8 op_mod[0x10];
6239
6240 u8 reserved_at_40[0xa0];
6241
60786f09 6242 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 6243};
6244
60786f09 6245struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 6246 u8 status[0x8];
6247 u8 reserved_at_8[0x18];
6248
6249 u8 syndrome[0x20];
6250
6251 u8 reserved_at_40[0x40];
6252};
6253
60786f09 6254struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 6255 u8 opcode[0x10];
6256 u8 reserved_at_10[0x10];
6257
6258 u8 reserved_20[0x10];
6259 u8 op_mod[0x10];
6260
60786f09 6261 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6262
6263 u8 reserved_60[0x20];
6264};
6265
2a69cb9f
OG		 6266struct mlx5_ifc_set_action_in_bits {
6267 u8 action_type[0x4];
6268 u8 field[0xc];
6269 u8 reserved_at_10[0x3];
6270 u8 offset[0x5];
6271 u8 reserved_at_18[0x3];
6272 u8 length[0x5];
6273
6274 u8 data[0x20];
6275};
6276
6277struct mlx5_ifc_add_action_in_bits {
6278 u8 action_type[0x4];
6279 u8 field[0xc];
6280 u8 reserved_at_10[0x10];
6281
6282 u8 data[0x20];
6283};
6284
31d8bde1
HI		 6285struct mlx5_ifc_copy_action_in_bits {
6286 u8 action_type[0x4];
6287 u8 src_field[0xc];
6288 u8 reserved_at_10[0x3];
6289 u8 src_offset[0x5];
6290 u8 reserved_at_18[0x3];
6291 u8 length[0x5];
6292
6293 u8 reserved_at_20[0x4];
6294 u8 dst_field[0xc];
6295 u8 reserved_at_30[0x3];
6296 u8 dst_offset[0x5];
6297 u8 reserved_at_38[0x8];
6298};
6299
d65dbedf
HN		 6300union mlx5_ifc_set_add_copy_action_in_auto_bits {
6301 struct mlx5_ifc_set_action_in_bits set_action_in;
6302 struct mlx5_ifc_add_action_in_bits add_action_in;
822e114b 6303 struct mlx5_ifc_copy_action_in_bits copy_action_in;
2a69cb9f
OG		 6304 u8 reserved_at_0[0x40];
6305};
6306
6307enum {
6308 MLX5_ACTION_TYPE_SET = 0x1,
6309 MLX5_ACTION_TYPE_ADD = 0x2,
31d8bde1 6310 MLX5_ACTION_TYPE_COPY = 0x3,
2a69cb9f
OG		 6311};
6312
6313enum {
6314 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6315 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6316 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6317 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6318 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6319 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6320 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6321 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6322 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6323 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6324 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6325 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6326 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6327 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6328 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6329 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6330 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6331 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6332 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6333 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6334 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6335 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0eb69bb9 6336 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
0c0316f5 6337 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
97b5484e
AV		 6338 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6339 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
65c0f2c1 6340 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
97b5484e
AV		 6341 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6342 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6343 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6344 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6345 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
822e114b
PB		 6346 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6347 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
97b5484e
AV		 6348 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6349 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
78fb6122 6350 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
67133eaa
YK		 6351 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6352 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
2a69cb9f
OG		 6353};
6354
6355struct mlx5_ifc_alloc_modify_header_context_out_bits {
6356 u8 status[0x8];
6357 u8 reserved_at_8[0x18];
6358
6359 u8 syndrome[0x20];
6360
6361 u8 modify_header_id[0x20];
6362
6363 u8 reserved_at_60[0x20];
6364};
6365
6366struct mlx5_ifc_alloc_modify_header_context_in_bits {
6367 u8 opcode[0x10];
6368 u8 reserved_at_10[0x10];
6369
6370 u8 reserved_at_20[0x10];
6371 u8 op_mod[0x10];
6372
6373 u8 reserved_at_40[0x20];
6374
6375 u8 table_type[0x8];
6376 u8 reserved_at_68[0x10];
6377 u8 num_of_actions[0x8];
6378
29056207 6379 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
2a69cb9f
OG		 6380};
6381
6382struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6383 u8 status[0x8];
6384 u8 reserved_at_8[0x18];
6385
6386 u8 syndrome[0x20];
6387
6388 u8 reserved_at_40[0x40];
6389};
6390
6391struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6392 u8 opcode[0x10];
6393 u8 reserved_at_10[0x10];
6394
6395 u8 reserved_at_20[0x10];
6396 u8 op_mod[0x10];
6397
6398 u8 modify_header_id[0x20];
6399
6400 u8 reserved_at_60[0x20];
6401};
6402
ab0da5a5
YH		 6403struct mlx5_ifc_query_modify_header_context_in_bits {
6404 u8 opcode[0x10];
6405 u8 uid[0x10];
6406
6407 u8 reserved_at_20[0x10];
6408 u8 op_mod[0x10];
6409
6410 u8 modify_header_id[0x20];
6411
6412 u8 reserved_at_60[0xa0];
6413};
6414
e281682b
SM		 6415struct mlx5_ifc_query_dct_out_bits {
6416 u8 status[0x8];
b4ff3a36 6417 u8 reserved_at_8[0x18];
e281682b
SM		 6418
6419 u8 syndrome[0x20];
6420
b4ff3a36 6421 u8 reserved_at_40[0x40];
e281682b
SM		 6422
6423 struct mlx5_ifc_dctc_bits dct_context_entry;
6424
b4ff3a36 6425 u8 reserved_at_280[0x180];
e281682b
SM		 6426};
6427
6428struct mlx5_ifc_query_dct_in_bits {
6429 u8 opcode[0x10];
b4ff3a36 6430 u8 reserved_at_10[0x10];
e281682b 6431
b4ff3a36 6432 u8 reserved_at_20[0x10];
e281682b
SM		 6433 u8 op_mod[0x10];
6434
b4ff3a36 6435 u8 reserved_at_40[0x8];
e281682b
SM		 6436 u8 dctn[0x18];
6437
b4ff3a36 6438 u8 reserved_at_60[0x20];
e281682b
SM		 6439};
6440
6441struct mlx5_ifc_query_cq_out_bits {
6442 u8 status[0x8];
b4ff3a36 6443 u8 reserved_at_8[0x18];
e281682b
SM		 6444
6445 u8 syndrome[0x20];
6446
b4ff3a36 6447 u8 reserved_at_40[0x40];
e281682b
SM		 6448
6449 struct mlx5_ifc_cqc_bits cq_context;
6450
b4ff3a36 6451 u8 reserved_at_280[0x600];
e281682b 6452
b6ca09cb 6453 u8 pas[][0x40];
e281682b
SM		 6454};
6455
6456struct mlx5_ifc_query_cq_in_bits {
6457 u8 opcode[0x10];
b4ff3a36 6458 u8 reserved_at_10[0x10];
e281682b 6459
b4ff3a36 6460 u8 reserved_at_20[0x10];
e281682b
SM		 6461 u8 op_mod[0x10];
6462
b4ff3a36 6463 u8 reserved_at_40[0x8];
e281682b
SM		 6464 u8 cqn[0x18];
6465
b4ff3a36 6466 u8 reserved_at_60[0x20];
e281682b
SM		 6467};
6468
6469struct mlx5_ifc_query_cong_status_out_bits {
6470 u8 status[0x8];
b4ff3a36 6471 u8 reserved_at_8[0x18];
e281682b
SM		 6472
6473 u8 syndrome[0x20];
6474
b4ff3a36 6475 u8 reserved_at_40[0x20];
e281682b
SM		 6476
6477 u8 enable[0x1];
6478 u8 tag_enable[0x1];
b4ff3a36 6479 u8 reserved_at_62[0x1e];
e281682b
SM		 6480};
6481
6482struct mlx5_ifc_query_cong_status_in_bits {
6483 u8 opcode[0x10];
b4ff3a36 6484 u8 reserved_at_10[0x10];
e281682b 6485
b4ff3a36 6486 u8 reserved_at_20[0x10];
e281682b
SM		 6487 u8 op_mod[0x10];
6488
b4ff3a36 6489 u8 reserved_at_40[0x18];
e281682b
SM		 6490 u8 priority[0x4];
6491 u8 cong_protocol[0x4];
6492
b4ff3a36 6493 u8 reserved_at_60[0x20];
e281682b
SM		 6494};
6495
6496struct mlx5_ifc_query_cong_statistics_out_bits {
6497 u8 status[0x8];
b4ff3a36 6498 u8 reserved_at_8[0x18];
e281682b
SM		 6499
6500 u8 syndrome[0x20];
6501
b4ff3a36 6502 u8 reserved_at_40[0x40];
e281682b 6503
e1f24a79 6504 u8 rp_cur_flows[0x20];
e281682b
SM		 6505
6506 u8 sum_flows[0x20];
6507
e1f24a79 6508 u8 rp_cnp_ignored_high[0x20];
e281682b 6509
e1f24a79 6510 u8 rp_cnp_ignored_low[0x20];
e281682b 6511
e1f24a79 6512 u8 rp_cnp_handled_high[0x20];
e281682b 6513
e1f24a79 6514 u8 rp_cnp_handled_low[0x20];
e281682b 6515
b4ff3a36 6516 u8 reserved_at_140[0x100];
e281682b
SM		 6517
6518 u8 time_stamp_high[0x20];
6519
6520 u8 time_stamp_low[0x20];
6521
6522 u8 accumulators_period[0x20];
6523
e1f24a79 6524 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 6525
e1f24a79 6526 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 6527
e1f24a79 6528 u8 np_cnp_sent_high[0x20];
e281682b 6529
e1f24a79 6530 u8 np_cnp_sent_low[0x20];
e281682b 6531
b4ff3a36 6532 u8 reserved_at_320[0x560];
e281682b
SM		 6533};
6534
6535struct mlx5_ifc_query_cong_statistics_in_bits {
6536 u8 opcode[0x10];
b4ff3a36 6537 u8 reserved_at_10[0x10];
e281682b 6538
b4ff3a36 6539 u8 reserved_at_20[0x10];
e281682b
SM		 6540 u8 op_mod[0x10];
6541
6542 u8 clear[0x1];
b4ff3a36 6543 u8 reserved_at_41[0x1f];
e281682b 6544
b4ff3a36 6545 u8 reserved_at_60[0x20];
e281682b
SM		 6546};
6547
6548struct mlx5_ifc_query_cong_params_out_bits {
6549 u8 status[0x8];
b4ff3a36 6550 u8 reserved_at_8[0x18];
e281682b
SM		 6551
6552 u8 syndrome[0x20];
6553
b4ff3a36 6554 u8 reserved_at_40[0x40];
e281682b
SM		 6555
6556 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6557};
6558
6559struct mlx5_ifc_query_cong_params_in_bits {
6560 u8 opcode[0x10];
b4ff3a36 6561 u8 reserved_at_10[0x10];
e281682b 6562
b4ff3a36 6563 u8 reserved_at_20[0x10];
e281682b
SM		 6564 u8 op_mod[0x10];
6565
b4ff3a36 6566 u8 reserved_at_40[0x1c];
e281682b
SM		 6567 u8 cong_protocol[0x4];
6568
b4ff3a36 6569 u8 reserved_at_60[0x20];
e281682b
SM		 6570};
6571
6572struct mlx5_ifc_query_adapter_out_bits {
6573 u8 status[0x8];
b4ff3a36 6574 u8 reserved_at_8[0x18];
e281682b
SM		 6575
6576 u8 syndrome[0x20];
6577
b4ff3a36 6578 u8 reserved_at_40[0x40];
e281682b
SM		 6579
6580 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6581};
6582
6583struct mlx5_ifc_query_adapter_in_bits {
6584 u8 opcode[0x10];
b4ff3a36 6585 u8 reserved_at_10[0x10];
e281682b 6586
b4ff3a36 6587 u8 reserved_at_20[0x10];
e281682b
SM		 6588 u8 op_mod[0x10];
6589
b4ff3a36 6590 u8 reserved_at_40[0x40];
e281682b
SM		 6591};
6592
6593struct mlx5_ifc_qp_2rst_out_bits {
6594 u8 status[0x8];
b4ff3a36 6595 u8 reserved_at_8[0x18];
e281682b
SM		 6596
6597 u8 syndrome[0x20];
6598
b4ff3a36 6599 u8 reserved_at_40[0x40];
e281682b
SM		 6600};
6601
6602struct mlx5_ifc_qp_2rst_in_bits {
6603 u8 opcode[0x10];
4ac63ec7 6604 u8 uid[0x10];
e281682b 6605
b4ff3a36 6606 u8 reserved_at_20[0x10];
e281682b
SM		 6607 u8 op_mod[0x10];
6608
b4ff3a36 6609 u8 reserved_at_40[0x8];
e281682b
SM		 6610 u8 qpn[0x18];
6611
b4ff3a36 6612 u8 reserved_at_60[0x20];
e281682b
SM		 6613};
6614
6615struct mlx5_ifc_qp_2err_out_bits {
6616 u8 status[0x8];
b4ff3a36 6617 u8 reserved_at_8[0x18];
e281682b
SM		 6618
6619 u8 syndrome[0x20];
6620
b4ff3a36 6621 u8 reserved_at_40[0x40];
e281682b
SM		 6622};
6623
6624struct mlx5_ifc_qp_2err_in_bits {
6625 u8 opcode[0x10];
4ac63ec7 6626 u8 uid[0x10];
e281682b 6627
b4ff3a36 6628 u8 reserved_at_20[0x10];
e281682b
SM		 6629 u8 op_mod[0x10];
6630
b4ff3a36 6631 u8 reserved_at_40[0x8];
e281682b
SM		 6632 u8 qpn[0x18];
6633
b4ff3a36 6634 u8 reserved_at_60[0x20];
e281682b
SM		 6635};
6636
6637struct mlx5_ifc_page_fault_resume_out_bits {
6638 u8 status[0x8];
b4ff3a36 6639 u8 reserved_at_8[0x18];
e281682b
SM		 6640
6641 u8 syndrome[0x20];
6642
b4ff3a36 6643 u8 reserved_at_40[0x40];
e281682b
SM		 6644};
6645
6646struct mlx5_ifc_page_fault_resume_in_bits {
6647 u8 opcode[0x10];
b4ff3a36 6648 u8 reserved_at_10[0x10];
e281682b 6649
b4ff3a36 6650 u8 reserved_at_20[0x10];
e281682b
SM		 6651 u8 op_mod[0x10];
6652
6653 u8 error[0x1];
b4ff3a36 6654 u8 reserved_at_41[0x4];
223cdc72
AK		 6655 u8 page_fault_type[0x3];
6656 u8 wq_number[0x18];
e281682b 6657
223cdc72
AK		 6658 u8 reserved_at_60[0x8];
6659 u8 token[0x18];
e281682b
SM		 6660};
6661
6662struct mlx5_ifc_nop_out_bits {
6663 u8 status[0x8];
b4ff3a36 6664 u8 reserved_at_8[0x18];
e281682b
SM		 6665
6666 u8 syndrome[0x20];
6667
b4ff3a36 6668 u8 reserved_at_40[0x40];
e281682b
SM		 6669};
6670
6671struct mlx5_ifc_nop_in_bits {
6672 u8 opcode[0x10];
b4ff3a36 6673 u8 reserved_at_10[0x10];
e281682b 6674
b4ff3a36 6675 u8 reserved_at_20[0x10];
e281682b
SM		 6676 u8 op_mod[0x10];
6677
b4ff3a36 6678 u8 reserved_at_40[0x40];
e281682b
SM		 6679};
6680
6681struct mlx5_ifc_modify_vport_state_out_bits {
6682 u8 status[0x8];
b4ff3a36 6683 u8 reserved_at_8[0x18];
e281682b
SM		 6684
6685 u8 syndrome[0x20];
6686
b4ff3a36 6687 u8 reserved_at_40[0x40];
e281682b
SM		 6688};
6689
6690struct mlx5_ifc_modify_vport_state_in_bits {
6691 u8 opcode[0x10];
b4ff3a36 6692 u8 reserved_at_10[0x10];
e281682b 6693
b4ff3a36 6694 u8 reserved_at_20[0x10];
e281682b
SM		 6695 u8 op_mod[0x10];
6696
6697 u8 other_vport[0x1];
b4ff3a36 6698 u8 reserved_at_41[0xf];
e281682b
SM		 6699 u8 vport_number[0x10];
6700
b4ff3a36 6701 u8 reserved_at_60[0x18];
e281682b 6702 u8 admin_state[0x4];
b4ff3a36 6703 u8 reserved_at_7c[0x4];
e281682b
SM		 6704};
6705
6706struct mlx5_ifc_modify_tis_out_bits {
6707 u8 status[0x8];
b4ff3a36 6708 u8 reserved_at_8[0x18];
e281682b
SM		 6709
6710 u8 syndrome[0x20];
6711
b4ff3a36 6712 u8 reserved_at_40[0x40];
e281682b
SM		 6713};
6714
75850d0b 6715struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 6716 u8 reserved_at_0[0x20];
75850d0b 6717
84df61eb
AH		 6718 u8 reserved_at_20[0x1d];
6719 u8 lag_tx_port_affinity[0x1];
6720 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 6721 u8 prio[0x1];
6722};
6723
e281682b
SM		 6724struct mlx5_ifc_modify_tis_in_bits {
6725 u8 opcode[0x10];
bd371975 6726 u8 uid[0x10];
e281682b 6727
b4ff3a36 6728 u8 reserved_at_20[0x10];
e281682b
SM		 6729 u8 op_mod[0x10];
6730
b4ff3a36 6731 u8 reserved_at_40[0x8];
e281682b
SM		 6732 u8 tisn[0x18];
6733
b4ff3a36 6734 u8 reserved_at_60[0x20];
e281682b 6735
75850d0b 6736 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 6737
b4ff3a36 6738 u8 reserved_at_c0[0x40];
e281682b
SM		 6739
6740 struct mlx5_ifc_tisc_bits ctx;
6741};
6742
d9eea403 6743struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 6744 u8 reserved_at_0[0x20];
d9eea403 6745
b4ff3a36 6746 u8 reserved_at_20[0x1b];
66189961 6747 u8 self_lb_en[0x1];
bdfc028d
TT		 6748 u8 reserved_at_3c[0x1];
6749 u8 hash[0x1];
6750 u8 reserved_at_3e[0x1];
eaee12f0 6751 u8 packet_merge[0x1];
d9eea403
AS		 6752};
6753
e281682b
SM		 6754struct mlx5_ifc_modify_tir_out_bits {
6755 u8 status[0x8];
b4ff3a36 6756 u8 reserved_at_8[0x18];
e281682b
SM		 6757
6758 u8 syndrome[0x20];
6759
b4ff3a36 6760 u8 reserved_at_40[0x40];
e281682b
SM		 6761};
6762
6763struct mlx5_ifc_modify_tir_in_bits {
6764 u8 opcode[0x10];
bd371975 6765 u8 uid[0x10];
e281682b 6766
b4ff3a36 6767 u8 reserved_at_20[0x10];
e281682b
SM		 6768 u8 op_mod[0x10];
6769
b4ff3a36 6770 u8 reserved_at_40[0x8];
e281682b
SM		 6771 u8 tirn[0x18];
6772
b4ff3a36 6773 u8 reserved_at_60[0x20];
e281682b 6774
d9eea403 6775 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 6776
b4ff3a36 6777 u8 reserved_at_c0[0x40];
e281682b
SM		 6778
6779 struct mlx5_ifc_tirc_bits ctx;
6780};
6781
6782struct mlx5_ifc_modify_sq_out_bits {
6783 u8 status[0x8];
b4ff3a36 6784 u8 reserved_at_8[0x18];
e281682b
SM		 6785
6786 u8 syndrome[0x20];
6787
b4ff3a36 6788 u8 reserved_at_40[0x40];
e281682b
SM		 6789};
6790
6791struct mlx5_ifc_modify_sq_in_bits {
6792 u8 opcode[0x10];
430ae0d5 6793 u8 uid[0x10];
e281682b 6794
b4ff3a36 6795 u8 reserved_at_20[0x10];
e281682b
SM		 6796 u8 op_mod[0x10];
6797
6798 u8 sq_state[0x4];
b4ff3a36 6799 u8 reserved_at_44[0x4];
e281682b
SM		 6800 u8 sqn[0x18];
6801
b4ff3a36 6802 u8 reserved_at_60[0x20];
e281682b
SM		 6803
6804 u8 modify_bitmask[0x40];
6805
b4ff3a36 6806 u8 reserved_at_c0[0x40];
e281682b
SM		 6807
6808 struct mlx5_ifc_sqc_bits ctx;
6809};
6810
813f8540
MHY		 6811struct mlx5_ifc_modify_scheduling_element_out_bits {
6812 u8 status[0x8];
6813 u8 reserved_at_8[0x18];
6814
6815 u8 syndrome[0x20];
6816
6817 u8 reserved_at_40[0x1c0];
6818};
6819
6820enum {
6821 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6822 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6823};
6824
6825struct mlx5_ifc_modify_scheduling_element_in_bits {
6826 u8 opcode[0x10];
6827 u8 reserved_at_10[0x10];
6828
6829 u8 reserved_at_20[0x10];
6830 u8 op_mod[0x10];
6831
6832 u8 scheduling_hierarchy[0x8];
6833 u8 reserved_at_48[0x18];
6834
6835 u8 scheduling_element_id[0x20];
6836
6837 u8 reserved_at_80[0x20];
6838
6839 u8 modify_bitmask[0x20];
6840
6841 u8 reserved_at_c0[0x40];
6842
6843 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6844
6845 u8 reserved_at_300[0x100];
6846};
6847
e281682b
SM		 6848struct mlx5_ifc_modify_rqt_out_bits {
6849 u8 status[0x8];
b4ff3a36 6850 u8 reserved_at_8[0x18];
e281682b
SM		 6851
6852 u8 syndrome[0x20];
6853
b4ff3a36 6854 u8 reserved_at_40[0x40];
e281682b
SM		 6855};
6856
5c50368f 6857struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 6858 u8 reserved_at_0[0x20];
5c50368f 6859
b4ff3a36 6860 u8 reserved_at_20[0x1f];
5c50368f
AS		 6861 u8 rqn_list[0x1];
6862};
6863
e281682b
SM		 6864struct mlx5_ifc_modify_rqt_in_bits {
6865 u8 opcode[0x10];
bd371975 6866 u8 uid[0x10];
e281682b 6867
b4ff3a36 6868 u8 reserved_at_20[0x10];
e281682b
SM		 6869 u8 op_mod[0x10];
6870
b4ff3a36 6871 u8 reserved_at_40[0x8];
e281682b
SM		 6872 u8 rqtn[0x18];
6873
b4ff3a36 6874 u8 reserved_at_60[0x20];
e281682b 6875
5c50368f 6876 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 6877
b4ff3a36 6878 u8 reserved_at_c0[0x40];
e281682b
SM		 6879
6880 struct mlx5_ifc_rqtc_bits ctx;
6881};
6882
6883struct mlx5_ifc_modify_rq_out_bits {
6884 u8 status[0x8];
b4ff3a36 6885 u8 reserved_at_8[0x18];
e281682b
SM		 6886
6887 u8 syndrome[0x20];
6888
b4ff3a36 6889 u8 reserved_at_40[0x40];
e281682b
SM		 6890};
6891
83b502a1
AV		 6892enum {
6893 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 6894 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 6895 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 6896};
6897
e281682b
SM		 6898struct mlx5_ifc_modify_rq_in_bits {
6899 u8 opcode[0x10];
d269b3af 6900 u8 uid[0x10];
e281682b 6901
b4ff3a36 6902 u8 reserved_at_20[0x10];
e281682b
SM		 6903 u8 op_mod[0x10];
6904
6905 u8 rq_state[0x4];
b4ff3a36 6906 u8 reserved_at_44[0x4];
e281682b
SM		 6907 u8 rqn[0x18];
6908
b4ff3a36 6909 u8 reserved_at_60[0x20];
e281682b
SM		 6910
6911 u8 modify_bitmask[0x40];
6912
b4ff3a36 6913 u8 reserved_at_c0[0x40];
e281682b
SM		 6914
6915 struct mlx5_ifc_rqc_bits ctx;
6916};
6917
6918struct mlx5_ifc_modify_rmp_out_bits {
6919 u8 status[0x8];
b4ff3a36 6920 u8 reserved_at_8[0x18];
e281682b
SM		 6921
6922 u8 syndrome[0x20];
6923
b4ff3a36 6924 u8 reserved_at_40[0x40];
e281682b
SM		 6925};
6926
01949d01 6927struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 6928 u8 reserved_at_0[0x20];
01949d01 6929
b4ff3a36 6930 u8 reserved_at_20[0x1f];
01949d01
HA		 6931 u8 lwm[0x1];
6932};
6933
e281682b
SM		 6934struct mlx5_ifc_modify_rmp_in_bits {
6935 u8 opcode[0x10];
a0d8c054 6936 u8 uid[0x10];
e281682b 6937
b4ff3a36 6938 u8 reserved_at_20[0x10];
e281682b
SM		 6939 u8 op_mod[0x10];
6940
6941 u8 rmp_state[0x4];
b4ff3a36 6942 u8 reserved_at_44[0x4];
e281682b
SM		 6943 u8 rmpn[0x18];
6944
b4ff3a36 6945 u8 reserved_at_60[0x20];
e281682b 6946
01949d01 6947 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 6948
b4ff3a36 6949 u8 reserved_at_c0[0x40];
e281682b
SM		 6950
6951 struct mlx5_ifc_rmpc_bits ctx;
6952};
6953
6954struct mlx5_ifc_modify_nic_vport_context_out_bits {
6955 u8 status[0x8];
b4ff3a36 6956 u8 reserved_at_8[0x18];
e281682b
SM		 6957
6958 u8 syndrome[0x20];
6959
b4ff3a36 6960 u8 reserved_at_40[0x40];
e281682b
SM		 6961};
6962
6963struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 6964 u8 reserved_at_0[0x12];
6965 u8 affiliation[0x1];
c74d90c1 6966 u8 reserved_at_13[0x1];
bded747b
HN		 6967 u8 disable_uc_local_lb[0x1];
6968 u8 disable_mc_local_lb[0x1];
23898c76
NO		 6969 u8 node_guid[0x1];
6970 u8 port_guid[0x1];
9def7121 6971 u8 min_inline[0x1];
d82b7318
SM		 6972 u8 mtu[0x1];
6973 u8 change_event[0x1];
6974 u8 promisc[0x1];
e281682b
SM		 6975 u8 permanent_address[0x1];
6976 u8 addresses_list[0x1];
6977 u8 roce_en[0x1];
b4ff3a36 6978 u8 reserved_at_1f[0x1];
e281682b
SM		 6979};
6980
6981struct mlx5_ifc_modify_nic_vport_context_in_bits {
6982 u8 opcode[0x10];
b4ff3a36 6983 u8 reserved_at_10[0x10];
e281682b 6984
b4ff3a36 6985 u8 reserved_at_20[0x10];
e281682b
SM		 6986 u8 op_mod[0x10];
6987
6988 u8 other_vport[0x1];
b4ff3a36 6989 u8 reserved_at_41[0xf];
e281682b
SM		 6990 u8 vport_number[0x10];
6991
6992 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6993
b4ff3a36 6994 u8 reserved_at_80[0x780];
e281682b
SM		 6995
6996 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6997};
6998
6999struct mlx5_ifc_modify_hca_vport_context_out_bits {
7000 u8 status[0x8];
b4ff3a36 7001 u8 reserved_at_8[0x18];
e281682b
SM		 7002
7003 u8 syndrome[0x20];
7004
b4ff3a36 7005 u8 reserved_at_40[0x40];
e281682b
SM		 7006};
7007
7008struct mlx5_ifc_modify_hca_vport_context_in_bits {
7009 u8 opcode[0x10];
b4ff3a36 7010 u8 reserved_at_10[0x10];
e281682b 7011
b4ff3a36 7012 u8 reserved_at_20[0x10];
e281682b
SM		 7013 u8 op_mod[0x10];
7014
7015 u8 other_vport[0x1];
b4ff3a36 7016 u8 reserved_at_41[0xb];
707c4602 7017 u8 port_num[0x4];
e281682b
SM		 7018 u8 vport_number[0x10];
7019
b4ff3a36 7020 u8 reserved_at_60[0x20];
e281682b
SM		 7021
7022 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7023};
7024
7025struct mlx5_ifc_modify_cq_out_bits {
7026 u8 status[0x8];
b4ff3a36 7027 u8 reserved_at_8[0x18];
e281682b
SM		 7028
7029 u8 syndrome[0x20];
7030
b4ff3a36 7031 u8 reserved_at_40[0x40];
e281682b
SM		 7032};
7033
7034enum {
7035 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7036 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7037};
7038
7039struct mlx5_ifc_modify_cq_in_bits {
7040 u8 opcode[0x10];
9ba481e2 7041 u8 uid[0x10];
e281682b 7042
b4ff3a36 7043 u8 reserved_at_20[0x10];
e281682b
SM		 7044 u8 op_mod[0x10];
7045
b4ff3a36 7046 u8 reserved_at_40[0x8];
e281682b
SM		 7047 u8 cqn[0x18];
7048
7049 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7050
7051 struct mlx5_ifc_cqc_bits cq_context;
7052
7a32f296 7053 u8 reserved_at_280[0x60];
bd371975
LR		 7054
7055 u8 cq_umem_valid[0x1];
7a32f296
ES		 7056 u8 reserved_at_2e1[0x1f];
7057
7058 u8 reserved_at_300[0x580];
e281682b 7059
b6ca09cb 7060 u8 pas[][0x40];
e281682b
SM		 7061};
7062
7063struct mlx5_ifc_modify_cong_status_out_bits {
7064 u8 status[0x8];
b4ff3a36 7065 u8 reserved_at_8[0x18];
e281682b
SM		 7066
7067 u8 syndrome[0x20];
7068
b4ff3a36 7069 u8 reserved_at_40[0x40];
e281682b
SM		 7070};
7071
7072struct mlx5_ifc_modify_cong_status_in_bits {
7073 u8 opcode[0x10];
b4ff3a36 7074 u8 reserved_at_10[0x10];
e281682b 7075
b4ff3a36 7076 u8 reserved_at_20[0x10];
e281682b
SM		 7077 u8 op_mod[0x10];
7078
b4ff3a36 7079 u8 reserved_at_40[0x18];
e281682b
SM		 7080 u8 priority[0x4];
7081 u8 cong_protocol[0x4];
7082
7083 u8 enable[0x1];
7084 u8 tag_enable[0x1];
b4ff3a36 7085 u8 reserved_at_62[0x1e];
e281682b
SM		 7086};
7087
7088struct mlx5_ifc_modify_cong_params_out_bits {
7089 u8 status[0x8];
b4ff3a36 7090 u8 reserved_at_8[0x18];
e281682b
SM		 7091
7092 u8 syndrome[0x20];
7093
b4ff3a36 7094 u8 reserved_at_40[0x40];
e281682b
SM		 7095};
7096
7097struct mlx5_ifc_modify_cong_params_in_bits {
7098 u8 opcode[0x10];
b4ff3a36 7099 u8 reserved_at_10[0x10];
e281682b 7100
b4ff3a36 7101 u8 reserved_at_20[0x10];
e281682b
SM		 7102 u8 op_mod[0x10];
7103
b4ff3a36 7104 u8 reserved_at_40[0x1c];
e281682b
SM		 7105 u8 cong_protocol[0x4];
7106
7107 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7108
b4ff3a36 7109 u8 reserved_at_80[0x80];
e281682b
SM		 7110
7111 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7112};
7113
7114struct mlx5_ifc_manage_pages_out_bits {
7115 u8 status[0x8];
b4ff3a36 7116 u8 reserved_at_8[0x18];
e281682b
SM		 7117
7118 u8 syndrome[0x20];
7119
7120 u8 output_num_entries[0x20];
7121
b4ff3a36 7122 u8 reserved_at_60[0x20];
e281682b 7123
b6ca09cb 7124 u8 pas[][0x40];
e281682b
SM		 7125};
7126
7127enum {
7128 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7129 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7130 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7131};
7132
7133struct mlx5_ifc_manage_pages_in_bits {
7134 u8 opcode[0x10];
b4ff3a36 7135 u8 reserved_at_10[0x10];
e281682b 7136
b4ff3a36 7137 u8 reserved_at_20[0x10];
e281682b
SM		 7138 u8 op_mod[0x10];
7139
591905ba
BW		 7140 u8 embedded_cpu_function[0x1];
7141 u8 reserved_at_41[0xf];
e281682b
SM		 7142 u8 function_id[0x10];
7143
7144 u8 input_num_entries[0x20];
7145
b6ca09cb 7146 u8 pas[][0x40];
e281682b
SM		 7147};
7148
7149struct mlx5_ifc_mad_ifc_out_bits {
7150 u8 status[0x8];
b4ff3a36 7151 u8 reserved_at_8[0x18];
e281682b
SM		 7152
7153 u8 syndrome[0x20];
7154
b4ff3a36 7155 u8 reserved_at_40[0x40];
e281682b
SM		 7156
7157 u8 response_mad_packet[256][0x8];
7158};
7159
7160struct mlx5_ifc_mad_ifc_in_bits {
7161 u8 opcode[0x10];
b4ff3a36 7162 u8 reserved_at_10[0x10];
e281682b 7163
b4ff3a36 7164 u8 reserved_at_20[0x10];
e281682b
SM		 7165 u8 op_mod[0x10];
7166
7167 u8 remote_lid[0x10];
b4ff3a36 7168 u8 reserved_at_50[0x8];
e281682b
SM		 7169 u8 port[0x8];
7170
b4ff3a36 7171 u8 reserved_at_60[0x20];
e281682b
SM		 7172
7173 u8 mad[256][0x8];
7174};
7175
7176struct mlx5_ifc_init_hca_out_bits {
7177 u8 status[0x8];
b4ff3a36 7178 u8 reserved_at_8[0x18];
e281682b
SM		 7179
7180 u8 syndrome[0x20];
7181
b4ff3a36 7182 u8 reserved_at_40[0x40];
e281682b
SM		 7183};
7184
7185struct mlx5_ifc_init_hca_in_bits {
7186 u8 opcode[0x10];
b4ff3a36 7187 u8 reserved_at_10[0x10];
e281682b 7188
b4ff3a36 7189 u8 reserved_at_20[0x10];
e281682b
SM		 7190 u8 op_mod[0x10];
7191
b4ff3a36 7192 u8 reserved_at_40[0x40];
8737f818 7193 u8 sw_owner_id[4][0x20];
e281682b
SM		 7194};
7195
7196struct mlx5_ifc_init2rtr_qp_out_bits {
7197 u8 status[0x8];
b4ff3a36 7198 u8 reserved_at_8[0x18];
e281682b
SM		 7199
7200 u8 syndrome[0x20];
7201
6b646a7e
LR		 7202 u8 reserved_at_40[0x20];
7203 u8 ece[0x20];
e281682b
SM		 7204};
7205
7206struct mlx5_ifc_init2rtr_qp_in_bits {
7207 u8 opcode[0x10];
4ac63ec7 7208 u8 uid[0x10];
e281682b 7209
b4ff3a36 7210 u8 reserved_at_20[0x10];
e281682b
SM		 7211 u8 op_mod[0x10];
7212
b4ff3a36 7213 u8 reserved_at_40[0x8];
e281682b
SM		 7214 u8 qpn[0x18];
7215
b4ff3a36 7216 u8 reserved_at_60[0x20];
e281682b
SM		 7217
7218 u8 opt_param_mask[0x20];
7219
6b646a7e 7220 u8 ece[0x20];
e281682b
SM		 7221
7222 struct mlx5_ifc_qpc_bits qpc;
7223
b4ff3a36 7224 u8 reserved_at_800[0x80];
e281682b
SM		 7225};
7226
7227struct mlx5_ifc_init2init_qp_out_bits {
7228 u8 status[0x8];
b4ff3a36 7229 u8 reserved_at_8[0x18];
e281682b
SM		 7230
7231 u8 syndrome[0x20];
7232
ab183d46
LR		 7233 u8 reserved_at_40[0x20];
7234 u8 ece[0x20];
e281682b
SM		 7235};
7236
7237struct mlx5_ifc_init2init_qp_in_bits {
7238 u8 opcode[0x10];
4ac63ec7 7239 u8 uid[0x10];
e281682b 7240
b4ff3a36 7241 u8 reserved_at_20[0x10];
e281682b
SM		 7242 u8 op_mod[0x10];
7243
b4ff3a36 7244 u8 reserved_at_40[0x8];
e281682b
SM		 7245 u8 qpn[0x18];
7246
b4ff3a36 7247 u8 reserved_at_60[0x20];
e281682b
SM		 7248
7249 u8 opt_param_mask[0x20];
7250
ab183d46 7251 u8 ece[0x20];
e281682b
SM		 7252
7253 struct mlx5_ifc_qpc_bits qpc;
7254
b4ff3a36 7255 u8 reserved_at_800[0x80];
e281682b
SM		 7256};
7257
7258struct mlx5_ifc_get_dropped_packet_log_out_bits {
7259 u8 status[0x8];
b4ff3a36 7260 u8 reserved_at_8[0x18];
e281682b
SM		 7261
7262 u8 syndrome[0x20];
7263
b4ff3a36 7264 u8 reserved_at_40[0x40];
e281682b
SM		 7265
7266 u8 packet_headers_log[128][0x8];
7267
7268 u8 packet_syndrome[64][0x8];
7269};
7270
7271struct mlx5_ifc_get_dropped_packet_log_in_bits {
7272 u8 opcode[0x10];
b4ff3a36 7273 u8 reserved_at_10[0x10];
e281682b 7274
b4ff3a36 7275 u8 reserved_at_20[0x10];
e281682b
SM		 7276 u8 op_mod[0x10];
7277
b4ff3a36 7278 u8 reserved_at_40[0x40];
e281682b
SM		 7279};
7280
7281struct mlx5_ifc_gen_eqe_in_bits {
7282 u8 opcode[0x10];
b4ff3a36 7283 u8 reserved_at_10[0x10];
e281682b 7284
b4ff3a36 7285 u8 reserved_at_20[0x10];
e281682b
SM		 7286 u8 op_mod[0x10];
7287
b4ff3a36 7288 u8 reserved_at_40[0x18];
e281682b
SM		 7289 u8 eq_number[0x8];
7290
b4ff3a36 7291 u8 reserved_at_60[0x20];
e281682b
SM		 7292
7293 u8 eqe[64][0x8];
7294};
7295
7296struct mlx5_ifc_gen_eq_out_bits {
7297 u8 status[0x8];
b4ff3a36 7298 u8 reserved_at_8[0x18];
e281682b
SM		 7299
7300 u8 syndrome[0x20];
7301
b4ff3a36 7302 u8 reserved_at_40[0x40];
e281682b
SM		 7303};
7304
7305struct mlx5_ifc_enable_hca_out_bits {
7306 u8 status[0x8];
b4ff3a36 7307 u8 reserved_at_8[0x18];
e281682b
SM		 7308
7309 u8 syndrome[0x20];
7310
b4ff3a36 7311 u8 reserved_at_40[0x20];
e281682b
SM		 7312};
7313
7314struct mlx5_ifc_enable_hca_in_bits {
7315 u8 opcode[0x10];
b4ff3a36 7316 u8 reserved_at_10[0x10];
e281682b 7317
b4ff3a36 7318 u8 reserved_at_20[0x10];
e281682b
SM		 7319 u8 op_mod[0x10];
7320
22e939a9
BW		 7321 u8 embedded_cpu_function[0x1];
7322 u8 reserved_at_41[0xf];
e281682b
SM		 7323 u8 function_id[0x10];
7324
b4ff3a36 7325 u8 reserved_at_60[0x20];
e281682b
SM		 7326};
7327
7328struct mlx5_ifc_drain_dct_out_bits {
7329 u8 status[0x8];
b4ff3a36 7330 u8 reserved_at_8[0x18];
e281682b
SM		 7331
7332 u8 syndrome[0x20];
7333
b4ff3a36 7334 u8 reserved_at_40[0x40];
e281682b
SM		 7335};
7336
7337struct mlx5_ifc_drain_dct_in_bits {
7338 u8 opcode[0x10];
774ea6ee 7339 u8 uid[0x10];
e281682b 7340
b4ff3a36 7341 u8 reserved_at_20[0x10];
e281682b
SM		 7342 u8 op_mod[0x10];
7343
b4ff3a36 7344 u8 reserved_at_40[0x8];
e281682b
SM		 7345 u8 dctn[0x18];
7346
b4ff3a36 7347 u8 reserved_at_60[0x20];
e281682b
SM		 7348};
7349
7350struct mlx5_ifc_disable_hca_out_bits {
7351 u8 status[0x8];
b4ff3a36 7352 u8 reserved_at_8[0x18];
e281682b
SM		 7353
7354 u8 syndrome[0x20];
7355
b4ff3a36 7356 u8 reserved_at_40[0x20];
e281682b
SM		 7357};
7358
7359struct mlx5_ifc_disable_hca_in_bits {
7360 u8 opcode[0x10];
b4ff3a36 7361 u8 reserved_at_10[0x10];
e281682b 7362
b4ff3a36 7363 u8 reserved_at_20[0x10];
e281682b
SM		 7364 u8 op_mod[0x10];
7365
22e939a9
BW		 7366 u8 embedded_cpu_function[0x1];
7367 u8 reserved_at_41[0xf];
e281682b
SM		 7368 u8 function_id[0x10];
7369
b4ff3a36 7370 u8 reserved_at_60[0x20];
e281682b
SM		 7371};
7372
7373struct mlx5_ifc_detach_from_mcg_out_bits {
7374 u8 status[0x8];
b4ff3a36 7375 u8 reserved_at_8[0x18];
e281682b
SM		 7376
7377 u8 syndrome[0x20];
7378
b4ff3a36 7379 u8 reserved_at_40[0x40];
e281682b
SM		 7380};
7381
7382struct mlx5_ifc_detach_from_mcg_in_bits {
7383 u8 opcode[0x10];
bd371975 7384 u8 uid[0x10];
e281682b 7385
b4ff3a36 7386 u8 reserved_at_20[0x10];
e281682b
SM		 7387 u8 op_mod[0x10];
7388
b4ff3a36 7389 u8 reserved_at_40[0x8];
e281682b
SM		 7390 u8 qpn[0x18];
7391
b4ff3a36 7392 u8 reserved_at_60[0x20];
e281682b
SM		 7393
7394 u8 multicast_gid[16][0x8];
7395};
7396
7486216b
SM		 7397struct mlx5_ifc_destroy_xrq_out_bits {
7398 u8 status[0x8];
7399 u8 reserved_at_8[0x18];
7400
7401 u8 syndrome[0x20];
7402
7403 u8 reserved_at_40[0x40];
7404};
7405
7406struct mlx5_ifc_destroy_xrq_in_bits {
7407 u8 opcode[0x10];
a0d8c054 7408 u8 uid[0x10];
7486216b
SM		 7409
7410 u8 reserved_at_20[0x10];
7411 u8 op_mod[0x10];
7412
7413 u8 reserved_at_40[0x8];
7414 u8 xrqn[0x18];
7415
7416 u8 reserved_at_60[0x20];
7417};
7418
e281682b
SM		 7419struct mlx5_ifc_destroy_xrc_srq_out_bits {
7420 u8 status[0x8];
b4ff3a36 7421 u8 reserved_at_8[0x18];
e281682b
SM		 7422
7423 u8 syndrome[0x20];
7424
b4ff3a36 7425 u8 reserved_at_40[0x40];
e281682b
SM		 7426};
7427
7428struct mlx5_ifc_destroy_xrc_srq_in_bits {
7429 u8 opcode[0x10];
a0d8c054 7430 u8 uid[0x10];
e281682b 7431
b4ff3a36 7432 u8 reserved_at_20[0x10];
e281682b
SM		 7433 u8 op_mod[0x10];
7434
b4ff3a36 7435 u8 reserved_at_40[0x8];
e281682b
SM		 7436 u8 xrc_srqn[0x18];
7437
b4ff3a36 7438 u8 reserved_at_60[0x20];
e281682b
SM		 7439};
7440
7441struct mlx5_ifc_destroy_tis_out_bits {
7442 u8 status[0x8];
b4ff3a36 7443 u8 reserved_at_8[0x18];
e281682b
SM		 7444
7445 u8 syndrome[0x20];
7446
b4ff3a36 7447 u8 reserved_at_40[0x40];
e281682b
SM		 7448};
7449
7450struct mlx5_ifc_destroy_tis_in_bits {
7451 u8 opcode[0x10];
bd371975 7452 u8 uid[0x10];
e281682b 7453
b4ff3a36 7454 u8 reserved_at_20[0x10];
e281682b
SM		 7455 u8 op_mod[0x10];
7456
b4ff3a36 7457 u8 reserved_at_40[0x8];
e281682b
SM		 7458 u8 tisn[0x18];
7459
b4ff3a36 7460 u8 reserved_at_60[0x20];
e281682b
SM		 7461};
7462
7463struct mlx5_ifc_destroy_tir_out_bits {
7464 u8 status[0x8];
b4ff3a36 7465 u8 reserved_at_8[0x18];
e281682b
SM		 7466
7467 u8 syndrome[0x20];
7468
b4ff3a36 7469 u8 reserved_at_40[0x40];
e281682b
SM		 7470};
7471
7472struct mlx5_ifc_destroy_tir_in_bits {
7473 u8 opcode[0x10];
bd371975 7474 u8 uid[0x10];
e281682b 7475
b4ff3a36 7476 u8 reserved_at_20[0x10];
e281682b
SM		 7477 u8 op_mod[0x10];
7478
b4ff3a36 7479 u8 reserved_at_40[0x8];
e281682b
SM		 7480 u8 tirn[0x18];
7481
b4ff3a36 7482 u8 reserved_at_60[0x20];
e281682b
SM		 7483};
7484
7485struct mlx5_ifc_destroy_srq_out_bits {
7486 u8 status[0x8];
b4ff3a36 7487 u8 reserved_at_8[0x18];
e281682b
SM		 7488
7489 u8 syndrome[0x20];
7490
b4ff3a36 7491 u8 reserved_at_40[0x40];
e281682b
SM		 7492};
7493
7494struct mlx5_ifc_destroy_srq_in_bits {
7495 u8 opcode[0x10];
a0d8c054 7496 u8 uid[0x10];
e281682b 7497
b4ff3a36 7498 u8 reserved_at_20[0x10];
e281682b
SM		 7499 u8 op_mod[0x10];
7500
b4ff3a36 7501 u8 reserved_at_40[0x8];
e281682b
SM		 7502 u8 srqn[0x18];
7503
b4ff3a36 7504 u8 reserved_at_60[0x20];
e281682b
SM		 7505};
7506
7507struct mlx5_ifc_destroy_sq_out_bits {
7508 u8 status[0x8];
b4ff3a36 7509 u8 reserved_at_8[0x18];
e281682b
SM		 7510
7511 u8 syndrome[0x20];
7512
b4ff3a36 7513 u8 reserved_at_40[0x40];
e281682b
SM		 7514};
7515
7516struct mlx5_ifc_destroy_sq_in_bits {
7517 u8 opcode[0x10];
430ae0d5 7518 u8 uid[0x10];
e281682b 7519
b4ff3a36 7520 u8 reserved_at_20[0x10];
e281682b
SM		 7521 u8 op_mod[0x10];
7522
b4ff3a36 7523 u8 reserved_at_40[0x8];
e281682b
SM		 7524 u8 sqn[0x18];
7525
b4ff3a36 7526 u8 reserved_at_60[0x20];
e281682b
SM		 7527};
7528
813f8540
MHY		 7529struct mlx5_ifc_destroy_scheduling_element_out_bits {
7530 u8 status[0x8];
7531 u8 reserved_at_8[0x18];
7532
7533 u8 syndrome[0x20];
7534
7535 u8 reserved_at_40[0x1c0];
7536};
7537
7538struct mlx5_ifc_destroy_scheduling_element_in_bits {
7539 u8 opcode[0x10];
7540 u8 reserved_at_10[0x10];
7541
7542 u8 reserved_at_20[0x10];
7543 u8 op_mod[0x10];
7544
7545 u8 scheduling_hierarchy[0x8];
7546 u8 reserved_at_48[0x18];
7547
7548 u8 scheduling_element_id[0x20];
7549
7550 u8 reserved_at_80[0x180];
7551};
7552
e281682b
SM		 7553struct mlx5_ifc_destroy_rqt_out_bits {
7554 u8 status[0x8];
b4ff3a36 7555 u8 reserved_at_8[0x18];
e281682b
SM		 7556
7557 u8 syndrome[0x20];
7558
b4ff3a36 7559 u8 reserved_at_40[0x40];
e281682b
SM		 7560};
7561
7562struct mlx5_ifc_destroy_rqt_in_bits {
7563 u8 opcode[0x10];
bd371975 7564 u8 uid[0x10];
e281682b 7565
b4ff3a36 7566 u8 reserved_at_20[0x10];
e281682b
SM		 7567 u8 op_mod[0x10];
7568
b4ff3a36 7569 u8 reserved_at_40[0x8];
e281682b
SM		 7570 u8 rqtn[0x18];
7571
b4ff3a36 7572 u8 reserved_at_60[0x20];
e281682b
SM		 7573};
7574
7575struct mlx5_ifc_destroy_rq_out_bits {
7576 u8 status[0x8];
b4ff3a36 7577 u8 reserved_at_8[0x18];
e281682b
SM		 7578
7579 u8 syndrome[0x20];
7580
b4ff3a36 7581 u8 reserved_at_40[0x40];
e281682b
SM		 7582};
7583
7584struct mlx5_ifc_destroy_rq_in_bits {
7585 u8 opcode[0x10];
d269b3af 7586 u8 uid[0x10];
e281682b 7587
b4ff3a36 7588 u8 reserved_at_20[0x10];
e281682b
SM		 7589 u8 op_mod[0x10];
7590
b4ff3a36 7591 u8 reserved_at_40[0x8];
e281682b
SM		 7592 u8 rqn[0x18];
7593
b4ff3a36 7594 u8 reserved_at_60[0x20];
e281682b
SM		 7595};
7596
c1e0bfc1
MG		 7597struct mlx5_ifc_set_delay_drop_params_in_bits {
7598 u8 opcode[0x10];
7599 u8 reserved_at_10[0x10];
7600
7601 u8 reserved_at_20[0x10];
7602 u8 op_mod[0x10];
7603
7604 u8 reserved_at_40[0x20];
7605
7606 u8 reserved_at_60[0x10];
7607 u8 delay_drop_timeout[0x10];
7608};
7609
7610struct mlx5_ifc_set_delay_drop_params_out_bits {
7611 u8 status[0x8];
7612 u8 reserved_at_8[0x18];
7613
7614 u8 syndrome[0x20];
7615
7616 u8 reserved_at_40[0x40];
7617};
7618
e281682b
SM		 7619struct mlx5_ifc_destroy_rmp_out_bits {
7620 u8 status[0x8];
b4ff3a36 7621 u8 reserved_at_8[0x18];
e281682b
SM		 7622
7623 u8 syndrome[0x20];
7624
b4ff3a36 7625 u8 reserved_at_40[0x40];
e281682b
SM		 7626};
7627
7628struct mlx5_ifc_destroy_rmp_in_bits {
7629 u8 opcode[0x10];
a0d8c054 7630 u8 uid[0x10];
e281682b 7631
b4ff3a36 7632 u8 reserved_at_20[0x10];
e281682b
SM		 7633 u8 op_mod[0x10];
7634
b4ff3a36 7635 u8 reserved_at_40[0x8];
e281682b
SM		 7636 u8 rmpn[0x18];
7637
b4ff3a36 7638 u8 reserved_at_60[0x20];
e281682b
SM		 7639};
7640
7641struct mlx5_ifc_destroy_qp_out_bits {
7642 u8 status[0x8];
b4ff3a36 7643 u8 reserved_at_8[0x18];
e281682b
SM		 7644
7645 u8 syndrome[0x20];
7646
b4ff3a36 7647 u8 reserved_at_40[0x40];
e281682b
SM		 7648};
7649
7650struct mlx5_ifc_destroy_qp_in_bits {
7651 u8 opcode[0x10];
4ac63ec7 7652 u8 uid[0x10];
e281682b 7653
b4ff3a36 7654 u8 reserved_at_20[0x10];
e281682b
SM		 7655 u8 op_mod[0x10];
7656
b4ff3a36 7657 u8 reserved_at_40[0x8];
e281682b
SM		 7658 u8 qpn[0x18];
7659
b4ff3a36 7660 u8 reserved_at_60[0x20];
e281682b
SM		 7661};
7662
7663struct mlx5_ifc_destroy_psv_out_bits {
7664 u8 status[0x8];
b4ff3a36 7665 u8 reserved_at_8[0x18];
e281682b
SM		 7666
7667 u8 syndrome[0x20];
7668
b4ff3a36 7669 u8 reserved_at_40[0x40];
e281682b
SM		 7670};
7671
7672struct mlx5_ifc_destroy_psv_in_bits {
7673 u8 opcode[0x10];
b4ff3a36 7674 u8 reserved_at_10[0x10];
e281682b 7675
b4ff3a36 7676 u8 reserved_at_20[0x10];
e281682b
SM		 7677 u8 op_mod[0x10];
7678
b4ff3a36 7679 u8 reserved_at_40[0x8];
e281682b
SM		 7680 u8 psvn[0x18];
7681
b4ff3a36 7682 u8 reserved_at_60[0x20];
e281682b
SM		 7683};
7684
7685struct mlx5_ifc_destroy_mkey_out_bits {
7686 u8 status[0x8];
b4ff3a36 7687 u8 reserved_at_8[0x18];
e281682b
SM		 7688
7689 u8 syndrome[0x20];
7690
b4ff3a36 7691 u8 reserved_at_40[0x40];
e281682b
SM		 7692};
7693
7694struct mlx5_ifc_destroy_mkey_in_bits {
7695 u8 opcode[0x10];
8a06a79b 7696 u8 uid[0x10];
e281682b 7697
b4ff3a36 7698 u8 reserved_at_20[0x10];
e281682b
SM		 7699 u8 op_mod[0x10];
7700
b4ff3a36 7701 u8 reserved_at_40[0x8];
e281682b
SM		 7702 u8 mkey_index[0x18];
7703
b4ff3a36 7704 u8 reserved_at_60[0x20];
e281682b
SM		 7705};
7706
7707struct mlx5_ifc_destroy_flow_table_out_bits {
7708 u8 status[0x8];
b4ff3a36 7709 u8 reserved_at_8[0x18];
e281682b
SM		 7710
7711 u8 syndrome[0x20];
7712
b4ff3a36 7713 u8 reserved_at_40[0x40];
e281682b
SM		 7714};
7715
7716struct mlx5_ifc_destroy_flow_table_in_bits {
7717 u8 opcode[0x10];
b4ff3a36 7718 u8 reserved_at_10[0x10];
e281682b 7719
b4ff3a36 7720 u8 reserved_at_20[0x10];
e281682b
SM		 7721 u8 op_mod[0x10];
7722
7d5e1423
SM		 7723 u8 other_vport[0x1];
7724 u8 reserved_at_41[0xf];
7725 u8 vport_number[0x10];
7726
7727 u8 reserved_at_60[0x20];
e281682b
SM		 7728
7729 u8 table_type[0x8];
b4ff3a36 7730 u8 reserved_at_88[0x18];
e281682b 7731
b4ff3a36 7732 u8 reserved_at_a0[0x8];
e281682b
SM		 7733 u8 table_id[0x18];
7734
b4ff3a36 7735 u8 reserved_at_c0[0x140];
e281682b
SM		 7736};
7737
7738struct mlx5_ifc_destroy_flow_group_out_bits {
7739 u8 status[0x8];
b4ff3a36 7740 u8 reserved_at_8[0x18];
e281682b
SM		 7741
7742 u8 syndrome[0x20];
7743
b4ff3a36 7744 u8 reserved_at_40[0x40];
e281682b
SM		 7745};
7746
7747struct mlx5_ifc_destroy_flow_group_in_bits {
7748 u8 opcode[0x10];
b4ff3a36 7749 u8 reserved_at_10[0x10];
e281682b 7750
b4ff3a36 7751 u8 reserved_at_20[0x10];
e281682b
SM		 7752 u8 op_mod[0x10];
7753
7d5e1423
SM		 7754 u8 other_vport[0x1];
7755 u8 reserved_at_41[0xf];
7756 u8 vport_number[0x10];
7757
7758 u8 reserved_at_60[0x20];
e281682b
SM		 7759
7760 u8 table_type[0x8];
b4ff3a36 7761 u8 reserved_at_88[0x18];
e281682b 7762
b4ff3a36 7763 u8 reserved_at_a0[0x8];
e281682b
SM		 7764 u8 table_id[0x18];
7765
7766 u8 group_id[0x20];
7767
b4ff3a36 7768 u8 reserved_at_e0[0x120];
e281682b
SM		 7769};
7770
7771struct mlx5_ifc_destroy_eq_out_bits {
7772 u8 status[0x8];
b4ff3a36 7773 u8 reserved_at_8[0x18];
e281682b
SM		 7774
7775 u8 syndrome[0x20];
7776
b4ff3a36 7777 u8 reserved_at_40[0x40];
e281682b
SM		 7778};
7779
7780struct mlx5_ifc_destroy_eq_in_bits {
7781 u8 opcode[0x10];
b4ff3a36 7782 u8 reserved_at_10[0x10];
e281682b 7783
b4ff3a36 7784 u8 reserved_at_20[0x10];
e281682b
SM		 7785 u8 op_mod[0x10];
7786
b4ff3a36 7787 u8 reserved_at_40[0x18];
e281682b
SM		 7788 u8 eq_number[0x8];
7789
b4ff3a36 7790 u8 reserved_at_60[0x20];
e281682b
SM		 7791};
7792
7793struct mlx5_ifc_destroy_dct_out_bits {
7794 u8 status[0x8];
b4ff3a36 7795 u8 reserved_at_8[0x18];
e281682b
SM		 7796
7797 u8 syndrome[0x20];
7798
b4ff3a36 7799 u8 reserved_at_40[0x40];
e281682b
SM		 7800};
7801
7802struct mlx5_ifc_destroy_dct_in_bits {
7803 u8 opcode[0x10];
774ea6ee 7804 u8 uid[0x10];
e281682b 7805
b4ff3a36 7806 u8 reserved_at_20[0x10];
e281682b
SM		 7807 u8 op_mod[0x10];
7808
b4ff3a36 7809 u8 reserved_at_40[0x8];
e281682b
SM		 7810 u8 dctn[0x18];
7811
b4ff3a36 7812 u8 reserved_at_60[0x20];
e281682b
SM		 7813};
7814
7815struct mlx5_ifc_destroy_cq_out_bits {
7816 u8 status[0x8];
b4ff3a36 7817 u8 reserved_at_8[0x18];
e281682b
SM		 7818
7819 u8 syndrome[0x20];
7820
b4ff3a36 7821 u8 reserved_at_40[0x40];
e281682b
SM		 7822};
7823
7824struct mlx5_ifc_destroy_cq_in_bits {
7825 u8 opcode[0x10];
9ba481e2 7826 u8 uid[0x10];
e281682b 7827
b4ff3a36 7828 u8 reserved_at_20[0x10];
e281682b
SM		 7829 u8 op_mod[0x10];
7830
b4ff3a36 7831 u8 reserved_at_40[0x8];
e281682b
SM		 7832 u8 cqn[0x18];
7833
b4ff3a36 7834 u8 reserved_at_60[0x20];
e281682b
SM		 7835};
7836
7837struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7838 u8 status[0x8];
b4ff3a36 7839 u8 reserved_at_8[0x18];
e281682b
SM		 7840
7841 u8 syndrome[0x20];
7842
b4ff3a36 7843 u8 reserved_at_40[0x40];
e281682b
SM		 7844};
7845
7846struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7847 u8 opcode[0x10];
b4ff3a36 7848 u8 reserved_at_10[0x10];
e281682b 7849
b4ff3a36 7850 u8 reserved_at_20[0x10];
e281682b
SM		 7851 u8 op_mod[0x10];
7852
b4ff3a36 7853 u8 reserved_at_40[0x20];
e281682b 7854
b4ff3a36 7855 u8 reserved_at_60[0x10];
e281682b
SM		 7856 u8 vxlan_udp_port[0x10];
7857};
7858
7859struct mlx5_ifc_delete_l2_table_entry_out_bits {
7860 u8 status[0x8];
b4ff3a36 7861 u8 reserved_at_8[0x18];
e281682b
SM		 7862
7863 u8 syndrome[0x20];
7864
b4ff3a36 7865 u8 reserved_at_40[0x40];
e281682b
SM		 7866};
7867
7868struct mlx5_ifc_delete_l2_table_entry_in_bits {
7869 u8 opcode[0x10];
b4ff3a36 7870 u8 reserved_at_10[0x10];
e281682b 7871
b4ff3a36 7872 u8 reserved_at_20[0x10];
e281682b
SM		 7873 u8 op_mod[0x10];
7874
b4ff3a36 7875 u8 reserved_at_40[0x60];
e281682b 7876
b4ff3a36 7877 u8 reserved_at_a0[0x8];
e281682b
SM		 7878 u8 table_index[0x18];
7879
b4ff3a36 7880 u8 reserved_at_c0[0x140];
e281682b
SM		 7881};
7882
7883struct mlx5_ifc_delete_fte_out_bits {
7884 u8 status[0x8];
b4ff3a36 7885 u8 reserved_at_8[0x18];
e281682b
SM		 7886
7887 u8 syndrome[0x20];
7888
b4ff3a36 7889 u8 reserved_at_40[0x40];
e281682b
SM		 7890};
7891
7892struct mlx5_ifc_delete_fte_in_bits {
7893 u8 opcode[0x10];
b4ff3a36 7894 u8 reserved_at_10[0x10];
e281682b 7895
b4ff3a36 7896 u8 reserved_at_20[0x10];
e281682b
SM		 7897 u8 op_mod[0x10];
7898
7d5e1423
SM		 7899 u8 other_vport[0x1];
7900 u8 reserved_at_41[0xf];
7901 u8 vport_number[0x10];
7902
7903 u8 reserved_at_60[0x20];
e281682b
SM		 7904
7905 u8 table_type[0x8];
b4ff3a36 7906 u8 reserved_at_88[0x18];
e281682b 7907
b4ff3a36 7908 u8 reserved_at_a0[0x8];
e281682b
SM		 7909 u8 table_id[0x18];
7910
b4ff3a36 7911 u8 reserved_at_c0[0x40];
e281682b
SM		 7912
7913 u8 flow_index[0x20];
7914
b4ff3a36 7915 u8 reserved_at_120[0xe0];
e281682b
SM		 7916};
7917
7918struct mlx5_ifc_dealloc_xrcd_out_bits {
7919 u8 status[0x8];
b4ff3a36 7920 u8 reserved_at_8[0x18];
e281682b
SM		 7921
7922 u8 syndrome[0x20];
7923
b4ff3a36 7924 u8 reserved_at_40[0x40];
e281682b
SM		 7925};
7926
7927struct mlx5_ifc_dealloc_xrcd_in_bits {
7928 u8 opcode[0x10];
bd371975 7929 u8 uid[0x10];
e281682b 7930
b4ff3a36 7931 u8 reserved_at_20[0x10];
e281682b
SM		 7932 u8 op_mod[0x10];
7933
b4ff3a36 7934 u8 reserved_at_40[0x8];
e281682b
SM		 7935 u8 xrcd[0x18];
7936
b4ff3a36 7937 u8 reserved_at_60[0x20];
e281682b
SM		 7938};
7939
7940struct mlx5_ifc_dealloc_uar_out_bits {
7941 u8 status[0x8];
b4ff3a36 7942 u8 reserved_at_8[0x18];
e281682b
SM		 7943
7944 u8 syndrome[0x20];
7945
b4ff3a36 7946 u8 reserved_at_40[0x40];
e281682b
SM		 7947};
7948
7949struct mlx5_ifc_dealloc_uar_in_bits {
7950 u8 opcode[0x10];
8de1e9b0 7951 u8 uid[0x10];
e281682b 7952
b4ff3a36 7953 u8 reserved_at_20[0x10];
e281682b
SM		 7954 u8 op_mod[0x10];
7955
b4ff3a36 7956 u8 reserved_at_40[0x8];
e281682b
SM		 7957 u8 uar[0x18];
7958
b4ff3a36 7959 u8 reserved_at_60[0x20];
e281682b
SM		 7960};
7961
7962struct mlx5_ifc_dealloc_transport_domain_out_bits {
7963 u8 status[0x8];
b4ff3a36 7964 u8 reserved_at_8[0x18];
e281682b
SM		 7965
7966 u8 syndrome[0x20];
7967
b4ff3a36 7968 u8 reserved_at_40[0x40];
e281682b
SM		 7969};
7970
7971struct mlx5_ifc_dealloc_transport_domain_in_bits {
7972 u8 opcode[0x10];
71bef2fd 7973 u8 uid[0x10];
e281682b 7974
b4ff3a36 7975 u8 reserved_at_20[0x10];
e281682b
SM		 7976 u8 op_mod[0x10];
7977
b4ff3a36 7978 u8 reserved_at_40[0x8];
e281682b
SM		 7979 u8 transport_domain[0x18];
7980
b4ff3a36 7981 u8 reserved_at_60[0x20];
e281682b
SM		 7982};
7983
7984struct mlx5_ifc_dealloc_q_counter_out_bits {
7985 u8 status[0x8];
b4ff3a36 7986 u8 reserved_at_8[0x18];
e281682b
SM		 7987
7988 u8 syndrome[0x20];
7989
b4ff3a36 7990 u8 reserved_at_40[0x40];
e281682b
SM		 7991};
7992
7993struct mlx5_ifc_dealloc_q_counter_in_bits {
7994 u8 opcode[0x10];
b4ff3a36 7995 u8 reserved_at_10[0x10];
e281682b 7996
b4ff3a36 7997 u8 reserved_at_20[0x10];
e281682b
SM		 7998 u8 op_mod[0x10];
7999
b4ff3a36 8000 u8 reserved_at_40[0x18];
e281682b
SM		 8001 u8 counter_set_id[0x8];
8002
b4ff3a36 8003 u8 reserved_at_60[0x20];
e281682b
SM		 8004};
8005
8006struct mlx5_ifc_dealloc_pd_out_bits {
8007 u8 status[0x8];
b4ff3a36 8008 u8 reserved_at_8[0x18];
e281682b
SM		 8009
8010 u8 syndrome[0x20];
8011
b4ff3a36 8012 u8 reserved_at_40[0x40];
e281682b
SM		 8013};
8014
8015struct mlx5_ifc_dealloc_pd_in_bits {
8016 u8 opcode[0x10];
bd371975 8017 u8 uid[0x10];
e281682b 8018
b4ff3a36 8019 u8 reserved_at_20[0x10];
e281682b
SM		 8020 u8 op_mod[0x10];
8021
b4ff3a36 8022 u8 reserved_at_40[0x8];
e281682b
SM		 8023 u8 pd[0x18];
8024
b4ff3a36 8025 u8 reserved_at_60[0x20];
e281682b
SM		 8026};
8027
9dc0b289
AV		 8028struct mlx5_ifc_dealloc_flow_counter_out_bits {
8029 u8 status[0x8];
8030 u8 reserved_at_8[0x18];
8031
8032 u8 syndrome[0x20];
8033
8034 u8 reserved_at_40[0x40];
8035};
8036
8037struct mlx5_ifc_dealloc_flow_counter_in_bits {
8038 u8 opcode[0x10];
8039 u8 reserved_at_10[0x10];
8040
8041 u8 reserved_at_20[0x10];
8042 u8 op_mod[0x10];
8043
a8ffcc74 8044 u8 flow_counter_id[0x20];
9dc0b289
AV		 8045
8046 u8 reserved_at_60[0x20];
8047};
8048
7486216b
SM		 8049struct mlx5_ifc_create_xrq_out_bits {
8050 u8 status[0x8];
8051 u8 reserved_at_8[0x18];
8052
8053 u8 syndrome[0x20];
8054
8055 u8 reserved_at_40[0x8];
8056 u8 xrqn[0x18];
8057
8058 u8 reserved_at_60[0x20];
8059};
8060
8061struct mlx5_ifc_create_xrq_in_bits {
8062 u8 opcode[0x10];
a0d8c054 8063 u8 uid[0x10];
7486216b
SM		 8064
8065 u8 reserved_at_20[0x10];
8066 u8 op_mod[0x10];
8067
8068 u8 reserved_at_40[0x40];
8069
8070 struct mlx5_ifc_xrqc_bits xrq_context;
8071};
8072
e281682b
SM		 8073struct mlx5_ifc_create_xrc_srq_out_bits {
8074 u8 status[0x8];
b4ff3a36 8075 u8 reserved_at_8[0x18];
e281682b
SM		 8076
8077 u8 syndrome[0x20];
8078
b4ff3a36 8079 u8 reserved_at_40[0x8];
e281682b
SM		 8080 u8 xrc_srqn[0x18];
8081
b4ff3a36 8082 u8 reserved_at_60[0x20];
e281682b
SM		 8083};
8084
8085struct mlx5_ifc_create_xrc_srq_in_bits {
8086 u8 opcode[0x10];
a0d8c054 8087 u8 uid[0x10];
e281682b 8088
b4ff3a36 8089 u8 reserved_at_20[0x10];
e281682b
SM		 8090 u8 op_mod[0x10];
8091
b4ff3a36 8092 u8 reserved_at_40[0x40];
e281682b
SM		 8093
8094 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8095
99b77fef
YH		 8096 u8 reserved_at_280[0x60];
8097
bd371975 8098 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 8099 u8 reserved_at_2e1[0x1f];
8100
8101 u8 reserved_at_300[0x580];
e281682b 8102
b6ca09cb 8103 u8 pas[][0x40];
e281682b
SM		 8104};
8105
8106struct mlx5_ifc_create_tis_out_bits {
8107 u8 status[0x8];
b4ff3a36 8108 u8 reserved_at_8[0x18];
e281682b
SM		 8109
8110 u8 syndrome[0x20];
8111
b4ff3a36 8112 u8 reserved_at_40[0x8];
e281682b
SM		 8113 u8 tisn[0x18];
8114
b4ff3a36 8115 u8 reserved_at_60[0x20];
e281682b
SM		 8116};
8117
8118struct mlx5_ifc_create_tis_in_bits {
8119 u8 opcode[0x10];
bd371975 8120 u8 uid[0x10];
e281682b 8121
b4ff3a36 8122 u8 reserved_at_20[0x10];
e281682b
SM		 8123 u8 op_mod[0x10];
8124
b4ff3a36 8125 u8 reserved_at_40[0xc0];
e281682b
SM		 8126
8127 struct mlx5_ifc_tisc_bits ctx;
8128};
8129
8130struct mlx5_ifc_create_tir_out_bits {
8131 u8 status[0x8];
3e070470 8132 u8 icm_address_63_40[0x18];
e281682b
SM		 8133
8134 u8 syndrome[0x20];
8135
3e070470 8136 u8 icm_address_39_32[0x8];
e281682b
SM		 8137 u8 tirn[0x18];
8138
3e070470 8139 u8 icm_address_31_0[0x20];
e281682b
SM		 8140};
8141
8142struct mlx5_ifc_create_tir_in_bits {
8143 u8 opcode[0x10];
bd371975 8144 u8 uid[0x10];
e281682b 8145
b4ff3a36 8146 u8 reserved_at_20[0x10];
e281682b
SM		 8147 u8 op_mod[0x10];
8148
b4ff3a36 8149 u8 reserved_at_40[0xc0];
e281682b
SM		 8150
8151 struct mlx5_ifc_tirc_bits ctx;
8152};
8153
8154struct mlx5_ifc_create_srq_out_bits {
8155 u8 status[0x8];
b4ff3a36 8156 u8 reserved_at_8[0x18];
e281682b
SM		 8157
8158 u8 syndrome[0x20];
8159
b4ff3a36 8160 u8 reserved_at_40[0x8];
e281682b
SM		 8161 u8 srqn[0x18];
8162
b4ff3a36 8163 u8 reserved_at_60[0x20];
e281682b
SM		 8164};
8165
8166struct mlx5_ifc_create_srq_in_bits {
8167 u8 opcode[0x10];
a0d8c054 8168 u8 uid[0x10];
e281682b 8169
b4ff3a36 8170 u8 reserved_at_20[0x10];
e281682b
SM		 8171 u8 op_mod[0x10];
8172
b4ff3a36 8173 u8 reserved_at_40[0x40];
e281682b
SM		 8174
8175 struct mlx5_ifc_srqc_bits srq_context_entry;
8176
b4ff3a36 8177 u8 reserved_at_280[0x600];
e281682b 8178
b6ca09cb 8179 u8 pas[][0x40];
e281682b
SM		 8180};
8181
8182struct mlx5_ifc_create_sq_out_bits {
8183 u8 status[0x8];
b4ff3a36 8184 u8 reserved_at_8[0x18];
e281682b
SM		 8185
8186 u8 syndrome[0x20];
8187
b4ff3a36 8188 u8 reserved_at_40[0x8];
e281682b
SM		 8189 u8 sqn[0x18];
8190
b4ff3a36 8191 u8 reserved_at_60[0x20];
e281682b
SM		 8192};
8193
8194struct mlx5_ifc_create_sq_in_bits {
8195 u8 opcode[0x10];
430ae0d5 8196 u8 uid[0x10];
e281682b 8197
b4ff3a36 8198 u8 reserved_at_20[0x10];
e281682b
SM		 8199 u8 op_mod[0x10];
8200
b4ff3a36 8201 u8 reserved_at_40[0xc0];
e281682b
SM		 8202
8203 struct mlx5_ifc_sqc_bits ctx;
8204};
8205
813f8540
MHY		 8206struct mlx5_ifc_create_scheduling_element_out_bits {
8207 u8 status[0x8];
8208 u8 reserved_at_8[0x18];
8209
8210 u8 syndrome[0x20];
8211
8212 u8 reserved_at_40[0x40];
8213
8214 u8 scheduling_element_id[0x20];
8215
8216 u8 reserved_at_a0[0x160];
8217};
8218
8219struct mlx5_ifc_create_scheduling_element_in_bits {
8220 u8 opcode[0x10];
8221 u8 reserved_at_10[0x10];
8222
8223 u8 reserved_at_20[0x10];
8224 u8 op_mod[0x10];
8225
8226 u8 scheduling_hierarchy[0x8];
8227 u8 reserved_at_48[0x18];
8228
8229 u8 reserved_at_60[0xa0];
8230
8231 struct mlx5_ifc_scheduling_context_bits scheduling_context;
8232
8233 u8 reserved_at_300[0x100];
8234};
8235
e281682b
SM		 8236struct mlx5_ifc_create_rqt_out_bits {
8237 u8 status[0x8];
b4ff3a36 8238 u8 reserved_at_8[0x18];
e281682b
SM		 8239
8240 u8 syndrome[0x20];
8241
b4ff3a36 8242 u8 reserved_at_40[0x8];
e281682b
SM		 8243 u8 rqtn[0x18];
8244
b4ff3a36 8245 u8 reserved_at_60[0x20];
e281682b
SM		 8246};
8247
8248struct mlx5_ifc_create_rqt_in_bits {
8249 u8 opcode[0x10];
bd371975 8250 u8 uid[0x10];
e281682b 8251
b4ff3a36 8252 u8 reserved_at_20[0x10];
e281682b
SM		 8253 u8 op_mod[0x10];
8254
b4ff3a36 8255 u8 reserved_at_40[0xc0];
e281682b
SM		 8256
8257 struct mlx5_ifc_rqtc_bits rqt_context;
8258};
8259
8260struct mlx5_ifc_create_rq_out_bits {
8261 u8 status[0x8];
b4ff3a36 8262 u8 reserved_at_8[0x18];
e281682b
SM		 8263
8264 u8 syndrome[0x20];
8265
b4ff3a36 8266 u8 reserved_at_40[0x8];
e281682b
SM		 8267 u8 rqn[0x18];
8268
b4ff3a36 8269 u8 reserved_at_60[0x20];
e281682b
SM		 8270};
8271
8272struct mlx5_ifc_create_rq_in_bits {
8273 u8 opcode[0x10];
d269b3af 8274 u8 uid[0x10];
e281682b 8275
b4ff3a36 8276 u8 reserved_at_20[0x10];
e281682b
SM		 8277 u8 op_mod[0x10];
8278
b4ff3a36 8279 u8 reserved_at_40[0xc0];
e281682b
SM		 8280
8281 struct mlx5_ifc_rqc_bits ctx;
8282};
8283
8284struct mlx5_ifc_create_rmp_out_bits {
8285 u8 status[0x8];
b4ff3a36 8286 u8 reserved_at_8[0x18];
e281682b
SM		 8287
8288 u8 syndrome[0x20];
8289
b4ff3a36 8290 u8 reserved_at_40[0x8];
e281682b
SM		 8291 u8 rmpn[0x18];
8292
b4ff3a36 8293 u8 reserved_at_60[0x20];
e281682b
SM		 8294};
8295
8296struct mlx5_ifc_create_rmp_in_bits {
8297 u8 opcode[0x10];
a0d8c054 8298 u8 uid[0x10];
e281682b 8299
b4ff3a36 8300 u8 reserved_at_20[0x10];
e281682b
SM		 8301 u8 op_mod[0x10];
8302
b4ff3a36 8303 u8 reserved_at_40[0xc0];
e281682b
SM		 8304
8305 struct mlx5_ifc_rmpc_bits ctx;
8306};
8307
8308struct mlx5_ifc_create_qp_out_bits {
8309 u8 status[0x8];
b4ff3a36 8310 u8 reserved_at_8[0x18];
e281682b
SM		 8311
8312 u8 syndrome[0x20];
8313
b4ff3a36 8314 u8 reserved_at_40[0x8];
e281682b
SM		 8315 u8 qpn[0x18];
8316
6b646a7e 8317 u8 ece[0x20];
e281682b
SM		 8318};
8319
8320struct mlx5_ifc_create_qp_in_bits {
8321 u8 opcode[0x10];
4ac63ec7 8322 u8 uid[0x10];
e281682b 8323
b4ff3a36 8324 u8 reserved_at_20[0x10];
e281682b
SM		 8325 u8 op_mod[0x10];
8326
4dca6509
MG		 8327 u8 reserved_at_40[0x8];
8328 u8 input_qpn[0x18];
e281682b 8329
4dca6509 8330 u8 reserved_at_60[0x20];
e281682b
SM		 8331 u8 opt_param_mask[0x20];
8332
6b646a7e 8333 u8 ece[0x20];
e281682b
SM		 8334
8335 struct mlx5_ifc_qpc_bits qpc;
8336
bd371975
LR		 8337 u8 reserved_at_800[0x60];
8338
8339 u8 wq_umem_valid[0x1];
8340 u8 reserved_at_861[0x1f];
e281682b 8341
b6ca09cb 8342 u8 pas[][0x40];
e281682b
SM		 8343};
8344
8345struct mlx5_ifc_create_psv_out_bits {
8346 u8 status[0x8];
b4ff3a36 8347 u8 reserved_at_8[0x18];
e281682b
SM		 8348
8349 u8 syndrome[0x20];
8350
b4ff3a36 8351 u8 reserved_at_40[0x40];
e281682b 8352
b4ff3a36 8353 u8 reserved_at_80[0x8];
e281682b
SM		 8354 u8 psv0_index[0x18];
8355
b4ff3a36 8356 u8 reserved_at_a0[0x8];
e281682b
SM		 8357 u8 psv1_index[0x18];
8358
b4ff3a36 8359 u8 reserved_at_c0[0x8];
e281682b
SM		 8360 u8 psv2_index[0x18];
8361
b4ff3a36 8362 u8 reserved_at_e0[0x8];
e281682b
SM		 8363 u8 psv3_index[0x18];
8364};
8365
8366struct mlx5_ifc_create_psv_in_bits {
8367 u8 opcode[0x10];
b4ff3a36 8368 u8 reserved_at_10[0x10];
e281682b 8369
b4ff3a36 8370 u8 reserved_at_20[0x10];
e281682b
SM		 8371 u8 op_mod[0x10];
8372
8373 u8 num_psv[0x4];
b4ff3a36 8374 u8 reserved_at_44[0x4];
e281682b
SM		 8375 u8 pd[0x18];
8376
b4ff3a36 8377 u8 reserved_at_60[0x20];
e281682b
SM		 8378};
8379
8380struct mlx5_ifc_create_mkey_out_bits {
8381 u8 status[0x8];
b4ff3a36 8382 u8 reserved_at_8[0x18];
e281682b
SM		 8383
8384 u8 syndrome[0x20];
8385
b4ff3a36 8386 u8 reserved_at_40[0x8];
e281682b
SM		 8387 u8 mkey_index[0x18];
8388
b4ff3a36 8389 u8 reserved_at_60[0x20];
e281682b
SM		 8390};
8391
8392struct mlx5_ifc_create_mkey_in_bits {
8393 u8 opcode[0x10];
8a06a79b 8394 u8 uid[0x10];
e281682b 8395
b4ff3a36 8396 u8 reserved_at_20[0x10];
e281682b
SM		 8397 u8 op_mod[0x10];
8398
b4ff3a36 8399 u8 reserved_at_40[0x20];
e281682b
SM		 8400
8401 u8 pg_access[0x1];
bd371975
LR		 8402 u8 mkey_umem_valid[0x1];
8403 u8 reserved_at_62[0x1e];
e281682b
SM		 8404
8405 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8406
b4ff3a36 8407 u8 reserved_at_280[0x80];
e281682b
SM		 8408
8409 u8 translations_octword_actual_size[0x20];
8410
b4ff3a36 8411 u8 reserved_at_320[0x560];
e281682b 8412
b6ca09cb 8413 u8 klm_pas_mtt[][0x20];
e281682b
SM		 8414};
8415
97b5484e
AV		 8416enum {
8417 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8418 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8419 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8420 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8421 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8422 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8423 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8424};
8425
e281682b
SM		 8426struct mlx5_ifc_create_flow_table_out_bits {
8427 u8 status[0x8];
97b5484e 8428 u8 icm_address_63_40[0x18];
e281682b
SM		 8429
8430 u8 syndrome[0x20];
8431
97b5484e 8432 u8 icm_address_39_32[0x8];
e281682b
SM		 8433 u8 table_id[0x18];
8434
97b5484e 8435 u8 icm_address_31_0[0x20];
0c90e9c6
MG		 8436};
8437
e281682b
SM		 8438struct mlx5_ifc_create_flow_table_in_bits {
8439 u8 opcode[0x10];
b4ff3a36 8440 u8 reserved_at_10[0x10];
e281682b 8441
b4ff3a36 8442 u8 reserved_at_20[0x10];
e281682b
SM		 8443 u8 op_mod[0x10];
8444
7d5e1423
SM		 8445 u8 other_vport[0x1];
8446 u8 reserved_at_41[0xf];
8447 u8 vport_number[0x10];
8448
8449 u8 reserved_at_60[0x20];
e281682b
SM		 8450
8451 u8 table_type[0x8];
b4ff3a36 8452 u8 reserved_at_88[0x18];
e281682b 8453
b4ff3a36 8454 u8 reserved_at_a0[0x20];
e281682b 8455
0c90e9c6 8456 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 8457};
8458
8459struct mlx5_ifc_create_flow_group_out_bits {
8460 u8 status[0x8];
b4ff3a36 8461 u8 reserved_at_8[0x18];
e281682b
SM		 8462
8463 u8 syndrome[0x20];
8464
b4ff3a36 8465 u8 reserved_at_40[0x8];
e281682b
SM		 8466 u8 group_id[0x18];
8467
b4ff3a36 8468 u8 reserved_at_60[0x20];
e281682b
SM		 8469};
8470
e7e2519e
MG		 8471enum {
8472 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8473 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8474};
8475
e281682b 8476enum {
71c6e863
AL		 8477 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8478 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8479 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8480 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 8481};
8482
8483struct mlx5_ifc_create_flow_group_in_bits {
8484 u8 opcode[0x10];
b4ff3a36 8485 u8 reserved_at_10[0x10];
e281682b 8486
b4ff3a36 8487 u8 reserved_at_20[0x10];
e281682b
SM		 8488 u8 op_mod[0x10];
8489
7d5e1423
SM		 8490 u8 other_vport[0x1];
8491 u8 reserved_at_41[0xf];
8492 u8 vport_number[0x10];
8493
8494 u8 reserved_at_60[0x20];
e281682b
SM		 8495
8496 u8 table_type[0x8];
e7e2519e
MG		 8497 u8 reserved_at_88[0x4];
8498 u8 group_type[0x4];
8499 u8 reserved_at_90[0x10];
e281682b 8500
b4ff3a36 8501 u8 reserved_at_a0[0x8];
e281682b
SM		 8502 u8 table_id[0x18];
8503
3e99df87
SK		 8504 u8 source_eswitch_owner_vhca_id_valid[0x1];
8505
8506 u8 reserved_at_c1[0x1f];
e281682b
SM		 8507
8508 u8 start_flow_index[0x20];
8509
b4ff3a36 8510 u8 reserved_at_100[0x20];
e281682b
SM		 8511
8512 u8 end_flow_index[0x20];
8513
e7e2519e
MG		 8514 u8 reserved_at_140[0x10];
8515 u8 match_definer_id[0x10];
8516
8517 u8 reserved_at_160[0x80];
e281682b 8518
b4ff3a36 8519 u8 reserved_at_1e0[0x18];
e281682b
SM		 8520 u8 match_criteria_enable[0x8];
8521
8522 struct mlx5_ifc_fte_match_param_bits match_criteria;
8523
b4ff3a36 8524 u8 reserved_at_1200[0xe00];
e281682b
SM		 8525};
8526
8527struct mlx5_ifc_create_eq_out_bits {
8528 u8 status[0x8];
b4ff3a36 8529 u8 reserved_at_8[0x18];
e281682b
SM		 8530
8531 u8 syndrome[0x20];
8532
b4ff3a36 8533 u8 reserved_at_40[0x18];
e281682b
SM		 8534 u8 eq_number[0x8];
8535
b4ff3a36 8536 u8 reserved_at_60[0x20];
e281682b
SM		 8537};
8538
8539struct mlx5_ifc_create_eq_in_bits {
8540 u8 opcode[0x10];
c191f934 8541 u8 uid[0x10];
e281682b 8542
b4ff3a36 8543 u8 reserved_at_20[0x10];
e281682b
SM		 8544 u8 op_mod[0x10];
8545
b4ff3a36 8546 u8 reserved_at_40[0x40];
e281682b
SM		 8547
8548 struct mlx5_ifc_eqc_bits eq_context_entry;
8549
b4ff3a36 8550 u8 reserved_at_280[0x40];
e281682b 8551
b9a7ba55 8552 u8 event_bitmask[4][0x40];
e281682b 8553
b9a7ba55 8554 u8 reserved_at_3c0[0x4c0];
e281682b 8555
b6ca09cb 8556 u8 pas[][0x40];
e281682b
SM		 8557};
8558
8559struct mlx5_ifc_create_dct_out_bits {
8560 u8 status[0x8];
b4ff3a36 8561 u8 reserved_at_8[0x18];
e281682b
SM		 8562
8563 u8 syndrome[0x20];
8564
b4ff3a36 8565 u8 reserved_at_40[0x8];
e281682b
SM		 8566 u8 dctn[0x18];
8567
a645a89d 8568 u8 ece[0x20];
e281682b
SM		 8569};
8570
8571struct mlx5_ifc_create_dct_in_bits {
8572 u8 opcode[0x10];
774ea6ee 8573 u8 uid[0x10];
e281682b 8574
b4ff3a36 8575 u8 reserved_at_20[0x10];
e281682b
SM		 8576 u8 op_mod[0x10];
8577
b4ff3a36 8578 u8 reserved_at_40[0x40];
e281682b
SM		 8579
8580 struct mlx5_ifc_dctc_bits dct_context_entry;
8581
b4ff3a36 8582 u8 reserved_at_280[0x180];
e281682b
SM		 8583};
8584
8585struct mlx5_ifc_create_cq_out_bits {
8586 u8 status[0x8];
b4ff3a36 8587 u8 reserved_at_8[0x18];
e281682b
SM		 8588
8589 u8 syndrome[0x20];
8590
b4ff3a36 8591 u8 reserved_at_40[0x8];
e281682b
SM		 8592 u8 cqn[0x18];
8593
b4ff3a36 8594 u8 reserved_at_60[0x20];
e281682b
SM		 8595};
8596
8597struct mlx5_ifc_create_cq_in_bits {
8598 u8 opcode[0x10];
9ba481e2 8599 u8 uid[0x10];
e281682b 8600
b4ff3a36 8601 u8 reserved_at_20[0x10];
e281682b
SM		 8602 u8 op_mod[0x10];
8603
b4ff3a36 8604 u8 reserved_at_40[0x40];
e281682b
SM		 8605
8606 struct mlx5_ifc_cqc_bits cq_context;
8607
bd371975
LR		 8608 u8 reserved_at_280[0x60];
8609
8610 u8 cq_umem_valid[0x1];
8611 u8 reserved_at_2e1[0x59f];
e281682b 8612
b6ca09cb 8613 u8 pas[][0x40];
e281682b
SM		 8614};
8615
8616struct mlx5_ifc_config_int_moderation_out_bits {
8617 u8 status[0x8];
b4ff3a36 8618 u8 reserved_at_8[0x18];
e281682b
SM		 8619
8620 u8 syndrome[0x20];
8621
b4ff3a36 8622 u8 reserved_at_40[0x4];
e281682b
SM		 8623 u8 min_delay[0xc];
8624 u8 int_vector[0x10];
8625
b4ff3a36 8626 u8 reserved_at_60[0x20];
e281682b
SM		 8627};
8628
8629enum {
8630 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8631 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8632};
8633
8634struct mlx5_ifc_config_int_moderation_in_bits {
8635 u8 opcode[0x10];
b4ff3a36 8636 u8 reserved_at_10[0x10];
e281682b 8637
b4ff3a36 8638 u8 reserved_at_20[0x10];
e281682b
SM		 8639 u8 op_mod[0x10];
8640
b4ff3a36 8641 u8 reserved_at_40[0x4];
e281682b
SM		 8642 u8 min_delay[0xc];
8643 u8 int_vector[0x10];
8644
b4ff3a36 8645 u8 reserved_at_60[0x20];
e281682b
SM		 8646};
8647
8648struct mlx5_ifc_attach_to_mcg_out_bits {
8649 u8 status[0x8];
b4ff3a36 8650 u8 reserved_at_8[0x18];
e281682b
SM		 8651
8652 u8 syndrome[0x20];
8653
b4ff3a36 8654 u8 reserved_at_40[0x40];
e281682b
SM		 8655};
8656
8657struct mlx5_ifc_attach_to_mcg_in_bits {
8658 u8 opcode[0x10];
bd371975 8659 u8 uid[0x10];
e281682b 8660
b4ff3a36 8661 u8 reserved_at_20[0x10];
e281682b
SM		 8662 u8 op_mod[0x10];
8663
b4ff3a36 8664 u8 reserved_at_40[0x8];
e281682b
SM		 8665 u8 qpn[0x18];
8666
b4ff3a36 8667 u8 reserved_at_60[0x20];
e281682b
SM		 8668
8669 u8 multicast_gid[16][0x8];
8670};
8671
7486216b
SM		 8672struct mlx5_ifc_arm_xrq_out_bits {
8673 u8 status[0x8];
8674 u8 reserved_at_8[0x18];
8675
8676 u8 syndrome[0x20];
8677
8678 u8 reserved_at_40[0x40];
8679};
8680
8681struct mlx5_ifc_arm_xrq_in_bits {
8682 u8 opcode[0x10];
8683 u8 reserved_at_10[0x10];
8684
8685 u8 reserved_at_20[0x10];
8686 u8 op_mod[0x10];
8687
8688 u8 reserved_at_40[0x8];
8689 u8 xrqn[0x18];
8690
8691 u8 reserved_at_60[0x10];
8692 u8 lwm[0x10];
8693};
8694
e281682b
SM		 8695struct mlx5_ifc_arm_xrc_srq_out_bits {
8696 u8 status[0x8];
b4ff3a36 8697 u8 reserved_at_8[0x18];
e281682b
SM		 8698
8699 u8 syndrome[0x20];
8700
b4ff3a36 8701 u8 reserved_at_40[0x40];
e281682b
SM		 8702};
8703
8704enum {
8705 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8706};
8707
8708struct mlx5_ifc_arm_xrc_srq_in_bits {
8709 u8 opcode[0x10];
a0d8c054 8710 u8 uid[0x10];
e281682b 8711
b4ff3a36 8712 u8 reserved_at_20[0x10];
e281682b
SM		 8713 u8 op_mod[0x10];
8714
b4ff3a36 8715 u8 reserved_at_40[0x8];
e281682b
SM		 8716 u8 xrc_srqn[0x18];
8717
b4ff3a36 8718 u8 reserved_at_60[0x10];
e281682b
SM		 8719 u8 lwm[0x10];
8720};
8721
8722struct mlx5_ifc_arm_rq_out_bits {
8723 u8 status[0x8];
b4ff3a36 8724 u8 reserved_at_8[0x18];
e281682b
SM		 8725
8726 u8 syndrome[0x20];
8727
b4ff3a36 8728 u8 reserved_at_40[0x40];
e281682b
SM		 8729};
8730
8731enum {
7486216b
SM		 8732 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8733 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 8734};
8735
8736struct mlx5_ifc_arm_rq_in_bits {
8737 u8 opcode[0x10];
a0d8c054 8738 u8 uid[0x10];
e281682b 8739
b4ff3a36 8740 u8 reserved_at_20[0x10];
e281682b
SM		 8741 u8 op_mod[0x10];
8742
b4ff3a36 8743 u8 reserved_at_40[0x8];
e281682b
SM		 8744 u8 srq_number[0x18];
8745
b4ff3a36 8746 u8 reserved_at_60[0x10];
e281682b
SM		 8747 u8 lwm[0x10];
8748};
8749
8750struct mlx5_ifc_arm_dct_out_bits {
8751 u8 status[0x8];
b4ff3a36 8752 u8 reserved_at_8[0x18];
e281682b
SM		 8753
8754 u8 syndrome[0x20];
8755
b4ff3a36 8756 u8 reserved_at_40[0x40];
e281682b
SM		 8757};
8758
8759struct mlx5_ifc_arm_dct_in_bits {
8760 u8 opcode[0x10];
b4ff3a36 8761 u8 reserved_at_10[0x10];
e281682b 8762
b4ff3a36 8763 u8 reserved_at_20[0x10];
e281682b
SM		 8764 u8 op_mod[0x10];
8765
b4ff3a36 8766 u8 reserved_at_40[0x8];
e281682b
SM		 8767 u8 dct_number[0x18];
8768
b4ff3a36 8769 u8 reserved_at_60[0x20];
e281682b
SM		 8770};
8771
8772struct mlx5_ifc_alloc_xrcd_out_bits {
8773 u8 status[0x8];
b4ff3a36 8774 u8 reserved_at_8[0x18];
e281682b
SM		 8775
8776 u8 syndrome[0x20];
8777
b4ff3a36 8778 u8 reserved_at_40[0x8];
e281682b
SM		 8779 u8 xrcd[0x18];
8780
b4ff3a36 8781 u8 reserved_at_60[0x20];
e281682b
SM		 8782};
8783
8784struct mlx5_ifc_alloc_xrcd_in_bits {
8785 u8 opcode[0x10];
bd371975 8786 u8 uid[0x10];
e281682b 8787
b4ff3a36 8788 u8 reserved_at_20[0x10];
e281682b
SM		 8789 u8 op_mod[0x10];
8790
b4ff3a36 8791 u8 reserved_at_40[0x40];
e281682b
SM		 8792};
8793
8794struct mlx5_ifc_alloc_uar_out_bits {
8795 u8 status[0x8];
b4ff3a36 8796 u8 reserved_at_8[0x18];
e281682b
SM		 8797
8798 u8 syndrome[0x20];
8799
b4ff3a36 8800 u8 reserved_at_40[0x8];
e281682b
SM		 8801 u8 uar[0x18];
8802
b4ff3a36 8803 u8 reserved_at_60[0x20];
e281682b
SM		 8804};
8805
8806struct mlx5_ifc_alloc_uar_in_bits {
8807 u8 opcode[0x10];
8de1e9b0 8808 u8 uid[0x10];
e281682b 8809
b4ff3a36 8810 u8 reserved_at_20[0x10];
e281682b
SM		 8811 u8 op_mod[0x10];
8812
b4ff3a36 8813 u8 reserved_at_40[0x40];
e281682b
SM		 8814};
8815
8816struct mlx5_ifc_alloc_transport_domain_out_bits {
8817 u8 status[0x8];
b4ff3a36 8818 u8 reserved_at_8[0x18];
e281682b
SM		 8819
8820 u8 syndrome[0x20];
8821
b4ff3a36 8822 u8 reserved_at_40[0x8];
e281682b
SM		 8823 u8 transport_domain[0x18];
8824
b4ff3a36 8825 u8 reserved_at_60[0x20];
e281682b
SM		 8826};
8827
8828struct mlx5_ifc_alloc_transport_domain_in_bits {
8829 u8 opcode[0x10];
71bef2fd 8830 u8 uid[0x10];
e281682b 8831
b4ff3a36 8832 u8 reserved_at_20[0x10];
e281682b
SM		 8833 u8 op_mod[0x10];
8834
b4ff3a36 8835 u8 reserved_at_40[0x40];
e281682b
SM		 8836};
8837
8838struct mlx5_ifc_alloc_q_counter_out_bits {
8839 u8 status[0x8];
b4ff3a36 8840 u8 reserved_at_8[0x18];
e281682b
SM		 8841
8842 u8 syndrome[0x20];
8843
b4ff3a36 8844 u8 reserved_at_40[0x18];
e281682b
SM		 8845 u8 counter_set_id[0x8];
8846
b4ff3a36 8847 u8 reserved_at_60[0x20];
e281682b
SM		 8848};
8849
8850struct mlx5_ifc_alloc_q_counter_in_bits {
8851 u8 opcode[0x10];
2acc7957 8852 u8 uid[0x10];
e281682b 8853
b4ff3a36 8854 u8 reserved_at_20[0x10];
e281682b
SM		 8855 u8 op_mod[0x10];
8856
b4ff3a36 8857 u8 reserved_at_40[0x40];
e281682b
SM		 8858};
8859
8860struct mlx5_ifc_alloc_pd_out_bits {
8861 u8 status[0x8];
b4ff3a36 8862 u8 reserved_at_8[0x18];
e281682b
SM		 8863
8864 u8 syndrome[0x20];
8865
b4ff3a36 8866 u8 reserved_at_40[0x8];
e281682b
SM		 8867 u8 pd[0x18];
8868
b4ff3a36 8869 u8 reserved_at_60[0x20];
e281682b
SM		 8870};
8871
8872struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 8873 u8 opcode[0x10];
bd371975 8874 u8 uid[0x10];
9dc0b289
AV		 8875
8876 u8 reserved_at_20[0x10];
8877 u8 op_mod[0x10];
8878
8879 u8 reserved_at_40[0x40];
8880};
8881
8882struct mlx5_ifc_alloc_flow_counter_out_bits {
8883 u8 status[0x8];
8884 u8 reserved_at_8[0x18];
8885
8886 u8 syndrome[0x20];
8887
a8ffcc74 8888 u8 flow_counter_id[0x20];
9dc0b289
AV		 8889
8890 u8 reserved_at_60[0x20];
8891};
8892
8893struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 8894 u8 opcode[0x10];
b4ff3a36 8895 u8 reserved_at_10[0x10];
e281682b 8896
b4ff3a36 8897 u8 reserved_at_20[0x10];
e281682b
SM		 8898 u8 op_mod[0x10];
8899
8536a6bf
GT		 8900 u8 reserved_at_40[0x38];
8901 u8 flow_counter_bulk[0x8];
e281682b
SM		 8902};
8903
8904struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8905 u8 status[0x8];
b4ff3a36 8906 u8 reserved_at_8[0x18];
e281682b
SM		 8907
8908 u8 syndrome[0x20];
8909
b4ff3a36 8910 u8 reserved_at_40[0x40];
e281682b
SM		 8911};
8912
8913struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8914 u8 opcode[0x10];
b4ff3a36 8915 u8 reserved_at_10[0x10];
e281682b 8916
b4ff3a36 8917 u8 reserved_at_20[0x10];
e281682b
SM		 8918 u8 op_mod[0x10];
8919
b4ff3a36 8920 u8 reserved_at_40[0x20];
e281682b 8921
b4ff3a36 8922 u8 reserved_at_60[0x10];
e281682b
SM		 8923 u8 vxlan_udp_port[0x10];
8924};
8925
37e92a9d 8926struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 8927 u8 status[0x8];
8928 u8 reserved_at_8[0x18];
8929
8930 u8 syndrome[0x20];
8931
8932 u8 reserved_at_40[0x40];
8933};
8934
1326034b
YH		 8935struct mlx5_ifc_set_pp_rate_limit_context_bits {
8936 u8 rate_limit[0x20];
8937
8938 u8 burst_upper_bound[0x20];
8939
8940 u8 reserved_at_40[0x10];
8941 u8 typical_packet_size[0x10];
8942
8943 u8 reserved_at_60[0x120];
8944};
8945
37e92a9d 8946struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b 8947 u8 opcode[0x10];
1326034b 8948 u8 uid[0x10];
7486216b
SM		 8949
8950 u8 reserved_at_20[0x10];
8951 u8 op_mod[0x10];
8952
8953 u8 reserved_at_40[0x10];
8954 u8 rate_limit_index[0x10];
8955
8956 u8 reserved_at_60[0x20];
8957
1326034b 8958 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
7486216b
SM		 8959};
8960
e281682b
SM		 8961struct mlx5_ifc_access_register_out_bits {
8962 u8 status[0x8];
b4ff3a36 8963 u8 reserved_at_8[0x18];
e281682b
SM		 8964
8965 u8 syndrome[0x20];
8966
b4ff3a36 8967 u8 reserved_at_40[0x40];
e281682b 8968
b6ca09cb 8969 u8 register_data[][0x20];
e281682b
SM		 8970};
8971
8972enum {
8973 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8974 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8975};
8976
8977struct mlx5_ifc_access_register_in_bits {
8978 u8 opcode[0x10];
b4ff3a36 8979 u8 reserved_at_10[0x10];
e281682b 8980
b4ff3a36 8981 u8 reserved_at_20[0x10];
e281682b
SM		 8982 u8 op_mod[0x10];
8983
b4ff3a36 8984 u8 reserved_at_40[0x10];
e281682b
SM		 8985 u8 register_id[0x10];
8986
8987 u8 argument[0x20];
8988
b6ca09cb 8989 u8 register_data[][0x20];
e281682b
SM		 8990};
8991
8992struct mlx5_ifc_sltp_reg_bits {
8993 u8 status[0x4];
8994 u8 version[0x4];
8995 u8 local_port[0x8];
8996 u8 pnat[0x2];
b4ff3a36 8997 u8 reserved_at_12[0x2];
e281682b 8998 u8 lane[0x4];
b4ff3a36 8999 u8 reserved_at_18[0x8];
e281682b 9000
b4ff3a36 9001 u8 reserved_at_20[0x20];
e281682b 9002
b4ff3a36 9003 u8 reserved_at_40[0x7];
e281682b
SM		 9004 u8 polarity[0x1];
9005 u8 ob_tap0[0x8];
9006 u8 ob_tap1[0x8];
9007 u8 ob_tap2[0x8];
9008
b4ff3a36 9009 u8 reserved_at_60[0xc];
e281682b
SM		 9010 u8 ob_preemp_mode[0x4];
9011 u8 ob_reg[0x8];
9012 u8 ob_bias[0x8];
9013
b4ff3a36 9014 u8 reserved_at_80[0x20];
e281682b
SM		 9015};
9016
9017struct mlx5_ifc_slrg_reg_bits {
9018 u8 status[0x4];
9019 u8 version[0x4];
9020 u8 local_port[0x8];
9021 u8 pnat[0x2];
b4ff3a36 9022 u8 reserved_at_12[0x2];
e281682b 9023 u8 lane[0x4];
b4ff3a36 9024 u8 reserved_at_18[0x8];
e281682b
SM		 9025
9026 u8 time_to_link_up[0x10];
b4ff3a36 9027 u8 reserved_at_30[0xc];
e281682b
SM		 9028 u8 grade_lane_speed[0x4];
9029
9030 u8 grade_version[0x8];
9031 u8 grade[0x18];
9032
b4ff3a36 9033 u8 reserved_at_60[0x4];
e281682b
SM		 9034 u8 height_grade_type[0x4];
9035 u8 height_grade[0x18];
9036
9037 u8 height_dz[0x10];
9038 u8 height_dv[0x10];
9039
b4ff3a36 9040 u8 reserved_at_a0[0x10];
e281682b
SM		 9041 u8 height_sigma[0x10];
9042
b4ff3a36 9043 u8 reserved_at_c0[0x20];
e281682b 9044
b4ff3a36 9045 u8 reserved_at_e0[0x4];
e281682b
SM		 9046 u8 phase_grade_type[0x4];
9047 u8 phase_grade[0x18];
9048
b4ff3a36 9049 u8 reserved_at_100[0x8];
e281682b 9050 u8 phase_eo_pos[0x8];
b4ff3a36 9051 u8 reserved_at_110[0x8];
e281682b
SM		 9052 u8 phase_eo_neg[0x8];
9053
9054 u8 ffe_set_tested[0x10];
9055 u8 test_errors_per_lane[0x10];
9056};
9057
9058struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 9059 u8 reserved_at_0[0x8];
e281682b 9060 u8 local_port[0x8];
b4ff3a36 9061 u8 reserved_at_10[0x10];
e281682b 9062
b4ff3a36 9063 u8 reserved_at_20[0x1c];
e281682b
SM		 9064 u8 vl_hw_cap[0x4];
9065
b4ff3a36 9066 u8 reserved_at_40[0x1c];
e281682b
SM		 9067 u8 vl_admin[0x4];
9068
b4ff3a36 9069 u8 reserved_at_60[0x1c];
e281682b
SM		 9070 u8 vl_operational[0x4];
9071};
9072
9073struct mlx5_ifc_pude_reg_bits {
9074 u8 swid[0x8];
9075 u8 local_port[0x8];
b4ff3a36 9076 u8 reserved_at_10[0x4];
e281682b 9077 u8 admin_status[0x4];
b4ff3a36 9078 u8 reserved_at_18[0x4];
e281682b
SM		 9079 u8 oper_status[0x4];
9080
b4ff3a36 9081 u8 reserved_at_20[0x60];
e281682b
SM		 9082};
9083
9084struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 9085 u8 reserved_at_0[0x1];
7486216b 9086 u8 an_disable_admin[0x1];
e7e31ca4
BW		 9087 u8 an_disable_cap[0x1];
9088 u8 reserved_at_3[0x5];
e281682b 9089 u8 local_port[0x8];
b4ff3a36 9090 u8 reserved_at_10[0xd];
e281682b
SM		 9091 u8 proto_mask[0x3];
9092
7486216b 9093 u8 an_status[0x4];
dc392fc5
MB		 9094 u8 reserved_at_24[0xc];
9095 u8 data_rate_oper[0x10];
a0a89989
AL		 9096
9097 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 9098
9099 u8 eth_proto_capability[0x20];
9100
9101 u8 ib_link_width_capability[0x10];
9102 u8 ib_proto_capability[0x10];
9103
a0a89989 9104 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 9105
9106 u8 eth_proto_admin[0x20];
9107
9108 u8 ib_link_width_admin[0x10];
9109 u8 ib_proto_admin[0x10];
9110
a0a89989 9111 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 9112
9113 u8 eth_proto_oper[0x20];
9114
9115 u8 ib_link_width_oper[0x10];
9116 u8 ib_proto_oper[0x10];
9117
5b4793f8
EBE		 9118 u8 reserved_at_160[0x1c];
9119 u8 connector_type[0x4];
e281682b
SM		 9120
9121 u8 eth_proto_lp_advertise[0x20];
9122
b4ff3a36 9123 u8 reserved_at_1a0[0x60];
e281682b
SM		 9124};
9125
7d5e1423
SM		 9126struct mlx5_ifc_mlcr_reg_bits {
9127 u8 reserved_at_0[0x8];
9128 u8 local_port[0x8];
9129 u8 reserved_at_10[0x20];
9130
9131 u8 beacon_duration[0x10];
9132 u8 reserved_at_40[0x10];
9133
9134 u8 beacon_remain[0x10];
9135};
9136
e281682b 9137struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 9138 u8 reserved_at_0[0x20];
e281682b
SM		 9139
9140 u8 algorithm_options[0x10];
b4ff3a36 9141 u8 reserved_at_30[0x4];
e281682b
SM		 9142 u8 repetitions_mode[0x4];
9143 u8 num_of_repetitions[0x8];
9144
9145 u8 grade_version[0x8];
9146 u8 height_grade_type[0x4];
9147 u8 phase_grade_type[0x4];
9148 u8 height_grade_weight[0x8];
9149 u8 phase_grade_weight[0x8];
9150
9151 u8 gisim_measure_bits[0x10];
9152 u8 adaptive_tap_measure_bits[0x10];
9153
9154 u8 ber_bath_high_error_threshold[0x10];
9155 u8 ber_bath_mid_error_threshold[0x10];
9156
9157 u8 ber_bath_low_error_threshold[0x10];
9158 u8 one_ratio_high_threshold[0x10];
9159
9160 u8 one_ratio_high_mid_threshold[0x10];
9161 u8 one_ratio_low_mid_threshold[0x10];
9162
9163 u8 one_ratio_low_threshold[0x10];
9164 u8 ndeo_error_threshold[0x10];
9165
9166 u8 mixer_offset_step_size[0x10];
b4ff3a36 9167 u8 reserved_at_110[0x8];
e281682b
SM		 9168 u8 mix90_phase_for_voltage_bath[0x8];
9169
9170 u8 mixer_offset_start[0x10];
9171 u8 mixer_offset_end[0x10];
9172
b4ff3a36 9173 u8 reserved_at_140[0x15];
e281682b
SM		 9174 u8 ber_test_time[0xb];
9175};
9176
9177struct mlx5_ifc_pspa_reg_bits {
9178 u8 swid[0x8];
9179 u8 local_port[0x8];
9180 u8 sub_port[0x8];
b4ff3a36 9181 u8 reserved_at_18[0x8];
e281682b 9182
b4ff3a36 9183 u8 reserved_at_20[0x20];
e281682b
SM		 9184};
9185
9186struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 9187 u8 reserved_at_0[0x8];
e281682b 9188 u8 local_port[0x8];
b4ff3a36 9189 u8 reserved_at_10[0x5];
e281682b 9190 u8 prio[0x3];
b4ff3a36 9191 u8 reserved_at_18[0x6];
e281682b
SM		 9192 u8 mode[0x2];
9193
b4ff3a36 9194 u8 reserved_at_20[0x20];
e281682b 9195
b4ff3a36 9196 u8 reserved_at_40[0x10];
e281682b
SM		 9197 u8 min_threshold[0x10];
9198
b4ff3a36 9199 u8 reserved_at_60[0x10];
e281682b
SM		 9200 u8 max_threshold[0x10];
9201
b4ff3a36 9202 u8 reserved_at_80[0x10];
e281682b
SM		 9203 u8 mark_probability_denominator[0x10];
9204
b4ff3a36 9205 u8 reserved_at_a0[0x60];
e281682b
SM		 9206};
9207
9208struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 9209 u8 reserved_at_0[0x8];
e281682b 9210 u8 local_port[0x8];
b4ff3a36 9211 u8 reserved_at_10[0x10];
e281682b 9212
b4ff3a36 9213 u8 reserved_at_20[0x60];
e281682b 9214
b4ff3a36 9215 u8 reserved_at_80[0x1c];
e281682b
SM		 9216 u8 wrps_admin[0x4];
9217
b4ff3a36 9218 u8 reserved_at_a0[0x1c];
e281682b
SM		 9219 u8 wrps_status[0x4];
9220
b4ff3a36 9221 u8 reserved_at_c0[0x8];
e281682b 9222 u8 up_threshold[0x8];
b4ff3a36 9223 u8 reserved_at_d0[0x8];
e281682b
SM		 9224 u8 down_threshold[0x8];
9225
b4ff3a36 9226 u8 reserved_at_e0[0x20];
e281682b 9227
b4ff3a36 9228 u8 reserved_at_100[0x1c];
e281682b
SM		 9229 u8 srps_admin[0x4];
9230
b4ff3a36 9231 u8 reserved_at_120[0x1c];
e281682b
SM		 9232 u8 srps_status[0x4];
9233
b4ff3a36 9234 u8 reserved_at_140[0x40];
e281682b
SM		 9235};
9236
9237struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 9238 u8 reserved_at_0[0x8];
e281682b 9239 u8 local_port[0x8];
b4ff3a36 9240 u8 reserved_at_10[0x10];
e281682b 9241
b4ff3a36 9242 u8 reserved_at_20[0x8];
e281682b 9243 u8 lb_cap[0x8];
b4ff3a36 9244 u8 reserved_at_30[0x8];
e281682b
SM		 9245 u8 lb_en[0x8];
9246};
9247
9248struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 9249 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 9250 u8 local_port[0x8];
9251 u8 reserved_at_10[0x10];
e281682b 9252
4b5b9c7d 9253 u8 reserved_at_20[0x20];
e281682b 9254
4b5b9c7d
SA		 9255 u8 port_profile_mode[0x8];
9256 u8 static_port_profile[0x8];
9257 u8 active_port_profile[0x8];
9258 u8 reserved_at_58[0x8];
e281682b 9259
4b5b9c7d
SA		 9260 u8 retransmission_active[0x8];
9261 u8 fec_mode_active[0x18];
e281682b 9262
4b5b9c7d
SA		 9263 u8 rs_fec_correction_bypass_cap[0x4];
9264 u8 reserved_at_84[0x8];
9265 u8 fec_override_cap_56g[0x4];
9266 u8 fec_override_cap_100g[0x4];
9267 u8 fec_override_cap_50g[0x4];
9268 u8 fec_override_cap_25g[0x4];
9269 u8 fec_override_cap_10g_40g[0x4];
9270
9271 u8 rs_fec_correction_bypass_admin[0x4];
9272 u8 reserved_at_a4[0x8];
9273 u8 fec_override_admin_56g[0x4];
9274 u8 fec_override_admin_100g[0x4];
9275 u8 fec_override_admin_50g[0x4];
9276 u8 fec_override_admin_25g[0x4];
9277 u8 fec_override_admin_10g_40g[0x4];
a58837f5
AL		 9278
9279 u8 fec_override_cap_400g_8x[0x10];
9280 u8 fec_override_cap_200g_4x[0x10];
9281
9282 u8 fec_override_cap_100g_2x[0x10];
9283 u8 fec_override_cap_50g_1x[0x10];
9284
9285 u8 fec_override_admin_400g_8x[0x10];
9286 u8 fec_override_admin_200g_4x[0x10];
9287
9288 u8 fec_override_admin_100g_2x[0x10];
9289 u8 fec_override_admin_50g_1x[0x10];
ce28f0fd
AL		 9290
9291 u8 reserved_at_140[0x140];
e281682b
SM		 9292};
9293
9294struct mlx5_ifc_ppcnt_reg_bits {
9295 u8 swid[0x8];
9296 u8 local_port[0x8];
9297 u8 pnat[0x2];
b4ff3a36 9298 u8 reserved_at_12[0x8];
e281682b
SM		 9299 u8 grp[0x6];
9300
9301 u8 clr[0x1];
b4ff3a36 9302 u8 reserved_at_21[0x1c];
e281682b
SM		 9303 u8 prio_tc[0x3];
9304
9305 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9306};
9307
4039049b
AL		 9308struct mlx5_ifc_mpein_reg_bits {
9309 u8 reserved_at_0[0x2];
9310 u8 depth[0x6];
9311 u8 pcie_index[0x8];
9312 u8 node[0x8];
9313 u8 reserved_at_18[0x8];
9314
9315 u8 capability_mask[0x20];
9316
9317 u8 reserved_at_40[0x8];
9318 u8 link_width_enabled[0x8];
9319 u8 link_speed_enabled[0x10];
9320
9321 u8 lane0_physical_position[0x8];
9322 u8 link_width_active[0x8];
9323 u8 link_speed_active[0x10];
9324
9325 u8 num_of_pfs[0x10];
9326 u8 num_of_vfs[0x10];
9327
9328 u8 bdf0[0x10];
9329 u8 reserved_at_b0[0x10];
9330
9331 u8 max_read_request_size[0x4];
9332 u8 max_payload_size[0x4];
9333 u8 reserved_at_c8[0x5];
9334 u8 pwr_status[0x3];
9335 u8 port_type[0x4];
9336 u8 reserved_at_d4[0xb];
9337 u8 lane_reversal[0x1];
9338
9339 u8 reserved_at_e0[0x14];
9340 u8 pci_power[0xc];
9341
9342 u8 reserved_at_100[0x20];
9343
9344 u8 device_status[0x10];
9345 u8 port_state[0x8];
9346 u8 reserved_at_138[0x8];
9347
9348 u8 reserved_at_140[0x10];
9349 u8 receiver_detect_result[0x10];
9350
9351 u8 reserved_at_160[0x20];
9352};
9353
8ed1a630
GP		 9354struct mlx5_ifc_mpcnt_reg_bits {
9355 u8 reserved_at_0[0x8];
9356 u8 pcie_index[0x8];
9357 u8 reserved_at_10[0xa];
9358 u8 grp[0x6];
9359
9360 u8 clr[0x1];
9361 u8 reserved_at_21[0x1f];
9362
9363 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9364};
9365
e281682b 9366struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 9367 u8 reserved_at_0[0x3];
e281682b 9368 u8 single_mac[0x1];
b4ff3a36 9369 u8 reserved_at_4[0x4];
e281682b
SM		 9370 u8 local_port[0x8];
9371 u8 mac_47_32[0x10];
9372
9373 u8 mac_31_0[0x20];
9374
b4ff3a36 9375 u8 reserved_at_40[0x40];
e281682b
SM		 9376};
9377
9378struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 9379 u8 reserved_at_0[0x8];
e281682b 9380 u8 local_port[0x8];
b4ff3a36 9381 u8 reserved_at_10[0x10];
e281682b
SM		 9382
9383 u8 max_mtu[0x10];
b4ff3a36 9384 u8 reserved_at_30[0x10];
e281682b
SM		 9385
9386 u8 admin_mtu[0x10];
b4ff3a36 9387 u8 reserved_at_50[0x10];
e281682b
SM		 9388
9389 u8 oper_mtu[0x10];
b4ff3a36 9390 u8 reserved_at_70[0x10];
e281682b
SM		 9391};
9392
9393struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 9394 u8 reserved_at_0[0x8];
e281682b 9395 u8 module[0x8];
b4ff3a36 9396 u8 reserved_at_10[0x10];
e281682b 9397
b4ff3a36 9398 u8 reserved_at_20[0x18];
e281682b
SM		 9399 u8 attenuation_5g[0x8];
9400
b4ff3a36 9401 u8 reserved_at_40[0x18];
e281682b
SM		 9402 u8 attenuation_7g[0x8];
9403
b4ff3a36 9404 u8 reserved_at_60[0x18];
e281682b
SM		 9405 u8 attenuation_12g[0x8];
9406};
9407
9408struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 9409 u8 reserved_at_0[0x8];
e281682b 9410 u8 module[0x8];
b4ff3a36 9411 u8 reserved_at_10[0xc];
e281682b
SM		 9412 u8 module_status[0x4];
9413
b4ff3a36 9414 u8 reserved_at_20[0x60];
e281682b
SM		 9415};
9416
9417struct mlx5_ifc_pmpc_reg_bits {
9418 u8 module_state_updated[32][0x8];
9419};
9420
9421struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 9422 u8 reserved_at_0[0x4];
e281682b
SM		 9423 u8 mlpn_status[0x4];
9424 u8 local_port[0x8];
b4ff3a36 9425 u8 reserved_at_10[0x10];
e281682b
SM		 9426
9427 u8 e[0x1];
b4ff3a36 9428 u8 reserved_at_21[0x1f];
e281682b
SM		 9429};
9430
9431struct mlx5_ifc_pmlp_reg_bits {
9432 u8 rxtx[0x1];
b4ff3a36 9433 u8 reserved_at_1[0x7];
e281682b 9434 u8 local_port[0x8];
b4ff3a36 9435 u8 reserved_at_10[0x8];
e281682b
SM		 9436 u8 width[0x8];
9437
9438 u8 lane0_module_mapping[0x20];
9439
9440 u8 lane1_module_mapping[0x20];
9441
9442 u8 lane2_module_mapping[0x20];
9443
9444 u8 lane3_module_mapping[0x20];
9445
b4ff3a36 9446 u8 reserved_at_a0[0x160];
e281682b
SM		 9447};
9448
9449struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 9450 u8 reserved_at_0[0x8];
e281682b 9451 u8 module[0x8];
b4ff3a36 9452 u8 reserved_at_10[0x4];
e281682b 9453 u8 admin_status[0x4];
b4ff3a36 9454 u8 reserved_at_18[0x4];
e281682b
SM		 9455 u8 oper_status[0x4];
9456
9457 u8 ase[0x1];
9458 u8 ee[0x1];
b4ff3a36 9459 u8 reserved_at_22[0x1c];
e281682b
SM		 9460 u8 e[0x2];
9461
b4ff3a36 9462 u8 reserved_at_40[0x40];
e281682b
SM		 9463};
9464
9465struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 9466 u8 reserved_at_0[0x4];
e281682b 9467 u8 profile_id[0xc];
b4ff3a36 9468 u8 reserved_at_10[0x4];
e281682b 9469 u8 proto_mask[0x4];
b4ff3a36 9470 u8 reserved_at_18[0x8];
e281682b 9471
b4ff3a36 9472 u8 reserved_at_20[0x10];
e281682b
SM		 9473 u8 lane_speed[0x10];
9474
b4ff3a36 9475 u8 reserved_at_40[0x17];
e281682b
SM		 9476 u8 lpbf[0x1];
9477 u8 fec_mode_policy[0x8];
9478
9479 u8 retransmission_capability[0x8];
9480 u8 fec_mode_capability[0x18];
9481
9482 u8 retransmission_support_admin[0x8];
9483 u8 fec_mode_support_admin[0x18];
9484
9485 u8 retransmission_request_admin[0x8];
9486 u8 fec_mode_request_admin[0x18];
9487
b4ff3a36 9488 u8 reserved_at_c0[0x80];
e281682b
SM		 9489};
9490
9491struct mlx5_ifc_plib_reg_bits {
b4ff3a36 9492 u8 reserved_at_0[0x8];
e281682b 9493 u8 local_port[0x8];
b4ff3a36 9494 u8 reserved_at_10[0x8];
e281682b
SM		 9495 u8 ib_port[0x8];
9496
b4ff3a36 9497 u8 reserved_at_20[0x60];
e281682b
SM		 9498};
9499
9500struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 9501 u8 reserved_at_0[0x8];
e281682b 9502 u8 local_port[0x8];
b4ff3a36 9503 u8 reserved_at_10[0xd];
e281682b
SM		 9504 u8 lbf_mode[0x3];
9505
b4ff3a36 9506 u8 reserved_at_20[0x20];
e281682b
SM		 9507};
9508
9509struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 9510 u8 reserved_at_0[0x8];
e281682b 9511 u8 local_port[0x8];
b4ff3a36 9512 u8 reserved_at_10[0x10];
e281682b
SM		 9513
9514 u8 dic[0x1];
b4ff3a36 9515 u8 reserved_at_21[0x19];
e281682b 9516 u8 ipg[0x4];
b4ff3a36 9517 u8 reserved_at_3e[0x2];
e281682b
SM		 9518};
9519
9520struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 9521 u8 reserved_at_0[0x8];
e281682b 9522 u8 local_port[0x8];
b4ff3a36 9523 u8 reserved_at_10[0x10];
e281682b 9524
b4ff3a36 9525 u8 reserved_at_20[0xe0];
e281682b
SM		 9526
9527 u8 port_filter[8][0x20];
9528
9529 u8 port_filter_update_en[8][0x20];
9530};
9531
9532struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 9533 u8 reserved_at_0[0x8];
e281682b 9534 u8 local_port[0x8];
2afa609f
IK		 9535 u8 reserved_at_10[0xb];
9536 u8 ppan_mask_n[0x1];
9537 u8 minor_stall_mask[0x1];
9538 u8 critical_stall_mask[0x1];
9539 u8 reserved_at_1e[0x2];
e281682b
SM		 9540
9541 u8 ppan[0x4];
b4ff3a36 9542 u8 reserved_at_24[0x4];
e281682b 9543 u8 prio_mask_tx[0x8];
b4ff3a36 9544 u8 reserved_at_30[0x8];
e281682b
SM		 9545 u8 prio_mask_rx[0x8];
9546
9547 u8 pptx[0x1];
9548 u8 aptx[0x1];
2afa609f
IK		 9549 u8 pptx_mask_n[0x1];
9550 u8 reserved_at_43[0x5];
e281682b 9551 u8 pfctx[0x8];
b4ff3a36 9552 u8 reserved_at_50[0x10];
e281682b
SM		 9553
9554 u8 pprx[0x1];
9555 u8 aprx[0x1];
2afa609f
IK		 9556 u8 pprx_mask_n[0x1];
9557 u8 reserved_at_63[0x5];
e281682b 9558 u8 pfcrx[0x8];
b4ff3a36 9559 u8 reserved_at_70[0x10];
e281682b 9560
2afa609f
IK		 9561 u8 device_stall_minor_watermark[0x10];
9562 u8 device_stall_critical_watermark[0x10];
9563
9564 u8 reserved_at_a0[0x60];
e281682b
SM		 9565};
9566
9567struct mlx5_ifc_pelc_reg_bits {
9568 u8 op[0x4];
b4ff3a36 9569 u8 reserved_at_4[0x4];
e281682b 9570 u8 local_port[0x8];
b4ff3a36 9571 u8 reserved_at_10[0x10];
e281682b
SM		 9572
9573 u8 op_admin[0x8];
9574 u8 op_capability[0x8];
9575 u8 op_request[0x8];
9576 u8 op_active[0x8];
9577
9578 u8 admin[0x40];
9579
9580 u8 capability[0x40];
9581
9582 u8 request[0x40];
9583
9584 u8 active[0x40];
9585
b4ff3a36 9586 u8 reserved_at_140[0x80];
e281682b
SM		 9587};
9588
9589struct mlx5_ifc_peir_reg_bits {
b4ff3a36 9590 u8 reserved_at_0[0x8];
e281682b 9591 u8 local_port[0x8];
b4ff3a36 9592 u8 reserved_at_10[0x10];
e281682b 9593
b4ff3a36 9594 u8 reserved_at_20[0xc];
e281682b 9595 u8 error_count[0x4];
b4ff3a36 9596 u8 reserved_at_30[0x10];
e281682b 9597
b4ff3a36 9598 u8 reserved_at_40[0xc];
e281682b 9599 u8 lane[0x4];
b4ff3a36 9600 u8 reserved_at_50[0x8];
e281682b
SM		 9601 u8 error_type[0x8];
9602};
9603
5e022dd3
EBE		 9604struct mlx5_ifc_mpegc_reg_bits {
9605 u8 reserved_at_0[0x30];
9606 u8 field_select[0x10];
9607
9608 u8 tx_overflow_sense[0x1];
9609 u8 mark_cqe[0x1];
9610 u8 mark_cnp[0x1];
9611 u8 reserved_at_43[0x1b];
9612 u8 tx_lossy_overflow_oper[0x2];
9613
9614 u8 reserved_at_60[0x100];
9615};
9616
ae02d415
EBE		 9617enum {
9618 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
9619 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
9620 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
9621};
9622
9623struct mlx5_ifc_mtutc_reg_bits {
9624 u8 reserved_at_0[0x1c];
9625 u8 operation[0x4];
9626
9627 u8 freq_adjustment[0x20];
9628
9629 u8 reserved_at_40[0x40];
9630
9631 u8 utc_sec[0x20];
9632
9633 u8 reserved_at_a0[0x2];
9634 u8 utc_nsec[0x1e];
9635
9636 u8 time_adjustment[0x20];
9637};
9638
cfdcbcea 9639struct mlx5_ifc_pcam_enhanced_features_bits {
a58837f5
AL		 9640 u8 reserved_at_0[0x68];
9641 u8 fec_50G_per_lane_in_pplm[0x1];
9642 u8 reserved_at_69[0x4];
0af5107c 9643 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 9644 u8 reserved_at_6e[0x4];
9645 u8 ptys_extended_ethernet[0x1];
9646 u8 reserved_at_73[0x3];
2fcb12df 9647 u8 pfcc_mask[0x1];
67daf118
SA		 9648 u8 reserved_at_77[0x3];
9649 u8 per_lane_error_counters[0x1];
2dba0797 9650 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 9651 u8 ptys_connector_type[0x1];
9652 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 9653 u8 ppcnt_discard_group[0x1];
9654 u8 ppcnt_statistical_group[0x1];
9655};
9656
df5f1361
HN		 9657struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9658 u8 port_access_reg_cap_mask_127_to_96[0x20];
9659 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 9660
9661 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9662 u8 pplm[0x1];
9663 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 9664
9665 u8 port_access_reg_cap_mask_31_to_13[0x13];
9666 u8 pbmc[0x1];
9667 u8 pptb[0x1];
75370eb0
ED		 9668 u8 port_access_reg_cap_mask_10_to_09[0x2];
9669 u8 ppcnt[0x1];
9670 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 9671};
9672
cfdcbcea
GP		 9673struct mlx5_ifc_pcam_reg_bits {
9674 u8 reserved_at_0[0x8];
9675 u8 feature_group[0x8];
9676 u8 reserved_at_10[0x8];
9677 u8 access_reg_group[0x8];
9678
9679 u8 reserved_at_20[0x20];
9680
9681 union {
df5f1361 9682 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 9683 u8 reserved_at_0[0x80];
9684 } port_access_reg_cap_mask;
9685
9686 u8 reserved_at_c0[0x80];
9687
9688 union {
9689 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9690 u8 reserved_at_0[0x80];
9691 } feature_cap_mask;
9692
9693 u8 reserved_at_1c0[0xc0];
9694};
9695
9696struct mlx5_ifc_mcam_enhanced_features_bits {
271907ee
GP		 9697 u8 reserved_at_0[0x5d];
9698 u8 mcia_32dwords[0x1];
9699 u8 reserved_at_5e[0xc];
72fb3b60 9700 u8 reset_state[0x1];
ae02d415
EBE		 9701 u8 ptpcyc2realtime_modify[0x1];
9702 u8 reserved_at_6c[0x2];
4039049b
AL		 9703 u8 pci_status_and_power[0x1];
9704 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 9705 u8 mark_tx_action_cnp[0x1];
9706 u8 mark_tx_action_cqe[0x1];
9707 u8 dynamic_tx_overflow[0x1];
9708 u8 reserved_at_77[0x4];
5405fa26 9709 u8 pcie_outbound_stalled[0x1];
efae7f78 9710 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 9711 u8 mtpps_enh_out_per_adj[0x1];
9712 u8 mtpps_fs[0x1];
cfdcbcea
GP		 9713 u8 pcie_performance_group[0x1];
9714};
9715
0ab87743
OG		 9716struct mlx5_ifc_mcam_access_reg_bits {
9717 u8 reserved_at_0[0x1c];
9718 u8 mcda[0x1];
9719 u8 mcc[0x1];
9720 u8 mcqi[0x1];
a82e0b5b 9721 u8 mcqs[0x1];
0ab87743 9722
5e022dd3
EBE		 9723 u8 regs_95_to_87[0x9];
9724 u8 mpegc[0x1];
ae02d415
EBE		 9725 u8 mtutc[0x1];
9726 u8 regs_84_to_68[0x11];
eff8ea8f
FD		 9727 u8 tracer_registers[0x4];
9728
502e82b9
AL		 9729 u8 regs_63_to_46[0x12];
9730 u8 mrtc[0x1];
9731 u8 regs_44_to_32[0xd];
9732
0ab87743
OG		 9733 u8 regs_31_to_0[0x20];
9734};
9735
f397464e
EBE		 9736struct mlx5_ifc_mcam_access_reg_bits1 {
9737 u8 regs_127_to_96[0x20];
9738
9739 u8 regs_95_to_64[0x20];
9740
9741 u8 regs_63_to_32[0x20];
9742
9743 u8 regs_31_to_0[0x20];
9744};
9745
9746struct mlx5_ifc_mcam_access_reg_bits2 {
9747 u8 regs_127_to_99[0x1d];
9748 u8 mirc[0x1];
9749 u8 regs_97_to_96[0x2];
9750
9751 u8 regs_95_to_64[0x20];
9752
9753 u8 regs_63_to_32[0x20];
9754
9755 u8 regs_31_to_0[0x20];
9756};
9757
cfdcbcea
GP		 9758struct mlx5_ifc_mcam_reg_bits {
9759 u8 reserved_at_0[0x8];
9760 u8 feature_group[0x8];
9761 u8 reserved_at_10[0x8];
9762 u8 access_reg_group[0x8];
9763
9764 u8 reserved_at_20[0x20];
9765
9766 union {
0ab87743 9767 struct mlx5_ifc_mcam_access_reg_bits access_regs;
f397464e
EBE		 9768 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9769 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
cfdcbcea
GP		 9770 u8 reserved_at_0[0x80];
9771 } mng_access_reg_cap_mask;
9772
9773 u8 reserved_at_c0[0x80];
9774
9775 union {
9776 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9777 u8 reserved_at_0[0x80];
9778 } mng_feature_cap_mask;
9779
9780 u8 reserved_at_1c0[0x80];
9781};
9782
c02762eb
HN		 9783struct mlx5_ifc_qcam_access_reg_cap_mask {
9784 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9785 u8 qpdpm[0x1];
9786 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9787 u8 qdpm[0x1];
9788 u8 qpts[0x1];
9789 u8 qcap[0x1];
9790 u8 qcam_access_reg_cap_mask_0[0x1];
9791};
9792
9793struct mlx5_ifc_qcam_qos_feature_cap_mask {
9794 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9795 u8 qpts_trust_both[0x1];
9796};
9797
9798struct mlx5_ifc_qcam_reg_bits {
9799 u8 reserved_at_0[0x8];
9800 u8 feature_group[0x8];
9801 u8 reserved_at_10[0x8];
9802 u8 access_reg_group[0x8];
9803 u8 reserved_at_20[0x20];
9804
9805 union {
9806 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9807 u8 reserved_at_0[0x80];
9808 } qos_access_reg_cap_mask;
9809
9810 u8 reserved_at_c0[0x80];
9811
9812 union {
9813 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9814 u8 reserved_at_0[0x80];
9815 } qos_feature_cap_mask;
9816
9817 u8 reserved_at_1c0[0x80];
9818};
9819
0b9055a1
MS		 9820struct mlx5_ifc_core_dump_reg_bits {
9821 u8 reserved_at_0[0x18];
9822 u8 core_dump_type[0x8];
9823
9824 u8 reserved_at_20[0x30];
9825 u8 vhca_id[0x10];
9826
9827 u8 reserved_at_60[0x8];
9828 u8 qpn[0x18];
9829 u8 reserved_at_80[0x180];
9830};
9831
e281682b 9832struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 9833 u8 reserved_at_0[0x8];
e281682b 9834 u8 local_port[0x8];
b4ff3a36 9835 u8 reserved_at_10[0x10];
e281682b
SM		 9836
9837 u8 port_capability_mask[4][0x20];
9838};
9839
9840struct mlx5_ifc_paos_reg_bits {
9841 u8 swid[0x8];
9842 u8 local_port[0x8];
b4ff3a36 9843 u8 reserved_at_10[0x4];
e281682b 9844 u8 admin_status[0x4];
b4ff3a36 9845 u8 reserved_at_18[0x4];
e281682b
SM		 9846 u8 oper_status[0x4];
9847
9848 u8 ase[0x1];
9849 u8 ee[0x1];
b4ff3a36 9850 u8 reserved_at_22[0x1c];
e281682b
SM		 9851 u8 e[0x2];
9852
b4ff3a36 9853 u8 reserved_at_40[0x40];
e281682b
SM		 9854};
9855
9856struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 9857 u8 reserved_at_0[0x8];
e281682b 9858 u8 opamp_group[0x8];
b4ff3a36 9859 u8 reserved_at_10[0xc];
e281682b
SM		 9860 u8 opamp_group_type[0x4];
9861
9862 u8 start_index[0x10];
b4ff3a36 9863 u8 reserved_at_30[0x4];
e281682b
SM		 9864 u8 num_of_indices[0xc];
9865
9866 u8 index_data[18][0x10];
9867};
9868
7d5e1423
SM		 9869struct mlx5_ifc_pcmr_reg_bits {
9870 u8 reserved_at_0[0x8];
9871 u8 local_port[0x8];
0dcaafc0 9872 u8 reserved_at_10[0x10];
0bc73ad4 9873
0dcaafc0
EB		 9874 u8 entropy_force_cap[0x1];
9875 u8 entropy_calc_cap[0x1];
9876 u8 entropy_gre_calc_cap[0x1];
0bc73ad4
AL		 9877 u8 reserved_at_23[0xf];
9878 u8 rx_ts_over_crc_cap[0x1];
9879 u8 reserved_at_33[0xb];
7d5e1423 9880 u8 fcs_cap[0x1];
0dcaafc0 9881 u8 reserved_at_3f[0x1];
0bc73ad4 9882
0dcaafc0
EB		 9883 u8 entropy_force[0x1];
9884 u8 entropy_calc[0x1];
9885 u8 entropy_gre_calc[0x1];
0bc73ad4
AL		 9886 u8 reserved_at_43[0xf];
9887 u8 rx_ts_over_crc[0x1];
9888 u8 reserved_at_53[0xb];
7d5e1423
SM		 9889 u8 fcs_chk[0x1];
9890 u8 reserved_at_5f[0x1];
9891};
9892
e281682b 9893struct mlx5_ifc_lane_2_module_mapping_bits {
fcb610a8
GP		 9894 u8 reserved_at_0[0x4];
9895 u8 rx_lane[0x4];
9896 u8 reserved_at_8[0x4];
9897 u8 tx_lane[0x4];
b4ff3a36 9898 u8 reserved_at_10[0x8];
e281682b
SM		 9899 u8 module[0x8];
9900};
9901
9902struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 9903 u8 reserved_at_0[0x6];
e281682b
SM		 9904 u8 lossy[0x1];
9905 u8 epsb[0x1];
ac77998b
MK		 9906 u8 reserved_at_8[0x8];
9907 u8 size[0x10];
e281682b
SM		 9908
9909 u8 xoff_threshold[0x10];
9910 u8 xon_threshold[0x10];
9911};
9912
9913struct mlx5_ifc_set_node_in_bits {
9914 u8 node_description[64][0x8];
9915};
9916
9917struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 9918 u8 reserved_at_0[0x18];
e281682b
SM		 9919 u8 power_settings_level[0x8];
9920
b4ff3a36 9921 u8 reserved_at_20[0x60];
e281682b
SM		 9922};
9923
9924struct mlx5_ifc_register_host_endianness_bits {
9925 u8 he[0x1];
b4ff3a36 9926 u8 reserved_at_1[0x1f];
e281682b 9927
b4ff3a36 9928 u8 reserved_at_20[0x60];
e281682b
SM		 9929};
9930
9931struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 9932 u8 reserved_at_0[0x20];
e281682b
SM		 9933
9934 u8 mkey[0x20];
9935
9936 u8 addressh_63_32[0x20];
9937
9938 u8 addressl_31_0[0x20];
9939};
9940
9941struct mlx5_ifc_ud_adrs_vector_bits {
9942 u8 dc_key[0x40];
9943
9944 u8 ext[0x1];
b4ff3a36 9945 u8 reserved_at_41[0x7];
e281682b
SM		 9946 u8 destination_qp_dct[0x18];
9947
9948 u8 static_rate[0x4];
9949 u8 sl_eth_prio[0x4];
9950 u8 fl[0x1];
9951 u8 mlid[0x7];
9952 u8 rlid_udp_sport[0x10];
9953
b4ff3a36 9954 u8 reserved_at_80[0x20];
e281682b
SM		 9955
9956 u8 rmac_47_16[0x20];
9957
9958 u8 rmac_15_0[0x10];
9959 u8 tclass[0x8];
9960 u8 hop_limit[0x8];
9961
b4ff3a36 9962 u8 reserved_at_e0[0x1];
e281682b 9963 u8 grh[0x1];
b4ff3a36 9964 u8 reserved_at_e2[0x2];
e281682b
SM		 9965 u8 src_addr_index[0x8];
9966 u8 flow_label[0x14];
9967
9968 u8 rgid_rip[16][0x8];
9969};
9970
9971struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 9972 u8 reserved_at_0[0x10];
e281682b
SM		 9973 u8 function_id[0x10];
9974
9975 u8 num_pages[0x20];
9976
b4ff3a36 9977 u8 reserved_at_40[0xa0];
e281682b
SM		 9978};
9979
9980struct mlx5_ifc_eqe_bits {
b4ff3a36 9981 u8 reserved_at_0[0x8];
e281682b 9982 u8 event_type[0x8];
b4ff3a36 9983 u8 reserved_at_10[0x8];
e281682b
SM		 9984 u8 event_sub_type[0x8];
9985
b4ff3a36 9986 u8 reserved_at_20[0xe0];
e281682b
SM		 9987
9988 union mlx5_ifc_event_auto_bits event_data;
9989
b4ff3a36 9990 u8 reserved_at_1e0[0x10];
e281682b 9991 u8 signature[0x8];
b4ff3a36 9992 u8 reserved_at_1f8[0x7];
e281682b
SM		 9993 u8 owner[0x1];
9994};
9995
9996enum {
9997 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9998};
9999
10000struct mlx5_ifc_cmd_queue_entry_bits {
10001 u8 type[0x8];
b4ff3a36 10002 u8 reserved_at_8[0x18];
e281682b
SM		 10003
10004 u8 input_length[0x20];
10005
10006 u8 input_mailbox_pointer_63_32[0x20];
10007
10008 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 10009 u8 reserved_at_77[0x9];
e281682b
SM		 10010
10011 u8 command_input_inline_data[16][0x8];
10012
10013 u8 command_output_inline_data[16][0x8];
10014
10015 u8 output_mailbox_pointer_63_32[0x20];
10016
10017 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 10018 u8 reserved_at_1b7[0x9];
e281682b
SM		 10019
10020 u8 output_length[0x20];
10021
10022 u8 token[0x8];
10023 u8 signature[0x8];
b4ff3a36 10024 u8 reserved_at_1f0[0x8];
e281682b
SM		 10025 u8 status[0x7];
10026 u8 ownership[0x1];
10027};
10028
10029struct mlx5_ifc_cmd_out_bits {
10030 u8 status[0x8];
b4ff3a36 10031 u8 reserved_at_8[0x18];
e281682b
SM		 10032
10033 u8 syndrome[0x20];
10034
10035 u8 command_output[0x20];
10036};
10037
10038struct mlx5_ifc_cmd_in_bits {
10039 u8 opcode[0x10];
b4ff3a36 10040 u8 reserved_at_10[0x10];
e281682b 10041
b4ff3a36 10042 u8 reserved_at_20[0x10];
e281682b
SM		 10043 u8 op_mod[0x10];
10044
b6ca09cb 10045 u8 command[][0x20];
e281682b
SM		 10046};
10047
10048struct mlx5_ifc_cmd_if_box_bits {
10049 u8 mailbox_data[512][0x8];
10050
b4ff3a36 10051 u8 reserved_at_1000[0x180];
e281682b
SM		 10052
10053 u8 next_pointer_63_32[0x20];
10054
10055 u8 next_pointer_31_10[0x16];
b4ff3a36 10056 u8 reserved_at_11b6[0xa];
e281682b
SM		 10057
10058 u8 block_number[0x20];
10059
b4ff3a36 10060 u8 reserved_at_11e0[0x8];
e281682b
SM		 10061 u8 token[0x8];
10062 u8 ctrl_signature[0x8];
10063 u8 signature[0x8];
10064};
10065
10066struct mlx5_ifc_mtt_bits {
10067 u8 ptag_63_32[0x20];
10068
10069 u8 ptag_31_8[0x18];
b4ff3a36 10070 u8 reserved_at_38[0x6];
e281682b
SM		 10071 u8 wr_en[0x1];
10072 u8 rd_en[0x1];
10073};
10074
928cfe87
TT		 10075struct mlx5_ifc_query_wol_rol_out_bits {
10076 u8 status[0x8];
10077 u8 reserved_at_8[0x18];
10078
10079 u8 syndrome[0x20];
10080
10081 u8 reserved_at_40[0x10];
10082 u8 rol_mode[0x8];
10083 u8 wol_mode[0x8];
10084
10085 u8 reserved_at_60[0x20];
10086};
10087
10088struct mlx5_ifc_query_wol_rol_in_bits {
10089 u8 opcode[0x10];
10090 u8 reserved_at_10[0x10];
10091
10092 u8 reserved_at_20[0x10];
10093 u8 op_mod[0x10];
10094
10095 u8 reserved_at_40[0x40];
10096};
10097
10098struct mlx5_ifc_set_wol_rol_out_bits {
10099 u8 status[0x8];
10100 u8 reserved_at_8[0x18];
10101
10102 u8 syndrome[0x20];
10103
10104 u8 reserved_at_40[0x40];
10105};
10106
10107struct mlx5_ifc_set_wol_rol_in_bits {
10108 u8 opcode[0x10];
10109 u8 reserved_at_10[0x10];
10110
10111 u8 reserved_at_20[0x10];
10112 u8 op_mod[0x10];
10113
10114 u8 rol_mode_valid[0x1];
10115 u8 wol_mode_valid[0x1];
10116 u8 reserved_at_42[0xe];
10117 u8 rol_mode[0x8];
10118 u8 wol_mode[0x8];
10119
10120 u8 reserved_at_60[0x20];
10121};
10122
e281682b
SM		 10123enum {
10124 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10125 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10126 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10127};
10128
10129enum {
10130 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10131 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10132 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10133};
10134
10135enum {
10136 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10137 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10138 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10139 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10140 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10141 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10142 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10143 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10144 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10145 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10146 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10147};
10148
10149struct mlx5_ifc_initial_seg_bits {
10150 u8 fw_rev_minor[0x10];
10151 u8 fw_rev_major[0x10];
10152
10153 u8 cmd_interface_rev[0x10];
10154 u8 fw_rev_subminor[0x10];
10155
b4ff3a36 10156 u8 reserved_at_40[0x40];
e281682b
SM		 10157
10158 u8 cmdq_phy_addr_63_32[0x20];
10159
10160 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 10161 u8 reserved_at_b4[0x2];
e281682b
SM		 10162 u8 nic_interface[0x2];
10163 u8 log_cmdq_size[0x4];
10164 u8 log_cmdq_stride[0x4];
10165
10166 u8 command_doorbell_vector[0x20];
10167
b4ff3a36 10168 u8 reserved_at_e0[0xf00];
e281682b
SM		 10169
10170 u8 initializing[0x1];
b4ff3a36 10171 u8 reserved_at_fe1[0x4];
e281682b 10172 u8 nic_interface_supported[0x3];
591905ba
BW		 10173 u8 embedded_cpu[0x1];
10174 u8 reserved_at_fe9[0x17];
e281682b
SM		 10175
10176 struct mlx5_ifc_health_buffer_bits health_buffer;
10177
10178 u8 no_dram_nic_offset[0x20];
10179
b4ff3a36 10180 u8 reserved_at_1220[0x6e40];
e281682b 10181
b4ff3a36 10182 u8 reserved_at_8060[0x1f];
e281682b
SM		 10183 u8 clear_int[0x1];
10184
10185 u8 health_syndrome[0x8];
10186 u8 health_counter[0x18];
10187
b4ff3a36 10188 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 10189};
10190
f9a1ef72
EE		 10191struct mlx5_ifc_mtpps_reg_bits {
10192 u8 reserved_at_0[0xc];
10193 u8 cap_number_of_pps_pins[0x4];
10194 u8 reserved_at_10[0x4];
10195 u8 cap_max_num_of_pps_in_pins[0x4];
10196 u8 reserved_at_18[0x4];
10197 u8 cap_max_num_of_pps_out_pins[0x4];
10198
10199 u8 reserved_at_20[0x24];
10200 u8 cap_pin_3_mode[0x4];
10201 u8 reserved_at_48[0x4];
10202 u8 cap_pin_2_mode[0x4];
10203 u8 reserved_at_50[0x4];
10204 u8 cap_pin_1_mode[0x4];
10205 u8 reserved_at_58[0x4];
10206 u8 cap_pin_0_mode[0x4];
10207
10208 u8 reserved_at_60[0x4];
10209 u8 cap_pin_7_mode[0x4];
10210 u8 reserved_at_68[0x4];
10211 u8 cap_pin_6_mode[0x4];
10212 u8 reserved_at_70[0x4];
10213 u8 cap_pin_5_mode[0x4];
10214 u8 reserved_at_78[0x4];
10215 u8 cap_pin_4_mode[0x4];
10216
fa367688
EE		 10217 u8 field_select[0x20];
10218 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 10219
10220 u8 enable[0x1];
10221 u8 reserved_at_101[0xb];
10222 u8 pattern[0x4];
10223 u8 reserved_at_110[0x4];
10224 u8 pin_mode[0x4];
10225 u8 pin[0x8];
10226
10227 u8 reserved_at_120[0x20];
10228
10229 u8 time_stamp[0x40];
10230
10231 u8 out_pulse_duration[0x10];
10232 u8 out_periodic_adjustment[0x10];
fa367688 10233 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 10234
fa367688 10235 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 10236};
10237
10238struct mlx5_ifc_mtppse_reg_bits {
10239 u8 reserved_at_0[0x18];
10240 u8 pin[0x8];
10241 u8 event_arm[0x1];
10242 u8 reserved_at_21[0x1b];
10243 u8 event_generation_mode[0x4];
10244 u8 reserved_at_40[0x40];
10245};
10246
a82e0b5b
SA		 10247struct mlx5_ifc_mcqs_reg_bits {
10248 u8 last_index_flag[0x1];
10249 u8 reserved_at_1[0x7];
10250 u8 fw_device[0x8];
10251 u8 component_index[0x10];
10252
10253 u8 reserved_at_20[0x10];
10254 u8 identifier[0x10];
10255
10256 u8 reserved_at_40[0x17];
10257 u8 component_status[0x5];
10258 u8 component_update_state[0x4];
10259
10260 u8 last_update_state_changer_type[0x4];
10261 u8 last_update_state_changer_host_id[0x4];
10262 u8 reserved_at_68[0x18];
10263};
10264
47176289
OG		 10265struct mlx5_ifc_mcqi_cap_bits {
10266 u8 supported_info_bitmask[0x20];
10267
10268 u8 component_size[0x20];
10269
10270 u8 max_component_size[0x20];
10271
10272 u8 log_mcda_word_size[0x4];
10273 u8 reserved_at_64[0xc];
10274 u8 mcda_max_write_size[0x10];
10275
10276 u8 rd_en[0x1];
10277 u8 reserved_at_81[0x1];
10278 u8 match_chip_id[0x1];
10279 u8 match_psid[0x1];
10280 u8 check_user_timestamp[0x1];
10281 u8 match_base_guid_mac[0x1];
10282 u8 reserved_at_86[0x1a];
10283};
10284
a82e0b5b
SA		 10285struct mlx5_ifc_mcqi_version_bits {
10286 u8 reserved_at_0[0x2];
10287 u8 build_time_valid[0x1];
10288 u8 user_defined_time_valid[0x1];
10289 u8 reserved_at_4[0x14];
10290 u8 version_string_length[0x8];
10291
10292 u8 version[0x20];
10293
10294 u8 build_time[0x40];
10295
10296 u8 user_defined_time[0x40];
10297
10298 u8 build_tool_version[0x20];
10299
10300 u8 reserved_at_e0[0x20];
10301
10302 u8 version_string[92][0x8];
10303};
10304
10305struct mlx5_ifc_mcqi_activation_method_bits {
10306 u8 pending_server_ac_power_cycle[0x1];
10307 u8 pending_server_dc_power_cycle[0x1];
10308 u8 pending_server_reboot[0x1];
10309 u8 pending_fw_reset[0x1];
10310 u8 auto_activate[0x1];
10311 u8 all_hosts_sync[0x1];
10312 u8 device_hw_reset[0x1];
10313 u8 reserved_at_7[0x19];
10314};
10315
10316union mlx5_ifc_mcqi_reg_data_bits {
10317 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
10318 struct mlx5_ifc_mcqi_version_bits mcqi_version;
10319 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10320};
10321
47176289
OG		 10322struct mlx5_ifc_mcqi_reg_bits {
10323 u8 read_pending_component[0x1];
10324 u8 reserved_at_1[0xf];
10325 u8 component_index[0x10];
10326
10327 u8 reserved_at_20[0x20];
10328
10329 u8 reserved_at_40[0x1b];
10330 u8 info_type[0x5];
10331
10332 u8 info_size[0x20];
10333
10334 u8 offset[0x20];
10335
10336 u8 reserved_at_a0[0x10];
10337 u8 data_size[0x10];
10338
b6ca09cb 10339 union mlx5_ifc_mcqi_reg_data_bits data[];
47176289
OG		 10340};
10341
10342struct mlx5_ifc_mcc_reg_bits {
10343 u8 reserved_at_0[0x4];
10344 u8 time_elapsed_since_last_cmd[0xc];
10345 u8 reserved_at_10[0x8];
10346 u8 instruction[0x8];
10347
10348 u8 reserved_at_20[0x10];
10349 u8 component_index[0x10];
10350
10351 u8 reserved_at_40[0x8];
10352 u8 update_handle[0x18];
10353
10354 u8 handle_owner_type[0x4];
10355 u8 handle_owner_host_id[0x4];
10356 u8 reserved_at_68[0x1];
10357 u8 control_progress[0x7];
10358 u8 error_code[0x8];
10359 u8 reserved_at_78[0x4];
10360 u8 control_state[0x4];
10361
10362 u8 component_size[0x20];
10363
10364 u8 reserved_at_a0[0x60];
10365};
10366
10367struct mlx5_ifc_mcda_reg_bits {
10368 u8 reserved_at_0[0x8];
10369 u8 update_handle[0x18];
10370
10371 u8 offset[0x20];
10372
10373 u8 reserved_at_40[0x10];
10374 u8 size[0x10];
10375
10376 u8 reserved_at_60[0x20];
10377
29056207 10378 u8 data[][0x20];
47176289
OG		 10379};
10380
72fb3b60
MS		 10381enum {
10382 MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10383 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10384 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10385 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10386 MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10387};
10388
06939536
MS		 10389enum {
10390 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10391 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10392};
10393
10394enum {
10395 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10396 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10397 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10398};
10399
10400struct mlx5_ifc_mfrl_reg_bits {
10401 u8 reserved_at_0[0x20];
10402
10403 u8 reserved_at_20[0x2];
10404 u8 pci_sync_for_fw_update_start[0x1];
10405 u8 pci_sync_for_fw_update_resp[0x2];
10406 u8 rst_type_sel[0x3];
72fb3b60
MS		 10407 u8 reserved_at_28[0x4];
10408 u8 reset_state[0x4];
06939536
MS		 10409 u8 reset_type[0x8];
10410 u8 reset_level[0x8];
10411};
10412
bab58ba1
EBE		 10413struct mlx5_ifc_mirc_reg_bits {
10414 u8 reserved_at_0[0x18];
10415 u8 status_code[0x8];
10416
10417 u8 reserved_at_20[0x20];
10418};
10419
36830159
MT		 10420struct mlx5_ifc_pddr_monitor_opcode_bits {
10421 u8 reserved_at_0[0x10];
10422 u8 monitor_opcode[0x10];
10423};
10424
10425union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10426 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10427 u8 reserved_at_0[0x20];
10428};
10429
10430enum {
10431 /* Monitor opcodes */
10432 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10433};
10434
10435struct mlx5_ifc_pddr_troubleshooting_page_bits {
10436 u8 reserved_at_0[0x10];
10437 u8 group_opcode[0x10];
10438
10439 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10440
10441 u8 reserved_at_40[0x20];
10442
10443 u8 status_message[59][0x20];
10444};
10445
10446union mlx5_ifc_pddr_reg_page_data_auto_bits {
10447 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10448 u8 reserved_at_0[0x7c0];
10449};
10450
10451enum {
10452 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
10453};
10454
10455struct mlx5_ifc_pddr_reg_bits {
10456 u8 reserved_at_0[0x8];
10457 u8 local_port[0x8];
10458 u8 pnat[0x2];
10459 u8 reserved_at_12[0xe];
10460
10461 u8 reserved_at_20[0x18];
10462 u8 page_select[0x8];
10463
10464 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10465};
10466
5a1023de
AL		 10467struct mlx5_ifc_mrtc_reg_bits {
10468 u8 time_synced[0x1];
10469 u8 reserved_at_1[0x1f];
10470
10471 u8 reserved_at_20[0x20];
10472
10473 u8 time_h[0x20];
10474
10475 u8 time_l[0x20];
10476};
10477
e281682b
SM		 10478union mlx5_ifc_ports_control_registers_document_bits {
10479 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10480 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10481 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10482 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10483 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10484 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10485 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 10486 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10487 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
e281682b
SM		 10488 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10489 struct mlx5_ifc_pamp_reg_bits pamp_reg;
10490 struct mlx5_ifc_paos_reg_bits paos_reg;
10491 struct mlx5_ifc_pcap_reg_bits pcap_reg;
36830159
MT		 10492 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10493 struct mlx5_ifc_pddr_reg_bits pddr_reg;
10494 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
e281682b
SM		 10495 struct mlx5_ifc_peir_reg_bits peir_reg;
10496 struct mlx5_ifc_pelc_reg_bits pelc_reg;
10497 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 10498 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 10499 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10500 struct mlx5_ifc_pifr_reg_bits pifr_reg;
10501 struct mlx5_ifc_pipg_reg_bits pipg_reg;
10502 struct mlx5_ifc_plbf_reg_bits plbf_reg;
10503 struct mlx5_ifc_plib_reg_bits plib_reg;
10504 struct mlx5_ifc_plpc_reg_bits plpc_reg;
10505 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10506 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10507 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10508 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10509 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10510 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10511 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10512 struct mlx5_ifc_ppad_reg_bits ppad_reg;
10513 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 10514 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 10515 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 10516 struct mlx5_ifc_pplm_reg_bits pplm_reg;
10517 struct mlx5_ifc_pplr_reg_bits pplr_reg;
10518 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10519 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10520 struct mlx5_ifc_pspa_reg_bits pspa_reg;
10521 struct mlx5_ifc_ptas_reg_bits ptas_reg;
10522 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 10523 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 10524 struct mlx5_ifc_pude_reg_bits pude_reg;
10525 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10526 struct mlx5_ifc_slrg_reg_bits slrg_reg;
10527 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 10528 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10529 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 10530 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 10531 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10532 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 10533 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10534 struct mlx5_ifc_mcc_reg_bits mcc_reg;
10535 struct mlx5_ifc_mcda_reg_bits mcda_reg;
bab58ba1 10536 struct mlx5_ifc_mirc_reg_bits mirc_reg;
06939536 10537 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
ae02d415 10538 struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
5a1023de 10539 struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
b4ff3a36 10540 u8 reserved_at_0[0x60e0];
e281682b
SM		 10541};
10542
10543union mlx5_ifc_debug_enhancements_document_bits {
10544 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 10545 u8 reserved_at_0[0x200];
e281682b
SM		 10546};
10547
10548union mlx5_ifc_uplink_pci_interface_document_bits {
10549 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 10550 u8 reserved_at_0[0x20060];
b775516b
EC		 10551};
10552
2cc43b49
MG		 10553struct mlx5_ifc_set_flow_table_root_out_bits {
10554 u8 status[0x8];
b4ff3a36 10555 u8 reserved_at_8[0x18];
2cc43b49
MG		 10556
10557 u8 syndrome[0x20];
10558
b4ff3a36 10559 u8 reserved_at_40[0x40];
2cc43b49
MG		 10560};
10561
10562struct mlx5_ifc_set_flow_table_root_in_bits {
10563 u8 opcode[0x10];
b4ff3a36 10564 u8 reserved_at_10[0x10];
2cc43b49 10565
b4ff3a36 10566 u8 reserved_at_20[0x10];
2cc43b49
MG		 10567 u8 op_mod[0x10];
10568
7d5e1423
SM		 10569 u8 other_vport[0x1];
10570 u8 reserved_at_41[0xf];
10571 u8 vport_number[0x10];
10572
10573 u8 reserved_at_60[0x20];
2cc43b49
MG		 10574
10575 u8 table_type[0x8];
c3e666f1
MB		 10576 u8 reserved_at_88[0x7];
10577 u8 table_of_other_vport[0x1];
10578 u8 table_vport_number[0x10];
2cc43b49 10579
b4ff3a36 10580 u8 reserved_at_a0[0x8];
2cc43b49
MG		 10581 u8 table_id[0x18];
10582
500a3d0d
ES		 10583 u8 reserved_at_c0[0x8];
10584 u8 underlay_qpn[0x18];
c3e666f1
MB		 10585 u8 table_eswitch_owner_vhca_id_valid[0x1];
10586 u8 reserved_at_e1[0xf];
10587 u8 table_eswitch_owner_vhca_id[0x10];
10588 u8 reserved_at_100[0x100];
2cc43b49
MG		 10589};
10590
34a40e68 10591enum {
84df61eb
AH		 10592 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
10593 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 10594};
10595
10596struct mlx5_ifc_modify_flow_table_out_bits {
10597 u8 status[0x8];
b4ff3a36 10598 u8 reserved_at_8[0x18];
34a40e68
MG		 10599
10600 u8 syndrome[0x20];
10601
b4ff3a36 10602 u8 reserved_at_40[0x40];
34a40e68
MG		 10603};
10604
10605struct mlx5_ifc_modify_flow_table_in_bits {
10606 u8 opcode[0x10];
b4ff3a36 10607 u8 reserved_at_10[0x10];
34a40e68 10608
b4ff3a36 10609 u8 reserved_at_20[0x10];
34a40e68
MG		 10610 u8 op_mod[0x10];
10611
7d5e1423
SM		 10612 u8 other_vport[0x1];
10613 u8 reserved_at_41[0xf];
10614 u8 vport_number[0x10];
34a40e68 10615
b4ff3a36 10616 u8 reserved_at_60[0x10];
34a40e68
MG		 10617 u8 modify_field_select[0x10];
10618
10619 u8 table_type[0x8];
b4ff3a36 10620 u8 reserved_at_88[0x18];
34a40e68 10621
b4ff3a36 10622 u8 reserved_at_a0[0x8];
34a40e68
MG		 10623 u8 table_id[0x18];
10624
0c90e9c6 10625 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 10626};
10627
4f3961ee
SM		 10628struct mlx5_ifc_ets_tcn_config_reg_bits {
10629 u8 g[0x1];
10630 u8 b[0x1];
10631 u8 r[0x1];
10632 u8 reserved_at_3[0x9];
10633 u8 group[0x4];
10634 u8 reserved_at_10[0x9];
10635 u8 bw_allocation[0x7];
10636
10637 u8 reserved_at_20[0xc];
10638 u8 max_bw_units[0x4];
10639 u8 reserved_at_30[0x8];
10640 u8 max_bw_value[0x8];
10641};
10642
10643struct mlx5_ifc_ets_global_config_reg_bits {
10644 u8 reserved_at_0[0x2];
10645 u8 r[0x1];
10646 u8 reserved_at_3[0x1d];
10647
10648 u8 reserved_at_20[0xc];
10649 u8 max_bw_units[0x4];
10650 u8 reserved_at_30[0x8];
10651 u8 max_bw_value[0x8];
10652};
10653
10654struct mlx5_ifc_qetc_reg_bits {
10655 u8 reserved_at_0[0x8];
10656 u8 port_number[0x8];
10657 u8 reserved_at_10[0x30];
10658
10659 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10660 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10661};
10662
415a64aa
HN		 10663struct mlx5_ifc_qpdpm_dscp_reg_bits {
10664 u8 e[0x1];
10665 u8 reserved_at_01[0x0b];
10666 u8 prio[0x04];
10667};
10668
10669struct mlx5_ifc_qpdpm_reg_bits {
10670 u8 reserved_at_0[0x8];
10671 u8 local_port[0x8];
10672 u8 reserved_at_10[0x10];
10673 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10674};
10675
10676struct mlx5_ifc_qpts_reg_bits {
10677 u8 reserved_at_0[0x8];
10678 u8 local_port[0x8];
10679 u8 reserved_at_10[0x2d];
10680 u8 trust_state[0x3];
10681};
10682
50b4a3c2
HN		 10683struct mlx5_ifc_pptb_reg_bits {
10684 u8 reserved_at_0[0x2];
10685 u8 mm[0x2];
10686 u8 reserved_at_4[0x4];
10687 u8 local_port[0x8];
10688 u8 reserved_at_10[0x6];
10689 u8 cm[0x1];
10690 u8 um[0x1];
10691 u8 pm[0x8];
10692
10693 u8 prio_x_buff[0x20];
10694
10695 u8 pm_msb[0x8];
10696 u8 reserved_at_48[0x10];
10697 u8 ctrl_buff[0x4];
10698 u8 untagged_buff[0x4];
10699};
10700
88b3d5c9
EBE		 10701struct mlx5_ifc_sbcam_reg_bits {
10702 u8 reserved_at_0[0x8];
10703 u8 feature_group[0x8];
10704 u8 reserved_at_10[0x8];
10705 u8 access_reg_group[0x8];
10706
10707 u8 reserved_at_20[0x20];
10708
10709 u8 sb_access_reg_cap_mask[4][0x20];
10710
10711 u8 reserved_at_c0[0x80];
10712
10713 u8 sb_feature_cap_mask[4][0x20];
10714
10715 u8 reserved_at_1c0[0x40];
10716
10717 u8 cap_total_buffer_size[0x20];
10718
10719 u8 cap_cell_size[0x10];
10720 u8 cap_max_pg_buffers[0x8];
10721 u8 cap_num_pool_supported[0x8];
10722
10723 u8 reserved_at_240[0x8];
10724 u8 cap_sbsr_stat_size[0x8];
10725 u8 cap_max_tclass_data[0x8];
10726 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10727};
10728
50b4a3c2
HN		 10729struct mlx5_ifc_pbmc_reg_bits {
10730 u8 reserved_at_0[0x8];
10731 u8 local_port[0x8];
10732 u8 reserved_at_10[0x10];
10733
10734 u8 xoff_timer_value[0x10];
10735 u8 xoff_refresh[0x10];
10736
10737 u8 reserved_at_40[0x9];
10738 u8 fullness_threshold[0x7];
10739 u8 port_buffer_size[0x10];
10740
10741 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10742
534b1204 10743 u8 reserved_at_2e0[0x80];
50b4a3c2
HN		 10744};
10745
4f3961ee
SM		 10746struct mlx5_ifc_qtct_reg_bits {
10747 u8 reserved_at_0[0x8];
10748 u8 port_number[0x8];
10749 u8 reserved_at_10[0xd];
10750 u8 prio[0x3];
10751
10752 u8 reserved_at_20[0x1d];
10753 u8 tclass[0x3];
10754};
10755
7d5e1423
SM		 10756struct mlx5_ifc_mcia_reg_bits {
10757 u8 l[0x1];
10758 u8 reserved_at_1[0x7];
10759 u8 module[0x8];
10760 u8 reserved_at_10[0x8];
10761 u8 status[0x8];
10762
10763 u8 i2c_device_address[0x8];
10764 u8 page_number[0x8];
10765 u8 device_address[0x10];
10766
10767 u8 reserved_at_40[0x10];
10768 u8 size[0x10];
10769
10770 u8 reserved_at_60[0x20];
10771
10772 u8 dword_0[0x20];
10773 u8 dword_1[0x20];
10774 u8 dword_2[0x20];
10775 u8 dword_3[0x20];
10776 u8 dword_4[0x20];
10777 u8 dword_5[0x20];
10778 u8 dword_6[0x20];
10779 u8 dword_7[0x20];
10780 u8 dword_8[0x20];
10781 u8 dword_9[0x20];
10782 u8 dword_10[0x20];
10783 u8 dword_11[0x20];
10784};
10785
7486216b
SM		 10786struct mlx5_ifc_dcbx_param_bits {
10787 u8 dcbx_cee_cap[0x1];
10788 u8 dcbx_ieee_cap[0x1];
10789 u8 dcbx_standby_cap[0x1];
c74d90c1 10790 u8 reserved_at_3[0x5];
7486216b
SM		 10791 u8 port_number[0x8];
10792 u8 reserved_at_10[0xa];
10793 u8 max_application_table_size[6];
10794 u8 reserved_at_20[0x15];
10795 u8 version_oper[0x3];
10796 u8 reserved_at_38[5];
10797 u8 version_admin[0x3];
10798 u8 willing_admin[0x1];
10799 u8 reserved_at_41[0x3];
10800 u8 pfc_cap_oper[0x4];
10801 u8 reserved_at_48[0x4];
10802 u8 pfc_cap_admin[0x4];
10803 u8 reserved_at_50[0x4];
10804 u8 num_of_tc_oper[0x4];
10805 u8 reserved_at_58[0x4];
10806 u8 num_of_tc_admin[0x4];
10807 u8 remote_willing[0x1];
10808 u8 reserved_at_61[3];
10809 u8 remote_pfc_cap[4];
10810 u8 reserved_at_68[0x14];
10811 u8 remote_num_of_tc[0x4];
10812 u8 reserved_at_80[0x18];
10813 u8 error[0x8];
10814 u8 reserved_at_a0[0x160];
10815};
84df61eb 10816
425a563a
MG		 10817enum {
10818 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
10819 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT,
10820};
10821
84df61eb 10822struct mlx5_ifc_lagc_bits {
c3e666f1 10823 u8 fdb_selection_mode[0x1];
425a563a
MG		 10824 u8 reserved_at_1[0x14];
10825 u8 port_select_mode[0x3];
10826 u8 reserved_at_18[0x5];
84df61eb
AH		 10827 u8 lag_state[0x3];
10828
10829 u8 reserved_at_20[0x14];
10830 u8 tx_remap_affinity_2[0x4];
10831 u8 reserved_at_38[0x4];
10832 u8 tx_remap_affinity_1[0x4];
10833};
10834
10835struct mlx5_ifc_create_lag_out_bits {
10836 u8 status[0x8];
10837 u8 reserved_at_8[0x18];
10838
10839 u8 syndrome[0x20];
10840
10841 u8 reserved_at_40[0x40];
10842};
10843
10844struct mlx5_ifc_create_lag_in_bits {
10845 u8 opcode[0x10];
10846 u8 reserved_at_10[0x10];
10847
10848 u8 reserved_at_20[0x10];
10849 u8 op_mod[0x10];
10850
10851 struct mlx5_ifc_lagc_bits ctx;
10852};
10853
10854struct mlx5_ifc_modify_lag_out_bits {
10855 u8 status[0x8];
10856 u8 reserved_at_8[0x18];
10857
10858 u8 syndrome[0x20];
10859
10860 u8 reserved_at_40[0x40];
10861};
10862
10863struct mlx5_ifc_modify_lag_in_bits {
10864 u8 opcode[0x10];
10865 u8 reserved_at_10[0x10];
10866
10867 u8 reserved_at_20[0x10];
10868 u8 op_mod[0x10];
10869
10870 u8 reserved_at_40[0x20];
10871 u8 field_select[0x20];
10872
10873 struct mlx5_ifc_lagc_bits ctx;
10874};
10875
10876struct mlx5_ifc_query_lag_out_bits {
10877 u8 status[0x8];
10878 u8 reserved_at_8[0x18];
10879
10880 u8 syndrome[0x20];
10881
84df61eb
AH		 10882 struct mlx5_ifc_lagc_bits ctx;
10883};
10884
10885struct mlx5_ifc_query_lag_in_bits {
10886 u8 opcode[0x10];
10887 u8 reserved_at_10[0x10];
10888
10889 u8 reserved_at_20[0x10];
10890 u8 op_mod[0x10];
10891
10892 u8 reserved_at_40[0x40];
10893};
10894
10895struct mlx5_ifc_destroy_lag_out_bits {
10896 u8 status[0x8];
10897 u8 reserved_at_8[0x18];
10898
10899 u8 syndrome[0x20];
10900
10901 u8 reserved_at_40[0x40];
10902};
10903
10904struct mlx5_ifc_destroy_lag_in_bits {
10905 u8 opcode[0x10];
10906 u8 reserved_at_10[0x10];
10907
10908 u8 reserved_at_20[0x10];
10909 u8 op_mod[0x10];
10910
10911 u8 reserved_at_40[0x40];
10912};
10913
10914struct mlx5_ifc_create_vport_lag_out_bits {
10915 u8 status[0x8];
10916 u8 reserved_at_8[0x18];
10917
10918 u8 syndrome[0x20];
10919
10920 u8 reserved_at_40[0x40];
10921};
10922
10923struct mlx5_ifc_create_vport_lag_in_bits {
10924 u8 opcode[0x10];
10925 u8 reserved_at_10[0x10];
10926
10927 u8 reserved_at_20[0x10];
10928 u8 op_mod[0x10];
10929
10930 u8 reserved_at_40[0x40];
10931};
10932
10933struct mlx5_ifc_destroy_vport_lag_out_bits {
10934 u8 status[0x8];
10935 u8 reserved_at_8[0x18];
10936
10937 u8 syndrome[0x20];
10938
10939 u8 reserved_at_40[0x40];
10940};
10941
10942struct mlx5_ifc_destroy_vport_lag_in_bits {
10943 u8 opcode[0x10];
10944 u8 reserved_at_10[0x10];
10945
10946 u8 reserved_at_20[0x10];
10947 u8 op_mod[0x10];
10948
10949 u8 reserved_at_40[0x40];
10950};
10951
63f9c44b
MG		 10952enum {
10953 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10954 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10955};
10956
10957struct mlx5_ifc_modify_memic_in_bits {
10958 u8 opcode[0x10];
10959 u8 uid[0x10];
10960
10961 u8 reserved_at_20[0x10];
10962 u8 op_mod[0x10];
10963
10964 u8 reserved_at_40[0x20];
10965
10966 u8 reserved_at_60[0x18];
10967 u8 memic_operation_type[0x8];
10968
10969 u8 memic_start_addr[0x40];
10970
10971 u8 reserved_at_c0[0x140];
10972};
10973
10974struct mlx5_ifc_modify_memic_out_bits {
10975 u8 status[0x8];
10976 u8 reserved_at_8[0x18];
10977
10978 u8 syndrome[0x20];
10979
10980 u8 reserved_at_40[0x40];
10981
10982 u8 memic_operation_addr[0x40];
10983
10984 u8 reserved_at_c0[0x140];
10985};
10986
24da0016
AL		 10987struct mlx5_ifc_alloc_memic_in_bits {
10988 u8 opcode[0x10];
10989 u8 reserved_at_10[0x10];
10990
10991 u8 reserved_at_20[0x10];
10992 u8 op_mod[0x10];
10993
10994 u8 reserved_at_30[0x20];
10995
10996 u8 reserved_at_40[0x18];
10997 u8 log_memic_addr_alignment[0x8];
10998
10999 u8 range_start_addr[0x40];
11000
11001 u8 range_size[0x20];
11002
11003 u8 memic_size[0x20];
11004};
11005
11006struct mlx5_ifc_alloc_memic_out_bits {
11007 u8 status[0x8];
11008 u8 reserved_at_8[0x18];
11009
11010 u8 syndrome[0x20];
11011
11012 u8 memic_start_addr[0x40];
11013};
11014
11015struct mlx5_ifc_dealloc_memic_in_bits {
11016 u8 opcode[0x10];
11017 u8 reserved_at_10[0x10];
11018
11019 u8 reserved_at_20[0x10];
11020 u8 op_mod[0x10];
11021
11022 u8 reserved_at_40[0x40];
11023
11024 u8 memic_start_addr[0x40];
11025
11026 u8 memic_size[0x20];
11027
11028 u8 reserved_at_e0[0x20];
11029};
11030
11031struct mlx5_ifc_dealloc_memic_out_bits {
11032 u8 status[0x8];
11033 u8 reserved_at_8[0x18];
11034
11035 u8 syndrome[0x20];
11036
11037 u8 reserved_at_40[0x40];
11038};
11039
38b7ca92 11040struct mlx5_ifc_umem_bits {
6e3722ba 11041 u8 reserved_at_0[0x80];
38b7ca92 11042
6e3722ba 11043 u8 reserved_at_80[0x1b];
38b7ca92
YH		 11044 u8 log_page_size[0x5];
11045
11046 u8 page_offset[0x20];
11047
11048 u8 num_of_mtt[0x40];
11049
b6ca09cb 11050 struct mlx5_ifc_mtt_bits mtt[];
38b7ca92
YH		 11051};
11052
11053struct mlx5_ifc_uctx_bits {
9d43faac
YH		 11054 u8 cap[0x20];
11055
6e3722ba 11056 u8 reserved_at_20[0x160];
38b7ca92
YH		 11057};
11058
9fba2b9b
AL		 11059struct mlx5_ifc_sw_icm_bits {
11060 u8 modify_field_select[0x40];
11061
11062 u8 reserved_at_40[0x18];
11063 u8 log_sw_icm_size[0x8];
11064
11065 u8 reserved_at_60[0x20];
11066
11067 u8 sw_icm_start_addr[0x40];
11068
11069 u8 reserved_at_c0[0x140];
91a40a48 11070};
b169e64a
YK		 11071
11072struct mlx5_ifc_geneve_tlv_option_bits {
11073 u8 modify_field_select[0x40];
11074
11075 u8 reserved_at_40[0x18];
11076 u8 geneve_option_fte_index[0x8];
11077
11078 u8 option_class[0x10];
11079 u8 option_type[0x8];
11080 u8 reserved_at_78[0x3];
11081 u8 option_data_length[0x5];
11082
11083 u8 reserved_at_80[0x180];
9fba2b9b
AL		 11084};
11085
38b7ca92 11086struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 11087 u8 opcode[0x10];
11088 u8 uid[0x10];
11089
11090 u8 reserved_at_20[0x10];
11091 u8 op_mod[0x10];
11092
11093 u8 reserved_at_40[0x40];
11094
11095 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 11096};
11097
8a06a79b
EC		 11098struct mlx5_ifc_create_umem_out_bits {
11099 u8 status[0x8];
11100 u8 reserved_at_8[0x18];
11101
11102 u8 syndrome[0x20];
11103
11104 u8 reserved_at_40[0x8];
11105 u8 umem_id[0x18];
11106
11107 u8 reserved_at_60[0x20];
11108};
11109
11110struct mlx5_ifc_destroy_umem_in_bits {
11111 u8 opcode[0x10];
11112 u8 uid[0x10];
11113
11114 u8 reserved_at_20[0x10];
11115 u8 op_mod[0x10];
11116
11117 u8 reserved_at_40[0x8];
11118 u8 umem_id[0x18];
11119
11120 u8 reserved_at_60[0x20];
11121};
11122
11123struct mlx5_ifc_destroy_umem_out_bits {
11124 u8 status[0x8];
11125 u8 reserved_at_8[0x18];
11126
11127 u8 syndrome[0x20];
11128
11129 u8 reserved_at_40[0x40];
11130};
11131
38b7ca92 11132struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 11133 u8 opcode[0x10];
11134 u8 reserved_at_10[0x10];
11135
11136 u8 reserved_at_20[0x10];
11137 u8 op_mod[0x10];
11138
11139 u8 reserved_at_40[0x40];
11140
11141 struct mlx5_ifc_uctx_bits uctx;
11142};
11143
8a06a79b
EC		 11144struct mlx5_ifc_create_uctx_out_bits {
11145 u8 status[0x8];
11146 u8 reserved_at_8[0x18];
11147
11148 u8 syndrome[0x20];
11149
11150 u8 reserved_at_40[0x10];
11151 u8 uid[0x10];
11152
11153 u8 reserved_at_60[0x20];
11154};
11155
6e3722ba
YH		 11156struct mlx5_ifc_destroy_uctx_in_bits {
11157 u8 opcode[0x10];
11158 u8 reserved_at_10[0x10];
11159
11160 u8 reserved_at_20[0x10];
11161 u8 op_mod[0x10];
11162
11163 u8 reserved_at_40[0x10];
11164 u8 uid[0x10];
11165
11166 u8 reserved_at_60[0x20];
38b7ca92
YH		 11167};
11168
8a06a79b
EC		 11169struct mlx5_ifc_destroy_uctx_out_bits {
11170 u8 status[0x8];
11171 u8 reserved_at_8[0x18];
11172
11173 u8 syndrome[0x20];
11174
11175 u8 reserved_at_40[0x40];
11176};
11177
9fba2b9b
AL		 11178struct mlx5_ifc_create_sw_icm_in_bits {
11179 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11180 struct mlx5_ifc_sw_icm_bits sw_icm;
11181};
11182
b169e64a
YK		 11183struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11184 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11185 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
11186};
11187
eff8ea8f
FD		 11188struct mlx5_ifc_mtrc_string_db_param_bits {
11189 u8 string_db_base_address[0x20];
11190
11191 u8 reserved_at_20[0x8];
11192 u8 string_db_size[0x18];
11193};
11194
11195struct mlx5_ifc_mtrc_cap_bits {
11196 u8 trace_owner[0x1];
11197 u8 trace_to_memory[0x1];
11198 u8 reserved_at_2[0x4];
11199 u8 trc_ver[0x2];
11200 u8 reserved_at_8[0x14];
11201 u8 num_string_db[0x4];
11202
11203 u8 first_string_trace[0x8];
11204 u8 num_string_trace[0x8];
11205 u8 reserved_at_30[0x28];
11206
11207 u8 log_max_trace_buffer_size[0x8];
11208
11209 u8 reserved_at_60[0x20];
11210
11211 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11212
11213 u8 reserved_at_280[0x180];
11214};
11215
11216struct mlx5_ifc_mtrc_conf_bits {
11217 u8 reserved_at_0[0x1c];
11218 u8 trace_mode[0x4];
11219 u8 reserved_at_20[0x18];
11220 u8 log_trace_buffer_size[0x8];
11221 u8 trace_mkey[0x20];
11222 u8 reserved_at_60[0x3a0];
11223};
11224
11225struct mlx5_ifc_mtrc_stdb_bits {
11226 u8 string_db_index[0x4];
11227 u8 reserved_at_4[0x4];
11228 u8 read_size[0x18];
11229 u8 start_offset[0x20];
b6ca09cb 11230 u8 string_db_data[];
eff8ea8f
FD		 11231};
11232
11233struct mlx5_ifc_mtrc_ctrl_bits {
11234 u8 trace_status[0x2];
11235 u8 reserved_at_2[0x2];
11236 u8 arm_event[0x1];
11237 u8 reserved_at_5[0xb];
11238 u8 modify_field_select[0x10];
11239 u8 reserved_at_20[0x2b];
11240 u8 current_timestamp52_32[0x15];
11241 u8 current_timestamp31_0[0x20];
11242 u8 reserved_at_80[0x180];
11243};
11244
c3a4e9f1
BW		 11245struct mlx5_ifc_host_params_context_bits {
11246 u8 host_number[0x8];
5ccf2770
BW		 11247 u8 reserved_at_8[0x7];
11248 u8 host_pf_disabled[0x1];
c3a4e9f1
BW		 11249 u8 host_num_of_vfs[0x10];
11250
86eec50b 11251 u8 host_total_vfs[0x10];
c3a4e9f1
BW		 11252 u8 host_pci_bus[0x10];
11253
11254 u8 reserved_at_40[0x10];
11255 u8 host_pci_device[0x10];
11256
11257 u8 reserved_at_60[0x10];
11258 u8 host_pci_function[0x10];
11259
11260 u8 reserved_at_80[0x180];
11261};
11262
cd56f929 11263struct mlx5_ifc_query_esw_functions_in_bits {
c3a4e9f1
BW		 11264 u8 opcode[0x10];
11265 u8 reserved_at_10[0x10];
11266
11267 u8 reserved_at_20[0x10];
11268 u8 op_mod[0x10];
11269
11270 u8 reserved_at_40[0x40];
11271};
11272
cd56f929 11273struct mlx5_ifc_query_esw_functions_out_bits {
c3a4e9f1
BW		 11274 u8 status[0x8];
11275 u8 reserved_at_8[0x18];
11276
11277 u8 syndrome[0x20];
11278
11279 u8 reserved_at_40[0x40];
11280
11281 struct mlx5_ifc_host_params_context_bits host_params_context;
11282
11283 u8 reserved_at_280[0x180];
b6ca09cb 11284 u8 host_sf_enable[][0x40];
1759d322
PP		 11285};
11286
11287struct mlx5_ifc_sf_partition_bits {
11288 u8 reserved_at_0[0x10];
11289 u8 log_num_sf[0x8];
11290 u8 log_sf_bar_size[0x8];
11291};
11292
11293struct mlx5_ifc_query_sf_partitions_out_bits {
11294 u8 status[0x8];
11295 u8 reserved_at_8[0x18];
11296
11297 u8 syndrome[0x20];
11298
11299 u8 reserved_at_40[0x18];
11300 u8 num_sf_partitions[0x8];
11301
11302 u8 reserved_at_60[0x20];
11303
b6ca09cb 11304 struct mlx5_ifc_sf_partition_bits sf_partition[];
1759d322
PP		 11305};
11306
11307struct mlx5_ifc_query_sf_partitions_in_bits {
11308 u8 opcode[0x10];
11309 u8 reserved_at_10[0x10];
11310
11311 u8 reserved_at_20[0x10];
11312 u8 op_mod[0x10];
11313
11314 u8 reserved_at_40[0x40];
11315};
11316
11317struct mlx5_ifc_dealloc_sf_out_bits {
11318 u8 status[0x8];
11319 u8 reserved_at_8[0x18];
11320
11321 u8 syndrome[0x20];
11322
11323 u8 reserved_at_40[0x40];
11324};
11325
11326struct mlx5_ifc_dealloc_sf_in_bits {
11327 u8 opcode[0x10];
11328 u8 reserved_at_10[0x10];
11329
11330 u8 reserved_at_20[0x10];
11331 u8 op_mod[0x10];
11332
11333 u8 reserved_at_40[0x10];
11334 u8 function_id[0x10];
11335
11336 u8 reserved_at_60[0x20];
11337};
11338
11339struct mlx5_ifc_alloc_sf_out_bits {
11340 u8 status[0x8];
11341 u8 reserved_at_8[0x18];
11342
11343 u8 syndrome[0x20];
11344
11345 u8 reserved_at_40[0x40];
11346};
11347
11348struct mlx5_ifc_alloc_sf_in_bits {
11349 u8 opcode[0x10];
11350 u8 reserved_at_10[0x10];
11351
11352 u8 reserved_at_20[0x10];
11353 u8 op_mod[0x10];
11354
11355 u8 reserved_at_40[0x10];
11356 u8 function_id[0x10];
11357
11358 u8 reserved_at_60[0x20];
c3a4e9f1
BW		 11359};
11360
e4075c44
YH		 11361struct mlx5_ifc_affiliated_event_header_bits {
11362 u8 reserved_at_0[0x10];
11363 u8 obj_type[0x10];
11364
11365 u8 obj_id[0x20];
11366};
11367
a12ff35e 11368enum {
49e27134
PP		 11369 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11370 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11371 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
a12ff35e
EBE		 11372};
11373
11374enum {
11375 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
2b58f6d9 11376 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
2a297089 11377 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
2b58f6d9
RS		 11378};
11379
11380enum {
11381 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
2b58f6d9
RS		 11382};
11383
11384struct mlx5_ifc_ipsec_obj_bits {
11385 u8 modify_field_select[0x40];
11386 u8 full_offload[0x1];
11387 u8 reserved_at_41[0x1];
11388 u8 esn_en[0x1];
11389 u8 esn_overlap[0x1];
11390 u8 reserved_at_44[0x2];
11391 u8 icv_length[0x2];
11392 u8 reserved_at_48[0x4];
11393 u8 aso_return_reg[0x4];
11394 u8 reserved_at_50[0x10];
11395
11396 u8 esn_msb[0x20];
11397
11398 u8 reserved_at_80[0x8];
11399 u8 dekn[0x18];
11400
11401 u8 salt[0x20];
11402
11403 u8 implicit_iv[0x40];
11404
11405 u8 reserved_at_100[0x700];
11406};
11407
11408struct mlx5_ifc_create_ipsec_obj_in_bits {
11409 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11410 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11411};
11412
11413enum {
11414 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11415 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11416};
11417
11418struct mlx5_ifc_query_ipsec_obj_out_bits {
11419 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11420 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11421};
11422
11423struct mlx5_ifc_modify_ipsec_obj_in_bits {
11424 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11425 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
a12ff35e
EBE		 11426};
11427
11428struct mlx5_ifc_encryption_key_obj_bits {
11429 u8 modify_field_select[0x40];
11430
11431 u8 reserved_at_40[0x14];
11432 u8 key_size[0x4];
11433 u8 reserved_at_58[0x4];
11434 u8 key_type[0x4];
11435
11436 u8 reserved_at_60[0x8];
11437 u8 pd[0x18];
11438
11439 u8 reserved_at_80[0x180];
11440 u8 key[8][0x20];
11441
11442 u8 reserved_at_300[0x500];
11443};
11444
11445struct mlx5_ifc_create_encryption_key_in_bits {
11446 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11447 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11448};
11449
2a297089
CM		 11450struct mlx5_ifc_sampler_obj_bits {
11451 u8 modify_field_select[0x40];
11452
11453 u8 table_type[0x8];
11454 u8 level[0x8];
11455 u8 reserved_at_50[0xf];
11456 u8 ignore_flow_level[0x1];
11457
11458 u8 sample_ratio[0x20];
11459
11460 u8 reserved_at_80[0x8];
11461 u8 sample_table_id[0x18];
11462
11463 u8 reserved_at_a0[0x8];
11464 u8 default_table_id[0x18];
11465
11466 u8 sw_steering_icm_address_rx[0x40];
11467 u8 sw_steering_icm_address_tx[0x40];
11468
11469 u8 reserved_at_140[0xa0];
11470};
11471
11472struct mlx5_ifc_create_sampler_obj_in_bits {
11473 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11474 struct mlx5_ifc_sampler_obj_bits sampler_object;
11475};
11476
1ab6dc35
YK		 11477struct mlx5_ifc_query_sampler_obj_out_bits {
11478 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11479 struct mlx5_ifc_sampler_obj_bits sampler_object;
11480};
11481
a12ff35e
EBE		 11482enum {
11483 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11484 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11485};
11486
11487enum {
bd673da6
SM		 11488 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11489 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
a12ff35e
EBE		 11490};
11491
11492struct mlx5_ifc_tls_static_params_bits {
11493 u8 const_2[0x2];
11494 u8 tls_version[0x4];
11495 u8 const_1[0x2];
11496 u8 reserved_at_8[0x14];
11497 u8 encryption_standard[0x4];
11498
11499 u8 reserved_at_20[0x20];
11500
11501 u8 initial_record_number[0x40];
11502
11503 u8 resync_tcp_sn[0x20];
11504
11505 u8 gcm_iv[0x20];
11506
11507 u8 implicit_iv[0x40];
11508
11509 u8 reserved_at_100[0x8];
11510 u8 dek_index[0x18];
11511
11512 u8 reserved_at_120[0xe0];
11513};
11514
11515struct mlx5_ifc_tls_progress_params_bits {
a12ff35e
EBE		 11516 u8 next_record_tcp_sn[0x20];
11517
11518 u8 hw_resync_tcp_sn[0x20];
11519
11520 u8 record_tracker_state[0x2];
11521 u8 auth_state[0x2];
2d1b69ed 11522 u8 reserved_at_44[0x4];
a12ff35e
EBE		 11523 u8 hw_offset_record_number[0x18];
11524};
11525
1dcb6c36
EC		 11526enum {
11527 MLX5_MTT_PERM_READ = 1 << 0,
11528 MLX5_MTT_PERM_WRITE = 1 << 1,
11529 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11530};
11531
adfdaff3
YH		 11532enum {
11533 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
11534 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
11535};
11536
11537struct mlx5_ifc_suspend_vhca_in_bits {
11538 u8 opcode[0x10];
11539 u8 uid[0x10];
11540
11541 u8 reserved_at_20[0x10];
11542 u8 op_mod[0x10];
11543
11544 u8 reserved_at_40[0x10];
11545 u8 vhca_id[0x10];
11546
11547 u8 reserved_at_60[0x20];
11548};
11549
11550struct mlx5_ifc_suspend_vhca_out_bits {
11551 u8 status[0x8];
11552 u8 reserved_at_8[0x18];
11553
11554 u8 syndrome[0x20];
11555
11556 u8 reserved_at_40[0x40];
11557};
11558
11559enum {
11560 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
11561 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
11562};
11563
11564struct mlx5_ifc_resume_vhca_in_bits {
11565 u8 opcode[0x10];
11566 u8 uid[0x10];
11567
11568 u8 reserved_at_20[0x10];
11569 u8 op_mod[0x10];
11570
11571 u8 reserved_at_40[0x10];
11572 u8 vhca_id[0x10];
11573
11574 u8 reserved_at_60[0x20];
11575};
11576
11577struct mlx5_ifc_resume_vhca_out_bits {
11578 u8 status[0x8];
11579 u8 reserved_at_8[0x18];
11580
11581 u8 syndrome[0x20];
11582
11583 u8 reserved_at_40[0x40];
11584};
11585
11586struct mlx5_ifc_query_vhca_migration_state_in_bits {
11587 u8 opcode[0x10];
11588 u8 uid[0x10];
11589
11590 u8 reserved_at_20[0x10];
11591 u8 op_mod[0x10];
11592
11593 u8 reserved_at_40[0x10];
11594 u8 vhca_id[0x10];
11595
11596 u8 reserved_at_60[0x20];
11597};
11598
11599struct mlx5_ifc_query_vhca_migration_state_out_bits {
11600 u8 status[0x8];
11601 u8 reserved_at_8[0x18];
11602
11603 u8 syndrome[0x20];
11604
11605 u8 reserved_at_40[0x40];
11606
11607 u8 required_umem_size[0x20];
11608
11609 u8 reserved_at_a0[0x160];
11610};
11611
11612struct mlx5_ifc_save_vhca_state_in_bits {
11613 u8 opcode[0x10];
11614 u8 uid[0x10];
11615
11616 u8 reserved_at_20[0x10];
11617 u8 op_mod[0x10];
11618
11619 u8 reserved_at_40[0x10];
11620 u8 vhca_id[0x10];
11621
11622 u8 reserved_at_60[0x20];
11623
11624 u8 va[0x40];
11625
11626 u8 mkey[0x20];
11627
11628 u8 size[0x20];
11629};
11630
11631struct mlx5_ifc_save_vhca_state_out_bits {
11632 u8 status[0x8];
11633 u8 reserved_at_8[0x18];
11634
11635 u8 syndrome[0x20];
11636
11637 u8 actual_image_size[0x20];
11638
11639 u8 reserved_at_60[0x20];
11640};
11641
11642struct mlx5_ifc_load_vhca_state_in_bits {
11643 u8 opcode[0x10];
11644 u8 uid[0x10];
11645
11646 u8 reserved_at_20[0x10];
11647 u8 op_mod[0x10];
11648
11649 u8 reserved_at_40[0x10];
11650 u8 vhca_id[0x10];
11651
11652 u8 reserved_at_60[0x20];
11653
11654 u8 va[0x40];
11655
11656 u8 mkey[0x20];
11657
11658 u8 size[0x20];
11659};
11660
11661struct mlx5_ifc_load_vhca_state_out_bits {
11662 u8 status[0x8];
11663 u8 reserved_at_8[0x18];
11664
11665 u8 syndrome[0x20];
11666
11667 u8 reserved_at_40[0x40];
11668};
11669
d29b796a 11670#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)