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net/mlx5e: Vxlan, reflect 4789 UDP port default addition to software database
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
66enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71};
72
f91e6d89
EBE		 73enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
76};
77
38b7ca92
YH		 78enum {
79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
81};
82
83enum {
84 MLX5_OBJ_TYPE_UCTX = 0x0004,
85};
86
d29b796a
EC		 87enum {
88 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
89 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
90 MLX5_CMD_OP_INIT_HCA = 0x102,
91 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
92 MLX5_CMD_OP_ENABLE_HCA = 0x104,
93 MLX5_CMD_OP_DISABLE_HCA = 0x105,
94 MLX5_CMD_OP_QUERY_PAGES = 0x107,
95 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
96 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 97 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
98 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 99 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 100 MLX5_CMD_OP_CREATE_MKEY = 0x200,
101 MLX5_CMD_OP_QUERY_MKEY = 0x201,
102 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
103 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
104 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 105 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
106 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 107 MLX5_CMD_OP_CREATE_EQ = 0x301,
108 MLX5_CMD_OP_DESTROY_EQ = 0x302,
109 MLX5_CMD_OP_QUERY_EQ = 0x303,
110 MLX5_CMD_OP_GEN_EQE = 0x304,
111 MLX5_CMD_OP_CREATE_CQ = 0x400,
112 MLX5_CMD_OP_DESTROY_CQ = 0x401,
113 MLX5_CMD_OP_QUERY_CQ = 0x402,
114 MLX5_CMD_OP_MODIFY_CQ = 0x403,
115 MLX5_CMD_OP_CREATE_QP = 0x500,
116 MLX5_CMD_OP_DESTROY_QP = 0x501,
117 MLX5_CMD_OP_RST2INIT_QP = 0x502,
118 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
119 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
120 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
121 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
122 MLX5_CMD_OP_2ERR_QP = 0x507,
123 MLX5_CMD_OP_2RST_QP = 0x50a,
124 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 125 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 126 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
127 MLX5_CMD_OP_CREATE_PSV = 0x600,
128 MLX5_CMD_OP_DESTROY_PSV = 0x601,
129 MLX5_CMD_OP_CREATE_SRQ = 0x700,
130 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
131 MLX5_CMD_OP_QUERY_SRQ = 0x702,
132 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 133 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
134 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
135 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
136 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 137 MLX5_CMD_OP_CREATE_DCT = 0x710,
138 MLX5_CMD_OP_DESTROY_DCT = 0x711,
139 MLX5_CMD_OP_DRAIN_DCT = 0x712,
140 MLX5_CMD_OP_QUERY_DCT = 0x713,
141 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 142 MLX5_CMD_OP_CREATE_XRQ = 0x717,
143 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
144 MLX5_CMD_OP_QUERY_XRQ = 0x719,
145 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 146 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
147 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
148 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
149 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
150 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
151 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 152 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 153 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 154 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
155 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
156 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
157 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 158 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 159 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
160 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
161 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
162 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
37e92a9d 163 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 164 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 165 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
166 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
167 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
168 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
169 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
170 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 171 MLX5_CMD_OP_ALLOC_PD = 0x800,
172 MLX5_CMD_OP_DEALLOC_PD = 0x801,
173 MLX5_CMD_OP_ALLOC_UAR = 0x802,
174 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
175 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
176 MLX5_CMD_OP_ACCESS_REG = 0x805,
177 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 178 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 179 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
180 MLX5_CMD_OP_MAD_IFC = 0x50d,
181 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
182 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
183 MLX5_CMD_OP_NOP = 0x80d,
184 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
185 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 186 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
187 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
188 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
189 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
190 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
191 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
192 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
193 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
194 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
195 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
196 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
197 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 198 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
199 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 200 MLX5_CMD_OP_CREATE_LAG = 0x840,
201 MLX5_CMD_OP_MODIFY_LAG = 0x841,
202 MLX5_CMD_OP_QUERY_LAG = 0x842,
203 MLX5_CMD_OP_DESTROY_LAG = 0x843,
204 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
205 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 206 MLX5_CMD_OP_CREATE_TIR = 0x900,
207 MLX5_CMD_OP_MODIFY_TIR = 0x901,
208 MLX5_CMD_OP_DESTROY_TIR = 0x902,
209 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 210 MLX5_CMD_OP_CREATE_SQ = 0x904,
211 MLX5_CMD_OP_MODIFY_SQ = 0x905,
212 MLX5_CMD_OP_DESTROY_SQ = 0x906,
213 MLX5_CMD_OP_QUERY_SQ = 0x907,
214 MLX5_CMD_OP_CREATE_RQ = 0x908,
215 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 216 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 217 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
218 MLX5_CMD_OP_QUERY_RQ = 0x90b,
219 MLX5_CMD_OP_CREATE_RMP = 0x90c,
220 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
221 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
222 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 223 MLX5_CMD_OP_CREATE_TIS = 0x912,
224 MLX5_CMD_OP_MODIFY_TIS = 0x913,
225 MLX5_CMD_OP_DESTROY_TIS = 0x914,
226 MLX5_CMD_OP_QUERY_TIS = 0x915,
227 MLX5_CMD_OP_CREATE_RQT = 0x916,
228 MLX5_CMD_OP_MODIFY_RQT = 0x917,
229 MLX5_CMD_OP_DESTROY_RQT = 0x918,
230 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 231 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 232 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
233 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
234 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
235 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
236 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
237 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
238 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
239 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 240 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
242 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
243 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 244 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 245 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
246 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 247 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
248 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 249 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
250 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
251 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
252 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
253 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92
YH		 254 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
255 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
86d56a1a 256 MLX5_CMD_OP_MAX
e281682b
SM		 257};
258
259struct mlx5_ifc_flow_table_fields_supported_bits {
260 u8 outer_dmac[0x1];
261 u8 outer_smac[0x1];
262 u8 outer_ether_type[0x1];
19cc7524 263 u8 outer_ip_version[0x1];
e281682b
SM		 264 u8 outer_first_prio[0x1];
265 u8 outer_first_cfi[0x1];
266 u8 outer_first_vid[0x1];
a8ade55f 267 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 268 u8 outer_second_prio[0x1];
269 u8 outer_second_cfi[0x1];
270 u8 outer_second_vid[0x1];
b4ff3a36 271 u8 reserved_at_b[0x1];
e281682b
SM		 272 u8 outer_sip[0x1];
273 u8 outer_dip[0x1];
274 u8 outer_frag[0x1];
275 u8 outer_ip_protocol[0x1];
276 u8 outer_ip_ecn[0x1];
277 u8 outer_ip_dscp[0x1];
278 u8 outer_udp_sport[0x1];
279 u8 outer_udp_dport[0x1];
280 u8 outer_tcp_sport[0x1];
281 u8 outer_tcp_dport[0x1];
282 u8 outer_tcp_flags[0x1];
283 u8 outer_gre_protocol[0x1];
284 u8 outer_gre_key[0x1];
285 u8 outer_vxlan_vni[0x1];
b4ff3a36 286 u8 reserved_at_1a[0x5];
e281682b
SM		 287 u8 source_eswitch_port[0x1];
288
289 u8 inner_dmac[0x1];
290 u8 inner_smac[0x1];
291 u8 inner_ether_type[0x1];
19cc7524 292 u8 inner_ip_version[0x1];
e281682b
SM		 293 u8 inner_first_prio[0x1];
294 u8 inner_first_cfi[0x1];
295 u8 inner_first_vid[0x1];
b4ff3a36 296 u8 reserved_at_27[0x1];
e281682b
SM		 297 u8 inner_second_prio[0x1];
298 u8 inner_second_cfi[0x1];
299 u8 inner_second_vid[0x1];
b4ff3a36 300 u8 reserved_at_2b[0x1];
e281682b
SM		 301 u8 inner_sip[0x1];
302 u8 inner_dip[0x1];
303 u8 inner_frag[0x1];
304 u8 inner_ip_protocol[0x1];
305 u8 inner_ip_ecn[0x1];
306 u8 inner_ip_dscp[0x1];
307 u8 inner_udp_sport[0x1];
308 u8 inner_udp_dport[0x1];
309 u8 inner_tcp_sport[0x1];
310 u8 inner_tcp_dport[0x1];
311 u8 inner_tcp_flags[0x1];
b4ff3a36 312 u8 reserved_at_37[0x9];
71c6e863
AL		 313
314 u8 reserved_at_40[0x5];
315 u8 outer_first_mpls_over_udp[0x4];
316 u8 outer_first_mpls_over_gre[0x4];
317 u8 inner_first_mpls[0x4];
318 u8 outer_first_mpls[0x4];
319 u8 reserved_at_55[0x2];
3346c487 320 u8 outer_esp_spi[0x1];
71c6e863 321 u8 reserved_at_58[0x2];
a550ddfc 322 u8 bth_dst_qp[0x1];
e281682b 323
a550ddfc 324 u8 reserved_at_5b[0x25];
e281682b
SM		 325};
326
327struct mlx5_ifc_flow_table_prop_layout_bits {
328 u8 ft_support[0x1];
9dc0b289
AV		 329 u8 reserved_at_1[0x1];
330 u8 flow_counter[0x1];
26a81453 331 u8 flow_modify_en[0x1];
2cc43b49 332 u8 modify_root[0x1];
34a40e68
MG		 333 u8 identified_miss_table_mode[0x1];
334 u8 flow_table_modify[0x1];
7adbde20
HHZ		 335 u8 encap[0x1];
336 u8 decap[0x1];
0c06897a
OG		 337 u8 reserved_at_9[0x1];
338 u8 pop_vlan[0x1];
339 u8 push_vlan[0x1];
8da6fe2a
JL		 340 u8 reserved_at_c[0x1];
341 u8 pop_vlan_2[0x1];
342 u8 push_vlan_2[0x1];
343 u8 reserved_at_f[0x11];
e281682b 344
b4ff3a36 345 u8 reserved_at_20[0x2];
e281682b 346 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 347 u8 log_max_modify_header_context[0x8];
348 u8 max_modify_header_actions[0x8];
e281682b
SM		 349 u8 max_ft_level[0x8];
350
b4ff3a36 351 u8 reserved_at_40[0x20];
e281682b 352
b4ff3a36 353 u8 reserved_at_60[0x18];
e281682b
SM		 354 u8 log_max_ft_num[0x8];
355
b4ff3a36 356 u8 reserved_at_80[0x18];
e281682b
SM		 357 u8 log_max_destination[0x8];
358
16f1c5bb
RS		 359 u8 log_max_flow_counter[0x8];
360 u8 reserved_at_a8[0x10];
e281682b
SM		 361 u8 log_max_flow[0x8];
362
b4ff3a36 363 u8 reserved_at_c0[0x40];
e281682b
SM		 364
365 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
366
367 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
368};
369
370struct mlx5_ifc_odp_per_transport_service_cap_bits {
371 u8 send[0x1];
372 u8 receive[0x1];
373 u8 write[0x1];
374 u8 read[0x1];
17d2f88f 375 u8 atomic[0x1];
e281682b 376 u8 srq_receive[0x1];
b4ff3a36 377 u8 reserved_at_6[0x1a];
e281682b
SM		 378};
379
380struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
381 u8 smac_47_16[0x20];
382
383 u8 smac_15_0[0x10];
384 u8 ethertype[0x10];
385
386 u8 dmac_47_16[0x20];
387
388 u8 dmac_15_0[0x10];
389 u8 first_prio[0x3];
390 u8 first_cfi[0x1];
391 u8 first_vid[0xc];
392
393 u8 ip_protocol[0x8];
394 u8 ip_dscp[0x6];
395 u8 ip_ecn[0x2];
10543365
MHY		 396 u8 cvlan_tag[0x1];
397 u8 svlan_tag[0x1];
e281682b 398 u8 frag[0x1];
19cc7524 399 u8 ip_version[0x4];
e281682b
SM		 400 u8 tcp_flags[0x9];
401
402 u8 tcp_sport[0x10];
403 u8 tcp_dport[0x10];
404
a8ade55f
OG		 405 u8 reserved_at_c0[0x18];
406 u8 ttl_hoplimit[0x8];
e281682b
SM		 407
408 u8 udp_sport[0x10];
409 u8 udp_dport[0x10];
410
b4d1f032 411 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 412
b4d1f032 413 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 414};
415
416struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 417 u8 reserved_at_0[0x8];
418 u8 source_sqn[0x18];
e281682b 419
3e99df87 420 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 421 u8 source_port[0x10];
422
423 u8 outer_second_prio[0x3];
424 u8 outer_second_cfi[0x1];
425 u8 outer_second_vid[0xc];
426 u8 inner_second_prio[0x3];
427 u8 inner_second_cfi[0x1];
428 u8 inner_second_vid[0xc];
429
10543365
MHY		 430 u8 outer_second_cvlan_tag[0x1];
431 u8 inner_second_cvlan_tag[0x1];
432 u8 outer_second_svlan_tag[0x1];
433 u8 inner_second_svlan_tag[0x1];
434 u8 reserved_at_64[0xc];
e281682b
SM		 435 u8 gre_protocol[0x10];
436
437 u8 gre_key_h[0x18];
438 u8 gre_key_l[0x8];
439
440 u8 vxlan_vni[0x18];
b4ff3a36 441 u8 reserved_at_b8[0x8];
e281682b 442
b4ff3a36 443 u8 reserved_at_c0[0x20];
e281682b 444
b4ff3a36 445 u8 reserved_at_e0[0xc];
e281682b
SM		 446 u8 outer_ipv6_flow_label[0x14];
447
b4ff3a36 448 u8 reserved_at_100[0xc];
e281682b
SM		 449 u8 inner_ipv6_flow_label[0x14];
450
a550ddfc
YH		 451 u8 reserved_at_120[0x28];
452 u8 bth_dst_qp[0x18];
3346c487
BP		 453 u8 reserved_at_160[0x20];
454 u8 outer_esp_spi[0x20];
455 u8 reserved_at_1a0[0x60];
e281682b
SM		 456};
457
71c6e863
AL		 458struct mlx5_ifc_fte_match_mpls_bits {
459 u8 mpls_label[0x14];
460 u8 mpls_exp[0x3];
461 u8 mpls_s_bos[0x1];
462 u8 mpls_ttl[0x8];
463};
464
465struct mlx5_ifc_fte_match_set_misc2_bits {
466 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
467
468 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
469
470 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
471
472 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
473
474 u8 reserved_at_80[0x100];
475
476 u8 metadata_reg_a[0x20];
477
478 u8 reserved_at_1a0[0x60];
479};
480
e281682b
SM		 481struct mlx5_ifc_cmd_pas_bits {
482 u8 pa_h[0x20];
483
484 u8 pa_l[0x14];
b4ff3a36 485 u8 reserved_at_34[0xc];
e281682b
SM		 486};
487
488struct mlx5_ifc_uint64_bits {
489 u8 hi[0x20];
490
491 u8 lo[0x20];
492};
493
494enum {
495 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
496 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
497 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
498 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
499 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
500 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
501 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
502 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
503 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
504 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
505};
506
507struct mlx5_ifc_ads_bits {
508 u8 fl[0x1];
509 u8 free_ar[0x1];
b4ff3a36 510 u8 reserved_at_2[0xe];
e281682b
SM		 511 u8 pkey_index[0x10];
512
b4ff3a36 513 u8 reserved_at_20[0x8];
e281682b
SM		 514 u8 grh[0x1];
515 u8 mlid[0x7];
516 u8 rlid[0x10];
517
518 u8 ack_timeout[0x5];
b4ff3a36 519 u8 reserved_at_45[0x3];
e281682b 520 u8 src_addr_index[0x8];
b4ff3a36 521 u8 reserved_at_50[0x4];
e281682b
SM		 522 u8 stat_rate[0x4];
523 u8 hop_limit[0x8];
524
b4ff3a36 525 u8 reserved_at_60[0x4];
e281682b
SM		 526 u8 tclass[0x8];
527 u8 flow_label[0x14];
528
529 u8 rgid_rip[16][0x8];
530
b4ff3a36 531 u8 reserved_at_100[0x4];
e281682b
SM		 532 u8 f_dscp[0x1];
533 u8 f_ecn[0x1];
b4ff3a36 534 u8 reserved_at_106[0x1];
e281682b
SM		 535 u8 f_eth_prio[0x1];
536 u8 ecn[0x2];
537 u8 dscp[0x6];
538 u8 udp_sport[0x10];
539
540 u8 dei_cfi[0x1];
541 u8 eth_prio[0x3];
542 u8 sl[0x4];
32f69e4b 543 u8 vhca_port_num[0x8];
e281682b
SM		 544 u8 rmac_47_32[0x10];
545
546 u8 rmac_31_0[0x20];
547};
548
549struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 550 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 551 u8 nic_rx_multi_path_tirs_fts[0x1];
552 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
553 u8 reserved_at_3[0x1fd];
e281682b
SM		 554
555 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
556
b4ff3a36 557 u8 reserved_at_400[0x200];
e281682b
SM		 558
559 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
560
561 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
562
b4ff3a36 563 u8 reserved_at_a00[0x200];
e281682b
SM		 564
565 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
566
b4ff3a36 567 u8 reserved_at_e00[0x7200];
e281682b
SM		 568};
569
495716b1 570struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4563002
CM		 571 u8 reserved_at_0[0x1c];
572 u8 fdb_multi_path_to_table[0x1];
573 u8 reserved_at_1d[0x1e3];
495716b1
SM		 574
575 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
576
577 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
578
579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
580
b4ff3a36 581 u8 reserved_at_800[0x7800];
495716b1
SM		 582};
583
d6666753
SM		 584struct mlx5_ifc_e_switch_cap_bits {
585 u8 vport_svlan_strip[0x1];
586 u8 vport_cvlan_strip[0x1];
587 u8 vport_svlan_insert[0x1];
588 u8 vport_cvlan_insert_if_not_exist[0x1];
589 u8 vport_cvlan_insert_overwrite[0x1];
a6d04569
RD		 590 u8 reserved_at_5[0x18];
591 u8 merged_eswitch[0x1];
23898c76
NO		 592 u8 nic_vport_node_guid_modify[0x1];
593 u8 nic_vport_port_guid_modify[0x1];
d6666753 594
7adbde20
HHZ		 595 u8 vxlan_encap_decap[0x1];
596 u8 nvgre_encap_decap[0x1];
597 u8 reserved_at_22[0x9];
598 u8 log_max_encap_headers[0x5];
599 u8 reserved_2b[0x6];
600 u8 max_encap_header_size[0xa];
601
602 u8 reserved_40[0x7c0];
603
d6666753
SM		 604};
605
7486216b
SM		 606struct mlx5_ifc_qos_cap_bits {
607 u8 packet_pacing[0x1];
813f8540 608 u8 esw_scheduling[0x1];
c9497c98
MHY		 609 u8 esw_bw_share[0x1];
610 u8 esw_rate_limit[0x1];
05d3ac97
BW		 611 u8 reserved_at_4[0x1];
612 u8 packet_pacing_burst_bound[0x1];
613 u8 packet_pacing_typical_size[0x1];
614 u8 reserved_at_7[0x19];
813f8540
MHY		 615
616 u8 reserved_at_20[0x20];
617
7486216b 618 u8 packet_pacing_max_rate[0x20];
813f8540 619
7486216b 620 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 621
622 u8 reserved_at_80[0x10];
7486216b 623 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 624
625 u8 esw_element_type[0x10];
626 u8 esw_tsar_type[0x10];
627
628 u8 reserved_at_c0[0x10];
629 u8 max_qos_para_vport[0x10];
630
631 u8 max_tsar_bw_share[0x20];
632
633 u8 reserved_at_100[0x700];
7486216b
SM		 634};
635
2fcb12df
IK		 636struct mlx5_ifc_debug_cap_bits {
637 u8 reserved_at_0[0x20];
638
639 u8 reserved_at_20[0x2];
640 u8 stall_detect[0x1];
641 u8 reserved_at_23[0x1d];
642
643 u8 reserved_at_40[0x7c0];
644};
645
e281682b
SM		 646struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
647 u8 csum_cap[0x1];
648 u8 vlan_cap[0x1];
649 u8 lro_cap[0x1];
650 u8 lro_psh_flag[0x1];
651 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 652 u8 reserved_at_5[0x2];
653 u8 wqe_vlan_insert[0x1];
66189961 654 u8 self_lb_en_modifiable[0x1];
b4ff3a36 655 u8 reserved_at_9[0x2];
e281682b 656 u8 max_lso_cap[0x5];
c226dc22 657 u8 multi_pkt_send_wqe[0x2];
cff92d7c 658 u8 wqe_inline_mode[0x2];
e281682b 659 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 660 u8 reg_umr_sq[0x1];
661 u8 scatter_fcs[0x1];
050da902 662 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 663 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 664 u8 reserved_at_1c[0x2];
27299841 665 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 666 u8 tunnel_stateless_vxlan[0x1];
667
547eede0
IT		 668 u8 swp[0x1];
669 u8 swp_csum[0x1];
670 u8 swp_lso[0x1];
4d350f1f
MG		 671 u8 reserved_at_23[0x1b];
672 u8 max_geneve_opt_len[0x1];
673 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 674
b4ff3a36 675 u8 reserved_at_40[0x10];
e281682b
SM		 676 u8 lro_min_mss_size[0x10];
677
b4ff3a36 678 u8 reserved_at_60[0x120];
e281682b
SM		 679
680 u8 lro_timer_supported_periods[4][0x20];
681
b4ff3a36 682 u8 reserved_at_200[0x600];
e281682b
SM		 683};
684
685struct mlx5_ifc_roce_cap_bits {
686 u8 roce_apm[0x1];
b4ff3a36 687 u8 reserved_at_1[0x1f];
e281682b 688
b4ff3a36 689 u8 reserved_at_20[0x60];
e281682b 690
b4ff3a36 691 u8 reserved_at_80[0xc];
e281682b 692 u8 l3_type[0x4];
b4ff3a36 693 u8 reserved_at_90[0x8];
e281682b
SM		 694 u8 roce_version[0x8];
695
b4ff3a36 696 u8 reserved_at_a0[0x10];
e281682b
SM		 697 u8 r_roce_dest_udp_port[0x10];
698
699 u8 r_roce_max_src_udp_port[0x10];
700 u8 r_roce_min_src_udp_port[0x10];
701
b4ff3a36 702 u8 reserved_at_e0[0x10];
e281682b
SM		 703 u8 roce_address_table_size[0x10];
704
b4ff3a36 705 u8 reserved_at_100[0x700];
e281682b
SM		 706};
707
e72bd817
AL		 708struct mlx5_ifc_device_mem_cap_bits {
709 u8 memic[0x1];
710 u8 reserved_at_1[0x1f];
711
712 u8 reserved_at_20[0xb];
713 u8 log_min_memic_alloc_size[0x5];
714 u8 reserved_at_30[0x8];
715 u8 log_max_memic_addr_alignment[0x8];
716
717 u8 memic_bar_start_addr[0x40];
718
719 u8 memic_bar_size[0x20];
720
721 u8 max_memic_size[0x20];
722
723 u8 reserved_at_c0[0x740];
724};
725
e281682b
SM		 726enum {
727 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
728 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
729 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
730 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
731 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
732 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
733 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
734 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
735 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
736};
737
738enum {
739 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
740 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
741 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
742 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
743 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
744 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
745 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
746 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
748};
749
750struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 751 u8 reserved_at_0[0x40];
e281682b 752
bd10838a 753 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 754 u8 reserved_at_42[0x4];
bd10838a 755 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 756
b4ff3a36 757 u8 reserved_at_47[0x19];
e281682b 758
b4ff3a36 759 u8 reserved_at_60[0x20];
e281682b 760
b4ff3a36 761 u8 reserved_at_80[0x10];
f91e6d89 762 u8 atomic_operations[0x10];
e281682b 763
b4ff3a36 764 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 765 u8 atomic_size_qp[0x10];
766
b4ff3a36 767 u8 reserved_at_c0[0x10];
e281682b
SM		 768 u8 atomic_size_dc[0x10];
769
b4ff3a36 770 u8 reserved_at_e0[0x720];
e281682b
SM		 771};
772
773struct mlx5_ifc_odp_cap_bits {
b4ff3a36 774 u8 reserved_at_0[0x40];
e281682b
SM		 775
776 u8 sig[0x1];
b4ff3a36 777 u8 reserved_at_41[0x1f];
e281682b 778
b4ff3a36 779 u8 reserved_at_60[0x20];
e281682b
SM		 780
781 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
782
783 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
784
785 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
786
b4ff3a36 787 u8 reserved_at_e0[0x720];
e281682b
SM		 788};
789
3f0393a5
SG		 790struct mlx5_ifc_calc_op {
791 u8 reserved_at_0[0x10];
792 u8 reserved_at_10[0x9];
793 u8 op_swap_endianness[0x1];
794 u8 op_min[0x1];
795 u8 op_xor[0x1];
796 u8 op_or[0x1];
797 u8 op_and[0x1];
798 u8 op_max[0x1];
799 u8 op_add[0x1];
800};
801
802struct mlx5_ifc_vector_calc_cap_bits {
803 u8 calc_matrix[0x1];
804 u8 reserved_at_1[0x1f];
805 u8 reserved_at_20[0x8];
806 u8 max_vec_count[0x8];
807 u8 reserved_at_30[0xd];
808 u8 max_chunk_size[0x3];
809 struct mlx5_ifc_calc_op calc0;
810 struct mlx5_ifc_calc_op calc1;
811 struct mlx5_ifc_calc_op calc2;
812 struct mlx5_ifc_calc_op calc3;
813
814 u8 reserved_at_e0[0x720];
815};
816
e281682b
SM		 817enum {
818 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
819 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 820 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 821 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 822};
823
824enum {
825 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
826 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
827};
828
829enum {
830 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
831 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
832 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
833 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
834 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
835};
836
837enum {
838 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
839 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
840 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
841 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
842 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
843 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
844};
845
846enum {
847 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
848 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
849};
850
851enum {
852 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
853 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
854 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
855};
856
857enum {
858 MLX5_CAP_PORT_TYPE_IB = 0x0,
859 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 860};
861
1410a90a
MG		 862enum {
863 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
864 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
865 MLX5_CAP_UMR_FENCE_NONE = 0x2,
866};
867
b775516b 868struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 869 u8 reserved_at_0[0x30];
870 u8 vhca_id[0x10];
871
872 u8 reserved_at_40[0x40];
b775516b
EC		 873
874 u8 log_max_srq_sz[0x8];
875 u8 log_max_qp_sz[0x8];
b4ff3a36 876 u8 reserved_at_90[0xb];
b775516b
EC		 877 u8 log_max_qp[0x5];
878
b4ff3a36 879 u8 reserved_at_a0[0xb];
e281682b 880 u8 log_max_srq[0x5];
b4ff3a36 881 u8 reserved_at_b0[0x10];
b775516b 882
b4ff3a36 883 u8 reserved_at_c0[0x8];
b775516b 884 u8 log_max_cq_sz[0x8];
b4ff3a36 885 u8 reserved_at_d0[0xb];
b775516b
EC		 886 u8 log_max_cq[0x5];
887
888 u8 log_max_eq_sz[0x8];
b4ff3a36 889 u8 reserved_at_e8[0x2];
b775516b 890 u8 log_max_mkey[0x6];
b183ee27
LR		 891 u8 reserved_at_f0[0x8];
892 u8 dump_fill_mkey[0x1];
893 u8 reserved_at_f9[0x3];
b775516b
EC		 894 u8 log_max_eq[0x4];
895
896 u8 max_indirection[0x8];
bcda1aca 897 u8 fixed_buffer_size[0x1];
b775516b 898 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 899 u8 force_teardown[0x1];
900 u8 reserved_at_111[0x1];
b775516b 901 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 902 u8 umr_extended_translation_offset[0x1];
903 u8 null_mkey[0x1];
b775516b
EC		 904 u8 log_max_klm_list_size[0x6];
905
b4ff3a36 906 u8 reserved_at_120[0xa];
b775516b 907 u8 log_max_ra_req_dc[0x6];
b4ff3a36 908 u8 reserved_at_130[0xa];
b775516b
EC		 909 u8 log_max_ra_res_dc[0x6];
910
b4ff3a36 911 u8 reserved_at_140[0xa];
b775516b 912 u8 log_max_ra_req_qp[0x6];
b4ff3a36 913 u8 reserved_at_150[0xa];
b775516b
EC		 914 u8 log_max_ra_res_qp[0x6];
915
f32f5bd2 916 u8 end_pad[0x1];
b775516b
EC		 917 u8 cc_query_allowed[0x1];
918 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 919 u8 start_pad[0x1];
920 u8 cache_line_128byte[0x1];
c02762eb
HN		 921 u8 reserved_at_165[0xa];
922 u8 qcam_reg[0x1];
e281682b 923 u8 gid_table_size[0x10];
b775516b 924
e281682b
SM		 925 u8 out_of_seq_cnt[0x1];
926 u8 vport_counters[0x1];
7486216b 927 u8 retransmission_q_counters[0x1];
2fcb12df 928 u8 debug[0x1];
83b502a1 929 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 930 u8 rq_delay_drop[0x1];
b775516b
EC		 931 u8 max_qp_cnt[0xa];
932 u8 pkey_table_size[0x10];
933
e281682b
SM		 934 u8 vport_group_manager[0x1];
935 u8 vhca_group_manager[0x1];
936 u8 ib_virt[0x1];
937 u8 eth_virt[0x1];
61c5b5c9 938 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 939 u8 ets[0x1];
940 u8 nic_flow_table[0x1];
0efc8562 941 u8 eswitch_manager[0x1];
e72bd817 942 u8 device_memory[0x1];
cfdcbcea
GP		 943 u8 mcam_reg[0x1];
944 u8 pcam_reg[0x1];
b775516b 945 u8 local_ca_ack_delay[0x5];
4ce3bf2f 946 u8 port_module_event[0x1];
58dcb60a 947 u8 enhanced_error_q_counters[0x1];
7d5e1423 948 u8 ports_check[0x1];
7b13558f 949 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 950 u8 disable_link_up[0x1];
951 u8 beacon_led[0x1];
e281682b 952 u8 port_type[0x2];
b775516b
EC		 953 u8 num_ports[0x8];
954
f9a1ef72
EE		 955 u8 reserved_at_1c0[0x1];
956 u8 pps[0x1];
957 u8 pps_modify[0x1];
b775516b 958 u8 log_max_msg[0x5];
e1c9c62b 959 u8 reserved_at_1c8[0x4];
4f3961ee 960 u8 max_tc[0x4];
1865ea9a 961 u8 temp_warn_event[0x1];
7486216b 962 u8 dcbx[0x1];
246ac981
MG		 963 u8 general_notification_event[0x1];
964 u8 reserved_at_1d3[0x2];
e29341fb 965 u8 fpga[0x1];
928cfe87
TT		 966 u8 rol_s[0x1];
967 u8 rol_g[0x1];
e1c9c62b 968 u8 reserved_at_1d8[0x1];
928cfe87
TT		 969 u8 wol_s[0x1];
970 u8 wol_g[0x1];
971 u8 wol_a[0x1];
972 u8 wol_b[0x1];
973 u8 wol_m[0x1];
974 u8 wol_u[0x1];
975 u8 wol_p[0x1];
b775516b
EC		 976
977 u8 stat_rate_support[0x10];
e1c9c62b 978 u8 reserved_at_1f0[0xc];
e281682b 979 u8 cqe_version[0x4];
b775516b 980
e281682b 981 u8 compact_address_vector[0x1];
7d5e1423 982 u8 striding_rq[0x1];
500a3d0d
ES		 983 u8 reserved_at_202[0x1];
984 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 985 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 986 u8 reserved_at_205[0x1];
987 u8 repeated_block_disabled[0x1];
988 u8 umr_modify_entity_size_disabled[0x1];
989 u8 umr_modify_atomic_disabled[0x1];
990 u8 umr_indirect_mkey_disabled[0x1];
1410a90a
MG		 991 u8 umr_fence[0x2];
992 u8 reserved_at_20c[0x3];
e281682b 993 u8 drain_sigerr[0x1];
b775516b
EC		 994 u8 cmdif_checksum[0x2];
995 u8 sigerr_cqe[0x1];
e1c9c62b 996 u8 reserved_at_213[0x1];
b775516b
EC		 997 u8 wq_signature[0x1];
998 u8 sctr_data_cqe[0x1];
e1c9c62b 999 u8 reserved_at_216[0x1];
b775516b
EC		 1000 u8 sho[0x1];
1001 u8 tph[0x1];
1002 u8 rf[0x1];
e281682b 1003 u8 dct[0x1];
7486216b 1004 u8 qos[0x1];
e281682b 1005 u8 eth_net_offloads[0x1];
b775516b
EC		 1006 u8 roce[0x1];
1007 u8 atomic[0x1];
e1c9c62b 1008 u8 reserved_at_21f[0x1];
b775516b
EC		 1009
1010 u8 cq_oi[0x1];
1011 u8 cq_resize[0x1];
1012 u8 cq_moderation[0x1];
e1c9c62b 1013 u8 reserved_at_223[0x3];
e281682b 1014 u8 cq_eq_remap[0x1];
b775516b
EC		 1015 u8 pg[0x1];
1016 u8 block_lb_mc[0x1];
e1c9c62b 1017 u8 reserved_at_229[0x1];
e281682b 1018 u8 scqe_break_moderation[0x1];
7d5e1423 1019 u8 cq_period_start_from_cqe[0x1];
b775516b 1020 u8 cd[0x1];
e1c9c62b 1021 u8 reserved_at_22d[0x1];
b775516b 1022 u8 apm[0x1];
3f0393a5 1023 u8 vector_calc[0x1];
7d5e1423 1024 u8 umr_ptr_rlky[0x1];
d2370e0a 1025 u8 imaicl[0x1];
e1c9c62b 1026 u8 reserved_at_232[0x4];
b775516b
EC		 1027 u8 qkv[0x1];
1028 u8 pkv[0x1];
b11a4f9c
HE		 1029 u8 set_deth_sqpn[0x1];
1030 u8 reserved_at_239[0x3];
b775516b
EC		 1031 u8 xrc[0x1];
1032 u8 ud[0x1];
1033 u8 uc[0x1];
1034 u8 rc[0x1];
1035
a6d51b68
EC		 1036 u8 uar_4k[0x1];
1037 u8 reserved_at_241[0x9];
b775516b 1038 u8 uar_sz[0x6];
e1c9c62b 1039 u8 reserved_at_250[0x8];
b775516b
EC		 1040 u8 log_pg_sz[0x8];
1041
1042 u8 bf[0x1];
0dbc6fe0 1043 u8 driver_version[0x1];
e281682b 1044 u8 pad_tx_eth_packet[0x1];
e1c9c62b 1045 u8 reserved_at_263[0x8];
b775516b 1046 u8 log_bf_reg_size[0x5];
84df61eb
AH		 1047
1048 u8 reserved_at_270[0xb];
1049 u8 lag_master[0x1];
1050 u8 num_lag_ports[0x4];
b775516b 1051
e1c9c62b 1052 u8 reserved_at_280[0x10];
b775516b
EC		 1053 u8 max_wqe_sz_sq[0x10];
1054
e1c9c62b 1055 u8 reserved_at_2a0[0x10];
b775516b
EC		 1056 u8 max_wqe_sz_rq[0x10];
1057
a8ffcc74 1058 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1059 u8 max_wqe_sz_sq_dc[0x10];
1060
e1c9c62b 1061 u8 reserved_at_2e0[0x7];
b775516b
EC		 1062 u8 max_qp_mcg[0x19];
1063
e1c9c62b 1064 u8 reserved_at_300[0x18];
b775516b
EC		 1065 u8 log_max_mcg[0x8];
1066
e1c9c62b 1067 u8 reserved_at_320[0x3];
e281682b 1068 u8 log_max_transport_domain[0x5];
e1c9c62b 1069 u8 reserved_at_328[0x3];
b775516b 1070 u8 log_max_pd[0x5];
e1c9c62b 1071 u8 reserved_at_330[0xb];
b775516b
EC		 1072 u8 log_max_xrcd[0x5];
1073
5c298143 1074 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1075 u8 receive_discard_vport_down[0x1];
1076 u8 transmit_discard_vport_down[0x1];
1077 u8 reserved_at_343[0x5];
a351a1b0 1078 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1079 u8 max_flow_counter_15_0[0x10];
a351a1b0 1080
b775516b 1081
e1c9c62b 1082 u8 reserved_at_360[0x3];
b775516b 1083 u8 log_max_rq[0x5];
e1c9c62b 1084 u8 reserved_at_368[0x3];
b775516b 1085 u8 log_max_sq[0x5];
e1c9c62b 1086 u8 reserved_at_370[0x3];
b775516b 1087 u8 log_max_tir[0x5];
e1c9c62b 1088 u8 reserved_at_378[0x3];
b775516b
EC		 1089 u8 log_max_tis[0x5];
1090
e281682b 1091 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1092 u8 reserved_at_381[0x2];
e281682b 1093 u8 log_max_rmp[0x5];
e1c9c62b 1094 u8 reserved_at_388[0x3];
e281682b 1095 u8 log_max_rqt[0x5];
e1c9c62b 1096 u8 reserved_at_390[0x3];
e281682b 1097 u8 log_max_rqt_size[0x5];
e1c9c62b 1098 u8 reserved_at_398[0x3];
b775516b
EC		 1099 u8 log_max_tis_per_sq[0x5];
1100
619a8f2a
TT		 1101 u8 ext_stride_num_range[0x1];
1102 u8 reserved_at_3a1[0x2];
e281682b 1103 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1104 u8 reserved_at_3a8[0x3];
e281682b 1105 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1106 u8 reserved_at_3b0[0x3];
e281682b 1107 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1108 u8 reserved_at_3b8[0x3];
e281682b
SM		 1109 u8 log_min_stride_sz_sq[0x5];
1110
40817cdb
OG		 1111 u8 hairpin[0x1];
1112 u8 reserved_at_3c1[0x2];
1113 u8 log_max_hairpin_queues[0x5];
1114 u8 reserved_at_3c8[0x3];
1115 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1116 u8 reserved_at_3d0[0x3];
1117 u8 log_max_hairpin_num_packets[0x5];
1118 u8 reserved_at_3d8[0x3];
e281682b
SM		 1119 u8 log_max_wq_sz[0x5];
1120
54f0a411 1121 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1122 u8 disable_local_lb_uc[0x1];
1123 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1124 u8 log_min_hairpin_wq_data_sz[0x5];
1125 u8 reserved_at_3e8[0x3];
54f0a411 1126 u8 log_max_vlan_list[0x5];
e1c9c62b 1127 u8 reserved_at_3f0[0x3];
54f0a411 1128 u8 log_max_current_mc_list[0x5];
e1c9c62b 1129 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1130 u8 log_max_current_uc_list[0x5];
1131
38b7ca92
YH		 1132 u8 general_obj_types[0x40];
1133
1134 u8 reserved_at_440[0x40];
54f0a411 1135
e1c9c62b 1136 u8 reserved_at_480[0x3];
e281682b 1137 u8 log_max_l2_table[0x5];
e1c9c62b 1138 u8 reserved_at_488[0x8];
b775516b
EC		 1139 u8 log_uar_page_sz[0x10];
1140
e1c9c62b 1141 u8 reserved_at_4a0[0x20];
048ccca8 1142 u8 device_frequency_mhz[0x20];
b0844444 1143 u8 device_frequency_khz[0x20];
e1c9c62b 1144
a6d51b68
EC		 1145 u8 reserved_at_500[0x20];
1146 u8 num_of_uars_per_page[0x20];
e1c9c62b 1147
e818e255
AL		 1148 u8 flex_parser_protocols[0x20];
1149 u8 reserved_at_560[0x20];
e1c9c62b 1150
ab741b2e
YC		 1151 u8 reserved_at_580[0x3c];
1152 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1153 u8 cqe_128_always[0x1];
1154 u8 cqe_compression_128[0x1];
7d5e1423 1155 u8 cqe_compression[0x1];
b775516b 1156
7d5e1423
SM		 1157 u8 cqe_compression_timeout[0x10];
1158 u8 cqe_compression_max_num[0x10];
b775516b 1159
7486216b
SM		 1160 u8 reserved_at_5e0[0x10];
1161 u8 tag_matching[0x1];
1162 u8 rndv_offload_rc[0x1];
1163 u8 rndv_offload_dc[0x1];
1164 u8 log_tag_matching_list_sz[0x5];
7b13558f 1165 u8 reserved_at_5f8[0x3];
7486216b
SM		 1166 u8 log_max_xrq[0x5];
1167
32f69e4b
DJ		 1168 u8 affiliate_nic_vport_criteria[0x8];
1169 u8 native_port_num[0x8];
1170 u8 num_vhca_ports[0x8];
1171 u8 reserved_at_618[0x6];
1172 u8 sw_owner_id[0x1];
8737f818 1173 u8 reserved_at_61f[0x1e1];
b775516b
EC		 1174};
1175
81848731
SM		 1176enum mlx5_flow_destination_type {
1177 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1178 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1179 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1180
5f418378 1181 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1182 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1183};
b775516b 1184
e281682b
SM		 1185struct mlx5_ifc_dest_format_struct_bits {
1186 u8 destination_type[0x8];
1187 u8 destination_id[0x18];
b17f7fc1
SK		 1188 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1189 u8 reserved_at_21[0xf];
1190 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1191};
1192
9dc0b289 1193struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1194 u8 flow_counter_id[0x20];
9dc0b289
AV		 1195
1196 u8 reserved_at_20[0x20];
1197};
1198
1199union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1200 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1201 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1202 u8 reserved_at_0[0x40];
1203};
1204
e281682b
SM		 1205struct mlx5_ifc_fte_match_param_bits {
1206 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1207
1208 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1209
1210 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1211
71c6e863
AL		 1212 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1213
1214 u8 reserved_at_800[0x800];
b775516b
EC		 1215};
1216
e281682b
SM		 1217enum {
1218 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1219 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1220 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1221 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1222 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1223};
b775516b 1224
e281682b
SM		 1225struct mlx5_ifc_rx_hash_field_select_bits {
1226 u8 l3_prot_type[0x1];
1227 u8 l4_prot_type[0x1];
1228 u8 selected_fields[0x1e];
1229};
b775516b 1230
e281682b
SM		 1231enum {
1232 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1233 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1234};
1235
e281682b
SM		 1236enum {
1237 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1238 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1239};
1240
1241struct mlx5_ifc_wq_bits {
1242 u8 wq_type[0x4];
1243 u8 wq_signature[0x1];
1244 u8 end_padding_mode[0x2];
1245 u8 cd_slave[0x1];
b4ff3a36 1246 u8 reserved_at_8[0x18];
b775516b 1247
e281682b
SM		 1248 u8 hds_skip_first_sge[0x1];
1249 u8 log2_hds_buf_size[0x3];
b4ff3a36 1250 u8 reserved_at_24[0x7];
e281682b
SM		 1251 u8 page_offset[0x5];
1252 u8 lwm[0x10];
b775516b 1253
b4ff3a36 1254 u8 reserved_at_40[0x8];
e281682b
SM		 1255 u8 pd[0x18];
1256
b4ff3a36 1257 u8 reserved_at_60[0x8];
e281682b
SM		 1258 u8 uar_page[0x18];
1259
1260 u8 dbr_addr[0x40];
1261
1262 u8 hw_counter[0x20];
1263
1264 u8 sw_counter[0x20];
1265
b4ff3a36 1266 u8 reserved_at_100[0xc];
e281682b 1267 u8 log_wq_stride[0x4];
b4ff3a36 1268 u8 reserved_at_110[0x3];
e281682b 1269 u8 log_wq_pg_sz[0x5];
b4ff3a36 1270 u8 reserved_at_118[0x3];
e281682b
SM		 1271 u8 log_wq_sz[0x5];
1272
4d533e0f
OG		 1273 u8 reserved_at_120[0x3];
1274 u8 log_hairpin_num_packets[0x5];
1275 u8 reserved_at_128[0x3];
40817cdb 1276 u8 log_hairpin_data_sz[0x5];
40817cdb 1277
619a8f2a
TT		 1278 u8 reserved_at_130[0x4];
1279 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1280 u8 two_byte_shift_en[0x1];
1281 u8 reserved_at_139[0x4];
1282 u8 log_wqe_stride_size[0x3];
1283
1284 u8 reserved_at_140[0x4c0];
b775516b 1285
e281682b 1286 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1287};
1288
e281682b 1289struct mlx5_ifc_rq_num_bits {
b4ff3a36 1290 u8 reserved_at_0[0x8];
e281682b
SM		 1291 u8 rq_num[0x18];
1292};
b775516b 1293
e281682b 1294struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1295 u8 reserved_at_0[0x10];
e281682b 1296 u8 mac_addr_47_32[0x10];
b775516b 1297
e281682b
SM		 1298 u8 mac_addr_31_0[0x20];
1299};
1300
c0046cf7 1301struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1302 u8 reserved_at_0[0x14];
c0046cf7
SM		 1303 u8 vlan[0x0c];
1304
b4ff3a36 1305 u8 reserved_at_20[0x20];
c0046cf7
SM		 1306};
1307
e281682b 1308struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1309 u8 reserved_at_0[0xa0];
e281682b
SM		 1310
1311 u8 min_time_between_cnps[0x20];
1312
b4ff3a36 1313 u8 reserved_at_c0[0x12];
e281682b 1314 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1315 u8 reserved_at_d8[0x4];
1316 u8 cnp_prio_mode[0x1];
e281682b
SM		 1317 u8 cnp_802p_prio[0x3];
1318
b4ff3a36 1319 u8 reserved_at_e0[0x720];
e281682b
SM		 1320};
1321
1322struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1323 u8 reserved_at_0[0x60];
e281682b 1324
b4ff3a36 1325 u8 reserved_at_60[0x4];
e281682b 1326 u8 clamp_tgt_rate[0x1];
b4ff3a36 1327 u8 reserved_at_65[0x3];
e281682b 1328 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1329 u8 reserved_at_69[0x17];
e281682b 1330
b4ff3a36 1331 u8 reserved_at_80[0x20];
e281682b
SM		 1332
1333 u8 rpg_time_reset[0x20];
1334
1335 u8 rpg_byte_reset[0x20];
1336
1337 u8 rpg_threshold[0x20];
1338
1339 u8 rpg_max_rate[0x20];
1340
1341 u8 rpg_ai_rate[0x20];
1342
1343 u8 rpg_hai_rate[0x20];
1344
1345 u8 rpg_gd[0x20];
1346
1347 u8 rpg_min_dec_fac[0x20];
1348
1349 u8 rpg_min_rate[0x20];
1350
b4ff3a36 1351 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1352
1353 u8 rate_to_set_on_first_cnp[0x20];
1354
1355 u8 dce_tcp_g[0x20];
1356
1357 u8 dce_tcp_rtt[0x20];
1358
1359 u8 rate_reduce_monitor_period[0x20];
1360
b4ff3a36 1361 u8 reserved_at_320[0x20];
e281682b
SM		 1362
1363 u8 initial_alpha_value[0x20];
1364
b4ff3a36 1365 u8 reserved_at_360[0x4a0];
e281682b
SM		 1366};
1367
1368struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1369 u8 reserved_at_0[0x80];
e281682b
SM		 1370
1371 u8 rppp_max_rps[0x20];
1372
1373 u8 rpg_time_reset[0x20];
1374
1375 u8 rpg_byte_reset[0x20];
1376
1377 u8 rpg_threshold[0x20];
1378
1379 u8 rpg_max_rate[0x20];
1380
1381 u8 rpg_ai_rate[0x20];
1382
1383 u8 rpg_hai_rate[0x20];
1384
1385 u8 rpg_gd[0x20];
1386
1387 u8 rpg_min_dec_fac[0x20];
1388
1389 u8 rpg_min_rate[0x20];
1390
b4ff3a36 1391 u8 reserved_at_1c0[0x640];
e281682b
SM		 1392};
1393
1394enum {
1395 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1396 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1397 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1398};
1399
1400struct mlx5_ifc_resize_field_select_bits {
1401 u8 resize_field_select[0x20];
1402};
1403
1404enum {
1405 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1406 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1407 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1408 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1409};
1410
1411struct mlx5_ifc_modify_field_select_bits {
1412 u8 modify_field_select[0x20];
1413};
1414
1415struct mlx5_ifc_field_select_r_roce_np_bits {
1416 u8 field_select_r_roce_np[0x20];
1417};
1418
1419struct mlx5_ifc_field_select_r_roce_rp_bits {
1420 u8 field_select_r_roce_rp[0x20];
1421};
1422
1423enum {
1424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1425 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1426 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1427 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1428 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1429 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1430 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1431 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1432 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1433 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1434};
1435
1436struct mlx5_ifc_field_select_802_1qau_rp_bits {
1437 u8 field_select_8021qaurp[0x20];
1438};
1439
1440struct mlx5_ifc_phys_layer_cntrs_bits {
1441 u8 time_since_last_clear_high[0x20];
1442
1443 u8 time_since_last_clear_low[0x20];
1444
1445 u8 symbol_errors_high[0x20];
1446
1447 u8 symbol_errors_low[0x20];
1448
1449 u8 sync_headers_errors_high[0x20];
1450
1451 u8 sync_headers_errors_low[0x20];
1452
1453 u8 edpl_bip_errors_lane0_high[0x20];
1454
1455 u8 edpl_bip_errors_lane0_low[0x20];
1456
1457 u8 edpl_bip_errors_lane1_high[0x20];
1458
1459 u8 edpl_bip_errors_lane1_low[0x20];
1460
1461 u8 edpl_bip_errors_lane2_high[0x20];
1462
1463 u8 edpl_bip_errors_lane2_low[0x20];
1464
1465 u8 edpl_bip_errors_lane3_high[0x20];
1466
1467 u8 edpl_bip_errors_lane3_low[0x20];
1468
1469 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1470
1471 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1472
1473 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1474
1475 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1476
1477 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1478
1479 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1480
1481 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1482
1483 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1484
1485 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1486
1487 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1488
1489 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1490
1491 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1492
1493 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1494
1495 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1496
1497 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1498
1499 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1500
1501 u8 rs_fec_corrected_blocks_high[0x20];
1502
1503 u8 rs_fec_corrected_blocks_low[0x20];
1504
1505 u8 rs_fec_uncorrectable_blocks_high[0x20];
1506
1507 u8 rs_fec_uncorrectable_blocks_low[0x20];
1508
1509 u8 rs_fec_no_errors_blocks_high[0x20];
1510
1511 u8 rs_fec_no_errors_blocks_low[0x20];
1512
1513 u8 rs_fec_single_error_blocks_high[0x20];
1514
1515 u8 rs_fec_single_error_blocks_low[0x20];
1516
1517 u8 rs_fec_corrected_symbols_total_high[0x20];
1518
1519 u8 rs_fec_corrected_symbols_total_low[0x20];
1520
1521 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1522
1523 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1524
1525 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1526
1527 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1528
1529 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1530
1531 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1532
1533 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1534
1535 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1536
1537 u8 link_down_events[0x20];
1538
1539 u8 successful_recovery_events[0x20];
1540
b4ff3a36 1541 u8 reserved_at_640[0x180];
e281682b
SM		 1542};
1543
d8dc0508
GP		 1544struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1545 u8 time_since_last_clear_high[0x20];
1546
1547 u8 time_since_last_clear_low[0x20];
1548
1549 u8 phy_received_bits_high[0x20];
1550
1551 u8 phy_received_bits_low[0x20];
1552
1553 u8 phy_symbol_errors_high[0x20];
1554
1555 u8 phy_symbol_errors_low[0x20];
1556
1557 u8 phy_corrected_bits_high[0x20];
1558
1559 u8 phy_corrected_bits_low[0x20];
1560
1561 u8 phy_corrected_bits_lane0_high[0x20];
1562
1563 u8 phy_corrected_bits_lane0_low[0x20];
1564
1565 u8 phy_corrected_bits_lane1_high[0x20];
1566
1567 u8 phy_corrected_bits_lane1_low[0x20];
1568
1569 u8 phy_corrected_bits_lane2_high[0x20];
1570
1571 u8 phy_corrected_bits_lane2_low[0x20];
1572
1573 u8 phy_corrected_bits_lane3_high[0x20];
1574
1575 u8 phy_corrected_bits_lane3_low[0x20];
1576
1577 u8 reserved_at_200[0x5c0];
1578};
1579
1c64bf6f
MY		 1580struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1581 u8 symbol_error_counter[0x10];
1582
1583 u8 link_error_recovery_counter[0x8];
1584
1585 u8 link_downed_counter[0x8];
1586
1587 u8 port_rcv_errors[0x10];
1588
1589 u8 port_rcv_remote_physical_errors[0x10];
1590
1591 u8 port_rcv_switch_relay_errors[0x10];
1592
1593 u8 port_xmit_discards[0x10];
1594
1595 u8 port_xmit_constraint_errors[0x8];
1596
1597 u8 port_rcv_constraint_errors[0x8];
1598
1599 u8 reserved_at_70[0x8];
1600
1601 u8 link_overrun_errors[0x8];
1602
1603 u8 reserved_at_80[0x10];
1604
1605 u8 vl_15_dropped[0x10];
1606
133bea04
TW		 1607 u8 reserved_at_a0[0x80];
1608
1609 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1610};
1611
e281682b
SM		 1612struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1613 u8 transmit_queue_high[0x20];
1614
1615 u8 transmit_queue_low[0x20];
1616
b4ff3a36 1617 u8 reserved_at_40[0x780];
e281682b
SM		 1618};
1619
1620struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1621 u8 rx_octets_high[0x20];
1622
1623 u8 rx_octets_low[0x20];
1624
b4ff3a36 1625 u8 reserved_at_40[0xc0];
e281682b
SM		 1626
1627 u8 rx_frames_high[0x20];
1628
1629 u8 rx_frames_low[0x20];
1630
1631 u8 tx_octets_high[0x20];
1632
1633 u8 tx_octets_low[0x20];
1634
b4ff3a36 1635 u8 reserved_at_180[0xc0];
e281682b
SM		 1636
1637 u8 tx_frames_high[0x20];
1638
1639 u8 tx_frames_low[0x20];
1640
1641 u8 rx_pause_high[0x20];
1642
1643 u8 rx_pause_low[0x20];
1644
1645 u8 rx_pause_duration_high[0x20];
1646
1647 u8 rx_pause_duration_low[0x20];
1648
1649 u8 tx_pause_high[0x20];
1650
1651 u8 tx_pause_low[0x20];
1652
1653 u8 tx_pause_duration_high[0x20];
1654
1655 u8 tx_pause_duration_low[0x20];
1656
1657 u8 rx_pause_transition_high[0x20];
1658
1659 u8 rx_pause_transition_low[0x20];
1660
2fcb12df
IK		 1661 u8 reserved_at_3c0[0x40];
1662
1663 u8 device_stall_minor_watermark_cnt_high[0x20];
1664
1665 u8 device_stall_minor_watermark_cnt_low[0x20];
1666
1667 u8 device_stall_critical_watermark_cnt_high[0x20];
1668
1669 u8 device_stall_critical_watermark_cnt_low[0x20];
1670
1671 u8 reserved_at_480[0x340];
e281682b
SM		 1672};
1673
1674struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1675 u8 port_transmit_wait_high[0x20];
1676
1677 u8 port_transmit_wait_low[0x20];
1678
2dba0797
GP		 1679 u8 reserved_at_40[0x100];
1680
1681 u8 rx_buffer_almost_full_high[0x20];
1682
1683 u8 rx_buffer_almost_full_low[0x20];
1684
1685 u8 rx_buffer_full_high[0x20];
1686
1687 u8 rx_buffer_full_low[0x20];
1688
0af5107c
TB		 1689 u8 rx_icrc_encapsulated_high[0x20];
1690
1691 u8 rx_icrc_encapsulated_low[0x20];
1692
1693 u8 reserved_at_200[0x5c0];
e281682b
SM		 1694};
1695
1696struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1697 u8 dot3stats_alignment_errors_high[0x20];
1698
1699 u8 dot3stats_alignment_errors_low[0x20];
1700
1701 u8 dot3stats_fcs_errors_high[0x20];
1702
1703 u8 dot3stats_fcs_errors_low[0x20];
1704
1705 u8 dot3stats_single_collision_frames_high[0x20];
1706
1707 u8 dot3stats_single_collision_frames_low[0x20];
1708
1709 u8 dot3stats_multiple_collision_frames_high[0x20];
1710
1711 u8 dot3stats_multiple_collision_frames_low[0x20];
1712
1713 u8 dot3stats_sqe_test_errors_high[0x20];
1714
1715 u8 dot3stats_sqe_test_errors_low[0x20];
1716
1717 u8 dot3stats_deferred_transmissions_high[0x20];
1718
1719 u8 dot3stats_deferred_transmissions_low[0x20];
1720
1721 u8 dot3stats_late_collisions_high[0x20];
1722
1723 u8 dot3stats_late_collisions_low[0x20];
1724
1725 u8 dot3stats_excessive_collisions_high[0x20];
1726
1727 u8 dot3stats_excessive_collisions_low[0x20];
1728
1729 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1730
1731 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1732
1733 u8 dot3stats_carrier_sense_errors_high[0x20];
1734
1735 u8 dot3stats_carrier_sense_errors_low[0x20];
1736
1737 u8 dot3stats_frame_too_longs_high[0x20];
1738
1739 u8 dot3stats_frame_too_longs_low[0x20];
1740
1741 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1742
1743 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1744
1745 u8 dot3stats_symbol_errors_high[0x20];
1746
1747 u8 dot3stats_symbol_errors_low[0x20];
1748
1749 u8 dot3control_in_unknown_opcodes_high[0x20];
1750
1751 u8 dot3control_in_unknown_opcodes_low[0x20];
1752
1753 u8 dot3in_pause_frames_high[0x20];
1754
1755 u8 dot3in_pause_frames_low[0x20];
1756
1757 u8 dot3out_pause_frames_high[0x20];
1758
1759 u8 dot3out_pause_frames_low[0x20];
1760
b4ff3a36 1761 u8 reserved_at_400[0x3c0];
e281682b
SM		 1762};
1763
1764struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1765 u8 ether_stats_drop_events_high[0x20];
1766
1767 u8 ether_stats_drop_events_low[0x20];
1768
1769 u8 ether_stats_octets_high[0x20];
1770
1771 u8 ether_stats_octets_low[0x20];
1772
1773 u8 ether_stats_pkts_high[0x20];
1774
1775 u8 ether_stats_pkts_low[0x20];
1776
1777 u8 ether_stats_broadcast_pkts_high[0x20];
1778
1779 u8 ether_stats_broadcast_pkts_low[0x20];
1780
1781 u8 ether_stats_multicast_pkts_high[0x20];
1782
1783 u8 ether_stats_multicast_pkts_low[0x20];
1784
1785 u8 ether_stats_crc_align_errors_high[0x20];
1786
1787 u8 ether_stats_crc_align_errors_low[0x20];
1788
1789 u8 ether_stats_undersize_pkts_high[0x20];
1790
1791 u8 ether_stats_undersize_pkts_low[0x20];
1792
1793 u8 ether_stats_oversize_pkts_high[0x20];
1794
1795 u8 ether_stats_oversize_pkts_low[0x20];
1796
1797 u8 ether_stats_fragments_high[0x20];
1798
1799 u8 ether_stats_fragments_low[0x20];
1800
1801 u8 ether_stats_jabbers_high[0x20];
1802
1803 u8 ether_stats_jabbers_low[0x20];
1804
1805 u8 ether_stats_collisions_high[0x20];
1806
1807 u8 ether_stats_collisions_low[0x20];
1808
1809 u8 ether_stats_pkts64octets_high[0x20];
1810
1811 u8 ether_stats_pkts64octets_low[0x20];
1812
1813 u8 ether_stats_pkts65to127octets_high[0x20];
1814
1815 u8 ether_stats_pkts65to127octets_low[0x20];
1816
1817 u8 ether_stats_pkts128to255octets_high[0x20];
1818
1819 u8 ether_stats_pkts128to255octets_low[0x20];
1820
1821 u8 ether_stats_pkts256to511octets_high[0x20];
1822
1823 u8 ether_stats_pkts256to511octets_low[0x20];
1824
1825 u8 ether_stats_pkts512to1023octets_high[0x20];
1826
1827 u8 ether_stats_pkts512to1023octets_low[0x20];
1828
1829 u8 ether_stats_pkts1024to1518octets_high[0x20];
1830
1831 u8 ether_stats_pkts1024to1518octets_low[0x20];
1832
1833 u8 ether_stats_pkts1519to2047octets_high[0x20];
1834
1835 u8 ether_stats_pkts1519to2047octets_low[0x20];
1836
1837 u8 ether_stats_pkts2048to4095octets_high[0x20];
1838
1839 u8 ether_stats_pkts2048to4095octets_low[0x20];
1840
1841 u8 ether_stats_pkts4096to8191octets_high[0x20];
1842
1843 u8 ether_stats_pkts4096to8191octets_low[0x20];
1844
1845 u8 ether_stats_pkts8192to10239octets_high[0x20];
1846
1847 u8 ether_stats_pkts8192to10239octets_low[0x20];
1848
b4ff3a36 1849 u8 reserved_at_540[0x280];
e281682b
SM		 1850};
1851
1852struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1853 u8 if_in_octets_high[0x20];
1854
1855 u8 if_in_octets_low[0x20];
1856
1857 u8 if_in_ucast_pkts_high[0x20];
1858
1859 u8 if_in_ucast_pkts_low[0x20];
1860
1861 u8 if_in_discards_high[0x20];
1862
1863 u8 if_in_discards_low[0x20];
1864
1865 u8 if_in_errors_high[0x20];
1866
1867 u8 if_in_errors_low[0x20];
1868
1869 u8 if_in_unknown_protos_high[0x20];
1870
1871 u8 if_in_unknown_protos_low[0x20];
1872
1873 u8 if_out_octets_high[0x20];
1874
1875 u8 if_out_octets_low[0x20];
1876
1877 u8 if_out_ucast_pkts_high[0x20];
1878
1879 u8 if_out_ucast_pkts_low[0x20];
1880
1881 u8 if_out_discards_high[0x20];
1882
1883 u8 if_out_discards_low[0x20];
1884
1885 u8 if_out_errors_high[0x20];
1886
1887 u8 if_out_errors_low[0x20];
1888
1889 u8 if_in_multicast_pkts_high[0x20];
1890
1891 u8 if_in_multicast_pkts_low[0x20];
1892
1893 u8 if_in_broadcast_pkts_high[0x20];
1894
1895 u8 if_in_broadcast_pkts_low[0x20];
1896
1897 u8 if_out_multicast_pkts_high[0x20];
1898
1899 u8 if_out_multicast_pkts_low[0x20];
1900
1901 u8 if_out_broadcast_pkts_high[0x20];
1902
1903 u8 if_out_broadcast_pkts_low[0x20];
1904
b4ff3a36 1905 u8 reserved_at_340[0x480];
e281682b
SM		 1906};
1907
1908struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1909 u8 a_frames_transmitted_ok_high[0x20];
1910
1911 u8 a_frames_transmitted_ok_low[0x20];
1912
1913 u8 a_frames_received_ok_high[0x20];
1914
1915 u8 a_frames_received_ok_low[0x20];
1916
1917 u8 a_frame_check_sequence_errors_high[0x20];
1918
1919 u8 a_frame_check_sequence_errors_low[0x20];
1920
1921 u8 a_alignment_errors_high[0x20];
1922
1923 u8 a_alignment_errors_low[0x20];
1924
1925 u8 a_octets_transmitted_ok_high[0x20];
1926
1927 u8 a_octets_transmitted_ok_low[0x20];
1928
1929 u8 a_octets_received_ok_high[0x20];
1930
1931 u8 a_octets_received_ok_low[0x20];
1932
1933 u8 a_multicast_frames_xmitted_ok_high[0x20];
1934
1935 u8 a_multicast_frames_xmitted_ok_low[0x20];
1936
1937 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1938
1939 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1940
1941 u8 a_multicast_frames_received_ok_high[0x20];
1942
1943 u8 a_multicast_frames_received_ok_low[0x20];
1944
1945 u8 a_broadcast_frames_received_ok_high[0x20];
1946
1947 u8 a_broadcast_frames_received_ok_low[0x20];
1948
1949 u8 a_in_range_length_errors_high[0x20];
1950
1951 u8 a_in_range_length_errors_low[0x20];
1952
1953 u8 a_out_of_range_length_field_high[0x20];
1954
1955 u8 a_out_of_range_length_field_low[0x20];
1956
1957 u8 a_frame_too_long_errors_high[0x20];
1958
1959 u8 a_frame_too_long_errors_low[0x20];
1960
1961 u8 a_symbol_error_during_carrier_high[0x20];
1962
1963 u8 a_symbol_error_during_carrier_low[0x20];
1964
1965 u8 a_mac_control_frames_transmitted_high[0x20];
1966
1967 u8 a_mac_control_frames_transmitted_low[0x20];
1968
1969 u8 a_mac_control_frames_received_high[0x20];
1970
1971 u8 a_mac_control_frames_received_low[0x20];
1972
1973 u8 a_unsupported_opcodes_received_high[0x20];
1974
1975 u8 a_unsupported_opcodes_received_low[0x20];
1976
1977 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1978
1979 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1980
1981 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1982
1983 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1984
b4ff3a36 1985 u8 reserved_at_4c0[0x300];
e281682b
SM		 1986};
1987
8ed1a630
GP		 1988struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1989 u8 life_time_counter_high[0x20];
1990
1991 u8 life_time_counter_low[0x20];
1992
1993 u8 rx_errors[0x20];
1994
1995 u8 tx_errors[0x20];
1996
1997 u8 l0_to_recovery_eieos[0x20];
1998
1999 u8 l0_to_recovery_ts[0x20];
2000
2001 u8 l0_to_recovery_framing[0x20];
2002
2003 u8 l0_to_recovery_retrain[0x20];
2004
2005 u8 crc_error_dllp[0x20];
2006
2007 u8 crc_error_tlp[0x20];
2008
efae7f78
EBE		 2009 u8 tx_overflow_buffer_pkt_high[0x20];
2010
2011 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2012
2013 u8 outbound_stalled_reads[0x20];
2014
2015 u8 outbound_stalled_writes[0x20];
2016
2017 u8 outbound_stalled_reads_events[0x20];
2018
2019 u8 outbound_stalled_writes_events[0x20];
2020
2021 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2022};
2023
e281682b
SM		 2024struct mlx5_ifc_cmd_inter_comp_event_bits {
2025 u8 command_completion_vector[0x20];
2026
b4ff3a36 2027 u8 reserved_at_20[0xc0];
e281682b
SM		 2028};
2029
2030struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2031 u8 reserved_at_0[0x18];
e281682b 2032 u8 port_num[0x1];
b4ff3a36 2033 u8 reserved_at_19[0x3];
e281682b
SM		 2034 u8 vl[0x4];
2035
b4ff3a36 2036 u8 reserved_at_20[0xa0];
e281682b
SM		 2037};
2038
2039struct mlx5_ifc_db_bf_congestion_event_bits {
2040 u8 event_subtype[0x8];
b4ff3a36 2041 u8 reserved_at_8[0x8];
e281682b 2042 u8 congestion_level[0x8];
b4ff3a36 2043 u8 reserved_at_18[0x8];
e281682b 2044
b4ff3a36 2045 u8 reserved_at_20[0xa0];
e281682b
SM		 2046};
2047
2048struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2049 u8 reserved_at_0[0x60];
e281682b
SM		 2050
2051 u8 gpio_event_hi[0x20];
2052
2053 u8 gpio_event_lo[0x20];
2054
b4ff3a36 2055 u8 reserved_at_a0[0x40];
e281682b
SM		 2056};
2057
2058struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2059 u8 reserved_at_0[0x40];
e281682b
SM		 2060
2061 u8 port_num[0x4];
b4ff3a36 2062 u8 reserved_at_44[0x1c];
e281682b 2063
b4ff3a36 2064 u8 reserved_at_60[0x80];
e281682b
SM		 2065};
2066
2067struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2068 u8 reserved_at_0[0xe0];
e281682b
SM		 2069};
2070
2071enum {
2072 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2073 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2074};
2075
2076struct mlx5_ifc_cq_error_bits {
b4ff3a36 2077 u8 reserved_at_0[0x8];
e281682b
SM		 2078 u8 cqn[0x18];
2079
b4ff3a36 2080 u8 reserved_at_20[0x20];
e281682b 2081
b4ff3a36 2082 u8 reserved_at_40[0x18];
e281682b
SM		 2083 u8 syndrome[0x8];
2084
b4ff3a36 2085 u8 reserved_at_60[0x80];
e281682b
SM		 2086};
2087
2088struct mlx5_ifc_rdma_page_fault_event_bits {
2089 u8 bytes_committed[0x20];
2090
2091 u8 r_key[0x20];
2092
b4ff3a36 2093 u8 reserved_at_40[0x10];
e281682b
SM		 2094 u8 packet_len[0x10];
2095
2096 u8 rdma_op_len[0x20];
2097
2098 u8 rdma_va[0x40];
2099
b4ff3a36 2100 u8 reserved_at_c0[0x5];
e281682b
SM		 2101 u8 rdma[0x1];
2102 u8 write[0x1];
2103 u8 requestor[0x1];
2104 u8 qp_number[0x18];
2105};
2106
2107struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2108 u8 bytes_committed[0x20];
2109
b4ff3a36 2110 u8 reserved_at_20[0x10];
e281682b
SM		 2111 u8 wqe_index[0x10];
2112
b4ff3a36 2113 u8 reserved_at_40[0x10];
e281682b
SM		 2114 u8 len[0x10];
2115
b4ff3a36 2116 u8 reserved_at_60[0x60];
e281682b 2117
b4ff3a36 2118 u8 reserved_at_c0[0x5];
e281682b
SM		 2119 u8 rdma[0x1];
2120 u8 write_read[0x1];
2121 u8 requestor[0x1];
2122 u8 qpn[0x18];
2123};
2124
2125struct mlx5_ifc_qp_events_bits {
b4ff3a36 2126 u8 reserved_at_0[0xa0];
e281682b
SM		 2127
2128 u8 type[0x8];
b4ff3a36 2129 u8 reserved_at_a8[0x18];
e281682b 2130
b4ff3a36 2131 u8 reserved_at_c0[0x8];
e281682b
SM		 2132 u8 qpn_rqn_sqn[0x18];
2133};
2134
2135struct mlx5_ifc_dct_events_bits {
b4ff3a36 2136 u8 reserved_at_0[0xc0];
e281682b 2137
b4ff3a36 2138 u8 reserved_at_c0[0x8];
e281682b
SM		 2139 u8 dct_number[0x18];
2140};
2141
2142struct mlx5_ifc_comp_event_bits {
b4ff3a36 2143 u8 reserved_at_0[0xc0];
e281682b 2144
b4ff3a36 2145 u8 reserved_at_c0[0x8];
e281682b
SM		 2146 u8 cq_number[0x18];
2147};
2148
2149enum {
2150 MLX5_QPC_STATE_RST = 0x0,
2151 MLX5_QPC_STATE_INIT = 0x1,
2152 MLX5_QPC_STATE_RTR = 0x2,
2153 MLX5_QPC_STATE_RTS = 0x3,
2154 MLX5_QPC_STATE_SQER = 0x4,
2155 MLX5_QPC_STATE_ERR = 0x6,
2156 MLX5_QPC_STATE_SQD = 0x7,
2157 MLX5_QPC_STATE_SUSPENDED = 0x9,
2158};
2159
2160enum {
2161 MLX5_QPC_ST_RC = 0x0,
2162 MLX5_QPC_ST_UC = 0x1,
2163 MLX5_QPC_ST_UD = 0x2,
2164 MLX5_QPC_ST_XRC = 0x3,
2165 MLX5_QPC_ST_DCI = 0x5,
2166 MLX5_QPC_ST_QP0 = 0x7,
2167 MLX5_QPC_ST_QP1 = 0x8,
2168 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2169 MLX5_QPC_ST_REG_UMR = 0xc,
2170};
2171
2172enum {
2173 MLX5_QPC_PM_STATE_ARMED = 0x0,
2174 MLX5_QPC_PM_STATE_REARM = 0x1,
2175 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2176 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2177};
2178
6e44636a
AK		 2179enum {
2180 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2181};
2182
e281682b
SM		 2183enum {
2184 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2185 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2186};
2187
2188enum {
2189 MLX5_QPC_MTU_256_BYTES = 0x1,
2190 MLX5_QPC_MTU_512_BYTES = 0x2,
2191 MLX5_QPC_MTU_1K_BYTES = 0x3,
2192 MLX5_QPC_MTU_2K_BYTES = 0x4,
2193 MLX5_QPC_MTU_4K_BYTES = 0x5,
2194 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2195};
2196
2197enum {
2198 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2199 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2200 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2201 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2202 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2203 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2204 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2205 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2206};
2207
2208enum {
2209 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2210 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2211 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2212};
2213
2214enum {
2215 MLX5_QPC_CS_RES_DISABLE = 0x0,
2216 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2217 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2218};
2219
2220struct mlx5_ifc_qpc_bits {
2221 u8 state[0x4];
84df61eb 2222 u8 lag_tx_port_affinity[0x4];
e281682b 2223 u8 st[0x8];
b4ff3a36 2224 u8 reserved_at_10[0x3];
e281682b 2225 u8 pm_state[0x2];
6e44636a
AK		 2226 u8 reserved_at_15[0x3];
2227 u8 offload_type[0x4];
e281682b 2228 u8 end_padding_mode[0x2];
b4ff3a36 2229 u8 reserved_at_1e[0x2];
e281682b
SM		 2230
2231 u8 wq_signature[0x1];
2232 u8 block_lb_mc[0x1];
2233 u8 atomic_like_write_en[0x1];
2234 u8 latency_sensitive[0x1];
b4ff3a36 2235 u8 reserved_at_24[0x1];
e281682b 2236 u8 drain_sigerr[0x1];
b4ff3a36 2237 u8 reserved_at_26[0x2];
e281682b
SM		 2238 u8 pd[0x18];
2239
2240 u8 mtu[0x3];
2241 u8 log_msg_max[0x5];
b4ff3a36 2242 u8 reserved_at_48[0x1];
e281682b
SM		 2243 u8 log_rq_size[0x4];
2244 u8 log_rq_stride[0x3];
2245 u8 no_sq[0x1];
2246 u8 log_sq_size[0x4];
b4ff3a36 2247 u8 reserved_at_55[0x6];
e281682b 2248 u8 rlky[0x1];
1015c2e8 2249 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2250
2251 u8 counter_set_id[0x8];
2252 u8 uar_page[0x18];
2253
b4ff3a36 2254 u8 reserved_at_80[0x8];
e281682b
SM		 2255 u8 user_index[0x18];
2256
b4ff3a36 2257 u8 reserved_at_a0[0x3];
e281682b
SM		 2258 u8 log_page_size[0x5];
2259 u8 remote_qpn[0x18];
2260
2261 struct mlx5_ifc_ads_bits primary_address_path;
2262
2263 struct mlx5_ifc_ads_bits secondary_address_path;
2264
2265 u8 log_ack_req_freq[0x4];
b4ff3a36 2266 u8 reserved_at_384[0x4];
e281682b 2267 u8 log_sra_max[0x3];
b4ff3a36 2268 u8 reserved_at_38b[0x2];
e281682b
SM		 2269 u8 retry_count[0x3];
2270 u8 rnr_retry[0x3];
b4ff3a36 2271 u8 reserved_at_393[0x1];
e281682b
SM		 2272 u8 fre[0x1];
2273 u8 cur_rnr_retry[0x3];
2274 u8 cur_retry_count[0x3];
b4ff3a36 2275 u8 reserved_at_39b[0x5];
e281682b 2276
b4ff3a36 2277 u8 reserved_at_3a0[0x20];
e281682b 2278
b4ff3a36 2279 u8 reserved_at_3c0[0x8];
e281682b
SM		 2280 u8 next_send_psn[0x18];
2281
b4ff3a36 2282 u8 reserved_at_3e0[0x8];
e281682b
SM		 2283 u8 cqn_snd[0x18];
2284
09a7d9ec
SM		 2285 u8 reserved_at_400[0x8];
2286 u8 deth_sqpn[0x18];
2287
2288 u8 reserved_at_420[0x20];
e281682b 2289
b4ff3a36 2290 u8 reserved_at_440[0x8];
e281682b
SM		 2291 u8 last_acked_psn[0x18];
2292
b4ff3a36 2293 u8 reserved_at_460[0x8];
e281682b
SM		 2294 u8 ssn[0x18];
2295
b4ff3a36 2296 u8 reserved_at_480[0x8];
e281682b 2297 u8 log_rra_max[0x3];
b4ff3a36 2298 u8 reserved_at_48b[0x1];
e281682b
SM		 2299 u8 atomic_mode[0x4];
2300 u8 rre[0x1];
2301 u8 rwe[0x1];
2302 u8 rae[0x1];
b4ff3a36 2303 u8 reserved_at_493[0x1];
e281682b 2304 u8 page_offset[0x6];
b4ff3a36 2305 u8 reserved_at_49a[0x3];
e281682b
SM		 2306 u8 cd_slave_receive[0x1];
2307 u8 cd_slave_send[0x1];
2308 u8 cd_master[0x1];
2309
b4ff3a36 2310 u8 reserved_at_4a0[0x3];
e281682b
SM		 2311 u8 min_rnr_nak[0x5];
2312 u8 next_rcv_psn[0x18];
2313
b4ff3a36 2314 u8 reserved_at_4c0[0x8];
e281682b
SM		 2315 u8 xrcd[0x18];
2316
b4ff3a36 2317 u8 reserved_at_4e0[0x8];
e281682b
SM		 2318 u8 cqn_rcv[0x18];
2319
2320 u8 dbr_addr[0x40];
2321
2322 u8 q_key[0x20];
2323
b4ff3a36 2324 u8 reserved_at_560[0x5];
e281682b 2325 u8 rq_type[0x3];
7486216b 2326 u8 srqn_rmpn_xrqn[0x18];
e281682b 2327
b4ff3a36 2328 u8 reserved_at_580[0x8];
e281682b
SM		 2329 u8 rmsn[0x18];
2330
2331 u8 hw_sq_wqebb_counter[0x10];
2332 u8 sw_sq_wqebb_counter[0x10];
2333
2334 u8 hw_rq_counter[0x20];
2335
2336 u8 sw_rq_counter[0x20];
2337
b4ff3a36 2338 u8 reserved_at_600[0x20];
e281682b 2339
b4ff3a36 2340 u8 reserved_at_620[0xf];
e281682b
SM		 2341 u8 cgs[0x1];
2342 u8 cs_req[0x8];
2343 u8 cs_res[0x8];
2344
2345 u8 dc_access_key[0x40];
2346
b4ff3a36 2347 u8 reserved_at_680[0xc0];
e281682b
SM		 2348};
2349
2350struct mlx5_ifc_roce_addr_layout_bits {
2351 u8 source_l3_address[16][0x8];
2352
b4ff3a36 2353 u8 reserved_at_80[0x3];
e281682b
SM		 2354 u8 vlan_valid[0x1];
2355 u8 vlan_id[0xc];
2356 u8 source_mac_47_32[0x10];
2357
2358 u8 source_mac_31_0[0x20];
2359
b4ff3a36 2360 u8 reserved_at_c0[0x14];
e281682b
SM		 2361 u8 roce_l3_type[0x4];
2362 u8 roce_version[0x8];
2363
b4ff3a36 2364 u8 reserved_at_e0[0x20];
e281682b
SM		 2365};
2366
2367union mlx5_ifc_hca_cap_union_bits {
2368 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2369 struct mlx5_ifc_odp_cap_bits odp_cap;
2370 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2371 struct mlx5_ifc_roce_cap_bits roce_cap;
2372 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2373 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2374 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2375 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2376 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2377 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2378 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2379 u8 reserved_at_0[0x8000];
e281682b
SM		 2380};
2381
2382enum {
2383 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2384 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2385 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2386 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2387 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2388 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2389 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2390 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2391 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 2392 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2393 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
0c06897a
OG		 2394};
2395
2396struct mlx5_ifc_vlan_bits {
2397 u8 ethtype[0x10];
2398 u8 prio[0x3];
2399 u8 cfi[0x1];
2400 u8 vid[0xc];
e281682b
SM		 2401};
2402
2403struct mlx5_ifc_flow_context_bits {
0c06897a 2404 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2405
2406 u8 group_id[0x20];
2407
b4ff3a36 2408 u8 reserved_at_40[0x8];
e281682b
SM		 2409 u8 flow_tag[0x18];
2410
b4ff3a36 2411 u8 reserved_at_60[0x10];
e281682b
SM		 2412 u8 action[0x10];
2413
b4ff3a36 2414 u8 reserved_at_80[0x8];
e281682b
SM		 2415 u8 destination_list_size[0x18];
2416
9dc0b289
AV		 2417 u8 reserved_at_a0[0x8];
2418 u8 flow_counter_list_size[0x18];
2419
7adbde20
HHZ		 2420 u8 encap_id[0x20];
2421
2a69cb9f
OG		 2422 u8 modify_header_id[0x20];
2423
8da6fe2a
JL		 2424 struct mlx5_ifc_vlan_bits push_vlan_2;
2425
2426 u8 reserved_at_120[0xe0];
e281682b
SM		 2427
2428 struct mlx5_ifc_fte_match_param_bits match_value;
2429
b4ff3a36 2430 u8 reserved_at_1200[0x600];
e281682b 2431
9dc0b289 2432 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2433};
2434
2435enum {
2436 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2437 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2438};
2439
2440struct mlx5_ifc_xrc_srqc_bits {
2441 u8 state[0x4];
2442 u8 log_xrc_srq_size[0x4];
b4ff3a36 2443 u8 reserved_at_8[0x18];
e281682b
SM		 2444
2445 u8 wq_signature[0x1];
2446 u8 cont_srq[0x1];
b4ff3a36 2447 u8 reserved_at_22[0x1];
e281682b
SM		 2448 u8 rlky[0x1];
2449 u8 basic_cyclic_rcv_wqe[0x1];
2450 u8 log_rq_stride[0x3];
2451 u8 xrcd[0x18];
2452
2453 u8 page_offset[0x6];
b4ff3a36 2454 u8 reserved_at_46[0x2];
e281682b
SM		 2455 u8 cqn[0x18];
2456
b4ff3a36 2457 u8 reserved_at_60[0x20];
e281682b
SM		 2458
2459 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2460 u8 reserved_at_81[0x1];
e281682b
SM		 2461 u8 log_page_size[0x6];
2462 u8 user_index[0x18];
2463
b4ff3a36 2464 u8 reserved_at_a0[0x20];
e281682b 2465
b4ff3a36 2466 u8 reserved_at_c0[0x8];
e281682b
SM		 2467 u8 pd[0x18];
2468
2469 u8 lwm[0x10];
2470 u8 wqe_cnt[0x10];
2471
b4ff3a36 2472 u8 reserved_at_100[0x40];
e281682b
SM		 2473
2474 u8 db_record_addr_h[0x20];
2475
2476 u8 db_record_addr_l[0x1e];
b4ff3a36 2477 u8 reserved_at_17e[0x2];
e281682b 2478
b4ff3a36 2479 u8 reserved_at_180[0x80];
e281682b
SM		 2480};
2481
61c5b5c9
MS		 2482struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2483 u8 counter_error_queues[0x20];
2484
2485 u8 total_error_queues[0x20];
2486
2487 u8 send_queue_priority_update_flow[0x20];
2488
2489 u8 reserved_at_60[0x20];
2490
2491 u8 nic_receive_steering_discard[0x40];
2492
2493 u8 receive_discard_vport_down[0x40];
2494
2495 u8 transmit_discard_vport_down[0x40];
2496
2497 u8 reserved_at_140[0xec0];
2498};
2499
e281682b
SM		 2500struct mlx5_ifc_traffic_counter_bits {
2501 u8 packets[0x40];
2502
2503 u8 octets[0x40];
2504};
2505
2506struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2507 u8 strict_lag_tx_port_affinity[0x1];
2508 u8 reserved_at_1[0x3];
2509 u8 lag_tx_port_affinity[0x04];
2510
2511 u8 reserved_at_8[0x4];
e281682b 2512 u8 prio[0x4];
b4ff3a36 2513 u8 reserved_at_10[0x10];
e281682b 2514
b4ff3a36 2515 u8 reserved_at_20[0x100];
e281682b 2516
b4ff3a36 2517 u8 reserved_at_120[0x8];
e281682b
SM		 2518 u8 transport_domain[0x18];
2519
500a3d0d
ES		 2520 u8 reserved_at_140[0x8];
2521 u8 underlay_qpn[0x18];
2522 u8 reserved_at_160[0x3a0];
e281682b
SM		 2523};
2524
2525enum {
2526 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2527 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2528};
2529
2530enum {
2531 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2532 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2533};
2534
2535enum {
2be6967c
SM		 2536 MLX5_RX_HASH_FN_NONE = 0x0,
2537 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2538 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2539};
2540
2541enum {
2542 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2543 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2544};
2545
2546struct mlx5_ifc_tirc_bits {
b4ff3a36 2547 u8 reserved_at_0[0x20];
e281682b
SM		 2548
2549 u8 disp_type[0x4];
b4ff3a36 2550 u8 reserved_at_24[0x1c];
e281682b 2551
b4ff3a36 2552 u8 reserved_at_40[0x40];
e281682b 2553
b4ff3a36 2554 u8 reserved_at_80[0x4];
e281682b
SM		 2555 u8 lro_timeout_period_usecs[0x10];
2556 u8 lro_enable_mask[0x4];
2557 u8 lro_max_ip_payload_size[0x8];
2558
b4ff3a36 2559 u8 reserved_at_a0[0x40];
e281682b 2560
b4ff3a36 2561 u8 reserved_at_e0[0x8];
e281682b
SM		 2562 u8 inline_rqn[0x18];
2563
2564 u8 rx_hash_symmetric[0x1];
b4ff3a36 2565 u8 reserved_at_101[0x1];
e281682b 2566 u8 tunneled_offload_en[0x1];
b4ff3a36 2567 u8 reserved_at_103[0x5];
e281682b
SM		 2568 u8 indirect_table[0x18];
2569
2570 u8 rx_hash_fn[0x4];
b4ff3a36 2571 u8 reserved_at_124[0x2];
e281682b
SM		 2572 u8 self_lb_block[0x2];
2573 u8 transport_domain[0x18];
2574
2575 u8 rx_hash_toeplitz_key[10][0x20];
2576
2577 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2578
2579 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2580
b4ff3a36 2581 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2582};
2583
2584enum {
2585 MLX5_SRQC_STATE_GOOD = 0x0,
2586 MLX5_SRQC_STATE_ERROR = 0x1,
2587};
2588
2589struct mlx5_ifc_srqc_bits {
2590 u8 state[0x4];
2591 u8 log_srq_size[0x4];
b4ff3a36 2592 u8 reserved_at_8[0x18];
e281682b
SM		 2593
2594 u8 wq_signature[0x1];
2595 u8 cont_srq[0x1];
b4ff3a36 2596 u8 reserved_at_22[0x1];
e281682b 2597 u8 rlky[0x1];
b4ff3a36 2598 u8 reserved_at_24[0x1];
e281682b
SM		 2599 u8 log_rq_stride[0x3];
2600 u8 xrcd[0x18];
2601
2602 u8 page_offset[0x6];
b4ff3a36 2603 u8 reserved_at_46[0x2];
e281682b
SM		 2604 u8 cqn[0x18];
2605
b4ff3a36 2606 u8 reserved_at_60[0x20];
e281682b 2607
b4ff3a36 2608 u8 reserved_at_80[0x2];
e281682b 2609 u8 log_page_size[0x6];
b4ff3a36 2610 u8 reserved_at_88[0x18];
e281682b 2611
b4ff3a36 2612 u8 reserved_at_a0[0x20];
e281682b 2613
b4ff3a36 2614 u8 reserved_at_c0[0x8];
e281682b
SM		 2615 u8 pd[0x18];
2616
2617 u8 lwm[0x10];
2618 u8 wqe_cnt[0x10];
2619
b4ff3a36 2620 u8 reserved_at_100[0x40];
e281682b 2621
01949d01 2622 u8 dbr_addr[0x40];
e281682b 2623
b4ff3a36 2624 u8 reserved_at_180[0x80];
e281682b
SM		 2625};
2626
2627enum {
2628 MLX5_SQC_STATE_RST = 0x0,
2629 MLX5_SQC_STATE_RDY = 0x1,
2630 MLX5_SQC_STATE_ERR = 0x3,
2631};
2632
2633struct mlx5_ifc_sqc_bits {
2634 u8 rlky[0x1];
2635 u8 cd_master[0x1];
2636 u8 fre[0x1];
2637 u8 flush_in_error_en[0x1];
795b609c 2638 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2639 u8 min_wqe_inline_mode[0x3];
e281682b 2640 u8 state[0x4];
7d5e1423 2641 u8 reg_umr[0x1];
547eede0 2642 u8 allow_swp[0x1];
40817cdb
OG		 2643 u8 hairpin[0x1];
2644 u8 reserved_at_f[0x11];
e281682b 2645
b4ff3a36 2646 u8 reserved_at_20[0x8];
e281682b
SM		 2647 u8 user_index[0x18];
2648
b4ff3a36 2649 u8 reserved_at_40[0x8];
e281682b
SM		 2650 u8 cqn[0x18];
2651
40817cdb
OG		 2652 u8 reserved_at_60[0x8];
2653 u8 hairpin_peer_rq[0x18];
2654
2655 u8 reserved_at_80[0x10];
2656 u8 hairpin_peer_vhca[0x10];
2657
2658 u8 reserved_at_a0[0x50];
e281682b 2659
7486216b 2660 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2661 u8 tis_lst_sz[0x10];
b4ff3a36 2662 u8 reserved_at_110[0x10];
e281682b 2663
b4ff3a36 2664 u8 reserved_at_120[0x40];
e281682b 2665
b4ff3a36 2666 u8 reserved_at_160[0x8];
e281682b
SM		 2667 u8 tis_num_0[0x18];
2668
2669 struct mlx5_ifc_wq_bits wq;
2670};
2671
813f8540
MHY		 2672enum {
2673 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2674 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2675 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2676 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2677};
2678
2679struct mlx5_ifc_scheduling_context_bits {
2680 u8 element_type[0x8];
2681 u8 reserved_at_8[0x18];
2682
2683 u8 element_attributes[0x20];
2684
2685 u8 parent_element_id[0x20];
2686
2687 u8 reserved_at_60[0x40];
2688
2689 u8 bw_share[0x20];
2690
2691 u8 max_average_bw[0x20];
2692
2693 u8 reserved_at_e0[0x120];
2694};
2695
e281682b 2696struct mlx5_ifc_rqtc_bits {
b4ff3a36 2697 u8 reserved_at_0[0xa0];
e281682b 2698
b4ff3a36 2699 u8 reserved_at_a0[0x10];
e281682b
SM		 2700 u8 rqt_max_size[0x10];
2701
b4ff3a36 2702 u8 reserved_at_c0[0x10];
e281682b
SM		 2703 u8 rqt_actual_size[0x10];
2704
b4ff3a36 2705 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2706
2707 struct mlx5_ifc_rq_num_bits rq_num[0];
2708};
2709
2710enum {
2711 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2712 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2713};
2714
2715enum {
2716 MLX5_RQC_STATE_RST = 0x0,
2717 MLX5_RQC_STATE_RDY = 0x1,
2718 MLX5_RQC_STATE_ERR = 0x3,
2719};
2720
2721struct mlx5_ifc_rqc_bits {
2722 u8 rlky[0x1];
03404e8a 2723 u8 delay_drop_en[0x1];
7d5e1423 2724 u8 scatter_fcs[0x1];
e281682b
SM		 2725 u8 vsd[0x1];
2726 u8 mem_rq_type[0x4];
2727 u8 state[0x4];
b4ff3a36 2728 u8 reserved_at_c[0x1];
e281682b 2729 u8 flush_in_error_en[0x1];
40817cdb
OG		 2730 u8 hairpin[0x1];
2731 u8 reserved_at_f[0x11];
e281682b 2732
b4ff3a36 2733 u8 reserved_at_20[0x8];
e281682b
SM		 2734 u8 user_index[0x18];
2735
b4ff3a36 2736 u8 reserved_at_40[0x8];
e281682b
SM		 2737 u8 cqn[0x18];
2738
2739 u8 counter_set_id[0x8];
b4ff3a36 2740 u8 reserved_at_68[0x18];
e281682b 2741
b4ff3a36 2742 u8 reserved_at_80[0x8];
e281682b
SM		 2743 u8 rmpn[0x18];
2744
40817cdb
OG		 2745 u8 reserved_at_a0[0x8];
2746 u8 hairpin_peer_sq[0x18];
2747
2748 u8 reserved_at_c0[0x10];
2749 u8 hairpin_peer_vhca[0x10];
2750
2751 u8 reserved_at_e0[0xa0];
e281682b
SM		 2752
2753 struct mlx5_ifc_wq_bits wq;
2754};
2755
2756enum {
2757 MLX5_RMPC_STATE_RDY = 0x1,
2758 MLX5_RMPC_STATE_ERR = 0x3,
2759};
2760
2761struct mlx5_ifc_rmpc_bits {
b4ff3a36 2762 u8 reserved_at_0[0x8];
e281682b 2763 u8 state[0x4];
b4ff3a36 2764 u8 reserved_at_c[0x14];
e281682b
SM		 2765
2766 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2767 u8 reserved_at_21[0x1f];
e281682b 2768
b4ff3a36 2769 u8 reserved_at_40[0x140];
e281682b
SM		 2770
2771 struct mlx5_ifc_wq_bits wq;
2772};
2773
e281682b 2774struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2775 u8 reserved_at_0[0x5];
2776 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2777 u8 reserved_at_8[0x15];
2778 u8 disable_mc_local_lb[0x1];
2779 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2780 u8 roce_en[0x1];
2781
d82b7318 2782 u8 arm_change_event[0x1];
b4ff3a36 2783 u8 reserved_at_21[0x1a];
d82b7318
SM		 2784 u8 event_on_mtu[0x1];
2785 u8 event_on_promisc_change[0x1];
2786 u8 event_on_vlan_change[0x1];
2787 u8 event_on_mc_address_change[0x1];
2788 u8 event_on_uc_address_change[0x1];
e281682b 2789
32f69e4b
DJ		 2790 u8 reserved_at_40[0xc];
2791
2792 u8 affiliation_criteria[0x4];
2793 u8 affiliated_vhca_id[0x10];
2794
2795 u8 reserved_at_60[0xd0];
d82b7318
SM		 2796
2797 u8 mtu[0x10];
2798
9efa7525
AS		 2799 u8 system_image_guid[0x40];
2800 u8 port_guid[0x40];
2801 u8 node_guid[0x40];
2802
b4ff3a36 2803 u8 reserved_at_200[0x140];
9efa7525 2804 u8 qkey_violation_counter[0x10];
b4ff3a36 2805 u8 reserved_at_350[0x430];
d82b7318
SM		 2806
2807 u8 promisc_uc[0x1];
2808 u8 promisc_mc[0x1];
2809 u8 promisc_all[0x1];
b4ff3a36 2810 u8 reserved_at_783[0x2];
e281682b 2811 u8 allowed_list_type[0x3];
b4ff3a36 2812 u8 reserved_at_788[0xc];
e281682b
SM		 2813 u8 allowed_list_size[0xc];
2814
2815 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2816
b4ff3a36 2817 u8 reserved_at_7e0[0x20];
e281682b
SM		 2818
2819 u8 current_uc_mac_address[0][0x40];
2820};
2821
2822enum {
2823 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2824 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2825 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2826 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
cdbd0d2b 2827 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 2828};
2829
2830struct mlx5_ifc_mkc_bits {
b4ff3a36 2831 u8 reserved_at_0[0x1];
e281682b 2832 u8 free[0x1];
cdbd0d2b
AL		 2833 u8 reserved_at_2[0x1];
2834 u8 access_mode_4_2[0x3];
2835 u8 reserved_at_6[0x7];
2836 u8 relaxed_ordering_write[0x1];
2837 u8 reserved_at_e[0x1];
e281682b
SM		 2838 u8 small_fence_on_rdma_read_response[0x1];
2839 u8 umr_en[0x1];
2840 u8 a[0x1];
2841 u8 rw[0x1];
2842 u8 rr[0x1];
2843 u8 lw[0x1];
2844 u8 lr[0x1];
cdbd0d2b 2845 u8 access_mode_1_0[0x2];
b4ff3a36 2846 u8 reserved_at_18[0x8];
e281682b
SM		 2847
2848 u8 qpn[0x18];
2849 u8 mkey_7_0[0x8];
2850
b4ff3a36 2851 u8 reserved_at_40[0x20];
e281682b
SM		 2852
2853 u8 length64[0x1];
2854 u8 bsf_en[0x1];
2855 u8 sync_umr[0x1];
b4ff3a36 2856 u8 reserved_at_63[0x2];
e281682b 2857 u8 expected_sigerr_count[0x1];
b4ff3a36 2858 u8 reserved_at_66[0x1];
e281682b
SM		 2859 u8 en_rinval[0x1];
2860 u8 pd[0x18];
2861
2862 u8 start_addr[0x40];
2863
2864 u8 len[0x40];
2865
2866 u8 bsf_octword_size[0x20];
2867
b4ff3a36 2868 u8 reserved_at_120[0x80];
e281682b
SM		 2869
2870 u8 translations_octword_size[0x20];
2871
b4ff3a36 2872 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2873 u8 log_page_size[0x5];
2874
b4ff3a36 2875 u8 reserved_at_1e0[0x20];
e281682b
SM		 2876};
2877
2878struct mlx5_ifc_pkey_bits {
b4ff3a36 2879 u8 reserved_at_0[0x10];
e281682b
SM		 2880 u8 pkey[0x10];
2881};
2882
2883struct mlx5_ifc_array128_auto_bits {
2884 u8 array128_auto[16][0x8];
2885};
2886
2887struct mlx5_ifc_hca_vport_context_bits {
2888 u8 field_select[0x20];
2889
b4ff3a36 2890 u8 reserved_at_20[0xe0];
e281682b
SM		 2891
2892 u8 sm_virt_aware[0x1];
2893 u8 has_smi[0x1];
2894 u8 has_raw[0x1];
2895 u8 grh_required[0x1];
b4ff3a36 2896 u8 reserved_at_104[0xc];
707c4602
MD		 2897 u8 port_physical_state[0x4];
2898 u8 vport_state_policy[0x4];
2899 u8 port_state[0x4];
e281682b
SM		 2900 u8 vport_state[0x4];
2901
b4ff3a36 2902 u8 reserved_at_120[0x20];
707c4602
MD		 2903
2904 u8 system_image_guid[0x40];
e281682b
SM		 2905
2906 u8 port_guid[0x40];
2907
2908 u8 node_guid[0x40];
2909
2910 u8 cap_mask1[0x20];
2911
2912 u8 cap_mask1_field_select[0x20];
2913
2914 u8 cap_mask2[0x20];
2915
2916 u8 cap_mask2_field_select[0x20];
2917
b4ff3a36 2918 u8 reserved_at_280[0x80];
e281682b
SM		 2919
2920 u8 lid[0x10];
b4ff3a36 2921 u8 reserved_at_310[0x4];
e281682b
SM		 2922 u8 init_type_reply[0x4];
2923 u8 lmc[0x3];
2924 u8 subnet_timeout[0x5];
2925
2926 u8 sm_lid[0x10];
2927 u8 sm_sl[0x4];
b4ff3a36 2928 u8 reserved_at_334[0xc];
e281682b
SM		 2929
2930 u8 qkey_violation_counter[0x10];
2931 u8 pkey_violation_counter[0x10];
2932
b4ff3a36 2933 u8 reserved_at_360[0xca0];
e281682b
SM		 2934};
2935
d6666753 2936struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2937 u8 reserved_at_0[0x3];
d6666753
SM		 2938 u8 vport_svlan_strip[0x1];
2939 u8 vport_cvlan_strip[0x1];
2940 u8 vport_svlan_insert[0x1];
2941 u8 vport_cvlan_insert[0x2];
b4ff3a36 2942 u8 reserved_at_8[0x18];
d6666753 2943
b4ff3a36 2944 u8 reserved_at_20[0x20];
d6666753
SM		 2945
2946 u8 svlan_cfi[0x1];
2947 u8 svlan_pcp[0x3];
2948 u8 svlan_id[0xc];
2949 u8 cvlan_cfi[0x1];
2950 u8 cvlan_pcp[0x3];
2951 u8 cvlan_id[0xc];
2952
b4ff3a36 2953 u8 reserved_at_60[0x7a0];
d6666753
SM		 2954};
2955
e281682b
SM		 2956enum {
2957 MLX5_EQC_STATUS_OK = 0x0,
2958 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2959};
2960
2961enum {
2962 MLX5_EQC_ST_ARMED = 0x9,
2963 MLX5_EQC_ST_FIRED = 0xa,
2964};
2965
2966struct mlx5_ifc_eqc_bits {
2967 u8 status[0x4];
b4ff3a36 2968 u8 reserved_at_4[0x9];
e281682b
SM		 2969 u8 ec[0x1];
2970 u8 oi[0x1];
b4ff3a36 2971 u8 reserved_at_f[0x5];
e281682b 2972 u8 st[0x4];
b4ff3a36 2973 u8 reserved_at_18[0x8];
e281682b 2974
b4ff3a36 2975 u8 reserved_at_20[0x20];
e281682b 2976
b4ff3a36 2977 u8 reserved_at_40[0x14];
e281682b 2978 u8 page_offset[0x6];
b4ff3a36 2979 u8 reserved_at_5a[0x6];
e281682b 2980
b4ff3a36 2981 u8 reserved_at_60[0x3];
e281682b
SM		 2982 u8 log_eq_size[0x5];
2983 u8 uar_page[0x18];
2984
b4ff3a36 2985 u8 reserved_at_80[0x20];
e281682b 2986
b4ff3a36 2987 u8 reserved_at_a0[0x18];
e281682b
SM		 2988 u8 intr[0x8];
2989
b4ff3a36 2990 u8 reserved_at_c0[0x3];
e281682b 2991 u8 log_page_size[0x5];
b4ff3a36 2992 u8 reserved_at_c8[0x18];
e281682b 2993
b4ff3a36 2994 u8 reserved_at_e0[0x60];
e281682b 2995
b4ff3a36 2996 u8 reserved_at_140[0x8];
e281682b
SM		 2997 u8 consumer_counter[0x18];
2998
b4ff3a36 2999 u8 reserved_at_160[0x8];
e281682b
SM		 3000 u8 producer_counter[0x18];
3001
b4ff3a36 3002 u8 reserved_at_180[0x80];
e281682b
SM		 3003};
3004
3005enum {
3006 MLX5_DCTC_STATE_ACTIVE = 0x0,
3007 MLX5_DCTC_STATE_DRAINING = 0x1,
3008 MLX5_DCTC_STATE_DRAINED = 0x2,
3009};
3010
3011enum {
3012 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3013 MLX5_DCTC_CS_RES_NA = 0x1,
3014 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3015};
3016
3017enum {
3018 MLX5_DCTC_MTU_256_BYTES = 0x1,
3019 MLX5_DCTC_MTU_512_BYTES = 0x2,
3020 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3021 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3022 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3023};
3024
3025struct mlx5_ifc_dctc_bits {
b4ff3a36 3026 u8 reserved_at_0[0x4];
e281682b 3027 u8 state[0x4];
b4ff3a36 3028 u8 reserved_at_8[0x18];
e281682b 3029
b4ff3a36 3030 u8 reserved_at_20[0x8];
e281682b
SM		 3031 u8 user_index[0x18];
3032
b4ff3a36 3033 u8 reserved_at_40[0x8];
e281682b
SM		 3034 u8 cqn[0x18];
3035
3036 u8 counter_set_id[0x8];
3037 u8 atomic_mode[0x4];
3038 u8 rre[0x1];
3039 u8 rwe[0x1];
3040 u8 rae[0x1];
3041 u8 atomic_like_write_en[0x1];
3042 u8 latency_sensitive[0x1];
3043 u8 rlky[0x1];
3044 u8 free_ar[0x1];
b4ff3a36 3045 u8 reserved_at_73[0xd];
e281682b 3046
b4ff3a36 3047 u8 reserved_at_80[0x8];
e281682b 3048 u8 cs_res[0x8];
b4ff3a36 3049 u8 reserved_at_90[0x3];
e281682b 3050 u8 min_rnr_nak[0x5];
b4ff3a36 3051 u8 reserved_at_98[0x8];
e281682b 3052
b4ff3a36 3053 u8 reserved_at_a0[0x8];
7486216b 3054 u8 srqn_xrqn[0x18];
e281682b 3055
b4ff3a36 3056 u8 reserved_at_c0[0x8];
e281682b
SM		 3057 u8 pd[0x18];
3058
3059 u8 tclass[0x8];
b4ff3a36 3060 u8 reserved_at_e8[0x4];
e281682b
SM		 3061 u8 flow_label[0x14];
3062
3063 u8 dc_access_key[0x40];
3064
b4ff3a36 3065 u8 reserved_at_140[0x5];
e281682b
SM		 3066 u8 mtu[0x3];
3067 u8 port[0x8];
3068 u8 pkey_index[0x10];
3069
b4ff3a36 3070 u8 reserved_at_160[0x8];
e281682b 3071 u8 my_addr_index[0x8];
b4ff3a36 3072 u8 reserved_at_170[0x8];
e281682b
SM		 3073 u8 hop_limit[0x8];
3074
3075 u8 dc_access_key_violation_count[0x20];
3076
b4ff3a36 3077 u8 reserved_at_1a0[0x14];
e281682b
SM		 3078 u8 dei_cfi[0x1];
3079 u8 eth_prio[0x3];
3080 u8 ecn[0x2];
3081 u8 dscp[0x6];
3082
b4ff3a36 3083 u8 reserved_at_1c0[0x40];
e281682b
SM		 3084};
3085
3086enum {
3087 MLX5_CQC_STATUS_OK = 0x0,
3088 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3089 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3090};
3091
3092enum {
3093 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3094 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3095};
3096
3097enum {
3098 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3099 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3100 MLX5_CQC_ST_FIRED = 0xa,
3101};
3102
7d5e1423
SM		 3103enum {
3104 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3105 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3106 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3107};
3108
e281682b
SM		 3109struct mlx5_ifc_cqc_bits {
3110 u8 status[0x4];
b4ff3a36 3111 u8 reserved_at_4[0x4];
e281682b
SM		 3112 u8 cqe_sz[0x3];
3113 u8 cc[0x1];
b4ff3a36 3114 u8 reserved_at_c[0x1];
e281682b
SM		 3115 u8 scqe_break_moderation_en[0x1];
3116 u8 oi[0x1];
7d5e1423
SM		 3117 u8 cq_period_mode[0x2];
3118 u8 cqe_comp_en[0x1];
e281682b
SM		 3119 u8 mini_cqe_res_format[0x2];
3120 u8 st[0x4];
b4ff3a36 3121 u8 reserved_at_18[0x8];
e281682b 3122
b4ff3a36 3123 u8 reserved_at_20[0x20];
e281682b 3124
b4ff3a36 3125 u8 reserved_at_40[0x14];
e281682b 3126 u8 page_offset[0x6];
b4ff3a36 3127 u8 reserved_at_5a[0x6];
e281682b 3128
b4ff3a36 3129 u8 reserved_at_60[0x3];
e281682b
SM		 3130 u8 log_cq_size[0x5];
3131 u8 uar_page[0x18];
3132
b4ff3a36 3133 u8 reserved_at_80[0x4];
e281682b
SM		 3134 u8 cq_period[0xc];
3135 u8 cq_max_count[0x10];
3136
b4ff3a36 3137 u8 reserved_at_a0[0x18];
e281682b
SM		 3138 u8 c_eqn[0x8];
3139
b4ff3a36 3140 u8 reserved_at_c0[0x3];
e281682b 3141 u8 log_page_size[0x5];
b4ff3a36 3142 u8 reserved_at_c8[0x18];
e281682b 3143
b4ff3a36 3144 u8 reserved_at_e0[0x20];
e281682b 3145
b4ff3a36 3146 u8 reserved_at_100[0x8];
e281682b
SM		 3147 u8 last_notified_index[0x18];
3148
b4ff3a36 3149 u8 reserved_at_120[0x8];
e281682b
SM		 3150 u8 last_solicit_index[0x18];
3151
b4ff3a36 3152 u8 reserved_at_140[0x8];
e281682b
SM		 3153 u8 consumer_counter[0x18];
3154
b4ff3a36 3155 u8 reserved_at_160[0x8];
e281682b
SM		 3156 u8 producer_counter[0x18];
3157
b4ff3a36 3158 u8 reserved_at_180[0x40];
e281682b
SM		 3159
3160 u8 dbr_addr[0x40];
3161};
3162
3163union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3164 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3165 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3166 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3167 u8 reserved_at_0[0x800];
e281682b
SM		 3168};
3169
3170struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3171 u8 reserved_at_0[0xc0];
e281682b 3172
b4ff3a36 3173 u8 reserved_at_c0[0x8];
211e6c80
MD		 3174 u8 ieee_vendor_id[0x18];
3175
b4ff3a36 3176 u8 reserved_at_e0[0x10];
e281682b
SM		 3177 u8 vsd_vendor_id[0x10];
3178
3179 u8 vsd[208][0x8];
3180
3181 u8 vsd_contd_psid[16][0x8];
3182};
3183
7486216b
SM		 3184enum {
3185 MLX5_XRQC_STATE_GOOD = 0x0,
3186 MLX5_XRQC_STATE_ERROR = 0x1,
3187};
3188
3189enum {
3190 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3191 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3192};
3193
3194enum {
3195 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3196};
3197
3198struct mlx5_ifc_tag_matching_topology_context_bits {
3199 u8 log_matching_list_sz[0x4];
3200 u8 reserved_at_4[0xc];
3201 u8 append_next_index[0x10];
3202
3203 u8 sw_phase_cnt[0x10];
3204 u8 hw_phase_cnt[0x10];
3205
3206 u8 reserved_at_40[0x40];
3207};
3208
3209struct mlx5_ifc_xrqc_bits {
3210 u8 state[0x4];
3211 u8 rlkey[0x1];
3212 u8 reserved_at_5[0xf];
3213 u8 topology[0x4];
3214 u8 reserved_at_18[0x4];
3215 u8 offload[0x4];
3216
3217 u8 reserved_at_20[0x8];
3218 u8 user_index[0x18];
3219
3220 u8 reserved_at_40[0x8];
3221 u8 cqn[0x18];
3222
3223 u8 reserved_at_60[0xa0];
3224
3225 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3226
6e44636a 3227 u8 reserved_at_180[0x280];
7486216b
SM		 3228
3229 struct mlx5_ifc_wq_bits wq;
3230};
3231
e281682b
SM		 3232union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3233 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3234 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3235 u8 reserved_at_0[0x20];
e281682b
SM		 3236};
3237
3238union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3239 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3240 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3241 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3242 u8 reserved_at_0[0x20];
e281682b
SM		 3243};
3244
3245union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3246 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3247 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3248 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3249 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3250 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3251 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3252 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3253 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3254 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3255 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3256 u8 reserved_at_0[0x7c0];
e281682b
SM		 3257};
3258
8ed1a630
GP		 3259union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3260 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3261 u8 reserved_at_0[0x7c0];
3262};
3263
e281682b
SM		 3264union mlx5_ifc_event_auto_bits {
3265 struct mlx5_ifc_comp_event_bits comp_event;
3266 struct mlx5_ifc_dct_events_bits dct_events;
3267 struct mlx5_ifc_qp_events_bits qp_events;
3268 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3269 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3270 struct mlx5_ifc_cq_error_bits cq_error;
3271 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3272 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3273 struct mlx5_ifc_gpio_event_bits gpio_event;
3274 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3275 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3276 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3277 u8 reserved_at_0[0xe0];
e281682b
SM		 3278};
3279
3280struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3281 u8 reserved_at_0[0x100];
e281682b
SM		 3282
3283 u8 assert_existptr[0x20];
3284
3285 u8 assert_callra[0x20];
3286
b4ff3a36 3287 u8 reserved_at_140[0x40];
e281682b
SM		 3288
3289 u8 fw_version[0x20];
3290
3291 u8 hw_id[0x20];
3292
b4ff3a36 3293 u8 reserved_at_1c0[0x20];
e281682b
SM		 3294
3295 u8 irisc_index[0x8];
3296 u8 synd[0x8];
3297 u8 ext_synd[0x10];
3298};
3299
3300struct mlx5_ifc_register_loopback_control_bits {
3301 u8 no_lb[0x1];
b4ff3a36 3302 u8 reserved_at_1[0x7];
e281682b 3303 u8 port[0x8];
b4ff3a36 3304 u8 reserved_at_10[0x10];
e281682b 3305
b4ff3a36 3306 u8 reserved_at_20[0x60];
e281682b
SM		 3307};
3308
813f8540
MHY		 3309struct mlx5_ifc_vport_tc_element_bits {
3310 u8 traffic_class[0x4];
3311 u8 reserved_at_4[0xc];
3312 u8 vport_number[0x10];
3313};
3314
3315struct mlx5_ifc_vport_element_bits {
3316 u8 reserved_at_0[0x10];
3317 u8 vport_number[0x10];
3318};
3319
3320enum {
3321 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3322 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3323 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3324};
3325
3326struct mlx5_ifc_tsar_element_bits {
3327 u8 reserved_at_0[0x8];
3328 u8 tsar_type[0x8];
3329 u8 reserved_at_10[0x10];
3330};
3331
8812c24d
MD		 3332enum {
3333 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3334 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3335};
3336
e281682b
SM		 3337struct mlx5_ifc_teardown_hca_out_bits {
3338 u8 status[0x8];
b4ff3a36 3339 u8 reserved_at_8[0x18];
e281682b
SM		 3340
3341 u8 syndrome[0x20];
3342
8812c24d
MD		 3343 u8 reserved_at_40[0x3f];
3344
3345 u8 force_state[0x1];
e281682b
SM		 3346};
3347
3348enum {
3349 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3350 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3351};
3352
3353struct mlx5_ifc_teardown_hca_in_bits {
3354 u8 opcode[0x10];
b4ff3a36 3355 u8 reserved_at_10[0x10];
e281682b 3356
b4ff3a36 3357 u8 reserved_at_20[0x10];
e281682b
SM		 3358 u8 op_mod[0x10];
3359
b4ff3a36 3360 u8 reserved_at_40[0x10];
e281682b
SM		 3361 u8 profile[0x10];
3362
b4ff3a36 3363 u8 reserved_at_60[0x20];
e281682b
SM		 3364};
3365
3366struct mlx5_ifc_sqerr2rts_qp_out_bits {
3367 u8 status[0x8];
b4ff3a36 3368 u8 reserved_at_8[0x18];
e281682b
SM		 3369
3370 u8 syndrome[0x20];
3371
b4ff3a36 3372 u8 reserved_at_40[0x40];
e281682b
SM		 3373};
3374
3375struct mlx5_ifc_sqerr2rts_qp_in_bits {
3376 u8 opcode[0x10];
b4ff3a36 3377 u8 reserved_at_10[0x10];
e281682b 3378
b4ff3a36 3379 u8 reserved_at_20[0x10];
e281682b
SM		 3380 u8 op_mod[0x10];
3381
b4ff3a36 3382 u8 reserved_at_40[0x8];
e281682b
SM		 3383 u8 qpn[0x18];
3384
b4ff3a36 3385 u8 reserved_at_60[0x20];
e281682b
SM		 3386
3387 u8 opt_param_mask[0x20];
3388
b4ff3a36 3389 u8 reserved_at_a0[0x20];
e281682b
SM		 3390
3391 struct mlx5_ifc_qpc_bits qpc;
3392
b4ff3a36 3393 u8 reserved_at_800[0x80];
e281682b
SM		 3394};
3395
3396struct mlx5_ifc_sqd2rts_qp_out_bits {
3397 u8 status[0x8];
b4ff3a36 3398 u8 reserved_at_8[0x18];
e281682b
SM		 3399
3400 u8 syndrome[0x20];
3401
b4ff3a36 3402 u8 reserved_at_40[0x40];
e281682b
SM		 3403};
3404
3405struct mlx5_ifc_sqd2rts_qp_in_bits {
3406 u8 opcode[0x10];
b4ff3a36 3407 u8 reserved_at_10[0x10];
e281682b 3408
b4ff3a36 3409 u8 reserved_at_20[0x10];
e281682b
SM		 3410 u8 op_mod[0x10];
3411
b4ff3a36 3412 u8 reserved_at_40[0x8];
e281682b
SM		 3413 u8 qpn[0x18];
3414
b4ff3a36 3415 u8 reserved_at_60[0x20];
e281682b
SM		 3416
3417 u8 opt_param_mask[0x20];
3418
b4ff3a36 3419 u8 reserved_at_a0[0x20];
e281682b
SM		 3420
3421 struct mlx5_ifc_qpc_bits qpc;
3422
b4ff3a36 3423 u8 reserved_at_800[0x80];
e281682b
SM		 3424};
3425
3426struct mlx5_ifc_set_roce_address_out_bits {
3427 u8 status[0x8];
b4ff3a36 3428 u8 reserved_at_8[0x18];
e281682b
SM		 3429
3430 u8 syndrome[0x20];
3431
b4ff3a36 3432 u8 reserved_at_40[0x40];
e281682b
SM		 3433};
3434
3435struct mlx5_ifc_set_roce_address_in_bits {
3436 u8 opcode[0x10];
b4ff3a36 3437 u8 reserved_at_10[0x10];
e281682b 3438
b4ff3a36 3439 u8 reserved_at_20[0x10];
e281682b
SM		 3440 u8 op_mod[0x10];
3441
3442 u8 roce_address_index[0x10];
32f69e4b
DJ		 3443 u8 reserved_at_50[0xc];
3444 u8 vhca_port_num[0x4];
e281682b 3445
b4ff3a36 3446 u8 reserved_at_60[0x20];
e281682b
SM		 3447
3448 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3449};
3450
3451struct mlx5_ifc_set_mad_demux_out_bits {
3452 u8 status[0x8];
b4ff3a36 3453 u8 reserved_at_8[0x18];
e281682b
SM		 3454
3455 u8 syndrome[0x20];
3456
b4ff3a36 3457 u8 reserved_at_40[0x40];
e281682b
SM		 3458};
3459
3460enum {
3461 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3462 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3463};
3464
3465struct mlx5_ifc_set_mad_demux_in_bits {
3466 u8 opcode[0x10];
b4ff3a36 3467 u8 reserved_at_10[0x10];
e281682b 3468
b4ff3a36 3469 u8 reserved_at_20[0x10];
e281682b
SM		 3470 u8 op_mod[0x10];
3471
b4ff3a36 3472 u8 reserved_at_40[0x20];
e281682b 3473
b4ff3a36 3474 u8 reserved_at_60[0x6];
e281682b 3475 u8 demux_mode[0x2];
b4ff3a36 3476 u8 reserved_at_68[0x18];
e281682b
SM		 3477};
3478
3479struct mlx5_ifc_set_l2_table_entry_out_bits {
3480 u8 status[0x8];
b4ff3a36 3481 u8 reserved_at_8[0x18];
e281682b
SM		 3482
3483 u8 syndrome[0x20];
3484
b4ff3a36 3485 u8 reserved_at_40[0x40];
e281682b
SM		 3486};
3487
3488struct mlx5_ifc_set_l2_table_entry_in_bits {
3489 u8 opcode[0x10];
b4ff3a36 3490 u8 reserved_at_10[0x10];
e281682b 3491
b4ff3a36 3492 u8 reserved_at_20[0x10];
e281682b
SM		 3493 u8 op_mod[0x10];
3494
b4ff3a36 3495 u8 reserved_at_40[0x60];
e281682b 3496
b4ff3a36 3497 u8 reserved_at_a0[0x8];
e281682b
SM		 3498 u8 table_index[0x18];
3499
b4ff3a36 3500 u8 reserved_at_c0[0x20];
e281682b 3501
b4ff3a36 3502 u8 reserved_at_e0[0x13];
e281682b
SM		 3503 u8 vlan_valid[0x1];
3504 u8 vlan[0xc];
3505
3506 struct mlx5_ifc_mac_address_layout_bits mac_address;
3507
b4ff3a36 3508 u8 reserved_at_140[0xc0];
e281682b
SM		 3509};
3510
3511struct mlx5_ifc_set_issi_out_bits {
3512 u8 status[0x8];
b4ff3a36 3513 u8 reserved_at_8[0x18];
e281682b
SM		 3514
3515 u8 syndrome[0x20];
3516
b4ff3a36 3517 u8 reserved_at_40[0x40];
e281682b
SM		 3518};
3519
3520struct mlx5_ifc_set_issi_in_bits {
3521 u8 opcode[0x10];
b4ff3a36 3522 u8 reserved_at_10[0x10];
e281682b 3523
b4ff3a36 3524 u8 reserved_at_20[0x10];
e281682b
SM		 3525 u8 op_mod[0x10];
3526
b4ff3a36 3527 u8 reserved_at_40[0x10];
e281682b
SM		 3528 u8 current_issi[0x10];
3529
b4ff3a36 3530 u8 reserved_at_60[0x20];
e281682b
SM		 3531};
3532
3533struct mlx5_ifc_set_hca_cap_out_bits {
3534 u8 status[0x8];
b4ff3a36 3535 u8 reserved_at_8[0x18];
e281682b
SM		 3536
3537 u8 syndrome[0x20];
3538
b4ff3a36 3539 u8 reserved_at_40[0x40];
e281682b
SM		 3540};
3541
3542struct mlx5_ifc_set_hca_cap_in_bits {
3543 u8 opcode[0x10];
b4ff3a36 3544 u8 reserved_at_10[0x10];
e281682b 3545
b4ff3a36 3546 u8 reserved_at_20[0x10];
e281682b
SM		 3547 u8 op_mod[0x10];
3548
b4ff3a36 3549 u8 reserved_at_40[0x40];
e281682b
SM		 3550
3551 union mlx5_ifc_hca_cap_union_bits capability;
3552};
3553
26a81453
MG		 3554enum {
3555 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3556 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3557 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3558 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3559};
3560
e281682b
SM		 3561struct mlx5_ifc_set_fte_out_bits {
3562 u8 status[0x8];
b4ff3a36 3563 u8 reserved_at_8[0x18];
e281682b
SM		 3564
3565 u8 syndrome[0x20];
3566
b4ff3a36 3567 u8 reserved_at_40[0x40];
e281682b
SM		 3568};
3569
3570struct mlx5_ifc_set_fte_in_bits {
3571 u8 opcode[0x10];
b4ff3a36 3572 u8 reserved_at_10[0x10];
e281682b 3573
b4ff3a36 3574 u8 reserved_at_20[0x10];
e281682b
SM		 3575 u8 op_mod[0x10];
3576
7d5e1423
SM		 3577 u8 other_vport[0x1];
3578 u8 reserved_at_41[0xf];
3579 u8 vport_number[0x10];
3580
3581 u8 reserved_at_60[0x20];
e281682b
SM		 3582
3583 u8 table_type[0x8];
b4ff3a36 3584 u8 reserved_at_88[0x18];
e281682b 3585
b4ff3a36 3586 u8 reserved_at_a0[0x8];
e281682b
SM		 3587 u8 table_id[0x18];
3588
b4ff3a36 3589 u8 reserved_at_c0[0x18];
26a81453
MG		 3590 u8 modify_enable_mask[0x8];
3591
b4ff3a36 3592 u8 reserved_at_e0[0x20];
e281682b
SM		 3593
3594 u8 flow_index[0x20];
3595
b4ff3a36 3596 u8 reserved_at_120[0xe0];
e281682b
SM		 3597
3598 struct mlx5_ifc_flow_context_bits flow_context;
3599};
3600
3601struct mlx5_ifc_rts2rts_qp_out_bits {
3602 u8 status[0x8];
b4ff3a36 3603 u8 reserved_at_8[0x18];
e281682b
SM		 3604
3605 u8 syndrome[0x20];
3606
b4ff3a36 3607 u8 reserved_at_40[0x40];
e281682b
SM		 3608};
3609
3610struct mlx5_ifc_rts2rts_qp_in_bits {
3611 u8 opcode[0x10];
b4ff3a36 3612 u8 reserved_at_10[0x10];
e281682b 3613
b4ff3a36 3614 u8 reserved_at_20[0x10];
e281682b
SM		 3615 u8 op_mod[0x10];
3616
b4ff3a36 3617 u8 reserved_at_40[0x8];
e281682b
SM		 3618 u8 qpn[0x18];
3619
b4ff3a36 3620 u8 reserved_at_60[0x20];
e281682b
SM		 3621
3622 u8 opt_param_mask[0x20];
3623
b4ff3a36 3624 u8 reserved_at_a0[0x20];
e281682b
SM		 3625
3626 struct mlx5_ifc_qpc_bits qpc;
3627
b4ff3a36 3628 u8 reserved_at_800[0x80];
e281682b
SM		 3629};
3630
3631struct mlx5_ifc_rtr2rts_qp_out_bits {
3632 u8 status[0x8];
b4ff3a36 3633 u8 reserved_at_8[0x18];
e281682b
SM		 3634
3635 u8 syndrome[0x20];
3636
b4ff3a36 3637 u8 reserved_at_40[0x40];
e281682b
SM		 3638};
3639
3640struct mlx5_ifc_rtr2rts_qp_in_bits {
3641 u8 opcode[0x10];
b4ff3a36 3642 u8 reserved_at_10[0x10];
e281682b 3643
b4ff3a36 3644 u8 reserved_at_20[0x10];
e281682b
SM		 3645 u8 op_mod[0x10];
3646
b4ff3a36 3647 u8 reserved_at_40[0x8];
e281682b
SM		 3648 u8 qpn[0x18];
3649
b4ff3a36 3650 u8 reserved_at_60[0x20];
e281682b
SM		 3651
3652 u8 opt_param_mask[0x20];
3653
b4ff3a36 3654 u8 reserved_at_a0[0x20];
e281682b
SM		 3655
3656 struct mlx5_ifc_qpc_bits qpc;
3657
b4ff3a36 3658 u8 reserved_at_800[0x80];
e281682b
SM		 3659};
3660
3661struct mlx5_ifc_rst2init_qp_out_bits {
3662 u8 status[0x8];
b4ff3a36 3663 u8 reserved_at_8[0x18];
e281682b
SM		 3664
3665 u8 syndrome[0x20];
3666
b4ff3a36 3667 u8 reserved_at_40[0x40];
e281682b
SM		 3668};
3669
3670struct mlx5_ifc_rst2init_qp_in_bits {
3671 u8 opcode[0x10];
b4ff3a36 3672 u8 reserved_at_10[0x10];
e281682b 3673
b4ff3a36 3674 u8 reserved_at_20[0x10];
e281682b
SM		 3675 u8 op_mod[0x10];
3676
b4ff3a36 3677 u8 reserved_at_40[0x8];
e281682b
SM		 3678 u8 qpn[0x18];
3679
b4ff3a36 3680 u8 reserved_at_60[0x20];
e281682b
SM		 3681
3682 u8 opt_param_mask[0x20];
3683
b4ff3a36 3684 u8 reserved_at_a0[0x20];
e281682b
SM		 3685
3686 struct mlx5_ifc_qpc_bits qpc;
3687
b4ff3a36 3688 u8 reserved_at_800[0x80];
e281682b
SM		 3689};
3690
7486216b
SM		 3691struct mlx5_ifc_query_xrq_out_bits {
3692 u8 status[0x8];
3693 u8 reserved_at_8[0x18];
3694
3695 u8 syndrome[0x20];
3696
3697 u8 reserved_at_40[0x40];
3698
3699 struct mlx5_ifc_xrqc_bits xrq_context;
3700};
3701
3702struct mlx5_ifc_query_xrq_in_bits {
3703 u8 opcode[0x10];
3704 u8 reserved_at_10[0x10];
3705
3706 u8 reserved_at_20[0x10];
3707 u8 op_mod[0x10];
3708
3709 u8 reserved_at_40[0x8];
3710 u8 xrqn[0x18];
3711
3712 u8 reserved_at_60[0x20];
3713};
3714
e281682b
SM		 3715struct mlx5_ifc_query_xrc_srq_out_bits {
3716 u8 status[0x8];
b4ff3a36 3717 u8 reserved_at_8[0x18];
e281682b
SM		 3718
3719 u8 syndrome[0x20];
3720
b4ff3a36 3721 u8 reserved_at_40[0x40];
e281682b
SM		 3722
3723 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3724
b4ff3a36 3725 u8 reserved_at_280[0x600];
e281682b
SM		 3726
3727 u8 pas[0][0x40];
3728};
3729
3730struct mlx5_ifc_query_xrc_srq_in_bits {
3731 u8 opcode[0x10];
b4ff3a36 3732 u8 reserved_at_10[0x10];
e281682b 3733
b4ff3a36 3734 u8 reserved_at_20[0x10];
e281682b
SM		 3735 u8 op_mod[0x10];
3736
b4ff3a36 3737 u8 reserved_at_40[0x8];
e281682b
SM		 3738 u8 xrc_srqn[0x18];
3739
b4ff3a36 3740 u8 reserved_at_60[0x20];
e281682b
SM		 3741};
3742
3743enum {
3744 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3745 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3746};
3747
3748struct mlx5_ifc_query_vport_state_out_bits {
3749 u8 status[0x8];
b4ff3a36 3750 u8 reserved_at_8[0x18];
e281682b
SM		 3751
3752 u8 syndrome[0x20];
3753
b4ff3a36 3754 u8 reserved_at_40[0x20];
e281682b 3755
b4ff3a36 3756 u8 reserved_at_60[0x18];
e281682b
SM		 3757 u8 admin_state[0x4];
3758 u8 state[0x4];
3759};
3760
3761enum {
3762 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3763 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3764};
3765
3766struct mlx5_ifc_query_vport_state_in_bits {
3767 u8 opcode[0x10];
b4ff3a36 3768 u8 reserved_at_10[0x10];
e281682b 3769
b4ff3a36 3770 u8 reserved_at_20[0x10];
e281682b
SM		 3771 u8 op_mod[0x10];
3772
3773 u8 other_vport[0x1];
b4ff3a36 3774 u8 reserved_at_41[0xf];
e281682b
SM		 3775 u8 vport_number[0x10];
3776
b4ff3a36 3777 u8 reserved_at_60[0x20];
e281682b
SM		 3778};
3779
61c5b5c9
MS		 3780struct mlx5_ifc_query_vnic_env_out_bits {
3781 u8 status[0x8];
3782 u8 reserved_at_8[0x18];
3783
3784 u8 syndrome[0x20];
3785
3786 u8 reserved_at_40[0x40];
3787
3788 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3789};
3790
3791enum {
3792 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3793};
3794
3795struct mlx5_ifc_query_vnic_env_in_bits {
3796 u8 opcode[0x10];
3797 u8 reserved_at_10[0x10];
3798
3799 u8 reserved_at_20[0x10];
3800 u8 op_mod[0x10];
3801
3802 u8 other_vport[0x1];
3803 u8 reserved_at_41[0xf];
3804 u8 vport_number[0x10];
3805
3806 u8 reserved_at_60[0x20];
3807};
3808
e281682b
SM		 3809struct mlx5_ifc_query_vport_counter_out_bits {
3810 u8 status[0x8];
b4ff3a36 3811 u8 reserved_at_8[0x18];
e281682b
SM		 3812
3813 u8 syndrome[0x20];
3814
b4ff3a36 3815 u8 reserved_at_40[0x40];
e281682b
SM		 3816
3817 struct mlx5_ifc_traffic_counter_bits received_errors;
3818
3819 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3820
3821 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3822
3823 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3824
3825 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3826
3827 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3828
3829 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3830
3831 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3832
3833 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3834
3835 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3836
3837 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3838
3839 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3840
b4ff3a36 3841 u8 reserved_at_680[0xa00];
e281682b
SM		 3842};
3843
3844enum {
3845 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3846};
3847
3848struct mlx5_ifc_query_vport_counter_in_bits {
3849 u8 opcode[0x10];
b4ff3a36 3850 u8 reserved_at_10[0x10];
e281682b 3851
b4ff3a36 3852 u8 reserved_at_20[0x10];
e281682b
SM		 3853 u8 op_mod[0x10];
3854
3855 u8 other_vport[0x1];
b54ba277
MY		 3856 u8 reserved_at_41[0xb];
3857 u8 port_num[0x4];
e281682b
SM		 3858 u8 vport_number[0x10];
3859
b4ff3a36 3860 u8 reserved_at_60[0x60];
e281682b
SM		 3861
3862 u8 clear[0x1];
b4ff3a36 3863 u8 reserved_at_c1[0x1f];
e281682b 3864
b4ff3a36 3865 u8 reserved_at_e0[0x20];
e281682b
SM		 3866};
3867
3868struct mlx5_ifc_query_tis_out_bits {
3869 u8 status[0x8];
b4ff3a36 3870 u8 reserved_at_8[0x18];
e281682b
SM		 3871
3872 u8 syndrome[0x20];
3873
b4ff3a36 3874 u8 reserved_at_40[0x40];
e281682b
SM		 3875
3876 struct mlx5_ifc_tisc_bits tis_context;
3877};
3878
3879struct mlx5_ifc_query_tis_in_bits {
3880 u8 opcode[0x10];
b4ff3a36 3881 u8 reserved_at_10[0x10];
e281682b 3882
b4ff3a36 3883 u8 reserved_at_20[0x10];
e281682b
SM		 3884 u8 op_mod[0x10];
3885
b4ff3a36 3886 u8 reserved_at_40[0x8];
e281682b
SM		 3887 u8 tisn[0x18];
3888
b4ff3a36 3889 u8 reserved_at_60[0x20];
e281682b
SM		 3890};
3891
3892struct mlx5_ifc_query_tir_out_bits {
3893 u8 status[0x8];
b4ff3a36 3894 u8 reserved_at_8[0x18];
e281682b
SM		 3895
3896 u8 syndrome[0x20];
3897
b4ff3a36 3898 u8 reserved_at_40[0xc0];
e281682b
SM		 3899
3900 struct mlx5_ifc_tirc_bits tir_context;
3901};
3902
3903struct mlx5_ifc_query_tir_in_bits {
3904 u8 opcode[0x10];
b4ff3a36 3905 u8 reserved_at_10[0x10];
e281682b 3906
b4ff3a36 3907 u8 reserved_at_20[0x10];
e281682b
SM		 3908 u8 op_mod[0x10];
3909
b4ff3a36 3910 u8 reserved_at_40[0x8];
e281682b
SM		 3911 u8 tirn[0x18];
3912
b4ff3a36 3913 u8 reserved_at_60[0x20];
e281682b
SM		 3914};
3915
3916struct mlx5_ifc_query_srq_out_bits {
3917 u8 status[0x8];
b4ff3a36 3918 u8 reserved_at_8[0x18];
e281682b
SM		 3919
3920 u8 syndrome[0x20];
3921
b4ff3a36 3922 u8 reserved_at_40[0x40];
e281682b
SM		 3923
3924 struct mlx5_ifc_srqc_bits srq_context_entry;
3925
b4ff3a36 3926 u8 reserved_at_280[0x600];
e281682b
SM		 3927
3928 u8 pas[0][0x40];
3929};
3930
3931struct mlx5_ifc_query_srq_in_bits {
3932 u8 opcode[0x10];
b4ff3a36 3933 u8 reserved_at_10[0x10];
e281682b 3934
b4ff3a36 3935 u8 reserved_at_20[0x10];
e281682b
SM		 3936 u8 op_mod[0x10];
3937
b4ff3a36 3938 u8 reserved_at_40[0x8];
e281682b
SM		 3939 u8 srqn[0x18];
3940
b4ff3a36 3941 u8 reserved_at_60[0x20];
e281682b
SM		 3942};
3943
3944struct mlx5_ifc_query_sq_out_bits {
3945 u8 status[0x8];
b4ff3a36 3946 u8 reserved_at_8[0x18];
e281682b
SM		 3947
3948 u8 syndrome[0x20];
3949
b4ff3a36 3950 u8 reserved_at_40[0xc0];
e281682b
SM		 3951
3952 struct mlx5_ifc_sqc_bits sq_context;
3953};
3954
3955struct mlx5_ifc_query_sq_in_bits {
3956 u8 opcode[0x10];
b4ff3a36 3957 u8 reserved_at_10[0x10];
e281682b 3958
b4ff3a36 3959 u8 reserved_at_20[0x10];
e281682b
SM		 3960 u8 op_mod[0x10];
3961
b4ff3a36 3962 u8 reserved_at_40[0x8];
e281682b
SM		 3963 u8 sqn[0x18];
3964
b4ff3a36 3965 u8 reserved_at_60[0x20];
e281682b
SM		 3966};
3967
3968struct mlx5_ifc_query_special_contexts_out_bits {
3969 u8 status[0x8];
b4ff3a36 3970 u8 reserved_at_8[0x18];
e281682b
SM		 3971
3972 u8 syndrome[0x20];
3973
ec22eb53 3974 u8 dump_fill_mkey[0x20];
e281682b
SM		 3975
3976 u8 resd_lkey[0x20];
bcda1aca
AK		 3977
3978 u8 null_mkey[0x20];
3979
3980 u8 reserved_at_a0[0x60];
e281682b
SM		 3981};
3982
3983struct mlx5_ifc_query_special_contexts_in_bits {
3984 u8 opcode[0x10];
b4ff3a36 3985 u8 reserved_at_10[0x10];
e281682b 3986
b4ff3a36 3987 u8 reserved_at_20[0x10];
e281682b
SM		 3988 u8 op_mod[0x10];
3989
b4ff3a36 3990 u8 reserved_at_40[0x40];
e281682b
SM		 3991};
3992
813f8540
MHY		 3993struct mlx5_ifc_query_scheduling_element_out_bits {
3994 u8 opcode[0x10];
3995 u8 reserved_at_10[0x10];
3996
3997 u8 reserved_at_20[0x10];
3998 u8 op_mod[0x10];
3999
4000 u8 reserved_at_40[0xc0];
4001
4002 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4003
4004 u8 reserved_at_300[0x100];
4005};
4006
4007enum {
4008 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4009};
4010
4011struct mlx5_ifc_query_scheduling_element_in_bits {
4012 u8 opcode[0x10];
4013 u8 reserved_at_10[0x10];
4014
4015 u8 reserved_at_20[0x10];
4016 u8 op_mod[0x10];
4017
4018 u8 scheduling_hierarchy[0x8];
4019 u8 reserved_at_48[0x18];
4020
4021 u8 scheduling_element_id[0x20];
4022
4023 u8 reserved_at_80[0x180];
4024};
4025
e281682b
SM		 4026struct mlx5_ifc_query_rqt_out_bits {
4027 u8 status[0x8];
b4ff3a36 4028 u8 reserved_at_8[0x18];
e281682b
SM		 4029
4030 u8 syndrome[0x20];
4031
b4ff3a36 4032 u8 reserved_at_40[0xc0];
e281682b
SM		 4033
4034 struct mlx5_ifc_rqtc_bits rqt_context;
4035};
4036
4037struct mlx5_ifc_query_rqt_in_bits {
4038 u8 opcode[0x10];
b4ff3a36 4039 u8 reserved_at_10[0x10];
e281682b 4040
b4ff3a36 4041 u8 reserved_at_20[0x10];
e281682b
SM		 4042 u8 op_mod[0x10];
4043
b4ff3a36 4044 u8 reserved_at_40[0x8];
e281682b
SM		 4045 u8 rqtn[0x18];
4046
b4ff3a36 4047 u8 reserved_at_60[0x20];
e281682b
SM		 4048};
4049
4050struct mlx5_ifc_query_rq_out_bits {
4051 u8 status[0x8];
b4ff3a36 4052 u8 reserved_at_8[0x18];
e281682b
SM		 4053
4054 u8 syndrome[0x20];
4055
b4ff3a36 4056 u8 reserved_at_40[0xc0];
e281682b
SM		 4057
4058 struct mlx5_ifc_rqc_bits rq_context;
4059};
4060
4061struct mlx5_ifc_query_rq_in_bits {
4062 u8 opcode[0x10];
b4ff3a36 4063 u8 reserved_at_10[0x10];
e281682b 4064
b4ff3a36 4065 u8 reserved_at_20[0x10];
e281682b
SM		 4066 u8 op_mod[0x10];
4067
b4ff3a36 4068 u8 reserved_at_40[0x8];
e281682b
SM		 4069 u8 rqn[0x18];
4070
b4ff3a36 4071 u8 reserved_at_60[0x20];
e281682b
SM		 4072};
4073
4074struct mlx5_ifc_query_roce_address_out_bits {
4075 u8 status[0x8];
b4ff3a36 4076 u8 reserved_at_8[0x18];
e281682b
SM		 4077
4078 u8 syndrome[0x20];
4079
b4ff3a36 4080 u8 reserved_at_40[0x40];
e281682b
SM		 4081
4082 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4083};
4084
4085struct mlx5_ifc_query_roce_address_in_bits {
4086 u8 opcode[0x10];
b4ff3a36 4087 u8 reserved_at_10[0x10];
e281682b 4088
b4ff3a36 4089 u8 reserved_at_20[0x10];
e281682b
SM		 4090 u8 op_mod[0x10];
4091
4092 u8 roce_address_index[0x10];
32f69e4b
DJ		 4093 u8 reserved_at_50[0xc];
4094 u8 vhca_port_num[0x4];
e281682b 4095
b4ff3a36 4096 u8 reserved_at_60[0x20];
e281682b
SM		 4097};
4098
4099struct mlx5_ifc_query_rmp_out_bits {
4100 u8 status[0x8];
b4ff3a36 4101 u8 reserved_at_8[0x18];
e281682b
SM		 4102
4103 u8 syndrome[0x20];
4104
b4ff3a36 4105 u8 reserved_at_40[0xc0];
e281682b
SM		 4106
4107 struct mlx5_ifc_rmpc_bits rmp_context;
4108};
4109
4110struct mlx5_ifc_query_rmp_in_bits {
4111 u8 opcode[0x10];
b4ff3a36 4112 u8 reserved_at_10[0x10];
e281682b 4113
b4ff3a36 4114 u8 reserved_at_20[0x10];
e281682b
SM		 4115 u8 op_mod[0x10];
4116
b4ff3a36 4117 u8 reserved_at_40[0x8];
e281682b
SM		 4118 u8 rmpn[0x18];
4119
b4ff3a36 4120 u8 reserved_at_60[0x20];
e281682b
SM		 4121};
4122
4123struct mlx5_ifc_query_qp_out_bits {
4124 u8 status[0x8];
b4ff3a36 4125 u8 reserved_at_8[0x18];
e281682b
SM		 4126
4127 u8 syndrome[0x20];
4128
b4ff3a36 4129 u8 reserved_at_40[0x40];
e281682b
SM		 4130
4131 u8 opt_param_mask[0x20];
4132
b4ff3a36 4133 u8 reserved_at_a0[0x20];
e281682b
SM		 4134
4135 struct mlx5_ifc_qpc_bits qpc;
4136
b4ff3a36 4137 u8 reserved_at_800[0x80];
e281682b
SM		 4138
4139 u8 pas[0][0x40];
4140};
4141
4142struct mlx5_ifc_query_qp_in_bits {
4143 u8 opcode[0x10];
b4ff3a36 4144 u8 reserved_at_10[0x10];
e281682b 4145
b4ff3a36 4146 u8 reserved_at_20[0x10];
e281682b
SM		 4147 u8 op_mod[0x10];
4148
b4ff3a36 4149 u8 reserved_at_40[0x8];
e281682b
SM		 4150 u8 qpn[0x18];
4151
b4ff3a36 4152 u8 reserved_at_60[0x20];
e281682b
SM		 4153};
4154
4155struct mlx5_ifc_query_q_counter_out_bits {
4156 u8 status[0x8];
b4ff3a36 4157 u8 reserved_at_8[0x18];
e281682b
SM		 4158
4159 u8 syndrome[0x20];
4160
b4ff3a36 4161 u8 reserved_at_40[0x40];
e281682b
SM		 4162
4163 u8 rx_write_requests[0x20];
4164
b4ff3a36 4165 u8 reserved_at_a0[0x20];
e281682b
SM		 4166
4167 u8 rx_read_requests[0x20];
4168
b4ff3a36 4169 u8 reserved_at_e0[0x20];
e281682b
SM		 4170
4171 u8 rx_atomic_requests[0x20];
4172
b4ff3a36 4173 u8 reserved_at_120[0x20];
e281682b
SM		 4174
4175 u8 rx_dct_connect[0x20];
4176
b4ff3a36 4177 u8 reserved_at_160[0x20];
e281682b
SM		 4178
4179 u8 out_of_buffer[0x20];
4180
b4ff3a36 4181 u8 reserved_at_1a0[0x20];
e281682b
SM		 4182
4183 u8 out_of_sequence[0x20];
4184
7486216b
SM		 4185 u8 reserved_at_1e0[0x20];
4186
4187 u8 duplicate_request[0x20];
4188
4189 u8 reserved_at_220[0x20];
4190
4191 u8 rnr_nak_retry_err[0x20];
4192
4193 u8 reserved_at_260[0x20];
4194
4195 u8 packet_seq_err[0x20];
4196
4197 u8 reserved_at_2a0[0x20];
4198
4199 u8 implied_nak_seq_err[0x20];
4200
4201 u8 reserved_at_2e0[0x20];
4202
4203 u8 local_ack_timeout_err[0x20];
4204
58dcb60a
PP		 4205 u8 reserved_at_320[0xa0];
4206
4207 u8 resp_local_length_error[0x20];
4208
4209 u8 req_local_length_error[0x20];
4210
4211 u8 resp_local_qp_error[0x20];
4212
4213 u8 local_operation_error[0x20];
4214
4215 u8 resp_local_protection[0x20];
4216
4217 u8 req_local_protection[0x20];
4218
4219 u8 resp_cqe_error[0x20];
4220
4221 u8 req_cqe_error[0x20];
4222
4223 u8 req_mw_binding[0x20];
4224
4225 u8 req_bad_response[0x20];
4226
4227 u8 req_remote_invalid_request[0x20];
4228
4229 u8 resp_remote_invalid_request[0x20];
4230
4231 u8 req_remote_access_errors[0x20];
4232
4233 u8 resp_remote_access_errors[0x20];
4234
4235 u8 req_remote_operation_errors[0x20];
4236
4237 u8 req_transport_retries_exceeded[0x20];
4238
4239 u8 cq_overflow[0x20];
4240
4241 u8 resp_cqe_flush_error[0x20];
4242
4243 u8 req_cqe_flush_error[0x20];
4244
4245 u8 reserved_at_620[0x1e0];
e281682b
SM		 4246};
4247
4248struct mlx5_ifc_query_q_counter_in_bits {
4249 u8 opcode[0x10];
b4ff3a36 4250 u8 reserved_at_10[0x10];
e281682b 4251
b4ff3a36 4252 u8 reserved_at_20[0x10];
e281682b
SM		 4253 u8 op_mod[0x10];
4254
b4ff3a36 4255 u8 reserved_at_40[0x80];
e281682b
SM		 4256
4257 u8 clear[0x1];
b4ff3a36 4258 u8 reserved_at_c1[0x1f];
e281682b 4259
b4ff3a36 4260 u8 reserved_at_e0[0x18];
e281682b
SM		 4261 u8 counter_set_id[0x8];
4262};
4263
4264struct mlx5_ifc_query_pages_out_bits {
4265 u8 status[0x8];
b4ff3a36 4266 u8 reserved_at_8[0x18];
e281682b
SM		 4267
4268 u8 syndrome[0x20];
4269
b4ff3a36 4270 u8 reserved_at_40[0x10];
e281682b
SM		 4271 u8 function_id[0x10];
4272
4273 u8 num_pages[0x20];
4274};
4275
4276enum {
4277 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4278 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4279 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4280};
4281
4282struct mlx5_ifc_query_pages_in_bits {
4283 u8 opcode[0x10];
b4ff3a36 4284 u8 reserved_at_10[0x10];
e281682b 4285
b4ff3a36 4286 u8 reserved_at_20[0x10];
e281682b
SM		 4287 u8 op_mod[0x10];
4288
b4ff3a36 4289 u8 reserved_at_40[0x10];
e281682b
SM		 4290 u8 function_id[0x10];
4291
b4ff3a36 4292 u8 reserved_at_60[0x20];
e281682b
SM		 4293};
4294
4295struct mlx5_ifc_query_nic_vport_context_out_bits {
4296 u8 status[0x8];
b4ff3a36 4297 u8 reserved_at_8[0x18];
e281682b
SM		 4298
4299 u8 syndrome[0x20];
4300
b4ff3a36 4301 u8 reserved_at_40[0x40];
e281682b
SM		 4302
4303 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4304};
4305
4306struct mlx5_ifc_query_nic_vport_context_in_bits {
4307 u8 opcode[0x10];
b4ff3a36 4308 u8 reserved_at_10[0x10];
e281682b 4309
b4ff3a36 4310 u8 reserved_at_20[0x10];
e281682b
SM		 4311 u8 op_mod[0x10];
4312
4313 u8 other_vport[0x1];
b4ff3a36 4314 u8 reserved_at_41[0xf];
e281682b
SM		 4315 u8 vport_number[0x10];
4316
b4ff3a36 4317 u8 reserved_at_60[0x5];
e281682b 4318 u8 allowed_list_type[0x3];
b4ff3a36 4319 u8 reserved_at_68[0x18];
e281682b
SM		 4320};
4321
4322struct mlx5_ifc_query_mkey_out_bits {
4323 u8 status[0x8];
b4ff3a36 4324 u8 reserved_at_8[0x18];
e281682b
SM		 4325
4326 u8 syndrome[0x20];
4327
b4ff3a36 4328 u8 reserved_at_40[0x40];
e281682b
SM		 4329
4330 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4331
b4ff3a36 4332 u8 reserved_at_280[0x600];
e281682b
SM		 4333
4334 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4335
4336 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4337};
4338
4339struct mlx5_ifc_query_mkey_in_bits {
4340 u8 opcode[0x10];
b4ff3a36 4341 u8 reserved_at_10[0x10];
e281682b 4342
b4ff3a36 4343 u8 reserved_at_20[0x10];
e281682b
SM		 4344 u8 op_mod[0x10];
4345
b4ff3a36 4346 u8 reserved_at_40[0x8];
e281682b
SM		 4347 u8 mkey_index[0x18];
4348
4349 u8 pg_access[0x1];
b4ff3a36 4350 u8 reserved_at_61[0x1f];
e281682b
SM		 4351};
4352
4353struct mlx5_ifc_query_mad_demux_out_bits {
4354 u8 status[0x8];
b4ff3a36 4355 u8 reserved_at_8[0x18];
e281682b
SM		 4356
4357 u8 syndrome[0x20];
4358
b4ff3a36 4359 u8 reserved_at_40[0x40];
e281682b
SM		 4360
4361 u8 mad_dumux_parameters_block[0x20];
4362};
4363
4364struct mlx5_ifc_query_mad_demux_in_bits {
4365 u8 opcode[0x10];
b4ff3a36 4366 u8 reserved_at_10[0x10];
e281682b 4367
b4ff3a36 4368 u8 reserved_at_20[0x10];
e281682b
SM		 4369 u8 op_mod[0x10];
4370
b4ff3a36 4371 u8 reserved_at_40[0x40];
e281682b
SM		 4372};
4373
4374struct mlx5_ifc_query_l2_table_entry_out_bits {
4375 u8 status[0x8];
b4ff3a36 4376 u8 reserved_at_8[0x18];
e281682b
SM		 4377
4378 u8 syndrome[0x20];
4379
b4ff3a36 4380 u8 reserved_at_40[0xa0];
e281682b 4381
b4ff3a36 4382 u8 reserved_at_e0[0x13];
e281682b
SM		 4383 u8 vlan_valid[0x1];
4384 u8 vlan[0xc];
4385
4386 struct mlx5_ifc_mac_address_layout_bits mac_address;
4387
b4ff3a36 4388 u8 reserved_at_140[0xc0];
e281682b
SM		 4389};
4390
4391struct mlx5_ifc_query_l2_table_entry_in_bits {
4392 u8 opcode[0x10];
b4ff3a36 4393 u8 reserved_at_10[0x10];
e281682b 4394
b4ff3a36 4395 u8 reserved_at_20[0x10];
e281682b
SM		 4396 u8 op_mod[0x10];
4397
b4ff3a36 4398 u8 reserved_at_40[0x60];
e281682b 4399
b4ff3a36 4400 u8 reserved_at_a0[0x8];
e281682b
SM		 4401 u8 table_index[0x18];
4402
b4ff3a36 4403 u8 reserved_at_c0[0x140];
e281682b
SM		 4404};
4405
4406struct mlx5_ifc_query_issi_out_bits {
4407 u8 status[0x8];
b4ff3a36 4408 u8 reserved_at_8[0x18];
e281682b
SM		 4409
4410 u8 syndrome[0x20];
4411
b4ff3a36 4412 u8 reserved_at_40[0x10];
e281682b
SM		 4413 u8 current_issi[0x10];
4414
b4ff3a36 4415 u8 reserved_at_60[0xa0];
e281682b 4416
b4ff3a36 4417 u8 reserved_at_100[76][0x8];
e281682b
SM		 4418 u8 supported_issi_dw0[0x20];
4419};
4420
4421struct mlx5_ifc_query_issi_in_bits {
4422 u8 opcode[0x10];
b4ff3a36 4423 u8 reserved_at_10[0x10];
e281682b 4424
b4ff3a36 4425 u8 reserved_at_20[0x10];
e281682b
SM		 4426 u8 op_mod[0x10];
4427
b4ff3a36 4428 u8 reserved_at_40[0x40];
e281682b
SM		 4429};
4430
0dbc6fe0
SM		 4431struct mlx5_ifc_set_driver_version_out_bits {
4432 u8 status[0x8];
4433 u8 reserved_0[0x18];
4434
4435 u8 syndrome[0x20];
4436 u8 reserved_1[0x40];
4437};
4438
4439struct mlx5_ifc_set_driver_version_in_bits {
4440 u8 opcode[0x10];
4441 u8 reserved_0[0x10];
4442
4443 u8 reserved_1[0x10];
4444 u8 op_mod[0x10];
4445
4446 u8 reserved_2[0x40];
4447 u8 driver_version[64][0x8];
4448};
4449
e281682b
SM		 4450struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4451 u8 status[0x8];
b4ff3a36 4452 u8 reserved_at_8[0x18];
e281682b
SM		 4453
4454 u8 syndrome[0x20];
4455
b4ff3a36 4456 u8 reserved_at_40[0x40];
e281682b
SM		 4457
4458 struct mlx5_ifc_pkey_bits pkey[0];
4459};
4460
4461struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4462 u8 opcode[0x10];
b4ff3a36 4463 u8 reserved_at_10[0x10];
e281682b 4464
b4ff3a36 4465 u8 reserved_at_20[0x10];
e281682b
SM		 4466 u8 op_mod[0x10];
4467
4468 u8 other_vport[0x1];
b4ff3a36 4469 u8 reserved_at_41[0xb];
707c4602 4470 u8 port_num[0x4];
e281682b
SM		 4471 u8 vport_number[0x10];
4472
b4ff3a36 4473 u8 reserved_at_60[0x10];
e281682b
SM		 4474 u8 pkey_index[0x10];
4475};
4476
eff901d3
EC		 4477enum {
4478 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4479 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4480 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4481};
4482
e281682b
SM		 4483struct mlx5_ifc_query_hca_vport_gid_out_bits {
4484 u8 status[0x8];
b4ff3a36 4485 u8 reserved_at_8[0x18];
e281682b
SM		 4486
4487 u8 syndrome[0x20];
4488
b4ff3a36 4489 u8 reserved_at_40[0x20];
e281682b
SM		 4490
4491 u8 gids_num[0x10];
b4ff3a36 4492 u8 reserved_at_70[0x10];
e281682b
SM		 4493
4494 struct mlx5_ifc_array128_auto_bits gid[0];
4495};
4496
4497struct mlx5_ifc_query_hca_vport_gid_in_bits {
4498 u8 opcode[0x10];
b4ff3a36 4499 u8 reserved_at_10[0x10];
e281682b 4500
b4ff3a36 4501 u8 reserved_at_20[0x10];
e281682b
SM		 4502 u8 op_mod[0x10];
4503
4504 u8 other_vport[0x1];
b4ff3a36 4505 u8 reserved_at_41[0xb];
707c4602 4506 u8 port_num[0x4];
e281682b
SM		 4507 u8 vport_number[0x10];
4508
b4ff3a36 4509 u8 reserved_at_60[0x10];
e281682b
SM		 4510 u8 gid_index[0x10];
4511};
4512
4513struct mlx5_ifc_query_hca_vport_context_out_bits {
4514 u8 status[0x8];
b4ff3a36 4515 u8 reserved_at_8[0x18];
e281682b
SM		 4516
4517 u8 syndrome[0x20];
4518
b4ff3a36 4519 u8 reserved_at_40[0x40];
e281682b
SM		 4520
4521 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4522};
4523
4524struct mlx5_ifc_query_hca_vport_context_in_bits {
4525 u8 opcode[0x10];
b4ff3a36 4526 u8 reserved_at_10[0x10];
e281682b 4527
b4ff3a36 4528 u8 reserved_at_20[0x10];
e281682b
SM		 4529 u8 op_mod[0x10];
4530
4531 u8 other_vport[0x1];
b4ff3a36 4532 u8 reserved_at_41[0xb];
707c4602 4533 u8 port_num[0x4];
e281682b
SM		 4534 u8 vport_number[0x10];
4535
b4ff3a36 4536 u8 reserved_at_60[0x20];
e281682b
SM		 4537};
4538
4539struct mlx5_ifc_query_hca_cap_out_bits {
4540 u8 status[0x8];
b4ff3a36 4541 u8 reserved_at_8[0x18];
e281682b
SM		 4542
4543 u8 syndrome[0x20];
4544
b4ff3a36 4545 u8 reserved_at_40[0x40];
e281682b
SM		 4546
4547 union mlx5_ifc_hca_cap_union_bits capability;
4548};
4549
4550struct mlx5_ifc_query_hca_cap_in_bits {
4551 u8 opcode[0x10];
b4ff3a36 4552 u8 reserved_at_10[0x10];
e281682b 4553
b4ff3a36 4554 u8 reserved_at_20[0x10];
e281682b
SM		 4555 u8 op_mod[0x10];
4556
b4ff3a36 4557 u8 reserved_at_40[0x40];
e281682b
SM		 4558};
4559
4560struct mlx5_ifc_query_flow_table_out_bits {
4561 u8 status[0x8];
b4ff3a36 4562 u8 reserved_at_8[0x18];
e281682b
SM		 4563
4564 u8 syndrome[0x20];
4565
b4ff3a36 4566 u8 reserved_at_40[0x80];
e281682b 4567
b4ff3a36 4568 u8 reserved_at_c0[0x8];
e281682b 4569 u8 level[0x8];
b4ff3a36 4570 u8 reserved_at_d0[0x8];
e281682b
SM		 4571 u8 log_size[0x8];
4572
b4ff3a36 4573 u8 reserved_at_e0[0x120];
e281682b
SM		 4574};
4575
4576struct mlx5_ifc_query_flow_table_in_bits {
4577 u8 opcode[0x10];
b4ff3a36 4578 u8 reserved_at_10[0x10];
e281682b 4579
b4ff3a36 4580 u8 reserved_at_20[0x10];
e281682b
SM		 4581 u8 op_mod[0x10];
4582
b4ff3a36 4583 u8 reserved_at_40[0x40];
e281682b
SM		 4584
4585 u8 table_type[0x8];
b4ff3a36 4586 u8 reserved_at_88[0x18];
e281682b 4587
b4ff3a36 4588 u8 reserved_at_a0[0x8];
e281682b
SM		 4589 u8 table_id[0x18];
4590
b4ff3a36 4591 u8 reserved_at_c0[0x140];
e281682b
SM		 4592};
4593
4594struct mlx5_ifc_query_fte_out_bits {
4595 u8 status[0x8];
b4ff3a36 4596 u8 reserved_at_8[0x18];
e281682b
SM		 4597
4598 u8 syndrome[0x20];
4599
b4ff3a36 4600 u8 reserved_at_40[0x1c0];
e281682b
SM		 4601
4602 struct mlx5_ifc_flow_context_bits flow_context;
4603};
4604
4605struct mlx5_ifc_query_fte_in_bits {
4606 u8 opcode[0x10];
b4ff3a36 4607 u8 reserved_at_10[0x10];
e281682b 4608
b4ff3a36 4609 u8 reserved_at_20[0x10];
e281682b
SM		 4610 u8 op_mod[0x10];
4611
b4ff3a36 4612 u8 reserved_at_40[0x40];
e281682b
SM		 4613
4614 u8 table_type[0x8];
b4ff3a36 4615 u8 reserved_at_88[0x18];
e281682b 4616
b4ff3a36 4617 u8 reserved_at_a0[0x8];
e281682b
SM		 4618 u8 table_id[0x18];
4619
b4ff3a36 4620 u8 reserved_at_c0[0x40];
e281682b
SM		 4621
4622 u8 flow_index[0x20];
4623
b4ff3a36 4624 u8 reserved_at_120[0xe0];
e281682b
SM		 4625};
4626
4627enum {
4628 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4629 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4630 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
71c6e863 4631 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
e281682b
SM		 4632};
4633
4634struct mlx5_ifc_query_flow_group_out_bits {
4635 u8 status[0x8];
b4ff3a36 4636 u8 reserved_at_8[0x18];
e281682b
SM		 4637
4638 u8 syndrome[0x20];
4639
b4ff3a36 4640 u8 reserved_at_40[0xa0];
e281682b
SM		 4641
4642 u8 start_flow_index[0x20];
4643
b4ff3a36 4644 u8 reserved_at_100[0x20];
e281682b
SM		 4645
4646 u8 end_flow_index[0x20];
4647
b4ff3a36 4648 u8 reserved_at_140[0xa0];
e281682b 4649
b4ff3a36 4650 u8 reserved_at_1e0[0x18];
e281682b
SM		 4651 u8 match_criteria_enable[0x8];
4652
4653 struct mlx5_ifc_fte_match_param_bits match_criteria;
4654
b4ff3a36 4655 u8 reserved_at_1200[0xe00];
e281682b
SM		 4656};
4657
4658struct mlx5_ifc_query_flow_group_in_bits {
4659 u8 opcode[0x10];
b4ff3a36 4660 u8 reserved_at_10[0x10];
e281682b 4661
b4ff3a36 4662 u8 reserved_at_20[0x10];
e281682b
SM		 4663 u8 op_mod[0x10];
4664
b4ff3a36 4665 u8 reserved_at_40[0x40];
e281682b
SM		 4666
4667 u8 table_type[0x8];
b4ff3a36 4668 u8 reserved_at_88[0x18];
e281682b 4669
b4ff3a36 4670 u8 reserved_at_a0[0x8];
e281682b
SM		 4671 u8 table_id[0x18];
4672
4673 u8 group_id[0x20];
4674
b4ff3a36 4675 u8 reserved_at_e0[0x120];
e281682b
SM		 4676};
4677
9dc0b289
AV		 4678struct mlx5_ifc_query_flow_counter_out_bits {
4679 u8 status[0x8];
4680 u8 reserved_at_8[0x18];
4681
4682 u8 syndrome[0x20];
4683
4684 u8 reserved_at_40[0x40];
4685
4686 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4687};
4688
4689struct mlx5_ifc_query_flow_counter_in_bits {
4690 u8 opcode[0x10];
4691 u8 reserved_at_10[0x10];
4692
4693 u8 reserved_at_20[0x10];
4694 u8 op_mod[0x10];
4695
4696 u8 reserved_at_40[0x80];
4697
4698 u8 clear[0x1];
4699 u8 reserved_at_c1[0xf];
4700 u8 num_of_counters[0x10];
4701
a8ffcc74 4702 u8 flow_counter_id[0x20];
9dc0b289
AV		 4703};
4704
d6666753
SM		 4705struct mlx5_ifc_query_esw_vport_context_out_bits {
4706 u8 status[0x8];
b4ff3a36 4707 u8 reserved_at_8[0x18];
d6666753
SM		 4708
4709 u8 syndrome[0x20];
4710
b4ff3a36 4711 u8 reserved_at_40[0x40];
d6666753
SM		 4712
4713 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4714};
4715
4716struct mlx5_ifc_query_esw_vport_context_in_bits {
4717 u8 opcode[0x10];
b4ff3a36 4718 u8 reserved_at_10[0x10];
d6666753 4719
b4ff3a36 4720 u8 reserved_at_20[0x10];
d6666753
SM		 4721 u8 op_mod[0x10];
4722
4723 u8 other_vport[0x1];
b4ff3a36 4724 u8 reserved_at_41[0xf];
d6666753
SM		 4725 u8 vport_number[0x10];
4726
b4ff3a36 4727 u8 reserved_at_60[0x20];
d6666753
SM		 4728};
4729
4730struct mlx5_ifc_modify_esw_vport_context_out_bits {
4731 u8 status[0x8];
b4ff3a36 4732 u8 reserved_at_8[0x18];
d6666753
SM		 4733
4734 u8 syndrome[0x20];
4735
b4ff3a36 4736 u8 reserved_at_40[0x40];
d6666753
SM		 4737};
4738
4739struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4740 u8 reserved_at_0[0x1c];
d6666753
SM		 4741 u8 vport_cvlan_insert[0x1];
4742 u8 vport_svlan_insert[0x1];
4743 u8 vport_cvlan_strip[0x1];
4744 u8 vport_svlan_strip[0x1];
4745};
4746
4747struct mlx5_ifc_modify_esw_vport_context_in_bits {
4748 u8 opcode[0x10];
b4ff3a36 4749 u8 reserved_at_10[0x10];
d6666753 4750
b4ff3a36 4751 u8 reserved_at_20[0x10];
d6666753
SM		 4752 u8 op_mod[0x10];
4753
4754 u8 other_vport[0x1];
b4ff3a36 4755 u8 reserved_at_41[0xf];
d6666753
SM		 4756 u8 vport_number[0x10];
4757
4758 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4759
4760 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4761};
4762
e281682b
SM		 4763struct mlx5_ifc_query_eq_out_bits {
4764 u8 status[0x8];
b4ff3a36 4765 u8 reserved_at_8[0x18];
e281682b
SM		 4766
4767 u8 syndrome[0x20];
4768
b4ff3a36 4769 u8 reserved_at_40[0x40];
e281682b
SM		 4770
4771 struct mlx5_ifc_eqc_bits eq_context_entry;
4772
b4ff3a36 4773 u8 reserved_at_280[0x40];
e281682b
SM		 4774
4775 u8 event_bitmask[0x40];
4776
b4ff3a36 4777 u8 reserved_at_300[0x580];
e281682b
SM		 4778
4779 u8 pas[0][0x40];
4780};
4781
4782struct mlx5_ifc_query_eq_in_bits {
4783 u8 opcode[0x10];
b4ff3a36 4784 u8 reserved_at_10[0x10];
e281682b 4785
b4ff3a36 4786 u8 reserved_at_20[0x10];
e281682b
SM		 4787 u8 op_mod[0x10];
4788
b4ff3a36 4789 u8 reserved_at_40[0x18];
e281682b
SM		 4790 u8 eq_number[0x8];
4791
b4ff3a36 4792 u8 reserved_at_60[0x20];
e281682b
SM		 4793};
4794
7adbde20
HHZ		 4795struct mlx5_ifc_encap_header_in_bits {
4796 u8 reserved_at_0[0x5];
4797 u8 header_type[0x3];
4798 u8 reserved_at_8[0xe];
4799 u8 encap_header_size[0xa];
4800
4801 u8 reserved_at_20[0x10];
4802 u8 encap_header[2][0x8];
4803
4804 u8 more_encap_header[0][0x8];
4805};
4806
4807struct mlx5_ifc_query_encap_header_out_bits {
4808 u8 status[0x8];
4809 u8 reserved_at_8[0x18];
4810
4811 u8 syndrome[0x20];
4812
4813 u8 reserved_at_40[0xa0];
4814
4815 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4816};
4817
4818struct mlx5_ifc_query_encap_header_in_bits {
4819 u8 opcode[0x10];
4820 u8 reserved_at_10[0x10];
4821
4822 u8 reserved_at_20[0x10];
4823 u8 op_mod[0x10];
4824
4825 u8 encap_id[0x20];
4826
4827 u8 reserved_at_60[0xa0];
4828};
4829
4830struct mlx5_ifc_alloc_encap_header_out_bits {
4831 u8 status[0x8];
4832 u8 reserved_at_8[0x18];
4833
4834 u8 syndrome[0x20];
4835
4836 u8 encap_id[0x20];
4837
4838 u8 reserved_at_60[0x20];
4839};
4840
4841struct mlx5_ifc_alloc_encap_header_in_bits {
4842 u8 opcode[0x10];
4843 u8 reserved_at_10[0x10];
4844
4845 u8 reserved_at_20[0x10];
4846 u8 op_mod[0x10];
4847
4848 u8 reserved_at_40[0xa0];
4849
4850 struct mlx5_ifc_encap_header_in_bits encap_header;
4851};
4852
4853struct mlx5_ifc_dealloc_encap_header_out_bits {
4854 u8 status[0x8];
4855 u8 reserved_at_8[0x18];
4856
4857 u8 syndrome[0x20];
4858
4859 u8 reserved_at_40[0x40];
4860};
4861
4862struct mlx5_ifc_dealloc_encap_header_in_bits {
4863 u8 opcode[0x10];
4864 u8 reserved_at_10[0x10];
4865
4866 u8 reserved_20[0x10];
4867 u8 op_mod[0x10];
4868
4869 u8 encap_id[0x20];
4870
4871 u8 reserved_60[0x20];
4872};
4873
2a69cb9f
OG		 4874struct mlx5_ifc_set_action_in_bits {
4875 u8 action_type[0x4];
4876 u8 field[0xc];
4877 u8 reserved_at_10[0x3];
4878 u8 offset[0x5];
4879 u8 reserved_at_18[0x3];
4880 u8 length[0x5];
4881
4882 u8 data[0x20];
4883};
4884
4885struct mlx5_ifc_add_action_in_bits {
4886 u8 action_type[0x4];
4887 u8 field[0xc];
4888 u8 reserved_at_10[0x10];
4889
4890 u8 data[0x20];
4891};
4892
4893union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4894 struct mlx5_ifc_set_action_in_bits set_action_in;
4895 struct mlx5_ifc_add_action_in_bits add_action_in;
4896 u8 reserved_at_0[0x40];
4897};
4898
4899enum {
4900 MLX5_ACTION_TYPE_SET = 0x1,
4901 MLX5_ACTION_TYPE_ADD = 0x2,
4902};
4903
4904enum {
4905 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4906 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4907 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4908 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4909 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4910 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4911 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4912 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4913 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4914 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4915 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4916 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4917 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4918 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4919 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4920 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4921 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4922 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4923 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4924 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4925 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4926 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4927 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4928};
4929
4930struct mlx5_ifc_alloc_modify_header_context_out_bits {
4931 u8 status[0x8];
4932 u8 reserved_at_8[0x18];
4933
4934 u8 syndrome[0x20];
4935
4936 u8 modify_header_id[0x20];
4937
4938 u8 reserved_at_60[0x20];
4939};
4940
4941struct mlx5_ifc_alloc_modify_header_context_in_bits {
4942 u8 opcode[0x10];
4943 u8 reserved_at_10[0x10];
4944
4945 u8 reserved_at_20[0x10];
4946 u8 op_mod[0x10];
4947
4948 u8 reserved_at_40[0x20];
4949
4950 u8 table_type[0x8];
4951 u8 reserved_at_68[0x10];
4952 u8 num_of_actions[0x8];
4953
4954 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4955};
4956
4957struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4958 u8 status[0x8];
4959 u8 reserved_at_8[0x18];
4960
4961 u8 syndrome[0x20];
4962
4963 u8 reserved_at_40[0x40];
4964};
4965
4966struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4967 u8 opcode[0x10];
4968 u8 reserved_at_10[0x10];
4969
4970 u8 reserved_at_20[0x10];
4971 u8 op_mod[0x10];
4972
4973 u8 modify_header_id[0x20];
4974
4975 u8 reserved_at_60[0x20];
4976};
4977
e281682b
SM		 4978struct mlx5_ifc_query_dct_out_bits {
4979 u8 status[0x8];
b4ff3a36 4980 u8 reserved_at_8[0x18];
e281682b
SM		 4981
4982 u8 syndrome[0x20];
4983
b4ff3a36 4984 u8 reserved_at_40[0x40];
e281682b
SM		 4985
4986 struct mlx5_ifc_dctc_bits dct_context_entry;
4987
b4ff3a36 4988 u8 reserved_at_280[0x180];
e281682b
SM		 4989};
4990
4991struct mlx5_ifc_query_dct_in_bits {
4992 u8 opcode[0x10];
b4ff3a36 4993 u8 reserved_at_10[0x10];
e281682b 4994
b4ff3a36 4995 u8 reserved_at_20[0x10];
e281682b
SM		 4996 u8 op_mod[0x10];
4997
b4ff3a36 4998 u8 reserved_at_40[0x8];
e281682b
SM		 4999 u8 dctn[0x18];
5000
b4ff3a36 5001 u8 reserved_at_60[0x20];
e281682b
SM		 5002};
5003
5004struct mlx5_ifc_query_cq_out_bits {
5005 u8 status[0x8];
b4ff3a36 5006 u8 reserved_at_8[0x18];
e281682b
SM		 5007
5008 u8 syndrome[0x20];
5009
b4ff3a36 5010 u8 reserved_at_40[0x40];
e281682b
SM		 5011
5012 struct mlx5_ifc_cqc_bits cq_context;
5013
b4ff3a36 5014 u8 reserved_at_280[0x600];
e281682b
SM		 5015
5016 u8 pas[0][0x40];
5017};
5018
5019struct mlx5_ifc_query_cq_in_bits {
5020 u8 opcode[0x10];
b4ff3a36 5021 u8 reserved_at_10[0x10];
e281682b 5022
b4ff3a36 5023 u8 reserved_at_20[0x10];
e281682b
SM		 5024 u8 op_mod[0x10];
5025
b4ff3a36 5026 u8 reserved_at_40[0x8];
e281682b
SM		 5027 u8 cqn[0x18];
5028
b4ff3a36 5029 u8 reserved_at_60[0x20];
e281682b
SM		 5030};
5031
5032struct mlx5_ifc_query_cong_status_out_bits {
5033 u8 status[0x8];
b4ff3a36 5034 u8 reserved_at_8[0x18];
e281682b
SM		 5035
5036 u8 syndrome[0x20];
5037
b4ff3a36 5038 u8 reserved_at_40[0x20];
e281682b
SM		 5039
5040 u8 enable[0x1];
5041 u8 tag_enable[0x1];
b4ff3a36 5042 u8 reserved_at_62[0x1e];
e281682b
SM		 5043};
5044
5045struct mlx5_ifc_query_cong_status_in_bits {
5046 u8 opcode[0x10];
b4ff3a36 5047 u8 reserved_at_10[0x10];
e281682b 5048
b4ff3a36 5049 u8 reserved_at_20[0x10];
e281682b
SM		 5050 u8 op_mod[0x10];
5051
b4ff3a36 5052 u8 reserved_at_40[0x18];
e281682b
SM		 5053 u8 priority[0x4];
5054 u8 cong_protocol[0x4];
5055
b4ff3a36 5056 u8 reserved_at_60[0x20];
e281682b
SM		 5057};
5058
5059struct mlx5_ifc_query_cong_statistics_out_bits {
5060 u8 status[0x8];
b4ff3a36 5061 u8 reserved_at_8[0x18];
e281682b
SM		 5062
5063 u8 syndrome[0x20];
5064
b4ff3a36 5065 u8 reserved_at_40[0x40];
e281682b 5066
e1f24a79 5067 u8 rp_cur_flows[0x20];
e281682b
SM		 5068
5069 u8 sum_flows[0x20];
5070
e1f24a79 5071 u8 rp_cnp_ignored_high[0x20];
e281682b 5072
e1f24a79 5073 u8 rp_cnp_ignored_low[0x20];
e281682b 5074
e1f24a79 5075 u8 rp_cnp_handled_high[0x20];
e281682b 5076
e1f24a79 5077 u8 rp_cnp_handled_low[0x20];
e281682b 5078
b4ff3a36 5079 u8 reserved_at_140[0x100];
e281682b
SM		 5080
5081 u8 time_stamp_high[0x20];
5082
5083 u8 time_stamp_low[0x20];
5084
5085 u8 accumulators_period[0x20];
5086
e1f24a79 5087 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5088
e1f24a79 5089 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5090
e1f24a79 5091 u8 np_cnp_sent_high[0x20];
e281682b 5092
e1f24a79 5093 u8 np_cnp_sent_low[0x20];
e281682b 5094
b4ff3a36 5095 u8 reserved_at_320[0x560];
e281682b
SM		 5096};
5097
5098struct mlx5_ifc_query_cong_statistics_in_bits {
5099 u8 opcode[0x10];
b4ff3a36 5100 u8 reserved_at_10[0x10];
e281682b 5101
b4ff3a36 5102 u8 reserved_at_20[0x10];
e281682b
SM		 5103 u8 op_mod[0x10];
5104
5105 u8 clear[0x1];
b4ff3a36 5106 u8 reserved_at_41[0x1f];
e281682b 5107
b4ff3a36 5108 u8 reserved_at_60[0x20];
e281682b
SM		 5109};
5110
5111struct mlx5_ifc_query_cong_params_out_bits {
5112 u8 status[0x8];
b4ff3a36 5113 u8 reserved_at_8[0x18];
e281682b
SM		 5114
5115 u8 syndrome[0x20];
5116
b4ff3a36 5117 u8 reserved_at_40[0x40];
e281682b
SM		 5118
5119 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5120};
5121
5122struct mlx5_ifc_query_cong_params_in_bits {
5123 u8 opcode[0x10];
b4ff3a36 5124 u8 reserved_at_10[0x10];
e281682b 5125
b4ff3a36 5126 u8 reserved_at_20[0x10];
e281682b
SM		 5127 u8 op_mod[0x10];
5128
b4ff3a36 5129 u8 reserved_at_40[0x1c];
e281682b
SM		 5130 u8 cong_protocol[0x4];
5131
b4ff3a36 5132 u8 reserved_at_60[0x20];
e281682b
SM		 5133};
5134
5135struct mlx5_ifc_query_adapter_out_bits {
5136 u8 status[0x8];
b4ff3a36 5137 u8 reserved_at_8[0x18];
e281682b
SM		 5138
5139 u8 syndrome[0x20];
5140
b4ff3a36 5141 u8 reserved_at_40[0x40];
e281682b
SM		 5142
5143 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5144};
5145
5146struct mlx5_ifc_query_adapter_in_bits {
5147 u8 opcode[0x10];
b4ff3a36 5148 u8 reserved_at_10[0x10];
e281682b 5149
b4ff3a36 5150 u8 reserved_at_20[0x10];
e281682b
SM		 5151 u8 op_mod[0x10];
5152
b4ff3a36 5153 u8 reserved_at_40[0x40];
e281682b
SM		 5154};
5155
5156struct mlx5_ifc_qp_2rst_out_bits {
5157 u8 status[0x8];
b4ff3a36 5158 u8 reserved_at_8[0x18];
e281682b
SM		 5159
5160 u8 syndrome[0x20];
5161
b4ff3a36 5162 u8 reserved_at_40[0x40];
e281682b
SM		 5163};
5164
5165struct mlx5_ifc_qp_2rst_in_bits {
5166 u8 opcode[0x10];
b4ff3a36 5167 u8 reserved_at_10[0x10];
e281682b 5168
b4ff3a36 5169 u8 reserved_at_20[0x10];
e281682b
SM		 5170 u8 op_mod[0x10];
5171
b4ff3a36 5172 u8 reserved_at_40[0x8];
e281682b
SM		 5173 u8 qpn[0x18];
5174
b4ff3a36 5175 u8 reserved_at_60[0x20];
e281682b
SM		 5176};
5177
5178struct mlx5_ifc_qp_2err_out_bits {
5179 u8 status[0x8];
b4ff3a36 5180 u8 reserved_at_8[0x18];
e281682b
SM		 5181
5182 u8 syndrome[0x20];
5183
b4ff3a36 5184 u8 reserved_at_40[0x40];
e281682b
SM		 5185};
5186
5187struct mlx5_ifc_qp_2err_in_bits {
5188 u8 opcode[0x10];
b4ff3a36 5189 u8 reserved_at_10[0x10];
e281682b 5190
b4ff3a36 5191 u8 reserved_at_20[0x10];
e281682b
SM		 5192 u8 op_mod[0x10];
5193
b4ff3a36 5194 u8 reserved_at_40[0x8];
e281682b
SM		 5195 u8 qpn[0x18];
5196
b4ff3a36 5197 u8 reserved_at_60[0x20];
e281682b
SM		 5198};
5199
5200struct mlx5_ifc_page_fault_resume_out_bits {
5201 u8 status[0x8];
b4ff3a36 5202 u8 reserved_at_8[0x18];
e281682b
SM		 5203
5204 u8 syndrome[0x20];
5205
b4ff3a36 5206 u8 reserved_at_40[0x40];
e281682b
SM		 5207};
5208
5209struct mlx5_ifc_page_fault_resume_in_bits {
5210 u8 opcode[0x10];
b4ff3a36 5211 u8 reserved_at_10[0x10];
e281682b 5212
b4ff3a36 5213 u8 reserved_at_20[0x10];
e281682b
SM		 5214 u8 op_mod[0x10];
5215
5216 u8 error[0x1];
b4ff3a36 5217 u8 reserved_at_41[0x4];
223cdc72
AK		 5218 u8 page_fault_type[0x3];
5219 u8 wq_number[0x18];
e281682b 5220
223cdc72
AK		 5221 u8 reserved_at_60[0x8];
5222 u8 token[0x18];
e281682b
SM		 5223};
5224
5225struct mlx5_ifc_nop_out_bits {
5226 u8 status[0x8];
b4ff3a36 5227 u8 reserved_at_8[0x18];
e281682b
SM		 5228
5229 u8 syndrome[0x20];
5230
b4ff3a36 5231 u8 reserved_at_40[0x40];
e281682b
SM		 5232};
5233
5234struct mlx5_ifc_nop_in_bits {
5235 u8 opcode[0x10];
b4ff3a36 5236 u8 reserved_at_10[0x10];
e281682b 5237
b4ff3a36 5238 u8 reserved_at_20[0x10];
e281682b
SM		 5239 u8 op_mod[0x10];
5240
b4ff3a36 5241 u8 reserved_at_40[0x40];
e281682b
SM		 5242};
5243
5244struct mlx5_ifc_modify_vport_state_out_bits {
5245 u8 status[0x8];
b4ff3a36 5246 u8 reserved_at_8[0x18];
e281682b
SM		 5247
5248 u8 syndrome[0x20];
5249
b4ff3a36 5250 u8 reserved_at_40[0x40];
e281682b
SM		 5251};
5252
5253struct mlx5_ifc_modify_vport_state_in_bits {
5254 u8 opcode[0x10];
b4ff3a36 5255 u8 reserved_at_10[0x10];
e281682b 5256
b4ff3a36 5257 u8 reserved_at_20[0x10];
e281682b
SM		 5258 u8 op_mod[0x10];
5259
5260 u8 other_vport[0x1];
b4ff3a36 5261 u8 reserved_at_41[0xf];
e281682b
SM		 5262 u8 vport_number[0x10];
5263
b4ff3a36 5264 u8 reserved_at_60[0x18];
e281682b 5265 u8 admin_state[0x4];
b4ff3a36 5266 u8 reserved_at_7c[0x4];
e281682b
SM		 5267};
5268
5269struct mlx5_ifc_modify_tis_out_bits {
5270 u8 status[0x8];
b4ff3a36 5271 u8 reserved_at_8[0x18];
e281682b
SM		 5272
5273 u8 syndrome[0x20];
5274
b4ff3a36 5275 u8 reserved_at_40[0x40];
e281682b
SM		 5276};
5277
75850d0b 5278struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5279 u8 reserved_at_0[0x20];
75850d0b 5280
84df61eb
AH		 5281 u8 reserved_at_20[0x1d];
5282 u8 lag_tx_port_affinity[0x1];
5283 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5284 u8 prio[0x1];
5285};
5286
e281682b
SM		 5287struct mlx5_ifc_modify_tis_in_bits {
5288 u8 opcode[0x10];
b4ff3a36 5289 u8 reserved_at_10[0x10];
e281682b 5290
b4ff3a36 5291 u8 reserved_at_20[0x10];
e281682b
SM		 5292 u8 op_mod[0x10];
5293
b4ff3a36 5294 u8 reserved_at_40[0x8];
e281682b
SM		 5295 u8 tisn[0x18];
5296
b4ff3a36 5297 u8 reserved_at_60[0x20];
e281682b 5298
75850d0b 5299 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5300
b4ff3a36 5301 u8 reserved_at_c0[0x40];
e281682b
SM		 5302
5303 struct mlx5_ifc_tisc_bits ctx;
5304};
5305
d9eea403 5306struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5307 u8 reserved_at_0[0x20];
d9eea403 5308
b4ff3a36 5309 u8 reserved_at_20[0x1b];
66189961 5310 u8 self_lb_en[0x1];
bdfc028d
TT		 5311 u8 reserved_at_3c[0x1];
5312 u8 hash[0x1];
5313 u8 reserved_at_3e[0x1];
d9eea403
AS		 5314 u8 lro[0x1];
5315};
5316
e281682b
SM		 5317struct mlx5_ifc_modify_tir_out_bits {
5318 u8 status[0x8];
b4ff3a36 5319 u8 reserved_at_8[0x18];
e281682b
SM		 5320
5321 u8 syndrome[0x20];
5322
b4ff3a36 5323 u8 reserved_at_40[0x40];
e281682b
SM		 5324};
5325
5326struct mlx5_ifc_modify_tir_in_bits {
5327 u8 opcode[0x10];
b4ff3a36 5328 u8 reserved_at_10[0x10];
e281682b 5329
b4ff3a36 5330 u8 reserved_at_20[0x10];
e281682b
SM		 5331 u8 op_mod[0x10];
5332
b4ff3a36 5333 u8 reserved_at_40[0x8];
e281682b
SM		 5334 u8 tirn[0x18];
5335
b4ff3a36 5336 u8 reserved_at_60[0x20];
e281682b 5337
d9eea403 5338 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5339
b4ff3a36 5340 u8 reserved_at_c0[0x40];
e281682b
SM		 5341
5342 struct mlx5_ifc_tirc_bits ctx;
5343};
5344
5345struct mlx5_ifc_modify_sq_out_bits {
5346 u8 status[0x8];
b4ff3a36 5347 u8 reserved_at_8[0x18];
e281682b
SM		 5348
5349 u8 syndrome[0x20];
5350
b4ff3a36 5351 u8 reserved_at_40[0x40];
e281682b
SM		 5352};
5353
5354struct mlx5_ifc_modify_sq_in_bits {
5355 u8 opcode[0x10];
b4ff3a36 5356 u8 reserved_at_10[0x10];
e281682b 5357
b4ff3a36 5358 u8 reserved_at_20[0x10];
e281682b
SM		 5359 u8 op_mod[0x10];
5360
5361 u8 sq_state[0x4];
b4ff3a36 5362 u8 reserved_at_44[0x4];
e281682b
SM		 5363 u8 sqn[0x18];
5364
b4ff3a36 5365 u8 reserved_at_60[0x20];
e281682b
SM		 5366
5367 u8 modify_bitmask[0x40];
5368
b4ff3a36 5369 u8 reserved_at_c0[0x40];
e281682b
SM		 5370
5371 struct mlx5_ifc_sqc_bits ctx;
5372};
5373
813f8540
MHY		 5374struct mlx5_ifc_modify_scheduling_element_out_bits {
5375 u8 status[0x8];
5376 u8 reserved_at_8[0x18];
5377
5378 u8 syndrome[0x20];
5379
5380 u8 reserved_at_40[0x1c0];
5381};
5382
5383enum {
5384 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5385 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5386};
5387
5388struct mlx5_ifc_modify_scheduling_element_in_bits {
5389 u8 opcode[0x10];
5390 u8 reserved_at_10[0x10];
5391
5392 u8 reserved_at_20[0x10];
5393 u8 op_mod[0x10];
5394
5395 u8 scheduling_hierarchy[0x8];
5396 u8 reserved_at_48[0x18];
5397
5398 u8 scheduling_element_id[0x20];
5399
5400 u8 reserved_at_80[0x20];
5401
5402 u8 modify_bitmask[0x20];
5403
5404 u8 reserved_at_c0[0x40];
5405
5406 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5407
5408 u8 reserved_at_300[0x100];
5409};
5410
e281682b
SM		 5411struct mlx5_ifc_modify_rqt_out_bits {
5412 u8 status[0x8];
b4ff3a36 5413 u8 reserved_at_8[0x18];
e281682b
SM		 5414
5415 u8 syndrome[0x20];
5416
b4ff3a36 5417 u8 reserved_at_40[0x40];
e281682b
SM		 5418};
5419
5c50368f 5420struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5421 u8 reserved_at_0[0x20];
5c50368f 5422
b4ff3a36 5423 u8 reserved_at_20[0x1f];
5c50368f
AS		 5424 u8 rqn_list[0x1];
5425};
5426
e281682b
SM		 5427struct mlx5_ifc_modify_rqt_in_bits {
5428 u8 opcode[0x10];
b4ff3a36 5429 u8 reserved_at_10[0x10];
e281682b 5430
b4ff3a36 5431 u8 reserved_at_20[0x10];
e281682b
SM		 5432 u8 op_mod[0x10];
5433
b4ff3a36 5434 u8 reserved_at_40[0x8];
e281682b
SM		 5435 u8 rqtn[0x18];
5436
b4ff3a36 5437 u8 reserved_at_60[0x20];
e281682b 5438
5c50368f 5439 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5440
b4ff3a36 5441 u8 reserved_at_c0[0x40];
e281682b
SM		 5442
5443 struct mlx5_ifc_rqtc_bits ctx;
5444};
5445
5446struct mlx5_ifc_modify_rq_out_bits {
5447 u8 status[0x8];
b4ff3a36 5448 u8 reserved_at_8[0x18];
e281682b
SM		 5449
5450 u8 syndrome[0x20];
5451
b4ff3a36 5452 u8 reserved_at_40[0x40];
e281682b
SM		 5453};
5454
83b502a1
AV		 5455enum {
5456 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5457 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5458 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5459};
5460
e281682b
SM		 5461struct mlx5_ifc_modify_rq_in_bits {
5462 u8 opcode[0x10];
b4ff3a36 5463 u8 reserved_at_10[0x10];
e281682b 5464
b4ff3a36 5465 u8 reserved_at_20[0x10];
e281682b
SM		 5466 u8 op_mod[0x10];
5467
5468 u8 rq_state[0x4];
b4ff3a36 5469 u8 reserved_at_44[0x4];
e281682b
SM		 5470 u8 rqn[0x18];
5471
b4ff3a36 5472 u8 reserved_at_60[0x20];
e281682b
SM		 5473
5474 u8 modify_bitmask[0x40];
5475
b4ff3a36 5476 u8 reserved_at_c0[0x40];
e281682b
SM		 5477
5478 struct mlx5_ifc_rqc_bits ctx;
5479};
5480
5481struct mlx5_ifc_modify_rmp_out_bits {
5482 u8 status[0x8];
b4ff3a36 5483 u8 reserved_at_8[0x18];
e281682b
SM		 5484
5485 u8 syndrome[0x20];
5486
b4ff3a36 5487 u8 reserved_at_40[0x40];
e281682b
SM		 5488};
5489
01949d01 5490struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5491 u8 reserved_at_0[0x20];
01949d01 5492
b4ff3a36 5493 u8 reserved_at_20[0x1f];
01949d01
HA		 5494 u8 lwm[0x1];
5495};
5496
e281682b
SM		 5497struct mlx5_ifc_modify_rmp_in_bits {
5498 u8 opcode[0x10];
b4ff3a36 5499 u8 reserved_at_10[0x10];
e281682b 5500
b4ff3a36 5501 u8 reserved_at_20[0x10];
e281682b
SM		 5502 u8 op_mod[0x10];
5503
5504 u8 rmp_state[0x4];
b4ff3a36 5505 u8 reserved_at_44[0x4];
e281682b
SM		 5506 u8 rmpn[0x18];
5507
b4ff3a36 5508 u8 reserved_at_60[0x20];
e281682b 5509
01949d01 5510 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5511
b4ff3a36 5512 u8 reserved_at_c0[0x40];
e281682b
SM		 5513
5514 struct mlx5_ifc_rmpc_bits ctx;
5515};
5516
5517struct mlx5_ifc_modify_nic_vport_context_out_bits {
5518 u8 status[0x8];
b4ff3a36 5519 u8 reserved_at_8[0x18];
e281682b
SM		 5520
5521 u8 syndrome[0x20];
5522
b4ff3a36 5523 u8 reserved_at_40[0x40];
e281682b
SM		 5524};
5525
5526struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5527 u8 reserved_at_0[0x12];
5528 u8 affiliation[0x1];
5529 u8 reserved_at_e[0x1];
bded747b
HN		 5530 u8 disable_uc_local_lb[0x1];
5531 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5532 u8 node_guid[0x1];
5533 u8 port_guid[0x1];
9def7121 5534 u8 min_inline[0x1];
d82b7318
SM		 5535 u8 mtu[0x1];
5536 u8 change_event[0x1];
5537 u8 promisc[0x1];
e281682b
SM		 5538 u8 permanent_address[0x1];
5539 u8 addresses_list[0x1];
5540 u8 roce_en[0x1];
b4ff3a36 5541 u8 reserved_at_1f[0x1];
e281682b
SM		 5542};
5543
5544struct mlx5_ifc_modify_nic_vport_context_in_bits {
5545 u8 opcode[0x10];
b4ff3a36 5546 u8 reserved_at_10[0x10];
e281682b 5547
b4ff3a36 5548 u8 reserved_at_20[0x10];
e281682b
SM		 5549 u8 op_mod[0x10];
5550
5551 u8 other_vport[0x1];
b4ff3a36 5552 u8 reserved_at_41[0xf];
e281682b
SM		 5553 u8 vport_number[0x10];
5554
5555 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5556
b4ff3a36 5557 u8 reserved_at_80[0x780];
e281682b
SM		 5558
5559 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5560};
5561
5562struct mlx5_ifc_modify_hca_vport_context_out_bits {
5563 u8 status[0x8];
b4ff3a36 5564 u8 reserved_at_8[0x18];
e281682b
SM		 5565
5566 u8 syndrome[0x20];
5567
b4ff3a36 5568 u8 reserved_at_40[0x40];
e281682b
SM		 5569};
5570
5571struct mlx5_ifc_modify_hca_vport_context_in_bits {
5572 u8 opcode[0x10];
b4ff3a36 5573 u8 reserved_at_10[0x10];
e281682b 5574
b4ff3a36 5575 u8 reserved_at_20[0x10];
e281682b
SM		 5576 u8 op_mod[0x10];
5577
5578 u8 other_vport[0x1];
b4ff3a36 5579 u8 reserved_at_41[0xb];
707c4602 5580 u8 port_num[0x4];
e281682b
SM		 5581 u8 vport_number[0x10];
5582
b4ff3a36 5583 u8 reserved_at_60[0x20];
e281682b
SM		 5584
5585 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5586};
5587
5588struct mlx5_ifc_modify_cq_out_bits {
5589 u8 status[0x8];
b4ff3a36 5590 u8 reserved_at_8[0x18];
e281682b
SM		 5591
5592 u8 syndrome[0x20];
5593
b4ff3a36 5594 u8 reserved_at_40[0x40];
e281682b
SM		 5595};
5596
5597enum {
5598 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5599 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5600};
5601
5602struct mlx5_ifc_modify_cq_in_bits {
5603 u8 opcode[0x10];
b4ff3a36 5604 u8 reserved_at_10[0x10];
e281682b 5605
b4ff3a36 5606 u8 reserved_at_20[0x10];
e281682b
SM		 5607 u8 op_mod[0x10];
5608
b4ff3a36 5609 u8 reserved_at_40[0x8];
e281682b
SM		 5610 u8 cqn[0x18];
5611
5612 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5613
5614 struct mlx5_ifc_cqc_bits cq_context;
5615
b4ff3a36 5616 u8 reserved_at_280[0x600];
e281682b
SM		 5617
5618 u8 pas[0][0x40];
5619};
5620
5621struct mlx5_ifc_modify_cong_status_out_bits {
5622 u8 status[0x8];
b4ff3a36 5623 u8 reserved_at_8[0x18];
e281682b
SM		 5624
5625 u8 syndrome[0x20];
5626
b4ff3a36 5627 u8 reserved_at_40[0x40];
e281682b
SM		 5628};
5629
5630struct mlx5_ifc_modify_cong_status_in_bits {
5631 u8 opcode[0x10];
b4ff3a36 5632 u8 reserved_at_10[0x10];
e281682b 5633
b4ff3a36 5634 u8 reserved_at_20[0x10];
e281682b
SM		 5635 u8 op_mod[0x10];
5636
b4ff3a36 5637 u8 reserved_at_40[0x18];
e281682b
SM		 5638 u8 priority[0x4];
5639 u8 cong_protocol[0x4];
5640
5641 u8 enable[0x1];
5642 u8 tag_enable[0x1];
b4ff3a36 5643 u8 reserved_at_62[0x1e];
e281682b
SM		 5644};
5645
5646struct mlx5_ifc_modify_cong_params_out_bits {
5647 u8 status[0x8];
b4ff3a36 5648 u8 reserved_at_8[0x18];
e281682b
SM		 5649
5650 u8 syndrome[0x20];
5651
b4ff3a36 5652 u8 reserved_at_40[0x40];
e281682b
SM		 5653};
5654
5655struct mlx5_ifc_modify_cong_params_in_bits {
5656 u8 opcode[0x10];
b4ff3a36 5657 u8 reserved_at_10[0x10];
e281682b 5658
b4ff3a36 5659 u8 reserved_at_20[0x10];
e281682b
SM		 5660 u8 op_mod[0x10];
5661
b4ff3a36 5662 u8 reserved_at_40[0x1c];
e281682b
SM		 5663 u8 cong_protocol[0x4];
5664
5665 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5666
b4ff3a36 5667 u8 reserved_at_80[0x80];
e281682b
SM		 5668
5669 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5670};
5671
5672struct mlx5_ifc_manage_pages_out_bits {
5673 u8 status[0x8];
b4ff3a36 5674 u8 reserved_at_8[0x18];
e281682b
SM		 5675
5676 u8 syndrome[0x20];
5677
5678 u8 output_num_entries[0x20];
5679
b4ff3a36 5680 u8 reserved_at_60[0x20];
e281682b
SM		 5681
5682 u8 pas[0][0x40];
5683};
5684
5685enum {
5686 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5687 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5688 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5689};
5690
5691struct mlx5_ifc_manage_pages_in_bits {
5692 u8 opcode[0x10];
b4ff3a36 5693 u8 reserved_at_10[0x10];
e281682b 5694
b4ff3a36 5695 u8 reserved_at_20[0x10];
e281682b
SM		 5696 u8 op_mod[0x10];
5697
b4ff3a36 5698 u8 reserved_at_40[0x10];
e281682b
SM		 5699 u8 function_id[0x10];
5700
5701 u8 input_num_entries[0x20];
5702
5703 u8 pas[0][0x40];
5704};
5705
5706struct mlx5_ifc_mad_ifc_out_bits {
5707 u8 status[0x8];
b4ff3a36 5708 u8 reserved_at_8[0x18];
e281682b
SM		 5709
5710 u8 syndrome[0x20];
5711
b4ff3a36 5712 u8 reserved_at_40[0x40];
e281682b
SM		 5713
5714 u8 response_mad_packet[256][0x8];
5715};
5716
5717struct mlx5_ifc_mad_ifc_in_bits {
5718 u8 opcode[0x10];
b4ff3a36 5719 u8 reserved_at_10[0x10];
e281682b 5720
b4ff3a36 5721 u8 reserved_at_20[0x10];
e281682b
SM		 5722 u8 op_mod[0x10];
5723
5724 u8 remote_lid[0x10];
b4ff3a36 5725 u8 reserved_at_50[0x8];
e281682b
SM		 5726 u8 port[0x8];
5727
b4ff3a36 5728 u8 reserved_at_60[0x20];
e281682b
SM		 5729
5730 u8 mad[256][0x8];
5731};
5732
5733struct mlx5_ifc_init_hca_out_bits {
5734 u8 status[0x8];
b4ff3a36 5735 u8 reserved_at_8[0x18];
e281682b
SM		 5736
5737 u8 syndrome[0x20];
5738
b4ff3a36 5739 u8 reserved_at_40[0x40];
e281682b
SM		 5740};
5741
5742struct mlx5_ifc_init_hca_in_bits {
5743 u8 opcode[0x10];
b4ff3a36 5744 u8 reserved_at_10[0x10];
e281682b 5745
b4ff3a36 5746 u8 reserved_at_20[0x10];
e281682b
SM		 5747 u8 op_mod[0x10];
5748
b4ff3a36 5749 u8 reserved_at_40[0x40];
8737f818 5750 u8 sw_owner_id[4][0x20];
e281682b
SM		 5751};
5752
5753struct mlx5_ifc_init2rtr_qp_out_bits {
5754 u8 status[0x8];
b4ff3a36 5755 u8 reserved_at_8[0x18];
e281682b
SM		 5756
5757 u8 syndrome[0x20];
5758
b4ff3a36 5759 u8 reserved_at_40[0x40];
e281682b
SM		 5760};
5761
5762struct mlx5_ifc_init2rtr_qp_in_bits {
5763 u8 opcode[0x10];
b4ff3a36 5764 u8 reserved_at_10[0x10];
e281682b 5765
b4ff3a36 5766 u8 reserved_at_20[0x10];
e281682b
SM		 5767 u8 op_mod[0x10];
5768
b4ff3a36 5769 u8 reserved_at_40[0x8];
e281682b
SM		 5770 u8 qpn[0x18];
5771
b4ff3a36 5772 u8 reserved_at_60[0x20];
e281682b
SM		 5773
5774 u8 opt_param_mask[0x20];
5775
b4ff3a36 5776 u8 reserved_at_a0[0x20];
e281682b
SM		 5777
5778 struct mlx5_ifc_qpc_bits qpc;
5779
b4ff3a36 5780 u8 reserved_at_800[0x80];
e281682b
SM		 5781};
5782
5783struct mlx5_ifc_init2init_qp_out_bits {
5784 u8 status[0x8];
b4ff3a36 5785 u8 reserved_at_8[0x18];
e281682b
SM		 5786
5787 u8 syndrome[0x20];
5788
b4ff3a36 5789 u8 reserved_at_40[0x40];
e281682b
SM		 5790};
5791
5792struct mlx5_ifc_init2init_qp_in_bits {
5793 u8 opcode[0x10];
b4ff3a36 5794 u8 reserved_at_10[0x10];
e281682b 5795
b4ff3a36 5796 u8 reserved_at_20[0x10];
e281682b
SM		 5797 u8 op_mod[0x10];
5798
b4ff3a36 5799 u8 reserved_at_40[0x8];
e281682b
SM		 5800 u8 qpn[0x18];
5801
b4ff3a36 5802 u8 reserved_at_60[0x20];
e281682b
SM		 5803
5804 u8 opt_param_mask[0x20];
5805
b4ff3a36 5806 u8 reserved_at_a0[0x20];
e281682b
SM		 5807
5808 struct mlx5_ifc_qpc_bits qpc;
5809
b4ff3a36 5810 u8 reserved_at_800[0x80];
e281682b
SM		 5811};
5812
5813struct mlx5_ifc_get_dropped_packet_log_out_bits {
5814 u8 status[0x8];
b4ff3a36 5815 u8 reserved_at_8[0x18];
e281682b
SM		 5816
5817 u8 syndrome[0x20];
5818
b4ff3a36 5819 u8 reserved_at_40[0x40];
e281682b
SM		 5820
5821 u8 packet_headers_log[128][0x8];
5822
5823 u8 packet_syndrome[64][0x8];
5824};
5825
5826struct mlx5_ifc_get_dropped_packet_log_in_bits {
5827 u8 opcode[0x10];
b4ff3a36 5828 u8 reserved_at_10[0x10];
e281682b 5829
b4ff3a36 5830 u8 reserved_at_20[0x10];
e281682b
SM		 5831 u8 op_mod[0x10];
5832
b4ff3a36 5833 u8 reserved_at_40[0x40];
e281682b
SM		 5834};
5835
5836struct mlx5_ifc_gen_eqe_in_bits {
5837 u8 opcode[0x10];
b4ff3a36 5838 u8 reserved_at_10[0x10];
e281682b 5839
b4ff3a36 5840 u8 reserved_at_20[0x10];
e281682b
SM		 5841 u8 op_mod[0x10];
5842
b4ff3a36 5843 u8 reserved_at_40[0x18];
e281682b
SM		 5844 u8 eq_number[0x8];
5845
b4ff3a36 5846 u8 reserved_at_60[0x20];
e281682b
SM		 5847
5848 u8 eqe[64][0x8];
5849};
5850
5851struct mlx5_ifc_gen_eq_out_bits {
5852 u8 status[0x8];
b4ff3a36 5853 u8 reserved_at_8[0x18];
e281682b
SM		 5854
5855 u8 syndrome[0x20];
5856
b4ff3a36 5857 u8 reserved_at_40[0x40];
e281682b
SM		 5858};
5859
5860struct mlx5_ifc_enable_hca_out_bits {
5861 u8 status[0x8];
b4ff3a36 5862 u8 reserved_at_8[0x18];
e281682b
SM		 5863
5864 u8 syndrome[0x20];
5865
b4ff3a36 5866 u8 reserved_at_40[0x20];
e281682b
SM		 5867};
5868
5869struct mlx5_ifc_enable_hca_in_bits {
5870 u8 opcode[0x10];
b4ff3a36 5871 u8 reserved_at_10[0x10];
e281682b 5872
b4ff3a36 5873 u8 reserved_at_20[0x10];
e281682b
SM		 5874 u8 op_mod[0x10];
5875
b4ff3a36 5876 u8 reserved_at_40[0x10];
e281682b
SM		 5877 u8 function_id[0x10];
5878
b4ff3a36 5879 u8 reserved_at_60[0x20];
e281682b
SM		 5880};
5881
5882struct mlx5_ifc_drain_dct_out_bits {
5883 u8 status[0x8];
b4ff3a36 5884 u8 reserved_at_8[0x18];
e281682b
SM		 5885
5886 u8 syndrome[0x20];
5887
b4ff3a36 5888 u8 reserved_at_40[0x40];
e281682b
SM		 5889};
5890
5891struct mlx5_ifc_drain_dct_in_bits {
5892 u8 opcode[0x10];
b4ff3a36 5893 u8 reserved_at_10[0x10];
e281682b 5894
b4ff3a36 5895 u8 reserved_at_20[0x10];
e281682b
SM		 5896 u8 op_mod[0x10];
5897
b4ff3a36 5898 u8 reserved_at_40[0x8];
e281682b
SM		 5899 u8 dctn[0x18];
5900
b4ff3a36 5901 u8 reserved_at_60[0x20];
e281682b
SM		 5902};
5903
5904struct mlx5_ifc_disable_hca_out_bits {
5905 u8 status[0x8];
b4ff3a36 5906 u8 reserved_at_8[0x18];
e281682b
SM		 5907
5908 u8 syndrome[0x20];
5909
b4ff3a36 5910 u8 reserved_at_40[0x20];
e281682b
SM		 5911};
5912
5913struct mlx5_ifc_disable_hca_in_bits {
5914 u8 opcode[0x10];
b4ff3a36 5915 u8 reserved_at_10[0x10];
e281682b 5916
b4ff3a36 5917 u8 reserved_at_20[0x10];
e281682b
SM		 5918 u8 op_mod[0x10];
5919
b4ff3a36 5920 u8 reserved_at_40[0x10];
e281682b
SM		 5921 u8 function_id[0x10];
5922
b4ff3a36 5923 u8 reserved_at_60[0x20];
e281682b
SM		 5924};
5925
5926struct mlx5_ifc_detach_from_mcg_out_bits {
5927 u8 status[0x8];
b4ff3a36 5928 u8 reserved_at_8[0x18];
e281682b
SM		 5929
5930 u8 syndrome[0x20];
5931
b4ff3a36 5932 u8 reserved_at_40[0x40];
e281682b
SM		 5933};
5934
5935struct mlx5_ifc_detach_from_mcg_in_bits {
5936 u8 opcode[0x10];
b4ff3a36 5937 u8 reserved_at_10[0x10];
e281682b 5938
b4ff3a36 5939 u8 reserved_at_20[0x10];
e281682b
SM		 5940 u8 op_mod[0x10];
5941
b4ff3a36 5942 u8 reserved_at_40[0x8];
e281682b
SM		 5943 u8 qpn[0x18];
5944
b4ff3a36 5945 u8 reserved_at_60[0x20];
e281682b
SM		 5946
5947 u8 multicast_gid[16][0x8];
5948};
5949
7486216b
SM		 5950struct mlx5_ifc_destroy_xrq_out_bits {
5951 u8 status[0x8];
5952 u8 reserved_at_8[0x18];
5953
5954 u8 syndrome[0x20];
5955
5956 u8 reserved_at_40[0x40];
5957};
5958
5959struct mlx5_ifc_destroy_xrq_in_bits {
5960 u8 opcode[0x10];
5961 u8 reserved_at_10[0x10];
5962
5963 u8 reserved_at_20[0x10];
5964 u8 op_mod[0x10];
5965
5966 u8 reserved_at_40[0x8];
5967 u8 xrqn[0x18];
5968
5969 u8 reserved_at_60[0x20];
5970};
5971
e281682b
SM		 5972struct mlx5_ifc_destroy_xrc_srq_out_bits {
5973 u8 status[0x8];
b4ff3a36 5974 u8 reserved_at_8[0x18];
e281682b
SM		 5975
5976 u8 syndrome[0x20];
5977
b4ff3a36 5978 u8 reserved_at_40[0x40];
e281682b
SM		 5979};
5980
5981struct mlx5_ifc_destroy_xrc_srq_in_bits {
5982 u8 opcode[0x10];
b4ff3a36 5983 u8 reserved_at_10[0x10];
e281682b 5984
b4ff3a36 5985 u8 reserved_at_20[0x10];
e281682b
SM		 5986 u8 op_mod[0x10];
5987
b4ff3a36 5988 u8 reserved_at_40[0x8];
e281682b
SM		 5989 u8 xrc_srqn[0x18];
5990
b4ff3a36 5991 u8 reserved_at_60[0x20];
e281682b
SM		 5992};
5993
5994struct mlx5_ifc_destroy_tis_out_bits {
5995 u8 status[0x8];
b4ff3a36 5996 u8 reserved_at_8[0x18];
e281682b
SM		 5997
5998 u8 syndrome[0x20];
5999
b4ff3a36 6000 u8 reserved_at_40[0x40];
e281682b
SM		 6001};
6002
6003struct mlx5_ifc_destroy_tis_in_bits {
6004 u8 opcode[0x10];
b4ff3a36 6005 u8 reserved_at_10[0x10];
e281682b 6006
b4ff3a36 6007 u8 reserved_at_20[0x10];
e281682b
SM		 6008 u8 op_mod[0x10];
6009
b4ff3a36 6010 u8 reserved_at_40[0x8];
e281682b
SM		 6011 u8 tisn[0x18];
6012
b4ff3a36 6013 u8 reserved_at_60[0x20];
e281682b
SM		 6014};
6015
6016struct mlx5_ifc_destroy_tir_out_bits {
6017 u8 status[0x8];
b4ff3a36 6018 u8 reserved_at_8[0x18];
e281682b
SM		 6019
6020 u8 syndrome[0x20];
6021
b4ff3a36 6022 u8 reserved_at_40[0x40];
e281682b
SM		 6023};
6024
6025struct mlx5_ifc_destroy_tir_in_bits {
6026 u8 opcode[0x10];
b4ff3a36 6027 u8 reserved_at_10[0x10];
e281682b 6028
b4ff3a36 6029 u8 reserved_at_20[0x10];
e281682b
SM		 6030 u8 op_mod[0x10];
6031
b4ff3a36 6032 u8 reserved_at_40[0x8];
e281682b
SM		 6033 u8 tirn[0x18];
6034
b4ff3a36 6035 u8 reserved_at_60[0x20];
e281682b
SM		 6036};
6037
6038struct mlx5_ifc_destroy_srq_out_bits {
6039 u8 status[0x8];
b4ff3a36 6040 u8 reserved_at_8[0x18];
e281682b
SM		 6041
6042 u8 syndrome[0x20];
6043
b4ff3a36 6044 u8 reserved_at_40[0x40];
e281682b
SM		 6045};
6046
6047struct mlx5_ifc_destroy_srq_in_bits {
6048 u8 opcode[0x10];
b4ff3a36 6049 u8 reserved_at_10[0x10];
e281682b 6050
b4ff3a36 6051 u8 reserved_at_20[0x10];
e281682b
SM		 6052 u8 op_mod[0x10];
6053
b4ff3a36 6054 u8 reserved_at_40[0x8];
e281682b
SM		 6055 u8 srqn[0x18];
6056
b4ff3a36 6057 u8 reserved_at_60[0x20];
e281682b
SM		 6058};
6059
6060struct mlx5_ifc_destroy_sq_out_bits {
6061 u8 status[0x8];
b4ff3a36 6062 u8 reserved_at_8[0x18];
e281682b
SM		 6063
6064 u8 syndrome[0x20];
6065
b4ff3a36 6066 u8 reserved_at_40[0x40];
e281682b
SM		 6067};
6068
6069struct mlx5_ifc_destroy_sq_in_bits {
6070 u8 opcode[0x10];
b4ff3a36 6071 u8 reserved_at_10[0x10];
e281682b 6072
b4ff3a36 6073 u8 reserved_at_20[0x10];
e281682b
SM		 6074 u8 op_mod[0x10];
6075
b4ff3a36 6076 u8 reserved_at_40[0x8];
e281682b
SM		 6077 u8 sqn[0x18];
6078
b4ff3a36 6079 u8 reserved_at_60[0x20];
e281682b
SM		 6080};
6081
813f8540
MHY		 6082struct mlx5_ifc_destroy_scheduling_element_out_bits {
6083 u8 status[0x8];
6084 u8 reserved_at_8[0x18];
6085
6086 u8 syndrome[0x20];
6087
6088 u8 reserved_at_40[0x1c0];
6089};
6090
6091struct mlx5_ifc_destroy_scheduling_element_in_bits {
6092 u8 opcode[0x10];
6093 u8 reserved_at_10[0x10];
6094
6095 u8 reserved_at_20[0x10];
6096 u8 op_mod[0x10];
6097
6098 u8 scheduling_hierarchy[0x8];
6099 u8 reserved_at_48[0x18];
6100
6101 u8 scheduling_element_id[0x20];
6102
6103 u8 reserved_at_80[0x180];
6104};
6105
e281682b
SM		 6106struct mlx5_ifc_destroy_rqt_out_bits {
6107 u8 status[0x8];
b4ff3a36 6108 u8 reserved_at_8[0x18];
e281682b
SM		 6109
6110 u8 syndrome[0x20];
6111
b4ff3a36 6112 u8 reserved_at_40[0x40];
e281682b
SM		 6113};
6114
6115struct mlx5_ifc_destroy_rqt_in_bits {
6116 u8 opcode[0x10];
b4ff3a36 6117 u8 reserved_at_10[0x10];
e281682b 6118
b4ff3a36 6119 u8 reserved_at_20[0x10];
e281682b
SM		 6120 u8 op_mod[0x10];
6121
b4ff3a36 6122 u8 reserved_at_40[0x8];
e281682b
SM		 6123 u8 rqtn[0x18];
6124
b4ff3a36 6125 u8 reserved_at_60[0x20];
e281682b
SM		 6126};
6127
6128struct mlx5_ifc_destroy_rq_out_bits {
6129 u8 status[0x8];
b4ff3a36 6130 u8 reserved_at_8[0x18];
e281682b
SM		 6131
6132 u8 syndrome[0x20];
6133
b4ff3a36 6134 u8 reserved_at_40[0x40];
e281682b
SM		 6135};
6136
6137struct mlx5_ifc_destroy_rq_in_bits {
6138 u8 opcode[0x10];
b4ff3a36 6139 u8 reserved_at_10[0x10];
e281682b 6140
b4ff3a36 6141 u8 reserved_at_20[0x10];
e281682b
SM		 6142 u8 op_mod[0x10];
6143
b4ff3a36 6144 u8 reserved_at_40[0x8];
e281682b
SM		 6145 u8 rqn[0x18];
6146
b4ff3a36 6147 u8 reserved_at_60[0x20];
e281682b
SM		 6148};
6149
c1e0bfc1
MG		 6150struct mlx5_ifc_set_delay_drop_params_in_bits {
6151 u8 opcode[0x10];
6152 u8 reserved_at_10[0x10];
6153
6154 u8 reserved_at_20[0x10];
6155 u8 op_mod[0x10];
6156
6157 u8 reserved_at_40[0x20];
6158
6159 u8 reserved_at_60[0x10];
6160 u8 delay_drop_timeout[0x10];
6161};
6162
6163struct mlx5_ifc_set_delay_drop_params_out_bits {
6164 u8 status[0x8];
6165 u8 reserved_at_8[0x18];
6166
6167 u8 syndrome[0x20];
6168
6169 u8 reserved_at_40[0x40];
6170};
6171
e281682b
SM		 6172struct mlx5_ifc_destroy_rmp_out_bits {
6173 u8 status[0x8];
b4ff3a36 6174 u8 reserved_at_8[0x18];
e281682b
SM		 6175
6176 u8 syndrome[0x20];
6177
b4ff3a36 6178 u8 reserved_at_40[0x40];
e281682b
SM		 6179};
6180
6181struct mlx5_ifc_destroy_rmp_in_bits {
6182 u8 opcode[0x10];
b4ff3a36 6183 u8 reserved_at_10[0x10];
e281682b 6184
b4ff3a36 6185 u8 reserved_at_20[0x10];
e281682b
SM		 6186 u8 op_mod[0x10];
6187
b4ff3a36 6188 u8 reserved_at_40[0x8];
e281682b
SM		 6189 u8 rmpn[0x18];
6190
b4ff3a36 6191 u8 reserved_at_60[0x20];
e281682b
SM		 6192};
6193
6194struct mlx5_ifc_destroy_qp_out_bits {
6195 u8 status[0x8];
b4ff3a36 6196 u8 reserved_at_8[0x18];
e281682b
SM		 6197
6198 u8 syndrome[0x20];
6199
b4ff3a36 6200 u8 reserved_at_40[0x40];
e281682b
SM		 6201};
6202
6203struct mlx5_ifc_destroy_qp_in_bits {
6204 u8 opcode[0x10];
b4ff3a36 6205 u8 reserved_at_10[0x10];
e281682b 6206
b4ff3a36 6207 u8 reserved_at_20[0x10];
e281682b
SM		 6208 u8 op_mod[0x10];
6209
b4ff3a36 6210 u8 reserved_at_40[0x8];
e281682b
SM		 6211 u8 qpn[0x18];
6212
b4ff3a36 6213 u8 reserved_at_60[0x20];
e281682b
SM		 6214};
6215
6216struct mlx5_ifc_destroy_psv_out_bits {
6217 u8 status[0x8];
b4ff3a36 6218 u8 reserved_at_8[0x18];
e281682b
SM		 6219
6220 u8 syndrome[0x20];
6221
b4ff3a36 6222 u8 reserved_at_40[0x40];
e281682b
SM		 6223};
6224
6225struct mlx5_ifc_destroy_psv_in_bits {
6226 u8 opcode[0x10];
b4ff3a36 6227 u8 reserved_at_10[0x10];
e281682b 6228
b4ff3a36 6229 u8 reserved_at_20[0x10];
e281682b
SM		 6230 u8 op_mod[0x10];
6231
b4ff3a36 6232 u8 reserved_at_40[0x8];
e281682b
SM		 6233 u8 psvn[0x18];
6234
b4ff3a36 6235 u8 reserved_at_60[0x20];
e281682b
SM		 6236};
6237
6238struct mlx5_ifc_destroy_mkey_out_bits {
6239 u8 status[0x8];
b4ff3a36 6240 u8 reserved_at_8[0x18];
e281682b
SM		 6241
6242 u8 syndrome[0x20];
6243
b4ff3a36 6244 u8 reserved_at_40[0x40];
e281682b
SM		 6245};
6246
6247struct mlx5_ifc_destroy_mkey_in_bits {
6248 u8 opcode[0x10];
b4ff3a36 6249 u8 reserved_at_10[0x10];
e281682b 6250
b4ff3a36 6251 u8 reserved_at_20[0x10];
e281682b
SM		 6252 u8 op_mod[0x10];
6253
b4ff3a36 6254 u8 reserved_at_40[0x8];
e281682b
SM		 6255 u8 mkey_index[0x18];
6256
b4ff3a36 6257 u8 reserved_at_60[0x20];
e281682b
SM		 6258};
6259
6260struct mlx5_ifc_destroy_flow_table_out_bits {
6261 u8 status[0x8];
b4ff3a36 6262 u8 reserved_at_8[0x18];
e281682b
SM		 6263
6264 u8 syndrome[0x20];
6265
b4ff3a36 6266 u8 reserved_at_40[0x40];
e281682b
SM		 6267};
6268
6269struct mlx5_ifc_destroy_flow_table_in_bits {
6270 u8 opcode[0x10];
b4ff3a36 6271 u8 reserved_at_10[0x10];
e281682b 6272
b4ff3a36 6273 u8 reserved_at_20[0x10];
e281682b
SM		 6274 u8 op_mod[0x10];
6275
7d5e1423
SM		 6276 u8 other_vport[0x1];
6277 u8 reserved_at_41[0xf];
6278 u8 vport_number[0x10];
6279
6280 u8 reserved_at_60[0x20];
e281682b
SM		 6281
6282 u8 table_type[0x8];
b4ff3a36 6283 u8 reserved_at_88[0x18];
e281682b 6284
b4ff3a36 6285 u8 reserved_at_a0[0x8];
e281682b
SM		 6286 u8 table_id[0x18];
6287
b4ff3a36 6288 u8 reserved_at_c0[0x140];
e281682b
SM		 6289};
6290
6291struct mlx5_ifc_destroy_flow_group_out_bits {
6292 u8 status[0x8];
b4ff3a36 6293 u8 reserved_at_8[0x18];
e281682b
SM		 6294
6295 u8 syndrome[0x20];
6296
b4ff3a36 6297 u8 reserved_at_40[0x40];
e281682b
SM		 6298};
6299
6300struct mlx5_ifc_destroy_flow_group_in_bits {
6301 u8 opcode[0x10];
b4ff3a36 6302 u8 reserved_at_10[0x10];
e281682b 6303
b4ff3a36 6304 u8 reserved_at_20[0x10];
e281682b
SM		 6305 u8 op_mod[0x10];
6306
7d5e1423
SM		 6307 u8 other_vport[0x1];
6308 u8 reserved_at_41[0xf];
6309 u8 vport_number[0x10];
6310
6311 u8 reserved_at_60[0x20];
e281682b
SM		 6312
6313 u8 table_type[0x8];
b4ff3a36 6314 u8 reserved_at_88[0x18];
e281682b 6315
b4ff3a36 6316 u8 reserved_at_a0[0x8];
e281682b
SM		 6317 u8 table_id[0x18];
6318
6319 u8 group_id[0x20];
6320
b4ff3a36 6321 u8 reserved_at_e0[0x120];
e281682b
SM		 6322};
6323
6324struct mlx5_ifc_destroy_eq_out_bits {
6325 u8 status[0x8];
b4ff3a36 6326 u8 reserved_at_8[0x18];
e281682b
SM		 6327
6328 u8 syndrome[0x20];
6329
b4ff3a36 6330 u8 reserved_at_40[0x40];
e281682b
SM		 6331};
6332
6333struct mlx5_ifc_destroy_eq_in_bits {
6334 u8 opcode[0x10];
b4ff3a36 6335 u8 reserved_at_10[0x10];
e281682b 6336
b4ff3a36 6337 u8 reserved_at_20[0x10];
e281682b
SM		 6338 u8 op_mod[0x10];
6339
b4ff3a36 6340 u8 reserved_at_40[0x18];
e281682b
SM		 6341 u8 eq_number[0x8];
6342
b4ff3a36 6343 u8 reserved_at_60[0x20];
e281682b
SM		 6344};
6345
6346struct mlx5_ifc_destroy_dct_out_bits {
6347 u8 status[0x8];
b4ff3a36 6348 u8 reserved_at_8[0x18];
e281682b
SM		 6349
6350 u8 syndrome[0x20];
6351
b4ff3a36 6352 u8 reserved_at_40[0x40];
e281682b
SM		 6353};
6354
6355struct mlx5_ifc_destroy_dct_in_bits {
6356 u8 opcode[0x10];
b4ff3a36 6357 u8 reserved_at_10[0x10];
e281682b 6358
b4ff3a36 6359 u8 reserved_at_20[0x10];
e281682b
SM		 6360 u8 op_mod[0x10];
6361
b4ff3a36 6362 u8 reserved_at_40[0x8];
e281682b
SM		 6363 u8 dctn[0x18];
6364
b4ff3a36 6365 u8 reserved_at_60[0x20];
e281682b
SM		 6366};
6367
6368struct mlx5_ifc_destroy_cq_out_bits {
6369 u8 status[0x8];
b4ff3a36 6370 u8 reserved_at_8[0x18];
e281682b
SM		 6371
6372 u8 syndrome[0x20];
6373
b4ff3a36 6374 u8 reserved_at_40[0x40];
e281682b
SM		 6375};
6376
6377struct mlx5_ifc_destroy_cq_in_bits {
6378 u8 opcode[0x10];
b4ff3a36 6379 u8 reserved_at_10[0x10];
e281682b 6380
b4ff3a36 6381 u8 reserved_at_20[0x10];
e281682b
SM		 6382 u8 op_mod[0x10];
6383
b4ff3a36 6384 u8 reserved_at_40[0x8];
e281682b
SM		 6385 u8 cqn[0x18];
6386
b4ff3a36 6387 u8 reserved_at_60[0x20];
e281682b
SM		 6388};
6389
6390struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6391 u8 status[0x8];
b4ff3a36 6392 u8 reserved_at_8[0x18];
e281682b
SM		 6393
6394 u8 syndrome[0x20];
6395
b4ff3a36 6396 u8 reserved_at_40[0x40];
e281682b
SM		 6397};
6398
6399struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6400 u8 opcode[0x10];
b4ff3a36 6401 u8 reserved_at_10[0x10];
e281682b 6402
b4ff3a36 6403 u8 reserved_at_20[0x10];
e281682b
SM		 6404 u8 op_mod[0x10];
6405
b4ff3a36 6406 u8 reserved_at_40[0x20];
e281682b 6407
b4ff3a36 6408 u8 reserved_at_60[0x10];
e281682b
SM		 6409 u8 vxlan_udp_port[0x10];
6410};
6411
6412struct mlx5_ifc_delete_l2_table_entry_out_bits {
6413 u8 status[0x8];
b4ff3a36 6414 u8 reserved_at_8[0x18];
e281682b
SM		 6415
6416 u8 syndrome[0x20];
6417
b4ff3a36 6418 u8 reserved_at_40[0x40];
e281682b
SM		 6419};
6420
6421struct mlx5_ifc_delete_l2_table_entry_in_bits {
6422 u8 opcode[0x10];
b4ff3a36 6423 u8 reserved_at_10[0x10];
e281682b 6424
b4ff3a36 6425 u8 reserved_at_20[0x10];
e281682b
SM		 6426 u8 op_mod[0x10];
6427
b4ff3a36 6428 u8 reserved_at_40[0x60];
e281682b 6429
b4ff3a36 6430 u8 reserved_at_a0[0x8];
e281682b
SM		 6431 u8 table_index[0x18];
6432
b4ff3a36 6433 u8 reserved_at_c0[0x140];
e281682b
SM		 6434};
6435
6436struct mlx5_ifc_delete_fte_out_bits {
6437 u8 status[0x8];
b4ff3a36 6438 u8 reserved_at_8[0x18];
e281682b
SM		 6439
6440 u8 syndrome[0x20];
6441
b4ff3a36 6442 u8 reserved_at_40[0x40];
e281682b
SM		 6443};
6444
6445struct mlx5_ifc_delete_fte_in_bits {
6446 u8 opcode[0x10];
b4ff3a36 6447 u8 reserved_at_10[0x10];
e281682b 6448
b4ff3a36 6449 u8 reserved_at_20[0x10];
e281682b
SM		 6450 u8 op_mod[0x10];
6451
7d5e1423
SM		 6452 u8 other_vport[0x1];
6453 u8 reserved_at_41[0xf];
6454 u8 vport_number[0x10];
6455
6456 u8 reserved_at_60[0x20];
e281682b
SM		 6457
6458 u8 table_type[0x8];
b4ff3a36 6459 u8 reserved_at_88[0x18];
e281682b 6460
b4ff3a36 6461 u8 reserved_at_a0[0x8];
e281682b
SM		 6462 u8 table_id[0x18];
6463
b4ff3a36 6464 u8 reserved_at_c0[0x40];
e281682b
SM		 6465
6466 u8 flow_index[0x20];
6467
b4ff3a36 6468 u8 reserved_at_120[0xe0];
e281682b
SM		 6469};
6470
6471struct mlx5_ifc_dealloc_xrcd_out_bits {
6472 u8 status[0x8];
b4ff3a36 6473 u8 reserved_at_8[0x18];
e281682b
SM		 6474
6475 u8 syndrome[0x20];
6476
b4ff3a36 6477 u8 reserved_at_40[0x40];
e281682b
SM		 6478};
6479
6480struct mlx5_ifc_dealloc_xrcd_in_bits {
6481 u8 opcode[0x10];
b4ff3a36 6482 u8 reserved_at_10[0x10];
e281682b 6483
b4ff3a36 6484 u8 reserved_at_20[0x10];
e281682b
SM		 6485 u8 op_mod[0x10];
6486
b4ff3a36 6487 u8 reserved_at_40[0x8];
e281682b
SM		 6488 u8 xrcd[0x18];
6489
b4ff3a36 6490 u8 reserved_at_60[0x20];
e281682b
SM		 6491};
6492
6493struct mlx5_ifc_dealloc_uar_out_bits {
6494 u8 status[0x8];
b4ff3a36 6495 u8 reserved_at_8[0x18];
e281682b
SM		 6496
6497 u8 syndrome[0x20];
6498
b4ff3a36 6499 u8 reserved_at_40[0x40];
e281682b
SM		 6500};
6501
6502struct mlx5_ifc_dealloc_uar_in_bits {
6503 u8 opcode[0x10];
b4ff3a36 6504 u8 reserved_at_10[0x10];
e281682b 6505
b4ff3a36 6506 u8 reserved_at_20[0x10];
e281682b
SM		 6507 u8 op_mod[0x10];
6508
b4ff3a36 6509 u8 reserved_at_40[0x8];
e281682b
SM		 6510 u8 uar[0x18];
6511
b4ff3a36 6512 u8 reserved_at_60[0x20];
e281682b
SM		 6513};
6514
6515struct mlx5_ifc_dealloc_transport_domain_out_bits {
6516 u8 status[0x8];
b4ff3a36 6517 u8 reserved_at_8[0x18];
e281682b
SM		 6518
6519 u8 syndrome[0x20];
6520
b4ff3a36 6521 u8 reserved_at_40[0x40];
e281682b
SM		 6522};
6523
6524struct mlx5_ifc_dealloc_transport_domain_in_bits {
6525 u8 opcode[0x10];
b4ff3a36 6526 u8 reserved_at_10[0x10];
e281682b 6527
b4ff3a36 6528 u8 reserved_at_20[0x10];
e281682b
SM		 6529 u8 op_mod[0x10];
6530
b4ff3a36 6531 u8 reserved_at_40[0x8];
e281682b
SM		 6532 u8 transport_domain[0x18];
6533
b4ff3a36 6534 u8 reserved_at_60[0x20];
e281682b
SM		 6535};
6536
6537struct mlx5_ifc_dealloc_q_counter_out_bits {
6538 u8 status[0x8];
b4ff3a36 6539 u8 reserved_at_8[0x18];
e281682b
SM		 6540
6541 u8 syndrome[0x20];
6542
b4ff3a36 6543 u8 reserved_at_40[0x40];
e281682b
SM		 6544};
6545
6546struct mlx5_ifc_dealloc_q_counter_in_bits {
6547 u8 opcode[0x10];
b4ff3a36 6548 u8 reserved_at_10[0x10];
e281682b 6549
b4ff3a36 6550 u8 reserved_at_20[0x10];
e281682b
SM		 6551 u8 op_mod[0x10];
6552
b4ff3a36 6553 u8 reserved_at_40[0x18];
e281682b
SM		 6554 u8 counter_set_id[0x8];
6555
b4ff3a36 6556 u8 reserved_at_60[0x20];
e281682b
SM		 6557};
6558
6559struct mlx5_ifc_dealloc_pd_out_bits {
6560 u8 status[0x8];
b4ff3a36 6561 u8 reserved_at_8[0x18];
e281682b
SM		 6562
6563 u8 syndrome[0x20];
6564
b4ff3a36 6565 u8 reserved_at_40[0x40];
e281682b
SM		 6566};
6567
6568struct mlx5_ifc_dealloc_pd_in_bits {
6569 u8 opcode[0x10];
b4ff3a36 6570 u8 reserved_at_10[0x10];
e281682b 6571
b4ff3a36 6572 u8 reserved_at_20[0x10];
e281682b
SM		 6573 u8 op_mod[0x10];
6574
b4ff3a36 6575 u8 reserved_at_40[0x8];
e281682b
SM		 6576 u8 pd[0x18];
6577
b4ff3a36 6578 u8 reserved_at_60[0x20];
e281682b
SM		 6579};
6580
9dc0b289
AV		 6581struct mlx5_ifc_dealloc_flow_counter_out_bits {
6582 u8 status[0x8];
6583 u8 reserved_at_8[0x18];
6584
6585 u8 syndrome[0x20];
6586
6587 u8 reserved_at_40[0x40];
6588};
6589
6590struct mlx5_ifc_dealloc_flow_counter_in_bits {
6591 u8 opcode[0x10];
6592 u8 reserved_at_10[0x10];
6593
6594 u8 reserved_at_20[0x10];
6595 u8 op_mod[0x10];
6596
a8ffcc74 6597 u8 flow_counter_id[0x20];
9dc0b289
AV		 6598
6599 u8 reserved_at_60[0x20];
6600};
6601
7486216b
SM		 6602struct mlx5_ifc_create_xrq_out_bits {
6603 u8 status[0x8];
6604 u8 reserved_at_8[0x18];
6605
6606 u8 syndrome[0x20];
6607
6608 u8 reserved_at_40[0x8];
6609 u8 xrqn[0x18];
6610
6611 u8 reserved_at_60[0x20];
6612};
6613
6614struct mlx5_ifc_create_xrq_in_bits {
6615 u8 opcode[0x10];
6616 u8 reserved_at_10[0x10];
6617
6618 u8 reserved_at_20[0x10];
6619 u8 op_mod[0x10];
6620
6621 u8 reserved_at_40[0x40];
6622
6623 struct mlx5_ifc_xrqc_bits xrq_context;
6624};
6625
e281682b
SM		 6626struct mlx5_ifc_create_xrc_srq_out_bits {
6627 u8 status[0x8];
b4ff3a36 6628 u8 reserved_at_8[0x18];
e281682b
SM		 6629
6630 u8 syndrome[0x20];
6631
b4ff3a36 6632 u8 reserved_at_40[0x8];
e281682b
SM		 6633 u8 xrc_srqn[0x18];
6634
b4ff3a36 6635 u8 reserved_at_60[0x20];
e281682b
SM		 6636};
6637
6638struct mlx5_ifc_create_xrc_srq_in_bits {
6639 u8 opcode[0x10];
b4ff3a36 6640 u8 reserved_at_10[0x10];
e281682b 6641
b4ff3a36 6642 u8 reserved_at_20[0x10];
e281682b
SM		 6643 u8 op_mod[0x10];
6644
b4ff3a36 6645 u8 reserved_at_40[0x40];
e281682b
SM		 6646
6647 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6648
b4ff3a36 6649 u8 reserved_at_280[0x600];
e281682b
SM		 6650
6651 u8 pas[0][0x40];
6652};
6653
6654struct mlx5_ifc_create_tis_out_bits {
6655 u8 status[0x8];
b4ff3a36 6656 u8 reserved_at_8[0x18];
e281682b
SM		 6657
6658 u8 syndrome[0x20];
6659
b4ff3a36 6660 u8 reserved_at_40[0x8];
e281682b
SM		 6661 u8 tisn[0x18];
6662
b4ff3a36 6663 u8 reserved_at_60[0x20];
e281682b
SM		 6664};
6665
6666struct mlx5_ifc_create_tis_in_bits {
6667 u8 opcode[0x10];
b4ff3a36 6668 u8 reserved_at_10[0x10];
e281682b 6669
b4ff3a36 6670 u8 reserved_at_20[0x10];
e281682b
SM		 6671 u8 op_mod[0x10];
6672
b4ff3a36 6673 u8 reserved_at_40[0xc0];
e281682b
SM		 6674
6675 struct mlx5_ifc_tisc_bits ctx;
6676};
6677
6678struct mlx5_ifc_create_tir_out_bits {
6679 u8 status[0x8];
b4ff3a36 6680 u8 reserved_at_8[0x18];
e281682b
SM		 6681
6682 u8 syndrome[0x20];
6683
b4ff3a36 6684 u8 reserved_at_40[0x8];
e281682b
SM		 6685 u8 tirn[0x18];
6686
b4ff3a36 6687 u8 reserved_at_60[0x20];
e281682b
SM		 6688};
6689
6690struct mlx5_ifc_create_tir_in_bits {
6691 u8 opcode[0x10];
b4ff3a36 6692 u8 reserved_at_10[0x10];
e281682b 6693
b4ff3a36 6694 u8 reserved_at_20[0x10];
e281682b
SM		 6695 u8 op_mod[0x10];
6696
b4ff3a36 6697 u8 reserved_at_40[0xc0];
e281682b
SM		 6698
6699 struct mlx5_ifc_tirc_bits ctx;
6700};
6701
6702struct mlx5_ifc_create_srq_out_bits {
6703 u8 status[0x8];
b4ff3a36 6704 u8 reserved_at_8[0x18];
e281682b
SM		 6705
6706 u8 syndrome[0x20];
6707
b4ff3a36 6708 u8 reserved_at_40[0x8];
e281682b
SM		 6709 u8 srqn[0x18];
6710
b4ff3a36 6711 u8 reserved_at_60[0x20];
e281682b
SM		 6712};
6713
6714struct mlx5_ifc_create_srq_in_bits {
6715 u8 opcode[0x10];
b4ff3a36 6716 u8 reserved_at_10[0x10];
e281682b 6717
b4ff3a36 6718 u8 reserved_at_20[0x10];
e281682b
SM		 6719 u8 op_mod[0x10];
6720
b4ff3a36 6721 u8 reserved_at_40[0x40];
e281682b
SM		 6722
6723 struct mlx5_ifc_srqc_bits srq_context_entry;
6724
b4ff3a36 6725 u8 reserved_at_280[0x600];
e281682b
SM		 6726
6727 u8 pas[0][0x40];
6728};
6729
6730struct mlx5_ifc_create_sq_out_bits {
6731 u8 status[0x8];
b4ff3a36 6732 u8 reserved_at_8[0x18];
e281682b
SM		 6733
6734 u8 syndrome[0x20];
6735
b4ff3a36 6736 u8 reserved_at_40[0x8];
e281682b
SM		 6737 u8 sqn[0x18];
6738
b4ff3a36 6739 u8 reserved_at_60[0x20];
e281682b
SM		 6740};
6741
6742struct mlx5_ifc_create_sq_in_bits {
6743 u8 opcode[0x10];
b4ff3a36 6744 u8 reserved_at_10[0x10];
e281682b 6745
b4ff3a36 6746 u8 reserved_at_20[0x10];
e281682b
SM		 6747 u8 op_mod[0x10];
6748
b4ff3a36 6749 u8 reserved_at_40[0xc0];
e281682b
SM		 6750
6751 struct mlx5_ifc_sqc_bits ctx;
6752};
6753
813f8540
MHY		 6754struct mlx5_ifc_create_scheduling_element_out_bits {
6755 u8 status[0x8];
6756 u8 reserved_at_8[0x18];
6757
6758 u8 syndrome[0x20];
6759
6760 u8 reserved_at_40[0x40];
6761
6762 u8 scheduling_element_id[0x20];
6763
6764 u8 reserved_at_a0[0x160];
6765};
6766
6767struct mlx5_ifc_create_scheduling_element_in_bits {
6768 u8 opcode[0x10];
6769 u8 reserved_at_10[0x10];
6770
6771 u8 reserved_at_20[0x10];
6772 u8 op_mod[0x10];
6773
6774 u8 scheduling_hierarchy[0x8];
6775 u8 reserved_at_48[0x18];
6776
6777 u8 reserved_at_60[0xa0];
6778
6779 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6780
6781 u8 reserved_at_300[0x100];
6782};
6783
e281682b
SM		 6784struct mlx5_ifc_create_rqt_out_bits {
6785 u8 status[0x8];
b4ff3a36 6786 u8 reserved_at_8[0x18];
e281682b
SM		 6787
6788 u8 syndrome[0x20];
6789
b4ff3a36 6790 u8 reserved_at_40[0x8];
e281682b
SM		 6791 u8 rqtn[0x18];
6792
b4ff3a36 6793 u8 reserved_at_60[0x20];
e281682b
SM		 6794};
6795
6796struct mlx5_ifc_create_rqt_in_bits {
6797 u8 opcode[0x10];
b4ff3a36 6798 u8 reserved_at_10[0x10];
e281682b 6799
b4ff3a36 6800 u8 reserved_at_20[0x10];
e281682b
SM		 6801 u8 op_mod[0x10];
6802
b4ff3a36 6803 u8 reserved_at_40[0xc0];
e281682b
SM		 6804
6805 struct mlx5_ifc_rqtc_bits rqt_context;
6806};
6807
6808struct mlx5_ifc_create_rq_out_bits {
6809 u8 status[0x8];
b4ff3a36 6810 u8 reserved_at_8[0x18];
e281682b
SM		 6811
6812 u8 syndrome[0x20];
6813
b4ff3a36 6814 u8 reserved_at_40[0x8];
e281682b
SM		 6815 u8 rqn[0x18];
6816
b4ff3a36 6817 u8 reserved_at_60[0x20];
e281682b
SM		 6818};
6819
6820struct mlx5_ifc_create_rq_in_bits {
6821 u8 opcode[0x10];
b4ff3a36 6822 u8 reserved_at_10[0x10];
e281682b 6823
b4ff3a36 6824 u8 reserved_at_20[0x10];
e281682b
SM		 6825 u8 op_mod[0x10];
6826
b4ff3a36 6827 u8 reserved_at_40[0xc0];
e281682b
SM		 6828
6829 struct mlx5_ifc_rqc_bits ctx;
6830};
6831
6832struct mlx5_ifc_create_rmp_out_bits {
6833 u8 status[0x8];
b4ff3a36 6834 u8 reserved_at_8[0x18];
e281682b
SM		 6835
6836 u8 syndrome[0x20];
6837
b4ff3a36 6838 u8 reserved_at_40[0x8];
e281682b
SM		 6839 u8 rmpn[0x18];
6840
b4ff3a36 6841 u8 reserved_at_60[0x20];
e281682b
SM		 6842};
6843
6844struct mlx5_ifc_create_rmp_in_bits {
6845 u8 opcode[0x10];
b4ff3a36 6846 u8 reserved_at_10[0x10];
e281682b 6847
b4ff3a36 6848 u8 reserved_at_20[0x10];
e281682b
SM		 6849 u8 op_mod[0x10];
6850
b4ff3a36 6851 u8 reserved_at_40[0xc0];
e281682b
SM		 6852
6853 struct mlx5_ifc_rmpc_bits ctx;
6854};
6855
6856struct mlx5_ifc_create_qp_out_bits {
6857 u8 status[0x8];
b4ff3a36 6858 u8 reserved_at_8[0x18];
e281682b
SM		 6859
6860 u8 syndrome[0x20];
6861
b4ff3a36 6862 u8 reserved_at_40[0x8];
e281682b
SM		 6863 u8 qpn[0x18];
6864
b4ff3a36 6865 u8 reserved_at_60[0x20];
e281682b
SM		 6866};
6867
6868struct mlx5_ifc_create_qp_in_bits {
6869 u8 opcode[0x10];
b4ff3a36 6870 u8 reserved_at_10[0x10];
e281682b 6871
b4ff3a36 6872 u8 reserved_at_20[0x10];
e281682b
SM		 6873 u8 op_mod[0x10];
6874
b4ff3a36 6875 u8 reserved_at_40[0x40];
e281682b
SM		 6876
6877 u8 opt_param_mask[0x20];
6878
b4ff3a36 6879 u8 reserved_at_a0[0x20];
e281682b
SM		 6880
6881 struct mlx5_ifc_qpc_bits qpc;
6882
b4ff3a36 6883 u8 reserved_at_800[0x80];
e281682b
SM		 6884
6885 u8 pas[0][0x40];
6886};
6887
6888struct mlx5_ifc_create_psv_out_bits {
6889 u8 status[0x8];
b4ff3a36 6890 u8 reserved_at_8[0x18];
e281682b
SM		 6891
6892 u8 syndrome[0x20];
6893
b4ff3a36 6894 u8 reserved_at_40[0x40];
e281682b 6895
b4ff3a36 6896 u8 reserved_at_80[0x8];
e281682b
SM		 6897 u8 psv0_index[0x18];
6898
b4ff3a36 6899 u8 reserved_at_a0[0x8];
e281682b
SM		 6900 u8 psv1_index[0x18];
6901
b4ff3a36 6902 u8 reserved_at_c0[0x8];
e281682b
SM		 6903 u8 psv2_index[0x18];
6904
b4ff3a36 6905 u8 reserved_at_e0[0x8];
e281682b
SM		 6906 u8 psv3_index[0x18];
6907};
6908
6909struct mlx5_ifc_create_psv_in_bits {
6910 u8 opcode[0x10];
b4ff3a36 6911 u8 reserved_at_10[0x10];
e281682b 6912
b4ff3a36 6913 u8 reserved_at_20[0x10];
e281682b
SM		 6914 u8 op_mod[0x10];
6915
6916 u8 num_psv[0x4];
b4ff3a36 6917 u8 reserved_at_44[0x4];
e281682b
SM		 6918 u8 pd[0x18];
6919
b4ff3a36 6920 u8 reserved_at_60[0x20];
e281682b
SM		 6921};
6922
6923struct mlx5_ifc_create_mkey_out_bits {
6924 u8 status[0x8];
b4ff3a36 6925 u8 reserved_at_8[0x18];
e281682b
SM		 6926
6927 u8 syndrome[0x20];
6928
b4ff3a36 6929 u8 reserved_at_40[0x8];
e281682b
SM		 6930 u8 mkey_index[0x18];
6931
b4ff3a36 6932 u8 reserved_at_60[0x20];
e281682b
SM		 6933};
6934
6935struct mlx5_ifc_create_mkey_in_bits {
6936 u8 opcode[0x10];
b4ff3a36 6937 u8 reserved_at_10[0x10];
e281682b 6938
b4ff3a36 6939 u8 reserved_at_20[0x10];
e281682b
SM		 6940 u8 op_mod[0x10];
6941
b4ff3a36 6942 u8 reserved_at_40[0x20];
e281682b
SM		 6943
6944 u8 pg_access[0x1];
b4ff3a36 6945 u8 reserved_at_61[0x1f];
e281682b
SM		 6946
6947 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6948
b4ff3a36 6949 u8 reserved_at_280[0x80];
e281682b
SM		 6950
6951 u8 translations_octword_actual_size[0x20];
6952
b4ff3a36 6953 u8 reserved_at_320[0x560];
e281682b
SM		 6954
6955 u8 klm_pas_mtt[0][0x20];
6956};
6957
6958struct mlx5_ifc_create_flow_table_out_bits {
6959 u8 status[0x8];
b4ff3a36 6960 u8 reserved_at_8[0x18];
e281682b
SM		 6961
6962 u8 syndrome[0x20];
6963
b4ff3a36 6964 u8 reserved_at_40[0x8];
e281682b
SM		 6965 u8 table_id[0x18];
6966
b4ff3a36 6967 u8 reserved_at_60[0x20];
e281682b
SM		 6968};
6969
0c90e9c6
MG		 6970struct mlx5_ifc_flow_table_context_bits {
6971 u8 encap_en[0x1];
6972 u8 decap_en[0x1];
6973 u8 reserved_at_2[0x2];
6974 u8 table_miss_action[0x4];
6975 u8 level[0x8];
6976 u8 reserved_at_10[0x8];
6977 u8 log_size[0x8];
6978
6979 u8 reserved_at_20[0x8];
6980 u8 table_miss_id[0x18];
6981
6982 u8 reserved_at_40[0x8];
6983 u8 lag_master_next_table_id[0x18];
6984
6985 u8 reserved_at_60[0xe0];
6986};
6987
e281682b
SM		 6988struct mlx5_ifc_create_flow_table_in_bits {
6989 u8 opcode[0x10];
b4ff3a36 6990 u8 reserved_at_10[0x10];
e281682b 6991
b4ff3a36 6992 u8 reserved_at_20[0x10];
e281682b
SM		 6993 u8 op_mod[0x10];
6994
7d5e1423
SM		 6995 u8 other_vport[0x1];
6996 u8 reserved_at_41[0xf];
6997 u8 vport_number[0x10];
6998
6999 u8 reserved_at_60[0x20];
e281682b
SM		 7000
7001 u8 table_type[0x8];
b4ff3a36 7002 u8 reserved_at_88[0x18];
e281682b 7003
b4ff3a36 7004 u8 reserved_at_a0[0x20];
e281682b 7005
0c90e9c6 7006 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 7007};
7008
7009struct mlx5_ifc_create_flow_group_out_bits {
7010 u8 status[0x8];
b4ff3a36 7011 u8 reserved_at_8[0x18];
e281682b
SM		 7012
7013 u8 syndrome[0x20];
7014
b4ff3a36 7015 u8 reserved_at_40[0x8];
e281682b
SM		 7016 u8 group_id[0x18];
7017
b4ff3a36 7018 u8 reserved_at_60[0x20];
e281682b
SM		 7019};
7020
7021enum {
71c6e863
AL		 7022 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7023 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7024 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7025 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 7026};
7027
7028struct mlx5_ifc_create_flow_group_in_bits {
7029 u8 opcode[0x10];
b4ff3a36 7030 u8 reserved_at_10[0x10];
e281682b 7031
b4ff3a36 7032 u8 reserved_at_20[0x10];
e281682b
SM		 7033 u8 op_mod[0x10];
7034
7d5e1423
SM		 7035 u8 other_vport[0x1];
7036 u8 reserved_at_41[0xf];
7037 u8 vport_number[0x10];
7038
7039 u8 reserved_at_60[0x20];
e281682b
SM		 7040
7041 u8 table_type[0x8];
b4ff3a36 7042 u8 reserved_at_88[0x18];
e281682b 7043
b4ff3a36 7044 u8 reserved_at_a0[0x8];
e281682b
SM		 7045 u8 table_id[0x18];
7046
3e99df87
SK		 7047 u8 source_eswitch_owner_vhca_id_valid[0x1];
7048
7049 u8 reserved_at_c1[0x1f];
e281682b
SM		 7050
7051 u8 start_flow_index[0x20];
7052
b4ff3a36 7053 u8 reserved_at_100[0x20];
e281682b
SM		 7054
7055 u8 end_flow_index[0x20];
7056
b4ff3a36 7057 u8 reserved_at_140[0xa0];
e281682b 7058
b4ff3a36 7059 u8 reserved_at_1e0[0x18];
e281682b
SM		 7060 u8 match_criteria_enable[0x8];
7061
7062 struct mlx5_ifc_fte_match_param_bits match_criteria;
7063
b4ff3a36 7064 u8 reserved_at_1200[0xe00];
e281682b
SM		 7065};
7066
7067struct mlx5_ifc_create_eq_out_bits {
7068 u8 status[0x8];
b4ff3a36 7069 u8 reserved_at_8[0x18];
e281682b
SM		 7070
7071 u8 syndrome[0x20];
7072
b4ff3a36 7073 u8 reserved_at_40[0x18];
e281682b
SM		 7074 u8 eq_number[0x8];
7075
b4ff3a36 7076 u8 reserved_at_60[0x20];
e281682b
SM		 7077};
7078
7079struct mlx5_ifc_create_eq_in_bits {
7080 u8 opcode[0x10];
b4ff3a36 7081 u8 reserved_at_10[0x10];
e281682b 7082
b4ff3a36 7083 u8 reserved_at_20[0x10];
e281682b
SM		 7084 u8 op_mod[0x10];
7085
b4ff3a36 7086 u8 reserved_at_40[0x40];
e281682b
SM		 7087
7088 struct mlx5_ifc_eqc_bits eq_context_entry;
7089
b4ff3a36 7090 u8 reserved_at_280[0x40];
e281682b
SM		 7091
7092 u8 event_bitmask[0x40];
7093
b4ff3a36 7094 u8 reserved_at_300[0x580];
e281682b
SM		 7095
7096 u8 pas[0][0x40];
7097};
7098
7099struct mlx5_ifc_create_dct_out_bits {
7100 u8 status[0x8];
b4ff3a36 7101 u8 reserved_at_8[0x18];
e281682b
SM		 7102
7103 u8 syndrome[0x20];
7104
b4ff3a36 7105 u8 reserved_at_40[0x8];
e281682b
SM		 7106 u8 dctn[0x18];
7107
b4ff3a36 7108 u8 reserved_at_60[0x20];
e281682b
SM		 7109};
7110
7111struct mlx5_ifc_create_dct_in_bits {
7112 u8 opcode[0x10];
b4ff3a36 7113 u8 reserved_at_10[0x10];
e281682b 7114
b4ff3a36 7115 u8 reserved_at_20[0x10];
e281682b
SM		 7116 u8 op_mod[0x10];
7117
b4ff3a36 7118 u8 reserved_at_40[0x40];
e281682b
SM		 7119
7120 struct mlx5_ifc_dctc_bits dct_context_entry;
7121
b4ff3a36 7122 u8 reserved_at_280[0x180];
e281682b
SM		 7123};
7124
7125struct mlx5_ifc_create_cq_out_bits {
7126 u8 status[0x8];
b4ff3a36 7127 u8 reserved_at_8[0x18];
e281682b
SM		 7128
7129 u8 syndrome[0x20];
7130
b4ff3a36 7131 u8 reserved_at_40[0x8];
e281682b
SM		 7132 u8 cqn[0x18];
7133
b4ff3a36 7134 u8 reserved_at_60[0x20];
e281682b
SM		 7135};
7136
7137struct mlx5_ifc_create_cq_in_bits {
7138 u8 opcode[0x10];
b4ff3a36 7139 u8 reserved_at_10[0x10];
e281682b 7140
b4ff3a36 7141 u8 reserved_at_20[0x10];
e281682b
SM		 7142 u8 op_mod[0x10];
7143
b4ff3a36 7144 u8 reserved_at_40[0x40];
e281682b
SM		 7145
7146 struct mlx5_ifc_cqc_bits cq_context;
7147
b4ff3a36 7148 u8 reserved_at_280[0x600];
e281682b
SM		 7149
7150 u8 pas[0][0x40];
7151};
7152
7153struct mlx5_ifc_config_int_moderation_out_bits {
7154 u8 status[0x8];
b4ff3a36 7155 u8 reserved_at_8[0x18];
e281682b
SM		 7156
7157 u8 syndrome[0x20];
7158
b4ff3a36 7159 u8 reserved_at_40[0x4];
e281682b
SM		 7160 u8 min_delay[0xc];
7161 u8 int_vector[0x10];
7162
b4ff3a36 7163 u8 reserved_at_60[0x20];
e281682b
SM		 7164};
7165
7166enum {
7167 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7168 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7169};
7170
7171struct mlx5_ifc_config_int_moderation_in_bits {
7172 u8 opcode[0x10];
b4ff3a36 7173 u8 reserved_at_10[0x10];
e281682b 7174
b4ff3a36 7175 u8 reserved_at_20[0x10];
e281682b
SM		 7176 u8 op_mod[0x10];
7177
b4ff3a36 7178 u8 reserved_at_40[0x4];
e281682b
SM		 7179 u8 min_delay[0xc];
7180 u8 int_vector[0x10];
7181
b4ff3a36 7182 u8 reserved_at_60[0x20];
e281682b
SM		 7183};
7184
7185struct mlx5_ifc_attach_to_mcg_out_bits {
7186 u8 status[0x8];
b4ff3a36 7187 u8 reserved_at_8[0x18];
e281682b
SM		 7188
7189 u8 syndrome[0x20];
7190
b4ff3a36 7191 u8 reserved_at_40[0x40];
e281682b
SM		 7192};
7193
7194struct mlx5_ifc_attach_to_mcg_in_bits {
7195 u8 opcode[0x10];
b4ff3a36 7196 u8 reserved_at_10[0x10];
e281682b 7197
b4ff3a36 7198 u8 reserved_at_20[0x10];
e281682b
SM		 7199 u8 op_mod[0x10];
7200
b4ff3a36 7201 u8 reserved_at_40[0x8];
e281682b
SM		 7202 u8 qpn[0x18];
7203
b4ff3a36 7204 u8 reserved_at_60[0x20];
e281682b
SM		 7205
7206 u8 multicast_gid[16][0x8];
7207};
7208
7486216b
SM		 7209struct mlx5_ifc_arm_xrq_out_bits {
7210 u8 status[0x8];
7211 u8 reserved_at_8[0x18];
7212
7213 u8 syndrome[0x20];
7214
7215 u8 reserved_at_40[0x40];
7216};
7217
7218struct mlx5_ifc_arm_xrq_in_bits {
7219 u8 opcode[0x10];
7220 u8 reserved_at_10[0x10];
7221
7222 u8 reserved_at_20[0x10];
7223 u8 op_mod[0x10];
7224
7225 u8 reserved_at_40[0x8];
7226 u8 xrqn[0x18];
7227
7228 u8 reserved_at_60[0x10];
7229 u8 lwm[0x10];
7230};
7231
e281682b
SM		 7232struct mlx5_ifc_arm_xrc_srq_out_bits {
7233 u8 status[0x8];
b4ff3a36 7234 u8 reserved_at_8[0x18];
e281682b
SM		 7235
7236 u8 syndrome[0x20];
7237
b4ff3a36 7238 u8 reserved_at_40[0x40];
e281682b
SM		 7239};
7240
7241enum {
7242 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7243};
7244
7245struct mlx5_ifc_arm_xrc_srq_in_bits {
7246 u8 opcode[0x10];
b4ff3a36 7247 u8 reserved_at_10[0x10];
e281682b 7248
b4ff3a36 7249 u8 reserved_at_20[0x10];
e281682b
SM		 7250 u8 op_mod[0x10];
7251
b4ff3a36 7252 u8 reserved_at_40[0x8];
e281682b
SM		 7253 u8 xrc_srqn[0x18];
7254
b4ff3a36 7255 u8 reserved_at_60[0x10];
e281682b
SM		 7256 u8 lwm[0x10];
7257};
7258
7259struct mlx5_ifc_arm_rq_out_bits {
7260 u8 status[0x8];
b4ff3a36 7261 u8 reserved_at_8[0x18];
e281682b
SM		 7262
7263 u8 syndrome[0x20];
7264
b4ff3a36 7265 u8 reserved_at_40[0x40];
e281682b
SM		 7266};
7267
7268enum {
7486216b
SM		 7269 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7270 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7271};
7272
7273struct mlx5_ifc_arm_rq_in_bits {
7274 u8 opcode[0x10];
b4ff3a36 7275 u8 reserved_at_10[0x10];
e281682b 7276
b4ff3a36 7277 u8 reserved_at_20[0x10];
e281682b
SM		 7278 u8 op_mod[0x10];
7279
b4ff3a36 7280 u8 reserved_at_40[0x8];
e281682b
SM		 7281 u8 srq_number[0x18];
7282
b4ff3a36 7283 u8 reserved_at_60[0x10];
e281682b
SM		 7284 u8 lwm[0x10];
7285};
7286
7287struct mlx5_ifc_arm_dct_out_bits {
7288 u8 status[0x8];
b4ff3a36 7289 u8 reserved_at_8[0x18];
e281682b
SM		 7290
7291 u8 syndrome[0x20];
7292
b4ff3a36 7293 u8 reserved_at_40[0x40];
e281682b
SM		 7294};
7295
7296struct mlx5_ifc_arm_dct_in_bits {
7297 u8 opcode[0x10];
b4ff3a36 7298 u8 reserved_at_10[0x10];
e281682b 7299
b4ff3a36 7300 u8 reserved_at_20[0x10];
e281682b
SM		 7301 u8 op_mod[0x10];
7302
b4ff3a36 7303 u8 reserved_at_40[0x8];
e281682b
SM		 7304 u8 dct_number[0x18];
7305
b4ff3a36 7306 u8 reserved_at_60[0x20];
e281682b
SM		 7307};
7308
7309struct mlx5_ifc_alloc_xrcd_out_bits {
7310 u8 status[0x8];
b4ff3a36 7311 u8 reserved_at_8[0x18];
e281682b
SM		 7312
7313 u8 syndrome[0x20];
7314
b4ff3a36 7315 u8 reserved_at_40[0x8];
e281682b
SM		 7316 u8 xrcd[0x18];
7317
b4ff3a36 7318 u8 reserved_at_60[0x20];
e281682b
SM		 7319};
7320
7321struct mlx5_ifc_alloc_xrcd_in_bits {
7322 u8 opcode[0x10];
b4ff3a36 7323 u8 reserved_at_10[0x10];
e281682b 7324
b4ff3a36 7325 u8 reserved_at_20[0x10];
e281682b
SM		 7326 u8 op_mod[0x10];
7327
b4ff3a36 7328 u8 reserved_at_40[0x40];
e281682b
SM		 7329};
7330
7331struct mlx5_ifc_alloc_uar_out_bits {
7332 u8 status[0x8];
b4ff3a36 7333 u8 reserved_at_8[0x18];
e281682b
SM		 7334
7335 u8 syndrome[0x20];
7336
b4ff3a36 7337 u8 reserved_at_40[0x8];
e281682b
SM		 7338 u8 uar[0x18];
7339
b4ff3a36 7340 u8 reserved_at_60[0x20];
e281682b
SM		 7341};
7342
7343struct mlx5_ifc_alloc_uar_in_bits {
7344 u8 opcode[0x10];
b4ff3a36 7345 u8 reserved_at_10[0x10];
e281682b 7346
b4ff3a36 7347 u8 reserved_at_20[0x10];
e281682b
SM		 7348 u8 op_mod[0x10];
7349
b4ff3a36 7350 u8 reserved_at_40[0x40];
e281682b
SM		 7351};
7352
7353struct mlx5_ifc_alloc_transport_domain_out_bits {
7354 u8 status[0x8];
b4ff3a36 7355 u8 reserved_at_8[0x18];
e281682b
SM		 7356
7357 u8 syndrome[0x20];
7358
b4ff3a36 7359 u8 reserved_at_40[0x8];
e281682b
SM		 7360 u8 transport_domain[0x18];
7361
b4ff3a36 7362 u8 reserved_at_60[0x20];
e281682b
SM		 7363};
7364
7365struct mlx5_ifc_alloc_transport_domain_in_bits {
7366 u8 opcode[0x10];
b4ff3a36 7367 u8 reserved_at_10[0x10];
e281682b 7368
b4ff3a36 7369 u8 reserved_at_20[0x10];
e281682b
SM		 7370 u8 op_mod[0x10];
7371
b4ff3a36 7372 u8 reserved_at_40[0x40];
e281682b
SM		 7373};
7374
7375struct mlx5_ifc_alloc_q_counter_out_bits {
7376 u8 status[0x8];
b4ff3a36 7377 u8 reserved_at_8[0x18];
e281682b
SM		 7378
7379 u8 syndrome[0x20];
7380
b4ff3a36 7381 u8 reserved_at_40[0x18];
e281682b
SM		 7382 u8 counter_set_id[0x8];
7383
b4ff3a36 7384 u8 reserved_at_60[0x20];
e281682b
SM		 7385};
7386
7387struct mlx5_ifc_alloc_q_counter_in_bits {
7388 u8 opcode[0x10];
b4ff3a36 7389 u8 reserved_at_10[0x10];
e281682b 7390
b4ff3a36 7391 u8 reserved_at_20[0x10];
e281682b
SM		 7392 u8 op_mod[0x10];
7393
b4ff3a36 7394 u8 reserved_at_40[0x40];
e281682b
SM		 7395};
7396
7397struct mlx5_ifc_alloc_pd_out_bits {
7398 u8 status[0x8];
b4ff3a36 7399 u8 reserved_at_8[0x18];
e281682b
SM		 7400
7401 u8 syndrome[0x20];
7402
b4ff3a36 7403 u8 reserved_at_40[0x8];
e281682b
SM		 7404 u8 pd[0x18];
7405
b4ff3a36 7406 u8 reserved_at_60[0x20];
e281682b
SM		 7407};
7408
7409struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7410 u8 opcode[0x10];
7411 u8 reserved_at_10[0x10];
7412
7413 u8 reserved_at_20[0x10];
7414 u8 op_mod[0x10];
7415
7416 u8 reserved_at_40[0x40];
7417};
7418
7419struct mlx5_ifc_alloc_flow_counter_out_bits {
7420 u8 status[0x8];
7421 u8 reserved_at_8[0x18];
7422
7423 u8 syndrome[0x20];
7424
a8ffcc74 7425 u8 flow_counter_id[0x20];
9dc0b289
AV		 7426
7427 u8 reserved_at_60[0x20];
7428};
7429
7430struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7431 u8 opcode[0x10];
b4ff3a36 7432 u8 reserved_at_10[0x10];
e281682b 7433
b4ff3a36 7434 u8 reserved_at_20[0x10];
e281682b
SM		 7435 u8 op_mod[0x10];
7436
b4ff3a36 7437 u8 reserved_at_40[0x40];
e281682b
SM		 7438};
7439
7440struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7441 u8 status[0x8];
b4ff3a36 7442 u8 reserved_at_8[0x18];
e281682b
SM		 7443
7444 u8 syndrome[0x20];
7445
b4ff3a36 7446 u8 reserved_at_40[0x40];
e281682b
SM		 7447};
7448
7449struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7450 u8 opcode[0x10];
b4ff3a36 7451 u8 reserved_at_10[0x10];
e281682b 7452
b4ff3a36 7453 u8 reserved_at_20[0x10];
e281682b
SM		 7454 u8 op_mod[0x10];
7455
b4ff3a36 7456 u8 reserved_at_40[0x20];
e281682b 7457
b4ff3a36 7458 u8 reserved_at_60[0x10];
e281682b
SM		 7459 u8 vxlan_udp_port[0x10];
7460};
7461
37e92a9d 7462struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7463 u8 status[0x8];
7464 u8 reserved_at_8[0x18];
7465
7466 u8 syndrome[0x20];
7467
7468 u8 reserved_at_40[0x40];
7469};
7470
37e92a9d 7471struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7472 u8 opcode[0x10];
7473 u8 reserved_at_10[0x10];
7474
7475 u8 reserved_at_20[0x10];
7476 u8 op_mod[0x10];
7477
7478 u8 reserved_at_40[0x10];
7479 u8 rate_limit_index[0x10];
7480
7481 u8 reserved_at_60[0x20];
7482
7483 u8 rate_limit[0x20];
37e92a9d 7484
05d3ac97
BW		 7485 u8 burst_upper_bound[0x20];
7486
7487 u8 reserved_at_c0[0x10];
7488 u8 typical_packet_size[0x10];
7489
7490 u8 reserved_at_e0[0x120];
7486216b
SM		 7491};
7492
e281682b
SM		 7493struct mlx5_ifc_access_register_out_bits {
7494 u8 status[0x8];
b4ff3a36 7495 u8 reserved_at_8[0x18];
e281682b
SM		 7496
7497 u8 syndrome[0x20];
7498
b4ff3a36 7499 u8 reserved_at_40[0x40];
e281682b
SM		 7500
7501 u8 register_data[0][0x20];
7502};
7503
7504enum {
7505 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7506 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7507};
7508
7509struct mlx5_ifc_access_register_in_bits {
7510 u8 opcode[0x10];
b4ff3a36 7511 u8 reserved_at_10[0x10];
e281682b 7512
b4ff3a36 7513 u8 reserved_at_20[0x10];
e281682b
SM		 7514 u8 op_mod[0x10];
7515
b4ff3a36 7516 u8 reserved_at_40[0x10];
e281682b
SM		 7517 u8 register_id[0x10];
7518
7519 u8 argument[0x20];
7520
7521 u8 register_data[0][0x20];
7522};
7523
7524struct mlx5_ifc_sltp_reg_bits {
7525 u8 status[0x4];
7526 u8 version[0x4];
7527 u8 local_port[0x8];
7528 u8 pnat[0x2];
b4ff3a36 7529 u8 reserved_at_12[0x2];
e281682b 7530 u8 lane[0x4];
b4ff3a36 7531 u8 reserved_at_18[0x8];
e281682b 7532
b4ff3a36 7533 u8 reserved_at_20[0x20];
e281682b 7534
b4ff3a36 7535 u8 reserved_at_40[0x7];
e281682b
SM		 7536 u8 polarity[0x1];
7537 u8 ob_tap0[0x8];
7538 u8 ob_tap1[0x8];
7539 u8 ob_tap2[0x8];
7540
b4ff3a36 7541 u8 reserved_at_60[0xc];
e281682b
SM		 7542 u8 ob_preemp_mode[0x4];
7543 u8 ob_reg[0x8];
7544 u8 ob_bias[0x8];
7545
b4ff3a36 7546 u8 reserved_at_80[0x20];
e281682b
SM		 7547};
7548
7549struct mlx5_ifc_slrg_reg_bits {
7550 u8 status[0x4];
7551 u8 version[0x4];
7552 u8 local_port[0x8];
7553 u8 pnat[0x2];
b4ff3a36 7554 u8 reserved_at_12[0x2];
e281682b 7555 u8 lane[0x4];
b4ff3a36 7556 u8 reserved_at_18[0x8];
e281682b
SM		 7557
7558 u8 time_to_link_up[0x10];
b4ff3a36 7559 u8 reserved_at_30[0xc];
e281682b
SM		 7560 u8 grade_lane_speed[0x4];
7561
7562 u8 grade_version[0x8];
7563 u8 grade[0x18];
7564
b4ff3a36 7565 u8 reserved_at_60[0x4];
e281682b
SM		 7566 u8 height_grade_type[0x4];
7567 u8 height_grade[0x18];
7568
7569 u8 height_dz[0x10];
7570 u8 height_dv[0x10];
7571
b4ff3a36 7572 u8 reserved_at_a0[0x10];
e281682b
SM		 7573 u8 height_sigma[0x10];
7574
b4ff3a36 7575 u8 reserved_at_c0[0x20];
e281682b 7576
b4ff3a36 7577 u8 reserved_at_e0[0x4];
e281682b
SM		 7578 u8 phase_grade_type[0x4];
7579 u8 phase_grade[0x18];
7580
b4ff3a36 7581 u8 reserved_at_100[0x8];
e281682b 7582 u8 phase_eo_pos[0x8];
b4ff3a36 7583 u8 reserved_at_110[0x8];
e281682b
SM		 7584 u8 phase_eo_neg[0x8];
7585
7586 u8 ffe_set_tested[0x10];
7587 u8 test_errors_per_lane[0x10];
7588};
7589
7590struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7591 u8 reserved_at_0[0x8];
e281682b 7592 u8 local_port[0x8];
b4ff3a36 7593 u8 reserved_at_10[0x10];
e281682b 7594
b4ff3a36 7595 u8 reserved_at_20[0x1c];
e281682b
SM		 7596 u8 vl_hw_cap[0x4];
7597
b4ff3a36 7598 u8 reserved_at_40[0x1c];
e281682b
SM		 7599 u8 vl_admin[0x4];
7600
b4ff3a36 7601 u8 reserved_at_60[0x1c];
e281682b
SM		 7602 u8 vl_operational[0x4];
7603};
7604
7605struct mlx5_ifc_pude_reg_bits {
7606 u8 swid[0x8];
7607 u8 local_port[0x8];
b4ff3a36 7608 u8 reserved_at_10[0x4];
e281682b 7609 u8 admin_status[0x4];
b4ff3a36 7610 u8 reserved_at_18[0x4];
e281682b
SM		 7611 u8 oper_status[0x4];
7612
b4ff3a36 7613 u8 reserved_at_20[0x60];
e281682b
SM		 7614};
7615
7616struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7617 u8 reserved_at_0[0x1];
7486216b 7618 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7619 u8 an_disable_cap[0x1];
7620 u8 reserved_at_3[0x5];
e281682b 7621 u8 local_port[0x8];
b4ff3a36 7622 u8 reserved_at_10[0xd];
e281682b
SM		 7623 u8 proto_mask[0x3];
7624
7486216b
SM		 7625 u8 an_status[0x4];
7626 u8 reserved_at_24[0x3c];
e281682b
SM		 7627
7628 u8 eth_proto_capability[0x20];
7629
7630 u8 ib_link_width_capability[0x10];
7631 u8 ib_proto_capability[0x10];
7632
b4ff3a36 7633 u8 reserved_at_a0[0x20];
e281682b
SM		 7634
7635 u8 eth_proto_admin[0x20];
7636
7637 u8 ib_link_width_admin[0x10];
7638 u8 ib_proto_admin[0x10];
7639
b4ff3a36 7640 u8 reserved_at_100[0x20];
e281682b
SM		 7641
7642 u8 eth_proto_oper[0x20];
7643
7644 u8 ib_link_width_oper[0x10];
7645 u8 ib_proto_oper[0x10];
7646
5b4793f8
EBE		 7647 u8 reserved_at_160[0x1c];
7648 u8 connector_type[0x4];
e281682b
SM		 7649
7650 u8 eth_proto_lp_advertise[0x20];
7651
b4ff3a36 7652 u8 reserved_at_1a0[0x60];
e281682b
SM		 7653};
7654
7d5e1423
SM		 7655struct mlx5_ifc_mlcr_reg_bits {
7656 u8 reserved_at_0[0x8];
7657 u8 local_port[0x8];
7658 u8 reserved_at_10[0x20];
7659
7660 u8 beacon_duration[0x10];
7661 u8 reserved_at_40[0x10];
7662
7663 u8 beacon_remain[0x10];
7664};
7665
e281682b 7666struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7667 u8 reserved_at_0[0x20];
e281682b
SM		 7668
7669 u8 algorithm_options[0x10];
b4ff3a36 7670 u8 reserved_at_30[0x4];
e281682b
SM		 7671 u8 repetitions_mode[0x4];
7672 u8 num_of_repetitions[0x8];
7673
7674 u8 grade_version[0x8];
7675 u8 height_grade_type[0x4];
7676 u8 phase_grade_type[0x4];
7677 u8 height_grade_weight[0x8];
7678 u8 phase_grade_weight[0x8];
7679
7680 u8 gisim_measure_bits[0x10];
7681 u8 adaptive_tap_measure_bits[0x10];
7682
7683 u8 ber_bath_high_error_threshold[0x10];
7684 u8 ber_bath_mid_error_threshold[0x10];
7685
7686 u8 ber_bath_low_error_threshold[0x10];
7687 u8 one_ratio_high_threshold[0x10];
7688
7689 u8 one_ratio_high_mid_threshold[0x10];
7690 u8 one_ratio_low_mid_threshold[0x10];
7691
7692 u8 one_ratio_low_threshold[0x10];
7693 u8 ndeo_error_threshold[0x10];
7694
7695 u8 mixer_offset_step_size[0x10];
b4ff3a36 7696 u8 reserved_at_110[0x8];
e281682b
SM		 7697 u8 mix90_phase_for_voltage_bath[0x8];
7698
7699 u8 mixer_offset_start[0x10];
7700 u8 mixer_offset_end[0x10];
7701
b4ff3a36 7702 u8 reserved_at_140[0x15];
e281682b
SM		 7703 u8 ber_test_time[0xb];
7704};
7705
7706struct mlx5_ifc_pspa_reg_bits {
7707 u8 swid[0x8];
7708 u8 local_port[0x8];
7709 u8 sub_port[0x8];
b4ff3a36 7710 u8 reserved_at_18[0x8];
e281682b 7711
b4ff3a36 7712 u8 reserved_at_20[0x20];
e281682b
SM		 7713};
7714
7715struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7716 u8 reserved_at_0[0x8];
e281682b 7717 u8 local_port[0x8];
b4ff3a36 7718 u8 reserved_at_10[0x5];
e281682b 7719 u8 prio[0x3];
b4ff3a36 7720 u8 reserved_at_18[0x6];
e281682b
SM		 7721 u8 mode[0x2];
7722
b4ff3a36 7723 u8 reserved_at_20[0x20];
e281682b 7724
b4ff3a36 7725 u8 reserved_at_40[0x10];
e281682b
SM		 7726 u8 min_threshold[0x10];
7727
b4ff3a36 7728 u8 reserved_at_60[0x10];
e281682b
SM		 7729 u8 max_threshold[0x10];
7730
b4ff3a36 7731 u8 reserved_at_80[0x10];
e281682b
SM		 7732 u8 mark_probability_denominator[0x10];
7733
b4ff3a36 7734 u8 reserved_at_a0[0x60];
e281682b
SM		 7735};
7736
7737struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7738 u8 reserved_at_0[0x8];
e281682b 7739 u8 local_port[0x8];
b4ff3a36 7740 u8 reserved_at_10[0x10];
e281682b 7741
b4ff3a36 7742 u8 reserved_at_20[0x60];
e281682b 7743
b4ff3a36 7744 u8 reserved_at_80[0x1c];
e281682b
SM		 7745 u8 wrps_admin[0x4];
7746
b4ff3a36 7747 u8 reserved_at_a0[0x1c];
e281682b
SM		 7748 u8 wrps_status[0x4];
7749
b4ff3a36 7750 u8 reserved_at_c0[0x8];
e281682b 7751 u8 up_threshold[0x8];
b4ff3a36 7752 u8 reserved_at_d0[0x8];
e281682b
SM		 7753 u8 down_threshold[0x8];
7754
b4ff3a36 7755 u8 reserved_at_e0[0x20];
e281682b 7756
b4ff3a36 7757 u8 reserved_at_100[0x1c];
e281682b
SM		 7758 u8 srps_admin[0x4];
7759
b4ff3a36 7760 u8 reserved_at_120[0x1c];
e281682b
SM		 7761 u8 srps_status[0x4];
7762
b4ff3a36 7763 u8 reserved_at_140[0x40];
e281682b
SM		 7764};
7765
7766struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7767 u8 reserved_at_0[0x8];
e281682b 7768 u8 local_port[0x8];
b4ff3a36 7769 u8 reserved_at_10[0x10];
e281682b 7770
b4ff3a36 7771 u8 reserved_at_20[0x8];
e281682b 7772 u8 lb_cap[0x8];
b4ff3a36 7773 u8 reserved_at_30[0x8];
e281682b
SM		 7774 u8 lb_en[0x8];
7775};
7776
7777struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7778 u8 reserved_at_0[0x8];
e281682b 7779 u8 local_port[0x8];
b4ff3a36 7780 u8 reserved_at_10[0x10];
e281682b 7781
b4ff3a36 7782 u8 reserved_at_20[0x20];
e281682b
SM		 7783
7784 u8 port_profile_mode[0x8];
7785 u8 static_port_profile[0x8];
7786 u8 active_port_profile[0x8];
b4ff3a36 7787 u8 reserved_at_58[0x8];
e281682b
SM		 7788
7789 u8 retransmission_active[0x8];
7790 u8 fec_mode_active[0x18];
7791
b4ff3a36 7792 u8 reserved_at_80[0x20];
e281682b
SM		 7793};
7794
7795struct mlx5_ifc_ppcnt_reg_bits {
7796 u8 swid[0x8];
7797 u8 local_port[0x8];
7798 u8 pnat[0x2];
b4ff3a36 7799 u8 reserved_at_12[0x8];
e281682b
SM		 7800 u8 grp[0x6];
7801
7802 u8 clr[0x1];
b4ff3a36 7803 u8 reserved_at_21[0x1c];
e281682b
SM		 7804 u8 prio_tc[0x3];
7805
7806 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7807};
7808
8ed1a630
GP		 7809struct mlx5_ifc_mpcnt_reg_bits {
7810 u8 reserved_at_0[0x8];
7811 u8 pcie_index[0x8];
7812 u8 reserved_at_10[0xa];
7813 u8 grp[0x6];
7814
7815 u8 clr[0x1];
7816 u8 reserved_at_21[0x1f];
7817
7818 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7819};
7820
e281682b 7821struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7822 u8 reserved_at_0[0x3];
e281682b 7823 u8 single_mac[0x1];
b4ff3a36 7824 u8 reserved_at_4[0x4];
e281682b
SM		 7825 u8 local_port[0x8];
7826 u8 mac_47_32[0x10];
7827
7828 u8 mac_31_0[0x20];
7829
b4ff3a36 7830 u8 reserved_at_40[0x40];
e281682b
SM		 7831};
7832
7833struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7834 u8 reserved_at_0[0x8];
e281682b 7835 u8 local_port[0x8];
b4ff3a36 7836 u8 reserved_at_10[0x10];
e281682b
SM		 7837
7838 u8 max_mtu[0x10];
b4ff3a36 7839 u8 reserved_at_30[0x10];
e281682b
SM		 7840
7841 u8 admin_mtu[0x10];
b4ff3a36 7842 u8 reserved_at_50[0x10];
e281682b
SM		 7843
7844 u8 oper_mtu[0x10];
b4ff3a36 7845 u8 reserved_at_70[0x10];
e281682b
SM		 7846};
7847
7848struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7849 u8 reserved_at_0[0x8];
e281682b 7850 u8 module[0x8];
b4ff3a36 7851 u8 reserved_at_10[0x10];
e281682b 7852
b4ff3a36 7853 u8 reserved_at_20[0x18];
e281682b
SM		 7854 u8 attenuation_5g[0x8];
7855
b4ff3a36 7856 u8 reserved_at_40[0x18];
e281682b
SM		 7857 u8 attenuation_7g[0x8];
7858
b4ff3a36 7859 u8 reserved_at_60[0x18];
e281682b
SM		 7860 u8 attenuation_12g[0x8];
7861};
7862
7863struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7864 u8 reserved_at_0[0x8];
e281682b 7865 u8 module[0x8];
b4ff3a36 7866 u8 reserved_at_10[0xc];
e281682b
SM		 7867 u8 module_status[0x4];
7868
b4ff3a36 7869 u8 reserved_at_20[0x60];
e281682b
SM		 7870};
7871
7872struct mlx5_ifc_pmpc_reg_bits {
7873 u8 module_state_updated[32][0x8];
7874};
7875
7876struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7877 u8 reserved_at_0[0x4];
e281682b
SM		 7878 u8 mlpn_status[0x4];
7879 u8 local_port[0x8];
b4ff3a36 7880 u8 reserved_at_10[0x10];
e281682b
SM		 7881
7882 u8 e[0x1];
b4ff3a36 7883 u8 reserved_at_21[0x1f];
e281682b
SM		 7884};
7885
7886struct mlx5_ifc_pmlp_reg_bits {
7887 u8 rxtx[0x1];
b4ff3a36 7888 u8 reserved_at_1[0x7];
e281682b 7889 u8 local_port[0x8];
b4ff3a36 7890 u8 reserved_at_10[0x8];
e281682b
SM		 7891 u8 width[0x8];
7892
7893 u8 lane0_module_mapping[0x20];
7894
7895 u8 lane1_module_mapping[0x20];
7896
7897 u8 lane2_module_mapping[0x20];
7898
7899 u8 lane3_module_mapping[0x20];
7900
b4ff3a36 7901 u8 reserved_at_a0[0x160];
e281682b
SM		 7902};
7903
7904struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7905 u8 reserved_at_0[0x8];
e281682b 7906 u8 module[0x8];
b4ff3a36 7907 u8 reserved_at_10[0x4];
e281682b 7908 u8 admin_status[0x4];
b4ff3a36 7909 u8 reserved_at_18[0x4];
e281682b
SM		 7910 u8 oper_status[0x4];
7911
7912 u8 ase[0x1];
7913 u8 ee[0x1];
b4ff3a36 7914 u8 reserved_at_22[0x1c];
e281682b
SM		 7915 u8 e[0x2];
7916
b4ff3a36 7917 u8 reserved_at_40[0x40];
e281682b
SM		 7918};
7919
7920struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7921 u8 reserved_at_0[0x4];
e281682b 7922 u8 profile_id[0xc];
b4ff3a36 7923 u8 reserved_at_10[0x4];
e281682b 7924 u8 proto_mask[0x4];
b4ff3a36 7925 u8 reserved_at_18[0x8];
e281682b 7926
b4ff3a36 7927 u8 reserved_at_20[0x10];
e281682b
SM		 7928 u8 lane_speed[0x10];
7929
b4ff3a36 7930 u8 reserved_at_40[0x17];
e281682b
SM		 7931 u8 lpbf[0x1];
7932 u8 fec_mode_policy[0x8];
7933
7934 u8 retransmission_capability[0x8];
7935 u8 fec_mode_capability[0x18];
7936
7937 u8 retransmission_support_admin[0x8];
7938 u8 fec_mode_support_admin[0x18];
7939
7940 u8 retransmission_request_admin[0x8];
7941 u8 fec_mode_request_admin[0x18];
7942
b4ff3a36 7943 u8 reserved_at_c0[0x80];
e281682b
SM		 7944};
7945
7946struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7947 u8 reserved_at_0[0x8];
e281682b 7948 u8 local_port[0x8];
b4ff3a36 7949 u8 reserved_at_10[0x8];
e281682b
SM		 7950 u8 ib_port[0x8];
7951
b4ff3a36 7952 u8 reserved_at_20[0x60];
e281682b
SM		 7953};
7954
7955struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7956 u8 reserved_at_0[0x8];
e281682b 7957 u8 local_port[0x8];
b4ff3a36 7958 u8 reserved_at_10[0xd];
e281682b
SM		 7959 u8 lbf_mode[0x3];
7960
b4ff3a36 7961 u8 reserved_at_20[0x20];
e281682b
SM		 7962};
7963
7964struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7965 u8 reserved_at_0[0x8];
e281682b 7966 u8 local_port[0x8];
b4ff3a36 7967 u8 reserved_at_10[0x10];
e281682b
SM		 7968
7969 u8 dic[0x1];
b4ff3a36 7970 u8 reserved_at_21[0x19];
e281682b 7971 u8 ipg[0x4];
b4ff3a36 7972 u8 reserved_at_3e[0x2];
e281682b
SM		 7973};
7974
7975struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7976 u8 reserved_at_0[0x8];
e281682b 7977 u8 local_port[0x8];
b4ff3a36 7978 u8 reserved_at_10[0x10];
e281682b 7979
b4ff3a36 7980 u8 reserved_at_20[0xe0];
e281682b
SM		 7981
7982 u8 port_filter[8][0x20];
7983
7984 u8 port_filter_update_en[8][0x20];
7985};
7986
7987struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7988 u8 reserved_at_0[0x8];
e281682b 7989 u8 local_port[0x8];
2afa609f
IK		 7990 u8 reserved_at_10[0xb];
7991 u8 ppan_mask_n[0x1];
7992 u8 minor_stall_mask[0x1];
7993 u8 critical_stall_mask[0x1];
7994 u8 reserved_at_1e[0x2];
e281682b
SM		 7995
7996 u8 ppan[0x4];
b4ff3a36 7997 u8 reserved_at_24[0x4];
e281682b 7998 u8 prio_mask_tx[0x8];
b4ff3a36 7999 u8 reserved_at_30[0x8];
e281682b
SM		 8000 u8 prio_mask_rx[0x8];
8001
8002 u8 pptx[0x1];
8003 u8 aptx[0x1];
2afa609f
IK		 8004 u8 pptx_mask_n[0x1];
8005 u8 reserved_at_43[0x5];
e281682b 8006 u8 pfctx[0x8];
b4ff3a36 8007 u8 reserved_at_50[0x10];
e281682b
SM		 8008
8009 u8 pprx[0x1];
8010 u8 aprx[0x1];
2afa609f
IK		 8011 u8 pprx_mask_n[0x1];
8012 u8 reserved_at_63[0x5];
e281682b 8013 u8 pfcrx[0x8];
b4ff3a36 8014 u8 reserved_at_70[0x10];
e281682b 8015
2afa609f
IK		 8016 u8 device_stall_minor_watermark[0x10];
8017 u8 device_stall_critical_watermark[0x10];
8018
8019 u8 reserved_at_a0[0x60];
e281682b
SM		 8020};
8021
8022struct mlx5_ifc_pelc_reg_bits {
8023 u8 op[0x4];
b4ff3a36 8024 u8 reserved_at_4[0x4];
e281682b 8025 u8 local_port[0x8];
b4ff3a36 8026 u8 reserved_at_10[0x10];
e281682b
SM		 8027
8028 u8 op_admin[0x8];
8029 u8 op_capability[0x8];
8030 u8 op_request[0x8];
8031 u8 op_active[0x8];
8032
8033 u8 admin[0x40];
8034
8035 u8 capability[0x40];
8036
8037 u8 request[0x40];
8038
8039 u8 active[0x40];
8040
b4ff3a36 8041 u8 reserved_at_140[0x80];
e281682b
SM		 8042};
8043
8044struct mlx5_ifc_peir_reg_bits {
b4ff3a36 8045 u8 reserved_at_0[0x8];
e281682b 8046 u8 local_port[0x8];
b4ff3a36 8047 u8 reserved_at_10[0x10];
e281682b 8048
b4ff3a36 8049 u8 reserved_at_20[0xc];
e281682b 8050 u8 error_count[0x4];
b4ff3a36 8051 u8 reserved_at_30[0x10];
e281682b 8052
b4ff3a36 8053 u8 reserved_at_40[0xc];
e281682b 8054 u8 lane[0x4];
b4ff3a36 8055 u8 reserved_at_50[0x8];
e281682b
SM		 8056 u8 error_type[0x8];
8057};
8058
5e022dd3
EBE		 8059struct mlx5_ifc_mpegc_reg_bits {
8060 u8 reserved_at_0[0x30];
8061 u8 field_select[0x10];
8062
8063 u8 tx_overflow_sense[0x1];
8064 u8 mark_cqe[0x1];
8065 u8 mark_cnp[0x1];
8066 u8 reserved_at_43[0x1b];
8067 u8 tx_lossy_overflow_oper[0x2];
8068
8069 u8 reserved_at_60[0x100];
8070};
cfdcbcea 8071
cfdcbcea 8072struct mlx5_ifc_pcam_enhanced_features_bits {
0af5107c
TB		 8073 u8 reserved_at_0[0x6d];
8074 u8 rx_icrc_encapsulated_counter[0x1];
8075 u8 reserved_at_6e[0x8];
2fcb12df
IK		 8076 u8 pfcc_mask[0x1];
8077 u8 reserved_at_77[0x4];
2dba0797 8078 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8079 u8 ptys_connector_type[0x1];
8080 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8081 u8 ppcnt_discard_group[0x1];
8082 u8 ppcnt_statistical_group[0x1];
8083};
8084
df5f1361
HN		 8085struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8086 u8 port_access_reg_cap_mask_127_to_96[0x20];
8087 u8 port_access_reg_cap_mask_95_to_64[0x20];
8088 u8 port_access_reg_cap_mask_63_to_32[0x20];
8089
8090 u8 port_access_reg_cap_mask_31_to_13[0x13];
8091 u8 pbmc[0x1];
8092 u8 pptb[0x1];
8093 u8 port_access_reg_cap_mask_10_to_0[0xb];
8094};
8095
cfdcbcea
GP		 8096struct mlx5_ifc_pcam_reg_bits {
8097 u8 reserved_at_0[0x8];
8098 u8 feature_group[0x8];
8099 u8 reserved_at_10[0x8];
8100 u8 access_reg_group[0x8];
8101
8102 u8 reserved_at_20[0x20];
8103
8104 union {
df5f1361 8105 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 8106 u8 reserved_at_0[0x80];
8107 } port_access_reg_cap_mask;
8108
8109 u8 reserved_at_c0[0x80];
8110
8111 union {
8112 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8113 u8 reserved_at_0[0x80];
8114 } feature_cap_mask;
8115
8116 u8 reserved_at_1c0[0xc0];
8117};
8118
8119struct mlx5_ifc_mcam_enhanced_features_bits {
5e022dd3
EBE		 8120 u8 reserved_at_0[0x74];
8121 u8 mark_tx_action_cnp[0x1];
8122 u8 mark_tx_action_cqe[0x1];
8123 u8 dynamic_tx_overflow[0x1];
8124 u8 reserved_at_77[0x4];
5405fa26 8125 u8 pcie_outbound_stalled[0x1];
efae7f78 8126 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8127 u8 mtpps_enh_out_per_adj[0x1];
8128 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8129 u8 pcie_performance_group[0x1];
8130};
8131
0ab87743
OG		 8132struct mlx5_ifc_mcam_access_reg_bits {
8133 u8 reserved_at_0[0x1c];
8134 u8 mcda[0x1];
8135 u8 mcc[0x1];
8136 u8 mcqi[0x1];
8137 u8 reserved_at_1f[0x1];
8138
5e022dd3
EBE		 8139 u8 regs_95_to_87[0x9];
8140 u8 mpegc[0x1];
8141 u8 regs_85_to_68[0x12];
eff8ea8f
FD		 8142 u8 tracer_registers[0x4];
8143
0ab87743
OG		 8144 u8 regs_63_to_32[0x20];
8145 u8 regs_31_to_0[0x20];
8146};
8147
cfdcbcea
GP		 8148struct mlx5_ifc_mcam_reg_bits {
8149 u8 reserved_at_0[0x8];
8150 u8 feature_group[0x8];
8151 u8 reserved_at_10[0x8];
8152 u8 access_reg_group[0x8];
8153
8154 u8 reserved_at_20[0x20];
8155
8156 union {
0ab87743 8157 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8158 u8 reserved_at_0[0x80];
8159 } mng_access_reg_cap_mask;
8160
8161 u8 reserved_at_c0[0x80];
8162
8163 union {
8164 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8165 u8 reserved_at_0[0x80];
8166 } mng_feature_cap_mask;
8167
8168 u8 reserved_at_1c0[0x80];
8169};
8170
c02762eb
HN		 8171struct mlx5_ifc_qcam_access_reg_cap_mask {
8172 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8173 u8 qpdpm[0x1];
8174 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8175 u8 qdpm[0x1];
8176 u8 qpts[0x1];
8177 u8 qcap[0x1];
8178 u8 qcam_access_reg_cap_mask_0[0x1];
8179};
8180
8181struct mlx5_ifc_qcam_qos_feature_cap_mask {
8182 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8183 u8 qpts_trust_both[0x1];
8184};
8185
8186struct mlx5_ifc_qcam_reg_bits {
8187 u8 reserved_at_0[0x8];
8188 u8 feature_group[0x8];
8189 u8 reserved_at_10[0x8];
8190 u8 access_reg_group[0x8];
8191 u8 reserved_at_20[0x20];
8192
8193 union {
8194 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8195 u8 reserved_at_0[0x80];
8196 } qos_access_reg_cap_mask;
8197
8198 u8 reserved_at_c0[0x80];
8199
8200 union {
8201 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8202 u8 reserved_at_0[0x80];
8203 } qos_feature_cap_mask;
8204
8205 u8 reserved_at_1c0[0x80];
8206};
8207
e281682b 8208struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8209 u8 reserved_at_0[0x8];
e281682b 8210 u8 local_port[0x8];
b4ff3a36 8211 u8 reserved_at_10[0x10];
e281682b
SM		 8212
8213 u8 port_capability_mask[4][0x20];
8214};
8215
8216struct mlx5_ifc_paos_reg_bits {
8217 u8 swid[0x8];
8218 u8 local_port[0x8];
b4ff3a36 8219 u8 reserved_at_10[0x4];
e281682b 8220 u8 admin_status[0x4];
b4ff3a36 8221 u8 reserved_at_18[0x4];
e281682b
SM		 8222 u8 oper_status[0x4];
8223
8224 u8 ase[0x1];
8225 u8 ee[0x1];
b4ff3a36 8226 u8 reserved_at_22[0x1c];
e281682b
SM		 8227 u8 e[0x2];
8228
b4ff3a36 8229 u8 reserved_at_40[0x40];
e281682b
SM		 8230};
8231
8232struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8233 u8 reserved_at_0[0x8];
e281682b 8234 u8 opamp_group[0x8];
b4ff3a36 8235 u8 reserved_at_10[0xc];
e281682b
SM		 8236 u8 opamp_group_type[0x4];
8237
8238 u8 start_index[0x10];
b4ff3a36 8239 u8 reserved_at_30[0x4];
e281682b
SM		 8240 u8 num_of_indices[0xc];
8241
8242 u8 index_data[18][0x10];
8243};
8244
7d5e1423
SM		 8245struct mlx5_ifc_pcmr_reg_bits {
8246 u8 reserved_at_0[0x8];
8247 u8 local_port[0x8];
8248 u8 reserved_at_10[0x2e];
8249 u8 fcs_cap[0x1];
8250 u8 reserved_at_3f[0x1f];
8251 u8 fcs_chk[0x1];
8252 u8 reserved_at_5f[0x1];
8253};
8254
e281682b 8255struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8256 u8 reserved_at_0[0x6];
e281682b 8257 u8 rx_lane[0x2];
b4ff3a36 8258 u8 reserved_at_8[0x6];
e281682b 8259 u8 tx_lane[0x2];
b4ff3a36 8260 u8 reserved_at_10[0x8];
e281682b
SM		 8261 u8 module[0x8];
8262};
8263
8264struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8265 u8 reserved_at_0[0x6];
e281682b
SM		 8266 u8 lossy[0x1];
8267 u8 epsb[0x1];
b4ff3a36 8268 u8 reserved_at_8[0xc];
e281682b
SM		 8269 u8 size[0xc];
8270
8271 u8 xoff_threshold[0x10];
8272 u8 xon_threshold[0x10];
8273};
8274
8275struct mlx5_ifc_set_node_in_bits {
8276 u8 node_description[64][0x8];
8277};
8278
8279struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8280 u8 reserved_at_0[0x18];
e281682b
SM		 8281 u8 power_settings_level[0x8];
8282
b4ff3a36 8283 u8 reserved_at_20[0x60];
e281682b
SM		 8284};
8285
8286struct mlx5_ifc_register_host_endianness_bits {
8287 u8 he[0x1];
b4ff3a36 8288 u8 reserved_at_1[0x1f];
e281682b 8289
b4ff3a36 8290 u8 reserved_at_20[0x60];
e281682b
SM		 8291};
8292
8293struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8294 u8 reserved_at_0[0x20];
e281682b
SM		 8295
8296 u8 mkey[0x20];
8297
8298 u8 addressh_63_32[0x20];
8299
8300 u8 addressl_31_0[0x20];
8301};
8302
8303struct mlx5_ifc_ud_adrs_vector_bits {
8304 u8 dc_key[0x40];
8305
8306 u8 ext[0x1];
b4ff3a36 8307 u8 reserved_at_41[0x7];
e281682b
SM		 8308 u8 destination_qp_dct[0x18];
8309
8310 u8 static_rate[0x4];
8311 u8 sl_eth_prio[0x4];
8312 u8 fl[0x1];
8313 u8 mlid[0x7];
8314 u8 rlid_udp_sport[0x10];
8315
b4ff3a36 8316 u8 reserved_at_80[0x20];
e281682b
SM		 8317
8318 u8 rmac_47_16[0x20];
8319
8320 u8 rmac_15_0[0x10];
8321 u8 tclass[0x8];
8322 u8 hop_limit[0x8];
8323
b4ff3a36 8324 u8 reserved_at_e0[0x1];
e281682b 8325 u8 grh[0x1];
b4ff3a36 8326 u8 reserved_at_e2[0x2];
e281682b
SM		 8327 u8 src_addr_index[0x8];
8328 u8 flow_label[0x14];
8329
8330 u8 rgid_rip[16][0x8];
8331};
8332
8333struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8334 u8 reserved_at_0[0x10];
e281682b
SM		 8335 u8 function_id[0x10];
8336
8337 u8 num_pages[0x20];
8338
b4ff3a36 8339 u8 reserved_at_40[0xa0];
e281682b
SM		 8340};
8341
8342struct mlx5_ifc_eqe_bits {
b4ff3a36 8343 u8 reserved_at_0[0x8];
e281682b 8344 u8 event_type[0x8];
b4ff3a36 8345 u8 reserved_at_10[0x8];
e281682b
SM		 8346 u8 event_sub_type[0x8];
8347
b4ff3a36 8348 u8 reserved_at_20[0xe0];
e281682b
SM		 8349
8350 union mlx5_ifc_event_auto_bits event_data;
8351
b4ff3a36 8352 u8 reserved_at_1e0[0x10];
e281682b 8353 u8 signature[0x8];
b4ff3a36 8354 u8 reserved_at_1f8[0x7];
e281682b
SM		 8355 u8 owner[0x1];
8356};
8357
8358enum {
8359 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8360};
8361
8362struct mlx5_ifc_cmd_queue_entry_bits {
8363 u8 type[0x8];
b4ff3a36 8364 u8 reserved_at_8[0x18];
e281682b
SM		 8365
8366 u8 input_length[0x20];
8367
8368 u8 input_mailbox_pointer_63_32[0x20];
8369
8370 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8371 u8 reserved_at_77[0x9];
e281682b
SM		 8372
8373 u8 command_input_inline_data[16][0x8];
8374
8375 u8 command_output_inline_data[16][0x8];
8376
8377 u8 output_mailbox_pointer_63_32[0x20];
8378
8379 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8380 u8 reserved_at_1b7[0x9];
e281682b
SM		 8381
8382 u8 output_length[0x20];
8383
8384 u8 token[0x8];
8385 u8 signature[0x8];
b4ff3a36 8386 u8 reserved_at_1f0[0x8];
e281682b
SM		 8387 u8 status[0x7];
8388 u8 ownership[0x1];
8389};
8390
8391struct mlx5_ifc_cmd_out_bits {
8392 u8 status[0x8];
b4ff3a36 8393 u8 reserved_at_8[0x18];
e281682b
SM		 8394
8395 u8 syndrome[0x20];
8396
8397 u8 command_output[0x20];
8398};
8399
8400struct mlx5_ifc_cmd_in_bits {
8401 u8 opcode[0x10];
b4ff3a36 8402 u8 reserved_at_10[0x10];
e281682b 8403
b4ff3a36 8404 u8 reserved_at_20[0x10];
e281682b
SM		 8405 u8 op_mod[0x10];
8406
8407 u8 command[0][0x20];
8408};
8409
8410struct mlx5_ifc_cmd_if_box_bits {
8411 u8 mailbox_data[512][0x8];
8412
b4ff3a36 8413 u8 reserved_at_1000[0x180];
e281682b
SM		 8414
8415 u8 next_pointer_63_32[0x20];
8416
8417 u8 next_pointer_31_10[0x16];
b4ff3a36 8418 u8 reserved_at_11b6[0xa];
e281682b
SM		 8419
8420 u8 block_number[0x20];
8421
b4ff3a36 8422 u8 reserved_at_11e0[0x8];
e281682b
SM		 8423 u8 token[0x8];
8424 u8 ctrl_signature[0x8];
8425 u8 signature[0x8];
8426};
8427
8428struct mlx5_ifc_mtt_bits {
8429 u8 ptag_63_32[0x20];
8430
8431 u8 ptag_31_8[0x18];
b4ff3a36 8432 u8 reserved_at_38[0x6];
e281682b
SM		 8433 u8 wr_en[0x1];
8434 u8 rd_en[0x1];
8435};
8436
928cfe87
TT		 8437struct mlx5_ifc_query_wol_rol_out_bits {
8438 u8 status[0x8];
8439 u8 reserved_at_8[0x18];
8440
8441 u8 syndrome[0x20];
8442
8443 u8 reserved_at_40[0x10];
8444 u8 rol_mode[0x8];
8445 u8 wol_mode[0x8];
8446
8447 u8 reserved_at_60[0x20];
8448};
8449
8450struct mlx5_ifc_query_wol_rol_in_bits {
8451 u8 opcode[0x10];
8452 u8 reserved_at_10[0x10];
8453
8454 u8 reserved_at_20[0x10];
8455 u8 op_mod[0x10];
8456
8457 u8 reserved_at_40[0x40];
8458};
8459
8460struct mlx5_ifc_set_wol_rol_out_bits {
8461 u8 status[0x8];
8462 u8 reserved_at_8[0x18];
8463
8464 u8 syndrome[0x20];
8465
8466 u8 reserved_at_40[0x40];
8467};
8468
8469struct mlx5_ifc_set_wol_rol_in_bits {
8470 u8 opcode[0x10];
8471 u8 reserved_at_10[0x10];
8472
8473 u8 reserved_at_20[0x10];
8474 u8 op_mod[0x10];
8475
8476 u8 rol_mode_valid[0x1];
8477 u8 wol_mode_valid[0x1];
8478 u8 reserved_at_42[0xe];
8479 u8 rol_mode[0x8];
8480 u8 wol_mode[0x8];
8481
8482 u8 reserved_at_60[0x20];
8483};
8484
e281682b
SM		 8485enum {
8486 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8487 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8488 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8489};
8490
8491enum {
8492 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8493 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8494 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8495};
8496
8497enum {
8498 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8499 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8500 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8501 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8502 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8503 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8504 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8505 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8506 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8507 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8508 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8509};
8510
8511struct mlx5_ifc_initial_seg_bits {
8512 u8 fw_rev_minor[0x10];
8513 u8 fw_rev_major[0x10];
8514
8515 u8 cmd_interface_rev[0x10];
8516 u8 fw_rev_subminor[0x10];
8517
b4ff3a36 8518 u8 reserved_at_40[0x40];
e281682b
SM		 8519
8520 u8 cmdq_phy_addr_63_32[0x20];
8521
8522 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8523 u8 reserved_at_b4[0x2];
e281682b
SM		 8524 u8 nic_interface[0x2];
8525 u8 log_cmdq_size[0x4];
8526 u8 log_cmdq_stride[0x4];
8527
8528 u8 command_doorbell_vector[0x20];
8529
b4ff3a36 8530 u8 reserved_at_e0[0xf00];
e281682b
SM		 8531
8532 u8 initializing[0x1];
b4ff3a36 8533 u8 reserved_at_fe1[0x4];
e281682b 8534 u8 nic_interface_supported[0x3];
b4ff3a36 8535 u8 reserved_at_fe8[0x18];
e281682b
SM		 8536
8537 struct mlx5_ifc_health_buffer_bits health_buffer;
8538
8539 u8 no_dram_nic_offset[0x20];
8540
b4ff3a36 8541 u8 reserved_at_1220[0x6e40];
e281682b 8542
b4ff3a36 8543 u8 reserved_at_8060[0x1f];
e281682b
SM		 8544 u8 clear_int[0x1];
8545
8546 u8 health_syndrome[0x8];
8547 u8 health_counter[0x18];
8548
b4ff3a36 8549 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8550};
8551
f9a1ef72
EE		 8552struct mlx5_ifc_mtpps_reg_bits {
8553 u8 reserved_at_0[0xc];
8554 u8 cap_number_of_pps_pins[0x4];
8555 u8 reserved_at_10[0x4];
8556 u8 cap_max_num_of_pps_in_pins[0x4];
8557 u8 reserved_at_18[0x4];
8558 u8 cap_max_num_of_pps_out_pins[0x4];
8559
8560 u8 reserved_at_20[0x24];
8561 u8 cap_pin_3_mode[0x4];
8562 u8 reserved_at_48[0x4];
8563 u8 cap_pin_2_mode[0x4];
8564 u8 reserved_at_50[0x4];
8565 u8 cap_pin_1_mode[0x4];
8566 u8 reserved_at_58[0x4];
8567 u8 cap_pin_0_mode[0x4];
8568
8569 u8 reserved_at_60[0x4];
8570 u8 cap_pin_7_mode[0x4];
8571 u8 reserved_at_68[0x4];
8572 u8 cap_pin_6_mode[0x4];
8573 u8 reserved_at_70[0x4];
8574 u8 cap_pin_5_mode[0x4];
8575 u8 reserved_at_78[0x4];
8576 u8 cap_pin_4_mode[0x4];
8577
fa367688
EE		 8578 u8 field_select[0x20];
8579 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8580
8581 u8 enable[0x1];
8582 u8 reserved_at_101[0xb];
8583 u8 pattern[0x4];
8584 u8 reserved_at_110[0x4];
8585 u8 pin_mode[0x4];
8586 u8 pin[0x8];
8587
8588 u8 reserved_at_120[0x20];
8589
8590 u8 time_stamp[0x40];
8591
8592 u8 out_pulse_duration[0x10];
8593 u8 out_periodic_adjustment[0x10];
fa367688 8594 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8595
fa367688 8596 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8597};
8598
8599struct mlx5_ifc_mtppse_reg_bits {
8600 u8 reserved_at_0[0x18];
8601 u8 pin[0x8];
8602 u8 event_arm[0x1];
8603 u8 reserved_at_21[0x1b];
8604 u8 event_generation_mode[0x4];
8605 u8 reserved_at_40[0x40];
8606};
8607
47176289
OG		 8608struct mlx5_ifc_mcqi_cap_bits {
8609 u8 supported_info_bitmask[0x20];
8610
8611 u8 component_size[0x20];
8612
8613 u8 max_component_size[0x20];
8614
8615 u8 log_mcda_word_size[0x4];
8616 u8 reserved_at_64[0xc];
8617 u8 mcda_max_write_size[0x10];
8618
8619 u8 rd_en[0x1];
8620 u8 reserved_at_81[0x1];
8621 u8 match_chip_id[0x1];
8622 u8 match_psid[0x1];
8623 u8 check_user_timestamp[0x1];
8624 u8 match_base_guid_mac[0x1];
8625 u8 reserved_at_86[0x1a];
8626};
8627
8628struct mlx5_ifc_mcqi_reg_bits {
8629 u8 read_pending_component[0x1];
8630 u8 reserved_at_1[0xf];
8631 u8 component_index[0x10];
8632
8633 u8 reserved_at_20[0x20];
8634
8635 u8 reserved_at_40[0x1b];
8636 u8 info_type[0x5];
8637
8638 u8 info_size[0x20];
8639
8640 u8 offset[0x20];
8641
8642 u8 reserved_at_a0[0x10];
8643 u8 data_size[0x10];
8644
8645 u8 data[0][0x20];
8646};
8647
8648struct mlx5_ifc_mcc_reg_bits {
8649 u8 reserved_at_0[0x4];
8650 u8 time_elapsed_since_last_cmd[0xc];
8651 u8 reserved_at_10[0x8];
8652 u8 instruction[0x8];
8653
8654 u8 reserved_at_20[0x10];
8655 u8 component_index[0x10];
8656
8657 u8 reserved_at_40[0x8];
8658 u8 update_handle[0x18];
8659
8660 u8 handle_owner_type[0x4];
8661 u8 handle_owner_host_id[0x4];
8662 u8 reserved_at_68[0x1];
8663 u8 control_progress[0x7];
8664 u8 error_code[0x8];
8665 u8 reserved_at_78[0x4];
8666 u8 control_state[0x4];
8667
8668 u8 component_size[0x20];
8669
8670 u8 reserved_at_a0[0x60];
8671};
8672
8673struct mlx5_ifc_mcda_reg_bits {
8674 u8 reserved_at_0[0x8];
8675 u8 update_handle[0x18];
8676
8677 u8 offset[0x20];
8678
8679 u8 reserved_at_40[0x10];
8680 u8 size[0x10];
8681
8682 u8 reserved_at_60[0x20];
8683
8684 u8 data[0][0x20];
8685};
8686
e281682b
SM		 8687union mlx5_ifc_ports_control_registers_document_bits {
8688 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8689 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8690 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8691 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8692 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8693 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8694 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8695 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8696 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8697 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8698 struct mlx5_ifc_paos_reg_bits paos_reg;
8699 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8700 struct mlx5_ifc_peir_reg_bits peir_reg;
8701 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8702 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8703 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8704 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8705 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8706 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8707 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8708 struct mlx5_ifc_plib_reg_bits plib_reg;
8709 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8710 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8711 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8712 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8713 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8714 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8715 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8716 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8717 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8718 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8719 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8720 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8721 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8722 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8723 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8724 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8725 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8726 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8727 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8728 struct mlx5_ifc_pude_reg_bits pude_reg;
8729 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8730 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8731 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8732 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8733 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8734 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8735 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8736 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8737 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8738 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8739 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8740 u8 reserved_at_0[0x60e0];
e281682b
SM		 8741};
8742
8743union mlx5_ifc_debug_enhancements_document_bits {
8744 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8745 u8 reserved_at_0[0x200];
e281682b
SM		 8746};
8747
8748union mlx5_ifc_uplink_pci_interface_document_bits {
8749 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8750 u8 reserved_at_0[0x20060];
b775516b
EC		 8751};
8752
2cc43b49
MG		 8753struct mlx5_ifc_set_flow_table_root_out_bits {
8754 u8 status[0x8];
b4ff3a36 8755 u8 reserved_at_8[0x18];
2cc43b49
MG		 8756
8757 u8 syndrome[0x20];
8758
b4ff3a36 8759 u8 reserved_at_40[0x40];
2cc43b49
MG		 8760};
8761
8762struct mlx5_ifc_set_flow_table_root_in_bits {
8763 u8 opcode[0x10];
b4ff3a36 8764 u8 reserved_at_10[0x10];
2cc43b49 8765
b4ff3a36 8766 u8 reserved_at_20[0x10];
2cc43b49
MG		 8767 u8 op_mod[0x10];
8768
7d5e1423
SM		 8769 u8 other_vport[0x1];
8770 u8 reserved_at_41[0xf];
8771 u8 vport_number[0x10];
8772
8773 u8 reserved_at_60[0x20];
2cc43b49
MG		 8774
8775 u8 table_type[0x8];
b4ff3a36 8776 u8 reserved_at_88[0x18];
2cc43b49 8777
b4ff3a36 8778 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8779 u8 table_id[0x18];
8780
500a3d0d
ES		 8781 u8 reserved_at_c0[0x8];
8782 u8 underlay_qpn[0x18];
8783 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8784};
8785
34a40e68 8786enum {
84df61eb
AH		 8787 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8788 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8789};
8790
8791struct mlx5_ifc_modify_flow_table_out_bits {
8792 u8 status[0x8];
b4ff3a36 8793 u8 reserved_at_8[0x18];
34a40e68
MG		 8794
8795 u8 syndrome[0x20];
8796
b4ff3a36 8797 u8 reserved_at_40[0x40];
34a40e68
MG		 8798};
8799
8800struct mlx5_ifc_modify_flow_table_in_bits {
8801 u8 opcode[0x10];
b4ff3a36 8802 u8 reserved_at_10[0x10];
34a40e68 8803
b4ff3a36 8804 u8 reserved_at_20[0x10];
34a40e68
MG		 8805 u8 op_mod[0x10];
8806
7d5e1423
SM		 8807 u8 other_vport[0x1];
8808 u8 reserved_at_41[0xf];
8809 u8 vport_number[0x10];
34a40e68 8810
b4ff3a36 8811 u8 reserved_at_60[0x10];
34a40e68
MG		 8812 u8 modify_field_select[0x10];
8813
8814 u8 table_type[0x8];
b4ff3a36 8815 u8 reserved_at_88[0x18];
34a40e68 8816
b4ff3a36 8817 u8 reserved_at_a0[0x8];
34a40e68
MG		 8818 u8 table_id[0x18];
8819
0c90e9c6 8820 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8821};
8822
4f3961ee
SM		 8823struct mlx5_ifc_ets_tcn_config_reg_bits {
8824 u8 g[0x1];
8825 u8 b[0x1];
8826 u8 r[0x1];
8827 u8 reserved_at_3[0x9];
8828 u8 group[0x4];
8829 u8 reserved_at_10[0x9];
8830 u8 bw_allocation[0x7];
8831
8832 u8 reserved_at_20[0xc];
8833 u8 max_bw_units[0x4];
8834 u8 reserved_at_30[0x8];
8835 u8 max_bw_value[0x8];
8836};
8837
8838struct mlx5_ifc_ets_global_config_reg_bits {
8839 u8 reserved_at_0[0x2];
8840 u8 r[0x1];
8841 u8 reserved_at_3[0x1d];
8842
8843 u8 reserved_at_20[0xc];
8844 u8 max_bw_units[0x4];
8845 u8 reserved_at_30[0x8];
8846 u8 max_bw_value[0x8];
8847};
8848
8849struct mlx5_ifc_qetc_reg_bits {
8850 u8 reserved_at_0[0x8];
8851 u8 port_number[0x8];
8852 u8 reserved_at_10[0x30];
8853
8854 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8855 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8856};
8857
415a64aa
HN		 8858struct mlx5_ifc_qpdpm_dscp_reg_bits {
8859 u8 e[0x1];
8860 u8 reserved_at_01[0x0b];
8861 u8 prio[0x04];
8862};
8863
8864struct mlx5_ifc_qpdpm_reg_bits {
8865 u8 reserved_at_0[0x8];
8866 u8 local_port[0x8];
8867 u8 reserved_at_10[0x10];
8868 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8869};
8870
8871struct mlx5_ifc_qpts_reg_bits {
8872 u8 reserved_at_0[0x8];
8873 u8 local_port[0x8];
8874 u8 reserved_at_10[0x2d];
8875 u8 trust_state[0x3];
8876};
8877
50b4a3c2
HN		 8878struct mlx5_ifc_pptb_reg_bits {
8879 u8 reserved_at_0[0x2];
8880 u8 mm[0x2];
8881 u8 reserved_at_4[0x4];
8882 u8 local_port[0x8];
8883 u8 reserved_at_10[0x6];
8884 u8 cm[0x1];
8885 u8 um[0x1];
8886 u8 pm[0x8];
8887
8888 u8 prio_x_buff[0x20];
8889
8890 u8 pm_msb[0x8];
8891 u8 reserved_at_48[0x10];
8892 u8 ctrl_buff[0x4];
8893 u8 untagged_buff[0x4];
8894};
8895
8896struct mlx5_ifc_pbmc_reg_bits {
8897 u8 reserved_at_0[0x8];
8898 u8 local_port[0x8];
8899 u8 reserved_at_10[0x10];
8900
8901 u8 xoff_timer_value[0x10];
8902 u8 xoff_refresh[0x10];
8903
8904 u8 reserved_at_40[0x9];
8905 u8 fullness_threshold[0x7];
8906 u8 port_buffer_size[0x10];
8907
8908 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8909
8910 u8 reserved_at_2e0[0x40];
8911};
8912
4f3961ee
SM		 8913struct mlx5_ifc_qtct_reg_bits {
8914 u8 reserved_at_0[0x8];
8915 u8 port_number[0x8];
8916 u8 reserved_at_10[0xd];
8917 u8 prio[0x3];
8918
8919 u8 reserved_at_20[0x1d];
8920 u8 tclass[0x3];
8921};
8922
7d5e1423
SM		 8923struct mlx5_ifc_mcia_reg_bits {
8924 u8 l[0x1];
8925 u8 reserved_at_1[0x7];
8926 u8 module[0x8];
8927 u8 reserved_at_10[0x8];
8928 u8 status[0x8];
8929
8930 u8 i2c_device_address[0x8];
8931 u8 page_number[0x8];
8932 u8 device_address[0x10];
8933
8934 u8 reserved_at_40[0x10];
8935 u8 size[0x10];
8936
8937 u8 reserved_at_60[0x20];
8938
8939 u8 dword_0[0x20];
8940 u8 dword_1[0x20];
8941 u8 dword_2[0x20];
8942 u8 dword_3[0x20];
8943 u8 dword_4[0x20];
8944 u8 dword_5[0x20];
8945 u8 dword_6[0x20];
8946 u8 dword_7[0x20];
8947 u8 dword_8[0x20];
8948 u8 dword_9[0x20];
8949 u8 dword_10[0x20];
8950 u8 dword_11[0x20];
8951};
8952
7486216b
SM		 8953struct mlx5_ifc_dcbx_param_bits {
8954 u8 dcbx_cee_cap[0x1];
8955 u8 dcbx_ieee_cap[0x1];
8956 u8 dcbx_standby_cap[0x1];
8957 u8 reserved_at_0[0x5];
8958 u8 port_number[0x8];
8959 u8 reserved_at_10[0xa];
8960 u8 max_application_table_size[6];
8961 u8 reserved_at_20[0x15];
8962 u8 version_oper[0x3];
8963 u8 reserved_at_38[5];
8964 u8 version_admin[0x3];
8965 u8 willing_admin[0x1];
8966 u8 reserved_at_41[0x3];
8967 u8 pfc_cap_oper[0x4];
8968 u8 reserved_at_48[0x4];
8969 u8 pfc_cap_admin[0x4];
8970 u8 reserved_at_50[0x4];
8971 u8 num_of_tc_oper[0x4];
8972 u8 reserved_at_58[0x4];
8973 u8 num_of_tc_admin[0x4];
8974 u8 remote_willing[0x1];
8975 u8 reserved_at_61[3];
8976 u8 remote_pfc_cap[4];
8977 u8 reserved_at_68[0x14];
8978 u8 remote_num_of_tc[0x4];
8979 u8 reserved_at_80[0x18];
8980 u8 error[0x8];
8981 u8 reserved_at_a0[0x160];
8982};
84df61eb
AH		 8983
8984struct mlx5_ifc_lagc_bits {
8985 u8 reserved_at_0[0x1d];
8986 u8 lag_state[0x3];
8987
8988 u8 reserved_at_20[0x14];
8989 u8 tx_remap_affinity_2[0x4];
8990 u8 reserved_at_38[0x4];
8991 u8 tx_remap_affinity_1[0x4];
8992};
8993
8994struct mlx5_ifc_create_lag_out_bits {
8995 u8 status[0x8];
8996 u8 reserved_at_8[0x18];
8997
8998 u8 syndrome[0x20];
8999
9000 u8 reserved_at_40[0x40];
9001};
9002
9003struct mlx5_ifc_create_lag_in_bits {
9004 u8 opcode[0x10];
9005 u8 reserved_at_10[0x10];
9006
9007 u8 reserved_at_20[0x10];
9008 u8 op_mod[0x10];
9009
9010 struct mlx5_ifc_lagc_bits ctx;
9011};
9012
9013struct mlx5_ifc_modify_lag_out_bits {
9014 u8 status[0x8];
9015 u8 reserved_at_8[0x18];
9016
9017 u8 syndrome[0x20];
9018
9019 u8 reserved_at_40[0x40];
9020};
9021
9022struct mlx5_ifc_modify_lag_in_bits {
9023 u8 opcode[0x10];
9024 u8 reserved_at_10[0x10];
9025
9026 u8 reserved_at_20[0x10];
9027 u8 op_mod[0x10];
9028
9029 u8 reserved_at_40[0x20];
9030 u8 field_select[0x20];
9031
9032 struct mlx5_ifc_lagc_bits ctx;
9033};
9034
9035struct mlx5_ifc_query_lag_out_bits {
9036 u8 status[0x8];
9037 u8 reserved_at_8[0x18];
9038
9039 u8 syndrome[0x20];
9040
9041 u8 reserved_at_40[0x40];
9042
9043 struct mlx5_ifc_lagc_bits ctx;
9044};
9045
9046struct mlx5_ifc_query_lag_in_bits {
9047 u8 opcode[0x10];
9048 u8 reserved_at_10[0x10];
9049
9050 u8 reserved_at_20[0x10];
9051 u8 op_mod[0x10];
9052
9053 u8 reserved_at_40[0x40];
9054};
9055
9056struct mlx5_ifc_destroy_lag_out_bits {
9057 u8 status[0x8];
9058 u8 reserved_at_8[0x18];
9059
9060 u8 syndrome[0x20];
9061
9062 u8 reserved_at_40[0x40];
9063};
9064
9065struct mlx5_ifc_destroy_lag_in_bits {
9066 u8 opcode[0x10];
9067 u8 reserved_at_10[0x10];
9068
9069 u8 reserved_at_20[0x10];
9070 u8 op_mod[0x10];
9071
9072 u8 reserved_at_40[0x40];
9073};
9074
9075struct mlx5_ifc_create_vport_lag_out_bits {
9076 u8 status[0x8];
9077 u8 reserved_at_8[0x18];
9078
9079 u8 syndrome[0x20];
9080
9081 u8 reserved_at_40[0x40];
9082};
9083
9084struct mlx5_ifc_create_vport_lag_in_bits {
9085 u8 opcode[0x10];
9086 u8 reserved_at_10[0x10];
9087
9088 u8 reserved_at_20[0x10];
9089 u8 op_mod[0x10];
9090
9091 u8 reserved_at_40[0x40];
9092};
9093
9094struct mlx5_ifc_destroy_vport_lag_out_bits {
9095 u8 status[0x8];
9096 u8 reserved_at_8[0x18];
9097
9098 u8 syndrome[0x20];
9099
9100 u8 reserved_at_40[0x40];
9101};
9102
9103struct mlx5_ifc_destroy_vport_lag_in_bits {
9104 u8 opcode[0x10];
9105 u8 reserved_at_10[0x10];
9106
9107 u8 reserved_at_20[0x10];
9108 u8 op_mod[0x10];
9109
9110 u8 reserved_at_40[0x40];
9111};
9112
24da0016
AL		 9113struct mlx5_ifc_alloc_memic_in_bits {
9114 u8 opcode[0x10];
9115 u8 reserved_at_10[0x10];
9116
9117 u8 reserved_at_20[0x10];
9118 u8 op_mod[0x10];
9119
9120 u8 reserved_at_30[0x20];
9121
9122 u8 reserved_at_40[0x18];
9123 u8 log_memic_addr_alignment[0x8];
9124
9125 u8 range_start_addr[0x40];
9126
9127 u8 range_size[0x20];
9128
9129 u8 memic_size[0x20];
9130};
9131
9132struct mlx5_ifc_alloc_memic_out_bits {
9133 u8 status[0x8];
9134 u8 reserved_at_8[0x18];
9135
9136 u8 syndrome[0x20];
9137
9138 u8 memic_start_addr[0x40];
9139};
9140
9141struct mlx5_ifc_dealloc_memic_in_bits {
9142 u8 opcode[0x10];
9143 u8 reserved_at_10[0x10];
9144
9145 u8 reserved_at_20[0x10];
9146 u8 op_mod[0x10];
9147
9148 u8 reserved_at_40[0x40];
9149
9150 u8 memic_start_addr[0x40];
9151
9152 u8 memic_size[0x20];
9153
9154 u8 reserved_at_e0[0x20];
9155};
9156
9157struct mlx5_ifc_dealloc_memic_out_bits {
9158 u8 status[0x8];
9159 u8 reserved_at_8[0x18];
9160
9161 u8 syndrome[0x20];
9162
9163 u8 reserved_at_40[0x40];
9164};
9165
38b7ca92
YH		 9166struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9167 u8 opcode[0x10];
9168 u8 uid[0x10];
9169
9170 u8 reserved_at_20[0x10];
9171 u8 obj_type[0x10];
9172
9173 u8 obj_id[0x20];
9174
9175 u8 reserved_at_60[0x20];
9176};
9177
9178struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9179 u8 status[0x8];
9180 u8 reserved_at_8[0x18];
9181
9182 u8 syndrome[0x20];
9183
9184 u8 obj_id[0x20];
9185
9186 u8 reserved_at_60[0x20];
9187};
9188
9189struct mlx5_ifc_umem_bits {
9190 u8 modify_field_select[0x40];
9191
9192 u8 reserved_at_40[0x5b];
9193 u8 log_page_size[0x5];
9194
9195 u8 page_offset[0x20];
9196
9197 u8 num_of_mtt[0x40];
9198
9199 struct mlx5_ifc_mtt_bits mtt[0];
9200};
9201
9202struct mlx5_ifc_uctx_bits {
9203 u8 modify_field_select[0x40];
9204
9205 u8 reserved_at_40[0x1c0];
9206};
9207
9208struct mlx5_ifc_create_umem_in_bits {
9209 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9210 struct mlx5_ifc_umem_bits umem;
9211};
9212
9213struct mlx5_ifc_create_uctx_in_bits {
9214 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9215 struct mlx5_ifc_uctx_bits uctx;
9216};
9217
eff8ea8f
FD		 9218struct mlx5_ifc_mtrc_string_db_param_bits {
9219 u8 string_db_base_address[0x20];
9220
9221 u8 reserved_at_20[0x8];
9222 u8 string_db_size[0x18];
9223};
9224
9225struct mlx5_ifc_mtrc_cap_bits {
9226 u8 trace_owner[0x1];
9227 u8 trace_to_memory[0x1];
9228 u8 reserved_at_2[0x4];
9229 u8 trc_ver[0x2];
9230 u8 reserved_at_8[0x14];
9231 u8 num_string_db[0x4];
9232
9233 u8 first_string_trace[0x8];
9234 u8 num_string_trace[0x8];
9235 u8 reserved_at_30[0x28];
9236
9237 u8 log_max_trace_buffer_size[0x8];
9238
9239 u8 reserved_at_60[0x20];
9240
9241 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9242
9243 u8 reserved_at_280[0x180];
9244};
9245
9246struct mlx5_ifc_mtrc_conf_bits {
9247 u8 reserved_at_0[0x1c];
9248 u8 trace_mode[0x4];
9249 u8 reserved_at_20[0x18];
9250 u8 log_trace_buffer_size[0x8];
9251 u8 trace_mkey[0x20];
9252 u8 reserved_at_60[0x3a0];
9253};
9254
9255struct mlx5_ifc_mtrc_stdb_bits {
9256 u8 string_db_index[0x4];
9257 u8 reserved_at_4[0x4];
9258 u8 read_size[0x18];
9259 u8 start_offset[0x20];
9260 u8 string_db_data[0];
9261};
9262
9263struct mlx5_ifc_mtrc_ctrl_bits {
9264 u8 trace_status[0x2];
9265 u8 reserved_at_2[0x2];
9266 u8 arm_event[0x1];
9267 u8 reserved_at_5[0xb];
9268 u8 modify_field_select[0x10];
9269 u8 reserved_at_20[0x2b];
9270 u8 current_timestamp52_32[0x15];
9271 u8 current_timestamp31_0[0x20];
9272 u8 reserved_at_80[0x180];
9273};
9274
d29b796a 9275#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)