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net/mlx5: Fix masking of reserved bits in XRCD number
[linux-2.6-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 169 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
170 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
d29b796a
EC		 171 MLX5_CMD_OP_CREATE_TIR = 0x900,
172 MLX5_CMD_OP_MODIFY_TIR = 0x901,
173 MLX5_CMD_OP_DESTROY_TIR = 0x902,
174 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 175 MLX5_CMD_OP_CREATE_SQ = 0x904,
176 MLX5_CMD_OP_MODIFY_SQ = 0x905,
177 MLX5_CMD_OP_DESTROY_SQ = 0x906,
178 MLX5_CMD_OP_QUERY_SQ = 0x907,
179 MLX5_CMD_OP_CREATE_RQ = 0x908,
180 MLX5_CMD_OP_MODIFY_RQ = 0x909,
181 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
182 MLX5_CMD_OP_QUERY_RQ = 0x90b,
183 MLX5_CMD_OP_CREATE_RMP = 0x90c,
184 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
185 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
186 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 187 MLX5_CMD_OP_CREATE_TIS = 0x912,
188 MLX5_CMD_OP_MODIFY_TIS = 0x913,
189 MLX5_CMD_OP_DESTROY_TIS = 0x914,
190 MLX5_CMD_OP_QUERY_TIS = 0x915,
191 MLX5_CMD_OP_CREATE_RQT = 0x916,
192 MLX5_CMD_OP_MODIFY_RQT = 0x917,
193 MLX5_CMD_OP_DESTROY_RQT = 0x918,
194 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 196 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
197 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
198 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
199 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
200 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
201 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 205 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
206 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
207 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
34a40e68 208 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
e281682b
SM		 209};
210
211struct mlx5_ifc_flow_table_fields_supported_bits {
212 u8 outer_dmac[0x1];
213 u8 outer_smac[0x1];
214 u8 outer_ether_type[0x1];
b4ff3a36 215 u8 reserved_at_3[0x1];
e281682b
SM		 216 u8 outer_first_prio[0x1];
217 u8 outer_first_cfi[0x1];
218 u8 outer_first_vid[0x1];
b4ff3a36 219 u8 reserved_at_7[0x1];
e281682b
SM		 220 u8 outer_second_prio[0x1];
221 u8 outer_second_cfi[0x1];
222 u8 outer_second_vid[0x1];
b4ff3a36 223 u8 reserved_at_b[0x1];
e281682b
SM		 224 u8 outer_sip[0x1];
225 u8 outer_dip[0x1];
226 u8 outer_frag[0x1];
227 u8 outer_ip_protocol[0x1];
228 u8 outer_ip_ecn[0x1];
229 u8 outer_ip_dscp[0x1];
230 u8 outer_udp_sport[0x1];
231 u8 outer_udp_dport[0x1];
232 u8 outer_tcp_sport[0x1];
233 u8 outer_tcp_dport[0x1];
234 u8 outer_tcp_flags[0x1];
235 u8 outer_gre_protocol[0x1];
236 u8 outer_gre_key[0x1];
237 u8 outer_vxlan_vni[0x1];
b4ff3a36 238 u8 reserved_at_1a[0x5];
e281682b
SM		 239 u8 source_eswitch_port[0x1];
240
241 u8 inner_dmac[0x1];
242 u8 inner_smac[0x1];
243 u8 inner_ether_type[0x1];
b4ff3a36 244 u8 reserved_at_23[0x1];
e281682b
SM		 245 u8 inner_first_prio[0x1];
246 u8 inner_first_cfi[0x1];
247 u8 inner_first_vid[0x1];
b4ff3a36 248 u8 reserved_at_27[0x1];
e281682b
SM		 249 u8 inner_second_prio[0x1];
250 u8 inner_second_cfi[0x1];
251 u8 inner_second_vid[0x1];
b4ff3a36 252 u8 reserved_at_2b[0x1];
e281682b
SM		 253 u8 inner_sip[0x1];
254 u8 inner_dip[0x1];
255 u8 inner_frag[0x1];
256 u8 inner_ip_protocol[0x1];
257 u8 inner_ip_ecn[0x1];
258 u8 inner_ip_dscp[0x1];
259 u8 inner_udp_sport[0x1];
260 u8 inner_udp_dport[0x1];
261 u8 inner_tcp_sport[0x1];
262 u8 inner_tcp_dport[0x1];
263 u8 inner_tcp_flags[0x1];
b4ff3a36 264 u8 reserved_at_37[0x9];
e281682b 265
b4ff3a36 266 u8 reserved_at_40[0x40];
e281682b
SM		 267};
268
269struct mlx5_ifc_flow_table_prop_layout_bits {
270 u8 ft_support[0x1];
9dc0b289
AV		 271 u8 reserved_at_1[0x1];
272 u8 flow_counter[0x1];
26a81453 273 u8 flow_modify_en[0x1];
2cc43b49 274 u8 modify_root[0x1];
34a40e68
MG		 275 u8 identified_miss_table_mode[0x1];
276 u8 flow_table_modify[0x1];
b4ff3a36 277 u8 reserved_at_7[0x19];
e281682b 278
b4ff3a36 279 u8 reserved_at_20[0x2];
e281682b 280 u8 log_max_ft_size[0x6];
b4ff3a36 281 u8 reserved_at_28[0x10];
e281682b
SM		 282 u8 max_ft_level[0x8];
283
b4ff3a36 284 u8 reserved_at_40[0x20];
e281682b 285
b4ff3a36 286 u8 reserved_at_60[0x18];
e281682b
SM		 287 u8 log_max_ft_num[0x8];
288
b4ff3a36 289 u8 reserved_at_80[0x18];
e281682b
SM		 290 u8 log_max_destination[0x8];
291
b4ff3a36 292 u8 reserved_at_a0[0x18];
e281682b
SM		 293 u8 log_max_flow[0x8];
294
b4ff3a36 295 u8 reserved_at_c0[0x40];
e281682b
SM		 296
297 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
298
299 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
300};
301
302struct mlx5_ifc_odp_per_transport_service_cap_bits {
303 u8 send[0x1];
304 u8 receive[0x1];
305 u8 write[0x1];
306 u8 read[0x1];
b4ff3a36 307 u8 reserved_at_4[0x1];
e281682b 308 u8 srq_receive[0x1];
b4ff3a36 309 u8 reserved_at_6[0x1a];
e281682b
SM		 310};
311
b4d1f032 312struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 313 u8 reserved_at_0[0x60];
b4d1f032
MG		 314
315 u8 ipv4[0x20];
316};
317
318struct mlx5_ifc_ipv6_layout_bits {
319 u8 ipv6[16][0x8];
320};
321
322union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
323 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
324 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 325 u8 reserved_at_0[0x80];
b4d1f032
MG		 326};
327
e281682b
SM		 328struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
329 u8 smac_47_16[0x20];
330
331 u8 smac_15_0[0x10];
332 u8 ethertype[0x10];
333
334 u8 dmac_47_16[0x20];
335
336 u8 dmac_15_0[0x10];
337 u8 first_prio[0x3];
338 u8 first_cfi[0x1];
339 u8 first_vid[0xc];
340
341 u8 ip_protocol[0x8];
342 u8 ip_dscp[0x6];
343 u8 ip_ecn[0x2];
344 u8 vlan_tag[0x1];
b4ff3a36 345 u8 reserved_at_91[0x1];
e281682b 346 u8 frag[0x1];
b4ff3a36 347 u8 reserved_at_93[0x4];
e281682b
SM		 348 u8 tcp_flags[0x9];
349
350 u8 tcp_sport[0x10];
351 u8 tcp_dport[0x10];
352
b4ff3a36 353 u8 reserved_at_c0[0x20];
e281682b
SM		 354
355 u8 udp_sport[0x10];
356 u8 udp_dport[0x10];
357
b4d1f032 358 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 359
b4d1f032 360 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 361};
362
363struct mlx5_ifc_fte_match_set_misc_bits {
b4ff3a36 364 u8 reserved_at_0[0x20];
e281682b 365
b4ff3a36 366 u8 reserved_at_20[0x10];
e281682b
SM		 367 u8 source_port[0x10];
368
369 u8 outer_second_prio[0x3];
370 u8 outer_second_cfi[0x1];
371 u8 outer_second_vid[0xc];
372 u8 inner_second_prio[0x3];
373 u8 inner_second_cfi[0x1];
374 u8 inner_second_vid[0xc];
375
376 u8 outer_second_vlan_tag[0x1];
377 u8 inner_second_vlan_tag[0x1];
b4ff3a36 378 u8 reserved_at_62[0xe];
e281682b
SM		 379 u8 gre_protocol[0x10];
380
381 u8 gre_key_h[0x18];
382 u8 gre_key_l[0x8];
383
384 u8 vxlan_vni[0x18];
b4ff3a36 385 u8 reserved_at_b8[0x8];
e281682b 386
b4ff3a36 387 u8 reserved_at_c0[0x20];
e281682b 388
b4ff3a36 389 u8 reserved_at_e0[0xc];
e281682b
SM		 390 u8 outer_ipv6_flow_label[0x14];
391
b4ff3a36 392 u8 reserved_at_100[0xc];
e281682b
SM		 393 u8 inner_ipv6_flow_label[0x14];
394
b4ff3a36 395 u8 reserved_at_120[0xe0];
e281682b
SM		 396};
397
398struct mlx5_ifc_cmd_pas_bits {
399 u8 pa_h[0x20];
400
401 u8 pa_l[0x14];
b4ff3a36 402 u8 reserved_at_34[0xc];
e281682b
SM		 403};
404
405struct mlx5_ifc_uint64_bits {
406 u8 hi[0x20];
407
408 u8 lo[0x20];
409};
410
411enum {
412 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
413 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
414 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
415 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
416 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
417 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
418 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
419 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
420 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
421 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
422};
423
424struct mlx5_ifc_ads_bits {
425 u8 fl[0x1];
426 u8 free_ar[0x1];
b4ff3a36 427 u8 reserved_at_2[0xe];
e281682b
SM		 428 u8 pkey_index[0x10];
429
b4ff3a36 430 u8 reserved_at_20[0x8];
e281682b
SM		 431 u8 grh[0x1];
432 u8 mlid[0x7];
433 u8 rlid[0x10];
434
435 u8 ack_timeout[0x5];
b4ff3a36 436 u8 reserved_at_45[0x3];
e281682b 437 u8 src_addr_index[0x8];
b4ff3a36 438 u8 reserved_at_50[0x4];
e281682b
SM		 439 u8 stat_rate[0x4];
440 u8 hop_limit[0x8];
441
b4ff3a36 442 u8 reserved_at_60[0x4];
e281682b
SM		 443 u8 tclass[0x8];
444 u8 flow_label[0x14];
445
446 u8 rgid_rip[16][0x8];
447
b4ff3a36 448 u8 reserved_at_100[0x4];
e281682b
SM		 449 u8 f_dscp[0x1];
450 u8 f_ecn[0x1];
b4ff3a36 451 u8 reserved_at_106[0x1];
e281682b
SM		 452 u8 f_eth_prio[0x1];
453 u8 ecn[0x2];
454 u8 dscp[0x6];
455 u8 udp_sport[0x10];
456
457 u8 dei_cfi[0x1];
458 u8 eth_prio[0x3];
459 u8 sl[0x4];
460 u8 port[0x8];
461 u8 rmac_47_32[0x10];
462
463 u8 rmac_31_0[0x20];
464};
465
466struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a
MG		 467 u8 nic_rx_multi_path_tirs[0x1];
468 u8 reserved_at_1[0x1ff];
e281682b
SM		 469
470 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
471
b4ff3a36 472 u8 reserved_at_400[0x200];
e281682b
SM		 473
474 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
475
476 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
477
b4ff3a36 478 u8 reserved_at_a00[0x200];
e281682b
SM		 479
480 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
481
b4ff3a36 482 u8 reserved_at_e00[0x7200];
e281682b
SM		 483};
484
495716b1 485struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 486 u8 reserved_at_0[0x200];
495716b1
SM		 487
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
489
490 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
491
492 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
493
b4ff3a36 494 u8 reserved_at_800[0x7800];
495716b1
SM		 495};
496
d6666753
SM		 497struct mlx5_ifc_e_switch_cap_bits {
498 u8 vport_svlan_strip[0x1];
499 u8 vport_cvlan_strip[0x1];
500 u8 vport_svlan_insert[0x1];
501 u8 vport_cvlan_insert_if_not_exist[0x1];
502 u8 vport_cvlan_insert_overwrite[0x1];
b4ff3a36 503 u8 reserved_at_5[0x1b];
d6666753 504
b4ff3a36 505 u8 reserved_at_20[0x7e0];
d6666753
SM		 506};
507
e281682b
SM		 508struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
509 u8 csum_cap[0x1];
510 u8 vlan_cap[0x1];
511 u8 lro_cap[0x1];
512 u8 lro_psh_flag[0x1];
513 u8 lro_time_stamp[0x1];
b4ff3a36 514 u8 reserved_at_5[0x3];
66189961 515 u8 self_lb_en_modifiable[0x1];
b4ff3a36 516 u8 reserved_at_9[0x2];
e281682b 517 u8 max_lso_cap[0x5];
b4ff3a36 518 u8 reserved_at_10[0x4];
e281682b 519 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 520 u8 reg_umr_sq[0x1];
521 u8 scatter_fcs[0x1];
522 u8 reserved_at_1a[0x1];
e281682b 523 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 524 u8 reserved_at_1c[0x2];
e281682b
SM		 525 u8 tunnel_statless_gre[0x1];
526 u8 tunnel_stateless_vxlan[0x1];
527
b4ff3a36 528 u8 reserved_at_20[0x20];
e281682b 529
b4ff3a36 530 u8 reserved_at_40[0x10];
e281682b
SM		 531 u8 lro_min_mss_size[0x10];
532
b4ff3a36 533 u8 reserved_at_60[0x120];
e281682b
SM		 534
535 u8 lro_timer_supported_periods[4][0x20];
536
b4ff3a36 537 u8 reserved_at_200[0x600];
e281682b
SM		 538};
539
540struct mlx5_ifc_roce_cap_bits {
541 u8 roce_apm[0x1];
b4ff3a36 542 u8 reserved_at_1[0x1f];
e281682b 543
b4ff3a36 544 u8 reserved_at_20[0x60];
e281682b 545
b4ff3a36 546 u8 reserved_at_80[0xc];
e281682b 547 u8 l3_type[0x4];
b4ff3a36 548 u8 reserved_at_90[0x8];
e281682b
SM		 549 u8 roce_version[0x8];
550
b4ff3a36 551 u8 reserved_at_a0[0x10];
e281682b
SM		 552 u8 r_roce_dest_udp_port[0x10];
553
554 u8 r_roce_max_src_udp_port[0x10];
555 u8 r_roce_min_src_udp_port[0x10];
556
b4ff3a36 557 u8 reserved_at_e0[0x10];
e281682b
SM		 558 u8 roce_address_table_size[0x10];
559
b4ff3a36 560 u8 reserved_at_100[0x700];
e281682b
SM		 561};
562
563enum {
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
565 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
566 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
567 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
573};
574
575enum {
576 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
577 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
578 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
579 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
580 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
581 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
582 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
583 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
584 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
585};
586
587struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 588 u8 reserved_at_0[0x40];
e281682b 589
f91e6d89 590 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 591 u8 reserved_at_42[0x4];
f91e6d89 592 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 593
b4ff3a36 594 u8 reserved_at_47[0x19];
e281682b 595
b4ff3a36 596 u8 reserved_at_60[0x20];
e281682b 597
b4ff3a36 598 u8 reserved_at_80[0x10];
f91e6d89 599 u8 atomic_operations[0x10];
e281682b 600
b4ff3a36 601 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 602 u8 atomic_size_qp[0x10];
603
b4ff3a36 604 u8 reserved_at_c0[0x10];
e281682b
SM		 605 u8 atomic_size_dc[0x10];
606
b4ff3a36 607 u8 reserved_at_e0[0x720];
e281682b
SM		 608};
609
610struct mlx5_ifc_odp_cap_bits {
b4ff3a36 611 u8 reserved_at_0[0x40];
e281682b
SM		 612
613 u8 sig[0x1];
b4ff3a36 614 u8 reserved_at_41[0x1f];
e281682b 615
b4ff3a36 616 u8 reserved_at_60[0x20];
e281682b
SM		 617
618 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
619
620 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
621
622 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
623
b4ff3a36 624 u8 reserved_at_e0[0x720];
e281682b
SM		 625};
626
3f0393a5
SG		 627struct mlx5_ifc_calc_op {
628 u8 reserved_at_0[0x10];
629 u8 reserved_at_10[0x9];
630 u8 op_swap_endianness[0x1];
631 u8 op_min[0x1];
632 u8 op_xor[0x1];
633 u8 op_or[0x1];
634 u8 op_and[0x1];
635 u8 op_max[0x1];
636 u8 op_add[0x1];
637};
638
639struct mlx5_ifc_vector_calc_cap_bits {
640 u8 calc_matrix[0x1];
641 u8 reserved_at_1[0x1f];
642 u8 reserved_at_20[0x8];
643 u8 max_vec_count[0x8];
644 u8 reserved_at_30[0xd];
645 u8 max_chunk_size[0x3];
646 struct mlx5_ifc_calc_op calc0;
647 struct mlx5_ifc_calc_op calc1;
648 struct mlx5_ifc_calc_op calc2;
649 struct mlx5_ifc_calc_op calc3;
650
651 u8 reserved_at_e0[0x720];
652};
653
e281682b
SM		 654enum {
655 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
656 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 657 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 658};
659
660enum {
661 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
662 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
663};
664
665enum {
666 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
667 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
668 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
669 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
670 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
671};
672
673enum {
674 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
675 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
676 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
677 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
678 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
679 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
680};
681
682enum {
683 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
684 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
685};
686
687enum {
688 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
689 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
690 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
691};
692
693enum {
694 MLX5_CAP_PORT_TYPE_IB = 0x0,
695 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 696};
697
b775516b 698struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 699 u8 reserved_at_0[0x80];
b775516b
EC		 700
701 u8 log_max_srq_sz[0x8];
702 u8 log_max_qp_sz[0x8];
b4ff3a36 703 u8 reserved_at_90[0xb];
b775516b
EC		 704 u8 log_max_qp[0x5];
705
b4ff3a36 706 u8 reserved_at_a0[0xb];
e281682b 707 u8 log_max_srq[0x5];
b4ff3a36 708 u8 reserved_at_b0[0x10];
b775516b 709
b4ff3a36 710 u8 reserved_at_c0[0x8];
b775516b 711 u8 log_max_cq_sz[0x8];
b4ff3a36 712 u8 reserved_at_d0[0xb];
b775516b
EC		 713 u8 log_max_cq[0x5];
714
715 u8 log_max_eq_sz[0x8];
b4ff3a36 716 u8 reserved_at_e8[0x2];
b775516b 717 u8 log_max_mkey[0x6];
b4ff3a36 718 u8 reserved_at_f0[0xc];
b775516b
EC		 719 u8 log_max_eq[0x4];
720
721 u8 max_indirection[0x8];
b4ff3a36 722 u8 reserved_at_108[0x1];
b775516b 723 u8 log_max_mrw_sz[0x7];
b4ff3a36 724 u8 reserved_at_110[0x2];
b775516b 725 u8 log_max_bsf_list_size[0x6];
b4ff3a36 726 u8 reserved_at_118[0x2];
b775516b
EC		 727 u8 log_max_klm_list_size[0x6];
728
b4ff3a36 729 u8 reserved_at_120[0xa];
b775516b 730 u8 log_max_ra_req_dc[0x6];
b4ff3a36 731 u8 reserved_at_130[0xa];
b775516b
EC		 732 u8 log_max_ra_res_dc[0x6];
733
b4ff3a36 734 u8 reserved_at_140[0xa];
b775516b 735 u8 log_max_ra_req_qp[0x6];
b4ff3a36 736 u8 reserved_at_150[0xa];
b775516b
EC		 737 u8 log_max_ra_res_qp[0x6];
738
739 u8 pad_cap[0x1];
740 u8 cc_query_allowed[0x1];
741 u8 cc_modify_allowed[0x1];
b4ff3a36 742 u8 reserved_at_163[0xd];
e281682b 743 u8 gid_table_size[0x10];
b775516b 744
e281682b
SM		 745 u8 out_of_seq_cnt[0x1];
746 u8 vport_counters[0x1];
b4ff3a36 747 u8 reserved_at_182[0x4];
b775516b
EC		 748 u8 max_qp_cnt[0xa];
749 u8 pkey_table_size[0x10];
750
e281682b
SM		 751 u8 vport_group_manager[0x1];
752 u8 vhca_group_manager[0x1];
753 u8 ib_virt[0x1];
754 u8 eth_virt[0x1];
b4ff3a36 755 u8 reserved_at_1a4[0x1];
e281682b
SM		 756 u8 ets[0x1];
757 u8 nic_flow_table[0x1];
54f0a411 758 u8 eswitch_flow_table[0x1];
e1c9c62b
TT		 759 u8 early_vf_enable[0x1];
760 u8 reserved_at_1a9[0x2];
b775516b 761 u8 local_ca_ack_delay[0x5];
7d5e1423
SM		 762 u8 reserved_at_1af[0x2];
763 u8 ports_check[0x1];
764 u8 reserved_at_1b2[0x1];
765 u8 disable_link_up[0x1];
766 u8 beacon_led[0x1];
e281682b 767 u8 port_type[0x2];
b775516b
EC		 768 u8 num_ports[0x8];
769
e1c9c62b 770 u8 reserved_at_1c0[0x3];
b775516b 771 u8 log_max_msg[0x5];
e1c9c62b 772 u8 reserved_at_1c8[0x4];
4f3961ee 773 u8 max_tc[0x4];
e1c9c62b 774 u8 reserved_at_1d0[0x6];
928cfe87
TT		 775 u8 rol_s[0x1];
776 u8 rol_g[0x1];
e1c9c62b 777 u8 reserved_at_1d8[0x1];
928cfe87
TT		 778 u8 wol_s[0x1];
779 u8 wol_g[0x1];
780 u8 wol_a[0x1];
781 u8 wol_b[0x1];
782 u8 wol_m[0x1];
783 u8 wol_u[0x1];
784 u8 wol_p[0x1];
b775516b
EC		 785
786 u8 stat_rate_support[0x10];
e1c9c62b 787 u8 reserved_at_1f0[0xc];
e281682b 788 u8 cqe_version[0x4];
b775516b 789
e281682b 790 u8 compact_address_vector[0x1];
7d5e1423
SM		 791 u8 striding_rq[0x1];
792 u8 reserved_at_201[0x2];
1015c2e8 793 u8 ipoib_basic_offloads[0x1];
e1c9c62b 794 u8 reserved_at_205[0xa];
e281682b 795 u8 drain_sigerr[0x1];
b775516b
EC		 796 u8 cmdif_checksum[0x2];
797 u8 sigerr_cqe[0x1];
e1c9c62b 798 u8 reserved_at_213[0x1];
b775516b
EC		 799 u8 wq_signature[0x1];
800 u8 sctr_data_cqe[0x1];
e1c9c62b 801 u8 reserved_at_216[0x1];
b775516b
EC		 802 u8 sho[0x1];
803 u8 tph[0x1];
804 u8 rf[0x1];
e281682b 805 u8 dct[0x1];
e1c9c62b 806 u8 reserved_at_21b[0x1];
e281682b 807 u8 eth_net_offloads[0x1];
b775516b
EC		 808 u8 roce[0x1];
809 u8 atomic[0x1];
e1c9c62b 810 u8 reserved_at_21f[0x1];
b775516b
EC		 811
812 u8 cq_oi[0x1];
813 u8 cq_resize[0x1];
814 u8 cq_moderation[0x1];
e1c9c62b 815 u8 reserved_at_223[0x3];
e281682b 816 u8 cq_eq_remap[0x1];
b775516b
EC		 817 u8 pg[0x1];
818 u8 block_lb_mc[0x1];
e1c9c62b 819 u8 reserved_at_229[0x1];
e281682b 820 u8 scqe_break_moderation[0x1];
7d5e1423 821 u8 cq_period_start_from_cqe[0x1];
b775516b 822 u8 cd[0x1];
e1c9c62b 823 u8 reserved_at_22d[0x1];
b775516b 824 u8 apm[0x1];
3f0393a5 825 u8 vector_calc[0x1];
7d5e1423 826 u8 umr_ptr_rlky[0x1];
d2370e0a 827 u8 imaicl[0x1];
e1c9c62b 828 u8 reserved_at_232[0x4];
b775516b
EC		 829 u8 qkv[0x1];
830 u8 pkv[0x1];
b11a4f9c
HE		 831 u8 set_deth_sqpn[0x1];
832 u8 reserved_at_239[0x3];
b775516b
EC		 833 u8 xrc[0x1];
834 u8 ud[0x1];
835 u8 uc[0x1];
836 u8 rc[0x1];
837
e1c9c62b 838 u8 reserved_at_240[0xa];
b775516b 839 u8 uar_sz[0x6];
e1c9c62b 840 u8 reserved_at_250[0x8];
b775516b
EC		 841 u8 log_pg_sz[0x8];
842
843 u8 bf[0x1];
e1c9c62b 844 u8 reserved_at_261[0x1];
e281682b 845 u8 pad_tx_eth_packet[0x1];
e1c9c62b 846 u8 reserved_at_263[0x8];
b775516b 847 u8 log_bf_reg_size[0x5];
e1c9c62b 848 u8 reserved_at_270[0x10];
b775516b 849
e1c9c62b 850 u8 reserved_at_280[0x10];
b775516b
EC		 851 u8 max_wqe_sz_sq[0x10];
852
e1c9c62b 853 u8 reserved_at_2a0[0x10];
b775516b
EC		 854 u8 max_wqe_sz_rq[0x10];
855
e1c9c62b 856 u8 reserved_at_2c0[0x10];
b775516b
EC		 857 u8 max_wqe_sz_sq_dc[0x10];
858
e1c9c62b 859 u8 reserved_at_2e0[0x7];
b775516b
EC		 860 u8 max_qp_mcg[0x19];
861
e1c9c62b 862 u8 reserved_at_300[0x18];
b775516b
EC		 863 u8 log_max_mcg[0x8];
864
e1c9c62b 865 u8 reserved_at_320[0x3];
e281682b 866 u8 log_max_transport_domain[0x5];
e1c9c62b 867 u8 reserved_at_328[0x3];
b775516b 868 u8 log_max_pd[0x5];
e1c9c62b 869 u8 reserved_at_330[0xb];
b775516b
EC		 870 u8 log_max_xrcd[0x5];
871
e1c9c62b 872 u8 reserved_at_340[0x20];
b775516b 873
e1c9c62b 874 u8 reserved_at_360[0x3];
b775516b 875 u8 log_max_rq[0x5];
e1c9c62b 876 u8 reserved_at_368[0x3];
b775516b 877 u8 log_max_sq[0x5];
e1c9c62b 878 u8 reserved_at_370[0x3];
b775516b 879 u8 log_max_tir[0x5];
e1c9c62b 880 u8 reserved_at_378[0x3];
b775516b
EC		 881 u8 log_max_tis[0x5];
882
e281682b 883 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 884 u8 reserved_at_381[0x2];
e281682b 885 u8 log_max_rmp[0x5];
e1c9c62b 886 u8 reserved_at_388[0x3];
e281682b 887 u8 log_max_rqt[0x5];
e1c9c62b 888 u8 reserved_at_390[0x3];
e281682b 889 u8 log_max_rqt_size[0x5];
e1c9c62b 890 u8 reserved_at_398[0x3];
b775516b
EC		 891 u8 log_max_tis_per_sq[0x5];
892
e1c9c62b 893 u8 reserved_at_3a0[0x3];
e281682b 894 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 895 u8 reserved_at_3a8[0x3];
e281682b 896 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 897 u8 reserved_at_3b0[0x3];
e281682b 898 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 899 u8 reserved_at_3b8[0x3];
e281682b
SM		 900 u8 log_min_stride_sz_sq[0x5];
901
e1c9c62b 902 u8 reserved_at_3c0[0x1b];
e281682b
SM		 903 u8 log_max_wq_sz[0x5];
904
54f0a411 905 u8 nic_vport_change_event[0x1];
e1c9c62b 906 u8 reserved_at_3e1[0xa];
54f0a411 907 u8 log_max_vlan_list[0x5];
e1c9c62b 908 u8 reserved_at_3f0[0x3];
54f0a411 909 u8 log_max_current_mc_list[0x5];
e1c9c62b 910 u8 reserved_at_3f8[0x3];
54f0a411
SM		 911 u8 log_max_current_uc_list[0x5];
912
e1c9c62b 913 u8 reserved_at_400[0x80];
54f0a411 914
e1c9c62b 915 u8 reserved_at_480[0x3];
e281682b 916 u8 log_max_l2_table[0x5];
e1c9c62b 917 u8 reserved_at_488[0x8];
b775516b
EC		 918 u8 log_uar_page_sz[0x10];
919
e1c9c62b 920 u8 reserved_at_4a0[0x20];
048ccca8 921 u8 device_frequency_mhz[0x20];
b0844444 922 u8 device_frequency_khz[0x20];
e1c9c62b
TT		 923
924 u8 reserved_at_500[0x80];
925
926 u8 reserved_at_580[0x3f];
7d5e1423 927 u8 cqe_compression[0x1];
b775516b 928
7d5e1423
SM		 929 u8 cqe_compression_timeout[0x10];
930 u8 cqe_compression_max_num[0x10];
b775516b 931
e1c9c62b 932 u8 reserved_at_5e0[0x220];
b775516b
EC		 933};
934
81848731
SM		 935enum mlx5_flow_destination_type {
936 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
937 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
938 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 939
940 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 941};
b775516b 942
e281682b
SM		 943struct mlx5_ifc_dest_format_struct_bits {
944 u8 destination_type[0x8];
945 u8 destination_id[0x18];
b775516b 946
b4ff3a36 947 u8 reserved_at_20[0x20];
e281682b
SM		 948};
949
9dc0b289
AV		 950struct mlx5_ifc_flow_counter_list_bits {
951 u8 reserved_at_0[0x10];
952 u8 flow_counter_id[0x10];
953
954 u8 reserved_at_20[0x20];
955};
956
957union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
958 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
959 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
960 u8 reserved_at_0[0x40];
961};
962
e281682b
SM		 963struct mlx5_ifc_fte_match_param_bits {
964 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
965
966 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
967
968 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 969
b4ff3a36 970 u8 reserved_at_600[0xa00];
b775516b
EC		 971};
972
e281682b
SM		 973enum {
974 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
975 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
976 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
977 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
978 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
979};
b775516b 980
e281682b
SM		 981struct mlx5_ifc_rx_hash_field_select_bits {
982 u8 l3_prot_type[0x1];
983 u8 l4_prot_type[0x1];
984 u8 selected_fields[0x1e];
985};
b775516b 986
e281682b
SM		 987enum {
988 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
989 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 990};
991
e281682b
SM		 992enum {
993 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
994 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
995};
996
997struct mlx5_ifc_wq_bits {
998 u8 wq_type[0x4];
999 u8 wq_signature[0x1];
1000 u8 end_padding_mode[0x2];
1001 u8 cd_slave[0x1];
b4ff3a36 1002 u8 reserved_at_8[0x18];
b775516b 1003
e281682b
SM		 1004 u8 hds_skip_first_sge[0x1];
1005 u8 log2_hds_buf_size[0x3];
b4ff3a36 1006 u8 reserved_at_24[0x7];
e281682b
SM		 1007 u8 page_offset[0x5];
1008 u8 lwm[0x10];
b775516b 1009
b4ff3a36 1010 u8 reserved_at_40[0x8];
e281682b
SM		 1011 u8 pd[0x18];
1012
b4ff3a36 1013 u8 reserved_at_60[0x8];
e281682b
SM		 1014 u8 uar_page[0x18];
1015
1016 u8 dbr_addr[0x40];
1017
1018 u8 hw_counter[0x20];
1019
1020 u8 sw_counter[0x20];
1021
b4ff3a36 1022 u8 reserved_at_100[0xc];
e281682b 1023 u8 log_wq_stride[0x4];
b4ff3a36 1024 u8 reserved_at_110[0x3];
e281682b 1025 u8 log_wq_pg_sz[0x5];
b4ff3a36 1026 u8 reserved_at_118[0x3];
e281682b
SM		 1027 u8 log_wq_sz[0x5];
1028
7d5e1423
SM		 1029 u8 reserved_at_120[0x15];
1030 u8 log_wqe_num_of_strides[0x3];
1031 u8 two_byte_shift_en[0x1];
1032 u8 reserved_at_139[0x4];
1033 u8 log_wqe_stride_size[0x3];
1034
1035 u8 reserved_at_140[0x4c0];
b775516b 1036
e281682b 1037 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1038};
1039
e281682b 1040struct mlx5_ifc_rq_num_bits {
b4ff3a36 1041 u8 reserved_at_0[0x8];
e281682b
SM		 1042 u8 rq_num[0x18];
1043};
b775516b 1044
e281682b 1045struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1046 u8 reserved_at_0[0x10];
e281682b 1047 u8 mac_addr_47_32[0x10];
b775516b 1048
e281682b
SM		 1049 u8 mac_addr_31_0[0x20];
1050};
1051
c0046cf7 1052struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1053 u8 reserved_at_0[0x14];
c0046cf7
SM		 1054 u8 vlan[0x0c];
1055
b4ff3a36 1056 u8 reserved_at_20[0x20];
c0046cf7
SM		 1057};
1058
e281682b 1059struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1060 u8 reserved_at_0[0xa0];
e281682b
SM		 1061
1062 u8 min_time_between_cnps[0x20];
1063
b4ff3a36 1064 u8 reserved_at_c0[0x12];
e281682b 1065 u8 cnp_dscp[0x6];
b4ff3a36 1066 u8 reserved_at_d8[0x5];
e281682b
SM		 1067 u8 cnp_802p_prio[0x3];
1068
b4ff3a36 1069 u8 reserved_at_e0[0x720];
e281682b
SM		 1070};
1071
1072struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1073 u8 reserved_at_0[0x60];
e281682b 1074
b4ff3a36 1075 u8 reserved_at_60[0x4];
e281682b 1076 u8 clamp_tgt_rate[0x1];
b4ff3a36 1077 u8 reserved_at_65[0x3];
e281682b 1078 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1079 u8 reserved_at_69[0x17];
e281682b 1080
b4ff3a36 1081 u8 reserved_at_80[0x20];
e281682b
SM		 1082
1083 u8 rpg_time_reset[0x20];
1084
1085 u8 rpg_byte_reset[0x20];
1086
1087 u8 rpg_threshold[0x20];
1088
1089 u8 rpg_max_rate[0x20];
1090
1091 u8 rpg_ai_rate[0x20];
1092
1093 u8 rpg_hai_rate[0x20];
1094
1095 u8 rpg_gd[0x20];
1096
1097 u8 rpg_min_dec_fac[0x20];
1098
1099 u8 rpg_min_rate[0x20];
1100
b4ff3a36 1101 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1102
1103 u8 rate_to_set_on_first_cnp[0x20];
1104
1105 u8 dce_tcp_g[0x20];
1106
1107 u8 dce_tcp_rtt[0x20];
1108
1109 u8 rate_reduce_monitor_period[0x20];
1110
b4ff3a36 1111 u8 reserved_at_320[0x20];
e281682b
SM		 1112
1113 u8 initial_alpha_value[0x20];
1114
b4ff3a36 1115 u8 reserved_at_360[0x4a0];
e281682b
SM		 1116};
1117
1118struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1119 u8 reserved_at_0[0x80];
e281682b
SM		 1120
1121 u8 rppp_max_rps[0x20];
1122
1123 u8 rpg_time_reset[0x20];
1124
1125 u8 rpg_byte_reset[0x20];
1126
1127 u8 rpg_threshold[0x20];
1128
1129 u8 rpg_max_rate[0x20];
1130
1131 u8 rpg_ai_rate[0x20];
1132
1133 u8 rpg_hai_rate[0x20];
1134
1135 u8 rpg_gd[0x20];
1136
1137 u8 rpg_min_dec_fac[0x20];
1138
1139 u8 rpg_min_rate[0x20];
1140
b4ff3a36 1141 u8 reserved_at_1c0[0x640];
e281682b
SM		 1142};
1143
1144enum {
1145 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1146 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1147 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1148};
1149
1150struct mlx5_ifc_resize_field_select_bits {
1151 u8 resize_field_select[0x20];
1152};
1153
1154enum {
1155 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1156 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1157 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1158 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1159};
1160
1161struct mlx5_ifc_modify_field_select_bits {
1162 u8 modify_field_select[0x20];
1163};
1164
1165struct mlx5_ifc_field_select_r_roce_np_bits {
1166 u8 field_select_r_roce_np[0x20];
1167};
1168
1169struct mlx5_ifc_field_select_r_roce_rp_bits {
1170 u8 field_select_r_roce_rp[0x20];
1171};
1172
1173enum {
1174 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1175 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1176 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1177 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1178 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1179 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1180 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1181 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1182 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1183 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1184};
1185
1186struct mlx5_ifc_field_select_802_1qau_rp_bits {
1187 u8 field_select_8021qaurp[0x20];
1188};
1189
1190struct mlx5_ifc_phys_layer_cntrs_bits {
1191 u8 time_since_last_clear_high[0x20];
1192
1193 u8 time_since_last_clear_low[0x20];
1194
1195 u8 symbol_errors_high[0x20];
1196
1197 u8 symbol_errors_low[0x20];
1198
1199 u8 sync_headers_errors_high[0x20];
1200
1201 u8 sync_headers_errors_low[0x20];
1202
1203 u8 edpl_bip_errors_lane0_high[0x20];
1204
1205 u8 edpl_bip_errors_lane0_low[0x20];
1206
1207 u8 edpl_bip_errors_lane1_high[0x20];
1208
1209 u8 edpl_bip_errors_lane1_low[0x20];
1210
1211 u8 edpl_bip_errors_lane2_high[0x20];
1212
1213 u8 edpl_bip_errors_lane2_low[0x20];
1214
1215 u8 edpl_bip_errors_lane3_high[0x20];
1216
1217 u8 edpl_bip_errors_lane3_low[0x20];
1218
1219 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1220
1221 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1222
1223 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1224
1225 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1226
1227 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1228
1229 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1230
1231 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1232
1233 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1234
1235 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1236
1237 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1238
1239 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1240
1241 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1242
1243 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1244
1245 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1246
1247 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1248
1249 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1250
1251 u8 rs_fec_corrected_blocks_high[0x20];
1252
1253 u8 rs_fec_corrected_blocks_low[0x20];
1254
1255 u8 rs_fec_uncorrectable_blocks_high[0x20];
1256
1257 u8 rs_fec_uncorrectable_blocks_low[0x20];
1258
1259 u8 rs_fec_no_errors_blocks_high[0x20];
1260
1261 u8 rs_fec_no_errors_blocks_low[0x20];
1262
1263 u8 rs_fec_single_error_blocks_high[0x20];
1264
1265 u8 rs_fec_single_error_blocks_low[0x20];
1266
1267 u8 rs_fec_corrected_symbols_total_high[0x20];
1268
1269 u8 rs_fec_corrected_symbols_total_low[0x20];
1270
1271 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1272
1273 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1274
1275 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1276
1277 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1278
1279 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1280
1281 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1282
1283 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1284
1285 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1286
1287 u8 link_down_events[0x20];
1288
1289 u8 successful_recovery_events[0x20];
1290
b4ff3a36 1291 u8 reserved_at_640[0x180];
e281682b
SM		 1292};
1293
1c64bf6f
MY		 1294struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1295 u8 symbol_error_counter[0x10];
1296
1297 u8 link_error_recovery_counter[0x8];
1298
1299 u8 link_downed_counter[0x8];
1300
1301 u8 port_rcv_errors[0x10];
1302
1303 u8 port_rcv_remote_physical_errors[0x10];
1304
1305 u8 port_rcv_switch_relay_errors[0x10];
1306
1307 u8 port_xmit_discards[0x10];
1308
1309 u8 port_xmit_constraint_errors[0x8];
1310
1311 u8 port_rcv_constraint_errors[0x8];
1312
1313 u8 reserved_at_70[0x8];
1314
1315 u8 link_overrun_errors[0x8];
1316
1317 u8 reserved_at_80[0x10];
1318
1319 u8 vl_15_dropped[0x10];
1320
1321 u8 reserved_at_a0[0xa0];
1322};
1323
e281682b
SM		 1324struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1325 u8 transmit_queue_high[0x20];
1326
1327 u8 transmit_queue_low[0x20];
1328
b4ff3a36 1329 u8 reserved_at_40[0x780];
e281682b
SM		 1330};
1331
1332struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1333 u8 rx_octets_high[0x20];
1334
1335 u8 rx_octets_low[0x20];
1336
b4ff3a36 1337 u8 reserved_at_40[0xc0];
e281682b
SM		 1338
1339 u8 rx_frames_high[0x20];
1340
1341 u8 rx_frames_low[0x20];
1342
1343 u8 tx_octets_high[0x20];
1344
1345 u8 tx_octets_low[0x20];
1346
b4ff3a36 1347 u8 reserved_at_180[0xc0];
e281682b
SM		 1348
1349 u8 tx_frames_high[0x20];
1350
1351 u8 tx_frames_low[0x20];
1352
1353 u8 rx_pause_high[0x20];
1354
1355 u8 rx_pause_low[0x20];
1356
1357 u8 rx_pause_duration_high[0x20];
1358
1359 u8 rx_pause_duration_low[0x20];
1360
1361 u8 tx_pause_high[0x20];
1362
1363 u8 tx_pause_low[0x20];
1364
1365 u8 tx_pause_duration_high[0x20];
1366
1367 u8 tx_pause_duration_low[0x20];
1368
1369 u8 rx_pause_transition_high[0x20];
1370
1371 u8 rx_pause_transition_low[0x20];
1372
b4ff3a36 1373 u8 reserved_at_3c0[0x400];
e281682b
SM		 1374};
1375
1376struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1377 u8 port_transmit_wait_high[0x20];
1378
1379 u8 port_transmit_wait_low[0x20];
1380
b4ff3a36 1381 u8 reserved_at_40[0x780];
e281682b
SM		 1382};
1383
1384struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1385 u8 dot3stats_alignment_errors_high[0x20];
1386
1387 u8 dot3stats_alignment_errors_low[0x20];
1388
1389 u8 dot3stats_fcs_errors_high[0x20];
1390
1391 u8 dot3stats_fcs_errors_low[0x20];
1392
1393 u8 dot3stats_single_collision_frames_high[0x20];
1394
1395 u8 dot3stats_single_collision_frames_low[0x20];
1396
1397 u8 dot3stats_multiple_collision_frames_high[0x20];
1398
1399 u8 dot3stats_multiple_collision_frames_low[0x20];
1400
1401 u8 dot3stats_sqe_test_errors_high[0x20];
1402
1403 u8 dot3stats_sqe_test_errors_low[0x20];
1404
1405 u8 dot3stats_deferred_transmissions_high[0x20];
1406
1407 u8 dot3stats_deferred_transmissions_low[0x20];
1408
1409 u8 dot3stats_late_collisions_high[0x20];
1410
1411 u8 dot3stats_late_collisions_low[0x20];
1412
1413 u8 dot3stats_excessive_collisions_high[0x20];
1414
1415 u8 dot3stats_excessive_collisions_low[0x20];
1416
1417 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1418
1419 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1420
1421 u8 dot3stats_carrier_sense_errors_high[0x20];
1422
1423 u8 dot3stats_carrier_sense_errors_low[0x20];
1424
1425 u8 dot3stats_frame_too_longs_high[0x20];
1426
1427 u8 dot3stats_frame_too_longs_low[0x20];
1428
1429 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1430
1431 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1432
1433 u8 dot3stats_symbol_errors_high[0x20];
1434
1435 u8 dot3stats_symbol_errors_low[0x20];
1436
1437 u8 dot3control_in_unknown_opcodes_high[0x20];
1438
1439 u8 dot3control_in_unknown_opcodes_low[0x20];
1440
1441 u8 dot3in_pause_frames_high[0x20];
1442
1443 u8 dot3in_pause_frames_low[0x20];
1444
1445 u8 dot3out_pause_frames_high[0x20];
1446
1447 u8 dot3out_pause_frames_low[0x20];
1448
b4ff3a36 1449 u8 reserved_at_400[0x3c0];
e281682b
SM		 1450};
1451
1452struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1453 u8 ether_stats_drop_events_high[0x20];
1454
1455 u8 ether_stats_drop_events_low[0x20];
1456
1457 u8 ether_stats_octets_high[0x20];
1458
1459 u8 ether_stats_octets_low[0x20];
1460
1461 u8 ether_stats_pkts_high[0x20];
1462
1463 u8 ether_stats_pkts_low[0x20];
1464
1465 u8 ether_stats_broadcast_pkts_high[0x20];
1466
1467 u8 ether_stats_broadcast_pkts_low[0x20];
1468
1469 u8 ether_stats_multicast_pkts_high[0x20];
1470
1471 u8 ether_stats_multicast_pkts_low[0x20];
1472
1473 u8 ether_stats_crc_align_errors_high[0x20];
1474
1475 u8 ether_stats_crc_align_errors_low[0x20];
1476
1477 u8 ether_stats_undersize_pkts_high[0x20];
1478
1479 u8 ether_stats_undersize_pkts_low[0x20];
1480
1481 u8 ether_stats_oversize_pkts_high[0x20];
1482
1483 u8 ether_stats_oversize_pkts_low[0x20];
1484
1485 u8 ether_stats_fragments_high[0x20];
1486
1487 u8 ether_stats_fragments_low[0x20];
1488
1489 u8 ether_stats_jabbers_high[0x20];
1490
1491 u8 ether_stats_jabbers_low[0x20];
1492
1493 u8 ether_stats_collisions_high[0x20];
1494
1495 u8 ether_stats_collisions_low[0x20];
1496
1497 u8 ether_stats_pkts64octets_high[0x20];
1498
1499 u8 ether_stats_pkts64octets_low[0x20];
1500
1501 u8 ether_stats_pkts65to127octets_high[0x20];
1502
1503 u8 ether_stats_pkts65to127octets_low[0x20];
1504
1505 u8 ether_stats_pkts128to255octets_high[0x20];
1506
1507 u8 ether_stats_pkts128to255octets_low[0x20];
1508
1509 u8 ether_stats_pkts256to511octets_high[0x20];
1510
1511 u8 ether_stats_pkts256to511octets_low[0x20];
1512
1513 u8 ether_stats_pkts512to1023octets_high[0x20];
1514
1515 u8 ether_stats_pkts512to1023octets_low[0x20];
1516
1517 u8 ether_stats_pkts1024to1518octets_high[0x20];
1518
1519 u8 ether_stats_pkts1024to1518octets_low[0x20];
1520
1521 u8 ether_stats_pkts1519to2047octets_high[0x20];
1522
1523 u8 ether_stats_pkts1519to2047octets_low[0x20];
1524
1525 u8 ether_stats_pkts2048to4095octets_high[0x20];
1526
1527 u8 ether_stats_pkts2048to4095octets_low[0x20];
1528
1529 u8 ether_stats_pkts4096to8191octets_high[0x20];
1530
1531 u8 ether_stats_pkts4096to8191octets_low[0x20];
1532
1533 u8 ether_stats_pkts8192to10239octets_high[0x20];
1534
1535 u8 ether_stats_pkts8192to10239octets_low[0x20];
1536
b4ff3a36 1537 u8 reserved_at_540[0x280];
e281682b
SM		 1538};
1539
1540struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1541 u8 if_in_octets_high[0x20];
1542
1543 u8 if_in_octets_low[0x20];
1544
1545 u8 if_in_ucast_pkts_high[0x20];
1546
1547 u8 if_in_ucast_pkts_low[0x20];
1548
1549 u8 if_in_discards_high[0x20];
1550
1551 u8 if_in_discards_low[0x20];
1552
1553 u8 if_in_errors_high[0x20];
1554
1555 u8 if_in_errors_low[0x20];
1556
1557 u8 if_in_unknown_protos_high[0x20];
1558
1559 u8 if_in_unknown_protos_low[0x20];
1560
1561 u8 if_out_octets_high[0x20];
1562
1563 u8 if_out_octets_low[0x20];
1564
1565 u8 if_out_ucast_pkts_high[0x20];
1566
1567 u8 if_out_ucast_pkts_low[0x20];
1568
1569 u8 if_out_discards_high[0x20];
1570
1571 u8 if_out_discards_low[0x20];
1572
1573 u8 if_out_errors_high[0x20];
1574
1575 u8 if_out_errors_low[0x20];
1576
1577 u8 if_in_multicast_pkts_high[0x20];
1578
1579 u8 if_in_multicast_pkts_low[0x20];
1580
1581 u8 if_in_broadcast_pkts_high[0x20];
1582
1583 u8 if_in_broadcast_pkts_low[0x20];
1584
1585 u8 if_out_multicast_pkts_high[0x20];
1586
1587 u8 if_out_multicast_pkts_low[0x20];
1588
1589 u8 if_out_broadcast_pkts_high[0x20];
1590
1591 u8 if_out_broadcast_pkts_low[0x20];
1592
b4ff3a36 1593 u8 reserved_at_340[0x480];
e281682b
SM		 1594};
1595
1596struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1597 u8 a_frames_transmitted_ok_high[0x20];
1598
1599 u8 a_frames_transmitted_ok_low[0x20];
1600
1601 u8 a_frames_received_ok_high[0x20];
1602
1603 u8 a_frames_received_ok_low[0x20];
1604
1605 u8 a_frame_check_sequence_errors_high[0x20];
1606
1607 u8 a_frame_check_sequence_errors_low[0x20];
1608
1609 u8 a_alignment_errors_high[0x20];
1610
1611 u8 a_alignment_errors_low[0x20];
1612
1613 u8 a_octets_transmitted_ok_high[0x20];
1614
1615 u8 a_octets_transmitted_ok_low[0x20];
1616
1617 u8 a_octets_received_ok_high[0x20];
1618
1619 u8 a_octets_received_ok_low[0x20];
1620
1621 u8 a_multicast_frames_xmitted_ok_high[0x20];
1622
1623 u8 a_multicast_frames_xmitted_ok_low[0x20];
1624
1625 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1626
1627 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1628
1629 u8 a_multicast_frames_received_ok_high[0x20];
1630
1631 u8 a_multicast_frames_received_ok_low[0x20];
1632
1633 u8 a_broadcast_frames_received_ok_high[0x20];
1634
1635 u8 a_broadcast_frames_received_ok_low[0x20];
1636
1637 u8 a_in_range_length_errors_high[0x20];
1638
1639 u8 a_in_range_length_errors_low[0x20];
1640
1641 u8 a_out_of_range_length_field_high[0x20];
1642
1643 u8 a_out_of_range_length_field_low[0x20];
1644
1645 u8 a_frame_too_long_errors_high[0x20];
1646
1647 u8 a_frame_too_long_errors_low[0x20];
1648
1649 u8 a_symbol_error_during_carrier_high[0x20];
1650
1651 u8 a_symbol_error_during_carrier_low[0x20];
1652
1653 u8 a_mac_control_frames_transmitted_high[0x20];
1654
1655 u8 a_mac_control_frames_transmitted_low[0x20];
1656
1657 u8 a_mac_control_frames_received_high[0x20];
1658
1659 u8 a_mac_control_frames_received_low[0x20];
1660
1661 u8 a_unsupported_opcodes_received_high[0x20];
1662
1663 u8 a_unsupported_opcodes_received_low[0x20];
1664
1665 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1666
1667 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1668
1669 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1670
1671 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1672
b4ff3a36 1673 u8 reserved_at_4c0[0x300];
e281682b
SM		 1674};
1675
1676struct mlx5_ifc_cmd_inter_comp_event_bits {
1677 u8 command_completion_vector[0x20];
1678
b4ff3a36 1679 u8 reserved_at_20[0xc0];
e281682b
SM		 1680};
1681
1682struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1683 u8 reserved_at_0[0x18];
e281682b 1684 u8 port_num[0x1];
b4ff3a36 1685 u8 reserved_at_19[0x3];
e281682b
SM		 1686 u8 vl[0x4];
1687
b4ff3a36 1688 u8 reserved_at_20[0xa0];
e281682b
SM		 1689};
1690
1691struct mlx5_ifc_db_bf_congestion_event_bits {
1692 u8 event_subtype[0x8];
b4ff3a36 1693 u8 reserved_at_8[0x8];
e281682b 1694 u8 congestion_level[0x8];
b4ff3a36 1695 u8 reserved_at_18[0x8];
e281682b 1696
b4ff3a36 1697 u8 reserved_at_20[0xa0];
e281682b
SM		 1698};
1699
1700struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1701 u8 reserved_at_0[0x60];
e281682b
SM		 1702
1703 u8 gpio_event_hi[0x20];
1704
1705 u8 gpio_event_lo[0x20];
1706
b4ff3a36 1707 u8 reserved_at_a0[0x40];
e281682b
SM		 1708};
1709
1710struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1711 u8 reserved_at_0[0x40];
e281682b
SM		 1712
1713 u8 port_num[0x4];
b4ff3a36 1714 u8 reserved_at_44[0x1c];
e281682b 1715
b4ff3a36 1716 u8 reserved_at_60[0x80];
e281682b
SM		 1717};
1718
1719struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1720 u8 reserved_at_0[0xe0];
e281682b
SM		 1721};
1722
1723enum {
1724 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1725 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1726};
1727
1728struct mlx5_ifc_cq_error_bits {
b4ff3a36 1729 u8 reserved_at_0[0x8];
e281682b
SM		 1730 u8 cqn[0x18];
1731
b4ff3a36 1732 u8 reserved_at_20[0x20];
e281682b 1733
b4ff3a36 1734 u8 reserved_at_40[0x18];
e281682b
SM		 1735 u8 syndrome[0x8];
1736
b4ff3a36 1737 u8 reserved_at_60[0x80];
e281682b
SM		 1738};
1739
1740struct mlx5_ifc_rdma_page_fault_event_bits {
1741 u8 bytes_committed[0x20];
1742
1743 u8 r_key[0x20];
1744
b4ff3a36 1745 u8 reserved_at_40[0x10];
e281682b
SM		 1746 u8 packet_len[0x10];
1747
1748 u8 rdma_op_len[0x20];
1749
1750 u8 rdma_va[0x40];
1751
b4ff3a36 1752 u8 reserved_at_c0[0x5];
e281682b
SM		 1753 u8 rdma[0x1];
1754 u8 write[0x1];
1755 u8 requestor[0x1];
1756 u8 qp_number[0x18];
1757};
1758
1759struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1760 u8 bytes_committed[0x20];
1761
b4ff3a36 1762 u8 reserved_at_20[0x10];
e281682b
SM		 1763 u8 wqe_index[0x10];
1764
b4ff3a36 1765 u8 reserved_at_40[0x10];
e281682b
SM		 1766 u8 len[0x10];
1767
b4ff3a36 1768 u8 reserved_at_60[0x60];
e281682b 1769
b4ff3a36 1770 u8 reserved_at_c0[0x5];
e281682b
SM		 1771 u8 rdma[0x1];
1772 u8 write_read[0x1];
1773 u8 requestor[0x1];
1774 u8 qpn[0x18];
1775};
1776
1777struct mlx5_ifc_qp_events_bits {
b4ff3a36 1778 u8 reserved_at_0[0xa0];
e281682b
SM		 1779
1780 u8 type[0x8];
b4ff3a36 1781 u8 reserved_at_a8[0x18];
e281682b 1782
b4ff3a36 1783 u8 reserved_at_c0[0x8];
e281682b
SM		 1784 u8 qpn_rqn_sqn[0x18];
1785};
1786
1787struct mlx5_ifc_dct_events_bits {
b4ff3a36 1788 u8 reserved_at_0[0xc0];
e281682b 1789
b4ff3a36 1790 u8 reserved_at_c0[0x8];
e281682b
SM		 1791 u8 dct_number[0x18];
1792};
1793
1794struct mlx5_ifc_comp_event_bits {
b4ff3a36 1795 u8 reserved_at_0[0xc0];
e281682b 1796
b4ff3a36 1797 u8 reserved_at_c0[0x8];
e281682b
SM		 1798 u8 cq_number[0x18];
1799};
1800
1801enum {
1802 MLX5_QPC_STATE_RST = 0x0,
1803 MLX5_QPC_STATE_INIT = 0x1,
1804 MLX5_QPC_STATE_RTR = 0x2,
1805 MLX5_QPC_STATE_RTS = 0x3,
1806 MLX5_QPC_STATE_SQER = 0x4,
1807 MLX5_QPC_STATE_ERR = 0x6,
1808 MLX5_QPC_STATE_SQD = 0x7,
1809 MLX5_QPC_STATE_SUSPENDED = 0x9,
1810};
1811
1812enum {
1813 MLX5_QPC_ST_RC = 0x0,
1814 MLX5_QPC_ST_UC = 0x1,
1815 MLX5_QPC_ST_UD = 0x2,
1816 MLX5_QPC_ST_XRC = 0x3,
1817 MLX5_QPC_ST_DCI = 0x5,
1818 MLX5_QPC_ST_QP0 = 0x7,
1819 MLX5_QPC_ST_QP1 = 0x8,
1820 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1821 MLX5_QPC_ST_REG_UMR = 0xc,
1822};
1823
1824enum {
1825 MLX5_QPC_PM_STATE_ARMED = 0x0,
1826 MLX5_QPC_PM_STATE_REARM = 0x1,
1827 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1828 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1829};
1830
1831enum {
1832 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1833 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1834};
1835
1836enum {
1837 MLX5_QPC_MTU_256_BYTES = 0x1,
1838 MLX5_QPC_MTU_512_BYTES = 0x2,
1839 MLX5_QPC_MTU_1K_BYTES = 0x3,
1840 MLX5_QPC_MTU_2K_BYTES = 0x4,
1841 MLX5_QPC_MTU_4K_BYTES = 0x5,
1842 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1843};
1844
1845enum {
1846 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1847 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1848 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1849 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1850 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1851 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1852 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1853 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1854};
1855
1856enum {
1857 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1858 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1859 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1860};
1861
1862enum {
1863 MLX5_QPC_CS_RES_DISABLE = 0x0,
1864 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1865 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1866};
1867
1868struct mlx5_ifc_qpc_bits {
1869 u8 state[0x4];
b4ff3a36 1870 u8 reserved_at_4[0x4];
e281682b 1871 u8 st[0x8];
b4ff3a36 1872 u8 reserved_at_10[0x3];
e281682b 1873 u8 pm_state[0x2];
b4ff3a36 1874 u8 reserved_at_15[0x7];
e281682b 1875 u8 end_padding_mode[0x2];
b4ff3a36 1876 u8 reserved_at_1e[0x2];
e281682b
SM		 1877
1878 u8 wq_signature[0x1];
1879 u8 block_lb_mc[0x1];
1880 u8 atomic_like_write_en[0x1];
1881 u8 latency_sensitive[0x1];
b4ff3a36 1882 u8 reserved_at_24[0x1];
e281682b 1883 u8 drain_sigerr[0x1];
b4ff3a36 1884 u8 reserved_at_26[0x2];
e281682b
SM		 1885 u8 pd[0x18];
1886
1887 u8 mtu[0x3];
1888 u8 log_msg_max[0x5];
b4ff3a36 1889 u8 reserved_at_48[0x1];
e281682b
SM		 1890 u8 log_rq_size[0x4];
1891 u8 log_rq_stride[0x3];
1892 u8 no_sq[0x1];
1893 u8 log_sq_size[0x4];
b4ff3a36 1894 u8 reserved_at_55[0x6];
e281682b 1895 u8 rlky[0x1];
1015c2e8 1896 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 1897
1898 u8 counter_set_id[0x8];
1899 u8 uar_page[0x18];
1900
b4ff3a36 1901 u8 reserved_at_80[0x8];
e281682b
SM		 1902 u8 user_index[0x18];
1903
b4ff3a36 1904 u8 reserved_at_a0[0x3];
e281682b
SM		 1905 u8 log_page_size[0x5];
1906 u8 remote_qpn[0x18];
1907
1908 struct mlx5_ifc_ads_bits primary_address_path;
1909
1910 struct mlx5_ifc_ads_bits secondary_address_path;
1911
1912 u8 log_ack_req_freq[0x4];
b4ff3a36 1913 u8 reserved_at_384[0x4];
e281682b 1914 u8 log_sra_max[0x3];
b4ff3a36 1915 u8 reserved_at_38b[0x2];
e281682b
SM		 1916 u8 retry_count[0x3];
1917 u8 rnr_retry[0x3];
b4ff3a36 1918 u8 reserved_at_393[0x1];
e281682b
SM		 1919 u8 fre[0x1];
1920 u8 cur_rnr_retry[0x3];
1921 u8 cur_retry_count[0x3];
b4ff3a36 1922 u8 reserved_at_39b[0x5];
e281682b 1923
b4ff3a36 1924 u8 reserved_at_3a0[0x20];
e281682b 1925
b4ff3a36 1926 u8 reserved_at_3c0[0x8];
e281682b
SM		 1927 u8 next_send_psn[0x18];
1928
b4ff3a36 1929 u8 reserved_at_3e0[0x8];
e281682b
SM		 1930 u8 cqn_snd[0x18];
1931
b4ff3a36 1932 u8 reserved_at_400[0x40];
e281682b 1933
b4ff3a36 1934 u8 reserved_at_440[0x8];
e281682b
SM		 1935 u8 last_acked_psn[0x18];
1936
b4ff3a36 1937 u8 reserved_at_460[0x8];
e281682b
SM		 1938 u8 ssn[0x18];
1939
b4ff3a36 1940 u8 reserved_at_480[0x8];
e281682b 1941 u8 log_rra_max[0x3];
b4ff3a36 1942 u8 reserved_at_48b[0x1];
e281682b
SM		 1943 u8 atomic_mode[0x4];
1944 u8 rre[0x1];
1945 u8 rwe[0x1];
1946 u8 rae[0x1];
b4ff3a36 1947 u8 reserved_at_493[0x1];
e281682b 1948 u8 page_offset[0x6];
b4ff3a36 1949 u8 reserved_at_49a[0x3];
e281682b
SM		 1950 u8 cd_slave_receive[0x1];
1951 u8 cd_slave_send[0x1];
1952 u8 cd_master[0x1];
1953
b4ff3a36 1954 u8 reserved_at_4a0[0x3];
e281682b
SM		 1955 u8 min_rnr_nak[0x5];
1956 u8 next_rcv_psn[0x18];
1957
b4ff3a36 1958 u8 reserved_at_4c0[0x8];
e281682b
SM		 1959 u8 xrcd[0x18];
1960
b4ff3a36 1961 u8 reserved_at_4e0[0x8];
e281682b
SM		 1962 u8 cqn_rcv[0x18];
1963
1964 u8 dbr_addr[0x40];
1965
1966 u8 q_key[0x20];
1967
b4ff3a36 1968 u8 reserved_at_560[0x5];
e281682b
SM		 1969 u8 rq_type[0x3];
1970 u8 srqn_rmpn[0x18];
1971
b4ff3a36 1972 u8 reserved_at_580[0x8];
e281682b
SM		 1973 u8 rmsn[0x18];
1974
1975 u8 hw_sq_wqebb_counter[0x10];
1976 u8 sw_sq_wqebb_counter[0x10];
1977
1978 u8 hw_rq_counter[0x20];
1979
1980 u8 sw_rq_counter[0x20];
1981
b4ff3a36 1982 u8 reserved_at_600[0x20];
e281682b 1983
b4ff3a36 1984 u8 reserved_at_620[0xf];
e281682b
SM		 1985 u8 cgs[0x1];
1986 u8 cs_req[0x8];
1987 u8 cs_res[0x8];
1988
1989 u8 dc_access_key[0x40];
1990
b4ff3a36 1991 u8 reserved_at_680[0xc0];
e281682b
SM		 1992};
1993
1994struct mlx5_ifc_roce_addr_layout_bits {
1995 u8 source_l3_address[16][0x8];
1996
b4ff3a36 1997 u8 reserved_at_80[0x3];
e281682b
SM		 1998 u8 vlan_valid[0x1];
1999 u8 vlan_id[0xc];
2000 u8 source_mac_47_32[0x10];
2001
2002 u8 source_mac_31_0[0x20];
2003
b4ff3a36 2004 u8 reserved_at_c0[0x14];
e281682b
SM		 2005 u8 roce_l3_type[0x4];
2006 u8 roce_version[0x8];
2007
b4ff3a36 2008 u8 reserved_at_e0[0x20];
e281682b
SM		 2009};
2010
2011union mlx5_ifc_hca_cap_union_bits {
2012 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2013 struct mlx5_ifc_odp_cap_bits odp_cap;
2014 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2015 struct mlx5_ifc_roce_cap_bits roce_cap;
2016 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2017 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2018 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2019 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2020 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
b4ff3a36 2021 u8 reserved_at_0[0x8000];
e281682b
SM		 2022};
2023
2024enum {
2025 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2026 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2027 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2028 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
e281682b
SM		 2029};
2030
2031struct mlx5_ifc_flow_context_bits {
b4ff3a36 2032 u8 reserved_at_0[0x20];
e281682b
SM		 2033
2034 u8 group_id[0x20];
2035
b4ff3a36 2036 u8 reserved_at_40[0x8];
e281682b
SM		 2037 u8 flow_tag[0x18];
2038
b4ff3a36 2039 u8 reserved_at_60[0x10];
e281682b
SM		 2040 u8 action[0x10];
2041
b4ff3a36 2042 u8 reserved_at_80[0x8];
e281682b
SM		 2043 u8 destination_list_size[0x18];
2044
9dc0b289
AV		 2045 u8 reserved_at_a0[0x8];
2046 u8 flow_counter_list_size[0x18];
2047
2048 u8 reserved_at_c0[0x140];
e281682b
SM		 2049
2050 struct mlx5_ifc_fte_match_param_bits match_value;
2051
b4ff3a36 2052 u8 reserved_at_1200[0x600];
e281682b 2053
9dc0b289 2054 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2055};
2056
2057enum {
2058 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2059 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2060};
2061
2062struct mlx5_ifc_xrc_srqc_bits {
2063 u8 state[0x4];
2064 u8 log_xrc_srq_size[0x4];
b4ff3a36 2065 u8 reserved_at_8[0x18];
e281682b
SM		 2066
2067 u8 wq_signature[0x1];
2068 u8 cont_srq[0x1];
b4ff3a36 2069 u8 reserved_at_22[0x1];
e281682b
SM		 2070 u8 rlky[0x1];
2071 u8 basic_cyclic_rcv_wqe[0x1];
2072 u8 log_rq_stride[0x3];
2073 u8 xrcd[0x18];
2074
2075 u8 page_offset[0x6];
b4ff3a36 2076 u8 reserved_at_46[0x2];
e281682b
SM		 2077 u8 cqn[0x18];
2078
b4ff3a36 2079 u8 reserved_at_60[0x20];
e281682b
SM		 2080
2081 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2082 u8 reserved_at_81[0x1];
e281682b
SM		 2083 u8 log_page_size[0x6];
2084 u8 user_index[0x18];
2085
b4ff3a36 2086 u8 reserved_at_a0[0x20];
e281682b 2087
b4ff3a36 2088 u8 reserved_at_c0[0x8];
e281682b
SM		 2089 u8 pd[0x18];
2090
2091 u8 lwm[0x10];
2092 u8 wqe_cnt[0x10];
2093
b4ff3a36 2094 u8 reserved_at_100[0x40];
e281682b
SM		 2095
2096 u8 db_record_addr_h[0x20];
2097
2098 u8 db_record_addr_l[0x1e];
b4ff3a36 2099 u8 reserved_at_17e[0x2];
e281682b 2100
b4ff3a36 2101 u8 reserved_at_180[0x80];
e281682b
SM		 2102};
2103
2104struct mlx5_ifc_traffic_counter_bits {
2105 u8 packets[0x40];
2106
2107 u8 octets[0x40];
2108};
2109
2110struct mlx5_ifc_tisc_bits {
b4ff3a36 2111 u8 reserved_at_0[0xc];
e281682b 2112 u8 prio[0x4];
b4ff3a36 2113 u8 reserved_at_10[0x10];
e281682b 2114
b4ff3a36 2115 u8 reserved_at_20[0x100];
e281682b 2116
b4ff3a36 2117 u8 reserved_at_120[0x8];
e281682b
SM		 2118 u8 transport_domain[0x18];
2119
b4ff3a36 2120 u8 reserved_at_140[0x3c0];
e281682b
SM		 2121};
2122
2123enum {
2124 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2125 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2126};
2127
2128enum {
2129 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2130 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2131};
2132
2133enum {
2be6967c
SM		 2134 MLX5_RX_HASH_FN_NONE = 0x0,
2135 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2136 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2137};
2138
2139enum {
2140 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2141 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2142};
2143
2144struct mlx5_ifc_tirc_bits {
b4ff3a36 2145 u8 reserved_at_0[0x20];
e281682b
SM		 2146
2147 u8 disp_type[0x4];
b4ff3a36 2148 u8 reserved_at_24[0x1c];
e281682b 2149
b4ff3a36 2150 u8 reserved_at_40[0x40];
e281682b 2151
b4ff3a36 2152 u8 reserved_at_80[0x4];
e281682b
SM		 2153 u8 lro_timeout_period_usecs[0x10];
2154 u8 lro_enable_mask[0x4];
2155 u8 lro_max_ip_payload_size[0x8];
2156
b4ff3a36 2157 u8 reserved_at_a0[0x40];
e281682b 2158
b4ff3a36 2159 u8 reserved_at_e0[0x8];
e281682b
SM		 2160 u8 inline_rqn[0x18];
2161
2162 u8 rx_hash_symmetric[0x1];
b4ff3a36 2163 u8 reserved_at_101[0x1];
e281682b 2164 u8 tunneled_offload_en[0x1];
b4ff3a36 2165 u8 reserved_at_103[0x5];
e281682b
SM		 2166 u8 indirect_table[0x18];
2167
2168 u8 rx_hash_fn[0x4];
b4ff3a36 2169 u8 reserved_at_124[0x2];
e281682b
SM		 2170 u8 self_lb_block[0x2];
2171 u8 transport_domain[0x18];
2172
2173 u8 rx_hash_toeplitz_key[10][0x20];
2174
2175 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2176
2177 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2178
b4ff3a36 2179 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2180};
2181
2182enum {
2183 MLX5_SRQC_STATE_GOOD = 0x0,
2184 MLX5_SRQC_STATE_ERROR = 0x1,
2185};
2186
2187struct mlx5_ifc_srqc_bits {
2188 u8 state[0x4];
2189 u8 log_srq_size[0x4];
b4ff3a36 2190 u8 reserved_at_8[0x18];
e281682b
SM		 2191
2192 u8 wq_signature[0x1];
2193 u8 cont_srq[0x1];
b4ff3a36 2194 u8 reserved_at_22[0x1];
e281682b 2195 u8 rlky[0x1];
b4ff3a36 2196 u8 reserved_at_24[0x1];
e281682b
SM		 2197 u8 log_rq_stride[0x3];
2198 u8 xrcd[0x18];
2199
2200 u8 page_offset[0x6];
b4ff3a36 2201 u8 reserved_at_46[0x2];
e281682b
SM		 2202 u8 cqn[0x18];
2203
b4ff3a36 2204 u8 reserved_at_60[0x20];
e281682b 2205
b4ff3a36 2206 u8 reserved_at_80[0x2];
e281682b 2207 u8 log_page_size[0x6];
b4ff3a36 2208 u8 reserved_at_88[0x18];
e281682b 2209
b4ff3a36 2210 u8 reserved_at_a0[0x20];
e281682b 2211
b4ff3a36 2212 u8 reserved_at_c0[0x8];
e281682b
SM		 2213 u8 pd[0x18];
2214
2215 u8 lwm[0x10];
2216 u8 wqe_cnt[0x10];
2217
b4ff3a36 2218 u8 reserved_at_100[0x40];
e281682b 2219
01949d01 2220 u8 dbr_addr[0x40];
e281682b 2221
b4ff3a36 2222 u8 reserved_at_180[0x80];
e281682b
SM		 2223};
2224
2225enum {
2226 MLX5_SQC_STATE_RST = 0x0,
2227 MLX5_SQC_STATE_RDY = 0x1,
2228 MLX5_SQC_STATE_ERR = 0x3,
2229};
2230
2231struct mlx5_ifc_sqc_bits {
2232 u8 rlky[0x1];
2233 u8 cd_master[0x1];
2234 u8 fre[0x1];
2235 u8 flush_in_error_en[0x1];
b4ff3a36 2236 u8 reserved_at_4[0x4];
e281682b 2237 u8 state[0x4];
7d5e1423
SM		 2238 u8 reg_umr[0x1];
2239 u8 reserved_at_d[0x13];
e281682b 2240
b4ff3a36 2241 u8 reserved_at_20[0x8];
e281682b
SM		 2242 u8 user_index[0x18];
2243
b4ff3a36 2244 u8 reserved_at_40[0x8];
e281682b
SM		 2245 u8 cqn[0x18];
2246
b4ff3a36 2247 u8 reserved_at_60[0xa0];
e281682b
SM		 2248
2249 u8 tis_lst_sz[0x10];
b4ff3a36 2250 u8 reserved_at_110[0x10];
e281682b 2251
b4ff3a36 2252 u8 reserved_at_120[0x40];
e281682b 2253
b4ff3a36 2254 u8 reserved_at_160[0x8];
e281682b
SM		 2255 u8 tis_num_0[0x18];
2256
2257 struct mlx5_ifc_wq_bits wq;
2258};
2259
2260struct mlx5_ifc_rqtc_bits {
b4ff3a36 2261 u8 reserved_at_0[0xa0];
e281682b 2262
b4ff3a36 2263 u8 reserved_at_a0[0x10];
e281682b
SM		 2264 u8 rqt_max_size[0x10];
2265
b4ff3a36 2266 u8 reserved_at_c0[0x10];
e281682b
SM		 2267 u8 rqt_actual_size[0x10];
2268
b4ff3a36 2269 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2270
2271 struct mlx5_ifc_rq_num_bits rq_num[0];
2272};
2273
2274enum {
2275 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2276 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2277};
2278
2279enum {
2280 MLX5_RQC_STATE_RST = 0x0,
2281 MLX5_RQC_STATE_RDY = 0x1,
2282 MLX5_RQC_STATE_ERR = 0x3,
2283};
2284
2285struct mlx5_ifc_rqc_bits {
2286 u8 rlky[0x1];
7d5e1423
SM		 2287 u8 reserved_at_1[0x1];
2288 u8 scatter_fcs[0x1];
e281682b
SM		 2289 u8 vsd[0x1];
2290 u8 mem_rq_type[0x4];
2291 u8 state[0x4];
b4ff3a36 2292 u8 reserved_at_c[0x1];
e281682b 2293 u8 flush_in_error_en[0x1];
b4ff3a36 2294 u8 reserved_at_e[0x12];
e281682b 2295
b4ff3a36 2296 u8 reserved_at_20[0x8];
e281682b
SM		 2297 u8 user_index[0x18];
2298
b4ff3a36 2299 u8 reserved_at_40[0x8];
e281682b
SM		 2300 u8 cqn[0x18];
2301
2302 u8 counter_set_id[0x8];
b4ff3a36 2303 u8 reserved_at_68[0x18];
e281682b 2304
b4ff3a36 2305 u8 reserved_at_80[0x8];
e281682b
SM		 2306 u8 rmpn[0x18];
2307
b4ff3a36 2308 u8 reserved_at_a0[0xe0];
e281682b
SM		 2309
2310 struct mlx5_ifc_wq_bits wq;
2311};
2312
2313enum {
2314 MLX5_RMPC_STATE_RDY = 0x1,
2315 MLX5_RMPC_STATE_ERR = 0x3,
2316};
2317
2318struct mlx5_ifc_rmpc_bits {
b4ff3a36 2319 u8 reserved_at_0[0x8];
e281682b 2320 u8 state[0x4];
b4ff3a36 2321 u8 reserved_at_c[0x14];
e281682b
SM		 2322
2323 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2324 u8 reserved_at_21[0x1f];
e281682b 2325
b4ff3a36 2326 u8 reserved_at_40[0x140];
e281682b
SM		 2327
2328 struct mlx5_ifc_wq_bits wq;
2329};
2330
e281682b 2331struct mlx5_ifc_nic_vport_context_bits {
b4ff3a36 2332 u8 reserved_at_0[0x1f];
e281682b
SM		 2333 u8 roce_en[0x1];
2334
d82b7318 2335 u8 arm_change_event[0x1];
b4ff3a36 2336 u8 reserved_at_21[0x1a];
d82b7318
SM		 2337 u8 event_on_mtu[0x1];
2338 u8 event_on_promisc_change[0x1];
2339 u8 event_on_vlan_change[0x1];
2340 u8 event_on_mc_address_change[0x1];
2341 u8 event_on_uc_address_change[0x1];
e281682b 2342
b4ff3a36 2343 u8 reserved_at_40[0xf0];
d82b7318
SM		 2344
2345 u8 mtu[0x10];
2346
9efa7525
AS		 2347 u8 system_image_guid[0x40];
2348 u8 port_guid[0x40];
2349 u8 node_guid[0x40];
2350
b4ff3a36 2351 u8 reserved_at_200[0x140];
9efa7525 2352 u8 qkey_violation_counter[0x10];
b4ff3a36 2353 u8 reserved_at_350[0x430];
d82b7318
SM		 2354
2355 u8 promisc_uc[0x1];
2356 u8 promisc_mc[0x1];
2357 u8 promisc_all[0x1];
b4ff3a36 2358 u8 reserved_at_783[0x2];
e281682b 2359 u8 allowed_list_type[0x3];
b4ff3a36 2360 u8 reserved_at_788[0xc];
e281682b
SM		 2361 u8 allowed_list_size[0xc];
2362
2363 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2364
b4ff3a36 2365 u8 reserved_at_7e0[0x20];
e281682b
SM		 2366
2367 u8 current_uc_mac_address[0][0x40];
2368};
2369
2370enum {
2371 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2372 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2373 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2374};
2375
2376struct mlx5_ifc_mkc_bits {
b4ff3a36 2377 u8 reserved_at_0[0x1];
e281682b 2378 u8 free[0x1];
b4ff3a36 2379 u8 reserved_at_2[0xd];
e281682b
SM		 2380 u8 small_fence_on_rdma_read_response[0x1];
2381 u8 umr_en[0x1];
2382 u8 a[0x1];
2383 u8 rw[0x1];
2384 u8 rr[0x1];
2385 u8 lw[0x1];
2386 u8 lr[0x1];
2387 u8 access_mode[0x2];
b4ff3a36 2388 u8 reserved_at_18[0x8];
e281682b
SM		 2389
2390 u8 qpn[0x18];
2391 u8 mkey_7_0[0x8];
2392
b4ff3a36 2393 u8 reserved_at_40[0x20];
e281682b
SM		 2394
2395 u8 length64[0x1];
2396 u8 bsf_en[0x1];
2397 u8 sync_umr[0x1];
b4ff3a36 2398 u8 reserved_at_63[0x2];
e281682b 2399 u8 expected_sigerr_count[0x1];
b4ff3a36 2400 u8 reserved_at_66[0x1];
e281682b
SM		 2401 u8 en_rinval[0x1];
2402 u8 pd[0x18];
2403
2404 u8 start_addr[0x40];
2405
2406 u8 len[0x40];
2407
2408 u8 bsf_octword_size[0x20];
2409
b4ff3a36 2410 u8 reserved_at_120[0x80];
e281682b
SM		 2411
2412 u8 translations_octword_size[0x20];
2413
b4ff3a36 2414 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2415 u8 log_page_size[0x5];
2416
b4ff3a36 2417 u8 reserved_at_1e0[0x20];
e281682b
SM		 2418};
2419
2420struct mlx5_ifc_pkey_bits {
b4ff3a36 2421 u8 reserved_at_0[0x10];
e281682b
SM		 2422 u8 pkey[0x10];
2423};
2424
2425struct mlx5_ifc_array128_auto_bits {
2426 u8 array128_auto[16][0x8];
2427};
2428
2429struct mlx5_ifc_hca_vport_context_bits {
2430 u8 field_select[0x20];
2431
b4ff3a36 2432 u8 reserved_at_20[0xe0];
e281682b
SM		 2433
2434 u8 sm_virt_aware[0x1];
2435 u8 has_smi[0x1];
2436 u8 has_raw[0x1];
2437 u8 grh_required[0x1];
b4ff3a36 2438 u8 reserved_at_104[0xc];
707c4602
MD		 2439 u8 port_physical_state[0x4];
2440 u8 vport_state_policy[0x4];
2441 u8 port_state[0x4];
e281682b
SM		 2442 u8 vport_state[0x4];
2443
b4ff3a36 2444 u8 reserved_at_120[0x20];
707c4602
MD		 2445
2446 u8 system_image_guid[0x40];
e281682b
SM		 2447
2448 u8 port_guid[0x40];
2449
2450 u8 node_guid[0x40];
2451
2452 u8 cap_mask1[0x20];
2453
2454 u8 cap_mask1_field_select[0x20];
2455
2456 u8 cap_mask2[0x20];
2457
2458 u8 cap_mask2_field_select[0x20];
2459
b4ff3a36 2460 u8 reserved_at_280[0x80];
e281682b
SM		 2461
2462 u8 lid[0x10];
b4ff3a36 2463 u8 reserved_at_310[0x4];
e281682b
SM		 2464 u8 init_type_reply[0x4];
2465 u8 lmc[0x3];
2466 u8 subnet_timeout[0x5];
2467
2468 u8 sm_lid[0x10];
2469 u8 sm_sl[0x4];
b4ff3a36 2470 u8 reserved_at_334[0xc];
e281682b
SM		 2471
2472 u8 qkey_violation_counter[0x10];
2473 u8 pkey_violation_counter[0x10];
2474
b4ff3a36 2475 u8 reserved_at_360[0xca0];
e281682b
SM		 2476};
2477
d6666753 2478struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2479 u8 reserved_at_0[0x3];
d6666753
SM		 2480 u8 vport_svlan_strip[0x1];
2481 u8 vport_cvlan_strip[0x1];
2482 u8 vport_svlan_insert[0x1];
2483 u8 vport_cvlan_insert[0x2];
b4ff3a36 2484 u8 reserved_at_8[0x18];
d6666753 2485
b4ff3a36 2486 u8 reserved_at_20[0x20];
d6666753
SM		 2487
2488 u8 svlan_cfi[0x1];
2489 u8 svlan_pcp[0x3];
2490 u8 svlan_id[0xc];
2491 u8 cvlan_cfi[0x1];
2492 u8 cvlan_pcp[0x3];
2493 u8 cvlan_id[0xc];
2494
b4ff3a36 2495 u8 reserved_at_60[0x7a0];
d6666753
SM		 2496};
2497
e281682b
SM		 2498enum {
2499 MLX5_EQC_STATUS_OK = 0x0,
2500 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2501};
2502
2503enum {
2504 MLX5_EQC_ST_ARMED = 0x9,
2505 MLX5_EQC_ST_FIRED = 0xa,
2506};
2507
2508struct mlx5_ifc_eqc_bits {
2509 u8 status[0x4];
b4ff3a36 2510 u8 reserved_at_4[0x9];
e281682b
SM		 2511 u8 ec[0x1];
2512 u8 oi[0x1];
b4ff3a36 2513 u8 reserved_at_f[0x5];
e281682b 2514 u8 st[0x4];
b4ff3a36 2515 u8 reserved_at_18[0x8];
e281682b 2516
b4ff3a36 2517 u8 reserved_at_20[0x20];
e281682b 2518
b4ff3a36 2519 u8 reserved_at_40[0x14];
e281682b 2520 u8 page_offset[0x6];
b4ff3a36 2521 u8 reserved_at_5a[0x6];
e281682b 2522
b4ff3a36 2523 u8 reserved_at_60[0x3];
e281682b
SM		 2524 u8 log_eq_size[0x5];
2525 u8 uar_page[0x18];
2526
b4ff3a36 2527 u8 reserved_at_80[0x20];
e281682b 2528
b4ff3a36 2529 u8 reserved_at_a0[0x18];
e281682b
SM		 2530 u8 intr[0x8];
2531
b4ff3a36 2532 u8 reserved_at_c0[0x3];
e281682b 2533 u8 log_page_size[0x5];
b4ff3a36 2534 u8 reserved_at_c8[0x18];
e281682b 2535
b4ff3a36 2536 u8 reserved_at_e0[0x60];
e281682b 2537
b4ff3a36 2538 u8 reserved_at_140[0x8];
e281682b
SM		 2539 u8 consumer_counter[0x18];
2540
b4ff3a36 2541 u8 reserved_at_160[0x8];
e281682b
SM		 2542 u8 producer_counter[0x18];
2543
b4ff3a36 2544 u8 reserved_at_180[0x80];
e281682b
SM		 2545};
2546
2547enum {
2548 MLX5_DCTC_STATE_ACTIVE = 0x0,
2549 MLX5_DCTC_STATE_DRAINING = 0x1,
2550 MLX5_DCTC_STATE_DRAINED = 0x2,
2551};
2552
2553enum {
2554 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2555 MLX5_DCTC_CS_RES_NA = 0x1,
2556 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2557};
2558
2559enum {
2560 MLX5_DCTC_MTU_256_BYTES = 0x1,
2561 MLX5_DCTC_MTU_512_BYTES = 0x2,
2562 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2563 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2564 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2565};
2566
2567struct mlx5_ifc_dctc_bits {
b4ff3a36 2568 u8 reserved_at_0[0x4];
e281682b 2569 u8 state[0x4];
b4ff3a36 2570 u8 reserved_at_8[0x18];
e281682b 2571
b4ff3a36 2572 u8 reserved_at_20[0x8];
e281682b
SM		 2573 u8 user_index[0x18];
2574
b4ff3a36 2575 u8 reserved_at_40[0x8];
e281682b
SM		 2576 u8 cqn[0x18];
2577
2578 u8 counter_set_id[0x8];
2579 u8 atomic_mode[0x4];
2580 u8 rre[0x1];
2581 u8 rwe[0x1];
2582 u8 rae[0x1];
2583 u8 atomic_like_write_en[0x1];
2584 u8 latency_sensitive[0x1];
2585 u8 rlky[0x1];
2586 u8 free_ar[0x1];
b4ff3a36 2587 u8 reserved_at_73[0xd];
e281682b 2588
b4ff3a36 2589 u8 reserved_at_80[0x8];
e281682b 2590 u8 cs_res[0x8];
b4ff3a36 2591 u8 reserved_at_90[0x3];
e281682b 2592 u8 min_rnr_nak[0x5];
b4ff3a36 2593 u8 reserved_at_98[0x8];
e281682b 2594
b4ff3a36 2595 u8 reserved_at_a0[0x8];
e281682b
SM		 2596 u8 srqn[0x18];
2597
b4ff3a36 2598 u8 reserved_at_c0[0x8];
e281682b
SM		 2599 u8 pd[0x18];
2600
2601 u8 tclass[0x8];
b4ff3a36 2602 u8 reserved_at_e8[0x4];
e281682b
SM		 2603 u8 flow_label[0x14];
2604
2605 u8 dc_access_key[0x40];
2606
b4ff3a36 2607 u8 reserved_at_140[0x5];
e281682b
SM		 2608 u8 mtu[0x3];
2609 u8 port[0x8];
2610 u8 pkey_index[0x10];
2611
b4ff3a36 2612 u8 reserved_at_160[0x8];
e281682b 2613 u8 my_addr_index[0x8];
b4ff3a36 2614 u8 reserved_at_170[0x8];
e281682b
SM		 2615 u8 hop_limit[0x8];
2616
2617 u8 dc_access_key_violation_count[0x20];
2618
b4ff3a36 2619 u8 reserved_at_1a0[0x14];
e281682b
SM		 2620 u8 dei_cfi[0x1];
2621 u8 eth_prio[0x3];
2622 u8 ecn[0x2];
2623 u8 dscp[0x6];
2624
b4ff3a36 2625 u8 reserved_at_1c0[0x40];
e281682b
SM		 2626};
2627
2628enum {
2629 MLX5_CQC_STATUS_OK = 0x0,
2630 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2631 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2632};
2633
2634enum {
2635 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2636 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2637};
2638
2639enum {
2640 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2641 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2642 MLX5_CQC_ST_FIRED = 0xa,
2643};
2644
7d5e1423
SM		 2645enum {
2646 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2647 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2648};
2649
e281682b
SM		 2650struct mlx5_ifc_cqc_bits {
2651 u8 status[0x4];
b4ff3a36 2652 u8 reserved_at_4[0x4];
e281682b
SM		 2653 u8 cqe_sz[0x3];
2654 u8 cc[0x1];
b4ff3a36 2655 u8 reserved_at_c[0x1];
e281682b
SM		 2656 u8 scqe_break_moderation_en[0x1];
2657 u8 oi[0x1];
7d5e1423
SM		 2658 u8 cq_period_mode[0x2];
2659 u8 cqe_comp_en[0x1];
e281682b
SM		 2660 u8 mini_cqe_res_format[0x2];
2661 u8 st[0x4];
b4ff3a36 2662 u8 reserved_at_18[0x8];
e281682b 2663
b4ff3a36 2664 u8 reserved_at_20[0x20];
e281682b 2665
b4ff3a36 2666 u8 reserved_at_40[0x14];
e281682b 2667 u8 page_offset[0x6];
b4ff3a36 2668 u8 reserved_at_5a[0x6];
e281682b 2669
b4ff3a36 2670 u8 reserved_at_60[0x3];
e281682b
SM		 2671 u8 log_cq_size[0x5];
2672 u8 uar_page[0x18];
2673
b4ff3a36 2674 u8 reserved_at_80[0x4];
e281682b
SM		 2675 u8 cq_period[0xc];
2676 u8 cq_max_count[0x10];
2677
b4ff3a36 2678 u8 reserved_at_a0[0x18];
e281682b
SM		 2679 u8 c_eqn[0x8];
2680
b4ff3a36 2681 u8 reserved_at_c0[0x3];
e281682b 2682 u8 log_page_size[0x5];
b4ff3a36 2683 u8 reserved_at_c8[0x18];
e281682b 2684
b4ff3a36 2685 u8 reserved_at_e0[0x20];
e281682b 2686
b4ff3a36 2687 u8 reserved_at_100[0x8];
e281682b
SM		 2688 u8 last_notified_index[0x18];
2689
b4ff3a36 2690 u8 reserved_at_120[0x8];
e281682b
SM		 2691 u8 last_solicit_index[0x18];
2692
b4ff3a36 2693 u8 reserved_at_140[0x8];
e281682b
SM		 2694 u8 consumer_counter[0x18];
2695
b4ff3a36 2696 u8 reserved_at_160[0x8];
e281682b
SM		 2697 u8 producer_counter[0x18];
2698
b4ff3a36 2699 u8 reserved_at_180[0x40];
e281682b
SM		 2700
2701 u8 dbr_addr[0x40];
2702};
2703
2704union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2705 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2706 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2707 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2708 u8 reserved_at_0[0x800];
e281682b
SM		 2709};
2710
2711struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2712 u8 reserved_at_0[0xc0];
e281682b 2713
b4ff3a36 2714 u8 reserved_at_c0[0x8];
211e6c80
MD		 2715 u8 ieee_vendor_id[0x18];
2716
b4ff3a36 2717 u8 reserved_at_e0[0x10];
e281682b
SM		 2718 u8 vsd_vendor_id[0x10];
2719
2720 u8 vsd[208][0x8];
2721
2722 u8 vsd_contd_psid[16][0x8];
2723};
2724
2725union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2726 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2727 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2728 u8 reserved_at_0[0x20];
e281682b
SM		 2729};
2730
2731union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2732 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2733 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2734 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2735 u8 reserved_at_0[0x20];
e281682b
SM		 2736};
2737
2738union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2739 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2740 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2741 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2742 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2743 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2744 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2745 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2746 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2747 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
b4ff3a36 2748 u8 reserved_at_0[0x7c0];
e281682b
SM		 2749};
2750
2751union mlx5_ifc_event_auto_bits {
2752 struct mlx5_ifc_comp_event_bits comp_event;
2753 struct mlx5_ifc_dct_events_bits dct_events;
2754 struct mlx5_ifc_qp_events_bits qp_events;
2755 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2756 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2757 struct mlx5_ifc_cq_error_bits cq_error;
2758 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2759 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2760 struct mlx5_ifc_gpio_event_bits gpio_event;
2761 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2762 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2763 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 2764 u8 reserved_at_0[0xe0];
e281682b
SM		 2765};
2766
2767struct mlx5_ifc_health_buffer_bits {
b4ff3a36 2768 u8 reserved_at_0[0x100];
e281682b
SM		 2769
2770 u8 assert_existptr[0x20];
2771
2772 u8 assert_callra[0x20];
2773
b4ff3a36 2774 u8 reserved_at_140[0x40];
e281682b
SM		 2775
2776 u8 fw_version[0x20];
2777
2778 u8 hw_id[0x20];
2779
b4ff3a36 2780 u8 reserved_at_1c0[0x20];
e281682b
SM		 2781
2782 u8 irisc_index[0x8];
2783 u8 synd[0x8];
2784 u8 ext_synd[0x10];
2785};
2786
2787struct mlx5_ifc_register_loopback_control_bits {
2788 u8 no_lb[0x1];
b4ff3a36 2789 u8 reserved_at_1[0x7];
e281682b 2790 u8 port[0x8];
b4ff3a36 2791 u8 reserved_at_10[0x10];
e281682b 2792
b4ff3a36 2793 u8 reserved_at_20[0x60];
e281682b
SM		 2794};
2795
2796struct mlx5_ifc_teardown_hca_out_bits {
2797 u8 status[0x8];
b4ff3a36 2798 u8 reserved_at_8[0x18];
e281682b
SM		 2799
2800 u8 syndrome[0x20];
2801
b4ff3a36 2802 u8 reserved_at_40[0x40];
e281682b
SM		 2803};
2804
2805enum {
2806 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2807 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2808};
2809
2810struct mlx5_ifc_teardown_hca_in_bits {
2811 u8 opcode[0x10];
b4ff3a36 2812 u8 reserved_at_10[0x10];
e281682b 2813
b4ff3a36 2814 u8 reserved_at_20[0x10];
e281682b
SM		 2815 u8 op_mod[0x10];
2816
b4ff3a36 2817 u8 reserved_at_40[0x10];
e281682b
SM		 2818 u8 profile[0x10];
2819
b4ff3a36 2820 u8 reserved_at_60[0x20];
e281682b
SM		 2821};
2822
2823struct mlx5_ifc_sqerr2rts_qp_out_bits {
2824 u8 status[0x8];
b4ff3a36 2825 u8 reserved_at_8[0x18];
e281682b
SM		 2826
2827 u8 syndrome[0x20];
2828
b4ff3a36 2829 u8 reserved_at_40[0x40];
e281682b
SM		 2830};
2831
2832struct mlx5_ifc_sqerr2rts_qp_in_bits {
2833 u8 opcode[0x10];
b4ff3a36 2834 u8 reserved_at_10[0x10];
e281682b 2835
b4ff3a36 2836 u8 reserved_at_20[0x10];
e281682b
SM		 2837 u8 op_mod[0x10];
2838
b4ff3a36 2839 u8 reserved_at_40[0x8];
e281682b
SM		 2840 u8 qpn[0x18];
2841
b4ff3a36 2842 u8 reserved_at_60[0x20];
e281682b
SM		 2843
2844 u8 opt_param_mask[0x20];
2845
b4ff3a36 2846 u8 reserved_at_a0[0x20];
e281682b
SM		 2847
2848 struct mlx5_ifc_qpc_bits qpc;
2849
b4ff3a36 2850 u8 reserved_at_800[0x80];
e281682b
SM		 2851};
2852
2853struct mlx5_ifc_sqd2rts_qp_out_bits {
2854 u8 status[0x8];
b4ff3a36 2855 u8 reserved_at_8[0x18];
e281682b
SM		 2856
2857 u8 syndrome[0x20];
2858
b4ff3a36 2859 u8 reserved_at_40[0x40];
e281682b
SM		 2860};
2861
2862struct mlx5_ifc_sqd2rts_qp_in_bits {
2863 u8 opcode[0x10];
b4ff3a36 2864 u8 reserved_at_10[0x10];
e281682b 2865
b4ff3a36 2866 u8 reserved_at_20[0x10];
e281682b
SM		 2867 u8 op_mod[0x10];
2868
b4ff3a36 2869 u8 reserved_at_40[0x8];
e281682b
SM		 2870 u8 qpn[0x18];
2871
b4ff3a36 2872 u8 reserved_at_60[0x20];
e281682b
SM		 2873
2874 u8 opt_param_mask[0x20];
2875
b4ff3a36 2876 u8 reserved_at_a0[0x20];
e281682b
SM		 2877
2878 struct mlx5_ifc_qpc_bits qpc;
2879
b4ff3a36 2880 u8 reserved_at_800[0x80];
e281682b
SM		 2881};
2882
2883struct mlx5_ifc_set_roce_address_out_bits {
2884 u8 status[0x8];
b4ff3a36 2885 u8 reserved_at_8[0x18];
e281682b
SM		 2886
2887 u8 syndrome[0x20];
2888
b4ff3a36 2889 u8 reserved_at_40[0x40];
e281682b
SM		 2890};
2891
2892struct mlx5_ifc_set_roce_address_in_bits {
2893 u8 opcode[0x10];
b4ff3a36 2894 u8 reserved_at_10[0x10];
e281682b 2895
b4ff3a36 2896 u8 reserved_at_20[0x10];
e281682b
SM		 2897 u8 op_mod[0x10];
2898
2899 u8 roce_address_index[0x10];
b4ff3a36 2900 u8 reserved_at_50[0x10];
e281682b 2901
b4ff3a36 2902 u8 reserved_at_60[0x20];
e281682b
SM		 2903
2904 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2905};
2906
2907struct mlx5_ifc_set_mad_demux_out_bits {
2908 u8 status[0x8];
b4ff3a36 2909 u8 reserved_at_8[0x18];
e281682b
SM		 2910
2911 u8 syndrome[0x20];
2912
b4ff3a36 2913 u8 reserved_at_40[0x40];
e281682b
SM		 2914};
2915
2916enum {
2917 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2918 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2919};
2920
2921struct mlx5_ifc_set_mad_demux_in_bits {
2922 u8 opcode[0x10];
b4ff3a36 2923 u8 reserved_at_10[0x10];
e281682b 2924
b4ff3a36 2925 u8 reserved_at_20[0x10];
e281682b
SM		 2926 u8 op_mod[0x10];
2927
b4ff3a36 2928 u8 reserved_at_40[0x20];
e281682b 2929
b4ff3a36 2930 u8 reserved_at_60[0x6];
e281682b 2931 u8 demux_mode[0x2];
b4ff3a36 2932 u8 reserved_at_68[0x18];
e281682b
SM		 2933};
2934
2935struct mlx5_ifc_set_l2_table_entry_out_bits {
2936 u8 status[0x8];
b4ff3a36 2937 u8 reserved_at_8[0x18];
e281682b
SM		 2938
2939 u8 syndrome[0x20];
2940
b4ff3a36 2941 u8 reserved_at_40[0x40];
e281682b
SM		 2942};
2943
2944struct mlx5_ifc_set_l2_table_entry_in_bits {
2945 u8 opcode[0x10];
b4ff3a36 2946 u8 reserved_at_10[0x10];
e281682b 2947
b4ff3a36 2948 u8 reserved_at_20[0x10];
e281682b
SM		 2949 u8 op_mod[0x10];
2950
b4ff3a36 2951 u8 reserved_at_40[0x60];
e281682b 2952
b4ff3a36 2953 u8 reserved_at_a0[0x8];
e281682b
SM		 2954 u8 table_index[0x18];
2955
b4ff3a36 2956 u8 reserved_at_c0[0x20];
e281682b 2957
b4ff3a36 2958 u8 reserved_at_e0[0x13];
e281682b
SM		 2959 u8 vlan_valid[0x1];
2960 u8 vlan[0xc];
2961
2962 struct mlx5_ifc_mac_address_layout_bits mac_address;
2963
b4ff3a36 2964 u8 reserved_at_140[0xc0];
e281682b
SM		 2965};
2966
2967struct mlx5_ifc_set_issi_out_bits {
2968 u8 status[0x8];
b4ff3a36 2969 u8 reserved_at_8[0x18];
e281682b
SM		 2970
2971 u8 syndrome[0x20];
2972
b4ff3a36 2973 u8 reserved_at_40[0x40];
e281682b
SM		 2974};
2975
2976struct mlx5_ifc_set_issi_in_bits {
2977 u8 opcode[0x10];
b4ff3a36 2978 u8 reserved_at_10[0x10];
e281682b 2979
b4ff3a36 2980 u8 reserved_at_20[0x10];
e281682b
SM		 2981 u8 op_mod[0x10];
2982
b4ff3a36 2983 u8 reserved_at_40[0x10];
e281682b
SM		 2984 u8 current_issi[0x10];
2985
b4ff3a36 2986 u8 reserved_at_60[0x20];
e281682b
SM		 2987};
2988
2989struct mlx5_ifc_set_hca_cap_out_bits {
2990 u8 status[0x8];
b4ff3a36 2991 u8 reserved_at_8[0x18];
e281682b
SM		 2992
2993 u8 syndrome[0x20];
2994
b4ff3a36 2995 u8 reserved_at_40[0x40];
e281682b
SM		 2996};
2997
2998struct mlx5_ifc_set_hca_cap_in_bits {
2999 u8 opcode[0x10];
b4ff3a36 3000 u8 reserved_at_10[0x10];
e281682b 3001
b4ff3a36 3002 u8 reserved_at_20[0x10];
e281682b
SM		 3003 u8 op_mod[0x10];
3004
b4ff3a36 3005 u8 reserved_at_40[0x40];
e281682b
SM		 3006
3007 union mlx5_ifc_hca_cap_union_bits capability;
3008};
3009
26a81453
MG		 3010enum {
3011 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3012 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3013 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3014 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3015};
3016
e281682b
SM		 3017struct mlx5_ifc_set_fte_out_bits {
3018 u8 status[0x8];
b4ff3a36 3019 u8 reserved_at_8[0x18];
e281682b
SM		 3020
3021 u8 syndrome[0x20];
3022
b4ff3a36 3023 u8 reserved_at_40[0x40];
e281682b
SM		 3024};
3025
3026struct mlx5_ifc_set_fte_in_bits {
3027 u8 opcode[0x10];
b4ff3a36 3028 u8 reserved_at_10[0x10];
e281682b 3029
b4ff3a36 3030 u8 reserved_at_20[0x10];
e281682b
SM		 3031 u8 op_mod[0x10];
3032
7d5e1423
SM		 3033 u8 other_vport[0x1];
3034 u8 reserved_at_41[0xf];
3035 u8 vport_number[0x10];
3036
3037 u8 reserved_at_60[0x20];
e281682b
SM		 3038
3039 u8 table_type[0x8];
b4ff3a36 3040 u8 reserved_at_88[0x18];
e281682b 3041
b4ff3a36 3042 u8 reserved_at_a0[0x8];
e281682b
SM		 3043 u8 table_id[0x18];
3044
b4ff3a36 3045 u8 reserved_at_c0[0x18];
26a81453
MG		 3046 u8 modify_enable_mask[0x8];
3047
b4ff3a36 3048 u8 reserved_at_e0[0x20];
e281682b
SM		 3049
3050 u8 flow_index[0x20];
3051
b4ff3a36 3052 u8 reserved_at_120[0xe0];
e281682b
SM		 3053
3054 struct mlx5_ifc_flow_context_bits flow_context;
3055};
3056
3057struct mlx5_ifc_rts2rts_qp_out_bits {
3058 u8 status[0x8];
b4ff3a36 3059 u8 reserved_at_8[0x18];
e281682b
SM		 3060
3061 u8 syndrome[0x20];
3062
b4ff3a36 3063 u8 reserved_at_40[0x40];
e281682b
SM		 3064};
3065
3066struct mlx5_ifc_rts2rts_qp_in_bits {
3067 u8 opcode[0x10];
b4ff3a36 3068 u8 reserved_at_10[0x10];
e281682b 3069
b4ff3a36 3070 u8 reserved_at_20[0x10];
e281682b
SM		 3071 u8 op_mod[0x10];
3072
b4ff3a36 3073 u8 reserved_at_40[0x8];
e281682b
SM		 3074 u8 qpn[0x18];
3075
b4ff3a36 3076 u8 reserved_at_60[0x20];
e281682b
SM		 3077
3078 u8 opt_param_mask[0x20];
3079
b4ff3a36 3080 u8 reserved_at_a0[0x20];
e281682b
SM		 3081
3082 struct mlx5_ifc_qpc_bits qpc;
3083
b4ff3a36 3084 u8 reserved_at_800[0x80];
e281682b
SM		 3085};
3086
3087struct mlx5_ifc_rtr2rts_qp_out_bits {
3088 u8 status[0x8];
b4ff3a36 3089 u8 reserved_at_8[0x18];
e281682b
SM		 3090
3091 u8 syndrome[0x20];
3092
b4ff3a36 3093 u8 reserved_at_40[0x40];
e281682b
SM		 3094};
3095
3096struct mlx5_ifc_rtr2rts_qp_in_bits {
3097 u8 opcode[0x10];
b4ff3a36 3098 u8 reserved_at_10[0x10];
e281682b 3099
b4ff3a36 3100 u8 reserved_at_20[0x10];
e281682b
SM		 3101 u8 op_mod[0x10];
3102
b4ff3a36 3103 u8 reserved_at_40[0x8];
e281682b
SM		 3104 u8 qpn[0x18];
3105
b4ff3a36 3106 u8 reserved_at_60[0x20];
e281682b
SM		 3107
3108 u8 opt_param_mask[0x20];
3109
b4ff3a36 3110 u8 reserved_at_a0[0x20];
e281682b
SM		 3111
3112 struct mlx5_ifc_qpc_bits qpc;
3113
b4ff3a36 3114 u8 reserved_at_800[0x80];
e281682b
SM		 3115};
3116
3117struct mlx5_ifc_rst2init_qp_out_bits {
3118 u8 status[0x8];
b4ff3a36 3119 u8 reserved_at_8[0x18];
e281682b
SM		 3120
3121 u8 syndrome[0x20];
3122
b4ff3a36 3123 u8 reserved_at_40[0x40];
e281682b
SM		 3124};
3125
3126struct mlx5_ifc_rst2init_qp_in_bits {
3127 u8 opcode[0x10];
b4ff3a36 3128 u8 reserved_at_10[0x10];
e281682b 3129
b4ff3a36 3130 u8 reserved_at_20[0x10];
e281682b
SM		 3131 u8 op_mod[0x10];
3132
b4ff3a36 3133 u8 reserved_at_40[0x8];
e281682b
SM		 3134 u8 qpn[0x18];
3135
b4ff3a36 3136 u8 reserved_at_60[0x20];
e281682b
SM		 3137
3138 u8 opt_param_mask[0x20];
3139
b4ff3a36 3140 u8 reserved_at_a0[0x20];
e281682b
SM		 3141
3142 struct mlx5_ifc_qpc_bits qpc;
3143
b4ff3a36 3144 u8 reserved_at_800[0x80];
e281682b
SM		 3145};
3146
3147struct mlx5_ifc_query_xrc_srq_out_bits {
3148 u8 status[0x8];
b4ff3a36 3149 u8 reserved_at_8[0x18];
e281682b
SM		 3150
3151 u8 syndrome[0x20];
3152
b4ff3a36 3153 u8 reserved_at_40[0x40];
e281682b
SM		 3154
3155 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3156
b4ff3a36 3157 u8 reserved_at_280[0x600];
e281682b
SM		 3158
3159 u8 pas[0][0x40];
3160};
3161
3162struct mlx5_ifc_query_xrc_srq_in_bits {
3163 u8 opcode[0x10];
b4ff3a36 3164 u8 reserved_at_10[0x10];
e281682b 3165
b4ff3a36 3166 u8 reserved_at_20[0x10];
e281682b
SM		 3167 u8 op_mod[0x10];
3168
b4ff3a36 3169 u8 reserved_at_40[0x8];
e281682b
SM		 3170 u8 xrc_srqn[0x18];
3171
b4ff3a36 3172 u8 reserved_at_60[0x20];
e281682b
SM		 3173};
3174
3175enum {
3176 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3177 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3178};
3179
3180struct mlx5_ifc_query_vport_state_out_bits {
3181 u8 status[0x8];
b4ff3a36 3182 u8 reserved_at_8[0x18];
e281682b
SM		 3183
3184 u8 syndrome[0x20];
3185
b4ff3a36 3186 u8 reserved_at_40[0x20];
e281682b 3187
b4ff3a36 3188 u8 reserved_at_60[0x18];
e281682b
SM		 3189 u8 admin_state[0x4];
3190 u8 state[0x4];
3191};
3192
3193enum {
3194 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3195 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3196};
3197
3198struct mlx5_ifc_query_vport_state_in_bits {
3199 u8 opcode[0x10];
b4ff3a36 3200 u8 reserved_at_10[0x10];
e281682b 3201
b4ff3a36 3202 u8 reserved_at_20[0x10];
e281682b
SM		 3203 u8 op_mod[0x10];
3204
3205 u8 other_vport[0x1];
b4ff3a36 3206 u8 reserved_at_41[0xf];
e281682b
SM		 3207 u8 vport_number[0x10];
3208
b4ff3a36 3209 u8 reserved_at_60[0x20];
e281682b
SM		 3210};
3211
3212struct mlx5_ifc_query_vport_counter_out_bits {
3213 u8 status[0x8];
b4ff3a36 3214 u8 reserved_at_8[0x18];
e281682b
SM		 3215
3216 u8 syndrome[0x20];
3217
b4ff3a36 3218 u8 reserved_at_40[0x40];
e281682b
SM		 3219
3220 struct mlx5_ifc_traffic_counter_bits received_errors;
3221
3222 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3223
3224 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3225
3226 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3227
3228 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3229
3230 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3231
3232 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3233
3234 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3235
3236 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3237
3238 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3239
3240 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3241
3242 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3243
b4ff3a36 3244 u8 reserved_at_680[0xa00];
e281682b
SM		 3245};
3246
3247enum {
3248 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3249};
3250
3251struct mlx5_ifc_query_vport_counter_in_bits {
3252 u8 opcode[0x10];
b4ff3a36 3253 u8 reserved_at_10[0x10];
e281682b 3254
b4ff3a36 3255 u8 reserved_at_20[0x10];
e281682b
SM		 3256 u8 op_mod[0x10];
3257
3258 u8 other_vport[0x1];
b54ba277
MY		 3259 u8 reserved_at_41[0xb];
3260 u8 port_num[0x4];
e281682b
SM		 3261 u8 vport_number[0x10];
3262
b4ff3a36 3263 u8 reserved_at_60[0x60];
e281682b
SM		 3264
3265 u8 clear[0x1];
b4ff3a36 3266 u8 reserved_at_c1[0x1f];
e281682b 3267
b4ff3a36 3268 u8 reserved_at_e0[0x20];
e281682b
SM		 3269};
3270
3271struct mlx5_ifc_query_tis_out_bits {
3272 u8 status[0x8];
b4ff3a36 3273 u8 reserved_at_8[0x18];
e281682b
SM		 3274
3275 u8 syndrome[0x20];
3276
b4ff3a36 3277 u8 reserved_at_40[0x40];
e281682b
SM		 3278
3279 struct mlx5_ifc_tisc_bits tis_context;
3280};
3281
3282struct mlx5_ifc_query_tis_in_bits {
3283 u8 opcode[0x10];
b4ff3a36 3284 u8 reserved_at_10[0x10];
e281682b 3285
b4ff3a36 3286 u8 reserved_at_20[0x10];
e281682b
SM		 3287 u8 op_mod[0x10];
3288
b4ff3a36 3289 u8 reserved_at_40[0x8];
e281682b
SM		 3290 u8 tisn[0x18];
3291
b4ff3a36 3292 u8 reserved_at_60[0x20];
e281682b
SM		 3293};
3294
3295struct mlx5_ifc_query_tir_out_bits {
3296 u8 status[0x8];
b4ff3a36 3297 u8 reserved_at_8[0x18];
e281682b
SM		 3298
3299 u8 syndrome[0x20];
3300
b4ff3a36 3301 u8 reserved_at_40[0xc0];
e281682b
SM		 3302
3303 struct mlx5_ifc_tirc_bits tir_context;
3304};
3305
3306struct mlx5_ifc_query_tir_in_bits {
3307 u8 opcode[0x10];
b4ff3a36 3308 u8 reserved_at_10[0x10];
e281682b 3309
b4ff3a36 3310 u8 reserved_at_20[0x10];
e281682b
SM		 3311 u8 op_mod[0x10];
3312
b4ff3a36 3313 u8 reserved_at_40[0x8];
e281682b
SM		 3314 u8 tirn[0x18];
3315
b4ff3a36 3316 u8 reserved_at_60[0x20];
e281682b
SM		 3317};
3318
3319struct mlx5_ifc_query_srq_out_bits {
3320 u8 status[0x8];
b4ff3a36 3321 u8 reserved_at_8[0x18];
e281682b
SM		 3322
3323 u8 syndrome[0x20];
3324
b4ff3a36 3325 u8 reserved_at_40[0x40];
e281682b
SM		 3326
3327 struct mlx5_ifc_srqc_bits srq_context_entry;
3328
b4ff3a36 3329 u8 reserved_at_280[0x600];
e281682b
SM		 3330
3331 u8 pas[0][0x40];
3332};
3333
3334struct mlx5_ifc_query_srq_in_bits {
3335 u8 opcode[0x10];
b4ff3a36 3336 u8 reserved_at_10[0x10];
e281682b 3337
b4ff3a36 3338 u8 reserved_at_20[0x10];
e281682b
SM		 3339 u8 op_mod[0x10];
3340
b4ff3a36 3341 u8 reserved_at_40[0x8];
e281682b
SM		 3342 u8 srqn[0x18];
3343
b4ff3a36 3344 u8 reserved_at_60[0x20];
e281682b
SM		 3345};
3346
3347struct mlx5_ifc_query_sq_out_bits {
3348 u8 status[0x8];
b4ff3a36 3349 u8 reserved_at_8[0x18];
e281682b
SM		 3350
3351 u8 syndrome[0x20];
3352
b4ff3a36 3353 u8 reserved_at_40[0xc0];
e281682b
SM		 3354
3355 struct mlx5_ifc_sqc_bits sq_context;
3356};
3357
3358struct mlx5_ifc_query_sq_in_bits {
3359 u8 opcode[0x10];
b4ff3a36 3360 u8 reserved_at_10[0x10];
e281682b 3361
b4ff3a36 3362 u8 reserved_at_20[0x10];
e281682b
SM		 3363 u8 op_mod[0x10];
3364
b4ff3a36 3365 u8 reserved_at_40[0x8];
e281682b
SM		 3366 u8 sqn[0x18];
3367
b4ff3a36 3368 u8 reserved_at_60[0x20];
e281682b
SM		 3369};
3370
3371struct mlx5_ifc_query_special_contexts_out_bits {
3372 u8 status[0x8];
b4ff3a36 3373 u8 reserved_at_8[0x18];
e281682b
SM		 3374
3375 u8 syndrome[0x20];
3376
b4ff3a36 3377 u8 reserved_at_40[0x20];
e281682b
SM		 3378
3379 u8 resd_lkey[0x20];
3380};
3381
3382struct mlx5_ifc_query_special_contexts_in_bits {
3383 u8 opcode[0x10];
b4ff3a36 3384 u8 reserved_at_10[0x10];
e281682b 3385
b4ff3a36 3386 u8 reserved_at_20[0x10];
e281682b
SM		 3387 u8 op_mod[0x10];
3388
b4ff3a36 3389 u8 reserved_at_40[0x40];
e281682b
SM		 3390};
3391
3392struct mlx5_ifc_query_rqt_out_bits {
3393 u8 status[0x8];
b4ff3a36 3394 u8 reserved_at_8[0x18];
e281682b
SM		 3395
3396 u8 syndrome[0x20];
3397
b4ff3a36 3398 u8 reserved_at_40[0xc0];
e281682b
SM		 3399
3400 struct mlx5_ifc_rqtc_bits rqt_context;
3401};
3402
3403struct mlx5_ifc_query_rqt_in_bits {
3404 u8 opcode[0x10];
b4ff3a36 3405 u8 reserved_at_10[0x10];
e281682b 3406
b4ff3a36 3407 u8 reserved_at_20[0x10];
e281682b
SM		 3408 u8 op_mod[0x10];
3409
b4ff3a36 3410 u8 reserved_at_40[0x8];
e281682b
SM		 3411 u8 rqtn[0x18];
3412
b4ff3a36 3413 u8 reserved_at_60[0x20];
e281682b
SM		 3414};
3415
3416struct mlx5_ifc_query_rq_out_bits {
3417 u8 status[0x8];
b4ff3a36 3418 u8 reserved_at_8[0x18];
e281682b
SM		 3419
3420 u8 syndrome[0x20];
3421
b4ff3a36 3422 u8 reserved_at_40[0xc0];
e281682b
SM		 3423
3424 struct mlx5_ifc_rqc_bits rq_context;
3425};
3426
3427struct mlx5_ifc_query_rq_in_bits {
3428 u8 opcode[0x10];
b4ff3a36 3429 u8 reserved_at_10[0x10];
e281682b 3430
b4ff3a36 3431 u8 reserved_at_20[0x10];
e281682b
SM		 3432 u8 op_mod[0x10];
3433
b4ff3a36 3434 u8 reserved_at_40[0x8];
e281682b
SM		 3435 u8 rqn[0x18];
3436
b4ff3a36 3437 u8 reserved_at_60[0x20];
e281682b
SM		 3438};
3439
3440struct mlx5_ifc_query_roce_address_out_bits {
3441 u8 status[0x8];
b4ff3a36 3442 u8 reserved_at_8[0x18];
e281682b
SM		 3443
3444 u8 syndrome[0x20];
3445
b4ff3a36 3446 u8 reserved_at_40[0x40];
e281682b
SM		 3447
3448 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3449};
3450
3451struct mlx5_ifc_query_roce_address_in_bits {
3452 u8 opcode[0x10];
b4ff3a36 3453 u8 reserved_at_10[0x10];
e281682b 3454
b4ff3a36 3455 u8 reserved_at_20[0x10];
e281682b
SM		 3456 u8 op_mod[0x10];
3457
3458 u8 roce_address_index[0x10];
b4ff3a36 3459 u8 reserved_at_50[0x10];
e281682b 3460
b4ff3a36 3461 u8 reserved_at_60[0x20];
e281682b
SM		 3462};
3463
3464struct mlx5_ifc_query_rmp_out_bits {
3465 u8 status[0x8];
b4ff3a36 3466 u8 reserved_at_8[0x18];
e281682b
SM		 3467
3468 u8 syndrome[0x20];
3469
b4ff3a36 3470 u8 reserved_at_40[0xc0];
e281682b
SM		 3471
3472 struct mlx5_ifc_rmpc_bits rmp_context;
3473};
3474
3475struct mlx5_ifc_query_rmp_in_bits {
3476 u8 opcode[0x10];
b4ff3a36 3477 u8 reserved_at_10[0x10];
e281682b 3478
b4ff3a36 3479 u8 reserved_at_20[0x10];
e281682b
SM		 3480 u8 op_mod[0x10];
3481
b4ff3a36 3482 u8 reserved_at_40[0x8];
e281682b
SM		 3483 u8 rmpn[0x18];
3484
b4ff3a36 3485 u8 reserved_at_60[0x20];
e281682b
SM		 3486};
3487
3488struct mlx5_ifc_query_qp_out_bits {
3489 u8 status[0x8];
b4ff3a36 3490 u8 reserved_at_8[0x18];
e281682b
SM		 3491
3492 u8 syndrome[0x20];
3493
b4ff3a36 3494 u8 reserved_at_40[0x40];
e281682b
SM		 3495
3496 u8 opt_param_mask[0x20];
3497
b4ff3a36 3498 u8 reserved_at_a0[0x20];
e281682b
SM		 3499
3500 struct mlx5_ifc_qpc_bits qpc;
3501
b4ff3a36 3502 u8 reserved_at_800[0x80];
e281682b
SM		 3503
3504 u8 pas[0][0x40];
3505};
3506
3507struct mlx5_ifc_query_qp_in_bits {
3508 u8 opcode[0x10];
b4ff3a36 3509 u8 reserved_at_10[0x10];
e281682b 3510
b4ff3a36 3511 u8 reserved_at_20[0x10];
e281682b
SM		 3512 u8 op_mod[0x10];
3513
b4ff3a36 3514 u8 reserved_at_40[0x8];
e281682b
SM		 3515 u8 qpn[0x18];
3516
b4ff3a36 3517 u8 reserved_at_60[0x20];
e281682b
SM		 3518};
3519
3520struct mlx5_ifc_query_q_counter_out_bits {
3521 u8 status[0x8];
b4ff3a36 3522 u8 reserved_at_8[0x18];
e281682b
SM		 3523
3524 u8 syndrome[0x20];
3525
b4ff3a36 3526 u8 reserved_at_40[0x40];
e281682b
SM		 3527
3528 u8 rx_write_requests[0x20];
3529
b4ff3a36 3530 u8 reserved_at_a0[0x20];
e281682b
SM		 3531
3532 u8 rx_read_requests[0x20];
3533
b4ff3a36 3534 u8 reserved_at_e0[0x20];
e281682b
SM		 3535
3536 u8 rx_atomic_requests[0x20];
3537
b4ff3a36 3538 u8 reserved_at_120[0x20];
e281682b
SM		 3539
3540 u8 rx_dct_connect[0x20];
3541
b4ff3a36 3542 u8 reserved_at_160[0x20];
e281682b
SM		 3543
3544 u8 out_of_buffer[0x20];
3545
b4ff3a36 3546 u8 reserved_at_1a0[0x20];
e281682b
SM		 3547
3548 u8 out_of_sequence[0x20];
3549
b4ff3a36 3550 u8 reserved_at_1e0[0x620];
e281682b
SM		 3551};
3552
3553struct mlx5_ifc_query_q_counter_in_bits {
3554 u8 opcode[0x10];
b4ff3a36 3555 u8 reserved_at_10[0x10];
e281682b 3556
b4ff3a36 3557 u8 reserved_at_20[0x10];
e281682b
SM		 3558 u8 op_mod[0x10];
3559
b4ff3a36 3560 u8 reserved_at_40[0x80];
e281682b
SM		 3561
3562 u8 clear[0x1];
b4ff3a36 3563 u8 reserved_at_c1[0x1f];
e281682b 3564
b4ff3a36 3565 u8 reserved_at_e0[0x18];
e281682b
SM		 3566 u8 counter_set_id[0x8];
3567};
3568
3569struct mlx5_ifc_query_pages_out_bits {
3570 u8 status[0x8];
b4ff3a36 3571 u8 reserved_at_8[0x18];
e281682b
SM		 3572
3573 u8 syndrome[0x20];
3574
b4ff3a36 3575 u8 reserved_at_40[0x10];
e281682b
SM		 3576 u8 function_id[0x10];
3577
3578 u8 num_pages[0x20];
3579};
3580
3581enum {
3582 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3583 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3584 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3585};
3586
3587struct mlx5_ifc_query_pages_in_bits {
3588 u8 opcode[0x10];
b4ff3a36 3589 u8 reserved_at_10[0x10];
e281682b 3590
b4ff3a36 3591 u8 reserved_at_20[0x10];
e281682b
SM		 3592 u8 op_mod[0x10];
3593
b4ff3a36 3594 u8 reserved_at_40[0x10];
e281682b
SM		 3595 u8 function_id[0x10];
3596
b4ff3a36 3597 u8 reserved_at_60[0x20];
e281682b
SM		 3598};
3599
3600struct mlx5_ifc_query_nic_vport_context_out_bits {
3601 u8 status[0x8];
b4ff3a36 3602 u8 reserved_at_8[0x18];
e281682b
SM		 3603
3604 u8 syndrome[0x20];
3605
b4ff3a36 3606 u8 reserved_at_40[0x40];
e281682b
SM		 3607
3608 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3609};
3610
3611struct mlx5_ifc_query_nic_vport_context_in_bits {
3612 u8 opcode[0x10];
b4ff3a36 3613 u8 reserved_at_10[0x10];
e281682b 3614
b4ff3a36 3615 u8 reserved_at_20[0x10];
e281682b
SM		 3616 u8 op_mod[0x10];
3617
3618 u8 other_vport[0x1];
b4ff3a36 3619 u8 reserved_at_41[0xf];
e281682b
SM		 3620 u8 vport_number[0x10];
3621
b4ff3a36 3622 u8 reserved_at_60[0x5];
e281682b 3623 u8 allowed_list_type[0x3];
b4ff3a36 3624 u8 reserved_at_68[0x18];
e281682b
SM		 3625};
3626
3627struct mlx5_ifc_query_mkey_out_bits {
3628 u8 status[0x8];
b4ff3a36 3629 u8 reserved_at_8[0x18];
e281682b
SM		 3630
3631 u8 syndrome[0x20];
3632
b4ff3a36 3633 u8 reserved_at_40[0x40];
e281682b
SM		 3634
3635 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3636
b4ff3a36 3637 u8 reserved_at_280[0x600];
e281682b
SM		 3638
3639 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3640
3641 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3642};
3643
3644struct mlx5_ifc_query_mkey_in_bits {
3645 u8 opcode[0x10];
b4ff3a36 3646 u8 reserved_at_10[0x10];
e281682b 3647
b4ff3a36 3648 u8 reserved_at_20[0x10];
e281682b
SM		 3649 u8 op_mod[0x10];
3650
b4ff3a36 3651 u8 reserved_at_40[0x8];
e281682b
SM		 3652 u8 mkey_index[0x18];
3653
3654 u8 pg_access[0x1];
b4ff3a36 3655 u8 reserved_at_61[0x1f];
e281682b
SM		 3656};
3657
3658struct mlx5_ifc_query_mad_demux_out_bits {
3659 u8 status[0x8];
b4ff3a36 3660 u8 reserved_at_8[0x18];
e281682b
SM		 3661
3662 u8 syndrome[0x20];
3663
b4ff3a36 3664 u8 reserved_at_40[0x40];
e281682b
SM		 3665
3666 u8 mad_dumux_parameters_block[0x20];
3667};
3668
3669struct mlx5_ifc_query_mad_demux_in_bits {
3670 u8 opcode[0x10];
b4ff3a36 3671 u8 reserved_at_10[0x10];
e281682b 3672
b4ff3a36 3673 u8 reserved_at_20[0x10];
e281682b
SM		 3674 u8 op_mod[0x10];
3675
b4ff3a36 3676 u8 reserved_at_40[0x40];
e281682b
SM		 3677};
3678
3679struct mlx5_ifc_query_l2_table_entry_out_bits {
3680 u8 status[0x8];
b4ff3a36 3681 u8 reserved_at_8[0x18];
e281682b
SM		 3682
3683 u8 syndrome[0x20];
3684
b4ff3a36 3685 u8 reserved_at_40[0xa0];
e281682b 3686
b4ff3a36 3687 u8 reserved_at_e0[0x13];
e281682b
SM		 3688 u8 vlan_valid[0x1];
3689 u8 vlan[0xc];
3690
3691 struct mlx5_ifc_mac_address_layout_bits mac_address;
3692
b4ff3a36 3693 u8 reserved_at_140[0xc0];
e281682b
SM		 3694};
3695
3696struct mlx5_ifc_query_l2_table_entry_in_bits {
3697 u8 opcode[0x10];
b4ff3a36 3698 u8 reserved_at_10[0x10];
e281682b 3699
b4ff3a36 3700 u8 reserved_at_20[0x10];
e281682b
SM		 3701 u8 op_mod[0x10];
3702
b4ff3a36 3703 u8 reserved_at_40[0x60];
e281682b 3704
b4ff3a36 3705 u8 reserved_at_a0[0x8];
e281682b
SM		 3706 u8 table_index[0x18];
3707
b4ff3a36 3708 u8 reserved_at_c0[0x140];
e281682b
SM		 3709};
3710
3711struct mlx5_ifc_query_issi_out_bits {
3712 u8 status[0x8];
b4ff3a36 3713 u8 reserved_at_8[0x18];
e281682b
SM		 3714
3715 u8 syndrome[0x20];
3716
b4ff3a36 3717 u8 reserved_at_40[0x10];
e281682b
SM		 3718 u8 current_issi[0x10];
3719
b4ff3a36 3720 u8 reserved_at_60[0xa0];
e281682b 3721
b4ff3a36 3722 u8 reserved_at_100[76][0x8];
e281682b
SM		 3723 u8 supported_issi_dw0[0x20];
3724};
3725
3726struct mlx5_ifc_query_issi_in_bits {
3727 u8 opcode[0x10];
b4ff3a36 3728 u8 reserved_at_10[0x10];
e281682b 3729
b4ff3a36 3730 u8 reserved_at_20[0x10];
e281682b
SM		 3731 u8 op_mod[0x10];
3732
b4ff3a36 3733 u8 reserved_at_40[0x40];
e281682b
SM		 3734};
3735
3736struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3737 u8 status[0x8];
b4ff3a36 3738 u8 reserved_at_8[0x18];
e281682b
SM		 3739
3740 u8 syndrome[0x20];
3741
b4ff3a36 3742 u8 reserved_at_40[0x40];
e281682b
SM		 3743
3744 struct mlx5_ifc_pkey_bits pkey[0];
3745};
3746
3747struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3748 u8 opcode[0x10];
b4ff3a36 3749 u8 reserved_at_10[0x10];
e281682b 3750
b4ff3a36 3751 u8 reserved_at_20[0x10];
e281682b
SM		 3752 u8 op_mod[0x10];
3753
3754 u8 other_vport[0x1];
b4ff3a36 3755 u8 reserved_at_41[0xb];
707c4602 3756 u8 port_num[0x4];
e281682b
SM		 3757 u8 vport_number[0x10];
3758
b4ff3a36 3759 u8 reserved_at_60[0x10];
e281682b
SM		 3760 u8 pkey_index[0x10];
3761};
3762
eff901d3
EC		 3763enum {
3764 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3765 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3766 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3767};
3768
e281682b
SM		 3769struct mlx5_ifc_query_hca_vport_gid_out_bits {
3770 u8 status[0x8];
b4ff3a36 3771 u8 reserved_at_8[0x18];
e281682b
SM		 3772
3773 u8 syndrome[0x20];
3774
b4ff3a36 3775 u8 reserved_at_40[0x20];
e281682b
SM		 3776
3777 u8 gids_num[0x10];
b4ff3a36 3778 u8 reserved_at_70[0x10];
e281682b
SM		 3779
3780 struct mlx5_ifc_array128_auto_bits gid[0];
3781};
3782
3783struct mlx5_ifc_query_hca_vport_gid_in_bits {
3784 u8 opcode[0x10];
b4ff3a36 3785 u8 reserved_at_10[0x10];
e281682b 3786
b4ff3a36 3787 u8 reserved_at_20[0x10];
e281682b
SM		 3788 u8 op_mod[0x10];
3789
3790 u8 other_vport[0x1];
b4ff3a36 3791 u8 reserved_at_41[0xb];
707c4602 3792 u8 port_num[0x4];
e281682b
SM		 3793 u8 vport_number[0x10];
3794
b4ff3a36 3795 u8 reserved_at_60[0x10];
e281682b
SM		 3796 u8 gid_index[0x10];
3797};
3798
3799struct mlx5_ifc_query_hca_vport_context_out_bits {
3800 u8 status[0x8];
b4ff3a36 3801 u8 reserved_at_8[0x18];
e281682b
SM		 3802
3803 u8 syndrome[0x20];
3804
b4ff3a36 3805 u8 reserved_at_40[0x40];
e281682b
SM		 3806
3807 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3808};
3809
3810struct mlx5_ifc_query_hca_vport_context_in_bits {
3811 u8 opcode[0x10];
b4ff3a36 3812 u8 reserved_at_10[0x10];
e281682b 3813
b4ff3a36 3814 u8 reserved_at_20[0x10];
e281682b
SM		 3815 u8 op_mod[0x10];
3816
3817 u8 other_vport[0x1];
b4ff3a36 3818 u8 reserved_at_41[0xb];
707c4602 3819 u8 port_num[0x4];
e281682b
SM		 3820 u8 vport_number[0x10];
3821
b4ff3a36 3822 u8 reserved_at_60[0x20];
e281682b
SM		 3823};
3824
3825struct mlx5_ifc_query_hca_cap_out_bits {
3826 u8 status[0x8];
b4ff3a36 3827 u8 reserved_at_8[0x18];
e281682b
SM		 3828
3829 u8 syndrome[0x20];
3830
b4ff3a36 3831 u8 reserved_at_40[0x40];
e281682b
SM		 3832
3833 union mlx5_ifc_hca_cap_union_bits capability;
3834};
3835
3836struct mlx5_ifc_query_hca_cap_in_bits {
3837 u8 opcode[0x10];
b4ff3a36 3838 u8 reserved_at_10[0x10];
e281682b 3839
b4ff3a36 3840 u8 reserved_at_20[0x10];
e281682b
SM		 3841 u8 op_mod[0x10];
3842
b4ff3a36 3843 u8 reserved_at_40[0x40];
e281682b
SM		 3844};
3845
3846struct mlx5_ifc_query_flow_table_out_bits {
3847 u8 status[0x8];
b4ff3a36 3848 u8 reserved_at_8[0x18];
e281682b
SM		 3849
3850 u8 syndrome[0x20];
3851
b4ff3a36 3852 u8 reserved_at_40[0x80];
e281682b 3853
b4ff3a36 3854 u8 reserved_at_c0[0x8];
e281682b 3855 u8 level[0x8];
b4ff3a36 3856 u8 reserved_at_d0[0x8];
e281682b
SM		 3857 u8 log_size[0x8];
3858
b4ff3a36 3859 u8 reserved_at_e0[0x120];
e281682b
SM		 3860};
3861
3862struct mlx5_ifc_query_flow_table_in_bits {
3863 u8 opcode[0x10];
b4ff3a36 3864 u8 reserved_at_10[0x10];
e281682b 3865
b4ff3a36 3866 u8 reserved_at_20[0x10];
e281682b
SM		 3867 u8 op_mod[0x10];
3868
b4ff3a36 3869 u8 reserved_at_40[0x40];
e281682b
SM		 3870
3871 u8 table_type[0x8];
b4ff3a36 3872 u8 reserved_at_88[0x18];
e281682b 3873
b4ff3a36 3874 u8 reserved_at_a0[0x8];
e281682b
SM		 3875 u8 table_id[0x18];
3876
b4ff3a36 3877 u8 reserved_at_c0[0x140];
e281682b
SM		 3878};
3879
3880struct mlx5_ifc_query_fte_out_bits {
3881 u8 status[0x8];
b4ff3a36 3882 u8 reserved_at_8[0x18];
e281682b
SM		 3883
3884 u8 syndrome[0x20];
3885
b4ff3a36 3886 u8 reserved_at_40[0x1c0];
e281682b
SM		 3887
3888 struct mlx5_ifc_flow_context_bits flow_context;
3889};
3890
3891struct mlx5_ifc_query_fte_in_bits {
3892 u8 opcode[0x10];
b4ff3a36 3893 u8 reserved_at_10[0x10];
e281682b 3894
b4ff3a36 3895 u8 reserved_at_20[0x10];
e281682b
SM		 3896 u8 op_mod[0x10];
3897
b4ff3a36 3898 u8 reserved_at_40[0x40];
e281682b
SM		 3899
3900 u8 table_type[0x8];
b4ff3a36 3901 u8 reserved_at_88[0x18];
e281682b 3902
b4ff3a36 3903 u8 reserved_at_a0[0x8];
e281682b
SM		 3904 u8 table_id[0x18];
3905
b4ff3a36 3906 u8 reserved_at_c0[0x40];
e281682b
SM		 3907
3908 u8 flow_index[0x20];
3909
b4ff3a36 3910 u8 reserved_at_120[0xe0];
e281682b
SM		 3911};
3912
3913enum {
3914 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3915 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3916 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3917};
3918
3919struct mlx5_ifc_query_flow_group_out_bits {
3920 u8 status[0x8];
b4ff3a36 3921 u8 reserved_at_8[0x18];
e281682b
SM		 3922
3923 u8 syndrome[0x20];
3924
b4ff3a36 3925 u8 reserved_at_40[0xa0];
e281682b
SM		 3926
3927 u8 start_flow_index[0x20];
3928
b4ff3a36 3929 u8 reserved_at_100[0x20];
e281682b
SM		 3930
3931 u8 end_flow_index[0x20];
3932
b4ff3a36 3933 u8 reserved_at_140[0xa0];
e281682b 3934
b4ff3a36 3935 u8 reserved_at_1e0[0x18];
e281682b
SM		 3936 u8 match_criteria_enable[0x8];
3937
3938 struct mlx5_ifc_fte_match_param_bits match_criteria;
3939
b4ff3a36 3940 u8 reserved_at_1200[0xe00];
e281682b
SM		 3941};
3942
3943struct mlx5_ifc_query_flow_group_in_bits {
3944 u8 opcode[0x10];
b4ff3a36 3945 u8 reserved_at_10[0x10];
e281682b 3946
b4ff3a36 3947 u8 reserved_at_20[0x10];
e281682b
SM		 3948 u8 op_mod[0x10];
3949
b4ff3a36 3950 u8 reserved_at_40[0x40];
e281682b
SM		 3951
3952 u8 table_type[0x8];
b4ff3a36 3953 u8 reserved_at_88[0x18];
e281682b 3954
b4ff3a36 3955 u8 reserved_at_a0[0x8];
e281682b
SM		 3956 u8 table_id[0x18];
3957
3958 u8 group_id[0x20];
3959
b4ff3a36 3960 u8 reserved_at_e0[0x120];
e281682b
SM		 3961};
3962
9dc0b289
AV		 3963struct mlx5_ifc_query_flow_counter_out_bits {
3964 u8 status[0x8];
3965 u8 reserved_at_8[0x18];
3966
3967 u8 syndrome[0x20];
3968
3969 u8 reserved_at_40[0x40];
3970
3971 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
3972};
3973
3974struct mlx5_ifc_query_flow_counter_in_bits {
3975 u8 opcode[0x10];
3976 u8 reserved_at_10[0x10];
3977
3978 u8 reserved_at_20[0x10];
3979 u8 op_mod[0x10];
3980
3981 u8 reserved_at_40[0x80];
3982
3983 u8 clear[0x1];
3984 u8 reserved_at_c1[0xf];
3985 u8 num_of_counters[0x10];
3986
3987 u8 reserved_at_e0[0x10];
3988 u8 flow_counter_id[0x10];
3989};
3990
d6666753
SM		 3991struct mlx5_ifc_query_esw_vport_context_out_bits {
3992 u8 status[0x8];
b4ff3a36 3993 u8 reserved_at_8[0x18];
d6666753
SM		 3994
3995 u8 syndrome[0x20];
3996
b4ff3a36 3997 u8 reserved_at_40[0x40];
d6666753
SM		 3998
3999 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4000};
4001
4002struct mlx5_ifc_query_esw_vport_context_in_bits {
4003 u8 opcode[0x10];
b4ff3a36 4004 u8 reserved_at_10[0x10];
d6666753 4005
b4ff3a36 4006 u8 reserved_at_20[0x10];
d6666753
SM		 4007 u8 op_mod[0x10];
4008
4009 u8 other_vport[0x1];
b4ff3a36 4010 u8 reserved_at_41[0xf];
d6666753
SM		 4011 u8 vport_number[0x10];
4012
b4ff3a36 4013 u8 reserved_at_60[0x20];
d6666753
SM		 4014};
4015
4016struct mlx5_ifc_modify_esw_vport_context_out_bits {
4017 u8 status[0x8];
b4ff3a36 4018 u8 reserved_at_8[0x18];
d6666753
SM		 4019
4020 u8 syndrome[0x20];
4021
b4ff3a36 4022 u8 reserved_at_40[0x40];
d6666753
SM		 4023};
4024
4025struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4026 u8 reserved_at_0[0x1c];
d6666753
SM		 4027 u8 vport_cvlan_insert[0x1];
4028 u8 vport_svlan_insert[0x1];
4029 u8 vport_cvlan_strip[0x1];
4030 u8 vport_svlan_strip[0x1];
4031};
4032
4033struct mlx5_ifc_modify_esw_vport_context_in_bits {
4034 u8 opcode[0x10];
b4ff3a36 4035 u8 reserved_at_10[0x10];
d6666753 4036
b4ff3a36 4037 u8 reserved_at_20[0x10];
d6666753
SM		 4038 u8 op_mod[0x10];
4039
4040 u8 other_vport[0x1];
b4ff3a36 4041 u8 reserved_at_41[0xf];
d6666753
SM		 4042 u8 vport_number[0x10];
4043
4044 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4045
4046 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4047};
4048
e281682b
SM		 4049struct mlx5_ifc_query_eq_out_bits {
4050 u8 status[0x8];
b4ff3a36 4051 u8 reserved_at_8[0x18];
e281682b
SM		 4052
4053 u8 syndrome[0x20];
4054
b4ff3a36 4055 u8 reserved_at_40[0x40];
e281682b
SM		 4056
4057 struct mlx5_ifc_eqc_bits eq_context_entry;
4058
b4ff3a36 4059 u8 reserved_at_280[0x40];
e281682b
SM		 4060
4061 u8 event_bitmask[0x40];
4062
b4ff3a36 4063 u8 reserved_at_300[0x580];
e281682b
SM		 4064
4065 u8 pas[0][0x40];
4066};
4067
4068struct mlx5_ifc_query_eq_in_bits {
4069 u8 opcode[0x10];
b4ff3a36 4070 u8 reserved_at_10[0x10];
e281682b 4071
b4ff3a36 4072 u8 reserved_at_20[0x10];
e281682b
SM		 4073 u8 op_mod[0x10];
4074
b4ff3a36 4075 u8 reserved_at_40[0x18];
e281682b
SM		 4076 u8 eq_number[0x8];
4077
b4ff3a36 4078 u8 reserved_at_60[0x20];
e281682b
SM		 4079};
4080
4081struct mlx5_ifc_query_dct_out_bits {
4082 u8 status[0x8];
b4ff3a36 4083 u8 reserved_at_8[0x18];
e281682b
SM		 4084
4085 u8 syndrome[0x20];
4086
b4ff3a36 4087 u8 reserved_at_40[0x40];
e281682b
SM		 4088
4089 struct mlx5_ifc_dctc_bits dct_context_entry;
4090
b4ff3a36 4091 u8 reserved_at_280[0x180];
e281682b
SM		 4092};
4093
4094struct mlx5_ifc_query_dct_in_bits {
4095 u8 opcode[0x10];
b4ff3a36 4096 u8 reserved_at_10[0x10];
e281682b 4097
b4ff3a36 4098 u8 reserved_at_20[0x10];
e281682b
SM		 4099 u8 op_mod[0x10];
4100
b4ff3a36 4101 u8 reserved_at_40[0x8];
e281682b
SM		 4102 u8 dctn[0x18];
4103
b4ff3a36 4104 u8 reserved_at_60[0x20];
e281682b
SM		 4105};
4106
4107struct mlx5_ifc_query_cq_out_bits {
4108 u8 status[0x8];
b4ff3a36 4109 u8 reserved_at_8[0x18];
e281682b
SM		 4110
4111 u8 syndrome[0x20];
4112
b4ff3a36 4113 u8 reserved_at_40[0x40];
e281682b
SM		 4114
4115 struct mlx5_ifc_cqc_bits cq_context;
4116
b4ff3a36 4117 u8 reserved_at_280[0x600];
e281682b
SM		 4118
4119 u8 pas[0][0x40];
4120};
4121
4122struct mlx5_ifc_query_cq_in_bits {
4123 u8 opcode[0x10];
b4ff3a36 4124 u8 reserved_at_10[0x10];
e281682b 4125
b4ff3a36 4126 u8 reserved_at_20[0x10];
e281682b
SM		 4127 u8 op_mod[0x10];
4128
b4ff3a36 4129 u8 reserved_at_40[0x8];
e281682b
SM		 4130 u8 cqn[0x18];
4131
b4ff3a36 4132 u8 reserved_at_60[0x20];
e281682b
SM		 4133};
4134
4135struct mlx5_ifc_query_cong_status_out_bits {
4136 u8 status[0x8];
b4ff3a36 4137 u8 reserved_at_8[0x18];
e281682b
SM		 4138
4139 u8 syndrome[0x20];
4140
b4ff3a36 4141 u8 reserved_at_40[0x20];
e281682b
SM		 4142
4143 u8 enable[0x1];
4144 u8 tag_enable[0x1];
b4ff3a36 4145 u8 reserved_at_62[0x1e];
e281682b
SM		 4146};
4147
4148struct mlx5_ifc_query_cong_status_in_bits {
4149 u8 opcode[0x10];
b4ff3a36 4150 u8 reserved_at_10[0x10];
e281682b 4151
b4ff3a36 4152 u8 reserved_at_20[0x10];
e281682b
SM		 4153 u8 op_mod[0x10];
4154
b4ff3a36 4155 u8 reserved_at_40[0x18];
e281682b
SM		 4156 u8 priority[0x4];
4157 u8 cong_protocol[0x4];
4158
b4ff3a36 4159 u8 reserved_at_60[0x20];
e281682b
SM		 4160};
4161
4162struct mlx5_ifc_query_cong_statistics_out_bits {
4163 u8 status[0x8];
b4ff3a36 4164 u8 reserved_at_8[0x18];
e281682b
SM		 4165
4166 u8 syndrome[0x20];
4167
b4ff3a36 4168 u8 reserved_at_40[0x40];
e281682b
SM		 4169
4170 u8 cur_flows[0x20];
4171
4172 u8 sum_flows[0x20];
4173
4174 u8 cnp_ignored_high[0x20];
4175
4176 u8 cnp_ignored_low[0x20];
4177
4178 u8 cnp_handled_high[0x20];
4179
4180 u8 cnp_handled_low[0x20];
4181
b4ff3a36 4182 u8 reserved_at_140[0x100];
e281682b
SM		 4183
4184 u8 time_stamp_high[0x20];
4185
4186 u8 time_stamp_low[0x20];
4187
4188 u8 accumulators_period[0x20];
4189
4190 u8 ecn_marked_roce_packets_high[0x20];
4191
4192 u8 ecn_marked_roce_packets_low[0x20];
4193
4194 u8 cnps_sent_high[0x20];
4195
4196 u8 cnps_sent_low[0x20];
4197
b4ff3a36 4198 u8 reserved_at_320[0x560];
e281682b
SM		 4199};
4200
4201struct mlx5_ifc_query_cong_statistics_in_bits {
4202 u8 opcode[0x10];
b4ff3a36 4203 u8 reserved_at_10[0x10];
e281682b 4204
b4ff3a36 4205 u8 reserved_at_20[0x10];
e281682b
SM		 4206 u8 op_mod[0x10];
4207
4208 u8 clear[0x1];
b4ff3a36 4209 u8 reserved_at_41[0x1f];
e281682b 4210
b4ff3a36 4211 u8 reserved_at_60[0x20];
e281682b
SM		 4212};
4213
4214struct mlx5_ifc_query_cong_params_out_bits {
4215 u8 status[0x8];
b4ff3a36 4216 u8 reserved_at_8[0x18];
e281682b
SM		 4217
4218 u8 syndrome[0x20];
4219
b4ff3a36 4220 u8 reserved_at_40[0x40];
e281682b
SM		 4221
4222 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4223};
4224
4225struct mlx5_ifc_query_cong_params_in_bits {
4226 u8 opcode[0x10];
b4ff3a36 4227 u8 reserved_at_10[0x10];
e281682b 4228
b4ff3a36 4229 u8 reserved_at_20[0x10];
e281682b
SM		 4230 u8 op_mod[0x10];
4231
b4ff3a36 4232 u8 reserved_at_40[0x1c];
e281682b
SM		 4233 u8 cong_protocol[0x4];
4234
b4ff3a36 4235 u8 reserved_at_60[0x20];
e281682b
SM		 4236};
4237
4238struct mlx5_ifc_query_adapter_out_bits {
4239 u8 status[0x8];
b4ff3a36 4240 u8 reserved_at_8[0x18];
e281682b
SM		 4241
4242 u8 syndrome[0x20];
4243
b4ff3a36 4244 u8 reserved_at_40[0x40];
e281682b
SM		 4245
4246 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4247};
4248
4249struct mlx5_ifc_query_adapter_in_bits {
4250 u8 opcode[0x10];
b4ff3a36 4251 u8 reserved_at_10[0x10];
e281682b 4252
b4ff3a36 4253 u8 reserved_at_20[0x10];
e281682b
SM		 4254 u8 op_mod[0x10];
4255
b4ff3a36 4256 u8 reserved_at_40[0x40];
e281682b
SM		 4257};
4258
4259struct mlx5_ifc_qp_2rst_out_bits {
4260 u8 status[0x8];
b4ff3a36 4261 u8 reserved_at_8[0x18];
e281682b
SM		 4262
4263 u8 syndrome[0x20];
4264
b4ff3a36 4265 u8 reserved_at_40[0x40];
e281682b
SM		 4266};
4267
4268struct mlx5_ifc_qp_2rst_in_bits {
4269 u8 opcode[0x10];
b4ff3a36 4270 u8 reserved_at_10[0x10];
e281682b 4271
b4ff3a36 4272 u8 reserved_at_20[0x10];
e281682b
SM		 4273 u8 op_mod[0x10];
4274
b4ff3a36 4275 u8 reserved_at_40[0x8];
e281682b
SM		 4276 u8 qpn[0x18];
4277
b4ff3a36 4278 u8 reserved_at_60[0x20];
e281682b
SM		 4279};
4280
4281struct mlx5_ifc_qp_2err_out_bits {
4282 u8 status[0x8];
b4ff3a36 4283 u8 reserved_at_8[0x18];
e281682b
SM		 4284
4285 u8 syndrome[0x20];
4286
b4ff3a36 4287 u8 reserved_at_40[0x40];
e281682b
SM		 4288};
4289
4290struct mlx5_ifc_qp_2err_in_bits {
4291 u8 opcode[0x10];
b4ff3a36 4292 u8 reserved_at_10[0x10];
e281682b 4293
b4ff3a36 4294 u8 reserved_at_20[0x10];
e281682b
SM		 4295 u8 op_mod[0x10];
4296
b4ff3a36 4297 u8 reserved_at_40[0x8];
e281682b
SM		 4298 u8 qpn[0x18];
4299
b4ff3a36 4300 u8 reserved_at_60[0x20];
e281682b
SM		 4301};
4302
4303struct mlx5_ifc_page_fault_resume_out_bits {
4304 u8 status[0x8];
b4ff3a36 4305 u8 reserved_at_8[0x18];
e281682b
SM		 4306
4307 u8 syndrome[0x20];
4308
b4ff3a36 4309 u8 reserved_at_40[0x40];
e281682b
SM		 4310};
4311
4312struct mlx5_ifc_page_fault_resume_in_bits {
4313 u8 opcode[0x10];
b4ff3a36 4314 u8 reserved_at_10[0x10];
e281682b 4315
b4ff3a36 4316 u8 reserved_at_20[0x10];
e281682b
SM		 4317 u8 op_mod[0x10];
4318
4319 u8 error[0x1];
b4ff3a36 4320 u8 reserved_at_41[0x4];
e281682b
SM		 4321 u8 rdma[0x1];
4322 u8 read_write[0x1];
4323 u8 req_res[0x1];
4324 u8 qpn[0x18];
4325
b4ff3a36 4326 u8 reserved_at_60[0x20];
e281682b
SM		 4327};
4328
4329struct mlx5_ifc_nop_out_bits {
4330 u8 status[0x8];
b4ff3a36 4331 u8 reserved_at_8[0x18];
e281682b
SM		 4332
4333 u8 syndrome[0x20];
4334
b4ff3a36 4335 u8 reserved_at_40[0x40];
e281682b
SM		 4336};
4337
4338struct mlx5_ifc_nop_in_bits {
4339 u8 opcode[0x10];
b4ff3a36 4340 u8 reserved_at_10[0x10];
e281682b 4341
b4ff3a36 4342 u8 reserved_at_20[0x10];
e281682b
SM		 4343 u8 op_mod[0x10];
4344
b4ff3a36 4345 u8 reserved_at_40[0x40];
e281682b
SM		 4346};
4347
4348struct mlx5_ifc_modify_vport_state_out_bits {
4349 u8 status[0x8];
b4ff3a36 4350 u8 reserved_at_8[0x18];
e281682b
SM		 4351
4352 u8 syndrome[0x20];
4353
b4ff3a36 4354 u8 reserved_at_40[0x40];
e281682b
SM		 4355};
4356
4357struct mlx5_ifc_modify_vport_state_in_bits {
4358 u8 opcode[0x10];
b4ff3a36 4359 u8 reserved_at_10[0x10];
e281682b 4360
b4ff3a36 4361 u8 reserved_at_20[0x10];
e281682b
SM		 4362 u8 op_mod[0x10];
4363
4364 u8 other_vport[0x1];
b4ff3a36 4365 u8 reserved_at_41[0xf];
e281682b
SM		 4366 u8 vport_number[0x10];
4367
b4ff3a36 4368 u8 reserved_at_60[0x18];
e281682b 4369 u8 admin_state[0x4];
b4ff3a36 4370 u8 reserved_at_7c[0x4];
e281682b
SM		 4371};
4372
4373struct mlx5_ifc_modify_tis_out_bits {
4374 u8 status[0x8];
b4ff3a36 4375 u8 reserved_at_8[0x18];
e281682b
SM		 4376
4377 u8 syndrome[0x20];
4378
b4ff3a36 4379 u8 reserved_at_40[0x40];
e281682b
SM		 4380};
4381
75850d0b 4382struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4383 u8 reserved_at_0[0x20];
75850d0b 4384
b4ff3a36 4385 u8 reserved_at_20[0x1f];
75850d0b 4386 u8 prio[0x1];
4387};
4388
e281682b
SM		 4389struct mlx5_ifc_modify_tis_in_bits {
4390 u8 opcode[0x10];
b4ff3a36 4391 u8 reserved_at_10[0x10];
e281682b 4392
b4ff3a36 4393 u8 reserved_at_20[0x10];
e281682b
SM		 4394 u8 op_mod[0x10];
4395
b4ff3a36 4396 u8 reserved_at_40[0x8];
e281682b
SM		 4397 u8 tisn[0x18];
4398
b4ff3a36 4399 u8 reserved_at_60[0x20];
e281682b 4400
75850d0b 4401 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4402
b4ff3a36 4403 u8 reserved_at_c0[0x40];
e281682b
SM		 4404
4405 struct mlx5_ifc_tisc_bits ctx;
4406};
4407
d9eea403 4408struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4409 u8 reserved_at_0[0x20];
d9eea403 4410
b4ff3a36 4411 u8 reserved_at_20[0x1b];
66189961 4412 u8 self_lb_en[0x1];
bdfc028d
TT		 4413 u8 reserved_at_3c[0x1];
4414 u8 hash[0x1];
4415 u8 reserved_at_3e[0x1];
d9eea403
AS		 4416 u8 lro[0x1];
4417};
4418
e281682b
SM		 4419struct mlx5_ifc_modify_tir_out_bits {
4420 u8 status[0x8];
b4ff3a36 4421 u8 reserved_at_8[0x18];
e281682b
SM		 4422
4423 u8 syndrome[0x20];
4424
b4ff3a36 4425 u8 reserved_at_40[0x40];
e281682b
SM		 4426};
4427
4428struct mlx5_ifc_modify_tir_in_bits {
4429 u8 opcode[0x10];
b4ff3a36 4430 u8 reserved_at_10[0x10];
e281682b 4431
b4ff3a36 4432 u8 reserved_at_20[0x10];
e281682b
SM		 4433 u8 op_mod[0x10];
4434
b4ff3a36 4435 u8 reserved_at_40[0x8];
e281682b
SM		 4436 u8 tirn[0x18];
4437
b4ff3a36 4438 u8 reserved_at_60[0x20];
e281682b 4439
d9eea403 4440 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4441
b4ff3a36 4442 u8 reserved_at_c0[0x40];
e281682b
SM		 4443
4444 struct mlx5_ifc_tirc_bits ctx;
4445};
4446
4447struct mlx5_ifc_modify_sq_out_bits {
4448 u8 status[0x8];
b4ff3a36 4449 u8 reserved_at_8[0x18];
e281682b
SM		 4450
4451 u8 syndrome[0x20];
4452
b4ff3a36 4453 u8 reserved_at_40[0x40];
e281682b
SM		 4454};
4455
4456struct mlx5_ifc_modify_sq_in_bits {
4457 u8 opcode[0x10];
b4ff3a36 4458 u8 reserved_at_10[0x10];
e281682b 4459
b4ff3a36 4460 u8 reserved_at_20[0x10];
e281682b
SM		 4461 u8 op_mod[0x10];
4462
4463 u8 sq_state[0x4];
b4ff3a36 4464 u8 reserved_at_44[0x4];
e281682b
SM		 4465 u8 sqn[0x18];
4466
b4ff3a36 4467 u8 reserved_at_60[0x20];
e281682b
SM		 4468
4469 u8 modify_bitmask[0x40];
4470
b4ff3a36 4471 u8 reserved_at_c0[0x40];
e281682b
SM		 4472
4473 struct mlx5_ifc_sqc_bits ctx;
4474};
4475
4476struct mlx5_ifc_modify_rqt_out_bits {
4477 u8 status[0x8];
b4ff3a36 4478 u8 reserved_at_8[0x18];
e281682b
SM		 4479
4480 u8 syndrome[0x20];
4481
b4ff3a36 4482 u8 reserved_at_40[0x40];
e281682b
SM		 4483};
4484
5c50368f 4485struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4486 u8 reserved_at_0[0x20];
5c50368f 4487
b4ff3a36 4488 u8 reserved_at_20[0x1f];
5c50368f
AS		 4489 u8 rqn_list[0x1];
4490};
4491
e281682b
SM		 4492struct mlx5_ifc_modify_rqt_in_bits {
4493 u8 opcode[0x10];
b4ff3a36 4494 u8 reserved_at_10[0x10];
e281682b 4495
b4ff3a36 4496 u8 reserved_at_20[0x10];
e281682b
SM		 4497 u8 op_mod[0x10];
4498
b4ff3a36 4499 u8 reserved_at_40[0x8];
e281682b
SM		 4500 u8 rqtn[0x18];
4501
b4ff3a36 4502 u8 reserved_at_60[0x20];
e281682b 4503
5c50368f 4504 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4505
b4ff3a36 4506 u8 reserved_at_c0[0x40];
e281682b
SM		 4507
4508 struct mlx5_ifc_rqtc_bits ctx;
4509};
4510
4511struct mlx5_ifc_modify_rq_out_bits {
4512 u8 status[0x8];
b4ff3a36 4513 u8 reserved_at_8[0x18];
e281682b
SM		 4514
4515 u8 syndrome[0x20];
4516
b4ff3a36 4517 u8 reserved_at_40[0x40];
e281682b
SM		 4518};
4519
4520struct mlx5_ifc_modify_rq_in_bits {
4521 u8 opcode[0x10];
b4ff3a36 4522 u8 reserved_at_10[0x10];
e281682b 4523
b4ff3a36 4524 u8 reserved_at_20[0x10];
e281682b
SM		 4525 u8 op_mod[0x10];
4526
4527 u8 rq_state[0x4];
b4ff3a36 4528 u8 reserved_at_44[0x4];
e281682b
SM		 4529 u8 rqn[0x18];
4530
b4ff3a36 4531 u8 reserved_at_60[0x20];
e281682b
SM		 4532
4533 u8 modify_bitmask[0x40];
4534
b4ff3a36 4535 u8 reserved_at_c0[0x40];
e281682b
SM		 4536
4537 struct mlx5_ifc_rqc_bits ctx;
4538};
4539
4540struct mlx5_ifc_modify_rmp_out_bits {
4541 u8 status[0x8];
b4ff3a36 4542 u8 reserved_at_8[0x18];
e281682b
SM		 4543
4544 u8 syndrome[0x20];
4545
b4ff3a36 4546 u8 reserved_at_40[0x40];
e281682b
SM		 4547};
4548
01949d01 4549struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 4550 u8 reserved_at_0[0x20];
01949d01 4551
b4ff3a36 4552 u8 reserved_at_20[0x1f];
01949d01
HA		 4553 u8 lwm[0x1];
4554};
4555
e281682b
SM		 4556struct mlx5_ifc_modify_rmp_in_bits {
4557 u8 opcode[0x10];
b4ff3a36 4558 u8 reserved_at_10[0x10];
e281682b 4559
b4ff3a36 4560 u8 reserved_at_20[0x10];
e281682b
SM		 4561 u8 op_mod[0x10];
4562
4563 u8 rmp_state[0x4];
b4ff3a36 4564 u8 reserved_at_44[0x4];
e281682b
SM		 4565 u8 rmpn[0x18];
4566
b4ff3a36 4567 u8 reserved_at_60[0x20];
e281682b 4568
01949d01 4569 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 4570
b4ff3a36 4571 u8 reserved_at_c0[0x40];
e281682b
SM		 4572
4573 struct mlx5_ifc_rmpc_bits ctx;
4574};
4575
4576struct mlx5_ifc_modify_nic_vport_context_out_bits {
4577 u8 status[0x8];
b4ff3a36 4578 u8 reserved_at_8[0x18];
e281682b
SM		 4579
4580 u8 syndrome[0x20];
4581
b4ff3a36 4582 u8 reserved_at_40[0x40];
e281682b
SM		 4583};
4584
4585struct mlx5_ifc_modify_nic_vport_field_select_bits {
b4ff3a36 4586 u8 reserved_at_0[0x19];
d82b7318
SM		 4587 u8 mtu[0x1];
4588 u8 change_event[0x1];
4589 u8 promisc[0x1];
e281682b
SM		 4590 u8 permanent_address[0x1];
4591 u8 addresses_list[0x1];
4592 u8 roce_en[0x1];
b4ff3a36 4593 u8 reserved_at_1f[0x1];
e281682b
SM		 4594};
4595
4596struct mlx5_ifc_modify_nic_vport_context_in_bits {
4597 u8 opcode[0x10];
b4ff3a36 4598 u8 reserved_at_10[0x10];
e281682b 4599
b4ff3a36 4600 u8 reserved_at_20[0x10];
e281682b
SM		 4601 u8 op_mod[0x10];
4602
4603 u8 other_vport[0x1];
b4ff3a36 4604 u8 reserved_at_41[0xf];
e281682b
SM		 4605 u8 vport_number[0x10];
4606
4607 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4608
b4ff3a36 4609 u8 reserved_at_80[0x780];
e281682b
SM		 4610
4611 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4612};
4613
4614struct mlx5_ifc_modify_hca_vport_context_out_bits {
4615 u8 status[0x8];
b4ff3a36 4616 u8 reserved_at_8[0x18];
e281682b
SM		 4617
4618 u8 syndrome[0x20];
4619
b4ff3a36 4620 u8 reserved_at_40[0x40];
e281682b
SM		 4621};
4622
4623struct mlx5_ifc_modify_hca_vport_context_in_bits {
4624 u8 opcode[0x10];
b4ff3a36 4625 u8 reserved_at_10[0x10];
e281682b 4626
b4ff3a36 4627 u8 reserved_at_20[0x10];
e281682b
SM		 4628 u8 op_mod[0x10];
4629
4630 u8 other_vport[0x1];
b4ff3a36 4631 u8 reserved_at_41[0xb];
707c4602 4632 u8 port_num[0x4];
e281682b
SM		 4633 u8 vport_number[0x10];
4634
b4ff3a36 4635 u8 reserved_at_60[0x20];
e281682b
SM		 4636
4637 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4638};
4639
4640struct mlx5_ifc_modify_cq_out_bits {
4641 u8 status[0x8];
b4ff3a36 4642 u8 reserved_at_8[0x18];
e281682b
SM		 4643
4644 u8 syndrome[0x20];
4645
b4ff3a36 4646 u8 reserved_at_40[0x40];
e281682b
SM		 4647};
4648
4649enum {
4650 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4651 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4652};
4653
4654struct mlx5_ifc_modify_cq_in_bits {
4655 u8 opcode[0x10];
b4ff3a36 4656 u8 reserved_at_10[0x10];
e281682b 4657
b4ff3a36 4658 u8 reserved_at_20[0x10];
e281682b
SM		 4659 u8 op_mod[0x10];
4660
b4ff3a36 4661 u8 reserved_at_40[0x8];
e281682b
SM		 4662 u8 cqn[0x18];
4663
4664 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4665
4666 struct mlx5_ifc_cqc_bits cq_context;
4667
b4ff3a36 4668 u8 reserved_at_280[0x600];
e281682b
SM		 4669
4670 u8 pas[0][0x40];
4671};
4672
4673struct mlx5_ifc_modify_cong_status_out_bits {
4674 u8 status[0x8];
b4ff3a36 4675 u8 reserved_at_8[0x18];
e281682b
SM		 4676
4677 u8 syndrome[0x20];
4678
b4ff3a36 4679 u8 reserved_at_40[0x40];
e281682b
SM		 4680};
4681
4682struct mlx5_ifc_modify_cong_status_in_bits {
4683 u8 opcode[0x10];
b4ff3a36 4684 u8 reserved_at_10[0x10];
e281682b 4685
b4ff3a36 4686 u8 reserved_at_20[0x10];
e281682b
SM		 4687 u8 op_mod[0x10];
4688
b4ff3a36 4689 u8 reserved_at_40[0x18];
e281682b
SM		 4690 u8 priority[0x4];
4691 u8 cong_protocol[0x4];
4692
4693 u8 enable[0x1];
4694 u8 tag_enable[0x1];
b4ff3a36 4695 u8 reserved_at_62[0x1e];
e281682b
SM		 4696};
4697
4698struct mlx5_ifc_modify_cong_params_out_bits {
4699 u8 status[0x8];
b4ff3a36 4700 u8 reserved_at_8[0x18];
e281682b
SM		 4701
4702 u8 syndrome[0x20];
4703
b4ff3a36 4704 u8 reserved_at_40[0x40];
e281682b
SM		 4705};
4706
4707struct mlx5_ifc_modify_cong_params_in_bits {
4708 u8 opcode[0x10];
b4ff3a36 4709 u8 reserved_at_10[0x10];
e281682b 4710
b4ff3a36 4711 u8 reserved_at_20[0x10];
e281682b
SM		 4712 u8 op_mod[0x10];
4713
b4ff3a36 4714 u8 reserved_at_40[0x1c];
e281682b
SM		 4715 u8 cong_protocol[0x4];
4716
4717 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4718
b4ff3a36 4719 u8 reserved_at_80[0x80];
e281682b
SM		 4720
4721 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4722};
4723
4724struct mlx5_ifc_manage_pages_out_bits {
4725 u8 status[0x8];
b4ff3a36 4726 u8 reserved_at_8[0x18];
e281682b
SM		 4727
4728 u8 syndrome[0x20];
4729
4730 u8 output_num_entries[0x20];
4731
b4ff3a36 4732 u8 reserved_at_60[0x20];
e281682b
SM		 4733
4734 u8 pas[0][0x40];
4735};
4736
4737enum {
4738 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4739 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4740 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4741};
4742
4743struct mlx5_ifc_manage_pages_in_bits {
4744 u8 opcode[0x10];
b4ff3a36 4745 u8 reserved_at_10[0x10];
e281682b 4746
b4ff3a36 4747 u8 reserved_at_20[0x10];
e281682b
SM		 4748 u8 op_mod[0x10];
4749
b4ff3a36 4750 u8 reserved_at_40[0x10];
e281682b
SM		 4751 u8 function_id[0x10];
4752
4753 u8 input_num_entries[0x20];
4754
4755 u8 pas[0][0x40];
4756};
4757
4758struct mlx5_ifc_mad_ifc_out_bits {
4759 u8 status[0x8];
b4ff3a36 4760 u8 reserved_at_8[0x18];
e281682b
SM		 4761
4762 u8 syndrome[0x20];
4763
b4ff3a36 4764 u8 reserved_at_40[0x40];
e281682b
SM		 4765
4766 u8 response_mad_packet[256][0x8];
4767};
4768
4769struct mlx5_ifc_mad_ifc_in_bits {
4770 u8 opcode[0x10];
b4ff3a36 4771 u8 reserved_at_10[0x10];
e281682b 4772
b4ff3a36 4773 u8 reserved_at_20[0x10];
e281682b
SM		 4774 u8 op_mod[0x10];
4775
4776 u8 remote_lid[0x10];
b4ff3a36 4777 u8 reserved_at_50[0x8];
e281682b
SM		 4778 u8 port[0x8];
4779
b4ff3a36 4780 u8 reserved_at_60[0x20];
e281682b
SM		 4781
4782 u8 mad[256][0x8];
4783};
4784
4785struct mlx5_ifc_init_hca_out_bits {
4786 u8 status[0x8];
b4ff3a36 4787 u8 reserved_at_8[0x18];
e281682b
SM		 4788
4789 u8 syndrome[0x20];
4790
b4ff3a36 4791 u8 reserved_at_40[0x40];
e281682b
SM		 4792};
4793
4794struct mlx5_ifc_init_hca_in_bits {
4795 u8 opcode[0x10];
b4ff3a36 4796 u8 reserved_at_10[0x10];
e281682b 4797
b4ff3a36 4798 u8 reserved_at_20[0x10];
e281682b
SM		 4799 u8 op_mod[0x10];
4800
b4ff3a36 4801 u8 reserved_at_40[0x40];
e281682b
SM		 4802};
4803
4804struct mlx5_ifc_init2rtr_qp_out_bits {
4805 u8 status[0x8];
b4ff3a36 4806 u8 reserved_at_8[0x18];
e281682b
SM		 4807
4808 u8 syndrome[0x20];
4809
b4ff3a36 4810 u8 reserved_at_40[0x40];
e281682b
SM		 4811};
4812
4813struct mlx5_ifc_init2rtr_qp_in_bits {
4814 u8 opcode[0x10];
b4ff3a36 4815 u8 reserved_at_10[0x10];
e281682b 4816
b4ff3a36 4817 u8 reserved_at_20[0x10];
e281682b
SM		 4818 u8 op_mod[0x10];
4819
b4ff3a36 4820 u8 reserved_at_40[0x8];
e281682b
SM		 4821 u8 qpn[0x18];
4822
b4ff3a36 4823 u8 reserved_at_60[0x20];
e281682b
SM		 4824
4825 u8 opt_param_mask[0x20];
4826
b4ff3a36 4827 u8 reserved_at_a0[0x20];
e281682b
SM		 4828
4829 struct mlx5_ifc_qpc_bits qpc;
4830
b4ff3a36 4831 u8 reserved_at_800[0x80];
e281682b
SM		 4832};
4833
4834struct mlx5_ifc_init2init_qp_out_bits {
4835 u8 status[0x8];
b4ff3a36 4836 u8 reserved_at_8[0x18];
e281682b
SM		 4837
4838 u8 syndrome[0x20];
4839
b4ff3a36 4840 u8 reserved_at_40[0x40];
e281682b
SM		 4841};
4842
4843struct mlx5_ifc_init2init_qp_in_bits {
4844 u8 opcode[0x10];
b4ff3a36 4845 u8 reserved_at_10[0x10];
e281682b 4846
b4ff3a36 4847 u8 reserved_at_20[0x10];
e281682b
SM		 4848 u8 op_mod[0x10];
4849
b4ff3a36 4850 u8 reserved_at_40[0x8];
e281682b
SM		 4851 u8 qpn[0x18];
4852
b4ff3a36 4853 u8 reserved_at_60[0x20];
e281682b
SM		 4854
4855 u8 opt_param_mask[0x20];
4856
b4ff3a36 4857 u8 reserved_at_a0[0x20];
e281682b
SM		 4858
4859 struct mlx5_ifc_qpc_bits qpc;
4860
b4ff3a36 4861 u8 reserved_at_800[0x80];
e281682b
SM		 4862};
4863
4864struct mlx5_ifc_get_dropped_packet_log_out_bits {
4865 u8 status[0x8];
b4ff3a36 4866 u8 reserved_at_8[0x18];
e281682b
SM		 4867
4868 u8 syndrome[0x20];
4869
b4ff3a36 4870 u8 reserved_at_40[0x40];
e281682b
SM		 4871
4872 u8 packet_headers_log[128][0x8];
4873
4874 u8 packet_syndrome[64][0x8];
4875};
4876
4877struct mlx5_ifc_get_dropped_packet_log_in_bits {
4878 u8 opcode[0x10];
b4ff3a36 4879 u8 reserved_at_10[0x10];
e281682b 4880
b4ff3a36 4881 u8 reserved_at_20[0x10];
e281682b
SM		 4882 u8 op_mod[0x10];
4883
b4ff3a36 4884 u8 reserved_at_40[0x40];
e281682b
SM		 4885};
4886
4887struct mlx5_ifc_gen_eqe_in_bits {
4888 u8 opcode[0x10];
b4ff3a36 4889 u8 reserved_at_10[0x10];
e281682b 4890
b4ff3a36 4891 u8 reserved_at_20[0x10];
e281682b
SM		 4892 u8 op_mod[0x10];
4893
b4ff3a36 4894 u8 reserved_at_40[0x18];
e281682b
SM		 4895 u8 eq_number[0x8];
4896
b4ff3a36 4897 u8 reserved_at_60[0x20];
e281682b
SM		 4898
4899 u8 eqe[64][0x8];
4900};
4901
4902struct mlx5_ifc_gen_eq_out_bits {
4903 u8 status[0x8];
b4ff3a36 4904 u8 reserved_at_8[0x18];
e281682b
SM		 4905
4906 u8 syndrome[0x20];
4907
b4ff3a36 4908 u8 reserved_at_40[0x40];
e281682b
SM		 4909};
4910
4911struct mlx5_ifc_enable_hca_out_bits {
4912 u8 status[0x8];
b4ff3a36 4913 u8 reserved_at_8[0x18];
e281682b
SM		 4914
4915 u8 syndrome[0x20];
4916
b4ff3a36 4917 u8 reserved_at_40[0x20];
e281682b
SM		 4918};
4919
4920struct mlx5_ifc_enable_hca_in_bits {
4921 u8 opcode[0x10];
b4ff3a36 4922 u8 reserved_at_10[0x10];
e281682b 4923
b4ff3a36 4924 u8 reserved_at_20[0x10];
e281682b
SM		 4925 u8 op_mod[0x10];
4926
b4ff3a36 4927 u8 reserved_at_40[0x10];
e281682b
SM		 4928 u8 function_id[0x10];
4929
b4ff3a36 4930 u8 reserved_at_60[0x20];
e281682b
SM		 4931};
4932
4933struct mlx5_ifc_drain_dct_out_bits {
4934 u8 status[0x8];
b4ff3a36 4935 u8 reserved_at_8[0x18];
e281682b
SM		 4936
4937 u8 syndrome[0x20];
4938
b4ff3a36 4939 u8 reserved_at_40[0x40];
e281682b
SM		 4940};
4941
4942struct mlx5_ifc_drain_dct_in_bits {
4943 u8 opcode[0x10];
b4ff3a36 4944 u8 reserved_at_10[0x10];
e281682b 4945
b4ff3a36 4946 u8 reserved_at_20[0x10];
e281682b
SM		 4947 u8 op_mod[0x10];
4948
b4ff3a36 4949 u8 reserved_at_40[0x8];
e281682b
SM		 4950 u8 dctn[0x18];
4951
b4ff3a36 4952 u8 reserved_at_60[0x20];
e281682b
SM		 4953};
4954
4955struct mlx5_ifc_disable_hca_out_bits {
4956 u8 status[0x8];
b4ff3a36 4957 u8 reserved_at_8[0x18];
e281682b
SM		 4958
4959 u8 syndrome[0x20];
4960
b4ff3a36 4961 u8 reserved_at_40[0x20];
e281682b
SM		 4962};
4963
4964struct mlx5_ifc_disable_hca_in_bits {
4965 u8 opcode[0x10];
b4ff3a36 4966 u8 reserved_at_10[0x10];
e281682b 4967
b4ff3a36 4968 u8 reserved_at_20[0x10];
e281682b
SM		 4969 u8 op_mod[0x10];
4970
b4ff3a36 4971 u8 reserved_at_40[0x10];
e281682b
SM		 4972 u8 function_id[0x10];
4973
b4ff3a36 4974 u8 reserved_at_60[0x20];
e281682b
SM		 4975};
4976
4977struct mlx5_ifc_detach_from_mcg_out_bits {
4978 u8 status[0x8];
b4ff3a36 4979 u8 reserved_at_8[0x18];
e281682b
SM		 4980
4981 u8 syndrome[0x20];
4982
b4ff3a36 4983 u8 reserved_at_40[0x40];
e281682b
SM		 4984};
4985
4986struct mlx5_ifc_detach_from_mcg_in_bits {
4987 u8 opcode[0x10];
b4ff3a36 4988 u8 reserved_at_10[0x10];
e281682b 4989
b4ff3a36 4990 u8 reserved_at_20[0x10];
e281682b
SM		 4991 u8 op_mod[0x10];
4992
b4ff3a36 4993 u8 reserved_at_40[0x8];
e281682b
SM		 4994 u8 qpn[0x18];
4995
b4ff3a36 4996 u8 reserved_at_60[0x20];
e281682b
SM		 4997
4998 u8 multicast_gid[16][0x8];
4999};
5000
5001struct mlx5_ifc_destroy_xrc_srq_out_bits {
5002 u8 status[0x8];
b4ff3a36 5003 u8 reserved_at_8[0x18];
e281682b
SM		 5004
5005 u8 syndrome[0x20];
5006
b4ff3a36 5007 u8 reserved_at_40[0x40];
e281682b
SM		 5008};
5009
5010struct mlx5_ifc_destroy_xrc_srq_in_bits {
5011 u8 opcode[0x10];
b4ff3a36 5012 u8 reserved_at_10[0x10];
e281682b 5013
b4ff3a36 5014 u8 reserved_at_20[0x10];
e281682b
SM		 5015 u8 op_mod[0x10];
5016
b4ff3a36 5017 u8 reserved_at_40[0x8];
e281682b
SM		 5018 u8 xrc_srqn[0x18];
5019
b4ff3a36 5020 u8 reserved_at_60[0x20];
e281682b
SM		 5021};
5022
5023struct mlx5_ifc_destroy_tis_out_bits {
5024 u8 status[0x8];
b4ff3a36 5025 u8 reserved_at_8[0x18];
e281682b
SM		 5026
5027 u8 syndrome[0x20];
5028
b4ff3a36 5029 u8 reserved_at_40[0x40];
e281682b
SM		 5030};
5031
5032struct mlx5_ifc_destroy_tis_in_bits {
5033 u8 opcode[0x10];
b4ff3a36 5034 u8 reserved_at_10[0x10];
e281682b 5035
b4ff3a36 5036 u8 reserved_at_20[0x10];
e281682b
SM		 5037 u8 op_mod[0x10];
5038
b4ff3a36 5039 u8 reserved_at_40[0x8];
e281682b
SM		 5040 u8 tisn[0x18];
5041
b4ff3a36 5042 u8 reserved_at_60[0x20];
e281682b
SM		 5043};
5044
5045struct mlx5_ifc_destroy_tir_out_bits {
5046 u8 status[0x8];
b4ff3a36 5047 u8 reserved_at_8[0x18];
e281682b
SM		 5048
5049 u8 syndrome[0x20];
5050
b4ff3a36 5051 u8 reserved_at_40[0x40];
e281682b
SM		 5052};
5053
5054struct mlx5_ifc_destroy_tir_in_bits {
5055 u8 opcode[0x10];
b4ff3a36 5056 u8 reserved_at_10[0x10];
e281682b 5057
b4ff3a36 5058 u8 reserved_at_20[0x10];
e281682b
SM		 5059 u8 op_mod[0x10];
5060
b4ff3a36 5061 u8 reserved_at_40[0x8];
e281682b
SM		 5062 u8 tirn[0x18];
5063
b4ff3a36 5064 u8 reserved_at_60[0x20];
e281682b
SM		 5065};
5066
5067struct mlx5_ifc_destroy_srq_out_bits {
5068 u8 status[0x8];
b4ff3a36 5069 u8 reserved_at_8[0x18];
e281682b
SM		 5070
5071 u8 syndrome[0x20];
5072
b4ff3a36 5073 u8 reserved_at_40[0x40];
e281682b
SM		 5074};
5075
5076struct mlx5_ifc_destroy_srq_in_bits {
5077 u8 opcode[0x10];
b4ff3a36 5078 u8 reserved_at_10[0x10];
e281682b 5079
b4ff3a36 5080 u8 reserved_at_20[0x10];
e281682b
SM		 5081 u8 op_mod[0x10];
5082
b4ff3a36 5083 u8 reserved_at_40[0x8];
e281682b
SM		 5084 u8 srqn[0x18];
5085
b4ff3a36 5086 u8 reserved_at_60[0x20];
e281682b
SM		 5087};
5088
5089struct mlx5_ifc_destroy_sq_out_bits {
5090 u8 status[0x8];
b4ff3a36 5091 u8 reserved_at_8[0x18];
e281682b
SM		 5092
5093 u8 syndrome[0x20];
5094
b4ff3a36 5095 u8 reserved_at_40[0x40];
e281682b
SM		 5096};
5097
5098struct mlx5_ifc_destroy_sq_in_bits {
5099 u8 opcode[0x10];
b4ff3a36 5100 u8 reserved_at_10[0x10];
e281682b 5101
b4ff3a36 5102 u8 reserved_at_20[0x10];
e281682b
SM		 5103 u8 op_mod[0x10];
5104
b4ff3a36 5105 u8 reserved_at_40[0x8];
e281682b
SM		 5106 u8 sqn[0x18];
5107
b4ff3a36 5108 u8 reserved_at_60[0x20];
e281682b
SM		 5109};
5110
5111struct mlx5_ifc_destroy_rqt_out_bits {
5112 u8 status[0x8];
b4ff3a36 5113 u8 reserved_at_8[0x18];
e281682b
SM		 5114
5115 u8 syndrome[0x20];
5116
b4ff3a36 5117 u8 reserved_at_40[0x40];
e281682b
SM		 5118};
5119
5120struct mlx5_ifc_destroy_rqt_in_bits {
5121 u8 opcode[0x10];
b4ff3a36 5122 u8 reserved_at_10[0x10];
e281682b 5123
b4ff3a36 5124 u8 reserved_at_20[0x10];
e281682b
SM		 5125 u8 op_mod[0x10];
5126
b4ff3a36 5127 u8 reserved_at_40[0x8];
e281682b
SM		 5128 u8 rqtn[0x18];
5129
b4ff3a36 5130 u8 reserved_at_60[0x20];
e281682b
SM		 5131};
5132
5133struct mlx5_ifc_destroy_rq_out_bits {
5134 u8 status[0x8];
b4ff3a36 5135 u8 reserved_at_8[0x18];
e281682b
SM		 5136
5137 u8 syndrome[0x20];
5138
b4ff3a36 5139 u8 reserved_at_40[0x40];
e281682b
SM		 5140};
5141
5142struct mlx5_ifc_destroy_rq_in_bits {
5143 u8 opcode[0x10];
b4ff3a36 5144 u8 reserved_at_10[0x10];
e281682b 5145
b4ff3a36 5146 u8 reserved_at_20[0x10];
e281682b
SM		 5147 u8 op_mod[0x10];
5148
b4ff3a36 5149 u8 reserved_at_40[0x8];
e281682b
SM		 5150 u8 rqn[0x18];
5151
b4ff3a36 5152 u8 reserved_at_60[0x20];
e281682b
SM		 5153};
5154
5155struct mlx5_ifc_destroy_rmp_out_bits {
5156 u8 status[0x8];
b4ff3a36 5157 u8 reserved_at_8[0x18];
e281682b
SM		 5158
5159 u8 syndrome[0x20];
5160
b4ff3a36 5161 u8 reserved_at_40[0x40];
e281682b
SM		 5162};
5163
5164struct mlx5_ifc_destroy_rmp_in_bits {
5165 u8 opcode[0x10];
b4ff3a36 5166 u8 reserved_at_10[0x10];
e281682b 5167
b4ff3a36 5168 u8 reserved_at_20[0x10];
e281682b
SM		 5169 u8 op_mod[0x10];
5170
b4ff3a36 5171 u8 reserved_at_40[0x8];
e281682b
SM		 5172 u8 rmpn[0x18];
5173
b4ff3a36 5174 u8 reserved_at_60[0x20];
e281682b
SM		 5175};
5176
5177struct mlx5_ifc_destroy_qp_out_bits {
5178 u8 status[0x8];
b4ff3a36 5179 u8 reserved_at_8[0x18];
e281682b
SM		 5180
5181 u8 syndrome[0x20];
5182
b4ff3a36 5183 u8 reserved_at_40[0x40];
e281682b
SM		 5184};
5185
5186struct mlx5_ifc_destroy_qp_in_bits {
5187 u8 opcode[0x10];
b4ff3a36 5188 u8 reserved_at_10[0x10];
e281682b 5189
b4ff3a36 5190 u8 reserved_at_20[0x10];
e281682b
SM		 5191 u8 op_mod[0x10];
5192
b4ff3a36 5193 u8 reserved_at_40[0x8];
e281682b
SM		 5194 u8 qpn[0x18];
5195
b4ff3a36 5196 u8 reserved_at_60[0x20];
e281682b
SM		 5197};
5198
5199struct mlx5_ifc_destroy_psv_out_bits {
5200 u8 status[0x8];
b4ff3a36 5201 u8 reserved_at_8[0x18];
e281682b
SM		 5202
5203 u8 syndrome[0x20];
5204
b4ff3a36 5205 u8 reserved_at_40[0x40];
e281682b
SM		 5206};
5207
5208struct mlx5_ifc_destroy_psv_in_bits {
5209 u8 opcode[0x10];
b4ff3a36 5210 u8 reserved_at_10[0x10];
e281682b 5211
b4ff3a36 5212 u8 reserved_at_20[0x10];
e281682b
SM		 5213 u8 op_mod[0x10];
5214
b4ff3a36 5215 u8 reserved_at_40[0x8];
e281682b
SM		 5216 u8 psvn[0x18];
5217
b4ff3a36 5218 u8 reserved_at_60[0x20];
e281682b
SM		 5219};
5220
5221struct mlx5_ifc_destroy_mkey_out_bits {
5222 u8 status[0x8];
b4ff3a36 5223 u8 reserved_at_8[0x18];
e281682b
SM		 5224
5225 u8 syndrome[0x20];
5226
b4ff3a36 5227 u8 reserved_at_40[0x40];
e281682b
SM		 5228};
5229
5230struct mlx5_ifc_destroy_mkey_in_bits {
5231 u8 opcode[0x10];
b4ff3a36 5232 u8 reserved_at_10[0x10];
e281682b 5233
b4ff3a36 5234 u8 reserved_at_20[0x10];
e281682b
SM		 5235 u8 op_mod[0x10];
5236
b4ff3a36 5237 u8 reserved_at_40[0x8];
e281682b
SM		 5238 u8 mkey_index[0x18];
5239
b4ff3a36 5240 u8 reserved_at_60[0x20];
e281682b
SM		 5241};
5242
5243struct mlx5_ifc_destroy_flow_table_out_bits {
5244 u8 status[0x8];
b4ff3a36 5245 u8 reserved_at_8[0x18];
e281682b
SM		 5246
5247 u8 syndrome[0x20];
5248
b4ff3a36 5249 u8 reserved_at_40[0x40];
e281682b
SM		 5250};
5251
5252struct mlx5_ifc_destroy_flow_table_in_bits {
5253 u8 opcode[0x10];
b4ff3a36 5254 u8 reserved_at_10[0x10];
e281682b 5255
b4ff3a36 5256 u8 reserved_at_20[0x10];
e281682b
SM		 5257 u8 op_mod[0x10];
5258
7d5e1423
SM		 5259 u8 other_vport[0x1];
5260 u8 reserved_at_41[0xf];
5261 u8 vport_number[0x10];
5262
5263 u8 reserved_at_60[0x20];
e281682b
SM		 5264
5265 u8 table_type[0x8];
b4ff3a36 5266 u8 reserved_at_88[0x18];
e281682b 5267
b4ff3a36 5268 u8 reserved_at_a0[0x8];
e281682b
SM		 5269 u8 table_id[0x18];
5270
b4ff3a36 5271 u8 reserved_at_c0[0x140];
e281682b
SM		 5272};
5273
5274struct mlx5_ifc_destroy_flow_group_out_bits {
5275 u8 status[0x8];
b4ff3a36 5276 u8 reserved_at_8[0x18];
e281682b
SM		 5277
5278 u8 syndrome[0x20];
5279
b4ff3a36 5280 u8 reserved_at_40[0x40];
e281682b
SM		 5281};
5282
5283struct mlx5_ifc_destroy_flow_group_in_bits {
5284 u8 opcode[0x10];
b4ff3a36 5285 u8 reserved_at_10[0x10];
e281682b 5286
b4ff3a36 5287 u8 reserved_at_20[0x10];
e281682b
SM		 5288 u8 op_mod[0x10];
5289
7d5e1423
SM		 5290 u8 other_vport[0x1];
5291 u8 reserved_at_41[0xf];
5292 u8 vport_number[0x10];
5293
5294 u8 reserved_at_60[0x20];
e281682b
SM		 5295
5296 u8 table_type[0x8];
b4ff3a36 5297 u8 reserved_at_88[0x18];
e281682b 5298
b4ff3a36 5299 u8 reserved_at_a0[0x8];
e281682b
SM		 5300 u8 table_id[0x18];
5301
5302 u8 group_id[0x20];
5303
b4ff3a36 5304 u8 reserved_at_e0[0x120];
e281682b
SM		 5305};
5306
5307struct mlx5_ifc_destroy_eq_out_bits {
5308 u8 status[0x8];
b4ff3a36 5309 u8 reserved_at_8[0x18];
e281682b
SM		 5310
5311 u8 syndrome[0x20];
5312
b4ff3a36 5313 u8 reserved_at_40[0x40];
e281682b
SM		 5314};
5315
5316struct mlx5_ifc_destroy_eq_in_bits {
5317 u8 opcode[0x10];
b4ff3a36 5318 u8 reserved_at_10[0x10];
e281682b 5319
b4ff3a36 5320 u8 reserved_at_20[0x10];
e281682b
SM		 5321 u8 op_mod[0x10];
5322
b4ff3a36 5323 u8 reserved_at_40[0x18];
e281682b
SM		 5324 u8 eq_number[0x8];
5325
b4ff3a36 5326 u8 reserved_at_60[0x20];
e281682b
SM		 5327};
5328
5329struct mlx5_ifc_destroy_dct_out_bits {
5330 u8 status[0x8];
b4ff3a36 5331 u8 reserved_at_8[0x18];
e281682b
SM		 5332
5333 u8 syndrome[0x20];
5334
b4ff3a36 5335 u8 reserved_at_40[0x40];
e281682b
SM		 5336};
5337
5338struct mlx5_ifc_destroy_dct_in_bits {
5339 u8 opcode[0x10];
b4ff3a36 5340 u8 reserved_at_10[0x10];
e281682b 5341
b4ff3a36 5342 u8 reserved_at_20[0x10];
e281682b
SM		 5343 u8 op_mod[0x10];
5344
b4ff3a36 5345 u8 reserved_at_40[0x8];
e281682b
SM		 5346 u8 dctn[0x18];
5347
b4ff3a36 5348 u8 reserved_at_60[0x20];
e281682b
SM		 5349};
5350
5351struct mlx5_ifc_destroy_cq_out_bits {
5352 u8 status[0x8];
b4ff3a36 5353 u8 reserved_at_8[0x18];
e281682b
SM		 5354
5355 u8 syndrome[0x20];
5356
b4ff3a36 5357 u8 reserved_at_40[0x40];
e281682b
SM		 5358};
5359
5360struct mlx5_ifc_destroy_cq_in_bits {
5361 u8 opcode[0x10];
b4ff3a36 5362 u8 reserved_at_10[0x10];
e281682b 5363
b4ff3a36 5364 u8 reserved_at_20[0x10];
e281682b
SM		 5365 u8 op_mod[0x10];
5366
b4ff3a36 5367 u8 reserved_at_40[0x8];
e281682b
SM		 5368 u8 cqn[0x18];
5369
b4ff3a36 5370 u8 reserved_at_60[0x20];
e281682b
SM		 5371};
5372
5373struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5374 u8 status[0x8];
b4ff3a36 5375 u8 reserved_at_8[0x18];
e281682b
SM		 5376
5377 u8 syndrome[0x20];
5378
b4ff3a36 5379 u8 reserved_at_40[0x40];
e281682b
SM		 5380};
5381
5382struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5383 u8 opcode[0x10];
b4ff3a36 5384 u8 reserved_at_10[0x10];
e281682b 5385
b4ff3a36 5386 u8 reserved_at_20[0x10];
e281682b
SM		 5387 u8 op_mod[0x10];
5388
b4ff3a36 5389 u8 reserved_at_40[0x20];
e281682b 5390
b4ff3a36 5391 u8 reserved_at_60[0x10];
e281682b
SM		 5392 u8 vxlan_udp_port[0x10];
5393};
5394
5395struct mlx5_ifc_delete_l2_table_entry_out_bits {
5396 u8 status[0x8];
b4ff3a36 5397 u8 reserved_at_8[0x18];
e281682b
SM		 5398
5399 u8 syndrome[0x20];
5400
b4ff3a36 5401 u8 reserved_at_40[0x40];
e281682b
SM		 5402};
5403
5404struct mlx5_ifc_delete_l2_table_entry_in_bits {
5405 u8 opcode[0x10];
b4ff3a36 5406 u8 reserved_at_10[0x10];
e281682b 5407
b4ff3a36 5408 u8 reserved_at_20[0x10];
e281682b
SM		 5409 u8 op_mod[0x10];
5410
b4ff3a36 5411 u8 reserved_at_40[0x60];
e281682b 5412
b4ff3a36 5413 u8 reserved_at_a0[0x8];
e281682b
SM		 5414 u8 table_index[0x18];
5415
b4ff3a36 5416 u8 reserved_at_c0[0x140];
e281682b
SM		 5417};
5418
5419struct mlx5_ifc_delete_fte_out_bits {
5420 u8 status[0x8];
b4ff3a36 5421 u8 reserved_at_8[0x18];
e281682b
SM		 5422
5423 u8 syndrome[0x20];
5424
b4ff3a36 5425 u8 reserved_at_40[0x40];
e281682b
SM		 5426};
5427
5428struct mlx5_ifc_delete_fte_in_bits {
5429 u8 opcode[0x10];
b4ff3a36 5430 u8 reserved_at_10[0x10];
e281682b 5431
b4ff3a36 5432 u8 reserved_at_20[0x10];
e281682b
SM		 5433 u8 op_mod[0x10];
5434
7d5e1423
SM		 5435 u8 other_vport[0x1];
5436 u8 reserved_at_41[0xf];
5437 u8 vport_number[0x10];
5438
5439 u8 reserved_at_60[0x20];
e281682b
SM		 5440
5441 u8 table_type[0x8];
b4ff3a36 5442 u8 reserved_at_88[0x18];
e281682b 5443
b4ff3a36 5444 u8 reserved_at_a0[0x8];
e281682b
SM		 5445 u8 table_id[0x18];
5446
b4ff3a36 5447 u8 reserved_at_c0[0x40];
e281682b
SM		 5448
5449 u8 flow_index[0x20];
5450
b4ff3a36 5451 u8 reserved_at_120[0xe0];
e281682b
SM		 5452};
5453
5454struct mlx5_ifc_dealloc_xrcd_out_bits {
5455 u8 status[0x8];
b4ff3a36 5456 u8 reserved_at_8[0x18];
e281682b
SM		 5457
5458 u8 syndrome[0x20];
5459
b4ff3a36 5460 u8 reserved_at_40[0x40];
e281682b
SM		 5461};
5462
5463struct mlx5_ifc_dealloc_xrcd_in_bits {
5464 u8 opcode[0x10];
b4ff3a36 5465 u8 reserved_at_10[0x10];
e281682b 5466
b4ff3a36 5467 u8 reserved_at_20[0x10];
e281682b
SM		 5468 u8 op_mod[0x10];
5469
b4ff3a36 5470 u8 reserved_at_40[0x8];
e281682b
SM		 5471 u8 xrcd[0x18];
5472
b4ff3a36 5473 u8 reserved_at_60[0x20];
e281682b
SM		 5474};
5475
5476struct mlx5_ifc_dealloc_uar_out_bits {
5477 u8 status[0x8];
b4ff3a36 5478 u8 reserved_at_8[0x18];
e281682b
SM		 5479
5480 u8 syndrome[0x20];
5481
b4ff3a36 5482 u8 reserved_at_40[0x40];
e281682b
SM		 5483};
5484
5485struct mlx5_ifc_dealloc_uar_in_bits {
5486 u8 opcode[0x10];
b4ff3a36 5487 u8 reserved_at_10[0x10];
e281682b 5488
b4ff3a36 5489 u8 reserved_at_20[0x10];
e281682b
SM		 5490 u8 op_mod[0x10];
5491
b4ff3a36 5492 u8 reserved_at_40[0x8];
e281682b
SM		 5493 u8 uar[0x18];
5494
b4ff3a36 5495 u8 reserved_at_60[0x20];
e281682b
SM		 5496};
5497
5498struct mlx5_ifc_dealloc_transport_domain_out_bits {
5499 u8 status[0x8];
b4ff3a36 5500 u8 reserved_at_8[0x18];
e281682b
SM		 5501
5502 u8 syndrome[0x20];
5503
b4ff3a36 5504 u8 reserved_at_40[0x40];
e281682b
SM		 5505};
5506
5507struct mlx5_ifc_dealloc_transport_domain_in_bits {
5508 u8 opcode[0x10];
b4ff3a36 5509 u8 reserved_at_10[0x10];
e281682b 5510
b4ff3a36 5511 u8 reserved_at_20[0x10];
e281682b
SM		 5512 u8 op_mod[0x10];
5513
b4ff3a36 5514 u8 reserved_at_40[0x8];
e281682b
SM		 5515 u8 transport_domain[0x18];
5516
b4ff3a36 5517 u8 reserved_at_60[0x20];
e281682b
SM		 5518};
5519
5520struct mlx5_ifc_dealloc_q_counter_out_bits {
5521 u8 status[0x8];
b4ff3a36 5522 u8 reserved_at_8[0x18];
e281682b
SM		 5523
5524 u8 syndrome[0x20];
5525
b4ff3a36 5526 u8 reserved_at_40[0x40];
e281682b
SM		 5527};
5528
5529struct mlx5_ifc_dealloc_q_counter_in_bits {
5530 u8 opcode[0x10];
b4ff3a36 5531 u8 reserved_at_10[0x10];
e281682b 5532
b4ff3a36 5533 u8 reserved_at_20[0x10];
e281682b
SM		 5534 u8 op_mod[0x10];
5535
b4ff3a36 5536 u8 reserved_at_40[0x18];
e281682b
SM		 5537 u8 counter_set_id[0x8];
5538
b4ff3a36 5539 u8 reserved_at_60[0x20];
e281682b
SM		 5540};
5541
5542struct mlx5_ifc_dealloc_pd_out_bits {
5543 u8 status[0x8];
b4ff3a36 5544 u8 reserved_at_8[0x18];
e281682b
SM		 5545
5546 u8 syndrome[0x20];
5547
b4ff3a36 5548 u8 reserved_at_40[0x40];
e281682b
SM		 5549};
5550
5551struct mlx5_ifc_dealloc_pd_in_bits {
5552 u8 opcode[0x10];
b4ff3a36 5553 u8 reserved_at_10[0x10];
e281682b 5554
b4ff3a36 5555 u8 reserved_at_20[0x10];
e281682b
SM		 5556 u8 op_mod[0x10];
5557
b4ff3a36 5558 u8 reserved_at_40[0x8];
e281682b
SM		 5559 u8 pd[0x18];
5560
b4ff3a36 5561 u8 reserved_at_60[0x20];
e281682b
SM		 5562};
5563
9dc0b289
AV		 5564struct mlx5_ifc_dealloc_flow_counter_out_bits {
5565 u8 status[0x8];
5566 u8 reserved_at_8[0x18];
5567
5568 u8 syndrome[0x20];
5569
5570 u8 reserved_at_40[0x40];
5571};
5572
5573struct mlx5_ifc_dealloc_flow_counter_in_bits {
5574 u8 opcode[0x10];
5575 u8 reserved_at_10[0x10];
5576
5577 u8 reserved_at_20[0x10];
5578 u8 op_mod[0x10];
5579
5580 u8 reserved_at_40[0x10];
5581 u8 flow_counter_id[0x10];
5582
5583 u8 reserved_at_60[0x20];
5584};
5585
e281682b
SM		 5586struct mlx5_ifc_create_xrc_srq_out_bits {
5587 u8 status[0x8];
b4ff3a36 5588 u8 reserved_at_8[0x18];
e281682b
SM		 5589
5590 u8 syndrome[0x20];
5591
b4ff3a36 5592 u8 reserved_at_40[0x8];
e281682b
SM		 5593 u8 xrc_srqn[0x18];
5594
b4ff3a36 5595 u8 reserved_at_60[0x20];
e281682b
SM		 5596};
5597
5598struct mlx5_ifc_create_xrc_srq_in_bits {
5599 u8 opcode[0x10];
b4ff3a36 5600 u8 reserved_at_10[0x10];
e281682b 5601
b4ff3a36 5602 u8 reserved_at_20[0x10];
e281682b
SM		 5603 u8 op_mod[0x10];
5604
b4ff3a36 5605 u8 reserved_at_40[0x40];
e281682b
SM		 5606
5607 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5608
b4ff3a36 5609 u8 reserved_at_280[0x600];
e281682b
SM		 5610
5611 u8 pas[0][0x40];
5612};
5613
5614struct mlx5_ifc_create_tis_out_bits {
5615 u8 status[0x8];
b4ff3a36 5616 u8 reserved_at_8[0x18];
e281682b
SM		 5617
5618 u8 syndrome[0x20];
5619
b4ff3a36 5620 u8 reserved_at_40[0x8];
e281682b
SM		 5621 u8 tisn[0x18];
5622
b4ff3a36 5623 u8 reserved_at_60[0x20];
e281682b
SM		 5624};
5625
5626struct mlx5_ifc_create_tis_in_bits {
5627 u8 opcode[0x10];
b4ff3a36 5628 u8 reserved_at_10[0x10];
e281682b 5629
b4ff3a36 5630 u8 reserved_at_20[0x10];
e281682b
SM		 5631 u8 op_mod[0x10];
5632
b4ff3a36 5633 u8 reserved_at_40[0xc0];
e281682b
SM		 5634
5635 struct mlx5_ifc_tisc_bits ctx;
5636};
5637
5638struct mlx5_ifc_create_tir_out_bits {
5639 u8 status[0x8];
b4ff3a36 5640 u8 reserved_at_8[0x18];
e281682b
SM		 5641
5642 u8 syndrome[0x20];
5643
b4ff3a36 5644 u8 reserved_at_40[0x8];
e281682b
SM		 5645 u8 tirn[0x18];
5646
b4ff3a36 5647 u8 reserved_at_60[0x20];
e281682b
SM		 5648};
5649
5650struct mlx5_ifc_create_tir_in_bits {
5651 u8 opcode[0x10];
b4ff3a36 5652 u8 reserved_at_10[0x10];
e281682b 5653
b4ff3a36 5654 u8 reserved_at_20[0x10];
e281682b
SM		 5655 u8 op_mod[0x10];
5656
b4ff3a36 5657 u8 reserved_at_40[0xc0];
e281682b
SM		 5658
5659 struct mlx5_ifc_tirc_bits ctx;
5660};
5661
5662struct mlx5_ifc_create_srq_out_bits {
5663 u8 status[0x8];
b4ff3a36 5664 u8 reserved_at_8[0x18];
e281682b
SM		 5665
5666 u8 syndrome[0x20];
5667
b4ff3a36 5668 u8 reserved_at_40[0x8];
e281682b
SM		 5669 u8 srqn[0x18];
5670
b4ff3a36 5671 u8 reserved_at_60[0x20];
e281682b
SM		 5672};
5673
5674struct mlx5_ifc_create_srq_in_bits {
5675 u8 opcode[0x10];
b4ff3a36 5676 u8 reserved_at_10[0x10];
e281682b 5677
b4ff3a36 5678 u8 reserved_at_20[0x10];
e281682b
SM		 5679 u8 op_mod[0x10];
5680
b4ff3a36 5681 u8 reserved_at_40[0x40];
e281682b
SM		 5682
5683 struct mlx5_ifc_srqc_bits srq_context_entry;
5684
b4ff3a36 5685 u8 reserved_at_280[0x600];
e281682b
SM		 5686
5687 u8 pas[0][0x40];
5688};
5689
5690struct mlx5_ifc_create_sq_out_bits {
5691 u8 status[0x8];
b4ff3a36 5692 u8 reserved_at_8[0x18];
e281682b
SM		 5693
5694 u8 syndrome[0x20];
5695
b4ff3a36 5696 u8 reserved_at_40[0x8];
e281682b
SM		 5697 u8 sqn[0x18];
5698
b4ff3a36 5699 u8 reserved_at_60[0x20];
e281682b
SM		 5700};
5701
5702struct mlx5_ifc_create_sq_in_bits {
5703 u8 opcode[0x10];
b4ff3a36 5704 u8 reserved_at_10[0x10];
e281682b 5705
b4ff3a36 5706 u8 reserved_at_20[0x10];
e281682b
SM		 5707 u8 op_mod[0x10];
5708
b4ff3a36 5709 u8 reserved_at_40[0xc0];
e281682b
SM		 5710
5711 struct mlx5_ifc_sqc_bits ctx;
5712};
5713
5714struct mlx5_ifc_create_rqt_out_bits {
5715 u8 status[0x8];
b4ff3a36 5716 u8 reserved_at_8[0x18];
e281682b
SM		 5717
5718 u8 syndrome[0x20];
5719
b4ff3a36 5720 u8 reserved_at_40[0x8];
e281682b
SM		 5721 u8 rqtn[0x18];
5722
b4ff3a36 5723 u8 reserved_at_60[0x20];
e281682b
SM		 5724};
5725
5726struct mlx5_ifc_create_rqt_in_bits {
5727 u8 opcode[0x10];
b4ff3a36 5728 u8 reserved_at_10[0x10];
e281682b 5729
b4ff3a36 5730 u8 reserved_at_20[0x10];
e281682b
SM		 5731 u8 op_mod[0x10];
5732
b4ff3a36 5733 u8 reserved_at_40[0xc0];
e281682b
SM		 5734
5735 struct mlx5_ifc_rqtc_bits rqt_context;
5736};
5737
5738struct mlx5_ifc_create_rq_out_bits {
5739 u8 status[0x8];
b4ff3a36 5740 u8 reserved_at_8[0x18];
e281682b
SM		 5741
5742 u8 syndrome[0x20];
5743
b4ff3a36 5744 u8 reserved_at_40[0x8];
e281682b
SM		 5745 u8 rqn[0x18];
5746
b4ff3a36 5747 u8 reserved_at_60[0x20];
e281682b
SM		 5748};
5749
5750struct mlx5_ifc_create_rq_in_bits {
5751 u8 opcode[0x10];
b4ff3a36 5752 u8 reserved_at_10[0x10];
e281682b 5753
b4ff3a36 5754 u8 reserved_at_20[0x10];
e281682b
SM		 5755 u8 op_mod[0x10];
5756
b4ff3a36 5757 u8 reserved_at_40[0xc0];
e281682b
SM		 5758
5759 struct mlx5_ifc_rqc_bits ctx;
5760};
5761
5762struct mlx5_ifc_create_rmp_out_bits {
5763 u8 status[0x8];
b4ff3a36 5764 u8 reserved_at_8[0x18];
e281682b
SM		 5765
5766 u8 syndrome[0x20];
5767
b4ff3a36 5768 u8 reserved_at_40[0x8];
e281682b
SM		 5769 u8 rmpn[0x18];
5770
b4ff3a36 5771 u8 reserved_at_60[0x20];
e281682b
SM		 5772};
5773
5774struct mlx5_ifc_create_rmp_in_bits {
5775 u8 opcode[0x10];
b4ff3a36 5776 u8 reserved_at_10[0x10];
e281682b 5777
b4ff3a36 5778 u8 reserved_at_20[0x10];
e281682b
SM		 5779 u8 op_mod[0x10];
5780
b4ff3a36 5781 u8 reserved_at_40[0xc0];
e281682b
SM		 5782
5783 struct mlx5_ifc_rmpc_bits ctx;
5784};
5785
5786struct mlx5_ifc_create_qp_out_bits {
5787 u8 status[0x8];
b4ff3a36 5788 u8 reserved_at_8[0x18];
e281682b
SM		 5789
5790 u8 syndrome[0x20];
5791
b4ff3a36 5792 u8 reserved_at_40[0x8];
e281682b
SM		 5793 u8 qpn[0x18];
5794
b4ff3a36 5795 u8 reserved_at_60[0x20];
e281682b
SM		 5796};
5797
5798struct mlx5_ifc_create_qp_in_bits {
5799 u8 opcode[0x10];
b4ff3a36 5800 u8 reserved_at_10[0x10];
e281682b 5801
b4ff3a36 5802 u8 reserved_at_20[0x10];
e281682b
SM		 5803 u8 op_mod[0x10];
5804
b4ff3a36 5805 u8 reserved_at_40[0x40];
e281682b
SM		 5806
5807 u8 opt_param_mask[0x20];
5808
b4ff3a36 5809 u8 reserved_at_a0[0x20];
e281682b
SM		 5810
5811 struct mlx5_ifc_qpc_bits qpc;
5812
b4ff3a36 5813 u8 reserved_at_800[0x80];
e281682b
SM		 5814
5815 u8 pas[0][0x40];
5816};
5817
5818struct mlx5_ifc_create_psv_out_bits {
5819 u8 status[0x8];
b4ff3a36 5820 u8 reserved_at_8[0x18];
e281682b
SM		 5821
5822 u8 syndrome[0x20];
5823
b4ff3a36 5824 u8 reserved_at_40[0x40];
e281682b 5825
b4ff3a36 5826 u8 reserved_at_80[0x8];
e281682b
SM		 5827 u8 psv0_index[0x18];
5828
b4ff3a36 5829 u8 reserved_at_a0[0x8];
e281682b
SM		 5830 u8 psv1_index[0x18];
5831
b4ff3a36 5832 u8 reserved_at_c0[0x8];
e281682b
SM		 5833 u8 psv2_index[0x18];
5834
b4ff3a36 5835 u8 reserved_at_e0[0x8];
e281682b
SM		 5836 u8 psv3_index[0x18];
5837};
5838
5839struct mlx5_ifc_create_psv_in_bits {
5840 u8 opcode[0x10];
b4ff3a36 5841 u8 reserved_at_10[0x10];
e281682b 5842
b4ff3a36 5843 u8 reserved_at_20[0x10];
e281682b
SM		 5844 u8 op_mod[0x10];
5845
5846 u8 num_psv[0x4];
b4ff3a36 5847 u8 reserved_at_44[0x4];
e281682b
SM		 5848 u8 pd[0x18];
5849
b4ff3a36 5850 u8 reserved_at_60[0x20];
e281682b
SM		 5851};
5852
5853struct mlx5_ifc_create_mkey_out_bits {
5854 u8 status[0x8];
b4ff3a36 5855 u8 reserved_at_8[0x18];
e281682b
SM		 5856
5857 u8 syndrome[0x20];
5858
b4ff3a36 5859 u8 reserved_at_40[0x8];
e281682b
SM		 5860 u8 mkey_index[0x18];
5861
b4ff3a36 5862 u8 reserved_at_60[0x20];
e281682b
SM		 5863};
5864
5865struct mlx5_ifc_create_mkey_in_bits {
5866 u8 opcode[0x10];
b4ff3a36 5867 u8 reserved_at_10[0x10];
e281682b 5868
b4ff3a36 5869 u8 reserved_at_20[0x10];
e281682b
SM		 5870 u8 op_mod[0x10];
5871
b4ff3a36 5872 u8 reserved_at_40[0x20];
e281682b
SM		 5873
5874 u8 pg_access[0x1];
b4ff3a36 5875 u8 reserved_at_61[0x1f];
e281682b
SM		 5876
5877 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5878
b4ff3a36 5879 u8 reserved_at_280[0x80];
e281682b
SM		 5880
5881 u8 translations_octword_actual_size[0x20];
5882
b4ff3a36 5883 u8 reserved_at_320[0x560];
e281682b
SM		 5884
5885 u8 klm_pas_mtt[0][0x20];
5886};
5887
5888struct mlx5_ifc_create_flow_table_out_bits {
5889 u8 status[0x8];
b4ff3a36 5890 u8 reserved_at_8[0x18];
e281682b
SM		 5891
5892 u8 syndrome[0x20];
5893
b4ff3a36 5894 u8 reserved_at_40[0x8];
e281682b
SM		 5895 u8 table_id[0x18];
5896
b4ff3a36 5897 u8 reserved_at_60[0x20];
e281682b
SM		 5898};
5899
5900struct mlx5_ifc_create_flow_table_in_bits {
5901 u8 opcode[0x10];
b4ff3a36 5902 u8 reserved_at_10[0x10];
e281682b 5903
b4ff3a36 5904 u8 reserved_at_20[0x10];
e281682b
SM		 5905 u8 op_mod[0x10];
5906
7d5e1423
SM		 5907 u8 other_vport[0x1];
5908 u8 reserved_at_41[0xf];
5909 u8 vport_number[0x10];
5910
5911 u8 reserved_at_60[0x20];
e281682b
SM		 5912
5913 u8 table_type[0x8];
b4ff3a36 5914 u8 reserved_at_88[0x18];
e281682b 5915
b4ff3a36 5916 u8 reserved_at_a0[0x20];
e281682b 5917
b4ff3a36 5918 u8 reserved_at_c0[0x4];
34a40e68 5919 u8 table_miss_mode[0x4];
e281682b 5920 u8 level[0x8];
b4ff3a36 5921 u8 reserved_at_d0[0x8];
e281682b
SM		 5922 u8 log_size[0x8];
5923
b4ff3a36 5924 u8 reserved_at_e0[0x8];
34a40e68
MG		 5925 u8 table_miss_id[0x18];
5926
b4ff3a36 5927 u8 reserved_at_100[0x100];
e281682b
SM		 5928};
5929
5930struct mlx5_ifc_create_flow_group_out_bits {
5931 u8 status[0x8];
b4ff3a36 5932 u8 reserved_at_8[0x18];
e281682b
SM		 5933
5934 u8 syndrome[0x20];
5935
b4ff3a36 5936 u8 reserved_at_40[0x8];
e281682b
SM		 5937 u8 group_id[0x18];
5938
b4ff3a36 5939 u8 reserved_at_60[0x20];
e281682b
SM		 5940};
5941
5942enum {
5943 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5944 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5945 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5946};
5947
5948struct mlx5_ifc_create_flow_group_in_bits {
5949 u8 opcode[0x10];
b4ff3a36 5950 u8 reserved_at_10[0x10];
e281682b 5951
b4ff3a36 5952 u8 reserved_at_20[0x10];
e281682b
SM		 5953 u8 op_mod[0x10];
5954
7d5e1423
SM		 5955 u8 other_vport[0x1];
5956 u8 reserved_at_41[0xf];
5957 u8 vport_number[0x10];
5958
5959 u8 reserved_at_60[0x20];
e281682b
SM		 5960
5961 u8 table_type[0x8];
b4ff3a36 5962 u8 reserved_at_88[0x18];
e281682b 5963
b4ff3a36 5964 u8 reserved_at_a0[0x8];
e281682b
SM		 5965 u8 table_id[0x18];
5966
b4ff3a36 5967 u8 reserved_at_c0[0x20];
e281682b
SM		 5968
5969 u8 start_flow_index[0x20];
5970
b4ff3a36 5971 u8 reserved_at_100[0x20];
e281682b
SM		 5972
5973 u8 end_flow_index[0x20];
5974
b4ff3a36 5975 u8 reserved_at_140[0xa0];
e281682b 5976
b4ff3a36 5977 u8 reserved_at_1e0[0x18];
e281682b
SM		 5978 u8 match_criteria_enable[0x8];
5979
5980 struct mlx5_ifc_fte_match_param_bits match_criteria;
5981
b4ff3a36 5982 u8 reserved_at_1200[0xe00];
e281682b
SM		 5983};
5984
5985struct mlx5_ifc_create_eq_out_bits {
5986 u8 status[0x8];
b4ff3a36 5987 u8 reserved_at_8[0x18];
e281682b
SM		 5988
5989 u8 syndrome[0x20];
5990
b4ff3a36 5991 u8 reserved_at_40[0x18];
e281682b
SM		 5992 u8 eq_number[0x8];
5993
b4ff3a36 5994 u8 reserved_at_60[0x20];
e281682b
SM		 5995};
5996
5997struct mlx5_ifc_create_eq_in_bits {
5998 u8 opcode[0x10];
b4ff3a36 5999 u8 reserved_at_10[0x10];
e281682b 6000
b4ff3a36 6001 u8 reserved_at_20[0x10];
e281682b
SM		 6002 u8 op_mod[0x10];
6003
b4ff3a36 6004 u8 reserved_at_40[0x40];
e281682b
SM		 6005
6006 struct mlx5_ifc_eqc_bits eq_context_entry;
6007
b4ff3a36 6008 u8 reserved_at_280[0x40];
e281682b
SM		 6009
6010 u8 event_bitmask[0x40];
6011
b4ff3a36 6012 u8 reserved_at_300[0x580];
e281682b
SM		 6013
6014 u8 pas[0][0x40];
6015};
6016
6017struct mlx5_ifc_create_dct_out_bits {
6018 u8 status[0x8];
b4ff3a36 6019 u8 reserved_at_8[0x18];
e281682b
SM		 6020
6021 u8 syndrome[0x20];
6022
b4ff3a36 6023 u8 reserved_at_40[0x8];
e281682b
SM		 6024 u8 dctn[0x18];
6025
b4ff3a36 6026 u8 reserved_at_60[0x20];
e281682b
SM		 6027};
6028
6029struct mlx5_ifc_create_dct_in_bits {
6030 u8 opcode[0x10];
b4ff3a36 6031 u8 reserved_at_10[0x10];
e281682b 6032
b4ff3a36 6033 u8 reserved_at_20[0x10];
e281682b
SM		 6034 u8 op_mod[0x10];
6035
b4ff3a36 6036 u8 reserved_at_40[0x40];
e281682b
SM		 6037
6038 struct mlx5_ifc_dctc_bits dct_context_entry;
6039
b4ff3a36 6040 u8 reserved_at_280[0x180];
e281682b
SM		 6041};
6042
6043struct mlx5_ifc_create_cq_out_bits {
6044 u8 status[0x8];
b4ff3a36 6045 u8 reserved_at_8[0x18];
e281682b
SM		 6046
6047 u8 syndrome[0x20];
6048
b4ff3a36 6049 u8 reserved_at_40[0x8];
e281682b
SM		 6050 u8 cqn[0x18];
6051
b4ff3a36 6052 u8 reserved_at_60[0x20];
e281682b
SM		 6053};
6054
6055struct mlx5_ifc_create_cq_in_bits {
6056 u8 opcode[0x10];
b4ff3a36 6057 u8 reserved_at_10[0x10];
e281682b 6058
b4ff3a36 6059 u8 reserved_at_20[0x10];
e281682b
SM		 6060 u8 op_mod[0x10];
6061
b4ff3a36 6062 u8 reserved_at_40[0x40];
e281682b
SM		 6063
6064 struct mlx5_ifc_cqc_bits cq_context;
6065
b4ff3a36 6066 u8 reserved_at_280[0x600];
e281682b
SM		 6067
6068 u8 pas[0][0x40];
6069};
6070
6071struct mlx5_ifc_config_int_moderation_out_bits {
6072 u8 status[0x8];
b4ff3a36 6073 u8 reserved_at_8[0x18];
e281682b
SM		 6074
6075 u8 syndrome[0x20];
6076
b4ff3a36 6077 u8 reserved_at_40[0x4];
e281682b
SM		 6078 u8 min_delay[0xc];
6079 u8 int_vector[0x10];
6080
b4ff3a36 6081 u8 reserved_at_60[0x20];
e281682b
SM		 6082};
6083
6084enum {
6085 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6086 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6087};
6088
6089struct mlx5_ifc_config_int_moderation_in_bits {
6090 u8 opcode[0x10];
b4ff3a36 6091 u8 reserved_at_10[0x10];
e281682b 6092
b4ff3a36 6093 u8 reserved_at_20[0x10];
e281682b
SM		 6094 u8 op_mod[0x10];
6095
b4ff3a36 6096 u8 reserved_at_40[0x4];
e281682b
SM		 6097 u8 min_delay[0xc];
6098 u8 int_vector[0x10];
6099
b4ff3a36 6100 u8 reserved_at_60[0x20];
e281682b
SM		 6101};
6102
6103struct mlx5_ifc_attach_to_mcg_out_bits {
6104 u8 status[0x8];
b4ff3a36 6105 u8 reserved_at_8[0x18];
e281682b
SM		 6106
6107 u8 syndrome[0x20];
6108
b4ff3a36 6109 u8 reserved_at_40[0x40];
e281682b
SM		 6110};
6111
6112struct mlx5_ifc_attach_to_mcg_in_bits {
6113 u8 opcode[0x10];
b4ff3a36 6114 u8 reserved_at_10[0x10];
e281682b 6115
b4ff3a36 6116 u8 reserved_at_20[0x10];
e281682b
SM		 6117 u8 op_mod[0x10];
6118
b4ff3a36 6119 u8 reserved_at_40[0x8];
e281682b
SM		 6120 u8 qpn[0x18];
6121
b4ff3a36 6122 u8 reserved_at_60[0x20];
e281682b
SM		 6123
6124 u8 multicast_gid[16][0x8];
6125};
6126
6127struct mlx5_ifc_arm_xrc_srq_out_bits {
6128 u8 status[0x8];
b4ff3a36 6129 u8 reserved_at_8[0x18];
e281682b
SM		 6130
6131 u8 syndrome[0x20];
6132
b4ff3a36 6133 u8 reserved_at_40[0x40];
e281682b
SM		 6134};
6135
6136enum {
6137 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6138};
6139
6140struct mlx5_ifc_arm_xrc_srq_in_bits {
6141 u8 opcode[0x10];
b4ff3a36 6142 u8 reserved_at_10[0x10];
e281682b 6143
b4ff3a36 6144 u8 reserved_at_20[0x10];
e281682b
SM		 6145 u8 op_mod[0x10];
6146
b4ff3a36 6147 u8 reserved_at_40[0x8];
e281682b
SM		 6148 u8 xrc_srqn[0x18];
6149
b4ff3a36 6150 u8 reserved_at_60[0x10];
e281682b
SM		 6151 u8 lwm[0x10];
6152};
6153
6154struct mlx5_ifc_arm_rq_out_bits {
6155 u8 status[0x8];
b4ff3a36 6156 u8 reserved_at_8[0x18];
e281682b
SM		 6157
6158 u8 syndrome[0x20];
6159
b4ff3a36 6160 u8 reserved_at_40[0x40];
e281682b
SM		 6161};
6162
6163enum {
6164 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
6165};
6166
6167struct mlx5_ifc_arm_rq_in_bits {
6168 u8 opcode[0x10];
b4ff3a36 6169 u8 reserved_at_10[0x10];
e281682b 6170
b4ff3a36 6171 u8 reserved_at_20[0x10];
e281682b
SM		 6172 u8 op_mod[0x10];
6173
b4ff3a36 6174 u8 reserved_at_40[0x8];
e281682b
SM		 6175 u8 srq_number[0x18];
6176
b4ff3a36 6177 u8 reserved_at_60[0x10];
e281682b
SM		 6178 u8 lwm[0x10];
6179};
6180
6181struct mlx5_ifc_arm_dct_out_bits {
6182 u8 status[0x8];
b4ff3a36 6183 u8 reserved_at_8[0x18];
e281682b
SM		 6184
6185 u8 syndrome[0x20];
6186
b4ff3a36 6187 u8 reserved_at_40[0x40];
e281682b
SM		 6188};
6189
6190struct mlx5_ifc_arm_dct_in_bits {
6191 u8 opcode[0x10];
b4ff3a36 6192 u8 reserved_at_10[0x10];
e281682b 6193
b4ff3a36 6194 u8 reserved_at_20[0x10];
e281682b
SM		 6195 u8 op_mod[0x10];
6196
b4ff3a36 6197 u8 reserved_at_40[0x8];
e281682b
SM		 6198 u8 dct_number[0x18];
6199
b4ff3a36 6200 u8 reserved_at_60[0x20];
e281682b
SM		 6201};
6202
6203struct mlx5_ifc_alloc_xrcd_out_bits {
6204 u8 status[0x8];
b4ff3a36 6205 u8 reserved_at_8[0x18];
e281682b
SM		 6206
6207 u8 syndrome[0x20];
6208
b4ff3a36 6209 u8 reserved_at_40[0x8];
e281682b
SM		 6210 u8 xrcd[0x18];
6211
b4ff3a36 6212 u8 reserved_at_60[0x20];
e281682b
SM		 6213};
6214
6215struct mlx5_ifc_alloc_xrcd_in_bits {
6216 u8 opcode[0x10];
b4ff3a36 6217 u8 reserved_at_10[0x10];
e281682b 6218
b4ff3a36 6219 u8 reserved_at_20[0x10];
e281682b
SM		 6220 u8 op_mod[0x10];
6221
b4ff3a36 6222 u8 reserved_at_40[0x40];
e281682b
SM		 6223};
6224
6225struct mlx5_ifc_alloc_uar_out_bits {
6226 u8 status[0x8];
b4ff3a36 6227 u8 reserved_at_8[0x18];
e281682b
SM		 6228
6229 u8 syndrome[0x20];
6230
b4ff3a36 6231 u8 reserved_at_40[0x8];
e281682b
SM		 6232 u8 uar[0x18];
6233
b4ff3a36 6234 u8 reserved_at_60[0x20];
e281682b
SM		 6235};
6236
6237struct mlx5_ifc_alloc_uar_in_bits {
6238 u8 opcode[0x10];
b4ff3a36 6239 u8 reserved_at_10[0x10];
e281682b 6240
b4ff3a36 6241 u8 reserved_at_20[0x10];
e281682b
SM		 6242 u8 op_mod[0x10];
6243
b4ff3a36 6244 u8 reserved_at_40[0x40];
e281682b
SM		 6245};
6246
6247struct mlx5_ifc_alloc_transport_domain_out_bits {
6248 u8 status[0x8];
b4ff3a36 6249 u8 reserved_at_8[0x18];
e281682b
SM		 6250
6251 u8 syndrome[0x20];
6252
b4ff3a36 6253 u8 reserved_at_40[0x8];
e281682b
SM		 6254 u8 transport_domain[0x18];
6255
b4ff3a36 6256 u8 reserved_at_60[0x20];
e281682b
SM		 6257};
6258
6259struct mlx5_ifc_alloc_transport_domain_in_bits {
6260 u8 opcode[0x10];
b4ff3a36 6261 u8 reserved_at_10[0x10];
e281682b 6262
b4ff3a36 6263 u8 reserved_at_20[0x10];
e281682b
SM		 6264 u8 op_mod[0x10];
6265
b4ff3a36 6266 u8 reserved_at_40[0x40];
e281682b
SM		 6267};
6268
6269struct mlx5_ifc_alloc_q_counter_out_bits {
6270 u8 status[0x8];
b4ff3a36 6271 u8 reserved_at_8[0x18];
e281682b
SM		 6272
6273 u8 syndrome[0x20];
6274
b4ff3a36 6275 u8 reserved_at_40[0x18];
e281682b
SM		 6276 u8 counter_set_id[0x8];
6277
b4ff3a36 6278 u8 reserved_at_60[0x20];
e281682b
SM		 6279};
6280
6281struct mlx5_ifc_alloc_q_counter_in_bits {
6282 u8 opcode[0x10];
b4ff3a36 6283 u8 reserved_at_10[0x10];
e281682b 6284
b4ff3a36 6285 u8 reserved_at_20[0x10];
e281682b
SM		 6286 u8 op_mod[0x10];
6287
b4ff3a36 6288 u8 reserved_at_40[0x40];
e281682b
SM		 6289};
6290
6291struct mlx5_ifc_alloc_pd_out_bits {
6292 u8 status[0x8];
b4ff3a36 6293 u8 reserved_at_8[0x18];
e281682b
SM		 6294
6295 u8 syndrome[0x20];
6296
b4ff3a36 6297 u8 reserved_at_40[0x8];
e281682b
SM		 6298 u8 pd[0x18];
6299
b4ff3a36 6300 u8 reserved_at_60[0x20];
e281682b
SM		 6301};
6302
6303struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6304 u8 opcode[0x10];
6305 u8 reserved_at_10[0x10];
6306
6307 u8 reserved_at_20[0x10];
6308 u8 op_mod[0x10];
6309
6310 u8 reserved_at_40[0x40];
6311};
6312
6313struct mlx5_ifc_alloc_flow_counter_out_bits {
6314 u8 status[0x8];
6315 u8 reserved_at_8[0x18];
6316
6317 u8 syndrome[0x20];
6318
6319 u8 reserved_at_40[0x10];
6320 u8 flow_counter_id[0x10];
6321
6322 u8 reserved_at_60[0x20];
6323};
6324
6325struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6326 u8 opcode[0x10];
b4ff3a36 6327 u8 reserved_at_10[0x10];
e281682b 6328
b4ff3a36 6329 u8 reserved_at_20[0x10];
e281682b
SM		 6330 u8 op_mod[0x10];
6331
b4ff3a36 6332 u8 reserved_at_40[0x40];
e281682b
SM		 6333};
6334
6335struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6336 u8 status[0x8];
b4ff3a36 6337 u8 reserved_at_8[0x18];
e281682b
SM		 6338
6339 u8 syndrome[0x20];
6340
b4ff3a36 6341 u8 reserved_at_40[0x40];
e281682b
SM		 6342};
6343
6344struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6345 u8 opcode[0x10];
b4ff3a36 6346 u8 reserved_at_10[0x10];
e281682b 6347
b4ff3a36 6348 u8 reserved_at_20[0x10];
e281682b
SM		 6349 u8 op_mod[0x10];
6350
b4ff3a36 6351 u8 reserved_at_40[0x20];
e281682b 6352
b4ff3a36 6353 u8 reserved_at_60[0x10];
e281682b
SM		 6354 u8 vxlan_udp_port[0x10];
6355};
6356
6357struct mlx5_ifc_access_register_out_bits {
6358 u8 status[0x8];
b4ff3a36 6359 u8 reserved_at_8[0x18];
e281682b
SM		 6360
6361 u8 syndrome[0x20];
6362
b4ff3a36 6363 u8 reserved_at_40[0x40];
e281682b
SM		 6364
6365 u8 register_data[0][0x20];
6366};
6367
6368enum {
6369 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6370 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6371};
6372
6373struct mlx5_ifc_access_register_in_bits {
6374 u8 opcode[0x10];
b4ff3a36 6375 u8 reserved_at_10[0x10];
e281682b 6376
b4ff3a36 6377 u8 reserved_at_20[0x10];
e281682b
SM		 6378 u8 op_mod[0x10];
6379
b4ff3a36 6380 u8 reserved_at_40[0x10];
e281682b
SM		 6381 u8 register_id[0x10];
6382
6383 u8 argument[0x20];
6384
6385 u8 register_data[0][0x20];
6386};
6387
6388struct mlx5_ifc_sltp_reg_bits {
6389 u8 status[0x4];
6390 u8 version[0x4];
6391 u8 local_port[0x8];
6392 u8 pnat[0x2];
b4ff3a36 6393 u8 reserved_at_12[0x2];
e281682b 6394 u8 lane[0x4];
b4ff3a36 6395 u8 reserved_at_18[0x8];
e281682b 6396
b4ff3a36 6397 u8 reserved_at_20[0x20];
e281682b 6398
b4ff3a36 6399 u8 reserved_at_40[0x7];
e281682b
SM		 6400 u8 polarity[0x1];
6401 u8 ob_tap0[0x8];
6402 u8 ob_tap1[0x8];
6403 u8 ob_tap2[0x8];
6404
b4ff3a36 6405 u8 reserved_at_60[0xc];
e281682b
SM		 6406 u8 ob_preemp_mode[0x4];
6407 u8 ob_reg[0x8];
6408 u8 ob_bias[0x8];
6409
b4ff3a36 6410 u8 reserved_at_80[0x20];
e281682b
SM		 6411};
6412
6413struct mlx5_ifc_slrg_reg_bits {
6414 u8 status[0x4];
6415 u8 version[0x4];
6416 u8 local_port[0x8];
6417 u8 pnat[0x2];
b4ff3a36 6418 u8 reserved_at_12[0x2];
e281682b 6419 u8 lane[0x4];
b4ff3a36 6420 u8 reserved_at_18[0x8];
e281682b
SM		 6421
6422 u8 time_to_link_up[0x10];
b4ff3a36 6423 u8 reserved_at_30[0xc];
e281682b
SM		 6424 u8 grade_lane_speed[0x4];
6425
6426 u8 grade_version[0x8];
6427 u8 grade[0x18];
6428
b4ff3a36 6429 u8 reserved_at_60[0x4];
e281682b
SM		 6430 u8 height_grade_type[0x4];
6431 u8 height_grade[0x18];
6432
6433 u8 height_dz[0x10];
6434 u8 height_dv[0x10];
6435
b4ff3a36 6436 u8 reserved_at_a0[0x10];
e281682b
SM		 6437 u8 height_sigma[0x10];
6438
b4ff3a36 6439 u8 reserved_at_c0[0x20];
e281682b 6440
b4ff3a36 6441 u8 reserved_at_e0[0x4];
e281682b
SM		 6442 u8 phase_grade_type[0x4];
6443 u8 phase_grade[0x18];
6444
b4ff3a36 6445 u8 reserved_at_100[0x8];
e281682b 6446 u8 phase_eo_pos[0x8];
b4ff3a36 6447 u8 reserved_at_110[0x8];
e281682b
SM		 6448 u8 phase_eo_neg[0x8];
6449
6450 u8 ffe_set_tested[0x10];
6451 u8 test_errors_per_lane[0x10];
6452};
6453
6454struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 6455 u8 reserved_at_0[0x8];
e281682b 6456 u8 local_port[0x8];
b4ff3a36 6457 u8 reserved_at_10[0x10];
e281682b 6458
b4ff3a36 6459 u8 reserved_at_20[0x1c];
e281682b
SM		 6460 u8 vl_hw_cap[0x4];
6461
b4ff3a36 6462 u8 reserved_at_40[0x1c];
e281682b
SM		 6463 u8 vl_admin[0x4];
6464
b4ff3a36 6465 u8 reserved_at_60[0x1c];
e281682b
SM		 6466 u8 vl_operational[0x4];
6467};
6468
6469struct mlx5_ifc_pude_reg_bits {
6470 u8 swid[0x8];
6471 u8 local_port[0x8];
b4ff3a36 6472 u8 reserved_at_10[0x4];
e281682b 6473 u8 admin_status[0x4];
b4ff3a36 6474 u8 reserved_at_18[0x4];
e281682b
SM		 6475 u8 oper_status[0x4];
6476
b4ff3a36 6477 u8 reserved_at_20[0x60];
e281682b
SM		 6478};
6479
6480struct mlx5_ifc_ptys_reg_bits {
b4ff3a36 6481 u8 reserved_at_0[0x8];
e281682b 6482 u8 local_port[0x8];
b4ff3a36 6483 u8 reserved_at_10[0xd];
e281682b
SM		 6484 u8 proto_mask[0x3];
6485
b4ff3a36 6486 u8 reserved_at_20[0x40];
e281682b
SM		 6487
6488 u8 eth_proto_capability[0x20];
6489
6490 u8 ib_link_width_capability[0x10];
6491 u8 ib_proto_capability[0x10];
6492
b4ff3a36 6493 u8 reserved_at_a0[0x20];
e281682b
SM		 6494
6495 u8 eth_proto_admin[0x20];
6496
6497 u8 ib_link_width_admin[0x10];
6498 u8 ib_proto_admin[0x10];
6499
b4ff3a36 6500 u8 reserved_at_100[0x20];
e281682b
SM		 6501
6502 u8 eth_proto_oper[0x20];
6503
6504 u8 ib_link_width_oper[0x10];
6505 u8 ib_proto_oper[0x10];
6506
b4ff3a36 6507 u8 reserved_at_160[0x20];
e281682b
SM		 6508
6509 u8 eth_proto_lp_advertise[0x20];
6510
b4ff3a36 6511 u8 reserved_at_1a0[0x60];
e281682b
SM		 6512};
6513
7d5e1423
SM		 6514struct mlx5_ifc_mlcr_reg_bits {
6515 u8 reserved_at_0[0x8];
6516 u8 local_port[0x8];
6517 u8 reserved_at_10[0x20];
6518
6519 u8 beacon_duration[0x10];
6520 u8 reserved_at_40[0x10];
6521
6522 u8 beacon_remain[0x10];
6523};
6524
e281682b 6525struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 6526 u8 reserved_at_0[0x20];
e281682b
SM		 6527
6528 u8 algorithm_options[0x10];
b4ff3a36 6529 u8 reserved_at_30[0x4];
e281682b
SM		 6530 u8 repetitions_mode[0x4];
6531 u8 num_of_repetitions[0x8];
6532
6533 u8 grade_version[0x8];
6534 u8 height_grade_type[0x4];
6535 u8 phase_grade_type[0x4];
6536 u8 height_grade_weight[0x8];
6537 u8 phase_grade_weight[0x8];
6538
6539 u8 gisim_measure_bits[0x10];
6540 u8 adaptive_tap_measure_bits[0x10];
6541
6542 u8 ber_bath_high_error_threshold[0x10];
6543 u8 ber_bath_mid_error_threshold[0x10];
6544
6545 u8 ber_bath_low_error_threshold[0x10];
6546 u8 one_ratio_high_threshold[0x10];
6547
6548 u8 one_ratio_high_mid_threshold[0x10];
6549 u8 one_ratio_low_mid_threshold[0x10];
6550
6551 u8 one_ratio_low_threshold[0x10];
6552 u8 ndeo_error_threshold[0x10];
6553
6554 u8 mixer_offset_step_size[0x10];
b4ff3a36 6555 u8 reserved_at_110[0x8];
e281682b
SM		 6556 u8 mix90_phase_for_voltage_bath[0x8];
6557
6558 u8 mixer_offset_start[0x10];
6559 u8 mixer_offset_end[0x10];
6560
b4ff3a36 6561 u8 reserved_at_140[0x15];
e281682b
SM		 6562 u8 ber_test_time[0xb];
6563};
6564
6565struct mlx5_ifc_pspa_reg_bits {
6566 u8 swid[0x8];
6567 u8 local_port[0x8];
6568 u8 sub_port[0x8];
b4ff3a36 6569 u8 reserved_at_18[0x8];
e281682b 6570
b4ff3a36 6571 u8 reserved_at_20[0x20];
e281682b
SM		 6572};
6573
6574struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 6575 u8 reserved_at_0[0x8];
e281682b 6576 u8 local_port[0x8];
b4ff3a36 6577 u8 reserved_at_10[0x5];
e281682b 6578 u8 prio[0x3];
b4ff3a36 6579 u8 reserved_at_18[0x6];
e281682b
SM		 6580 u8 mode[0x2];
6581
b4ff3a36 6582 u8 reserved_at_20[0x20];
e281682b 6583
b4ff3a36 6584 u8 reserved_at_40[0x10];
e281682b
SM		 6585 u8 min_threshold[0x10];
6586
b4ff3a36 6587 u8 reserved_at_60[0x10];
e281682b
SM		 6588 u8 max_threshold[0x10];
6589
b4ff3a36 6590 u8 reserved_at_80[0x10];
e281682b
SM		 6591 u8 mark_probability_denominator[0x10];
6592
b4ff3a36 6593 u8 reserved_at_a0[0x60];
e281682b
SM		 6594};
6595
6596struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 6597 u8 reserved_at_0[0x8];
e281682b 6598 u8 local_port[0x8];
b4ff3a36 6599 u8 reserved_at_10[0x10];
e281682b 6600
b4ff3a36 6601 u8 reserved_at_20[0x60];
e281682b 6602
b4ff3a36 6603 u8 reserved_at_80[0x1c];
e281682b
SM		 6604 u8 wrps_admin[0x4];
6605
b4ff3a36 6606 u8 reserved_at_a0[0x1c];
e281682b
SM		 6607 u8 wrps_status[0x4];
6608
b4ff3a36 6609 u8 reserved_at_c0[0x8];
e281682b 6610 u8 up_threshold[0x8];
b4ff3a36 6611 u8 reserved_at_d0[0x8];
e281682b
SM		 6612 u8 down_threshold[0x8];
6613
b4ff3a36 6614 u8 reserved_at_e0[0x20];
e281682b 6615
b4ff3a36 6616 u8 reserved_at_100[0x1c];
e281682b
SM		 6617 u8 srps_admin[0x4];
6618
b4ff3a36 6619 u8 reserved_at_120[0x1c];
e281682b
SM		 6620 u8 srps_status[0x4];
6621
b4ff3a36 6622 u8 reserved_at_140[0x40];
e281682b
SM		 6623};
6624
6625struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 6626 u8 reserved_at_0[0x8];
e281682b 6627 u8 local_port[0x8];
b4ff3a36 6628 u8 reserved_at_10[0x10];
e281682b 6629
b4ff3a36 6630 u8 reserved_at_20[0x8];
e281682b 6631 u8 lb_cap[0x8];
b4ff3a36 6632 u8 reserved_at_30[0x8];
e281682b
SM		 6633 u8 lb_en[0x8];
6634};
6635
6636struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 6637 u8 reserved_at_0[0x8];
e281682b 6638 u8 local_port[0x8];
b4ff3a36 6639 u8 reserved_at_10[0x10];
e281682b 6640
b4ff3a36 6641 u8 reserved_at_20[0x20];
e281682b
SM		 6642
6643 u8 port_profile_mode[0x8];
6644 u8 static_port_profile[0x8];
6645 u8 active_port_profile[0x8];
b4ff3a36 6646 u8 reserved_at_58[0x8];
e281682b
SM		 6647
6648 u8 retransmission_active[0x8];
6649 u8 fec_mode_active[0x18];
6650
b4ff3a36 6651 u8 reserved_at_80[0x20];
e281682b
SM		 6652};
6653
6654struct mlx5_ifc_ppcnt_reg_bits {
6655 u8 swid[0x8];
6656 u8 local_port[0x8];
6657 u8 pnat[0x2];
b4ff3a36 6658 u8 reserved_at_12[0x8];
e281682b
SM		 6659 u8 grp[0x6];
6660
6661 u8 clr[0x1];
b4ff3a36 6662 u8 reserved_at_21[0x1c];
e281682b
SM		 6663 u8 prio_tc[0x3];
6664
6665 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6666};
6667
6668struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 6669 u8 reserved_at_0[0x3];
e281682b 6670 u8 single_mac[0x1];
b4ff3a36 6671 u8 reserved_at_4[0x4];
e281682b
SM		 6672 u8 local_port[0x8];
6673 u8 mac_47_32[0x10];
6674
6675 u8 mac_31_0[0x20];
6676
b4ff3a36 6677 u8 reserved_at_40[0x40];
e281682b
SM		 6678};
6679
6680struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 6681 u8 reserved_at_0[0x8];
e281682b 6682 u8 local_port[0x8];
b4ff3a36 6683 u8 reserved_at_10[0x10];
e281682b
SM		 6684
6685 u8 max_mtu[0x10];
b4ff3a36 6686 u8 reserved_at_30[0x10];
e281682b
SM		 6687
6688 u8 admin_mtu[0x10];
b4ff3a36 6689 u8 reserved_at_50[0x10];
e281682b
SM		 6690
6691 u8 oper_mtu[0x10];
b4ff3a36 6692 u8 reserved_at_70[0x10];
e281682b
SM		 6693};
6694
6695struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 6696 u8 reserved_at_0[0x8];
e281682b 6697 u8 module[0x8];
b4ff3a36 6698 u8 reserved_at_10[0x10];
e281682b 6699
b4ff3a36 6700 u8 reserved_at_20[0x18];
e281682b
SM		 6701 u8 attenuation_5g[0x8];
6702
b4ff3a36 6703 u8 reserved_at_40[0x18];
e281682b
SM		 6704 u8 attenuation_7g[0x8];
6705
b4ff3a36 6706 u8 reserved_at_60[0x18];
e281682b
SM		 6707 u8 attenuation_12g[0x8];
6708};
6709
6710struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 6711 u8 reserved_at_0[0x8];
e281682b 6712 u8 module[0x8];
b4ff3a36 6713 u8 reserved_at_10[0xc];
e281682b
SM		 6714 u8 module_status[0x4];
6715
b4ff3a36 6716 u8 reserved_at_20[0x60];
e281682b
SM		 6717};
6718
6719struct mlx5_ifc_pmpc_reg_bits {
6720 u8 module_state_updated[32][0x8];
6721};
6722
6723struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 6724 u8 reserved_at_0[0x4];
e281682b
SM		 6725 u8 mlpn_status[0x4];
6726 u8 local_port[0x8];
b4ff3a36 6727 u8 reserved_at_10[0x10];
e281682b
SM		 6728
6729 u8 e[0x1];
b4ff3a36 6730 u8 reserved_at_21[0x1f];
e281682b
SM		 6731};
6732
6733struct mlx5_ifc_pmlp_reg_bits {
6734 u8 rxtx[0x1];
b4ff3a36 6735 u8 reserved_at_1[0x7];
e281682b 6736 u8 local_port[0x8];
b4ff3a36 6737 u8 reserved_at_10[0x8];
e281682b
SM		 6738 u8 width[0x8];
6739
6740 u8 lane0_module_mapping[0x20];
6741
6742 u8 lane1_module_mapping[0x20];
6743
6744 u8 lane2_module_mapping[0x20];
6745
6746 u8 lane3_module_mapping[0x20];
6747
b4ff3a36 6748 u8 reserved_at_a0[0x160];
e281682b
SM		 6749};
6750
6751struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 6752 u8 reserved_at_0[0x8];
e281682b 6753 u8 module[0x8];
b4ff3a36 6754 u8 reserved_at_10[0x4];
e281682b 6755 u8 admin_status[0x4];
b4ff3a36 6756 u8 reserved_at_18[0x4];
e281682b
SM		 6757 u8 oper_status[0x4];
6758
6759 u8 ase[0x1];
6760 u8 ee[0x1];
b4ff3a36 6761 u8 reserved_at_22[0x1c];
e281682b
SM		 6762 u8 e[0x2];
6763
b4ff3a36 6764 u8 reserved_at_40[0x40];
e281682b
SM		 6765};
6766
6767struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 6768 u8 reserved_at_0[0x4];
e281682b 6769 u8 profile_id[0xc];
b4ff3a36 6770 u8 reserved_at_10[0x4];
e281682b 6771 u8 proto_mask[0x4];
b4ff3a36 6772 u8 reserved_at_18[0x8];
e281682b 6773
b4ff3a36 6774 u8 reserved_at_20[0x10];
e281682b
SM		 6775 u8 lane_speed[0x10];
6776
b4ff3a36 6777 u8 reserved_at_40[0x17];
e281682b
SM		 6778 u8 lpbf[0x1];
6779 u8 fec_mode_policy[0x8];
6780
6781 u8 retransmission_capability[0x8];
6782 u8 fec_mode_capability[0x18];
6783
6784 u8 retransmission_support_admin[0x8];
6785 u8 fec_mode_support_admin[0x18];
6786
6787 u8 retransmission_request_admin[0x8];
6788 u8 fec_mode_request_admin[0x18];
6789
b4ff3a36 6790 u8 reserved_at_c0[0x80];
e281682b
SM		 6791};
6792
6793struct mlx5_ifc_plib_reg_bits {
b4ff3a36 6794 u8 reserved_at_0[0x8];
e281682b 6795 u8 local_port[0x8];
b4ff3a36 6796 u8 reserved_at_10[0x8];
e281682b
SM		 6797 u8 ib_port[0x8];
6798
b4ff3a36 6799 u8 reserved_at_20[0x60];
e281682b
SM		 6800};
6801
6802struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 6803 u8 reserved_at_0[0x8];
e281682b 6804 u8 local_port[0x8];
b4ff3a36 6805 u8 reserved_at_10[0xd];
e281682b
SM		 6806 u8 lbf_mode[0x3];
6807
b4ff3a36 6808 u8 reserved_at_20[0x20];
e281682b
SM		 6809};
6810
6811struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 6812 u8 reserved_at_0[0x8];
e281682b 6813 u8 local_port[0x8];
b4ff3a36 6814 u8 reserved_at_10[0x10];
e281682b
SM		 6815
6816 u8 dic[0x1];
b4ff3a36 6817 u8 reserved_at_21[0x19];
e281682b 6818 u8 ipg[0x4];
b4ff3a36 6819 u8 reserved_at_3e[0x2];
e281682b
SM		 6820};
6821
6822struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 6823 u8 reserved_at_0[0x8];
e281682b 6824 u8 local_port[0x8];
b4ff3a36 6825 u8 reserved_at_10[0x10];
e281682b 6826
b4ff3a36 6827 u8 reserved_at_20[0xe0];
e281682b
SM		 6828
6829 u8 port_filter[8][0x20];
6830
6831 u8 port_filter_update_en[8][0x20];
6832};
6833
6834struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 6835 u8 reserved_at_0[0x8];
e281682b 6836 u8 local_port[0x8];
b4ff3a36 6837 u8 reserved_at_10[0x10];
e281682b
SM		 6838
6839 u8 ppan[0x4];
b4ff3a36 6840 u8 reserved_at_24[0x4];
e281682b 6841 u8 prio_mask_tx[0x8];
b4ff3a36 6842 u8 reserved_at_30[0x8];
e281682b
SM		 6843 u8 prio_mask_rx[0x8];
6844
6845 u8 pptx[0x1];
6846 u8 aptx[0x1];
b4ff3a36 6847 u8 reserved_at_42[0x6];
e281682b 6848 u8 pfctx[0x8];
b4ff3a36 6849 u8 reserved_at_50[0x10];
e281682b
SM		 6850
6851 u8 pprx[0x1];
6852 u8 aprx[0x1];
b4ff3a36 6853 u8 reserved_at_62[0x6];
e281682b 6854 u8 pfcrx[0x8];
b4ff3a36 6855 u8 reserved_at_70[0x10];
e281682b 6856
b4ff3a36 6857 u8 reserved_at_80[0x80];
e281682b
SM		 6858};
6859
6860struct mlx5_ifc_pelc_reg_bits {
6861 u8 op[0x4];
b4ff3a36 6862 u8 reserved_at_4[0x4];
e281682b 6863 u8 local_port[0x8];
b4ff3a36 6864 u8 reserved_at_10[0x10];
e281682b
SM		 6865
6866 u8 op_admin[0x8];
6867 u8 op_capability[0x8];
6868 u8 op_request[0x8];
6869 u8 op_active[0x8];
6870
6871 u8 admin[0x40];
6872
6873 u8 capability[0x40];
6874
6875 u8 request[0x40];
6876
6877 u8 active[0x40];
6878
b4ff3a36 6879 u8 reserved_at_140[0x80];
e281682b
SM		 6880};
6881
6882struct mlx5_ifc_peir_reg_bits {
b4ff3a36 6883 u8 reserved_at_0[0x8];
e281682b 6884 u8 local_port[0x8];
b4ff3a36 6885 u8 reserved_at_10[0x10];
e281682b 6886
b4ff3a36 6887 u8 reserved_at_20[0xc];
e281682b 6888 u8 error_count[0x4];
b4ff3a36 6889 u8 reserved_at_30[0x10];
e281682b 6890
b4ff3a36 6891 u8 reserved_at_40[0xc];
e281682b 6892 u8 lane[0x4];
b4ff3a36 6893 u8 reserved_at_50[0x8];
e281682b
SM		 6894 u8 error_type[0x8];
6895};
6896
6897struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 6898 u8 reserved_at_0[0x8];
e281682b 6899 u8 local_port[0x8];
b4ff3a36 6900 u8 reserved_at_10[0x10];
e281682b
SM		 6901
6902 u8 port_capability_mask[4][0x20];
6903};
6904
6905struct mlx5_ifc_paos_reg_bits {
6906 u8 swid[0x8];
6907 u8 local_port[0x8];
b4ff3a36 6908 u8 reserved_at_10[0x4];
e281682b 6909 u8 admin_status[0x4];
b4ff3a36 6910 u8 reserved_at_18[0x4];
e281682b
SM		 6911 u8 oper_status[0x4];
6912
6913 u8 ase[0x1];
6914 u8 ee[0x1];
b4ff3a36 6915 u8 reserved_at_22[0x1c];
e281682b
SM		 6916 u8 e[0x2];
6917
b4ff3a36 6918 u8 reserved_at_40[0x40];
e281682b
SM		 6919};
6920
6921struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 6922 u8 reserved_at_0[0x8];
e281682b 6923 u8 opamp_group[0x8];
b4ff3a36 6924 u8 reserved_at_10[0xc];
e281682b
SM		 6925 u8 opamp_group_type[0x4];
6926
6927 u8 start_index[0x10];
b4ff3a36 6928 u8 reserved_at_30[0x4];
e281682b
SM		 6929 u8 num_of_indices[0xc];
6930
6931 u8 index_data[18][0x10];
6932};
6933
7d5e1423
SM		 6934struct mlx5_ifc_pcmr_reg_bits {
6935 u8 reserved_at_0[0x8];
6936 u8 local_port[0x8];
6937 u8 reserved_at_10[0x2e];
6938 u8 fcs_cap[0x1];
6939 u8 reserved_at_3f[0x1f];
6940 u8 fcs_chk[0x1];
6941 u8 reserved_at_5f[0x1];
6942};
6943
e281682b 6944struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 6945 u8 reserved_at_0[0x6];
e281682b 6946 u8 rx_lane[0x2];
b4ff3a36 6947 u8 reserved_at_8[0x6];
e281682b 6948 u8 tx_lane[0x2];
b4ff3a36 6949 u8 reserved_at_10[0x8];
e281682b
SM		 6950 u8 module[0x8];
6951};
6952
6953struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 6954 u8 reserved_at_0[0x6];
e281682b
SM		 6955 u8 lossy[0x1];
6956 u8 epsb[0x1];
b4ff3a36 6957 u8 reserved_at_8[0xc];
e281682b
SM		 6958 u8 size[0xc];
6959
6960 u8 xoff_threshold[0x10];
6961 u8 xon_threshold[0x10];
6962};
6963
6964struct mlx5_ifc_set_node_in_bits {
6965 u8 node_description[64][0x8];
6966};
6967
6968struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 6969 u8 reserved_at_0[0x18];
e281682b
SM		 6970 u8 power_settings_level[0x8];
6971
b4ff3a36 6972 u8 reserved_at_20[0x60];
e281682b
SM		 6973};
6974
6975struct mlx5_ifc_register_host_endianness_bits {
6976 u8 he[0x1];
b4ff3a36 6977 u8 reserved_at_1[0x1f];
e281682b 6978
b4ff3a36 6979 u8 reserved_at_20[0x60];
e281682b
SM		 6980};
6981
6982struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 6983 u8 reserved_at_0[0x20];
e281682b
SM		 6984
6985 u8 mkey[0x20];
6986
6987 u8 addressh_63_32[0x20];
6988
6989 u8 addressl_31_0[0x20];
6990};
6991
6992struct mlx5_ifc_ud_adrs_vector_bits {
6993 u8 dc_key[0x40];
6994
6995 u8 ext[0x1];
b4ff3a36 6996 u8 reserved_at_41[0x7];
e281682b
SM		 6997 u8 destination_qp_dct[0x18];
6998
6999 u8 static_rate[0x4];
7000 u8 sl_eth_prio[0x4];
7001 u8 fl[0x1];
7002 u8 mlid[0x7];
7003 u8 rlid_udp_sport[0x10];
7004
b4ff3a36 7005 u8 reserved_at_80[0x20];
e281682b
SM		 7006
7007 u8 rmac_47_16[0x20];
7008
7009 u8 rmac_15_0[0x10];
7010 u8 tclass[0x8];
7011 u8 hop_limit[0x8];
7012
b4ff3a36 7013 u8 reserved_at_e0[0x1];
e281682b 7014 u8 grh[0x1];
b4ff3a36 7015 u8 reserved_at_e2[0x2];
e281682b
SM		 7016 u8 src_addr_index[0x8];
7017 u8 flow_label[0x14];
7018
7019 u8 rgid_rip[16][0x8];
7020};
7021
7022struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7023 u8 reserved_at_0[0x10];
e281682b
SM		 7024 u8 function_id[0x10];
7025
7026 u8 num_pages[0x20];
7027
b4ff3a36 7028 u8 reserved_at_40[0xa0];
e281682b
SM		 7029};
7030
7031struct mlx5_ifc_eqe_bits {
b4ff3a36 7032 u8 reserved_at_0[0x8];
e281682b 7033 u8 event_type[0x8];
b4ff3a36 7034 u8 reserved_at_10[0x8];
e281682b
SM		 7035 u8 event_sub_type[0x8];
7036
b4ff3a36 7037 u8 reserved_at_20[0xe0];
e281682b
SM		 7038
7039 union mlx5_ifc_event_auto_bits event_data;
7040
b4ff3a36 7041 u8 reserved_at_1e0[0x10];
e281682b 7042 u8 signature[0x8];
b4ff3a36 7043 u8 reserved_at_1f8[0x7];
e281682b
SM		 7044 u8 owner[0x1];
7045};
7046
7047enum {
7048 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7049};
7050
7051struct mlx5_ifc_cmd_queue_entry_bits {
7052 u8 type[0x8];
b4ff3a36 7053 u8 reserved_at_8[0x18];
e281682b
SM		 7054
7055 u8 input_length[0x20];
7056
7057 u8 input_mailbox_pointer_63_32[0x20];
7058
7059 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7060 u8 reserved_at_77[0x9];
e281682b
SM		 7061
7062 u8 command_input_inline_data[16][0x8];
7063
7064 u8 command_output_inline_data[16][0x8];
7065
7066 u8 output_mailbox_pointer_63_32[0x20];
7067
7068 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7069 u8 reserved_at_1b7[0x9];
e281682b
SM		 7070
7071 u8 output_length[0x20];
7072
7073 u8 token[0x8];
7074 u8 signature[0x8];
b4ff3a36 7075 u8 reserved_at_1f0[0x8];
e281682b
SM		 7076 u8 status[0x7];
7077 u8 ownership[0x1];
7078};
7079
7080struct mlx5_ifc_cmd_out_bits {
7081 u8 status[0x8];
b4ff3a36 7082 u8 reserved_at_8[0x18];
e281682b
SM		 7083
7084 u8 syndrome[0x20];
7085
7086 u8 command_output[0x20];
7087};
7088
7089struct mlx5_ifc_cmd_in_bits {
7090 u8 opcode[0x10];
b4ff3a36 7091 u8 reserved_at_10[0x10];
e281682b 7092
b4ff3a36 7093 u8 reserved_at_20[0x10];
e281682b
SM		 7094 u8 op_mod[0x10];
7095
7096 u8 command[0][0x20];
7097};
7098
7099struct mlx5_ifc_cmd_if_box_bits {
7100 u8 mailbox_data[512][0x8];
7101
b4ff3a36 7102 u8 reserved_at_1000[0x180];
e281682b
SM		 7103
7104 u8 next_pointer_63_32[0x20];
7105
7106 u8 next_pointer_31_10[0x16];
b4ff3a36 7107 u8 reserved_at_11b6[0xa];
e281682b
SM		 7108
7109 u8 block_number[0x20];
7110
b4ff3a36 7111 u8 reserved_at_11e0[0x8];
e281682b
SM		 7112 u8 token[0x8];
7113 u8 ctrl_signature[0x8];
7114 u8 signature[0x8];
7115};
7116
7117struct mlx5_ifc_mtt_bits {
7118 u8 ptag_63_32[0x20];
7119
7120 u8 ptag_31_8[0x18];
b4ff3a36 7121 u8 reserved_at_38[0x6];
e281682b
SM		 7122 u8 wr_en[0x1];
7123 u8 rd_en[0x1];
7124};
7125
928cfe87
TT		 7126struct mlx5_ifc_query_wol_rol_out_bits {
7127 u8 status[0x8];
7128 u8 reserved_at_8[0x18];
7129
7130 u8 syndrome[0x20];
7131
7132 u8 reserved_at_40[0x10];
7133 u8 rol_mode[0x8];
7134 u8 wol_mode[0x8];
7135
7136 u8 reserved_at_60[0x20];
7137};
7138
7139struct mlx5_ifc_query_wol_rol_in_bits {
7140 u8 opcode[0x10];
7141 u8 reserved_at_10[0x10];
7142
7143 u8 reserved_at_20[0x10];
7144 u8 op_mod[0x10];
7145
7146 u8 reserved_at_40[0x40];
7147};
7148
7149struct mlx5_ifc_set_wol_rol_out_bits {
7150 u8 status[0x8];
7151 u8 reserved_at_8[0x18];
7152
7153 u8 syndrome[0x20];
7154
7155 u8 reserved_at_40[0x40];
7156};
7157
7158struct mlx5_ifc_set_wol_rol_in_bits {
7159 u8 opcode[0x10];
7160 u8 reserved_at_10[0x10];
7161
7162 u8 reserved_at_20[0x10];
7163 u8 op_mod[0x10];
7164
7165 u8 rol_mode_valid[0x1];
7166 u8 wol_mode_valid[0x1];
7167 u8 reserved_at_42[0xe];
7168 u8 rol_mode[0x8];
7169 u8 wol_mode[0x8];
7170
7171 u8 reserved_at_60[0x20];
7172};
7173
e281682b
SM		 7174enum {
7175 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7176 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7177 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7178};
7179
7180enum {
7181 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7182 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7183 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7184};
7185
7186enum {
7187 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7188 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7189 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7190 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7191 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7192 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7196 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7197 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7198};
7199
7200struct mlx5_ifc_initial_seg_bits {
7201 u8 fw_rev_minor[0x10];
7202 u8 fw_rev_major[0x10];
7203
7204 u8 cmd_interface_rev[0x10];
7205 u8 fw_rev_subminor[0x10];
7206
b4ff3a36 7207 u8 reserved_at_40[0x40];
e281682b
SM		 7208
7209 u8 cmdq_phy_addr_63_32[0x20];
7210
7211 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7212 u8 reserved_at_b4[0x2];
e281682b
SM		 7213 u8 nic_interface[0x2];
7214 u8 log_cmdq_size[0x4];
7215 u8 log_cmdq_stride[0x4];
7216
7217 u8 command_doorbell_vector[0x20];
7218
b4ff3a36 7219 u8 reserved_at_e0[0xf00];
e281682b
SM		 7220
7221 u8 initializing[0x1];
b4ff3a36 7222 u8 reserved_at_fe1[0x4];
e281682b 7223 u8 nic_interface_supported[0x3];
b4ff3a36 7224 u8 reserved_at_fe8[0x18];
e281682b
SM		 7225
7226 struct mlx5_ifc_health_buffer_bits health_buffer;
7227
7228 u8 no_dram_nic_offset[0x20];
7229
b4ff3a36 7230 u8 reserved_at_1220[0x6e40];
e281682b 7231
b4ff3a36 7232 u8 reserved_at_8060[0x1f];
e281682b
SM		 7233 u8 clear_int[0x1];
7234
7235 u8 health_syndrome[0x8];
7236 u8 health_counter[0x18];
7237
b4ff3a36 7238 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7239};
7240
7241union mlx5_ifc_ports_control_registers_document_bits {
7242 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7243 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7244 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7245 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7246 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7247 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7248 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7249 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7250 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7251 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7252 struct mlx5_ifc_paos_reg_bits paos_reg;
7253 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7254 struct mlx5_ifc_peir_reg_bits peir_reg;
7255 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7256 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 7257 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 7258 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7259 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7260 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7261 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7262 struct mlx5_ifc_plib_reg_bits plib_reg;
7263 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7264 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7265 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7266 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7267 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7268 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7269 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7270 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7271 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7272 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7273 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7274 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7275 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7276 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7277 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7278 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7279 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 7280 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 7281 struct mlx5_ifc_pude_reg_bits pude_reg;
7282 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7283 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7284 struct mlx5_ifc_sltp_reg_bits sltp_reg;
b4ff3a36 7285 u8 reserved_at_0[0x60e0];
e281682b
SM		 7286};
7287
7288union mlx5_ifc_debug_enhancements_document_bits {
7289 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 7290 u8 reserved_at_0[0x200];
e281682b
SM		 7291};
7292
7293union mlx5_ifc_uplink_pci_interface_document_bits {
7294 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 7295 u8 reserved_at_0[0x20060];
b775516b
EC		 7296};
7297
2cc43b49
MG		 7298struct mlx5_ifc_set_flow_table_root_out_bits {
7299 u8 status[0x8];
b4ff3a36 7300 u8 reserved_at_8[0x18];
2cc43b49
MG		 7301
7302 u8 syndrome[0x20];
7303
b4ff3a36 7304 u8 reserved_at_40[0x40];
2cc43b49
MG		 7305};
7306
7307struct mlx5_ifc_set_flow_table_root_in_bits {
7308 u8 opcode[0x10];
b4ff3a36 7309 u8 reserved_at_10[0x10];
2cc43b49 7310
b4ff3a36 7311 u8 reserved_at_20[0x10];
2cc43b49
MG		 7312 u8 op_mod[0x10];
7313
7d5e1423
SM		 7314 u8 other_vport[0x1];
7315 u8 reserved_at_41[0xf];
7316 u8 vport_number[0x10];
7317
7318 u8 reserved_at_60[0x20];
2cc43b49
MG		 7319
7320 u8 table_type[0x8];
b4ff3a36 7321 u8 reserved_at_88[0x18];
2cc43b49 7322
b4ff3a36 7323 u8 reserved_at_a0[0x8];
2cc43b49
MG		 7324 u8 table_id[0x18];
7325
b4ff3a36 7326 u8 reserved_at_c0[0x140];
2cc43b49
MG		 7327};
7328
34a40e68
MG		 7329enum {
7330 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7331};
7332
7333struct mlx5_ifc_modify_flow_table_out_bits {
7334 u8 status[0x8];
b4ff3a36 7335 u8 reserved_at_8[0x18];
34a40e68
MG		 7336
7337 u8 syndrome[0x20];
7338
b4ff3a36 7339 u8 reserved_at_40[0x40];
34a40e68
MG		 7340};
7341
7342struct mlx5_ifc_modify_flow_table_in_bits {
7343 u8 opcode[0x10];
b4ff3a36 7344 u8 reserved_at_10[0x10];
34a40e68 7345
b4ff3a36 7346 u8 reserved_at_20[0x10];
34a40e68
MG		 7347 u8 op_mod[0x10];
7348
7d5e1423
SM		 7349 u8 other_vport[0x1];
7350 u8 reserved_at_41[0xf];
7351 u8 vport_number[0x10];
34a40e68 7352
b4ff3a36 7353 u8 reserved_at_60[0x10];
34a40e68
MG		 7354 u8 modify_field_select[0x10];
7355
7356 u8 table_type[0x8];
b4ff3a36 7357 u8 reserved_at_88[0x18];
34a40e68 7358
b4ff3a36 7359 u8 reserved_at_a0[0x8];
34a40e68
MG		 7360 u8 table_id[0x18];
7361
b4ff3a36 7362 u8 reserved_at_c0[0x4];
34a40e68 7363 u8 table_miss_mode[0x4];
b4ff3a36 7364 u8 reserved_at_c8[0x18];
34a40e68 7365
b4ff3a36 7366 u8 reserved_at_e0[0x8];
34a40e68
MG		 7367 u8 table_miss_id[0x18];
7368
b4ff3a36 7369 u8 reserved_at_100[0x100];
34a40e68
MG		 7370};
7371
4f3961ee
SM		 7372struct mlx5_ifc_ets_tcn_config_reg_bits {
7373 u8 g[0x1];
7374 u8 b[0x1];
7375 u8 r[0x1];
7376 u8 reserved_at_3[0x9];
7377 u8 group[0x4];
7378 u8 reserved_at_10[0x9];
7379 u8 bw_allocation[0x7];
7380
7381 u8 reserved_at_20[0xc];
7382 u8 max_bw_units[0x4];
7383 u8 reserved_at_30[0x8];
7384 u8 max_bw_value[0x8];
7385};
7386
7387struct mlx5_ifc_ets_global_config_reg_bits {
7388 u8 reserved_at_0[0x2];
7389 u8 r[0x1];
7390 u8 reserved_at_3[0x1d];
7391
7392 u8 reserved_at_20[0xc];
7393 u8 max_bw_units[0x4];
7394 u8 reserved_at_30[0x8];
7395 u8 max_bw_value[0x8];
7396};
7397
7398struct mlx5_ifc_qetc_reg_bits {
7399 u8 reserved_at_0[0x8];
7400 u8 port_number[0x8];
7401 u8 reserved_at_10[0x30];
7402
7403 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7404 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7405};
7406
7407struct mlx5_ifc_qtct_reg_bits {
7408 u8 reserved_at_0[0x8];
7409 u8 port_number[0x8];
7410 u8 reserved_at_10[0xd];
7411 u8 prio[0x3];
7412
7413 u8 reserved_at_20[0x1d];
7414 u8 tclass[0x3];
7415};
7416
7d5e1423
SM		 7417struct mlx5_ifc_mcia_reg_bits {
7418 u8 l[0x1];
7419 u8 reserved_at_1[0x7];
7420 u8 module[0x8];
7421 u8 reserved_at_10[0x8];
7422 u8 status[0x8];
7423
7424 u8 i2c_device_address[0x8];
7425 u8 page_number[0x8];
7426 u8 device_address[0x10];
7427
7428 u8 reserved_at_40[0x10];
7429 u8 size[0x10];
7430
7431 u8 reserved_at_60[0x20];
7432
7433 u8 dword_0[0x20];
7434 u8 dword_1[0x20];
7435 u8 dword_2[0x20];
7436 u8 dword_3[0x20];
7437 u8 dword_4[0x20];
7438 u8 dword_5[0x20];
7439 u8 dword_6[0x20];
7440 u8 dword_7[0x20];
7441 u8 dword_8[0x20];
7442 u8 dword_9[0x20];
7443 u8 dword_10[0x20];
7444 u8 dword_11[0x20];
7445};
7446
d29b796a 7447#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)