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net/mlx5: Geneve, Add basic Geneve encap/decap flow table capabilities
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
66enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71};
72
f91e6d89
EBE		 73enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89
EBE		 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77};
78
38b7ca92 79enum {
2acc7957 80 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 81};
82
9fba2b9b
AL		 83enum {
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
85};
86
87enum {
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89};
90
d29b796a
EC		 91enum {
92 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
93 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
94 MLX5_CMD_OP_INIT_HCA = 0x102,
95 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
96 MLX5_CMD_OP_ENABLE_HCA = 0x104,
97 MLX5_CMD_OP_DISABLE_HCA = 0x105,
98 MLX5_CMD_OP_QUERY_PAGES = 0x107,
99 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
100 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 101 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
102 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 103 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 104 MLX5_CMD_OP_CREATE_MKEY = 0x200,
105 MLX5_CMD_OP_QUERY_MKEY = 0x201,
106 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
107 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
108 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 109 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
110 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 111 MLX5_CMD_OP_CREATE_EQ = 0x301,
112 MLX5_CMD_OP_DESTROY_EQ = 0x302,
113 MLX5_CMD_OP_QUERY_EQ = 0x303,
114 MLX5_CMD_OP_GEN_EQE = 0x304,
115 MLX5_CMD_OP_CREATE_CQ = 0x400,
116 MLX5_CMD_OP_DESTROY_CQ = 0x401,
117 MLX5_CMD_OP_QUERY_CQ = 0x402,
118 MLX5_CMD_OP_MODIFY_CQ = 0x403,
119 MLX5_CMD_OP_CREATE_QP = 0x500,
120 MLX5_CMD_OP_DESTROY_QP = 0x501,
121 MLX5_CMD_OP_RST2INIT_QP = 0x502,
122 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
123 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
124 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
125 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
126 MLX5_CMD_OP_2ERR_QP = 0x507,
127 MLX5_CMD_OP_2RST_QP = 0x50a,
128 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 129 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 130 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
131 MLX5_CMD_OP_CREATE_PSV = 0x600,
132 MLX5_CMD_OP_DESTROY_PSV = 0x601,
133 MLX5_CMD_OP_CREATE_SRQ = 0x700,
134 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
135 MLX5_CMD_OP_QUERY_SRQ = 0x702,
136 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 137 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
138 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
139 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
140 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 141 MLX5_CMD_OP_CREATE_DCT = 0x710,
142 MLX5_CMD_OP_DESTROY_DCT = 0x711,
143 MLX5_CMD_OP_DRAIN_DCT = 0x712,
144 MLX5_CMD_OP_QUERY_DCT = 0x713,
145 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 146 MLX5_CMD_OP_CREATE_XRQ = 0x717,
147 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
148 MLX5_CMD_OP_QUERY_XRQ = 0x719,
149 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 150 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
151 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
152 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
c3a4e9f1 153 MLX5_CMD_OP_QUERY_HOST_PARAMS = 0x740,
d29b796a
EC		 154 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
155 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
156 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
157 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
158 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
159 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 160 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 161 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 162 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
163 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
164 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
165 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 166 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 167 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
168 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
169 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
170 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 171 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
172 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 173 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 174 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 175 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
176 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
177 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
178 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
179 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
180 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 181 MLX5_CMD_OP_ALLOC_PD = 0x800,
182 MLX5_CMD_OP_DEALLOC_PD = 0x801,
183 MLX5_CMD_OP_ALLOC_UAR = 0x802,
184 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
185 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
186 MLX5_CMD_OP_ACCESS_REG = 0x805,
187 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 188 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 189 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
190 MLX5_CMD_OP_MAD_IFC = 0x50d,
191 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
192 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
193 MLX5_CMD_OP_NOP = 0x80d,
194 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
195 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 196 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
197 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
198 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
199 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
200 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
201 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
202 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
203 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
204 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
205 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
206 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
207 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 208 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
209 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 210 MLX5_CMD_OP_CREATE_LAG = 0x840,
211 MLX5_CMD_OP_MODIFY_LAG = 0x841,
212 MLX5_CMD_OP_QUERY_LAG = 0x842,
213 MLX5_CMD_OP_DESTROY_LAG = 0x843,
214 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
215 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 216 MLX5_CMD_OP_CREATE_TIR = 0x900,
217 MLX5_CMD_OP_MODIFY_TIR = 0x901,
218 MLX5_CMD_OP_DESTROY_TIR = 0x902,
219 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 220 MLX5_CMD_OP_CREATE_SQ = 0x904,
221 MLX5_CMD_OP_MODIFY_SQ = 0x905,
222 MLX5_CMD_OP_DESTROY_SQ = 0x906,
223 MLX5_CMD_OP_QUERY_SQ = 0x907,
224 MLX5_CMD_OP_CREATE_RQ = 0x908,
225 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 226 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 227 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
228 MLX5_CMD_OP_QUERY_RQ = 0x90b,
229 MLX5_CMD_OP_CREATE_RMP = 0x90c,
230 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
231 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
232 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 233 MLX5_CMD_OP_CREATE_TIS = 0x912,
234 MLX5_CMD_OP_MODIFY_TIS = 0x913,
235 MLX5_CMD_OP_DESTROY_TIS = 0x914,
236 MLX5_CMD_OP_QUERY_TIS = 0x915,
237 MLX5_CMD_OP_CREATE_RQT = 0x916,
238 MLX5_CMD_OP_MODIFY_RQT = 0x917,
239 MLX5_CMD_OP_DESTROY_RQT = 0x918,
240 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 241 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 242 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
243 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
244 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
245 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
246 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
247 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
248 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
249 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 250 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 251 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
252 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
253 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 254 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 255 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
256 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 257 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 258 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
259 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 260 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 261 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
262 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
263 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
264 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
265 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 266 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 267 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
268 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 269 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 270 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
271 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
272 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
273 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
86d56a1a 274 MLX5_CMD_OP_MAX
e281682b
SM		 275};
276
719598c9
YH		 277/* Valid range for general commands that don't work over an object */
278enum {
279 MLX5_CMD_OP_GENERAL_START = 0xb00,
280 MLX5_CMD_OP_GENERAL_END = 0xd00,
281};
282
e281682b
SM		 283struct mlx5_ifc_flow_table_fields_supported_bits {
284 u8 outer_dmac[0x1];
285 u8 outer_smac[0x1];
286 u8 outer_ether_type[0x1];
19cc7524 287 u8 outer_ip_version[0x1];
e281682b
SM		 288 u8 outer_first_prio[0x1];
289 u8 outer_first_cfi[0x1];
290 u8 outer_first_vid[0x1];
a8ade55f 291 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 292 u8 outer_second_prio[0x1];
293 u8 outer_second_cfi[0x1];
294 u8 outer_second_vid[0x1];
b4ff3a36 295 u8 reserved_at_b[0x1];
e281682b
SM		 296 u8 outer_sip[0x1];
297 u8 outer_dip[0x1];
298 u8 outer_frag[0x1];
299 u8 outer_ip_protocol[0x1];
300 u8 outer_ip_ecn[0x1];
301 u8 outer_ip_dscp[0x1];
302 u8 outer_udp_sport[0x1];
303 u8 outer_udp_dport[0x1];
304 u8 outer_tcp_sport[0x1];
305 u8 outer_tcp_dport[0x1];
306 u8 outer_tcp_flags[0x1];
307 u8 outer_gre_protocol[0x1];
308 u8 outer_gre_key[0x1];
309 u8 outer_vxlan_vni[0x1];
75d90e7d
YK		 310 u8 outer_geneve_vni[0x1];
311 u8 outer_geneve_oam[0x1];
312 u8 outer_geneve_protocol_type[0x1];
313 u8 outer_geneve_opt_len[0x1];
314 u8 reserved_at_1e[0x1];
e281682b
SM		 315 u8 source_eswitch_port[0x1];
316
317 u8 inner_dmac[0x1];
318 u8 inner_smac[0x1];
319 u8 inner_ether_type[0x1];
19cc7524 320 u8 inner_ip_version[0x1];
e281682b
SM		 321 u8 inner_first_prio[0x1];
322 u8 inner_first_cfi[0x1];
323 u8 inner_first_vid[0x1];
b4ff3a36 324 u8 reserved_at_27[0x1];
e281682b
SM		 325 u8 inner_second_prio[0x1];
326 u8 inner_second_cfi[0x1];
327 u8 inner_second_vid[0x1];
b4ff3a36 328 u8 reserved_at_2b[0x1];
e281682b
SM		 329 u8 inner_sip[0x1];
330 u8 inner_dip[0x1];
331 u8 inner_frag[0x1];
332 u8 inner_ip_protocol[0x1];
333 u8 inner_ip_ecn[0x1];
334 u8 inner_ip_dscp[0x1];
335 u8 inner_udp_sport[0x1];
336 u8 inner_udp_dport[0x1];
337 u8 inner_tcp_sport[0x1];
338 u8 inner_tcp_dport[0x1];
339 u8 inner_tcp_flags[0x1];
b4ff3a36 340 u8 reserved_at_37[0x9];
71c6e863
AL		 341
342 u8 reserved_at_40[0x5];
343 u8 outer_first_mpls_over_udp[0x4];
344 u8 outer_first_mpls_over_gre[0x4];
345 u8 inner_first_mpls[0x4];
346 u8 outer_first_mpls[0x4];
347 u8 reserved_at_55[0x2];
3346c487 348 u8 outer_esp_spi[0x1];
71c6e863 349 u8 reserved_at_58[0x2];
a550ddfc 350 u8 bth_dst_qp[0x1];
e281682b 351
a550ddfc 352 u8 reserved_at_5b[0x25];
e281682b
SM		 353};
354
355struct mlx5_ifc_flow_table_prop_layout_bits {
356 u8 ft_support[0x1];
9dc0b289
AV		 357 u8 reserved_at_1[0x1];
358 u8 flow_counter[0x1];
26a81453 359 u8 flow_modify_en[0x1];
2cc43b49 360 u8 modify_root[0x1];
34a40e68
MG		 361 u8 identified_miss_table_mode[0x1];
362 u8 flow_table_modify[0x1];
60786f09 363 u8 reformat[0x1];
7adbde20 364 u8 decap[0x1];
0c06897a
OG		 365 u8 reserved_at_9[0x1];
366 u8 pop_vlan[0x1];
367 u8 push_vlan[0x1];
8da6fe2a
JL		 368 u8 reserved_at_c[0x1];
369 u8 pop_vlan_2[0x1];
370 u8 push_vlan_2[0x1];
bea4e1f6 371 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 372 u8 reserved_at_10[0x1];
373 u8 sw_owner[0x1];
bea4e1f6
MB		 374 u8 reformat_l3_tunnel_to_l2[0x1];
375 u8 reformat_l2_to_l3_tunnel[0x1];
376 u8 reformat_and_modify_action[0x1];
f6f7d6b5
MG		 377 u8 reserved_at_15[0x2];
378 u8 table_miss_action_domain[0x1];
379 u8 reserved_at_18[0x8];
b4ff3a36 380 u8 reserved_at_20[0x2];
e281682b 381 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 382 u8 log_max_modify_header_context[0x8];
383 u8 max_modify_header_actions[0x8];
e281682b
SM		 384 u8 max_ft_level[0x8];
385
b4ff3a36 386 u8 reserved_at_40[0x20];
e281682b 387
b4ff3a36 388 u8 reserved_at_60[0x18];
e281682b
SM		 389 u8 log_max_ft_num[0x8];
390
b4ff3a36 391 u8 reserved_at_80[0x18];
e281682b
SM		 392 u8 log_max_destination[0x8];
393
16f1c5bb
RS		 394 u8 log_max_flow_counter[0x8];
395 u8 reserved_at_a8[0x10];
e281682b
SM		 396 u8 log_max_flow[0x8];
397
b4ff3a36 398 u8 reserved_at_c0[0x40];
e281682b
SM		 399
400 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
401
402 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
403};
404
405struct mlx5_ifc_odp_per_transport_service_cap_bits {
406 u8 send[0x1];
407 u8 receive[0x1];
408 u8 write[0x1];
409 u8 read[0x1];
17d2f88f 410 u8 atomic[0x1];
e281682b 411 u8 srq_receive[0x1];
b4ff3a36 412 u8 reserved_at_6[0x1a];
e281682b
SM		 413};
414
415struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
416 u8 smac_47_16[0x20];
417
418 u8 smac_15_0[0x10];
419 u8 ethertype[0x10];
420
421 u8 dmac_47_16[0x20];
422
423 u8 dmac_15_0[0x10];
424 u8 first_prio[0x3];
425 u8 first_cfi[0x1];
426 u8 first_vid[0xc];
427
428 u8 ip_protocol[0x8];
429 u8 ip_dscp[0x6];
430 u8 ip_ecn[0x2];
10543365
MHY		 431 u8 cvlan_tag[0x1];
432 u8 svlan_tag[0x1];
e281682b 433 u8 frag[0x1];
19cc7524 434 u8 ip_version[0x4];
e281682b
SM		 435 u8 tcp_flags[0x9];
436
437 u8 tcp_sport[0x10];
438 u8 tcp_dport[0x10];
439
a8ade55f
OG		 440 u8 reserved_at_c0[0x18];
441 u8 ttl_hoplimit[0x8];
e281682b
SM		 442
443 u8 udp_sport[0x10];
444 u8 udp_dport[0x10];
445
b4d1f032 446 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 447
b4d1f032 448 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 449};
450
5886a96a
OS		 451struct mlx5_ifc_nvgre_key_bits {
452 u8 hi[0x18];
453 u8 lo[0x8];
454};
455
456union mlx5_ifc_gre_key_bits {
457 struct mlx5_ifc_nvgre_key_bits nvgre;
458 u8 key[0x20];
459};
460
e281682b 461struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 462 u8 reserved_at_0[0x8];
463 u8 source_sqn[0x18];
e281682b 464
3e99df87 465 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 466 u8 source_port[0x10];
467
468 u8 outer_second_prio[0x3];
469 u8 outer_second_cfi[0x1];
470 u8 outer_second_vid[0xc];
471 u8 inner_second_prio[0x3];
472 u8 inner_second_cfi[0x1];
473 u8 inner_second_vid[0xc];
474
10543365
MHY		 475 u8 outer_second_cvlan_tag[0x1];
476 u8 inner_second_cvlan_tag[0x1];
477 u8 outer_second_svlan_tag[0x1];
478 u8 inner_second_svlan_tag[0x1];
479 u8 reserved_at_64[0xc];
e281682b
SM		 480 u8 gre_protocol[0x10];
481
5886a96a 482 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 483
484 u8 vxlan_vni[0x18];
b4ff3a36 485 u8 reserved_at_b8[0x8];
e281682b 486
75d90e7d
YK		 487 u8 geneve_vni[0x18];
488 u8 reserved_at_d8[0x7];
489 u8 geneve_oam[0x1];
e281682b 490
b4ff3a36 491 u8 reserved_at_e0[0xc];
e281682b
SM		 492 u8 outer_ipv6_flow_label[0x14];
493
b4ff3a36 494 u8 reserved_at_100[0xc];
e281682b
SM		 495 u8 inner_ipv6_flow_label[0x14];
496
75d90e7d
YK		 497 u8 reserved_at_120[0xa];
498 u8 geneve_opt_len[0x6];
499 u8 geneve_protocol_type[0x10];
500
501 u8 reserved_at_140[0x8];
a550ddfc 502 u8 bth_dst_qp[0x18];
3346c487
BP		 503 u8 reserved_at_160[0x20];
504 u8 outer_esp_spi[0x20];
505 u8 reserved_at_1a0[0x60];
e281682b
SM		 506};
507
71c6e863
AL		 508struct mlx5_ifc_fte_match_mpls_bits {
509 u8 mpls_label[0x14];
510 u8 mpls_exp[0x3];
511 u8 mpls_s_bos[0x1];
512 u8 mpls_ttl[0x8];
513};
514
515struct mlx5_ifc_fte_match_set_misc2_bits {
516 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
517
518 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
519
520 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
521
522 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
523
524 u8 reserved_at_80[0x100];
525
526 u8 metadata_reg_a[0x20];
527
528 u8 reserved_at_1a0[0x60];
529};
530
e281682b
SM		 531struct mlx5_ifc_cmd_pas_bits {
532 u8 pa_h[0x20];
533
534 u8 pa_l[0x14];
b4ff3a36 535 u8 reserved_at_34[0xc];
e281682b
SM		 536};
537
538struct mlx5_ifc_uint64_bits {
539 u8 hi[0x20];
540
541 u8 lo[0x20];
542};
543
544enum {
545 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
546 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
547 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
548 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
549 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
550 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
551 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
552 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
553 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
554 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
555};
556
557struct mlx5_ifc_ads_bits {
558 u8 fl[0x1];
559 u8 free_ar[0x1];
b4ff3a36 560 u8 reserved_at_2[0xe];
e281682b
SM		 561 u8 pkey_index[0x10];
562
b4ff3a36 563 u8 reserved_at_20[0x8];
e281682b
SM		 564 u8 grh[0x1];
565 u8 mlid[0x7];
566 u8 rlid[0x10];
567
568 u8 ack_timeout[0x5];
b4ff3a36 569 u8 reserved_at_45[0x3];
e281682b 570 u8 src_addr_index[0x8];
b4ff3a36 571 u8 reserved_at_50[0x4];
e281682b
SM		 572 u8 stat_rate[0x4];
573 u8 hop_limit[0x8];
574
b4ff3a36 575 u8 reserved_at_60[0x4];
e281682b
SM		 576 u8 tclass[0x8];
577 u8 flow_label[0x14];
578
579 u8 rgid_rip[16][0x8];
580
b4ff3a36 581 u8 reserved_at_100[0x4];
e281682b
SM		 582 u8 f_dscp[0x1];
583 u8 f_ecn[0x1];
b4ff3a36 584 u8 reserved_at_106[0x1];
e281682b
SM		 585 u8 f_eth_prio[0x1];
586 u8 ecn[0x2];
587 u8 dscp[0x6];
588 u8 udp_sport[0x10];
589
590 u8 dei_cfi[0x1];
591 u8 eth_prio[0x3];
592 u8 sl[0x4];
32f69e4b 593 u8 vhca_port_num[0x8];
e281682b
SM		 594 u8 rmac_47_32[0x10];
595
596 u8 rmac_31_0[0x20];
597};
598
599struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 600 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 601 u8 nic_rx_multi_path_tirs_fts[0x1];
602 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
bea4e1f6
MB		 603 u8 reserved_at_3[0x1d];
604 u8 encap_general_header[0x1];
605 u8 reserved_at_21[0xa];
606 u8 log_max_packet_reformat_context[0x5];
607 u8 reserved_at_30[0x6];
608 u8 max_encap_header_size[0xa];
609 u8 reserved_at_40[0x1c0];
e281682b
SM		 610
611 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
612
d83eb50e 613 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
e281682b
SM		 614
615 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
616
617 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
618
b4ff3a36 619 u8 reserved_at_a00[0x200];
e281682b
SM		 620
621 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
622
b4ff3a36 623 u8 reserved_at_e00[0x7200];
e281682b
SM		 624};
625
495716b1 626struct mlx5_ifc_flow_table_eswitch_cap_bits {
663f146f 627 u8 reserved_at_0[0x1a];
b9aa0ba1 628 u8 multi_fdb_encap[0x1];
663f146f
VP		 629 u8 reserved_at_1b[0x1];
630 u8 fdb_multi_path_to_table[0x1];
631 u8 reserved_at_1d[0x3];
632
633 u8 reserved_at_20[0x1e0];
495716b1
SM		 634
635 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
636
637 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
638
639 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
640
b4ff3a36 641 u8 reserved_at_800[0x7800];
495716b1
SM		 642};
643
8bb957d2
SK		 644enum {
645 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
646 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
647};
648
d6666753
SM		 649struct mlx5_ifc_e_switch_cap_bits {
650 u8 vport_svlan_strip[0x1];
651 u8 vport_cvlan_strip[0x1];
652 u8 vport_svlan_insert[0x1];
653 u8 vport_cvlan_insert_if_not_exist[0x1];
654 u8 vport_cvlan_insert_overwrite[0x1];
81cd229c
BW		 655 u8 reserved_at_5[0x16];
656 u8 ecpf_vport_exists[0x1];
8bb957d2 657 u8 counter_eswitch_affinity[0x1];
a6d04569 658 u8 merged_eswitch[0x1];
23898c76
NO		 659 u8 nic_vport_node_guid_modify[0x1];
660 u8 nic_vport_port_guid_modify[0x1];
d6666753 661
7adbde20
HHZ		 662 u8 vxlan_encap_decap[0x1];
663 u8 nvgre_encap_decap[0x1];
1b115498
EB		 664 u8 reserved_at_22[0x1];
665 u8 log_max_fdb_encap_uplink[0x5];
666 u8 reserved_at_21[0x3];
60786f09 667 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 668 u8 reserved_2b[0x6];
669 u8 max_encap_header_size[0xa];
670
671 u8 reserved_40[0x7c0];
672
d6666753
SM		 673};
674
7486216b
SM		 675struct mlx5_ifc_qos_cap_bits {
676 u8 packet_pacing[0x1];
813f8540 677 u8 esw_scheduling[0x1];
c9497c98
MHY		 678 u8 esw_bw_share[0x1];
679 u8 esw_rate_limit[0x1];
05d3ac97
BW		 680 u8 reserved_at_4[0x1];
681 u8 packet_pacing_burst_bound[0x1];
682 u8 packet_pacing_typical_size[0x1];
683 u8 reserved_at_7[0x19];
813f8540
MHY		 684
685 u8 reserved_at_20[0x20];
686
7486216b 687 u8 packet_pacing_max_rate[0x20];
813f8540 688
7486216b 689 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 690
691 u8 reserved_at_80[0x10];
7486216b 692 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 693
694 u8 esw_element_type[0x10];
695 u8 esw_tsar_type[0x10];
696
697 u8 reserved_at_c0[0x10];
698 u8 max_qos_para_vport[0x10];
699
700 u8 max_tsar_bw_share[0x20];
701
702 u8 reserved_at_100[0x700];
7486216b
SM		 703};
704
2fcb12df
IK		 705struct mlx5_ifc_debug_cap_bits {
706 u8 reserved_at_0[0x20];
707
708 u8 reserved_at_20[0x2];
709 u8 stall_detect[0x1];
710 u8 reserved_at_23[0x1d];
711
712 u8 reserved_at_40[0x7c0];
713};
714
e281682b
SM		 715struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
716 u8 csum_cap[0x1];
717 u8 vlan_cap[0x1];
718 u8 lro_cap[0x1];
719 u8 lro_psh_flag[0x1];
720 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 721 u8 reserved_at_5[0x2];
722 u8 wqe_vlan_insert[0x1];
66189961 723 u8 self_lb_en_modifiable[0x1];
b4ff3a36 724 u8 reserved_at_9[0x2];
e281682b 725 u8 max_lso_cap[0x5];
c226dc22 726 u8 multi_pkt_send_wqe[0x2];
cff92d7c 727 u8 wqe_inline_mode[0x2];
e281682b 728 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 729 u8 reg_umr_sq[0x1];
730 u8 scatter_fcs[0x1];
050da902 731 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 732 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 733 u8 reserved_at_1c[0x2];
27299841 734 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 735 u8 tunnel_stateless_vxlan[0x1];
736
547eede0
IT		 737 u8 swp[0x1];
738 u8 swp_csum[0x1];
739 u8 swp_lso[0x1];
22a65aa8
GP		 740 u8 reserved_at_23[0xd];
741 u8 max_vxlan_udp_ports[0x8];
742 u8 reserved_at_38[0x6];
4d350f1f
MG		 743 u8 max_geneve_opt_len[0x1];
744 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 745
b4ff3a36 746 u8 reserved_at_40[0x10];
e281682b
SM		 747 u8 lro_min_mss_size[0x10];
748
b4ff3a36 749 u8 reserved_at_60[0x120];
e281682b
SM		 750
751 u8 lro_timer_supported_periods[4][0x20];
752
b4ff3a36 753 u8 reserved_at_200[0x600];
e281682b
SM		 754};
755
756struct mlx5_ifc_roce_cap_bits {
757 u8 roce_apm[0x1];
b4ff3a36 758 u8 reserved_at_1[0x1f];
e281682b 759
b4ff3a36 760 u8 reserved_at_20[0x60];
e281682b 761
b4ff3a36 762 u8 reserved_at_80[0xc];
e281682b 763 u8 l3_type[0x4];
b4ff3a36 764 u8 reserved_at_90[0x8];
e281682b
SM		 765 u8 roce_version[0x8];
766
b4ff3a36 767 u8 reserved_at_a0[0x10];
e281682b
SM		 768 u8 r_roce_dest_udp_port[0x10];
769
770 u8 r_roce_max_src_udp_port[0x10];
771 u8 r_roce_min_src_udp_port[0x10];
772
b4ff3a36 773 u8 reserved_at_e0[0x10];
e281682b
SM		 774 u8 roce_address_table_size[0x10];
775
b4ff3a36 776 u8 reserved_at_100[0x700];
e281682b
SM		 777};
778
e72bd817
AL		 779struct mlx5_ifc_device_mem_cap_bits {
780 u8 memic[0x1];
781 u8 reserved_at_1[0x1f];
782
783 u8 reserved_at_20[0xb];
784 u8 log_min_memic_alloc_size[0x5];
785 u8 reserved_at_30[0x8];
786 u8 log_max_memic_addr_alignment[0x8];
787
788 u8 memic_bar_start_addr[0x40];
789
790 u8 memic_bar_size[0x20];
791
792 u8 max_memic_size[0x20];
793
9fba2b9b
AL		 794 u8 steering_sw_icm_start_address[0x40];
795
796 u8 reserved_at_100[0x8];
797 u8 log_header_modify_sw_icm_size[0x8];
798 u8 reserved_at_110[0x2];
799 u8 log_sw_icm_alloc_granularity[0x6];
800 u8 log_steering_sw_icm_size[0x8];
801
802 u8 reserved_at_120[0x20];
803
804 u8 header_modify_sw_icm_start_address[0x40];
805
806 u8 reserved_at_180[0x680];
e72bd817
AL		 807};
808
e281682b
SM		 809enum {
810 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
811 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
812 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
813 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
814 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
815 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
816 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
817 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
818 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
819};
820
821enum {
822 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
823 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
824 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
825 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
826 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
827 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
828 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
829 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
830 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
831};
832
833struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 834 u8 reserved_at_0[0x40];
e281682b 835
bd10838a 836 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 837 u8 reserved_at_42[0x4];
bd10838a 838 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 839
b4ff3a36 840 u8 reserved_at_47[0x19];
e281682b 841
b4ff3a36 842 u8 reserved_at_60[0x20];
e281682b 843
b4ff3a36 844 u8 reserved_at_80[0x10];
f91e6d89 845 u8 atomic_operations[0x10];
e281682b 846
b4ff3a36 847 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 848 u8 atomic_size_qp[0x10];
849
b4ff3a36 850 u8 reserved_at_c0[0x10];
e281682b
SM		 851 u8 atomic_size_dc[0x10];
852
b4ff3a36 853 u8 reserved_at_e0[0x720];
e281682b
SM		 854};
855
856struct mlx5_ifc_odp_cap_bits {
b4ff3a36 857 u8 reserved_at_0[0x40];
e281682b
SM		 858
859 u8 sig[0x1];
b4ff3a36 860 u8 reserved_at_41[0x1f];
e281682b 861
b4ff3a36 862 u8 reserved_at_60[0x20];
e281682b
SM		 863
864 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
865
866 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
867
868 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
869
dda7a817
MS		 870 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
871
872 u8 reserved_at_100[0x700];
e281682b
SM		 873};
874
3f0393a5
SG		 875struct mlx5_ifc_calc_op {
876 u8 reserved_at_0[0x10];
877 u8 reserved_at_10[0x9];
878 u8 op_swap_endianness[0x1];
879 u8 op_min[0x1];
880 u8 op_xor[0x1];
881 u8 op_or[0x1];
882 u8 op_and[0x1];
883 u8 op_max[0x1];
884 u8 op_add[0x1];
885};
886
887struct mlx5_ifc_vector_calc_cap_bits {
888 u8 calc_matrix[0x1];
889 u8 reserved_at_1[0x1f];
890 u8 reserved_at_20[0x8];
891 u8 max_vec_count[0x8];
892 u8 reserved_at_30[0xd];
893 u8 max_chunk_size[0x3];
894 struct mlx5_ifc_calc_op calc0;
895 struct mlx5_ifc_calc_op calc1;
896 struct mlx5_ifc_calc_op calc2;
897 struct mlx5_ifc_calc_op calc3;
898
c74d90c1 899 u8 reserved_at_c0[0x720];
3f0393a5
SG		 900};
901
e281682b
SM		 902enum {
903 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
904 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 905 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 906 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 907};
908
909enum {
910 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
911 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
912};
913
914enum {
915 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
916 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
917 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
918 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
919 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
920};
921
922enum {
923 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
924 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
925 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
926 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
927 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
928 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
929};
930
931enum {
932 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
933 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
934};
935
936enum {
937 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
938 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
939 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
940};
941
942enum {
943 MLX5_CAP_PORT_TYPE_IB = 0x0,
944 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 945};
946
1410a90a
MG		 947enum {
948 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
949 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
950 MLX5_CAP_UMR_FENCE_NONE = 0x2,
951};
952
9d43faac
YH		 953enum {
954 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 955 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 956};
957
b775516b 958struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 959 u8 reserved_at_0[0x30];
960 u8 vhca_id[0x10];
961
962 u8 reserved_at_40[0x40];
b775516b
EC		 963
964 u8 log_max_srq_sz[0x8];
965 u8 log_max_qp_sz[0x8];
316793fb
EB		 966 u8 reserved_at_90[0x8];
967 u8 prio_tag_required[0x1];
968 u8 reserved_at_99[0x2];
b775516b
EC		 969 u8 log_max_qp[0x5];
970
b4ff3a36 971 u8 reserved_at_a0[0xb];
e281682b 972 u8 log_max_srq[0x5];
b4ff3a36 973 u8 reserved_at_b0[0x10];
b775516b 974
b4ff3a36 975 u8 reserved_at_c0[0x8];
b775516b 976 u8 log_max_cq_sz[0x8];
b4ff3a36 977 u8 reserved_at_d0[0xb];
b775516b
EC		 978 u8 log_max_cq[0x5];
979
980 u8 log_max_eq_sz[0x8];
b4ff3a36 981 u8 reserved_at_e8[0x2];
b775516b 982 u8 log_max_mkey[0x6];
b183ee27
LR		 983 u8 reserved_at_f0[0x8];
984 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 985 u8 reserved_at_f9[0x2];
986 u8 fast_teardown[0x1];
b775516b
EC		 987 u8 log_max_eq[0x4];
988
989 u8 max_indirection[0x8];
bcda1aca 990 u8 fixed_buffer_size[0x1];
b775516b 991 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 992 u8 force_teardown[0x1];
993 u8 reserved_at_111[0x1];
b775516b 994 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 995 u8 umr_extended_translation_offset[0x1];
996 u8 null_mkey[0x1];
b775516b
EC		 997 u8 log_max_klm_list_size[0x6];
998
b4ff3a36 999 u8 reserved_at_120[0xa];
b775516b 1000 u8 log_max_ra_req_dc[0x6];
b4ff3a36 1001 u8 reserved_at_130[0xa];
b775516b
EC		 1002 u8 log_max_ra_res_dc[0x6];
1003
b4ff3a36 1004 u8 reserved_at_140[0xa];
b775516b 1005 u8 log_max_ra_req_qp[0x6];
b4ff3a36 1006 u8 reserved_at_150[0xa];
b775516b
EC		 1007 u8 log_max_ra_res_qp[0x6];
1008
f32f5bd2 1009 u8 end_pad[0x1];
b775516b
EC		 1010 u8 cc_query_allowed[0x1];
1011 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 1012 u8 start_pad[0x1];
1013 u8 cache_line_128byte[0x1];
c02762eb
HN		 1014 u8 reserved_at_165[0xa];
1015 u8 qcam_reg[0x1];
e281682b 1016 u8 gid_table_size[0x10];
b775516b 1017
e281682b
SM		 1018 u8 out_of_seq_cnt[0x1];
1019 u8 vport_counters[0x1];
7486216b 1020 u8 retransmission_q_counters[0x1];
2fcb12df 1021 u8 debug[0x1];
83b502a1 1022 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1023 u8 rq_delay_drop[0x1];
b775516b
EC		 1024 u8 max_qp_cnt[0xa];
1025 u8 pkey_table_size[0x10];
1026
e281682b
SM		 1027 u8 vport_group_manager[0x1];
1028 u8 vhca_group_manager[0x1];
1029 u8 ib_virt[0x1];
1030 u8 eth_virt[0x1];
61c5b5c9 1031 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1032 u8 ets[0x1];
1033 u8 nic_flow_table[0x1];
0efc8562 1034 u8 eswitch_manager[0x1];
e72bd817 1035 u8 device_memory[0x1];
cfdcbcea
GP		 1036 u8 mcam_reg[0x1];
1037 u8 pcam_reg[0x1];
b775516b 1038 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1039 u8 port_module_event[0x1];
58dcb60a 1040 u8 enhanced_error_q_counters[0x1];
7d5e1423 1041 u8 ports_check[0x1];
7b13558f 1042 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1043 u8 disable_link_up[0x1];
1044 u8 beacon_led[0x1];
e281682b 1045 u8 port_type[0x2];
b775516b
EC		 1046 u8 num_ports[0x8];
1047
f9a1ef72
EE		 1048 u8 reserved_at_1c0[0x1];
1049 u8 pps[0x1];
1050 u8 pps_modify[0x1];
b775516b 1051 u8 log_max_msg[0x5];
e1c9c62b 1052 u8 reserved_at_1c8[0x4];
4f3961ee 1053 u8 max_tc[0x4];
1865ea9a 1054 u8 temp_warn_event[0x1];
7486216b 1055 u8 dcbx[0x1];
246ac981
MG		 1056 u8 general_notification_event[0x1];
1057 u8 reserved_at_1d3[0x2];
e29341fb 1058 u8 fpga[0x1];
928cfe87
TT		 1059 u8 rol_s[0x1];
1060 u8 rol_g[0x1];
e1c9c62b 1061 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1062 u8 wol_s[0x1];
1063 u8 wol_g[0x1];
1064 u8 wol_a[0x1];
1065 u8 wol_b[0x1];
1066 u8 wol_m[0x1];
1067 u8 wol_u[0x1];
1068 u8 wol_p[0x1];
b775516b
EC		 1069
1070 u8 stat_rate_support[0x10];
e1c9c62b 1071 u8 reserved_at_1f0[0xc];
e281682b 1072 u8 cqe_version[0x4];
b775516b 1073
e281682b 1074 u8 compact_address_vector[0x1];
7d5e1423 1075 u8 striding_rq[0x1];
500a3d0d
ES		 1076 u8 reserved_at_202[0x1];
1077 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1078 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1079 u8 reserved_at_205[0x1];
1080 u8 repeated_block_disabled[0x1];
1081 u8 umr_modify_entity_size_disabled[0x1];
1082 u8 umr_modify_atomic_disabled[0x1];
1083 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1084 u8 umr_fence[0x2];
94a04d1d
YC		 1085 u8 dc_req_scat_data_cqe[0x1];
1086 u8 reserved_at_20d[0x2];
e281682b 1087 u8 drain_sigerr[0x1];
b775516b
EC		 1088 u8 cmdif_checksum[0x2];
1089 u8 sigerr_cqe[0x1];
e1c9c62b 1090 u8 reserved_at_213[0x1];
b775516b
EC		 1091 u8 wq_signature[0x1];
1092 u8 sctr_data_cqe[0x1];
e1c9c62b 1093 u8 reserved_at_216[0x1];
b775516b
EC		 1094 u8 sho[0x1];
1095 u8 tph[0x1];
1096 u8 rf[0x1];
e281682b 1097 u8 dct[0x1];
7486216b 1098 u8 qos[0x1];
e281682b 1099 u8 eth_net_offloads[0x1];
b775516b
EC		 1100 u8 roce[0x1];
1101 u8 atomic[0x1];
e1c9c62b 1102 u8 reserved_at_21f[0x1];
b775516b
EC		 1103
1104 u8 cq_oi[0x1];
1105 u8 cq_resize[0x1];
1106 u8 cq_moderation[0x1];
e1c9c62b 1107 u8 reserved_at_223[0x3];
e281682b 1108 u8 cq_eq_remap[0x1];
b775516b
EC		 1109 u8 pg[0x1];
1110 u8 block_lb_mc[0x1];
e1c9c62b 1111 u8 reserved_at_229[0x1];
e281682b 1112 u8 scqe_break_moderation[0x1];
7d5e1423 1113 u8 cq_period_start_from_cqe[0x1];
b775516b 1114 u8 cd[0x1];
e1c9c62b 1115 u8 reserved_at_22d[0x1];
b775516b 1116 u8 apm[0x1];
3f0393a5 1117 u8 vector_calc[0x1];
7d5e1423 1118 u8 umr_ptr_rlky[0x1];
d2370e0a 1119 u8 imaicl[0x1];
3fd3c80a
DG		 1120 u8 qp_packet_based[0x1];
1121 u8 reserved_at_233[0x3];
b775516b
EC		 1122 u8 qkv[0x1];
1123 u8 pkv[0x1];
b11a4f9c
HE		 1124 u8 set_deth_sqpn[0x1];
1125 u8 reserved_at_239[0x3];
b775516b
EC		 1126 u8 xrc[0x1];
1127 u8 ud[0x1];
1128 u8 uc[0x1];
1129 u8 rc[0x1];
1130
a6d51b68
EC		 1131 u8 uar_4k[0x1];
1132 u8 reserved_at_241[0x9];
b775516b 1133 u8 uar_sz[0x6];
e1c9c62b 1134 u8 reserved_at_250[0x8];
b775516b
EC		 1135 u8 log_pg_sz[0x8];
1136
1137 u8 bf[0x1];
0dbc6fe0 1138 u8 driver_version[0x1];
e281682b 1139 u8 pad_tx_eth_packet[0x1];
e1c9c62b 1140 u8 reserved_at_263[0x8];
b775516b 1141 u8 log_bf_reg_size[0x5];
84df61eb
AH		 1142
1143 u8 reserved_at_270[0xb];
1144 u8 lag_master[0x1];
1145 u8 num_lag_ports[0x4];
b775516b 1146
e1c9c62b 1147 u8 reserved_at_280[0x10];
b775516b
EC		 1148 u8 max_wqe_sz_sq[0x10];
1149
e1c9c62b 1150 u8 reserved_at_2a0[0x10];
b775516b
EC		 1151 u8 max_wqe_sz_rq[0x10];
1152
a8ffcc74 1153 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1154 u8 max_wqe_sz_sq_dc[0x10];
1155
e1c9c62b 1156 u8 reserved_at_2e0[0x7];
b775516b
EC		 1157 u8 max_qp_mcg[0x19];
1158
e1c9c62b 1159 u8 reserved_at_300[0x18];
b775516b
EC		 1160 u8 log_max_mcg[0x8];
1161
e1c9c62b 1162 u8 reserved_at_320[0x3];
e281682b 1163 u8 log_max_transport_domain[0x5];
e1c9c62b 1164 u8 reserved_at_328[0x3];
b775516b 1165 u8 log_max_pd[0x5];
e1c9c62b 1166 u8 reserved_at_330[0xb];
b775516b
EC		 1167 u8 log_max_xrcd[0x5];
1168
5c298143 1169 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1170 u8 receive_discard_vport_down[0x1];
1171 u8 transmit_discard_vport_down[0x1];
1172 u8 reserved_at_343[0x5];
a351a1b0 1173 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1174 u8 max_flow_counter_15_0[0x10];
a351a1b0 1175
b775516b 1176
e1c9c62b 1177 u8 reserved_at_360[0x3];
b775516b 1178 u8 log_max_rq[0x5];
e1c9c62b 1179 u8 reserved_at_368[0x3];
b775516b 1180 u8 log_max_sq[0x5];
e1c9c62b 1181 u8 reserved_at_370[0x3];
b775516b 1182 u8 log_max_tir[0x5];
e1c9c62b 1183 u8 reserved_at_378[0x3];
b775516b
EC		 1184 u8 log_max_tis[0x5];
1185
e281682b 1186 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1187 u8 reserved_at_381[0x2];
e281682b 1188 u8 log_max_rmp[0x5];
e1c9c62b 1189 u8 reserved_at_388[0x3];
e281682b 1190 u8 log_max_rqt[0x5];
e1c9c62b 1191 u8 reserved_at_390[0x3];
e281682b 1192 u8 log_max_rqt_size[0x5];
e1c9c62b 1193 u8 reserved_at_398[0x3];
b775516b
EC		 1194 u8 log_max_tis_per_sq[0x5];
1195
619a8f2a
TT		 1196 u8 ext_stride_num_range[0x1];
1197 u8 reserved_at_3a1[0x2];
e281682b 1198 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1199 u8 reserved_at_3a8[0x3];
e281682b 1200 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1201 u8 reserved_at_3b0[0x3];
e281682b 1202 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1203 u8 reserved_at_3b8[0x3];
e281682b
SM		 1204 u8 log_min_stride_sz_sq[0x5];
1205
40817cdb
OG		 1206 u8 hairpin[0x1];
1207 u8 reserved_at_3c1[0x2];
1208 u8 log_max_hairpin_queues[0x5];
1209 u8 reserved_at_3c8[0x3];
1210 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1211 u8 reserved_at_3d0[0x3];
1212 u8 log_max_hairpin_num_packets[0x5];
1213 u8 reserved_at_3d8[0x3];
e281682b
SM		 1214 u8 log_max_wq_sz[0x5];
1215
54f0a411 1216 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1217 u8 disable_local_lb_uc[0x1];
1218 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1219 u8 log_min_hairpin_wq_data_sz[0x5];
1220 u8 reserved_at_3e8[0x3];
54f0a411 1221 u8 log_max_vlan_list[0x5];
e1c9c62b 1222 u8 reserved_at_3f0[0x3];
54f0a411 1223 u8 log_max_current_mc_list[0x5];
e1c9c62b 1224 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1225 u8 log_max_current_uc_list[0x5];
1226
38b7ca92
YH		 1227 u8 general_obj_types[0x40];
1228
342ac844
DD		 1229 u8 reserved_at_440[0x20];
1230
6e3722ba
YH		 1231 u8 reserved_at_460[0x3];
1232 u8 log_max_uctx[0x5];
1233 u8 reserved_at_468[0x3];
1234 u8 log_max_umem[0x5];
342ac844 1235 u8 max_num_eqs[0x10];
54f0a411 1236
e1c9c62b 1237 u8 reserved_at_480[0x3];
e281682b 1238 u8 log_max_l2_table[0x5];
e1c9c62b 1239 u8 reserved_at_488[0x8];
b775516b
EC		 1240 u8 log_uar_page_sz[0x10];
1241
e1c9c62b 1242 u8 reserved_at_4a0[0x20];
048ccca8 1243 u8 device_frequency_mhz[0x20];
b0844444 1244 u8 device_frequency_khz[0x20];
e1c9c62b 1245
a6d51b68
EC		 1246 u8 reserved_at_500[0x20];
1247 u8 num_of_uars_per_page[0x20];
e1c9c62b 1248
e818e255
AL		 1249 u8 flex_parser_protocols[0x20];
1250 u8 reserved_at_560[0x20];
e1c9c62b 1251
ab741b2e
YC		 1252 u8 reserved_at_580[0x3c];
1253 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1254 u8 cqe_128_always[0x1];
1255 u8 cqe_compression_128[0x1];
7d5e1423 1256 u8 cqe_compression[0x1];
b775516b 1257
7d5e1423
SM		 1258 u8 cqe_compression_timeout[0x10];
1259 u8 cqe_compression_max_num[0x10];
b775516b 1260
7486216b
SM		 1261 u8 reserved_at_5e0[0x10];
1262 u8 tag_matching[0x1];
1263 u8 rndv_offload_rc[0x1];
1264 u8 rndv_offload_dc[0x1];
1265 u8 log_tag_matching_list_sz[0x5];
7b13558f 1266 u8 reserved_at_5f8[0x3];
7486216b
SM		 1267 u8 log_max_xrq[0x5];
1268
32f69e4b
DJ		 1269 u8 affiliate_nic_vport_criteria[0x8];
1270 u8 native_port_num[0x8];
1271 u8 num_vhca_ports[0x8];
1272 u8 reserved_at_618[0x6];
1273 u8 sw_owner_id[0x1];
9d43faac
YH		 1274 u8 reserved_at_61f[0x1];
1275
fd4572b3
ED		 1276 u8 max_num_of_monitor_counters[0x10];
1277 u8 num_ppcnt_monitor_counters[0x10];
1278
1279 u8 reserved_at_640[0x10];
1280 u8 num_q_monitor_counters[0x10];
1281
1282 u8 reserved_at_660[0x40];
9d43faac
YH		 1283
1284 u8 uctx_cap[0x20];
1285
1286 u8 reserved_at_6c0[0x140];
b775516b
EC		 1287};
1288
81848731
SM		 1289enum mlx5_flow_destination_type {
1290 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1291 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1292 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1293
5f418378 1294 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1295 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
664000b6 1296 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
e281682b 1297};
b775516b 1298
f6f7d6b5
MG		 1299enum mlx5_flow_table_miss_action {
1300 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1301 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1302 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1303};
1304
e281682b
SM		 1305struct mlx5_ifc_dest_format_struct_bits {
1306 u8 destination_type[0x8];
1307 u8 destination_id[0x18];
1b115498 1308
b17f7fc1 1309 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1310 u8 packet_reformat[0x1];
1311 u8 reserved_at_22[0xe];
b17f7fc1 1312 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1313};
1314
9dc0b289 1315struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1316 u8 flow_counter_id[0x20];
9dc0b289
AV		 1317
1318 u8 reserved_at_20[0x20];
1319};
1320
1b115498
EB		 1321struct mlx5_ifc_extended_dest_format_bits {
1322 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1323
1324 u8 packet_reformat_id[0x20];
1325
1326 u8 reserved_at_60[0x20];
1327};
1328
9dc0b289
AV		 1329union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1330 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1331 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1332 u8 reserved_at_0[0x40];
1333};
1334
e281682b
SM		 1335struct mlx5_ifc_fte_match_param_bits {
1336 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1337
1338 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1339
1340 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1341
71c6e863
AL		 1342 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1343
1344 u8 reserved_at_800[0x800];
b775516b
EC		 1345};
1346
e281682b
SM		 1347enum {
1348 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1349 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1350 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1351 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1352 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1353};
b775516b 1354
e281682b
SM		 1355struct mlx5_ifc_rx_hash_field_select_bits {
1356 u8 l3_prot_type[0x1];
1357 u8 l4_prot_type[0x1];
1358 u8 selected_fields[0x1e];
1359};
b775516b 1360
e281682b
SM		 1361enum {
1362 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1363 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1364};
1365
e281682b
SM		 1366enum {
1367 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1368 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1369};
1370
1371struct mlx5_ifc_wq_bits {
1372 u8 wq_type[0x4];
1373 u8 wq_signature[0x1];
1374 u8 end_padding_mode[0x2];
1375 u8 cd_slave[0x1];
b4ff3a36 1376 u8 reserved_at_8[0x18];
b775516b 1377
e281682b
SM		 1378 u8 hds_skip_first_sge[0x1];
1379 u8 log2_hds_buf_size[0x3];
b4ff3a36 1380 u8 reserved_at_24[0x7];
e281682b
SM		 1381 u8 page_offset[0x5];
1382 u8 lwm[0x10];
b775516b 1383
b4ff3a36 1384 u8 reserved_at_40[0x8];
e281682b
SM		 1385 u8 pd[0x18];
1386
b4ff3a36 1387 u8 reserved_at_60[0x8];
e281682b
SM		 1388 u8 uar_page[0x18];
1389
1390 u8 dbr_addr[0x40];
1391
1392 u8 hw_counter[0x20];
1393
1394 u8 sw_counter[0x20];
1395
b4ff3a36 1396 u8 reserved_at_100[0xc];
e281682b 1397 u8 log_wq_stride[0x4];
b4ff3a36 1398 u8 reserved_at_110[0x3];
e281682b 1399 u8 log_wq_pg_sz[0x5];
b4ff3a36 1400 u8 reserved_at_118[0x3];
e281682b
SM		 1401 u8 log_wq_sz[0x5];
1402
bd371975
LR		 1403 u8 dbr_umem_valid[0x1];
1404 u8 wq_umem_valid[0x1];
1405 u8 reserved_at_122[0x1];
4d533e0f
OG		 1406 u8 log_hairpin_num_packets[0x5];
1407 u8 reserved_at_128[0x3];
40817cdb 1408 u8 log_hairpin_data_sz[0x5];
40817cdb 1409
619a8f2a
TT		 1410 u8 reserved_at_130[0x4];
1411 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1412 u8 two_byte_shift_en[0x1];
1413 u8 reserved_at_139[0x4];
1414 u8 log_wqe_stride_size[0x3];
1415
1416 u8 reserved_at_140[0x4c0];
b775516b 1417
e281682b 1418 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1419};
1420
e281682b 1421struct mlx5_ifc_rq_num_bits {
b4ff3a36 1422 u8 reserved_at_0[0x8];
e281682b
SM		 1423 u8 rq_num[0x18];
1424};
b775516b 1425
e281682b 1426struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1427 u8 reserved_at_0[0x10];
e281682b 1428 u8 mac_addr_47_32[0x10];
b775516b 1429
e281682b
SM		 1430 u8 mac_addr_31_0[0x20];
1431};
1432
c0046cf7 1433struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1434 u8 reserved_at_0[0x14];
c0046cf7
SM		 1435 u8 vlan[0x0c];
1436
b4ff3a36 1437 u8 reserved_at_20[0x20];
c0046cf7
SM		 1438};
1439
e281682b 1440struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1441 u8 reserved_at_0[0xa0];
e281682b
SM		 1442
1443 u8 min_time_between_cnps[0x20];
1444
b4ff3a36 1445 u8 reserved_at_c0[0x12];
e281682b 1446 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1447 u8 reserved_at_d8[0x4];
1448 u8 cnp_prio_mode[0x1];
e281682b
SM		 1449 u8 cnp_802p_prio[0x3];
1450
b4ff3a36 1451 u8 reserved_at_e0[0x720];
e281682b
SM		 1452};
1453
1454struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1455 u8 reserved_at_0[0x60];
e281682b 1456
b4ff3a36 1457 u8 reserved_at_60[0x4];
e281682b 1458 u8 clamp_tgt_rate[0x1];
b4ff3a36 1459 u8 reserved_at_65[0x3];
e281682b 1460 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1461 u8 reserved_at_69[0x17];
e281682b 1462
b4ff3a36 1463 u8 reserved_at_80[0x20];
e281682b
SM		 1464
1465 u8 rpg_time_reset[0x20];
1466
1467 u8 rpg_byte_reset[0x20];
1468
1469 u8 rpg_threshold[0x20];
1470
1471 u8 rpg_max_rate[0x20];
1472
1473 u8 rpg_ai_rate[0x20];
1474
1475 u8 rpg_hai_rate[0x20];
1476
1477 u8 rpg_gd[0x20];
1478
1479 u8 rpg_min_dec_fac[0x20];
1480
1481 u8 rpg_min_rate[0x20];
1482
b4ff3a36 1483 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1484
1485 u8 rate_to_set_on_first_cnp[0x20];
1486
1487 u8 dce_tcp_g[0x20];
1488
1489 u8 dce_tcp_rtt[0x20];
1490
1491 u8 rate_reduce_monitor_period[0x20];
1492
b4ff3a36 1493 u8 reserved_at_320[0x20];
e281682b
SM		 1494
1495 u8 initial_alpha_value[0x20];
1496
b4ff3a36 1497 u8 reserved_at_360[0x4a0];
e281682b
SM		 1498};
1499
1500struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1501 u8 reserved_at_0[0x80];
e281682b
SM		 1502
1503 u8 rppp_max_rps[0x20];
1504
1505 u8 rpg_time_reset[0x20];
1506
1507 u8 rpg_byte_reset[0x20];
1508
1509 u8 rpg_threshold[0x20];
1510
1511 u8 rpg_max_rate[0x20];
1512
1513 u8 rpg_ai_rate[0x20];
1514
1515 u8 rpg_hai_rate[0x20];
1516
1517 u8 rpg_gd[0x20];
1518
1519 u8 rpg_min_dec_fac[0x20];
1520
1521 u8 rpg_min_rate[0x20];
1522
b4ff3a36 1523 u8 reserved_at_1c0[0x640];
e281682b
SM		 1524};
1525
1526enum {
1527 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1528 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1529 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1530};
1531
1532struct mlx5_ifc_resize_field_select_bits {
1533 u8 resize_field_select[0x20];
1534};
1535
1536enum {
1537 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1538 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1539 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1540 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1541};
1542
1543struct mlx5_ifc_modify_field_select_bits {
1544 u8 modify_field_select[0x20];
1545};
1546
1547struct mlx5_ifc_field_select_r_roce_np_bits {
1548 u8 field_select_r_roce_np[0x20];
1549};
1550
1551struct mlx5_ifc_field_select_r_roce_rp_bits {
1552 u8 field_select_r_roce_rp[0x20];
1553};
1554
1555enum {
1556 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1557 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1558 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1559 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1560 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1561 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1562 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1563 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1564 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1565 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1566};
1567
1568struct mlx5_ifc_field_select_802_1qau_rp_bits {
1569 u8 field_select_8021qaurp[0x20];
1570};
1571
1572struct mlx5_ifc_phys_layer_cntrs_bits {
1573 u8 time_since_last_clear_high[0x20];
1574
1575 u8 time_since_last_clear_low[0x20];
1576
1577 u8 symbol_errors_high[0x20];
1578
1579 u8 symbol_errors_low[0x20];
1580
1581 u8 sync_headers_errors_high[0x20];
1582
1583 u8 sync_headers_errors_low[0x20];
1584
1585 u8 edpl_bip_errors_lane0_high[0x20];
1586
1587 u8 edpl_bip_errors_lane0_low[0x20];
1588
1589 u8 edpl_bip_errors_lane1_high[0x20];
1590
1591 u8 edpl_bip_errors_lane1_low[0x20];
1592
1593 u8 edpl_bip_errors_lane2_high[0x20];
1594
1595 u8 edpl_bip_errors_lane2_low[0x20];
1596
1597 u8 edpl_bip_errors_lane3_high[0x20];
1598
1599 u8 edpl_bip_errors_lane3_low[0x20];
1600
1601 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1602
1603 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1604
1605 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1606
1607 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1608
1609 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1610
1611 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1612
1613 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1614
1615 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1616
1617 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1618
1619 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1620
1621 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1622
1623 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1624
1625 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1626
1627 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1628
1629 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1630
1631 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1632
1633 u8 rs_fec_corrected_blocks_high[0x20];
1634
1635 u8 rs_fec_corrected_blocks_low[0x20];
1636
1637 u8 rs_fec_uncorrectable_blocks_high[0x20];
1638
1639 u8 rs_fec_uncorrectable_blocks_low[0x20];
1640
1641 u8 rs_fec_no_errors_blocks_high[0x20];
1642
1643 u8 rs_fec_no_errors_blocks_low[0x20];
1644
1645 u8 rs_fec_single_error_blocks_high[0x20];
1646
1647 u8 rs_fec_single_error_blocks_low[0x20];
1648
1649 u8 rs_fec_corrected_symbols_total_high[0x20];
1650
1651 u8 rs_fec_corrected_symbols_total_low[0x20];
1652
1653 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1654
1655 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1656
1657 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1658
1659 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1660
1661 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1662
1663 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1664
1665 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1666
1667 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1668
1669 u8 link_down_events[0x20];
1670
1671 u8 successful_recovery_events[0x20];
1672
b4ff3a36 1673 u8 reserved_at_640[0x180];
e281682b
SM		 1674};
1675
d8dc0508
GP		 1676struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1677 u8 time_since_last_clear_high[0x20];
1678
1679 u8 time_since_last_clear_low[0x20];
1680
1681 u8 phy_received_bits_high[0x20];
1682
1683 u8 phy_received_bits_low[0x20];
1684
1685 u8 phy_symbol_errors_high[0x20];
1686
1687 u8 phy_symbol_errors_low[0x20];
1688
1689 u8 phy_corrected_bits_high[0x20];
1690
1691 u8 phy_corrected_bits_low[0x20];
1692
1693 u8 phy_corrected_bits_lane0_high[0x20];
1694
1695 u8 phy_corrected_bits_lane0_low[0x20];
1696
1697 u8 phy_corrected_bits_lane1_high[0x20];
1698
1699 u8 phy_corrected_bits_lane1_low[0x20];
1700
1701 u8 phy_corrected_bits_lane2_high[0x20];
1702
1703 u8 phy_corrected_bits_lane2_low[0x20];
1704
1705 u8 phy_corrected_bits_lane3_high[0x20];
1706
1707 u8 phy_corrected_bits_lane3_low[0x20];
1708
1709 u8 reserved_at_200[0x5c0];
1710};
1711
1c64bf6f
MY		 1712struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1713 u8 symbol_error_counter[0x10];
1714
1715 u8 link_error_recovery_counter[0x8];
1716
1717 u8 link_downed_counter[0x8];
1718
1719 u8 port_rcv_errors[0x10];
1720
1721 u8 port_rcv_remote_physical_errors[0x10];
1722
1723 u8 port_rcv_switch_relay_errors[0x10];
1724
1725 u8 port_xmit_discards[0x10];
1726
1727 u8 port_xmit_constraint_errors[0x8];
1728
1729 u8 port_rcv_constraint_errors[0x8];
1730
1731 u8 reserved_at_70[0x8];
1732
1733 u8 link_overrun_errors[0x8];
1734
1735 u8 reserved_at_80[0x10];
1736
1737 u8 vl_15_dropped[0x10];
1738
133bea04
TW		 1739 u8 reserved_at_a0[0x80];
1740
1741 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1742};
1743
e281682b
SM		 1744struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1745 u8 transmit_queue_high[0x20];
1746
1747 u8 transmit_queue_low[0x20];
1748
b4ff3a36 1749 u8 reserved_at_40[0x780];
e281682b
SM		 1750};
1751
1752struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1753 u8 rx_octets_high[0x20];
1754
1755 u8 rx_octets_low[0x20];
1756
b4ff3a36 1757 u8 reserved_at_40[0xc0];
e281682b
SM		 1758
1759 u8 rx_frames_high[0x20];
1760
1761 u8 rx_frames_low[0x20];
1762
1763 u8 tx_octets_high[0x20];
1764
1765 u8 tx_octets_low[0x20];
1766
b4ff3a36 1767 u8 reserved_at_180[0xc0];
e281682b
SM		 1768
1769 u8 tx_frames_high[0x20];
1770
1771 u8 tx_frames_low[0x20];
1772
1773 u8 rx_pause_high[0x20];
1774
1775 u8 rx_pause_low[0x20];
1776
1777 u8 rx_pause_duration_high[0x20];
1778
1779 u8 rx_pause_duration_low[0x20];
1780
1781 u8 tx_pause_high[0x20];
1782
1783 u8 tx_pause_low[0x20];
1784
1785 u8 tx_pause_duration_high[0x20];
1786
1787 u8 tx_pause_duration_low[0x20];
1788
1789 u8 rx_pause_transition_high[0x20];
1790
1791 u8 rx_pause_transition_low[0x20];
1792
2fcb12df
IK		 1793 u8 reserved_at_3c0[0x40];
1794
1795 u8 device_stall_minor_watermark_cnt_high[0x20];
1796
1797 u8 device_stall_minor_watermark_cnt_low[0x20];
1798
1799 u8 device_stall_critical_watermark_cnt_high[0x20];
1800
1801 u8 device_stall_critical_watermark_cnt_low[0x20];
1802
1803 u8 reserved_at_480[0x340];
e281682b
SM		 1804};
1805
1806struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1807 u8 port_transmit_wait_high[0x20];
1808
1809 u8 port_transmit_wait_low[0x20];
1810
2dba0797
GP		 1811 u8 reserved_at_40[0x100];
1812
1813 u8 rx_buffer_almost_full_high[0x20];
1814
1815 u8 rx_buffer_almost_full_low[0x20];
1816
1817 u8 rx_buffer_full_high[0x20];
1818
1819 u8 rx_buffer_full_low[0x20];
1820
0af5107c
TB		 1821 u8 rx_icrc_encapsulated_high[0x20];
1822
1823 u8 rx_icrc_encapsulated_low[0x20];
1824
1825 u8 reserved_at_200[0x5c0];
e281682b
SM		 1826};
1827
1828struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1829 u8 dot3stats_alignment_errors_high[0x20];
1830
1831 u8 dot3stats_alignment_errors_low[0x20];
1832
1833 u8 dot3stats_fcs_errors_high[0x20];
1834
1835 u8 dot3stats_fcs_errors_low[0x20];
1836
1837 u8 dot3stats_single_collision_frames_high[0x20];
1838
1839 u8 dot3stats_single_collision_frames_low[0x20];
1840
1841 u8 dot3stats_multiple_collision_frames_high[0x20];
1842
1843 u8 dot3stats_multiple_collision_frames_low[0x20];
1844
1845 u8 dot3stats_sqe_test_errors_high[0x20];
1846
1847 u8 dot3stats_sqe_test_errors_low[0x20];
1848
1849 u8 dot3stats_deferred_transmissions_high[0x20];
1850
1851 u8 dot3stats_deferred_transmissions_low[0x20];
1852
1853 u8 dot3stats_late_collisions_high[0x20];
1854
1855 u8 dot3stats_late_collisions_low[0x20];
1856
1857 u8 dot3stats_excessive_collisions_high[0x20];
1858
1859 u8 dot3stats_excessive_collisions_low[0x20];
1860
1861 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1862
1863 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1864
1865 u8 dot3stats_carrier_sense_errors_high[0x20];
1866
1867 u8 dot3stats_carrier_sense_errors_low[0x20];
1868
1869 u8 dot3stats_frame_too_longs_high[0x20];
1870
1871 u8 dot3stats_frame_too_longs_low[0x20];
1872
1873 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1874
1875 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1876
1877 u8 dot3stats_symbol_errors_high[0x20];
1878
1879 u8 dot3stats_symbol_errors_low[0x20];
1880
1881 u8 dot3control_in_unknown_opcodes_high[0x20];
1882
1883 u8 dot3control_in_unknown_opcodes_low[0x20];
1884
1885 u8 dot3in_pause_frames_high[0x20];
1886
1887 u8 dot3in_pause_frames_low[0x20];
1888
1889 u8 dot3out_pause_frames_high[0x20];
1890
1891 u8 dot3out_pause_frames_low[0x20];
1892
b4ff3a36 1893 u8 reserved_at_400[0x3c0];
e281682b
SM		 1894};
1895
1896struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1897 u8 ether_stats_drop_events_high[0x20];
1898
1899 u8 ether_stats_drop_events_low[0x20];
1900
1901 u8 ether_stats_octets_high[0x20];
1902
1903 u8 ether_stats_octets_low[0x20];
1904
1905 u8 ether_stats_pkts_high[0x20];
1906
1907 u8 ether_stats_pkts_low[0x20];
1908
1909 u8 ether_stats_broadcast_pkts_high[0x20];
1910
1911 u8 ether_stats_broadcast_pkts_low[0x20];
1912
1913 u8 ether_stats_multicast_pkts_high[0x20];
1914
1915 u8 ether_stats_multicast_pkts_low[0x20];
1916
1917 u8 ether_stats_crc_align_errors_high[0x20];
1918
1919 u8 ether_stats_crc_align_errors_low[0x20];
1920
1921 u8 ether_stats_undersize_pkts_high[0x20];
1922
1923 u8 ether_stats_undersize_pkts_low[0x20];
1924
1925 u8 ether_stats_oversize_pkts_high[0x20];
1926
1927 u8 ether_stats_oversize_pkts_low[0x20];
1928
1929 u8 ether_stats_fragments_high[0x20];
1930
1931 u8 ether_stats_fragments_low[0x20];
1932
1933 u8 ether_stats_jabbers_high[0x20];
1934
1935 u8 ether_stats_jabbers_low[0x20];
1936
1937 u8 ether_stats_collisions_high[0x20];
1938
1939 u8 ether_stats_collisions_low[0x20];
1940
1941 u8 ether_stats_pkts64octets_high[0x20];
1942
1943 u8 ether_stats_pkts64octets_low[0x20];
1944
1945 u8 ether_stats_pkts65to127octets_high[0x20];
1946
1947 u8 ether_stats_pkts65to127octets_low[0x20];
1948
1949 u8 ether_stats_pkts128to255octets_high[0x20];
1950
1951 u8 ether_stats_pkts128to255octets_low[0x20];
1952
1953 u8 ether_stats_pkts256to511octets_high[0x20];
1954
1955 u8 ether_stats_pkts256to511octets_low[0x20];
1956
1957 u8 ether_stats_pkts512to1023octets_high[0x20];
1958
1959 u8 ether_stats_pkts512to1023octets_low[0x20];
1960
1961 u8 ether_stats_pkts1024to1518octets_high[0x20];
1962
1963 u8 ether_stats_pkts1024to1518octets_low[0x20];
1964
1965 u8 ether_stats_pkts1519to2047octets_high[0x20];
1966
1967 u8 ether_stats_pkts1519to2047octets_low[0x20];
1968
1969 u8 ether_stats_pkts2048to4095octets_high[0x20];
1970
1971 u8 ether_stats_pkts2048to4095octets_low[0x20];
1972
1973 u8 ether_stats_pkts4096to8191octets_high[0x20];
1974
1975 u8 ether_stats_pkts4096to8191octets_low[0x20];
1976
1977 u8 ether_stats_pkts8192to10239octets_high[0x20];
1978
1979 u8 ether_stats_pkts8192to10239octets_low[0x20];
1980
b4ff3a36 1981 u8 reserved_at_540[0x280];
e281682b
SM		 1982};
1983
1984struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1985 u8 if_in_octets_high[0x20];
1986
1987 u8 if_in_octets_low[0x20];
1988
1989 u8 if_in_ucast_pkts_high[0x20];
1990
1991 u8 if_in_ucast_pkts_low[0x20];
1992
1993 u8 if_in_discards_high[0x20];
1994
1995 u8 if_in_discards_low[0x20];
1996
1997 u8 if_in_errors_high[0x20];
1998
1999 u8 if_in_errors_low[0x20];
2000
2001 u8 if_in_unknown_protos_high[0x20];
2002
2003 u8 if_in_unknown_protos_low[0x20];
2004
2005 u8 if_out_octets_high[0x20];
2006
2007 u8 if_out_octets_low[0x20];
2008
2009 u8 if_out_ucast_pkts_high[0x20];
2010
2011 u8 if_out_ucast_pkts_low[0x20];
2012
2013 u8 if_out_discards_high[0x20];
2014
2015 u8 if_out_discards_low[0x20];
2016
2017 u8 if_out_errors_high[0x20];
2018
2019 u8 if_out_errors_low[0x20];
2020
2021 u8 if_in_multicast_pkts_high[0x20];
2022
2023 u8 if_in_multicast_pkts_low[0x20];
2024
2025 u8 if_in_broadcast_pkts_high[0x20];
2026
2027 u8 if_in_broadcast_pkts_low[0x20];
2028
2029 u8 if_out_multicast_pkts_high[0x20];
2030
2031 u8 if_out_multicast_pkts_low[0x20];
2032
2033 u8 if_out_broadcast_pkts_high[0x20];
2034
2035 u8 if_out_broadcast_pkts_low[0x20];
2036
b4ff3a36 2037 u8 reserved_at_340[0x480];
e281682b
SM		 2038};
2039
2040struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2041 u8 a_frames_transmitted_ok_high[0x20];
2042
2043 u8 a_frames_transmitted_ok_low[0x20];
2044
2045 u8 a_frames_received_ok_high[0x20];
2046
2047 u8 a_frames_received_ok_low[0x20];
2048
2049 u8 a_frame_check_sequence_errors_high[0x20];
2050
2051 u8 a_frame_check_sequence_errors_low[0x20];
2052
2053 u8 a_alignment_errors_high[0x20];
2054
2055 u8 a_alignment_errors_low[0x20];
2056
2057 u8 a_octets_transmitted_ok_high[0x20];
2058
2059 u8 a_octets_transmitted_ok_low[0x20];
2060
2061 u8 a_octets_received_ok_high[0x20];
2062
2063 u8 a_octets_received_ok_low[0x20];
2064
2065 u8 a_multicast_frames_xmitted_ok_high[0x20];
2066
2067 u8 a_multicast_frames_xmitted_ok_low[0x20];
2068
2069 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2070
2071 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2072
2073 u8 a_multicast_frames_received_ok_high[0x20];
2074
2075 u8 a_multicast_frames_received_ok_low[0x20];
2076
2077 u8 a_broadcast_frames_received_ok_high[0x20];
2078
2079 u8 a_broadcast_frames_received_ok_low[0x20];
2080
2081 u8 a_in_range_length_errors_high[0x20];
2082
2083 u8 a_in_range_length_errors_low[0x20];
2084
2085 u8 a_out_of_range_length_field_high[0x20];
2086
2087 u8 a_out_of_range_length_field_low[0x20];
2088
2089 u8 a_frame_too_long_errors_high[0x20];
2090
2091 u8 a_frame_too_long_errors_low[0x20];
2092
2093 u8 a_symbol_error_during_carrier_high[0x20];
2094
2095 u8 a_symbol_error_during_carrier_low[0x20];
2096
2097 u8 a_mac_control_frames_transmitted_high[0x20];
2098
2099 u8 a_mac_control_frames_transmitted_low[0x20];
2100
2101 u8 a_mac_control_frames_received_high[0x20];
2102
2103 u8 a_mac_control_frames_received_low[0x20];
2104
2105 u8 a_unsupported_opcodes_received_high[0x20];
2106
2107 u8 a_unsupported_opcodes_received_low[0x20];
2108
2109 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2110
2111 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2112
2113 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2114
2115 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2116
b4ff3a36 2117 u8 reserved_at_4c0[0x300];
e281682b
SM		 2118};
2119
8ed1a630
GP		 2120struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2121 u8 life_time_counter_high[0x20];
2122
2123 u8 life_time_counter_low[0x20];
2124
2125 u8 rx_errors[0x20];
2126
2127 u8 tx_errors[0x20];
2128
2129 u8 l0_to_recovery_eieos[0x20];
2130
2131 u8 l0_to_recovery_ts[0x20];
2132
2133 u8 l0_to_recovery_framing[0x20];
2134
2135 u8 l0_to_recovery_retrain[0x20];
2136
2137 u8 crc_error_dllp[0x20];
2138
2139 u8 crc_error_tlp[0x20];
2140
efae7f78
EBE		 2141 u8 tx_overflow_buffer_pkt_high[0x20];
2142
2143 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2144
2145 u8 outbound_stalled_reads[0x20];
2146
2147 u8 outbound_stalled_writes[0x20];
2148
2149 u8 outbound_stalled_reads_events[0x20];
2150
2151 u8 outbound_stalled_writes_events[0x20];
2152
2153 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2154};
2155
e281682b
SM		 2156struct mlx5_ifc_cmd_inter_comp_event_bits {
2157 u8 command_completion_vector[0x20];
2158
b4ff3a36 2159 u8 reserved_at_20[0xc0];
e281682b
SM		 2160};
2161
2162struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2163 u8 reserved_at_0[0x18];
e281682b 2164 u8 port_num[0x1];
b4ff3a36 2165 u8 reserved_at_19[0x3];
e281682b
SM		 2166 u8 vl[0x4];
2167
b4ff3a36 2168 u8 reserved_at_20[0xa0];
e281682b
SM		 2169};
2170
2171struct mlx5_ifc_db_bf_congestion_event_bits {
2172 u8 event_subtype[0x8];
b4ff3a36 2173 u8 reserved_at_8[0x8];
e281682b 2174 u8 congestion_level[0x8];
b4ff3a36 2175 u8 reserved_at_18[0x8];
e281682b 2176
b4ff3a36 2177 u8 reserved_at_20[0xa0];
e281682b
SM		 2178};
2179
2180struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2181 u8 reserved_at_0[0x60];
e281682b
SM		 2182
2183 u8 gpio_event_hi[0x20];
2184
2185 u8 gpio_event_lo[0x20];
2186
b4ff3a36 2187 u8 reserved_at_a0[0x40];
e281682b
SM		 2188};
2189
2190struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2191 u8 reserved_at_0[0x40];
e281682b
SM		 2192
2193 u8 port_num[0x4];
b4ff3a36 2194 u8 reserved_at_44[0x1c];
e281682b 2195
b4ff3a36 2196 u8 reserved_at_60[0x80];
e281682b
SM		 2197};
2198
2199struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2200 u8 reserved_at_0[0xe0];
e281682b
SM		 2201};
2202
2203enum {
2204 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2205 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2206};
2207
2208struct mlx5_ifc_cq_error_bits {
b4ff3a36 2209 u8 reserved_at_0[0x8];
e281682b
SM		 2210 u8 cqn[0x18];
2211
b4ff3a36 2212 u8 reserved_at_20[0x20];
e281682b 2213
b4ff3a36 2214 u8 reserved_at_40[0x18];
e281682b
SM		 2215 u8 syndrome[0x8];
2216
b4ff3a36 2217 u8 reserved_at_60[0x80];
e281682b
SM		 2218};
2219
2220struct mlx5_ifc_rdma_page_fault_event_bits {
2221 u8 bytes_committed[0x20];
2222
2223 u8 r_key[0x20];
2224
b4ff3a36 2225 u8 reserved_at_40[0x10];
e281682b
SM		 2226 u8 packet_len[0x10];
2227
2228 u8 rdma_op_len[0x20];
2229
2230 u8 rdma_va[0x40];
2231
b4ff3a36 2232 u8 reserved_at_c0[0x5];
e281682b
SM		 2233 u8 rdma[0x1];
2234 u8 write[0x1];
2235 u8 requestor[0x1];
2236 u8 qp_number[0x18];
2237};
2238
2239struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2240 u8 bytes_committed[0x20];
2241
b4ff3a36 2242 u8 reserved_at_20[0x10];
e281682b
SM		 2243 u8 wqe_index[0x10];
2244
b4ff3a36 2245 u8 reserved_at_40[0x10];
e281682b
SM		 2246 u8 len[0x10];
2247
b4ff3a36 2248 u8 reserved_at_60[0x60];
e281682b 2249
b4ff3a36 2250 u8 reserved_at_c0[0x5];
e281682b
SM		 2251 u8 rdma[0x1];
2252 u8 write_read[0x1];
2253 u8 requestor[0x1];
2254 u8 qpn[0x18];
2255};
2256
2257struct mlx5_ifc_qp_events_bits {
b4ff3a36 2258 u8 reserved_at_0[0xa0];
e281682b
SM		 2259
2260 u8 type[0x8];
b4ff3a36 2261 u8 reserved_at_a8[0x18];
e281682b 2262
b4ff3a36 2263 u8 reserved_at_c0[0x8];
e281682b
SM		 2264 u8 qpn_rqn_sqn[0x18];
2265};
2266
2267struct mlx5_ifc_dct_events_bits {
b4ff3a36 2268 u8 reserved_at_0[0xc0];
e281682b 2269
b4ff3a36 2270 u8 reserved_at_c0[0x8];
e281682b
SM		 2271 u8 dct_number[0x18];
2272};
2273
2274struct mlx5_ifc_comp_event_bits {
b4ff3a36 2275 u8 reserved_at_0[0xc0];
e281682b 2276
b4ff3a36 2277 u8 reserved_at_c0[0x8];
e281682b
SM		 2278 u8 cq_number[0x18];
2279};
2280
2281enum {
2282 MLX5_QPC_STATE_RST = 0x0,
2283 MLX5_QPC_STATE_INIT = 0x1,
2284 MLX5_QPC_STATE_RTR = 0x2,
2285 MLX5_QPC_STATE_RTS = 0x3,
2286 MLX5_QPC_STATE_SQER = 0x4,
2287 MLX5_QPC_STATE_ERR = 0x6,
2288 MLX5_QPC_STATE_SQD = 0x7,
2289 MLX5_QPC_STATE_SUSPENDED = 0x9,
2290};
2291
2292enum {
2293 MLX5_QPC_ST_RC = 0x0,
2294 MLX5_QPC_ST_UC = 0x1,
2295 MLX5_QPC_ST_UD = 0x2,
2296 MLX5_QPC_ST_XRC = 0x3,
2297 MLX5_QPC_ST_DCI = 0x5,
2298 MLX5_QPC_ST_QP0 = 0x7,
2299 MLX5_QPC_ST_QP1 = 0x8,
2300 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2301 MLX5_QPC_ST_REG_UMR = 0xc,
2302};
2303
2304enum {
2305 MLX5_QPC_PM_STATE_ARMED = 0x0,
2306 MLX5_QPC_PM_STATE_REARM = 0x1,
2307 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2308 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2309};
2310
6e44636a
AK		 2311enum {
2312 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2313};
2314
e281682b
SM		 2315enum {
2316 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2317 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2318};
2319
2320enum {
2321 MLX5_QPC_MTU_256_BYTES = 0x1,
2322 MLX5_QPC_MTU_512_BYTES = 0x2,
2323 MLX5_QPC_MTU_1K_BYTES = 0x3,
2324 MLX5_QPC_MTU_2K_BYTES = 0x4,
2325 MLX5_QPC_MTU_4K_BYTES = 0x5,
2326 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2327};
2328
2329enum {
2330 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2331 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2332 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2333 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2334 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2335 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2336 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2337 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2338};
2339
2340enum {
2341 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2342 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2343 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2344};
2345
2346enum {
2347 MLX5_QPC_CS_RES_DISABLE = 0x0,
2348 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2349 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2350};
2351
2352struct mlx5_ifc_qpc_bits {
2353 u8 state[0x4];
84df61eb 2354 u8 lag_tx_port_affinity[0x4];
e281682b 2355 u8 st[0x8];
b4ff3a36 2356 u8 reserved_at_10[0x3];
e281682b 2357 u8 pm_state[0x2];
3fd3c80a
DG		 2358 u8 reserved_at_15[0x1];
2359 u8 req_e2e_credit_mode[0x2];
6e44636a 2360 u8 offload_type[0x4];
e281682b 2361 u8 end_padding_mode[0x2];
b4ff3a36 2362 u8 reserved_at_1e[0x2];
e281682b
SM		 2363
2364 u8 wq_signature[0x1];
2365 u8 block_lb_mc[0x1];
2366 u8 atomic_like_write_en[0x1];
2367 u8 latency_sensitive[0x1];
b4ff3a36 2368 u8 reserved_at_24[0x1];
e281682b 2369 u8 drain_sigerr[0x1];
b4ff3a36 2370 u8 reserved_at_26[0x2];
e281682b
SM		 2371 u8 pd[0x18];
2372
2373 u8 mtu[0x3];
2374 u8 log_msg_max[0x5];
b4ff3a36 2375 u8 reserved_at_48[0x1];
e281682b
SM		 2376 u8 log_rq_size[0x4];
2377 u8 log_rq_stride[0x3];
2378 u8 no_sq[0x1];
2379 u8 log_sq_size[0x4];
b4ff3a36 2380 u8 reserved_at_55[0x6];
e281682b 2381 u8 rlky[0x1];
1015c2e8 2382 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2383
2384 u8 counter_set_id[0x8];
2385 u8 uar_page[0x18];
2386
b4ff3a36 2387 u8 reserved_at_80[0x8];
e281682b
SM		 2388 u8 user_index[0x18];
2389
b4ff3a36 2390 u8 reserved_at_a0[0x3];
e281682b
SM		 2391 u8 log_page_size[0x5];
2392 u8 remote_qpn[0x18];
2393
2394 struct mlx5_ifc_ads_bits primary_address_path;
2395
2396 struct mlx5_ifc_ads_bits secondary_address_path;
2397
2398 u8 log_ack_req_freq[0x4];
b4ff3a36 2399 u8 reserved_at_384[0x4];
e281682b 2400 u8 log_sra_max[0x3];
b4ff3a36 2401 u8 reserved_at_38b[0x2];
e281682b
SM		 2402 u8 retry_count[0x3];
2403 u8 rnr_retry[0x3];
b4ff3a36 2404 u8 reserved_at_393[0x1];
e281682b
SM		 2405 u8 fre[0x1];
2406 u8 cur_rnr_retry[0x3];
2407 u8 cur_retry_count[0x3];
b4ff3a36 2408 u8 reserved_at_39b[0x5];
e281682b 2409
b4ff3a36 2410 u8 reserved_at_3a0[0x20];
e281682b 2411
b4ff3a36 2412 u8 reserved_at_3c0[0x8];
e281682b
SM		 2413 u8 next_send_psn[0x18];
2414
b4ff3a36 2415 u8 reserved_at_3e0[0x8];
e281682b
SM		 2416 u8 cqn_snd[0x18];
2417
09a7d9ec
SM		 2418 u8 reserved_at_400[0x8];
2419 u8 deth_sqpn[0x18];
2420
2421 u8 reserved_at_420[0x20];
e281682b 2422
b4ff3a36 2423 u8 reserved_at_440[0x8];
e281682b
SM		 2424 u8 last_acked_psn[0x18];
2425
b4ff3a36 2426 u8 reserved_at_460[0x8];
e281682b
SM		 2427 u8 ssn[0x18];
2428
b4ff3a36 2429 u8 reserved_at_480[0x8];
e281682b 2430 u8 log_rra_max[0x3];
b4ff3a36 2431 u8 reserved_at_48b[0x1];
e281682b
SM		 2432 u8 atomic_mode[0x4];
2433 u8 rre[0x1];
2434 u8 rwe[0x1];
2435 u8 rae[0x1];
b4ff3a36 2436 u8 reserved_at_493[0x1];
e281682b 2437 u8 page_offset[0x6];
b4ff3a36 2438 u8 reserved_at_49a[0x3];
e281682b
SM		 2439 u8 cd_slave_receive[0x1];
2440 u8 cd_slave_send[0x1];
2441 u8 cd_master[0x1];
2442
b4ff3a36 2443 u8 reserved_at_4a0[0x3];
e281682b
SM		 2444 u8 min_rnr_nak[0x5];
2445 u8 next_rcv_psn[0x18];
2446
b4ff3a36 2447 u8 reserved_at_4c0[0x8];
e281682b
SM		 2448 u8 xrcd[0x18];
2449
b4ff3a36 2450 u8 reserved_at_4e0[0x8];
e281682b
SM		 2451 u8 cqn_rcv[0x18];
2452
2453 u8 dbr_addr[0x40];
2454
2455 u8 q_key[0x20];
2456
b4ff3a36 2457 u8 reserved_at_560[0x5];
e281682b 2458 u8 rq_type[0x3];
7486216b 2459 u8 srqn_rmpn_xrqn[0x18];
e281682b 2460
b4ff3a36 2461 u8 reserved_at_580[0x8];
e281682b
SM		 2462 u8 rmsn[0x18];
2463
2464 u8 hw_sq_wqebb_counter[0x10];
2465 u8 sw_sq_wqebb_counter[0x10];
2466
2467 u8 hw_rq_counter[0x20];
2468
2469 u8 sw_rq_counter[0x20];
2470
b4ff3a36 2471 u8 reserved_at_600[0x20];
e281682b 2472
b4ff3a36 2473 u8 reserved_at_620[0xf];
e281682b
SM		 2474 u8 cgs[0x1];
2475 u8 cs_req[0x8];
2476 u8 cs_res[0x8];
2477
2478 u8 dc_access_key[0x40];
2479
bd371975
LR		 2480 u8 reserved_at_680[0x3];
2481 u8 dbr_umem_valid[0x1];
2482
2483 u8 reserved_at_684[0xbc];
e281682b
SM		 2484};
2485
2486struct mlx5_ifc_roce_addr_layout_bits {
2487 u8 source_l3_address[16][0x8];
2488
b4ff3a36 2489 u8 reserved_at_80[0x3];
e281682b
SM		 2490 u8 vlan_valid[0x1];
2491 u8 vlan_id[0xc];
2492 u8 source_mac_47_32[0x10];
2493
2494 u8 source_mac_31_0[0x20];
2495
b4ff3a36 2496 u8 reserved_at_c0[0x14];
e281682b
SM		 2497 u8 roce_l3_type[0x4];
2498 u8 roce_version[0x8];
2499
b4ff3a36 2500 u8 reserved_at_e0[0x20];
e281682b
SM		 2501};
2502
2503union mlx5_ifc_hca_cap_union_bits {
2504 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2505 struct mlx5_ifc_odp_cap_bits odp_cap;
2506 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2507 struct mlx5_ifc_roce_cap_bits roce_cap;
2508 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2509 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2510 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2511 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2512 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2513 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2514 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2515 u8 reserved_at_0[0x8000];
e281682b
SM		 2516};
2517
2518enum {
2519 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2520 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2521 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2522 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 2523 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 2524 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2525 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2526 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2527 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 2528 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2529 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
0c06897a
OG		 2530};
2531
2532struct mlx5_ifc_vlan_bits {
2533 u8 ethtype[0x10];
2534 u8 prio[0x3];
2535 u8 cfi[0x1];
2536 u8 vid[0xc];
e281682b
SM		 2537};
2538
2539struct mlx5_ifc_flow_context_bits {
0c06897a 2540 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2541
2542 u8 group_id[0x20];
2543
b4ff3a36 2544 u8 reserved_at_40[0x8];
e281682b
SM		 2545 u8 flow_tag[0x18];
2546
b4ff3a36 2547 u8 reserved_at_60[0x10];
e281682b
SM		 2548 u8 action[0x10];
2549
1b115498
EB		 2550 u8 extended_destination[0x1];
2551 u8 reserved_at_80[0x7];
e281682b
SM		 2552 u8 destination_list_size[0x18];
2553
9dc0b289
AV		 2554 u8 reserved_at_a0[0x8];
2555 u8 flow_counter_list_size[0x18];
2556
60786f09 2557 u8 packet_reformat_id[0x20];
7adbde20 2558
2a69cb9f
OG		 2559 u8 modify_header_id[0x20];
2560
8da6fe2a
JL		 2561 struct mlx5_ifc_vlan_bits push_vlan_2;
2562
2563 u8 reserved_at_120[0xe0];
e281682b
SM		 2564
2565 struct mlx5_ifc_fte_match_param_bits match_value;
2566
b4ff3a36 2567 u8 reserved_at_1200[0x600];
e281682b 2568
9dc0b289 2569 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2570};
2571
2572enum {
2573 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2574 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2575};
2576
2577struct mlx5_ifc_xrc_srqc_bits {
2578 u8 state[0x4];
2579 u8 log_xrc_srq_size[0x4];
b4ff3a36 2580 u8 reserved_at_8[0x18];
e281682b
SM		 2581
2582 u8 wq_signature[0x1];
2583 u8 cont_srq[0x1];
99b77fef 2584 u8 reserved_at_22[0x1];
e281682b
SM		 2585 u8 rlky[0x1];
2586 u8 basic_cyclic_rcv_wqe[0x1];
2587 u8 log_rq_stride[0x3];
2588 u8 xrcd[0x18];
2589
2590 u8 page_offset[0x6];
99b77fef
YH		 2591 u8 reserved_at_46[0x1];
2592 u8 dbr_umem_valid[0x1];
e281682b
SM		 2593 u8 cqn[0x18];
2594
b4ff3a36 2595 u8 reserved_at_60[0x20];
e281682b
SM		 2596
2597 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2598 u8 reserved_at_81[0x1];
e281682b
SM		 2599 u8 log_page_size[0x6];
2600 u8 user_index[0x18];
2601
b4ff3a36 2602 u8 reserved_at_a0[0x20];
e281682b 2603
b4ff3a36 2604 u8 reserved_at_c0[0x8];
e281682b
SM		 2605 u8 pd[0x18];
2606
2607 u8 lwm[0x10];
2608 u8 wqe_cnt[0x10];
2609
b4ff3a36 2610 u8 reserved_at_100[0x40];
e281682b
SM		 2611
2612 u8 db_record_addr_h[0x20];
2613
2614 u8 db_record_addr_l[0x1e];
b4ff3a36 2615 u8 reserved_at_17e[0x2];
e281682b 2616
b4ff3a36 2617 u8 reserved_at_180[0x80];
e281682b
SM		 2618};
2619
61c5b5c9
MS		 2620struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2621 u8 counter_error_queues[0x20];
2622
2623 u8 total_error_queues[0x20];
2624
2625 u8 send_queue_priority_update_flow[0x20];
2626
2627 u8 reserved_at_60[0x20];
2628
2629 u8 nic_receive_steering_discard[0x40];
2630
2631 u8 receive_discard_vport_down[0x40];
2632
2633 u8 transmit_discard_vport_down[0x40];
2634
2635 u8 reserved_at_140[0xec0];
2636};
2637
e281682b
SM		 2638struct mlx5_ifc_traffic_counter_bits {
2639 u8 packets[0x40];
2640
2641 u8 octets[0x40];
2642};
2643
2644struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2645 u8 strict_lag_tx_port_affinity[0x1];
2646 u8 reserved_at_1[0x3];
2647 u8 lag_tx_port_affinity[0x04];
2648
2649 u8 reserved_at_8[0x4];
e281682b 2650 u8 prio[0x4];
b4ff3a36 2651 u8 reserved_at_10[0x10];
e281682b 2652
b4ff3a36 2653 u8 reserved_at_20[0x100];
e281682b 2654
b4ff3a36 2655 u8 reserved_at_120[0x8];
e281682b
SM		 2656 u8 transport_domain[0x18];
2657
500a3d0d
ES		 2658 u8 reserved_at_140[0x8];
2659 u8 underlay_qpn[0x18];
2660 u8 reserved_at_160[0x3a0];
e281682b
SM		 2661};
2662
2663enum {
2664 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2665 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2666};
2667
2668enum {
2669 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2670 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2671};
2672
2673enum {
2be6967c
SM		 2674 MLX5_RX_HASH_FN_NONE = 0x0,
2675 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2676 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2677};
2678
2679enum {
5d773ff4
MB		 2680 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2681 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 2682};
2683
2684struct mlx5_ifc_tirc_bits {
b4ff3a36 2685 u8 reserved_at_0[0x20];
e281682b
SM		 2686
2687 u8 disp_type[0x4];
b4ff3a36 2688 u8 reserved_at_24[0x1c];
e281682b 2689
b4ff3a36 2690 u8 reserved_at_40[0x40];
e281682b 2691
b4ff3a36 2692 u8 reserved_at_80[0x4];
e281682b
SM		 2693 u8 lro_timeout_period_usecs[0x10];
2694 u8 lro_enable_mask[0x4];
2695 u8 lro_max_ip_payload_size[0x8];
2696
b4ff3a36 2697 u8 reserved_at_a0[0x40];
e281682b 2698
b4ff3a36 2699 u8 reserved_at_e0[0x8];
e281682b
SM		 2700 u8 inline_rqn[0x18];
2701
2702 u8 rx_hash_symmetric[0x1];
b4ff3a36 2703 u8 reserved_at_101[0x1];
e281682b 2704 u8 tunneled_offload_en[0x1];
b4ff3a36 2705 u8 reserved_at_103[0x5];
e281682b
SM		 2706 u8 indirect_table[0x18];
2707
2708 u8 rx_hash_fn[0x4];
b4ff3a36 2709 u8 reserved_at_124[0x2];
e281682b
SM		 2710 u8 self_lb_block[0x2];
2711 u8 transport_domain[0x18];
2712
2713 u8 rx_hash_toeplitz_key[10][0x20];
2714
2715 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2716
2717 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2718
b4ff3a36 2719 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2720};
2721
2722enum {
2723 MLX5_SRQC_STATE_GOOD = 0x0,
2724 MLX5_SRQC_STATE_ERROR = 0x1,
2725};
2726
2727struct mlx5_ifc_srqc_bits {
2728 u8 state[0x4];
2729 u8 log_srq_size[0x4];
b4ff3a36 2730 u8 reserved_at_8[0x18];
e281682b
SM		 2731
2732 u8 wq_signature[0x1];
2733 u8 cont_srq[0x1];
b4ff3a36 2734 u8 reserved_at_22[0x1];
e281682b 2735 u8 rlky[0x1];
b4ff3a36 2736 u8 reserved_at_24[0x1];
e281682b
SM		 2737 u8 log_rq_stride[0x3];
2738 u8 xrcd[0x18];
2739
2740 u8 page_offset[0x6];
b4ff3a36 2741 u8 reserved_at_46[0x2];
e281682b
SM		 2742 u8 cqn[0x18];
2743
b4ff3a36 2744 u8 reserved_at_60[0x20];
e281682b 2745
b4ff3a36 2746 u8 reserved_at_80[0x2];
e281682b 2747 u8 log_page_size[0x6];
b4ff3a36 2748 u8 reserved_at_88[0x18];
e281682b 2749
b4ff3a36 2750 u8 reserved_at_a0[0x20];
e281682b 2751
b4ff3a36 2752 u8 reserved_at_c0[0x8];
e281682b
SM		 2753 u8 pd[0x18];
2754
2755 u8 lwm[0x10];
2756 u8 wqe_cnt[0x10];
2757
b4ff3a36 2758 u8 reserved_at_100[0x40];
e281682b 2759
01949d01 2760 u8 dbr_addr[0x40];
e281682b 2761
b4ff3a36 2762 u8 reserved_at_180[0x80];
e281682b
SM		 2763};
2764
2765enum {
2766 MLX5_SQC_STATE_RST = 0x0,
2767 MLX5_SQC_STATE_RDY = 0x1,
2768 MLX5_SQC_STATE_ERR = 0x3,
2769};
2770
2771struct mlx5_ifc_sqc_bits {
2772 u8 rlky[0x1];
2773 u8 cd_master[0x1];
2774 u8 fre[0x1];
2775 u8 flush_in_error_en[0x1];
795b609c 2776 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2777 u8 min_wqe_inline_mode[0x3];
e281682b 2778 u8 state[0x4];
7d5e1423 2779 u8 reg_umr[0x1];
547eede0 2780 u8 allow_swp[0x1];
40817cdb
OG		 2781 u8 hairpin[0x1];
2782 u8 reserved_at_f[0x11];
e281682b 2783
b4ff3a36 2784 u8 reserved_at_20[0x8];
e281682b
SM		 2785 u8 user_index[0x18];
2786
b4ff3a36 2787 u8 reserved_at_40[0x8];
e281682b
SM		 2788 u8 cqn[0x18];
2789
40817cdb
OG		 2790 u8 reserved_at_60[0x8];
2791 u8 hairpin_peer_rq[0x18];
2792
2793 u8 reserved_at_80[0x10];
2794 u8 hairpin_peer_vhca[0x10];
2795
2796 u8 reserved_at_a0[0x50];
e281682b 2797
7486216b 2798 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2799 u8 tis_lst_sz[0x10];
b4ff3a36 2800 u8 reserved_at_110[0x10];
e281682b 2801
b4ff3a36 2802 u8 reserved_at_120[0x40];
e281682b 2803
b4ff3a36 2804 u8 reserved_at_160[0x8];
e281682b
SM		 2805 u8 tis_num_0[0x18];
2806
2807 struct mlx5_ifc_wq_bits wq;
2808};
2809
813f8540
MHY		 2810enum {
2811 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2812 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2813 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2814 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2815};
2816
2817struct mlx5_ifc_scheduling_context_bits {
2818 u8 element_type[0x8];
2819 u8 reserved_at_8[0x18];
2820
2821 u8 element_attributes[0x20];
2822
2823 u8 parent_element_id[0x20];
2824
2825 u8 reserved_at_60[0x40];
2826
2827 u8 bw_share[0x20];
2828
2829 u8 max_average_bw[0x20];
2830
2831 u8 reserved_at_e0[0x120];
2832};
2833
e281682b 2834struct mlx5_ifc_rqtc_bits {
b4ff3a36 2835 u8 reserved_at_0[0xa0];
e281682b 2836
b4ff3a36 2837 u8 reserved_at_a0[0x10];
e281682b
SM		 2838 u8 rqt_max_size[0x10];
2839
b4ff3a36 2840 u8 reserved_at_c0[0x10];
e281682b
SM		 2841 u8 rqt_actual_size[0x10];
2842
b4ff3a36 2843 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2844
2845 struct mlx5_ifc_rq_num_bits rq_num[0];
2846};
2847
2848enum {
2849 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2850 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2851};
2852
2853enum {
2854 MLX5_RQC_STATE_RST = 0x0,
2855 MLX5_RQC_STATE_RDY = 0x1,
2856 MLX5_RQC_STATE_ERR = 0x3,
2857};
2858
2859struct mlx5_ifc_rqc_bits {
2860 u8 rlky[0x1];
03404e8a 2861 u8 delay_drop_en[0x1];
7d5e1423 2862 u8 scatter_fcs[0x1];
e281682b
SM		 2863 u8 vsd[0x1];
2864 u8 mem_rq_type[0x4];
2865 u8 state[0x4];
b4ff3a36 2866 u8 reserved_at_c[0x1];
e281682b 2867 u8 flush_in_error_en[0x1];
40817cdb
OG		 2868 u8 hairpin[0x1];
2869 u8 reserved_at_f[0x11];
e281682b 2870
b4ff3a36 2871 u8 reserved_at_20[0x8];
e281682b
SM		 2872 u8 user_index[0x18];
2873
b4ff3a36 2874 u8 reserved_at_40[0x8];
e281682b
SM		 2875 u8 cqn[0x18];
2876
2877 u8 counter_set_id[0x8];
b4ff3a36 2878 u8 reserved_at_68[0x18];
e281682b 2879
b4ff3a36 2880 u8 reserved_at_80[0x8];
e281682b
SM		 2881 u8 rmpn[0x18];
2882
40817cdb
OG		 2883 u8 reserved_at_a0[0x8];
2884 u8 hairpin_peer_sq[0x18];
2885
2886 u8 reserved_at_c0[0x10];
2887 u8 hairpin_peer_vhca[0x10];
2888
2889 u8 reserved_at_e0[0xa0];
e281682b
SM		 2890
2891 struct mlx5_ifc_wq_bits wq;
2892};
2893
2894enum {
2895 MLX5_RMPC_STATE_RDY = 0x1,
2896 MLX5_RMPC_STATE_ERR = 0x3,
2897};
2898
2899struct mlx5_ifc_rmpc_bits {
b4ff3a36 2900 u8 reserved_at_0[0x8];
e281682b 2901 u8 state[0x4];
b4ff3a36 2902 u8 reserved_at_c[0x14];
e281682b
SM		 2903
2904 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2905 u8 reserved_at_21[0x1f];
e281682b 2906
b4ff3a36 2907 u8 reserved_at_40[0x140];
e281682b
SM		 2908
2909 struct mlx5_ifc_wq_bits wq;
2910};
2911
e281682b 2912struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2913 u8 reserved_at_0[0x5];
2914 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2915 u8 reserved_at_8[0x15];
2916 u8 disable_mc_local_lb[0x1];
2917 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2918 u8 roce_en[0x1];
2919
d82b7318 2920 u8 arm_change_event[0x1];
b4ff3a36 2921 u8 reserved_at_21[0x1a];
d82b7318
SM		 2922 u8 event_on_mtu[0x1];
2923 u8 event_on_promisc_change[0x1];
2924 u8 event_on_vlan_change[0x1];
2925 u8 event_on_mc_address_change[0x1];
2926 u8 event_on_uc_address_change[0x1];
e281682b 2927
32f69e4b
DJ		 2928 u8 reserved_at_40[0xc];
2929
2930 u8 affiliation_criteria[0x4];
2931 u8 affiliated_vhca_id[0x10];
2932
2933 u8 reserved_at_60[0xd0];
d82b7318
SM		 2934
2935 u8 mtu[0x10];
2936
9efa7525
AS		 2937 u8 system_image_guid[0x40];
2938 u8 port_guid[0x40];
2939 u8 node_guid[0x40];
2940
b4ff3a36 2941 u8 reserved_at_200[0x140];
9efa7525 2942 u8 qkey_violation_counter[0x10];
b4ff3a36 2943 u8 reserved_at_350[0x430];
d82b7318
SM		 2944
2945 u8 promisc_uc[0x1];
2946 u8 promisc_mc[0x1];
2947 u8 promisc_all[0x1];
b4ff3a36 2948 u8 reserved_at_783[0x2];
e281682b 2949 u8 allowed_list_type[0x3];
b4ff3a36 2950 u8 reserved_at_788[0xc];
e281682b
SM		 2951 u8 allowed_list_size[0xc];
2952
2953 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2954
b4ff3a36 2955 u8 reserved_at_7e0[0x20];
e281682b
SM		 2956
2957 u8 current_uc_mac_address[0][0x40];
2958};
2959
2960enum {
2961 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2962 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2963 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2964 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 2965 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 2966 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 2967};
2968
2969struct mlx5_ifc_mkc_bits {
b4ff3a36 2970 u8 reserved_at_0[0x1];
e281682b 2971 u8 free[0x1];
cdbd0d2b
AL		 2972 u8 reserved_at_2[0x1];
2973 u8 access_mode_4_2[0x3];
2974 u8 reserved_at_6[0x7];
2975 u8 relaxed_ordering_write[0x1];
2976 u8 reserved_at_e[0x1];
e281682b
SM		 2977 u8 small_fence_on_rdma_read_response[0x1];
2978 u8 umr_en[0x1];
2979 u8 a[0x1];
2980 u8 rw[0x1];
2981 u8 rr[0x1];
2982 u8 lw[0x1];
2983 u8 lr[0x1];
cdbd0d2b 2984 u8 access_mode_1_0[0x2];
b4ff3a36 2985 u8 reserved_at_18[0x8];
e281682b
SM		 2986
2987 u8 qpn[0x18];
2988 u8 mkey_7_0[0x8];
2989
b4ff3a36 2990 u8 reserved_at_40[0x20];
e281682b
SM		 2991
2992 u8 length64[0x1];
2993 u8 bsf_en[0x1];
2994 u8 sync_umr[0x1];
b4ff3a36 2995 u8 reserved_at_63[0x2];
e281682b 2996 u8 expected_sigerr_count[0x1];
b4ff3a36 2997 u8 reserved_at_66[0x1];
e281682b
SM		 2998 u8 en_rinval[0x1];
2999 u8 pd[0x18];
3000
3001 u8 start_addr[0x40];
3002
3003 u8 len[0x40];
3004
3005 u8 bsf_octword_size[0x20];
3006
b4ff3a36 3007 u8 reserved_at_120[0x80];
e281682b
SM		 3008
3009 u8 translations_octword_size[0x20];
3010
b4ff3a36 3011 u8 reserved_at_1c0[0x1b];
e281682b
SM		 3012 u8 log_page_size[0x5];
3013
b4ff3a36 3014 u8 reserved_at_1e0[0x20];
e281682b
SM		 3015};
3016
3017struct mlx5_ifc_pkey_bits {
b4ff3a36 3018 u8 reserved_at_0[0x10];
e281682b
SM		 3019 u8 pkey[0x10];
3020};
3021
3022struct mlx5_ifc_array128_auto_bits {
3023 u8 array128_auto[16][0x8];
3024};
3025
3026struct mlx5_ifc_hca_vport_context_bits {
3027 u8 field_select[0x20];
3028
b4ff3a36 3029 u8 reserved_at_20[0xe0];
e281682b
SM		 3030
3031 u8 sm_virt_aware[0x1];
3032 u8 has_smi[0x1];
3033 u8 has_raw[0x1];
3034 u8 grh_required[0x1];
b4ff3a36 3035 u8 reserved_at_104[0xc];
707c4602
MD		 3036 u8 port_physical_state[0x4];
3037 u8 vport_state_policy[0x4];
3038 u8 port_state[0x4];
e281682b
SM		 3039 u8 vport_state[0x4];
3040
b4ff3a36 3041 u8 reserved_at_120[0x20];
707c4602
MD		 3042
3043 u8 system_image_guid[0x40];
e281682b
SM		 3044
3045 u8 port_guid[0x40];
3046
3047 u8 node_guid[0x40];
3048
3049 u8 cap_mask1[0x20];
3050
3051 u8 cap_mask1_field_select[0x20];
3052
3053 u8 cap_mask2[0x20];
3054
3055 u8 cap_mask2_field_select[0x20];
3056
b4ff3a36 3057 u8 reserved_at_280[0x80];
e281682b
SM		 3058
3059 u8 lid[0x10];
b4ff3a36 3060 u8 reserved_at_310[0x4];
e281682b
SM		 3061 u8 init_type_reply[0x4];
3062 u8 lmc[0x3];
3063 u8 subnet_timeout[0x5];
3064
3065 u8 sm_lid[0x10];
3066 u8 sm_sl[0x4];
b4ff3a36 3067 u8 reserved_at_334[0xc];
e281682b
SM		 3068
3069 u8 qkey_violation_counter[0x10];
3070 u8 pkey_violation_counter[0x10];
3071
b4ff3a36 3072 u8 reserved_at_360[0xca0];
e281682b
SM		 3073};
3074
d6666753 3075struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 3076 u8 reserved_at_0[0x3];
d6666753
SM		 3077 u8 vport_svlan_strip[0x1];
3078 u8 vport_cvlan_strip[0x1];
3079 u8 vport_svlan_insert[0x1];
3080 u8 vport_cvlan_insert[0x2];
b4ff3a36 3081 u8 reserved_at_8[0x18];
d6666753 3082
b4ff3a36 3083 u8 reserved_at_20[0x20];
d6666753
SM		 3084
3085 u8 svlan_cfi[0x1];
3086 u8 svlan_pcp[0x3];
3087 u8 svlan_id[0xc];
3088 u8 cvlan_cfi[0x1];
3089 u8 cvlan_pcp[0x3];
3090 u8 cvlan_id[0xc];
3091
b4ff3a36 3092 u8 reserved_at_60[0x7a0];
d6666753
SM		 3093};
3094
e281682b
SM		 3095enum {
3096 MLX5_EQC_STATUS_OK = 0x0,
3097 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3098};
3099
3100enum {
3101 MLX5_EQC_ST_ARMED = 0x9,
3102 MLX5_EQC_ST_FIRED = 0xa,
3103};
3104
3105struct mlx5_ifc_eqc_bits {
3106 u8 status[0x4];
b4ff3a36 3107 u8 reserved_at_4[0x9];
e281682b
SM		 3108 u8 ec[0x1];
3109 u8 oi[0x1];
b4ff3a36 3110 u8 reserved_at_f[0x5];
e281682b 3111 u8 st[0x4];
b4ff3a36 3112 u8 reserved_at_18[0x8];
e281682b 3113
b4ff3a36 3114 u8 reserved_at_20[0x20];
e281682b 3115
b4ff3a36 3116 u8 reserved_at_40[0x14];
e281682b 3117 u8 page_offset[0x6];
b4ff3a36 3118 u8 reserved_at_5a[0x6];
e281682b 3119
b4ff3a36 3120 u8 reserved_at_60[0x3];
e281682b
SM		 3121 u8 log_eq_size[0x5];
3122 u8 uar_page[0x18];
3123
b4ff3a36 3124 u8 reserved_at_80[0x20];
e281682b 3125
b4ff3a36 3126 u8 reserved_at_a0[0x18];
e281682b
SM		 3127 u8 intr[0x8];
3128
b4ff3a36 3129 u8 reserved_at_c0[0x3];
e281682b 3130 u8 log_page_size[0x5];
b4ff3a36 3131 u8 reserved_at_c8[0x18];
e281682b 3132
b4ff3a36 3133 u8 reserved_at_e0[0x60];
e281682b 3134
b4ff3a36 3135 u8 reserved_at_140[0x8];
e281682b
SM		 3136 u8 consumer_counter[0x18];
3137
b4ff3a36 3138 u8 reserved_at_160[0x8];
e281682b
SM		 3139 u8 producer_counter[0x18];
3140
b4ff3a36 3141 u8 reserved_at_180[0x80];
e281682b
SM		 3142};
3143
3144enum {
3145 MLX5_DCTC_STATE_ACTIVE = 0x0,
3146 MLX5_DCTC_STATE_DRAINING = 0x1,
3147 MLX5_DCTC_STATE_DRAINED = 0x2,
3148};
3149
3150enum {
3151 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3152 MLX5_DCTC_CS_RES_NA = 0x1,
3153 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3154};
3155
3156enum {
3157 MLX5_DCTC_MTU_256_BYTES = 0x1,
3158 MLX5_DCTC_MTU_512_BYTES = 0x2,
3159 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3160 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3161 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3162};
3163
3164struct mlx5_ifc_dctc_bits {
b4ff3a36 3165 u8 reserved_at_0[0x4];
e281682b 3166 u8 state[0x4];
b4ff3a36 3167 u8 reserved_at_8[0x18];
e281682b 3168
b4ff3a36 3169 u8 reserved_at_20[0x8];
e281682b
SM		 3170 u8 user_index[0x18];
3171
b4ff3a36 3172 u8 reserved_at_40[0x8];
e281682b
SM		 3173 u8 cqn[0x18];
3174
3175 u8 counter_set_id[0x8];
3176 u8 atomic_mode[0x4];
3177 u8 rre[0x1];
3178 u8 rwe[0x1];
3179 u8 rae[0x1];
3180 u8 atomic_like_write_en[0x1];
3181 u8 latency_sensitive[0x1];
3182 u8 rlky[0x1];
3183 u8 free_ar[0x1];
b4ff3a36 3184 u8 reserved_at_73[0xd];
e281682b 3185
b4ff3a36 3186 u8 reserved_at_80[0x8];
e281682b 3187 u8 cs_res[0x8];
b4ff3a36 3188 u8 reserved_at_90[0x3];
e281682b 3189 u8 min_rnr_nak[0x5];
b4ff3a36 3190 u8 reserved_at_98[0x8];
e281682b 3191
b4ff3a36 3192 u8 reserved_at_a0[0x8];
7486216b 3193 u8 srqn_xrqn[0x18];
e281682b 3194
b4ff3a36 3195 u8 reserved_at_c0[0x8];
e281682b
SM		 3196 u8 pd[0x18];
3197
3198 u8 tclass[0x8];
b4ff3a36 3199 u8 reserved_at_e8[0x4];
e281682b
SM		 3200 u8 flow_label[0x14];
3201
3202 u8 dc_access_key[0x40];
3203
b4ff3a36 3204 u8 reserved_at_140[0x5];
e281682b
SM		 3205 u8 mtu[0x3];
3206 u8 port[0x8];
3207 u8 pkey_index[0x10];
3208
b4ff3a36 3209 u8 reserved_at_160[0x8];
e281682b 3210 u8 my_addr_index[0x8];
b4ff3a36 3211 u8 reserved_at_170[0x8];
e281682b
SM		 3212 u8 hop_limit[0x8];
3213
3214 u8 dc_access_key_violation_count[0x20];
3215
b4ff3a36 3216 u8 reserved_at_1a0[0x14];
e281682b
SM		 3217 u8 dei_cfi[0x1];
3218 u8 eth_prio[0x3];
3219 u8 ecn[0x2];
3220 u8 dscp[0x6];
3221
b4ff3a36 3222 u8 reserved_at_1c0[0x40];
e281682b
SM		 3223};
3224
3225enum {
3226 MLX5_CQC_STATUS_OK = 0x0,
3227 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3228 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3229};
3230
3231enum {
3232 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3233 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3234};
3235
3236enum {
3237 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3238 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3239 MLX5_CQC_ST_FIRED = 0xa,
3240};
3241
7d5e1423
SM		 3242enum {
3243 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3244 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3245 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3246};
3247
e281682b
SM		 3248struct mlx5_ifc_cqc_bits {
3249 u8 status[0x4];
bd371975
LR		 3250 u8 reserved_at_4[0x2];
3251 u8 dbr_umem_valid[0x1];
3252 u8 reserved_at_7[0x1];
e281682b
SM		 3253 u8 cqe_sz[0x3];
3254 u8 cc[0x1];
b4ff3a36 3255 u8 reserved_at_c[0x1];
e281682b
SM		 3256 u8 scqe_break_moderation_en[0x1];
3257 u8 oi[0x1];
7d5e1423
SM		 3258 u8 cq_period_mode[0x2];
3259 u8 cqe_comp_en[0x1];
e281682b
SM		 3260 u8 mini_cqe_res_format[0x2];
3261 u8 st[0x4];
b4ff3a36 3262 u8 reserved_at_18[0x8];
e281682b 3263
b4ff3a36 3264 u8 reserved_at_20[0x20];
e281682b 3265
b4ff3a36 3266 u8 reserved_at_40[0x14];
e281682b 3267 u8 page_offset[0x6];
b4ff3a36 3268 u8 reserved_at_5a[0x6];
e281682b 3269
b4ff3a36 3270 u8 reserved_at_60[0x3];
e281682b
SM		 3271 u8 log_cq_size[0x5];
3272 u8 uar_page[0x18];
3273
b4ff3a36 3274 u8 reserved_at_80[0x4];
e281682b
SM		 3275 u8 cq_period[0xc];
3276 u8 cq_max_count[0x10];
3277
b4ff3a36 3278 u8 reserved_at_a0[0x18];
e281682b
SM		 3279 u8 c_eqn[0x8];
3280
b4ff3a36 3281 u8 reserved_at_c0[0x3];
e281682b 3282 u8 log_page_size[0x5];
b4ff3a36 3283 u8 reserved_at_c8[0x18];
e281682b 3284
b4ff3a36 3285 u8 reserved_at_e0[0x20];
e281682b 3286
b4ff3a36 3287 u8 reserved_at_100[0x8];
e281682b
SM		 3288 u8 last_notified_index[0x18];
3289
b4ff3a36 3290 u8 reserved_at_120[0x8];
e281682b
SM		 3291 u8 last_solicit_index[0x18];
3292
b4ff3a36 3293 u8 reserved_at_140[0x8];
e281682b
SM		 3294 u8 consumer_counter[0x18];
3295
b4ff3a36 3296 u8 reserved_at_160[0x8];
e281682b
SM		 3297 u8 producer_counter[0x18];
3298
b4ff3a36 3299 u8 reserved_at_180[0x40];
e281682b
SM		 3300
3301 u8 dbr_addr[0x40];
3302};
3303
3304union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3305 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3306 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3307 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3308 u8 reserved_at_0[0x800];
e281682b
SM		 3309};
3310
3311struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3312 u8 reserved_at_0[0xc0];
e281682b 3313
b4ff3a36 3314 u8 reserved_at_c0[0x8];
211e6c80
MD		 3315 u8 ieee_vendor_id[0x18];
3316
b4ff3a36 3317 u8 reserved_at_e0[0x10];
e281682b
SM		 3318 u8 vsd_vendor_id[0x10];
3319
3320 u8 vsd[208][0x8];
3321
3322 u8 vsd_contd_psid[16][0x8];
3323};
3324
7486216b
SM		 3325enum {
3326 MLX5_XRQC_STATE_GOOD = 0x0,
3327 MLX5_XRQC_STATE_ERROR = 0x1,
3328};
3329
3330enum {
3331 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3332 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3333};
3334
3335enum {
3336 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3337};
3338
3339struct mlx5_ifc_tag_matching_topology_context_bits {
3340 u8 log_matching_list_sz[0x4];
3341 u8 reserved_at_4[0xc];
3342 u8 append_next_index[0x10];
3343
3344 u8 sw_phase_cnt[0x10];
3345 u8 hw_phase_cnt[0x10];
3346
3347 u8 reserved_at_40[0x40];
3348};
3349
3350struct mlx5_ifc_xrqc_bits {
3351 u8 state[0x4];
3352 u8 rlkey[0x1];
3353 u8 reserved_at_5[0xf];
3354 u8 topology[0x4];
3355 u8 reserved_at_18[0x4];
3356 u8 offload[0x4];
3357
3358 u8 reserved_at_20[0x8];
3359 u8 user_index[0x18];
3360
3361 u8 reserved_at_40[0x8];
3362 u8 cqn[0x18];
3363
3364 u8 reserved_at_60[0xa0];
3365
3366 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3367
6e44636a 3368 u8 reserved_at_180[0x280];
7486216b
SM		 3369
3370 struct mlx5_ifc_wq_bits wq;
3371};
3372
e281682b
SM		 3373union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3374 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3375 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3376 u8 reserved_at_0[0x20];
e281682b
SM		 3377};
3378
3379union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3380 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3381 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3382 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3383 u8 reserved_at_0[0x20];
e281682b
SM		 3384};
3385
3386union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3387 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3388 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3389 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3390 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3391 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3392 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3393 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3394 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3395 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3396 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3397 u8 reserved_at_0[0x7c0];
e281682b
SM		 3398};
3399
8ed1a630
GP		 3400union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3401 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3402 u8 reserved_at_0[0x7c0];
3403};
3404
e281682b
SM		 3405union mlx5_ifc_event_auto_bits {
3406 struct mlx5_ifc_comp_event_bits comp_event;
3407 struct mlx5_ifc_dct_events_bits dct_events;
3408 struct mlx5_ifc_qp_events_bits qp_events;
3409 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3410 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3411 struct mlx5_ifc_cq_error_bits cq_error;
3412 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3413 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3414 struct mlx5_ifc_gpio_event_bits gpio_event;
3415 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3416 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3417 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3418 u8 reserved_at_0[0xe0];
e281682b
SM		 3419};
3420
3421struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3422 u8 reserved_at_0[0x100];
e281682b
SM		 3423
3424 u8 assert_existptr[0x20];
3425
3426 u8 assert_callra[0x20];
3427
b4ff3a36 3428 u8 reserved_at_140[0x40];
e281682b
SM		 3429
3430 u8 fw_version[0x20];
3431
3432 u8 hw_id[0x20];
3433
b4ff3a36 3434 u8 reserved_at_1c0[0x20];
e281682b
SM		 3435
3436 u8 irisc_index[0x8];
3437 u8 synd[0x8];
3438 u8 ext_synd[0x10];
3439};
3440
3441struct mlx5_ifc_register_loopback_control_bits {
3442 u8 no_lb[0x1];
b4ff3a36 3443 u8 reserved_at_1[0x7];
e281682b 3444 u8 port[0x8];
b4ff3a36 3445 u8 reserved_at_10[0x10];
e281682b 3446
b4ff3a36 3447 u8 reserved_at_20[0x60];
e281682b
SM		 3448};
3449
813f8540
MHY		 3450struct mlx5_ifc_vport_tc_element_bits {
3451 u8 traffic_class[0x4];
3452 u8 reserved_at_4[0xc];
3453 u8 vport_number[0x10];
3454};
3455
3456struct mlx5_ifc_vport_element_bits {
3457 u8 reserved_at_0[0x10];
3458 u8 vport_number[0x10];
3459};
3460
3461enum {
3462 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3463 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3464 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3465};
3466
3467struct mlx5_ifc_tsar_element_bits {
3468 u8 reserved_at_0[0x8];
3469 u8 tsar_type[0x8];
3470 u8 reserved_at_10[0x10];
3471};
3472
8812c24d
MD		 3473enum {
3474 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3475 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3476};
3477
e281682b
SM		 3478struct mlx5_ifc_teardown_hca_out_bits {
3479 u8 status[0x8];
b4ff3a36 3480 u8 reserved_at_8[0x18];
e281682b
SM		 3481
3482 u8 syndrome[0x20];
3483
8812c24d
MD		 3484 u8 reserved_at_40[0x3f];
3485
fcd29ad1 3486 u8 state[0x1];
e281682b
SM		 3487};
3488
3489enum {
3490 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3491 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 3492 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 3493};
3494
3495struct mlx5_ifc_teardown_hca_in_bits {
3496 u8 opcode[0x10];
b4ff3a36 3497 u8 reserved_at_10[0x10];
e281682b 3498
b4ff3a36 3499 u8 reserved_at_20[0x10];
e281682b
SM		 3500 u8 op_mod[0x10];
3501
b4ff3a36 3502 u8 reserved_at_40[0x10];
e281682b
SM		 3503 u8 profile[0x10];
3504
b4ff3a36 3505 u8 reserved_at_60[0x20];
e281682b
SM		 3506};
3507
3508struct mlx5_ifc_sqerr2rts_qp_out_bits {
3509 u8 status[0x8];
b4ff3a36 3510 u8 reserved_at_8[0x18];
e281682b
SM		 3511
3512 u8 syndrome[0x20];
3513
b4ff3a36 3514 u8 reserved_at_40[0x40];
e281682b
SM		 3515};
3516
3517struct mlx5_ifc_sqerr2rts_qp_in_bits {
3518 u8 opcode[0x10];
4ac63ec7 3519 u8 uid[0x10];
e281682b 3520
b4ff3a36 3521 u8 reserved_at_20[0x10];
e281682b
SM		 3522 u8 op_mod[0x10];
3523
b4ff3a36 3524 u8 reserved_at_40[0x8];
e281682b
SM		 3525 u8 qpn[0x18];
3526
b4ff3a36 3527 u8 reserved_at_60[0x20];
e281682b
SM		 3528
3529 u8 opt_param_mask[0x20];
3530
b4ff3a36 3531 u8 reserved_at_a0[0x20];
e281682b
SM		 3532
3533 struct mlx5_ifc_qpc_bits qpc;
3534
b4ff3a36 3535 u8 reserved_at_800[0x80];
e281682b
SM		 3536};
3537
3538struct mlx5_ifc_sqd2rts_qp_out_bits {
3539 u8 status[0x8];
b4ff3a36 3540 u8 reserved_at_8[0x18];
e281682b
SM		 3541
3542 u8 syndrome[0x20];
3543
b4ff3a36 3544 u8 reserved_at_40[0x40];
e281682b
SM		 3545};
3546
3547struct mlx5_ifc_sqd2rts_qp_in_bits {
3548 u8 opcode[0x10];
4ac63ec7 3549 u8 uid[0x10];
e281682b 3550
b4ff3a36 3551 u8 reserved_at_20[0x10];
e281682b
SM		 3552 u8 op_mod[0x10];
3553
b4ff3a36 3554 u8 reserved_at_40[0x8];
e281682b
SM		 3555 u8 qpn[0x18];
3556
b4ff3a36 3557 u8 reserved_at_60[0x20];
e281682b
SM		 3558
3559 u8 opt_param_mask[0x20];
3560
b4ff3a36 3561 u8 reserved_at_a0[0x20];
e281682b
SM		 3562
3563 struct mlx5_ifc_qpc_bits qpc;
3564
b4ff3a36 3565 u8 reserved_at_800[0x80];
e281682b
SM		 3566};
3567
3568struct mlx5_ifc_set_roce_address_out_bits {
3569 u8 status[0x8];
b4ff3a36 3570 u8 reserved_at_8[0x18];
e281682b
SM		 3571
3572 u8 syndrome[0x20];
3573
b4ff3a36 3574 u8 reserved_at_40[0x40];
e281682b
SM		 3575};
3576
3577struct mlx5_ifc_set_roce_address_in_bits {
3578 u8 opcode[0x10];
b4ff3a36 3579 u8 reserved_at_10[0x10];
e281682b 3580
b4ff3a36 3581 u8 reserved_at_20[0x10];
e281682b
SM		 3582 u8 op_mod[0x10];
3583
3584 u8 roce_address_index[0x10];
32f69e4b
DJ		 3585 u8 reserved_at_50[0xc];
3586 u8 vhca_port_num[0x4];
e281682b 3587
b4ff3a36 3588 u8 reserved_at_60[0x20];
e281682b
SM		 3589
3590 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3591};
3592
3593struct mlx5_ifc_set_mad_demux_out_bits {
3594 u8 status[0x8];
b4ff3a36 3595 u8 reserved_at_8[0x18];
e281682b
SM		 3596
3597 u8 syndrome[0x20];
3598
b4ff3a36 3599 u8 reserved_at_40[0x40];
e281682b
SM		 3600};
3601
3602enum {
3603 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3604 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3605};
3606
3607struct mlx5_ifc_set_mad_demux_in_bits {
3608 u8 opcode[0x10];
b4ff3a36 3609 u8 reserved_at_10[0x10];
e281682b 3610
b4ff3a36 3611 u8 reserved_at_20[0x10];
e281682b
SM		 3612 u8 op_mod[0x10];
3613
b4ff3a36 3614 u8 reserved_at_40[0x20];
e281682b 3615
b4ff3a36 3616 u8 reserved_at_60[0x6];
e281682b 3617 u8 demux_mode[0x2];
b4ff3a36 3618 u8 reserved_at_68[0x18];
e281682b
SM		 3619};
3620
3621struct mlx5_ifc_set_l2_table_entry_out_bits {
3622 u8 status[0x8];
b4ff3a36 3623 u8 reserved_at_8[0x18];
e281682b
SM		 3624
3625 u8 syndrome[0x20];
3626
b4ff3a36 3627 u8 reserved_at_40[0x40];
e281682b
SM		 3628};
3629
3630struct mlx5_ifc_set_l2_table_entry_in_bits {
3631 u8 opcode[0x10];
b4ff3a36 3632 u8 reserved_at_10[0x10];
e281682b 3633
b4ff3a36 3634 u8 reserved_at_20[0x10];
e281682b
SM		 3635 u8 op_mod[0x10];
3636
b4ff3a36 3637 u8 reserved_at_40[0x60];
e281682b 3638
b4ff3a36 3639 u8 reserved_at_a0[0x8];
e281682b
SM		 3640 u8 table_index[0x18];
3641
b4ff3a36 3642 u8 reserved_at_c0[0x20];
e281682b 3643
b4ff3a36 3644 u8 reserved_at_e0[0x13];
e281682b
SM		 3645 u8 vlan_valid[0x1];
3646 u8 vlan[0xc];
3647
3648 struct mlx5_ifc_mac_address_layout_bits mac_address;
3649
b4ff3a36 3650 u8 reserved_at_140[0xc0];
e281682b
SM		 3651};
3652
3653struct mlx5_ifc_set_issi_out_bits {
3654 u8 status[0x8];
b4ff3a36 3655 u8 reserved_at_8[0x18];
e281682b
SM		 3656
3657 u8 syndrome[0x20];
3658
b4ff3a36 3659 u8 reserved_at_40[0x40];
e281682b
SM		 3660};
3661
3662struct mlx5_ifc_set_issi_in_bits {
3663 u8 opcode[0x10];
b4ff3a36 3664 u8 reserved_at_10[0x10];
e281682b 3665
b4ff3a36 3666 u8 reserved_at_20[0x10];
e281682b
SM		 3667 u8 op_mod[0x10];
3668
b4ff3a36 3669 u8 reserved_at_40[0x10];
e281682b
SM		 3670 u8 current_issi[0x10];
3671
b4ff3a36 3672 u8 reserved_at_60[0x20];
e281682b
SM		 3673};
3674
3675struct mlx5_ifc_set_hca_cap_out_bits {
3676 u8 status[0x8];
b4ff3a36 3677 u8 reserved_at_8[0x18];
e281682b
SM		 3678
3679 u8 syndrome[0x20];
3680
b4ff3a36 3681 u8 reserved_at_40[0x40];
e281682b
SM		 3682};
3683
3684struct mlx5_ifc_set_hca_cap_in_bits {
3685 u8 opcode[0x10];
b4ff3a36 3686 u8 reserved_at_10[0x10];
e281682b 3687
b4ff3a36 3688 u8 reserved_at_20[0x10];
e281682b
SM		 3689 u8 op_mod[0x10];
3690
b4ff3a36 3691 u8 reserved_at_40[0x40];
e281682b
SM		 3692
3693 union mlx5_ifc_hca_cap_union_bits capability;
3694};
3695
26a81453
MG		 3696enum {
3697 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3698 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3699 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3700 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3701};
3702
e281682b
SM		 3703struct mlx5_ifc_set_fte_out_bits {
3704 u8 status[0x8];
b4ff3a36 3705 u8 reserved_at_8[0x18];
e281682b
SM		 3706
3707 u8 syndrome[0x20];
3708
b4ff3a36 3709 u8 reserved_at_40[0x40];
e281682b
SM		 3710};
3711
3712struct mlx5_ifc_set_fte_in_bits {
3713 u8 opcode[0x10];
b4ff3a36 3714 u8 reserved_at_10[0x10];
e281682b 3715
b4ff3a36 3716 u8 reserved_at_20[0x10];
e281682b
SM		 3717 u8 op_mod[0x10];
3718
7d5e1423
SM		 3719 u8 other_vport[0x1];
3720 u8 reserved_at_41[0xf];
3721 u8 vport_number[0x10];
3722
3723 u8 reserved_at_60[0x20];
e281682b
SM		 3724
3725 u8 table_type[0x8];
b4ff3a36 3726 u8 reserved_at_88[0x18];
e281682b 3727
b4ff3a36 3728 u8 reserved_at_a0[0x8];
e281682b
SM		 3729 u8 table_id[0x18];
3730
b4ff3a36 3731 u8 reserved_at_c0[0x18];
26a81453
MG		 3732 u8 modify_enable_mask[0x8];
3733
b4ff3a36 3734 u8 reserved_at_e0[0x20];
e281682b
SM		 3735
3736 u8 flow_index[0x20];
3737
b4ff3a36 3738 u8 reserved_at_120[0xe0];
e281682b
SM		 3739
3740 struct mlx5_ifc_flow_context_bits flow_context;
3741};
3742
3743struct mlx5_ifc_rts2rts_qp_out_bits {
3744 u8 status[0x8];
b4ff3a36 3745 u8 reserved_at_8[0x18];
e281682b
SM		 3746
3747 u8 syndrome[0x20];
3748
b4ff3a36 3749 u8 reserved_at_40[0x40];
e281682b
SM		 3750};
3751
3752struct mlx5_ifc_rts2rts_qp_in_bits {
3753 u8 opcode[0x10];
4ac63ec7 3754 u8 uid[0x10];
e281682b 3755
b4ff3a36 3756 u8 reserved_at_20[0x10];
e281682b
SM		 3757 u8 op_mod[0x10];
3758
b4ff3a36 3759 u8 reserved_at_40[0x8];
e281682b
SM		 3760 u8 qpn[0x18];
3761
b4ff3a36 3762 u8 reserved_at_60[0x20];
e281682b
SM		 3763
3764 u8 opt_param_mask[0x20];
3765
b4ff3a36 3766 u8 reserved_at_a0[0x20];
e281682b
SM		 3767
3768 struct mlx5_ifc_qpc_bits qpc;
3769
b4ff3a36 3770 u8 reserved_at_800[0x80];
e281682b
SM		 3771};
3772
3773struct mlx5_ifc_rtr2rts_qp_out_bits {
3774 u8 status[0x8];
b4ff3a36 3775 u8 reserved_at_8[0x18];
e281682b
SM		 3776
3777 u8 syndrome[0x20];
3778
b4ff3a36 3779 u8 reserved_at_40[0x40];
e281682b
SM		 3780};
3781
3782struct mlx5_ifc_rtr2rts_qp_in_bits {
3783 u8 opcode[0x10];
4ac63ec7 3784 u8 uid[0x10];
e281682b 3785
b4ff3a36 3786 u8 reserved_at_20[0x10];
e281682b
SM		 3787 u8 op_mod[0x10];
3788
b4ff3a36 3789 u8 reserved_at_40[0x8];
e281682b
SM		 3790 u8 qpn[0x18];
3791
b4ff3a36 3792 u8 reserved_at_60[0x20];
e281682b
SM		 3793
3794 u8 opt_param_mask[0x20];
3795
b4ff3a36 3796 u8 reserved_at_a0[0x20];
e281682b
SM		 3797
3798 struct mlx5_ifc_qpc_bits qpc;
3799
b4ff3a36 3800 u8 reserved_at_800[0x80];
e281682b
SM		 3801};
3802
3803struct mlx5_ifc_rst2init_qp_out_bits {
3804 u8 status[0x8];
b4ff3a36 3805 u8 reserved_at_8[0x18];
e281682b
SM		 3806
3807 u8 syndrome[0x20];
3808
b4ff3a36 3809 u8 reserved_at_40[0x40];
e281682b
SM		 3810};
3811
3812struct mlx5_ifc_rst2init_qp_in_bits {
3813 u8 opcode[0x10];
4ac63ec7 3814 u8 uid[0x10];
e281682b 3815
b4ff3a36 3816 u8 reserved_at_20[0x10];
e281682b
SM		 3817 u8 op_mod[0x10];
3818
b4ff3a36 3819 u8 reserved_at_40[0x8];
e281682b
SM		 3820 u8 qpn[0x18];
3821
b4ff3a36 3822 u8 reserved_at_60[0x20];
e281682b
SM		 3823
3824 u8 opt_param_mask[0x20];
3825
b4ff3a36 3826 u8 reserved_at_a0[0x20];
e281682b
SM		 3827
3828 struct mlx5_ifc_qpc_bits qpc;
3829
b4ff3a36 3830 u8 reserved_at_800[0x80];
e281682b
SM		 3831};
3832
7486216b
SM		 3833struct mlx5_ifc_query_xrq_out_bits {
3834 u8 status[0x8];
3835 u8 reserved_at_8[0x18];
3836
3837 u8 syndrome[0x20];
3838
3839 u8 reserved_at_40[0x40];
3840
3841 struct mlx5_ifc_xrqc_bits xrq_context;
3842};
3843
3844struct mlx5_ifc_query_xrq_in_bits {
3845 u8 opcode[0x10];
3846 u8 reserved_at_10[0x10];
3847
3848 u8 reserved_at_20[0x10];
3849 u8 op_mod[0x10];
3850
3851 u8 reserved_at_40[0x8];
3852 u8 xrqn[0x18];
3853
3854 u8 reserved_at_60[0x20];
3855};
3856
e281682b
SM		 3857struct mlx5_ifc_query_xrc_srq_out_bits {
3858 u8 status[0x8];
b4ff3a36 3859 u8 reserved_at_8[0x18];
e281682b
SM		 3860
3861 u8 syndrome[0x20];
3862
b4ff3a36 3863 u8 reserved_at_40[0x40];
e281682b
SM		 3864
3865 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3866
b4ff3a36 3867 u8 reserved_at_280[0x600];
e281682b
SM		 3868
3869 u8 pas[0][0x40];
3870};
3871
3872struct mlx5_ifc_query_xrc_srq_in_bits {
3873 u8 opcode[0x10];
b4ff3a36 3874 u8 reserved_at_10[0x10];
e281682b 3875
b4ff3a36 3876 u8 reserved_at_20[0x10];
e281682b
SM		 3877 u8 op_mod[0x10];
3878
b4ff3a36 3879 u8 reserved_at_40[0x8];
e281682b
SM		 3880 u8 xrc_srqn[0x18];
3881
b4ff3a36 3882 u8 reserved_at_60[0x20];
e281682b
SM		 3883};
3884
3885enum {
3886 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3887 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3888};
3889
3890struct mlx5_ifc_query_vport_state_out_bits {
3891 u8 status[0x8];
b4ff3a36 3892 u8 reserved_at_8[0x18];
e281682b
SM		 3893
3894 u8 syndrome[0x20];
3895
b4ff3a36 3896 u8 reserved_at_40[0x20];
e281682b 3897
b4ff3a36 3898 u8 reserved_at_60[0x18];
e281682b
SM		 3899 u8 admin_state[0x4];
3900 u8 state[0x4];
3901};
3902
3903enum {
cc9c82a8
EBE		 3904 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
3905 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3906};
3907
fd4572b3
ED		 3908struct mlx5_ifc_arm_monitor_counter_in_bits {
3909 u8 opcode[0x10];
3910 u8 uid[0x10];
3911
3912 u8 reserved_at_20[0x10];
3913 u8 op_mod[0x10];
3914
3915 u8 reserved_at_40[0x20];
3916
3917 u8 reserved_at_60[0x20];
3918};
3919
3920struct mlx5_ifc_arm_monitor_counter_out_bits {
3921 u8 status[0x8];
3922 u8 reserved_at_8[0x18];
3923
3924 u8 syndrome[0x20];
3925
3926 u8 reserved_at_40[0x40];
3927};
3928
3929enum {
3930 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
3931 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
3932};
3933
3934enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 3935 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
3936 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
3937 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
3938 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
3939 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
3940 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 3941};
3942
3943enum {
4c8b8518 3944 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 3945};
3946
3947struct mlx5_ifc_monitor_counter_output_bits {
3948 u8 reserved_at_0[0x4];
3949 u8 type[0x4];
3950 u8 reserved_at_8[0x8];
3951 u8 counter[0x10];
3952
3953 u8 counter_group_id[0x20];
3954};
3955
3956#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
3957#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
3958#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
3959 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
3960
3961struct mlx5_ifc_set_monitor_counter_in_bits {
3962 u8 opcode[0x10];
3963 u8 uid[0x10];
3964
3965 u8 reserved_at_20[0x10];
3966 u8 op_mod[0x10];
3967
3968 u8 reserved_at_40[0x10];
3969 u8 num_of_counters[0x10];
3970
3971 u8 reserved_at_60[0x20];
3972
3973 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
3974};
3975
3976struct mlx5_ifc_set_monitor_counter_out_bits {
3977 u8 status[0x8];
3978 u8 reserved_at_8[0x18];
3979
3980 u8 syndrome[0x20];
3981
3982 u8 reserved_at_40[0x40];
3983};
3984
e281682b
SM		 3985struct mlx5_ifc_query_vport_state_in_bits {
3986 u8 opcode[0x10];
b4ff3a36 3987 u8 reserved_at_10[0x10];
e281682b 3988
b4ff3a36 3989 u8 reserved_at_20[0x10];
e281682b
SM		 3990 u8 op_mod[0x10];
3991
3992 u8 other_vport[0x1];
b4ff3a36 3993 u8 reserved_at_41[0xf];
e281682b
SM		 3994 u8 vport_number[0x10];
3995
b4ff3a36 3996 u8 reserved_at_60[0x20];
e281682b
SM		 3997};
3998
61c5b5c9
MS		 3999struct mlx5_ifc_query_vnic_env_out_bits {
4000 u8 status[0x8];
4001 u8 reserved_at_8[0x18];
4002
4003 u8 syndrome[0x20];
4004
4005 u8 reserved_at_40[0x40];
4006
4007 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4008};
4009
4010enum {
4011 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4012};
4013
4014struct mlx5_ifc_query_vnic_env_in_bits {
4015 u8 opcode[0x10];
4016 u8 reserved_at_10[0x10];
4017
4018 u8 reserved_at_20[0x10];
4019 u8 op_mod[0x10];
4020
4021 u8 other_vport[0x1];
4022 u8 reserved_at_41[0xf];
4023 u8 vport_number[0x10];
4024
4025 u8 reserved_at_60[0x20];
4026};
4027
e281682b
SM		 4028struct mlx5_ifc_query_vport_counter_out_bits {
4029 u8 status[0x8];
b4ff3a36 4030 u8 reserved_at_8[0x18];
e281682b
SM		 4031
4032 u8 syndrome[0x20];
4033
b4ff3a36 4034 u8 reserved_at_40[0x40];
e281682b
SM		 4035
4036 struct mlx5_ifc_traffic_counter_bits received_errors;
4037
4038 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4039
4040 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4041
4042 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4043
4044 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4045
4046 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4047
4048 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4049
4050 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4051
4052 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4053
4054 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4055
4056 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4057
4058 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4059
b4ff3a36 4060 u8 reserved_at_680[0xa00];
e281682b
SM		 4061};
4062
4063enum {
4064 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4065};
4066
4067struct mlx5_ifc_query_vport_counter_in_bits {
4068 u8 opcode[0x10];
b4ff3a36 4069 u8 reserved_at_10[0x10];
e281682b 4070
b4ff3a36 4071 u8 reserved_at_20[0x10];
e281682b
SM		 4072 u8 op_mod[0x10];
4073
4074 u8 other_vport[0x1];
b54ba277
MY		 4075 u8 reserved_at_41[0xb];
4076 u8 port_num[0x4];
e281682b
SM		 4077 u8 vport_number[0x10];
4078
b4ff3a36 4079 u8 reserved_at_60[0x60];
e281682b
SM		 4080
4081 u8 clear[0x1];
b4ff3a36 4082 u8 reserved_at_c1[0x1f];
e281682b 4083
b4ff3a36 4084 u8 reserved_at_e0[0x20];
e281682b
SM		 4085};
4086
4087struct mlx5_ifc_query_tis_out_bits {
4088 u8 status[0x8];
b4ff3a36 4089 u8 reserved_at_8[0x18];
e281682b
SM		 4090
4091 u8 syndrome[0x20];
4092
b4ff3a36 4093 u8 reserved_at_40[0x40];
e281682b
SM		 4094
4095 struct mlx5_ifc_tisc_bits tis_context;
4096};
4097
4098struct mlx5_ifc_query_tis_in_bits {
4099 u8 opcode[0x10];
b4ff3a36 4100 u8 reserved_at_10[0x10];
e281682b 4101
b4ff3a36 4102 u8 reserved_at_20[0x10];
e281682b
SM		 4103 u8 op_mod[0x10];
4104
b4ff3a36 4105 u8 reserved_at_40[0x8];
e281682b
SM		 4106 u8 tisn[0x18];
4107
b4ff3a36 4108 u8 reserved_at_60[0x20];
e281682b
SM		 4109};
4110
4111struct mlx5_ifc_query_tir_out_bits {
4112 u8 status[0x8];
b4ff3a36 4113 u8 reserved_at_8[0x18];
e281682b
SM		 4114
4115 u8 syndrome[0x20];
4116
b4ff3a36 4117 u8 reserved_at_40[0xc0];
e281682b
SM		 4118
4119 struct mlx5_ifc_tirc_bits tir_context;
4120};
4121
4122struct mlx5_ifc_query_tir_in_bits {
4123 u8 opcode[0x10];
b4ff3a36 4124 u8 reserved_at_10[0x10];
e281682b 4125
b4ff3a36 4126 u8 reserved_at_20[0x10];
e281682b
SM		 4127 u8 op_mod[0x10];
4128
b4ff3a36 4129 u8 reserved_at_40[0x8];
e281682b
SM		 4130 u8 tirn[0x18];
4131
b4ff3a36 4132 u8 reserved_at_60[0x20];
e281682b
SM		 4133};
4134
4135struct mlx5_ifc_query_srq_out_bits {
4136 u8 status[0x8];
b4ff3a36 4137 u8 reserved_at_8[0x18];
e281682b
SM		 4138
4139 u8 syndrome[0x20];
4140
b4ff3a36 4141 u8 reserved_at_40[0x40];
e281682b
SM		 4142
4143 struct mlx5_ifc_srqc_bits srq_context_entry;
4144
b4ff3a36 4145 u8 reserved_at_280[0x600];
e281682b
SM		 4146
4147 u8 pas[0][0x40];
4148};
4149
4150struct mlx5_ifc_query_srq_in_bits {
4151 u8 opcode[0x10];
b4ff3a36 4152 u8 reserved_at_10[0x10];
e281682b 4153
b4ff3a36 4154 u8 reserved_at_20[0x10];
e281682b
SM		 4155 u8 op_mod[0x10];
4156
b4ff3a36 4157 u8 reserved_at_40[0x8];
e281682b
SM		 4158 u8 srqn[0x18];
4159
b4ff3a36 4160 u8 reserved_at_60[0x20];
e281682b
SM		 4161};
4162
4163struct mlx5_ifc_query_sq_out_bits {
4164 u8 status[0x8];
b4ff3a36 4165 u8 reserved_at_8[0x18];
e281682b
SM		 4166
4167 u8 syndrome[0x20];
4168
b4ff3a36 4169 u8 reserved_at_40[0xc0];
e281682b
SM		 4170
4171 struct mlx5_ifc_sqc_bits sq_context;
4172};
4173
4174struct mlx5_ifc_query_sq_in_bits {
4175 u8 opcode[0x10];
b4ff3a36 4176 u8 reserved_at_10[0x10];
e281682b 4177
b4ff3a36 4178 u8 reserved_at_20[0x10];
e281682b
SM		 4179 u8 op_mod[0x10];
4180
b4ff3a36 4181 u8 reserved_at_40[0x8];
e281682b
SM		 4182 u8 sqn[0x18];
4183
b4ff3a36 4184 u8 reserved_at_60[0x20];
e281682b
SM		 4185};
4186
4187struct mlx5_ifc_query_special_contexts_out_bits {
4188 u8 status[0x8];
b4ff3a36 4189 u8 reserved_at_8[0x18];
e281682b
SM		 4190
4191 u8 syndrome[0x20];
4192
ec22eb53 4193 u8 dump_fill_mkey[0x20];
e281682b
SM		 4194
4195 u8 resd_lkey[0x20];
bcda1aca
AK		 4196
4197 u8 null_mkey[0x20];
4198
4199 u8 reserved_at_a0[0x60];
e281682b
SM		 4200};
4201
4202struct mlx5_ifc_query_special_contexts_in_bits {
4203 u8 opcode[0x10];
b4ff3a36 4204 u8 reserved_at_10[0x10];
e281682b 4205
b4ff3a36 4206 u8 reserved_at_20[0x10];
e281682b
SM		 4207 u8 op_mod[0x10];
4208
b4ff3a36 4209 u8 reserved_at_40[0x40];
e281682b
SM		 4210};
4211
813f8540
MHY		 4212struct mlx5_ifc_query_scheduling_element_out_bits {
4213 u8 opcode[0x10];
4214 u8 reserved_at_10[0x10];
4215
4216 u8 reserved_at_20[0x10];
4217 u8 op_mod[0x10];
4218
4219 u8 reserved_at_40[0xc0];
4220
4221 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4222
4223 u8 reserved_at_300[0x100];
4224};
4225
4226enum {
4227 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4228};
4229
4230struct mlx5_ifc_query_scheduling_element_in_bits {
4231 u8 opcode[0x10];
4232 u8 reserved_at_10[0x10];
4233
4234 u8 reserved_at_20[0x10];
4235 u8 op_mod[0x10];
4236
4237 u8 scheduling_hierarchy[0x8];
4238 u8 reserved_at_48[0x18];
4239
4240 u8 scheduling_element_id[0x20];
4241
4242 u8 reserved_at_80[0x180];
4243};
4244
e281682b
SM		 4245struct mlx5_ifc_query_rqt_out_bits {
4246 u8 status[0x8];
b4ff3a36 4247 u8 reserved_at_8[0x18];
e281682b
SM		 4248
4249 u8 syndrome[0x20];
4250
b4ff3a36 4251 u8 reserved_at_40[0xc0];
e281682b
SM		 4252
4253 struct mlx5_ifc_rqtc_bits rqt_context;
4254};
4255
4256struct mlx5_ifc_query_rqt_in_bits {
4257 u8 opcode[0x10];
b4ff3a36 4258 u8 reserved_at_10[0x10];
e281682b 4259
b4ff3a36 4260 u8 reserved_at_20[0x10];
e281682b
SM		 4261 u8 op_mod[0x10];
4262
b4ff3a36 4263 u8 reserved_at_40[0x8];
e281682b
SM		 4264 u8 rqtn[0x18];
4265
b4ff3a36 4266 u8 reserved_at_60[0x20];
e281682b
SM		 4267};
4268
4269struct mlx5_ifc_query_rq_out_bits {
4270 u8 status[0x8];
b4ff3a36 4271 u8 reserved_at_8[0x18];
e281682b
SM		 4272
4273 u8 syndrome[0x20];
4274
b4ff3a36 4275 u8 reserved_at_40[0xc0];
e281682b
SM		 4276
4277 struct mlx5_ifc_rqc_bits rq_context;
4278};
4279
4280struct mlx5_ifc_query_rq_in_bits {
4281 u8 opcode[0x10];
b4ff3a36 4282 u8 reserved_at_10[0x10];
e281682b 4283
b4ff3a36 4284 u8 reserved_at_20[0x10];
e281682b
SM		 4285 u8 op_mod[0x10];
4286
b4ff3a36 4287 u8 reserved_at_40[0x8];
e281682b
SM		 4288 u8 rqn[0x18];
4289
b4ff3a36 4290 u8 reserved_at_60[0x20];
e281682b
SM		 4291};
4292
4293struct mlx5_ifc_query_roce_address_out_bits {
4294 u8 status[0x8];
b4ff3a36 4295 u8 reserved_at_8[0x18];
e281682b
SM		 4296
4297 u8 syndrome[0x20];
4298
b4ff3a36 4299 u8 reserved_at_40[0x40];
e281682b
SM		 4300
4301 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4302};
4303
4304struct mlx5_ifc_query_roce_address_in_bits {
4305 u8 opcode[0x10];
b4ff3a36 4306 u8 reserved_at_10[0x10];
e281682b 4307
b4ff3a36 4308 u8 reserved_at_20[0x10];
e281682b
SM		 4309 u8 op_mod[0x10];
4310
4311 u8 roce_address_index[0x10];
32f69e4b
DJ		 4312 u8 reserved_at_50[0xc];
4313 u8 vhca_port_num[0x4];
e281682b 4314
b4ff3a36 4315 u8 reserved_at_60[0x20];
e281682b
SM		 4316};
4317
4318struct mlx5_ifc_query_rmp_out_bits {
4319 u8 status[0x8];
b4ff3a36 4320 u8 reserved_at_8[0x18];
e281682b
SM		 4321
4322 u8 syndrome[0x20];
4323
b4ff3a36 4324 u8 reserved_at_40[0xc0];
e281682b
SM		 4325
4326 struct mlx5_ifc_rmpc_bits rmp_context;
4327};
4328
4329struct mlx5_ifc_query_rmp_in_bits {
4330 u8 opcode[0x10];
b4ff3a36 4331 u8 reserved_at_10[0x10];
e281682b 4332
b4ff3a36 4333 u8 reserved_at_20[0x10];
e281682b
SM		 4334 u8 op_mod[0x10];
4335
b4ff3a36 4336 u8 reserved_at_40[0x8];
e281682b
SM		 4337 u8 rmpn[0x18];
4338
b4ff3a36 4339 u8 reserved_at_60[0x20];
e281682b
SM		 4340};
4341
4342struct mlx5_ifc_query_qp_out_bits {
4343 u8 status[0x8];
b4ff3a36 4344 u8 reserved_at_8[0x18];
e281682b
SM		 4345
4346 u8 syndrome[0x20];
4347
b4ff3a36 4348 u8 reserved_at_40[0x40];
e281682b
SM		 4349
4350 u8 opt_param_mask[0x20];
4351
b4ff3a36 4352 u8 reserved_at_a0[0x20];
e281682b
SM		 4353
4354 struct mlx5_ifc_qpc_bits qpc;
4355
b4ff3a36 4356 u8 reserved_at_800[0x80];
e281682b
SM		 4357
4358 u8 pas[0][0x40];
4359};
4360
4361struct mlx5_ifc_query_qp_in_bits {
4362 u8 opcode[0x10];
b4ff3a36 4363 u8 reserved_at_10[0x10];
e281682b 4364
b4ff3a36 4365 u8 reserved_at_20[0x10];
e281682b
SM		 4366 u8 op_mod[0x10];
4367
b4ff3a36 4368 u8 reserved_at_40[0x8];
e281682b
SM		 4369 u8 qpn[0x18];
4370
b4ff3a36 4371 u8 reserved_at_60[0x20];
e281682b
SM		 4372};
4373
4374struct mlx5_ifc_query_q_counter_out_bits {
4375 u8 status[0x8];
b4ff3a36 4376 u8 reserved_at_8[0x18];
e281682b
SM		 4377
4378 u8 syndrome[0x20];
4379
b4ff3a36 4380 u8 reserved_at_40[0x40];
e281682b
SM		 4381
4382 u8 rx_write_requests[0x20];
4383
b4ff3a36 4384 u8 reserved_at_a0[0x20];
e281682b
SM		 4385
4386 u8 rx_read_requests[0x20];
4387
b4ff3a36 4388 u8 reserved_at_e0[0x20];
e281682b
SM		 4389
4390 u8 rx_atomic_requests[0x20];
4391
b4ff3a36 4392 u8 reserved_at_120[0x20];
e281682b
SM		 4393
4394 u8 rx_dct_connect[0x20];
4395
b4ff3a36 4396 u8 reserved_at_160[0x20];
e281682b
SM		 4397
4398 u8 out_of_buffer[0x20];
4399
b4ff3a36 4400 u8 reserved_at_1a0[0x20];
e281682b
SM		 4401
4402 u8 out_of_sequence[0x20];
4403
7486216b
SM		 4404 u8 reserved_at_1e0[0x20];
4405
4406 u8 duplicate_request[0x20];
4407
4408 u8 reserved_at_220[0x20];
4409
4410 u8 rnr_nak_retry_err[0x20];
4411
4412 u8 reserved_at_260[0x20];
4413
4414 u8 packet_seq_err[0x20];
4415
4416 u8 reserved_at_2a0[0x20];
4417
4418 u8 implied_nak_seq_err[0x20];
4419
4420 u8 reserved_at_2e0[0x20];
4421
4422 u8 local_ack_timeout_err[0x20];
4423
58dcb60a
PP		 4424 u8 reserved_at_320[0xa0];
4425
4426 u8 resp_local_length_error[0x20];
4427
4428 u8 req_local_length_error[0x20];
4429
4430 u8 resp_local_qp_error[0x20];
4431
4432 u8 local_operation_error[0x20];
4433
4434 u8 resp_local_protection[0x20];
4435
4436 u8 req_local_protection[0x20];
4437
4438 u8 resp_cqe_error[0x20];
4439
4440 u8 req_cqe_error[0x20];
4441
4442 u8 req_mw_binding[0x20];
4443
4444 u8 req_bad_response[0x20];
4445
4446 u8 req_remote_invalid_request[0x20];
4447
4448 u8 resp_remote_invalid_request[0x20];
4449
4450 u8 req_remote_access_errors[0x20];
4451
4452 u8 resp_remote_access_errors[0x20];
4453
4454 u8 req_remote_operation_errors[0x20];
4455
4456 u8 req_transport_retries_exceeded[0x20];
4457
4458 u8 cq_overflow[0x20];
4459
4460 u8 resp_cqe_flush_error[0x20];
4461
4462 u8 req_cqe_flush_error[0x20];
4463
4464 u8 reserved_at_620[0x1e0];
e281682b
SM		 4465};
4466
4467struct mlx5_ifc_query_q_counter_in_bits {
4468 u8 opcode[0x10];
b4ff3a36 4469 u8 reserved_at_10[0x10];
e281682b 4470
b4ff3a36 4471 u8 reserved_at_20[0x10];
e281682b
SM		 4472 u8 op_mod[0x10];
4473
b4ff3a36 4474 u8 reserved_at_40[0x80];
e281682b
SM		 4475
4476 u8 clear[0x1];
b4ff3a36 4477 u8 reserved_at_c1[0x1f];
e281682b 4478
b4ff3a36 4479 u8 reserved_at_e0[0x18];
e281682b
SM		 4480 u8 counter_set_id[0x8];
4481};
4482
4483struct mlx5_ifc_query_pages_out_bits {
4484 u8 status[0x8];
b4ff3a36 4485 u8 reserved_at_8[0x18];
e281682b
SM		 4486
4487 u8 syndrome[0x20];
4488
591905ba
BW		 4489 u8 embedded_cpu_function[0x1];
4490 u8 reserved_at_41[0xf];
e281682b
SM		 4491 u8 function_id[0x10];
4492
4493 u8 num_pages[0x20];
4494};
4495
4496enum {
4497 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4498 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4499 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4500};
4501
4502struct mlx5_ifc_query_pages_in_bits {
4503 u8 opcode[0x10];
b4ff3a36 4504 u8 reserved_at_10[0x10];
e281682b 4505
b4ff3a36 4506 u8 reserved_at_20[0x10];
e281682b
SM		 4507 u8 op_mod[0x10];
4508
591905ba
BW		 4509 u8 embedded_cpu_function[0x1];
4510 u8 reserved_at_41[0xf];
e281682b
SM		 4511 u8 function_id[0x10];
4512
b4ff3a36 4513 u8 reserved_at_60[0x20];
e281682b
SM		 4514};
4515
4516struct mlx5_ifc_query_nic_vport_context_out_bits {
4517 u8 status[0x8];
b4ff3a36 4518 u8 reserved_at_8[0x18];
e281682b
SM		 4519
4520 u8 syndrome[0x20];
4521
b4ff3a36 4522 u8 reserved_at_40[0x40];
e281682b
SM		 4523
4524 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4525};
4526
4527struct mlx5_ifc_query_nic_vport_context_in_bits {
4528 u8 opcode[0x10];
b4ff3a36 4529 u8 reserved_at_10[0x10];
e281682b 4530
b4ff3a36 4531 u8 reserved_at_20[0x10];
e281682b
SM		 4532 u8 op_mod[0x10];
4533
4534 u8 other_vport[0x1];
b4ff3a36 4535 u8 reserved_at_41[0xf];
e281682b
SM		 4536 u8 vport_number[0x10];
4537
b4ff3a36 4538 u8 reserved_at_60[0x5];
e281682b 4539 u8 allowed_list_type[0x3];
b4ff3a36 4540 u8 reserved_at_68[0x18];
e281682b
SM		 4541};
4542
4543struct mlx5_ifc_query_mkey_out_bits {
4544 u8 status[0x8];
b4ff3a36 4545 u8 reserved_at_8[0x18];
e281682b
SM		 4546
4547 u8 syndrome[0x20];
4548
b4ff3a36 4549 u8 reserved_at_40[0x40];
e281682b
SM		 4550
4551 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4552
b4ff3a36 4553 u8 reserved_at_280[0x600];
e281682b
SM		 4554
4555 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4556
4557 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4558};
4559
4560struct mlx5_ifc_query_mkey_in_bits {
4561 u8 opcode[0x10];
b4ff3a36 4562 u8 reserved_at_10[0x10];
e281682b 4563
b4ff3a36 4564 u8 reserved_at_20[0x10];
e281682b
SM		 4565 u8 op_mod[0x10];
4566
b4ff3a36 4567 u8 reserved_at_40[0x8];
e281682b
SM		 4568 u8 mkey_index[0x18];
4569
4570 u8 pg_access[0x1];
b4ff3a36 4571 u8 reserved_at_61[0x1f];
e281682b
SM		 4572};
4573
4574struct mlx5_ifc_query_mad_demux_out_bits {
4575 u8 status[0x8];
b4ff3a36 4576 u8 reserved_at_8[0x18];
e281682b
SM		 4577
4578 u8 syndrome[0x20];
4579
b4ff3a36 4580 u8 reserved_at_40[0x40];
e281682b
SM		 4581
4582 u8 mad_dumux_parameters_block[0x20];
4583};
4584
4585struct mlx5_ifc_query_mad_demux_in_bits {
4586 u8 opcode[0x10];
b4ff3a36 4587 u8 reserved_at_10[0x10];
e281682b 4588
b4ff3a36 4589 u8 reserved_at_20[0x10];
e281682b
SM		 4590 u8 op_mod[0x10];
4591
b4ff3a36 4592 u8 reserved_at_40[0x40];
e281682b
SM		 4593};
4594
4595struct mlx5_ifc_query_l2_table_entry_out_bits {
4596 u8 status[0x8];
b4ff3a36 4597 u8 reserved_at_8[0x18];
e281682b
SM		 4598
4599 u8 syndrome[0x20];
4600
b4ff3a36 4601 u8 reserved_at_40[0xa0];
e281682b 4602
b4ff3a36 4603 u8 reserved_at_e0[0x13];
e281682b
SM		 4604 u8 vlan_valid[0x1];
4605 u8 vlan[0xc];
4606
4607 struct mlx5_ifc_mac_address_layout_bits mac_address;
4608
b4ff3a36 4609 u8 reserved_at_140[0xc0];
e281682b
SM		 4610};
4611
4612struct mlx5_ifc_query_l2_table_entry_in_bits {
4613 u8 opcode[0x10];
b4ff3a36 4614 u8 reserved_at_10[0x10];
e281682b 4615
b4ff3a36 4616 u8 reserved_at_20[0x10];
e281682b
SM		 4617 u8 op_mod[0x10];
4618
b4ff3a36 4619 u8 reserved_at_40[0x60];
e281682b 4620
b4ff3a36 4621 u8 reserved_at_a0[0x8];
e281682b
SM		 4622 u8 table_index[0x18];
4623
b4ff3a36 4624 u8 reserved_at_c0[0x140];
e281682b
SM		 4625};
4626
4627struct mlx5_ifc_query_issi_out_bits {
4628 u8 status[0x8];
b4ff3a36 4629 u8 reserved_at_8[0x18];
e281682b
SM		 4630
4631 u8 syndrome[0x20];
4632
b4ff3a36 4633 u8 reserved_at_40[0x10];
e281682b
SM		 4634 u8 current_issi[0x10];
4635
b4ff3a36 4636 u8 reserved_at_60[0xa0];
e281682b 4637
b4ff3a36 4638 u8 reserved_at_100[76][0x8];
e281682b
SM		 4639 u8 supported_issi_dw0[0x20];
4640};
4641
4642struct mlx5_ifc_query_issi_in_bits {
4643 u8 opcode[0x10];
b4ff3a36 4644 u8 reserved_at_10[0x10];
e281682b 4645
b4ff3a36 4646 u8 reserved_at_20[0x10];
e281682b
SM		 4647 u8 op_mod[0x10];
4648
b4ff3a36 4649 u8 reserved_at_40[0x40];
e281682b
SM		 4650};
4651
0dbc6fe0
SM		 4652struct mlx5_ifc_set_driver_version_out_bits {
4653 u8 status[0x8];
4654 u8 reserved_0[0x18];
4655
4656 u8 syndrome[0x20];
4657 u8 reserved_1[0x40];
4658};
4659
4660struct mlx5_ifc_set_driver_version_in_bits {
4661 u8 opcode[0x10];
4662 u8 reserved_0[0x10];
4663
4664 u8 reserved_1[0x10];
4665 u8 op_mod[0x10];
4666
4667 u8 reserved_2[0x40];
4668 u8 driver_version[64][0x8];
4669};
4670
e281682b
SM		 4671struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4672 u8 status[0x8];
b4ff3a36 4673 u8 reserved_at_8[0x18];
e281682b
SM		 4674
4675 u8 syndrome[0x20];
4676
b4ff3a36 4677 u8 reserved_at_40[0x40];
e281682b
SM		 4678
4679 struct mlx5_ifc_pkey_bits pkey[0];
4680};
4681
4682struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4683 u8 opcode[0x10];
b4ff3a36 4684 u8 reserved_at_10[0x10];
e281682b 4685
b4ff3a36 4686 u8 reserved_at_20[0x10];
e281682b
SM		 4687 u8 op_mod[0x10];
4688
4689 u8 other_vport[0x1];
b4ff3a36 4690 u8 reserved_at_41[0xb];
707c4602 4691 u8 port_num[0x4];
e281682b
SM		 4692 u8 vport_number[0x10];
4693
b4ff3a36 4694 u8 reserved_at_60[0x10];
e281682b
SM		 4695 u8 pkey_index[0x10];
4696};
4697
eff901d3
EC		 4698enum {
4699 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4700 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4701 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4702};
4703
e281682b
SM		 4704struct mlx5_ifc_query_hca_vport_gid_out_bits {
4705 u8 status[0x8];
b4ff3a36 4706 u8 reserved_at_8[0x18];
e281682b
SM		 4707
4708 u8 syndrome[0x20];
4709
b4ff3a36 4710 u8 reserved_at_40[0x20];
e281682b
SM		 4711
4712 u8 gids_num[0x10];
b4ff3a36 4713 u8 reserved_at_70[0x10];
e281682b
SM		 4714
4715 struct mlx5_ifc_array128_auto_bits gid[0];
4716};
4717
4718struct mlx5_ifc_query_hca_vport_gid_in_bits {
4719 u8 opcode[0x10];
b4ff3a36 4720 u8 reserved_at_10[0x10];
e281682b 4721
b4ff3a36 4722 u8 reserved_at_20[0x10];
e281682b
SM		 4723 u8 op_mod[0x10];
4724
4725 u8 other_vport[0x1];
b4ff3a36 4726 u8 reserved_at_41[0xb];
707c4602 4727 u8 port_num[0x4];
e281682b
SM		 4728 u8 vport_number[0x10];
4729
b4ff3a36 4730 u8 reserved_at_60[0x10];
e281682b
SM		 4731 u8 gid_index[0x10];
4732};
4733
4734struct mlx5_ifc_query_hca_vport_context_out_bits {
4735 u8 status[0x8];
b4ff3a36 4736 u8 reserved_at_8[0x18];
e281682b
SM		 4737
4738 u8 syndrome[0x20];
4739
b4ff3a36 4740 u8 reserved_at_40[0x40];
e281682b
SM		 4741
4742 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4743};
4744
4745struct mlx5_ifc_query_hca_vport_context_in_bits {
4746 u8 opcode[0x10];
b4ff3a36 4747 u8 reserved_at_10[0x10];
e281682b 4748
b4ff3a36 4749 u8 reserved_at_20[0x10];
e281682b
SM		 4750 u8 op_mod[0x10];
4751
4752 u8 other_vport[0x1];
b4ff3a36 4753 u8 reserved_at_41[0xb];
707c4602 4754 u8 port_num[0x4];
e281682b
SM		 4755 u8 vport_number[0x10];
4756
b4ff3a36 4757 u8 reserved_at_60[0x20];
e281682b
SM		 4758};
4759
4760struct mlx5_ifc_query_hca_cap_out_bits {
4761 u8 status[0x8];
b4ff3a36 4762 u8 reserved_at_8[0x18];
e281682b
SM		 4763
4764 u8 syndrome[0x20];
4765
b4ff3a36 4766 u8 reserved_at_40[0x40];
e281682b
SM		 4767
4768 union mlx5_ifc_hca_cap_union_bits capability;
4769};
4770
4771struct mlx5_ifc_query_hca_cap_in_bits {
4772 u8 opcode[0x10];
b4ff3a36 4773 u8 reserved_at_10[0x10];
e281682b 4774
b4ff3a36 4775 u8 reserved_at_20[0x10];
e281682b
SM		 4776 u8 op_mod[0x10];
4777
b4ff3a36 4778 u8 reserved_at_40[0x40];
e281682b
SM		 4779};
4780
4781struct mlx5_ifc_query_flow_table_out_bits {
4782 u8 status[0x8];
b4ff3a36 4783 u8 reserved_at_8[0x18];
e281682b
SM		 4784
4785 u8 syndrome[0x20];
4786
b4ff3a36 4787 u8 reserved_at_40[0x80];
e281682b 4788
b4ff3a36 4789 u8 reserved_at_c0[0x8];
e281682b 4790 u8 level[0x8];
b4ff3a36 4791 u8 reserved_at_d0[0x8];
e281682b
SM		 4792 u8 log_size[0x8];
4793
b4ff3a36 4794 u8 reserved_at_e0[0x120];
e281682b
SM		 4795};
4796
4797struct mlx5_ifc_query_flow_table_in_bits {
4798 u8 opcode[0x10];
b4ff3a36 4799 u8 reserved_at_10[0x10];
e281682b 4800
b4ff3a36 4801 u8 reserved_at_20[0x10];
e281682b
SM		 4802 u8 op_mod[0x10];
4803
b4ff3a36 4804 u8 reserved_at_40[0x40];
e281682b
SM		 4805
4806 u8 table_type[0x8];
b4ff3a36 4807 u8 reserved_at_88[0x18];
e281682b 4808
b4ff3a36 4809 u8 reserved_at_a0[0x8];
e281682b
SM		 4810 u8 table_id[0x18];
4811
b4ff3a36 4812 u8 reserved_at_c0[0x140];
e281682b
SM		 4813};
4814
4815struct mlx5_ifc_query_fte_out_bits {
4816 u8 status[0x8];
b4ff3a36 4817 u8 reserved_at_8[0x18];
e281682b
SM		 4818
4819 u8 syndrome[0x20];
4820
b4ff3a36 4821 u8 reserved_at_40[0x1c0];
e281682b
SM		 4822
4823 struct mlx5_ifc_flow_context_bits flow_context;
4824};
4825
4826struct mlx5_ifc_query_fte_in_bits {
4827 u8 opcode[0x10];
b4ff3a36 4828 u8 reserved_at_10[0x10];
e281682b 4829
b4ff3a36 4830 u8 reserved_at_20[0x10];
e281682b
SM		 4831 u8 op_mod[0x10];
4832
b4ff3a36 4833 u8 reserved_at_40[0x40];
e281682b
SM		 4834
4835 u8 table_type[0x8];
b4ff3a36 4836 u8 reserved_at_88[0x18];
e281682b 4837
b4ff3a36 4838 u8 reserved_at_a0[0x8];
e281682b
SM		 4839 u8 table_id[0x18];
4840
b4ff3a36 4841 u8 reserved_at_c0[0x40];
e281682b
SM		 4842
4843 u8 flow_index[0x20];
4844
b4ff3a36 4845 u8 reserved_at_120[0xe0];
e281682b
SM		 4846};
4847
4848enum {
4849 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4850 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4851 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 4852 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 4853};
4854
4855struct mlx5_ifc_query_flow_group_out_bits {
4856 u8 status[0x8];
b4ff3a36 4857 u8 reserved_at_8[0x18];
e281682b
SM		 4858
4859 u8 syndrome[0x20];
4860
b4ff3a36 4861 u8 reserved_at_40[0xa0];
e281682b
SM		 4862
4863 u8 start_flow_index[0x20];
4864
b4ff3a36 4865 u8 reserved_at_100[0x20];
e281682b
SM		 4866
4867 u8 end_flow_index[0x20];
4868
b4ff3a36 4869 u8 reserved_at_140[0xa0];
e281682b 4870
b4ff3a36 4871 u8 reserved_at_1e0[0x18];
e281682b
SM		 4872 u8 match_criteria_enable[0x8];
4873
4874 struct mlx5_ifc_fte_match_param_bits match_criteria;
4875
b4ff3a36 4876 u8 reserved_at_1200[0xe00];
e281682b
SM		 4877};
4878
4879struct mlx5_ifc_query_flow_group_in_bits {
4880 u8 opcode[0x10];
b4ff3a36 4881 u8 reserved_at_10[0x10];
e281682b 4882
b4ff3a36 4883 u8 reserved_at_20[0x10];
e281682b
SM		 4884 u8 op_mod[0x10];
4885
b4ff3a36 4886 u8 reserved_at_40[0x40];
e281682b
SM		 4887
4888 u8 table_type[0x8];
b4ff3a36 4889 u8 reserved_at_88[0x18];
e281682b 4890
b4ff3a36 4891 u8 reserved_at_a0[0x8];
e281682b
SM		 4892 u8 table_id[0x18];
4893
4894 u8 group_id[0x20];
4895
b4ff3a36 4896 u8 reserved_at_e0[0x120];
e281682b
SM		 4897};
4898
9dc0b289
AV		 4899struct mlx5_ifc_query_flow_counter_out_bits {
4900 u8 status[0x8];
4901 u8 reserved_at_8[0x18];
4902
4903 u8 syndrome[0x20];
4904
4905 u8 reserved_at_40[0x40];
4906
4907 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4908};
4909
4910struct mlx5_ifc_query_flow_counter_in_bits {
4911 u8 opcode[0x10];
4912 u8 reserved_at_10[0x10];
4913
4914 u8 reserved_at_20[0x10];
4915 u8 op_mod[0x10];
4916
4917 u8 reserved_at_40[0x80];
4918
4919 u8 clear[0x1];
4920 u8 reserved_at_c1[0xf];
4921 u8 num_of_counters[0x10];
4922
a8ffcc74 4923 u8 flow_counter_id[0x20];
9dc0b289
AV		 4924};
4925
d6666753
SM		 4926struct mlx5_ifc_query_esw_vport_context_out_bits {
4927 u8 status[0x8];
b4ff3a36 4928 u8 reserved_at_8[0x18];
d6666753
SM		 4929
4930 u8 syndrome[0x20];
4931
b4ff3a36 4932 u8 reserved_at_40[0x40];
d6666753
SM		 4933
4934 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4935};
4936
4937struct mlx5_ifc_query_esw_vport_context_in_bits {
4938 u8 opcode[0x10];
b4ff3a36 4939 u8 reserved_at_10[0x10];
d6666753 4940
b4ff3a36 4941 u8 reserved_at_20[0x10];
d6666753
SM		 4942 u8 op_mod[0x10];
4943
4944 u8 other_vport[0x1];
b4ff3a36 4945 u8 reserved_at_41[0xf];
d6666753
SM		 4946 u8 vport_number[0x10];
4947
b4ff3a36 4948 u8 reserved_at_60[0x20];
d6666753
SM		 4949};
4950
4951struct mlx5_ifc_modify_esw_vport_context_out_bits {
4952 u8 status[0x8];
b4ff3a36 4953 u8 reserved_at_8[0x18];
d6666753
SM		 4954
4955 u8 syndrome[0x20];
4956
b4ff3a36 4957 u8 reserved_at_40[0x40];
d6666753
SM		 4958};
4959
4960struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4961 u8 reserved_at_0[0x1c];
d6666753
SM		 4962 u8 vport_cvlan_insert[0x1];
4963 u8 vport_svlan_insert[0x1];
4964 u8 vport_cvlan_strip[0x1];
4965 u8 vport_svlan_strip[0x1];
4966};
4967
4968struct mlx5_ifc_modify_esw_vport_context_in_bits {
4969 u8 opcode[0x10];
b4ff3a36 4970 u8 reserved_at_10[0x10];
d6666753 4971
b4ff3a36 4972 u8 reserved_at_20[0x10];
d6666753
SM		 4973 u8 op_mod[0x10];
4974
4975 u8 other_vport[0x1];
b4ff3a36 4976 u8 reserved_at_41[0xf];
d6666753
SM		 4977 u8 vport_number[0x10];
4978
4979 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4980
4981 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4982};
4983
e281682b
SM		 4984struct mlx5_ifc_query_eq_out_bits {
4985 u8 status[0x8];
b4ff3a36 4986 u8 reserved_at_8[0x18];
e281682b
SM		 4987
4988 u8 syndrome[0x20];
4989
b4ff3a36 4990 u8 reserved_at_40[0x40];
e281682b
SM		 4991
4992 struct mlx5_ifc_eqc_bits eq_context_entry;
4993
b4ff3a36 4994 u8 reserved_at_280[0x40];
e281682b
SM		 4995
4996 u8 event_bitmask[0x40];
4997
b4ff3a36 4998 u8 reserved_at_300[0x580];
e281682b
SM		 4999
5000 u8 pas[0][0x40];
5001};
5002
5003struct mlx5_ifc_query_eq_in_bits {
5004 u8 opcode[0x10];
b4ff3a36 5005 u8 reserved_at_10[0x10];
e281682b 5006
b4ff3a36 5007 u8 reserved_at_20[0x10];
e281682b
SM		 5008 u8 op_mod[0x10];
5009
b4ff3a36 5010 u8 reserved_at_40[0x18];
e281682b
SM		 5011 u8 eq_number[0x8];
5012
b4ff3a36 5013 u8 reserved_at_60[0x20];
e281682b
SM		 5014};
5015
60786f09 5016struct mlx5_ifc_packet_reformat_context_in_bits {
7adbde20 5017 u8 reserved_at_0[0x5];
60786f09 5018 u8 reformat_type[0x3];
7adbde20 5019 u8 reserved_at_8[0xe];
60786f09 5020 u8 reformat_data_size[0xa];
7adbde20
HHZ		 5021
5022 u8 reserved_at_20[0x10];
60786f09 5023 u8 reformat_data[2][0x8];
7adbde20 5024
60786f09 5025 u8 more_reformat_data[0][0x8];
7adbde20
HHZ		 5026};
5027
60786f09 5028struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 5029 u8 status[0x8];
5030 u8 reserved_at_8[0x18];
5031
5032 u8 syndrome[0x20];
5033
5034 u8 reserved_at_40[0xa0];
5035
60786f09 5036 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
7adbde20
HHZ		 5037};
5038
60786f09 5039struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 5040 u8 opcode[0x10];
5041 u8 reserved_at_10[0x10];
5042
5043 u8 reserved_at_20[0x10];
5044 u8 op_mod[0x10];
5045
60786f09 5046 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5047
5048 u8 reserved_at_60[0xa0];
5049};
5050
60786f09 5051struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5052 u8 status[0x8];
5053 u8 reserved_at_8[0x18];
5054
5055 u8 syndrome[0x20];
5056
60786f09 5057 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5058
5059 u8 reserved_at_60[0x20];
5060};
5061
e0e7a386 5062enum {
60786f09
MB		 5063 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5064 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 5065 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5066 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5067 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
e0e7a386
MB		 5068};
5069
60786f09 5070struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5071 u8 opcode[0x10];
5072 u8 reserved_at_10[0x10];
5073
5074 u8 reserved_at_20[0x10];
5075 u8 op_mod[0x10];
5076
5077 u8 reserved_at_40[0xa0];
5078
60786f09 5079 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 5080};
5081
60786f09 5082struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5083 u8 status[0x8];
5084 u8 reserved_at_8[0x18];
5085
5086 u8 syndrome[0x20];
5087
5088 u8 reserved_at_40[0x40];
5089};
5090
60786f09 5091struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5092 u8 opcode[0x10];
5093 u8 reserved_at_10[0x10];
5094
5095 u8 reserved_20[0x10];
5096 u8 op_mod[0x10];
5097
60786f09 5098 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5099
5100 u8 reserved_60[0x20];
5101};
5102
2a69cb9f
OG		 5103struct mlx5_ifc_set_action_in_bits {
5104 u8 action_type[0x4];
5105 u8 field[0xc];
5106 u8 reserved_at_10[0x3];
5107 u8 offset[0x5];
5108 u8 reserved_at_18[0x3];
5109 u8 length[0x5];
5110
5111 u8 data[0x20];
5112};
5113
5114struct mlx5_ifc_add_action_in_bits {
5115 u8 action_type[0x4];
5116 u8 field[0xc];
5117 u8 reserved_at_10[0x10];
5118
5119 u8 data[0x20];
5120};
5121
5122union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5123 struct mlx5_ifc_set_action_in_bits set_action_in;
5124 struct mlx5_ifc_add_action_in_bits add_action_in;
5125 u8 reserved_at_0[0x40];
5126};
5127
5128enum {
5129 MLX5_ACTION_TYPE_SET = 0x1,
5130 MLX5_ACTION_TYPE_ADD = 0x2,
5131};
5132
5133enum {
5134 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5135 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5136 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5137 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5138 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5139 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5140 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5141 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5142 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5143 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5144 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5145 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5146 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5147 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5148 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5149 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5150 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5151 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5152 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5153 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5154 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5155 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 5156 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 5157};
5158
5159struct mlx5_ifc_alloc_modify_header_context_out_bits {
5160 u8 status[0x8];
5161 u8 reserved_at_8[0x18];
5162
5163 u8 syndrome[0x20];
5164
5165 u8 modify_header_id[0x20];
5166
5167 u8 reserved_at_60[0x20];
5168};
5169
5170struct mlx5_ifc_alloc_modify_header_context_in_bits {
5171 u8 opcode[0x10];
5172 u8 reserved_at_10[0x10];
5173
5174 u8 reserved_at_20[0x10];
5175 u8 op_mod[0x10];
5176
5177 u8 reserved_at_40[0x20];
5178
5179 u8 table_type[0x8];
5180 u8 reserved_at_68[0x10];
5181 u8 num_of_actions[0x8];
5182
5183 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5184};
5185
5186struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5187 u8 status[0x8];
5188 u8 reserved_at_8[0x18];
5189
5190 u8 syndrome[0x20];
5191
5192 u8 reserved_at_40[0x40];
5193};
5194
5195struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5196 u8 opcode[0x10];
5197 u8 reserved_at_10[0x10];
5198
5199 u8 reserved_at_20[0x10];
5200 u8 op_mod[0x10];
5201
5202 u8 modify_header_id[0x20];
5203
5204 u8 reserved_at_60[0x20];
5205};
5206
e281682b
SM		 5207struct mlx5_ifc_query_dct_out_bits {
5208 u8 status[0x8];
b4ff3a36 5209 u8 reserved_at_8[0x18];
e281682b
SM		 5210
5211 u8 syndrome[0x20];
5212
b4ff3a36 5213 u8 reserved_at_40[0x40];
e281682b
SM		 5214
5215 struct mlx5_ifc_dctc_bits dct_context_entry;
5216
b4ff3a36 5217 u8 reserved_at_280[0x180];
e281682b
SM		 5218};
5219
5220struct mlx5_ifc_query_dct_in_bits {
5221 u8 opcode[0x10];
b4ff3a36 5222 u8 reserved_at_10[0x10];
e281682b 5223
b4ff3a36 5224 u8 reserved_at_20[0x10];
e281682b
SM		 5225 u8 op_mod[0x10];
5226
b4ff3a36 5227 u8 reserved_at_40[0x8];
e281682b
SM		 5228 u8 dctn[0x18];
5229
b4ff3a36 5230 u8 reserved_at_60[0x20];
e281682b
SM		 5231};
5232
5233struct mlx5_ifc_query_cq_out_bits {
5234 u8 status[0x8];
b4ff3a36 5235 u8 reserved_at_8[0x18];
e281682b
SM		 5236
5237 u8 syndrome[0x20];
5238
b4ff3a36 5239 u8 reserved_at_40[0x40];
e281682b
SM		 5240
5241 struct mlx5_ifc_cqc_bits cq_context;
5242
b4ff3a36 5243 u8 reserved_at_280[0x600];
e281682b
SM		 5244
5245 u8 pas[0][0x40];
5246};
5247
5248struct mlx5_ifc_query_cq_in_bits {
5249 u8 opcode[0x10];
b4ff3a36 5250 u8 reserved_at_10[0x10];
e281682b 5251
b4ff3a36 5252 u8 reserved_at_20[0x10];
e281682b
SM		 5253 u8 op_mod[0x10];
5254
b4ff3a36 5255 u8 reserved_at_40[0x8];
e281682b
SM		 5256 u8 cqn[0x18];
5257
b4ff3a36 5258 u8 reserved_at_60[0x20];
e281682b
SM		 5259};
5260
5261struct mlx5_ifc_query_cong_status_out_bits {
5262 u8 status[0x8];
b4ff3a36 5263 u8 reserved_at_8[0x18];
e281682b
SM		 5264
5265 u8 syndrome[0x20];
5266
b4ff3a36 5267 u8 reserved_at_40[0x20];
e281682b
SM		 5268
5269 u8 enable[0x1];
5270 u8 tag_enable[0x1];
b4ff3a36 5271 u8 reserved_at_62[0x1e];
e281682b
SM		 5272};
5273
5274struct mlx5_ifc_query_cong_status_in_bits {
5275 u8 opcode[0x10];
b4ff3a36 5276 u8 reserved_at_10[0x10];
e281682b 5277
b4ff3a36 5278 u8 reserved_at_20[0x10];
e281682b
SM		 5279 u8 op_mod[0x10];
5280
b4ff3a36 5281 u8 reserved_at_40[0x18];
e281682b
SM		 5282 u8 priority[0x4];
5283 u8 cong_protocol[0x4];
5284
b4ff3a36 5285 u8 reserved_at_60[0x20];
e281682b
SM		 5286};
5287
5288struct mlx5_ifc_query_cong_statistics_out_bits {
5289 u8 status[0x8];
b4ff3a36 5290 u8 reserved_at_8[0x18];
e281682b
SM		 5291
5292 u8 syndrome[0x20];
5293
b4ff3a36 5294 u8 reserved_at_40[0x40];
e281682b 5295
e1f24a79 5296 u8 rp_cur_flows[0x20];
e281682b
SM		 5297
5298 u8 sum_flows[0x20];
5299
e1f24a79 5300 u8 rp_cnp_ignored_high[0x20];
e281682b 5301
e1f24a79 5302 u8 rp_cnp_ignored_low[0x20];
e281682b 5303
e1f24a79 5304 u8 rp_cnp_handled_high[0x20];
e281682b 5305
e1f24a79 5306 u8 rp_cnp_handled_low[0x20];
e281682b 5307
b4ff3a36 5308 u8 reserved_at_140[0x100];
e281682b
SM		 5309
5310 u8 time_stamp_high[0x20];
5311
5312 u8 time_stamp_low[0x20];
5313
5314 u8 accumulators_period[0x20];
5315
e1f24a79 5316 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5317
e1f24a79 5318 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5319
e1f24a79 5320 u8 np_cnp_sent_high[0x20];
e281682b 5321
e1f24a79 5322 u8 np_cnp_sent_low[0x20];
e281682b 5323
b4ff3a36 5324 u8 reserved_at_320[0x560];
e281682b
SM		 5325};
5326
5327struct mlx5_ifc_query_cong_statistics_in_bits {
5328 u8 opcode[0x10];
b4ff3a36 5329 u8 reserved_at_10[0x10];
e281682b 5330
b4ff3a36 5331 u8 reserved_at_20[0x10];
e281682b
SM		 5332 u8 op_mod[0x10];
5333
5334 u8 clear[0x1];
b4ff3a36 5335 u8 reserved_at_41[0x1f];
e281682b 5336
b4ff3a36 5337 u8 reserved_at_60[0x20];
e281682b
SM		 5338};
5339
5340struct mlx5_ifc_query_cong_params_out_bits {
5341 u8 status[0x8];
b4ff3a36 5342 u8 reserved_at_8[0x18];
e281682b
SM		 5343
5344 u8 syndrome[0x20];
5345
b4ff3a36 5346 u8 reserved_at_40[0x40];
e281682b
SM		 5347
5348 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5349};
5350
5351struct mlx5_ifc_query_cong_params_in_bits {
5352 u8 opcode[0x10];
b4ff3a36 5353 u8 reserved_at_10[0x10];
e281682b 5354
b4ff3a36 5355 u8 reserved_at_20[0x10];
e281682b
SM		 5356 u8 op_mod[0x10];
5357
b4ff3a36 5358 u8 reserved_at_40[0x1c];
e281682b
SM		 5359 u8 cong_protocol[0x4];
5360
b4ff3a36 5361 u8 reserved_at_60[0x20];
e281682b
SM		 5362};
5363
5364struct mlx5_ifc_query_adapter_out_bits {
5365 u8 status[0x8];
b4ff3a36 5366 u8 reserved_at_8[0x18];
e281682b
SM		 5367
5368 u8 syndrome[0x20];
5369
b4ff3a36 5370 u8 reserved_at_40[0x40];
e281682b
SM		 5371
5372 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5373};
5374
5375struct mlx5_ifc_query_adapter_in_bits {
5376 u8 opcode[0x10];
b4ff3a36 5377 u8 reserved_at_10[0x10];
e281682b 5378
b4ff3a36 5379 u8 reserved_at_20[0x10];
e281682b
SM		 5380 u8 op_mod[0x10];
5381
b4ff3a36 5382 u8 reserved_at_40[0x40];
e281682b
SM		 5383};
5384
5385struct mlx5_ifc_qp_2rst_out_bits {
5386 u8 status[0x8];
b4ff3a36 5387 u8 reserved_at_8[0x18];
e281682b
SM		 5388
5389 u8 syndrome[0x20];
5390
b4ff3a36 5391 u8 reserved_at_40[0x40];
e281682b
SM		 5392};
5393
5394struct mlx5_ifc_qp_2rst_in_bits {
5395 u8 opcode[0x10];
4ac63ec7 5396 u8 uid[0x10];
e281682b 5397
b4ff3a36 5398 u8 reserved_at_20[0x10];
e281682b
SM		 5399 u8 op_mod[0x10];
5400
b4ff3a36 5401 u8 reserved_at_40[0x8];
e281682b
SM		 5402 u8 qpn[0x18];
5403
b4ff3a36 5404 u8 reserved_at_60[0x20];
e281682b
SM		 5405};
5406
5407struct mlx5_ifc_qp_2err_out_bits {
5408 u8 status[0x8];
b4ff3a36 5409 u8 reserved_at_8[0x18];
e281682b
SM		 5410
5411 u8 syndrome[0x20];
5412
b4ff3a36 5413 u8 reserved_at_40[0x40];
e281682b
SM		 5414};
5415
5416struct mlx5_ifc_qp_2err_in_bits {
5417 u8 opcode[0x10];
4ac63ec7 5418 u8 uid[0x10];
e281682b 5419
b4ff3a36 5420 u8 reserved_at_20[0x10];
e281682b
SM		 5421 u8 op_mod[0x10];
5422
b4ff3a36 5423 u8 reserved_at_40[0x8];
e281682b
SM		 5424 u8 qpn[0x18];
5425
b4ff3a36 5426 u8 reserved_at_60[0x20];
e281682b
SM		 5427};
5428
5429struct mlx5_ifc_page_fault_resume_out_bits {
5430 u8 status[0x8];
b4ff3a36 5431 u8 reserved_at_8[0x18];
e281682b
SM		 5432
5433 u8 syndrome[0x20];
5434
b4ff3a36 5435 u8 reserved_at_40[0x40];
e281682b
SM		 5436};
5437
5438struct mlx5_ifc_page_fault_resume_in_bits {
5439 u8 opcode[0x10];
b4ff3a36 5440 u8 reserved_at_10[0x10];
e281682b 5441
b4ff3a36 5442 u8 reserved_at_20[0x10];
e281682b
SM		 5443 u8 op_mod[0x10];
5444
5445 u8 error[0x1];
b4ff3a36 5446 u8 reserved_at_41[0x4];
223cdc72
AK		 5447 u8 page_fault_type[0x3];
5448 u8 wq_number[0x18];
e281682b 5449
223cdc72
AK		 5450 u8 reserved_at_60[0x8];
5451 u8 token[0x18];
e281682b
SM		 5452};
5453
5454struct mlx5_ifc_nop_out_bits {
5455 u8 status[0x8];
b4ff3a36 5456 u8 reserved_at_8[0x18];
e281682b
SM		 5457
5458 u8 syndrome[0x20];
5459
b4ff3a36 5460 u8 reserved_at_40[0x40];
e281682b
SM		 5461};
5462
5463struct mlx5_ifc_nop_in_bits {
5464 u8 opcode[0x10];
b4ff3a36 5465 u8 reserved_at_10[0x10];
e281682b 5466
b4ff3a36 5467 u8 reserved_at_20[0x10];
e281682b
SM		 5468 u8 op_mod[0x10];
5469
b4ff3a36 5470 u8 reserved_at_40[0x40];
e281682b
SM		 5471};
5472
5473struct mlx5_ifc_modify_vport_state_out_bits {
5474 u8 status[0x8];
b4ff3a36 5475 u8 reserved_at_8[0x18];
e281682b
SM		 5476
5477 u8 syndrome[0x20];
5478
b4ff3a36 5479 u8 reserved_at_40[0x40];
e281682b
SM		 5480};
5481
5482struct mlx5_ifc_modify_vport_state_in_bits {
5483 u8 opcode[0x10];
b4ff3a36 5484 u8 reserved_at_10[0x10];
e281682b 5485
b4ff3a36 5486 u8 reserved_at_20[0x10];
e281682b
SM		 5487 u8 op_mod[0x10];
5488
5489 u8 other_vport[0x1];
b4ff3a36 5490 u8 reserved_at_41[0xf];
e281682b
SM		 5491 u8 vport_number[0x10];
5492
b4ff3a36 5493 u8 reserved_at_60[0x18];
e281682b 5494 u8 admin_state[0x4];
b4ff3a36 5495 u8 reserved_at_7c[0x4];
e281682b
SM		 5496};
5497
5498struct mlx5_ifc_modify_tis_out_bits {
5499 u8 status[0x8];
b4ff3a36 5500 u8 reserved_at_8[0x18];
e281682b
SM		 5501
5502 u8 syndrome[0x20];
5503
b4ff3a36 5504 u8 reserved_at_40[0x40];
e281682b
SM		 5505};
5506
75850d0b 5507struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5508 u8 reserved_at_0[0x20];
75850d0b 5509
84df61eb
AH		 5510 u8 reserved_at_20[0x1d];
5511 u8 lag_tx_port_affinity[0x1];
5512 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5513 u8 prio[0x1];
5514};
5515
e281682b
SM		 5516struct mlx5_ifc_modify_tis_in_bits {
5517 u8 opcode[0x10];
bd371975 5518 u8 uid[0x10];
e281682b 5519
b4ff3a36 5520 u8 reserved_at_20[0x10];
e281682b
SM		 5521 u8 op_mod[0x10];
5522
b4ff3a36 5523 u8 reserved_at_40[0x8];
e281682b
SM		 5524 u8 tisn[0x18];
5525
b4ff3a36 5526 u8 reserved_at_60[0x20];
e281682b 5527
75850d0b 5528 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5529
b4ff3a36 5530 u8 reserved_at_c0[0x40];
e281682b
SM		 5531
5532 struct mlx5_ifc_tisc_bits ctx;
5533};
5534
d9eea403 5535struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5536 u8 reserved_at_0[0x20];
d9eea403 5537
b4ff3a36 5538 u8 reserved_at_20[0x1b];
66189961 5539 u8 self_lb_en[0x1];
bdfc028d
TT		 5540 u8 reserved_at_3c[0x1];
5541 u8 hash[0x1];
5542 u8 reserved_at_3e[0x1];
d9eea403
AS		 5543 u8 lro[0x1];
5544};
5545
e281682b
SM		 5546struct mlx5_ifc_modify_tir_out_bits {
5547 u8 status[0x8];
b4ff3a36 5548 u8 reserved_at_8[0x18];
e281682b
SM		 5549
5550 u8 syndrome[0x20];
5551
b4ff3a36 5552 u8 reserved_at_40[0x40];
e281682b
SM		 5553};
5554
5555struct mlx5_ifc_modify_tir_in_bits {
5556 u8 opcode[0x10];
bd371975 5557 u8 uid[0x10];
e281682b 5558
b4ff3a36 5559 u8 reserved_at_20[0x10];
e281682b
SM		 5560 u8 op_mod[0x10];
5561
b4ff3a36 5562 u8 reserved_at_40[0x8];
e281682b
SM		 5563 u8 tirn[0x18];
5564
b4ff3a36 5565 u8 reserved_at_60[0x20];
e281682b 5566
d9eea403 5567 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5568
b4ff3a36 5569 u8 reserved_at_c0[0x40];
e281682b
SM		 5570
5571 struct mlx5_ifc_tirc_bits ctx;
5572};
5573
5574struct mlx5_ifc_modify_sq_out_bits {
5575 u8 status[0x8];
b4ff3a36 5576 u8 reserved_at_8[0x18];
e281682b
SM		 5577
5578 u8 syndrome[0x20];
5579
b4ff3a36 5580 u8 reserved_at_40[0x40];
e281682b
SM		 5581};
5582
5583struct mlx5_ifc_modify_sq_in_bits {
5584 u8 opcode[0x10];
430ae0d5 5585 u8 uid[0x10];
e281682b 5586
b4ff3a36 5587 u8 reserved_at_20[0x10];
e281682b
SM		 5588 u8 op_mod[0x10];
5589
5590 u8 sq_state[0x4];
b4ff3a36 5591 u8 reserved_at_44[0x4];
e281682b
SM		 5592 u8 sqn[0x18];
5593
b4ff3a36 5594 u8 reserved_at_60[0x20];
e281682b
SM		 5595
5596 u8 modify_bitmask[0x40];
5597
b4ff3a36 5598 u8 reserved_at_c0[0x40];
e281682b
SM		 5599
5600 struct mlx5_ifc_sqc_bits ctx;
5601};
5602
813f8540
MHY		 5603struct mlx5_ifc_modify_scheduling_element_out_bits {
5604 u8 status[0x8];
5605 u8 reserved_at_8[0x18];
5606
5607 u8 syndrome[0x20];
5608
5609 u8 reserved_at_40[0x1c0];
5610};
5611
5612enum {
5613 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5614 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5615};
5616
5617struct mlx5_ifc_modify_scheduling_element_in_bits {
5618 u8 opcode[0x10];
5619 u8 reserved_at_10[0x10];
5620
5621 u8 reserved_at_20[0x10];
5622 u8 op_mod[0x10];
5623
5624 u8 scheduling_hierarchy[0x8];
5625 u8 reserved_at_48[0x18];
5626
5627 u8 scheduling_element_id[0x20];
5628
5629 u8 reserved_at_80[0x20];
5630
5631 u8 modify_bitmask[0x20];
5632
5633 u8 reserved_at_c0[0x40];
5634
5635 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5636
5637 u8 reserved_at_300[0x100];
5638};
5639
e281682b
SM		 5640struct mlx5_ifc_modify_rqt_out_bits {
5641 u8 status[0x8];
b4ff3a36 5642 u8 reserved_at_8[0x18];
e281682b
SM		 5643
5644 u8 syndrome[0x20];
5645
b4ff3a36 5646 u8 reserved_at_40[0x40];
e281682b
SM		 5647};
5648
5c50368f 5649struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5650 u8 reserved_at_0[0x20];
5c50368f 5651
b4ff3a36 5652 u8 reserved_at_20[0x1f];
5c50368f
AS		 5653 u8 rqn_list[0x1];
5654};
5655
e281682b
SM		 5656struct mlx5_ifc_modify_rqt_in_bits {
5657 u8 opcode[0x10];
bd371975 5658 u8 uid[0x10];
e281682b 5659
b4ff3a36 5660 u8 reserved_at_20[0x10];
e281682b
SM		 5661 u8 op_mod[0x10];
5662
b4ff3a36 5663 u8 reserved_at_40[0x8];
e281682b
SM		 5664 u8 rqtn[0x18];
5665
b4ff3a36 5666 u8 reserved_at_60[0x20];
e281682b 5667
5c50368f 5668 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5669
b4ff3a36 5670 u8 reserved_at_c0[0x40];
e281682b
SM		 5671
5672 struct mlx5_ifc_rqtc_bits ctx;
5673};
5674
5675struct mlx5_ifc_modify_rq_out_bits {
5676 u8 status[0x8];
b4ff3a36 5677 u8 reserved_at_8[0x18];
e281682b
SM		 5678
5679 u8 syndrome[0x20];
5680
b4ff3a36 5681 u8 reserved_at_40[0x40];
e281682b
SM		 5682};
5683
83b502a1
AV		 5684enum {
5685 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5686 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5687 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5688};
5689
e281682b
SM		 5690struct mlx5_ifc_modify_rq_in_bits {
5691 u8 opcode[0x10];
d269b3af 5692 u8 uid[0x10];
e281682b 5693
b4ff3a36 5694 u8 reserved_at_20[0x10];
e281682b
SM		 5695 u8 op_mod[0x10];
5696
5697 u8 rq_state[0x4];
b4ff3a36 5698 u8 reserved_at_44[0x4];
e281682b
SM		 5699 u8 rqn[0x18];
5700
b4ff3a36 5701 u8 reserved_at_60[0x20];
e281682b
SM		 5702
5703 u8 modify_bitmask[0x40];
5704
b4ff3a36 5705 u8 reserved_at_c0[0x40];
e281682b
SM		 5706
5707 struct mlx5_ifc_rqc_bits ctx;
5708};
5709
5710struct mlx5_ifc_modify_rmp_out_bits {
5711 u8 status[0x8];
b4ff3a36 5712 u8 reserved_at_8[0x18];
e281682b
SM		 5713
5714 u8 syndrome[0x20];
5715
b4ff3a36 5716 u8 reserved_at_40[0x40];
e281682b
SM		 5717};
5718
01949d01 5719struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5720 u8 reserved_at_0[0x20];
01949d01 5721
b4ff3a36 5722 u8 reserved_at_20[0x1f];
01949d01
HA		 5723 u8 lwm[0x1];
5724};
5725
e281682b
SM		 5726struct mlx5_ifc_modify_rmp_in_bits {
5727 u8 opcode[0x10];
a0d8c054 5728 u8 uid[0x10];
e281682b 5729
b4ff3a36 5730 u8 reserved_at_20[0x10];
e281682b
SM		 5731 u8 op_mod[0x10];
5732
5733 u8 rmp_state[0x4];
b4ff3a36 5734 u8 reserved_at_44[0x4];
e281682b
SM		 5735 u8 rmpn[0x18];
5736
b4ff3a36 5737 u8 reserved_at_60[0x20];
e281682b 5738
01949d01 5739 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5740
b4ff3a36 5741 u8 reserved_at_c0[0x40];
e281682b
SM		 5742
5743 struct mlx5_ifc_rmpc_bits ctx;
5744};
5745
5746struct mlx5_ifc_modify_nic_vport_context_out_bits {
5747 u8 status[0x8];
b4ff3a36 5748 u8 reserved_at_8[0x18];
e281682b
SM		 5749
5750 u8 syndrome[0x20];
5751
b4ff3a36 5752 u8 reserved_at_40[0x40];
e281682b
SM		 5753};
5754
5755struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5756 u8 reserved_at_0[0x12];
5757 u8 affiliation[0x1];
c74d90c1 5758 u8 reserved_at_13[0x1];
bded747b
HN		 5759 u8 disable_uc_local_lb[0x1];
5760 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5761 u8 node_guid[0x1];
5762 u8 port_guid[0x1];
9def7121 5763 u8 min_inline[0x1];
d82b7318
SM		 5764 u8 mtu[0x1];
5765 u8 change_event[0x1];
5766 u8 promisc[0x1];
e281682b
SM		 5767 u8 permanent_address[0x1];
5768 u8 addresses_list[0x1];
5769 u8 roce_en[0x1];
b4ff3a36 5770 u8 reserved_at_1f[0x1];
e281682b
SM		 5771};
5772
5773struct mlx5_ifc_modify_nic_vport_context_in_bits {
5774 u8 opcode[0x10];
b4ff3a36 5775 u8 reserved_at_10[0x10];
e281682b 5776
b4ff3a36 5777 u8 reserved_at_20[0x10];
e281682b
SM		 5778 u8 op_mod[0x10];
5779
5780 u8 other_vport[0x1];
b4ff3a36 5781 u8 reserved_at_41[0xf];
e281682b
SM		 5782 u8 vport_number[0x10];
5783
5784 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5785
b4ff3a36 5786 u8 reserved_at_80[0x780];
e281682b
SM		 5787
5788 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5789};
5790
5791struct mlx5_ifc_modify_hca_vport_context_out_bits {
5792 u8 status[0x8];
b4ff3a36 5793 u8 reserved_at_8[0x18];
e281682b
SM		 5794
5795 u8 syndrome[0x20];
5796
b4ff3a36 5797 u8 reserved_at_40[0x40];
e281682b
SM		 5798};
5799
5800struct mlx5_ifc_modify_hca_vport_context_in_bits {
5801 u8 opcode[0x10];
b4ff3a36 5802 u8 reserved_at_10[0x10];
e281682b 5803
b4ff3a36 5804 u8 reserved_at_20[0x10];
e281682b
SM		 5805 u8 op_mod[0x10];
5806
5807 u8 other_vport[0x1];
b4ff3a36 5808 u8 reserved_at_41[0xb];
707c4602 5809 u8 port_num[0x4];
e281682b
SM		 5810 u8 vport_number[0x10];
5811
b4ff3a36 5812 u8 reserved_at_60[0x20];
e281682b
SM		 5813
5814 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5815};
5816
5817struct mlx5_ifc_modify_cq_out_bits {
5818 u8 status[0x8];
b4ff3a36 5819 u8 reserved_at_8[0x18];
e281682b
SM		 5820
5821 u8 syndrome[0x20];
5822
b4ff3a36 5823 u8 reserved_at_40[0x40];
e281682b
SM		 5824};
5825
5826enum {
5827 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5828 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5829};
5830
5831struct mlx5_ifc_modify_cq_in_bits {
5832 u8 opcode[0x10];
9ba481e2 5833 u8 uid[0x10];
e281682b 5834
b4ff3a36 5835 u8 reserved_at_20[0x10];
e281682b
SM		 5836 u8 op_mod[0x10];
5837
b4ff3a36 5838 u8 reserved_at_40[0x8];
e281682b
SM		 5839 u8 cqn[0x18];
5840
5841 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5842
5843 struct mlx5_ifc_cqc_bits cq_context;
5844
bd371975
LR		 5845 u8 reserved_at_280[0x40];
5846
5847 u8 cq_umem_valid[0x1];
5848 u8 reserved_at_2c1[0x5bf];
e281682b
SM		 5849
5850 u8 pas[0][0x40];
5851};
5852
5853struct mlx5_ifc_modify_cong_status_out_bits {
5854 u8 status[0x8];
b4ff3a36 5855 u8 reserved_at_8[0x18];
e281682b
SM		 5856
5857 u8 syndrome[0x20];
5858
b4ff3a36 5859 u8 reserved_at_40[0x40];
e281682b
SM		 5860};
5861
5862struct mlx5_ifc_modify_cong_status_in_bits {
5863 u8 opcode[0x10];
b4ff3a36 5864 u8 reserved_at_10[0x10];
e281682b 5865
b4ff3a36 5866 u8 reserved_at_20[0x10];
e281682b
SM		 5867 u8 op_mod[0x10];
5868
b4ff3a36 5869 u8 reserved_at_40[0x18];
e281682b
SM		 5870 u8 priority[0x4];
5871 u8 cong_protocol[0x4];
5872
5873 u8 enable[0x1];
5874 u8 tag_enable[0x1];
b4ff3a36 5875 u8 reserved_at_62[0x1e];
e281682b
SM		 5876};
5877
5878struct mlx5_ifc_modify_cong_params_out_bits {
5879 u8 status[0x8];
b4ff3a36 5880 u8 reserved_at_8[0x18];
e281682b
SM		 5881
5882 u8 syndrome[0x20];
5883
b4ff3a36 5884 u8 reserved_at_40[0x40];
e281682b
SM		 5885};
5886
5887struct mlx5_ifc_modify_cong_params_in_bits {
5888 u8 opcode[0x10];
b4ff3a36 5889 u8 reserved_at_10[0x10];
e281682b 5890
b4ff3a36 5891 u8 reserved_at_20[0x10];
e281682b
SM		 5892 u8 op_mod[0x10];
5893
b4ff3a36 5894 u8 reserved_at_40[0x1c];
e281682b
SM		 5895 u8 cong_protocol[0x4];
5896
5897 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5898
b4ff3a36 5899 u8 reserved_at_80[0x80];
e281682b
SM		 5900
5901 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5902};
5903
5904struct mlx5_ifc_manage_pages_out_bits {
5905 u8 status[0x8];
b4ff3a36 5906 u8 reserved_at_8[0x18];
e281682b
SM		 5907
5908 u8 syndrome[0x20];
5909
5910 u8 output_num_entries[0x20];
5911
b4ff3a36 5912 u8 reserved_at_60[0x20];
e281682b
SM		 5913
5914 u8 pas[0][0x40];
5915};
5916
5917enum {
5918 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5919 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5920 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5921};
5922
5923struct mlx5_ifc_manage_pages_in_bits {
5924 u8 opcode[0x10];
b4ff3a36 5925 u8 reserved_at_10[0x10];
e281682b 5926
b4ff3a36 5927 u8 reserved_at_20[0x10];
e281682b
SM		 5928 u8 op_mod[0x10];
5929
591905ba
BW		 5930 u8 embedded_cpu_function[0x1];
5931 u8 reserved_at_41[0xf];
e281682b
SM		 5932 u8 function_id[0x10];
5933
5934 u8 input_num_entries[0x20];
5935
5936 u8 pas[0][0x40];
5937};
5938
5939struct mlx5_ifc_mad_ifc_out_bits {
5940 u8 status[0x8];
b4ff3a36 5941 u8 reserved_at_8[0x18];
e281682b
SM		 5942
5943 u8 syndrome[0x20];
5944
b4ff3a36 5945 u8 reserved_at_40[0x40];
e281682b
SM		 5946
5947 u8 response_mad_packet[256][0x8];
5948};
5949
5950struct mlx5_ifc_mad_ifc_in_bits {
5951 u8 opcode[0x10];
b4ff3a36 5952 u8 reserved_at_10[0x10];
e281682b 5953
b4ff3a36 5954 u8 reserved_at_20[0x10];
e281682b
SM		 5955 u8 op_mod[0x10];
5956
5957 u8 remote_lid[0x10];
b4ff3a36 5958 u8 reserved_at_50[0x8];
e281682b
SM		 5959 u8 port[0x8];
5960
b4ff3a36 5961 u8 reserved_at_60[0x20];
e281682b
SM		 5962
5963 u8 mad[256][0x8];
5964};
5965
5966struct mlx5_ifc_init_hca_out_bits {
5967 u8 status[0x8];
b4ff3a36 5968 u8 reserved_at_8[0x18];
e281682b
SM		 5969
5970 u8 syndrome[0x20];
5971
b4ff3a36 5972 u8 reserved_at_40[0x40];
e281682b
SM		 5973};
5974
5975struct mlx5_ifc_init_hca_in_bits {
5976 u8 opcode[0x10];
b4ff3a36 5977 u8 reserved_at_10[0x10];
e281682b 5978
b4ff3a36 5979 u8 reserved_at_20[0x10];
e281682b
SM		 5980 u8 op_mod[0x10];
5981
b4ff3a36 5982 u8 reserved_at_40[0x40];
8737f818 5983 u8 sw_owner_id[4][0x20];
e281682b
SM		 5984};
5985
5986struct mlx5_ifc_init2rtr_qp_out_bits {
5987 u8 status[0x8];
b4ff3a36 5988 u8 reserved_at_8[0x18];
e281682b
SM		 5989
5990 u8 syndrome[0x20];
5991
b4ff3a36 5992 u8 reserved_at_40[0x40];
e281682b
SM		 5993};
5994
5995struct mlx5_ifc_init2rtr_qp_in_bits {
5996 u8 opcode[0x10];
4ac63ec7 5997 u8 uid[0x10];
e281682b 5998
b4ff3a36 5999 u8 reserved_at_20[0x10];
e281682b
SM		 6000 u8 op_mod[0x10];
6001
b4ff3a36 6002 u8 reserved_at_40[0x8];
e281682b
SM		 6003 u8 qpn[0x18];
6004
b4ff3a36 6005 u8 reserved_at_60[0x20];
e281682b
SM		 6006
6007 u8 opt_param_mask[0x20];
6008
b4ff3a36 6009 u8 reserved_at_a0[0x20];
e281682b
SM		 6010
6011 struct mlx5_ifc_qpc_bits qpc;
6012
b4ff3a36 6013 u8 reserved_at_800[0x80];
e281682b
SM		 6014};
6015
6016struct mlx5_ifc_init2init_qp_out_bits {
6017 u8 status[0x8];
b4ff3a36 6018 u8 reserved_at_8[0x18];
e281682b
SM		 6019
6020 u8 syndrome[0x20];
6021
b4ff3a36 6022 u8 reserved_at_40[0x40];
e281682b
SM		 6023};
6024
6025struct mlx5_ifc_init2init_qp_in_bits {
6026 u8 opcode[0x10];
4ac63ec7 6027 u8 uid[0x10];
e281682b 6028
b4ff3a36 6029 u8 reserved_at_20[0x10];
e281682b
SM		 6030 u8 op_mod[0x10];
6031
b4ff3a36 6032 u8 reserved_at_40[0x8];
e281682b
SM		 6033 u8 qpn[0x18];
6034
b4ff3a36 6035 u8 reserved_at_60[0x20];
e281682b
SM		 6036
6037 u8 opt_param_mask[0x20];
6038
b4ff3a36 6039 u8 reserved_at_a0[0x20];
e281682b
SM		 6040
6041 struct mlx5_ifc_qpc_bits qpc;
6042
b4ff3a36 6043 u8 reserved_at_800[0x80];
e281682b
SM		 6044};
6045
6046struct mlx5_ifc_get_dropped_packet_log_out_bits {
6047 u8 status[0x8];
b4ff3a36 6048 u8 reserved_at_8[0x18];
e281682b
SM		 6049
6050 u8 syndrome[0x20];
6051
b4ff3a36 6052 u8 reserved_at_40[0x40];
e281682b
SM		 6053
6054 u8 packet_headers_log[128][0x8];
6055
6056 u8 packet_syndrome[64][0x8];
6057};
6058
6059struct mlx5_ifc_get_dropped_packet_log_in_bits {
6060 u8 opcode[0x10];
b4ff3a36 6061 u8 reserved_at_10[0x10];
e281682b 6062
b4ff3a36 6063 u8 reserved_at_20[0x10];
e281682b
SM		 6064 u8 op_mod[0x10];
6065
b4ff3a36 6066 u8 reserved_at_40[0x40];
e281682b
SM		 6067};
6068
6069struct mlx5_ifc_gen_eqe_in_bits {
6070 u8 opcode[0x10];
b4ff3a36 6071 u8 reserved_at_10[0x10];
e281682b 6072
b4ff3a36 6073 u8 reserved_at_20[0x10];
e281682b
SM		 6074 u8 op_mod[0x10];
6075
b4ff3a36 6076 u8 reserved_at_40[0x18];
e281682b
SM		 6077 u8 eq_number[0x8];
6078
b4ff3a36 6079 u8 reserved_at_60[0x20];
e281682b
SM		 6080
6081 u8 eqe[64][0x8];
6082};
6083
6084struct mlx5_ifc_gen_eq_out_bits {
6085 u8 status[0x8];
b4ff3a36 6086 u8 reserved_at_8[0x18];
e281682b
SM		 6087
6088 u8 syndrome[0x20];
6089
b4ff3a36 6090 u8 reserved_at_40[0x40];
e281682b
SM		 6091};
6092
6093struct mlx5_ifc_enable_hca_out_bits {
6094 u8 status[0x8];
b4ff3a36 6095 u8 reserved_at_8[0x18];
e281682b
SM		 6096
6097 u8 syndrome[0x20];
6098
b4ff3a36 6099 u8 reserved_at_40[0x20];
e281682b
SM		 6100};
6101
6102struct mlx5_ifc_enable_hca_in_bits {
6103 u8 opcode[0x10];
b4ff3a36 6104 u8 reserved_at_10[0x10];
e281682b 6105
b4ff3a36 6106 u8 reserved_at_20[0x10];
e281682b
SM		 6107 u8 op_mod[0x10];
6108
22e939a9
BW		 6109 u8 embedded_cpu_function[0x1];
6110 u8 reserved_at_41[0xf];
e281682b
SM		 6111 u8 function_id[0x10];
6112
b4ff3a36 6113 u8 reserved_at_60[0x20];
e281682b
SM		 6114};
6115
6116struct mlx5_ifc_drain_dct_out_bits {
6117 u8 status[0x8];
b4ff3a36 6118 u8 reserved_at_8[0x18];
e281682b
SM		 6119
6120 u8 syndrome[0x20];
6121
b4ff3a36 6122 u8 reserved_at_40[0x40];
e281682b
SM		 6123};
6124
6125struct mlx5_ifc_drain_dct_in_bits {
6126 u8 opcode[0x10];
774ea6ee 6127 u8 uid[0x10];
e281682b 6128
b4ff3a36 6129 u8 reserved_at_20[0x10];
e281682b
SM		 6130 u8 op_mod[0x10];
6131
b4ff3a36 6132 u8 reserved_at_40[0x8];
e281682b
SM		 6133 u8 dctn[0x18];
6134
b4ff3a36 6135 u8 reserved_at_60[0x20];
e281682b
SM		 6136};
6137
6138struct mlx5_ifc_disable_hca_out_bits {
6139 u8 status[0x8];
b4ff3a36 6140 u8 reserved_at_8[0x18];
e281682b
SM		 6141
6142 u8 syndrome[0x20];
6143
b4ff3a36 6144 u8 reserved_at_40[0x20];
e281682b
SM		 6145};
6146
6147struct mlx5_ifc_disable_hca_in_bits {
6148 u8 opcode[0x10];
b4ff3a36 6149 u8 reserved_at_10[0x10];
e281682b 6150
b4ff3a36 6151 u8 reserved_at_20[0x10];
e281682b
SM		 6152 u8 op_mod[0x10];
6153
22e939a9
BW		 6154 u8 embedded_cpu_function[0x1];
6155 u8 reserved_at_41[0xf];
e281682b
SM		 6156 u8 function_id[0x10];
6157
b4ff3a36 6158 u8 reserved_at_60[0x20];
e281682b
SM		 6159};
6160
6161struct mlx5_ifc_detach_from_mcg_out_bits {
6162 u8 status[0x8];
b4ff3a36 6163 u8 reserved_at_8[0x18];
e281682b
SM		 6164
6165 u8 syndrome[0x20];
6166
b4ff3a36 6167 u8 reserved_at_40[0x40];
e281682b
SM		 6168};
6169
6170struct mlx5_ifc_detach_from_mcg_in_bits {
6171 u8 opcode[0x10];
bd371975 6172 u8 uid[0x10];
e281682b 6173
b4ff3a36 6174 u8 reserved_at_20[0x10];
e281682b
SM		 6175 u8 op_mod[0x10];
6176
b4ff3a36 6177 u8 reserved_at_40[0x8];
e281682b
SM		 6178 u8 qpn[0x18];
6179
b4ff3a36 6180 u8 reserved_at_60[0x20];
e281682b
SM		 6181
6182 u8 multicast_gid[16][0x8];
6183};
6184
7486216b
SM		 6185struct mlx5_ifc_destroy_xrq_out_bits {
6186 u8 status[0x8];
6187 u8 reserved_at_8[0x18];
6188
6189 u8 syndrome[0x20];
6190
6191 u8 reserved_at_40[0x40];
6192};
6193
6194struct mlx5_ifc_destroy_xrq_in_bits {
6195 u8 opcode[0x10];
a0d8c054 6196 u8 uid[0x10];
7486216b
SM		 6197
6198 u8 reserved_at_20[0x10];
6199 u8 op_mod[0x10];
6200
6201 u8 reserved_at_40[0x8];
6202 u8 xrqn[0x18];
6203
6204 u8 reserved_at_60[0x20];
6205};
6206
e281682b
SM		 6207struct mlx5_ifc_destroy_xrc_srq_out_bits {
6208 u8 status[0x8];
b4ff3a36 6209 u8 reserved_at_8[0x18];
e281682b
SM		 6210
6211 u8 syndrome[0x20];
6212
b4ff3a36 6213 u8 reserved_at_40[0x40];
e281682b
SM		 6214};
6215
6216struct mlx5_ifc_destroy_xrc_srq_in_bits {
6217 u8 opcode[0x10];
a0d8c054 6218 u8 uid[0x10];
e281682b 6219
b4ff3a36 6220 u8 reserved_at_20[0x10];
e281682b
SM		 6221 u8 op_mod[0x10];
6222
b4ff3a36 6223 u8 reserved_at_40[0x8];
e281682b
SM		 6224 u8 xrc_srqn[0x18];
6225
b4ff3a36 6226 u8 reserved_at_60[0x20];
e281682b
SM		 6227};
6228
6229struct mlx5_ifc_destroy_tis_out_bits {
6230 u8 status[0x8];
b4ff3a36 6231 u8 reserved_at_8[0x18];
e281682b
SM		 6232
6233 u8 syndrome[0x20];
6234
b4ff3a36 6235 u8 reserved_at_40[0x40];
e281682b
SM		 6236};
6237
6238struct mlx5_ifc_destroy_tis_in_bits {
6239 u8 opcode[0x10];
bd371975 6240 u8 uid[0x10];
e281682b 6241
b4ff3a36 6242 u8 reserved_at_20[0x10];
e281682b
SM		 6243 u8 op_mod[0x10];
6244
b4ff3a36 6245 u8 reserved_at_40[0x8];
e281682b
SM		 6246 u8 tisn[0x18];
6247
b4ff3a36 6248 u8 reserved_at_60[0x20];
e281682b
SM		 6249};
6250
6251struct mlx5_ifc_destroy_tir_out_bits {
6252 u8 status[0x8];
b4ff3a36 6253 u8 reserved_at_8[0x18];
e281682b
SM		 6254
6255 u8 syndrome[0x20];
6256
b4ff3a36 6257 u8 reserved_at_40[0x40];
e281682b
SM		 6258};
6259
6260struct mlx5_ifc_destroy_tir_in_bits {
6261 u8 opcode[0x10];
bd371975 6262 u8 uid[0x10];
e281682b 6263
b4ff3a36 6264 u8 reserved_at_20[0x10];
e281682b
SM		 6265 u8 op_mod[0x10];
6266
b4ff3a36 6267 u8 reserved_at_40[0x8];
e281682b
SM		 6268 u8 tirn[0x18];
6269
b4ff3a36 6270 u8 reserved_at_60[0x20];
e281682b
SM		 6271};
6272
6273struct mlx5_ifc_destroy_srq_out_bits {
6274 u8 status[0x8];
b4ff3a36 6275 u8 reserved_at_8[0x18];
e281682b
SM		 6276
6277 u8 syndrome[0x20];
6278
b4ff3a36 6279 u8 reserved_at_40[0x40];
e281682b
SM		 6280};
6281
6282struct mlx5_ifc_destroy_srq_in_bits {
6283 u8 opcode[0x10];
a0d8c054 6284 u8 uid[0x10];
e281682b 6285
b4ff3a36 6286 u8 reserved_at_20[0x10];
e281682b
SM		 6287 u8 op_mod[0x10];
6288
b4ff3a36 6289 u8 reserved_at_40[0x8];
e281682b
SM		 6290 u8 srqn[0x18];
6291
b4ff3a36 6292 u8 reserved_at_60[0x20];
e281682b
SM		 6293};
6294
6295struct mlx5_ifc_destroy_sq_out_bits {
6296 u8 status[0x8];
b4ff3a36 6297 u8 reserved_at_8[0x18];
e281682b
SM		 6298
6299 u8 syndrome[0x20];
6300
b4ff3a36 6301 u8 reserved_at_40[0x40];
e281682b
SM		 6302};
6303
6304struct mlx5_ifc_destroy_sq_in_bits {
6305 u8 opcode[0x10];
430ae0d5 6306 u8 uid[0x10];
e281682b 6307
b4ff3a36 6308 u8 reserved_at_20[0x10];
e281682b
SM		 6309 u8 op_mod[0x10];
6310
b4ff3a36 6311 u8 reserved_at_40[0x8];
e281682b
SM		 6312 u8 sqn[0x18];
6313
b4ff3a36 6314 u8 reserved_at_60[0x20];
e281682b
SM		 6315};
6316
813f8540
MHY		 6317struct mlx5_ifc_destroy_scheduling_element_out_bits {
6318 u8 status[0x8];
6319 u8 reserved_at_8[0x18];
6320
6321 u8 syndrome[0x20];
6322
6323 u8 reserved_at_40[0x1c0];
6324};
6325
6326struct mlx5_ifc_destroy_scheduling_element_in_bits {
6327 u8 opcode[0x10];
6328 u8 reserved_at_10[0x10];
6329
6330 u8 reserved_at_20[0x10];
6331 u8 op_mod[0x10];
6332
6333 u8 scheduling_hierarchy[0x8];
6334 u8 reserved_at_48[0x18];
6335
6336 u8 scheduling_element_id[0x20];
6337
6338 u8 reserved_at_80[0x180];
6339};
6340
e281682b
SM		 6341struct mlx5_ifc_destroy_rqt_out_bits {
6342 u8 status[0x8];
b4ff3a36 6343 u8 reserved_at_8[0x18];
e281682b
SM		 6344
6345 u8 syndrome[0x20];
6346
b4ff3a36 6347 u8 reserved_at_40[0x40];
e281682b
SM		 6348};
6349
6350struct mlx5_ifc_destroy_rqt_in_bits {
6351 u8 opcode[0x10];
bd371975 6352 u8 uid[0x10];
e281682b 6353
b4ff3a36 6354 u8 reserved_at_20[0x10];
e281682b
SM		 6355 u8 op_mod[0x10];
6356
b4ff3a36 6357 u8 reserved_at_40[0x8];
e281682b
SM		 6358 u8 rqtn[0x18];
6359
b4ff3a36 6360 u8 reserved_at_60[0x20];
e281682b
SM		 6361};
6362
6363struct mlx5_ifc_destroy_rq_out_bits {
6364 u8 status[0x8];
b4ff3a36 6365 u8 reserved_at_8[0x18];
e281682b
SM		 6366
6367 u8 syndrome[0x20];
6368
b4ff3a36 6369 u8 reserved_at_40[0x40];
e281682b
SM		 6370};
6371
6372struct mlx5_ifc_destroy_rq_in_bits {
6373 u8 opcode[0x10];
d269b3af 6374 u8 uid[0x10];
e281682b 6375
b4ff3a36 6376 u8 reserved_at_20[0x10];
e281682b
SM		 6377 u8 op_mod[0x10];
6378
b4ff3a36 6379 u8 reserved_at_40[0x8];
e281682b
SM		 6380 u8 rqn[0x18];
6381
b4ff3a36 6382 u8 reserved_at_60[0x20];
e281682b
SM		 6383};
6384
c1e0bfc1
MG		 6385struct mlx5_ifc_set_delay_drop_params_in_bits {
6386 u8 opcode[0x10];
6387 u8 reserved_at_10[0x10];
6388
6389 u8 reserved_at_20[0x10];
6390 u8 op_mod[0x10];
6391
6392 u8 reserved_at_40[0x20];
6393
6394 u8 reserved_at_60[0x10];
6395 u8 delay_drop_timeout[0x10];
6396};
6397
6398struct mlx5_ifc_set_delay_drop_params_out_bits {
6399 u8 status[0x8];
6400 u8 reserved_at_8[0x18];
6401
6402 u8 syndrome[0x20];
6403
6404 u8 reserved_at_40[0x40];
6405};
6406
e281682b
SM		 6407struct mlx5_ifc_destroy_rmp_out_bits {
6408 u8 status[0x8];
b4ff3a36 6409 u8 reserved_at_8[0x18];
e281682b
SM		 6410
6411 u8 syndrome[0x20];
6412
b4ff3a36 6413 u8 reserved_at_40[0x40];
e281682b
SM		 6414};
6415
6416struct mlx5_ifc_destroy_rmp_in_bits {
6417 u8 opcode[0x10];
a0d8c054 6418 u8 uid[0x10];
e281682b 6419
b4ff3a36 6420 u8 reserved_at_20[0x10];
e281682b
SM		 6421 u8 op_mod[0x10];
6422
b4ff3a36 6423 u8 reserved_at_40[0x8];
e281682b
SM		 6424 u8 rmpn[0x18];
6425
b4ff3a36 6426 u8 reserved_at_60[0x20];
e281682b
SM		 6427};
6428
6429struct mlx5_ifc_destroy_qp_out_bits {
6430 u8 status[0x8];
b4ff3a36 6431 u8 reserved_at_8[0x18];
e281682b
SM		 6432
6433 u8 syndrome[0x20];
6434
b4ff3a36 6435 u8 reserved_at_40[0x40];
e281682b
SM		 6436};
6437
6438struct mlx5_ifc_destroy_qp_in_bits {
6439 u8 opcode[0x10];
4ac63ec7 6440 u8 uid[0x10];
e281682b 6441
b4ff3a36 6442 u8 reserved_at_20[0x10];
e281682b
SM		 6443 u8 op_mod[0x10];
6444
b4ff3a36 6445 u8 reserved_at_40[0x8];
e281682b
SM		 6446 u8 qpn[0x18];
6447
b4ff3a36 6448 u8 reserved_at_60[0x20];
e281682b
SM		 6449};
6450
6451struct mlx5_ifc_destroy_psv_out_bits {
6452 u8 status[0x8];
b4ff3a36 6453 u8 reserved_at_8[0x18];
e281682b
SM		 6454
6455 u8 syndrome[0x20];
6456
b4ff3a36 6457 u8 reserved_at_40[0x40];
e281682b
SM		 6458};
6459
6460struct mlx5_ifc_destroy_psv_in_bits {
6461 u8 opcode[0x10];
b4ff3a36 6462 u8 reserved_at_10[0x10];
e281682b 6463
b4ff3a36 6464 u8 reserved_at_20[0x10];
e281682b
SM		 6465 u8 op_mod[0x10];
6466
b4ff3a36 6467 u8 reserved_at_40[0x8];
e281682b
SM		 6468 u8 psvn[0x18];
6469
b4ff3a36 6470 u8 reserved_at_60[0x20];
e281682b
SM		 6471};
6472
6473struct mlx5_ifc_destroy_mkey_out_bits {
6474 u8 status[0x8];
b4ff3a36 6475 u8 reserved_at_8[0x18];
e281682b
SM		 6476
6477 u8 syndrome[0x20];
6478
b4ff3a36 6479 u8 reserved_at_40[0x40];
e281682b
SM		 6480};
6481
6482struct mlx5_ifc_destroy_mkey_in_bits {
6483 u8 opcode[0x10];
b4ff3a36 6484 u8 reserved_at_10[0x10];
e281682b 6485
b4ff3a36 6486 u8 reserved_at_20[0x10];
e281682b
SM		 6487 u8 op_mod[0x10];
6488
b4ff3a36 6489 u8 reserved_at_40[0x8];
e281682b
SM		 6490 u8 mkey_index[0x18];
6491
b4ff3a36 6492 u8 reserved_at_60[0x20];
e281682b
SM		 6493};
6494
6495struct mlx5_ifc_destroy_flow_table_out_bits {
6496 u8 status[0x8];
b4ff3a36 6497 u8 reserved_at_8[0x18];
e281682b
SM		 6498
6499 u8 syndrome[0x20];
6500
b4ff3a36 6501 u8 reserved_at_40[0x40];
e281682b
SM		 6502};
6503
6504struct mlx5_ifc_destroy_flow_table_in_bits {
6505 u8 opcode[0x10];
b4ff3a36 6506 u8 reserved_at_10[0x10];
e281682b 6507
b4ff3a36 6508 u8 reserved_at_20[0x10];
e281682b
SM		 6509 u8 op_mod[0x10];
6510
7d5e1423
SM		 6511 u8 other_vport[0x1];
6512 u8 reserved_at_41[0xf];
6513 u8 vport_number[0x10];
6514
6515 u8 reserved_at_60[0x20];
e281682b
SM		 6516
6517 u8 table_type[0x8];
b4ff3a36 6518 u8 reserved_at_88[0x18];
e281682b 6519
b4ff3a36 6520 u8 reserved_at_a0[0x8];
e281682b
SM		 6521 u8 table_id[0x18];
6522
b4ff3a36 6523 u8 reserved_at_c0[0x140];
e281682b
SM		 6524};
6525
6526struct mlx5_ifc_destroy_flow_group_out_bits {
6527 u8 status[0x8];
b4ff3a36 6528 u8 reserved_at_8[0x18];
e281682b
SM		 6529
6530 u8 syndrome[0x20];
6531
b4ff3a36 6532 u8 reserved_at_40[0x40];
e281682b
SM		 6533};
6534
6535struct mlx5_ifc_destroy_flow_group_in_bits {
6536 u8 opcode[0x10];
b4ff3a36 6537 u8 reserved_at_10[0x10];
e281682b 6538
b4ff3a36 6539 u8 reserved_at_20[0x10];
e281682b
SM		 6540 u8 op_mod[0x10];
6541
7d5e1423
SM		 6542 u8 other_vport[0x1];
6543 u8 reserved_at_41[0xf];
6544 u8 vport_number[0x10];
6545
6546 u8 reserved_at_60[0x20];
e281682b
SM		 6547
6548 u8 table_type[0x8];
b4ff3a36 6549 u8 reserved_at_88[0x18];
e281682b 6550
b4ff3a36 6551 u8 reserved_at_a0[0x8];
e281682b
SM		 6552 u8 table_id[0x18];
6553
6554 u8 group_id[0x20];
6555
b4ff3a36 6556 u8 reserved_at_e0[0x120];
e281682b
SM		 6557};
6558
6559struct mlx5_ifc_destroy_eq_out_bits {
6560 u8 status[0x8];
b4ff3a36 6561 u8 reserved_at_8[0x18];
e281682b
SM		 6562
6563 u8 syndrome[0x20];
6564
b4ff3a36 6565 u8 reserved_at_40[0x40];
e281682b
SM		 6566};
6567
6568struct mlx5_ifc_destroy_eq_in_bits {
6569 u8 opcode[0x10];
b4ff3a36 6570 u8 reserved_at_10[0x10];
e281682b 6571
b4ff3a36 6572 u8 reserved_at_20[0x10];
e281682b
SM		 6573 u8 op_mod[0x10];
6574
b4ff3a36 6575 u8 reserved_at_40[0x18];
e281682b
SM		 6576 u8 eq_number[0x8];
6577
b4ff3a36 6578 u8 reserved_at_60[0x20];
e281682b
SM		 6579};
6580
6581struct mlx5_ifc_destroy_dct_out_bits {
6582 u8 status[0x8];
b4ff3a36 6583 u8 reserved_at_8[0x18];
e281682b
SM		 6584
6585 u8 syndrome[0x20];
6586
b4ff3a36 6587 u8 reserved_at_40[0x40];
e281682b
SM		 6588};
6589
6590struct mlx5_ifc_destroy_dct_in_bits {
6591 u8 opcode[0x10];
774ea6ee 6592 u8 uid[0x10];
e281682b 6593
b4ff3a36 6594 u8 reserved_at_20[0x10];
e281682b
SM		 6595 u8 op_mod[0x10];
6596
b4ff3a36 6597 u8 reserved_at_40[0x8];
e281682b
SM		 6598 u8 dctn[0x18];
6599
b4ff3a36 6600 u8 reserved_at_60[0x20];
e281682b
SM		 6601};
6602
6603struct mlx5_ifc_destroy_cq_out_bits {
6604 u8 status[0x8];
b4ff3a36 6605 u8 reserved_at_8[0x18];
e281682b
SM		 6606
6607 u8 syndrome[0x20];
6608
b4ff3a36 6609 u8 reserved_at_40[0x40];
e281682b
SM		 6610};
6611
6612struct mlx5_ifc_destroy_cq_in_bits {
6613 u8 opcode[0x10];
9ba481e2 6614 u8 uid[0x10];
e281682b 6615
b4ff3a36 6616 u8 reserved_at_20[0x10];
e281682b
SM		 6617 u8 op_mod[0x10];
6618
b4ff3a36 6619 u8 reserved_at_40[0x8];
e281682b
SM		 6620 u8 cqn[0x18];
6621
b4ff3a36 6622 u8 reserved_at_60[0x20];
e281682b
SM		 6623};
6624
6625struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6626 u8 status[0x8];
b4ff3a36 6627 u8 reserved_at_8[0x18];
e281682b
SM		 6628
6629 u8 syndrome[0x20];
6630
b4ff3a36 6631 u8 reserved_at_40[0x40];
e281682b
SM		 6632};
6633
6634struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6635 u8 opcode[0x10];
b4ff3a36 6636 u8 reserved_at_10[0x10];
e281682b 6637
b4ff3a36 6638 u8 reserved_at_20[0x10];
e281682b
SM		 6639 u8 op_mod[0x10];
6640
b4ff3a36 6641 u8 reserved_at_40[0x20];
e281682b 6642
b4ff3a36 6643 u8 reserved_at_60[0x10];
e281682b
SM		 6644 u8 vxlan_udp_port[0x10];
6645};
6646
6647struct mlx5_ifc_delete_l2_table_entry_out_bits {
6648 u8 status[0x8];
b4ff3a36 6649 u8 reserved_at_8[0x18];
e281682b
SM		 6650
6651 u8 syndrome[0x20];
6652
b4ff3a36 6653 u8 reserved_at_40[0x40];
e281682b
SM		 6654};
6655
6656struct mlx5_ifc_delete_l2_table_entry_in_bits {
6657 u8 opcode[0x10];
b4ff3a36 6658 u8 reserved_at_10[0x10];
e281682b 6659
b4ff3a36 6660 u8 reserved_at_20[0x10];
e281682b
SM		 6661 u8 op_mod[0x10];
6662
b4ff3a36 6663 u8 reserved_at_40[0x60];
e281682b 6664
b4ff3a36 6665 u8 reserved_at_a0[0x8];
e281682b
SM		 6666 u8 table_index[0x18];
6667
b4ff3a36 6668 u8 reserved_at_c0[0x140];
e281682b
SM		 6669};
6670
6671struct mlx5_ifc_delete_fte_out_bits {
6672 u8 status[0x8];
b4ff3a36 6673 u8 reserved_at_8[0x18];
e281682b
SM		 6674
6675 u8 syndrome[0x20];
6676
b4ff3a36 6677 u8 reserved_at_40[0x40];
e281682b
SM		 6678};
6679
6680struct mlx5_ifc_delete_fte_in_bits {
6681 u8 opcode[0x10];
b4ff3a36 6682 u8 reserved_at_10[0x10];
e281682b 6683
b4ff3a36 6684 u8 reserved_at_20[0x10];
e281682b
SM		 6685 u8 op_mod[0x10];
6686
7d5e1423
SM		 6687 u8 other_vport[0x1];
6688 u8 reserved_at_41[0xf];
6689 u8 vport_number[0x10];
6690
6691 u8 reserved_at_60[0x20];
e281682b
SM		 6692
6693 u8 table_type[0x8];
b4ff3a36 6694 u8 reserved_at_88[0x18];
e281682b 6695
b4ff3a36 6696 u8 reserved_at_a0[0x8];
e281682b
SM		 6697 u8 table_id[0x18];
6698
b4ff3a36 6699 u8 reserved_at_c0[0x40];
e281682b
SM		 6700
6701 u8 flow_index[0x20];
6702
b4ff3a36 6703 u8 reserved_at_120[0xe0];
e281682b
SM		 6704};
6705
6706struct mlx5_ifc_dealloc_xrcd_out_bits {
6707 u8 status[0x8];
b4ff3a36 6708 u8 reserved_at_8[0x18];
e281682b
SM		 6709
6710 u8 syndrome[0x20];
6711
b4ff3a36 6712 u8 reserved_at_40[0x40];
e281682b
SM		 6713};
6714
6715struct mlx5_ifc_dealloc_xrcd_in_bits {
6716 u8 opcode[0x10];
bd371975 6717 u8 uid[0x10];
e281682b 6718
b4ff3a36 6719 u8 reserved_at_20[0x10];
e281682b
SM		 6720 u8 op_mod[0x10];
6721
b4ff3a36 6722 u8 reserved_at_40[0x8];
e281682b
SM		 6723 u8 xrcd[0x18];
6724
b4ff3a36 6725 u8 reserved_at_60[0x20];
e281682b
SM		 6726};
6727
6728struct mlx5_ifc_dealloc_uar_out_bits {
6729 u8 status[0x8];
b4ff3a36 6730 u8 reserved_at_8[0x18];
e281682b
SM		 6731
6732 u8 syndrome[0x20];
6733
b4ff3a36 6734 u8 reserved_at_40[0x40];
e281682b
SM		 6735};
6736
6737struct mlx5_ifc_dealloc_uar_in_bits {
6738 u8 opcode[0x10];
b4ff3a36 6739 u8 reserved_at_10[0x10];
e281682b 6740
b4ff3a36 6741 u8 reserved_at_20[0x10];
e281682b
SM		 6742 u8 op_mod[0x10];
6743
b4ff3a36 6744 u8 reserved_at_40[0x8];
e281682b
SM		 6745 u8 uar[0x18];
6746
b4ff3a36 6747 u8 reserved_at_60[0x20];
e281682b
SM		 6748};
6749
6750struct mlx5_ifc_dealloc_transport_domain_out_bits {
6751 u8 status[0x8];
b4ff3a36 6752 u8 reserved_at_8[0x18];
e281682b
SM		 6753
6754 u8 syndrome[0x20];
6755
b4ff3a36 6756 u8 reserved_at_40[0x40];
e281682b
SM		 6757};
6758
6759struct mlx5_ifc_dealloc_transport_domain_in_bits {
6760 u8 opcode[0x10];
71bef2fd 6761 u8 uid[0x10];
e281682b 6762
b4ff3a36 6763 u8 reserved_at_20[0x10];
e281682b
SM		 6764 u8 op_mod[0x10];
6765
b4ff3a36 6766 u8 reserved_at_40[0x8];
e281682b
SM		 6767 u8 transport_domain[0x18];
6768
b4ff3a36 6769 u8 reserved_at_60[0x20];
e281682b
SM		 6770};
6771
6772struct mlx5_ifc_dealloc_q_counter_out_bits {
6773 u8 status[0x8];
b4ff3a36 6774 u8 reserved_at_8[0x18];
e281682b
SM		 6775
6776 u8 syndrome[0x20];
6777
b4ff3a36 6778 u8 reserved_at_40[0x40];
e281682b
SM		 6779};
6780
6781struct mlx5_ifc_dealloc_q_counter_in_bits {
6782 u8 opcode[0x10];
b4ff3a36 6783 u8 reserved_at_10[0x10];
e281682b 6784
b4ff3a36 6785 u8 reserved_at_20[0x10];
e281682b
SM		 6786 u8 op_mod[0x10];
6787
b4ff3a36 6788 u8 reserved_at_40[0x18];
e281682b
SM		 6789 u8 counter_set_id[0x8];
6790
b4ff3a36 6791 u8 reserved_at_60[0x20];
e281682b
SM		 6792};
6793
6794struct mlx5_ifc_dealloc_pd_out_bits {
6795 u8 status[0x8];
b4ff3a36 6796 u8 reserved_at_8[0x18];
e281682b
SM		 6797
6798 u8 syndrome[0x20];
6799
b4ff3a36 6800 u8 reserved_at_40[0x40];
e281682b
SM		 6801};
6802
6803struct mlx5_ifc_dealloc_pd_in_bits {
6804 u8 opcode[0x10];
bd371975 6805 u8 uid[0x10];
e281682b 6806
b4ff3a36 6807 u8 reserved_at_20[0x10];
e281682b
SM		 6808 u8 op_mod[0x10];
6809
b4ff3a36 6810 u8 reserved_at_40[0x8];
e281682b
SM		 6811 u8 pd[0x18];
6812
b4ff3a36 6813 u8 reserved_at_60[0x20];
e281682b
SM		 6814};
6815
9dc0b289
AV		 6816struct mlx5_ifc_dealloc_flow_counter_out_bits {
6817 u8 status[0x8];
6818 u8 reserved_at_8[0x18];
6819
6820 u8 syndrome[0x20];
6821
6822 u8 reserved_at_40[0x40];
6823};
6824
6825struct mlx5_ifc_dealloc_flow_counter_in_bits {
6826 u8 opcode[0x10];
6827 u8 reserved_at_10[0x10];
6828
6829 u8 reserved_at_20[0x10];
6830 u8 op_mod[0x10];
6831
a8ffcc74 6832 u8 flow_counter_id[0x20];
9dc0b289
AV		 6833
6834 u8 reserved_at_60[0x20];
6835};
6836
7486216b
SM		 6837struct mlx5_ifc_create_xrq_out_bits {
6838 u8 status[0x8];
6839 u8 reserved_at_8[0x18];
6840
6841 u8 syndrome[0x20];
6842
6843 u8 reserved_at_40[0x8];
6844 u8 xrqn[0x18];
6845
6846 u8 reserved_at_60[0x20];
6847};
6848
6849struct mlx5_ifc_create_xrq_in_bits {
6850 u8 opcode[0x10];
a0d8c054 6851 u8 uid[0x10];
7486216b
SM		 6852
6853 u8 reserved_at_20[0x10];
6854 u8 op_mod[0x10];
6855
6856 u8 reserved_at_40[0x40];
6857
6858 struct mlx5_ifc_xrqc_bits xrq_context;
6859};
6860
e281682b
SM		 6861struct mlx5_ifc_create_xrc_srq_out_bits {
6862 u8 status[0x8];
b4ff3a36 6863 u8 reserved_at_8[0x18];
e281682b
SM		 6864
6865 u8 syndrome[0x20];
6866
b4ff3a36 6867 u8 reserved_at_40[0x8];
e281682b
SM		 6868 u8 xrc_srqn[0x18];
6869
b4ff3a36 6870 u8 reserved_at_60[0x20];
e281682b
SM		 6871};
6872
6873struct mlx5_ifc_create_xrc_srq_in_bits {
6874 u8 opcode[0x10];
a0d8c054 6875 u8 uid[0x10];
e281682b 6876
b4ff3a36 6877 u8 reserved_at_20[0x10];
e281682b
SM		 6878 u8 op_mod[0x10];
6879
b4ff3a36 6880 u8 reserved_at_40[0x40];
e281682b
SM		 6881
6882 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6883
99b77fef
YH		 6884 u8 reserved_at_280[0x60];
6885
bd371975 6886 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 6887 u8 reserved_at_2e1[0x1f];
6888
6889 u8 reserved_at_300[0x580];
e281682b
SM		 6890
6891 u8 pas[0][0x40];
6892};
6893
6894struct mlx5_ifc_create_tis_out_bits {
6895 u8 status[0x8];
b4ff3a36 6896 u8 reserved_at_8[0x18];
e281682b
SM		 6897
6898 u8 syndrome[0x20];
6899
b4ff3a36 6900 u8 reserved_at_40[0x8];
e281682b
SM		 6901 u8 tisn[0x18];
6902
b4ff3a36 6903 u8 reserved_at_60[0x20];
e281682b
SM		 6904};
6905
6906struct mlx5_ifc_create_tis_in_bits {
6907 u8 opcode[0x10];
bd371975 6908 u8 uid[0x10];
e281682b 6909
b4ff3a36 6910 u8 reserved_at_20[0x10];
e281682b
SM		 6911 u8 op_mod[0x10];
6912
b4ff3a36 6913 u8 reserved_at_40[0xc0];
e281682b
SM		 6914
6915 struct mlx5_ifc_tisc_bits ctx;
6916};
6917
6918struct mlx5_ifc_create_tir_out_bits {
6919 u8 status[0x8];
3e070470 6920 u8 icm_address_63_40[0x18];
e281682b
SM		 6921
6922 u8 syndrome[0x20];
6923
3e070470 6924 u8 icm_address_39_32[0x8];
e281682b
SM		 6925 u8 tirn[0x18];
6926
3e070470 6927 u8 icm_address_31_0[0x20];
e281682b
SM		 6928};
6929
6930struct mlx5_ifc_create_tir_in_bits {
6931 u8 opcode[0x10];
bd371975 6932 u8 uid[0x10];
e281682b 6933
b4ff3a36 6934 u8 reserved_at_20[0x10];
e281682b
SM		 6935 u8 op_mod[0x10];
6936
b4ff3a36 6937 u8 reserved_at_40[0xc0];
e281682b
SM		 6938
6939 struct mlx5_ifc_tirc_bits ctx;
6940};
6941
6942struct mlx5_ifc_create_srq_out_bits {
6943 u8 status[0x8];
b4ff3a36 6944 u8 reserved_at_8[0x18];
e281682b
SM		 6945
6946 u8 syndrome[0x20];
6947
b4ff3a36 6948 u8 reserved_at_40[0x8];
e281682b
SM		 6949 u8 srqn[0x18];
6950
b4ff3a36 6951 u8 reserved_at_60[0x20];
e281682b
SM		 6952};
6953
6954struct mlx5_ifc_create_srq_in_bits {
6955 u8 opcode[0x10];
a0d8c054 6956 u8 uid[0x10];
e281682b 6957
b4ff3a36 6958 u8 reserved_at_20[0x10];
e281682b
SM		 6959 u8 op_mod[0x10];
6960
b4ff3a36 6961 u8 reserved_at_40[0x40];
e281682b
SM		 6962
6963 struct mlx5_ifc_srqc_bits srq_context_entry;
6964
b4ff3a36 6965 u8 reserved_at_280[0x600];
e281682b
SM		 6966
6967 u8 pas[0][0x40];
6968};
6969
6970struct mlx5_ifc_create_sq_out_bits {
6971 u8 status[0x8];
b4ff3a36 6972 u8 reserved_at_8[0x18];
e281682b
SM		 6973
6974 u8 syndrome[0x20];
6975
b4ff3a36 6976 u8 reserved_at_40[0x8];
e281682b
SM		 6977 u8 sqn[0x18];
6978
b4ff3a36 6979 u8 reserved_at_60[0x20];
e281682b
SM		 6980};
6981
6982struct mlx5_ifc_create_sq_in_bits {
6983 u8 opcode[0x10];
430ae0d5 6984 u8 uid[0x10];
e281682b 6985
b4ff3a36 6986 u8 reserved_at_20[0x10];
e281682b
SM		 6987 u8 op_mod[0x10];
6988
b4ff3a36 6989 u8 reserved_at_40[0xc0];
e281682b
SM		 6990
6991 struct mlx5_ifc_sqc_bits ctx;
6992};
6993
813f8540
MHY		 6994struct mlx5_ifc_create_scheduling_element_out_bits {
6995 u8 status[0x8];
6996 u8 reserved_at_8[0x18];
6997
6998 u8 syndrome[0x20];
6999
7000 u8 reserved_at_40[0x40];
7001
7002 u8 scheduling_element_id[0x20];
7003
7004 u8 reserved_at_a0[0x160];
7005};
7006
7007struct mlx5_ifc_create_scheduling_element_in_bits {
7008 u8 opcode[0x10];
7009 u8 reserved_at_10[0x10];
7010
7011 u8 reserved_at_20[0x10];
7012 u8 op_mod[0x10];
7013
7014 u8 scheduling_hierarchy[0x8];
7015 u8 reserved_at_48[0x18];
7016
7017 u8 reserved_at_60[0xa0];
7018
7019 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7020
7021 u8 reserved_at_300[0x100];
7022};
7023
e281682b
SM		 7024struct mlx5_ifc_create_rqt_out_bits {
7025 u8 status[0x8];
b4ff3a36 7026 u8 reserved_at_8[0x18];
e281682b
SM		 7027
7028 u8 syndrome[0x20];
7029
b4ff3a36 7030 u8 reserved_at_40[0x8];
e281682b
SM		 7031 u8 rqtn[0x18];
7032
b4ff3a36 7033 u8 reserved_at_60[0x20];
e281682b
SM		 7034};
7035
7036struct mlx5_ifc_create_rqt_in_bits {
7037 u8 opcode[0x10];
bd371975 7038 u8 uid[0x10];
e281682b 7039
b4ff3a36 7040 u8 reserved_at_20[0x10];
e281682b
SM		 7041 u8 op_mod[0x10];
7042
b4ff3a36 7043 u8 reserved_at_40[0xc0];
e281682b
SM		 7044
7045 struct mlx5_ifc_rqtc_bits rqt_context;
7046};
7047
7048struct mlx5_ifc_create_rq_out_bits {
7049 u8 status[0x8];
b4ff3a36 7050 u8 reserved_at_8[0x18];
e281682b
SM		 7051
7052 u8 syndrome[0x20];
7053
b4ff3a36 7054 u8 reserved_at_40[0x8];
e281682b
SM		 7055 u8 rqn[0x18];
7056
b4ff3a36 7057 u8 reserved_at_60[0x20];
e281682b
SM		 7058};
7059
7060struct mlx5_ifc_create_rq_in_bits {
7061 u8 opcode[0x10];
d269b3af 7062 u8 uid[0x10];
e281682b 7063
b4ff3a36 7064 u8 reserved_at_20[0x10];
e281682b
SM		 7065 u8 op_mod[0x10];
7066
b4ff3a36 7067 u8 reserved_at_40[0xc0];
e281682b
SM		 7068
7069 struct mlx5_ifc_rqc_bits ctx;
7070};
7071
7072struct mlx5_ifc_create_rmp_out_bits {
7073 u8 status[0x8];
b4ff3a36 7074 u8 reserved_at_8[0x18];
e281682b
SM		 7075
7076 u8 syndrome[0x20];
7077
b4ff3a36 7078 u8 reserved_at_40[0x8];
e281682b
SM		 7079 u8 rmpn[0x18];
7080
b4ff3a36 7081 u8 reserved_at_60[0x20];
e281682b
SM		 7082};
7083
7084struct mlx5_ifc_create_rmp_in_bits {
7085 u8 opcode[0x10];
a0d8c054 7086 u8 uid[0x10];
e281682b 7087
b4ff3a36 7088 u8 reserved_at_20[0x10];
e281682b
SM		 7089 u8 op_mod[0x10];
7090
b4ff3a36 7091 u8 reserved_at_40[0xc0];
e281682b
SM		 7092
7093 struct mlx5_ifc_rmpc_bits ctx;
7094};
7095
7096struct mlx5_ifc_create_qp_out_bits {
7097 u8 status[0x8];
b4ff3a36 7098 u8 reserved_at_8[0x18];
e281682b
SM		 7099
7100 u8 syndrome[0x20];
7101
b4ff3a36 7102 u8 reserved_at_40[0x8];
e281682b
SM		 7103 u8 qpn[0x18];
7104
b4ff3a36 7105 u8 reserved_at_60[0x20];
e281682b
SM		 7106};
7107
7108struct mlx5_ifc_create_qp_in_bits {
7109 u8 opcode[0x10];
4ac63ec7 7110 u8 uid[0x10];
e281682b 7111
b4ff3a36 7112 u8 reserved_at_20[0x10];
e281682b
SM		 7113 u8 op_mod[0x10];
7114
b4ff3a36 7115 u8 reserved_at_40[0x40];
e281682b
SM		 7116
7117 u8 opt_param_mask[0x20];
7118
b4ff3a36 7119 u8 reserved_at_a0[0x20];
e281682b
SM		 7120
7121 struct mlx5_ifc_qpc_bits qpc;
7122
bd371975
LR		 7123 u8 reserved_at_800[0x60];
7124
7125 u8 wq_umem_valid[0x1];
7126 u8 reserved_at_861[0x1f];
e281682b
SM		 7127
7128 u8 pas[0][0x40];
7129};
7130
7131struct mlx5_ifc_create_psv_out_bits {
7132 u8 status[0x8];
b4ff3a36 7133 u8 reserved_at_8[0x18];
e281682b
SM		 7134
7135 u8 syndrome[0x20];
7136
b4ff3a36 7137 u8 reserved_at_40[0x40];
e281682b 7138
b4ff3a36 7139 u8 reserved_at_80[0x8];
e281682b
SM		 7140 u8 psv0_index[0x18];
7141
b4ff3a36 7142 u8 reserved_at_a0[0x8];
e281682b
SM		 7143 u8 psv1_index[0x18];
7144
b4ff3a36 7145 u8 reserved_at_c0[0x8];
e281682b
SM		 7146 u8 psv2_index[0x18];
7147
b4ff3a36 7148 u8 reserved_at_e0[0x8];
e281682b
SM		 7149 u8 psv3_index[0x18];
7150};
7151
7152struct mlx5_ifc_create_psv_in_bits {
7153 u8 opcode[0x10];
b4ff3a36 7154 u8 reserved_at_10[0x10];
e281682b 7155
b4ff3a36 7156 u8 reserved_at_20[0x10];
e281682b
SM		 7157 u8 op_mod[0x10];
7158
7159 u8 num_psv[0x4];
b4ff3a36 7160 u8 reserved_at_44[0x4];
e281682b
SM		 7161 u8 pd[0x18];
7162
b4ff3a36 7163 u8 reserved_at_60[0x20];
e281682b
SM		 7164};
7165
7166struct mlx5_ifc_create_mkey_out_bits {
7167 u8 status[0x8];
b4ff3a36 7168 u8 reserved_at_8[0x18];
e281682b
SM		 7169
7170 u8 syndrome[0x20];
7171
b4ff3a36 7172 u8 reserved_at_40[0x8];
e281682b
SM		 7173 u8 mkey_index[0x18];
7174
b4ff3a36 7175 u8 reserved_at_60[0x20];
e281682b
SM		 7176};
7177
7178struct mlx5_ifc_create_mkey_in_bits {
7179 u8 opcode[0x10];
b4ff3a36 7180 u8 reserved_at_10[0x10];
e281682b 7181
b4ff3a36 7182 u8 reserved_at_20[0x10];
e281682b
SM		 7183 u8 op_mod[0x10];
7184
b4ff3a36 7185 u8 reserved_at_40[0x20];
e281682b
SM		 7186
7187 u8 pg_access[0x1];
bd371975
LR		 7188 u8 mkey_umem_valid[0x1];
7189 u8 reserved_at_62[0x1e];
e281682b
SM		 7190
7191 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7192
b4ff3a36 7193 u8 reserved_at_280[0x80];
e281682b
SM		 7194
7195 u8 translations_octword_actual_size[0x20];
7196
b4ff3a36 7197 u8 reserved_at_320[0x560];
e281682b
SM		 7198
7199 u8 klm_pas_mtt[0][0x20];
7200};
7201
7202struct mlx5_ifc_create_flow_table_out_bits {
7203 u8 status[0x8];
b4ff3a36 7204 u8 reserved_at_8[0x18];
e281682b
SM		 7205
7206 u8 syndrome[0x20];
7207
b4ff3a36 7208 u8 reserved_at_40[0x8];
e281682b
SM		 7209 u8 table_id[0x18];
7210
b4ff3a36 7211 u8 reserved_at_60[0x20];
e281682b
SM		 7212};
7213
0c90e9c6 7214struct mlx5_ifc_flow_table_context_bits {
60786f09 7215 u8 reformat_en[0x1];
0c90e9c6
MG		 7216 u8 decap_en[0x1];
7217 u8 reserved_at_2[0x2];
7218 u8 table_miss_action[0x4];
7219 u8 level[0x8];
7220 u8 reserved_at_10[0x8];
7221 u8 log_size[0x8];
7222
7223 u8 reserved_at_20[0x8];
7224 u8 table_miss_id[0x18];
7225
7226 u8 reserved_at_40[0x8];
7227 u8 lag_master_next_table_id[0x18];
7228
7229 u8 reserved_at_60[0xe0];
7230};
7231
e281682b
SM		 7232struct mlx5_ifc_create_flow_table_in_bits {
7233 u8 opcode[0x10];
b4ff3a36 7234 u8 reserved_at_10[0x10];
e281682b 7235
b4ff3a36 7236 u8 reserved_at_20[0x10];
e281682b
SM		 7237 u8 op_mod[0x10];
7238
7d5e1423
SM		 7239 u8 other_vport[0x1];
7240 u8 reserved_at_41[0xf];
7241 u8 vport_number[0x10];
7242
7243 u8 reserved_at_60[0x20];
e281682b
SM		 7244
7245 u8 table_type[0x8];
b4ff3a36 7246 u8 reserved_at_88[0x18];
e281682b 7247
b4ff3a36 7248 u8 reserved_at_a0[0x20];
e281682b 7249
0c90e9c6 7250 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 7251};
7252
7253struct mlx5_ifc_create_flow_group_out_bits {
7254 u8 status[0x8];
b4ff3a36 7255 u8 reserved_at_8[0x18];
e281682b
SM		 7256
7257 u8 syndrome[0x20];
7258
b4ff3a36 7259 u8 reserved_at_40[0x8];
e281682b
SM		 7260 u8 group_id[0x18];
7261
b4ff3a36 7262 u8 reserved_at_60[0x20];
e281682b
SM		 7263};
7264
7265enum {
71c6e863
AL		 7266 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7267 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7268 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7269 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 7270};
7271
7272struct mlx5_ifc_create_flow_group_in_bits {
7273 u8 opcode[0x10];
b4ff3a36 7274 u8 reserved_at_10[0x10];
e281682b 7275
b4ff3a36 7276 u8 reserved_at_20[0x10];
e281682b
SM		 7277 u8 op_mod[0x10];
7278
7d5e1423
SM		 7279 u8 other_vport[0x1];
7280 u8 reserved_at_41[0xf];
7281 u8 vport_number[0x10];
7282
7283 u8 reserved_at_60[0x20];
e281682b
SM		 7284
7285 u8 table_type[0x8];
b4ff3a36 7286 u8 reserved_at_88[0x18];
e281682b 7287
b4ff3a36 7288 u8 reserved_at_a0[0x8];
e281682b
SM		 7289 u8 table_id[0x18];
7290
3e99df87
SK		 7291 u8 source_eswitch_owner_vhca_id_valid[0x1];
7292
7293 u8 reserved_at_c1[0x1f];
e281682b
SM		 7294
7295 u8 start_flow_index[0x20];
7296
b4ff3a36 7297 u8 reserved_at_100[0x20];
e281682b
SM		 7298
7299 u8 end_flow_index[0x20];
7300
b4ff3a36 7301 u8 reserved_at_140[0xa0];
e281682b 7302
b4ff3a36 7303 u8 reserved_at_1e0[0x18];
e281682b
SM		 7304 u8 match_criteria_enable[0x8];
7305
7306 struct mlx5_ifc_fte_match_param_bits match_criteria;
7307
b4ff3a36 7308 u8 reserved_at_1200[0xe00];
e281682b
SM		 7309};
7310
7311struct mlx5_ifc_create_eq_out_bits {
7312 u8 status[0x8];
b4ff3a36 7313 u8 reserved_at_8[0x18];
e281682b
SM		 7314
7315 u8 syndrome[0x20];
7316
b4ff3a36 7317 u8 reserved_at_40[0x18];
e281682b
SM		 7318 u8 eq_number[0x8];
7319
b4ff3a36 7320 u8 reserved_at_60[0x20];
e281682b
SM		 7321};
7322
7323struct mlx5_ifc_create_eq_in_bits {
7324 u8 opcode[0x10];
b4ff3a36 7325 u8 reserved_at_10[0x10];
e281682b 7326
b4ff3a36 7327 u8 reserved_at_20[0x10];
e281682b
SM		 7328 u8 op_mod[0x10];
7329
b4ff3a36 7330 u8 reserved_at_40[0x40];
e281682b
SM		 7331
7332 struct mlx5_ifc_eqc_bits eq_context_entry;
7333
b4ff3a36 7334 u8 reserved_at_280[0x40];
e281682b
SM		 7335
7336 u8 event_bitmask[0x40];
7337
b4ff3a36 7338 u8 reserved_at_300[0x580];
e281682b
SM		 7339
7340 u8 pas[0][0x40];
7341};
7342
7343struct mlx5_ifc_create_dct_out_bits {
7344 u8 status[0x8];
b4ff3a36 7345 u8 reserved_at_8[0x18];
e281682b
SM		 7346
7347 u8 syndrome[0x20];
7348
b4ff3a36 7349 u8 reserved_at_40[0x8];
e281682b
SM		 7350 u8 dctn[0x18];
7351
b4ff3a36 7352 u8 reserved_at_60[0x20];
e281682b
SM		 7353};
7354
7355struct mlx5_ifc_create_dct_in_bits {
7356 u8 opcode[0x10];
774ea6ee 7357 u8 uid[0x10];
e281682b 7358
b4ff3a36 7359 u8 reserved_at_20[0x10];
e281682b
SM		 7360 u8 op_mod[0x10];
7361
b4ff3a36 7362 u8 reserved_at_40[0x40];
e281682b
SM		 7363
7364 struct mlx5_ifc_dctc_bits dct_context_entry;
7365
b4ff3a36 7366 u8 reserved_at_280[0x180];
e281682b
SM		 7367};
7368
7369struct mlx5_ifc_create_cq_out_bits {
7370 u8 status[0x8];
b4ff3a36 7371 u8 reserved_at_8[0x18];
e281682b
SM		 7372
7373 u8 syndrome[0x20];
7374
b4ff3a36 7375 u8 reserved_at_40[0x8];
e281682b
SM		 7376 u8 cqn[0x18];
7377
b4ff3a36 7378 u8 reserved_at_60[0x20];
e281682b
SM		 7379};
7380
7381struct mlx5_ifc_create_cq_in_bits {
7382 u8 opcode[0x10];
9ba481e2 7383 u8 uid[0x10];
e281682b 7384
b4ff3a36 7385 u8 reserved_at_20[0x10];
e281682b
SM		 7386 u8 op_mod[0x10];
7387
b4ff3a36 7388 u8 reserved_at_40[0x40];
e281682b
SM		 7389
7390 struct mlx5_ifc_cqc_bits cq_context;
7391
bd371975
LR		 7392 u8 reserved_at_280[0x60];
7393
7394 u8 cq_umem_valid[0x1];
7395 u8 reserved_at_2e1[0x59f];
e281682b
SM		 7396
7397 u8 pas[0][0x40];
7398};
7399
7400struct mlx5_ifc_config_int_moderation_out_bits {
7401 u8 status[0x8];
b4ff3a36 7402 u8 reserved_at_8[0x18];
e281682b
SM		 7403
7404 u8 syndrome[0x20];
7405
b4ff3a36 7406 u8 reserved_at_40[0x4];
e281682b
SM		 7407 u8 min_delay[0xc];
7408 u8 int_vector[0x10];
7409
b4ff3a36 7410 u8 reserved_at_60[0x20];
e281682b
SM		 7411};
7412
7413enum {
7414 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7415 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7416};
7417
7418struct mlx5_ifc_config_int_moderation_in_bits {
7419 u8 opcode[0x10];
b4ff3a36 7420 u8 reserved_at_10[0x10];
e281682b 7421
b4ff3a36 7422 u8 reserved_at_20[0x10];
e281682b
SM		 7423 u8 op_mod[0x10];
7424
b4ff3a36 7425 u8 reserved_at_40[0x4];
e281682b
SM		 7426 u8 min_delay[0xc];
7427 u8 int_vector[0x10];
7428
b4ff3a36 7429 u8 reserved_at_60[0x20];
e281682b
SM		 7430};
7431
7432struct mlx5_ifc_attach_to_mcg_out_bits {
7433 u8 status[0x8];
b4ff3a36 7434 u8 reserved_at_8[0x18];
e281682b
SM		 7435
7436 u8 syndrome[0x20];
7437
b4ff3a36 7438 u8 reserved_at_40[0x40];
e281682b
SM		 7439};
7440
7441struct mlx5_ifc_attach_to_mcg_in_bits {
7442 u8 opcode[0x10];
bd371975 7443 u8 uid[0x10];
e281682b 7444
b4ff3a36 7445 u8 reserved_at_20[0x10];
e281682b
SM		 7446 u8 op_mod[0x10];
7447
b4ff3a36 7448 u8 reserved_at_40[0x8];
e281682b
SM		 7449 u8 qpn[0x18];
7450
b4ff3a36 7451 u8 reserved_at_60[0x20];
e281682b
SM		 7452
7453 u8 multicast_gid[16][0x8];
7454};
7455
7486216b
SM		 7456struct mlx5_ifc_arm_xrq_out_bits {
7457 u8 status[0x8];
7458 u8 reserved_at_8[0x18];
7459
7460 u8 syndrome[0x20];
7461
7462 u8 reserved_at_40[0x40];
7463};
7464
7465struct mlx5_ifc_arm_xrq_in_bits {
7466 u8 opcode[0x10];
7467 u8 reserved_at_10[0x10];
7468
7469 u8 reserved_at_20[0x10];
7470 u8 op_mod[0x10];
7471
7472 u8 reserved_at_40[0x8];
7473 u8 xrqn[0x18];
7474
7475 u8 reserved_at_60[0x10];
7476 u8 lwm[0x10];
7477};
7478
e281682b
SM		 7479struct mlx5_ifc_arm_xrc_srq_out_bits {
7480 u8 status[0x8];
b4ff3a36 7481 u8 reserved_at_8[0x18];
e281682b
SM		 7482
7483 u8 syndrome[0x20];
7484
b4ff3a36 7485 u8 reserved_at_40[0x40];
e281682b
SM		 7486};
7487
7488enum {
7489 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7490};
7491
7492struct mlx5_ifc_arm_xrc_srq_in_bits {
7493 u8 opcode[0x10];
a0d8c054 7494 u8 uid[0x10];
e281682b 7495
b4ff3a36 7496 u8 reserved_at_20[0x10];
e281682b
SM		 7497 u8 op_mod[0x10];
7498
b4ff3a36 7499 u8 reserved_at_40[0x8];
e281682b
SM		 7500 u8 xrc_srqn[0x18];
7501
b4ff3a36 7502 u8 reserved_at_60[0x10];
e281682b
SM		 7503 u8 lwm[0x10];
7504};
7505
7506struct mlx5_ifc_arm_rq_out_bits {
7507 u8 status[0x8];
b4ff3a36 7508 u8 reserved_at_8[0x18];
e281682b
SM		 7509
7510 u8 syndrome[0x20];
7511
b4ff3a36 7512 u8 reserved_at_40[0x40];
e281682b
SM		 7513};
7514
7515enum {
7486216b
SM		 7516 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7517 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7518};
7519
7520struct mlx5_ifc_arm_rq_in_bits {
7521 u8 opcode[0x10];
a0d8c054 7522 u8 uid[0x10];
e281682b 7523
b4ff3a36 7524 u8 reserved_at_20[0x10];
e281682b
SM		 7525 u8 op_mod[0x10];
7526
b4ff3a36 7527 u8 reserved_at_40[0x8];
e281682b
SM		 7528 u8 srq_number[0x18];
7529
b4ff3a36 7530 u8 reserved_at_60[0x10];
e281682b
SM		 7531 u8 lwm[0x10];
7532};
7533
7534struct mlx5_ifc_arm_dct_out_bits {
7535 u8 status[0x8];
b4ff3a36 7536 u8 reserved_at_8[0x18];
e281682b
SM		 7537
7538 u8 syndrome[0x20];
7539
b4ff3a36 7540 u8 reserved_at_40[0x40];
e281682b
SM		 7541};
7542
7543struct mlx5_ifc_arm_dct_in_bits {
7544 u8 opcode[0x10];
b4ff3a36 7545 u8 reserved_at_10[0x10];
e281682b 7546
b4ff3a36 7547 u8 reserved_at_20[0x10];
e281682b
SM		 7548 u8 op_mod[0x10];
7549
b4ff3a36 7550 u8 reserved_at_40[0x8];
e281682b
SM		 7551 u8 dct_number[0x18];
7552
b4ff3a36 7553 u8 reserved_at_60[0x20];
e281682b
SM		 7554};
7555
7556struct mlx5_ifc_alloc_xrcd_out_bits {
7557 u8 status[0x8];
b4ff3a36 7558 u8 reserved_at_8[0x18];
e281682b
SM		 7559
7560 u8 syndrome[0x20];
7561
b4ff3a36 7562 u8 reserved_at_40[0x8];
e281682b
SM		 7563 u8 xrcd[0x18];
7564
b4ff3a36 7565 u8 reserved_at_60[0x20];
e281682b
SM		 7566};
7567
7568struct mlx5_ifc_alloc_xrcd_in_bits {
7569 u8 opcode[0x10];
bd371975 7570 u8 uid[0x10];
e281682b 7571
b4ff3a36 7572 u8 reserved_at_20[0x10];
e281682b
SM		 7573 u8 op_mod[0x10];
7574
b4ff3a36 7575 u8 reserved_at_40[0x40];
e281682b
SM		 7576};
7577
7578struct mlx5_ifc_alloc_uar_out_bits {
7579 u8 status[0x8];
b4ff3a36 7580 u8 reserved_at_8[0x18];
e281682b
SM		 7581
7582 u8 syndrome[0x20];
7583
b4ff3a36 7584 u8 reserved_at_40[0x8];
e281682b
SM		 7585 u8 uar[0x18];
7586
b4ff3a36 7587 u8 reserved_at_60[0x20];
e281682b
SM		 7588};
7589
7590struct mlx5_ifc_alloc_uar_in_bits {
7591 u8 opcode[0x10];
b4ff3a36 7592 u8 reserved_at_10[0x10];
e281682b 7593
b4ff3a36 7594 u8 reserved_at_20[0x10];
e281682b
SM		 7595 u8 op_mod[0x10];
7596
b4ff3a36 7597 u8 reserved_at_40[0x40];
e281682b
SM		 7598};
7599
7600struct mlx5_ifc_alloc_transport_domain_out_bits {
7601 u8 status[0x8];
b4ff3a36 7602 u8 reserved_at_8[0x18];
e281682b
SM		 7603
7604 u8 syndrome[0x20];
7605
b4ff3a36 7606 u8 reserved_at_40[0x8];
e281682b
SM		 7607 u8 transport_domain[0x18];
7608
b4ff3a36 7609 u8 reserved_at_60[0x20];
e281682b
SM		 7610};
7611
7612struct mlx5_ifc_alloc_transport_domain_in_bits {
7613 u8 opcode[0x10];
71bef2fd 7614 u8 uid[0x10];
e281682b 7615
b4ff3a36 7616 u8 reserved_at_20[0x10];
e281682b
SM		 7617 u8 op_mod[0x10];
7618
b4ff3a36 7619 u8 reserved_at_40[0x40];
e281682b
SM		 7620};
7621
7622struct mlx5_ifc_alloc_q_counter_out_bits {
7623 u8 status[0x8];
b4ff3a36 7624 u8 reserved_at_8[0x18];
e281682b
SM		 7625
7626 u8 syndrome[0x20];
7627
b4ff3a36 7628 u8 reserved_at_40[0x18];
e281682b
SM		 7629 u8 counter_set_id[0x8];
7630
b4ff3a36 7631 u8 reserved_at_60[0x20];
e281682b
SM		 7632};
7633
7634struct mlx5_ifc_alloc_q_counter_in_bits {
7635 u8 opcode[0x10];
2acc7957 7636 u8 uid[0x10];
e281682b 7637
b4ff3a36 7638 u8 reserved_at_20[0x10];
e281682b
SM		 7639 u8 op_mod[0x10];
7640
b4ff3a36 7641 u8 reserved_at_40[0x40];
e281682b
SM		 7642};
7643
7644struct mlx5_ifc_alloc_pd_out_bits {
7645 u8 status[0x8];
b4ff3a36 7646 u8 reserved_at_8[0x18];
e281682b
SM		 7647
7648 u8 syndrome[0x20];
7649
b4ff3a36 7650 u8 reserved_at_40[0x8];
e281682b
SM		 7651 u8 pd[0x18];
7652
b4ff3a36 7653 u8 reserved_at_60[0x20];
e281682b
SM		 7654};
7655
7656struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 7657 u8 opcode[0x10];
bd371975 7658 u8 uid[0x10];
9dc0b289
AV		 7659
7660 u8 reserved_at_20[0x10];
7661 u8 op_mod[0x10];
7662
7663 u8 reserved_at_40[0x40];
7664};
7665
7666struct mlx5_ifc_alloc_flow_counter_out_bits {
7667 u8 status[0x8];
7668 u8 reserved_at_8[0x18];
7669
7670 u8 syndrome[0x20];
7671
a8ffcc74 7672 u8 flow_counter_id[0x20];
9dc0b289
AV		 7673
7674 u8 reserved_at_60[0x20];
7675};
7676
7677struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7678 u8 opcode[0x10];
b4ff3a36 7679 u8 reserved_at_10[0x10];
e281682b 7680
b4ff3a36 7681 u8 reserved_at_20[0x10];
e281682b
SM		 7682 u8 op_mod[0x10];
7683
b4ff3a36 7684 u8 reserved_at_40[0x40];
e281682b
SM		 7685};
7686
7687struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7688 u8 status[0x8];
b4ff3a36 7689 u8 reserved_at_8[0x18];
e281682b
SM		 7690
7691 u8 syndrome[0x20];
7692
b4ff3a36 7693 u8 reserved_at_40[0x40];
e281682b
SM		 7694};
7695
7696struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7697 u8 opcode[0x10];
b4ff3a36 7698 u8 reserved_at_10[0x10];
e281682b 7699
b4ff3a36 7700 u8 reserved_at_20[0x10];
e281682b
SM		 7701 u8 op_mod[0x10];
7702
b4ff3a36 7703 u8 reserved_at_40[0x20];
e281682b 7704
b4ff3a36 7705 u8 reserved_at_60[0x10];
e281682b
SM		 7706 u8 vxlan_udp_port[0x10];
7707};
7708
37e92a9d 7709struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7710 u8 status[0x8];
7711 u8 reserved_at_8[0x18];
7712
7713 u8 syndrome[0x20];
7714
7715 u8 reserved_at_40[0x40];
7716};
7717
37e92a9d 7718struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7719 u8 opcode[0x10];
7720 u8 reserved_at_10[0x10];
7721
7722 u8 reserved_at_20[0x10];
7723 u8 op_mod[0x10];
7724
7725 u8 reserved_at_40[0x10];
7726 u8 rate_limit_index[0x10];
7727
7728 u8 reserved_at_60[0x20];
7729
7730 u8 rate_limit[0x20];
37e92a9d 7731
05d3ac97
BW		 7732 u8 burst_upper_bound[0x20];
7733
7734 u8 reserved_at_c0[0x10];
7735 u8 typical_packet_size[0x10];
7736
7737 u8 reserved_at_e0[0x120];
7486216b
SM		 7738};
7739
e281682b
SM		 7740struct mlx5_ifc_access_register_out_bits {
7741 u8 status[0x8];
b4ff3a36 7742 u8 reserved_at_8[0x18];
e281682b
SM		 7743
7744 u8 syndrome[0x20];
7745
b4ff3a36 7746 u8 reserved_at_40[0x40];
e281682b
SM		 7747
7748 u8 register_data[0][0x20];
7749};
7750
7751enum {
7752 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7753 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7754};
7755
7756struct mlx5_ifc_access_register_in_bits {
7757 u8 opcode[0x10];
b4ff3a36 7758 u8 reserved_at_10[0x10];
e281682b 7759
b4ff3a36 7760 u8 reserved_at_20[0x10];
e281682b
SM		 7761 u8 op_mod[0x10];
7762
b4ff3a36 7763 u8 reserved_at_40[0x10];
e281682b
SM		 7764 u8 register_id[0x10];
7765
7766 u8 argument[0x20];
7767
7768 u8 register_data[0][0x20];
7769};
7770
7771struct mlx5_ifc_sltp_reg_bits {
7772 u8 status[0x4];
7773 u8 version[0x4];
7774 u8 local_port[0x8];
7775 u8 pnat[0x2];
b4ff3a36 7776 u8 reserved_at_12[0x2];
e281682b 7777 u8 lane[0x4];
b4ff3a36 7778 u8 reserved_at_18[0x8];
e281682b 7779
b4ff3a36 7780 u8 reserved_at_20[0x20];
e281682b 7781
b4ff3a36 7782 u8 reserved_at_40[0x7];
e281682b
SM		 7783 u8 polarity[0x1];
7784 u8 ob_tap0[0x8];
7785 u8 ob_tap1[0x8];
7786 u8 ob_tap2[0x8];
7787
b4ff3a36 7788 u8 reserved_at_60[0xc];
e281682b
SM		 7789 u8 ob_preemp_mode[0x4];
7790 u8 ob_reg[0x8];
7791 u8 ob_bias[0x8];
7792
b4ff3a36 7793 u8 reserved_at_80[0x20];
e281682b
SM		 7794};
7795
7796struct mlx5_ifc_slrg_reg_bits {
7797 u8 status[0x4];
7798 u8 version[0x4];
7799 u8 local_port[0x8];
7800 u8 pnat[0x2];
b4ff3a36 7801 u8 reserved_at_12[0x2];
e281682b 7802 u8 lane[0x4];
b4ff3a36 7803 u8 reserved_at_18[0x8];
e281682b
SM		 7804
7805 u8 time_to_link_up[0x10];
b4ff3a36 7806 u8 reserved_at_30[0xc];
e281682b
SM		 7807 u8 grade_lane_speed[0x4];
7808
7809 u8 grade_version[0x8];
7810 u8 grade[0x18];
7811
b4ff3a36 7812 u8 reserved_at_60[0x4];
e281682b
SM		 7813 u8 height_grade_type[0x4];
7814 u8 height_grade[0x18];
7815
7816 u8 height_dz[0x10];
7817 u8 height_dv[0x10];
7818
b4ff3a36 7819 u8 reserved_at_a0[0x10];
e281682b
SM		 7820 u8 height_sigma[0x10];
7821
b4ff3a36 7822 u8 reserved_at_c0[0x20];
e281682b 7823
b4ff3a36 7824 u8 reserved_at_e0[0x4];
e281682b
SM		 7825 u8 phase_grade_type[0x4];
7826 u8 phase_grade[0x18];
7827
b4ff3a36 7828 u8 reserved_at_100[0x8];
e281682b 7829 u8 phase_eo_pos[0x8];
b4ff3a36 7830 u8 reserved_at_110[0x8];
e281682b
SM		 7831 u8 phase_eo_neg[0x8];
7832
7833 u8 ffe_set_tested[0x10];
7834 u8 test_errors_per_lane[0x10];
7835};
7836
7837struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7838 u8 reserved_at_0[0x8];
e281682b 7839 u8 local_port[0x8];
b4ff3a36 7840 u8 reserved_at_10[0x10];
e281682b 7841
b4ff3a36 7842 u8 reserved_at_20[0x1c];
e281682b
SM		 7843 u8 vl_hw_cap[0x4];
7844
b4ff3a36 7845 u8 reserved_at_40[0x1c];
e281682b
SM		 7846 u8 vl_admin[0x4];
7847
b4ff3a36 7848 u8 reserved_at_60[0x1c];
e281682b
SM		 7849 u8 vl_operational[0x4];
7850};
7851
7852struct mlx5_ifc_pude_reg_bits {
7853 u8 swid[0x8];
7854 u8 local_port[0x8];
b4ff3a36 7855 u8 reserved_at_10[0x4];
e281682b 7856 u8 admin_status[0x4];
b4ff3a36 7857 u8 reserved_at_18[0x4];
e281682b
SM		 7858 u8 oper_status[0x4];
7859
b4ff3a36 7860 u8 reserved_at_20[0x60];
e281682b
SM		 7861};
7862
7863struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7864 u8 reserved_at_0[0x1];
7486216b 7865 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7866 u8 an_disable_cap[0x1];
7867 u8 reserved_at_3[0x5];
e281682b 7868 u8 local_port[0x8];
b4ff3a36 7869 u8 reserved_at_10[0xd];
e281682b
SM		 7870 u8 proto_mask[0x3];
7871
7486216b 7872 u8 an_status[0x4];
a0a89989
AL		 7873 u8 reserved_at_24[0x1c];
7874
7875 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 7876
7877 u8 eth_proto_capability[0x20];
7878
7879 u8 ib_link_width_capability[0x10];
7880 u8 ib_proto_capability[0x10];
7881
a0a89989 7882 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 7883
7884 u8 eth_proto_admin[0x20];
7885
7886 u8 ib_link_width_admin[0x10];
7887 u8 ib_proto_admin[0x10];
7888
a0a89989 7889 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 7890
7891 u8 eth_proto_oper[0x20];
7892
7893 u8 ib_link_width_oper[0x10];
7894 u8 ib_proto_oper[0x10];
7895
5b4793f8
EBE		 7896 u8 reserved_at_160[0x1c];
7897 u8 connector_type[0x4];
e281682b
SM		 7898
7899 u8 eth_proto_lp_advertise[0x20];
7900
b4ff3a36 7901 u8 reserved_at_1a0[0x60];
e281682b
SM		 7902};
7903
7d5e1423
SM		 7904struct mlx5_ifc_mlcr_reg_bits {
7905 u8 reserved_at_0[0x8];
7906 u8 local_port[0x8];
7907 u8 reserved_at_10[0x20];
7908
7909 u8 beacon_duration[0x10];
7910 u8 reserved_at_40[0x10];
7911
7912 u8 beacon_remain[0x10];
7913};
7914
e281682b 7915struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7916 u8 reserved_at_0[0x20];
e281682b
SM		 7917
7918 u8 algorithm_options[0x10];
b4ff3a36 7919 u8 reserved_at_30[0x4];
e281682b
SM		 7920 u8 repetitions_mode[0x4];
7921 u8 num_of_repetitions[0x8];
7922
7923 u8 grade_version[0x8];
7924 u8 height_grade_type[0x4];
7925 u8 phase_grade_type[0x4];
7926 u8 height_grade_weight[0x8];
7927 u8 phase_grade_weight[0x8];
7928
7929 u8 gisim_measure_bits[0x10];
7930 u8 adaptive_tap_measure_bits[0x10];
7931
7932 u8 ber_bath_high_error_threshold[0x10];
7933 u8 ber_bath_mid_error_threshold[0x10];
7934
7935 u8 ber_bath_low_error_threshold[0x10];
7936 u8 one_ratio_high_threshold[0x10];
7937
7938 u8 one_ratio_high_mid_threshold[0x10];
7939 u8 one_ratio_low_mid_threshold[0x10];
7940
7941 u8 one_ratio_low_threshold[0x10];
7942 u8 ndeo_error_threshold[0x10];
7943
7944 u8 mixer_offset_step_size[0x10];
b4ff3a36 7945 u8 reserved_at_110[0x8];
e281682b
SM		 7946 u8 mix90_phase_for_voltage_bath[0x8];
7947
7948 u8 mixer_offset_start[0x10];
7949 u8 mixer_offset_end[0x10];
7950
b4ff3a36 7951 u8 reserved_at_140[0x15];
e281682b
SM		 7952 u8 ber_test_time[0xb];
7953};
7954
7955struct mlx5_ifc_pspa_reg_bits {
7956 u8 swid[0x8];
7957 u8 local_port[0x8];
7958 u8 sub_port[0x8];
b4ff3a36 7959 u8 reserved_at_18[0x8];
e281682b 7960
b4ff3a36 7961 u8 reserved_at_20[0x20];
e281682b
SM		 7962};
7963
7964struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7965 u8 reserved_at_0[0x8];
e281682b 7966 u8 local_port[0x8];
b4ff3a36 7967 u8 reserved_at_10[0x5];
e281682b 7968 u8 prio[0x3];
b4ff3a36 7969 u8 reserved_at_18[0x6];
e281682b
SM		 7970 u8 mode[0x2];
7971
b4ff3a36 7972 u8 reserved_at_20[0x20];
e281682b 7973
b4ff3a36 7974 u8 reserved_at_40[0x10];
e281682b
SM		 7975 u8 min_threshold[0x10];
7976
b4ff3a36 7977 u8 reserved_at_60[0x10];
e281682b
SM		 7978 u8 max_threshold[0x10];
7979
b4ff3a36 7980 u8 reserved_at_80[0x10];
e281682b
SM		 7981 u8 mark_probability_denominator[0x10];
7982
b4ff3a36 7983 u8 reserved_at_a0[0x60];
e281682b
SM		 7984};
7985
7986struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7987 u8 reserved_at_0[0x8];
e281682b 7988 u8 local_port[0x8];
b4ff3a36 7989 u8 reserved_at_10[0x10];
e281682b 7990
b4ff3a36 7991 u8 reserved_at_20[0x60];
e281682b 7992
b4ff3a36 7993 u8 reserved_at_80[0x1c];
e281682b
SM		 7994 u8 wrps_admin[0x4];
7995
b4ff3a36 7996 u8 reserved_at_a0[0x1c];
e281682b
SM		 7997 u8 wrps_status[0x4];
7998
b4ff3a36 7999 u8 reserved_at_c0[0x8];
e281682b 8000 u8 up_threshold[0x8];
b4ff3a36 8001 u8 reserved_at_d0[0x8];
e281682b
SM		 8002 u8 down_threshold[0x8];
8003
b4ff3a36 8004 u8 reserved_at_e0[0x20];
e281682b 8005
b4ff3a36 8006 u8 reserved_at_100[0x1c];
e281682b
SM		 8007 u8 srps_admin[0x4];
8008
b4ff3a36 8009 u8 reserved_at_120[0x1c];
e281682b
SM		 8010 u8 srps_status[0x4];
8011
b4ff3a36 8012 u8 reserved_at_140[0x40];
e281682b
SM		 8013};
8014
8015struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 8016 u8 reserved_at_0[0x8];
e281682b 8017 u8 local_port[0x8];
b4ff3a36 8018 u8 reserved_at_10[0x10];
e281682b 8019
b4ff3a36 8020 u8 reserved_at_20[0x8];
e281682b 8021 u8 lb_cap[0x8];
b4ff3a36 8022 u8 reserved_at_30[0x8];
e281682b
SM		 8023 u8 lb_en[0x8];
8024};
8025
8026struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 8027 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 8028 u8 local_port[0x8];
8029 u8 reserved_at_10[0x10];
e281682b 8030
4b5b9c7d 8031 u8 reserved_at_20[0x20];
e281682b 8032
4b5b9c7d
SA		 8033 u8 port_profile_mode[0x8];
8034 u8 static_port_profile[0x8];
8035 u8 active_port_profile[0x8];
8036 u8 reserved_at_58[0x8];
e281682b 8037
4b5b9c7d
SA		 8038 u8 retransmission_active[0x8];
8039 u8 fec_mode_active[0x18];
e281682b 8040
4b5b9c7d
SA		 8041 u8 rs_fec_correction_bypass_cap[0x4];
8042 u8 reserved_at_84[0x8];
8043 u8 fec_override_cap_56g[0x4];
8044 u8 fec_override_cap_100g[0x4];
8045 u8 fec_override_cap_50g[0x4];
8046 u8 fec_override_cap_25g[0x4];
8047 u8 fec_override_cap_10g_40g[0x4];
8048
8049 u8 rs_fec_correction_bypass_admin[0x4];
8050 u8 reserved_at_a4[0x8];
8051 u8 fec_override_admin_56g[0x4];
8052 u8 fec_override_admin_100g[0x4];
8053 u8 fec_override_admin_50g[0x4];
8054 u8 fec_override_admin_25g[0x4];
8055 u8 fec_override_admin_10g_40g[0x4];
e281682b
SM		 8056};
8057
8058struct mlx5_ifc_ppcnt_reg_bits {
8059 u8 swid[0x8];
8060 u8 local_port[0x8];
8061 u8 pnat[0x2];
b4ff3a36 8062 u8 reserved_at_12[0x8];
e281682b
SM		 8063 u8 grp[0x6];
8064
8065 u8 clr[0x1];
b4ff3a36 8066 u8 reserved_at_21[0x1c];
e281682b
SM		 8067 u8 prio_tc[0x3];
8068
8069 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8070};
8071
4039049b
AL		 8072struct mlx5_ifc_mpein_reg_bits {
8073 u8 reserved_at_0[0x2];
8074 u8 depth[0x6];
8075 u8 pcie_index[0x8];
8076 u8 node[0x8];
8077 u8 reserved_at_18[0x8];
8078
8079 u8 capability_mask[0x20];
8080
8081 u8 reserved_at_40[0x8];
8082 u8 link_width_enabled[0x8];
8083 u8 link_speed_enabled[0x10];
8084
8085 u8 lane0_physical_position[0x8];
8086 u8 link_width_active[0x8];
8087 u8 link_speed_active[0x10];
8088
8089 u8 num_of_pfs[0x10];
8090 u8 num_of_vfs[0x10];
8091
8092 u8 bdf0[0x10];
8093 u8 reserved_at_b0[0x10];
8094
8095 u8 max_read_request_size[0x4];
8096 u8 max_payload_size[0x4];
8097 u8 reserved_at_c8[0x5];
8098 u8 pwr_status[0x3];
8099 u8 port_type[0x4];
8100 u8 reserved_at_d4[0xb];
8101 u8 lane_reversal[0x1];
8102
8103 u8 reserved_at_e0[0x14];
8104 u8 pci_power[0xc];
8105
8106 u8 reserved_at_100[0x20];
8107
8108 u8 device_status[0x10];
8109 u8 port_state[0x8];
8110 u8 reserved_at_138[0x8];
8111
8112 u8 reserved_at_140[0x10];
8113 u8 receiver_detect_result[0x10];
8114
8115 u8 reserved_at_160[0x20];
8116};
8117
8ed1a630
GP		 8118struct mlx5_ifc_mpcnt_reg_bits {
8119 u8 reserved_at_0[0x8];
8120 u8 pcie_index[0x8];
8121 u8 reserved_at_10[0xa];
8122 u8 grp[0x6];
8123
8124 u8 clr[0x1];
8125 u8 reserved_at_21[0x1f];
8126
8127 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8128};
8129
e281682b 8130struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 8131 u8 reserved_at_0[0x3];
e281682b 8132 u8 single_mac[0x1];
b4ff3a36 8133 u8 reserved_at_4[0x4];
e281682b
SM		 8134 u8 local_port[0x8];
8135 u8 mac_47_32[0x10];
8136
8137 u8 mac_31_0[0x20];
8138
b4ff3a36 8139 u8 reserved_at_40[0x40];
e281682b
SM		 8140};
8141
8142struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 8143 u8 reserved_at_0[0x8];
e281682b 8144 u8 local_port[0x8];
b4ff3a36 8145 u8 reserved_at_10[0x10];
e281682b
SM		 8146
8147 u8 max_mtu[0x10];
b4ff3a36 8148 u8 reserved_at_30[0x10];
e281682b
SM		 8149
8150 u8 admin_mtu[0x10];
b4ff3a36 8151 u8 reserved_at_50[0x10];
e281682b
SM		 8152
8153 u8 oper_mtu[0x10];
b4ff3a36 8154 u8 reserved_at_70[0x10];
e281682b
SM		 8155};
8156
8157struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 8158 u8 reserved_at_0[0x8];
e281682b 8159 u8 module[0x8];
b4ff3a36 8160 u8 reserved_at_10[0x10];
e281682b 8161
b4ff3a36 8162 u8 reserved_at_20[0x18];
e281682b
SM		 8163 u8 attenuation_5g[0x8];
8164
b4ff3a36 8165 u8 reserved_at_40[0x18];
e281682b
SM		 8166 u8 attenuation_7g[0x8];
8167
b4ff3a36 8168 u8 reserved_at_60[0x18];
e281682b
SM		 8169 u8 attenuation_12g[0x8];
8170};
8171
8172struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 8173 u8 reserved_at_0[0x8];
e281682b 8174 u8 module[0x8];
b4ff3a36 8175 u8 reserved_at_10[0xc];
e281682b
SM		 8176 u8 module_status[0x4];
8177
b4ff3a36 8178 u8 reserved_at_20[0x60];
e281682b
SM		 8179};
8180
8181struct mlx5_ifc_pmpc_reg_bits {
8182 u8 module_state_updated[32][0x8];
8183};
8184
8185struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 8186 u8 reserved_at_0[0x4];
e281682b
SM		 8187 u8 mlpn_status[0x4];
8188 u8 local_port[0x8];
b4ff3a36 8189 u8 reserved_at_10[0x10];
e281682b
SM		 8190
8191 u8 e[0x1];
b4ff3a36 8192 u8 reserved_at_21[0x1f];
e281682b
SM		 8193};
8194
8195struct mlx5_ifc_pmlp_reg_bits {
8196 u8 rxtx[0x1];
b4ff3a36 8197 u8 reserved_at_1[0x7];
e281682b 8198 u8 local_port[0x8];
b4ff3a36 8199 u8 reserved_at_10[0x8];
e281682b
SM		 8200 u8 width[0x8];
8201
8202 u8 lane0_module_mapping[0x20];
8203
8204 u8 lane1_module_mapping[0x20];
8205
8206 u8 lane2_module_mapping[0x20];
8207
8208 u8 lane3_module_mapping[0x20];
8209
b4ff3a36 8210 u8 reserved_at_a0[0x160];
e281682b
SM		 8211};
8212
8213struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 8214 u8 reserved_at_0[0x8];
e281682b 8215 u8 module[0x8];
b4ff3a36 8216 u8 reserved_at_10[0x4];
e281682b 8217 u8 admin_status[0x4];
b4ff3a36 8218 u8 reserved_at_18[0x4];
e281682b
SM		 8219 u8 oper_status[0x4];
8220
8221 u8 ase[0x1];
8222 u8 ee[0x1];
b4ff3a36 8223 u8 reserved_at_22[0x1c];
e281682b
SM		 8224 u8 e[0x2];
8225
b4ff3a36 8226 u8 reserved_at_40[0x40];
e281682b
SM		 8227};
8228
8229struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 8230 u8 reserved_at_0[0x4];
e281682b 8231 u8 profile_id[0xc];
b4ff3a36 8232 u8 reserved_at_10[0x4];
e281682b 8233 u8 proto_mask[0x4];
b4ff3a36 8234 u8 reserved_at_18[0x8];
e281682b 8235
b4ff3a36 8236 u8 reserved_at_20[0x10];
e281682b
SM		 8237 u8 lane_speed[0x10];
8238
b4ff3a36 8239 u8 reserved_at_40[0x17];
e281682b
SM		 8240 u8 lpbf[0x1];
8241 u8 fec_mode_policy[0x8];
8242
8243 u8 retransmission_capability[0x8];
8244 u8 fec_mode_capability[0x18];
8245
8246 u8 retransmission_support_admin[0x8];
8247 u8 fec_mode_support_admin[0x18];
8248
8249 u8 retransmission_request_admin[0x8];
8250 u8 fec_mode_request_admin[0x18];
8251
b4ff3a36 8252 u8 reserved_at_c0[0x80];
e281682b
SM		 8253};
8254
8255struct mlx5_ifc_plib_reg_bits {
b4ff3a36 8256 u8 reserved_at_0[0x8];
e281682b 8257 u8 local_port[0x8];
b4ff3a36 8258 u8 reserved_at_10[0x8];
e281682b
SM		 8259 u8 ib_port[0x8];
8260
b4ff3a36 8261 u8 reserved_at_20[0x60];
e281682b
SM		 8262};
8263
8264struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 8265 u8 reserved_at_0[0x8];
e281682b 8266 u8 local_port[0x8];
b4ff3a36 8267 u8 reserved_at_10[0xd];
e281682b
SM		 8268 u8 lbf_mode[0x3];
8269
b4ff3a36 8270 u8 reserved_at_20[0x20];
e281682b
SM		 8271};
8272
8273struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 8274 u8 reserved_at_0[0x8];
e281682b 8275 u8 local_port[0x8];
b4ff3a36 8276 u8 reserved_at_10[0x10];
e281682b
SM		 8277
8278 u8 dic[0x1];
b4ff3a36 8279 u8 reserved_at_21[0x19];
e281682b 8280 u8 ipg[0x4];
b4ff3a36 8281 u8 reserved_at_3e[0x2];
e281682b
SM		 8282};
8283
8284struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 8285 u8 reserved_at_0[0x8];
e281682b 8286 u8 local_port[0x8];
b4ff3a36 8287 u8 reserved_at_10[0x10];
e281682b 8288
b4ff3a36 8289 u8 reserved_at_20[0xe0];
e281682b
SM		 8290
8291 u8 port_filter[8][0x20];
8292
8293 u8 port_filter_update_en[8][0x20];
8294};
8295
8296struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 8297 u8 reserved_at_0[0x8];
e281682b 8298 u8 local_port[0x8];
2afa609f
IK		 8299 u8 reserved_at_10[0xb];
8300 u8 ppan_mask_n[0x1];
8301 u8 minor_stall_mask[0x1];
8302 u8 critical_stall_mask[0x1];
8303 u8 reserved_at_1e[0x2];
e281682b
SM		 8304
8305 u8 ppan[0x4];
b4ff3a36 8306 u8 reserved_at_24[0x4];
e281682b 8307 u8 prio_mask_tx[0x8];
b4ff3a36 8308 u8 reserved_at_30[0x8];
e281682b
SM		 8309 u8 prio_mask_rx[0x8];
8310
8311 u8 pptx[0x1];
8312 u8 aptx[0x1];
2afa609f
IK		 8313 u8 pptx_mask_n[0x1];
8314 u8 reserved_at_43[0x5];
e281682b 8315 u8 pfctx[0x8];
b4ff3a36 8316 u8 reserved_at_50[0x10];
e281682b
SM		 8317
8318 u8 pprx[0x1];
8319 u8 aprx[0x1];
2afa609f
IK		 8320 u8 pprx_mask_n[0x1];
8321 u8 reserved_at_63[0x5];
e281682b 8322 u8 pfcrx[0x8];
b4ff3a36 8323 u8 reserved_at_70[0x10];
e281682b 8324
2afa609f
IK		 8325 u8 device_stall_minor_watermark[0x10];
8326 u8 device_stall_critical_watermark[0x10];
8327
8328 u8 reserved_at_a0[0x60];
e281682b
SM		 8329};
8330
8331struct mlx5_ifc_pelc_reg_bits {
8332 u8 op[0x4];
b4ff3a36 8333 u8 reserved_at_4[0x4];
e281682b 8334 u8 local_port[0x8];
b4ff3a36 8335 u8 reserved_at_10[0x10];
e281682b
SM		 8336
8337 u8 op_admin[0x8];
8338 u8 op_capability[0x8];
8339 u8 op_request[0x8];
8340 u8 op_active[0x8];
8341
8342 u8 admin[0x40];
8343
8344 u8 capability[0x40];
8345
8346 u8 request[0x40];
8347
8348 u8 active[0x40];
8349
b4ff3a36 8350 u8 reserved_at_140[0x80];
e281682b
SM		 8351};
8352
8353struct mlx5_ifc_peir_reg_bits {
b4ff3a36 8354 u8 reserved_at_0[0x8];
e281682b 8355 u8 local_port[0x8];
b4ff3a36 8356 u8 reserved_at_10[0x10];
e281682b 8357
b4ff3a36 8358 u8 reserved_at_20[0xc];
e281682b 8359 u8 error_count[0x4];
b4ff3a36 8360 u8 reserved_at_30[0x10];
e281682b 8361
b4ff3a36 8362 u8 reserved_at_40[0xc];
e281682b 8363 u8 lane[0x4];
b4ff3a36 8364 u8 reserved_at_50[0x8];
e281682b
SM		 8365 u8 error_type[0x8];
8366};
8367
5e022dd3
EBE		 8368struct mlx5_ifc_mpegc_reg_bits {
8369 u8 reserved_at_0[0x30];
8370 u8 field_select[0x10];
8371
8372 u8 tx_overflow_sense[0x1];
8373 u8 mark_cqe[0x1];
8374 u8 mark_cnp[0x1];
8375 u8 reserved_at_43[0x1b];
8376 u8 tx_lossy_overflow_oper[0x2];
8377
8378 u8 reserved_at_60[0x100];
8379};
8380
cfdcbcea 8381struct mlx5_ifc_pcam_enhanced_features_bits {
0af5107c
TB		 8382 u8 reserved_at_0[0x6d];
8383 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 8384 u8 reserved_at_6e[0x4];
8385 u8 ptys_extended_ethernet[0x1];
8386 u8 reserved_at_73[0x3];
2fcb12df 8387 u8 pfcc_mask[0x1];
67daf118
SA		 8388 u8 reserved_at_77[0x3];
8389 u8 per_lane_error_counters[0x1];
2dba0797 8390 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8391 u8 ptys_connector_type[0x1];
8392 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8393 u8 ppcnt_discard_group[0x1];
8394 u8 ppcnt_statistical_group[0x1];
8395};
8396
df5f1361
HN		 8397struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8398 u8 port_access_reg_cap_mask_127_to_96[0x20];
8399 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 8400
8401 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8402 u8 pplm[0x1];
8403 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 8404
8405 u8 port_access_reg_cap_mask_31_to_13[0x13];
8406 u8 pbmc[0x1];
8407 u8 pptb[0x1];
75370eb0
ED		 8408 u8 port_access_reg_cap_mask_10_to_09[0x2];
8409 u8 ppcnt[0x1];
8410 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 8411};
8412
cfdcbcea
GP		 8413struct mlx5_ifc_pcam_reg_bits {
8414 u8 reserved_at_0[0x8];
8415 u8 feature_group[0x8];
8416 u8 reserved_at_10[0x8];
8417 u8 access_reg_group[0x8];
8418
8419 u8 reserved_at_20[0x20];
8420
8421 union {
df5f1361 8422 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 8423 u8 reserved_at_0[0x80];
8424 } port_access_reg_cap_mask;
8425
8426 u8 reserved_at_c0[0x80];
8427
8428 union {
8429 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8430 u8 reserved_at_0[0x80];
8431 } feature_cap_mask;
8432
8433 u8 reserved_at_1c0[0xc0];
8434};
8435
8436struct mlx5_ifc_mcam_enhanced_features_bits {
4039049b
AL		 8437 u8 reserved_at_0[0x6e];
8438 u8 pci_status_and_power[0x1];
8439 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 8440 u8 mark_tx_action_cnp[0x1];
8441 u8 mark_tx_action_cqe[0x1];
8442 u8 dynamic_tx_overflow[0x1];
8443 u8 reserved_at_77[0x4];
5405fa26 8444 u8 pcie_outbound_stalled[0x1];
efae7f78 8445 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8446 u8 mtpps_enh_out_per_adj[0x1];
8447 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8448 u8 pcie_performance_group[0x1];
8449};
8450
0ab87743
OG		 8451struct mlx5_ifc_mcam_access_reg_bits {
8452 u8 reserved_at_0[0x1c];
8453 u8 mcda[0x1];
8454 u8 mcc[0x1];
8455 u8 mcqi[0x1];
8456 u8 reserved_at_1f[0x1];
8457
5e022dd3
EBE		 8458 u8 regs_95_to_87[0x9];
8459 u8 mpegc[0x1];
8460 u8 regs_85_to_68[0x12];
eff8ea8f
FD		 8461 u8 tracer_registers[0x4];
8462
0ab87743
OG		 8463 u8 regs_63_to_32[0x20];
8464 u8 regs_31_to_0[0x20];
8465};
8466
cfdcbcea
GP		 8467struct mlx5_ifc_mcam_reg_bits {
8468 u8 reserved_at_0[0x8];
8469 u8 feature_group[0x8];
8470 u8 reserved_at_10[0x8];
8471 u8 access_reg_group[0x8];
8472
8473 u8 reserved_at_20[0x20];
8474
8475 union {
0ab87743 8476 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8477 u8 reserved_at_0[0x80];
8478 } mng_access_reg_cap_mask;
8479
8480 u8 reserved_at_c0[0x80];
8481
8482 union {
8483 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8484 u8 reserved_at_0[0x80];
8485 } mng_feature_cap_mask;
8486
8487 u8 reserved_at_1c0[0x80];
8488};
8489
c02762eb
HN		 8490struct mlx5_ifc_qcam_access_reg_cap_mask {
8491 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8492 u8 qpdpm[0x1];
8493 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8494 u8 qdpm[0x1];
8495 u8 qpts[0x1];
8496 u8 qcap[0x1];
8497 u8 qcam_access_reg_cap_mask_0[0x1];
8498};
8499
8500struct mlx5_ifc_qcam_qos_feature_cap_mask {
8501 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8502 u8 qpts_trust_both[0x1];
8503};
8504
8505struct mlx5_ifc_qcam_reg_bits {
8506 u8 reserved_at_0[0x8];
8507 u8 feature_group[0x8];
8508 u8 reserved_at_10[0x8];
8509 u8 access_reg_group[0x8];
8510 u8 reserved_at_20[0x20];
8511
8512 union {
8513 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8514 u8 reserved_at_0[0x80];
8515 } qos_access_reg_cap_mask;
8516
8517 u8 reserved_at_c0[0x80];
8518
8519 union {
8520 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8521 u8 reserved_at_0[0x80];
8522 } qos_feature_cap_mask;
8523
8524 u8 reserved_at_1c0[0x80];
8525};
8526
e281682b 8527struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8528 u8 reserved_at_0[0x8];
e281682b 8529 u8 local_port[0x8];
b4ff3a36 8530 u8 reserved_at_10[0x10];
e281682b
SM		 8531
8532 u8 port_capability_mask[4][0x20];
8533};
8534
8535struct mlx5_ifc_paos_reg_bits {
8536 u8 swid[0x8];
8537 u8 local_port[0x8];
b4ff3a36 8538 u8 reserved_at_10[0x4];
e281682b 8539 u8 admin_status[0x4];
b4ff3a36 8540 u8 reserved_at_18[0x4];
e281682b
SM		 8541 u8 oper_status[0x4];
8542
8543 u8 ase[0x1];
8544 u8 ee[0x1];
b4ff3a36 8545 u8 reserved_at_22[0x1c];
e281682b
SM		 8546 u8 e[0x2];
8547
b4ff3a36 8548 u8 reserved_at_40[0x40];
e281682b
SM		 8549};
8550
8551struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8552 u8 reserved_at_0[0x8];
e281682b 8553 u8 opamp_group[0x8];
b4ff3a36 8554 u8 reserved_at_10[0xc];
e281682b
SM		 8555 u8 opamp_group_type[0x4];
8556
8557 u8 start_index[0x10];
b4ff3a36 8558 u8 reserved_at_30[0x4];
e281682b
SM		 8559 u8 num_of_indices[0xc];
8560
8561 u8 index_data[18][0x10];
8562};
8563
7d5e1423
SM		 8564struct mlx5_ifc_pcmr_reg_bits {
8565 u8 reserved_at_0[0x8];
8566 u8 local_port[0x8];
0dcaafc0
EB		 8567 u8 reserved_at_10[0x10];
8568 u8 entropy_force_cap[0x1];
8569 u8 entropy_calc_cap[0x1];
8570 u8 entropy_gre_calc_cap[0x1];
8571 u8 reserved_at_23[0x1b];
7d5e1423 8572 u8 fcs_cap[0x1];
0dcaafc0
EB		 8573 u8 reserved_at_3f[0x1];
8574 u8 entropy_force[0x1];
8575 u8 entropy_calc[0x1];
8576 u8 entropy_gre_calc[0x1];
8577 u8 reserved_at_43[0x1b];
7d5e1423
SM		 8578 u8 fcs_chk[0x1];
8579 u8 reserved_at_5f[0x1];
8580};
8581
e281682b 8582struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8583 u8 reserved_at_0[0x6];
e281682b 8584 u8 rx_lane[0x2];
b4ff3a36 8585 u8 reserved_at_8[0x6];
e281682b 8586 u8 tx_lane[0x2];
b4ff3a36 8587 u8 reserved_at_10[0x8];
e281682b
SM		 8588 u8 module[0x8];
8589};
8590
8591struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8592 u8 reserved_at_0[0x6];
e281682b
SM		 8593 u8 lossy[0x1];
8594 u8 epsb[0x1];
b4ff3a36 8595 u8 reserved_at_8[0xc];
e281682b
SM		 8596 u8 size[0xc];
8597
8598 u8 xoff_threshold[0x10];
8599 u8 xon_threshold[0x10];
8600};
8601
8602struct mlx5_ifc_set_node_in_bits {
8603 u8 node_description[64][0x8];
8604};
8605
8606struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8607 u8 reserved_at_0[0x18];
e281682b
SM		 8608 u8 power_settings_level[0x8];
8609
b4ff3a36 8610 u8 reserved_at_20[0x60];
e281682b
SM		 8611};
8612
8613struct mlx5_ifc_register_host_endianness_bits {
8614 u8 he[0x1];
b4ff3a36 8615 u8 reserved_at_1[0x1f];
e281682b 8616
b4ff3a36 8617 u8 reserved_at_20[0x60];
e281682b
SM		 8618};
8619
8620struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8621 u8 reserved_at_0[0x20];
e281682b
SM		 8622
8623 u8 mkey[0x20];
8624
8625 u8 addressh_63_32[0x20];
8626
8627 u8 addressl_31_0[0x20];
8628};
8629
8630struct mlx5_ifc_ud_adrs_vector_bits {
8631 u8 dc_key[0x40];
8632
8633 u8 ext[0x1];
b4ff3a36 8634 u8 reserved_at_41[0x7];
e281682b
SM		 8635 u8 destination_qp_dct[0x18];
8636
8637 u8 static_rate[0x4];
8638 u8 sl_eth_prio[0x4];
8639 u8 fl[0x1];
8640 u8 mlid[0x7];
8641 u8 rlid_udp_sport[0x10];
8642
b4ff3a36 8643 u8 reserved_at_80[0x20];
e281682b
SM		 8644
8645 u8 rmac_47_16[0x20];
8646
8647 u8 rmac_15_0[0x10];
8648 u8 tclass[0x8];
8649 u8 hop_limit[0x8];
8650
b4ff3a36 8651 u8 reserved_at_e0[0x1];
e281682b 8652 u8 grh[0x1];
b4ff3a36 8653 u8 reserved_at_e2[0x2];
e281682b
SM		 8654 u8 src_addr_index[0x8];
8655 u8 flow_label[0x14];
8656
8657 u8 rgid_rip[16][0x8];
8658};
8659
8660struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8661 u8 reserved_at_0[0x10];
e281682b
SM		 8662 u8 function_id[0x10];
8663
8664 u8 num_pages[0x20];
8665
b4ff3a36 8666 u8 reserved_at_40[0xa0];
e281682b
SM		 8667};
8668
8669struct mlx5_ifc_eqe_bits {
b4ff3a36 8670 u8 reserved_at_0[0x8];
e281682b 8671 u8 event_type[0x8];
b4ff3a36 8672 u8 reserved_at_10[0x8];
e281682b
SM		 8673 u8 event_sub_type[0x8];
8674
b4ff3a36 8675 u8 reserved_at_20[0xe0];
e281682b
SM		 8676
8677 union mlx5_ifc_event_auto_bits event_data;
8678
b4ff3a36 8679 u8 reserved_at_1e0[0x10];
e281682b 8680 u8 signature[0x8];
b4ff3a36 8681 u8 reserved_at_1f8[0x7];
e281682b
SM		 8682 u8 owner[0x1];
8683};
8684
8685enum {
8686 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8687};
8688
8689struct mlx5_ifc_cmd_queue_entry_bits {
8690 u8 type[0x8];
b4ff3a36 8691 u8 reserved_at_8[0x18];
e281682b
SM		 8692
8693 u8 input_length[0x20];
8694
8695 u8 input_mailbox_pointer_63_32[0x20];
8696
8697 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8698 u8 reserved_at_77[0x9];
e281682b
SM		 8699
8700 u8 command_input_inline_data[16][0x8];
8701
8702 u8 command_output_inline_data[16][0x8];
8703
8704 u8 output_mailbox_pointer_63_32[0x20];
8705
8706 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8707 u8 reserved_at_1b7[0x9];
e281682b
SM		 8708
8709 u8 output_length[0x20];
8710
8711 u8 token[0x8];
8712 u8 signature[0x8];
b4ff3a36 8713 u8 reserved_at_1f0[0x8];
e281682b
SM		 8714 u8 status[0x7];
8715 u8 ownership[0x1];
8716};
8717
8718struct mlx5_ifc_cmd_out_bits {
8719 u8 status[0x8];
b4ff3a36 8720 u8 reserved_at_8[0x18];
e281682b
SM		 8721
8722 u8 syndrome[0x20];
8723
8724 u8 command_output[0x20];
8725};
8726
8727struct mlx5_ifc_cmd_in_bits {
8728 u8 opcode[0x10];
b4ff3a36 8729 u8 reserved_at_10[0x10];
e281682b 8730
b4ff3a36 8731 u8 reserved_at_20[0x10];
e281682b
SM		 8732 u8 op_mod[0x10];
8733
8734 u8 command[0][0x20];
8735};
8736
8737struct mlx5_ifc_cmd_if_box_bits {
8738 u8 mailbox_data[512][0x8];
8739
b4ff3a36 8740 u8 reserved_at_1000[0x180];
e281682b
SM		 8741
8742 u8 next_pointer_63_32[0x20];
8743
8744 u8 next_pointer_31_10[0x16];
b4ff3a36 8745 u8 reserved_at_11b6[0xa];
e281682b
SM		 8746
8747 u8 block_number[0x20];
8748
b4ff3a36 8749 u8 reserved_at_11e0[0x8];
e281682b
SM		 8750 u8 token[0x8];
8751 u8 ctrl_signature[0x8];
8752 u8 signature[0x8];
8753};
8754
8755struct mlx5_ifc_mtt_bits {
8756 u8 ptag_63_32[0x20];
8757
8758 u8 ptag_31_8[0x18];
b4ff3a36 8759 u8 reserved_at_38[0x6];
e281682b
SM		 8760 u8 wr_en[0x1];
8761 u8 rd_en[0x1];
8762};
8763
928cfe87
TT		 8764struct mlx5_ifc_query_wol_rol_out_bits {
8765 u8 status[0x8];
8766 u8 reserved_at_8[0x18];
8767
8768 u8 syndrome[0x20];
8769
8770 u8 reserved_at_40[0x10];
8771 u8 rol_mode[0x8];
8772 u8 wol_mode[0x8];
8773
8774 u8 reserved_at_60[0x20];
8775};
8776
8777struct mlx5_ifc_query_wol_rol_in_bits {
8778 u8 opcode[0x10];
8779 u8 reserved_at_10[0x10];
8780
8781 u8 reserved_at_20[0x10];
8782 u8 op_mod[0x10];
8783
8784 u8 reserved_at_40[0x40];
8785};
8786
8787struct mlx5_ifc_set_wol_rol_out_bits {
8788 u8 status[0x8];
8789 u8 reserved_at_8[0x18];
8790
8791 u8 syndrome[0x20];
8792
8793 u8 reserved_at_40[0x40];
8794};
8795
8796struct mlx5_ifc_set_wol_rol_in_bits {
8797 u8 opcode[0x10];
8798 u8 reserved_at_10[0x10];
8799
8800 u8 reserved_at_20[0x10];
8801 u8 op_mod[0x10];
8802
8803 u8 rol_mode_valid[0x1];
8804 u8 wol_mode_valid[0x1];
8805 u8 reserved_at_42[0xe];
8806 u8 rol_mode[0x8];
8807 u8 wol_mode[0x8];
8808
8809 u8 reserved_at_60[0x20];
8810};
8811
e281682b
SM		 8812enum {
8813 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8814 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8815 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8816};
8817
8818enum {
8819 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8820 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8821 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8822};
8823
8824enum {
8825 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8826 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8827 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8828 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8829 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8830 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8831 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8832 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8833 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8834 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8835 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8836};
8837
8838struct mlx5_ifc_initial_seg_bits {
8839 u8 fw_rev_minor[0x10];
8840 u8 fw_rev_major[0x10];
8841
8842 u8 cmd_interface_rev[0x10];
8843 u8 fw_rev_subminor[0x10];
8844
b4ff3a36 8845 u8 reserved_at_40[0x40];
e281682b
SM		 8846
8847 u8 cmdq_phy_addr_63_32[0x20];
8848
8849 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8850 u8 reserved_at_b4[0x2];
e281682b
SM		 8851 u8 nic_interface[0x2];
8852 u8 log_cmdq_size[0x4];
8853 u8 log_cmdq_stride[0x4];
8854
8855 u8 command_doorbell_vector[0x20];
8856
b4ff3a36 8857 u8 reserved_at_e0[0xf00];
e281682b
SM		 8858
8859 u8 initializing[0x1];
b4ff3a36 8860 u8 reserved_at_fe1[0x4];
e281682b 8861 u8 nic_interface_supported[0x3];
591905ba
BW		 8862 u8 embedded_cpu[0x1];
8863 u8 reserved_at_fe9[0x17];
e281682b
SM		 8864
8865 struct mlx5_ifc_health_buffer_bits health_buffer;
8866
8867 u8 no_dram_nic_offset[0x20];
8868
b4ff3a36 8869 u8 reserved_at_1220[0x6e40];
e281682b 8870
b4ff3a36 8871 u8 reserved_at_8060[0x1f];
e281682b
SM		 8872 u8 clear_int[0x1];
8873
8874 u8 health_syndrome[0x8];
8875 u8 health_counter[0x18];
8876
b4ff3a36 8877 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8878};
8879
f9a1ef72
EE		 8880struct mlx5_ifc_mtpps_reg_bits {
8881 u8 reserved_at_0[0xc];
8882 u8 cap_number_of_pps_pins[0x4];
8883 u8 reserved_at_10[0x4];
8884 u8 cap_max_num_of_pps_in_pins[0x4];
8885 u8 reserved_at_18[0x4];
8886 u8 cap_max_num_of_pps_out_pins[0x4];
8887
8888 u8 reserved_at_20[0x24];
8889 u8 cap_pin_3_mode[0x4];
8890 u8 reserved_at_48[0x4];
8891 u8 cap_pin_2_mode[0x4];
8892 u8 reserved_at_50[0x4];
8893 u8 cap_pin_1_mode[0x4];
8894 u8 reserved_at_58[0x4];
8895 u8 cap_pin_0_mode[0x4];
8896
8897 u8 reserved_at_60[0x4];
8898 u8 cap_pin_7_mode[0x4];
8899 u8 reserved_at_68[0x4];
8900 u8 cap_pin_6_mode[0x4];
8901 u8 reserved_at_70[0x4];
8902 u8 cap_pin_5_mode[0x4];
8903 u8 reserved_at_78[0x4];
8904 u8 cap_pin_4_mode[0x4];
8905
fa367688
EE		 8906 u8 field_select[0x20];
8907 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8908
8909 u8 enable[0x1];
8910 u8 reserved_at_101[0xb];
8911 u8 pattern[0x4];
8912 u8 reserved_at_110[0x4];
8913 u8 pin_mode[0x4];
8914 u8 pin[0x8];
8915
8916 u8 reserved_at_120[0x20];
8917
8918 u8 time_stamp[0x40];
8919
8920 u8 out_pulse_duration[0x10];
8921 u8 out_periodic_adjustment[0x10];
fa367688 8922 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8923
fa367688 8924 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8925};
8926
8927struct mlx5_ifc_mtppse_reg_bits {
8928 u8 reserved_at_0[0x18];
8929 u8 pin[0x8];
8930 u8 event_arm[0x1];
8931 u8 reserved_at_21[0x1b];
8932 u8 event_generation_mode[0x4];
8933 u8 reserved_at_40[0x40];
8934};
8935
47176289
OG		 8936struct mlx5_ifc_mcqi_cap_bits {
8937 u8 supported_info_bitmask[0x20];
8938
8939 u8 component_size[0x20];
8940
8941 u8 max_component_size[0x20];
8942
8943 u8 log_mcda_word_size[0x4];
8944 u8 reserved_at_64[0xc];
8945 u8 mcda_max_write_size[0x10];
8946
8947 u8 rd_en[0x1];
8948 u8 reserved_at_81[0x1];
8949 u8 match_chip_id[0x1];
8950 u8 match_psid[0x1];
8951 u8 check_user_timestamp[0x1];
8952 u8 match_base_guid_mac[0x1];
8953 u8 reserved_at_86[0x1a];
8954};
8955
8956struct mlx5_ifc_mcqi_reg_bits {
8957 u8 read_pending_component[0x1];
8958 u8 reserved_at_1[0xf];
8959 u8 component_index[0x10];
8960
8961 u8 reserved_at_20[0x20];
8962
8963 u8 reserved_at_40[0x1b];
8964 u8 info_type[0x5];
8965
8966 u8 info_size[0x20];
8967
8968 u8 offset[0x20];
8969
8970 u8 reserved_at_a0[0x10];
8971 u8 data_size[0x10];
8972
8973 u8 data[0][0x20];
8974};
8975
8976struct mlx5_ifc_mcc_reg_bits {
8977 u8 reserved_at_0[0x4];
8978 u8 time_elapsed_since_last_cmd[0xc];
8979 u8 reserved_at_10[0x8];
8980 u8 instruction[0x8];
8981
8982 u8 reserved_at_20[0x10];
8983 u8 component_index[0x10];
8984
8985 u8 reserved_at_40[0x8];
8986 u8 update_handle[0x18];
8987
8988 u8 handle_owner_type[0x4];
8989 u8 handle_owner_host_id[0x4];
8990 u8 reserved_at_68[0x1];
8991 u8 control_progress[0x7];
8992 u8 error_code[0x8];
8993 u8 reserved_at_78[0x4];
8994 u8 control_state[0x4];
8995
8996 u8 component_size[0x20];
8997
8998 u8 reserved_at_a0[0x60];
8999};
9000
9001struct mlx5_ifc_mcda_reg_bits {
9002 u8 reserved_at_0[0x8];
9003 u8 update_handle[0x18];
9004
9005 u8 offset[0x20];
9006
9007 u8 reserved_at_40[0x10];
9008 u8 size[0x10];
9009
9010 u8 reserved_at_60[0x20];
9011
9012 u8 data[0][0x20];
9013};
9014
e281682b
SM		 9015union mlx5_ifc_ports_control_registers_document_bits {
9016 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9017 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9018 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9019 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9020 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9021 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9022 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9023 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9024 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9025 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9026 struct mlx5_ifc_paos_reg_bits paos_reg;
9027 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9028 struct mlx5_ifc_peir_reg_bits peir_reg;
9029 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9030 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 9031 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 9032 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9033 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9034 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9035 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9036 struct mlx5_ifc_plib_reg_bits plib_reg;
9037 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9038 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9039 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9040 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9041 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9042 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9043 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9044 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9045 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9046 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 9047 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 9048 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 9049 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9050 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9051 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9052 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9053 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9054 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9055 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 9056 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 9057 struct mlx5_ifc_pude_reg_bits pude_reg;
9058 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9059 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9060 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 9061 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9062 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 9063 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 9064 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9065 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 9066 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9067 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9068 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 9069 u8 reserved_at_0[0x60e0];
e281682b
SM		 9070};
9071
9072union mlx5_ifc_debug_enhancements_document_bits {
9073 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 9074 u8 reserved_at_0[0x200];
e281682b
SM		 9075};
9076
9077union mlx5_ifc_uplink_pci_interface_document_bits {
9078 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 9079 u8 reserved_at_0[0x20060];
b775516b
EC		 9080};
9081
2cc43b49
MG		 9082struct mlx5_ifc_set_flow_table_root_out_bits {
9083 u8 status[0x8];
b4ff3a36 9084 u8 reserved_at_8[0x18];
2cc43b49
MG		 9085
9086 u8 syndrome[0x20];
9087
b4ff3a36 9088 u8 reserved_at_40[0x40];
2cc43b49
MG		 9089};
9090
9091struct mlx5_ifc_set_flow_table_root_in_bits {
9092 u8 opcode[0x10];
b4ff3a36 9093 u8 reserved_at_10[0x10];
2cc43b49 9094
b4ff3a36 9095 u8 reserved_at_20[0x10];
2cc43b49
MG		 9096 u8 op_mod[0x10];
9097
7d5e1423
SM		 9098 u8 other_vport[0x1];
9099 u8 reserved_at_41[0xf];
9100 u8 vport_number[0x10];
9101
9102 u8 reserved_at_60[0x20];
2cc43b49
MG		 9103
9104 u8 table_type[0x8];
b4ff3a36 9105 u8 reserved_at_88[0x18];
2cc43b49 9106
b4ff3a36 9107 u8 reserved_at_a0[0x8];
2cc43b49
MG		 9108 u8 table_id[0x18];
9109
500a3d0d
ES		 9110 u8 reserved_at_c0[0x8];
9111 u8 underlay_qpn[0x18];
9112 u8 reserved_at_e0[0x120];
2cc43b49
MG		 9113};
9114
34a40e68 9115enum {
84df61eb
AH		 9116 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9117 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 9118};
9119
9120struct mlx5_ifc_modify_flow_table_out_bits {
9121 u8 status[0x8];
b4ff3a36 9122 u8 reserved_at_8[0x18];
34a40e68
MG		 9123
9124 u8 syndrome[0x20];
9125
b4ff3a36 9126 u8 reserved_at_40[0x40];
34a40e68
MG		 9127};
9128
9129struct mlx5_ifc_modify_flow_table_in_bits {
9130 u8 opcode[0x10];
b4ff3a36 9131 u8 reserved_at_10[0x10];
34a40e68 9132
b4ff3a36 9133 u8 reserved_at_20[0x10];
34a40e68
MG		 9134 u8 op_mod[0x10];
9135
7d5e1423
SM		 9136 u8 other_vport[0x1];
9137 u8 reserved_at_41[0xf];
9138 u8 vport_number[0x10];
34a40e68 9139
b4ff3a36 9140 u8 reserved_at_60[0x10];
34a40e68
MG		 9141 u8 modify_field_select[0x10];
9142
9143 u8 table_type[0x8];
b4ff3a36 9144 u8 reserved_at_88[0x18];
34a40e68 9145
b4ff3a36 9146 u8 reserved_at_a0[0x8];
34a40e68
MG		 9147 u8 table_id[0x18];
9148
0c90e9c6 9149 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 9150};
9151
4f3961ee
SM		 9152struct mlx5_ifc_ets_tcn_config_reg_bits {
9153 u8 g[0x1];
9154 u8 b[0x1];
9155 u8 r[0x1];
9156 u8 reserved_at_3[0x9];
9157 u8 group[0x4];
9158 u8 reserved_at_10[0x9];
9159 u8 bw_allocation[0x7];
9160
9161 u8 reserved_at_20[0xc];
9162 u8 max_bw_units[0x4];
9163 u8 reserved_at_30[0x8];
9164 u8 max_bw_value[0x8];
9165};
9166
9167struct mlx5_ifc_ets_global_config_reg_bits {
9168 u8 reserved_at_0[0x2];
9169 u8 r[0x1];
9170 u8 reserved_at_3[0x1d];
9171
9172 u8 reserved_at_20[0xc];
9173 u8 max_bw_units[0x4];
9174 u8 reserved_at_30[0x8];
9175 u8 max_bw_value[0x8];
9176};
9177
9178struct mlx5_ifc_qetc_reg_bits {
9179 u8 reserved_at_0[0x8];
9180 u8 port_number[0x8];
9181 u8 reserved_at_10[0x30];
9182
9183 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9184 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9185};
9186
415a64aa
HN		 9187struct mlx5_ifc_qpdpm_dscp_reg_bits {
9188 u8 e[0x1];
9189 u8 reserved_at_01[0x0b];
9190 u8 prio[0x04];
9191};
9192
9193struct mlx5_ifc_qpdpm_reg_bits {
9194 u8 reserved_at_0[0x8];
9195 u8 local_port[0x8];
9196 u8 reserved_at_10[0x10];
9197 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9198};
9199
9200struct mlx5_ifc_qpts_reg_bits {
9201 u8 reserved_at_0[0x8];
9202 u8 local_port[0x8];
9203 u8 reserved_at_10[0x2d];
9204 u8 trust_state[0x3];
9205};
9206
50b4a3c2
HN		 9207struct mlx5_ifc_pptb_reg_bits {
9208 u8 reserved_at_0[0x2];
9209 u8 mm[0x2];
9210 u8 reserved_at_4[0x4];
9211 u8 local_port[0x8];
9212 u8 reserved_at_10[0x6];
9213 u8 cm[0x1];
9214 u8 um[0x1];
9215 u8 pm[0x8];
9216
9217 u8 prio_x_buff[0x20];
9218
9219 u8 pm_msb[0x8];
9220 u8 reserved_at_48[0x10];
9221 u8 ctrl_buff[0x4];
9222 u8 untagged_buff[0x4];
9223};
9224
9225struct mlx5_ifc_pbmc_reg_bits {
9226 u8 reserved_at_0[0x8];
9227 u8 local_port[0x8];
9228 u8 reserved_at_10[0x10];
9229
9230 u8 xoff_timer_value[0x10];
9231 u8 xoff_refresh[0x10];
9232
9233 u8 reserved_at_40[0x9];
9234 u8 fullness_threshold[0x7];
9235 u8 port_buffer_size[0x10];
9236
9237 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9238
9239 u8 reserved_at_2e0[0x40];
9240};
9241
4f3961ee
SM		 9242struct mlx5_ifc_qtct_reg_bits {
9243 u8 reserved_at_0[0x8];
9244 u8 port_number[0x8];
9245 u8 reserved_at_10[0xd];
9246 u8 prio[0x3];
9247
9248 u8 reserved_at_20[0x1d];
9249 u8 tclass[0x3];
9250};
9251
7d5e1423
SM		 9252struct mlx5_ifc_mcia_reg_bits {
9253 u8 l[0x1];
9254 u8 reserved_at_1[0x7];
9255 u8 module[0x8];
9256 u8 reserved_at_10[0x8];
9257 u8 status[0x8];
9258
9259 u8 i2c_device_address[0x8];
9260 u8 page_number[0x8];
9261 u8 device_address[0x10];
9262
9263 u8 reserved_at_40[0x10];
9264 u8 size[0x10];
9265
9266 u8 reserved_at_60[0x20];
9267
9268 u8 dword_0[0x20];
9269 u8 dword_1[0x20];
9270 u8 dword_2[0x20];
9271 u8 dword_3[0x20];
9272 u8 dword_4[0x20];
9273 u8 dword_5[0x20];
9274 u8 dword_6[0x20];
9275 u8 dword_7[0x20];
9276 u8 dword_8[0x20];
9277 u8 dword_9[0x20];
9278 u8 dword_10[0x20];
9279 u8 dword_11[0x20];
9280};
9281
7486216b
SM		 9282struct mlx5_ifc_dcbx_param_bits {
9283 u8 dcbx_cee_cap[0x1];
9284 u8 dcbx_ieee_cap[0x1];
9285 u8 dcbx_standby_cap[0x1];
c74d90c1 9286 u8 reserved_at_3[0x5];
7486216b
SM		 9287 u8 port_number[0x8];
9288 u8 reserved_at_10[0xa];
9289 u8 max_application_table_size[6];
9290 u8 reserved_at_20[0x15];
9291 u8 version_oper[0x3];
9292 u8 reserved_at_38[5];
9293 u8 version_admin[0x3];
9294 u8 willing_admin[0x1];
9295 u8 reserved_at_41[0x3];
9296 u8 pfc_cap_oper[0x4];
9297 u8 reserved_at_48[0x4];
9298 u8 pfc_cap_admin[0x4];
9299 u8 reserved_at_50[0x4];
9300 u8 num_of_tc_oper[0x4];
9301 u8 reserved_at_58[0x4];
9302 u8 num_of_tc_admin[0x4];
9303 u8 remote_willing[0x1];
9304 u8 reserved_at_61[3];
9305 u8 remote_pfc_cap[4];
9306 u8 reserved_at_68[0x14];
9307 u8 remote_num_of_tc[0x4];
9308 u8 reserved_at_80[0x18];
9309 u8 error[0x8];
9310 u8 reserved_at_a0[0x160];
9311};
84df61eb
AH		 9312
9313struct mlx5_ifc_lagc_bits {
9314 u8 reserved_at_0[0x1d];
9315 u8 lag_state[0x3];
9316
9317 u8 reserved_at_20[0x14];
9318 u8 tx_remap_affinity_2[0x4];
9319 u8 reserved_at_38[0x4];
9320 u8 tx_remap_affinity_1[0x4];
9321};
9322
9323struct mlx5_ifc_create_lag_out_bits {
9324 u8 status[0x8];
9325 u8 reserved_at_8[0x18];
9326
9327 u8 syndrome[0x20];
9328
9329 u8 reserved_at_40[0x40];
9330};
9331
9332struct mlx5_ifc_create_lag_in_bits {
9333 u8 opcode[0x10];
9334 u8 reserved_at_10[0x10];
9335
9336 u8 reserved_at_20[0x10];
9337 u8 op_mod[0x10];
9338
9339 struct mlx5_ifc_lagc_bits ctx;
9340};
9341
9342struct mlx5_ifc_modify_lag_out_bits {
9343 u8 status[0x8];
9344 u8 reserved_at_8[0x18];
9345
9346 u8 syndrome[0x20];
9347
9348 u8 reserved_at_40[0x40];
9349};
9350
9351struct mlx5_ifc_modify_lag_in_bits {
9352 u8 opcode[0x10];
9353 u8 reserved_at_10[0x10];
9354
9355 u8 reserved_at_20[0x10];
9356 u8 op_mod[0x10];
9357
9358 u8 reserved_at_40[0x20];
9359 u8 field_select[0x20];
9360
9361 struct mlx5_ifc_lagc_bits ctx;
9362};
9363
9364struct mlx5_ifc_query_lag_out_bits {
9365 u8 status[0x8];
9366 u8 reserved_at_8[0x18];
9367
9368 u8 syndrome[0x20];
9369
9370 u8 reserved_at_40[0x40];
9371
9372 struct mlx5_ifc_lagc_bits ctx;
9373};
9374
9375struct mlx5_ifc_query_lag_in_bits {
9376 u8 opcode[0x10];
9377 u8 reserved_at_10[0x10];
9378
9379 u8 reserved_at_20[0x10];
9380 u8 op_mod[0x10];
9381
9382 u8 reserved_at_40[0x40];
9383};
9384
9385struct mlx5_ifc_destroy_lag_out_bits {
9386 u8 status[0x8];
9387 u8 reserved_at_8[0x18];
9388
9389 u8 syndrome[0x20];
9390
9391 u8 reserved_at_40[0x40];
9392};
9393
9394struct mlx5_ifc_destroy_lag_in_bits {
9395 u8 opcode[0x10];
9396 u8 reserved_at_10[0x10];
9397
9398 u8 reserved_at_20[0x10];
9399 u8 op_mod[0x10];
9400
9401 u8 reserved_at_40[0x40];
9402};
9403
9404struct mlx5_ifc_create_vport_lag_out_bits {
9405 u8 status[0x8];
9406 u8 reserved_at_8[0x18];
9407
9408 u8 syndrome[0x20];
9409
9410 u8 reserved_at_40[0x40];
9411};
9412
9413struct mlx5_ifc_create_vport_lag_in_bits {
9414 u8 opcode[0x10];
9415 u8 reserved_at_10[0x10];
9416
9417 u8 reserved_at_20[0x10];
9418 u8 op_mod[0x10];
9419
9420 u8 reserved_at_40[0x40];
9421};
9422
9423struct mlx5_ifc_destroy_vport_lag_out_bits {
9424 u8 status[0x8];
9425 u8 reserved_at_8[0x18];
9426
9427 u8 syndrome[0x20];
9428
9429 u8 reserved_at_40[0x40];
9430};
9431
9432struct mlx5_ifc_destroy_vport_lag_in_bits {
9433 u8 opcode[0x10];
9434 u8 reserved_at_10[0x10];
9435
9436 u8 reserved_at_20[0x10];
9437 u8 op_mod[0x10];
9438
9439 u8 reserved_at_40[0x40];
9440};
9441
24da0016
AL		 9442struct mlx5_ifc_alloc_memic_in_bits {
9443 u8 opcode[0x10];
9444 u8 reserved_at_10[0x10];
9445
9446 u8 reserved_at_20[0x10];
9447 u8 op_mod[0x10];
9448
9449 u8 reserved_at_30[0x20];
9450
9451 u8 reserved_at_40[0x18];
9452 u8 log_memic_addr_alignment[0x8];
9453
9454 u8 range_start_addr[0x40];
9455
9456 u8 range_size[0x20];
9457
9458 u8 memic_size[0x20];
9459};
9460
9461struct mlx5_ifc_alloc_memic_out_bits {
9462 u8 status[0x8];
9463 u8 reserved_at_8[0x18];
9464
9465 u8 syndrome[0x20];
9466
9467 u8 memic_start_addr[0x40];
9468};
9469
9470struct mlx5_ifc_dealloc_memic_in_bits {
9471 u8 opcode[0x10];
9472 u8 reserved_at_10[0x10];
9473
9474 u8 reserved_at_20[0x10];
9475 u8 op_mod[0x10];
9476
9477 u8 reserved_at_40[0x40];
9478
9479 u8 memic_start_addr[0x40];
9480
9481 u8 memic_size[0x20];
9482
9483 u8 reserved_at_e0[0x20];
9484};
9485
9486struct mlx5_ifc_dealloc_memic_out_bits {
9487 u8 status[0x8];
9488 u8 reserved_at_8[0x18];
9489
9490 u8 syndrome[0x20];
9491
9492 u8 reserved_at_40[0x40];
9493};
9494
38b7ca92
YH		 9495struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9496 u8 opcode[0x10];
9497 u8 uid[0x10];
9498
9499 u8 reserved_at_20[0x10];
9500 u8 obj_type[0x10];
9501
9502 u8 obj_id[0x20];
9503
9504 u8 reserved_at_60[0x20];
9505};
9506
9507struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9508 u8 status[0x8];
9509 u8 reserved_at_8[0x18];
9510
9511 u8 syndrome[0x20];
9512
9513 u8 obj_id[0x20];
9514
9515 u8 reserved_at_60[0x20];
9516};
9517
9518struct mlx5_ifc_umem_bits {
6e3722ba 9519 u8 reserved_at_0[0x80];
38b7ca92 9520
6e3722ba 9521 u8 reserved_at_80[0x1b];
38b7ca92
YH		 9522 u8 log_page_size[0x5];
9523
9524 u8 page_offset[0x20];
9525
9526 u8 num_of_mtt[0x40];
9527
9528 struct mlx5_ifc_mtt_bits mtt[0];
9529};
9530
9531struct mlx5_ifc_uctx_bits {
9d43faac
YH		 9532 u8 cap[0x20];
9533
6e3722ba 9534 u8 reserved_at_20[0x160];
38b7ca92
YH		 9535};
9536
9fba2b9b
AL		 9537struct mlx5_ifc_sw_icm_bits {
9538 u8 modify_field_select[0x40];
9539
9540 u8 reserved_at_40[0x18];
9541 u8 log_sw_icm_size[0x8];
9542
9543 u8 reserved_at_60[0x20];
9544
9545 u8 sw_icm_start_addr[0x40];
9546
9547 u8 reserved_at_c0[0x140];
9548};
9549
38b7ca92 9550struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 9551 u8 opcode[0x10];
9552 u8 uid[0x10];
9553
9554 u8 reserved_at_20[0x10];
9555 u8 op_mod[0x10];
9556
9557 u8 reserved_at_40[0x40];
9558
9559 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 9560};
9561
9562struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 9563 u8 opcode[0x10];
9564 u8 reserved_at_10[0x10];
9565
9566 u8 reserved_at_20[0x10];
9567 u8 op_mod[0x10];
9568
9569 u8 reserved_at_40[0x40];
9570
9571 struct mlx5_ifc_uctx_bits uctx;
9572};
9573
9574struct mlx5_ifc_destroy_uctx_in_bits {
9575 u8 opcode[0x10];
9576 u8 reserved_at_10[0x10];
9577
9578 u8 reserved_at_20[0x10];
9579 u8 op_mod[0x10];
9580
9581 u8 reserved_at_40[0x10];
9582 u8 uid[0x10];
9583
9584 u8 reserved_at_60[0x20];
38b7ca92
YH		 9585};
9586
9fba2b9b
AL		 9587struct mlx5_ifc_create_sw_icm_in_bits {
9588 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9589 struct mlx5_ifc_sw_icm_bits sw_icm;
9590};
9591
eff8ea8f
FD		 9592struct mlx5_ifc_mtrc_string_db_param_bits {
9593 u8 string_db_base_address[0x20];
9594
9595 u8 reserved_at_20[0x8];
9596 u8 string_db_size[0x18];
9597};
9598
9599struct mlx5_ifc_mtrc_cap_bits {
9600 u8 trace_owner[0x1];
9601 u8 trace_to_memory[0x1];
9602 u8 reserved_at_2[0x4];
9603 u8 trc_ver[0x2];
9604 u8 reserved_at_8[0x14];
9605 u8 num_string_db[0x4];
9606
9607 u8 first_string_trace[0x8];
9608 u8 num_string_trace[0x8];
9609 u8 reserved_at_30[0x28];
9610
9611 u8 log_max_trace_buffer_size[0x8];
9612
9613 u8 reserved_at_60[0x20];
9614
9615 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9616
9617 u8 reserved_at_280[0x180];
9618};
9619
9620struct mlx5_ifc_mtrc_conf_bits {
9621 u8 reserved_at_0[0x1c];
9622 u8 trace_mode[0x4];
9623 u8 reserved_at_20[0x18];
9624 u8 log_trace_buffer_size[0x8];
9625 u8 trace_mkey[0x20];
9626 u8 reserved_at_60[0x3a0];
9627};
9628
9629struct mlx5_ifc_mtrc_stdb_bits {
9630 u8 string_db_index[0x4];
9631 u8 reserved_at_4[0x4];
9632 u8 read_size[0x18];
9633 u8 start_offset[0x20];
9634 u8 string_db_data[0];
9635};
9636
9637struct mlx5_ifc_mtrc_ctrl_bits {
9638 u8 trace_status[0x2];
9639 u8 reserved_at_2[0x2];
9640 u8 arm_event[0x1];
9641 u8 reserved_at_5[0xb];
9642 u8 modify_field_select[0x10];
9643 u8 reserved_at_20[0x2b];
9644 u8 current_timestamp52_32[0x15];
9645 u8 current_timestamp31_0[0x20];
9646 u8 reserved_at_80[0x180];
9647};
9648
c3a4e9f1
BW		 9649struct mlx5_ifc_host_params_context_bits {
9650 u8 host_number[0x8];
9651 u8 reserved_at_8[0x8];
9652 u8 host_num_of_vfs[0x10];
9653
9654 u8 reserved_at_20[0x10];
9655 u8 host_pci_bus[0x10];
9656
9657 u8 reserved_at_40[0x10];
9658 u8 host_pci_device[0x10];
9659
9660 u8 reserved_at_60[0x10];
9661 u8 host_pci_function[0x10];
9662
9663 u8 reserved_at_80[0x180];
9664};
9665
9666struct mlx5_ifc_query_host_params_in_bits {
9667 u8 opcode[0x10];
9668 u8 reserved_at_10[0x10];
9669
9670 u8 reserved_at_20[0x10];
9671 u8 op_mod[0x10];
9672
9673 u8 reserved_at_40[0x40];
9674};
9675
9676struct mlx5_ifc_query_host_params_out_bits {
9677 u8 status[0x8];
9678 u8 reserved_at_8[0x18];
9679
9680 u8 syndrome[0x20];
9681
9682 u8 reserved_at_40[0x40];
9683
9684 struct mlx5_ifc_host_params_context_bits host_params_context;
9685
9686 u8 reserved_at_280[0x180];
9687};
9688
d29b796a 9689#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)