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net/mlx5: Properly handle a vport destination when setting FTE
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 95 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
96 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 97 MLX5_CMD_OP_CREATE_EQ = 0x301,
98 MLX5_CMD_OP_DESTROY_EQ = 0x302,
99 MLX5_CMD_OP_QUERY_EQ = 0x303,
100 MLX5_CMD_OP_GEN_EQE = 0x304,
101 MLX5_CMD_OP_CREATE_CQ = 0x400,
102 MLX5_CMD_OP_DESTROY_CQ = 0x401,
103 MLX5_CMD_OP_QUERY_CQ = 0x402,
104 MLX5_CMD_OP_MODIFY_CQ = 0x403,
105 MLX5_CMD_OP_CREATE_QP = 0x500,
106 MLX5_CMD_OP_DESTROY_QP = 0x501,
107 MLX5_CMD_OP_RST2INIT_QP = 0x502,
108 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
109 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
110 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
112 MLX5_CMD_OP_2ERR_QP = 0x507,
113 MLX5_CMD_OP_2RST_QP = 0x50a,
114 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
117 MLX5_CMD_OP_CREATE_PSV = 0x600,
118 MLX5_CMD_OP_DESTROY_PSV = 0x601,
119 MLX5_CMD_OP_CREATE_SRQ = 0x700,
120 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
121 MLX5_CMD_OP_QUERY_SRQ = 0x702,
122 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 127 MLX5_CMD_OP_CREATE_DCT = 0x710,
128 MLX5_CMD_OP_DESTROY_DCT = 0x711,
129 MLX5_CMD_OP_DRAIN_DCT = 0x712,
130 MLX5_CMD_OP_QUERY_DCT = 0x713,
131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 132 MLX5_CMD_OP_CREATE_XRQ = 0x717,
133 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
134 MLX5_CMD_OP_QUERY_XRQ = 0x719,
135 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 136 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
137 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 143 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 148 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 149 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
150 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
151 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
152 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
37e92a9d 153 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 154 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 155 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
156 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
157 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
158 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
159 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
160 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 161 MLX5_CMD_OP_ALLOC_PD = 0x800,
162 MLX5_CMD_OP_DEALLOC_PD = 0x801,
163 MLX5_CMD_OP_ALLOC_UAR = 0x802,
164 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
165 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
166 MLX5_CMD_OP_ACCESS_REG = 0x805,
167 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 168 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 169 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
170 MLX5_CMD_OP_MAD_IFC = 0x50d,
171 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
172 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
173 MLX5_CMD_OP_NOP = 0x80d,
174 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
175 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 176 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
177 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
178 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
179 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
180 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
181 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
182 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
183 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
184 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
185 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
186 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
187 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 188 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
189 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 190 MLX5_CMD_OP_CREATE_LAG = 0x840,
191 MLX5_CMD_OP_MODIFY_LAG = 0x841,
192 MLX5_CMD_OP_QUERY_LAG = 0x842,
193 MLX5_CMD_OP_DESTROY_LAG = 0x843,
194 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
195 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 196 MLX5_CMD_OP_CREATE_TIR = 0x900,
197 MLX5_CMD_OP_MODIFY_TIR = 0x901,
198 MLX5_CMD_OP_DESTROY_TIR = 0x902,
199 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 200 MLX5_CMD_OP_CREATE_SQ = 0x904,
201 MLX5_CMD_OP_MODIFY_SQ = 0x905,
202 MLX5_CMD_OP_DESTROY_SQ = 0x906,
203 MLX5_CMD_OP_QUERY_SQ = 0x907,
204 MLX5_CMD_OP_CREATE_RQ = 0x908,
205 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 206 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 207 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
208 MLX5_CMD_OP_QUERY_RQ = 0x90b,
209 MLX5_CMD_OP_CREATE_RMP = 0x90c,
210 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
211 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
212 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 213 MLX5_CMD_OP_CREATE_TIS = 0x912,
214 MLX5_CMD_OP_MODIFY_TIS = 0x913,
215 MLX5_CMD_OP_DESTROY_TIS = 0x914,
216 MLX5_CMD_OP_QUERY_TIS = 0x915,
217 MLX5_CMD_OP_CREATE_RQT = 0x916,
218 MLX5_CMD_OP_MODIFY_RQT = 0x917,
219 MLX5_CMD_OP_DESTROY_RQT = 0x918,
220 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 221 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 222 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
223 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
224 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
225 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
226 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
227 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
228 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
229 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 230 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 231 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
232 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
233 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 234 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 235 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
236 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 237 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
238 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 239 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
240 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
241 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
242 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
243 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 244 MLX5_CMD_OP_MAX
e281682b
SM		 245};
246
247struct mlx5_ifc_flow_table_fields_supported_bits {
248 u8 outer_dmac[0x1];
249 u8 outer_smac[0x1];
250 u8 outer_ether_type[0x1];
19cc7524 251 u8 outer_ip_version[0x1];
e281682b
SM		 252 u8 outer_first_prio[0x1];
253 u8 outer_first_cfi[0x1];
254 u8 outer_first_vid[0x1];
a8ade55f 255 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 256 u8 outer_second_prio[0x1];
257 u8 outer_second_cfi[0x1];
258 u8 outer_second_vid[0x1];
b4ff3a36 259 u8 reserved_at_b[0x1];
e281682b
SM		 260 u8 outer_sip[0x1];
261 u8 outer_dip[0x1];
262 u8 outer_frag[0x1];
263 u8 outer_ip_protocol[0x1];
264 u8 outer_ip_ecn[0x1];
265 u8 outer_ip_dscp[0x1];
266 u8 outer_udp_sport[0x1];
267 u8 outer_udp_dport[0x1];
268 u8 outer_tcp_sport[0x1];
269 u8 outer_tcp_dport[0x1];
270 u8 outer_tcp_flags[0x1];
271 u8 outer_gre_protocol[0x1];
272 u8 outer_gre_key[0x1];
273 u8 outer_vxlan_vni[0x1];
b4ff3a36 274 u8 reserved_at_1a[0x5];
e281682b
SM		 275 u8 source_eswitch_port[0x1];
276
277 u8 inner_dmac[0x1];
278 u8 inner_smac[0x1];
279 u8 inner_ether_type[0x1];
19cc7524 280 u8 inner_ip_version[0x1];
e281682b
SM		 281 u8 inner_first_prio[0x1];
282 u8 inner_first_cfi[0x1];
283 u8 inner_first_vid[0x1];
b4ff3a36 284 u8 reserved_at_27[0x1];
e281682b
SM		 285 u8 inner_second_prio[0x1];
286 u8 inner_second_cfi[0x1];
287 u8 inner_second_vid[0x1];
b4ff3a36 288 u8 reserved_at_2b[0x1];
e281682b
SM		 289 u8 inner_sip[0x1];
290 u8 inner_dip[0x1];
291 u8 inner_frag[0x1];
292 u8 inner_ip_protocol[0x1];
293 u8 inner_ip_ecn[0x1];
294 u8 inner_ip_dscp[0x1];
295 u8 inner_udp_sport[0x1];
296 u8 inner_udp_dport[0x1];
297 u8 inner_tcp_sport[0x1];
298 u8 inner_tcp_dport[0x1];
299 u8 inner_tcp_flags[0x1];
b4ff3a36 300 u8 reserved_at_37[0x9];
3346c487
BP		 301 u8 reserved_at_40[0x17];
302 u8 outer_esp_spi[0x1];
303 u8 reserved_at_58[0x2];
a550ddfc 304 u8 bth_dst_qp[0x1];
e281682b 305
a550ddfc 306 u8 reserved_at_5b[0x25];
e281682b
SM		 307};
308
309struct mlx5_ifc_flow_table_prop_layout_bits {
310 u8 ft_support[0x1];
9dc0b289
AV		 311 u8 reserved_at_1[0x1];
312 u8 flow_counter[0x1];
26a81453 313 u8 flow_modify_en[0x1];
2cc43b49 314 u8 modify_root[0x1];
34a40e68
MG		 315 u8 identified_miss_table_mode[0x1];
316 u8 flow_table_modify[0x1];
7adbde20
HHZ		 317 u8 encap[0x1];
318 u8 decap[0x1];
0c06897a
OG		 319 u8 reserved_at_9[0x1];
320 u8 pop_vlan[0x1];
321 u8 push_vlan[0x1];
322 u8 reserved_at_c[0x14];
e281682b 323
b4ff3a36 324 u8 reserved_at_20[0x2];
e281682b 325 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 326 u8 log_max_modify_header_context[0x8];
327 u8 max_modify_header_actions[0x8];
e281682b
SM		 328 u8 max_ft_level[0x8];
329
b4ff3a36 330 u8 reserved_at_40[0x20];
e281682b 331
b4ff3a36 332 u8 reserved_at_60[0x18];
e281682b
SM		 333 u8 log_max_ft_num[0x8];
334
b4ff3a36 335 u8 reserved_at_80[0x18];
e281682b
SM		 336 u8 log_max_destination[0x8];
337
16f1c5bb
RS		 338 u8 log_max_flow_counter[0x8];
339 u8 reserved_at_a8[0x10];
e281682b
SM		 340 u8 log_max_flow[0x8];
341
b4ff3a36 342 u8 reserved_at_c0[0x40];
e281682b
SM		 343
344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
345
346 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
347};
348
349struct mlx5_ifc_odp_per_transport_service_cap_bits {
350 u8 send[0x1];
351 u8 receive[0x1];
352 u8 write[0x1];
353 u8 read[0x1];
17d2f88f 354 u8 atomic[0x1];
e281682b 355 u8 srq_receive[0x1];
b4ff3a36 356 u8 reserved_at_6[0x1a];
e281682b
SM		 357};
358
b4d1f032 359struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 360 u8 reserved_at_0[0x60];
b4d1f032
MG		 361
362 u8 ipv4[0x20];
363};
364
365struct mlx5_ifc_ipv6_layout_bits {
366 u8 ipv6[16][0x8];
367};
368
369union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
370 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
371 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 372 u8 reserved_at_0[0x80];
b4d1f032
MG		 373};
374
e281682b
SM		 375struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
376 u8 smac_47_16[0x20];
377
378 u8 smac_15_0[0x10];
379 u8 ethertype[0x10];
380
381 u8 dmac_47_16[0x20];
382
383 u8 dmac_15_0[0x10];
384 u8 first_prio[0x3];
385 u8 first_cfi[0x1];
386 u8 first_vid[0xc];
387
388 u8 ip_protocol[0x8];
389 u8 ip_dscp[0x6];
390 u8 ip_ecn[0x2];
10543365
MHY		 391 u8 cvlan_tag[0x1];
392 u8 svlan_tag[0x1];
e281682b 393 u8 frag[0x1];
19cc7524 394 u8 ip_version[0x4];
e281682b
SM		 395 u8 tcp_flags[0x9];
396
397 u8 tcp_sport[0x10];
398 u8 tcp_dport[0x10];
399
a8ade55f
OG		 400 u8 reserved_at_c0[0x18];
401 u8 ttl_hoplimit[0x8];
e281682b
SM		 402
403 u8 udp_sport[0x10];
404 u8 udp_dport[0x10];
405
b4d1f032 406 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 407
b4d1f032 408 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 409};
410
411struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 412 u8 reserved_at_0[0x8];
413 u8 source_sqn[0x18];
e281682b 414
b4ff3a36 415 u8 reserved_at_20[0x10];
e281682b
SM		 416 u8 source_port[0x10];
417
418 u8 outer_second_prio[0x3];
419 u8 outer_second_cfi[0x1];
420 u8 outer_second_vid[0xc];
421 u8 inner_second_prio[0x3];
422 u8 inner_second_cfi[0x1];
423 u8 inner_second_vid[0xc];
424
10543365
MHY		 425 u8 outer_second_cvlan_tag[0x1];
426 u8 inner_second_cvlan_tag[0x1];
427 u8 outer_second_svlan_tag[0x1];
428 u8 inner_second_svlan_tag[0x1];
429 u8 reserved_at_64[0xc];
e281682b
SM		 430 u8 gre_protocol[0x10];
431
432 u8 gre_key_h[0x18];
433 u8 gre_key_l[0x8];
434
435 u8 vxlan_vni[0x18];
b4ff3a36 436 u8 reserved_at_b8[0x8];
e281682b 437
b4ff3a36 438 u8 reserved_at_c0[0x20];
e281682b 439
b4ff3a36 440 u8 reserved_at_e0[0xc];
e281682b
SM		 441 u8 outer_ipv6_flow_label[0x14];
442
b4ff3a36 443 u8 reserved_at_100[0xc];
e281682b
SM		 444 u8 inner_ipv6_flow_label[0x14];
445
a550ddfc
YH		 446 u8 reserved_at_120[0x28];
447 u8 bth_dst_qp[0x18];
3346c487
BP		 448 u8 reserved_at_160[0x20];
449 u8 outer_esp_spi[0x20];
450 u8 reserved_at_1a0[0x60];
e281682b
SM		 451};
452
453struct mlx5_ifc_cmd_pas_bits {
454 u8 pa_h[0x20];
455
456 u8 pa_l[0x14];
b4ff3a36 457 u8 reserved_at_34[0xc];
e281682b
SM		 458};
459
460struct mlx5_ifc_uint64_bits {
461 u8 hi[0x20];
462
463 u8 lo[0x20];
464};
465
466enum {
467 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
468 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
469 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
470 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
471 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
472 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
473 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
474 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
475 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
476 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
477};
478
479struct mlx5_ifc_ads_bits {
480 u8 fl[0x1];
481 u8 free_ar[0x1];
b4ff3a36 482 u8 reserved_at_2[0xe];
e281682b
SM		 483 u8 pkey_index[0x10];
484
b4ff3a36 485 u8 reserved_at_20[0x8];
e281682b
SM		 486 u8 grh[0x1];
487 u8 mlid[0x7];
488 u8 rlid[0x10];
489
490 u8 ack_timeout[0x5];
b4ff3a36 491 u8 reserved_at_45[0x3];
e281682b 492 u8 src_addr_index[0x8];
b4ff3a36 493 u8 reserved_at_50[0x4];
e281682b
SM		 494 u8 stat_rate[0x4];
495 u8 hop_limit[0x8];
496
b4ff3a36 497 u8 reserved_at_60[0x4];
e281682b
SM		 498 u8 tclass[0x8];
499 u8 flow_label[0x14];
500
501 u8 rgid_rip[16][0x8];
502
b4ff3a36 503 u8 reserved_at_100[0x4];
e281682b
SM		 504 u8 f_dscp[0x1];
505 u8 f_ecn[0x1];
b4ff3a36 506 u8 reserved_at_106[0x1];
e281682b
SM		 507 u8 f_eth_prio[0x1];
508 u8 ecn[0x2];
509 u8 dscp[0x6];
510 u8 udp_sport[0x10];
511
512 u8 dei_cfi[0x1];
513 u8 eth_prio[0x3];
514 u8 sl[0x4];
32f69e4b 515 u8 vhca_port_num[0x8];
e281682b
SM		 516 u8 rmac_47_32[0x10];
517
518 u8 rmac_31_0[0x20];
519};
520
521struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 522 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 523 u8 nic_rx_multi_path_tirs_fts[0x1];
524 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
525 u8 reserved_at_3[0x1fd];
e281682b
SM		 526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
528
b4ff3a36 529 u8 reserved_at_400[0x200];
e281682b
SM		 530
531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
532
533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
534
b4ff3a36 535 u8 reserved_at_a00[0x200];
e281682b
SM		 536
537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
538
b4ff3a36 539 u8 reserved_at_e00[0x7200];
e281682b
SM		 540};
541
495716b1 542struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 543 u8 reserved_at_0[0x200];
495716b1
SM		 544
545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
546
547 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
548
549 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
550
b4ff3a36 551 u8 reserved_at_800[0x7800];
495716b1
SM		 552};
553
d6666753
SM		 554struct mlx5_ifc_e_switch_cap_bits {
555 u8 vport_svlan_strip[0x1];
556 u8 vport_cvlan_strip[0x1];
557 u8 vport_svlan_insert[0x1];
558 u8 vport_cvlan_insert_if_not_exist[0x1];
559 u8 vport_cvlan_insert_overwrite[0x1];
a6d04569
RD		 560 u8 reserved_at_5[0x18];
561 u8 merged_eswitch[0x1];
23898c76
NO		 562 u8 nic_vport_node_guid_modify[0x1];
563 u8 nic_vport_port_guid_modify[0x1];
d6666753 564
7adbde20
HHZ		 565 u8 vxlan_encap_decap[0x1];
566 u8 nvgre_encap_decap[0x1];
567 u8 reserved_at_22[0x9];
568 u8 log_max_encap_headers[0x5];
569 u8 reserved_2b[0x6];
570 u8 max_encap_header_size[0xa];
571
572 u8 reserved_40[0x7c0];
573
d6666753
SM		 574};
575
7486216b
SM		 576struct mlx5_ifc_qos_cap_bits {
577 u8 packet_pacing[0x1];
813f8540 578 u8 esw_scheduling[0x1];
c9497c98
MHY		 579 u8 esw_bw_share[0x1];
580 u8 esw_rate_limit[0x1];
05d3ac97
BW		 581 u8 reserved_at_4[0x1];
582 u8 packet_pacing_burst_bound[0x1];
583 u8 packet_pacing_typical_size[0x1];
584 u8 reserved_at_7[0x19];
813f8540
MHY		 585
586 u8 reserved_at_20[0x20];
587
7486216b 588 u8 packet_pacing_max_rate[0x20];
813f8540 589
7486216b 590 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 591
592 u8 reserved_at_80[0x10];
7486216b 593 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 594
595 u8 esw_element_type[0x10];
596 u8 esw_tsar_type[0x10];
597
598 u8 reserved_at_c0[0x10];
599 u8 max_qos_para_vport[0x10];
600
601 u8 max_tsar_bw_share[0x20];
602
603 u8 reserved_at_100[0x700];
7486216b
SM		 604};
605
2fcb12df
IK		 606struct mlx5_ifc_debug_cap_bits {
607 u8 reserved_at_0[0x20];
608
609 u8 reserved_at_20[0x2];
610 u8 stall_detect[0x1];
611 u8 reserved_at_23[0x1d];
612
613 u8 reserved_at_40[0x7c0];
614};
615
e281682b
SM		 616struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
617 u8 csum_cap[0x1];
618 u8 vlan_cap[0x1];
619 u8 lro_cap[0x1];
620 u8 lro_psh_flag[0x1];
621 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 622 u8 reserved_at_5[0x2];
623 u8 wqe_vlan_insert[0x1];
66189961 624 u8 self_lb_en_modifiable[0x1];
b4ff3a36 625 u8 reserved_at_9[0x2];
e281682b 626 u8 max_lso_cap[0x5];
c226dc22 627 u8 multi_pkt_send_wqe[0x2];
cff92d7c 628 u8 wqe_inline_mode[0x2];
e281682b 629 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 630 u8 reg_umr_sq[0x1];
631 u8 scatter_fcs[0x1];
050da902 632 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 633 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 634 u8 reserved_at_1c[0x2];
27299841 635 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 636 u8 tunnel_stateless_vxlan[0x1];
637
547eede0
IT		 638 u8 swp[0x1];
639 u8 swp_csum[0x1];
640 u8 swp_lso[0x1];
4d350f1f
MG		 641 u8 reserved_at_23[0x1b];
642 u8 max_geneve_opt_len[0x1];
643 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 644
b4ff3a36 645 u8 reserved_at_40[0x10];
e281682b
SM		 646 u8 lro_min_mss_size[0x10];
647
b4ff3a36 648 u8 reserved_at_60[0x120];
e281682b
SM		 649
650 u8 lro_timer_supported_periods[4][0x20];
651
b4ff3a36 652 u8 reserved_at_200[0x600];
e281682b
SM		 653};
654
655struct mlx5_ifc_roce_cap_bits {
656 u8 roce_apm[0x1];
b4ff3a36 657 u8 reserved_at_1[0x1f];
e281682b 658
b4ff3a36 659 u8 reserved_at_20[0x60];
e281682b 660
b4ff3a36 661 u8 reserved_at_80[0xc];
e281682b 662 u8 l3_type[0x4];
b4ff3a36 663 u8 reserved_at_90[0x8];
e281682b
SM		 664 u8 roce_version[0x8];
665
b4ff3a36 666 u8 reserved_at_a0[0x10];
e281682b
SM		 667 u8 r_roce_dest_udp_port[0x10];
668
669 u8 r_roce_max_src_udp_port[0x10];
670 u8 r_roce_min_src_udp_port[0x10];
671
b4ff3a36 672 u8 reserved_at_e0[0x10];
e281682b
SM		 673 u8 roce_address_table_size[0x10];
674
b4ff3a36 675 u8 reserved_at_100[0x700];
e281682b
SM		 676};
677
e72bd817
AL		 678struct mlx5_ifc_device_mem_cap_bits {
679 u8 memic[0x1];
680 u8 reserved_at_1[0x1f];
681
682 u8 reserved_at_20[0xb];
683 u8 log_min_memic_alloc_size[0x5];
684 u8 reserved_at_30[0x8];
685 u8 log_max_memic_addr_alignment[0x8];
686
687 u8 memic_bar_start_addr[0x40];
688
689 u8 memic_bar_size[0x20];
690
691 u8 max_memic_size[0x20];
692
693 u8 reserved_at_c0[0x740];
694};
695
e281682b
SM		 696enum {
697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
702 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
703 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
704 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
705 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
706};
707
708enum {
709 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
710 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
711 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
712 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
713 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
714 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
715 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
716 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
717 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
718};
719
720struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 721 u8 reserved_at_0[0x40];
e281682b 722
bd10838a 723 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 724 u8 reserved_at_42[0x4];
bd10838a 725 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 726
b4ff3a36 727 u8 reserved_at_47[0x19];
e281682b 728
b4ff3a36 729 u8 reserved_at_60[0x20];
e281682b 730
b4ff3a36 731 u8 reserved_at_80[0x10];
f91e6d89 732 u8 atomic_operations[0x10];
e281682b 733
b4ff3a36 734 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 735 u8 atomic_size_qp[0x10];
736
b4ff3a36 737 u8 reserved_at_c0[0x10];
e281682b
SM		 738 u8 atomic_size_dc[0x10];
739
b4ff3a36 740 u8 reserved_at_e0[0x720];
e281682b
SM		 741};
742
743struct mlx5_ifc_odp_cap_bits {
b4ff3a36 744 u8 reserved_at_0[0x40];
e281682b
SM		 745
746 u8 sig[0x1];
b4ff3a36 747 u8 reserved_at_41[0x1f];
e281682b 748
b4ff3a36 749 u8 reserved_at_60[0x20];
e281682b
SM		 750
751 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
752
753 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
754
755 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
756
b4ff3a36 757 u8 reserved_at_e0[0x720];
e281682b
SM		 758};
759
3f0393a5
SG		 760struct mlx5_ifc_calc_op {
761 u8 reserved_at_0[0x10];
762 u8 reserved_at_10[0x9];
763 u8 op_swap_endianness[0x1];
764 u8 op_min[0x1];
765 u8 op_xor[0x1];
766 u8 op_or[0x1];
767 u8 op_and[0x1];
768 u8 op_max[0x1];
769 u8 op_add[0x1];
770};
771
772struct mlx5_ifc_vector_calc_cap_bits {
773 u8 calc_matrix[0x1];
774 u8 reserved_at_1[0x1f];
775 u8 reserved_at_20[0x8];
776 u8 max_vec_count[0x8];
777 u8 reserved_at_30[0xd];
778 u8 max_chunk_size[0x3];
779 struct mlx5_ifc_calc_op calc0;
780 struct mlx5_ifc_calc_op calc1;
781 struct mlx5_ifc_calc_op calc2;
782 struct mlx5_ifc_calc_op calc3;
783
784 u8 reserved_at_e0[0x720];
785};
786
e281682b
SM		 787enum {
788 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
789 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 790 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 791 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 792};
793
794enum {
795 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
796 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
797};
798
799enum {
800 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
801 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
802 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
803 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
804 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
805};
806
807enum {
808 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
809 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
810 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
811 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
812 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
813 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
814};
815
816enum {
817 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
818 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
819};
820
821enum {
822 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
823 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
824 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
825};
826
827enum {
828 MLX5_CAP_PORT_TYPE_IB = 0x0,
829 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 830};
831
1410a90a
MG		 832enum {
833 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
834 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
835 MLX5_CAP_UMR_FENCE_NONE = 0x2,
836};
837
b775516b 838struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 839 u8 reserved_at_0[0x30];
840 u8 vhca_id[0x10];
841
842 u8 reserved_at_40[0x40];
b775516b
EC		 843
844 u8 log_max_srq_sz[0x8];
845 u8 log_max_qp_sz[0x8];
b4ff3a36 846 u8 reserved_at_90[0xb];
b775516b
EC		 847 u8 log_max_qp[0x5];
848
b4ff3a36 849 u8 reserved_at_a0[0xb];
e281682b 850 u8 log_max_srq[0x5];
b4ff3a36 851 u8 reserved_at_b0[0x10];
b775516b 852
b4ff3a36 853 u8 reserved_at_c0[0x8];
b775516b 854 u8 log_max_cq_sz[0x8];
b4ff3a36 855 u8 reserved_at_d0[0xb];
b775516b
EC		 856 u8 log_max_cq[0x5];
857
858 u8 log_max_eq_sz[0x8];
b4ff3a36 859 u8 reserved_at_e8[0x2];
b775516b 860 u8 log_max_mkey[0x6];
b4ff3a36 861 u8 reserved_at_f0[0xc];
b775516b
EC		 862 u8 log_max_eq[0x4];
863
864 u8 max_indirection[0x8];
bcda1aca 865 u8 fixed_buffer_size[0x1];
b775516b 866 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 867 u8 force_teardown[0x1];
868 u8 reserved_at_111[0x1];
b775516b 869 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 870 u8 umr_extended_translation_offset[0x1];
871 u8 null_mkey[0x1];
b775516b
EC		 872 u8 log_max_klm_list_size[0x6];
873
b4ff3a36 874 u8 reserved_at_120[0xa];
b775516b 875 u8 log_max_ra_req_dc[0x6];
b4ff3a36 876 u8 reserved_at_130[0xa];
b775516b
EC		 877 u8 log_max_ra_res_dc[0x6];
878
b4ff3a36 879 u8 reserved_at_140[0xa];
b775516b 880 u8 log_max_ra_req_qp[0x6];
b4ff3a36 881 u8 reserved_at_150[0xa];
b775516b
EC		 882 u8 log_max_ra_res_qp[0x6];
883
f32f5bd2 884 u8 end_pad[0x1];
b775516b
EC		 885 u8 cc_query_allowed[0x1];
886 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 887 u8 start_pad[0x1];
888 u8 cache_line_128byte[0x1];
c02762eb
HN		 889 u8 reserved_at_165[0xa];
890 u8 qcam_reg[0x1];
e281682b 891 u8 gid_table_size[0x10];
b775516b 892
e281682b
SM		 893 u8 out_of_seq_cnt[0x1];
894 u8 vport_counters[0x1];
7486216b 895 u8 retransmission_q_counters[0x1];
2fcb12df 896 u8 debug[0x1];
83b502a1 897 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 898 u8 rq_delay_drop[0x1];
b775516b
EC		 899 u8 max_qp_cnt[0xa];
900 u8 pkey_table_size[0x10];
901
e281682b
SM		 902 u8 vport_group_manager[0x1];
903 u8 vhca_group_manager[0x1];
904 u8 ib_virt[0x1];
905 u8 eth_virt[0x1];
61c5b5c9 906 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 907 u8 ets[0x1];
908 u8 nic_flow_table[0x1];
54f0a411 909 u8 eswitch_flow_table[0x1];
e72bd817 910 u8 device_memory[0x1];
cfdcbcea
GP		 911 u8 mcam_reg[0x1];
912 u8 pcam_reg[0x1];
b775516b 913 u8 local_ca_ack_delay[0x5];
4ce3bf2f 914 u8 port_module_event[0x1];
58dcb60a 915 u8 enhanced_error_q_counters[0x1];
7d5e1423 916 u8 ports_check[0x1];
7b13558f 917 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 918 u8 disable_link_up[0x1];
919 u8 beacon_led[0x1];
e281682b 920 u8 port_type[0x2];
b775516b
EC		 921 u8 num_ports[0x8];
922
f9a1ef72
EE		 923 u8 reserved_at_1c0[0x1];
924 u8 pps[0x1];
925 u8 pps_modify[0x1];
b775516b 926 u8 log_max_msg[0x5];
e1c9c62b 927 u8 reserved_at_1c8[0x4];
4f3961ee 928 u8 max_tc[0x4];
7486216b
SM		 929 u8 reserved_at_1d0[0x1];
930 u8 dcbx[0x1];
246ac981
MG		 931 u8 general_notification_event[0x1];
932 u8 reserved_at_1d3[0x2];
e29341fb 933 u8 fpga[0x1];
928cfe87
TT		 934 u8 rol_s[0x1];
935 u8 rol_g[0x1];
e1c9c62b 936 u8 reserved_at_1d8[0x1];
928cfe87
TT		 937 u8 wol_s[0x1];
938 u8 wol_g[0x1];
939 u8 wol_a[0x1];
940 u8 wol_b[0x1];
941 u8 wol_m[0x1];
942 u8 wol_u[0x1];
943 u8 wol_p[0x1];
b775516b
EC		 944
945 u8 stat_rate_support[0x10];
e1c9c62b 946 u8 reserved_at_1f0[0xc];
e281682b 947 u8 cqe_version[0x4];
b775516b 948
e281682b 949 u8 compact_address_vector[0x1];
7d5e1423 950 u8 striding_rq[0x1];
500a3d0d
ES		 951 u8 reserved_at_202[0x1];
952 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 953 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 954 u8 reserved_at_205[0x1];
955 u8 repeated_block_disabled[0x1];
956 u8 umr_modify_entity_size_disabled[0x1];
957 u8 umr_modify_atomic_disabled[0x1];
958 u8 umr_indirect_mkey_disabled[0x1];
1410a90a
MG		 959 u8 umr_fence[0x2];
960 u8 reserved_at_20c[0x3];
e281682b 961 u8 drain_sigerr[0x1];
b775516b
EC		 962 u8 cmdif_checksum[0x2];
963 u8 sigerr_cqe[0x1];
e1c9c62b 964 u8 reserved_at_213[0x1];
b775516b
EC		 965 u8 wq_signature[0x1];
966 u8 sctr_data_cqe[0x1];
e1c9c62b 967 u8 reserved_at_216[0x1];
b775516b
EC		 968 u8 sho[0x1];
969 u8 tph[0x1];
970 u8 rf[0x1];
e281682b 971 u8 dct[0x1];
7486216b 972 u8 qos[0x1];
e281682b 973 u8 eth_net_offloads[0x1];
b775516b
EC		 974 u8 roce[0x1];
975 u8 atomic[0x1];
e1c9c62b 976 u8 reserved_at_21f[0x1];
b775516b
EC		 977
978 u8 cq_oi[0x1];
979 u8 cq_resize[0x1];
980 u8 cq_moderation[0x1];
e1c9c62b 981 u8 reserved_at_223[0x3];
e281682b 982 u8 cq_eq_remap[0x1];
b775516b
EC		 983 u8 pg[0x1];
984 u8 block_lb_mc[0x1];
e1c9c62b 985 u8 reserved_at_229[0x1];
e281682b 986 u8 scqe_break_moderation[0x1];
7d5e1423 987 u8 cq_period_start_from_cqe[0x1];
b775516b 988 u8 cd[0x1];
e1c9c62b 989 u8 reserved_at_22d[0x1];
b775516b 990 u8 apm[0x1];
3f0393a5 991 u8 vector_calc[0x1];
7d5e1423 992 u8 umr_ptr_rlky[0x1];
d2370e0a 993 u8 imaicl[0x1];
e1c9c62b 994 u8 reserved_at_232[0x4];
b775516b
EC		 995 u8 qkv[0x1];
996 u8 pkv[0x1];
b11a4f9c
HE		 997 u8 set_deth_sqpn[0x1];
998 u8 reserved_at_239[0x3];
b775516b
EC		 999 u8 xrc[0x1];
1000 u8 ud[0x1];
1001 u8 uc[0x1];
1002 u8 rc[0x1];
1003
a6d51b68
EC		 1004 u8 uar_4k[0x1];
1005 u8 reserved_at_241[0x9];
b775516b 1006 u8 uar_sz[0x6];
e1c9c62b 1007 u8 reserved_at_250[0x8];
b775516b
EC		 1008 u8 log_pg_sz[0x8];
1009
1010 u8 bf[0x1];
0dbc6fe0 1011 u8 driver_version[0x1];
e281682b 1012 u8 pad_tx_eth_packet[0x1];
e1c9c62b 1013 u8 reserved_at_263[0x8];
b775516b 1014 u8 log_bf_reg_size[0x5];
84df61eb
AH		 1015
1016 u8 reserved_at_270[0xb];
1017 u8 lag_master[0x1];
1018 u8 num_lag_ports[0x4];
b775516b 1019
e1c9c62b 1020 u8 reserved_at_280[0x10];
b775516b
EC		 1021 u8 max_wqe_sz_sq[0x10];
1022
e1c9c62b 1023 u8 reserved_at_2a0[0x10];
b775516b
EC		 1024 u8 max_wqe_sz_rq[0x10];
1025
a8ffcc74 1026 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1027 u8 max_wqe_sz_sq_dc[0x10];
1028
e1c9c62b 1029 u8 reserved_at_2e0[0x7];
b775516b
EC		 1030 u8 max_qp_mcg[0x19];
1031
e1c9c62b 1032 u8 reserved_at_300[0x18];
b775516b
EC		 1033 u8 log_max_mcg[0x8];
1034
e1c9c62b 1035 u8 reserved_at_320[0x3];
e281682b 1036 u8 log_max_transport_domain[0x5];
e1c9c62b 1037 u8 reserved_at_328[0x3];
b775516b 1038 u8 log_max_pd[0x5];
e1c9c62b 1039 u8 reserved_at_330[0xb];
b775516b
EC		 1040 u8 log_max_xrcd[0x5];
1041
5c298143 1042 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1043 u8 receive_discard_vport_down[0x1];
1044 u8 transmit_discard_vport_down[0x1];
1045 u8 reserved_at_343[0x5];
a351a1b0 1046 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1047 u8 max_flow_counter_15_0[0x10];
a351a1b0 1048
b775516b 1049
e1c9c62b 1050 u8 reserved_at_360[0x3];
b775516b 1051 u8 log_max_rq[0x5];
e1c9c62b 1052 u8 reserved_at_368[0x3];
b775516b 1053 u8 log_max_sq[0x5];
e1c9c62b 1054 u8 reserved_at_370[0x3];
b775516b 1055 u8 log_max_tir[0x5];
e1c9c62b 1056 u8 reserved_at_378[0x3];
b775516b
EC		 1057 u8 log_max_tis[0x5];
1058
e281682b 1059 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1060 u8 reserved_at_381[0x2];
e281682b 1061 u8 log_max_rmp[0x5];
e1c9c62b 1062 u8 reserved_at_388[0x3];
e281682b 1063 u8 log_max_rqt[0x5];
e1c9c62b 1064 u8 reserved_at_390[0x3];
e281682b 1065 u8 log_max_rqt_size[0x5];
e1c9c62b 1066 u8 reserved_at_398[0x3];
b775516b
EC		 1067 u8 log_max_tis_per_sq[0x5];
1068
619a8f2a
TT		 1069 u8 ext_stride_num_range[0x1];
1070 u8 reserved_at_3a1[0x2];
e281682b 1071 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1072 u8 reserved_at_3a8[0x3];
e281682b 1073 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1074 u8 reserved_at_3b0[0x3];
e281682b 1075 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1076 u8 reserved_at_3b8[0x3];
e281682b
SM		 1077 u8 log_min_stride_sz_sq[0x5];
1078
40817cdb
OG		 1079 u8 hairpin[0x1];
1080 u8 reserved_at_3c1[0x2];
1081 u8 log_max_hairpin_queues[0x5];
1082 u8 reserved_at_3c8[0x3];
1083 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1084 u8 reserved_at_3d0[0x3];
1085 u8 log_max_hairpin_num_packets[0x5];
1086 u8 reserved_at_3d8[0x3];
e281682b
SM		 1087 u8 log_max_wq_sz[0x5];
1088
54f0a411 1089 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1090 u8 disable_local_lb_uc[0x1];
1091 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1092 u8 log_min_hairpin_wq_data_sz[0x5];
1093 u8 reserved_at_3e8[0x3];
54f0a411 1094 u8 log_max_vlan_list[0x5];
e1c9c62b 1095 u8 reserved_at_3f0[0x3];
54f0a411 1096 u8 log_max_current_mc_list[0x5];
e1c9c62b 1097 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1098 u8 log_max_current_uc_list[0x5];
1099
e1c9c62b 1100 u8 reserved_at_400[0x80];
54f0a411 1101
e1c9c62b 1102 u8 reserved_at_480[0x3];
e281682b 1103 u8 log_max_l2_table[0x5];
e1c9c62b 1104 u8 reserved_at_488[0x8];
b775516b
EC		 1105 u8 log_uar_page_sz[0x10];
1106
e1c9c62b 1107 u8 reserved_at_4a0[0x20];
048ccca8 1108 u8 device_frequency_mhz[0x20];
b0844444 1109 u8 device_frequency_khz[0x20];
e1c9c62b 1110
a6d51b68
EC		 1111 u8 reserved_at_500[0x20];
1112 u8 num_of_uars_per_page[0x20];
1113 u8 reserved_at_540[0x40];
e1c9c62b 1114
0ff8e79c
GL		 1115 u8 reserved_at_580[0x3d];
1116 u8 cqe_128_always[0x1];
1117 u8 cqe_compression_128[0x1];
7d5e1423 1118 u8 cqe_compression[0x1];
b775516b 1119
7d5e1423
SM		 1120 u8 cqe_compression_timeout[0x10];
1121 u8 cqe_compression_max_num[0x10];
b775516b 1122
7486216b
SM		 1123 u8 reserved_at_5e0[0x10];
1124 u8 tag_matching[0x1];
1125 u8 rndv_offload_rc[0x1];
1126 u8 rndv_offload_dc[0x1];
1127 u8 log_tag_matching_list_sz[0x5];
7b13558f 1128 u8 reserved_at_5f8[0x3];
7486216b
SM		 1129 u8 log_max_xrq[0x5];
1130
32f69e4b
DJ		 1131 u8 affiliate_nic_vport_criteria[0x8];
1132 u8 native_port_num[0x8];
1133 u8 num_vhca_ports[0x8];
1134 u8 reserved_at_618[0x6];
1135 u8 sw_owner_id[0x1];
8737f818 1136 u8 reserved_at_61f[0x1e1];
b775516b
EC		 1137};
1138
81848731
SM		 1139enum mlx5_flow_destination_type {
1140 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1141 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1142 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1143
5f418378 1144 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1145 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1146};
b775516b 1147
e281682b
SM		 1148struct mlx5_ifc_dest_format_struct_bits {
1149 u8 destination_type[0x8];
1150 u8 destination_id[0x18];
b775516b 1151
b4ff3a36 1152 u8 reserved_at_20[0x20];
e281682b
SM		 1153};
1154
9dc0b289 1155struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1156 u8 flow_counter_id[0x20];
9dc0b289
AV		 1157
1158 u8 reserved_at_20[0x20];
1159};
1160
1161union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1162 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1163 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1164 u8 reserved_at_0[0x40];
1165};
1166
e281682b
SM		 1167struct mlx5_ifc_fte_match_param_bits {
1168 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1169
1170 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1171
1172 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1173
b4ff3a36 1174 u8 reserved_at_600[0xa00];
b775516b
EC		 1175};
1176
e281682b
SM		 1177enum {
1178 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1179 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1180 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1181 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1182 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1183};
b775516b 1184
e281682b
SM		 1185struct mlx5_ifc_rx_hash_field_select_bits {
1186 u8 l3_prot_type[0x1];
1187 u8 l4_prot_type[0x1];
1188 u8 selected_fields[0x1e];
1189};
b775516b 1190
e281682b
SM		 1191enum {
1192 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1193 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1194};
1195
e281682b
SM		 1196enum {
1197 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1198 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1199};
1200
1201struct mlx5_ifc_wq_bits {
1202 u8 wq_type[0x4];
1203 u8 wq_signature[0x1];
1204 u8 end_padding_mode[0x2];
1205 u8 cd_slave[0x1];
b4ff3a36 1206 u8 reserved_at_8[0x18];
b775516b 1207
e281682b
SM		 1208 u8 hds_skip_first_sge[0x1];
1209 u8 log2_hds_buf_size[0x3];
b4ff3a36 1210 u8 reserved_at_24[0x7];
e281682b
SM		 1211 u8 page_offset[0x5];
1212 u8 lwm[0x10];
b775516b 1213
b4ff3a36 1214 u8 reserved_at_40[0x8];
e281682b
SM		 1215 u8 pd[0x18];
1216
b4ff3a36 1217 u8 reserved_at_60[0x8];
e281682b
SM		 1218 u8 uar_page[0x18];
1219
1220 u8 dbr_addr[0x40];
1221
1222 u8 hw_counter[0x20];
1223
1224 u8 sw_counter[0x20];
1225
b4ff3a36 1226 u8 reserved_at_100[0xc];
e281682b 1227 u8 log_wq_stride[0x4];
b4ff3a36 1228 u8 reserved_at_110[0x3];
e281682b 1229 u8 log_wq_pg_sz[0x5];
b4ff3a36 1230 u8 reserved_at_118[0x3];
e281682b
SM		 1231 u8 log_wq_sz[0x5];
1232
4d533e0f
OG		 1233 u8 reserved_at_120[0x3];
1234 u8 log_hairpin_num_packets[0x5];
1235 u8 reserved_at_128[0x3];
40817cdb 1236 u8 log_hairpin_data_sz[0x5];
40817cdb 1237
619a8f2a
TT		 1238 u8 reserved_at_130[0x4];
1239 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1240 u8 two_byte_shift_en[0x1];
1241 u8 reserved_at_139[0x4];
1242 u8 log_wqe_stride_size[0x3];
1243
1244 u8 reserved_at_140[0x4c0];
b775516b 1245
e281682b 1246 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1247};
1248
e281682b 1249struct mlx5_ifc_rq_num_bits {
b4ff3a36 1250 u8 reserved_at_0[0x8];
e281682b
SM		 1251 u8 rq_num[0x18];
1252};
b775516b 1253
e281682b 1254struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1255 u8 reserved_at_0[0x10];
e281682b 1256 u8 mac_addr_47_32[0x10];
b775516b 1257
e281682b
SM		 1258 u8 mac_addr_31_0[0x20];
1259};
1260
c0046cf7 1261struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1262 u8 reserved_at_0[0x14];
c0046cf7
SM		 1263 u8 vlan[0x0c];
1264
b4ff3a36 1265 u8 reserved_at_20[0x20];
c0046cf7
SM		 1266};
1267
e281682b 1268struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1269 u8 reserved_at_0[0xa0];
e281682b
SM		 1270
1271 u8 min_time_between_cnps[0x20];
1272
b4ff3a36 1273 u8 reserved_at_c0[0x12];
e281682b 1274 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1275 u8 reserved_at_d8[0x4];
1276 u8 cnp_prio_mode[0x1];
e281682b
SM		 1277 u8 cnp_802p_prio[0x3];
1278
b4ff3a36 1279 u8 reserved_at_e0[0x720];
e281682b
SM		 1280};
1281
1282struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1283 u8 reserved_at_0[0x60];
e281682b 1284
b4ff3a36 1285 u8 reserved_at_60[0x4];
e281682b 1286 u8 clamp_tgt_rate[0x1];
b4ff3a36 1287 u8 reserved_at_65[0x3];
e281682b 1288 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1289 u8 reserved_at_69[0x17];
e281682b 1290
b4ff3a36 1291 u8 reserved_at_80[0x20];
e281682b
SM		 1292
1293 u8 rpg_time_reset[0x20];
1294
1295 u8 rpg_byte_reset[0x20];
1296
1297 u8 rpg_threshold[0x20];
1298
1299 u8 rpg_max_rate[0x20];
1300
1301 u8 rpg_ai_rate[0x20];
1302
1303 u8 rpg_hai_rate[0x20];
1304
1305 u8 rpg_gd[0x20];
1306
1307 u8 rpg_min_dec_fac[0x20];
1308
1309 u8 rpg_min_rate[0x20];
1310
b4ff3a36 1311 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1312
1313 u8 rate_to_set_on_first_cnp[0x20];
1314
1315 u8 dce_tcp_g[0x20];
1316
1317 u8 dce_tcp_rtt[0x20];
1318
1319 u8 rate_reduce_monitor_period[0x20];
1320
b4ff3a36 1321 u8 reserved_at_320[0x20];
e281682b
SM		 1322
1323 u8 initial_alpha_value[0x20];
1324
b4ff3a36 1325 u8 reserved_at_360[0x4a0];
e281682b
SM		 1326};
1327
1328struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1329 u8 reserved_at_0[0x80];
e281682b
SM		 1330
1331 u8 rppp_max_rps[0x20];
1332
1333 u8 rpg_time_reset[0x20];
1334
1335 u8 rpg_byte_reset[0x20];
1336
1337 u8 rpg_threshold[0x20];
1338
1339 u8 rpg_max_rate[0x20];
1340
1341 u8 rpg_ai_rate[0x20];
1342
1343 u8 rpg_hai_rate[0x20];
1344
1345 u8 rpg_gd[0x20];
1346
1347 u8 rpg_min_dec_fac[0x20];
1348
1349 u8 rpg_min_rate[0x20];
1350
b4ff3a36 1351 u8 reserved_at_1c0[0x640];
e281682b
SM		 1352};
1353
1354enum {
1355 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1356 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1357 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1358};
1359
1360struct mlx5_ifc_resize_field_select_bits {
1361 u8 resize_field_select[0x20];
1362};
1363
1364enum {
1365 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1366 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1367 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1368 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1369};
1370
1371struct mlx5_ifc_modify_field_select_bits {
1372 u8 modify_field_select[0x20];
1373};
1374
1375struct mlx5_ifc_field_select_r_roce_np_bits {
1376 u8 field_select_r_roce_np[0x20];
1377};
1378
1379struct mlx5_ifc_field_select_r_roce_rp_bits {
1380 u8 field_select_r_roce_rp[0x20];
1381};
1382
1383enum {
1384 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1385 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1386 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1387 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1388 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1389 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1390 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1391 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1392 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1393 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1394};
1395
1396struct mlx5_ifc_field_select_802_1qau_rp_bits {
1397 u8 field_select_8021qaurp[0x20];
1398};
1399
1400struct mlx5_ifc_phys_layer_cntrs_bits {
1401 u8 time_since_last_clear_high[0x20];
1402
1403 u8 time_since_last_clear_low[0x20];
1404
1405 u8 symbol_errors_high[0x20];
1406
1407 u8 symbol_errors_low[0x20];
1408
1409 u8 sync_headers_errors_high[0x20];
1410
1411 u8 sync_headers_errors_low[0x20];
1412
1413 u8 edpl_bip_errors_lane0_high[0x20];
1414
1415 u8 edpl_bip_errors_lane0_low[0x20];
1416
1417 u8 edpl_bip_errors_lane1_high[0x20];
1418
1419 u8 edpl_bip_errors_lane1_low[0x20];
1420
1421 u8 edpl_bip_errors_lane2_high[0x20];
1422
1423 u8 edpl_bip_errors_lane2_low[0x20];
1424
1425 u8 edpl_bip_errors_lane3_high[0x20];
1426
1427 u8 edpl_bip_errors_lane3_low[0x20];
1428
1429 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1430
1431 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1432
1433 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1434
1435 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1436
1437 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1438
1439 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1440
1441 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1442
1443 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1444
1445 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1446
1447 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1448
1449 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1450
1451 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1452
1453 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1454
1455 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1456
1457 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1458
1459 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1460
1461 u8 rs_fec_corrected_blocks_high[0x20];
1462
1463 u8 rs_fec_corrected_blocks_low[0x20];
1464
1465 u8 rs_fec_uncorrectable_blocks_high[0x20];
1466
1467 u8 rs_fec_uncorrectable_blocks_low[0x20];
1468
1469 u8 rs_fec_no_errors_blocks_high[0x20];
1470
1471 u8 rs_fec_no_errors_blocks_low[0x20];
1472
1473 u8 rs_fec_single_error_blocks_high[0x20];
1474
1475 u8 rs_fec_single_error_blocks_low[0x20];
1476
1477 u8 rs_fec_corrected_symbols_total_high[0x20];
1478
1479 u8 rs_fec_corrected_symbols_total_low[0x20];
1480
1481 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1482
1483 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1484
1485 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1486
1487 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1488
1489 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1490
1491 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1492
1493 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1494
1495 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1496
1497 u8 link_down_events[0x20];
1498
1499 u8 successful_recovery_events[0x20];
1500
b4ff3a36 1501 u8 reserved_at_640[0x180];
e281682b
SM		 1502};
1503
d8dc0508
GP		 1504struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1505 u8 time_since_last_clear_high[0x20];
1506
1507 u8 time_since_last_clear_low[0x20];
1508
1509 u8 phy_received_bits_high[0x20];
1510
1511 u8 phy_received_bits_low[0x20];
1512
1513 u8 phy_symbol_errors_high[0x20];
1514
1515 u8 phy_symbol_errors_low[0x20];
1516
1517 u8 phy_corrected_bits_high[0x20];
1518
1519 u8 phy_corrected_bits_low[0x20];
1520
1521 u8 phy_corrected_bits_lane0_high[0x20];
1522
1523 u8 phy_corrected_bits_lane0_low[0x20];
1524
1525 u8 phy_corrected_bits_lane1_high[0x20];
1526
1527 u8 phy_corrected_bits_lane1_low[0x20];
1528
1529 u8 phy_corrected_bits_lane2_high[0x20];
1530
1531 u8 phy_corrected_bits_lane2_low[0x20];
1532
1533 u8 phy_corrected_bits_lane3_high[0x20];
1534
1535 u8 phy_corrected_bits_lane3_low[0x20];
1536
1537 u8 reserved_at_200[0x5c0];
1538};
1539
1c64bf6f
MY		 1540struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1541 u8 symbol_error_counter[0x10];
1542
1543 u8 link_error_recovery_counter[0x8];
1544
1545 u8 link_downed_counter[0x8];
1546
1547 u8 port_rcv_errors[0x10];
1548
1549 u8 port_rcv_remote_physical_errors[0x10];
1550
1551 u8 port_rcv_switch_relay_errors[0x10];
1552
1553 u8 port_xmit_discards[0x10];
1554
1555 u8 port_xmit_constraint_errors[0x8];
1556
1557 u8 port_rcv_constraint_errors[0x8];
1558
1559 u8 reserved_at_70[0x8];
1560
1561 u8 link_overrun_errors[0x8];
1562
1563 u8 reserved_at_80[0x10];
1564
1565 u8 vl_15_dropped[0x10];
1566
133bea04
TW		 1567 u8 reserved_at_a0[0x80];
1568
1569 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1570};
1571
e281682b
SM		 1572struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1573 u8 transmit_queue_high[0x20];
1574
1575 u8 transmit_queue_low[0x20];
1576
b4ff3a36 1577 u8 reserved_at_40[0x780];
e281682b
SM		 1578};
1579
1580struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1581 u8 rx_octets_high[0x20];
1582
1583 u8 rx_octets_low[0x20];
1584
b4ff3a36 1585 u8 reserved_at_40[0xc0];
e281682b
SM		 1586
1587 u8 rx_frames_high[0x20];
1588
1589 u8 rx_frames_low[0x20];
1590
1591 u8 tx_octets_high[0x20];
1592
1593 u8 tx_octets_low[0x20];
1594
b4ff3a36 1595 u8 reserved_at_180[0xc0];
e281682b
SM		 1596
1597 u8 tx_frames_high[0x20];
1598
1599 u8 tx_frames_low[0x20];
1600
1601 u8 rx_pause_high[0x20];
1602
1603 u8 rx_pause_low[0x20];
1604
1605 u8 rx_pause_duration_high[0x20];
1606
1607 u8 rx_pause_duration_low[0x20];
1608
1609 u8 tx_pause_high[0x20];
1610
1611 u8 tx_pause_low[0x20];
1612
1613 u8 tx_pause_duration_high[0x20];
1614
1615 u8 tx_pause_duration_low[0x20];
1616
1617 u8 rx_pause_transition_high[0x20];
1618
1619 u8 rx_pause_transition_low[0x20];
1620
2fcb12df
IK		 1621 u8 reserved_at_3c0[0x40];
1622
1623 u8 device_stall_minor_watermark_cnt_high[0x20];
1624
1625 u8 device_stall_minor_watermark_cnt_low[0x20];
1626
1627 u8 device_stall_critical_watermark_cnt_high[0x20];
1628
1629 u8 device_stall_critical_watermark_cnt_low[0x20];
1630
1631 u8 reserved_at_480[0x340];
e281682b
SM		 1632};
1633
1634struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1635 u8 port_transmit_wait_high[0x20];
1636
1637 u8 port_transmit_wait_low[0x20];
1638
2dba0797
GP		 1639 u8 reserved_at_40[0x100];
1640
1641 u8 rx_buffer_almost_full_high[0x20];
1642
1643 u8 rx_buffer_almost_full_low[0x20];
1644
1645 u8 rx_buffer_full_high[0x20];
1646
1647 u8 rx_buffer_full_low[0x20];
1648
1649 u8 reserved_at_1c0[0x600];
e281682b
SM		 1650};
1651
1652struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1653 u8 dot3stats_alignment_errors_high[0x20];
1654
1655 u8 dot3stats_alignment_errors_low[0x20];
1656
1657 u8 dot3stats_fcs_errors_high[0x20];
1658
1659 u8 dot3stats_fcs_errors_low[0x20];
1660
1661 u8 dot3stats_single_collision_frames_high[0x20];
1662
1663 u8 dot3stats_single_collision_frames_low[0x20];
1664
1665 u8 dot3stats_multiple_collision_frames_high[0x20];
1666
1667 u8 dot3stats_multiple_collision_frames_low[0x20];
1668
1669 u8 dot3stats_sqe_test_errors_high[0x20];
1670
1671 u8 dot3stats_sqe_test_errors_low[0x20];
1672
1673 u8 dot3stats_deferred_transmissions_high[0x20];
1674
1675 u8 dot3stats_deferred_transmissions_low[0x20];
1676
1677 u8 dot3stats_late_collisions_high[0x20];
1678
1679 u8 dot3stats_late_collisions_low[0x20];
1680
1681 u8 dot3stats_excessive_collisions_high[0x20];
1682
1683 u8 dot3stats_excessive_collisions_low[0x20];
1684
1685 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1686
1687 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1688
1689 u8 dot3stats_carrier_sense_errors_high[0x20];
1690
1691 u8 dot3stats_carrier_sense_errors_low[0x20];
1692
1693 u8 dot3stats_frame_too_longs_high[0x20];
1694
1695 u8 dot3stats_frame_too_longs_low[0x20];
1696
1697 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1698
1699 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1700
1701 u8 dot3stats_symbol_errors_high[0x20];
1702
1703 u8 dot3stats_symbol_errors_low[0x20];
1704
1705 u8 dot3control_in_unknown_opcodes_high[0x20];
1706
1707 u8 dot3control_in_unknown_opcodes_low[0x20];
1708
1709 u8 dot3in_pause_frames_high[0x20];
1710
1711 u8 dot3in_pause_frames_low[0x20];
1712
1713 u8 dot3out_pause_frames_high[0x20];
1714
1715 u8 dot3out_pause_frames_low[0x20];
1716
b4ff3a36 1717 u8 reserved_at_400[0x3c0];
e281682b
SM		 1718};
1719
1720struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1721 u8 ether_stats_drop_events_high[0x20];
1722
1723 u8 ether_stats_drop_events_low[0x20];
1724
1725 u8 ether_stats_octets_high[0x20];
1726
1727 u8 ether_stats_octets_low[0x20];
1728
1729 u8 ether_stats_pkts_high[0x20];
1730
1731 u8 ether_stats_pkts_low[0x20];
1732
1733 u8 ether_stats_broadcast_pkts_high[0x20];
1734
1735 u8 ether_stats_broadcast_pkts_low[0x20];
1736
1737 u8 ether_stats_multicast_pkts_high[0x20];
1738
1739 u8 ether_stats_multicast_pkts_low[0x20];
1740
1741 u8 ether_stats_crc_align_errors_high[0x20];
1742
1743 u8 ether_stats_crc_align_errors_low[0x20];
1744
1745 u8 ether_stats_undersize_pkts_high[0x20];
1746
1747 u8 ether_stats_undersize_pkts_low[0x20];
1748
1749 u8 ether_stats_oversize_pkts_high[0x20];
1750
1751 u8 ether_stats_oversize_pkts_low[0x20];
1752
1753 u8 ether_stats_fragments_high[0x20];
1754
1755 u8 ether_stats_fragments_low[0x20];
1756
1757 u8 ether_stats_jabbers_high[0x20];
1758
1759 u8 ether_stats_jabbers_low[0x20];
1760
1761 u8 ether_stats_collisions_high[0x20];
1762
1763 u8 ether_stats_collisions_low[0x20];
1764
1765 u8 ether_stats_pkts64octets_high[0x20];
1766
1767 u8 ether_stats_pkts64octets_low[0x20];
1768
1769 u8 ether_stats_pkts65to127octets_high[0x20];
1770
1771 u8 ether_stats_pkts65to127octets_low[0x20];
1772
1773 u8 ether_stats_pkts128to255octets_high[0x20];
1774
1775 u8 ether_stats_pkts128to255octets_low[0x20];
1776
1777 u8 ether_stats_pkts256to511octets_high[0x20];
1778
1779 u8 ether_stats_pkts256to511octets_low[0x20];
1780
1781 u8 ether_stats_pkts512to1023octets_high[0x20];
1782
1783 u8 ether_stats_pkts512to1023octets_low[0x20];
1784
1785 u8 ether_stats_pkts1024to1518octets_high[0x20];
1786
1787 u8 ether_stats_pkts1024to1518octets_low[0x20];
1788
1789 u8 ether_stats_pkts1519to2047octets_high[0x20];
1790
1791 u8 ether_stats_pkts1519to2047octets_low[0x20];
1792
1793 u8 ether_stats_pkts2048to4095octets_high[0x20];
1794
1795 u8 ether_stats_pkts2048to4095octets_low[0x20];
1796
1797 u8 ether_stats_pkts4096to8191octets_high[0x20];
1798
1799 u8 ether_stats_pkts4096to8191octets_low[0x20];
1800
1801 u8 ether_stats_pkts8192to10239octets_high[0x20];
1802
1803 u8 ether_stats_pkts8192to10239octets_low[0x20];
1804
b4ff3a36 1805 u8 reserved_at_540[0x280];
e281682b
SM		 1806};
1807
1808struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1809 u8 if_in_octets_high[0x20];
1810
1811 u8 if_in_octets_low[0x20];
1812
1813 u8 if_in_ucast_pkts_high[0x20];
1814
1815 u8 if_in_ucast_pkts_low[0x20];
1816
1817 u8 if_in_discards_high[0x20];
1818
1819 u8 if_in_discards_low[0x20];
1820
1821 u8 if_in_errors_high[0x20];
1822
1823 u8 if_in_errors_low[0x20];
1824
1825 u8 if_in_unknown_protos_high[0x20];
1826
1827 u8 if_in_unknown_protos_low[0x20];
1828
1829 u8 if_out_octets_high[0x20];
1830
1831 u8 if_out_octets_low[0x20];
1832
1833 u8 if_out_ucast_pkts_high[0x20];
1834
1835 u8 if_out_ucast_pkts_low[0x20];
1836
1837 u8 if_out_discards_high[0x20];
1838
1839 u8 if_out_discards_low[0x20];
1840
1841 u8 if_out_errors_high[0x20];
1842
1843 u8 if_out_errors_low[0x20];
1844
1845 u8 if_in_multicast_pkts_high[0x20];
1846
1847 u8 if_in_multicast_pkts_low[0x20];
1848
1849 u8 if_in_broadcast_pkts_high[0x20];
1850
1851 u8 if_in_broadcast_pkts_low[0x20];
1852
1853 u8 if_out_multicast_pkts_high[0x20];
1854
1855 u8 if_out_multicast_pkts_low[0x20];
1856
1857 u8 if_out_broadcast_pkts_high[0x20];
1858
1859 u8 if_out_broadcast_pkts_low[0x20];
1860
b4ff3a36 1861 u8 reserved_at_340[0x480];
e281682b
SM		 1862};
1863
1864struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1865 u8 a_frames_transmitted_ok_high[0x20];
1866
1867 u8 a_frames_transmitted_ok_low[0x20];
1868
1869 u8 a_frames_received_ok_high[0x20];
1870
1871 u8 a_frames_received_ok_low[0x20];
1872
1873 u8 a_frame_check_sequence_errors_high[0x20];
1874
1875 u8 a_frame_check_sequence_errors_low[0x20];
1876
1877 u8 a_alignment_errors_high[0x20];
1878
1879 u8 a_alignment_errors_low[0x20];
1880
1881 u8 a_octets_transmitted_ok_high[0x20];
1882
1883 u8 a_octets_transmitted_ok_low[0x20];
1884
1885 u8 a_octets_received_ok_high[0x20];
1886
1887 u8 a_octets_received_ok_low[0x20];
1888
1889 u8 a_multicast_frames_xmitted_ok_high[0x20];
1890
1891 u8 a_multicast_frames_xmitted_ok_low[0x20];
1892
1893 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1894
1895 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1896
1897 u8 a_multicast_frames_received_ok_high[0x20];
1898
1899 u8 a_multicast_frames_received_ok_low[0x20];
1900
1901 u8 a_broadcast_frames_received_ok_high[0x20];
1902
1903 u8 a_broadcast_frames_received_ok_low[0x20];
1904
1905 u8 a_in_range_length_errors_high[0x20];
1906
1907 u8 a_in_range_length_errors_low[0x20];
1908
1909 u8 a_out_of_range_length_field_high[0x20];
1910
1911 u8 a_out_of_range_length_field_low[0x20];
1912
1913 u8 a_frame_too_long_errors_high[0x20];
1914
1915 u8 a_frame_too_long_errors_low[0x20];
1916
1917 u8 a_symbol_error_during_carrier_high[0x20];
1918
1919 u8 a_symbol_error_during_carrier_low[0x20];
1920
1921 u8 a_mac_control_frames_transmitted_high[0x20];
1922
1923 u8 a_mac_control_frames_transmitted_low[0x20];
1924
1925 u8 a_mac_control_frames_received_high[0x20];
1926
1927 u8 a_mac_control_frames_received_low[0x20];
1928
1929 u8 a_unsupported_opcodes_received_high[0x20];
1930
1931 u8 a_unsupported_opcodes_received_low[0x20];
1932
1933 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1934
1935 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1936
1937 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1938
1939 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1940
b4ff3a36 1941 u8 reserved_at_4c0[0x300];
e281682b
SM		 1942};
1943
8ed1a630
GP		 1944struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1945 u8 life_time_counter_high[0x20];
1946
1947 u8 life_time_counter_low[0x20];
1948
1949 u8 rx_errors[0x20];
1950
1951 u8 tx_errors[0x20];
1952
1953 u8 l0_to_recovery_eieos[0x20];
1954
1955 u8 l0_to_recovery_ts[0x20];
1956
1957 u8 l0_to_recovery_framing[0x20];
1958
1959 u8 l0_to_recovery_retrain[0x20];
1960
1961 u8 crc_error_dllp[0x20];
1962
1963 u8 crc_error_tlp[0x20];
1964
efae7f78
EBE		 1965 u8 tx_overflow_buffer_pkt_high[0x20];
1966
1967 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 1968
1969 u8 outbound_stalled_reads[0x20];
1970
1971 u8 outbound_stalled_writes[0x20];
1972
1973 u8 outbound_stalled_reads_events[0x20];
1974
1975 u8 outbound_stalled_writes_events[0x20];
1976
1977 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 1978};
1979
e281682b
SM		 1980struct mlx5_ifc_cmd_inter_comp_event_bits {
1981 u8 command_completion_vector[0x20];
1982
b4ff3a36 1983 u8 reserved_at_20[0xc0];
e281682b
SM		 1984};
1985
1986struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1987 u8 reserved_at_0[0x18];
e281682b 1988 u8 port_num[0x1];
b4ff3a36 1989 u8 reserved_at_19[0x3];
e281682b
SM		 1990 u8 vl[0x4];
1991
b4ff3a36 1992 u8 reserved_at_20[0xa0];
e281682b
SM		 1993};
1994
1995struct mlx5_ifc_db_bf_congestion_event_bits {
1996 u8 event_subtype[0x8];
b4ff3a36 1997 u8 reserved_at_8[0x8];
e281682b 1998 u8 congestion_level[0x8];
b4ff3a36 1999 u8 reserved_at_18[0x8];
e281682b 2000
b4ff3a36 2001 u8 reserved_at_20[0xa0];
e281682b
SM		 2002};
2003
2004struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2005 u8 reserved_at_0[0x60];
e281682b
SM		 2006
2007 u8 gpio_event_hi[0x20];
2008
2009 u8 gpio_event_lo[0x20];
2010
b4ff3a36 2011 u8 reserved_at_a0[0x40];
e281682b
SM		 2012};
2013
2014struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2015 u8 reserved_at_0[0x40];
e281682b
SM		 2016
2017 u8 port_num[0x4];
b4ff3a36 2018 u8 reserved_at_44[0x1c];
e281682b 2019
b4ff3a36 2020 u8 reserved_at_60[0x80];
e281682b
SM		 2021};
2022
2023struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2024 u8 reserved_at_0[0xe0];
e281682b
SM		 2025};
2026
2027enum {
2028 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2029 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2030};
2031
2032struct mlx5_ifc_cq_error_bits {
b4ff3a36 2033 u8 reserved_at_0[0x8];
e281682b
SM		 2034 u8 cqn[0x18];
2035
b4ff3a36 2036 u8 reserved_at_20[0x20];
e281682b 2037
b4ff3a36 2038 u8 reserved_at_40[0x18];
e281682b
SM		 2039 u8 syndrome[0x8];
2040
b4ff3a36 2041 u8 reserved_at_60[0x80];
e281682b
SM		 2042};
2043
2044struct mlx5_ifc_rdma_page_fault_event_bits {
2045 u8 bytes_committed[0x20];
2046
2047 u8 r_key[0x20];
2048
b4ff3a36 2049 u8 reserved_at_40[0x10];
e281682b
SM		 2050 u8 packet_len[0x10];
2051
2052 u8 rdma_op_len[0x20];
2053
2054 u8 rdma_va[0x40];
2055
b4ff3a36 2056 u8 reserved_at_c0[0x5];
e281682b
SM		 2057 u8 rdma[0x1];
2058 u8 write[0x1];
2059 u8 requestor[0x1];
2060 u8 qp_number[0x18];
2061};
2062
2063struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2064 u8 bytes_committed[0x20];
2065
b4ff3a36 2066 u8 reserved_at_20[0x10];
e281682b
SM		 2067 u8 wqe_index[0x10];
2068
b4ff3a36 2069 u8 reserved_at_40[0x10];
e281682b
SM		 2070 u8 len[0x10];
2071
b4ff3a36 2072 u8 reserved_at_60[0x60];
e281682b 2073
b4ff3a36 2074 u8 reserved_at_c0[0x5];
e281682b
SM		 2075 u8 rdma[0x1];
2076 u8 write_read[0x1];
2077 u8 requestor[0x1];
2078 u8 qpn[0x18];
2079};
2080
2081struct mlx5_ifc_qp_events_bits {
b4ff3a36 2082 u8 reserved_at_0[0xa0];
e281682b
SM		 2083
2084 u8 type[0x8];
b4ff3a36 2085 u8 reserved_at_a8[0x18];
e281682b 2086
b4ff3a36 2087 u8 reserved_at_c0[0x8];
e281682b
SM		 2088 u8 qpn_rqn_sqn[0x18];
2089};
2090
2091struct mlx5_ifc_dct_events_bits {
b4ff3a36 2092 u8 reserved_at_0[0xc0];
e281682b 2093
b4ff3a36 2094 u8 reserved_at_c0[0x8];
e281682b
SM		 2095 u8 dct_number[0x18];
2096};
2097
2098struct mlx5_ifc_comp_event_bits {
b4ff3a36 2099 u8 reserved_at_0[0xc0];
e281682b 2100
b4ff3a36 2101 u8 reserved_at_c0[0x8];
e281682b
SM		 2102 u8 cq_number[0x18];
2103};
2104
2105enum {
2106 MLX5_QPC_STATE_RST = 0x0,
2107 MLX5_QPC_STATE_INIT = 0x1,
2108 MLX5_QPC_STATE_RTR = 0x2,
2109 MLX5_QPC_STATE_RTS = 0x3,
2110 MLX5_QPC_STATE_SQER = 0x4,
2111 MLX5_QPC_STATE_ERR = 0x6,
2112 MLX5_QPC_STATE_SQD = 0x7,
2113 MLX5_QPC_STATE_SUSPENDED = 0x9,
2114};
2115
2116enum {
2117 MLX5_QPC_ST_RC = 0x0,
2118 MLX5_QPC_ST_UC = 0x1,
2119 MLX5_QPC_ST_UD = 0x2,
2120 MLX5_QPC_ST_XRC = 0x3,
2121 MLX5_QPC_ST_DCI = 0x5,
2122 MLX5_QPC_ST_QP0 = 0x7,
2123 MLX5_QPC_ST_QP1 = 0x8,
2124 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2125 MLX5_QPC_ST_REG_UMR = 0xc,
2126};
2127
2128enum {
2129 MLX5_QPC_PM_STATE_ARMED = 0x0,
2130 MLX5_QPC_PM_STATE_REARM = 0x1,
2131 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2132 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2133};
2134
6e44636a
AK		 2135enum {
2136 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2137};
2138
e281682b
SM		 2139enum {
2140 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2141 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2142};
2143
2144enum {
2145 MLX5_QPC_MTU_256_BYTES = 0x1,
2146 MLX5_QPC_MTU_512_BYTES = 0x2,
2147 MLX5_QPC_MTU_1K_BYTES = 0x3,
2148 MLX5_QPC_MTU_2K_BYTES = 0x4,
2149 MLX5_QPC_MTU_4K_BYTES = 0x5,
2150 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2151};
2152
2153enum {
2154 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2155 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2156 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2157 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2158 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2159 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2160 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2161 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2162};
2163
2164enum {
2165 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2166 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2167 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2168};
2169
2170enum {
2171 MLX5_QPC_CS_RES_DISABLE = 0x0,
2172 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2173 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2174};
2175
2176struct mlx5_ifc_qpc_bits {
2177 u8 state[0x4];
84df61eb 2178 u8 lag_tx_port_affinity[0x4];
e281682b 2179 u8 st[0x8];
b4ff3a36 2180 u8 reserved_at_10[0x3];
e281682b 2181 u8 pm_state[0x2];
6e44636a
AK		 2182 u8 reserved_at_15[0x3];
2183 u8 offload_type[0x4];
e281682b 2184 u8 end_padding_mode[0x2];
b4ff3a36 2185 u8 reserved_at_1e[0x2];
e281682b
SM		 2186
2187 u8 wq_signature[0x1];
2188 u8 block_lb_mc[0x1];
2189 u8 atomic_like_write_en[0x1];
2190 u8 latency_sensitive[0x1];
b4ff3a36 2191 u8 reserved_at_24[0x1];
e281682b 2192 u8 drain_sigerr[0x1];
b4ff3a36 2193 u8 reserved_at_26[0x2];
e281682b
SM		 2194 u8 pd[0x18];
2195
2196 u8 mtu[0x3];
2197 u8 log_msg_max[0x5];
b4ff3a36 2198 u8 reserved_at_48[0x1];
e281682b
SM		 2199 u8 log_rq_size[0x4];
2200 u8 log_rq_stride[0x3];
2201 u8 no_sq[0x1];
2202 u8 log_sq_size[0x4];
b4ff3a36 2203 u8 reserved_at_55[0x6];
e281682b 2204 u8 rlky[0x1];
1015c2e8 2205 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2206
2207 u8 counter_set_id[0x8];
2208 u8 uar_page[0x18];
2209
b4ff3a36 2210 u8 reserved_at_80[0x8];
e281682b
SM		 2211 u8 user_index[0x18];
2212
b4ff3a36 2213 u8 reserved_at_a0[0x3];
e281682b
SM		 2214 u8 log_page_size[0x5];
2215 u8 remote_qpn[0x18];
2216
2217 struct mlx5_ifc_ads_bits primary_address_path;
2218
2219 struct mlx5_ifc_ads_bits secondary_address_path;
2220
2221 u8 log_ack_req_freq[0x4];
b4ff3a36 2222 u8 reserved_at_384[0x4];
e281682b 2223 u8 log_sra_max[0x3];
b4ff3a36 2224 u8 reserved_at_38b[0x2];
e281682b
SM		 2225 u8 retry_count[0x3];
2226 u8 rnr_retry[0x3];
b4ff3a36 2227 u8 reserved_at_393[0x1];
e281682b
SM		 2228 u8 fre[0x1];
2229 u8 cur_rnr_retry[0x3];
2230 u8 cur_retry_count[0x3];
b4ff3a36 2231 u8 reserved_at_39b[0x5];
e281682b 2232
b4ff3a36 2233 u8 reserved_at_3a0[0x20];
e281682b 2234
b4ff3a36 2235 u8 reserved_at_3c0[0x8];
e281682b
SM		 2236 u8 next_send_psn[0x18];
2237
b4ff3a36 2238 u8 reserved_at_3e0[0x8];
e281682b
SM		 2239 u8 cqn_snd[0x18];
2240
09a7d9ec
SM		 2241 u8 reserved_at_400[0x8];
2242 u8 deth_sqpn[0x18];
2243
2244 u8 reserved_at_420[0x20];
e281682b 2245
b4ff3a36 2246 u8 reserved_at_440[0x8];
e281682b
SM		 2247 u8 last_acked_psn[0x18];
2248
b4ff3a36 2249 u8 reserved_at_460[0x8];
e281682b
SM		 2250 u8 ssn[0x18];
2251
b4ff3a36 2252 u8 reserved_at_480[0x8];
e281682b 2253 u8 log_rra_max[0x3];
b4ff3a36 2254 u8 reserved_at_48b[0x1];
e281682b
SM		 2255 u8 atomic_mode[0x4];
2256 u8 rre[0x1];
2257 u8 rwe[0x1];
2258 u8 rae[0x1];
b4ff3a36 2259 u8 reserved_at_493[0x1];
e281682b 2260 u8 page_offset[0x6];
b4ff3a36 2261 u8 reserved_at_49a[0x3];
e281682b
SM		 2262 u8 cd_slave_receive[0x1];
2263 u8 cd_slave_send[0x1];
2264 u8 cd_master[0x1];
2265
b4ff3a36 2266 u8 reserved_at_4a0[0x3];
e281682b
SM		 2267 u8 min_rnr_nak[0x5];
2268 u8 next_rcv_psn[0x18];
2269
b4ff3a36 2270 u8 reserved_at_4c0[0x8];
e281682b
SM		 2271 u8 xrcd[0x18];
2272
b4ff3a36 2273 u8 reserved_at_4e0[0x8];
e281682b
SM		 2274 u8 cqn_rcv[0x18];
2275
2276 u8 dbr_addr[0x40];
2277
2278 u8 q_key[0x20];
2279
b4ff3a36 2280 u8 reserved_at_560[0x5];
e281682b 2281 u8 rq_type[0x3];
7486216b 2282 u8 srqn_rmpn_xrqn[0x18];
e281682b 2283
b4ff3a36 2284 u8 reserved_at_580[0x8];
e281682b
SM		 2285 u8 rmsn[0x18];
2286
2287 u8 hw_sq_wqebb_counter[0x10];
2288 u8 sw_sq_wqebb_counter[0x10];
2289
2290 u8 hw_rq_counter[0x20];
2291
2292 u8 sw_rq_counter[0x20];
2293
b4ff3a36 2294 u8 reserved_at_600[0x20];
e281682b 2295
b4ff3a36 2296 u8 reserved_at_620[0xf];
e281682b
SM		 2297 u8 cgs[0x1];
2298 u8 cs_req[0x8];
2299 u8 cs_res[0x8];
2300
2301 u8 dc_access_key[0x40];
2302
b4ff3a36 2303 u8 reserved_at_680[0xc0];
e281682b
SM		 2304};
2305
2306struct mlx5_ifc_roce_addr_layout_bits {
2307 u8 source_l3_address[16][0x8];
2308
b4ff3a36 2309 u8 reserved_at_80[0x3];
e281682b
SM		 2310 u8 vlan_valid[0x1];
2311 u8 vlan_id[0xc];
2312 u8 source_mac_47_32[0x10];
2313
2314 u8 source_mac_31_0[0x20];
2315
b4ff3a36 2316 u8 reserved_at_c0[0x14];
e281682b
SM		 2317 u8 roce_l3_type[0x4];
2318 u8 roce_version[0x8];
2319
b4ff3a36 2320 u8 reserved_at_e0[0x20];
e281682b
SM		 2321};
2322
2323union mlx5_ifc_hca_cap_union_bits {
2324 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2325 struct mlx5_ifc_odp_cap_bits odp_cap;
2326 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2327 struct mlx5_ifc_roce_cap_bits roce_cap;
2328 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2329 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2330 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2331 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2332 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2333 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2334 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2335 u8 reserved_at_0[0x8000];
e281682b
SM		 2336};
2337
2338enum {
2339 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2340 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2341 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2342 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2343 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2344 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2345 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2346 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2347 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2348};
2349
2350struct mlx5_ifc_vlan_bits {
2351 u8 ethtype[0x10];
2352 u8 prio[0x3];
2353 u8 cfi[0x1];
2354 u8 vid[0xc];
e281682b
SM		 2355};
2356
2357struct mlx5_ifc_flow_context_bits {
0c06897a 2358 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2359
2360 u8 group_id[0x20];
2361
b4ff3a36 2362 u8 reserved_at_40[0x8];
e281682b
SM		 2363 u8 flow_tag[0x18];
2364
b4ff3a36 2365 u8 reserved_at_60[0x10];
e281682b
SM		 2366 u8 action[0x10];
2367
b4ff3a36 2368 u8 reserved_at_80[0x8];
e281682b
SM		 2369 u8 destination_list_size[0x18];
2370
9dc0b289
AV		 2371 u8 reserved_at_a0[0x8];
2372 u8 flow_counter_list_size[0x18];
2373
7adbde20
HHZ		 2374 u8 encap_id[0x20];
2375
2a69cb9f
OG		 2376 u8 modify_header_id[0x20];
2377
2378 u8 reserved_at_100[0x100];
e281682b
SM		 2379
2380 struct mlx5_ifc_fte_match_param_bits match_value;
2381
b4ff3a36 2382 u8 reserved_at_1200[0x600];
e281682b 2383
9dc0b289 2384 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2385};
2386
2387enum {
2388 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2389 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2390};
2391
2392struct mlx5_ifc_xrc_srqc_bits {
2393 u8 state[0x4];
2394 u8 log_xrc_srq_size[0x4];
b4ff3a36 2395 u8 reserved_at_8[0x18];
e281682b
SM		 2396
2397 u8 wq_signature[0x1];
2398 u8 cont_srq[0x1];
b4ff3a36 2399 u8 reserved_at_22[0x1];
e281682b
SM		 2400 u8 rlky[0x1];
2401 u8 basic_cyclic_rcv_wqe[0x1];
2402 u8 log_rq_stride[0x3];
2403 u8 xrcd[0x18];
2404
2405 u8 page_offset[0x6];
b4ff3a36 2406 u8 reserved_at_46[0x2];
e281682b
SM		 2407 u8 cqn[0x18];
2408
b4ff3a36 2409 u8 reserved_at_60[0x20];
e281682b
SM		 2410
2411 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2412 u8 reserved_at_81[0x1];
e281682b
SM		 2413 u8 log_page_size[0x6];
2414 u8 user_index[0x18];
2415
b4ff3a36 2416 u8 reserved_at_a0[0x20];
e281682b 2417
b4ff3a36 2418 u8 reserved_at_c0[0x8];
e281682b
SM		 2419 u8 pd[0x18];
2420
2421 u8 lwm[0x10];
2422 u8 wqe_cnt[0x10];
2423
b4ff3a36 2424 u8 reserved_at_100[0x40];
e281682b
SM		 2425
2426 u8 db_record_addr_h[0x20];
2427
2428 u8 db_record_addr_l[0x1e];
b4ff3a36 2429 u8 reserved_at_17e[0x2];
e281682b 2430
b4ff3a36 2431 u8 reserved_at_180[0x80];
e281682b
SM		 2432};
2433
61c5b5c9
MS		 2434struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2435 u8 counter_error_queues[0x20];
2436
2437 u8 total_error_queues[0x20];
2438
2439 u8 send_queue_priority_update_flow[0x20];
2440
2441 u8 reserved_at_60[0x20];
2442
2443 u8 nic_receive_steering_discard[0x40];
2444
2445 u8 receive_discard_vport_down[0x40];
2446
2447 u8 transmit_discard_vport_down[0x40];
2448
2449 u8 reserved_at_140[0xec0];
2450};
2451
e281682b
SM		 2452struct mlx5_ifc_traffic_counter_bits {
2453 u8 packets[0x40];
2454
2455 u8 octets[0x40];
2456};
2457
2458struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2459 u8 strict_lag_tx_port_affinity[0x1];
2460 u8 reserved_at_1[0x3];
2461 u8 lag_tx_port_affinity[0x04];
2462
2463 u8 reserved_at_8[0x4];
e281682b 2464 u8 prio[0x4];
b4ff3a36 2465 u8 reserved_at_10[0x10];
e281682b 2466
b4ff3a36 2467 u8 reserved_at_20[0x100];
e281682b 2468
b4ff3a36 2469 u8 reserved_at_120[0x8];
e281682b
SM		 2470 u8 transport_domain[0x18];
2471
500a3d0d
ES		 2472 u8 reserved_at_140[0x8];
2473 u8 underlay_qpn[0x18];
2474 u8 reserved_at_160[0x3a0];
e281682b
SM		 2475};
2476
2477enum {
2478 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2479 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2480};
2481
2482enum {
2483 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2484 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2485};
2486
2487enum {
2be6967c
SM		 2488 MLX5_RX_HASH_FN_NONE = 0x0,
2489 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2490 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2491};
2492
2493enum {
2494 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2495 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2496};
2497
2498struct mlx5_ifc_tirc_bits {
b4ff3a36 2499 u8 reserved_at_0[0x20];
e281682b
SM		 2500
2501 u8 disp_type[0x4];
b4ff3a36 2502 u8 reserved_at_24[0x1c];
e281682b 2503
b4ff3a36 2504 u8 reserved_at_40[0x40];
e281682b 2505
b4ff3a36 2506 u8 reserved_at_80[0x4];
e281682b
SM		 2507 u8 lro_timeout_period_usecs[0x10];
2508 u8 lro_enable_mask[0x4];
2509 u8 lro_max_ip_payload_size[0x8];
2510
b4ff3a36 2511 u8 reserved_at_a0[0x40];
e281682b 2512
b4ff3a36 2513 u8 reserved_at_e0[0x8];
e281682b
SM		 2514 u8 inline_rqn[0x18];
2515
2516 u8 rx_hash_symmetric[0x1];
b4ff3a36 2517 u8 reserved_at_101[0x1];
e281682b 2518 u8 tunneled_offload_en[0x1];
b4ff3a36 2519 u8 reserved_at_103[0x5];
e281682b
SM		 2520 u8 indirect_table[0x18];
2521
2522 u8 rx_hash_fn[0x4];
b4ff3a36 2523 u8 reserved_at_124[0x2];
e281682b
SM		 2524 u8 self_lb_block[0x2];
2525 u8 transport_domain[0x18];
2526
2527 u8 rx_hash_toeplitz_key[10][0x20];
2528
2529 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2530
2531 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2532
b4ff3a36 2533 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2534};
2535
2536enum {
2537 MLX5_SRQC_STATE_GOOD = 0x0,
2538 MLX5_SRQC_STATE_ERROR = 0x1,
2539};
2540
2541struct mlx5_ifc_srqc_bits {
2542 u8 state[0x4];
2543 u8 log_srq_size[0x4];
b4ff3a36 2544 u8 reserved_at_8[0x18];
e281682b
SM		 2545
2546 u8 wq_signature[0x1];
2547 u8 cont_srq[0x1];
b4ff3a36 2548 u8 reserved_at_22[0x1];
e281682b 2549 u8 rlky[0x1];
b4ff3a36 2550 u8 reserved_at_24[0x1];
e281682b
SM		 2551 u8 log_rq_stride[0x3];
2552 u8 xrcd[0x18];
2553
2554 u8 page_offset[0x6];
b4ff3a36 2555 u8 reserved_at_46[0x2];
e281682b
SM		 2556 u8 cqn[0x18];
2557
b4ff3a36 2558 u8 reserved_at_60[0x20];
e281682b 2559
b4ff3a36 2560 u8 reserved_at_80[0x2];
e281682b 2561 u8 log_page_size[0x6];
b4ff3a36 2562 u8 reserved_at_88[0x18];
e281682b 2563
b4ff3a36 2564 u8 reserved_at_a0[0x20];
e281682b 2565
b4ff3a36 2566 u8 reserved_at_c0[0x8];
e281682b
SM		 2567 u8 pd[0x18];
2568
2569 u8 lwm[0x10];
2570 u8 wqe_cnt[0x10];
2571
b4ff3a36 2572 u8 reserved_at_100[0x40];
e281682b 2573
01949d01 2574 u8 dbr_addr[0x40];
e281682b 2575
b4ff3a36 2576 u8 reserved_at_180[0x80];
e281682b
SM		 2577};
2578
2579enum {
2580 MLX5_SQC_STATE_RST = 0x0,
2581 MLX5_SQC_STATE_RDY = 0x1,
2582 MLX5_SQC_STATE_ERR = 0x3,
2583};
2584
2585struct mlx5_ifc_sqc_bits {
2586 u8 rlky[0x1];
2587 u8 cd_master[0x1];
2588 u8 fre[0x1];
2589 u8 flush_in_error_en[0x1];
795b609c 2590 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2591 u8 min_wqe_inline_mode[0x3];
e281682b 2592 u8 state[0x4];
7d5e1423 2593 u8 reg_umr[0x1];
547eede0 2594 u8 allow_swp[0x1];
40817cdb
OG		 2595 u8 hairpin[0x1];
2596 u8 reserved_at_f[0x11];
e281682b 2597
b4ff3a36 2598 u8 reserved_at_20[0x8];
e281682b
SM		 2599 u8 user_index[0x18];
2600
b4ff3a36 2601 u8 reserved_at_40[0x8];
e281682b
SM		 2602 u8 cqn[0x18];
2603
40817cdb
OG		 2604 u8 reserved_at_60[0x8];
2605 u8 hairpin_peer_rq[0x18];
2606
2607 u8 reserved_at_80[0x10];
2608 u8 hairpin_peer_vhca[0x10];
2609
2610 u8 reserved_at_a0[0x50];
e281682b 2611
7486216b 2612 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2613 u8 tis_lst_sz[0x10];
b4ff3a36 2614 u8 reserved_at_110[0x10];
e281682b 2615
b4ff3a36 2616 u8 reserved_at_120[0x40];
e281682b 2617
b4ff3a36 2618 u8 reserved_at_160[0x8];
e281682b
SM		 2619 u8 tis_num_0[0x18];
2620
2621 struct mlx5_ifc_wq_bits wq;
2622};
2623
813f8540
MHY		 2624enum {
2625 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2626 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2627 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2628 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2629};
2630
2631struct mlx5_ifc_scheduling_context_bits {
2632 u8 element_type[0x8];
2633 u8 reserved_at_8[0x18];
2634
2635 u8 element_attributes[0x20];
2636
2637 u8 parent_element_id[0x20];
2638
2639 u8 reserved_at_60[0x40];
2640
2641 u8 bw_share[0x20];
2642
2643 u8 max_average_bw[0x20];
2644
2645 u8 reserved_at_e0[0x120];
2646};
2647
e281682b 2648struct mlx5_ifc_rqtc_bits {
b4ff3a36 2649 u8 reserved_at_0[0xa0];
e281682b 2650
b4ff3a36 2651 u8 reserved_at_a0[0x10];
e281682b
SM		 2652 u8 rqt_max_size[0x10];
2653
b4ff3a36 2654 u8 reserved_at_c0[0x10];
e281682b
SM		 2655 u8 rqt_actual_size[0x10];
2656
b4ff3a36 2657 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2658
2659 struct mlx5_ifc_rq_num_bits rq_num[0];
2660};
2661
2662enum {
2663 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2664 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2665};
2666
2667enum {
2668 MLX5_RQC_STATE_RST = 0x0,
2669 MLX5_RQC_STATE_RDY = 0x1,
2670 MLX5_RQC_STATE_ERR = 0x3,
2671};
2672
2673struct mlx5_ifc_rqc_bits {
2674 u8 rlky[0x1];
03404e8a 2675 u8 delay_drop_en[0x1];
7d5e1423 2676 u8 scatter_fcs[0x1];
e281682b
SM		 2677 u8 vsd[0x1];
2678 u8 mem_rq_type[0x4];
2679 u8 state[0x4];
b4ff3a36 2680 u8 reserved_at_c[0x1];
e281682b 2681 u8 flush_in_error_en[0x1];
40817cdb
OG		 2682 u8 hairpin[0x1];
2683 u8 reserved_at_f[0x11];
e281682b 2684
b4ff3a36 2685 u8 reserved_at_20[0x8];
e281682b
SM		 2686 u8 user_index[0x18];
2687
b4ff3a36 2688 u8 reserved_at_40[0x8];
e281682b
SM		 2689 u8 cqn[0x18];
2690
2691 u8 counter_set_id[0x8];
b4ff3a36 2692 u8 reserved_at_68[0x18];
e281682b 2693
b4ff3a36 2694 u8 reserved_at_80[0x8];
e281682b
SM		 2695 u8 rmpn[0x18];
2696
40817cdb
OG		 2697 u8 reserved_at_a0[0x8];
2698 u8 hairpin_peer_sq[0x18];
2699
2700 u8 reserved_at_c0[0x10];
2701 u8 hairpin_peer_vhca[0x10];
2702
2703 u8 reserved_at_e0[0xa0];
e281682b
SM		 2704
2705 struct mlx5_ifc_wq_bits wq;
2706};
2707
2708enum {
2709 MLX5_RMPC_STATE_RDY = 0x1,
2710 MLX5_RMPC_STATE_ERR = 0x3,
2711};
2712
2713struct mlx5_ifc_rmpc_bits {
b4ff3a36 2714 u8 reserved_at_0[0x8];
e281682b 2715 u8 state[0x4];
b4ff3a36 2716 u8 reserved_at_c[0x14];
e281682b
SM		 2717
2718 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2719 u8 reserved_at_21[0x1f];
e281682b 2720
b4ff3a36 2721 u8 reserved_at_40[0x140];
e281682b
SM		 2722
2723 struct mlx5_ifc_wq_bits wq;
2724};
2725
e281682b 2726struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2727 u8 reserved_at_0[0x5];
2728 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2729 u8 reserved_at_8[0x15];
2730 u8 disable_mc_local_lb[0x1];
2731 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2732 u8 roce_en[0x1];
2733
d82b7318 2734 u8 arm_change_event[0x1];
b4ff3a36 2735 u8 reserved_at_21[0x1a];
d82b7318
SM		 2736 u8 event_on_mtu[0x1];
2737 u8 event_on_promisc_change[0x1];
2738 u8 event_on_vlan_change[0x1];
2739 u8 event_on_mc_address_change[0x1];
2740 u8 event_on_uc_address_change[0x1];
e281682b 2741
32f69e4b
DJ		 2742 u8 reserved_at_40[0xc];
2743
2744 u8 affiliation_criteria[0x4];
2745 u8 affiliated_vhca_id[0x10];
2746
2747 u8 reserved_at_60[0xd0];
d82b7318
SM		 2748
2749 u8 mtu[0x10];
2750
9efa7525
AS		 2751 u8 system_image_guid[0x40];
2752 u8 port_guid[0x40];
2753 u8 node_guid[0x40];
2754
b4ff3a36 2755 u8 reserved_at_200[0x140];
9efa7525 2756 u8 qkey_violation_counter[0x10];
b4ff3a36 2757 u8 reserved_at_350[0x430];
d82b7318
SM		 2758
2759 u8 promisc_uc[0x1];
2760 u8 promisc_mc[0x1];
2761 u8 promisc_all[0x1];
b4ff3a36 2762 u8 reserved_at_783[0x2];
e281682b 2763 u8 allowed_list_type[0x3];
b4ff3a36 2764 u8 reserved_at_788[0xc];
e281682b
SM		 2765 u8 allowed_list_size[0xc];
2766
2767 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2768
b4ff3a36 2769 u8 reserved_at_7e0[0x20];
e281682b
SM		 2770
2771 u8 current_uc_mac_address[0][0x40];
2772};
2773
2774enum {
2775 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2776 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2777 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2778 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
cdbd0d2b 2779 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 2780};
2781
2782struct mlx5_ifc_mkc_bits {
b4ff3a36 2783 u8 reserved_at_0[0x1];
e281682b 2784 u8 free[0x1];
cdbd0d2b
AL		 2785 u8 reserved_at_2[0x1];
2786 u8 access_mode_4_2[0x3];
2787 u8 reserved_at_6[0x7];
2788 u8 relaxed_ordering_write[0x1];
2789 u8 reserved_at_e[0x1];
e281682b
SM		 2790 u8 small_fence_on_rdma_read_response[0x1];
2791 u8 umr_en[0x1];
2792 u8 a[0x1];
2793 u8 rw[0x1];
2794 u8 rr[0x1];
2795 u8 lw[0x1];
2796 u8 lr[0x1];
cdbd0d2b 2797 u8 access_mode_1_0[0x2];
b4ff3a36 2798 u8 reserved_at_18[0x8];
e281682b
SM		 2799
2800 u8 qpn[0x18];
2801 u8 mkey_7_0[0x8];
2802
b4ff3a36 2803 u8 reserved_at_40[0x20];
e281682b
SM		 2804
2805 u8 length64[0x1];
2806 u8 bsf_en[0x1];
2807 u8 sync_umr[0x1];
b4ff3a36 2808 u8 reserved_at_63[0x2];
e281682b 2809 u8 expected_sigerr_count[0x1];
b4ff3a36 2810 u8 reserved_at_66[0x1];
e281682b
SM		 2811 u8 en_rinval[0x1];
2812 u8 pd[0x18];
2813
2814 u8 start_addr[0x40];
2815
2816 u8 len[0x40];
2817
2818 u8 bsf_octword_size[0x20];
2819
b4ff3a36 2820 u8 reserved_at_120[0x80];
e281682b
SM		 2821
2822 u8 translations_octword_size[0x20];
2823
b4ff3a36 2824 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2825 u8 log_page_size[0x5];
2826
b4ff3a36 2827 u8 reserved_at_1e0[0x20];
e281682b
SM		 2828};
2829
2830struct mlx5_ifc_pkey_bits {
b4ff3a36 2831 u8 reserved_at_0[0x10];
e281682b
SM		 2832 u8 pkey[0x10];
2833};
2834
2835struct mlx5_ifc_array128_auto_bits {
2836 u8 array128_auto[16][0x8];
2837};
2838
2839struct mlx5_ifc_hca_vport_context_bits {
2840 u8 field_select[0x20];
2841
b4ff3a36 2842 u8 reserved_at_20[0xe0];
e281682b
SM		 2843
2844 u8 sm_virt_aware[0x1];
2845 u8 has_smi[0x1];
2846 u8 has_raw[0x1];
2847 u8 grh_required[0x1];
b4ff3a36 2848 u8 reserved_at_104[0xc];
707c4602
MD		 2849 u8 port_physical_state[0x4];
2850 u8 vport_state_policy[0x4];
2851 u8 port_state[0x4];
e281682b
SM		 2852 u8 vport_state[0x4];
2853
b4ff3a36 2854 u8 reserved_at_120[0x20];
707c4602
MD		 2855
2856 u8 system_image_guid[0x40];
e281682b
SM		 2857
2858 u8 port_guid[0x40];
2859
2860 u8 node_guid[0x40];
2861
2862 u8 cap_mask1[0x20];
2863
2864 u8 cap_mask1_field_select[0x20];
2865
2866 u8 cap_mask2[0x20];
2867
2868 u8 cap_mask2_field_select[0x20];
2869
b4ff3a36 2870 u8 reserved_at_280[0x80];
e281682b
SM		 2871
2872 u8 lid[0x10];
b4ff3a36 2873 u8 reserved_at_310[0x4];
e281682b
SM		 2874 u8 init_type_reply[0x4];
2875 u8 lmc[0x3];
2876 u8 subnet_timeout[0x5];
2877
2878 u8 sm_lid[0x10];
2879 u8 sm_sl[0x4];
b4ff3a36 2880 u8 reserved_at_334[0xc];
e281682b
SM		 2881
2882 u8 qkey_violation_counter[0x10];
2883 u8 pkey_violation_counter[0x10];
2884
b4ff3a36 2885 u8 reserved_at_360[0xca0];
e281682b
SM		 2886};
2887
d6666753 2888struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2889 u8 reserved_at_0[0x3];
d6666753
SM		 2890 u8 vport_svlan_strip[0x1];
2891 u8 vport_cvlan_strip[0x1];
2892 u8 vport_svlan_insert[0x1];
2893 u8 vport_cvlan_insert[0x2];
b4ff3a36 2894 u8 reserved_at_8[0x18];
d6666753 2895
b4ff3a36 2896 u8 reserved_at_20[0x20];
d6666753
SM		 2897
2898 u8 svlan_cfi[0x1];
2899 u8 svlan_pcp[0x3];
2900 u8 svlan_id[0xc];
2901 u8 cvlan_cfi[0x1];
2902 u8 cvlan_pcp[0x3];
2903 u8 cvlan_id[0xc];
2904
b4ff3a36 2905 u8 reserved_at_60[0x7a0];
d6666753
SM		 2906};
2907
e281682b
SM		 2908enum {
2909 MLX5_EQC_STATUS_OK = 0x0,
2910 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2911};
2912
2913enum {
2914 MLX5_EQC_ST_ARMED = 0x9,
2915 MLX5_EQC_ST_FIRED = 0xa,
2916};
2917
2918struct mlx5_ifc_eqc_bits {
2919 u8 status[0x4];
b4ff3a36 2920 u8 reserved_at_4[0x9];
e281682b
SM		 2921 u8 ec[0x1];
2922 u8 oi[0x1];
b4ff3a36 2923 u8 reserved_at_f[0x5];
e281682b 2924 u8 st[0x4];
b4ff3a36 2925 u8 reserved_at_18[0x8];
e281682b 2926
b4ff3a36 2927 u8 reserved_at_20[0x20];
e281682b 2928
b4ff3a36 2929 u8 reserved_at_40[0x14];
e281682b 2930 u8 page_offset[0x6];
b4ff3a36 2931 u8 reserved_at_5a[0x6];
e281682b 2932
b4ff3a36 2933 u8 reserved_at_60[0x3];
e281682b
SM		 2934 u8 log_eq_size[0x5];
2935 u8 uar_page[0x18];
2936
b4ff3a36 2937 u8 reserved_at_80[0x20];
e281682b 2938
b4ff3a36 2939 u8 reserved_at_a0[0x18];
e281682b
SM		 2940 u8 intr[0x8];
2941
b4ff3a36 2942 u8 reserved_at_c0[0x3];
e281682b 2943 u8 log_page_size[0x5];
b4ff3a36 2944 u8 reserved_at_c8[0x18];
e281682b 2945
b4ff3a36 2946 u8 reserved_at_e0[0x60];
e281682b 2947
b4ff3a36 2948 u8 reserved_at_140[0x8];
e281682b
SM		 2949 u8 consumer_counter[0x18];
2950
b4ff3a36 2951 u8 reserved_at_160[0x8];
e281682b
SM		 2952 u8 producer_counter[0x18];
2953
b4ff3a36 2954 u8 reserved_at_180[0x80];
e281682b
SM		 2955};
2956
2957enum {
2958 MLX5_DCTC_STATE_ACTIVE = 0x0,
2959 MLX5_DCTC_STATE_DRAINING = 0x1,
2960 MLX5_DCTC_STATE_DRAINED = 0x2,
2961};
2962
2963enum {
2964 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2965 MLX5_DCTC_CS_RES_NA = 0x1,
2966 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2967};
2968
2969enum {
2970 MLX5_DCTC_MTU_256_BYTES = 0x1,
2971 MLX5_DCTC_MTU_512_BYTES = 0x2,
2972 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2973 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2974 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2975};
2976
2977struct mlx5_ifc_dctc_bits {
b4ff3a36 2978 u8 reserved_at_0[0x4];
e281682b 2979 u8 state[0x4];
b4ff3a36 2980 u8 reserved_at_8[0x18];
e281682b 2981
b4ff3a36 2982 u8 reserved_at_20[0x8];
e281682b
SM		 2983 u8 user_index[0x18];
2984
b4ff3a36 2985 u8 reserved_at_40[0x8];
e281682b
SM		 2986 u8 cqn[0x18];
2987
2988 u8 counter_set_id[0x8];
2989 u8 atomic_mode[0x4];
2990 u8 rre[0x1];
2991 u8 rwe[0x1];
2992 u8 rae[0x1];
2993 u8 atomic_like_write_en[0x1];
2994 u8 latency_sensitive[0x1];
2995 u8 rlky[0x1];
2996 u8 free_ar[0x1];
b4ff3a36 2997 u8 reserved_at_73[0xd];
e281682b 2998
b4ff3a36 2999 u8 reserved_at_80[0x8];
e281682b 3000 u8 cs_res[0x8];
b4ff3a36 3001 u8 reserved_at_90[0x3];
e281682b 3002 u8 min_rnr_nak[0x5];
b4ff3a36 3003 u8 reserved_at_98[0x8];
e281682b 3004
b4ff3a36 3005 u8 reserved_at_a0[0x8];
7486216b 3006 u8 srqn_xrqn[0x18];
e281682b 3007
b4ff3a36 3008 u8 reserved_at_c0[0x8];
e281682b
SM		 3009 u8 pd[0x18];
3010
3011 u8 tclass[0x8];
b4ff3a36 3012 u8 reserved_at_e8[0x4];
e281682b
SM		 3013 u8 flow_label[0x14];
3014
3015 u8 dc_access_key[0x40];
3016
b4ff3a36 3017 u8 reserved_at_140[0x5];
e281682b
SM		 3018 u8 mtu[0x3];
3019 u8 port[0x8];
3020 u8 pkey_index[0x10];
3021
b4ff3a36 3022 u8 reserved_at_160[0x8];
e281682b 3023 u8 my_addr_index[0x8];
b4ff3a36 3024 u8 reserved_at_170[0x8];
e281682b
SM		 3025 u8 hop_limit[0x8];
3026
3027 u8 dc_access_key_violation_count[0x20];
3028
b4ff3a36 3029 u8 reserved_at_1a0[0x14];
e281682b
SM		 3030 u8 dei_cfi[0x1];
3031 u8 eth_prio[0x3];
3032 u8 ecn[0x2];
3033 u8 dscp[0x6];
3034
b4ff3a36 3035 u8 reserved_at_1c0[0x40];
e281682b
SM		 3036};
3037
3038enum {
3039 MLX5_CQC_STATUS_OK = 0x0,
3040 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3041 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3042};
3043
3044enum {
3045 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3046 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3047};
3048
3049enum {
3050 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3051 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3052 MLX5_CQC_ST_FIRED = 0xa,
3053};
3054
7d5e1423
SM		 3055enum {
3056 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3057 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3058 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3059};
3060
e281682b
SM		 3061struct mlx5_ifc_cqc_bits {
3062 u8 status[0x4];
b4ff3a36 3063 u8 reserved_at_4[0x4];
e281682b
SM		 3064 u8 cqe_sz[0x3];
3065 u8 cc[0x1];
b4ff3a36 3066 u8 reserved_at_c[0x1];
e281682b
SM		 3067 u8 scqe_break_moderation_en[0x1];
3068 u8 oi[0x1];
7d5e1423
SM		 3069 u8 cq_period_mode[0x2];
3070 u8 cqe_comp_en[0x1];
e281682b
SM		 3071 u8 mini_cqe_res_format[0x2];
3072 u8 st[0x4];
b4ff3a36 3073 u8 reserved_at_18[0x8];
e281682b 3074
b4ff3a36 3075 u8 reserved_at_20[0x20];
e281682b 3076
b4ff3a36 3077 u8 reserved_at_40[0x14];
e281682b 3078 u8 page_offset[0x6];
b4ff3a36 3079 u8 reserved_at_5a[0x6];
e281682b 3080
b4ff3a36 3081 u8 reserved_at_60[0x3];
e281682b
SM		 3082 u8 log_cq_size[0x5];
3083 u8 uar_page[0x18];
3084
b4ff3a36 3085 u8 reserved_at_80[0x4];
e281682b
SM		 3086 u8 cq_period[0xc];
3087 u8 cq_max_count[0x10];
3088
b4ff3a36 3089 u8 reserved_at_a0[0x18];
e281682b
SM		 3090 u8 c_eqn[0x8];
3091
b4ff3a36 3092 u8 reserved_at_c0[0x3];
e281682b 3093 u8 log_page_size[0x5];
b4ff3a36 3094 u8 reserved_at_c8[0x18];
e281682b 3095
b4ff3a36 3096 u8 reserved_at_e0[0x20];
e281682b 3097
b4ff3a36 3098 u8 reserved_at_100[0x8];
e281682b
SM		 3099 u8 last_notified_index[0x18];
3100
b4ff3a36 3101 u8 reserved_at_120[0x8];
e281682b
SM		 3102 u8 last_solicit_index[0x18];
3103
b4ff3a36 3104 u8 reserved_at_140[0x8];
e281682b
SM		 3105 u8 consumer_counter[0x18];
3106
b4ff3a36 3107 u8 reserved_at_160[0x8];
e281682b
SM		 3108 u8 producer_counter[0x18];
3109
b4ff3a36 3110 u8 reserved_at_180[0x40];
e281682b
SM		 3111
3112 u8 dbr_addr[0x40];
3113};
3114
3115union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3116 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3117 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3118 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3119 u8 reserved_at_0[0x800];
e281682b
SM		 3120};
3121
3122struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3123 u8 reserved_at_0[0xc0];
e281682b 3124
b4ff3a36 3125 u8 reserved_at_c0[0x8];
211e6c80
MD		 3126 u8 ieee_vendor_id[0x18];
3127
b4ff3a36 3128 u8 reserved_at_e0[0x10];
e281682b
SM		 3129 u8 vsd_vendor_id[0x10];
3130
3131 u8 vsd[208][0x8];
3132
3133 u8 vsd_contd_psid[16][0x8];
3134};
3135
7486216b
SM		 3136enum {
3137 MLX5_XRQC_STATE_GOOD = 0x0,
3138 MLX5_XRQC_STATE_ERROR = 0x1,
3139};
3140
3141enum {
3142 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3143 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3144};
3145
3146enum {
3147 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3148};
3149
3150struct mlx5_ifc_tag_matching_topology_context_bits {
3151 u8 log_matching_list_sz[0x4];
3152 u8 reserved_at_4[0xc];
3153 u8 append_next_index[0x10];
3154
3155 u8 sw_phase_cnt[0x10];
3156 u8 hw_phase_cnt[0x10];
3157
3158 u8 reserved_at_40[0x40];
3159};
3160
3161struct mlx5_ifc_xrqc_bits {
3162 u8 state[0x4];
3163 u8 rlkey[0x1];
3164 u8 reserved_at_5[0xf];
3165 u8 topology[0x4];
3166 u8 reserved_at_18[0x4];
3167 u8 offload[0x4];
3168
3169 u8 reserved_at_20[0x8];
3170 u8 user_index[0x18];
3171
3172 u8 reserved_at_40[0x8];
3173 u8 cqn[0x18];
3174
3175 u8 reserved_at_60[0xa0];
3176
3177 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3178
6e44636a 3179 u8 reserved_at_180[0x280];
7486216b
SM		 3180
3181 struct mlx5_ifc_wq_bits wq;
3182};
3183
e281682b
SM		 3184union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3185 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3186 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3187 u8 reserved_at_0[0x20];
e281682b
SM		 3188};
3189
3190union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3191 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3192 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3193 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3194 u8 reserved_at_0[0x20];
e281682b
SM		 3195};
3196
3197union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3198 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3199 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3200 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3201 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3202 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3203 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3204 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3205 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3206 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3207 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3208 u8 reserved_at_0[0x7c0];
e281682b
SM		 3209};
3210
8ed1a630
GP		 3211union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3212 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3213 u8 reserved_at_0[0x7c0];
3214};
3215
e281682b
SM		 3216union mlx5_ifc_event_auto_bits {
3217 struct mlx5_ifc_comp_event_bits comp_event;
3218 struct mlx5_ifc_dct_events_bits dct_events;
3219 struct mlx5_ifc_qp_events_bits qp_events;
3220 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3221 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3222 struct mlx5_ifc_cq_error_bits cq_error;
3223 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3224 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3225 struct mlx5_ifc_gpio_event_bits gpio_event;
3226 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3227 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3228 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3229 u8 reserved_at_0[0xe0];
e281682b
SM		 3230};
3231
3232struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3233 u8 reserved_at_0[0x100];
e281682b
SM		 3234
3235 u8 assert_existptr[0x20];
3236
3237 u8 assert_callra[0x20];
3238
b4ff3a36 3239 u8 reserved_at_140[0x40];
e281682b
SM		 3240
3241 u8 fw_version[0x20];
3242
3243 u8 hw_id[0x20];
3244
b4ff3a36 3245 u8 reserved_at_1c0[0x20];
e281682b
SM		 3246
3247 u8 irisc_index[0x8];
3248 u8 synd[0x8];
3249 u8 ext_synd[0x10];
3250};
3251
3252struct mlx5_ifc_register_loopback_control_bits {
3253 u8 no_lb[0x1];
b4ff3a36 3254 u8 reserved_at_1[0x7];
e281682b 3255 u8 port[0x8];
b4ff3a36 3256 u8 reserved_at_10[0x10];
e281682b 3257
b4ff3a36 3258 u8 reserved_at_20[0x60];
e281682b
SM		 3259};
3260
813f8540
MHY		 3261struct mlx5_ifc_vport_tc_element_bits {
3262 u8 traffic_class[0x4];
3263 u8 reserved_at_4[0xc];
3264 u8 vport_number[0x10];
3265};
3266
3267struct mlx5_ifc_vport_element_bits {
3268 u8 reserved_at_0[0x10];
3269 u8 vport_number[0x10];
3270};
3271
3272enum {
3273 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3274 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3275 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3276};
3277
3278struct mlx5_ifc_tsar_element_bits {
3279 u8 reserved_at_0[0x8];
3280 u8 tsar_type[0x8];
3281 u8 reserved_at_10[0x10];
3282};
3283
8812c24d
MD		 3284enum {
3285 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3286 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3287};
3288
e281682b
SM		 3289struct mlx5_ifc_teardown_hca_out_bits {
3290 u8 status[0x8];
b4ff3a36 3291 u8 reserved_at_8[0x18];
e281682b
SM		 3292
3293 u8 syndrome[0x20];
3294
8812c24d
MD		 3295 u8 reserved_at_40[0x3f];
3296
3297 u8 force_state[0x1];
e281682b
SM		 3298};
3299
3300enum {
3301 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3302 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3303};
3304
3305struct mlx5_ifc_teardown_hca_in_bits {
3306 u8 opcode[0x10];
b4ff3a36 3307 u8 reserved_at_10[0x10];
e281682b 3308
b4ff3a36 3309 u8 reserved_at_20[0x10];
e281682b
SM		 3310 u8 op_mod[0x10];
3311
b4ff3a36 3312 u8 reserved_at_40[0x10];
e281682b
SM		 3313 u8 profile[0x10];
3314
b4ff3a36 3315 u8 reserved_at_60[0x20];
e281682b
SM		 3316};
3317
3318struct mlx5_ifc_sqerr2rts_qp_out_bits {
3319 u8 status[0x8];
b4ff3a36 3320 u8 reserved_at_8[0x18];
e281682b
SM		 3321
3322 u8 syndrome[0x20];
3323
b4ff3a36 3324 u8 reserved_at_40[0x40];
e281682b
SM		 3325};
3326
3327struct mlx5_ifc_sqerr2rts_qp_in_bits {
3328 u8 opcode[0x10];
b4ff3a36 3329 u8 reserved_at_10[0x10];
e281682b 3330
b4ff3a36 3331 u8 reserved_at_20[0x10];
e281682b
SM		 3332 u8 op_mod[0x10];
3333
b4ff3a36 3334 u8 reserved_at_40[0x8];
e281682b
SM		 3335 u8 qpn[0x18];
3336
b4ff3a36 3337 u8 reserved_at_60[0x20];
e281682b
SM		 3338
3339 u8 opt_param_mask[0x20];
3340
b4ff3a36 3341 u8 reserved_at_a0[0x20];
e281682b
SM		 3342
3343 struct mlx5_ifc_qpc_bits qpc;
3344
b4ff3a36 3345 u8 reserved_at_800[0x80];
e281682b
SM		 3346};
3347
3348struct mlx5_ifc_sqd2rts_qp_out_bits {
3349 u8 status[0x8];
b4ff3a36 3350 u8 reserved_at_8[0x18];
e281682b
SM		 3351
3352 u8 syndrome[0x20];
3353
b4ff3a36 3354 u8 reserved_at_40[0x40];
e281682b
SM		 3355};
3356
3357struct mlx5_ifc_sqd2rts_qp_in_bits {
3358 u8 opcode[0x10];
b4ff3a36 3359 u8 reserved_at_10[0x10];
e281682b 3360
b4ff3a36 3361 u8 reserved_at_20[0x10];
e281682b
SM		 3362 u8 op_mod[0x10];
3363
b4ff3a36 3364 u8 reserved_at_40[0x8];
e281682b
SM		 3365 u8 qpn[0x18];
3366
b4ff3a36 3367 u8 reserved_at_60[0x20];
e281682b
SM		 3368
3369 u8 opt_param_mask[0x20];
3370
b4ff3a36 3371 u8 reserved_at_a0[0x20];
e281682b
SM		 3372
3373 struct mlx5_ifc_qpc_bits qpc;
3374
b4ff3a36 3375 u8 reserved_at_800[0x80];
e281682b
SM		 3376};
3377
3378struct mlx5_ifc_set_roce_address_out_bits {
3379 u8 status[0x8];
b4ff3a36 3380 u8 reserved_at_8[0x18];
e281682b
SM		 3381
3382 u8 syndrome[0x20];
3383
b4ff3a36 3384 u8 reserved_at_40[0x40];
e281682b
SM		 3385};
3386
3387struct mlx5_ifc_set_roce_address_in_bits {
3388 u8 opcode[0x10];
b4ff3a36 3389 u8 reserved_at_10[0x10];
e281682b 3390
b4ff3a36 3391 u8 reserved_at_20[0x10];
e281682b
SM		 3392 u8 op_mod[0x10];
3393
3394 u8 roce_address_index[0x10];
32f69e4b
DJ		 3395 u8 reserved_at_50[0xc];
3396 u8 vhca_port_num[0x4];
e281682b 3397
b4ff3a36 3398 u8 reserved_at_60[0x20];
e281682b
SM		 3399
3400 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3401};
3402
3403struct mlx5_ifc_set_mad_demux_out_bits {
3404 u8 status[0x8];
b4ff3a36 3405 u8 reserved_at_8[0x18];
e281682b
SM		 3406
3407 u8 syndrome[0x20];
3408
b4ff3a36 3409 u8 reserved_at_40[0x40];
e281682b
SM		 3410};
3411
3412enum {
3413 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3414 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3415};
3416
3417struct mlx5_ifc_set_mad_demux_in_bits {
3418 u8 opcode[0x10];
b4ff3a36 3419 u8 reserved_at_10[0x10];
e281682b 3420
b4ff3a36 3421 u8 reserved_at_20[0x10];
e281682b
SM		 3422 u8 op_mod[0x10];
3423
b4ff3a36 3424 u8 reserved_at_40[0x20];
e281682b 3425
b4ff3a36 3426 u8 reserved_at_60[0x6];
e281682b 3427 u8 demux_mode[0x2];
b4ff3a36 3428 u8 reserved_at_68[0x18];
e281682b
SM		 3429};
3430
3431struct mlx5_ifc_set_l2_table_entry_out_bits {
3432 u8 status[0x8];
b4ff3a36 3433 u8 reserved_at_8[0x18];
e281682b
SM		 3434
3435 u8 syndrome[0x20];
3436
b4ff3a36 3437 u8 reserved_at_40[0x40];
e281682b
SM		 3438};
3439
3440struct mlx5_ifc_set_l2_table_entry_in_bits {
3441 u8 opcode[0x10];
b4ff3a36 3442 u8 reserved_at_10[0x10];
e281682b 3443
b4ff3a36 3444 u8 reserved_at_20[0x10];
e281682b
SM		 3445 u8 op_mod[0x10];
3446
b4ff3a36 3447 u8 reserved_at_40[0x60];
e281682b 3448
b4ff3a36 3449 u8 reserved_at_a0[0x8];
e281682b
SM		 3450 u8 table_index[0x18];
3451
b4ff3a36 3452 u8 reserved_at_c0[0x20];
e281682b 3453
b4ff3a36 3454 u8 reserved_at_e0[0x13];
e281682b
SM		 3455 u8 vlan_valid[0x1];
3456 u8 vlan[0xc];
3457
3458 struct mlx5_ifc_mac_address_layout_bits mac_address;
3459
b4ff3a36 3460 u8 reserved_at_140[0xc0];
e281682b
SM		 3461};
3462
3463struct mlx5_ifc_set_issi_out_bits {
3464 u8 status[0x8];
b4ff3a36 3465 u8 reserved_at_8[0x18];
e281682b
SM		 3466
3467 u8 syndrome[0x20];
3468
b4ff3a36 3469 u8 reserved_at_40[0x40];
e281682b
SM		 3470};
3471
3472struct mlx5_ifc_set_issi_in_bits {
3473 u8 opcode[0x10];
b4ff3a36 3474 u8 reserved_at_10[0x10];
e281682b 3475
b4ff3a36 3476 u8 reserved_at_20[0x10];
e281682b
SM		 3477 u8 op_mod[0x10];
3478
b4ff3a36 3479 u8 reserved_at_40[0x10];
e281682b
SM		 3480 u8 current_issi[0x10];
3481
b4ff3a36 3482 u8 reserved_at_60[0x20];
e281682b
SM		 3483};
3484
3485struct mlx5_ifc_set_hca_cap_out_bits {
3486 u8 status[0x8];
b4ff3a36 3487 u8 reserved_at_8[0x18];
e281682b
SM		 3488
3489 u8 syndrome[0x20];
3490
b4ff3a36 3491 u8 reserved_at_40[0x40];
e281682b
SM		 3492};
3493
3494struct mlx5_ifc_set_hca_cap_in_bits {
3495 u8 opcode[0x10];
b4ff3a36 3496 u8 reserved_at_10[0x10];
e281682b 3497
b4ff3a36 3498 u8 reserved_at_20[0x10];
e281682b
SM		 3499 u8 op_mod[0x10];
3500
b4ff3a36 3501 u8 reserved_at_40[0x40];
e281682b
SM		 3502
3503 union mlx5_ifc_hca_cap_union_bits capability;
3504};
3505
26a81453
MG		 3506enum {
3507 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3508 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3509 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3510 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3511};
3512
e281682b
SM		 3513struct mlx5_ifc_set_fte_out_bits {
3514 u8 status[0x8];
b4ff3a36 3515 u8 reserved_at_8[0x18];
e281682b
SM		 3516
3517 u8 syndrome[0x20];
3518
b4ff3a36 3519 u8 reserved_at_40[0x40];
e281682b
SM		 3520};
3521
3522struct mlx5_ifc_set_fte_in_bits {
3523 u8 opcode[0x10];
b4ff3a36 3524 u8 reserved_at_10[0x10];
e281682b 3525
b4ff3a36 3526 u8 reserved_at_20[0x10];
e281682b
SM		 3527 u8 op_mod[0x10];
3528
7d5e1423
SM		 3529 u8 other_vport[0x1];
3530 u8 reserved_at_41[0xf];
3531 u8 vport_number[0x10];
3532
3533 u8 reserved_at_60[0x20];
e281682b
SM		 3534
3535 u8 table_type[0x8];
b4ff3a36 3536 u8 reserved_at_88[0x18];
e281682b 3537
b4ff3a36 3538 u8 reserved_at_a0[0x8];
e281682b
SM		 3539 u8 table_id[0x18];
3540
b4ff3a36 3541 u8 reserved_at_c0[0x18];
26a81453
MG		 3542 u8 modify_enable_mask[0x8];
3543
b4ff3a36 3544 u8 reserved_at_e0[0x20];
e281682b
SM		 3545
3546 u8 flow_index[0x20];
3547
b4ff3a36 3548 u8 reserved_at_120[0xe0];
e281682b
SM		 3549
3550 struct mlx5_ifc_flow_context_bits flow_context;
3551};
3552
3553struct mlx5_ifc_rts2rts_qp_out_bits {
3554 u8 status[0x8];
b4ff3a36 3555 u8 reserved_at_8[0x18];
e281682b
SM		 3556
3557 u8 syndrome[0x20];
3558
b4ff3a36 3559 u8 reserved_at_40[0x40];
e281682b
SM		 3560};
3561
3562struct mlx5_ifc_rts2rts_qp_in_bits {
3563 u8 opcode[0x10];
b4ff3a36 3564 u8 reserved_at_10[0x10];
e281682b 3565
b4ff3a36 3566 u8 reserved_at_20[0x10];
e281682b
SM		 3567 u8 op_mod[0x10];
3568
b4ff3a36 3569 u8 reserved_at_40[0x8];
e281682b
SM		 3570 u8 qpn[0x18];
3571
b4ff3a36 3572 u8 reserved_at_60[0x20];
e281682b
SM		 3573
3574 u8 opt_param_mask[0x20];
3575
b4ff3a36 3576 u8 reserved_at_a0[0x20];
e281682b
SM		 3577
3578 struct mlx5_ifc_qpc_bits qpc;
3579
b4ff3a36 3580 u8 reserved_at_800[0x80];
e281682b
SM		 3581};
3582
3583struct mlx5_ifc_rtr2rts_qp_out_bits {
3584 u8 status[0x8];
b4ff3a36 3585 u8 reserved_at_8[0x18];
e281682b
SM		 3586
3587 u8 syndrome[0x20];
3588
b4ff3a36 3589 u8 reserved_at_40[0x40];
e281682b
SM		 3590};
3591
3592struct mlx5_ifc_rtr2rts_qp_in_bits {
3593 u8 opcode[0x10];
b4ff3a36 3594 u8 reserved_at_10[0x10];
e281682b 3595
b4ff3a36 3596 u8 reserved_at_20[0x10];
e281682b
SM		 3597 u8 op_mod[0x10];
3598
b4ff3a36 3599 u8 reserved_at_40[0x8];
e281682b
SM		 3600 u8 qpn[0x18];
3601
b4ff3a36 3602 u8 reserved_at_60[0x20];
e281682b
SM		 3603
3604 u8 opt_param_mask[0x20];
3605
b4ff3a36 3606 u8 reserved_at_a0[0x20];
e281682b
SM		 3607
3608 struct mlx5_ifc_qpc_bits qpc;
3609
b4ff3a36 3610 u8 reserved_at_800[0x80];
e281682b
SM		 3611};
3612
3613struct mlx5_ifc_rst2init_qp_out_bits {
3614 u8 status[0x8];
b4ff3a36 3615 u8 reserved_at_8[0x18];
e281682b
SM		 3616
3617 u8 syndrome[0x20];
3618
b4ff3a36 3619 u8 reserved_at_40[0x40];
e281682b
SM		 3620};
3621
3622struct mlx5_ifc_rst2init_qp_in_bits {
3623 u8 opcode[0x10];
b4ff3a36 3624 u8 reserved_at_10[0x10];
e281682b 3625
b4ff3a36 3626 u8 reserved_at_20[0x10];
e281682b
SM		 3627 u8 op_mod[0x10];
3628
b4ff3a36 3629 u8 reserved_at_40[0x8];
e281682b
SM		 3630 u8 qpn[0x18];
3631
b4ff3a36 3632 u8 reserved_at_60[0x20];
e281682b
SM		 3633
3634 u8 opt_param_mask[0x20];
3635
b4ff3a36 3636 u8 reserved_at_a0[0x20];
e281682b
SM		 3637
3638 struct mlx5_ifc_qpc_bits qpc;
3639
b4ff3a36 3640 u8 reserved_at_800[0x80];
e281682b
SM		 3641};
3642
7486216b
SM		 3643struct mlx5_ifc_query_xrq_out_bits {
3644 u8 status[0x8];
3645 u8 reserved_at_8[0x18];
3646
3647 u8 syndrome[0x20];
3648
3649 u8 reserved_at_40[0x40];
3650
3651 struct mlx5_ifc_xrqc_bits xrq_context;
3652};
3653
3654struct mlx5_ifc_query_xrq_in_bits {
3655 u8 opcode[0x10];
3656 u8 reserved_at_10[0x10];
3657
3658 u8 reserved_at_20[0x10];
3659 u8 op_mod[0x10];
3660
3661 u8 reserved_at_40[0x8];
3662 u8 xrqn[0x18];
3663
3664 u8 reserved_at_60[0x20];
3665};
3666
e281682b
SM		 3667struct mlx5_ifc_query_xrc_srq_out_bits {
3668 u8 status[0x8];
b4ff3a36 3669 u8 reserved_at_8[0x18];
e281682b
SM		 3670
3671 u8 syndrome[0x20];
3672
b4ff3a36 3673 u8 reserved_at_40[0x40];
e281682b
SM		 3674
3675 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3676
b4ff3a36 3677 u8 reserved_at_280[0x600];
e281682b
SM		 3678
3679 u8 pas[0][0x40];
3680};
3681
3682struct mlx5_ifc_query_xrc_srq_in_bits {
3683 u8 opcode[0x10];
b4ff3a36 3684 u8 reserved_at_10[0x10];
e281682b 3685
b4ff3a36 3686 u8 reserved_at_20[0x10];
e281682b
SM		 3687 u8 op_mod[0x10];
3688
b4ff3a36 3689 u8 reserved_at_40[0x8];
e281682b
SM		 3690 u8 xrc_srqn[0x18];
3691
b4ff3a36 3692 u8 reserved_at_60[0x20];
e281682b
SM		 3693};
3694
3695enum {
3696 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3697 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3698};
3699
3700struct mlx5_ifc_query_vport_state_out_bits {
3701 u8 status[0x8];
b4ff3a36 3702 u8 reserved_at_8[0x18];
e281682b
SM		 3703
3704 u8 syndrome[0x20];
3705
b4ff3a36 3706 u8 reserved_at_40[0x20];
e281682b 3707
b4ff3a36 3708 u8 reserved_at_60[0x18];
e281682b
SM		 3709 u8 admin_state[0x4];
3710 u8 state[0x4];
3711};
3712
3713enum {
3714 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3715 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3716};
3717
3718struct mlx5_ifc_query_vport_state_in_bits {
3719 u8 opcode[0x10];
b4ff3a36 3720 u8 reserved_at_10[0x10];
e281682b 3721
b4ff3a36 3722 u8 reserved_at_20[0x10];
e281682b
SM		 3723 u8 op_mod[0x10];
3724
3725 u8 other_vport[0x1];
b4ff3a36 3726 u8 reserved_at_41[0xf];
e281682b
SM		 3727 u8 vport_number[0x10];
3728
b4ff3a36 3729 u8 reserved_at_60[0x20];
e281682b
SM		 3730};
3731
61c5b5c9
MS		 3732struct mlx5_ifc_query_vnic_env_out_bits {
3733 u8 status[0x8];
3734 u8 reserved_at_8[0x18];
3735
3736 u8 syndrome[0x20];
3737
3738 u8 reserved_at_40[0x40];
3739
3740 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3741};
3742
3743enum {
3744 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3745};
3746
3747struct mlx5_ifc_query_vnic_env_in_bits {
3748 u8 opcode[0x10];
3749 u8 reserved_at_10[0x10];
3750
3751 u8 reserved_at_20[0x10];
3752 u8 op_mod[0x10];
3753
3754 u8 other_vport[0x1];
3755 u8 reserved_at_41[0xf];
3756 u8 vport_number[0x10];
3757
3758 u8 reserved_at_60[0x20];
3759};
3760
e281682b
SM		 3761struct mlx5_ifc_query_vport_counter_out_bits {
3762 u8 status[0x8];
b4ff3a36 3763 u8 reserved_at_8[0x18];
e281682b
SM		 3764
3765 u8 syndrome[0x20];
3766
b4ff3a36 3767 u8 reserved_at_40[0x40];
e281682b
SM		 3768
3769 struct mlx5_ifc_traffic_counter_bits received_errors;
3770
3771 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3772
3773 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3774
3775 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3776
3777 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3778
3779 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3780
3781 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3782
3783 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3784
3785 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3786
3787 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3788
3789 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3790
3791 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3792
b4ff3a36 3793 u8 reserved_at_680[0xa00];
e281682b
SM		 3794};
3795
3796enum {
3797 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3798};
3799
3800struct mlx5_ifc_query_vport_counter_in_bits {
3801 u8 opcode[0x10];
b4ff3a36 3802 u8 reserved_at_10[0x10];
e281682b 3803
b4ff3a36 3804 u8 reserved_at_20[0x10];
e281682b
SM		 3805 u8 op_mod[0x10];
3806
3807 u8 other_vport[0x1];
b54ba277
MY		 3808 u8 reserved_at_41[0xb];
3809 u8 port_num[0x4];
e281682b
SM		 3810 u8 vport_number[0x10];
3811
b4ff3a36 3812 u8 reserved_at_60[0x60];
e281682b
SM		 3813
3814 u8 clear[0x1];
b4ff3a36 3815 u8 reserved_at_c1[0x1f];
e281682b 3816
b4ff3a36 3817 u8 reserved_at_e0[0x20];
e281682b
SM		 3818};
3819
3820struct mlx5_ifc_query_tis_out_bits {
3821 u8 status[0x8];
b4ff3a36 3822 u8 reserved_at_8[0x18];
e281682b
SM		 3823
3824 u8 syndrome[0x20];
3825
b4ff3a36 3826 u8 reserved_at_40[0x40];
e281682b
SM		 3827
3828 struct mlx5_ifc_tisc_bits tis_context;
3829};
3830
3831struct mlx5_ifc_query_tis_in_bits {
3832 u8 opcode[0x10];
b4ff3a36 3833 u8 reserved_at_10[0x10];
e281682b 3834
b4ff3a36 3835 u8 reserved_at_20[0x10];
e281682b
SM		 3836 u8 op_mod[0x10];
3837
b4ff3a36 3838 u8 reserved_at_40[0x8];
e281682b
SM		 3839 u8 tisn[0x18];
3840
b4ff3a36 3841 u8 reserved_at_60[0x20];
e281682b
SM		 3842};
3843
3844struct mlx5_ifc_query_tir_out_bits {
3845 u8 status[0x8];
b4ff3a36 3846 u8 reserved_at_8[0x18];
e281682b
SM		 3847
3848 u8 syndrome[0x20];
3849
b4ff3a36 3850 u8 reserved_at_40[0xc0];
e281682b
SM		 3851
3852 struct mlx5_ifc_tirc_bits tir_context;
3853};
3854
3855struct mlx5_ifc_query_tir_in_bits {
3856 u8 opcode[0x10];
b4ff3a36 3857 u8 reserved_at_10[0x10];
e281682b 3858
b4ff3a36 3859 u8 reserved_at_20[0x10];
e281682b
SM		 3860 u8 op_mod[0x10];
3861
b4ff3a36 3862 u8 reserved_at_40[0x8];
e281682b
SM		 3863 u8 tirn[0x18];
3864
b4ff3a36 3865 u8 reserved_at_60[0x20];
e281682b
SM		 3866};
3867
3868struct mlx5_ifc_query_srq_out_bits {
3869 u8 status[0x8];
b4ff3a36 3870 u8 reserved_at_8[0x18];
e281682b
SM		 3871
3872 u8 syndrome[0x20];
3873
b4ff3a36 3874 u8 reserved_at_40[0x40];
e281682b
SM		 3875
3876 struct mlx5_ifc_srqc_bits srq_context_entry;
3877
b4ff3a36 3878 u8 reserved_at_280[0x600];
e281682b
SM		 3879
3880 u8 pas[0][0x40];
3881};
3882
3883struct mlx5_ifc_query_srq_in_bits {
3884 u8 opcode[0x10];
b4ff3a36 3885 u8 reserved_at_10[0x10];
e281682b 3886
b4ff3a36 3887 u8 reserved_at_20[0x10];
e281682b
SM		 3888 u8 op_mod[0x10];
3889
b4ff3a36 3890 u8 reserved_at_40[0x8];
e281682b
SM		 3891 u8 srqn[0x18];
3892
b4ff3a36 3893 u8 reserved_at_60[0x20];
e281682b
SM		 3894};
3895
3896struct mlx5_ifc_query_sq_out_bits {
3897 u8 status[0x8];
b4ff3a36 3898 u8 reserved_at_8[0x18];
e281682b
SM		 3899
3900 u8 syndrome[0x20];
3901
b4ff3a36 3902 u8 reserved_at_40[0xc0];
e281682b
SM		 3903
3904 struct mlx5_ifc_sqc_bits sq_context;
3905};
3906
3907struct mlx5_ifc_query_sq_in_bits {
3908 u8 opcode[0x10];
b4ff3a36 3909 u8 reserved_at_10[0x10];
e281682b 3910
b4ff3a36 3911 u8 reserved_at_20[0x10];
e281682b
SM		 3912 u8 op_mod[0x10];
3913
b4ff3a36 3914 u8 reserved_at_40[0x8];
e281682b
SM		 3915 u8 sqn[0x18];
3916
b4ff3a36 3917 u8 reserved_at_60[0x20];
e281682b
SM		 3918};
3919
3920struct mlx5_ifc_query_special_contexts_out_bits {
3921 u8 status[0x8];
b4ff3a36 3922 u8 reserved_at_8[0x18];
e281682b
SM		 3923
3924 u8 syndrome[0x20];
3925
ec22eb53 3926 u8 dump_fill_mkey[0x20];
e281682b
SM		 3927
3928 u8 resd_lkey[0x20];
bcda1aca
AK		 3929
3930 u8 null_mkey[0x20];
3931
3932 u8 reserved_at_a0[0x60];
e281682b
SM		 3933};
3934
3935struct mlx5_ifc_query_special_contexts_in_bits {
3936 u8 opcode[0x10];
b4ff3a36 3937 u8 reserved_at_10[0x10];
e281682b 3938
b4ff3a36 3939 u8 reserved_at_20[0x10];
e281682b
SM		 3940 u8 op_mod[0x10];
3941
b4ff3a36 3942 u8 reserved_at_40[0x40];
e281682b
SM		 3943};
3944
813f8540
MHY		 3945struct mlx5_ifc_query_scheduling_element_out_bits {
3946 u8 opcode[0x10];
3947 u8 reserved_at_10[0x10];
3948
3949 u8 reserved_at_20[0x10];
3950 u8 op_mod[0x10];
3951
3952 u8 reserved_at_40[0xc0];
3953
3954 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3955
3956 u8 reserved_at_300[0x100];
3957};
3958
3959enum {
3960 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3961};
3962
3963struct mlx5_ifc_query_scheduling_element_in_bits {
3964 u8 opcode[0x10];
3965 u8 reserved_at_10[0x10];
3966
3967 u8 reserved_at_20[0x10];
3968 u8 op_mod[0x10];
3969
3970 u8 scheduling_hierarchy[0x8];
3971 u8 reserved_at_48[0x18];
3972
3973 u8 scheduling_element_id[0x20];
3974
3975 u8 reserved_at_80[0x180];
3976};
3977
e281682b
SM		 3978struct mlx5_ifc_query_rqt_out_bits {
3979 u8 status[0x8];
b4ff3a36 3980 u8 reserved_at_8[0x18];
e281682b
SM		 3981
3982 u8 syndrome[0x20];
3983
b4ff3a36 3984 u8 reserved_at_40[0xc0];
e281682b
SM		 3985
3986 struct mlx5_ifc_rqtc_bits rqt_context;
3987};
3988
3989struct mlx5_ifc_query_rqt_in_bits {
3990 u8 opcode[0x10];
b4ff3a36 3991 u8 reserved_at_10[0x10];
e281682b 3992
b4ff3a36 3993 u8 reserved_at_20[0x10];
e281682b
SM		 3994 u8 op_mod[0x10];
3995
b4ff3a36 3996 u8 reserved_at_40[0x8];
e281682b
SM		 3997 u8 rqtn[0x18];
3998
b4ff3a36 3999 u8 reserved_at_60[0x20];
e281682b
SM		 4000};
4001
4002struct mlx5_ifc_query_rq_out_bits {
4003 u8 status[0x8];
b4ff3a36 4004 u8 reserved_at_8[0x18];
e281682b
SM		 4005
4006 u8 syndrome[0x20];
4007
b4ff3a36 4008 u8 reserved_at_40[0xc0];
e281682b
SM		 4009
4010 struct mlx5_ifc_rqc_bits rq_context;
4011};
4012
4013struct mlx5_ifc_query_rq_in_bits {
4014 u8 opcode[0x10];
b4ff3a36 4015 u8 reserved_at_10[0x10];
e281682b 4016
b4ff3a36 4017 u8 reserved_at_20[0x10];
e281682b
SM		 4018 u8 op_mod[0x10];
4019
b4ff3a36 4020 u8 reserved_at_40[0x8];
e281682b
SM		 4021 u8 rqn[0x18];
4022
b4ff3a36 4023 u8 reserved_at_60[0x20];
e281682b
SM		 4024};
4025
4026struct mlx5_ifc_query_roce_address_out_bits {
4027 u8 status[0x8];
b4ff3a36 4028 u8 reserved_at_8[0x18];
e281682b
SM		 4029
4030 u8 syndrome[0x20];
4031
b4ff3a36 4032 u8 reserved_at_40[0x40];
e281682b
SM		 4033
4034 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4035};
4036
4037struct mlx5_ifc_query_roce_address_in_bits {
4038 u8 opcode[0x10];
b4ff3a36 4039 u8 reserved_at_10[0x10];
e281682b 4040
b4ff3a36 4041 u8 reserved_at_20[0x10];
e281682b
SM		 4042 u8 op_mod[0x10];
4043
4044 u8 roce_address_index[0x10];
32f69e4b
DJ		 4045 u8 reserved_at_50[0xc];
4046 u8 vhca_port_num[0x4];
e281682b 4047
b4ff3a36 4048 u8 reserved_at_60[0x20];
e281682b
SM		 4049};
4050
4051struct mlx5_ifc_query_rmp_out_bits {
4052 u8 status[0x8];
b4ff3a36 4053 u8 reserved_at_8[0x18];
e281682b
SM		 4054
4055 u8 syndrome[0x20];
4056
b4ff3a36 4057 u8 reserved_at_40[0xc0];
e281682b
SM		 4058
4059 struct mlx5_ifc_rmpc_bits rmp_context;
4060};
4061
4062struct mlx5_ifc_query_rmp_in_bits {
4063 u8 opcode[0x10];
b4ff3a36 4064 u8 reserved_at_10[0x10];
e281682b 4065
b4ff3a36 4066 u8 reserved_at_20[0x10];
e281682b
SM		 4067 u8 op_mod[0x10];
4068
b4ff3a36 4069 u8 reserved_at_40[0x8];
e281682b
SM		 4070 u8 rmpn[0x18];
4071
b4ff3a36 4072 u8 reserved_at_60[0x20];
e281682b
SM		 4073};
4074
4075struct mlx5_ifc_query_qp_out_bits {
4076 u8 status[0x8];
b4ff3a36 4077 u8 reserved_at_8[0x18];
e281682b
SM		 4078
4079 u8 syndrome[0x20];
4080
b4ff3a36 4081 u8 reserved_at_40[0x40];
e281682b
SM		 4082
4083 u8 opt_param_mask[0x20];
4084
b4ff3a36 4085 u8 reserved_at_a0[0x20];
e281682b
SM		 4086
4087 struct mlx5_ifc_qpc_bits qpc;
4088
b4ff3a36 4089 u8 reserved_at_800[0x80];
e281682b
SM		 4090
4091 u8 pas[0][0x40];
4092};
4093
4094struct mlx5_ifc_query_qp_in_bits {
4095 u8 opcode[0x10];
b4ff3a36 4096 u8 reserved_at_10[0x10];
e281682b 4097
b4ff3a36 4098 u8 reserved_at_20[0x10];
e281682b
SM		 4099 u8 op_mod[0x10];
4100
b4ff3a36 4101 u8 reserved_at_40[0x8];
e281682b
SM		 4102 u8 qpn[0x18];
4103
b4ff3a36 4104 u8 reserved_at_60[0x20];
e281682b
SM		 4105};
4106
4107struct mlx5_ifc_query_q_counter_out_bits {
4108 u8 status[0x8];
b4ff3a36 4109 u8 reserved_at_8[0x18];
e281682b
SM		 4110
4111 u8 syndrome[0x20];
4112
b4ff3a36 4113 u8 reserved_at_40[0x40];
e281682b
SM		 4114
4115 u8 rx_write_requests[0x20];
4116
b4ff3a36 4117 u8 reserved_at_a0[0x20];
e281682b
SM		 4118
4119 u8 rx_read_requests[0x20];
4120
b4ff3a36 4121 u8 reserved_at_e0[0x20];
e281682b
SM		 4122
4123 u8 rx_atomic_requests[0x20];
4124
b4ff3a36 4125 u8 reserved_at_120[0x20];
e281682b
SM		 4126
4127 u8 rx_dct_connect[0x20];
4128
b4ff3a36 4129 u8 reserved_at_160[0x20];
e281682b
SM		 4130
4131 u8 out_of_buffer[0x20];
4132
b4ff3a36 4133 u8 reserved_at_1a0[0x20];
e281682b
SM		 4134
4135 u8 out_of_sequence[0x20];
4136
7486216b
SM		 4137 u8 reserved_at_1e0[0x20];
4138
4139 u8 duplicate_request[0x20];
4140
4141 u8 reserved_at_220[0x20];
4142
4143 u8 rnr_nak_retry_err[0x20];
4144
4145 u8 reserved_at_260[0x20];
4146
4147 u8 packet_seq_err[0x20];
4148
4149 u8 reserved_at_2a0[0x20];
4150
4151 u8 implied_nak_seq_err[0x20];
4152
4153 u8 reserved_at_2e0[0x20];
4154
4155 u8 local_ack_timeout_err[0x20];
4156
58dcb60a
PP		 4157 u8 reserved_at_320[0xa0];
4158
4159 u8 resp_local_length_error[0x20];
4160
4161 u8 req_local_length_error[0x20];
4162
4163 u8 resp_local_qp_error[0x20];
4164
4165 u8 local_operation_error[0x20];
4166
4167 u8 resp_local_protection[0x20];
4168
4169 u8 req_local_protection[0x20];
4170
4171 u8 resp_cqe_error[0x20];
4172
4173 u8 req_cqe_error[0x20];
4174
4175 u8 req_mw_binding[0x20];
4176
4177 u8 req_bad_response[0x20];
4178
4179 u8 req_remote_invalid_request[0x20];
4180
4181 u8 resp_remote_invalid_request[0x20];
4182
4183 u8 req_remote_access_errors[0x20];
4184
4185 u8 resp_remote_access_errors[0x20];
4186
4187 u8 req_remote_operation_errors[0x20];
4188
4189 u8 req_transport_retries_exceeded[0x20];
4190
4191 u8 cq_overflow[0x20];
4192
4193 u8 resp_cqe_flush_error[0x20];
4194
4195 u8 req_cqe_flush_error[0x20];
4196
4197 u8 reserved_at_620[0x1e0];
e281682b
SM		 4198};
4199
4200struct mlx5_ifc_query_q_counter_in_bits {
4201 u8 opcode[0x10];
b4ff3a36 4202 u8 reserved_at_10[0x10];
e281682b 4203
b4ff3a36 4204 u8 reserved_at_20[0x10];
e281682b
SM		 4205 u8 op_mod[0x10];
4206
b4ff3a36 4207 u8 reserved_at_40[0x80];
e281682b
SM		 4208
4209 u8 clear[0x1];
b4ff3a36 4210 u8 reserved_at_c1[0x1f];
e281682b 4211
b4ff3a36 4212 u8 reserved_at_e0[0x18];
e281682b
SM		 4213 u8 counter_set_id[0x8];
4214};
4215
4216struct mlx5_ifc_query_pages_out_bits {
4217 u8 status[0x8];
b4ff3a36 4218 u8 reserved_at_8[0x18];
e281682b
SM		 4219
4220 u8 syndrome[0x20];
4221
b4ff3a36 4222 u8 reserved_at_40[0x10];
e281682b
SM		 4223 u8 function_id[0x10];
4224
4225 u8 num_pages[0x20];
4226};
4227
4228enum {
4229 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4230 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4231 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4232};
4233
4234struct mlx5_ifc_query_pages_in_bits {
4235 u8 opcode[0x10];
b4ff3a36 4236 u8 reserved_at_10[0x10];
e281682b 4237
b4ff3a36 4238 u8 reserved_at_20[0x10];
e281682b
SM		 4239 u8 op_mod[0x10];
4240
b4ff3a36 4241 u8 reserved_at_40[0x10];
e281682b
SM		 4242 u8 function_id[0x10];
4243
b4ff3a36 4244 u8 reserved_at_60[0x20];
e281682b
SM		 4245};
4246
4247struct mlx5_ifc_query_nic_vport_context_out_bits {
4248 u8 status[0x8];
b4ff3a36 4249 u8 reserved_at_8[0x18];
e281682b
SM		 4250
4251 u8 syndrome[0x20];
4252
b4ff3a36 4253 u8 reserved_at_40[0x40];
e281682b
SM		 4254
4255 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4256};
4257
4258struct mlx5_ifc_query_nic_vport_context_in_bits {
4259 u8 opcode[0x10];
b4ff3a36 4260 u8 reserved_at_10[0x10];
e281682b 4261
b4ff3a36 4262 u8 reserved_at_20[0x10];
e281682b
SM		 4263 u8 op_mod[0x10];
4264
4265 u8 other_vport[0x1];
b4ff3a36 4266 u8 reserved_at_41[0xf];
e281682b
SM		 4267 u8 vport_number[0x10];
4268
b4ff3a36 4269 u8 reserved_at_60[0x5];
e281682b 4270 u8 allowed_list_type[0x3];
b4ff3a36 4271 u8 reserved_at_68[0x18];
e281682b
SM		 4272};
4273
4274struct mlx5_ifc_query_mkey_out_bits {
4275 u8 status[0x8];
b4ff3a36 4276 u8 reserved_at_8[0x18];
e281682b
SM		 4277
4278 u8 syndrome[0x20];
4279
b4ff3a36 4280 u8 reserved_at_40[0x40];
e281682b
SM		 4281
4282 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4283
b4ff3a36 4284 u8 reserved_at_280[0x600];
e281682b
SM		 4285
4286 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4287
4288 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4289};
4290
4291struct mlx5_ifc_query_mkey_in_bits {
4292 u8 opcode[0x10];
b4ff3a36 4293 u8 reserved_at_10[0x10];
e281682b 4294
b4ff3a36 4295 u8 reserved_at_20[0x10];
e281682b
SM		 4296 u8 op_mod[0x10];
4297
b4ff3a36 4298 u8 reserved_at_40[0x8];
e281682b
SM		 4299 u8 mkey_index[0x18];
4300
4301 u8 pg_access[0x1];
b4ff3a36 4302 u8 reserved_at_61[0x1f];
e281682b
SM		 4303};
4304
4305struct mlx5_ifc_query_mad_demux_out_bits {
4306 u8 status[0x8];
b4ff3a36 4307 u8 reserved_at_8[0x18];
e281682b
SM		 4308
4309 u8 syndrome[0x20];
4310
b4ff3a36 4311 u8 reserved_at_40[0x40];
e281682b
SM		 4312
4313 u8 mad_dumux_parameters_block[0x20];
4314};
4315
4316struct mlx5_ifc_query_mad_demux_in_bits {
4317 u8 opcode[0x10];
b4ff3a36 4318 u8 reserved_at_10[0x10];
e281682b 4319
b4ff3a36 4320 u8 reserved_at_20[0x10];
e281682b
SM		 4321 u8 op_mod[0x10];
4322
b4ff3a36 4323 u8 reserved_at_40[0x40];
e281682b
SM		 4324};
4325
4326struct mlx5_ifc_query_l2_table_entry_out_bits {
4327 u8 status[0x8];
b4ff3a36 4328 u8 reserved_at_8[0x18];
e281682b
SM		 4329
4330 u8 syndrome[0x20];
4331
b4ff3a36 4332 u8 reserved_at_40[0xa0];
e281682b 4333
b4ff3a36 4334 u8 reserved_at_e0[0x13];
e281682b
SM		 4335 u8 vlan_valid[0x1];
4336 u8 vlan[0xc];
4337
4338 struct mlx5_ifc_mac_address_layout_bits mac_address;
4339
b4ff3a36 4340 u8 reserved_at_140[0xc0];
e281682b
SM		 4341};
4342
4343struct mlx5_ifc_query_l2_table_entry_in_bits {
4344 u8 opcode[0x10];
b4ff3a36 4345 u8 reserved_at_10[0x10];
e281682b 4346
b4ff3a36 4347 u8 reserved_at_20[0x10];
e281682b
SM		 4348 u8 op_mod[0x10];
4349
b4ff3a36 4350 u8 reserved_at_40[0x60];
e281682b 4351
b4ff3a36 4352 u8 reserved_at_a0[0x8];
e281682b
SM		 4353 u8 table_index[0x18];
4354
b4ff3a36 4355 u8 reserved_at_c0[0x140];
e281682b
SM		 4356};
4357
4358struct mlx5_ifc_query_issi_out_bits {
4359 u8 status[0x8];
b4ff3a36 4360 u8 reserved_at_8[0x18];
e281682b
SM		 4361
4362 u8 syndrome[0x20];
4363
b4ff3a36 4364 u8 reserved_at_40[0x10];
e281682b
SM		 4365 u8 current_issi[0x10];
4366
b4ff3a36 4367 u8 reserved_at_60[0xa0];
e281682b 4368
b4ff3a36 4369 u8 reserved_at_100[76][0x8];
e281682b
SM		 4370 u8 supported_issi_dw0[0x20];
4371};
4372
4373struct mlx5_ifc_query_issi_in_bits {
4374 u8 opcode[0x10];
b4ff3a36 4375 u8 reserved_at_10[0x10];
e281682b 4376
b4ff3a36 4377 u8 reserved_at_20[0x10];
e281682b
SM		 4378 u8 op_mod[0x10];
4379
b4ff3a36 4380 u8 reserved_at_40[0x40];
e281682b
SM		 4381};
4382
0dbc6fe0
SM		 4383struct mlx5_ifc_set_driver_version_out_bits {
4384 u8 status[0x8];
4385 u8 reserved_0[0x18];
4386
4387 u8 syndrome[0x20];
4388 u8 reserved_1[0x40];
4389};
4390
4391struct mlx5_ifc_set_driver_version_in_bits {
4392 u8 opcode[0x10];
4393 u8 reserved_0[0x10];
4394
4395 u8 reserved_1[0x10];
4396 u8 op_mod[0x10];
4397
4398 u8 reserved_2[0x40];
4399 u8 driver_version[64][0x8];
4400};
4401
e281682b
SM		 4402struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4403 u8 status[0x8];
b4ff3a36 4404 u8 reserved_at_8[0x18];
e281682b
SM		 4405
4406 u8 syndrome[0x20];
4407
b4ff3a36 4408 u8 reserved_at_40[0x40];
e281682b
SM		 4409
4410 struct mlx5_ifc_pkey_bits pkey[0];
4411};
4412
4413struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4414 u8 opcode[0x10];
b4ff3a36 4415 u8 reserved_at_10[0x10];
e281682b 4416
b4ff3a36 4417 u8 reserved_at_20[0x10];
e281682b
SM		 4418 u8 op_mod[0x10];
4419
4420 u8 other_vport[0x1];
b4ff3a36 4421 u8 reserved_at_41[0xb];
707c4602 4422 u8 port_num[0x4];
e281682b
SM		 4423 u8 vport_number[0x10];
4424
b4ff3a36 4425 u8 reserved_at_60[0x10];
e281682b
SM		 4426 u8 pkey_index[0x10];
4427};
4428
eff901d3
EC		 4429enum {
4430 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4431 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4432 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4433};
4434
e281682b
SM		 4435struct mlx5_ifc_query_hca_vport_gid_out_bits {
4436 u8 status[0x8];
b4ff3a36 4437 u8 reserved_at_8[0x18];
e281682b
SM		 4438
4439 u8 syndrome[0x20];
4440
b4ff3a36 4441 u8 reserved_at_40[0x20];
e281682b
SM		 4442
4443 u8 gids_num[0x10];
b4ff3a36 4444 u8 reserved_at_70[0x10];
e281682b
SM		 4445
4446 struct mlx5_ifc_array128_auto_bits gid[0];
4447};
4448
4449struct mlx5_ifc_query_hca_vport_gid_in_bits {
4450 u8 opcode[0x10];
b4ff3a36 4451 u8 reserved_at_10[0x10];
e281682b 4452
b4ff3a36 4453 u8 reserved_at_20[0x10];
e281682b
SM		 4454 u8 op_mod[0x10];
4455
4456 u8 other_vport[0x1];
b4ff3a36 4457 u8 reserved_at_41[0xb];
707c4602 4458 u8 port_num[0x4];
e281682b
SM		 4459 u8 vport_number[0x10];
4460
b4ff3a36 4461 u8 reserved_at_60[0x10];
e281682b
SM		 4462 u8 gid_index[0x10];
4463};
4464
4465struct mlx5_ifc_query_hca_vport_context_out_bits {
4466 u8 status[0x8];
b4ff3a36 4467 u8 reserved_at_8[0x18];
e281682b
SM		 4468
4469 u8 syndrome[0x20];
4470
b4ff3a36 4471 u8 reserved_at_40[0x40];
e281682b
SM		 4472
4473 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4474};
4475
4476struct mlx5_ifc_query_hca_vport_context_in_bits {
4477 u8 opcode[0x10];
b4ff3a36 4478 u8 reserved_at_10[0x10];
e281682b 4479
b4ff3a36 4480 u8 reserved_at_20[0x10];
e281682b
SM		 4481 u8 op_mod[0x10];
4482
4483 u8 other_vport[0x1];
b4ff3a36 4484 u8 reserved_at_41[0xb];
707c4602 4485 u8 port_num[0x4];
e281682b
SM		 4486 u8 vport_number[0x10];
4487
b4ff3a36 4488 u8 reserved_at_60[0x20];
e281682b
SM		 4489};
4490
4491struct mlx5_ifc_query_hca_cap_out_bits {
4492 u8 status[0x8];
b4ff3a36 4493 u8 reserved_at_8[0x18];
e281682b
SM		 4494
4495 u8 syndrome[0x20];
4496
b4ff3a36 4497 u8 reserved_at_40[0x40];
e281682b
SM		 4498
4499 union mlx5_ifc_hca_cap_union_bits capability;
4500};
4501
4502struct mlx5_ifc_query_hca_cap_in_bits {
4503 u8 opcode[0x10];
b4ff3a36 4504 u8 reserved_at_10[0x10];
e281682b 4505
b4ff3a36 4506 u8 reserved_at_20[0x10];
e281682b
SM		 4507 u8 op_mod[0x10];
4508
b4ff3a36 4509 u8 reserved_at_40[0x40];
e281682b
SM		 4510};
4511
4512struct mlx5_ifc_query_flow_table_out_bits {
4513 u8 status[0x8];
b4ff3a36 4514 u8 reserved_at_8[0x18];
e281682b
SM		 4515
4516 u8 syndrome[0x20];
4517
b4ff3a36 4518 u8 reserved_at_40[0x80];
e281682b 4519
b4ff3a36 4520 u8 reserved_at_c0[0x8];
e281682b 4521 u8 level[0x8];
b4ff3a36 4522 u8 reserved_at_d0[0x8];
e281682b
SM		 4523 u8 log_size[0x8];
4524
b4ff3a36 4525 u8 reserved_at_e0[0x120];
e281682b
SM		 4526};
4527
4528struct mlx5_ifc_query_flow_table_in_bits {
4529 u8 opcode[0x10];
b4ff3a36 4530 u8 reserved_at_10[0x10];
e281682b 4531
b4ff3a36 4532 u8 reserved_at_20[0x10];
e281682b
SM		 4533 u8 op_mod[0x10];
4534
b4ff3a36 4535 u8 reserved_at_40[0x40];
e281682b
SM		 4536
4537 u8 table_type[0x8];
b4ff3a36 4538 u8 reserved_at_88[0x18];
e281682b 4539
b4ff3a36 4540 u8 reserved_at_a0[0x8];
e281682b
SM		 4541 u8 table_id[0x18];
4542
b4ff3a36 4543 u8 reserved_at_c0[0x140];
e281682b
SM		 4544};
4545
4546struct mlx5_ifc_query_fte_out_bits {
4547 u8 status[0x8];
b4ff3a36 4548 u8 reserved_at_8[0x18];
e281682b
SM		 4549
4550 u8 syndrome[0x20];
4551
b4ff3a36 4552 u8 reserved_at_40[0x1c0];
e281682b
SM		 4553
4554 struct mlx5_ifc_flow_context_bits flow_context;
4555};
4556
4557struct mlx5_ifc_query_fte_in_bits {
4558 u8 opcode[0x10];
b4ff3a36 4559 u8 reserved_at_10[0x10];
e281682b 4560
b4ff3a36 4561 u8 reserved_at_20[0x10];
e281682b
SM		 4562 u8 op_mod[0x10];
4563
b4ff3a36 4564 u8 reserved_at_40[0x40];
e281682b
SM		 4565
4566 u8 table_type[0x8];
b4ff3a36 4567 u8 reserved_at_88[0x18];
e281682b 4568
b4ff3a36 4569 u8 reserved_at_a0[0x8];
e281682b
SM		 4570 u8 table_id[0x18];
4571
b4ff3a36 4572 u8 reserved_at_c0[0x40];
e281682b
SM		 4573
4574 u8 flow_index[0x20];
4575
b4ff3a36 4576 u8 reserved_at_120[0xe0];
e281682b
SM		 4577};
4578
4579enum {
4580 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4581 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4582 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4583};
4584
4585struct mlx5_ifc_query_flow_group_out_bits {
4586 u8 status[0x8];
b4ff3a36 4587 u8 reserved_at_8[0x18];
e281682b
SM		 4588
4589 u8 syndrome[0x20];
4590
b4ff3a36 4591 u8 reserved_at_40[0xa0];
e281682b
SM		 4592
4593 u8 start_flow_index[0x20];
4594
b4ff3a36 4595 u8 reserved_at_100[0x20];
e281682b
SM		 4596
4597 u8 end_flow_index[0x20];
4598
b4ff3a36 4599 u8 reserved_at_140[0xa0];
e281682b 4600
b4ff3a36 4601 u8 reserved_at_1e0[0x18];
e281682b
SM		 4602 u8 match_criteria_enable[0x8];
4603
4604 struct mlx5_ifc_fte_match_param_bits match_criteria;
4605
b4ff3a36 4606 u8 reserved_at_1200[0xe00];
e281682b
SM		 4607};
4608
4609struct mlx5_ifc_query_flow_group_in_bits {
4610 u8 opcode[0x10];
b4ff3a36 4611 u8 reserved_at_10[0x10];
e281682b 4612
b4ff3a36 4613 u8 reserved_at_20[0x10];
e281682b
SM		 4614 u8 op_mod[0x10];
4615
b4ff3a36 4616 u8 reserved_at_40[0x40];
e281682b
SM		 4617
4618 u8 table_type[0x8];
b4ff3a36 4619 u8 reserved_at_88[0x18];
e281682b 4620
b4ff3a36 4621 u8 reserved_at_a0[0x8];
e281682b
SM		 4622 u8 table_id[0x18];
4623
4624 u8 group_id[0x20];
4625
b4ff3a36 4626 u8 reserved_at_e0[0x120];
e281682b
SM		 4627};
4628
9dc0b289
AV		 4629struct mlx5_ifc_query_flow_counter_out_bits {
4630 u8 status[0x8];
4631 u8 reserved_at_8[0x18];
4632
4633 u8 syndrome[0x20];
4634
4635 u8 reserved_at_40[0x40];
4636
4637 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4638};
4639
4640struct mlx5_ifc_query_flow_counter_in_bits {
4641 u8 opcode[0x10];
4642 u8 reserved_at_10[0x10];
4643
4644 u8 reserved_at_20[0x10];
4645 u8 op_mod[0x10];
4646
4647 u8 reserved_at_40[0x80];
4648
4649 u8 clear[0x1];
4650 u8 reserved_at_c1[0xf];
4651 u8 num_of_counters[0x10];
4652
a8ffcc74 4653 u8 flow_counter_id[0x20];
9dc0b289
AV		 4654};
4655
d6666753
SM		 4656struct mlx5_ifc_query_esw_vport_context_out_bits {
4657 u8 status[0x8];
b4ff3a36 4658 u8 reserved_at_8[0x18];
d6666753
SM		 4659
4660 u8 syndrome[0x20];
4661
b4ff3a36 4662 u8 reserved_at_40[0x40];
d6666753
SM		 4663
4664 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4665};
4666
4667struct mlx5_ifc_query_esw_vport_context_in_bits {
4668 u8 opcode[0x10];
b4ff3a36 4669 u8 reserved_at_10[0x10];
d6666753 4670
b4ff3a36 4671 u8 reserved_at_20[0x10];
d6666753
SM		 4672 u8 op_mod[0x10];
4673
4674 u8 other_vport[0x1];
b4ff3a36 4675 u8 reserved_at_41[0xf];
d6666753
SM		 4676 u8 vport_number[0x10];
4677
b4ff3a36 4678 u8 reserved_at_60[0x20];
d6666753
SM		 4679};
4680
4681struct mlx5_ifc_modify_esw_vport_context_out_bits {
4682 u8 status[0x8];
b4ff3a36 4683 u8 reserved_at_8[0x18];
d6666753
SM		 4684
4685 u8 syndrome[0x20];
4686
b4ff3a36 4687 u8 reserved_at_40[0x40];
d6666753
SM		 4688};
4689
4690struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4691 u8 reserved_at_0[0x1c];
d6666753
SM		 4692 u8 vport_cvlan_insert[0x1];
4693 u8 vport_svlan_insert[0x1];
4694 u8 vport_cvlan_strip[0x1];
4695 u8 vport_svlan_strip[0x1];
4696};
4697
4698struct mlx5_ifc_modify_esw_vport_context_in_bits {
4699 u8 opcode[0x10];
b4ff3a36 4700 u8 reserved_at_10[0x10];
d6666753 4701
b4ff3a36 4702 u8 reserved_at_20[0x10];
d6666753
SM		 4703 u8 op_mod[0x10];
4704
4705 u8 other_vport[0x1];
b4ff3a36 4706 u8 reserved_at_41[0xf];
d6666753
SM		 4707 u8 vport_number[0x10];
4708
4709 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4710
4711 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4712};
4713
e281682b
SM		 4714struct mlx5_ifc_query_eq_out_bits {
4715 u8 status[0x8];
b4ff3a36 4716 u8 reserved_at_8[0x18];
e281682b
SM		 4717
4718 u8 syndrome[0x20];
4719
b4ff3a36 4720 u8 reserved_at_40[0x40];
e281682b
SM		 4721
4722 struct mlx5_ifc_eqc_bits eq_context_entry;
4723
b4ff3a36 4724 u8 reserved_at_280[0x40];
e281682b
SM		 4725
4726 u8 event_bitmask[0x40];
4727
b4ff3a36 4728 u8 reserved_at_300[0x580];
e281682b
SM		 4729
4730 u8 pas[0][0x40];
4731};
4732
4733struct mlx5_ifc_query_eq_in_bits {
4734 u8 opcode[0x10];
b4ff3a36 4735 u8 reserved_at_10[0x10];
e281682b 4736
b4ff3a36 4737 u8 reserved_at_20[0x10];
e281682b
SM		 4738 u8 op_mod[0x10];
4739
b4ff3a36 4740 u8 reserved_at_40[0x18];
e281682b
SM		 4741 u8 eq_number[0x8];
4742
b4ff3a36 4743 u8 reserved_at_60[0x20];
e281682b
SM		 4744};
4745
7adbde20
HHZ		 4746struct mlx5_ifc_encap_header_in_bits {
4747 u8 reserved_at_0[0x5];
4748 u8 header_type[0x3];
4749 u8 reserved_at_8[0xe];
4750 u8 encap_header_size[0xa];
4751
4752 u8 reserved_at_20[0x10];
4753 u8 encap_header[2][0x8];
4754
4755 u8 more_encap_header[0][0x8];
4756};
4757
4758struct mlx5_ifc_query_encap_header_out_bits {
4759 u8 status[0x8];
4760 u8 reserved_at_8[0x18];
4761
4762 u8 syndrome[0x20];
4763
4764 u8 reserved_at_40[0xa0];
4765
4766 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4767};
4768
4769struct mlx5_ifc_query_encap_header_in_bits {
4770 u8 opcode[0x10];
4771 u8 reserved_at_10[0x10];
4772
4773 u8 reserved_at_20[0x10];
4774 u8 op_mod[0x10];
4775
4776 u8 encap_id[0x20];
4777
4778 u8 reserved_at_60[0xa0];
4779};
4780
4781struct mlx5_ifc_alloc_encap_header_out_bits {
4782 u8 status[0x8];
4783 u8 reserved_at_8[0x18];
4784
4785 u8 syndrome[0x20];
4786
4787 u8 encap_id[0x20];
4788
4789 u8 reserved_at_60[0x20];
4790};
4791
4792struct mlx5_ifc_alloc_encap_header_in_bits {
4793 u8 opcode[0x10];
4794 u8 reserved_at_10[0x10];
4795
4796 u8 reserved_at_20[0x10];
4797 u8 op_mod[0x10];
4798
4799 u8 reserved_at_40[0xa0];
4800
4801 struct mlx5_ifc_encap_header_in_bits encap_header;
4802};
4803
4804struct mlx5_ifc_dealloc_encap_header_out_bits {
4805 u8 status[0x8];
4806 u8 reserved_at_8[0x18];
4807
4808 u8 syndrome[0x20];
4809
4810 u8 reserved_at_40[0x40];
4811};
4812
4813struct mlx5_ifc_dealloc_encap_header_in_bits {
4814 u8 opcode[0x10];
4815 u8 reserved_at_10[0x10];
4816
4817 u8 reserved_20[0x10];
4818 u8 op_mod[0x10];
4819
4820 u8 encap_id[0x20];
4821
4822 u8 reserved_60[0x20];
4823};
4824
2a69cb9f
OG		 4825struct mlx5_ifc_set_action_in_bits {
4826 u8 action_type[0x4];
4827 u8 field[0xc];
4828 u8 reserved_at_10[0x3];
4829 u8 offset[0x5];
4830 u8 reserved_at_18[0x3];
4831 u8 length[0x5];
4832
4833 u8 data[0x20];
4834};
4835
4836struct mlx5_ifc_add_action_in_bits {
4837 u8 action_type[0x4];
4838 u8 field[0xc];
4839 u8 reserved_at_10[0x10];
4840
4841 u8 data[0x20];
4842};
4843
4844union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4845 struct mlx5_ifc_set_action_in_bits set_action_in;
4846 struct mlx5_ifc_add_action_in_bits add_action_in;
4847 u8 reserved_at_0[0x40];
4848};
4849
4850enum {
4851 MLX5_ACTION_TYPE_SET = 0x1,
4852 MLX5_ACTION_TYPE_ADD = 0x2,
4853};
4854
4855enum {
4856 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4857 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4858 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4859 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4860 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4861 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4862 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4863 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4864 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4865 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4866 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4867 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4868 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4869 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4870 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4871 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4872 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4873 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4874 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4875 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4876 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4877 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4878 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4879};
4880
4881struct mlx5_ifc_alloc_modify_header_context_out_bits {
4882 u8 status[0x8];
4883 u8 reserved_at_8[0x18];
4884
4885 u8 syndrome[0x20];
4886
4887 u8 modify_header_id[0x20];
4888
4889 u8 reserved_at_60[0x20];
4890};
4891
4892struct mlx5_ifc_alloc_modify_header_context_in_bits {
4893 u8 opcode[0x10];
4894 u8 reserved_at_10[0x10];
4895
4896 u8 reserved_at_20[0x10];
4897 u8 op_mod[0x10];
4898
4899 u8 reserved_at_40[0x20];
4900
4901 u8 table_type[0x8];
4902 u8 reserved_at_68[0x10];
4903 u8 num_of_actions[0x8];
4904
4905 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4906};
4907
4908struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4909 u8 status[0x8];
4910 u8 reserved_at_8[0x18];
4911
4912 u8 syndrome[0x20];
4913
4914 u8 reserved_at_40[0x40];
4915};
4916
4917struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4918 u8 opcode[0x10];
4919 u8 reserved_at_10[0x10];
4920
4921 u8 reserved_at_20[0x10];
4922 u8 op_mod[0x10];
4923
4924 u8 modify_header_id[0x20];
4925
4926 u8 reserved_at_60[0x20];
4927};
4928
e281682b
SM		 4929struct mlx5_ifc_query_dct_out_bits {
4930 u8 status[0x8];
b4ff3a36 4931 u8 reserved_at_8[0x18];
e281682b
SM		 4932
4933 u8 syndrome[0x20];
4934
b4ff3a36 4935 u8 reserved_at_40[0x40];
e281682b
SM		 4936
4937 struct mlx5_ifc_dctc_bits dct_context_entry;
4938
b4ff3a36 4939 u8 reserved_at_280[0x180];
e281682b
SM		 4940};
4941
4942struct mlx5_ifc_query_dct_in_bits {
4943 u8 opcode[0x10];
b4ff3a36 4944 u8 reserved_at_10[0x10];
e281682b 4945
b4ff3a36 4946 u8 reserved_at_20[0x10];
e281682b
SM		 4947 u8 op_mod[0x10];
4948
b4ff3a36 4949 u8 reserved_at_40[0x8];
e281682b
SM		 4950 u8 dctn[0x18];
4951
b4ff3a36 4952 u8 reserved_at_60[0x20];
e281682b
SM		 4953};
4954
4955struct mlx5_ifc_query_cq_out_bits {
4956 u8 status[0x8];
b4ff3a36 4957 u8 reserved_at_8[0x18];
e281682b
SM		 4958
4959 u8 syndrome[0x20];
4960
b4ff3a36 4961 u8 reserved_at_40[0x40];
e281682b
SM		 4962
4963 struct mlx5_ifc_cqc_bits cq_context;
4964
b4ff3a36 4965 u8 reserved_at_280[0x600];
e281682b
SM		 4966
4967 u8 pas[0][0x40];
4968};
4969
4970struct mlx5_ifc_query_cq_in_bits {
4971 u8 opcode[0x10];
b4ff3a36 4972 u8 reserved_at_10[0x10];
e281682b 4973
b4ff3a36 4974 u8 reserved_at_20[0x10];
e281682b
SM		 4975 u8 op_mod[0x10];
4976
b4ff3a36 4977 u8 reserved_at_40[0x8];
e281682b
SM		 4978 u8 cqn[0x18];
4979
b4ff3a36 4980 u8 reserved_at_60[0x20];
e281682b
SM		 4981};
4982
4983struct mlx5_ifc_query_cong_status_out_bits {
4984 u8 status[0x8];
b4ff3a36 4985 u8 reserved_at_8[0x18];
e281682b
SM		 4986
4987 u8 syndrome[0x20];
4988
b4ff3a36 4989 u8 reserved_at_40[0x20];
e281682b
SM		 4990
4991 u8 enable[0x1];
4992 u8 tag_enable[0x1];
b4ff3a36 4993 u8 reserved_at_62[0x1e];
e281682b
SM		 4994};
4995
4996struct mlx5_ifc_query_cong_status_in_bits {
4997 u8 opcode[0x10];
b4ff3a36 4998 u8 reserved_at_10[0x10];
e281682b 4999
b4ff3a36 5000 u8 reserved_at_20[0x10];
e281682b
SM		 5001 u8 op_mod[0x10];
5002
b4ff3a36 5003 u8 reserved_at_40[0x18];
e281682b
SM		 5004 u8 priority[0x4];
5005 u8 cong_protocol[0x4];
5006
b4ff3a36 5007 u8 reserved_at_60[0x20];
e281682b
SM		 5008};
5009
5010struct mlx5_ifc_query_cong_statistics_out_bits {
5011 u8 status[0x8];
b4ff3a36 5012 u8 reserved_at_8[0x18];
e281682b
SM		 5013
5014 u8 syndrome[0x20];
5015
b4ff3a36 5016 u8 reserved_at_40[0x40];
e281682b 5017
e1f24a79 5018 u8 rp_cur_flows[0x20];
e281682b
SM		 5019
5020 u8 sum_flows[0x20];
5021
e1f24a79 5022 u8 rp_cnp_ignored_high[0x20];
e281682b 5023
e1f24a79 5024 u8 rp_cnp_ignored_low[0x20];
e281682b 5025
e1f24a79 5026 u8 rp_cnp_handled_high[0x20];
e281682b 5027
e1f24a79 5028 u8 rp_cnp_handled_low[0x20];
e281682b 5029
b4ff3a36 5030 u8 reserved_at_140[0x100];
e281682b
SM		 5031
5032 u8 time_stamp_high[0x20];
5033
5034 u8 time_stamp_low[0x20];
5035
5036 u8 accumulators_period[0x20];
5037
e1f24a79 5038 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5039
e1f24a79 5040 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5041
e1f24a79 5042 u8 np_cnp_sent_high[0x20];
e281682b 5043
e1f24a79 5044 u8 np_cnp_sent_low[0x20];
e281682b 5045
b4ff3a36 5046 u8 reserved_at_320[0x560];
e281682b
SM		 5047};
5048
5049struct mlx5_ifc_query_cong_statistics_in_bits {
5050 u8 opcode[0x10];
b4ff3a36 5051 u8 reserved_at_10[0x10];
e281682b 5052
b4ff3a36 5053 u8 reserved_at_20[0x10];
e281682b
SM		 5054 u8 op_mod[0x10];
5055
5056 u8 clear[0x1];
b4ff3a36 5057 u8 reserved_at_41[0x1f];
e281682b 5058
b4ff3a36 5059 u8 reserved_at_60[0x20];
e281682b
SM		 5060};
5061
5062struct mlx5_ifc_query_cong_params_out_bits {
5063 u8 status[0x8];
b4ff3a36 5064 u8 reserved_at_8[0x18];
e281682b
SM		 5065
5066 u8 syndrome[0x20];
5067
b4ff3a36 5068 u8 reserved_at_40[0x40];
e281682b
SM		 5069
5070 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5071};
5072
5073struct mlx5_ifc_query_cong_params_in_bits {
5074 u8 opcode[0x10];
b4ff3a36 5075 u8 reserved_at_10[0x10];
e281682b 5076
b4ff3a36 5077 u8 reserved_at_20[0x10];
e281682b
SM		 5078 u8 op_mod[0x10];
5079
b4ff3a36 5080 u8 reserved_at_40[0x1c];
e281682b
SM		 5081 u8 cong_protocol[0x4];
5082
b4ff3a36 5083 u8 reserved_at_60[0x20];
e281682b
SM		 5084};
5085
5086struct mlx5_ifc_query_adapter_out_bits {
5087 u8 status[0x8];
b4ff3a36 5088 u8 reserved_at_8[0x18];
e281682b
SM		 5089
5090 u8 syndrome[0x20];
5091
b4ff3a36 5092 u8 reserved_at_40[0x40];
e281682b
SM		 5093
5094 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5095};
5096
5097struct mlx5_ifc_query_adapter_in_bits {
5098 u8 opcode[0x10];
b4ff3a36 5099 u8 reserved_at_10[0x10];
e281682b 5100
b4ff3a36 5101 u8 reserved_at_20[0x10];
e281682b
SM		 5102 u8 op_mod[0x10];
5103
b4ff3a36 5104 u8 reserved_at_40[0x40];
e281682b
SM		 5105};
5106
5107struct mlx5_ifc_qp_2rst_out_bits {
5108 u8 status[0x8];
b4ff3a36 5109 u8 reserved_at_8[0x18];
e281682b
SM		 5110
5111 u8 syndrome[0x20];
5112
b4ff3a36 5113 u8 reserved_at_40[0x40];
e281682b
SM		 5114};
5115
5116struct mlx5_ifc_qp_2rst_in_bits {
5117 u8 opcode[0x10];
b4ff3a36 5118 u8 reserved_at_10[0x10];
e281682b 5119
b4ff3a36 5120 u8 reserved_at_20[0x10];
e281682b
SM		 5121 u8 op_mod[0x10];
5122
b4ff3a36 5123 u8 reserved_at_40[0x8];
e281682b
SM		 5124 u8 qpn[0x18];
5125
b4ff3a36 5126 u8 reserved_at_60[0x20];
e281682b
SM		 5127};
5128
5129struct mlx5_ifc_qp_2err_out_bits {
5130 u8 status[0x8];
b4ff3a36 5131 u8 reserved_at_8[0x18];
e281682b
SM		 5132
5133 u8 syndrome[0x20];
5134
b4ff3a36 5135 u8 reserved_at_40[0x40];
e281682b
SM		 5136};
5137
5138struct mlx5_ifc_qp_2err_in_bits {
5139 u8 opcode[0x10];
b4ff3a36 5140 u8 reserved_at_10[0x10];
e281682b 5141
b4ff3a36 5142 u8 reserved_at_20[0x10];
e281682b
SM		 5143 u8 op_mod[0x10];
5144
b4ff3a36 5145 u8 reserved_at_40[0x8];
e281682b
SM		 5146 u8 qpn[0x18];
5147
b4ff3a36 5148 u8 reserved_at_60[0x20];
e281682b
SM		 5149};
5150
5151struct mlx5_ifc_page_fault_resume_out_bits {
5152 u8 status[0x8];
b4ff3a36 5153 u8 reserved_at_8[0x18];
e281682b
SM		 5154
5155 u8 syndrome[0x20];
5156
b4ff3a36 5157 u8 reserved_at_40[0x40];
e281682b
SM		 5158};
5159
5160struct mlx5_ifc_page_fault_resume_in_bits {
5161 u8 opcode[0x10];
b4ff3a36 5162 u8 reserved_at_10[0x10];
e281682b 5163
b4ff3a36 5164 u8 reserved_at_20[0x10];
e281682b
SM		 5165 u8 op_mod[0x10];
5166
5167 u8 error[0x1];
b4ff3a36 5168 u8 reserved_at_41[0x4];
223cdc72
AK		 5169 u8 page_fault_type[0x3];
5170 u8 wq_number[0x18];
e281682b 5171
223cdc72
AK		 5172 u8 reserved_at_60[0x8];
5173 u8 token[0x18];
e281682b
SM		 5174};
5175
5176struct mlx5_ifc_nop_out_bits {
5177 u8 status[0x8];
b4ff3a36 5178 u8 reserved_at_8[0x18];
e281682b
SM		 5179
5180 u8 syndrome[0x20];
5181
b4ff3a36 5182 u8 reserved_at_40[0x40];
e281682b
SM		 5183};
5184
5185struct mlx5_ifc_nop_in_bits {
5186 u8 opcode[0x10];
b4ff3a36 5187 u8 reserved_at_10[0x10];
e281682b 5188
b4ff3a36 5189 u8 reserved_at_20[0x10];
e281682b
SM		 5190 u8 op_mod[0x10];
5191
b4ff3a36 5192 u8 reserved_at_40[0x40];
e281682b
SM		 5193};
5194
5195struct mlx5_ifc_modify_vport_state_out_bits {
5196 u8 status[0x8];
b4ff3a36 5197 u8 reserved_at_8[0x18];
e281682b
SM		 5198
5199 u8 syndrome[0x20];
5200
b4ff3a36 5201 u8 reserved_at_40[0x40];
e281682b
SM		 5202};
5203
5204struct mlx5_ifc_modify_vport_state_in_bits {
5205 u8 opcode[0x10];
b4ff3a36 5206 u8 reserved_at_10[0x10];
e281682b 5207
b4ff3a36 5208 u8 reserved_at_20[0x10];
e281682b
SM		 5209 u8 op_mod[0x10];
5210
5211 u8 other_vport[0x1];
b4ff3a36 5212 u8 reserved_at_41[0xf];
e281682b
SM		 5213 u8 vport_number[0x10];
5214
b4ff3a36 5215 u8 reserved_at_60[0x18];
e281682b 5216 u8 admin_state[0x4];
b4ff3a36 5217 u8 reserved_at_7c[0x4];
e281682b
SM		 5218};
5219
5220struct mlx5_ifc_modify_tis_out_bits {
5221 u8 status[0x8];
b4ff3a36 5222 u8 reserved_at_8[0x18];
e281682b
SM		 5223
5224 u8 syndrome[0x20];
5225
b4ff3a36 5226 u8 reserved_at_40[0x40];
e281682b
SM		 5227};
5228
75850d0b 5229struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5230 u8 reserved_at_0[0x20];
75850d0b 5231
84df61eb
AH		 5232 u8 reserved_at_20[0x1d];
5233 u8 lag_tx_port_affinity[0x1];
5234 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5235 u8 prio[0x1];
5236};
5237
e281682b
SM		 5238struct mlx5_ifc_modify_tis_in_bits {
5239 u8 opcode[0x10];
b4ff3a36 5240 u8 reserved_at_10[0x10];
e281682b 5241
b4ff3a36 5242 u8 reserved_at_20[0x10];
e281682b
SM		 5243 u8 op_mod[0x10];
5244
b4ff3a36 5245 u8 reserved_at_40[0x8];
e281682b
SM		 5246 u8 tisn[0x18];
5247
b4ff3a36 5248 u8 reserved_at_60[0x20];
e281682b 5249
75850d0b 5250 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5251
b4ff3a36 5252 u8 reserved_at_c0[0x40];
e281682b
SM		 5253
5254 struct mlx5_ifc_tisc_bits ctx;
5255};
5256
d9eea403 5257struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5258 u8 reserved_at_0[0x20];
d9eea403 5259
b4ff3a36 5260 u8 reserved_at_20[0x1b];
66189961 5261 u8 self_lb_en[0x1];
bdfc028d
TT		 5262 u8 reserved_at_3c[0x1];
5263 u8 hash[0x1];
5264 u8 reserved_at_3e[0x1];
d9eea403
AS		 5265 u8 lro[0x1];
5266};
5267
e281682b
SM		 5268struct mlx5_ifc_modify_tir_out_bits {
5269 u8 status[0x8];
b4ff3a36 5270 u8 reserved_at_8[0x18];
e281682b
SM		 5271
5272 u8 syndrome[0x20];
5273
b4ff3a36 5274 u8 reserved_at_40[0x40];
e281682b
SM		 5275};
5276
5277struct mlx5_ifc_modify_tir_in_bits {
5278 u8 opcode[0x10];
b4ff3a36 5279 u8 reserved_at_10[0x10];
e281682b 5280
b4ff3a36 5281 u8 reserved_at_20[0x10];
e281682b
SM		 5282 u8 op_mod[0x10];
5283
b4ff3a36 5284 u8 reserved_at_40[0x8];
e281682b
SM		 5285 u8 tirn[0x18];
5286
b4ff3a36 5287 u8 reserved_at_60[0x20];
e281682b 5288
d9eea403 5289 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5290
b4ff3a36 5291 u8 reserved_at_c0[0x40];
e281682b
SM		 5292
5293 struct mlx5_ifc_tirc_bits ctx;
5294};
5295
5296struct mlx5_ifc_modify_sq_out_bits {
5297 u8 status[0x8];
b4ff3a36 5298 u8 reserved_at_8[0x18];
e281682b
SM		 5299
5300 u8 syndrome[0x20];
5301
b4ff3a36 5302 u8 reserved_at_40[0x40];
e281682b
SM		 5303};
5304
5305struct mlx5_ifc_modify_sq_in_bits {
5306 u8 opcode[0x10];
b4ff3a36 5307 u8 reserved_at_10[0x10];
e281682b 5308
b4ff3a36 5309 u8 reserved_at_20[0x10];
e281682b
SM		 5310 u8 op_mod[0x10];
5311
5312 u8 sq_state[0x4];
b4ff3a36 5313 u8 reserved_at_44[0x4];
e281682b
SM		 5314 u8 sqn[0x18];
5315
b4ff3a36 5316 u8 reserved_at_60[0x20];
e281682b
SM		 5317
5318 u8 modify_bitmask[0x40];
5319
b4ff3a36 5320 u8 reserved_at_c0[0x40];
e281682b
SM		 5321
5322 struct mlx5_ifc_sqc_bits ctx;
5323};
5324
813f8540
MHY		 5325struct mlx5_ifc_modify_scheduling_element_out_bits {
5326 u8 status[0x8];
5327 u8 reserved_at_8[0x18];
5328
5329 u8 syndrome[0x20];
5330
5331 u8 reserved_at_40[0x1c0];
5332};
5333
5334enum {
5335 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5336 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5337};
5338
5339struct mlx5_ifc_modify_scheduling_element_in_bits {
5340 u8 opcode[0x10];
5341 u8 reserved_at_10[0x10];
5342
5343 u8 reserved_at_20[0x10];
5344 u8 op_mod[0x10];
5345
5346 u8 scheduling_hierarchy[0x8];
5347 u8 reserved_at_48[0x18];
5348
5349 u8 scheduling_element_id[0x20];
5350
5351 u8 reserved_at_80[0x20];
5352
5353 u8 modify_bitmask[0x20];
5354
5355 u8 reserved_at_c0[0x40];
5356
5357 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5358
5359 u8 reserved_at_300[0x100];
5360};
5361
e281682b
SM		 5362struct mlx5_ifc_modify_rqt_out_bits {
5363 u8 status[0x8];
b4ff3a36 5364 u8 reserved_at_8[0x18];
e281682b
SM		 5365
5366 u8 syndrome[0x20];
5367
b4ff3a36 5368 u8 reserved_at_40[0x40];
e281682b
SM		 5369};
5370
5c50368f 5371struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5372 u8 reserved_at_0[0x20];
5c50368f 5373
b4ff3a36 5374 u8 reserved_at_20[0x1f];
5c50368f
AS		 5375 u8 rqn_list[0x1];
5376};
5377
e281682b
SM		 5378struct mlx5_ifc_modify_rqt_in_bits {
5379 u8 opcode[0x10];
b4ff3a36 5380 u8 reserved_at_10[0x10];
e281682b 5381
b4ff3a36 5382 u8 reserved_at_20[0x10];
e281682b
SM		 5383 u8 op_mod[0x10];
5384
b4ff3a36 5385 u8 reserved_at_40[0x8];
e281682b
SM		 5386 u8 rqtn[0x18];
5387
b4ff3a36 5388 u8 reserved_at_60[0x20];
e281682b 5389
5c50368f 5390 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5391
b4ff3a36 5392 u8 reserved_at_c0[0x40];
e281682b
SM		 5393
5394 struct mlx5_ifc_rqtc_bits ctx;
5395};
5396
5397struct mlx5_ifc_modify_rq_out_bits {
5398 u8 status[0x8];
b4ff3a36 5399 u8 reserved_at_8[0x18];
e281682b
SM		 5400
5401 u8 syndrome[0x20];
5402
b4ff3a36 5403 u8 reserved_at_40[0x40];
e281682b
SM		 5404};
5405
83b502a1
AV		 5406enum {
5407 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5408 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5409 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5410};
5411
e281682b
SM		 5412struct mlx5_ifc_modify_rq_in_bits {
5413 u8 opcode[0x10];
b4ff3a36 5414 u8 reserved_at_10[0x10];
e281682b 5415
b4ff3a36 5416 u8 reserved_at_20[0x10];
e281682b
SM		 5417 u8 op_mod[0x10];
5418
5419 u8 rq_state[0x4];
b4ff3a36 5420 u8 reserved_at_44[0x4];
e281682b
SM		 5421 u8 rqn[0x18];
5422
b4ff3a36 5423 u8 reserved_at_60[0x20];
e281682b
SM		 5424
5425 u8 modify_bitmask[0x40];
5426
b4ff3a36 5427 u8 reserved_at_c0[0x40];
e281682b
SM		 5428
5429 struct mlx5_ifc_rqc_bits ctx;
5430};
5431
5432struct mlx5_ifc_modify_rmp_out_bits {
5433 u8 status[0x8];
b4ff3a36 5434 u8 reserved_at_8[0x18];
e281682b
SM		 5435
5436 u8 syndrome[0x20];
5437
b4ff3a36 5438 u8 reserved_at_40[0x40];
e281682b
SM		 5439};
5440
01949d01 5441struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5442 u8 reserved_at_0[0x20];
01949d01 5443
b4ff3a36 5444 u8 reserved_at_20[0x1f];
01949d01
HA		 5445 u8 lwm[0x1];
5446};
5447
e281682b
SM		 5448struct mlx5_ifc_modify_rmp_in_bits {
5449 u8 opcode[0x10];
b4ff3a36 5450 u8 reserved_at_10[0x10];
e281682b 5451
b4ff3a36 5452 u8 reserved_at_20[0x10];
e281682b
SM		 5453 u8 op_mod[0x10];
5454
5455 u8 rmp_state[0x4];
b4ff3a36 5456 u8 reserved_at_44[0x4];
e281682b
SM		 5457 u8 rmpn[0x18];
5458
b4ff3a36 5459 u8 reserved_at_60[0x20];
e281682b 5460
01949d01 5461 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5462
b4ff3a36 5463 u8 reserved_at_c0[0x40];
e281682b
SM		 5464
5465 struct mlx5_ifc_rmpc_bits ctx;
5466};
5467
5468struct mlx5_ifc_modify_nic_vport_context_out_bits {
5469 u8 status[0x8];
b4ff3a36 5470 u8 reserved_at_8[0x18];
e281682b
SM		 5471
5472 u8 syndrome[0x20];
5473
b4ff3a36 5474 u8 reserved_at_40[0x40];
e281682b
SM		 5475};
5476
5477struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5478 u8 reserved_at_0[0x12];
5479 u8 affiliation[0x1];
5480 u8 reserved_at_e[0x1];
bded747b
HN		 5481 u8 disable_uc_local_lb[0x1];
5482 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5483 u8 node_guid[0x1];
5484 u8 port_guid[0x1];
9def7121 5485 u8 min_inline[0x1];
d82b7318
SM		 5486 u8 mtu[0x1];
5487 u8 change_event[0x1];
5488 u8 promisc[0x1];
e281682b
SM		 5489 u8 permanent_address[0x1];
5490 u8 addresses_list[0x1];
5491 u8 roce_en[0x1];
b4ff3a36 5492 u8 reserved_at_1f[0x1];
e281682b
SM		 5493};
5494
5495struct mlx5_ifc_modify_nic_vport_context_in_bits {
5496 u8 opcode[0x10];
b4ff3a36 5497 u8 reserved_at_10[0x10];
e281682b 5498
b4ff3a36 5499 u8 reserved_at_20[0x10];
e281682b
SM		 5500 u8 op_mod[0x10];
5501
5502 u8 other_vport[0x1];
b4ff3a36 5503 u8 reserved_at_41[0xf];
e281682b
SM		 5504 u8 vport_number[0x10];
5505
5506 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5507
b4ff3a36 5508 u8 reserved_at_80[0x780];
e281682b
SM		 5509
5510 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5511};
5512
5513struct mlx5_ifc_modify_hca_vport_context_out_bits {
5514 u8 status[0x8];
b4ff3a36 5515 u8 reserved_at_8[0x18];
e281682b
SM		 5516
5517 u8 syndrome[0x20];
5518
b4ff3a36 5519 u8 reserved_at_40[0x40];
e281682b
SM		 5520};
5521
5522struct mlx5_ifc_modify_hca_vport_context_in_bits {
5523 u8 opcode[0x10];
b4ff3a36 5524 u8 reserved_at_10[0x10];
e281682b 5525
b4ff3a36 5526 u8 reserved_at_20[0x10];
e281682b
SM		 5527 u8 op_mod[0x10];
5528
5529 u8 other_vport[0x1];
b4ff3a36 5530 u8 reserved_at_41[0xb];
707c4602 5531 u8 port_num[0x4];
e281682b
SM		 5532 u8 vport_number[0x10];
5533
b4ff3a36 5534 u8 reserved_at_60[0x20];
e281682b
SM		 5535
5536 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5537};
5538
5539struct mlx5_ifc_modify_cq_out_bits {
5540 u8 status[0x8];
b4ff3a36 5541 u8 reserved_at_8[0x18];
e281682b
SM		 5542
5543 u8 syndrome[0x20];
5544
b4ff3a36 5545 u8 reserved_at_40[0x40];
e281682b
SM		 5546};
5547
5548enum {
5549 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5550 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5551};
5552
5553struct mlx5_ifc_modify_cq_in_bits {
5554 u8 opcode[0x10];
b4ff3a36 5555 u8 reserved_at_10[0x10];
e281682b 5556
b4ff3a36 5557 u8 reserved_at_20[0x10];
e281682b
SM		 5558 u8 op_mod[0x10];
5559
b4ff3a36 5560 u8 reserved_at_40[0x8];
e281682b
SM		 5561 u8 cqn[0x18];
5562
5563 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5564
5565 struct mlx5_ifc_cqc_bits cq_context;
5566
b4ff3a36 5567 u8 reserved_at_280[0x600];
e281682b
SM		 5568
5569 u8 pas[0][0x40];
5570};
5571
5572struct mlx5_ifc_modify_cong_status_out_bits {
5573 u8 status[0x8];
b4ff3a36 5574 u8 reserved_at_8[0x18];
e281682b
SM		 5575
5576 u8 syndrome[0x20];
5577
b4ff3a36 5578 u8 reserved_at_40[0x40];
e281682b
SM		 5579};
5580
5581struct mlx5_ifc_modify_cong_status_in_bits {
5582 u8 opcode[0x10];
b4ff3a36 5583 u8 reserved_at_10[0x10];
e281682b 5584
b4ff3a36 5585 u8 reserved_at_20[0x10];
e281682b
SM		 5586 u8 op_mod[0x10];
5587
b4ff3a36 5588 u8 reserved_at_40[0x18];
e281682b
SM		 5589 u8 priority[0x4];
5590 u8 cong_protocol[0x4];
5591
5592 u8 enable[0x1];
5593 u8 tag_enable[0x1];
b4ff3a36 5594 u8 reserved_at_62[0x1e];
e281682b
SM		 5595};
5596
5597struct mlx5_ifc_modify_cong_params_out_bits {
5598 u8 status[0x8];
b4ff3a36 5599 u8 reserved_at_8[0x18];
e281682b
SM		 5600
5601 u8 syndrome[0x20];
5602
b4ff3a36 5603 u8 reserved_at_40[0x40];
e281682b
SM		 5604};
5605
5606struct mlx5_ifc_modify_cong_params_in_bits {
5607 u8 opcode[0x10];
b4ff3a36 5608 u8 reserved_at_10[0x10];
e281682b 5609
b4ff3a36 5610 u8 reserved_at_20[0x10];
e281682b
SM		 5611 u8 op_mod[0x10];
5612
b4ff3a36 5613 u8 reserved_at_40[0x1c];
e281682b
SM		 5614 u8 cong_protocol[0x4];
5615
5616 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5617
b4ff3a36 5618 u8 reserved_at_80[0x80];
e281682b
SM		 5619
5620 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5621};
5622
5623struct mlx5_ifc_manage_pages_out_bits {
5624 u8 status[0x8];
b4ff3a36 5625 u8 reserved_at_8[0x18];
e281682b
SM		 5626
5627 u8 syndrome[0x20];
5628
5629 u8 output_num_entries[0x20];
5630
b4ff3a36 5631 u8 reserved_at_60[0x20];
e281682b
SM		 5632
5633 u8 pas[0][0x40];
5634};
5635
5636enum {
5637 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5638 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5639 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5640};
5641
5642struct mlx5_ifc_manage_pages_in_bits {
5643 u8 opcode[0x10];
b4ff3a36 5644 u8 reserved_at_10[0x10];
e281682b 5645
b4ff3a36 5646 u8 reserved_at_20[0x10];
e281682b
SM		 5647 u8 op_mod[0x10];
5648
b4ff3a36 5649 u8 reserved_at_40[0x10];
e281682b
SM		 5650 u8 function_id[0x10];
5651
5652 u8 input_num_entries[0x20];
5653
5654 u8 pas[0][0x40];
5655};
5656
5657struct mlx5_ifc_mad_ifc_out_bits {
5658 u8 status[0x8];
b4ff3a36 5659 u8 reserved_at_8[0x18];
e281682b
SM		 5660
5661 u8 syndrome[0x20];
5662
b4ff3a36 5663 u8 reserved_at_40[0x40];
e281682b
SM		 5664
5665 u8 response_mad_packet[256][0x8];
5666};
5667
5668struct mlx5_ifc_mad_ifc_in_bits {
5669 u8 opcode[0x10];
b4ff3a36 5670 u8 reserved_at_10[0x10];
e281682b 5671
b4ff3a36 5672 u8 reserved_at_20[0x10];
e281682b
SM		 5673 u8 op_mod[0x10];
5674
5675 u8 remote_lid[0x10];
b4ff3a36 5676 u8 reserved_at_50[0x8];
e281682b
SM		 5677 u8 port[0x8];
5678
b4ff3a36 5679 u8 reserved_at_60[0x20];
e281682b
SM		 5680
5681 u8 mad[256][0x8];
5682};
5683
5684struct mlx5_ifc_init_hca_out_bits {
5685 u8 status[0x8];
b4ff3a36 5686 u8 reserved_at_8[0x18];
e281682b
SM		 5687
5688 u8 syndrome[0x20];
5689
b4ff3a36 5690 u8 reserved_at_40[0x40];
e281682b
SM		 5691};
5692
5693struct mlx5_ifc_init_hca_in_bits {
5694 u8 opcode[0x10];
b4ff3a36 5695 u8 reserved_at_10[0x10];
e281682b 5696
b4ff3a36 5697 u8 reserved_at_20[0x10];
e281682b
SM		 5698 u8 op_mod[0x10];
5699
b4ff3a36 5700 u8 reserved_at_40[0x40];
8737f818 5701 u8 sw_owner_id[4][0x20];
e281682b
SM		 5702};
5703
5704struct mlx5_ifc_init2rtr_qp_out_bits {
5705 u8 status[0x8];
b4ff3a36 5706 u8 reserved_at_8[0x18];
e281682b
SM		 5707
5708 u8 syndrome[0x20];
5709
b4ff3a36 5710 u8 reserved_at_40[0x40];
e281682b
SM		 5711};
5712
5713struct mlx5_ifc_init2rtr_qp_in_bits {
5714 u8 opcode[0x10];
b4ff3a36 5715 u8 reserved_at_10[0x10];
e281682b 5716
b4ff3a36 5717 u8 reserved_at_20[0x10];
e281682b
SM		 5718 u8 op_mod[0x10];
5719
b4ff3a36 5720 u8 reserved_at_40[0x8];
e281682b
SM		 5721 u8 qpn[0x18];
5722
b4ff3a36 5723 u8 reserved_at_60[0x20];
e281682b
SM		 5724
5725 u8 opt_param_mask[0x20];
5726
b4ff3a36 5727 u8 reserved_at_a0[0x20];
e281682b
SM		 5728
5729 struct mlx5_ifc_qpc_bits qpc;
5730
b4ff3a36 5731 u8 reserved_at_800[0x80];
e281682b
SM		 5732};
5733
5734struct mlx5_ifc_init2init_qp_out_bits {
5735 u8 status[0x8];
b4ff3a36 5736 u8 reserved_at_8[0x18];
e281682b
SM		 5737
5738 u8 syndrome[0x20];
5739
b4ff3a36 5740 u8 reserved_at_40[0x40];
e281682b
SM		 5741};
5742
5743struct mlx5_ifc_init2init_qp_in_bits {
5744 u8 opcode[0x10];
b4ff3a36 5745 u8 reserved_at_10[0x10];
e281682b 5746
b4ff3a36 5747 u8 reserved_at_20[0x10];
e281682b
SM		 5748 u8 op_mod[0x10];
5749
b4ff3a36 5750 u8 reserved_at_40[0x8];
e281682b
SM		 5751 u8 qpn[0x18];
5752
b4ff3a36 5753 u8 reserved_at_60[0x20];
e281682b
SM		 5754
5755 u8 opt_param_mask[0x20];
5756
b4ff3a36 5757 u8 reserved_at_a0[0x20];
e281682b
SM		 5758
5759 struct mlx5_ifc_qpc_bits qpc;
5760
b4ff3a36 5761 u8 reserved_at_800[0x80];
e281682b
SM		 5762};
5763
5764struct mlx5_ifc_get_dropped_packet_log_out_bits {
5765 u8 status[0x8];
b4ff3a36 5766 u8 reserved_at_8[0x18];
e281682b
SM		 5767
5768 u8 syndrome[0x20];
5769
b4ff3a36 5770 u8 reserved_at_40[0x40];
e281682b
SM		 5771
5772 u8 packet_headers_log[128][0x8];
5773
5774 u8 packet_syndrome[64][0x8];
5775};
5776
5777struct mlx5_ifc_get_dropped_packet_log_in_bits {
5778 u8 opcode[0x10];
b4ff3a36 5779 u8 reserved_at_10[0x10];
e281682b 5780
b4ff3a36 5781 u8 reserved_at_20[0x10];
e281682b
SM		 5782 u8 op_mod[0x10];
5783
b4ff3a36 5784 u8 reserved_at_40[0x40];
e281682b
SM		 5785};
5786
5787struct mlx5_ifc_gen_eqe_in_bits {
5788 u8 opcode[0x10];
b4ff3a36 5789 u8 reserved_at_10[0x10];
e281682b 5790
b4ff3a36 5791 u8 reserved_at_20[0x10];
e281682b
SM		 5792 u8 op_mod[0x10];
5793
b4ff3a36 5794 u8 reserved_at_40[0x18];
e281682b
SM		 5795 u8 eq_number[0x8];
5796
b4ff3a36 5797 u8 reserved_at_60[0x20];
e281682b
SM		 5798
5799 u8 eqe[64][0x8];
5800};
5801
5802struct mlx5_ifc_gen_eq_out_bits {
5803 u8 status[0x8];
b4ff3a36 5804 u8 reserved_at_8[0x18];
e281682b
SM		 5805
5806 u8 syndrome[0x20];
5807
b4ff3a36 5808 u8 reserved_at_40[0x40];
e281682b
SM		 5809};
5810
5811struct mlx5_ifc_enable_hca_out_bits {
5812 u8 status[0x8];
b4ff3a36 5813 u8 reserved_at_8[0x18];
e281682b
SM		 5814
5815 u8 syndrome[0x20];
5816
b4ff3a36 5817 u8 reserved_at_40[0x20];
e281682b
SM		 5818};
5819
5820struct mlx5_ifc_enable_hca_in_bits {
5821 u8 opcode[0x10];
b4ff3a36 5822 u8 reserved_at_10[0x10];
e281682b 5823
b4ff3a36 5824 u8 reserved_at_20[0x10];
e281682b
SM		 5825 u8 op_mod[0x10];
5826
b4ff3a36 5827 u8 reserved_at_40[0x10];
e281682b
SM		 5828 u8 function_id[0x10];
5829
b4ff3a36 5830 u8 reserved_at_60[0x20];
e281682b
SM		 5831};
5832
5833struct mlx5_ifc_drain_dct_out_bits {
5834 u8 status[0x8];
b4ff3a36 5835 u8 reserved_at_8[0x18];
e281682b
SM		 5836
5837 u8 syndrome[0x20];
5838
b4ff3a36 5839 u8 reserved_at_40[0x40];
e281682b
SM		 5840};
5841
5842struct mlx5_ifc_drain_dct_in_bits {
5843 u8 opcode[0x10];
b4ff3a36 5844 u8 reserved_at_10[0x10];
e281682b 5845
b4ff3a36 5846 u8 reserved_at_20[0x10];
e281682b
SM		 5847 u8 op_mod[0x10];
5848
b4ff3a36 5849 u8 reserved_at_40[0x8];
e281682b
SM		 5850 u8 dctn[0x18];
5851
b4ff3a36 5852 u8 reserved_at_60[0x20];
e281682b
SM		 5853};
5854
5855struct mlx5_ifc_disable_hca_out_bits {
5856 u8 status[0x8];
b4ff3a36 5857 u8 reserved_at_8[0x18];
e281682b
SM		 5858
5859 u8 syndrome[0x20];
5860
b4ff3a36 5861 u8 reserved_at_40[0x20];
e281682b
SM		 5862};
5863
5864struct mlx5_ifc_disable_hca_in_bits {
5865 u8 opcode[0x10];
b4ff3a36 5866 u8 reserved_at_10[0x10];
e281682b 5867
b4ff3a36 5868 u8 reserved_at_20[0x10];
e281682b
SM		 5869 u8 op_mod[0x10];
5870
b4ff3a36 5871 u8 reserved_at_40[0x10];
e281682b
SM		 5872 u8 function_id[0x10];
5873
b4ff3a36 5874 u8 reserved_at_60[0x20];
e281682b
SM		 5875};
5876
5877struct mlx5_ifc_detach_from_mcg_out_bits {
5878 u8 status[0x8];
b4ff3a36 5879 u8 reserved_at_8[0x18];
e281682b
SM		 5880
5881 u8 syndrome[0x20];
5882
b4ff3a36 5883 u8 reserved_at_40[0x40];
e281682b
SM		 5884};
5885
5886struct mlx5_ifc_detach_from_mcg_in_bits {
5887 u8 opcode[0x10];
b4ff3a36 5888 u8 reserved_at_10[0x10];
e281682b 5889
b4ff3a36 5890 u8 reserved_at_20[0x10];
e281682b
SM		 5891 u8 op_mod[0x10];
5892
b4ff3a36 5893 u8 reserved_at_40[0x8];
e281682b
SM		 5894 u8 qpn[0x18];
5895
b4ff3a36 5896 u8 reserved_at_60[0x20];
e281682b
SM		 5897
5898 u8 multicast_gid[16][0x8];
5899};
5900
7486216b
SM		 5901struct mlx5_ifc_destroy_xrq_out_bits {
5902 u8 status[0x8];
5903 u8 reserved_at_8[0x18];
5904
5905 u8 syndrome[0x20];
5906
5907 u8 reserved_at_40[0x40];
5908};
5909
5910struct mlx5_ifc_destroy_xrq_in_bits {
5911 u8 opcode[0x10];
5912 u8 reserved_at_10[0x10];
5913
5914 u8 reserved_at_20[0x10];
5915 u8 op_mod[0x10];
5916
5917 u8 reserved_at_40[0x8];
5918 u8 xrqn[0x18];
5919
5920 u8 reserved_at_60[0x20];
5921};
5922
e281682b
SM		 5923struct mlx5_ifc_destroy_xrc_srq_out_bits {
5924 u8 status[0x8];
b4ff3a36 5925 u8 reserved_at_8[0x18];
e281682b
SM		 5926
5927 u8 syndrome[0x20];
5928
b4ff3a36 5929 u8 reserved_at_40[0x40];
e281682b
SM		 5930};
5931
5932struct mlx5_ifc_destroy_xrc_srq_in_bits {
5933 u8 opcode[0x10];
b4ff3a36 5934 u8 reserved_at_10[0x10];
e281682b 5935
b4ff3a36 5936 u8 reserved_at_20[0x10];
e281682b
SM		 5937 u8 op_mod[0x10];
5938
b4ff3a36 5939 u8 reserved_at_40[0x8];
e281682b
SM		 5940 u8 xrc_srqn[0x18];
5941
b4ff3a36 5942 u8 reserved_at_60[0x20];
e281682b
SM		 5943};
5944
5945struct mlx5_ifc_destroy_tis_out_bits {
5946 u8 status[0x8];
b4ff3a36 5947 u8 reserved_at_8[0x18];
e281682b
SM		 5948
5949 u8 syndrome[0x20];
5950
b4ff3a36 5951 u8 reserved_at_40[0x40];
e281682b
SM		 5952};
5953
5954struct mlx5_ifc_destroy_tis_in_bits {
5955 u8 opcode[0x10];
b4ff3a36 5956 u8 reserved_at_10[0x10];
e281682b 5957
b4ff3a36 5958 u8 reserved_at_20[0x10];
e281682b
SM		 5959 u8 op_mod[0x10];
5960
b4ff3a36 5961 u8 reserved_at_40[0x8];
e281682b
SM		 5962 u8 tisn[0x18];
5963
b4ff3a36 5964 u8 reserved_at_60[0x20];
e281682b
SM		 5965};
5966
5967struct mlx5_ifc_destroy_tir_out_bits {
5968 u8 status[0x8];
b4ff3a36 5969 u8 reserved_at_8[0x18];
e281682b
SM		 5970
5971 u8 syndrome[0x20];
5972
b4ff3a36 5973 u8 reserved_at_40[0x40];
e281682b
SM		 5974};
5975
5976struct mlx5_ifc_destroy_tir_in_bits {
5977 u8 opcode[0x10];
b4ff3a36 5978 u8 reserved_at_10[0x10];
e281682b 5979
b4ff3a36 5980 u8 reserved_at_20[0x10];
e281682b
SM		 5981 u8 op_mod[0x10];
5982
b4ff3a36 5983 u8 reserved_at_40[0x8];
e281682b
SM		 5984 u8 tirn[0x18];
5985
b4ff3a36 5986 u8 reserved_at_60[0x20];
e281682b
SM		 5987};
5988
5989struct mlx5_ifc_destroy_srq_out_bits {
5990 u8 status[0x8];
b4ff3a36 5991 u8 reserved_at_8[0x18];
e281682b
SM		 5992
5993 u8 syndrome[0x20];
5994
b4ff3a36 5995 u8 reserved_at_40[0x40];
e281682b
SM		 5996};
5997
5998struct mlx5_ifc_destroy_srq_in_bits {
5999 u8 opcode[0x10];
b4ff3a36 6000 u8 reserved_at_10[0x10];
e281682b 6001
b4ff3a36 6002 u8 reserved_at_20[0x10];
e281682b
SM		 6003 u8 op_mod[0x10];
6004
b4ff3a36 6005 u8 reserved_at_40[0x8];
e281682b
SM		 6006 u8 srqn[0x18];
6007
b4ff3a36 6008 u8 reserved_at_60[0x20];
e281682b
SM		 6009};
6010
6011struct mlx5_ifc_destroy_sq_out_bits {
6012 u8 status[0x8];
b4ff3a36 6013 u8 reserved_at_8[0x18];
e281682b
SM		 6014
6015 u8 syndrome[0x20];
6016
b4ff3a36 6017 u8 reserved_at_40[0x40];
e281682b
SM		 6018};
6019
6020struct mlx5_ifc_destroy_sq_in_bits {
6021 u8 opcode[0x10];
b4ff3a36 6022 u8 reserved_at_10[0x10];
e281682b 6023
b4ff3a36 6024 u8 reserved_at_20[0x10];
e281682b
SM		 6025 u8 op_mod[0x10];
6026
b4ff3a36 6027 u8 reserved_at_40[0x8];
e281682b
SM		 6028 u8 sqn[0x18];
6029
b4ff3a36 6030 u8 reserved_at_60[0x20];
e281682b
SM		 6031};
6032
813f8540
MHY		 6033struct mlx5_ifc_destroy_scheduling_element_out_bits {
6034 u8 status[0x8];
6035 u8 reserved_at_8[0x18];
6036
6037 u8 syndrome[0x20];
6038
6039 u8 reserved_at_40[0x1c0];
6040};
6041
6042struct mlx5_ifc_destroy_scheduling_element_in_bits {
6043 u8 opcode[0x10];
6044 u8 reserved_at_10[0x10];
6045
6046 u8 reserved_at_20[0x10];
6047 u8 op_mod[0x10];
6048
6049 u8 scheduling_hierarchy[0x8];
6050 u8 reserved_at_48[0x18];
6051
6052 u8 scheduling_element_id[0x20];
6053
6054 u8 reserved_at_80[0x180];
6055};
6056
e281682b
SM		 6057struct mlx5_ifc_destroy_rqt_out_bits {
6058 u8 status[0x8];
b4ff3a36 6059 u8 reserved_at_8[0x18];
e281682b
SM		 6060
6061 u8 syndrome[0x20];
6062
b4ff3a36 6063 u8 reserved_at_40[0x40];
e281682b
SM		 6064};
6065
6066struct mlx5_ifc_destroy_rqt_in_bits {
6067 u8 opcode[0x10];
b4ff3a36 6068 u8 reserved_at_10[0x10];
e281682b 6069
b4ff3a36 6070 u8 reserved_at_20[0x10];
e281682b
SM		 6071 u8 op_mod[0x10];
6072
b4ff3a36 6073 u8 reserved_at_40[0x8];
e281682b
SM		 6074 u8 rqtn[0x18];
6075
b4ff3a36 6076 u8 reserved_at_60[0x20];
e281682b
SM		 6077};
6078
6079struct mlx5_ifc_destroy_rq_out_bits {
6080 u8 status[0x8];
b4ff3a36 6081 u8 reserved_at_8[0x18];
e281682b
SM		 6082
6083 u8 syndrome[0x20];
6084
b4ff3a36 6085 u8 reserved_at_40[0x40];
e281682b
SM		 6086};
6087
6088struct mlx5_ifc_destroy_rq_in_bits {
6089 u8 opcode[0x10];
b4ff3a36 6090 u8 reserved_at_10[0x10];
e281682b 6091
b4ff3a36 6092 u8 reserved_at_20[0x10];
e281682b
SM		 6093 u8 op_mod[0x10];
6094
b4ff3a36 6095 u8 reserved_at_40[0x8];
e281682b
SM		 6096 u8 rqn[0x18];
6097
b4ff3a36 6098 u8 reserved_at_60[0x20];
e281682b
SM		 6099};
6100
c1e0bfc1
MG		 6101struct mlx5_ifc_set_delay_drop_params_in_bits {
6102 u8 opcode[0x10];
6103 u8 reserved_at_10[0x10];
6104
6105 u8 reserved_at_20[0x10];
6106 u8 op_mod[0x10];
6107
6108 u8 reserved_at_40[0x20];
6109
6110 u8 reserved_at_60[0x10];
6111 u8 delay_drop_timeout[0x10];
6112};
6113
6114struct mlx5_ifc_set_delay_drop_params_out_bits {
6115 u8 status[0x8];
6116 u8 reserved_at_8[0x18];
6117
6118 u8 syndrome[0x20];
6119
6120 u8 reserved_at_40[0x40];
6121};
6122
e281682b
SM		 6123struct mlx5_ifc_destroy_rmp_out_bits {
6124 u8 status[0x8];
b4ff3a36 6125 u8 reserved_at_8[0x18];
e281682b
SM		 6126
6127 u8 syndrome[0x20];
6128
b4ff3a36 6129 u8 reserved_at_40[0x40];
e281682b
SM		 6130};
6131
6132struct mlx5_ifc_destroy_rmp_in_bits {
6133 u8 opcode[0x10];
b4ff3a36 6134 u8 reserved_at_10[0x10];
e281682b 6135
b4ff3a36 6136 u8 reserved_at_20[0x10];
e281682b
SM		 6137 u8 op_mod[0x10];
6138
b4ff3a36 6139 u8 reserved_at_40[0x8];
e281682b
SM		 6140 u8 rmpn[0x18];
6141
b4ff3a36 6142 u8 reserved_at_60[0x20];
e281682b
SM		 6143};
6144
6145struct mlx5_ifc_destroy_qp_out_bits {
6146 u8 status[0x8];
b4ff3a36 6147 u8 reserved_at_8[0x18];
e281682b
SM		 6148
6149 u8 syndrome[0x20];
6150
b4ff3a36 6151 u8 reserved_at_40[0x40];
e281682b
SM		 6152};
6153
6154struct mlx5_ifc_destroy_qp_in_bits {
6155 u8 opcode[0x10];
b4ff3a36 6156 u8 reserved_at_10[0x10];
e281682b 6157
b4ff3a36 6158 u8 reserved_at_20[0x10];
e281682b
SM		 6159 u8 op_mod[0x10];
6160
b4ff3a36 6161 u8 reserved_at_40[0x8];
e281682b
SM		 6162 u8 qpn[0x18];
6163
b4ff3a36 6164 u8 reserved_at_60[0x20];
e281682b
SM		 6165};
6166
6167struct mlx5_ifc_destroy_psv_out_bits {
6168 u8 status[0x8];
b4ff3a36 6169 u8 reserved_at_8[0x18];
e281682b
SM		 6170
6171 u8 syndrome[0x20];
6172
b4ff3a36 6173 u8 reserved_at_40[0x40];
e281682b
SM		 6174};
6175
6176struct mlx5_ifc_destroy_psv_in_bits {
6177 u8 opcode[0x10];
b4ff3a36 6178 u8 reserved_at_10[0x10];
e281682b 6179
b4ff3a36 6180 u8 reserved_at_20[0x10];
e281682b
SM		 6181 u8 op_mod[0x10];
6182
b4ff3a36 6183 u8 reserved_at_40[0x8];
e281682b
SM		 6184 u8 psvn[0x18];
6185
b4ff3a36 6186 u8 reserved_at_60[0x20];
e281682b
SM		 6187};
6188
6189struct mlx5_ifc_destroy_mkey_out_bits {
6190 u8 status[0x8];
b4ff3a36 6191 u8 reserved_at_8[0x18];
e281682b
SM		 6192
6193 u8 syndrome[0x20];
6194
b4ff3a36 6195 u8 reserved_at_40[0x40];
e281682b
SM		 6196};
6197
6198struct mlx5_ifc_destroy_mkey_in_bits {
6199 u8 opcode[0x10];
b4ff3a36 6200 u8 reserved_at_10[0x10];
e281682b 6201
b4ff3a36 6202 u8 reserved_at_20[0x10];
e281682b
SM		 6203 u8 op_mod[0x10];
6204
b4ff3a36 6205 u8 reserved_at_40[0x8];
e281682b
SM		 6206 u8 mkey_index[0x18];
6207
b4ff3a36 6208 u8 reserved_at_60[0x20];
e281682b
SM		 6209};
6210
6211struct mlx5_ifc_destroy_flow_table_out_bits {
6212 u8 status[0x8];
b4ff3a36 6213 u8 reserved_at_8[0x18];
e281682b
SM		 6214
6215 u8 syndrome[0x20];
6216
b4ff3a36 6217 u8 reserved_at_40[0x40];
e281682b
SM		 6218};
6219
6220struct mlx5_ifc_destroy_flow_table_in_bits {
6221 u8 opcode[0x10];
b4ff3a36 6222 u8 reserved_at_10[0x10];
e281682b 6223
b4ff3a36 6224 u8 reserved_at_20[0x10];
e281682b
SM		 6225 u8 op_mod[0x10];
6226
7d5e1423
SM		 6227 u8 other_vport[0x1];
6228 u8 reserved_at_41[0xf];
6229 u8 vport_number[0x10];
6230
6231 u8 reserved_at_60[0x20];
e281682b
SM		 6232
6233 u8 table_type[0x8];
b4ff3a36 6234 u8 reserved_at_88[0x18];
e281682b 6235
b4ff3a36 6236 u8 reserved_at_a0[0x8];
e281682b
SM		 6237 u8 table_id[0x18];
6238
b4ff3a36 6239 u8 reserved_at_c0[0x140];
e281682b
SM		 6240};
6241
6242struct mlx5_ifc_destroy_flow_group_out_bits {
6243 u8 status[0x8];
b4ff3a36 6244 u8 reserved_at_8[0x18];
e281682b
SM		 6245
6246 u8 syndrome[0x20];
6247
b4ff3a36 6248 u8 reserved_at_40[0x40];
e281682b
SM		 6249};
6250
6251struct mlx5_ifc_destroy_flow_group_in_bits {
6252 u8 opcode[0x10];
b4ff3a36 6253 u8 reserved_at_10[0x10];
e281682b 6254
b4ff3a36 6255 u8 reserved_at_20[0x10];
e281682b
SM		 6256 u8 op_mod[0x10];
6257
7d5e1423
SM		 6258 u8 other_vport[0x1];
6259 u8 reserved_at_41[0xf];
6260 u8 vport_number[0x10];
6261
6262 u8 reserved_at_60[0x20];
e281682b
SM		 6263
6264 u8 table_type[0x8];
b4ff3a36 6265 u8 reserved_at_88[0x18];
e281682b 6266
b4ff3a36 6267 u8 reserved_at_a0[0x8];
e281682b
SM		 6268 u8 table_id[0x18];
6269
6270 u8 group_id[0x20];
6271
b4ff3a36 6272 u8 reserved_at_e0[0x120];
e281682b
SM		 6273};
6274
6275struct mlx5_ifc_destroy_eq_out_bits {
6276 u8 status[0x8];
b4ff3a36 6277 u8 reserved_at_8[0x18];
e281682b
SM		 6278
6279 u8 syndrome[0x20];
6280
b4ff3a36 6281 u8 reserved_at_40[0x40];
e281682b
SM		 6282};
6283
6284struct mlx5_ifc_destroy_eq_in_bits {
6285 u8 opcode[0x10];
b4ff3a36 6286 u8 reserved_at_10[0x10];
e281682b 6287
b4ff3a36 6288 u8 reserved_at_20[0x10];
e281682b
SM		 6289 u8 op_mod[0x10];
6290
b4ff3a36 6291 u8 reserved_at_40[0x18];
e281682b
SM		 6292 u8 eq_number[0x8];
6293
b4ff3a36 6294 u8 reserved_at_60[0x20];
e281682b
SM		 6295};
6296
6297struct mlx5_ifc_destroy_dct_out_bits {
6298 u8 status[0x8];
b4ff3a36 6299 u8 reserved_at_8[0x18];
e281682b
SM		 6300
6301 u8 syndrome[0x20];
6302
b4ff3a36 6303 u8 reserved_at_40[0x40];
e281682b
SM		 6304};
6305
6306struct mlx5_ifc_destroy_dct_in_bits {
6307 u8 opcode[0x10];
b4ff3a36 6308 u8 reserved_at_10[0x10];
e281682b 6309
b4ff3a36 6310 u8 reserved_at_20[0x10];
e281682b
SM		 6311 u8 op_mod[0x10];
6312
b4ff3a36 6313 u8 reserved_at_40[0x8];
e281682b
SM		 6314 u8 dctn[0x18];
6315
b4ff3a36 6316 u8 reserved_at_60[0x20];
e281682b
SM		 6317};
6318
6319struct mlx5_ifc_destroy_cq_out_bits {
6320 u8 status[0x8];
b4ff3a36 6321 u8 reserved_at_8[0x18];
e281682b
SM		 6322
6323 u8 syndrome[0x20];
6324
b4ff3a36 6325 u8 reserved_at_40[0x40];
e281682b
SM		 6326};
6327
6328struct mlx5_ifc_destroy_cq_in_bits {
6329 u8 opcode[0x10];
b4ff3a36 6330 u8 reserved_at_10[0x10];
e281682b 6331
b4ff3a36 6332 u8 reserved_at_20[0x10];
e281682b
SM		 6333 u8 op_mod[0x10];
6334
b4ff3a36 6335 u8 reserved_at_40[0x8];
e281682b
SM		 6336 u8 cqn[0x18];
6337
b4ff3a36 6338 u8 reserved_at_60[0x20];
e281682b
SM		 6339};
6340
6341struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6342 u8 status[0x8];
b4ff3a36 6343 u8 reserved_at_8[0x18];
e281682b
SM		 6344
6345 u8 syndrome[0x20];
6346
b4ff3a36 6347 u8 reserved_at_40[0x40];
e281682b
SM		 6348};
6349
6350struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6351 u8 opcode[0x10];
b4ff3a36 6352 u8 reserved_at_10[0x10];
e281682b 6353
b4ff3a36 6354 u8 reserved_at_20[0x10];
e281682b
SM		 6355 u8 op_mod[0x10];
6356
b4ff3a36 6357 u8 reserved_at_40[0x20];
e281682b 6358
b4ff3a36 6359 u8 reserved_at_60[0x10];
e281682b
SM		 6360 u8 vxlan_udp_port[0x10];
6361};
6362
6363struct mlx5_ifc_delete_l2_table_entry_out_bits {
6364 u8 status[0x8];
b4ff3a36 6365 u8 reserved_at_8[0x18];
e281682b
SM		 6366
6367 u8 syndrome[0x20];
6368
b4ff3a36 6369 u8 reserved_at_40[0x40];
e281682b
SM		 6370};
6371
6372struct mlx5_ifc_delete_l2_table_entry_in_bits {
6373 u8 opcode[0x10];
b4ff3a36 6374 u8 reserved_at_10[0x10];
e281682b 6375
b4ff3a36 6376 u8 reserved_at_20[0x10];
e281682b
SM		 6377 u8 op_mod[0x10];
6378
b4ff3a36 6379 u8 reserved_at_40[0x60];
e281682b 6380
b4ff3a36 6381 u8 reserved_at_a0[0x8];
e281682b
SM		 6382 u8 table_index[0x18];
6383
b4ff3a36 6384 u8 reserved_at_c0[0x140];
e281682b
SM		 6385};
6386
6387struct mlx5_ifc_delete_fte_out_bits {
6388 u8 status[0x8];
b4ff3a36 6389 u8 reserved_at_8[0x18];
e281682b
SM		 6390
6391 u8 syndrome[0x20];
6392
b4ff3a36 6393 u8 reserved_at_40[0x40];
e281682b
SM		 6394};
6395
6396struct mlx5_ifc_delete_fte_in_bits {
6397 u8 opcode[0x10];
b4ff3a36 6398 u8 reserved_at_10[0x10];
e281682b 6399
b4ff3a36 6400 u8 reserved_at_20[0x10];
e281682b
SM		 6401 u8 op_mod[0x10];
6402
7d5e1423
SM		 6403 u8 other_vport[0x1];
6404 u8 reserved_at_41[0xf];
6405 u8 vport_number[0x10];
6406
6407 u8 reserved_at_60[0x20];
e281682b
SM		 6408
6409 u8 table_type[0x8];
b4ff3a36 6410 u8 reserved_at_88[0x18];
e281682b 6411
b4ff3a36 6412 u8 reserved_at_a0[0x8];
e281682b
SM		 6413 u8 table_id[0x18];
6414
b4ff3a36 6415 u8 reserved_at_c0[0x40];
e281682b
SM		 6416
6417 u8 flow_index[0x20];
6418
b4ff3a36 6419 u8 reserved_at_120[0xe0];
e281682b
SM		 6420};
6421
6422struct mlx5_ifc_dealloc_xrcd_out_bits {
6423 u8 status[0x8];
b4ff3a36 6424 u8 reserved_at_8[0x18];
e281682b
SM		 6425
6426 u8 syndrome[0x20];
6427
b4ff3a36 6428 u8 reserved_at_40[0x40];
e281682b
SM		 6429};
6430
6431struct mlx5_ifc_dealloc_xrcd_in_bits {
6432 u8 opcode[0x10];
b4ff3a36 6433 u8 reserved_at_10[0x10];
e281682b 6434
b4ff3a36 6435 u8 reserved_at_20[0x10];
e281682b
SM		 6436 u8 op_mod[0x10];
6437
b4ff3a36 6438 u8 reserved_at_40[0x8];
e281682b
SM		 6439 u8 xrcd[0x18];
6440
b4ff3a36 6441 u8 reserved_at_60[0x20];
e281682b
SM		 6442};
6443
6444struct mlx5_ifc_dealloc_uar_out_bits {
6445 u8 status[0x8];
b4ff3a36 6446 u8 reserved_at_8[0x18];
e281682b
SM		 6447
6448 u8 syndrome[0x20];
6449
b4ff3a36 6450 u8 reserved_at_40[0x40];
e281682b
SM		 6451};
6452
6453struct mlx5_ifc_dealloc_uar_in_bits {
6454 u8 opcode[0x10];
b4ff3a36 6455 u8 reserved_at_10[0x10];
e281682b 6456
b4ff3a36 6457 u8 reserved_at_20[0x10];
e281682b
SM		 6458 u8 op_mod[0x10];
6459
b4ff3a36 6460 u8 reserved_at_40[0x8];
e281682b
SM		 6461 u8 uar[0x18];
6462
b4ff3a36 6463 u8 reserved_at_60[0x20];
e281682b
SM		 6464};
6465
6466struct mlx5_ifc_dealloc_transport_domain_out_bits {
6467 u8 status[0x8];
b4ff3a36 6468 u8 reserved_at_8[0x18];
e281682b
SM		 6469
6470 u8 syndrome[0x20];
6471
b4ff3a36 6472 u8 reserved_at_40[0x40];
e281682b
SM		 6473};
6474
6475struct mlx5_ifc_dealloc_transport_domain_in_bits {
6476 u8 opcode[0x10];
b4ff3a36 6477 u8 reserved_at_10[0x10];
e281682b 6478
b4ff3a36 6479 u8 reserved_at_20[0x10];
e281682b
SM		 6480 u8 op_mod[0x10];
6481
b4ff3a36 6482 u8 reserved_at_40[0x8];
e281682b
SM		 6483 u8 transport_domain[0x18];
6484
b4ff3a36 6485 u8 reserved_at_60[0x20];
e281682b
SM		 6486};
6487
6488struct mlx5_ifc_dealloc_q_counter_out_bits {
6489 u8 status[0x8];
b4ff3a36 6490 u8 reserved_at_8[0x18];
e281682b
SM		 6491
6492 u8 syndrome[0x20];
6493
b4ff3a36 6494 u8 reserved_at_40[0x40];
e281682b
SM		 6495};
6496
6497struct mlx5_ifc_dealloc_q_counter_in_bits {
6498 u8 opcode[0x10];
b4ff3a36 6499 u8 reserved_at_10[0x10];
e281682b 6500
b4ff3a36 6501 u8 reserved_at_20[0x10];
e281682b
SM		 6502 u8 op_mod[0x10];
6503
b4ff3a36 6504 u8 reserved_at_40[0x18];
e281682b
SM		 6505 u8 counter_set_id[0x8];
6506
b4ff3a36 6507 u8 reserved_at_60[0x20];
e281682b
SM		 6508};
6509
6510struct mlx5_ifc_dealloc_pd_out_bits {
6511 u8 status[0x8];
b4ff3a36 6512 u8 reserved_at_8[0x18];
e281682b
SM		 6513
6514 u8 syndrome[0x20];
6515
b4ff3a36 6516 u8 reserved_at_40[0x40];
e281682b
SM		 6517};
6518
6519struct mlx5_ifc_dealloc_pd_in_bits {
6520 u8 opcode[0x10];
b4ff3a36 6521 u8 reserved_at_10[0x10];
e281682b 6522
b4ff3a36 6523 u8 reserved_at_20[0x10];
e281682b
SM		 6524 u8 op_mod[0x10];
6525
b4ff3a36 6526 u8 reserved_at_40[0x8];
e281682b
SM		 6527 u8 pd[0x18];
6528
b4ff3a36 6529 u8 reserved_at_60[0x20];
e281682b
SM		 6530};
6531
9dc0b289
AV		 6532struct mlx5_ifc_dealloc_flow_counter_out_bits {
6533 u8 status[0x8];
6534 u8 reserved_at_8[0x18];
6535
6536 u8 syndrome[0x20];
6537
6538 u8 reserved_at_40[0x40];
6539};
6540
6541struct mlx5_ifc_dealloc_flow_counter_in_bits {
6542 u8 opcode[0x10];
6543 u8 reserved_at_10[0x10];
6544
6545 u8 reserved_at_20[0x10];
6546 u8 op_mod[0x10];
6547
a8ffcc74 6548 u8 flow_counter_id[0x20];
9dc0b289
AV		 6549
6550 u8 reserved_at_60[0x20];
6551};
6552
7486216b
SM		 6553struct mlx5_ifc_create_xrq_out_bits {
6554 u8 status[0x8];
6555 u8 reserved_at_8[0x18];
6556
6557 u8 syndrome[0x20];
6558
6559 u8 reserved_at_40[0x8];
6560 u8 xrqn[0x18];
6561
6562 u8 reserved_at_60[0x20];
6563};
6564
6565struct mlx5_ifc_create_xrq_in_bits {
6566 u8 opcode[0x10];
6567 u8 reserved_at_10[0x10];
6568
6569 u8 reserved_at_20[0x10];
6570 u8 op_mod[0x10];
6571
6572 u8 reserved_at_40[0x40];
6573
6574 struct mlx5_ifc_xrqc_bits xrq_context;
6575};
6576
e281682b
SM		 6577struct mlx5_ifc_create_xrc_srq_out_bits {
6578 u8 status[0x8];
b4ff3a36 6579 u8 reserved_at_8[0x18];
e281682b
SM		 6580
6581 u8 syndrome[0x20];
6582
b4ff3a36 6583 u8 reserved_at_40[0x8];
e281682b
SM		 6584 u8 xrc_srqn[0x18];
6585
b4ff3a36 6586 u8 reserved_at_60[0x20];
e281682b
SM		 6587};
6588
6589struct mlx5_ifc_create_xrc_srq_in_bits {
6590 u8 opcode[0x10];
b4ff3a36 6591 u8 reserved_at_10[0x10];
e281682b 6592
b4ff3a36 6593 u8 reserved_at_20[0x10];
e281682b
SM		 6594 u8 op_mod[0x10];
6595
b4ff3a36 6596 u8 reserved_at_40[0x40];
e281682b
SM		 6597
6598 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6599
b4ff3a36 6600 u8 reserved_at_280[0x600];
e281682b
SM		 6601
6602 u8 pas[0][0x40];
6603};
6604
6605struct mlx5_ifc_create_tis_out_bits {
6606 u8 status[0x8];
b4ff3a36 6607 u8 reserved_at_8[0x18];
e281682b
SM		 6608
6609 u8 syndrome[0x20];
6610
b4ff3a36 6611 u8 reserved_at_40[0x8];
e281682b
SM		 6612 u8 tisn[0x18];
6613
b4ff3a36 6614 u8 reserved_at_60[0x20];
e281682b
SM		 6615};
6616
6617struct mlx5_ifc_create_tis_in_bits {
6618 u8 opcode[0x10];
b4ff3a36 6619 u8 reserved_at_10[0x10];
e281682b 6620
b4ff3a36 6621 u8 reserved_at_20[0x10];
e281682b
SM		 6622 u8 op_mod[0x10];
6623
b4ff3a36 6624 u8 reserved_at_40[0xc0];
e281682b
SM		 6625
6626 struct mlx5_ifc_tisc_bits ctx;
6627};
6628
6629struct mlx5_ifc_create_tir_out_bits {
6630 u8 status[0x8];
b4ff3a36 6631 u8 reserved_at_8[0x18];
e281682b
SM		 6632
6633 u8 syndrome[0x20];
6634
b4ff3a36 6635 u8 reserved_at_40[0x8];
e281682b
SM		 6636 u8 tirn[0x18];
6637
b4ff3a36 6638 u8 reserved_at_60[0x20];
e281682b
SM		 6639};
6640
6641struct mlx5_ifc_create_tir_in_bits {
6642 u8 opcode[0x10];
b4ff3a36 6643 u8 reserved_at_10[0x10];
e281682b 6644
b4ff3a36 6645 u8 reserved_at_20[0x10];
e281682b
SM		 6646 u8 op_mod[0x10];
6647
b4ff3a36 6648 u8 reserved_at_40[0xc0];
e281682b
SM		 6649
6650 struct mlx5_ifc_tirc_bits ctx;
6651};
6652
6653struct mlx5_ifc_create_srq_out_bits {
6654 u8 status[0x8];
b4ff3a36 6655 u8 reserved_at_8[0x18];
e281682b
SM		 6656
6657 u8 syndrome[0x20];
6658
b4ff3a36 6659 u8 reserved_at_40[0x8];
e281682b
SM		 6660 u8 srqn[0x18];
6661
b4ff3a36 6662 u8 reserved_at_60[0x20];
e281682b
SM		 6663};
6664
6665struct mlx5_ifc_create_srq_in_bits {
6666 u8 opcode[0x10];
b4ff3a36 6667 u8 reserved_at_10[0x10];
e281682b 6668
b4ff3a36 6669 u8 reserved_at_20[0x10];
e281682b
SM		 6670 u8 op_mod[0x10];
6671
b4ff3a36 6672 u8 reserved_at_40[0x40];
e281682b
SM		 6673
6674 struct mlx5_ifc_srqc_bits srq_context_entry;
6675
b4ff3a36 6676 u8 reserved_at_280[0x600];
e281682b
SM		 6677
6678 u8 pas[0][0x40];
6679};
6680
6681struct mlx5_ifc_create_sq_out_bits {
6682 u8 status[0x8];
b4ff3a36 6683 u8 reserved_at_8[0x18];
e281682b
SM		 6684
6685 u8 syndrome[0x20];
6686
b4ff3a36 6687 u8 reserved_at_40[0x8];
e281682b
SM		 6688 u8 sqn[0x18];
6689
b4ff3a36 6690 u8 reserved_at_60[0x20];
e281682b
SM		 6691};
6692
6693struct mlx5_ifc_create_sq_in_bits {
6694 u8 opcode[0x10];
b4ff3a36 6695 u8 reserved_at_10[0x10];
e281682b 6696
b4ff3a36 6697 u8 reserved_at_20[0x10];
e281682b
SM		 6698 u8 op_mod[0x10];
6699
b4ff3a36 6700 u8 reserved_at_40[0xc0];
e281682b
SM		 6701
6702 struct mlx5_ifc_sqc_bits ctx;
6703};
6704
813f8540
MHY		 6705struct mlx5_ifc_create_scheduling_element_out_bits {
6706 u8 status[0x8];
6707 u8 reserved_at_8[0x18];
6708
6709 u8 syndrome[0x20];
6710
6711 u8 reserved_at_40[0x40];
6712
6713 u8 scheduling_element_id[0x20];
6714
6715 u8 reserved_at_a0[0x160];
6716};
6717
6718struct mlx5_ifc_create_scheduling_element_in_bits {
6719 u8 opcode[0x10];
6720 u8 reserved_at_10[0x10];
6721
6722 u8 reserved_at_20[0x10];
6723 u8 op_mod[0x10];
6724
6725 u8 scheduling_hierarchy[0x8];
6726 u8 reserved_at_48[0x18];
6727
6728 u8 reserved_at_60[0xa0];
6729
6730 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6731
6732 u8 reserved_at_300[0x100];
6733};
6734
e281682b
SM		 6735struct mlx5_ifc_create_rqt_out_bits {
6736 u8 status[0x8];
b4ff3a36 6737 u8 reserved_at_8[0x18];
e281682b
SM		 6738
6739 u8 syndrome[0x20];
6740
b4ff3a36 6741 u8 reserved_at_40[0x8];
e281682b
SM		 6742 u8 rqtn[0x18];
6743
b4ff3a36 6744 u8 reserved_at_60[0x20];
e281682b
SM		 6745};
6746
6747struct mlx5_ifc_create_rqt_in_bits {
6748 u8 opcode[0x10];
b4ff3a36 6749 u8 reserved_at_10[0x10];
e281682b 6750
b4ff3a36 6751 u8 reserved_at_20[0x10];
e281682b
SM		 6752 u8 op_mod[0x10];
6753
b4ff3a36 6754 u8 reserved_at_40[0xc0];
e281682b
SM		 6755
6756 struct mlx5_ifc_rqtc_bits rqt_context;
6757};
6758
6759struct mlx5_ifc_create_rq_out_bits {
6760 u8 status[0x8];
b4ff3a36 6761 u8 reserved_at_8[0x18];
e281682b
SM		 6762
6763 u8 syndrome[0x20];
6764
b4ff3a36 6765 u8 reserved_at_40[0x8];
e281682b
SM		 6766 u8 rqn[0x18];
6767
b4ff3a36 6768 u8 reserved_at_60[0x20];
e281682b
SM		 6769};
6770
6771struct mlx5_ifc_create_rq_in_bits {
6772 u8 opcode[0x10];
b4ff3a36 6773 u8 reserved_at_10[0x10];
e281682b 6774
b4ff3a36 6775 u8 reserved_at_20[0x10];
e281682b
SM		 6776 u8 op_mod[0x10];
6777
b4ff3a36 6778 u8 reserved_at_40[0xc0];
e281682b
SM		 6779
6780 struct mlx5_ifc_rqc_bits ctx;
6781};
6782
6783struct mlx5_ifc_create_rmp_out_bits {
6784 u8 status[0x8];
b4ff3a36 6785 u8 reserved_at_8[0x18];
e281682b
SM		 6786
6787 u8 syndrome[0x20];
6788
b4ff3a36 6789 u8 reserved_at_40[0x8];
e281682b
SM		 6790 u8 rmpn[0x18];
6791
b4ff3a36 6792 u8 reserved_at_60[0x20];
e281682b
SM		 6793};
6794
6795struct mlx5_ifc_create_rmp_in_bits {
6796 u8 opcode[0x10];
b4ff3a36 6797 u8 reserved_at_10[0x10];
e281682b 6798
b4ff3a36 6799 u8 reserved_at_20[0x10];
e281682b
SM		 6800 u8 op_mod[0x10];
6801
b4ff3a36 6802 u8 reserved_at_40[0xc0];
e281682b
SM		 6803
6804 struct mlx5_ifc_rmpc_bits ctx;
6805};
6806
6807struct mlx5_ifc_create_qp_out_bits {
6808 u8 status[0x8];
b4ff3a36 6809 u8 reserved_at_8[0x18];
e281682b
SM		 6810
6811 u8 syndrome[0x20];
6812
b4ff3a36 6813 u8 reserved_at_40[0x8];
e281682b
SM		 6814 u8 qpn[0x18];
6815
b4ff3a36 6816 u8 reserved_at_60[0x20];
e281682b
SM		 6817};
6818
6819struct mlx5_ifc_create_qp_in_bits {
6820 u8 opcode[0x10];
b4ff3a36 6821 u8 reserved_at_10[0x10];
e281682b 6822
b4ff3a36 6823 u8 reserved_at_20[0x10];
e281682b
SM		 6824 u8 op_mod[0x10];
6825
b4ff3a36 6826 u8 reserved_at_40[0x40];
e281682b
SM		 6827
6828 u8 opt_param_mask[0x20];
6829
b4ff3a36 6830 u8 reserved_at_a0[0x20];
e281682b
SM		 6831
6832 struct mlx5_ifc_qpc_bits qpc;
6833
b4ff3a36 6834 u8 reserved_at_800[0x80];
e281682b
SM		 6835
6836 u8 pas[0][0x40];
6837};
6838
6839struct mlx5_ifc_create_psv_out_bits {
6840 u8 status[0x8];
b4ff3a36 6841 u8 reserved_at_8[0x18];
e281682b
SM		 6842
6843 u8 syndrome[0x20];
6844
b4ff3a36 6845 u8 reserved_at_40[0x40];
e281682b 6846
b4ff3a36 6847 u8 reserved_at_80[0x8];
e281682b
SM		 6848 u8 psv0_index[0x18];
6849
b4ff3a36 6850 u8 reserved_at_a0[0x8];
e281682b
SM		 6851 u8 psv1_index[0x18];
6852
b4ff3a36 6853 u8 reserved_at_c0[0x8];
e281682b
SM		 6854 u8 psv2_index[0x18];
6855
b4ff3a36 6856 u8 reserved_at_e0[0x8];
e281682b
SM		 6857 u8 psv3_index[0x18];
6858};
6859
6860struct mlx5_ifc_create_psv_in_bits {
6861 u8 opcode[0x10];
b4ff3a36 6862 u8 reserved_at_10[0x10];
e281682b 6863
b4ff3a36 6864 u8 reserved_at_20[0x10];
e281682b
SM		 6865 u8 op_mod[0x10];
6866
6867 u8 num_psv[0x4];
b4ff3a36 6868 u8 reserved_at_44[0x4];
e281682b
SM		 6869 u8 pd[0x18];
6870
b4ff3a36 6871 u8 reserved_at_60[0x20];
e281682b
SM		 6872};
6873
6874struct mlx5_ifc_create_mkey_out_bits {
6875 u8 status[0x8];
b4ff3a36 6876 u8 reserved_at_8[0x18];
e281682b
SM		 6877
6878 u8 syndrome[0x20];
6879
b4ff3a36 6880 u8 reserved_at_40[0x8];
e281682b
SM		 6881 u8 mkey_index[0x18];
6882
b4ff3a36 6883 u8 reserved_at_60[0x20];
e281682b
SM		 6884};
6885
6886struct mlx5_ifc_create_mkey_in_bits {
6887 u8 opcode[0x10];
b4ff3a36 6888 u8 reserved_at_10[0x10];
e281682b 6889
b4ff3a36 6890 u8 reserved_at_20[0x10];
e281682b
SM		 6891 u8 op_mod[0x10];
6892
b4ff3a36 6893 u8 reserved_at_40[0x20];
e281682b
SM		 6894
6895 u8 pg_access[0x1];
b4ff3a36 6896 u8 reserved_at_61[0x1f];
e281682b
SM		 6897
6898 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6899
b4ff3a36 6900 u8 reserved_at_280[0x80];
e281682b
SM		 6901
6902 u8 translations_octword_actual_size[0x20];
6903
b4ff3a36 6904 u8 reserved_at_320[0x560];
e281682b
SM		 6905
6906 u8 klm_pas_mtt[0][0x20];
6907};
6908
6909struct mlx5_ifc_create_flow_table_out_bits {
6910 u8 status[0x8];
b4ff3a36 6911 u8 reserved_at_8[0x18];
e281682b
SM		 6912
6913 u8 syndrome[0x20];
6914
b4ff3a36 6915 u8 reserved_at_40[0x8];
e281682b
SM		 6916 u8 table_id[0x18];
6917
b4ff3a36 6918 u8 reserved_at_60[0x20];
e281682b
SM		 6919};
6920
0c90e9c6
MG		 6921struct mlx5_ifc_flow_table_context_bits {
6922 u8 encap_en[0x1];
6923 u8 decap_en[0x1];
6924 u8 reserved_at_2[0x2];
6925 u8 table_miss_action[0x4];
6926 u8 level[0x8];
6927 u8 reserved_at_10[0x8];
6928 u8 log_size[0x8];
6929
6930 u8 reserved_at_20[0x8];
6931 u8 table_miss_id[0x18];
6932
6933 u8 reserved_at_40[0x8];
6934 u8 lag_master_next_table_id[0x18];
6935
6936 u8 reserved_at_60[0xe0];
6937};
6938
e281682b
SM		 6939struct mlx5_ifc_create_flow_table_in_bits {
6940 u8 opcode[0x10];
b4ff3a36 6941 u8 reserved_at_10[0x10];
e281682b 6942
b4ff3a36 6943 u8 reserved_at_20[0x10];
e281682b
SM		 6944 u8 op_mod[0x10];
6945
7d5e1423
SM		 6946 u8 other_vport[0x1];
6947 u8 reserved_at_41[0xf];
6948 u8 vport_number[0x10];
6949
6950 u8 reserved_at_60[0x20];
e281682b
SM		 6951
6952 u8 table_type[0x8];
b4ff3a36 6953 u8 reserved_at_88[0x18];
e281682b 6954
b4ff3a36 6955 u8 reserved_at_a0[0x20];
e281682b 6956
0c90e9c6 6957 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6958};
6959
6960struct mlx5_ifc_create_flow_group_out_bits {
6961 u8 status[0x8];
b4ff3a36 6962 u8 reserved_at_8[0x18];
e281682b
SM		 6963
6964 u8 syndrome[0x20];
6965
b4ff3a36 6966 u8 reserved_at_40[0x8];
e281682b
SM		 6967 u8 group_id[0x18];
6968
b4ff3a36 6969 u8 reserved_at_60[0x20];
e281682b
SM		 6970};
6971
6972enum {
6973 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6974 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6975 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6976};
6977
6978struct mlx5_ifc_create_flow_group_in_bits {
6979 u8 opcode[0x10];
b4ff3a36 6980 u8 reserved_at_10[0x10];
e281682b 6981
b4ff3a36 6982 u8 reserved_at_20[0x10];
e281682b
SM		 6983 u8 op_mod[0x10];
6984
7d5e1423
SM		 6985 u8 other_vport[0x1];
6986 u8 reserved_at_41[0xf];
6987 u8 vport_number[0x10];
6988
6989 u8 reserved_at_60[0x20];
e281682b
SM		 6990
6991 u8 table_type[0x8];
b4ff3a36 6992 u8 reserved_at_88[0x18];
e281682b 6993
b4ff3a36 6994 u8 reserved_at_a0[0x8];
e281682b
SM		 6995 u8 table_id[0x18];
6996
b4ff3a36 6997 u8 reserved_at_c0[0x20];
e281682b
SM		 6998
6999 u8 start_flow_index[0x20];
7000
b4ff3a36 7001 u8 reserved_at_100[0x20];
e281682b
SM		 7002
7003 u8 end_flow_index[0x20];
7004
b4ff3a36 7005 u8 reserved_at_140[0xa0];
e281682b 7006
b4ff3a36 7007 u8 reserved_at_1e0[0x18];
e281682b
SM		 7008 u8 match_criteria_enable[0x8];
7009
7010 struct mlx5_ifc_fte_match_param_bits match_criteria;
7011
b4ff3a36 7012 u8 reserved_at_1200[0xe00];
e281682b
SM		 7013};
7014
7015struct mlx5_ifc_create_eq_out_bits {
7016 u8 status[0x8];
b4ff3a36 7017 u8 reserved_at_8[0x18];
e281682b
SM		 7018
7019 u8 syndrome[0x20];
7020
b4ff3a36 7021 u8 reserved_at_40[0x18];
e281682b
SM		 7022 u8 eq_number[0x8];
7023
b4ff3a36 7024 u8 reserved_at_60[0x20];
e281682b
SM		 7025};
7026
7027struct mlx5_ifc_create_eq_in_bits {
7028 u8 opcode[0x10];
b4ff3a36 7029 u8 reserved_at_10[0x10];
e281682b 7030
b4ff3a36 7031 u8 reserved_at_20[0x10];
e281682b
SM		 7032 u8 op_mod[0x10];
7033
b4ff3a36 7034 u8 reserved_at_40[0x40];
e281682b
SM		 7035
7036 struct mlx5_ifc_eqc_bits eq_context_entry;
7037
b4ff3a36 7038 u8 reserved_at_280[0x40];
e281682b
SM		 7039
7040 u8 event_bitmask[0x40];
7041
b4ff3a36 7042 u8 reserved_at_300[0x580];
e281682b
SM		 7043
7044 u8 pas[0][0x40];
7045};
7046
7047struct mlx5_ifc_create_dct_out_bits {
7048 u8 status[0x8];
b4ff3a36 7049 u8 reserved_at_8[0x18];
e281682b
SM		 7050
7051 u8 syndrome[0x20];
7052
b4ff3a36 7053 u8 reserved_at_40[0x8];
e281682b
SM		 7054 u8 dctn[0x18];
7055
b4ff3a36 7056 u8 reserved_at_60[0x20];
e281682b
SM		 7057};
7058
7059struct mlx5_ifc_create_dct_in_bits {
7060 u8 opcode[0x10];
b4ff3a36 7061 u8 reserved_at_10[0x10];
e281682b 7062
b4ff3a36 7063 u8 reserved_at_20[0x10];
e281682b
SM		 7064 u8 op_mod[0x10];
7065
b4ff3a36 7066 u8 reserved_at_40[0x40];
e281682b
SM		 7067
7068 struct mlx5_ifc_dctc_bits dct_context_entry;
7069
b4ff3a36 7070 u8 reserved_at_280[0x180];
e281682b
SM		 7071};
7072
7073struct mlx5_ifc_create_cq_out_bits {
7074 u8 status[0x8];
b4ff3a36 7075 u8 reserved_at_8[0x18];
e281682b
SM		 7076
7077 u8 syndrome[0x20];
7078
b4ff3a36 7079 u8 reserved_at_40[0x8];
e281682b
SM		 7080 u8 cqn[0x18];
7081
b4ff3a36 7082 u8 reserved_at_60[0x20];
e281682b
SM		 7083};
7084
7085struct mlx5_ifc_create_cq_in_bits {
7086 u8 opcode[0x10];
b4ff3a36 7087 u8 reserved_at_10[0x10];
e281682b 7088
b4ff3a36 7089 u8 reserved_at_20[0x10];
e281682b
SM		 7090 u8 op_mod[0x10];
7091
b4ff3a36 7092 u8 reserved_at_40[0x40];
e281682b
SM		 7093
7094 struct mlx5_ifc_cqc_bits cq_context;
7095
b4ff3a36 7096 u8 reserved_at_280[0x600];
e281682b
SM		 7097
7098 u8 pas[0][0x40];
7099};
7100
7101struct mlx5_ifc_config_int_moderation_out_bits {
7102 u8 status[0x8];
b4ff3a36 7103 u8 reserved_at_8[0x18];
e281682b
SM		 7104
7105 u8 syndrome[0x20];
7106
b4ff3a36 7107 u8 reserved_at_40[0x4];
e281682b
SM		 7108 u8 min_delay[0xc];
7109 u8 int_vector[0x10];
7110
b4ff3a36 7111 u8 reserved_at_60[0x20];
e281682b
SM		 7112};
7113
7114enum {
7115 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7116 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7117};
7118
7119struct mlx5_ifc_config_int_moderation_in_bits {
7120 u8 opcode[0x10];
b4ff3a36 7121 u8 reserved_at_10[0x10];
e281682b 7122
b4ff3a36 7123 u8 reserved_at_20[0x10];
e281682b
SM		 7124 u8 op_mod[0x10];
7125
b4ff3a36 7126 u8 reserved_at_40[0x4];
e281682b
SM		 7127 u8 min_delay[0xc];
7128 u8 int_vector[0x10];
7129
b4ff3a36 7130 u8 reserved_at_60[0x20];
e281682b
SM		 7131};
7132
7133struct mlx5_ifc_attach_to_mcg_out_bits {
7134 u8 status[0x8];
b4ff3a36 7135 u8 reserved_at_8[0x18];
e281682b
SM		 7136
7137 u8 syndrome[0x20];
7138
b4ff3a36 7139 u8 reserved_at_40[0x40];
e281682b
SM		 7140};
7141
7142struct mlx5_ifc_attach_to_mcg_in_bits {
7143 u8 opcode[0x10];
b4ff3a36 7144 u8 reserved_at_10[0x10];
e281682b 7145
b4ff3a36 7146 u8 reserved_at_20[0x10];
e281682b
SM		 7147 u8 op_mod[0x10];
7148
b4ff3a36 7149 u8 reserved_at_40[0x8];
e281682b
SM		 7150 u8 qpn[0x18];
7151
b4ff3a36 7152 u8 reserved_at_60[0x20];
e281682b
SM		 7153
7154 u8 multicast_gid[16][0x8];
7155};
7156
7486216b
SM		 7157struct mlx5_ifc_arm_xrq_out_bits {
7158 u8 status[0x8];
7159 u8 reserved_at_8[0x18];
7160
7161 u8 syndrome[0x20];
7162
7163 u8 reserved_at_40[0x40];
7164};
7165
7166struct mlx5_ifc_arm_xrq_in_bits {
7167 u8 opcode[0x10];
7168 u8 reserved_at_10[0x10];
7169
7170 u8 reserved_at_20[0x10];
7171 u8 op_mod[0x10];
7172
7173 u8 reserved_at_40[0x8];
7174 u8 xrqn[0x18];
7175
7176 u8 reserved_at_60[0x10];
7177 u8 lwm[0x10];
7178};
7179
e281682b
SM		 7180struct mlx5_ifc_arm_xrc_srq_out_bits {
7181 u8 status[0x8];
b4ff3a36 7182 u8 reserved_at_8[0x18];
e281682b
SM		 7183
7184 u8 syndrome[0x20];
7185
b4ff3a36 7186 u8 reserved_at_40[0x40];
e281682b
SM		 7187};
7188
7189enum {
7190 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7191};
7192
7193struct mlx5_ifc_arm_xrc_srq_in_bits {
7194 u8 opcode[0x10];
b4ff3a36 7195 u8 reserved_at_10[0x10];
e281682b 7196
b4ff3a36 7197 u8 reserved_at_20[0x10];
e281682b
SM		 7198 u8 op_mod[0x10];
7199
b4ff3a36 7200 u8 reserved_at_40[0x8];
e281682b
SM		 7201 u8 xrc_srqn[0x18];
7202
b4ff3a36 7203 u8 reserved_at_60[0x10];
e281682b
SM		 7204 u8 lwm[0x10];
7205};
7206
7207struct mlx5_ifc_arm_rq_out_bits {
7208 u8 status[0x8];
b4ff3a36 7209 u8 reserved_at_8[0x18];
e281682b
SM		 7210
7211 u8 syndrome[0x20];
7212
b4ff3a36 7213 u8 reserved_at_40[0x40];
e281682b
SM		 7214};
7215
7216enum {
7486216b
SM		 7217 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7218 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7219};
7220
7221struct mlx5_ifc_arm_rq_in_bits {
7222 u8 opcode[0x10];
b4ff3a36 7223 u8 reserved_at_10[0x10];
e281682b 7224
b4ff3a36 7225 u8 reserved_at_20[0x10];
e281682b
SM		 7226 u8 op_mod[0x10];
7227
b4ff3a36 7228 u8 reserved_at_40[0x8];
e281682b
SM		 7229 u8 srq_number[0x18];
7230
b4ff3a36 7231 u8 reserved_at_60[0x10];
e281682b
SM		 7232 u8 lwm[0x10];
7233};
7234
7235struct mlx5_ifc_arm_dct_out_bits {
7236 u8 status[0x8];
b4ff3a36 7237 u8 reserved_at_8[0x18];
e281682b
SM		 7238
7239 u8 syndrome[0x20];
7240
b4ff3a36 7241 u8 reserved_at_40[0x40];
e281682b
SM		 7242};
7243
7244struct mlx5_ifc_arm_dct_in_bits {
7245 u8 opcode[0x10];
b4ff3a36 7246 u8 reserved_at_10[0x10];
e281682b 7247
b4ff3a36 7248 u8 reserved_at_20[0x10];
e281682b
SM		 7249 u8 op_mod[0x10];
7250
b4ff3a36 7251 u8 reserved_at_40[0x8];
e281682b
SM		 7252 u8 dct_number[0x18];
7253
b4ff3a36 7254 u8 reserved_at_60[0x20];
e281682b
SM		 7255};
7256
7257struct mlx5_ifc_alloc_xrcd_out_bits {
7258 u8 status[0x8];
b4ff3a36 7259 u8 reserved_at_8[0x18];
e281682b
SM		 7260
7261 u8 syndrome[0x20];
7262
b4ff3a36 7263 u8 reserved_at_40[0x8];
e281682b
SM		 7264 u8 xrcd[0x18];
7265
b4ff3a36 7266 u8 reserved_at_60[0x20];
e281682b
SM		 7267};
7268
7269struct mlx5_ifc_alloc_xrcd_in_bits {
7270 u8 opcode[0x10];
b4ff3a36 7271 u8 reserved_at_10[0x10];
e281682b 7272
b4ff3a36 7273 u8 reserved_at_20[0x10];
e281682b
SM		 7274 u8 op_mod[0x10];
7275
b4ff3a36 7276 u8 reserved_at_40[0x40];
e281682b
SM		 7277};
7278
7279struct mlx5_ifc_alloc_uar_out_bits {
7280 u8 status[0x8];
b4ff3a36 7281 u8 reserved_at_8[0x18];
e281682b
SM		 7282
7283 u8 syndrome[0x20];
7284
b4ff3a36 7285 u8 reserved_at_40[0x8];
e281682b
SM		 7286 u8 uar[0x18];
7287
b4ff3a36 7288 u8 reserved_at_60[0x20];
e281682b
SM		 7289};
7290
7291struct mlx5_ifc_alloc_uar_in_bits {
7292 u8 opcode[0x10];
b4ff3a36 7293 u8 reserved_at_10[0x10];
e281682b 7294
b4ff3a36 7295 u8 reserved_at_20[0x10];
e281682b
SM		 7296 u8 op_mod[0x10];
7297
b4ff3a36 7298 u8 reserved_at_40[0x40];
e281682b
SM		 7299};
7300
7301struct mlx5_ifc_alloc_transport_domain_out_bits {
7302 u8 status[0x8];
b4ff3a36 7303 u8 reserved_at_8[0x18];
e281682b
SM		 7304
7305 u8 syndrome[0x20];
7306
b4ff3a36 7307 u8 reserved_at_40[0x8];
e281682b
SM		 7308 u8 transport_domain[0x18];
7309
b4ff3a36 7310 u8 reserved_at_60[0x20];
e281682b
SM		 7311};
7312
7313struct mlx5_ifc_alloc_transport_domain_in_bits {
7314 u8 opcode[0x10];
b4ff3a36 7315 u8 reserved_at_10[0x10];
e281682b 7316
b4ff3a36 7317 u8 reserved_at_20[0x10];
e281682b
SM		 7318 u8 op_mod[0x10];
7319
b4ff3a36 7320 u8 reserved_at_40[0x40];
e281682b
SM		 7321};
7322
7323struct mlx5_ifc_alloc_q_counter_out_bits {
7324 u8 status[0x8];
b4ff3a36 7325 u8 reserved_at_8[0x18];
e281682b
SM		 7326
7327 u8 syndrome[0x20];
7328
b4ff3a36 7329 u8 reserved_at_40[0x18];
e281682b
SM		 7330 u8 counter_set_id[0x8];
7331
b4ff3a36 7332 u8 reserved_at_60[0x20];
e281682b
SM		 7333};
7334
7335struct mlx5_ifc_alloc_q_counter_in_bits {
7336 u8 opcode[0x10];
b4ff3a36 7337 u8 reserved_at_10[0x10];
e281682b 7338
b4ff3a36 7339 u8 reserved_at_20[0x10];
e281682b
SM		 7340 u8 op_mod[0x10];
7341
b4ff3a36 7342 u8 reserved_at_40[0x40];
e281682b
SM		 7343};
7344
7345struct mlx5_ifc_alloc_pd_out_bits {
7346 u8 status[0x8];
b4ff3a36 7347 u8 reserved_at_8[0x18];
e281682b
SM		 7348
7349 u8 syndrome[0x20];
7350
b4ff3a36 7351 u8 reserved_at_40[0x8];
e281682b
SM		 7352 u8 pd[0x18];
7353
b4ff3a36 7354 u8 reserved_at_60[0x20];
e281682b
SM		 7355};
7356
7357struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7358 u8 opcode[0x10];
7359 u8 reserved_at_10[0x10];
7360
7361 u8 reserved_at_20[0x10];
7362 u8 op_mod[0x10];
7363
7364 u8 reserved_at_40[0x40];
7365};
7366
7367struct mlx5_ifc_alloc_flow_counter_out_bits {
7368 u8 status[0x8];
7369 u8 reserved_at_8[0x18];
7370
7371 u8 syndrome[0x20];
7372
a8ffcc74 7373 u8 flow_counter_id[0x20];
9dc0b289
AV		 7374
7375 u8 reserved_at_60[0x20];
7376};
7377
7378struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7379 u8 opcode[0x10];
b4ff3a36 7380 u8 reserved_at_10[0x10];
e281682b 7381
b4ff3a36 7382 u8 reserved_at_20[0x10];
e281682b
SM		 7383 u8 op_mod[0x10];
7384
b4ff3a36 7385 u8 reserved_at_40[0x40];
e281682b
SM		 7386};
7387
7388struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7389 u8 status[0x8];
b4ff3a36 7390 u8 reserved_at_8[0x18];
e281682b
SM		 7391
7392 u8 syndrome[0x20];
7393
b4ff3a36 7394 u8 reserved_at_40[0x40];
e281682b
SM		 7395};
7396
7397struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7398 u8 opcode[0x10];
b4ff3a36 7399 u8 reserved_at_10[0x10];
e281682b 7400
b4ff3a36 7401 u8 reserved_at_20[0x10];
e281682b
SM		 7402 u8 op_mod[0x10];
7403
b4ff3a36 7404 u8 reserved_at_40[0x20];
e281682b 7405
b4ff3a36 7406 u8 reserved_at_60[0x10];
e281682b
SM		 7407 u8 vxlan_udp_port[0x10];
7408};
7409
37e92a9d 7410struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7411 u8 status[0x8];
7412 u8 reserved_at_8[0x18];
7413
7414 u8 syndrome[0x20];
7415
7416 u8 reserved_at_40[0x40];
7417};
7418
37e92a9d 7419struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7420 u8 opcode[0x10];
7421 u8 reserved_at_10[0x10];
7422
7423 u8 reserved_at_20[0x10];
7424 u8 op_mod[0x10];
7425
7426 u8 reserved_at_40[0x10];
7427 u8 rate_limit_index[0x10];
7428
7429 u8 reserved_at_60[0x20];
7430
7431 u8 rate_limit[0x20];
37e92a9d 7432
05d3ac97
BW		 7433 u8 burst_upper_bound[0x20];
7434
7435 u8 reserved_at_c0[0x10];
7436 u8 typical_packet_size[0x10];
7437
7438 u8 reserved_at_e0[0x120];
7486216b
SM		 7439};
7440
e281682b
SM		 7441struct mlx5_ifc_access_register_out_bits {
7442 u8 status[0x8];
b4ff3a36 7443 u8 reserved_at_8[0x18];
e281682b
SM		 7444
7445 u8 syndrome[0x20];
7446
b4ff3a36 7447 u8 reserved_at_40[0x40];
e281682b
SM		 7448
7449 u8 register_data[0][0x20];
7450};
7451
7452enum {
7453 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7454 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7455};
7456
7457struct mlx5_ifc_access_register_in_bits {
7458 u8 opcode[0x10];
b4ff3a36 7459 u8 reserved_at_10[0x10];
e281682b 7460
b4ff3a36 7461 u8 reserved_at_20[0x10];
e281682b
SM		 7462 u8 op_mod[0x10];
7463
b4ff3a36 7464 u8 reserved_at_40[0x10];
e281682b
SM		 7465 u8 register_id[0x10];
7466
7467 u8 argument[0x20];
7468
7469 u8 register_data[0][0x20];
7470};
7471
7472struct mlx5_ifc_sltp_reg_bits {
7473 u8 status[0x4];
7474 u8 version[0x4];
7475 u8 local_port[0x8];
7476 u8 pnat[0x2];
b4ff3a36 7477 u8 reserved_at_12[0x2];
e281682b 7478 u8 lane[0x4];
b4ff3a36 7479 u8 reserved_at_18[0x8];
e281682b 7480
b4ff3a36 7481 u8 reserved_at_20[0x20];
e281682b 7482
b4ff3a36 7483 u8 reserved_at_40[0x7];
e281682b
SM		 7484 u8 polarity[0x1];
7485 u8 ob_tap0[0x8];
7486 u8 ob_tap1[0x8];
7487 u8 ob_tap2[0x8];
7488
b4ff3a36 7489 u8 reserved_at_60[0xc];
e281682b
SM		 7490 u8 ob_preemp_mode[0x4];
7491 u8 ob_reg[0x8];
7492 u8 ob_bias[0x8];
7493
b4ff3a36 7494 u8 reserved_at_80[0x20];
e281682b
SM		 7495};
7496
7497struct mlx5_ifc_slrg_reg_bits {
7498 u8 status[0x4];
7499 u8 version[0x4];
7500 u8 local_port[0x8];
7501 u8 pnat[0x2];
b4ff3a36 7502 u8 reserved_at_12[0x2];
e281682b 7503 u8 lane[0x4];
b4ff3a36 7504 u8 reserved_at_18[0x8];
e281682b
SM		 7505
7506 u8 time_to_link_up[0x10];
b4ff3a36 7507 u8 reserved_at_30[0xc];
e281682b
SM		 7508 u8 grade_lane_speed[0x4];
7509
7510 u8 grade_version[0x8];
7511 u8 grade[0x18];
7512
b4ff3a36 7513 u8 reserved_at_60[0x4];
e281682b
SM		 7514 u8 height_grade_type[0x4];
7515 u8 height_grade[0x18];
7516
7517 u8 height_dz[0x10];
7518 u8 height_dv[0x10];
7519
b4ff3a36 7520 u8 reserved_at_a0[0x10];
e281682b
SM		 7521 u8 height_sigma[0x10];
7522
b4ff3a36 7523 u8 reserved_at_c0[0x20];
e281682b 7524
b4ff3a36 7525 u8 reserved_at_e0[0x4];
e281682b
SM		 7526 u8 phase_grade_type[0x4];
7527 u8 phase_grade[0x18];
7528
b4ff3a36 7529 u8 reserved_at_100[0x8];
e281682b 7530 u8 phase_eo_pos[0x8];
b4ff3a36 7531 u8 reserved_at_110[0x8];
e281682b
SM		 7532 u8 phase_eo_neg[0x8];
7533
7534 u8 ffe_set_tested[0x10];
7535 u8 test_errors_per_lane[0x10];
7536};
7537
7538struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7539 u8 reserved_at_0[0x8];
e281682b 7540 u8 local_port[0x8];
b4ff3a36 7541 u8 reserved_at_10[0x10];
e281682b 7542
b4ff3a36 7543 u8 reserved_at_20[0x1c];
e281682b
SM		 7544 u8 vl_hw_cap[0x4];
7545
b4ff3a36 7546 u8 reserved_at_40[0x1c];
e281682b
SM		 7547 u8 vl_admin[0x4];
7548
b4ff3a36 7549 u8 reserved_at_60[0x1c];
e281682b
SM		 7550 u8 vl_operational[0x4];
7551};
7552
7553struct mlx5_ifc_pude_reg_bits {
7554 u8 swid[0x8];
7555 u8 local_port[0x8];
b4ff3a36 7556 u8 reserved_at_10[0x4];
e281682b 7557 u8 admin_status[0x4];
b4ff3a36 7558 u8 reserved_at_18[0x4];
e281682b
SM		 7559 u8 oper_status[0x4];
7560
b4ff3a36 7561 u8 reserved_at_20[0x60];
e281682b
SM		 7562};
7563
7564struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7565 u8 reserved_at_0[0x1];
7486216b 7566 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7567 u8 an_disable_cap[0x1];
7568 u8 reserved_at_3[0x5];
e281682b 7569 u8 local_port[0x8];
b4ff3a36 7570 u8 reserved_at_10[0xd];
e281682b
SM		 7571 u8 proto_mask[0x3];
7572
7486216b
SM		 7573 u8 an_status[0x4];
7574 u8 reserved_at_24[0x3c];
e281682b
SM		 7575
7576 u8 eth_proto_capability[0x20];
7577
7578 u8 ib_link_width_capability[0x10];
7579 u8 ib_proto_capability[0x10];
7580
b4ff3a36 7581 u8 reserved_at_a0[0x20];
e281682b
SM		 7582
7583 u8 eth_proto_admin[0x20];
7584
7585 u8 ib_link_width_admin[0x10];
7586 u8 ib_proto_admin[0x10];
7587
b4ff3a36 7588 u8 reserved_at_100[0x20];
e281682b
SM		 7589
7590 u8 eth_proto_oper[0x20];
7591
7592 u8 ib_link_width_oper[0x10];
7593 u8 ib_proto_oper[0x10];
7594
5b4793f8
EBE		 7595 u8 reserved_at_160[0x1c];
7596 u8 connector_type[0x4];
e281682b
SM		 7597
7598 u8 eth_proto_lp_advertise[0x20];
7599
b4ff3a36 7600 u8 reserved_at_1a0[0x60];
e281682b
SM		 7601};
7602
7d5e1423
SM		 7603struct mlx5_ifc_mlcr_reg_bits {
7604 u8 reserved_at_0[0x8];
7605 u8 local_port[0x8];
7606 u8 reserved_at_10[0x20];
7607
7608 u8 beacon_duration[0x10];
7609 u8 reserved_at_40[0x10];
7610
7611 u8 beacon_remain[0x10];
7612};
7613
e281682b 7614struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7615 u8 reserved_at_0[0x20];
e281682b
SM		 7616
7617 u8 algorithm_options[0x10];
b4ff3a36 7618 u8 reserved_at_30[0x4];
e281682b
SM		 7619 u8 repetitions_mode[0x4];
7620 u8 num_of_repetitions[0x8];
7621
7622 u8 grade_version[0x8];
7623 u8 height_grade_type[0x4];
7624 u8 phase_grade_type[0x4];
7625 u8 height_grade_weight[0x8];
7626 u8 phase_grade_weight[0x8];
7627
7628 u8 gisim_measure_bits[0x10];
7629 u8 adaptive_tap_measure_bits[0x10];
7630
7631 u8 ber_bath_high_error_threshold[0x10];
7632 u8 ber_bath_mid_error_threshold[0x10];
7633
7634 u8 ber_bath_low_error_threshold[0x10];
7635 u8 one_ratio_high_threshold[0x10];
7636
7637 u8 one_ratio_high_mid_threshold[0x10];
7638 u8 one_ratio_low_mid_threshold[0x10];
7639
7640 u8 one_ratio_low_threshold[0x10];
7641 u8 ndeo_error_threshold[0x10];
7642
7643 u8 mixer_offset_step_size[0x10];
b4ff3a36 7644 u8 reserved_at_110[0x8];
e281682b
SM		 7645 u8 mix90_phase_for_voltage_bath[0x8];
7646
7647 u8 mixer_offset_start[0x10];
7648 u8 mixer_offset_end[0x10];
7649
b4ff3a36 7650 u8 reserved_at_140[0x15];
e281682b
SM		 7651 u8 ber_test_time[0xb];
7652};
7653
7654struct mlx5_ifc_pspa_reg_bits {
7655 u8 swid[0x8];
7656 u8 local_port[0x8];
7657 u8 sub_port[0x8];
b4ff3a36 7658 u8 reserved_at_18[0x8];
e281682b 7659
b4ff3a36 7660 u8 reserved_at_20[0x20];
e281682b
SM		 7661};
7662
7663struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7664 u8 reserved_at_0[0x8];
e281682b 7665 u8 local_port[0x8];
b4ff3a36 7666 u8 reserved_at_10[0x5];
e281682b 7667 u8 prio[0x3];
b4ff3a36 7668 u8 reserved_at_18[0x6];
e281682b
SM		 7669 u8 mode[0x2];
7670
b4ff3a36 7671 u8 reserved_at_20[0x20];
e281682b 7672
b4ff3a36 7673 u8 reserved_at_40[0x10];
e281682b
SM		 7674 u8 min_threshold[0x10];
7675
b4ff3a36 7676 u8 reserved_at_60[0x10];
e281682b
SM		 7677 u8 max_threshold[0x10];
7678
b4ff3a36 7679 u8 reserved_at_80[0x10];
e281682b
SM		 7680 u8 mark_probability_denominator[0x10];
7681
b4ff3a36 7682 u8 reserved_at_a0[0x60];
e281682b
SM		 7683};
7684
7685struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7686 u8 reserved_at_0[0x8];
e281682b 7687 u8 local_port[0x8];
b4ff3a36 7688 u8 reserved_at_10[0x10];
e281682b 7689
b4ff3a36 7690 u8 reserved_at_20[0x60];
e281682b 7691
b4ff3a36 7692 u8 reserved_at_80[0x1c];
e281682b
SM		 7693 u8 wrps_admin[0x4];
7694
b4ff3a36 7695 u8 reserved_at_a0[0x1c];
e281682b
SM		 7696 u8 wrps_status[0x4];
7697
b4ff3a36 7698 u8 reserved_at_c0[0x8];
e281682b 7699 u8 up_threshold[0x8];
b4ff3a36 7700 u8 reserved_at_d0[0x8];
e281682b
SM		 7701 u8 down_threshold[0x8];
7702
b4ff3a36 7703 u8 reserved_at_e0[0x20];
e281682b 7704
b4ff3a36 7705 u8 reserved_at_100[0x1c];
e281682b
SM		 7706 u8 srps_admin[0x4];
7707
b4ff3a36 7708 u8 reserved_at_120[0x1c];
e281682b
SM		 7709 u8 srps_status[0x4];
7710
b4ff3a36 7711 u8 reserved_at_140[0x40];
e281682b
SM		 7712};
7713
7714struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7715 u8 reserved_at_0[0x8];
e281682b 7716 u8 local_port[0x8];
b4ff3a36 7717 u8 reserved_at_10[0x10];
e281682b 7718
b4ff3a36 7719 u8 reserved_at_20[0x8];
e281682b 7720 u8 lb_cap[0x8];
b4ff3a36 7721 u8 reserved_at_30[0x8];
e281682b
SM		 7722 u8 lb_en[0x8];
7723};
7724
7725struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7726 u8 reserved_at_0[0x8];
e281682b 7727 u8 local_port[0x8];
b4ff3a36 7728 u8 reserved_at_10[0x10];
e281682b 7729
b4ff3a36 7730 u8 reserved_at_20[0x20];
e281682b
SM		 7731
7732 u8 port_profile_mode[0x8];
7733 u8 static_port_profile[0x8];
7734 u8 active_port_profile[0x8];
b4ff3a36 7735 u8 reserved_at_58[0x8];
e281682b
SM		 7736
7737 u8 retransmission_active[0x8];
7738 u8 fec_mode_active[0x18];
7739
b4ff3a36 7740 u8 reserved_at_80[0x20];
e281682b
SM		 7741};
7742
7743struct mlx5_ifc_ppcnt_reg_bits {
7744 u8 swid[0x8];
7745 u8 local_port[0x8];
7746 u8 pnat[0x2];
b4ff3a36 7747 u8 reserved_at_12[0x8];
e281682b
SM		 7748 u8 grp[0x6];
7749
7750 u8 clr[0x1];
b4ff3a36 7751 u8 reserved_at_21[0x1c];
e281682b
SM		 7752 u8 prio_tc[0x3];
7753
7754 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7755};
7756
8ed1a630
GP		 7757struct mlx5_ifc_mpcnt_reg_bits {
7758 u8 reserved_at_0[0x8];
7759 u8 pcie_index[0x8];
7760 u8 reserved_at_10[0xa];
7761 u8 grp[0x6];
7762
7763 u8 clr[0x1];
7764 u8 reserved_at_21[0x1f];
7765
7766 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7767};
7768
e281682b 7769struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7770 u8 reserved_at_0[0x3];
e281682b 7771 u8 single_mac[0x1];
b4ff3a36 7772 u8 reserved_at_4[0x4];
e281682b
SM		 7773 u8 local_port[0x8];
7774 u8 mac_47_32[0x10];
7775
7776 u8 mac_31_0[0x20];
7777
b4ff3a36 7778 u8 reserved_at_40[0x40];
e281682b
SM		 7779};
7780
7781struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7782 u8 reserved_at_0[0x8];
e281682b 7783 u8 local_port[0x8];
b4ff3a36 7784 u8 reserved_at_10[0x10];
e281682b
SM		 7785
7786 u8 max_mtu[0x10];
b4ff3a36 7787 u8 reserved_at_30[0x10];
e281682b
SM		 7788
7789 u8 admin_mtu[0x10];
b4ff3a36 7790 u8 reserved_at_50[0x10];
e281682b
SM		 7791
7792 u8 oper_mtu[0x10];
b4ff3a36 7793 u8 reserved_at_70[0x10];
e281682b
SM		 7794};
7795
7796struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7797 u8 reserved_at_0[0x8];
e281682b 7798 u8 module[0x8];
b4ff3a36 7799 u8 reserved_at_10[0x10];
e281682b 7800
b4ff3a36 7801 u8 reserved_at_20[0x18];
e281682b
SM		 7802 u8 attenuation_5g[0x8];
7803
b4ff3a36 7804 u8 reserved_at_40[0x18];
e281682b
SM		 7805 u8 attenuation_7g[0x8];
7806
b4ff3a36 7807 u8 reserved_at_60[0x18];
e281682b
SM		 7808 u8 attenuation_12g[0x8];
7809};
7810
7811struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7812 u8 reserved_at_0[0x8];
e281682b 7813 u8 module[0x8];
b4ff3a36 7814 u8 reserved_at_10[0xc];
e281682b
SM		 7815 u8 module_status[0x4];
7816
b4ff3a36 7817 u8 reserved_at_20[0x60];
e281682b
SM		 7818};
7819
7820struct mlx5_ifc_pmpc_reg_bits {
7821 u8 module_state_updated[32][0x8];
7822};
7823
7824struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7825 u8 reserved_at_0[0x4];
e281682b
SM		 7826 u8 mlpn_status[0x4];
7827 u8 local_port[0x8];
b4ff3a36 7828 u8 reserved_at_10[0x10];
e281682b
SM		 7829
7830 u8 e[0x1];
b4ff3a36 7831 u8 reserved_at_21[0x1f];
e281682b
SM		 7832};
7833
7834struct mlx5_ifc_pmlp_reg_bits {
7835 u8 rxtx[0x1];
b4ff3a36 7836 u8 reserved_at_1[0x7];
e281682b 7837 u8 local_port[0x8];
b4ff3a36 7838 u8 reserved_at_10[0x8];
e281682b
SM		 7839 u8 width[0x8];
7840
7841 u8 lane0_module_mapping[0x20];
7842
7843 u8 lane1_module_mapping[0x20];
7844
7845 u8 lane2_module_mapping[0x20];
7846
7847 u8 lane3_module_mapping[0x20];
7848
b4ff3a36 7849 u8 reserved_at_a0[0x160];
e281682b
SM		 7850};
7851
7852struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7853 u8 reserved_at_0[0x8];
e281682b 7854 u8 module[0x8];
b4ff3a36 7855 u8 reserved_at_10[0x4];
e281682b 7856 u8 admin_status[0x4];
b4ff3a36 7857 u8 reserved_at_18[0x4];
e281682b
SM		 7858 u8 oper_status[0x4];
7859
7860 u8 ase[0x1];
7861 u8 ee[0x1];
b4ff3a36 7862 u8 reserved_at_22[0x1c];
e281682b
SM		 7863 u8 e[0x2];
7864
b4ff3a36 7865 u8 reserved_at_40[0x40];
e281682b
SM		 7866};
7867
7868struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7869 u8 reserved_at_0[0x4];
e281682b 7870 u8 profile_id[0xc];
b4ff3a36 7871 u8 reserved_at_10[0x4];
e281682b 7872 u8 proto_mask[0x4];
b4ff3a36 7873 u8 reserved_at_18[0x8];
e281682b 7874
b4ff3a36 7875 u8 reserved_at_20[0x10];
e281682b
SM		 7876 u8 lane_speed[0x10];
7877
b4ff3a36 7878 u8 reserved_at_40[0x17];
e281682b
SM		 7879 u8 lpbf[0x1];
7880 u8 fec_mode_policy[0x8];
7881
7882 u8 retransmission_capability[0x8];
7883 u8 fec_mode_capability[0x18];
7884
7885 u8 retransmission_support_admin[0x8];
7886 u8 fec_mode_support_admin[0x18];
7887
7888 u8 retransmission_request_admin[0x8];
7889 u8 fec_mode_request_admin[0x18];
7890
b4ff3a36 7891 u8 reserved_at_c0[0x80];
e281682b
SM		 7892};
7893
7894struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7895 u8 reserved_at_0[0x8];
e281682b 7896 u8 local_port[0x8];
b4ff3a36 7897 u8 reserved_at_10[0x8];
e281682b
SM		 7898 u8 ib_port[0x8];
7899
b4ff3a36 7900 u8 reserved_at_20[0x60];
e281682b
SM		 7901};
7902
7903struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7904 u8 reserved_at_0[0x8];
e281682b 7905 u8 local_port[0x8];
b4ff3a36 7906 u8 reserved_at_10[0xd];
e281682b
SM		 7907 u8 lbf_mode[0x3];
7908
b4ff3a36 7909 u8 reserved_at_20[0x20];
e281682b
SM		 7910};
7911
7912struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7913 u8 reserved_at_0[0x8];
e281682b 7914 u8 local_port[0x8];
b4ff3a36 7915 u8 reserved_at_10[0x10];
e281682b
SM		 7916
7917 u8 dic[0x1];
b4ff3a36 7918 u8 reserved_at_21[0x19];
e281682b 7919 u8 ipg[0x4];
b4ff3a36 7920 u8 reserved_at_3e[0x2];
e281682b
SM		 7921};
7922
7923struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7924 u8 reserved_at_0[0x8];
e281682b 7925 u8 local_port[0x8];
b4ff3a36 7926 u8 reserved_at_10[0x10];
e281682b 7927
b4ff3a36 7928 u8 reserved_at_20[0xe0];
e281682b
SM		 7929
7930 u8 port_filter[8][0x20];
7931
7932 u8 port_filter_update_en[8][0x20];
7933};
7934
7935struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7936 u8 reserved_at_0[0x8];
e281682b 7937 u8 local_port[0x8];
2afa609f
IK		 7938 u8 reserved_at_10[0xb];
7939 u8 ppan_mask_n[0x1];
7940 u8 minor_stall_mask[0x1];
7941 u8 critical_stall_mask[0x1];
7942 u8 reserved_at_1e[0x2];
e281682b
SM		 7943
7944 u8 ppan[0x4];
b4ff3a36 7945 u8 reserved_at_24[0x4];
e281682b 7946 u8 prio_mask_tx[0x8];
b4ff3a36 7947 u8 reserved_at_30[0x8];
e281682b
SM		 7948 u8 prio_mask_rx[0x8];
7949
7950 u8 pptx[0x1];
7951 u8 aptx[0x1];
2afa609f
IK		 7952 u8 pptx_mask_n[0x1];
7953 u8 reserved_at_43[0x5];
e281682b 7954 u8 pfctx[0x8];
b4ff3a36 7955 u8 reserved_at_50[0x10];
e281682b
SM		 7956
7957 u8 pprx[0x1];
7958 u8 aprx[0x1];
2afa609f
IK		 7959 u8 pprx_mask_n[0x1];
7960 u8 reserved_at_63[0x5];
e281682b 7961 u8 pfcrx[0x8];
b4ff3a36 7962 u8 reserved_at_70[0x10];
e281682b 7963
2afa609f
IK		 7964 u8 device_stall_minor_watermark[0x10];
7965 u8 device_stall_critical_watermark[0x10];
7966
7967 u8 reserved_at_a0[0x60];
e281682b
SM		 7968};
7969
7970struct mlx5_ifc_pelc_reg_bits {
7971 u8 op[0x4];
b4ff3a36 7972 u8 reserved_at_4[0x4];
e281682b 7973 u8 local_port[0x8];
b4ff3a36 7974 u8 reserved_at_10[0x10];
e281682b
SM		 7975
7976 u8 op_admin[0x8];
7977 u8 op_capability[0x8];
7978 u8 op_request[0x8];
7979 u8 op_active[0x8];
7980
7981 u8 admin[0x40];
7982
7983 u8 capability[0x40];
7984
7985 u8 request[0x40];
7986
7987 u8 active[0x40];
7988
b4ff3a36 7989 u8 reserved_at_140[0x80];
e281682b
SM		 7990};
7991
7992struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7993 u8 reserved_at_0[0x8];
e281682b 7994 u8 local_port[0x8];
b4ff3a36 7995 u8 reserved_at_10[0x10];
e281682b 7996
b4ff3a36 7997 u8 reserved_at_20[0xc];
e281682b 7998 u8 error_count[0x4];
b4ff3a36 7999 u8 reserved_at_30[0x10];
e281682b 8000
b4ff3a36 8001 u8 reserved_at_40[0xc];
e281682b 8002 u8 lane[0x4];
b4ff3a36 8003 u8 reserved_at_50[0x8];
e281682b
SM		 8004 u8 error_type[0x8];
8005};
8006
cfdcbcea 8007struct mlx5_ifc_pcam_enhanced_features_bits {
2fcb12df 8008 u8 reserved_at_0[0x76];
cfdcbcea 8009
2fcb12df
IK		 8010 u8 pfcc_mask[0x1];
8011 u8 reserved_at_77[0x4];
2dba0797 8012 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8013 u8 ptys_connector_type[0x1];
8014 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8015 u8 ppcnt_discard_group[0x1];
8016 u8 ppcnt_statistical_group[0x1];
8017};
8018
8019struct mlx5_ifc_pcam_reg_bits {
8020 u8 reserved_at_0[0x8];
8021 u8 feature_group[0x8];
8022 u8 reserved_at_10[0x8];
8023 u8 access_reg_group[0x8];
8024
8025 u8 reserved_at_20[0x20];
8026
8027 union {
8028 u8 reserved_at_0[0x80];
8029 } port_access_reg_cap_mask;
8030
8031 u8 reserved_at_c0[0x80];
8032
8033 union {
8034 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8035 u8 reserved_at_0[0x80];
8036 } feature_cap_mask;
8037
8038 u8 reserved_at_1c0[0xc0];
8039};
8040
8041struct mlx5_ifc_mcam_enhanced_features_bits {
5405fa26
GP		 8042 u8 reserved_at_0[0x7b];
8043 u8 pcie_outbound_stalled[0x1];
efae7f78 8044 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8045 u8 mtpps_enh_out_per_adj[0x1];
8046 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8047 u8 pcie_performance_group[0x1];
8048};
8049
0ab87743
OG		 8050struct mlx5_ifc_mcam_access_reg_bits {
8051 u8 reserved_at_0[0x1c];
8052 u8 mcda[0x1];
8053 u8 mcc[0x1];
8054 u8 mcqi[0x1];
8055 u8 reserved_at_1f[0x1];
8056
8057 u8 regs_95_to_64[0x20];
8058 u8 regs_63_to_32[0x20];
8059 u8 regs_31_to_0[0x20];
8060};
8061
cfdcbcea
GP		 8062struct mlx5_ifc_mcam_reg_bits {
8063 u8 reserved_at_0[0x8];
8064 u8 feature_group[0x8];
8065 u8 reserved_at_10[0x8];
8066 u8 access_reg_group[0x8];
8067
8068 u8 reserved_at_20[0x20];
8069
8070 union {
0ab87743 8071 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8072 u8 reserved_at_0[0x80];
8073 } mng_access_reg_cap_mask;
8074
8075 u8 reserved_at_c0[0x80];
8076
8077 union {
8078 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8079 u8 reserved_at_0[0x80];
8080 } mng_feature_cap_mask;
8081
8082 u8 reserved_at_1c0[0x80];
8083};
8084
c02762eb
HN		 8085struct mlx5_ifc_qcam_access_reg_cap_mask {
8086 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8087 u8 qpdpm[0x1];
8088 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8089 u8 qdpm[0x1];
8090 u8 qpts[0x1];
8091 u8 qcap[0x1];
8092 u8 qcam_access_reg_cap_mask_0[0x1];
8093};
8094
8095struct mlx5_ifc_qcam_qos_feature_cap_mask {
8096 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8097 u8 qpts_trust_both[0x1];
8098};
8099
8100struct mlx5_ifc_qcam_reg_bits {
8101 u8 reserved_at_0[0x8];
8102 u8 feature_group[0x8];
8103 u8 reserved_at_10[0x8];
8104 u8 access_reg_group[0x8];
8105 u8 reserved_at_20[0x20];
8106
8107 union {
8108 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8109 u8 reserved_at_0[0x80];
8110 } qos_access_reg_cap_mask;
8111
8112 u8 reserved_at_c0[0x80];
8113
8114 union {
8115 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8116 u8 reserved_at_0[0x80];
8117 } qos_feature_cap_mask;
8118
8119 u8 reserved_at_1c0[0x80];
8120};
8121
e281682b 8122struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8123 u8 reserved_at_0[0x8];
e281682b 8124 u8 local_port[0x8];
b4ff3a36 8125 u8 reserved_at_10[0x10];
e281682b
SM		 8126
8127 u8 port_capability_mask[4][0x20];
8128};
8129
8130struct mlx5_ifc_paos_reg_bits {
8131 u8 swid[0x8];
8132 u8 local_port[0x8];
b4ff3a36 8133 u8 reserved_at_10[0x4];
e281682b 8134 u8 admin_status[0x4];
b4ff3a36 8135 u8 reserved_at_18[0x4];
e281682b
SM		 8136 u8 oper_status[0x4];
8137
8138 u8 ase[0x1];
8139 u8 ee[0x1];
b4ff3a36 8140 u8 reserved_at_22[0x1c];
e281682b
SM		 8141 u8 e[0x2];
8142
b4ff3a36 8143 u8 reserved_at_40[0x40];
e281682b
SM		 8144};
8145
8146struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8147 u8 reserved_at_0[0x8];
e281682b 8148 u8 opamp_group[0x8];
b4ff3a36 8149 u8 reserved_at_10[0xc];
e281682b
SM		 8150 u8 opamp_group_type[0x4];
8151
8152 u8 start_index[0x10];
b4ff3a36 8153 u8 reserved_at_30[0x4];
e281682b
SM		 8154 u8 num_of_indices[0xc];
8155
8156 u8 index_data[18][0x10];
8157};
8158
7d5e1423
SM		 8159struct mlx5_ifc_pcmr_reg_bits {
8160 u8 reserved_at_0[0x8];
8161 u8 local_port[0x8];
8162 u8 reserved_at_10[0x2e];
8163 u8 fcs_cap[0x1];
8164 u8 reserved_at_3f[0x1f];
8165 u8 fcs_chk[0x1];
8166 u8 reserved_at_5f[0x1];
8167};
8168
e281682b 8169struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8170 u8 reserved_at_0[0x6];
e281682b 8171 u8 rx_lane[0x2];
b4ff3a36 8172 u8 reserved_at_8[0x6];
e281682b 8173 u8 tx_lane[0x2];
b4ff3a36 8174 u8 reserved_at_10[0x8];
e281682b
SM		 8175 u8 module[0x8];
8176};
8177
8178struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8179 u8 reserved_at_0[0x6];
e281682b
SM		 8180 u8 lossy[0x1];
8181 u8 epsb[0x1];
b4ff3a36 8182 u8 reserved_at_8[0xc];
e281682b
SM		 8183 u8 size[0xc];
8184
8185 u8 xoff_threshold[0x10];
8186 u8 xon_threshold[0x10];
8187};
8188
8189struct mlx5_ifc_set_node_in_bits {
8190 u8 node_description[64][0x8];
8191};
8192
8193struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8194 u8 reserved_at_0[0x18];
e281682b
SM		 8195 u8 power_settings_level[0x8];
8196
b4ff3a36 8197 u8 reserved_at_20[0x60];
e281682b
SM		 8198};
8199
8200struct mlx5_ifc_register_host_endianness_bits {
8201 u8 he[0x1];
b4ff3a36 8202 u8 reserved_at_1[0x1f];
e281682b 8203
b4ff3a36 8204 u8 reserved_at_20[0x60];
e281682b
SM		 8205};
8206
8207struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8208 u8 reserved_at_0[0x20];
e281682b
SM		 8209
8210 u8 mkey[0x20];
8211
8212 u8 addressh_63_32[0x20];
8213
8214 u8 addressl_31_0[0x20];
8215};
8216
8217struct mlx5_ifc_ud_adrs_vector_bits {
8218 u8 dc_key[0x40];
8219
8220 u8 ext[0x1];
b4ff3a36 8221 u8 reserved_at_41[0x7];
e281682b
SM		 8222 u8 destination_qp_dct[0x18];
8223
8224 u8 static_rate[0x4];
8225 u8 sl_eth_prio[0x4];
8226 u8 fl[0x1];
8227 u8 mlid[0x7];
8228 u8 rlid_udp_sport[0x10];
8229
b4ff3a36 8230 u8 reserved_at_80[0x20];
e281682b
SM		 8231
8232 u8 rmac_47_16[0x20];
8233
8234 u8 rmac_15_0[0x10];
8235 u8 tclass[0x8];
8236 u8 hop_limit[0x8];
8237
b4ff3a36 8238 u8 reserved_at_e0[0x1];
e281682b 8239 u8 grh[0x1];
b4ff3a36 8240 u8 reserved_at_e2[0x2];
e281682b
SM		 8241 u8 src_addr_index[0x8];
8242 u8 flow_label[0x14];
8243
8244 u8 rgid_rip[16][0x8];
8245};
8246
8247struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8248 u8 reserved_at_0[0x10];
e281682b
SM		 8249 u8 function_id[0x10];
8250
8251 u8 num_pages[0x20];
8252
b4ff3a36 8253 u8 reserved_at_40[0xa0];
e281682b
SM		 8254};
8255
8256struct mlx5_ifc_eqe_bits {
b4ff3a36 8257 u8 reserved_at_0[0x8];
e281682b 8258 u8 event_type[0x8];
b4ff3a36 8259 u8 reserved_at_10[0x8];
e281682b
SM		 8260 u8 event_sub_type[0x8];
8261
b4ff3a36 8262 u8 reserved_at_20[0xe0];
e281682b
SM		 8263
8264 union mlx5_ifc_event_auto_bits event_data;
8265
b4ff3a36 8266 u8 reserved_at_1e0[0x10];
e281682b 8267 u8 signature[0x8];
b4ff3a36 8268 u8 reserved_at_1f8[0x7];
e281682b
SM		 8269 u8 owner[0x1];
8270};
8271
8272enum {
8273 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8274};
8275
8276struct mlx5_ifc_cmd_queue_entry_bits {
8277 u8 type[0x8];
b4ff3a36 8278 u8 reserved_at_8[0x18];
e281682b
SM		 8279
8280 u8 input_length[0x20];
8281
8282 u8 input_mailbox_pointer_63_32[0x20];
8283
8284 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8285 u8 reserved_at_77[0x9];
e281682b
SM		 8286
8287 u8 command_input_inline_data[16][0x8];
8288
8289 u8 command_output_inline_data[16][0x8];
8290
8291 u8 output_mailbox_pointer_63_32[0x20];
8292
8293 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8294 u8 reserved_at_1b7[0x9];
e281682b
SM		 8295
8296 u8 output_length[0x20];
8297
8298 u8 token[0x8];
8299 u8 signature[0x8];
b4ff3a36 8300 u8 reserved_at_1f0[0x8];
e281682b
SM		 8301 u8 status[0x7];
8302 u8 ownership[0x1];
8303};
8304
8305struct mlx5_ifc_cmd_out_bits {
8306 u8 status[0x8];
b4ff3a36 8307 u8 reserved_at_8[0x18];
e281682b
SM		 8308
8309 u8 syndrome[0x20];
8310
8311 u8 command_output[0x20];
8312};
8313
8314struct mlx5_ifc_cmd_in_bits {
8315 u8 opcode[0x10];
b4ff3a36 8316 u8 reserved_at_10[0x10];
e281682b 8317
b4ff3a36 8318 u8 reserved_at_20[0x10];
e281682b
SM		 8319 u8 op_mod[0x10];
8320
8321 u8 command[0][0x20];
8322};
8323
8324struct mlx5_ifc_cmd_if_box_bits {
8325 u8 mailbox_data[512][0x8];
8326
b4ff3a36 8327 u8 reserved_at_1000[0x180];
e281682b
SM		 8328
8329 u8 next_pointer_63_32[0x20];
8330
8331 u8 next_pointer_31_10[0x16];
b4ff3a36 8332 u8 reserved_at_11b6[0xa];
e281682b
SM		 8333
8334 u8 block_number[0x20];
8335
b4ff3a36 8336 u8 reserved_at_11e0[0x8];
e281682b
SM		 8337 u8 token[0x8];
8338 u8 ctrl_signature[0x8];
8339 u8 signature[0x8];
8340};
8341
8342struct mlx5_ifc_mtt_bits {
8343 u8 ptag_63_32[0x20];
8344
8345 u8 ptag_31_8[0x18];
b4ff3a36 8346 u8 reserved_at_38[0x6];
e281682b
SM		 8347 u8 wr_en[0x1];
8348 u8 rd_en[0x1];
8349};
8350
928cfe87
TT		 8351struct mlx5_ifc_query_wol_rol_out_bits {
8352 u8 status[0x8];
8353 u8 reserved_at_8[0x18];
8354
8355 u8 syndrome[0x20];
8356
8357 u8 reserved_at_40[0x10];
8358 u8 rol_mode[0x8];
8359 u8 wol_mode[0x8];
8360
8361 u8 reserved_at_60[0x20];
8362};
8363
8364struct mlx5_ifc_query_wol_rol_in_bits {
8365 u8 opcode[0x10];
8366 u8 reserved_at_10[0x10];
8367
8368 u8 reserved_at_20[0x10];
8369 u8 op_mod[0x10];
8370
8371 u8 reserved_at_40[0x40];
8372};
8373
8374struct mlx5_ifc_set_wol_rol_out_bits {
8375 u8 status[0x8];
8376 u8 reserved_at_8[0x18];
8377
8378 u8 syndrome[0x20];
8379
8380 u8 reserved_at_40[0x40];
8381};
8382
8383struct mlx5_ifc_set_wol_rol_in_bits {
8384 u8 opcode[0x10];
8385 u8 reserved_at_10[0x10];
8386
8387 u8 reserved_at_20[0x10];
8388 u8 op_mod[0x10];
8389
8390 u8 rol_mode_valid[0x1];
8391 u8 wol_mode_valid[0x1];
8392 u8 reserved_at_42[0xe];
8393 u8 rol_mode[0x8];
8394 u8 wol_mode[0x8];
8395
8396 u8 reserved_at_60[0x20];
8397};
8398
e281682b
SM		 8399enum {
8400 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8401 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8402 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8403};
8404
8405enum {
8406 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8407 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8408 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8409};
8410
8411enum {
8412 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8413 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8414 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8415 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8416 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8417 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8423};
8424
8425struct mlx5_ifc_initial_seg_bits {
8426 u8 fw_rev_minor[0x10];
8427 u8 fw_rev_major[0x10];
8428
8429 u8 cmd_interface_rev[0x10];
8430 u8 fw_rev_subminor[0x10];
8431
b4ff3a36 8432 u8 reserved_at_40[0x40];
e281682b
SM		 8433
8434 u8 cmdq_phy_addr_63_32[0x20];
8435
8436 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8437 u8 reserved_at_b4[0x2];
e281682b
SM		 8438 u8 nic_interface[0x2];
8439 u8 log_cmdq_size[0x4];
8440 u8 log_cmdq_stride[0x4];
8441
8442 u8 command_doorbell_vector[0x20];
8443
b4ff3a36 8444 u8 reserved_at_e0[0xf00];
e281682b
SM		 8445
8446 u8 initializing[0x1];
b4ff3a36 8447 u8 reserved_at_fe1[0x4];
e281682b 8448 u8 nic_interface_supported[0x3];
b4ff3a36 8449 u8 reserved_at_fe8[0x18];
e281682b
SM		 8450
8451 struct mlx5_ifc_health_buffer_bits health_buffer;
8452
8453 u8 no_dram_nic_offset[0x20];
8454
b4ff3a36 8455 u8 reserved_at_1220[0x6e40];
e281682b 8456
b4ff3a36 8457 u8 reserved_at_8060[0x1f];
e281682b
SM		 8458 u8 clear_int[0x1];
8459
8460 u8 health_syndrome[0x8];
8461 u8 health_counter[0x18];
8462
b4ff3a36 8463 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8464};
8465
f9a1ef72
EE		 8466struct mlx5_ifc_mtpps_reg_bits {
8467 u8 reserved_at_0[0xc];
8468 u8 cap_number_of_pps_pins[0x4];
8469 u8 reserved_at_10[0x4];
8470 u8 cap_max_num_of_pps_in_pins[0x4];
8471 u8 reserved_at_18[0x4];
8472 u8 cap_max_num_of_pps_out_pins[0x4];
8473
8474 u8 reserved_at_20[0x24];
8475 u8 cap_pin_3_mode[0x4];
8476 u8 reserved_at_48[0x4];
8477 u8 cap_pin_2_mode[0x4];
8478 u8 reserved_at_50[0x4];
8479 u8 cap_pin_1_mode[0x4];
8480 u8 reserved_at_58[0x4];
8481 u8 cap_pin_0_mode[0x4];
8482
8483 u8 reserved_at_60[0x4];
8484 u8 cap_pin_7_mode[0x4];
8485 u8 reserved_at_68[0x4];
8486 u8 cap_pin_6_mode[0x4];
8487 u8 reserved_at_70[0x4];
8488 u8 cap_pin_5_mode[0x4];
8489 u8 reserved_at_78[0x4];
8490 u8 cap_pin_4_mode[0x4];
8491
fa367688
EE		 8492 u8 field_select[0x20];
8493 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8494
8495 u8 enable[0x1];
8496 u8 reserved_at_101[0xb];
8497 u8 pattern[0x4];
8498 u8 reserved_at_110[0x4];
8499 u8 pin_mode[0x4];
8500 u8 pin[0x8];
8501
8502 u8 reserved_at_120[0x20];
8503
8504 u8 time_stamp[0x40];
8505
8506 u8 out_pulse_duration[0x10];
8507 u8 out_periodic_adjustment[0x10];
fa367688 8508 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8509
fa367688 8510 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8511};
8512
8513struct mlx5_ifc_mtppse_reg_bits {
8514 u8 reserved_at_0[0x18];
8515 u8 pin[0x8];
8516 u8 event_arm[0x1];
8517 u8 reserved_at_21[0x1b];
8518 u8 event_generation_mode[0x4];
8519 u8 reserved_at_40[0x40];
8520};
8521
47176289
OG		 8522struct mlx5_ifc_mcqi_cap_bits {
8523 u8 supported_info_bitmask[0x20];
8524
8525 u8 component_size[0x20];
8526
8527 u8 max_component_size[0x20];
8528
8529 u8 log_mcda_word_size[0x4];
8530 u8 reserved_at_64[0xc];
8531 u8 mcda_max_write_size[0x10];
8532
8533 u8 rd_en[0x1];
8534 u8 reserved_at_81[0x1];
8535 u8 match_chip_id[0x1];
8536 u8 match_psid[0x1];
8537 u8 check_user_timestamp[0x1];
8538 u8 match_base_guid_mac[0x1];
8539 u8 reserved_at_86[0x1a];
8540};
8541
8542struct mlx5_ifc_mcqi_reg_bits {
8543 u8 read_pending_component[0x1];
8544 u8 reserved_at_1[0xf];
8545 u8 component_index[0x10];
8546
8547 u8 reserved_at_20[0x20];
8548
8549 u8 reserved_at_40[0x1b];
8550 u8 info_type[0x5];
8551
8552 u8 info_size[0x20];
8553
8554 u8 offset[0x20];
8555
8556 u8 reserved_at_a0[0x10];
8557 u8 data_size[0x10];
8558
8559 u8 data[0][0x20];
8560};
8561
8562struct mlx5_ifc_mcc_reg_bits {
8563 u8 reserved_at_0[0x4];
8564 u8 time_elapsed_since_last_cmd[0xc];
8565 u8 reserved_at_10[0x8];
8566 u8 instruction[0x8];
8567
8568 u8 reserved_at_20[0x10];
8569 u8 component_index[0x10];
8570
8571 u8 reserved_at_40[0x8];
8572 u8 update_handle[0x18];
8573
8574 u8 handle_owner_type[0x4];
8575 u8 handle_owner_host_id[0x4];
8576 u8 reserved_at_68[0x1];
8577 u8 control_progress[0x7];
8578 u8 error_code[0x8];
8579 u8 reserved_at_78[0x4];
8580 u8 control_state[0x4];
8581
8582 u8 component_size[0x20];
8583
8584 u8 reserved_at_a0[0x60];
8585};
8586
8587struct mlx5_ifc_mcda_reg_bits {
8588 u8 reserved_at_0[0x8];
8589 u8 update_handle[0x18];
8590
8591 u8 offset[0x20];
8592
8593 u8 reserved_at_40[0x10];
8594 u8 size[0x10];
8595
8596 u8 reserved_at_60[0x20];
8597
8598 u8 data[0][0x20];
8599};
8600
e281682b
SM		 8601union mlx5_ifc_ports_control_registers_document_bits {
8602 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8603 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8604 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8605 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8606 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8607 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8608 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8609 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8610 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8611 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8612 struct mlx5_ifc_paos_reg_bits paos_reg;
8613 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8614 struct mlx5_ifc_peir_reg_bits peir_reg;
8615 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8616 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8617 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8618 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8619 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8620 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8621 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8622 struct mlx5_ifc_plib_reg_bits plib_reg;
8623 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8624 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8625 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8626 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8627 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8628 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8629 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8630 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8631 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8632 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8633 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8634 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8635 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8636 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8637 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8638 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8639 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8640 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8641 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8642 struct mlx5_ifc_pude_reg_bits pude_reg;
8643 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8644 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8645 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8646 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8647 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8648 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8649 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8650 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8651 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8652 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8653 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8654 u8 reserved_at_0[0x60e0];
e281682b
SM		 8655};
8656
8657union mlx5_ifc_debug_enhancements_document_bits {
8658 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8659 u8 reserved_at_0[0x200];
e281682b
SM		 8660};
8661
8662union mlx5_ifc_uplink_pci_interface_document_bits {
8663 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8664 u8 reserved_at_0[0x20060];
b775516b
EC		 8665};
8666
2cc43b49
MG		 8667struct mlx5_ifc_set_flow_table_root_out_bits {
8668 u8 status[0x8];
b4ff3a36 8669 u8 reserved_at_8[0x18];
2cc43b49
MG		 8670
8671 u8 syndrome[0x20];
8672
b4ff3a36 8673 u8 reserved_at_40[0x40];
2cc43b49
MG		 8674};
8675
8676struct mlx5_ifc_set_flow_table_root_in_bits {
8677 u8 opcode[0x10];
b4ff3a36 8678 u8 reserved_at_10[0x10];
2cc43b49 8679
b4ff3a36 8680 u8 reserved_at_20[0x10];
2cc43b49
MG		 8681 u8 op_mod[0x10];
8682
7d5e1423
SM		 8683 u8 other_vport[0x1];
8684 u8 reserved_at_41[0xf];
8685 u8 vport_number[0x10];
8686
8687 u8 reserved_at_60[0x20];
2cc43b49
MG		 8688
8689 u8 table_type[0x8];
b4ff3a36 8690 u8 reserved_at_88[0x18];
2cc43b49 8691
b4ff3a36 8692 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8693 u8 table_id[0x18];
8694
500a3d0d
ES		 8695 u8 reserved_at_c0[0x8];
8696 u8 underlay_qpn[0x18];
8697 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8698};
8699
34a40e68 8700enum {
84df61eb
AH		 8701 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8702 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8703};
8704
8705struct mlx5_ifc_modify_flow_table_out_bits {
8706 u8 status[0x8];
b4ff3a36 8707 u8 reserved_at_8[0x18];
34a40e68
MG		 8708
8709 u8 syndrome[0x20];
8710
b4ff3a36 8711 u8 reserved_at_40[0x40];
34a40e68
MG		 8712};
8713
8714struct mlx5_ifc_modify_flow_table_in_bits {
8715 u8 opcode[0x10];
b4ff3a36 8716 u8 reserved_at_10[0x10];
34a40e68 8717
b4ff3a36 8718 u8 reserved_at_20[0x10];
34a40e68
MG		 8719 u8 op_mod[0x10];
8720
7d5e1423
SM		 8721 u8 other_vport[0x1];
8722 u8 reserved_at_41[0xf];
8723 u8 vport_number[0x10];
34a40e68 8724
b4ff3a36 8725 u8 reserved_at_60[0x10];
34a40e68
MG		 8726 u8 modify_field_select[0x10];
8727
8728 u8 table_type[0x8];
b4ff3a36 8729 u8 reserved_at_88[0x18];
34a40e68 8730
b4ff3a36 8731 u8 reserved_at_a0[0x8];
34a40e68
MG		 8732 u8 table_id[0x18];
8733
0c90e9c6 8734 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8735};
8736
4f3961ee
SM		 8737struct mlx5_ifc_ets_tcn_config_reg_bits {
8738 u8 g[0x1];
8739 u8 b[0x1];
8740 u8 r[0x1];
8741 u8 reserved_at_3[0x9];
8742 u8 group[0x4];
8743 u8 reserved_at_10[0x9];
8744 u8 bw_allocation[0x7];
8745
8746 u8 reserved_at_20[0xc];
8747 u8 max_bw_units[0x4];
8748 u8 reserved_at_30[0x8];
8749 u8 max_bw_value[0x8];
8750};
8751
8752struct mlx5_ifc_ets_global_config_reg_bits {
8753 u8 reserved_at_0[0x2];
8754 u8 r[0x1];
8755 u8 reserved_at_3[0x1d];
8756
8757 u8 reserved_at_20[0xc];
8758 u8 max_bw_units[0x4];
8759 u8 reserved_at_30[0x8];
8760 u8 max_bw_value[0x8];
8761};
8762
8763struct mlx5_ifc_qetc_reg_bits {
8764 u8 reserved_at_0[0x8];
8765 u8 port_number[0x8];
8766 u8 reserved_at_10[0x30];
8767
8768 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8769 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8770};
8771
415a64aa
HN		 8772struct mlx5_ifc_qpdpm_dscp_reg_bits {
8773 u8 e[0x1];
8774 u8 reserved_at_01[0x0b];
8775 u8 prio[0x04];
8776};
8777
8778struct mlx5_ifc_qpdpm_reg_bits {
8779 u8 reserved_at_0[0x8];
8780 u8 local_port[0x8];
8781 u8 reserved_at_10[0x10];
8782 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8783};
8784
8785struct mlx5_ifc_qpts_reg_bits {
8786 u8 reserved_at_0[0x8];
8787 u8 local_port[0x8];
8788 u8 reserved_at_10[0x2d];
8789 u8 trust_state[0x3];
8790};
8791
4f3961ee
SM		 8792struct mlx5_ifc_qtct_reg_bits {
8793 u8 reserved_at_0[0x8];
8794 u8 port_number[0x8];
8795 u8 reserved_at_10[0xd];
8796 u8 prio[0x3];
8797
8798 u8 reserved_at_20[0x1d];
8799 u8 tclass[0x3];
8800};
8801
7d5e1423
SM		 8802struct mlx5_ifc_mcia_reg_bits {
8803 u8 l[0x1];
8804 u8 reserved_at_1[0x7];
8805 u8 module[0x8];
8806 u8 reserved_at_10[0x8];
8807 u8 status[0x8];
8808
8809 u8 i2c_device_address[0x8];
8810 u8 page_number[0x8];
8811 u8 device_address[0x10];
8812
8813 u8 reserved_at_40[0x10];
8814 u8 size[0x10];
8815
8816 u8 reserved_at_60[0x20];
8817
8818 u8 dword_0[0x20];
8819 u8 dword_1[0x20];
8820 u8 dword_2[0x20];
8821 u8 dword_3[0x20];
8822 u8 dword_4[0x20];
8823 u8 dword_5[0x20];
8824 u8 dword_6[0x20];
8825 u8 dword_7[0x20];
8826 u8 dword_8[0x20];
8827 u8 dword_9[0x20];
8828 u8 dword_10[0x20];
8829 u8 dword_11[0x20];
8830};
8831
7486216b
SM		 8832struct mlx5_ifc_dcbx_param_bits {
8833 u8 dcbx_cee_cap[0x1];
8834 u8 dcbx_ieee_cap[0x1];
8835 u8 dcbx_standby_cap[0x1];
8836 u8 reserved_at_0[0x5];
8837 u8 port_number[0x8];
8838 u8 reserved_at_10[0xa];
8839 u8 max_application_table_size[6];
8840 u8 reserved_at_20[0x15];
8841 u8 version_oper[0x3];
8842 u8 reserved_at_38[5];
8843 u8 version_admin[0x3];
8844 u8 willing_admin[0x1];
8845 u8 reserved_at_41[0x3];
8846 u8 pfc_cap_oper[0x4];
8847 u8 reserved_at_48[0x4];
8848 u8 pfc_cap_admin[0x4];
8849 u8 reserved_at_50[0x4];
8850 u8 num_of_tc_oper[0x4];
8851 u8 reserved_at_58[0x4];
8852 u8 num_of_tc_admin[0x4];
8853 u8 remote_willing[0x1];
8854 u8 reserved_at_61[3];
8855 u8 remote_pfc_cap[4];
8856 u8 reserved_at_68[0x14];
8857 u8 remote_num_of_tc[0x4];
8858 u8 reserved_at_80[0x18];
8859 u8 error[0x8];
8860 u8 reserved_at_a0[0x160];
8861};
84df61eb
AH		 8862
8863struct mlx5_ifc_lagc_bits {
8864 u8 reserved_at_0[0x1d];
8865 u8 lag_state[0x3];
8866
8867 u8 reserved_at_20[0x14];
8868 u8 tx_remap_affinity_2[0x4];
8869 u8 reserved_at_38[0x4];
8870 u8 tx_remap_affinity_1[0x4];
8871};
8872
8873struct mlx5_ifc_create_lag_out_bits {
8874 u8 status[0x8];
8875 u8 reserved_at_8[0x18];
8876
8877 u8 syndrome[0x20];
8878
8879 u8 reserved_at_40[0x40];
8880};
8881
8882struct mlx5_ifc_create_lag_in_bits {
8883 u8 opcode[0x10];
8884 u8 reserved_at_10[0x10];
8885
8886 u8 reserved_at_20[0x10];
8887 u8 op_mod[0x10];
8888
8889 struct mlx5_ifc_lagc_bits ctx;
8890};
8891
8892struct mlx5_ifc_modify_lag_out_bits {
8893 u8 status[0x8];
8894 u8 reserved_at_8[0x18];
8895
8896 u8 syndrome[0x20];
8897
8898 u8 reserved_at_40[0x40];
8899};
8900
8901struct mlx5_ifc_modify_lag_in_bits {
8902 u8 opcode[0x10];
8903 u8 reserved_at_10[0x10];
8904
8905 u8 reserved_at_20[0x10];
8906 u8 op_mod[0x10];
8907
8908 u8 reserved_at_40[0x20];
8909 u8 field_select[0x20];
8910
8911 struct mlx5_ifc_lagc_bits ctx;
8912};
8913
8914struct mlx5_ifc_query_lag_out_bits {
8915 u8 status[0x8];
8916 u8 reserved_at_8[0x18];
8917
8918 u8 syndrome[0x20];
8919
8920 u8 reserved_at_40[0x40];
8921
8922 struct mlx5_ifc_lagc_bits ctx;
8923};
8924
8925struct mlx5_ifc_query_lag_in_bits {
8926 u8 opcode[0x10];
8927 u8 reserved_at_10[0x10];
8928
8929 u8 reserved_at_20[0x10];
8930 u8 op_mod[0x10];
8931
8932 u8 reserved_at_40[0x40];
8933};
8934
8935struct mlx5_ifc_destroy_lag_out_bits {
8936 u8 status[0x8];
8937 u8 reserved_at_8[0x18];
8938
8939 u8 syndrome[0x20];
8940
8941 u8 reserved_at_40[0x40];
8942};
8943
8944struct mlx5_ifc_destroy_lag_in_bits {
8945 u8 opcode[0x10];
8946 u8 reserved_at_10[0x10];
8947
8948 u8 reserved_at_20[0x10];
8949 u8 op_mod[0x10];
8950
8951 u8 reserved_at_40[0x40];
8952};
8953
8954struct mlx5_ifc_create_vport_lag_out_bits {
8955 u8 status[0x8];
8956 u8 reserved_at_8[0x18];
8957
8958 u8 syndrome[0x20];
8959
8960 u8 reserved_at_40[0x40];
8961};
8962
8963struct mlx5_ifc_create_vport_lag_in_bits {
8964 u8 opcode[0x10];
8965 u8 reserved_at_10[0x10];
8966
8967 u8 reserved_at_20[0x10];
8968 u8 op_mod[0x10];
8969
8970 u8 reserved_at_40[0x40];
8971};
8972
8973struct mlx5_ifc_destroy_vport_lag_out_bits {
8974 u8 status[0x8];
8975 u8 reserved_at_8[0x18];
8976
8977 u8 syndrome[0x20];
8978
8979 u8 reserved_at_40[0x40];
8980};
8981
8982struct mlx5_ifc_destroy_vport_lag_in_bits {
8983 u8 opcode[0x10];
8984 u8 reserved_at_10[0x10];
8985
8986 u8 reserved_at_20[0x10];
8987 u8 op_mod[0x10];
8988
8989 u8 reserved_at_40[0x40];
8990};
8991
24da0016
AL		 8992struct mlx5_ifc_alloc_memic_in_bits {
8993 u8 opcode[0x10];
8994 u8 reserved_at_10[0x10];
8995
8996 u8 reserved_at_20[0x10];
8997 u8 op_mod[0x10];
8998
8999 u8 reserved_at_30[0x20];
9000
9001 u8 reserved_at_40[0x18];
9002 u8 log_memic_addr_alignment[0x8];
9003
9004 u8 range_start_addr[0x40];
9005
9006 u8 range_size[0x20];
9007
9008 u8 memic_size[0x20];
9009};
9010
9011struct mlx5_ifc_alloc_memic_out_bits {
9012 u8 status[0x8];
9013 u8 reserved_at_8[0x18];
9014
9015 u8 syndrome[0x20];
9016
9017 u8 memic_start_addr[0x40];
9018};
9019
9020struct mlx5_ifc_dealloc_memic_in_bits {
9021 u8 opcode[0x10];
9022 u8 reserved_at_10[0x10];
9023
9024 u8 reserved_at_20[0x10];
9025 u8 op_mod[0x10];
9026
9027 u8 reserved_at_40[0x40];
9028
9029 u8 memic_start_addr[0x40];
9030
9031 u8 memic_size[0x20];
9032
9033 u8 reserved_at_e0[0x20];
9034};
9035
9036struct mlx5_ifc_dealloc_memic_out_bits {
9037 u8 status[0x8];
9038 u8 reserved_at_8[0x18];
9039
9040 u8 syndrome[0x20];
9041
9042 u8 reserved_at_40[0x40];
9043};
9044
d29b796a 9045#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)