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net/mlx5e: Move port speed code from en_ethtool.c to en/port.c
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 95 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
96 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 97 MLX5_CMD_OP_CREATE_EQ = 0x301,
98 MLX5_CMD_OP_DESTROY_EQ = 0x302,
99 MLX5_CMD_OP_QUERY_EQ = 0x303,
100 MLX5_CMD_OP_GEN_EQE = 0x304,
101 MLX5_CMD_OP_CREATE_CQ = 0x400,
102 MLX5_CMD_OP_DESTROY_CQ = 0x401,
103 MLX5_CMD_OP_QUERY_CQ = 0x402,
104 MLX5_CMD_OP_MODIFY_CQ = 0x403,
105 MLX5_CMD_OP_CREATE_QP = 0x500,
106 MLX5_CMD_OP_DESTROY_QP = 0x501,
107 MLX5_CMD_OP_RST2INIT_QP = 0x502,
108 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
109 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
110 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
112 MLX5_CMD_OP_2ERR_QP = 0x507,
113 MLX5_CMD_OP_2RST_QP = 0x50a,
114 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
117 MLX5_CMD_OP_CREATE_PSV = 0x600,
118 MLX5_CMD_OP_DESTROY_PSV = 0x601,
119 MLX5_CMD_OP_CREATE_SRQ = 0x700,
120 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
121 MLX5_CMD_OP_QUERY_SRQ = 0x702,
122 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 127 MLX5_CMD_OP_CREATE_DCT = 0x710,
128 MLX5_CMD_OP_DESTROY_DCT = 0x711,
129 MLX5_CMD_OP_DRAIN_DCT = 0x712,
130 MLX5_CMD_OP_QUERY_DCT = 0x713,
131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 132 MLX5_CMD_OP_CREATE_XRQ = 0x717,
133 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
134 MLX5_CMD_OP_QUERY_XRQ = 0x719,
135 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 136 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
137 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 143 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 148 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 149 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
150 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
151 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
152 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
37e92a9d 153 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 154 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 155 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
156 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
157 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
158 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
159 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
160 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 161 MLX5_CMD_OP_ALLOC_PD = 0x800,
162 MLX5_CMD_OP_DEALLOC_PD = 0x801,
163 MLX5_CMD_OP_ALLOC_UAR = 0x802,
164 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
165 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
166 MLX5_CMD_OP_ACCESS_REG = 0x805,
167 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 168 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 169 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
170 MLX5_CMD_OP_MAD_IFC = 0x50d,
171 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
172 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
173 MLX5_CMD_OP_NOP = 0x80d,
174 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
175 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 176 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
177 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
178 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
179 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
180 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
181 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
182 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
183 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
184 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
185 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
186 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
187 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 188 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
189 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 190 MLX5_CMD_OP_CREATE_LAG = 0x840,
191 MLX5_CMD_OP_MODIFY_LAG = 0x841,
192 MLX5_CMD_OP_QUERY_LAG = 0x842,
193 MLX5_CMD_OP_DESTROY_LAG = 0x843,
194 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
195 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 196 MLX5_CMD_OP_CREATE_TIR = 0x900,
197 MLX5_CMD_OP_MODIFY_TIR = 0x901,
198 MLX5_CMD_OP_DESTROY_TIR = 0x902,
199 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 200 MLX5_CMD_OP_CREATE_SQ = 0x904,
201 MLX5_CMD_OP_MODIFY_SQ = 0x905,
202 MLX5_CMD_OP_DESTROY_SQ = 0x906,
203 MLX5_CMD_OP_QUERY_SQ = 0x907,
204 MLX5_CMD_OP_CREATE_RQ = 0x908,
205 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 206 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 207 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
208 MLX5_CMD_OP_QUERY_RQ = 0x90b,
209 MLX5_CMD_OP_CREATE_RMP = 0x90c,
210 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
211 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
212 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 213 MLX5_CMD_OP_CREATE_TIS = 0x912,
214 MLX5_CMD_OP_MODIFY_TIS = 0x913,
215 MLX5_CMD_OP_DESTROY_TIS = 0x914,
216 MLX5_CMD_OP_QUERY_TIS = 0x915,
217 MLX5_CMD_OP_CREATE_RQT = 0x916,
218 MLX5_CMD_OP_MODIFY_RQT = 0x917,
219 MLX5_CMD_OP_DESTROY_RQT = 0x918,
220 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 221 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 222 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
223 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
224 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
225 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
226 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
227 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
228 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
229 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 230 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 231 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
232 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
233 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 234 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 235 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
236 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 237 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
238 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 239 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
240 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
241 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
242 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
243 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 244 MLX5_CMD_OP_MAX
e281682b
SM		 245};
246
247struct mlx5_ifc_flow_table_fields_supported_bits {
248 u8 outer_dmac[0x1];
249 u8 outer_smac[0x1];
250 u8 outer_ether_type[0x1];
19cc7524 251 u8 outer_ip_version[0x1];
e281682b
SM		 252 u8 outer_first_prio[0x1];
253 u8 outer_first_cfi[0x1];
254 u8 outer_first_vid[0x1];
a8ade55f 255 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 256 u8 outer_second_prio[0x1];
257 u8 outer_second_cfi[0x1];
258 u8 outer_second_vid[0x1];
b4ff3a36 259 u8 reserved_at_b[0x1];
e281682b
SM		 260 u8 outer_sip[0x1];
261 u8 outer_dip[0x1];
262 u8 outer_frag[0x1];
263 u8 outer_ip_protocol[0x1];
264 u8 outer_ip_ecn[0x1];
265 u8 outer_ip_dscp[0x1];
266 u8 outer_udp_sport[0x1];
267 u8 outer_udp_dport[0x1];
268 u8 outer_tcp_sport[0x1];
269 u8 outer_tcp_dport[0x1];
270 u8 outer_tcp_flags[0x1];
271 u8 outer_gre_protocol[0x1];
272 u8 outer_gre_key[0x1];
273 u8 outer_vxlan_vni[0x1];
b4ff3a36 274 u8 reserved_at_1a[0x5];
e281682b
SM		 275 u8 source_eswitch_port[0x1];
276
277 u8 inner_dmac[0x1];
278 u8 inner_smac[0x1];
279 u8 inner_ether_type[0x1];
19cc7524 280 u8 inner_ip_version[0x1];
e281682b
SM		 281 u8 inner_first_prio[0x1];
282 u8 inner_first_cfi[0x1];
283 u8 inner_first_vid[0x1];
b4ff3a36 284 u8 reserved_at_27[0x1];
e281682b
SM		 285 u8 inner_second_prio[0x1];
286 u8 inner_second_cfi[0x1];
287 u8 inner_second_vid[0x1];
b4ff3a36 288 u8 reserved_at_2b[0x1];
e281682b
SM		 289 u8 inner_sip[0x1];
290 u8 inner_dip[0x1];
291 u8 inner_frag[0x1];
292 u8 inner_ip_protocol[0x1];
293 u8 inner_ip_ecn[0x1];
294 u8 inner_ip_dscp[0x1];
295 u8 inner_udp_sport[0x1];
296 u8 inner_udp_dport[0x1];
297 u8 inner_tcp_sport[0x1];
298 u8 inner_tcp_dport[0x1];
299 u8 inner_tcp_flags[0x1];
b4ff3a36 300 u8 reserved_at_37[0x9];
3346c487
BP		 301 u8 reserved_at_40[0x17];
302 u8 outer_esp_spi[0x1];
303 u8 reserved_at_58[0x2];
a550ddfc 304 u8 bth_dst_qp[0x1];
e281682b 305
a550ddfc 306 u8 reserved_at_5b[0x25];
e281682b
SM		 307};
308
309struct mlx5_ifc_flow_table_prop_layout_bits {
310 u8 ft_support[0x1];
9dc0b289
AV		 311 u8 reserved_at_1[0x1];
312 u8 flow_counter[0x1];
26a81453 313 u8 flow_modify_en[0x1];
2cc43b49 314 u8 modify_root[0x1];
34a40e68
MG		 315 u8 identified_miss_table_mode[0x1];
316 u8 flow_table_modify[0x1];
7adbde20
HHZ		 317 u8 encap[0x1];
318 u8 decap[0x1];
0c06897a
OG		 319 u8 reserved_at_9[0x1];
320 u8 pop_vlan[0x1];
321 u8 push_vlan[0x1];
322 u8 reserved_at_c[0x14];
e281682b 323
b4ff3a36 324 u8 reserved_at_20[0x2];
e281682b 325 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 326 u8 log_max_modify_header_context[0x8];
327 u8 max_modify_header_actions[0x8];
e281682b
SM		 328 u8 max_ft_level[0x8];
329
b4ff3a36 330 u8 reserved_at_40[0x20];
e281682b 331
b4ff3a36 332 u8 reserved_at_60[0x18];
e281682b
SM		 333 u8 log_max_ft_num[0x8];
334
b4ff3a36 335 u8 reserved_at_80[0x18];
e281682b
SM		 336 u8 log_max_destination[0x8];
337
16f1c5bb
RS		 338 u8 log_max_flow_counter[0x8];
339 u8 reserved_at_a8[0x10];
e281682b
SM		 340 u8 log_max_flow[0x8];
341
b4ff3a36 342 u8 reserved_at_c0[0x40];
e281682b
SM		 343
344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
345
346 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
347};
348
349struct mlx5_ifc_odp_per_transport_service_cap_bits {
350 u8 send[0x1];
351 u8 receive[0x1];
352 u8 write[0x1];
353 u8 read[0x1];
17d2f88f 354 u8 atomic[0x1];
e281682b 355 u8 srq_receive[0x1];
b4ff3a36 356 u8 reserved_at_6[0x1a];
e281682b
SM		 357};
358
359struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
360 u8 smac_47_16[0x20];
361
362 u8 smac_15_0[0x10];
363 u8 ethertype[0x10];
364
365 u8 dmac_47_16[0x20];
366
367 u8 dmac_15_0[0x10];
368 u8 first_prio[0x3];
369 u8 first_cfi[0x1];
370 u8 first_vid[0xc];
371
372 u8 ip_protocol[0x8];
373 u8 ip_dscp[0x6];
374 u8 ip_ecn[0x2];
10543365
MHY		 375 u8 cvlan_tag[0x1];
376 u8 svlan_tag[0x1];
e281682b 377 u8 frag[0x1];
19cc7524 378 u8 ip_version[0x4];
e281682b
SM		 379 u8 tcp_flags[0x9];
380
381 u8 tcp_sport[0x10];
382 u8 tcp_dport[0x10];
383
a8ade55f
OG		 384 u8 reserved_at_c0[0x18];
385 u8 ttl_hoplimit[0x8];
e281682b
SM		 386
387 u8 udp_sport[0x10];
388 u8 udp_dport[0x10];
389
b4d1f032 390 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 391
b4d1f032 392 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 393};
394
395struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 396 u8 reserved_at_0[0x8];
397 u8 source_sqn[0x18];
e281682b 398
3e99df87 399 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 400 u8 source_port[0x10];
401
402 u8 outer_second_prio[0x3];
403 u8 outer_second_cfi[0x1];
404 u8 outer_second_vid[0xc];
405 u8 inner_second_prio[0x3];
406 u8 inner_second_cfi[0x1];
407 u8 inner_second_vid[0xc];
408
10543365
MHY		 409 u8 outer_second_cvlan_tag[0x1];
410 u8 inner_second_cvlan_tag[0x1];
411 u8 outer_second_svlan_tag[0x1];
412 u8 inner_second_svlan_tag[0x1];
413 u8 reserved_at_64[0xc];
e281682b
SM		 414 u8 gre_protocol[0x10];
415
416 u8 gre_key_h[0x18];
417 u8 gre_key_l[0x8];
418
419 u8 vxlan_vni[0x18];
b4ff3a36 420 u8 reserved_at_b8[0x8];
e281682b 421
b4ff3a36 422 u8 reserved_at_c0[0x20];
e281682b 423
b4ff3a36 424 u8 reserved_at_e0[0xc];
e281682b
SM		 425 u8 outer_ipv6_flow_label[0x14];
426
b4ff3a36 427 u8 reserved_at_100[0xc];
e281682b
SM		 428 u8 inner_ipv6_flow_label[0x14];
429
a550ddfc
YH		 430 u8 reserved_at_120[0x28];
431 u8 bth_dst_qp[0x18];
3346c487
BP		 432 u8 reserved_at_160[0x20];
433 u8 outer_esp_spi[0x20];
434 u8 reserved_at_1a0[0x60];
e281682b
SM		 435};
436
437struct mlx5_ifc_cmd_pas_bits {
438 u8 pa_h[0x20];
439
440 u8 pa_l[0x14];
b4ff3a36 441 u8 reserved_at_34[0xc];
e281682b
SM		 442};
443
444struct mlx5_ifc_uint64_bits {
445 u8 hi[0x20];
446
447 u8 lo[0x20];
448};
449
450enum {
451 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
452 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
453 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
454 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
455 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
456 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
457 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
458 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
459 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
460 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
461};
462
463struct mlx5_ifc_ads_bits {
464 u8 fl[0x1];
465 u8 free_ar[0x1];
b4ff3a36 466 u8 reserved_at_2[0xe];
e281682b
SM		 467 u8 pkey_index[0x10];
468
b4ff3a36 469 u8 reserved_at_20[0x8];
e281682b
SM		 470 u8 grh[0x1];
471 u8 mlid[0x7];
472 u8 rlid[0x10];
473
474 u8 ack_timeout[0x5];
b4ff3a36 475 u8 reserved_at_45[0x3];
e281682b 476 u8 src_addr_index[0x8];
b4ff3a36 477 u8 reserved_at_50[0x4];
e281682b
SM		 478 u8 stat_rate[0x4];
479 u8 hop_limit[0x8];
480
b4ff3a36 481 u8 reserved_at_60[0x4];
e281682b
SM		 482 u8 tclass[0x8];
483 u8 flow_label[0x14];
484
485 u8 rgid_rip[16][0x8];
486
b4ff3a36 487 u8 reserved_at_100[0x4];
e281682b
SM		 488 u8 f_dscp[0x1];
489 u8 f_ecn[0x1];
b4ff3a36 490 u8 reserved_at_106[0x1];
e281682b
SM		 491 u8 f_eth_prio[0x1];
492 u8 ecn[0x2];
493 u8 dscp[0x6];
494 u8 udp_sport[0x10];
495
496 u8 dei_cfi[0x1];
497 u8 eth_prio[0x3];
498 u8 sl[0x4];
32f69e4b 499 u8 vhca_port_num[0x8];
e281682b
SM		 500 u8 rmac_47_32[0x10];
501
502 u8 rmac_31_0[0x20];
503};
504
505struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 506 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 507 u8 nic_rx_multi_path_tirs_fts[0x1];
508 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
509 u8 reserved_at_3[0x1fd];
e281682b
SM		 510
511 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
512
b4ff3a36 513 u8 reserved_at_400[0x200];
e281682b
SM		 514
515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
518
b4ff3a36 519 u8 reserved_at_a00[0x200];
e281682b
SM		 520
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
522
b4ff3a36 523 u8 reserved_at_e00[0x7200];
e281682b
SM		 524};
525
495716b1 526struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 527 u8 reserved_at_0[0x200];
495716b1
SM		 528
529 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
530
531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
532
533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
534
b4ff3a36 535 u8 reserved_at_800[0x7800];
495716b1
SM		 536};
537
d6666753
SM		 538struct mlx5_ifc_e_switch_cap_bits {
539 u8 vport_svlan_strip[0x1];
540 u8 vport_cvlan_strip[0x1];
541 u8 vport_svlan_insert[0x1];
542 u8 vport_cvlan_insert_if_not_exist[0x1];
543 u8 vport_cvlan_insert_overwrite[0x1];
a6d04569
RD		 544 u8 reserved_at_5[0x18];
545 u8 merged_eswitch[0x1];
23898c76
NO		 546 u8 nic_vport_node_guid_modify[0x1];
547 u8 nic_vport_port_guid_modify[0x1];
d6666753 548
7adbde20
HHZ		 549 u8 vxlan_encap_decap[0x1];
550 u8 nvgre_encap_decap[0x1];
551 u8 reserved_at_22[0x9];
552 u8 log_max_encap_headers[0x5];
553 u8 reserved_2b[0x6];
554 u8 max_encap_header_size[0xa];
555
556 u8 reserved_40[0x7c0];
557
d6666753
SM		 558};
559
7486216b
SM		 560struct mlx5_ifc_qos_cap_bits {
561 u8 packet_pacing[0x1];
813f8540 562 u8 esw_scheduling[0x1];
c9497c98
MHY		 563 u8 esw_bw_share[0x1];
564 u8 esw_rate_limit[0x1];
05d3ac97
BW		 565 u8 reserved_at_4[0x1];
566 u8 packet_pacing_burst_bound[0x1];
567 u8 packet_pacing_typical_size[0x1];
568 u8 reserved_at_7[0x19];
813f8540
MHY		 569
570 u8 reserved_at_20[0x20];
571
7486216b 572 u8 packet_pacing_max_rate[0x20];
813f8540 573
7486216b 574 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 575
576 u8 reserved_at_80[0x10];
7486216b 577 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 578
579 u8 esw_element_type[0x10];
580 u8 esw_tsar_type[0x10];
581
582 u8 reserved_at_c0[0x10];
583 u8 max_qos_para_vport[0x10];
584
585 u8 max_tsar_bw_share[0x20];
586
587 u8 reserved_at_100[0x700];
7486216b
SM		 588};
589
2fcb12df
IK		 590struct mlx5_ifc_debug_cap_bits {
591 u8 reserved_at_0[0x20];
592
593 u8 reserved_at_20[0x2];
594 u8 stall_detect[0x1];
595 u8 reserved_at_23[0x1d];
596
597 u8 reserved_at_40[0x7c0];
598};
599
e281682b
SM		 600struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
601 u8 csum_cap[0x1];
602 u8 vlan_cap[0x1];
603 u8 lro_cap[0x1];
604 u8 lro_psh_flag[0x1];
605 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 606 u8 reserved_at_5[0x2];
607 u8 wqe_vlan_insert[0x1];
66189961 608 u8 self_lb_en_modifiable[0x1];
b4ff3a36 609 u8 reserved_at_9[0x2];
e281682b 610 u8 max_lso_cap[0x5];
c226dc22 611 u8 multi_pkt_send_wqe[0x2];
cff92d7c 612 u8 wqe_inline_mode[0x2];
e281682b 613 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 614 u8 reg_umr_sq[0x1];
615 u8 scatter_fcs[0x1];
050da902 616 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 617 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 618 u8 reserved_at_1c[0x2];
27299841 619 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 620 u8 tunnel_stateless_vxlan[0x1];
621
547eede0
IT		 622 u8 swp[0x1];
623 u8 swp_csum[0x1];
624 u8 swp_lso[0x1];
4d350f1f
MG		 625 u8 reserved_at_23[0x1b];
626 u8 max_geneve_opt_len[0x1];
627 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 628
b4ff3a36 629 u8 reserved_at_40[0x10];
e281682b
SM		 630 u8 lro_min_mss_size[0x10];
631
b4ff3a36 632 u8 reserved_at_60[0x120];
e281682b
SM		 633
634 u8 lro_timer_supported_periods[4][0x20];
635
b4ff3a36 636 u8 reserved_at_200[0x600];
e281682b
SM		 637};
638
639struct mlx5_ifc_roce_cap_bits {
640 u8 roce_apm[0x1];
b4ff3a36 641 u8 reserved_at_1[0x1f];
e281682b 642
b4ff3a36 643 u8 reserved_at_20[0x60];
e281682b 644
b4ff3a36 645 u8 reserved_at_80[0xc];
e281682b 646 u8 l3_type[0x4];
b4ff3a36 647 u8 reserved_at_90[0x8];
e281682b
SM		 648 u8 roce_version[0x8];
649
b4ff3a36 650 u8 reserved_at_a0[0x10];
e281682b
SM		 651 u8 r_roce_dest_udp_port[0x10];
652
653 u8 r_roce_max_src_udp_port[0x10];
654 u8 r_roce_min_src_udp_port[0x10];
655
b4ff3a36 656 u8 reserved_at_e0[0x10];
e281682b
SM		 657 u8 roce_address_table_size[0x10];
658
b4ff3a36 659 u8 reserved_at_100[0x700];
e281682b
SM		 660};
661
e72bd817
AL		 662struct mlx5_ifc_device_mem_cap_bits {
663 u8 memic[0x1];
664 u8 reserved_at_1[0x1f];
665
666 u8 reserved_at_20[0xb];
667 u8 log_min_memic_alloc_size[0x5];
668 u8 reserved_at_30[0x8];
669 u8 log_max_memic_addr_alignment[0x8];
670
671 u8 memic_bar_start_addr[0x40];
672
673 u8 memic_bar_size[0x20];
674
675 u8 max_memic_size[0x20];
676
677 u8 reserved_at_c0[0x740];
678};
679
e281682b
SM		 680enum {
681 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
682 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
683 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
684 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
689 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
690};
691
692enum {
693 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
694 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
695 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
696 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
702};
703
704struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 705 u8 reserved_at_0[0x40];
e281682b 706
bd10838a 707 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 708 u8 reserved_at_42[0x4];
bd10838a 709 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 710
b4ff3a36 711 u8 reserved_at_47[0x19];
e281682b 712
b4ff3a36 713 u8 reserved_at_60[0x20];
e281682b 714
b4ff3a36 715 u8 reserved_at_80[0x10];
f91e6d89 716 u8 atomic_operations[0x10];
e281682b 717
b4ff3a36 718 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 719 u8 atomic_size_qp[0x10];
720
b4ff3a36 721 u8 reserved_at_c0[0x10];
e281682b
SM		 722 u8 atomic_size_dc[0x10];
723
b4ff3a36 724 u8 reserved_at_e0[0x720];
e281682b
SM		 725};
726
727struct mlx5_ifc_odp_cap_bits {
b4ff3a36 728 u8 reserved_at_0[0x40];
e281682b
SM		 729
730 u8 sig[0x1];
b4ff3a36 731 u8 reserved_at_41[0x1f];
e281682b 732
b4ff3a36 733 u8 reserved_at_60[0x20];
e281682b
SM		 734
735 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
736
737 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
738
739 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
740
b4ff3a36 741 u8 reserved_at_e0[0x720];
e281682b
SM		 742};
743
3f0393a5
SG		 744struct mlx5_ifc_calc_op {
745 u8 reserved_at_0[0x10];
746 u8 reserved_at_10[0x9];
747 u8 op_swap_endianness[0x1];
748 u8 op_min[0x1];
749 u8 op_xor[0x1];
750 u8 op_or[0x1];
751 u8 op_and[0x1];
752 u8 op_max[0x1];
753 u8 op_add[0x1];
754};
755
756struct mlx5_ifc_vector_calc_cap_bits {
757 u8 calc_matrix[0x1];
758 u8 reserved_at_1[0x1f];
759 u8 reserved_at_20[0x8];
760 u8 max_vec_count[0x8];
761 u8 reserved_at_30[0xd];
762 u8 max_chunk_size[0x3];
763 struct mlx5_ifc_calc_op calc0;
764 struct mlx5_ifc_calc_op calc1;
765 struct mlx5_ifc_calc_op calc2;
766 struct mlx5_ifc_calc_op calc3;
767
768 u8 reserved_at_e0[0x720];
769};
770
e281682b
SM		 771enum {
772 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
773 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 774 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 775 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 776};
777
778enum {
779 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
780 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
781};
782
783enum {
784 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
785 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
786 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
787 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
788 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
789};
790
791enum {
792 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
793 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
794 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
795 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
796 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
797 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
798};
799
800enum {
801 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
802 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
803};
804
805enum {
806 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
807 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
808 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
809};
810
811enum {
812 MLX5_CAP_PORT_TYPE_IB = 0x0,
813 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 814};
815
1410a90a
MG		 816enum {
817 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
818 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
819 MLX5_CAP_UMR_FENCE_NONE = 0x2,
820};
821
b775516b 822struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 823 u8 reserved_at_0[0x30];
824 u8 vhca_id[0x10];
825
826 u8 reserved_at_40[0x40];
b775516b
EC		 827
828 u8 log_max_srq_sz[0x8];
829 u8 log_max_qp_sz[0x8];
b4ff3a36 830 u8 reserved_at_90[0xb];
b775516b
EC		 831 u8 log_max_qp[0x5];
832
b4ff3a36 833 u8 reserved_at_a0[0xb];
e281682b 834 u8 log_max_srq[0x5];
b4ff3a36 835 u8 reserved_at_b0[0x10];
b775516b 836
b4ff3a36 837 u8 reserved_at_c0[0x8];
b775516b 838 u8 log_max_cq_sz[0x8];
b4ff3a36 839 u8 reserved_at_d0[0xb];
b775516b
EC		 840 u8 log_max_cq[0x5];
841
842 u8 log_max_eq_sz[0x8];
b4ff3a36 843 u8 reserved_at_e8[0x2];
b775516b 844 u8 log_max_mkey[0x6];
b4ff3a36 845 u8 reserved_at_f0[0xc];
b775516b
EC		 846 u8 log_max_eq[0x4];
847
848 u8 max_indirection[0x8];
bcda1aca 849 u8 fixed_buffer_size[0x1];
b775516b 850 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 851 u8 force_teardown[0x1];
852 u8 reserved_at_111[0x1];
b775516b 853 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 854 u8 umr_extended_translation_offset[0x1];
855 u8 null_mkey[0x1];
b775516b
EC		 856 u8 log_max_klm_list_size[0x6];
857
b4ff3a36 858 u8 reserved_at_120[0xa];
b775516b 859 u8 log_max_ra_req_dc[0x6];
b4ff3a36 860 u8 reserved_at_130[0xa];
b775516b
EC		 861 u8 log_max_ra_res_dc[0x6];
862
b4ff3a36 863 u8 reserved_at_140[0xa];
b775516b 864 u8 log_max_ra_req_qp[0x6];
b4ff3a36 865 u8 reserved_at_150[0xa];
b775516b
EC		 866 u8 log_max_ra_res_qp[0x6];
867
f32f5bd2 868 u8 end_pad[0x1];
b775516b
EC		 869 u8 cc_query_allowed[0x1];
870 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 871 u8 start_pad[0x1];
872 u8 cache_line_128byte[0x1];
c02762eb
HN		 873 u8 reserved_at_165[0xa];
874 u8 qcam_reg[0x1];
e281682b 875 u8 gid_table_size[0x10];
b775516b 876
e281682b
SM		 877 u8 out_of_seq_cnt[0x1];
878 u8 vport_counters[0x1];
7486216b 879 u8 retransmission_q_counters[0x1];
2fcb12df 880 u8 debug[0x1];
83b502a1 881 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 882 u8 rq_delay_drop[0x1];
b775516b
EC		 883 u8 max_qp_cnt[0xa];
884 u8 pkey_table_size[0x10];
885
e281682b
SM		 886 u8 vport_group_manager[0x1];
887 u8 vhca_group_manager[0x1];
888 u8 ib_virt[0x1];
889 u8 eth_virt[0x1];
61c5b5c9 890 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 891 u8 ets[0x1];
892 u8 nic_flow_table[0x1];
54f0a411 893 u8 eswitch_flow_table[0x1];
e72bd817 894 u8 device_memory[0x1];
cfdcbcea
GP		 895 u8 mcam_reg[0x1];
896 u8 pcam_reg[0x1];
b775516b 897 u8 local_ca_ack_delay[0x5];
4ce3bf2f 898 u8 port_module_event[0x1];
58dcb60a 899 u8 enhanced_error_q_counters[0x1];
7d5e1423 900 u8 ports_check[0x1];
7b13558f 901 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 902 u8 disable_link_up[0x1];
903 u8 beacon_led[0x1];
e281682b 904 u8 port_type[0x2];
b775516b
EC		 905 u8 num_ports[0x8];
906
f9a1ef72
EE		 907 u8 reserved_at_1c0[0x1];
908 u8 pps[0x1];
909 u8 pps_modify[0x1];
b775516b 910 u8 log_max_msg[0x5];
e1c9c62b 911 u8 reserved_at_1c8[0x4];
4f3961ee 912 u8 max_tc[0x4];
7486216b
SM		 913 u8 reserved_at_1d0[0x1];
914 u8 dcbx[0x1];
246ac981
MG		 915 u8 general_notification_event[0x1];
916 u8 reserved_at_1d3[0x2];
e29341fb 917 u8 fpga[0x1];
928cfe87
TT		 918 u8 rol_s[0x1];
919 u8 rol_g[0x1];
e1c9c62b 920 u8 reserved_at_1d8[0x1];
928cfe87
TT		 921 u8 wol_s[0x1];
922 u8 wol_g[0x1];
923 u8 wol_a[0x1];
924 u8 wol_b[0x1];
925 u8 wol_m[0x1];
926 u8 wol_u[0x1];
927 u8 wol_p[0x1];
b775516b
EC		 928
929 u8 stat_rate_support[0x10];
e1c9c62b 930 u8 reserved_at_1f0[0xc];
e281682b 931 u8 cqe_version[0x4];
b775516b 932
e281682b 933 u8 compact_address_vector[0x1];
7d5e1423 934 u8 striding_rq[0x1];
500a3d0d
ES		 935 u8 reserved_at_202[0x1];
936 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 937 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 938 u8 reserved_at_205[0x1];
939 u8 repeated_block_disabled[0x1];
940 u8 umr_modify_entity_size_disabled[0x1];
941 u8 umr_modify_atomic_disabled[0x1];
942 u8 umr_indirect_mkey_disabled[0x1];
1410a90a
MG		 943 u8 umr_fence[0x2];
944 u8 reserved_at_20c[0x3];
e281682b 945 u8 drain_sigerr[0x1];
b775516b
EC		 946 u8 cmdif_checksum[0x2];
947 u8 sigerr_cqe[0x1];
e1c9c62b 948 u8 reserved_at_213[0x1];
b775516b
EC		 949 u8 wq_signature[0x1];
950 u8 sctr_data_cqe[0x1];
e1c9c62b 951 u8 reserved_at_216[0x1];
b775516b
EC		 952 u8 sho[0x1];
953 u8 tph[0x1];
954 u8 rf[0x1];
e281682b 955 u8 dct[0x1];
7486216b 956 u8 qos[0x1];
e281682b 957 u8 eth_net_offloads[0x1];
b775516b
EC		 958 u8 roce[0x1];
959 u8 atomic[0x1];
e1c9c62b 960 u8 reserved_at_21f[0x1];
b775516b
EC		 961
962 u8 cq_oi[0x1];
963 u8 cq_resize[0x1];
964 u8 cq_moderation[0x1];
e1c9c62b 965 u8 reserved_at_223[0x3];
e281682b 966 u8 cq_eq_remap[0x1];
b775516b
EC		 967 u8 pg[0x1];
968 u8 block_lb_mc[0x1];
e1c9c62b 969 u8 reserved_at_229[0x1];
e281682b 970 u8 scqe_break_moderation[0x1];
7d5e1423 971 u8 cq_period_start_from_cqe[0x1];
b775516b 972 u8 cd[0x1];
e1c9c62b 973 u8 reserved_at_22d[0x1];
b775516b 974 u8 apm[0x1];
3f0393a5 975 u8 vector_calc[0x1];
7d5e1423 976 u8 umr_ptr_rlky[0x1];
d2370e0a 977 u8 imaicl[0x1];
e1c9c62b 978 u8 reserved_at_232[0x4];
b775516b
EC		 979 u8 qkv[0x1];
980 u8 pkv[0x1];
b11a4f9c
HE		 981 u8 set_deth_sqpn[0x1];
982 u8 reserved_at_239[0x3];
b775516b
EC		 983 u8 xrc[0x1];
984 u8 ud[0x1];
985 u8 uc[0x1];
986 u8 rc[0x1];
987
a6d51b68
EC		 988 u8 uar_4k[0x1];
989 u8 reserved_at_241[0x9];
b775516b 990 u8 uar_sz[0x6];
e1c9c62b 991 u8 reserved_at_250[0x8];
b775516b
EC		 992 u8 log_pg_sz[0x8];
993
994 u8 bf[0x1];
0dbc6fe0 995 u8 driver_version[0x1];
e281682b 996 u8 pad_tx_eth_packet[0x1];
e1c9c62b 997 u8 reserved_at_263[0x8];
b775516b 998 u8 log_bf_reg_size[0x5];
84df61eb
AH		 999
1000 u8 reserved_at_270[0xb];
1001 u8 lag_master[0x1];
1002 u8 num_lag_ports[0x4];
b775516b 1003
e1c9c62b 1004 u8 reserved_at_280[0x10];
b775516b
EC		 1005 u8 max_wqe_sz_sq[0x10];
1006
e1c9c62b 1007 u8 reserved_at_2a0[0x10];
b775516b
EC		 1008 u8 max_wqe_sz_rq[0x10];
1009
a8ffcc74 1010 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1011 u8 max_wqe_sz_sq_dc[0x10];
1012
e1c9c62b 1013 u8 reserved_at_2e0[0x7];
b775516b
EC		 1014 u8 max_qp_mcg[0x19];
1015
e1c9c62b 1016 u8 reserved_at_300[0x18];
b775516b
EC		 1017 u8 log_max_mcg[0x8];
1018
e1c9c62b 1019 u8 reserved_at_320[0x3];
e281682b 1020 u8 log_max_transport_domain[0x5];
e1c9c62b 1021 u8 reserved_at_328[0x3];
b775516b 1022 u8 log_max_pd[0x5];
e1c9c62b 1023 u8 reserved_at_330[0xb];
b775516b
EC		 1024 u8 log_max_xrcd[0x5];
1025
5c298143 1026 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1027 u8 receive_discard_vport_down[0x1];
1028 u8 transmit_discard_vport_down[0x1];
1029 u8 reserved_at_343[0x5];
a351a1b0 1030 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1031 u8 max_flow_counter_15_0[0x10];
a351a1b0 1032
b775516b 1033
e1c9c62b 1034 u8 reserved_at_360[0x3];
b775516b 1035 u8 log_max_rq[0x5];
e1c9c62b 1036 u8 reserved_at_368[0x3];
b775516b 1037 u8 log_max_sq[0x5];
e1c9c62b 1038 u8 reserved_at_370[0x3];
b775516b 1039 u8 log_max_tir[0x5];
e1c9c62b 1040 u8 reserved_at_378[0x3];
b775516b
EC		 1041 u8 log_max_tis[0x5];
1042
e281682b 1043 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1044 u8 reserved_at_381[0x2];
e281682b 1045 u8 log_max_rmp[0x5];
e1c9c62b 1046 u8 reserved_at_388[0x3];
e281682b 1047 u8 log_max_rqt[0x5];
e1c9c62b 1048 u8 reserved_at_390[0x3];
e281682b 1049 u8 log_max_rqt_size[0x5];
e1c9c62b 1050 u8 reserved_at_398[0x3];
b775516b
EC		 1051 u8 log_max_tis_per_sq[0x5];
1052
619a8f2a
TT		 1053 u8 ext_stride_num_range[0x1];
1054 u8 reserved_at_3a1[0x2];
e281682b 1055 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1056 u8 reserved_at_3a8[0x3];
e281682b 1057 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1058 u8 reserved_at_3b0[0x3];
e281682b 1059 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1060 u8 reserved_at_3b8[0x3];
e281682b
SM		 1061 u8 log_min_stride_sz_sq[0x5];
1062
40817cdb
OG		 1063 u8 hairpin[0x1];
1064 u8 reserved_at_3c1[0x2];
1065 u8 log_max_hairpin_queues[0x5];
1066 u8 reserved_at_3c8[0x3];
1067 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1068 u8 reserved_at_3d0[0x3];
1069 u8 log_max_hairpin_num_packets[0x5];
1070 u8 reserved_at_3d8[0x3];
e281682b
SM		 1071 u8 log_max_wq_sz[0x5];
1072
54f0a411 1073 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1074 u8 disable_local_lb_uc[0x1];
1075 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1076 u8 log_min_hairpin_wq_data_sz[0x5];
1077 u8 reserved_at_3e8[0x3];
54f0a411 1078 u8 log_max_vlan_list[0x5];
e1c9c62b 1079 u8 reserved_at_3f0[0x3];
54f0a411 1080 u8 log_max_current_mc_list[0x5];
e1c9c62b 1081 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1082 u8 log_max_current_uc_list[0x5];
1083
e1c9c62b 1084 u8 reserved_at_400[0x80];
54f0a411 1085
e1c9c62b 1086 u8 reserved_at_480[0x3];
e281682b 1087 u8 log_max_l2_table[0x5];
e1c9c62b 1088 u8 reserved_at_488[0x8];
b775516b
EC		 1089 u8 log_uar_page_sz[0x10];
1090
e1c9c62b 1091 u8 reserved_at_4a0[0x20];
048ccca8 1092 u8 device_frequency_mhz[0x20];
b0844444 1093 u8 device_frequency_khz[0x20];
e1c9c62b 1094
a6d51b68
EC		 1095 u8 reserved_at_500[0x20];
1096 u8 num_of_uars_per_page[0x20];
1097 u8 reserved_at_540[0x40];
e1c9c62b 1098
0ff8e79c
GL		 1099 u8 reserved_at_580[0x3d];
1100 u8 cqe_128_always[0x1];
1101 u8 cqe_compression_128[0x1];
7d5e1423 1102 u8 cqe_compression[0x1];
b775516b 1103
7d5e1423
SM		 1104 u8 cqe_compression_timeout[0x10];
1105 u8 cqe_compression_max_num[0x10];
b775516b 1106
7486216b
SM		 1107 u8 reserved_at_5e0[0x10];
1108 u8 tag_matching[0x1];
1109 u8 rndv_offload_rc[0x1];
1110 u8 rndv_offload_dc[0x1];
1111 u8 log_tag_matching_list_sz[0x5];
7b13558f 1112 u8 reserved_at_5f8[0x3];
7486216b
SM		 1113 u8 log_max_xrq[0x5];
1114
32f69e4b
DJ		 1115 u8 affiliate_nic_vport_criteria[0x8];
1116 u8 native_port_num[0x8];
1117 u8 num_vhca_ports[0x8];
1118 u8 reserved_at_618[0x6];
1119 u8 sw_owner_id[0x1];
8737f818 1120 u8 reserved_at_61f[0x1e1];
b775516b
EC		 1121};
1122
81848731
SM		 1123enum mlx5_flow_destination_type {
1124 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1125 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1126 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1127
5f418378 1128 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1129 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1130};
b775516b 1131
e281682b
SM		 1132struct mlx5_ifc_dest_format_struct_bits {
1133 u8 destination_type[0x8];
1134 u8 destination_id[0x18];
b17f7fc1
SK		 1135 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1136 u8 reserved_at_21[0xf];
1137 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1138};
1139
9dc0b289 1140struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1141 u8 flow_counter_id[0x20];
9dc0b289
AV		 1142
1143 u8 reserved_at_20[0x20];
1144};
1145
1146union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1147 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1148 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1149 u8 reserved_at_0[0x40];
1150};
1151
e281682b
SM		 1152struct mlx5_ifc_fte_match_param_bits {
1153 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1154
1155 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1156
1157 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1158
b4ff3a36 1159 u8 reserved_at_600[0xa00];
b775516b
EC		 1160};
1161
e281682b
SM		 1162enum {
1163 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1164 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1165 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1166 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1167 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1168};
b775516b 1169
e281682b
SM		 1170struct mlx5_ifc_rx_hash_field_select_bits {
1171 u8 l3_prot_type[0x1];
1172 u8 l4_prot_type[0x1];
1173 u8 selected_fields[0x1e];
1174};
b775516b 1175
e281682b
SM		 1176enum {
1177 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1178 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1179};
1180
e281682b
SM		 1181enum {
1182 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1183 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1184};
1185
1186struct mlx5_ifc_wq_bits {
1187 u8 wq_type[0x4];
1188 u8 wq_signature[0x1];
1189 u8 end_padding_mode[0x2];
1190 u8 cd_slave[0x1];
b4ff3a36 1191 u8 reserved_at_8[0x18];
b775516b 1192
e281682b
SM		 1193 u8 hds_skip_first_sge[0x1];
1194 u8 log2_hds_buf_size[0x3];
b4ff3a36 1195 u8 reserved_at_24[0x7];
e281682b
SM		 1196 u8 page_offset[0x5];
1197 u8 lwm[0x10];
b775516b 1198
b4ff3a36 1199 u8 reserved_at_40[0x8];
e281682b
SM		 1200 u8 pd[0x18];
1201
b4ff3a36 1202 u8 reserved_at_60[0x8];
e281682b
SM		 1203 u8 uar_page[0x18];
1204
1205 u8 dbr_addr[0x40];
1206
1207 u8 hw_counter[0x20];
1208
1209 u8 sw_counter[0x20];
1210
b4ff3a36 1211 u8 reserved_at_100[0xc];
e281682b 1212 u8 log_wq_stride[0x4];
b4ff3a36 1213 u8 reserved_at_110[0x3];
e281682b 1214 u8 log_wq_pg_sz[0x5];
b4ff3a36 1215 u8 reserved_at_118[0x3];
e281682b
SM		 1216 u8 log_wq_sz[0x5];
1217
4d533e0f
OG		 1218 u8 reserved_at_120[0x3];
1219 u8 log_hairpin_num_packets[0x5];
1220 u8 reserved_at_128[0x3];
40817cdb 1221 u8 log_hairpin_data_sz[0x5];
40817cdb 1222
619a8f2a
TT		 1223 u8 reserved_at_130[0x4];
1224 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1225 u8 two_byte_shift_en[0x1];
1226 u8 reserved_at_139[0x4];
1227 u8 log_wqe_stride_size[0x3];
1228
1229 u8 reserved_at_140[0x4c0];
b775516b 1230
e281682b 1231 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1232};
1233
e281682b 1234struct mlx5_ifc_rq_num_bits {
b4ff3a36 1235 u8 reserved_at_0[0x8];
e281682b
SM		 1236 u8 rq_num[0x18];
1237};
b775516b 1238
e281682b 1239struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1240 u8 reserved_at_0[0x10];
e281682b 1241 u8 mac_addr_47_32[0x10];
b775516b 1242
e281682b
SM		 1243 u8 mac_addr_31_0[0x20];
1244};
1245
c0046cf7 1246struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1247 u8 reserved_at_0[0x14];
c0046cf7
SM		 1248 u8 vlan[0x0c];
1249
b4ff3a36 1250 u8 reserved_at_20[0x20];
c0046cf7
SM		 1251};
1252
e281682b 1253struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1254 u8 reserved_at_0[0xa0];
e281682b
SM		 1255
1256 u8 min_time_between_cnps[0x20];
1257
b4ff3a36 1258 u8 reserved_at_c0[0x12];
e281682b 1259 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1260 u8 reserved_at_d8[0x4];
1261 u8 cnp_prio_mode[0x1];
e281682b
SM		 1262 u8 cnp_802p_prio[0x3];
1263
b4ff3a36 1264 u8 reserved_at_e0[0x720];
e281682b
SM		 1265};
1266
1267struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1268 u8 reserved_at_0[0x60];
e281682b 1269
b4ff3a36 1270 u8 reserved_at_60[0x4];
e281682b 1271 u8 clamp_tgt_rate[0x1];
b4ff3a36 1272 u8 reserved_at_65[0x3];
e281682b 1273 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1274 u8 reserved_at_69[0x17];
e281682b 1275
b4ff3a36 1276 u8 reserved_at_80[0x20];
e281682b
SM		 1277
1278 u8 rpg_time_reset[0x20];
1279
1280 u8 rpg_byte_reset[0x20];
1281
1282 u8 rpg_threshold[0x20];
1283
1284 u8 rpg_max_rate[0x20];
1285
1286 u8 rpg_ai_rate[0x20];
1287
1288 u8 rpg_hai_rate[0x20];
1289
1290 u8 rpg_gd[0x20];
1291
1292 u8 rpg_min_dec_fac[0x20];
1293
1294 u8 rpg_min_rate[0x20];
1295
b4ff3a36 1296 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1297
1298 u8 rate_to_set_on_first_cnp[0x20];
1299
1300 u8 dce_tcp_g[0x20];
1301
1302 u8 dce_tcp_rtt[0x20];
1303
1304 u8 rate_reduce_monitor_period[0x20];
1305
b4ff3a36 1306 u8 reserved_at_320[0x20];
e281682b
SM		 1307
1308 u8 initial_alpha_value[0x20];
1309
b4ff3a36 1310 u8 reserved_at_360[0x4a0];
e281682b
SM		 1311};
1312
1313struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1314 u8 reserved_at_0[0x80];
e281682b
SM		 1315
1316 u8 rppp_max_rps[0x20];
1317
1318 u8 rpg_time_reset[0x20];
1319
1320 u8 rpg_byte_reset[0x20];
1321
1322 u8 rpg_threshold[0x20];
1323
1324 u8 rpg_max_rate[0x20];
1325
1326 u8 rpg_ai_rate[0x20];
1327
1328 u8 rpg_hai_rate[0x20];
1329
1330 u8 rpg_gd[0x20];
1331
1332 u8 rpg_min_dec_fac[0x20];
1333
1334 u8 rpg_min_rate[0x20];
1335
b4ff3a36 1336 u8 reserved_at_1c0[0x640];
e281682b
SM		 1337};
1338
1339enum {
1340 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1341 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1342 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1343};
1344
1345struct mlx5_ifc_resize_field_select_bits {
1346 u8 resize_field_select[0x20];
1347};
1348
1349enum {
1350 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1351 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1352 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1353 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1354};
1355
1356struct mlx5_ifc_modify_field_select_bits {
1357 u8 modify_field_select[0x20];
1358};
1359
1360struct mlx5_ifc_field_select_r_roce_np_bits {
1361 u8 field_select_r_roce_np[0x20];
1362};
1363
1364struct mlx5_ifc_field_select_r_roce_rp_bits {
1365 u8 field_select_r_roce_rp[0x20];
1366};
1367
1368enum {
1369 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1370 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1371 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1372 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1373 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1374 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1375 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1376 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1377 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1378 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1379};
1380
1381struct mlx5_ifc_field_select_802_1qau_rp_bits {
1382 u8 field_select_8021qaurp[0x20];
1383};
1384
1385struct mlx5_ifc_phys_layer_cntrs_bits {
1386 u8 time_since_last_clear_high[0x20];
1387
1388 u8 time_since_last_clear_low[0x20];
1389
1390 u8 symbol_errors_high[0x20];
1391
1392 u8 symbol_errors_low[0x20];
1393
1394 u8 sync_headers_errors_high[0x20];
1395
1396 u8 sync_headers_errors_low[0x20];
1397
1398 u8 edpl_bip_errors_lane0_high[0x20];
1399
1400 u8 edpl_bip_errors_lane0_low[0x20];
1401
1402 u8 edpl_bip_errors_lane1_high[0x20];
1403
1404 u8 edpl_bip_errors_lane1_low[0x20];
1405
1406 u8 edpl_bip_errors_lane2_high[0x20];
1407
1408 u8 edpl_bip_errors_lane2_low[0x20];
1409
1410 u8 edpl_bip_errors_lane3_high[0x20];
1411
1412 u8 edpl_bip_errors_lane3_low[0x20];
1413
1414 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1415
1416 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1417
1418 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1419
1420 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1421
1422 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1423
1424 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1425
1426 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1427
1428 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1429
1430 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1431
1432 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1433
1434 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1435
1436 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1437
1438 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1439
1440 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1441
1442 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1443
1444 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1445
1446 u8 rs_fec_corrected_blocks_high[0x20];
1447
1448 u8 rs_fec_corrected_blocks_low[0x20];
1449
1450 u8 rs_fec_uncorrectable_blocks_high[0x20];
1451
1452 u8 rs_fec_uncorrectable_blocks_low[0x20];
1453
1454 u8 rs_fec_no_errors_blocks_high[0x20];
1455
1456 u8 rs_fec_no_errors_blocks_low[0x20];
1457
1458 u8 rs_fec_single_error_blocks_high[0x20];
1459
1460 u8 rs_fec_single_error_blocks_low[0x20];
1461
1462 u8 rs_fec_corrected_symbols_total_high[0x20];
1463
1464 u8 rs_fec_corrected_symbols_total_low[0x20];
1465
1466 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1467
1468 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1469
1470 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1471
1472 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1473
1474 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1475
1476 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1477
1478 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1479
1480 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1481
1482 u8 link_down_events[0x20];
1483
1484 u8 successful_recovery_events[0x20];
1485
b4ff3a36 1486 u8 reserved_at_640[0x180];
e281682b
SM		 1487};
1488
d8dc0508
GP		 1489struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1490 u8 time_since_last_clear_high[0x20];
1491
1492 u8 time_since_last_clear_low[0x20];
1493
1494 u8 phy_received_bits_high[0x20];
1495
1496 u8 phy_received_bits_low[0x20];
1497
1498 u8 phy_symbol_errors_high[0x20];
1499
1500 u8 phy_symbol_errors_low[0x20];
1501
1502 u8 phy_corrected_bits_high[0x20];
1503
1504 u8 phy_corrected_bits_low[0x20];
1505
1506 u8 phy_corrected_bits_lane0_high[0x20];
1507
1508 u8 phy_corrected_bits_lane0_low[0x20];
1509
1510 u8 phy_corrected_bits_lane1_high[0x20];
1511
1512 u8 phy_corrected_bits_lane1_low[0x20];
1513
1514 u8 phy_corrected_bits_lane2_high[0x20];
1515
1516 u8 phy_corrected_bits_lane2_low[0x20];
1517
1518 u8 phy_corrected_bits_lane3_high[0x20];
1519
1520 u8 phy_corrected_bits_lane3_low[0x20];
1521
1522 u8 reserved_at_200[0x5c0];
1523};
1524
1c64bf6f
MY		 1525struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1526 u8 symbol_error_counter[0x10];
1527
1528 u8 link_error_recovery_counter[0x8];
1529
1530 u8 link_downed_counter[0x8];
1531
1532 u8 port_rcv_errors[0x10];
1533
1534 u8 port_rcv_remote_physical_errors[0x10];
1535
1536 u8 port_rcv_switch_relay_errors[0x10];
1537
1538 u8 port_xmit_discards[0x10];
1539
1540 u8 port_xmit_constraint_errors[0x8];
1541
1542 u8 port_rcv_constraint_errors[0x8];
1543
1544 u8 reserved_at_70[0x8];
1545
1546 u8 link_overrun_errors[0x8];
1547
1548 u8 reserved_at_80[0x10];
1549
1550 u8 vl_15_dropped[0x10];
1551
133bea04
TW		 1552 u8 reserved_at_a0[0x80];
1553
1554 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1555};
1556
e281682b
SM		 1557struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1558 u8 transmit_queue_high[0x20];
1559
1560 u8 transmit_queue_low[0x20];
1561
b4ff3a36 1562 u8 reserved_at_40[0x780];
e281682b
SM		 1563};
1564
1565struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1566 u8 rx_octets_high[0x20];
1567
1568 u8 rx_octets_low[0x20];
1569
b4ff3a36 1570 u8 reserved_at_40[0xc0];
e281682b
SM		 1571
1572 u8 rx_frames_high[0x20];
1573
1574 u8 rx_frames_low[0x20];
1575
1576 u8 tx_octets_high[0x20];
1577
1578 u8 tx_octets_low[0x20];
1579
b4ff3a36 1580 u8 reserved_at_180[0xc0];
e281682b
SM		 1581
1582 u8 tx_frames_high[0x20];
1583
1584 u8 tx_frames_low[0x20];
1585
1586 u8 rx_pause_high[0x20];
1587
1588 u8 rx_pause_low[0x20];
1589
1590 u8 rx_pause_duration_high[0x20];
1591
1592 u8 rx_pause_duration_low[0x20];
1593
1594 u8 tx_pause_high[0x20];
1595
1596 u8 tx_pause_low[0x20];
1597
1598 u8 tx_pause_duration_high[0x20];
1599
1600 u8 tx_pause_duration_low[0x20];
1601
1602 u8 rx_pause_transition_high[0x20];
1603
1604 u8 rx_pause_transition_low[0x20];
1605
2fcb12df
IK		 1606 u8 reserved_at_3c0[0x40];
1607
1608 u8 device_stall_minor_watermark_cnt_high[0x20];
1609
1610 u8 device_stall_minor_watermark_cnt_low[0x20];
1611
1612 u8 device_stall_critical_watermark_cnt_high[0x20];
1613
1614 u8 device_stall_critical_watermark_cnt_low[0x20];
1615
1616 u8 reserved_at_480[0x340];
e281682b
SM		 1617};
1618
1619struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1620 u8 port_transmit_wait_high[0x20];
1621
1622 u8 port_transmit_wait_low[0x20];
1623
2dba0797
GP		 1624 u8 reserved_at_40[0x100];
1625
1626 u8 rx_buffer_almost_full_high[0x20];
1627
1628 u8 rx_buffer_almost_full_low[0x20];
1629
1630 u8 rx_buffer_full_high[0x20];
1631
1632 u8 rx_buffer_full_low[0x20];
1633
1634 u8 reserved_at_1c0[0x600];
e281682b
SM		 1635};
1636
1637struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1638 u8 dot3stats_alignment_errors_high[0x20];
1639
1640 u8 dot3stats_alignment_errors_low[0x20];
1641
1642 u8 dot3stats_fcs_errors_high[0x20];
1643
1644 u8 dot3stats_fcs_errors_low[0x20];
1645
1646 u8 dot3stats_single_collision_frames_high[0x20];
1647
1648 u8 dot3stats_single_collision_frames_low[0x20];
1649
1650 u8 dot3stats_multiple_collision_frames_high[0x20];
1651
1652 u8 dot3stats_multiple_collision_frames_low[0x20];
1653
1654 u8 dot3stats_sqe_test_errors_high[0x20];
1655
1656 u8 dot3stats_sqe_test_errors_low[0x20];
1657
1658 u8 dot3stats_deferred_transmissions_high[0x20];
1659
1660 u8 dot3stats_deferred_transmissions_low[0x20];
1661
1662 u8 dot3stats_late_collisions_high[0x20];
1663
1664 u8 dot3stats_late_collisions_low[0x20];
1665
1666 u8 dot3stats_excessive_collisions_high[0x20];
1667
1668 u8 dot3stats_excessive_collisions_low[0x20];
1669
1670 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1671
1672 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1673
1674 u8 dot3stats_carrier_sense_errors_high[0x20];
1675
1676 u8 dot3stats_carrier_sense_errors_low[0x20];
1677
1678 u8 dot3stats_frame_too_longs_high[0x20];
1679
1680 u8 dot3stats_frame_too_longs_low[0x20];
1681
1682 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1683
1684 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1685
1686 u8 dot3stats_symbol_errors_high[0x20];
1687
1688 u8 dot3stats_symbol_errors_low[0x20];
1689
1690 u8 dot3control_in_unknown_opcodes_high[0x20];
1691
1692 u8 dot3control_in_unknown_opcodes_low[0x20];
1693
1694 u8 dot3in_pause_frames_high[0x20];
1695
1696 u8 dot3in_pause_frames_low[0x20];
1697
1698 u8 dot3out_pause_frames_high[0x20];
1699
1700 u8 dot3out_pause_frames_low[0x20];
1701
b4ff3a36 1702 u8 reserved_at_400[0x3c0];
e281682b
SM		 1703};
1704
1705struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1706 u8 ether_stats_drop_events_high[0x20];
1707
1708 u8 ether_stats_drop_events_low[0x20];
1709
1710 u8 ether_stats_octets_high[0x20];
1711
1712 u8 ether_stats_octets_low[0x20];
1713
1714 u8 ether_stats_pkts_high[0x20];
1715
1716 u8 ether_stats_pkts_low[0x20];
1717
1718 u8 ether_stats_broadcast_pkts_high[0x20];
1719
1720 u8 ether_stats_broadcast_pkts_low[0x20];
1721
1722 u8 ether_stats_multicast_pkts_high[0x20];
1723
1724 u8 ether_stats_multicast_pkts_low[0x20];
1725
1726 u8 ether_stats_crc_align_errors_high[0x20];
1727
1728 u8 ether_stats_crc_align_errors_low[0x20];
1729
1730 u8 ether_stats_undersize_pkts_high[0x20];
1731
1732 u8 ether_stats_undersize_pkts_low[0x20];
1733
1734 u8 ether_stats_oversize_pkts_high[0x20];
1735
1736 u8 ether_stats_oversize_pkts_low[0x20];
1737
1738 u8 ether_stats_fragments_high[0x20];
1739
1740 u8 ether_stats_fragments_low[0x20];
1741
1742 u8 ether_stats_jabbers_high[0x20];
1743
1744 u8 ether_stats_jabbers_low[0x20];
1745
1746 u8 ether_stats_collisions_high[0x20];
1747
1748 u8 ether_stats_collisions_low[0x20];
1749
1750 u8 ether_stats_pkts64octets_high[0x20];
1751
1752 u8 ether_stats_pkts64octets_low[0x20];
1753
1754 u8 ether_stats_pkts65to127octets_high[0x20];
1755
1756 u8 ether_stats_pkts65to127octets_low[0x20];
1757
1758 u8 ether_stats_pkts128to255octets_high[0x20];
1759
1760 u8 ether_stats_pkts128to255octets_low[0x20];
1761
1762 u8 ether_stats_pkts256to511octets_high[0x20];
1763
1764 u8 ether_stats_pkts256to511octets_low[0x20];
1765
1766 u8 ether_stats_pkts512to1023octets_high[0x20];
1767
1768 u8 ether_stats_pkts512to1023octets_low[0x20];
1769
1770 u8 ether_stats_pkts1024to1518octets_high[0x20];
1771
1772 u8 ether_stats_pkts1024to1518octets_low[0x20];
1773
1774 u8 ether_stats_pkts1519to2047octets_high[0x20];
1775
1776 u8 ether_stats_pkts1519to2047octets_low[0x20];
1777
1778 u8 ether_stats_pkts2048to4095octets_high[0x20];
1779
1780 u8 ether_stats_pkts2048to4095octets_low[0x20];
1781
1782 u8 ether_stats_pkts4096to8191octets_high[0x20];
1783
1784 u8 ether_stats_pkts4096to8191octets_low[0x20];
1785
1786 u8 ether_stats_pkts8192to10239octets_high[0x20];
1787
1788 u8 ether_stats_pkts8192to10239octets_low[0x20];
1789
b4ff3a36 1790 u8 reserved_at_540[0x280];
e281682b
SM		 1791};
1792
1793struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1794 u8 if_in_octets_high[0x20];
1795
1796 u8 if_in_octets_low[0x20];
1797
1798 u8 if_in_ucast_pkts_high[0x20];
1799
1800 u8 if_in_ucast_pkts_low[0x20];
1801
1802 u8 if_in_discards_high[0x20];
1803
1804 u8 if_in_discards_low[0x20];
1805
1806 u8 if_in_errors_high[0x20];
1807
1808 u8 if_in_errors_low[0x20];
1809
1810 u8 if_in_unknown_protos_high[0x20];
1811
1812 u8 if_in_unknown_protos_low[0x20];
1813
1814 u8 if_out_octets_high[0x20];
1815
1816 u8 if_out_octets_low[0x20];
1817
1818 u8 if_out_ucast_pkts_high[0x20];
1819
1820 u8 if_out_ucast_pkts_low[0x20];
1821
1822 u8 if_out_discards_high[0x20];
1823
1824 u8 if_out_discards_low[0x20];
1825
1826 u8 if_out_errors_high[0x20];
1827
1828 u8 if_out_errors_low[0x20];
1829
1830 u8 if_in_multicast_pkts_high[0x20];
1831
1832 u8 if_in_multicast_pkts_low[0x20];
1833
1834 u8 if_in_broadcast_pkts_high[0x20];
1835
1836 u8 if_in_broadcast_pkts_low[0x20];
1837
1838 u8 if_out_multicast_pkts_high[0x20];
1839
1840 u8 if_out_multicast_pkts_low[0x20];
1841
1842 u8 if_out_broadcast_pkts_high[0x20];
1843
1844 u8 if_out_broadcast_pkts_low[0x20];
1845
b4ff3a36 1846 u8 reserved_at_340[0x480];
e281682b
SM		 1847};
1848
1849struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1850 u8 a_frames_transmitted_ok_high[0x20];
1851
1852 u8 a_frames_transmitted_ok_low[0x20];
1853
1854 u8 a_frames_received_ok_high[0x20];
1855
1856 u8 a_frames_received_ok_low[0x20];
1857
1858 u8 a_frame_check_sequence_errors_high[0x20];
1859
1860 u8 a_frame_check_sequence_errors_low[0x20];
1861
1862 u8 a_alignment_errors_high[0x20];
1863
1864 u8 a_alignment_errors_low[0x20];
1865
1866 u8 a_octets_transmitted_ok_high[0x20];
1867
1868 u8 a_octets_transmitted_ok_low[0x20];
1869
1870 u8 a_octets_received_ok_high[0x20];
1871
1872 u8 a_octets_received_ok_low[0x20];
1873
1874 u8 a_multicast_frames_xmitted_ok_high[0x20];
1875
1876 u8 a_multicast_frames_xmitted_ok_low[0x20];
1877
1878 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1879
1880 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1881
1882 u8 a_multicast_frames_received_ok_high[0x20];
1883
1884 u8 a_multicast_frames_received_ok_low[0x20];
1885
1886 u8 a_broadcast_frames_received_ok_high[0x20];
1887
1888 u8 a_broadcast_frames_received_ok_low[0x20];
1889
1890 u8 a_in_range_length_errors_high[0x20];
1891
1892 u8 a_in_range_length_errors_low[0x20];
1893
1894 u8 a_out_of_range_length_field_high[0x20];
1895
1896 u8 a_out_of_range_length_field_low[0x20];
1897
1898 u8 a_frame_too_long_errors_high[0x20];
1899
1900 u8 a_frame_too_long_errors_low[0x20];
1901
1902 u8 a_symbol_error_during_carrier_high[0x20];
1903
1904 u8 a_symbol_error_during_carrier_low[0x20];
1905
1906 u8 a_mac_control_frames_transmitted_high[0x20];
1907
1908 u8 a_mac_control_frames_transmitted_low[0x20];
1909
1910 u8 a_mac_control_frames_received_high[0x20];
1911
1912 u8 a_mac_control_frames_received_low[0x20];
1913
1914 u8 a_unsupported_opcodes_received_high[0x20];
1915
1916 u8 a_unsupported_opcodes_received_low[0x20];
1917
1918 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1919
1920 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1921
1922 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1923
1924 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1925
b4ff3a36 1926 u8 reserved_at_4c0[0x300];
e281682b
SM		 1927};
1928
8ed1a630
GP		 1929struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1930 u8 life_time_counter_high[0x20];
1931
1932 u8 life_time_counter_low[0x20];
1933
1934 u8 rx_errors[0x20];
1935
1936 u8 tx_errors[0x20];
1937
1938 u8 l0_to_recovery_eieos[0x20];
1939
1940 u8 l0_to_recovery_ts[0x20];
1941
1942 u8 l0_to_recovery_framing[0x20];
1943
1944 u8 l0_to_recovery_retrain[0x20];
1945
1946 u8 crc_error_dllp[0x20];
1947
1948 u8 crc_error_tlp[0x20];
1949
efae7f78
EBE		 1950 u8 tx_overflow_buffer_pkt_high[0x20];
1951
1952 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 1953
1954 u8 outbound_stalled_reads[0x20];
1955
1956 u8 outbound_stalled_writes[0x20];
1957
1958 u8 outbound_stalled_reads_events[0x20];
1959
1960 u8 outbound_stalled_writes_events[0x20];
1961
1962 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 1963};
1964
e281682b
SM		 1965struct mlx5_ifc_cmd_inter_comp_event_bits {
1966 u8 command_completion_vector[0x20];
1967
b4ff3a36 1968 u8 reserved_at_20[0xc0];
e281682b
SM		 1969};
1970
1971struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1972 u8 reserved_at_0[0x18];
e281682b 1973 u8 port_num[0x1];
b4ff3a36 1974 u8 reserved_at_19[0x3];
e281682b
SM		 1975 u8 vl[0x4];
1976
b4ff3a36 1977 u8 reserved_at_20[0xa0];
e281682b
SM		 1978};
1979
1980struct mlx5_ifc_db_bf_congestion_event_bits {
1981 u8 event_subtype[0x8];
b4ff3a36 1982 u8 reserved_at_8[0x8];
e281682b 1983 u8 congestion_level[0x8];
b4ff3a36 1984 u8 reserved_at_18[0x8];
e281682b 1985
b4ff3a36 1986 u8 reserved_at_20[0xa0];
e281682b
SM		 1987};
1988
1989struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1990 u8 reserved_at_0[0x60];
e281682b
SM		 1991
1992 u8 gpio_event_hi[0x20];
1993
1994 u8 gpio_event_lo[0x20];
1995
b4ff3a36 1996 u8 reserved_at_a0[0x40];
e281682b
SM		 1997};
1998
1999struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2000 u8 reserved_at_0[0x40];
e281682b
SM		 2001
2002 u8 port_num[0x4];
b4ff3a36 2003 u8 reserved_at_44[0x1c];
e281682b 2004
b4ff3a36 2005 u8 reserved_at_60[0x80];
e281682b
SM		 2006};
2007
2008struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2009 u8 reserved_at_0[0xe0];
e281682b
SM		 2010};
2011
2012enum {
2013 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2014 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2015};
2016
2017struct mlx5_ifc_cq_error_bits {
b4ff3a36 2018 u8 reserved_at_0[0x8];
e281682b
SM		 2019 u8 cqn[0x18];
2020
b4ff3a36 2021 u8 reserved_at_20[0x20];
e281682b 2022
b4ff3a36 2023 u8 reserved_at_40[0x18];
e281682b
SM		 2024 u8 syndrome[0x8];
2025
b4ff3a36 2026 u8 reserved_at_60[0x80];
e281682b
SM		 2027};
2028
2029struct mlx5_ifc_rdma_page_fault_event_bits {
2030 u8 bytes_committed[0x20];
2031
2032 u8 r_key[0x20];
2033
b4ff3a36 2034 u8 reserved_at_40[0x10];
e281682b
SM		 2035 u8 packet_len[0x10];
2036
2037 u8 rdma_op_len[0x20];
2038
2039 u8 rdma_va[0x40];
2040
b4ff3a36 2041 u8 reserved_at_c0[0x5];
e281682b
SM		 2042 u8 rdma[0x1];
2043 u8 write[0x1];
2044 u8 requestor[0x1];
2045 u8 qp_number[0x18];
2046};
2047
2048struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2049 u8 bytes_committed[0x20];
2050
b4ff3a36 2051 u8 reserved_at_20[0x10];
e281682b
SM		 2052 u8 wqe_index[0x10];
2053
b4ff3a36 2054 u8 reserved_at_40[0x10];
e281682b
SM		 2055 u8 len[0x10];
2056
b4ff3a36 2057 u8 reserved_at_60[0x60];
e281682b 2058
b4ff3a36 2059 u8 reserved_at_c0[0x5];
e281682b
SM		 2060 u8 rdma[0x1];
2061 u8 write_read[0x1];
2062 u8 requestor[0x1];
2063 u8 qpn[0x18];
2064};
2065
2066struct mlx5_ifc_qp_events_bits {
b4ff3a36 2067 u8 reserved_at_0[0xa0];
e281682b
SM		 2068
2069 u8 type[0x8];
b4ff3a36 2070 u8 reserved_at_a8[0x18];
e281682b 2071
b4ff3a36 2072 u8 reserved_at_c0[0x8];
e281682b
SM		 2073 u8 qpn_rqn_sqn[0x18];
2074};
2075
2076struct mlx5_ifc_dct_events_bits {
b4ff3a36 2077 u8 reserved_at_0[0xc0];
e281682b 2078
b4ff3a36 2079 u8 reserved_at_c0[0x8];
e281682b
SM		 2080 u8 dct_number[0x18];
2081};
2082
2083struct mlx5_ifc_comp_event_bits {
b4ff3a36 2084 u8 reserved_at_0[0xc0];
e281682b 2085
b4ff3a36 2086 u8 reserved_at_c0[0x8];
e281682b
SM		 2087 u8 cq_number[0x18];
2088};
2089
2090enum {
2091 MLX5_QPC_STATE_RST = 0x0,
2092 MLX5_QPC_STATE_INIT = 0x1,
2093 MLX5_QPC_STATE_RTR = 0x2,
2094 MLX5_QPC_STATE_RTS = 0x3,
2095 MLX5_QPC_STATE_SQER = 0x4,
2096 MLX5_QPC_STATE_ERR = 0x6,
2097 MLX5_QPC_STATE_SQD = 0x7,
2098 MLX5_QPC_STATE_SUSPENDED = 0x9,
2099};
2100
2101enum {
2102 MLX5_QPC_ST_RC = 0x0,
2103 MLX5_QPC_ST_UC = 0x1,
2104 MLX5_QPC_ST_UD = 0x2,
2105 MLX5_QPC_ST_XRC = 0x3,
2106 MLX5_QPC_ST_DCI = 0x5,
2107 MLX5_QPC_ST_QP0 = 0x7,
2108 MLX5_QPC_ST_QP1 = 0x8,
2109 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2110 MLX5_QPC_ST_REG_UMR = 0xc,
2111};
2112
2113enum {
2114 MLX5_QPC_PM_STATE_ARMED = 0x0,
2115 MLX5_QPC_PM_STATE_REARM = 0x1,
2116 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2117 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2118};
2119
6e44636a
AK		 2120enum {
2121 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2122};
2123
e281682b
SM		 2124enum {
2125 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2126 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2127};
2128
2129enum {
2130 MLX5_QPC_MTU_256_BYTES = 0x1,
2131 MLX5_QPC_MTU_512_BYTES = 0x2,
2132 MLX5_QPC_MTU_1K_BYTES = 0x3,
2133 MLX5_QPC_MTU_2K_BYTES = 0x4,
2134 MLX5_QPC_MTU_4K_BYTES = 0x5,
2135 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2136};
2137
2138enum {
2139 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2140 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2141 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2142 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2143 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2144 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2145 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2146 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2147};
2148
2149enum {
2150 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2151 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2152 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2153};
2154
2155enum {
2156 MLX5_QPC_CS_RES_DISABLE = 0x0,
2157 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2158 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2159};
2160
2161struct mlx5_ifc_qpc_bits {
2162 u8 state[0x4];
84df61eb 2163 u8 lag_tx_port_affinity[0x4];
e281682b 2164 u8 st[0x8];
b4ff3a36 2165 u8 reserved_at_10[0x3];
e281682b 2166 u8 pm_state[0x2];
6e44636a
AK		 2167 u8 reserved_at_15[0x3];
2168 u8 offload_type[0x4];
e281682b 2169 u8 end_padding_mode[0x2];
b4ff3a36 2170 u8 reserved_at_1e[0x2];
e281682b
SM		 2171
2172 u8 wq_signature[0x1];
2173 u8 block_lb_mc[0x1];
2174 u8 atomic_like_write_en[0x1];
2175 u8 latency_sensitive[0x1];
b4ff3a36 2176 u8 reserved_at_24[0x1];
e281682b 2177 u8 drain_sigerr[0x1];
b4ff3a36 2178 u8 reserved_at_26[0x2];
e281682b
SM		 2179 u8 pd[0x18];
2180
2181 u8 mtu[0x3];
2182 u8 log_msg_max[0x5];
b4ff3a36 2183 u8 reserved_at_48[0x1];
e281682b
SM		 2184 u8 log_rq_size[0x4];
2185 u8 log_rq_stride[0x3];
2186 u8 no_sq[0x1];
2187 u8 log_sq_size[0x4];
b4ff3a36 2188 u8 reserved_at_55[0x6];
e281682b 2189 u8 rlky[0x1];
1015c2e8 2190 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2191
2192 u8 counter_set_id[0x8];
2193 u8 uar_page[0x18];
2194
b4ff3a36 2195 u8 reserved_at_80[0x8];
e281682b
SM		 2196 u8 user_index[0x18];
2197
b4ff3a36 2198 u8 reserved_at_a0[0x3];
e281682b
SM		 2199 u8 log_page_size[0x5];
2200 u8 remote_qpn[0x18];
2201
2202 struct mlx5_ifc_ads_bits primary_address_path;
2203
2204 struct mlx5_ifc_ads_bits secondary_address_path;
2205
2206 u8 log_ack_req_freq[0x4];
b4ff3a36 2207 u8 reserved_at_384[0x4];
e281682b 2208 u8 log_sra_max[0x3];
b4ff3a36 2209 u8 reserved_at_38b[0x2];
e281682b
SM		 2210 u8 retry_count[0x3];
2211 u8 rnr_retry[0x3];
b4ff3a36 2212 u8 reserved_at_393[0x1];
e281682b
SM		 2213 u8 fre[0x1];
2214 u8 cur_rnr_retry[0x3];
2215 u8 cur_retry_count[0x3];
b4ff3a36 2216 u8 reserved_at_39b[0x5];
e281682b 2217
b4ff3a36 2218 u8 reserved_at_3a0[0x20];
e281682b 2219
b4ff3a36 2220 u8 reserved_at_3c0[0x8];
e281682b
SM		 2221 u8 next_send_psn[0x18];
2222
b4ff3a36 2223 u8 reserved_at_3e0[0x8];
e281682b
SM		 2224 u8 cqn_snd[0x18];
2225
09a7d9ec
SM		 2226 u8 reserved_at_400[0x8];
2227 u8 deth_sqpn[0x18];
2228
2229 u8 reserved_at_420[0x20];
e281682b 2230
b4ff3a36 2231 u8 reserved_at_440[0x8];
e281682b
SM		 2232 u8 last_acked_psn[0x18];
2233
b4ff3a36 2234 u8 reserved_at_460[0x8];
e281682b
SM		 2235 u8 ssn[0x18];
2236
b4ff3a36 2237 u8 reserved_at_480[0x8];
e281682b 2238 u8 log_rra_max[0x3];
b4ff3a36 2239 u8 reserved_at_48b[0x1];
e281682b
SM		 2240 u8 atomic_mode[0x4];
2241 u8 rre[0x1];
2242 u8 rwe[0x1];
2243 u8 rae[0x1];
b4ff3a36 2244 u8 reserved_at_493[0x1];
e281682b 2245 u8 page_offset[0x6];
b4ff3a36 2246 u8 reserved_at_49a[0x3];
e281682b
SM		 2247 u8 cd_slave_receive[0x1];
2248 u8 cd_slave_send[0x1];
2249 u8 cd_master[0x1];
2250
b4ff3a36 2251 u8 reserved_at_4a0[0x3];
e281682b
SM		 2252 u8 min_rnr_nak[0x5];
2253 u8 next_rcv_psn[0x18];
2254
b4ff3a36 2255 u8 reserved_at_4c0[0x8];
e281682b
SM		 2256 u8 xrcd[0x18];
2257
b4ff3a36 2258 u8 reserved_at_4e0[0x8];
e281682b
SM		 2259 u8 cqn_rcv[0x18];
2260
2261 u8 dbr_addr[0x40];
2262
2263 u8 q_key[0x20];
2264
b4ff3a36 2265 u8 reserved_at_560[0x5];
e281682b 2266 u8 rq_type[0x3];
7486216b 2267 u8 srqn_rmpn_xrqn[0x18];
e281682b 2268
b4ff3a36 2269 u8 reserved_at_580[0x8];
e281682b
SM		 2270 u8 rmsn[0x18];
2271
2272 u8 hw_sq_wqebb_counter[0x10];
2273 u8 sw_sq_wqebb_counter[0x10];
2274
2275 u8 hw_rq_counter[0x20];
2276
2277 u8 sw_rq_counter[0x20];
2278
b4ff3a36 2279 u8 reserved_at_600[0x20];
e281682b 2280
b4ff3a36 2281 u8 reserved_at_620[0xf];
e281682b
SM		 2282 u8 cgs[0x1];
2283 u8 cs_req[0x8];
2284 u8 cs_res[0x8];
2285
2286 u8 dc_access_key[0x40];
2287
b4ff3a36 2288 u8 reserved_at_680[0xc0];
e281682b
SM		 2289};
2290
2291struct mlx5_ifc_roce_addr_layout_bits {
2292 u8 source_l3_address[16][0x8];
2293
b4ff3a36 2294 u8 reserved_at_80[0x3];
e281682b
SM		 2295 u8 vlan_valid[0x1];
2296 u8 vlan_id[0xc];
2297 u8 source_mac_47_32[0x10];
2298
2299 u8 source_mac_31_0[0x20];
2300
b4ff3a36 2301 u8 reserved_at_c0[0x14];
e281682b
SM		 2302 u8 roce_l3_type[0x4];
2303 u8 roce_version[0x8];
2304
b4ff3a36 2305 u8 reserved_at_e0[0x20];
e281682b
SM		 2306};
2307
2308union mlx5_ifc_hca_cap_union_bits {
2309 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2310 struct mlx5_ifc_odp_cap_bits odp_cap;
2311 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2312 struct mlx5_ifc_roce_cap_bits roce_cap;
2313 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2314 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2315 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2316 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2317 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2318 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2319 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2320 u8 reserved_at_0[0x8000];
e281682b
SM		 2321};
2322
2323enum {
2324 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2325 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2326 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2327 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2328 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2329 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2330 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2331 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2332 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2333};
2334
2335struct mlx5_ifc_vlan_bits {
2336 u8 ethtype[0x10];
2337 u8 prio[0x3];
2338 u8 cfi[0x1];
2339 u8 vid[0xc];
e281682b
SM		 2340};
2341
2342struct mlx5_ifc_flow_context_bits {
0c06897a 2343 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2344
2345 u8 group_id[0x20];
2346
b4ff3a36 2347 u8 reserved_at_40[0x8];
e281682b
SM		 2348 u8 flow_tag[0x18];
2349
b4ff3a36 2350 u8 reserved_at_60[0x10];
e281682b
SM		 2351 u8 action[0x10];
2352
b4ff3a36 2353 u8 reserved_at_80[0x8];
e281682b
SM		 2354 u8 destination_list_size[0x18];
2355
9dc0b289
AV		 2356 u8 reserved_at_a0[0x8];
2357 u8 flow_counter_list_size[0x18];
2358
7adbde20
HHZ		 2359 u8 encap_id[0x20];
2360
2a69cb9f
OG		 2361 u8 modify_header_id[0x20];
2362
2363 u8 reserved_at_100[0x100];
e281682b
SM		 2364
2365 struct mlx5_ifc_fte_match_param_bits match_value;
2366
b4ff3a36 2367 u8 reserved_at_1200[0x600];
e281682b 2368
9dc0b289 2369 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2370};
2371
2372enum {
2373 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2374 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2375};
2376
2377struct mlx5_ifc_xrc_srqc_bits {
2378 u8 state[0x4];
2379 u8 log_xrc_srq_size[0x4];
b4ff3a36 2380 u8 reserved_at_8[0x18];
e281682b
SM		 2381
2382 u8 wq_signature[0x1];
2383 u8 cont_srq[0x1];
b4ff3a36 2384 u8 reserved_at_22[0x1];
e281682b
SM		 2385 u8 rlky[0x1];
2386 u8 basic_cyclic_rcv_wqe[0x1];
2387 u8 log_rq_stride[0x3];
2388 u8 xrcd[0x18];
2389
2390 u8 page_offset[0x6];
b4ff3a36 2391 u8 reserved_at_46[0x2];
e281682b
SM		 2392 u8 cqn[0x18];
2393
b4ff3a36 2394 u8 reserved_at_60[0x20];
e281682b
SM		 2395
2396 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2397 u8 reserved_at_81[0x1];
e281682b
SM		 2398 u8 log_page_size[0x6];
2399 u8 user_index[0x18];
2400
b4ff3a36 2401 u8 reserved_at_a0[0x20];
e281682b 2402
b4ff3a36 2403 u8 reserved_at_c0[0x8];
e281682b
SM		 2404 u8 pd[0x18];
2405
2406 u8 lwm[0x10];
2407 u8 wqe_cnt[0x10];
2408
b4ff3a36 2409 u8 reserved_at_100[0x40];
e281682b
SM		 2410
2411 u8 db_record_addr_h[0x20];
2412
2413 u8 db_record_addr_l[0x1e];
b4ff3a36 2414 u8 reserved_at_17e[0x2];
e281682b 2415
b4ff3a36 2416 u8 reserved_at_180[0x80];
e281682b
SM		 2417};
2418
61c5b5c9
MS		 2419struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2420 u8 counter_error_queues[0x20];
2421
2422 u8 total_error_queues[0x20];
2423
2424 u8 send_queue_priority_update_flow[0x20];
2425
2426 u8 reserved_at_60[0x20];
2427
2428 u8 nic_receive_steering_discard[0x40];
2429
2430 u8 receive_discard_vport_down[0x40];
2431
2432 u8 transmit_discard_vport_down[0x40];
2433
2434 u8 reserved_at_140[0xec0];
2435};
2436
e281682b
SM		 2437struct mlx5_ifc_traffic_counter_bits {
2438 u8 packets[0x40];
2439
2440 u8 octets[0x40];
2441};
2442
2443struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2444 u8 strict_lag_tx_port_affinity[0x1];
2445 u8 reserved_at_1[0x3];
2446 u8 lag_tx_port_affinity[0x04];
2447
2448 u8 reserved_at_8[0x4];
e281682b 2449 u8 prio[0x4];
b4ff3a36 2450 u8 reserved_at_10[0x10];
e281682b 2451
b4ff3a36 2452 u8 reserved_at_20[0x100];
e281682b 2453
b4ff3a36 2454 u8 reserved_at_120[0x8];
e281682b
SM		 2455 u8 transport_domain[0x18];
2456
500a3d0d
ES		 2457 u8 reserved_at_140[0x8];
2458 u8 underlay_qpn[0x18];
2459 u8 reserved_at_160[0x3a0];
e281682b
SM		 2460};
2461
2462enum {
2463 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2464 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2465};
2466
2467enum {
2468 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2469 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2470};
2471
2472enum {
2be6967c
SM		 2473 MLX5_RX_HASH_FN_NONE = 0x0,
2474 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2475 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2476};
2477
2478enum {
2479 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2480 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2481};
2482
2483struct mlx5_ifc_tirc_bits {
b4ff3a36 2484 u8 reserved_at_0[0x20];
e281682b
SM		 2485
2486 u8 disp_type[0x4];
b4ff3a36 2487 u8 reserved_at_24[0x1c];
e281682b 2488
b4ff3a36 2489 u8 reserved_at_40[0x40];
e281682b 2490
b4ff3a36 2491 u8 reserved_at_80[0x4];
e281682b
SM		 2492 u8 lro_timeout_period_usecs[0x10];
2493 u8 lro_enable_mask[0x4];
2494 u8 lro_max_ip_payload_size[0x8];
2495
b4ff3a36 2496 u8 reserved_at_a0[0x40];
e281682b 2497
b4ff3a36 2498 u8 reserved_at_e0[0x8];
e281682b
SM		 2499 u8 inline_rqn[0x18];
2500
2501 u8 rx_hash_symmetric[0x1];
b4ff3a36 2502 u8 reserved_at_101[0x1];
e281682b 2503 u8 tunneled_offload_en[0x1];
b4ff3a36 2504 u8 reserved_at_103[0x5];
e281682b
SM		 2505 u8 indirect_table[0x18];
2506
2507 u8 rx_hash_fn[0x4];
b4ff3a36 2508 u8 reserved_at_124[0x2];
e281682b
SM		 2509 u8 self_lb_block[0x2];
2510 u8 transport_domain[0x18];
2511
2512 u8 rx_hash_toeplitz_key[10][0x20];
2513
2514 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2515
2516 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2517
b4ff3a36 2518 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2519};
2520
2521enum {
2522 MLX5_SRQC_STATE_GOOD = 0x0,
2523 MLX5_SRQC_STATE_ERROR = 0x1,
2524};
2525
2526struct mlx5_ifc_srqc_bits {
2527 u8 state[0x4];
2528 u8 log_srq_size[0x4];
b4ff3a36 2529 u8 reserved_at_8[0x18];
e281682b
SM		 2530
2531 u8 wq_signature[0x1];
2532 u8 cont_srq[0x1];
b4ff3a36 2533 u8 reserved_at_22[0x1];
e281682b 2534 u8 rlky[0x1];
b4ff3a36 2535 u8 reserved_at_24[0x1];
e281682b
SM		 2536 u8 log_rq_stride[0x3];
2537 u8 xrcd[0x18];
2538
2539 u8 page_offset[0x6];
b4ff3a36 2540 u8 reserved_at_46[0x2];
e281682b
SM		 2541 u8 cqn[0x18];
2542
b4ff3a36 2543 u8 reserved_at_60[0x20];
e281682b 2544
b4ff3a36 2545 u8 reserved_at_80[0x2];
e281682b 2546 u8 log_page_size[0x6];
b4ff3a36 2547 u8 reserved_at_88[0x18];
e281682b 2548
b4ff3a36 2549 u8 reserved_at_a0[0x20];
e281682b 2550
b4ff3a36 2551 u8 reserved_at_c0[0x8];
e281682b
SM		 2552 u8 pd[0x18];
2553
2554 u8 lwm[0x10];
2555 u8 wqe_cnt[0x10];
2556
b4ff3a36 2557 u8 reserved_at_100[0x40];
e281682b 2558
01949d01 2559 u8 dbr_addr[0x40];
e281682b 2560
b4ff3a36 2561 u8 reserved_at_180[0x80];
e281682b
SM		 2562};
2563
2564enum {
2565 MLX5_SQC_STATE_RST = 0x0,
2566 MLX5_SQC_STATE_RDY = 0x1,
2567 MLX5_SQC_STATE_ERR = 0x3,
2568};
2569
2570struct mlx5_ifc_sqc_bits {
2571 u8 rlky[0x1];
2572 u8 cd_master[0x1];
2573 u8 fre[0x1];
2574 u8 flush_in_error_en[0x1];
795b609c 2575 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2576 u8 min_wqe_inline_mode[0x3];
e281682b 2577 u8 state[0x4];
7d5e1423 2578 u8 reg_umr[0x1];
547eede0 2579 u8 allow_swp[0x1];
40817cdb
OG		 2580 u8 hairpin[0x1];
2581 u8 reserved_at_f[0x11];
e281682b 2582
b4ff3a36 2583 u8 reserved_at_20[0x8];
e281682b
SM		 2584 u8 user_index[0x18];
2585
b4ff3a36 2586 u8 reserved_at_40[0x8];
e281682b
SM		 2587 u8 cqn[0x18];
2588
40817cdb
OG		 2589 u8 reserved_at_60[0x8];
2590 u8 hairpin_peer_rq[0x18];
2591
2592 u8 reserved_at_80[0x10];
2593 u8 hairpin_peer_vhca[0x10];
2594
2595 u8 reserved_at_a0[0x50];
e281682b 2596
7486216b 2597 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2598 u8 tis_lst_sz[0x10];
b4ff3a36 2599 u8 reserved_at_110[0x10];
e281682b 2600
b4ff3a36 2601 u8 reserved_at_120[0x40];
e281682b 2602
b4ff3a36 2603 u8 reserved_at_160[0x8];
e281682b
SM		 2604 u8 tis_num_0[0x18];
2605
2606 struct mlx5_ifc_wq_bits wq;
2607};
2608
813f8540
MHY		 2609enum {
2610 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2611 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2612 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2613 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2614};
2615
2616struct mlx5_ifc_scheduling_context_bits {
2617 u8 element_type[0x8];
2618 u8 reserved_at_8[0x18];
2619
2620 u8 element_attributes[0x20];
2621
2622 u8 parent_element_id[0x20];
2623
2624 u8 reserved_at_60[0x40];
2625
2626 u8 bw_share[0x20];
2627
2628 u8 max_average_bw[0x20];
2629
2630 u8 reserved_at_e0[0x120];
2631};
2632
e281682b 2633struct mlx5_ifc_rqtc_bits {
b4ff3a36 2634 u8 reserved_at_0[0xa0];
e281682b 2635
b4ff3a36 2636 u8 reserved_at_a0[0x10];
e281682b
SM		 2637 u8 rqt_max_size[0x10];
2638
b4ff3a36 2639 u8 reserved_at_c0[0x10];
e281682b
SM		 2640 u8 rqt_actual_size[0x10];
2641
b4ff3a36 2642 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2643
2644 struct mlx5_ifc_rq_num_bits rq_num[0];
2645};
2646
2647enum {
2648 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2649 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2650};
2651
2652enum {
2653 MLX5_RQC_STATE_RST = 0x0,
2654 MLX5_RQC_STATE_RDY = 0x1,
2655 MLX5_RQC_STATE_ERR = 0x3,
2656};
2657
2658struct mlx5_ifc_rqc_bits {
2659 u8 rlky[0x1];
03404e8a 2660 u8 delay_drop_en[0x1];
7d5e1423 2661 u8 scatter_fcs[0x1];
e281682b
SM		 2662 u8 vsd[0x1];
2663 u8 mem_rq_type[0x4];
2664 u8 state[0x4];
b4ff3a36 2665 u8 reserved_at_c[0x1];
e281682b 2666 u8 flush_in_error_en[0x1];
40817cdb
OG		 2667 u8 hairpin[0x1];
2668 u8 reserved_at_f[0x11];
e281682b 2669
b4ff3a36 2670 u8 reserved_at_20[0x8];
e281682b
SM		 2671 u8 user_index[0x18];
2672
b4ff3a36 2673 u8 reserved_at_40[0x8];
e281682b
SM		 2674 u8 cqn[0x18];
2675
2676 u8 counter_set_id[0x8];
b4ff3a36 2677 u8 reserved_at_68[0x18];
e281682b 2678
b4ff3a36 2679 u8 reserved_at_80[0x8];
e281682b
SM		 2680 u8 rmpn[0x18];
2681
40817cdb
OG		 2682 u8 reserved_at_a0[0x8];
2683 u8 hairpin_peer_sq[0x18];
2684
2685 u8 reserved_at_c0[0x10];
2686 u8 hairpin_peer_vhca[0x10];
2687
2688 u8 reserved_at_e0[0xa0];
e281682b
SM		 2689
2690 struct mlx5_ifc_wq_bits wq;
2691};
2692
2693enum {
2694 MLX5_RMPC_STATE_RDY = 0x1,
2695 MLX5_RMPC_STATE_ERR = 0x3,
2696};
2697
2698struct mlx5_ifc_rmpc_bits {
b4ff3a36 2699 u8 reserved_at_0[0x8];
e281682b 2700 u8 state[0x4];
b4ff3a36 2701 u8 reserved_at_c[0x14];
e281682b
SM		 2702
2703 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2704 u8 reserved_at_21[0x1f];
e281682b 2705
b4ff3a36 2706 u8 reserved_at_40[0x140];
e281682b
SM		 2707
2708 struct mlx5_ifc_wq_bits wq;
2709};
2710
e281682b 2711struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2712 u8 reserved_at_0[0x5];
2713 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2714 u8 reserved_at_8[0x15];
2715 u8 disable_mc_local_lb[0x1];
2716 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2717 u8 roce_en[0x1];
2718
d82b7318 2719 u8 arm_change_event[0x1];
b4ff3a36 2720 u8 reserved_at_21[0x1a];
d82b7318
SM		 2721 u8 event_on_mtu[0x1];
2722 u8 event_on_promisc_change[0x1];
2723 u8 event_on_vlan_change[0x1];
2724 u8 event_on_mc_address_change[0x1];
2725 u8 event_on_uc_address_change[0x1];
e281682b 2726
32f69e4b
DJ		 2727 u8 reserved_at_40[0xc];
2728
2729 u8 affiliation_criteria[0x4];
2730 u8 affiliated_vhca_id[0x10];
2731
2732 u8 reserved_at_60[0xd0];
d82b7318
SM		 2733
2734 u8 mtu[0x10];
2735
9efa7525
AS		 2736 u8 system_image_guid[0x40];
2737 u8 port_guid[0x40];
2738 u8 node_guid[0x40];
2739
b4ff3a36 2740 u8 reserved_at_200[0x140];
9efa7525 2741 u8 qkey_violation_counter[0x10];
b4ff3a36 2742 u8 reserved_at_350[0x430];
d82b7318
SM		 2743
2744 u8 promisc_uc[0x1];
2745 u8 promisc_mc[0x1];
2746 u8 promisc_all[0x1];
b4ff3a36 2747 u8 reserved_at_783[0x2];
e281682b 2748 u8 allowed_list_type[0x3];
b4ff3a36 2749 u8 reserved_at_788[0xc];
e281682b
SM		 2750 u8 allowed_list_size[0xc];
2751
2752 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2753
b4ff3a36 2754 u8 reserved_at_7e0[0x20];
e281682b
SM		 2755
2756 u8 current_uc_mac_address[0][0x40];
2757};
2758
2759enum {
2760 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2761 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2762 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2763 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
cdbd0d2b 2764 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 2765};
2766
2767struct mlx5_ifc_mkc_bits {
b4ff3a36 2768 u8 reserved_at_0[0x1];
e281682b 2769 u8 free[0x1];
cdbd0d2b
AL		 2770 u8 reserved_at_2[0x1];
2771 u8 access_mode_4_2[0x3];
2772 u8 reserved_at_6[0x7];
2773 u8 relaxed_ordering_write[0x1];
2774 u8 reserved_at_e[0x1];
e281682b
SM		 2775 u8 small_fence_on_rdma_read_response[0x1];
2776 u8 umr_en[0x1];
2777 u8 a[0x1];
2778 u8 rw[0x1];
2779 u8 rr[0x1];
2780 u8 lw[0x1];
2781 u8 lr[0x1];
cdbd0d2b 2782 u8 access_mode_1_0[0x2];
b4ff3a36 2783 u8 reserved_at_18[0x8];
e281682b
SM		 2784
2785 u8 qpn[0x18];
2786 u8 mkey_7_0[0x8];
2787
b4ff3a36 2788 u8 reserved_at_40[0x20];
e281682b
SM		 2789
2790 u8 length64[0x1];
2791 u8 bsf_en[0x1];
2792 u8 sync_umr[0x1];
b4ff3a36 2793 u8 reserved_at_63[0x2];
e281682b 2794 u8 expected_sigerr_count[0x1];
b4ff3a36 2795 u8 reserved_at_66[0x1];
e281682b
SM		 2796 u8 en_rinval[0x1];
2797 u8 pd[0x18];
2798
2799 u8 start_addr[0x40];
2800
2801 u8 len[0x40];
2802
2803 u8 bsf_octword_size[0x20];
2804
b4ff3a36 2805 u8 reserved_at_120[0x80];
e281682b
SM		 2806
2807 u8 translations_octword_size[0x20];
2808
b4ff3a36 2809 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2810 u8 log_page_size[0x5];
2811
b4ff3a36 2812 u8 reserved_at_1e0[0x20];
e281682b
SM		 2813};
2814
2815struct mlx5_ifc_pkey_bits {
b4ff3a36 2816 u8 reserved_at_0[0x10];
e281682b
SM		 2817 u8 pkey[0x10];
2818};
2819
2820struct mlx5_ifc_array128_auto_bits {
2821 u8 array128_auto[16][0x8];
2822};
2823
2824struct mlx5_ifc_hca_vport_context_bits {
2825 u8 field_select[0x20];
2826
b4ff3a36 2827 u8 reserved_at_20[0xe0];
e281682b
SM		 2828
2829 u8 sm_virt_aware[0x1];
2830 u8 has_smi[0x1];
2831 u8 has_raw[0x1];
2832 u8 grh_required[0x1];
b4ff3a36 2833 u8 reserved_at_104[0xc];
707c4602
MD		 2834 u8 port_physical_state[0x4];
2835 u8 vport_state_policy[0x4];
2836 u8 port_state[0x4];
e281682b
SM		 2837 u8 vport_state[0x4];
2838
b4ff3a36 2839 u8 reserved_at_120[0x20];
707c4602
MD		 2840
2841 u8 system_image_guid[0x40];
e281682b
SM		 2842
2843 u8 port_guid[0x40];
2844
2845 u8 node_guid[0x40];
2846
2847 u8 cap_mask1[0x20];
2848
2849 u8 cap_mask1_field_select[0x20];
2850
2851 u8 cap_mask2[0x20];
2852
2853 u8 cap_mask2_field_select[0x20];
2854
b4ff3a36 2855 u8 reserved_at_280[0x80];
e281682b
SM		 2856
2857 u8 lid[0x10];
b4ff3a36 2858 u8 reserved_at_310[0x4];
e281682b
SM		 2859 u8 init_type_reply[0x4];
2860 u8 lmc[0x3];
2861 u8 subnet_timeout[0x5];
2862
2863 u8 sm_lid[0x10];
2864 u8 sm_sl[0x4];
b4ff3a36 2865 u8 reserved_at_334[0xc];
e281682b
SM		 2866
2867 u8 qkey_violation_counter[0x10];
2868 u8 pkey_violation_counter[0x10];
2869
b4ff3a36 2870 u8 reserved_at_360[0xca0];
e281682b
SM		 2871};
2872
d6666753 2873struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2874 u8 reserved_at_0[0x3];
d6666753
SM		 2875 u8 vport_svlan_strip[0x1];
2876 u8 vport_cvlan_strip[0x1];
2877 u8 vport_svlan_insert[0x1];
2878 u8 vport_cvlan_insert[0x2];
b4ff3a36 2879 u8 reserved_at_8[0x18];
d6666753 2880
b4ff3a36 2881 u8 reserved_at_20[0x20];
d6666753
SM		 2882
2883 u8 svlan_cfi[0x1];
2884 u8 svlan_pcp[0x3];
2885 u8 svlan_id[0xc];
2886 u8 cvlan_cfi[0x1];
2887 u8 cvlan_pcp[0x3];
2888 u8 cvlan_id[0xc];
2889
b4ff3a36 2890 u8 reserved_at_60[0x7a0];
d6666753
SM		 2891};
2892
e281682b
SM		 2893enum {
2894 MLX5_EQC_STATUS_OK = 0x0,
2895 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2896};
2897
2898enum {
2899 MLX5_EQC_ST_ARMED = 0x9,
2900 MLX5_EQC_ST_FIRED = 0xa,
2901};
2902
2903struct mlx5_ifc_eqc_bits {
2904 u8 status[0x4];
b4ff3a36 2905 u8 reserved_at_4[0x9];
e281682b
SM		 2906 u8 ec[0x1];
2907 u8 oi[0x1];
b4ff3a36 2908 u8 reserved_at_f[0x5];
e281682b 2909 u8 st[0x4];
b4ff3a36 2910 u8 reserved_at_18[0x8];
e281682b 2911
b4ff3a36 2912 u8 reserved_at_20[0x20];
e281682b 2913
b4ff3a36 2914 u8 reserved_at_40[0x14];
e281682b 2915 u8 page_offset[0x6];
b4ff3a36 2916 u8 reserved_at_5a[0x6];
e281682b 2917
b4ff3a36 2918 u8 reserved_at_60[0x3];
e281682b
SM		 2919 u8 log_eq_size[0x5];
2920 u8 uar_page[0x18];
2921
b4ff3a36 2922 u8 reserved_at_80[0x20];
e281682b 2923
b4ff3a36 2924 u8 reserved_at_a0[0x18];
e281682b
SM		 2925 u8 intr[0x8];
2926
b4ff3a36 2927 u8 reserved_at_c0[0x3];
e281682b 2928 u8 log_page_size[0x5];
b4ff3a36 2929 u8 reserved_at_c8[0x18];
e281682b 2930
b4ff3a36 2931 u8 reserved_at_e0[0x60];
e281682b 2932
b4ff3a36 2933 u8 reserved_at_140[0x8];
e281682b
SM		 2934 u8 consumer_counter[0x18];
2935
b4ff3a36 2936 u8 reserved_at_160[0x8];
e281682b
SM		 2937 u8 producer_counter[0x18];
2938
b4ff3a36 2939 u8 reserved_at_180[0x80];
e281682b
SM		 2940};
2941
2942enum {
2943 MLX5_DCTC_STATE_ACTIVE = 0x0,
2944 MLX5_DCTC_STATE_DRAINING = 0x1,
2945 MLX5_DCTC_STATE_DRAINED = 0x2,
2946};
2947
2948enum {
2949 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2950 MLX5_DCTC_CS_RES_NA = 0x1,
2951 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2952};
2953
2954enum {
2955 MLX5_DCTC_MTU_256_BYTES = 0x1,
2956 MLX5_DCTC_MTU_512_BYTES = 0x2,
2957 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2958 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2959 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2960};
2961
2962struct mlx5_ifc_dctc_bits {
b4ff3a36 2963 u8 reserved_at_0[0x4];
e281682b 2964 u8 state[0x4];
b4ff3a36 2965 u8 reserved_at_8[0x18];
e281682b 2966
b4ff3a36 2967 u8 reserved_at_20[0x8];
e281682b
SM		 2968 u8 user_index[0x18];
2969
b4ff3a36 2970 u8 reserved_at_40[0x8];
e281682b
SM		 2971 u8 cqn[0x18];
2972
2973 u8 counter_set_id[0x8];
2974 u8 atomic_mode[0x4];
2975 u8 rre[0x1];
2976 u8 rwe[0x1];
2977 u8 rae[0x1];
2978 u8 atomic_like_write_en[0x1];
2979 u8 latency_sensitive[0x1];
2980 u8 rlky[0x1];
2981 u8 free_ar[0x1];
b4ff3a36 2982 u8 reserved_at_73[0xd];
e281682b 2983
b4ff3a36 2984 u8 reserved_at_80[0x8];
e281682b 2985 u8 cs_res[0x8];
b4ff3a36 2986 u8 reserved_at_90[0x3];
e281682b 2987 u8 min_rnr_nak[0x5];
b4ff3a36 2988 u8 reserved_at_98[0x8];
e281682b 2989
b4ff3a36 2990 u8 reserved_at_a0[0x8];
7486216b 2991 u8 srqn_xrqn[0x18];
e281682b 2992
b4ff3a36 2993 u8 reserved_at_c0[0x8];
e281682b
SM		 2994 u8 pd[0x18];
2995
2996 u8 tclass[0x8];
b4ff3a36 2997 u8 reserved_at_e8[0x4];
e281682b
SM		 2998 u8 flow_label[0x14];
2999
3000 u8 dc_access_key[0x40];
3001
b4ff3a36 3002 u8 reserved_at_140[0x5];
e281682b
SM		 3003 u8 mtu[0x3];
3004 u8 port[0x8];
3005 u8 pkey_index[0x10];
3006
b4ff3a36 3007 u8 reserved_at_160[0x8];
e281682b 3008 u8 my_addr_index[0x8];
b4ff3a36 3009 u8 reserved_at_170[0x8];
e281682b
SM		 3010 u8 hop_limit[0x8];
3011
3012 u8 dc_access_key_violation_count[0x20];
3013
b4ff3a36 3014 u8 reserved_at_1a0[0x14];
e281682b
SM		 3015 u8 dei_cfi[0x1];
3016 u8 eth_prio[0x3];
3017 u8 ecn[0x2];
3018 u8 dscp[0x6];
3019
b4ff3a36 3020 u8 reserved_at_1c0[0x40];
e281682b
SM		 3021};
3022
3023enum {
3024 MLX5_CQC_STATUS_OK = 0x0,
3025 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3026 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3027};
3028
3029enum {
3030 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3031 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3032};
3033
3034enum {
3035 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3036 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3037 MLX5_CQC_ST_FIRED = 0xa,
3038};
3039
7d5e1423
SM		 3040enum {
3041 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3042 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3043 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3044};
3045
e281682b
SM		 3046struct mlx5_ifc_cqc_bits {
3047 u8 status[0x4];
b4ff3a36 3048 u8 reserved_at_4[0x4];
e281682b
SM		 3049 u8 cqe_sz[0x3];
3050 u8 cc[0x1];
b4ff3a36 3051 u8 reserved_at_c[0x1];
e281682b
SM		 3052 u8 scqe_break_moderation_en[0x1];
3053 u8 oi[0x1];
7d5e1423
SM		 3054 u8 cq_period_mode[0x2];
3055 u8 cqe_comp_en[0x1];
e281682b
SM		 3056 u8 mini_cqe_res_format[0x2];
3057 u8 st[0x4];
b4ff3a36 3058 u8 reserved_at_18[0x8];
e281682b 3059
b4ff3a36 3060 u8 reserved_at_20[0x20];
e281682b 3061
b4ff3a36 3062 u8 reserved_at_40[0x14];
e281682b 3063 u8 page_offset[0x6];
b4ff3a36 3064 u8 reserved_at_5a[0x6];
e281682b 3065
b4ff3a36 3066 u8 reserved_at_60[0x3];
e281682b
SM		 3067 u8 log_cq_size[0x5];
3068 u8 uar_page[0x18];
3069
b4ff3a36 3070 u8 reserved_at_80[0x4];
e281682b
SM		 3071 u8 cq_period[0xc];
3072 u8 cq_max_count[0x10];
3073
b4ff3a36 3074 u8 reserved_at_a0[0x18];
e281682b
SM		 3075 u8 c_eqn[0x8];
3076
b4ff3a36 3077 u8 reserved_at_c0[0x3];
e281682b 3078 u8 log_page_size[0x5];
b4ff3a36 3079 u8 reserved_at_c8[0x18];
e281682b 3080
b4ff3a36 3081 u8 reserved_at_e0[0x20];
e281682b 3082
b4ff3a36 3083 u8 reserved_at_100[0x8];
e281682b
SM		 3084 u8 last_notified_index[0x18];
3085
b4ff3a36 3086 u8 reserved_at_120[0x8];
e281682b
SM		 3087 u8 last_solicit_index[0x18];
3088
b4ff3a36 3089 u8 reserved_at_140[0x8];
e281682b
SM		 3090 u8 consumer_counter[0x18];
3091
b4ff3a36 3092 u8 reserved_at_160[0x8];
e281682b
SM		 3093 u8 producer_counter[0x18];
3094
b4ff3a36 3095 u8 reserved_at_180[0x40];
e281682b
SM		 3096
3097 u8 dbr_addr[0x40];
3098};
3099
3100union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3101 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3102 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3103 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3104 u8 reserved_at_0[0x800];
e281682b
SM		 3105};
3106
3107struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3108 u8 reserved_at_0[0xc0];
e281682b 3109
b4ff3a36 3110 u8 reserved_at_c0[0x8];
211e6c80
MD		 3111 u8 ieee_vendor_id[0x18];
3112
b4ff3a36 3113 u8 reserved_at_e0[0x10];
e281682b
SM		 3114 u8 vsd_vendor_id[0x10];
3115
3116 u8 vsd[208][0x8];
3117
3118 u8 vsd_contd_psid[16][0x8];
3119};
3120
7486216b
SM		 3121enum {
3122 MLX5_XRQC_STATE_GOOD = 0x0,
3123 MLX5_XRQC_STATE_ERROR = 0x1,
3124};
3125
3126enum {
3127 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3128 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3129};
3130
3131enum {
3132 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3133};
3134
3135struct mlx5_ifc_tag_matching_topology_context_bits {
3136 u8 log_matching_list_sz[0x4];
3137 u8 reserved_at_4[0xc];
3138 u8 append_next_index[0x10];
3139
3140 u8 sw_phase_cnt[0x10];
3141 u8 hw_phase_cnt[0x10];
3142
3143 u8 reserved_at_40[0x40];
3144};
3145
3146struct mlx5_ifc_xrqc_bits {
3147 u8 state[0x4];
3148 u8 rlkey[0x1];
3149 u8 reserved_at_5[0xf];
3150 u8 topology[0x4];
3151 u8 reserved_at_18[0x4];
3152 u8 offload[0x4];
3153
3154 u8 reserved_at_20[0x8];
3155 u8 user_index[0x18];
3156
3157 u8 reserved_at_40[0x8];
3158 u8 cqn[0x18];
3159
3160 u8 reserved_at_60[0xa0];
3161
3162 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3163
6e44636a 3164 u8 reserved_at_180[0x280];
7486216b
SM		 3165
3166 struct mlx5_ifc_wq_bits wq;
3167};
3168
e281682b
SM		 3169union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3170 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3171 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3172 u8 reserved_at_0[0x20];
e281682b
SM		 3173};
3174
3175union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3176 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3177 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3178 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3179 u8 reserved_at_0[0x20];
e281682b
SM		 3180};
3181
3182union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3183 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3184 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3185 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3186 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3187 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3188 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3189 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3190 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3191 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3192 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3193 u8 reserved_at_0[0x7c0];
e281682b
SM		 3194};
3195
8ed1a630
GP		 3196union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3197 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3198 u8 reserved_at_0[0x7c0];
3199};
3200
e281682b
SM		 3201union mlx5_ifc_event_auto_bits {
3202 struct mlx5_ifc_comp_event_bits comp_event;
3203 struct mlx5_ifc_dct_events_bits dct_events;
3204 struct mlx5_ifc_qp_events_bits qp_events;
3205 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3206 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3207 struct mlx5_ifc_cq_error_bits cq_error;
3208 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3209 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3210 struct mlx5_ifc_gpio_event_bits gpio_event;
3211 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3212 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3213 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3214 u8 reserved_at_0[0xe0];
e281682b
SM		 3215};
3216
3217struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3218 u8 reserved_at_0[0x100];
e281682b
SM		 3219
3220 u8 assert_existptr[0x20];
3221
3222 u8 assert_callra[0x20];
3223
b4ff3a36 3224 u8 reserved_at_140[0x40];
e281682b
SM		 3225
3226 u8 fw_version[0x20];
3227
3228 u8 hw_id[0x20];
3229
b4ff3a36 3230 u8 reserved_at_1c0[0x20];
e281682b
SM		 3231
3232 u8 irisc_index[0x8];
3233 u8 synd[0x8];
3234 u8 ext_synd[0x10];
3235};
3236
3237struct mlx5_ifc_register_loopback_control_bits {
3238 u8 no_lb[0x1];
b4ff3a36 3239 u8 reserved_at_1[0x7];
e281682b 3240 u8 port[0x8];
b4ff3a36 3241 u8 reserved_at_10[0x10];
e281682b 3242
b4ff3a36 3243 u8 reserved_at_20[0x60];
e281682b
SM		 3244};
3245
813f8540
MHY		 3246struct mlx5_ifc_vport_tc_element_bits {
3247 u8 traffic_class[0x4];
3248 u8 reserved_at_4[0xc];
3249 u8 vport_number[0x10];
3250};
3251
3252struct mlx5_ifc_vport_element_bits {
3253 u8 reserved_at_0[0x10];
3254 u8 vport_number[0x10];
3255};
3256
3257enum {
3258 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3259 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3260 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3261};
3262
3263struct mlx5_ifc_tsar_element_bits {
3264 u8 reserved_at_0[0x8];
3265 u8 tsar_type[0x8];
3266 u8 reserved_at_10[0x10];
3267};
3268
8812c24d
MD		 3269enum {
3270 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3271 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3272};
3273
e281682b
SM		 3274struct mlx5_ifc_teardown_hca_out_bits {
3275 u8 status[0x8];
b4ff3a36 3276 u8 reserved_at_8[0x18];
e281682b
SM		 3277
3278 u8 syndrome[0x20];
3279
8812c24d
MD		 3280 u8 reserved_at_40[0x3f];
3281
3282 u8 force_state[0x1];
e281682b
SM		 3283};
3284
3285enum {
3286 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3287 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3288};
3289
3290struct mlx5_ifc_teardown_hca_in_bits {
3291 u8 opcode[0x10];
b4ff3a36 3292 u8 reserved_at_10[0x10];
e281682b 3293
b4ff3a36 3294 u8 reserved_at_20[0x10];
e281682b
SM		 3295 u8 op_mod[0x10];
3296
b4ff3a36 3297 u8 reserved_at_40[0x10];
e281682b
SM		 3298 u8 profile[0x10];
3299
b4ff3a36 3300 u8 reserved_at_60[0x20];
e281682b
SM		 3301};
3302
3303struct mlx5_ifc_sqerr2rts_qp_out_bits {
3304 u8 status[0x8];
b4ff3a36 3305 u8 reserved_at_8[0x18];
e281682b
SM		 3306
3307 u8 syndrome[0x20];
3308
b4ff3a36 3309 u8 reserved_at_40[0x40];
e281682b
SM		 3310};
3311
3312struct mlx5_ifc_sqerr2rts_qp_in_bits {
3313 u8 opcode[0x10];
b4ff3a36 3314 u8 reserved_at_10[0x10];
e281682b 3315
b4ff3a36 3316 u8 reserved_at_20[0x10];
e281682b
SM		 3317 u8 op_mod[0x10];
3318
b4ff3a36 3319 u8 reserved_at_40[0x8];
e281682b
SM		 3320 u8 qpn[0x18];
3321
b4ff3a36 3322 u8 reserved_at_60[0x20];
e281682b
SM		 3323
3324 u8 opt_param_mask[0x20];
3325
b4ff3a36 3326 u8 reserved_at_a0[0x20];
e281682b
SM		 3327
3328 struct mlx5_ifc_qpc_bits qpc;
3329
b4ff3a36 3330 u8 reserved_at_800[0x80];
e281682b
SM		 3331};
3332
3333struct mlx5_ifc_sqd2rts_qp_out_bits {
3334 u8 status[0x8];
b4ff3a36 3335 u8 reserved_at_8[0x18];
e281682b
SM		 3336
3337 u8 syndrome[0x20];
3338
b4ff3a36 3339 u8 reserved_at_40[0x40];
e281682b
SM		 3340};
3341
3342struct mlx5_ifc_sqd2rts_qp_in_bits {
3343 u8 opcode[0x10];
b4ff3a36 3344 u8 reserved_at_10[0x10];
e281682b 3345
b4ff3a36 3346 u8 reserved_at_20[0x10];
e281682b
SM		 3347 u8 op_mod[0x10];
3348
b4ff3a36 3349 u8 reserved_at_40[0x8];
e281682b
SM		 3350 u8 qpn[0x18];
3351
b4ff3a36 3352 u8 reserved_at_60[0x20];
e281682b
SM		 3353
3354 u8 opt_param_mask[0x20];
3355
b4ff3a36 3356 u8 reserved_at_a0[0x20];
e281682b
SM		 3357
3358 struct mlx5_ifc_qpc_bits qpc;
3359
b4ff3a36 3360 u8 reserved_at_800[0x80];
e281682b
SM		 3361};
3362
3363struct mlx5_ifc_set_roce_address_out_bits {
3364 u8 status[0x8];
b4ff3a36 3365 u8 reserved_at_8[0x18];
e281682b
SM		 3366
3367 u8 syndrome[0x20];
3368
b4ff3a36 3369 u8 reserved_at_40[0x40];
e281682b
SM		 3370};
3371
3372struct mlx5_ifc_set_roce_address_in_bits {
3373 u8 opcode[0x10];
b4ff3a36 3374 u8 reserved_at_10[0x10];
e281682b 3375
b4ff3a36 3376 u8 reserved_at_20[0x10];
e281682b
SM		 3377 u8 op_mod[0x10];
3378
3379 u8 roce_address_index[0x10];
32f69e4b
DJ		 3380 u8 reserved_at_50[0xc];
3381 u8 vhca_port_num[0x4];
e281682b 3382
b4ff3a36 3383 u8 reserved_at_60[0x20];
e281682b
SM		 3384
3385 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3386};
3387
3388struct mlx5_ifc_set_mad_demux_out_bits {
3389 u8 status[0x8];
b4ff3a36 3390 u8 reserved_at_8[0x18];
e281682b
SM		 3391
3392 u8 syndrome[0x20];
3393
b4ff3a36 3394 u8 reserved_at_40[0x40];
e281682b
SM		 3395};
3396
3397enum {
3398 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3399 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3400};
3401
3402struct mlx5_ifc_set_mad_demux_in_bits {
3403 u8 opcode[0x10];
b4ff3a36 3404 u8 reserved_at_10[0x10];
e281682b 3405
b4ff3a36 3406 u8 reserved_at_20[0x10];
e281682b
SM		 3407 u8 op_mod[0x10];
3408
b4ff3a36 3409 u8 reserved_at_40[0x20];
e281682b 3410
b4ff3a36 3411 u8 reserved_at_60[0x6];
e281682b 3412 u8 demux_mode[0x2];
b4ff3a36 3413 u8 reserved_at_68[0x18];
e281682b
SM		 3414};
3415
3416struct mlx5_ifc_set_l2_table_entry_out_bits {
3417 u8 status[0x8];
b4ff3a36 3418 u8 reserved_at_8[0x18];
e281682b
SM		 3419
3420 u8 syndrome[0x20];
3421
b4ff3a36 3422 u8 reserved_at_40[0x40];
e281682b
SM		 3423};
3424
3425struct mlx5_ifc_set_l2_table_entry_in_bits {
3426 u8 opcode[0x10];
b4ff3a36 3427 u8 reserved_at_10[0x10];
e281682b 3428
b4ff3a36 3429 u8 reserved_at_20[0x10];
e281682b
SM		 3430 u8 op_mod[0x10];
3431
b4ff3a36 3432 u8 reserved_at_40[0x60];
e281682b 3433
b4ff3a36 3434 u8 reserved_at_a0[0x8];
e281682b
SM		 3435 u8 table_index[0x18];
3436
b4ff3a36 3437 u8 reserved_at_c0[0x20];
e281682b 3438
b4ff3a36 3439 u8 reserved_at_e0[0x13];
e281682b
SM		 3440 u8 vlan_valid[0x1];
3441 u8 vlan[0xc];
3442
3443 struct mlx5_ifc_mac_address_layout_bits mac_address;
3444
b4ff3a36 3445 u8 reserved_at_140[0xc0];
e281682b
SM		 3446};
3447
3448struct mlx5_ifc_set_issi_out_bits {
3449 u8 status[0x8];
b4ff3a36 3450 u8 reserved_at_8[0x18];
e281682b
SM		 3451
3452 u8 syndrome[0x20];
3453
b4ff3a36 3454 u8 reserved_at_40[0x40];
e281682b
SM		 3455};
3456
3457struct mlx5_ifc_set_issi_in_bits {
3458 u8 opcode[0x10];
b4ff3a36 3459 u8 reserved_at_10[0x10];
e281682b 3460
b4ff3a36 3461 u8 reserved_at_20[0x10];
e281682b
SM		 3462 u8 op_mod[0x10];
3463
b4ff3a36 3464 u8 reserved_at_40[0x10];
e281682b
SM		 3465 u8 current_issi[0x10];
3466
b4ff3a36 3467 u8 reserved_at_60[0x20];
e281682b
SM		 3468};
3469
3470struct mlx5_ifc_set_hca_cap_out_bits {
3471 u8 status[0x8];
b4ff3a36 3472 u8 reserved_at_8[0x18];
e281682b
SM		 3473
3474 u8 syndrome[0x20];
3475
b4ff3a36 3476 u8 reserved_at_40[0x40];
e281682b
SM		 3477};
3478
3479struct mlx5_ifc_set_hca_cap_in_bits {
3480 u8 opcode[0x10];
b4ff3a36 3481 u8 reserved_at_10[0x10];
e281682b 3482
b4ff3a36 3483 u8 reserved_at_20[0x10];
e281682b
SM		 3484 u8 op_mod[0x10];
3485
b4ff3a36 3486 u8 reserved_at_40[0x40];
e281682b
SM		 3487
3488 union mlx5_ifc_hca_cap_union_bits capability;
3489};
3490
26a81453
MG		 3491enum {
3492 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3493 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3494 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3495 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3496};
3497
e281682b
SM		 3498struct mlx5_ifc_set_fte_out_bits {
3499 u8 status[0x8];
b4ff3a36 3500 u8 reserved_at_8[0x18];
e281682b
SM		 3501
3502 u8 syndrome[0x20];
3503
b4ff3a36 3504 u8 reserved_at_40[0x40];
e281682b
SM		 3505};
3506
3507struct mlx5_ifc_set_fte_in_bits {
3508 u8 opcode[0x10];
b4ff3a36 3509 u8 reserved_at_10[0x10];
e281682b 3510
b4ff3a36 3511 u8 reserved_at_20[0x10];
e281682b
SM		 3512 u8 op_mod[0x10];
3513
7d5e1423
SM		 3514 u8 other_vport[0x1];
3515 u8 reserved_at_41[0xf];
3516 u8 vport_number[0x10];
3517
3518 u8 reserved_at_60[0x20];
e281682b
SM		 3519
3520 u8 table_type[0x8];
b4ff3a36 3521 u8 reserved_at_88[0x18];
e281682b 3522
b4ff3a36 3523 u8 reserved_at_a0[0x8];
e281682b
SM		 3524 u8 table_id[0x18];
3525
b4ff3a36 3526 u8 reserved_at_c0[0x18];
26a81453
MG		 3527 u8 modify_enable_mask[0x8];
3528
b4ff3a36 3529 u8 reserved_at_e0[0x20];
e281682b
SM		 3530
3531 u8 flow_index[0x20];
3532
b4ff3a36 3533 u8 reserved_at_120[0xe0];
e281682b
SM		 3534
3535 struct mlx5_ifc_flow_context_bits flow_context;
3536};
3537
3538struct mlx5_ifc_rts2rts_qp_out_bits {
3539 u8 status[0x8];
b4ff3a36 3540 u8 reserved_at_8[0x18];
e281682b
SM		 3541
3542 u8 syndrome[0x20];
3543
b4ff3a36 3544 u8 reserved_at_40[0x40];
e281682b
SM		 3545};
3546
3547struct mlx5_ifc_rts2rts_qp_in_bits {
3548 u8 opcode[0x10];
b4ff3a36 3549 u8 reserved_at_10[0x10];
e281682b 3550
b4ff3a36 3551 u8 reserved_at_20[0x10];
e281682b
SM		 3552 u8 op_mod[0x10];
3553
b4ff3a36 3554 u8 reserved_at_40[0x8];
e281682b
SM		 3555 u8 qpn[0x18];
3556
b4ff3a36 3557 u8 reserved_at_60[0x20];
e281682b
SM		 3558
3559 u8 opt_param_mask[0x20];
3560
b4ff3a36 3561 u8 reserved_at_a0[0x20];
e281682b
SM		 3562
3563 struct mlx5_ifc_qpc_bits qpc;
3564
b4ff3a36 3565 u8 reserved_at_800[0x80];
e281682b
SM		 3566};
3567
3568struct mlx5_ifc_rtr2rts_qp_out_bits {
3569 u8 status[0x8];
b4ff3a36 3570 u8 reserved_at_8[0x18];
e281682b
SM		 3571
3572 u8 syndrome[0x20];
3573
b4ff3a36 3574 u8 reserved_at_40[0x40];
e281682b
SM		 3575};
3576
3577struct mlx5_ifc_rtr2rts_qp_in_bits {
3578 u8 opcode[0x10];
b4ff3a36 3579 u8 reserved_at_10[0x10];
e281682b 3580
b4ff3a36 3581 u8 reserved_at_20[0x10];
e281682b
SM		 3582 u8 op_mod[0x10];
3583
b4ff3a36 3584 u8 reserved_at_40[0x8];
e281682b
SM		 3585 u8 qpn[0x18];
3586
b4ff3a36 3587 u8 reserved_at_60[0x20];
e281682b
SM		 3588
3589 u8 opt_param_mask[0x20];
3590
b4ff3a36 3591 u8 reserved_at_a0[0x20];
e281682b
SM		 3592
3593 struct mlx5_ifc_qpc_bits qpc;
3594
b4ff3a36 3595 u8 reserved_at_800[0x80];
e281682b
SM		 3596};
3597
3598struct mlx5_ifc_rst2init_qp_out_bits {
3599 u8 status[0x8];
b4ff3a36 3600 u8 reserved_at_8[0x18];
e281682b
SM		 3601
3602 u8 syndrome[0x20];
3603
b4ff3a36 3604 u8 reserved_at_40[0x40];
e281682b
SM		 3605};
3606
3607struct mlx5_ifc_rst2init_qp_in_bits {
3608 u8 opcode[0x10];
b4ff3a36 3609 u8 reserved_at_10[0x10];
e281682b 3610
b4ff3a36 3611 u8 reserved_at_20[0x10];
e281682b
SM		 3612 u8 op_mod[0x10];
3613
b4ff3a36 3614 u8 reserved_at_40[0x8];
e281682b
SM		 3615 u8 qpn[0x18];
3616
b4ff3a36 3617 u8 reserved_at_60[0x20];
e281682b
SM		 3618
3619 u8 opt_param_mask[0x20];
3620
b4ff3a36 3621 u8 reserved_at_a0[0x20];
e281682b
SM		 3622
3623 struct mlx5_ifc_qpc_bits qpc;
3624
b4ff3a36 3625 u8 reserved_at_800[0x80];
e281682b
SM		 3626};
3627
7486216b
SM		 3628struct mlx5_ifc_query_xrq_out_bits {
3629 u8 status[0x8];
3630 u8 reserved_at_8[0x18];
3631
3632 u8 syndrome[0x20];
3633
3634 u8 reserved_at_40[0x40];
3635
3636 struct mlx5_ifc_xrqc_bits xrq_context;
3637};
3638
3639struct mlx5_ifc_query_xrq_in_bits {
3640 u8 opcode[0x10];
3641 u8 reserved_at_10[0x10];
3642
3643 u8 reserved_at_20[0x10];
3644 u8 op_mod[0x10];
3645
3646 u8 reserved_at_40[0x8];
3647 u8 xrqn[0x18];
3648
3649 u8 reserved_at_60[0x20];
3650};
3651
e281682b
SM		 3652struct mlx5_ifc_query_xrc_srq_out_bits {
3653 u8 status[0x8];
b4ff3a36 3654 u8 reserved_at_8[0x18];
e281682b
SM		 3655
3656 u8 syndrome[0x20];
3657
b4ff3a36 3658 u8 reserved_at_40[0x40];
e281682b
SM		 3659
3660 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3661
b4ff3a36 3662 u8 reserved_at_280[0x600];
e281682b
SM		 3663
3664 u8 pas[0][0x40];
3665};
3666
3667struct mlx5_ifc_query_xrc_srq_in_bits {
3668 u8 opcode[0x10];
b4ff3a36 3669 u8 reserved_at_10[0x10];
e281682b 3670
b4ff3a36 3671 u8 reserved_at_20[0x10];
e281682b
SM		 3672 u8 op_mod[0x10];
3673
b4ff3a36 3674 u8 reserved_at_40[0x8];
e281682b
SM		 3675 u8 xrc_srqn[0x18];
3676
b4ff3a36 3677 u8 reserved_at_60[0x20];
e281682b
SM		 3678};
3679
3680enum {
3681 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3682 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3683};
3684
3685struct mlx5_ifc_query_vport_state_out_bits {
3686 u8 status[0x8];
b4ff3a36 3687 u8 reserved_at_8[0x18];
e281682b
SM		 3688
3689 u8 syndrome[0x20];
3690
b4ff3a36 3691 u8 reserved_at_40[0x20];
e281682b 3692
b4ff3a36 3693 u8 reserved_at_60[0x18];
e281682b
SM		 3694 u8 admin_state[0x4];
3695 u8 state[0x4];
3696};
3697
3698enum {
3699 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3700 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3701};
3702
3703struct mlx5_ifc_query_vport_state_in_bits {
3704 u8 opcode[0x10];
b4ff3a36 3705 u8 reserved_at_10[0x10];
e281682b 3706
b4ff3a36 3707 u8 reserved_at_20[0x10];
e281682b
SM		 3708 u8 op_mod[0x10];
3709
3710 u8 other_vport[0x1];
b4ff3a36 3711 u8 reserved_at_41[0xf];
e281682b
SM		 3712 u8 vport_number[0x10];
3713
b4ff3a36 3714 u8 reserved_at_60[0x20];
e281682b
SM		 3715};
3716
61c5b5c9
MS		 3717struct mlx5_ifc_query_vnic_env_out_bits {
3718 u8 status[0x8];
3719 u8 reserved_at_8[0x18];
3720
3721 u8 syndrome[0x20];
3722
3723 u8 reserved_at_40[0x40];
3724
3725 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3726};
3727
3728enum {
3729 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3730};
3731
3732struct mlx5_ifc_query_vnic_env_in_bits {
3733 u8 opcode[0x10];
3734 u8 reserved_at_10[0x10];
3735
3736 u8 reserved_at_20[0x10];
3737 u8 op_mod[0x10];
3738
3739 u8 other_vport[0x1];
3740 u8 reserved_at_41[0xf];
3741 u8 vport_number[0x10];
3742
3743 u8 reserved_at_60[0x20];
3744};
3745
e281682b
SM		 3746struct mlx5_ifc_query_vport_counter_out_bits {
3747 u8 status[0x8];
b4ff3a36 3748 u8 reserved_at_8[0x18];
e281682b
SM		 3749
3750 u8 syndrome[0x20];
3751
b4ff3a36 3752 u8 reserved_at_40[0x40];
e281682b
SM		 3753
3754 struct mlx5_ifc_traffic_counter_bits received_errors;
3755
3756 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3757
3758 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3759
3760 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3761
3762 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3763
3764 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3765
3766 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3767
3768 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3769
3770 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3771
3772 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3773
3774 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3775
3776 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3777
b4ff3a36 3778 u8 reserved_at_680[0xa00];
e281682b
SM		 3779};
3780
3781enum {
3782 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3783};
3784
3785struct mlx5_ifc_query_vport_counter_in_bits {
3786 u8 opcode[0x10];
b4ff3a36 3787 u8 reserved_at_10[0x10];
e281682b 3788
b4ff3a36 3789 u8 reserved_at_20[0x10];
e281682b
SM		 3790 u8 op_mod[0x10];
3791
3792 u8 other_vport[0x1];
b54ba277
MY		 3793 u8 reserved_at_41[0xb];
3794 u8 port_num[0x4];
e281682b
SM		 3795 u8 vport_number[0x10];
3796
b4ff3a36 3797 u8 reserved_at_60[0x60];
e281682b
SM		 3798
3799 u8 clear[0x1];
b4ff3a36 3800 u8 reserved_at_c1[0x1f];
e281682b 3801
b4ff3a36 3802 u8 reserved_at_e0[0x20];
e281682b
SM		 3803};
3804
3805struct mlx5_ifc_query_tis_out_bits {
3806 u8 status[0x8];
b4ff3a36 3807 u8 reserved_at_8[0x18];
e281682b
SM		 3808
3809 u8 syndrome[0x20];
3810
b4ff3a36 3811 u8 reserved_at_40[0x40];
e281682b
SM		 3812
3813 struct mlx5_ifc_tisc_bits tis_context;
3814};
3815
3816struct mlx5_ifc_query_tis_in_bits {
3817 u8 opcode[0x10];
b4ff3a36 3818 u8 reserved_at_10[0x10];
e281682b 3819
b4ff3a36 3820 u8 reserved_at_20[0x10];
e281682b
SM		 3821 u8 op_mod[0x10];
3822
b4ff3a36 3823 u8 reserved_at_40[0x8];
e281682b
SM		 3824 u8 tisn[0x18];
3825
b4ff3a36 3826 u8 reserved_at_60[0x20];
e281682b
SM		 3827};
3828
3829struct mlx5_ifc_query_tir_out_bits {
3830 u8 status[0x8];
b4ff3a36 3831 u8 reserved_at_8[0x18];
e281682b
SM		 3832
3833 u8 syndrome[0x20];
3834
b4ff3a36 3835 u8 reserved_at_40[0xc0];
e281682b
SM		 3836
3837 struct mlx5_ifc_tirc_bits tir_context;
3838};
3839
3840struct mlx5_ifc_query_tir_in_bits {
3841 u8 opcode[0x10];
b4ff3a36 3842 u8 reserved_at_10[0x10];
e281682b 3843
b4ff3a36 3844 u8 reserved_at_20[0x10];
e281682b
SM		 3845 u8 op_mod[0x10];
3846
b4ff3a36 3847 u8 reserved_at_40[0x8];
e281682b
SM		 3848 u8 tirn[0x18];
3849
b4ff3a36 3850 u8 reserved_at_60[0x20];
e281682b
SM		 3851};
3852
3853struct mlx5_ifc_query_srq_out_bits {
3854 u8 status[0x8];
b4ff3a36 3855 u8 reserved_at_8[0x18];
e281682b
SM		 3856
3857 u8 syndrome[0x20];
3858
b4ff3a36 3859 u8 reserved_at_40[0x40];
e281682b
SM		 3860
3861 struct mlx5_ifc_srqc_bits srq_context_entry;
3862
b4ff3a36 3863 u8 reserved_at_280[0x600];
e281682b
SM		 3864
3865 u8 pas[0][0x40];
3866};
3867
3868struct mlx5_ifc_query_srq_in_bits {
3869 u8 opcode[0x10];
b4ff3a36 3870 u8 reserved_at_10[0x10];
e281682b 3871
b4ff3a36 3872 u8 reserved_at_20[0x10];
e281682b
SM		 3873 u8 op_mod[0x10];
3874
b4ff3a36 3875 u8 reserved_at_40[0x8];
e281682b
SM		 3876 u8 srqn[0x18];
3877
b4ff3a36 3878 u8 reserved_at_60[0x20];
e281682b
SM		 3879};
3880
3881struct mlx5_ifc_query_sq_out_bits {
3882 u8 status[0x8];
b4ff3a36 3883 u8 reserved_at_8[0x18];
e281682b
SM		 3884
3885 u8 syndrome[0x20];
3886
b4ff3a36 3887 u8 reserved_at_40[0xc0];
e281682b
SM		 3888
3889 struct mlx5_ifc_sqc_bits sq_context;
3890};
3891
3892struct mlx5_ifc_query_sq_in_bits {
3893 u8 opcode[0x10];
b4ff3a36 3894 u8 reserved_at_10[0x10];
e281682b 3895
b4ff3a36 3896 u8 reserved_at_20[0x10];
e281682b
SM		 3897 u8 op_mod[0x10];
3898
b4ff3a36 3899 u8 reserved_at_40[0x8];
e281682b
SM		 3900 u8 sqn[0x18];
3901
b4ff3a36 3902 u8 reserved_at_60[0x20];
e281682b
SM		 3903};
3904
3905struct mlx5_ifc_query_special_contexts_out_bits {
3906 u8 status[0x8];
b4ff3a36 3907 u8 reserved_at_8[0x18];
e281682b
SM		 3908
3909 u8 syndrome[0x20];
3910
ec22eb53 3911 u8 dump_fill_mkey[0x20];
e281682b
SM		 3912
3913 u8 resd_lkey[0x20];
bcda1aca
AK		 3914
3915 u8 null_mkey[0x20];
3916
3917 u8 reserved_at_a0[0x60];
e281682b
SM		 3918};
3919
3920struct mlx5_ifc_query_special_contexts_in_bits {
3921 u8 opcode[0x10];
b4ff3a36 3922 u8 reserved_at_10[0x10];
e281682b 3923
b4ff3a36 3924 u8 reserved_at_20[0x10];
e281682b
SM		 3925 u8 op_mod[0x10];
3926
b4ff3a36 3927 u8 reserved_at_40[0x40];
e281682b
SM		 3928};
3929
813f8540
MHY		 3930struct mlx5_ifc_query_scheduling_element_out_bits {
3931 u8 opcode[0x10];
3932 u8 reserved_at_10[0x10];
3933
3934 u8 reserved_at_20[0x10];
3935 u8 op_mod[0x10];
3936
3937 u8 reserved_at_40[0xc0];
3938
3939 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3940
3941 u8 reserved_at_300[0x100];
3942};
3943
3944enum {
3945 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3946};
3947
3948struct mlx5_ifc_query_scheduling_element_in_bits {
3949 u8 opcode[0x10];
3950 u8 reserved_at_10[0x10];
3951
3952 u8 reserved_at_20[0x10];
3953 u8 op_mod[0x10];
3954
3955 u8 scheduling_hierarchy[0x8];
3956 u8 reserved_at_48[0x18];
3957
3958 u8 scheduling_element_id[0x20];
3959
3960 u8 reserved_at_80[0x180];
3961};
3962
e281682b
SM		 3963struct mlx5_ifc_query_rqt_out_bits {
3964 u8 status[0x8];
b4ff3a36 3965 u8 reserved_at_8[0x18];
e281682b
SM		 3966
3967 u8 syndrome[0x20];
3968
b4ff3a36 3969 u8 reserved_at_40[0xc0];
e281682b
SM		 3970
3971 struct mlx5_ifc_rqtc_bits rqt_context;
3972};
3973
3974struct mlx5_ifc_query_rqt_in_bits {
3975 u8 opcode[0x10];
b4ff3a36 3976 u8 reserved_at_10[0x10];
e281682b 3977
b4ff3a36 3978 u8 reserved_at_20[0x10];
e281682b
SM		 3979 u8 op_mod[0x10];
3980
b4ff3a36 3981 u8 reserved_at_40[0x8];
e281682b
SM		 3982 u8 rqtn[0x18];
3983
b4ff3a36 3984 u8 reserved_at_60[0x20];
e281682b
SM		 3985};
3986
3987struct mlx5_ifc_query_rq_out_bits {
3988 u8 status[0x8];
b4ff3a36 3989 u8 reserved_at_8[0x18];
e281682b
SM		 3990
3991 u8 syndrome[0x20];
3992
b4ff3a36 3993 u8 reserved_at_40[0xc0];
e281682b
SM		 3994
3995 struct mlx5_ifc_rqc_bits rq_context;
3996};
3997
3998struct mlx5_ifc_query_rq_in_bits {
3999 u8 opcode[0x10];
b4ff3a36 4000 u8 reserved_at_10[0x10];
e281682b 4001
b4ff3a36 4002 u8 reserved_at_20[0x10];
e281682b
SM		 4003 u8 op_mod[0x10];
4004
b4ff3a36 4005 u8 reserved_at_40[0x8];
e281682b
SM		 4006 u8 rqn[0x18];
4007
b4ff3a36 4008 u8 reserved_at_60[0x20];
e281682b
SM		 4009};
4010
4011struct mlx5_ifc_query_roce_address_out_bits {
4012 u8 status[0x8];
b4ff3a36 4013 u8 reserved_at_8[0x18];
e281682b
SM		 4014
4015 u8 syndrome[0x20];
4016
b4ff3a36 4017 u8 reserved_at_40[0x40];
e281682b
SM		 4018
4019 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4020};
4021
4022struct mlx5_ifc_query_roce_address_in_bits {
4023 u8 opcode[0x10];
b4ff3a36 4024 u8 reserved_at_10[0x10];
e281682b 4025
b4ff3a36 4026 u8 reserved_at_20[0x10];
e281682b
SM		 4027 u8 op_mod[0x10];
4028
4029 u8 roce_address_index[0x10];
32f69e4b
DJ		 4030 u8 reserved_at_50[0xc];
4031 u8 vhca_port_num[0x4];
e281682b 4032
b4ff3a36 4033 u8 reserved_at_60[0x20];
e281682b
SM		 4034};
4035
4036struct mlx5_ifc_query_rmp_out_bits {
4037 u8 status[0x8];
b4ff3a36 4038 u8 reserved_at_8[0x18];
e281682b
SM		 4039
4040 u8 syndrome[0x20];
4041
b4ff3a36 4042 u8 reserved_at_40[0xc0];
e281682b
SM		 4043
4044 struct mlx5_ifc_rmpc_bits rmp_context;
4045};
4046
4047struct mlx5_ifc_query_rmp_in_bits {
4048 u8 opcode[0x10];
b4ff3a36 4049 u8 reserved_at_10[0x10];
e281682b 4050
b4ff3a36 4051 u8 reserved_at_20[0x10];
e281682b
SM		 4052 u8 op_mod[0x10];
4053
b4ff3a36 4054 u8 reserved_at_40[0x8];
e281682b
SM		 4055 u8 rmpn[0x18];
4056
b4ff3a36 4057 u8 reserved_at_60[0x20];
e281682b
SM		 4058};
4059
4060struct mlx5_ifc_query_qp_out_bits {
4061 u8 status[0x8];
b4ff3a36 4062 u8 reserved_at_8[0x18];
e281682b
SM		 4063
4064 u8 syndrome[0x20];
4065
b4ff3a36 4066 u8 reserved_at_40[0x40];
e281682b
SM		 4067
4068 u8 opt_param_mask[0x20];
4069
b4ff3a36 4070 u8 reserved_at_a0[0x20];
e281682b
SM		 4071
4072 struct mlx5_ifc_qpc_bits qpc;
4073
b4ff3a36 4074 u8 reserved_at_800[0x80];
e281682b
SM		 4075
4076 u8 pas[0][0x40];
4077};
4078
4079struct mlx5_ifc_query_qp_in_bits {
4080 u8 opcode[0x10];
b4ff3a36 4081 u8 reserved_at_10[0x10];
e281682b 4082
b4ff3a36 4083 u8 reserved_at_20[0x10];
e281682b
SM		 4084 u8 op_mod[0x10];
4085
b4ff3a36 4086 u8 reserved_at_40[0x8];
e281682b
SM		 4087 u8 qpn[0x18];
4088
b4ff3a36 4089 u8 reserved_at_60[0x20];
e281682b
SM		 4090};
4091
4092struct mlx5_ifc_query_q_counter_out_bits {
4093 u8 status[0x8];
b4ff3a36 4094 u8 reserved_at_8[0x18];
e281682b
SM		 4095
4096 u8 syndrome[0x20];
4097
b4ff3a36 4098 u8 reserved_at_40[0x40];
e281682b
SM		 4099
4100 u8 rx_write_requests[0x20];
4101
b4ff3a36 4102 u8 reserved_at_a0[0x20];
e281682b
SM		 4103
4104 u8 rx_read_requests[0x20];
4105
b4ff3a36 4106 u8 reserved_at_e0[0x20];
e281682b
SM		 4107
4108 u8 rx_atomic_requests[0x20];
4109
b4ff3a36 4110 u8 reserved_at_120[0x20];
e281682b
SM		 4111
4112 u8 rx_dct_connect[0x20];
4113
b4ff3a36 4114 u8 reserved_at_160[0x20];
e281682b
SM		 4115
4116 u8 out_of_buffer[0x20];
4117
b4ff3a36 4118 u8 reserved_at_1a0[0x20];
e281682b
SM		 4119
4120 u8 out_of_sequence[0x20];
4121
7486216b
SM		 4122 u8 reserved_at_1e0[0x20];
4123
4124 u8 duplicate_request[0x20];
4125
4126 u8 reserved_at_220[0x20];
4127
4128 u8 rnr_nak_retry_err[0x20];
4129
4130 u8 reserved_at_260[0x20];
4131
4132 u8 packet_seq_err[0x20];
4133
4134 u8 reserved_at_2a0[0x20];
4135
4136 u8 implied_nak_seq_err[0x20];
4137
4138 u8 reserved_at_2e0[0x20];
4139
4140 u8 local_ack_timeout_err[0x20];
4141
58dcb60a
PP		 4142 u8 reserved_at_320[0xa0];
4143
4144 u8 resp_local_length_error[0x20];
4145
4146 u8 req_local_length_error[0x20];
4147
4148 u8 resp_local_qp_error[0x20];
4149
4150 u8 local_operation_error[0x20];
4151
4152 u8 resp_local_protection[0x20];
4153
4154 u8 req_local_protection[0x20];
4155
4156 u8 resp_cqe_error[0x20];
4157
4158 u8 req_cqe_error[0x20];
4159
4160 u8 req_mw_binding[0x20];
4161
4162 u8 req_bad_response[0x20];
4163
4164 u8 req_remote_invalid_request[0x20];
4165
4166 u8 resp_remote_invalid_request[0x20];
4167
4168 u8 req_remote_access_errors[0x20];
4169
4170 u8 resp_remote_access_errors[0x20];
4171
4172 u8 req_remote_operation_errors[0x20];
4173
4174 u8 req_transport_retries_exceeded[0x20];
4175
4176 u8 cq_overflow[0x20];
4177
4178 u8 resp_cqe_flush_error[0x20];
4179
4180 u8 req_cqe_flush_error[0x20];
4181
4182 u8 reserved_at_620[0x1e0];
e281682b
SM		 4183};
4184
4185struct mlx5_ifc_query_q_counter_in_bits {
4186 u8 opcode[0x10];
b4ff3a36 4187 u8 reserved_at_10[0x10];
e281682b 4188
b4ff3a36 4189 u8 reserved_at_20[0x10];
e281682b
SM		 4190 u8 op_mod[0x10];
4191
b4ff3a36 4192 u8 reserved_at_40[0x80];
e281682b
SM		 4193
4194 u8 clear[0x1];
b4ff3a36 4195 u8 reserved_at_c1[0x1f];
e281682b 4196
b4ff3a36 4197 u8 reserved_at_e0[0x18];
e281682b
SM		 4198 u8 counter_set_id[0x8];
4199};
4200
4201struct mlx5_ifc_query_pages_out_bits {
4202 u8 status[0x8];
b4ff3a36 4203 u8 reserved_at_8[0x18];
e281682b
SM		 4204
4205 u8 syndrome[0x20];
4206
b4ff3a36 4207 u8 reserved_at_40[0x10];
e281682b
SM		 4208 u8 function_id[0x10];
4209
4210 u8 num_pages[0x20];
4211};
4212
4213enum {
4214 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4215 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4216 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4217};
4218
4219struct mlx5_ifc_query_pages_in_bits {
4220 u8 opcode[0x10];
b4ff3a36 4221 u8 reserved_at_10[0x10];
e281682b 4222
b4ff3a36 4223 u8 reserved_at_20[0x10];
e281682b
SM		 4224 u8 op_mod[0x10];
4225
b4ff3a36 4226 u8 reserved_at_40[0x10];
e281682b
SM		 4227 u8 function_id[0x10];
4228
b4ff3a36 4229 u8 reserved_at_60[0x20];
e281682b
SM		 4230};
4231
4232struct mlx5_ifc_query_nic_vport_context_out_bits {
4233 u8 status[0x8];
b4ff3a36 4234 u8 reserved_at_8[0x18];
e281682b
SM		 4235
4236 u8 syndrome[0x20];
4237
b4ff3a36 4238 u8 reserved_at_40[0x40];
e281682b
SM		 4239
4240 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4241};
4242
4243struct mlx5_ifc_query_nic_vport_context_in_bits {
4244 u8 opcode[0x10];
b4ff3a36 4245 u8 reserved_at_10[0x10];
e281682b 4246
b4ff3a36 4247 u8 reserved_at_20[0x10];
e281682b
SM		 4248 u8 op_mod[0x10];
4249
4250 u8 other_vport[0x1];
b4ff3a36 4251 u8 reserved_at_41[0xf];
e281682b
SM		 4252 u8 vport_number[0x10];
4253
b4ff3a36 4254 u8 reserved_at_60[0x5];
e281682b 4255 u8 allowed_list_type[0x3];
b4ff3a36 4256 u8 reserved_at_68[0x18];
e281682b
SM		 4257};
4258
4259struct mlx5_ifc_query_mkey_out_bits {
4260 u8 status[0x8];
b4ff3a36 4261 u8 reserved_at_8[0x18];
e281682b
SM		 4262
4263 u8 syndrome[0x20];
4264
b4ff3a36 4265 u8 reserved_at_40[0x40];
e281682b
SM		 4266
4267 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4268
b4ff3a36 4269 u8 reserved_at_280[0x600];
e281682b
SM		 4270
4271 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4272
4273 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4274};
4275
4276struct mlx5_ifc_query_mkey_in_bits {
4277 u8 opcode[0x10];
b4ff3a36 4278 u8 reserved_at_10[0x10];
e281682b 4279
b4ff3a36 4280 u8 reserved_at_20[0x10];
e281682b
SM		 4281 u8 op_mod[0x10];
4282
b4ff3a36 4283 u8 reserved_at_40[0x8];
e281682b
SM		 4284 u8 mkey_index[0x18];
4285
4286 u8 pg_access[0x1];
b4ff3a36 4287 u8 reserved_at_61[0x1f];
e281682b
SM		 4288};
4289
4290struct mlx5_ifc_query_mad_demux_out_bits {
4291 u8 status[0x8];
b4ff3a36 4292 u8 reserved_at_8[0x18];
e281682b
SM		 4293
4294 u8 syndrome[0x20];
4295
b4ff3a36 4296 u8 reserved_at_40[0x40];
e281682b
SM		 4297
4298 u8 mad_dumux_parameters_block[0x20];
4299};
4300
4301struct mlx5_ifc_query_mad_demux_in_bits {
4302 u8 opcode[0x10];
b4ff3a36 4303 u8 reserved_at_10[0x10];
e281682b 4304
b4ff3a36 4305 u8 reserved_at_20[0x10];
e281682b
SM		 4306 u8 op_mod[0x10];
4307
b4ff3a36 4308 u8 reserved_at_40[0x40];
e281682b
SM		 4309};
4310
4311struct mlx5_ifc_query_l2_table_entry_out_bits {
4312 u8 status[0x8];
b4ff3a36 4313 u8 reserved_at_8[0x18];
e281682b
SM		 4314
4315 u8 syndrome[0x20];
4316
b4ff3a36 4317 u8 reserved_at_40[0xa0];
e281682b 4318
b4ff3a36 4319 u8 reserved_at_e0[0x13];
e281682b
SM		 4320 u8 vlan_valid[0x1];
4321 u8 vlan[0xc];
4322
4323 struct mlx5_ifc_mac_address_layout_bits mac_address;
4324
b4ff3a36 4325 u8 reserved_at_140[0xc0];
e281682b
SM		 4326};
4327
4328struct mlx5_ifc_query_l2_table_entry_in_bits {
4329 u8 opcode[0x10];
b4ff3a36 4330 u8 reserved_at_10[0x10];
e281682b 4331
b4ff3a36 4332 u8 reserved_at_20[0x10];
e281682b
SM		 4333 u8 op_mod[0x10];
4334
b4ff3a36 4335 u8 reserved_at_40[0x60];
e281682b 4336
b4ff3a36 4337 u8 reserved_at_a0[0x8];
e281682b
SM		 4338 u8 table_index[0x18];
4339
b4ff3a36 4340 u8 reserved_at_c0[0x140];
e281682b
SM		 4341};
4342
4343struct mlx5_ifc_query_issi_out_bits {
4344 u8 status[0x8];
b4ff3a36 4345 u8 reserved_at_8[0x18];
e281682b
SM		 4346
4347 u8 syndrome[0x20];
4348
b4ff3a36 4349 u8 reserved_at_40[0x10];
e281682b
SM		 4350 u8 current_issi[0x10];
4351
b4ff3a36 4352 u8 reserved_at_60[0xa0];
e281682b 4353
b4ff3a36 4354 u8 reserved_at_100[76][0x8];
e281682b
SM		 4355 u8 supported_issi_dw0[0x20];
4356};
4357
4358struct mlx5_ifc_query_issi_in_bits {
4359 u8 opcode[0x10];
b4ff3a36 4360 u8 reserved_at_10[0x10];
e281682b 4361
b4ff3a36 4362 u8 reserved_at_20[0x10];
e281682b
SM		 4363 u8 op_mod[0x10];
4364
b4ff3a36 4365 u8 reserved_at_40[0x40];
e281682b
SM		 4366};
4367
0dbc6fe0
SM		 4368struct mlx5_ifc_set_driver_version_out_bits {
4369 u8 status[0x8];
4370 u8 reserved_0[0x18];
4371
4372 u8 syndrome[0x20];
4373 u8 reserved_1[0x40];
4374};
4375
4376struct mlx5_ifc_set_driver_version_in_bits {
4377 u8 opcode[0x10];
4378 u8 reserved_0[0x10];
4379
4380 u8 reserved_1[0x10];
4381 u8 op_mod[0x10];
4382
4383 u8 reserved_2[0x40];
4384 u8 driver_version[64][0x8];
4385};
4386
e281682b
SM		 4387struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4388 u8 status[0x8];
b4ff3a36 4389 u8 reserved_at_8[0x18];
e281682b
SM		 4390
4391 u8 syndrome[0x20];
4392
b4ff3a36 4393 u8 reserved_at_40[0x40];
e281682b
SM		 4394
4395 struct mlx5_ifc_pkey_bits pkey[0];
4396};
4397
4398struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4399 u8 opcode[0x10];
b4ff3a36 4400 u8 reserved_at_10[0x10];
e281682b 4401
b4ff3a36 4402 u8 reserved_at_20[0x10];
e281682b
SM		 4403 u8 op_mod[0x10];
4404
4405 u8 other_vport[0x1];
b4ff3a36 4406 u8 reserved_at_41[0xb];
707c4602 4407 u8 port_num[0x4];
e281682b
SM		 4408 u8 vport_number[0x10];
4409
b4ff3a36 4410 u8 reserved_at_60[0x10];
e281682b
SM		 4411 u8 pkey_index[0x10];
4412};
4413
eff901d3
EC		 4414enum {
4415 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4416 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4417 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4418};
4419
e281682b
SM		 4420struct mlx5_ifc_query_hca_vport_gid_out_bits {
4421 u8 status[0x8];
b4ff3a36 4422 u8 reserved_at_8[0x18];
e281682b
SM		 4423
4424 u8 syndrome[0x20];
4425
b4ff3a36 4426 u8 reserved_at_40[0x20];
e281682b
SM		 4427
4428 u8 gids_num[0x10];
b4ff3a36 4429 u8 reserved_at_70[0x10];
e281682b
SM		 4430
4431 struct mlx5_ifc_array128_auto_bits gid[0];
4432};
4433
4434struct mlx5_ifc_query_hca_vport_gid_in_bits {
4435 u8 opcode[0x10];
b4ff3a36 4436 u8 reserved_at_10[0x10];
e281682b 4437
b4ff3a36 4438 u8 reserved_at_20[0x10];
e281682b
SM		 4439 u8 op_mod[0x10];
4440
4441 u8 other_vport[0x1];
b4ff3a36 4442 u8 reserved_at_41[0xb];
707c4602 4443 u8 port_num[0x4];
e281682b
SM		 4444 u8 vport_number[0x10];
4445
b4ff3a36 4446 u8 reserved_at_60[0x10];
e281682b
SM		 4447 u8 gid_index[0x10];
4448};
4449
4450struct mlx5_ifc_query_hca_vport_context_out_bits {
4451 u8 status[0x8];
b4ff3a36 4452 u8 reserved_at_8[0x18];
e281682b
SM		 4453
4454 u8 syndrome[0x20];
4455
b4ff3a36 4456 u8 reserved_at_40[0x40];
e281682b
SM		 4457
4458 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4459};
4460
4461struct mlx5_ifc_query_hca_vport_context_in_bits {
4462 u8 opcode[0x10];
b4ff3a36 4463 u8 reserved_at_10[0x10];
e281682b 4464
b4ff3a36 4465 u8 reserved_at_20[0x10];
e281682b
SM		 4466 u8 op_mod[0x10];
4467
4468 u8 other_vport[0x1];
b4ff3a36 4469 u8 reserved_at_41[0xb];
707c4602 4470 u8 port_num[0x4];
e281682b
SM		 4471 u8 vport_number[0x10];
4472
b4ff3a36 4473 u8 reserved_at_60[0x20];
e281682b
SM		 4474};
4475
4476struct mlx5_ifc_query_hca_cap_out_bits {
4477 u8 status[0x8];
b4ff3a36 4478 u8 reserved_at_8[0x18];
e281682b
SM		 4479
4480 u8 syndrome[0x20];
4481
b4ff3a36 4482 u8 reserved_at_40[0x40];
e281682b
SM		 4483
4484 union mlx5_ifc_hca_cap_union_bits capability;
4485};
4486
4487struct mlx5_ifc_query_hca_cap_in_bits {
4488 u8 opcode[0x10];
b4ff3a36 4489 u8 reserved_at_10[0x10];
e281682b 4490
b4ff3a36 4491 u8 reserved_at_20[0x10];
e281682b
SM		 4492 u8 op_mod[0x10];
4493
b4ff3a36 4494 u8 reserved_at_40[0x40];
e281682b
SM		 4495};
4496
4497struct mlx5_ifc_query_flow_table_out_bits {
4498 u8 status[0x8];
b4ff3a36 4499 u8 reserved_at_8[0x18];
e281682b
SM		 4500
4501 u8 syndrome[0x20];
4502
b4ff3a36 4503 u8 reserved_at_40[0x80];
e281682b 4504
b4ff3a36 4505 u8 reserved_at_c0[0x8];
e281682b 4506 u8 level[0x8];
b4ff3a36 4507 u8 reserved_at_d0[0x8];
e281682b
SM		 4508 u8 log_size[0x8];
4509
b4ff3a36 4510 u8 reserved_at_e0[0x120];
e281682b
SM		 4511};
4512
4513struct mlx5_ifc_query_flow_table_in_bits {
4514 u8 opcode[0x10];
b4ff3a36 4515 u8 reserved_at_10[0x10];
e281682b 4516
b4ff3a36 4517 u8 reserved_at_20[0x10];
e281682b
SM		 4518 u8 op_mod[0x10];
4519
b4ff3a36 4520 u8 reserved_at_40[0x40];
e281682b
SM		 4521
4522 u8 table_type[0x8];
b4ff3a36 4523 u8 reserved_at_88[0x18];
e281682b 4524
b4ff3a36 4525 u8 reserved_at_a0[0x8];
e281682b
SM		 4526 u8 table_id[0x18];
4527
b4ff3a36 4528 u8 reserved_at_c0[0x140];
e281682b
SM		 4529};
4530
4531struct mlx5_ifc_query_fte_out_bits {
4532 u8 status[0x8];
b4ff3a36 4533 u8 reserved_at_8[0x18];
e281682b
SM		 4534
4535 u8 syndrome[0x20];
4536
b4ff3a36 4537 u8 reserved_at_40[0x1c0];
e281682b
SM		 4538
4539 struct mlx5_ifc_flow_context_bits flow_context;
4540};
4541
4542struct mlx5_ifc_query_fte_in_bits {
4543 u8 opcode[0x10];
b4ff3a36 4544 u8 reserved_at_10[0x10];
e281682b 4545
b4ff3a36 4546 u8 reserved_at_20[0x10];
e281682b
SM		 4547 u8 op_mod[0x10];
4548
b4ff3a36 4549 u8 reserved_at_40[0x40];
e281682b
SM		 4550
4551 u8 table_type[0x8];
b4ff3a36 4552 u8 reserved_at_88[0x18];
e281682b 4553
b4ff3a36 4554 u8 reserved_at_a0[0x8];
e281682b
SM		 4555 u8 table_id[0x18];
4556
b4ff3a36 4557 u8 reserved_at_c0[0x40];
e281682b
SM		 4558
4559 u8 flow_index[0x20];
4560
b4ff3a36 4561 u8 reserved_at_120[0xe0];
e281682b
SM		 4562};
4563
4564enum {
4565 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4566 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4567 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4568};
4569
4570struct mlx5_ifc_query_flow_group_out_bits {
4571 u8 status[0x8];
b4ff3a36 4572 u8 reserved_at_8[0x18];
e281682b
SM		 4573
4574 u8 syndrome[0x20];
4575
b4ff3a36 4576 u8 reserved_at_40[0xa0];
e281682b
SM		 4577
4578 u8 start_flow_index[0x20];
4579
b4ff3a36 4580 u8 reserved_at_100[0x20];
e281682b
SM		 4581
4582 u8 end_flow_index[0x20];
4583
b4ff3a36 4584 u8 reserved_at_140[0xa0];
e281682b 4585
b4ff3a36 4586 u8 reserved_at_1e0[0x18];
e281682b
SM		 4587 u8 match_criteria_enable[0x8];
4588
4589 struct mlx5_ifc_fte_match_param_bits match_criteria;
4590
b4ff3a36 4591 u8 reserved_at_1200[0xe00];
e281682b
SM		 4592};
4593
4594struct mlx5_ifc_query_flow_group_in_bits {
4595 u8 opcode[0x10];
b4ff3a36 4596 u8 reserved_at_10[0x10];
e281682b 4597
b4ff3a36 4598 u8 reserved_at_20[0x10];
e281682b
SM		 4599 u8 op_mod[0x10];
4600
b4ff3a36 4601 u8 reserved_at_40[0x40];
e281682b
SM		 4602
4603 u8 table_type[0x8];
b4ff3a36 4604 u8 reserved_at_88[0x18];
e281682b 4605
b4ff3a36 4606 u8 reserved_at_a0[0x8];
e281682b
SM		 4607 u8 table_id[0x18];
4608
4609 u8 group_id[0x20];
4610
b4ff3a36 4611 u8 reserved_at_e0[0x120];
e281682b
SM		 4612};
4613
9dc0b289
AV		 4614struct mlx5_ifc_query_flow_counter_out_bits {
4615 u8 status[0x8];
4616 u8 reserved_at_8[0x18];
4617
4618 u8 syndrome[0x20];
4619
4620 u8 reserved_at_40[0x40];
4621
4622 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4623};
4624
4625struct mlx5_ifc_query_flow_counter_in_bits {
4626 u8 opcode[0x10];
4627 u8 reserved_at_10[0x10];
4628
4629 u8 reserved_at_20[0x10];
4630 u8 op_mod[0x10];
4631
4632 u8 reserved_at_40[0x80];
4633
4634 u8 clear[0x1];
4635 u8 reserved_at_c1[0xf];
4636 u8 num_of_counters[0x10];
4637
a8ffcc74 4638 u8 flow_counter_id[0x20];
9dc0b289
AV		 4639};
4640
d6666753
SM		 4641struct mlx5_ifc_query_esw_vport_context_out_bits {
4642 u8 status[0x8];
b4ff3a36 4643 u8 reserved_at_8[0x18];
d6666753
SM		 4644
4645 u8 syndrome[0x20];
4646
b4ff3a36 4647 u8 reserved_at_40[0x40];
d6666753
SM		 4648
4649 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4650};
4651
4652struct mlx5_ifc_query_esw_vport_context_in_bits {
4653 u8 opcode[0x10];
b4ff3a36 4654 u8 reserved_at_10[0x10];
d6666753 4655
b4ff3a36 4656 u8 reserved_at_20[0x10];
d6666753
SM		 4657 u8 op_mod[0x10];
4658
4659 u8 other_vport[0x1];
b4ff3a36 4660 u8 reserved_at_41[0xf];
d6666753
SM		 4661 u8 vport_number[0x10];
4662
b4ff3a36 4663 u8 reserved_at_60[0x20];
d6666753
SM		 4664};
4665
4666struct mlx5_ifc_modify_esw_vport_context_out_bits {
4667 u8 status[0x8];
b4ff3a36 4668 u8 reserved_at_8[0x18];
d6666753
SM		 4669
4670 u8 syndrome[0x20];
4671
b4ff3a36 4672 u8 reserved_at_40[0x40];
d6666753
SM		 4673};
4674
4675struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4676 u8 reserved_at_0[0x1c];
d6666753
SM		 4677 u8 vport_cvlan_insert[0x1];
4678 u8 vport_svlan_insert[0x1];
4679 u8 vport_cvlan_strip[0x1];
4680 u8 vport_svlan_strip[0x1];
4681};
4682
4683struct mlx5_ifc_modify_esw_vport_context_in_bits {
4684 u8 opcode[0x10];
b4ff3a36 4685 u8 reserved_at_10[0x10];
d6666753 4686
b4ff3a36 4687 u8 reserved_at_20[0x10];
d6666753
SM		 4688 u8 op_mod[0x10];
4689
4690 u8 other_vport[0x1];
b4ff3a36 4691 u8 reserved_at_41[0xf];
d6666753
SM		 4692 u8 vport_number[0x10];
4693
4694 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4695
4696 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4697};
4698
e281682b
SM		 4699struct mlx5_ifc_query_eq_out_bits {
4700 u8 status[0x8];
b4ff3a36 4701 u8 reserved_at_8[0x18];
e281682b
SM		 4702
4703 u8 syndrome[0x20];
4704
b4ff3a36 4705 u8 reserved_at_40[0x40];
e281682b
SM		 4706
4707 struct mlx5_ifc_eqc_bits eq_context_entry;
4708
b4ff3a36 4709 u8 reserved_at_280[0x40];
e281682b
SM		 4710
4711 u8 event_bitmask[0x40];
4712
b4ff3a36 4713 u8 reserved_at_300[0x580];
e281682b
SM		 4714
4715 u8 pas[0][0x40];
4716};
4717
4718struct mlx5_ifc_query_eq_in_bits {
4719 u8 opcode[0x10];
b4ff3a36 4720 u8 reserved_at_10[0x10];
e281682b 4721
b4ff3a36 4722 u8 reserved_at_20[0x10];
e281682b
SM		 4723 u8 op_mod[0x10];
4724
b4ff3a36 4725 u8 reserved_at_40[0x18];
e281682b
SM		 4726 u8 eq_number[0x8];
4727
b4ff3a36 4728 u8 reserved_at_60[0x20];
e281682b
SM		 4729};
4730
7adbde20
HHZ		 4731struct mlx5_ifc_encap_header_in_bits {
4732 u8 reserved_at_0[0x5];
4733 u8 header_type[0x3];
4734 u8 reserved_at_8[0xe];
4735 u8 encap_header_size[0xa];
4736
4737 u8 reserved_at_20[0x10];
4738 u8 encap_header[2][0x8];
4739
4740 u8 more_encap_header[0][0x8];
4741};
4742
4743struct mlx5_ifc_query_encap_header_out_bits {
4744 u8 status[0x8];
4745 u8 reserved_at_8[0x18];
4746
4747 u8 syndrome[0x20];
4748
4749 u8 reserved_at_40[0xa0];
4750
4751 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4752};
4753
4754struct mlx5_ifc_query_encap_header_in_bits {
4755 u8 opcode[0x10];
4756 u8 reserved_at_10[0x10];
4757
4758 u8 reserved_at_20[0x10];
4759 u8 op_mod[0x10];
4760
4761 u8 encap_id[0x20];
4762
4763 u8 reserved_at_60[0xa0];
4764};
4765
4766struct mlx5_ifc_alloc_encap_header_out_bits {
4767 u8 status[0x8];
4768 u8 reserved_at_8[0x18];
4769
4770 u8 syndrome[0x20];
4771
4772 u8 encap_id[0x20];
4773
4774 u8 reserved_at_60[0x20];
4775};
4776
4777struct mlx5_ifc_alloc_encap_header_in_bits {
4778 u8 opcode[0x10];
4779 u8 reserved_at_10[0x10];
4780
4781 u8 reserved_at_20[0x10];
4782 u8 op_mod[0x10];
4783
4784 u8 reserved_at_40[0xa0];
4785
4786 struct mlx5_ifc_encap_header_in_bits encap_header;
4787};
4788
4789struct mlx5_ifc_dealloc_encap_header_out_bits {
4790 u8 status[0x8];
4791 u8 reserved_at_8[0x18];
4792
4793 u8 syndrome[0x20];
4794
4795 u8 reserved_at_40[0x40];
4796};
4797
4798struct mlx5_ifc_dealloc_encap_header_in_bits {
4799 u8 opcode[0x10];
4800 u8 reserved_at_10[0x10];
4801
4802 u8 reserved_20[0x10];
4803 u8 op_mod[0x10];
4804
4805 u8 encap_id[0x20];
4806
4807 u8 reserved_60[0x20];
4808};
4809
2a69cb9f
OG		 4810struct mlx5_ifc_set_action_in_bits {
4811 u8 action_type[0x4];
4812 u8 field[0xc];
4813 u8 reserved_at_10[0x3];
4814 u8 offset[0x5];
4815 u8 reserved_at_18[0x3];
4816 u8 length[0x5];
4817
4818 u8 data[0x20];
4819};
4820
4821struct mlx5_ifc_add_action_in_bits {
4822 u8 action_type[0x4];
4823 u8 field[0xc];
4824 u8 reserved_at_10[0x10];
4825
4826 u8 data[0x20];
4827};
4828
4829union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4830 struct mlx5_ifc_set_action_in_bits set_action_in;
4831 struct mlx5_ifc_add_action_in_bits add_action_in;
4832 u8 reserved_at_0[0x40];
4833};
4834
4835enum {
4836 MLX5_ACTION_TYPE_SET = 0x1,
4837 MLX5_ACTION_TYPE_ADD = 0x2,
4838};
4839
4840enum {
4841 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4842 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4843 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4844 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4845 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4846 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4847 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4848 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4849 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4850 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4851 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4852 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4853 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4854 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4855 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4856 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4857 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4858 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4859 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4860 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4861 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4862 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4863 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4864};
4865
4866struct mlx5_ifc_alloc_modify_header_context_out_bits {
4867 u8 status[0x8];
4868 u8 reserved_at_8[0x18];
4869
4870 u8 syndrome[0x20];
4871
4872 u8 modify_header_id[0x20];
4873
4874 u8 reserved_at_60[0x20];
4875};
4876
4877struct mlx5_ifc_alloc_modify_header_context_in_bits {
4878 u8 opcode[0x10];
4879 u8 reserved_at_10[0x10];
4880
4881 u8 reserved_at_20[0x10];
4882 u8 op_mod[0x10];
4883
4884 u8 reserved_at_40[0x20];
4885
4886 u8 table_type[0x8];
4887 u8 reserved_at_68[0x10];
4888 u8 num_of_actions[0x8];
4889
4890 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4891};
4892
4893struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4894 u8 status[0x8];
4895 u8 reserved_at_8[0x18];
4896
4897 u8 syndrome[0x20];
4898
4899 u8 reserved_at_40[0x40];
4900};
4901
4902struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4903 u8 opcode[0x10];
4904 u8 reserved_at_10[0x10];
4905
4906 u8 reserved_at_20[0x10];
4907 u8 op_mod[0x10];
4908
4909 u8 modify_header_id[0x20];
4910
4911 u8 reserved_at_60[0x20];
4912};
4913
e281682b
SM		 4914struct mlx5_ifc_query_dct_out_bits {
4915 u8 status[0x8];
b4ff3a36 4916 u8 reserved_at_8[0x18];
e281682b
SM		 4917
4918 u8 syndrome[0x20];
4919
b4ff3a36 4920 u8 reserved_at_40[0x40];
e281682b
SM		 4921
4922 struct mlx5_ifc_dctc_bits dct_context_entry;
4923
b4ff3a36 4924 u8 reserved_at_280[0x180];
e281682b
SM		 4925};
4926
4927struct mlx5_ifc_query_dct_in_bits {
4928 u8 opcode[0x10];
b4ff3a36 4929 u8 reserved_at_10[0x10];
e281682b 4930
b4ff3a36 4931 u8 reserved_at_20[0x10];
e281682b
SM		 4932 u8 op_mod[0x10];
4933
b4ff3a36 4934 u8 reserved_at_40[0x8];
e281682b
SM		 4935 u8 dctn[0x18];
4936
b4ff3a36 4937 u8 reserved_at_60[0x20];
e281682b
SM		 4938};
4939
4940struct mlx5_ifc_query_cq_out_bits {
4941 u8 status[0x8];
b4ff3a36 4942 u8 reserved_at_8[0x18];
e281682b
SM		 4943
4944 u8 syndrome[0x20];
4945
b4ff3a36 4946 u8 reserved_at_40[0x40];
e281682b
SM		 4947
4948 struct mlx5_ifc_cqc_bits cq_context;
4949
b4ff3a36 4950 u8 reserved_at_280[0x600];
e281682b
SM		 4951
4952 u8 pas[0][0x40];
4953};
4954
4955struct mlx5_ifc_query_cq_in_bits {
4956 u8 opcode[0x10];
b4ff3a36 4957 u8 reserved_at_10[0x10];
e281682b 4958
b4ff3a36 4959 u8 reserved_at_20[0x10];
e281682b
SM		 4960 u8 op_mod[0x10];
4961
b4ff3a36 4962 u8 reserved_at_40[0x8];
e281682b
SM		 4963 u8 cqn[0x18];
4964
b4ff3a36 4965 u8 reserved_at_60[0x20];
e281682b
SM		 4966};
4967
4968struct mlx5_ifc_query_cong_status_out_bits {
4969 u8 status[0x8];
b4ff3a36 4970 u8 reserved_at_8[0x18];
e281682b
SM		 4971
4972 u8 syndrome[0x20];
4973
b4ff3a36 4974 u8 reserved_at_40[0x20];
e281682b
SM		 4975
4976 u8 enable[0x1];
4977 u8 tag_enable[0x1];
b4ff3a36 4978 u8 reserved_at_62[0x1e];
e281682b
SM		 4979};
4980
4981struct mlx5_ifc_query_cong_status_in_bits {
4982 u8 opcode[0x10];
b4ff3a36 4983 u8 reserved_at_10[0x10];
e281682b 4984
b4ff3a36 4985 u8 reserved_at_20[0x10];
e281682b
SM		 4986 u8 op_mod[0x10];
4987
b4ff3a36 4988 u8 reserved_at_40[0x18];
e281682b
SM		 4989 u8 priority[0x4];
4990 u8 cong_protocol[0x4];
4991
b4ff3a36 4992 u8 reserved_at_60[0x20];
e281682b
SM		 4993};
4994
4995struct mlx5_ifc_query_cong_statistics_out_bits {
4996 u8 status[0x8];
b4ff3a36 4997 u8 reserved_at_8[0x18];
e281682b
SM		 4998
4999 u8 syndrome[0x20];
5000
b4ff3a36 5001 u8 reserved_at_40[0x40];
e281682b 5002
e1f24a79 5003 u8 rp_cur_flows[0x20];
e281682b
SM		 5004
5005 u8 sum_flows[0x20];
5006
e1f24a79 5007 u8 rp_cnp_ignored_high[0x20];
e281682b 5008
e1f24a79 5009 u8 rp_cnp_ignored_low[0x20];
e281682b 5010
e1f24a79 5011 u8 rp_cnp_handled_high[0x20];
e281682b 5012
e1f24a79 5013 u8 rp_cnp_handled_low[0x20];
e281682b 5014
b4ff3a36 5015 u8 reserved_at_140[0x100];
e281682b
SM		 5016
5017 u8 time_stamp_high[0x20];
5018
5019 u8 time_stamp_low[0x20];
5020
5021 u8 accumulators_period[0x20];
5022
e1f24a79 5023 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5024
e1f24a79 5025 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5026
e1f24a79 5027 u8 np_cnp_sent_high[0x20];
e281682b 5028
e1f24a79 5029 u8 np_cnp_sent_low[0x20];
e281682b 5030
b4ff3a36 5031 u8 reserved_at_320[0x560];
e281682b
SM		 5032};
5033
5034struct mlx5_ifc_query_cong_statistics_in_bits {
5035 u8 opcode[0x10];
b4ff3a36 5036 u8 reserved_at_10[0x10];
e281682b 5037
b4ff3a36 5038 u8 reserved_at_20[0x10];
e281682b
SM		 5039 u8 op_mod[0x10];
5040
5041 u8 clear[0x1];
b4ff3a36 5042 u8 reserved_at_41[0x1f];
e281682b 5043
b4ff3a36 5044 u8 reserved_at_60[0x20];
e281682b
SM		 5045};
5046
5047struct mlx5_ifc_query_cong_params_out_bits {
5048 u8 status[0x8];
b4ff3a36 5049 u8 reserved_at_8[0x18];
e281682b
SM		 5050
5051 u8 syndrome[0x20];
5052
b4ff3a36 5053 u8 reserved_at_40[0x40];
e281682b
SM		 5054
5055 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5056};
5057
5058struct mlx5_ifc_query_cong_params_in_bits {
5059 u8 opcode[0x10];
b4ff3a36 5060 u8 reserved_at_10[0x10];
e281682b 5061
b4ff3a36 5062 u8 reserved_at_20[0x10];
e281682b
SM		 5063 u8 op_mod[0x10];
5064
b4ff3a36 5065 u8 reserved_at_40[0x1c];
e281682b
SM		 5066 u8 cong_protocol[0x4];
5067
b4ff3a36 5068 u8 reserved_at_60[0x20];
e281682b
SM		 5069};
5070
5071struct mlx5_ifc_query_adapter_out_bits {
5072 u8 status[0x8];
b4ff3a36 5073 u8 reserved_at_8[0x18];
e281682b
SM		 5074
5075 u8 syndrome[0x20];
5076
b4ff3a36 5077 u8 reserved_at_40[0x40];
e281682b
SM		 5078
5079 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5080};
5081
5082struct mlx5_ifc_query_adapter_in_bits {
5083 u8 opcode[0x10];
b4ff3a36 5084 u8 reserved_at_10[0x10];
e281682b 5085
b4ff3a36 5086 u8 reserved_at_20[0x10];
e281682b
SM		 5087 u8 op_mod[0x10];
5088
b4ff3a36 5089 u8 reserved_at_40[0x40];
e281682b
SM		 5090};
5091
5092struct mlx5_ifc_qp_2rst_out_bits {
5093 u8 status[0x8];
b4ff3a36 5094 u8 reserved_at_8[0x18];
e281682b
SM		 5095
5096 u8 syndrome[0x20];
5097
b4ff3a36 5098 u8 reserved_at_40[0x40];
e281682b
SM		 5099};
5100
5101struct mlx5_ifc_qp_2rst_in_bits {
5102 u8 opcode[0x10];
b4ff3a36 5103 u8 reserved_at_10[0x10];
e281682b 5104
b4ff3a36 5105 u8 reserved_at_20[0x10];
e281682b
SM		 5106 u8 op_mod[0x10];
5107
b4ff3a36 5108 u8 reserved_at_40[0x8];
e281682b
SM		 5109 u8 qpn[0x18];
5110
b4ff3a36 5111 u8 reserved_at_60[0x20];
e281682b
SM		 5112};
5113
5114struct mlx5_ifc_qp_2err_out_bits {
5115 u8 status[0x8];
b4ff3a36 5116 u8 reserved_at_8[0x18];
e281682b
SM		 5117
5118 u8 syndrome[0x20];
5119
b4ff3a36 5120 u8 reserved_at_40[0x40];
e281682b
SM		 5121};
5122
5123struct mlx5_ifc_qp_2err_in_bits {
5124 u8 opcode[0x10];
b4ff3a36 5125 u8 reserved_at_10[0x10];
e281682b 5126
b4ff3a36 5127 u8 reserved_at_20[0x10];
e281682b
SM		 5128 u8 op_mod[0x10];
5129
b4ff3a36 5130 u8 reserved_at_40[0x8];
e281682b
SM		 5131 u8 qpn[0x18];
5132
b4ff3a36 5133 u8 reserved_at_60[0x20];
e281682b
SM		 5134};
5135
5136struct mlx5_ifc_page_fault_resume_out_bits {
5137 u8 status[0x8];
b4ff3a36 5138 u8 reserved_at_8[0x18];
e281682b
SM		 5139
5140 u8 syndrome[0x20];
5141
b4ff3a36 5142 u8 reserved_at_40[0x40];
e281682b
SM		 5143};
5144
5145struct mlx5_ifc_page_fault_resume_in_bits {
5146 u8 opcode[0x10];
b4ff3a36 5147 u8 reserved_at_10[0x10];
e281682b 5148
b4ff3a36 5149 u8 reserved_at_20[0x10];
e281682b
SM		 5150 u8 op_mod[0x10];
5151
5152 u8 error[0x1];
b4ff3a36 5153 u8 reserved_at_41[0x4];
223cdc72
AK		 5154 u8 page_fault_type[0x3];
5155 u8 wq_number[0x18];
e281682b 5156
223cdc72
AK		 5157 u8 reserved_at_60[0x8];
5158 u8 token[0x18];
e281682b
SM		 5159};
5160
5161struct mlx5_ifc_nop_out_bits {
5162 u8 status[0x8];
b4ff3a36 5163 u8 reserved_at_8[0x18];
e281682b
SM		 5164
5165 u8 syndrome[0x20];
5166
b4ff3a36 5167 u8 reserved_at_40[0x40];
e281682b
SM		 5168};
5169
5170struct mlx5_ifc_nop_in_bits {
5171 u8 opcode[0x10];
b4ff3a36 5172 u8 reserved_at_10[0x10];
e281682b 5173
b4ff3a36 5174 u8 reserved_at_20[0x10];
e281682b
SM		 5175 u8 op_mod[0x10];
5176
b4ff3a36 5177 u8 reserved_at_40[0x40];
e281682b
SM		 5178};
5179
5180struct mlx5_ifc_modify_vport_state_out_bits {
5181 u8 status[0x8];
b4ff3a36 5182 u8 reserved_at_8[0x18];
e281682b
SM		 5183
5184 u8 syndrome[0x20];
5185
b4ff3a36 5186 u8 reserved_at_40[0x40];
e281682b
SM		 5187};
5188
5189struct mlx5_ifc_modify_vport_state_in_bits {
5190 u8 opcode[0x10];
b4ff3a36 5191 u8 reserved_at_10[0x10];
e281682b 5192
b4ff3a36 5193 u8 reserved_at_20[0x10];
e281682b
SM		 5194 u8 op_mod[0x10];
5195
5196 u8 other_vport[0x1];
b4ff3a36 5197 u8 reserved_at_41[0xf];
e281682b
SM		 5198 u8 vport_number[0x10];
5199
b4ff3a36 5200 u8 reserved_at_60[0x18];
e281682b 5201 u8 admin_state[0x4];
b4ff3a36 5202 u8 reserved_at_7c[0x4];
e281682b
SM		 5203};
5204
5205struct mlx5_ifc_modify_tis_out_bits {
5206 u8 status[0x8];
b4ff3a36 5207 u8 reserved_at_8[0x18];
e281682b
SM		 5208
5209 u8 syndrome[0x20];
5210
b4ff3a36 5211 u8 reserved_at_40[0x40];
e281682b
SM		 5212};
5213
75850d0b 5214struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5215 u8 reserved_at_0[0x20];
75850d0b 5216
84df61eb
AH		 5217 u8 reserved_at_20[0x1d];
5218 u8 lag_tx_port_affinity[0x1];
5219 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5220 u8 prio[0x1];
5221};
5222
e281682b
SM		 5223struct mlx5_ifc_modify_tis_in_bits {
5224 u8 opcode[0x10];
b4ff3a36 5225 u8 reserved_at_10[0x10];
e281682b 5226
b4ff3a36 5227 u8 reserved_at_20[0x10];
e281682b
SM		 5228 u8 op_mod[0x10];
5229
b4ff3a36 5230 u8 reserved_at_40[0x8];
e281682b
SM		 5231 u8 tisn[0x18];
5232
b4ff3a36 5233 u8 reserved_at_60[0x20];
e281682b 5234
75850d0b 5235 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5236
b4ff3a36 5237 u8 reserved_at_c0[0x40];
e281682b
SM		 5238
5239 struct mlx5_ifc_tisc_bits ctx;
5240};
5241
d9eea403 5242struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5243 u8 reserved_at_0[0x20];
d9eea403 5244
b4ff3a36 5245 u8 reserved_at_20[0x1b];
66189961 5246 u8 self_lb_en[0x1];
bdfc028d
TT		 5247 u8 reserved_at_3c[0x1];
5248 u8 hash[0x1];
5249 u8 reserved_at_3e[0x1];
d9eea403
AS		 5250 u8 lro[0x1];
5251};
5252
e281682b
SM		 5253struct mlx5_ifc_modify_tir_out_bits {
5254 u8 status[0x8];
b4ff3a36 5255 u8 reserved_at_8[0x18];
e281682b
SM		 5256
5257 u8 syndrome[0x20];
5258
b4ff3a36 5259 u8 reserved_at_40[0x40];
e281682b
SM		 5260};
5261
5262struct mlx5_ifc_modify_tir_in_bits {
5263 u8 opcode[0x10];
b4ff3a36 5264 u8 reserved_at_10[0x10];
e281682b 5265
b4ff3a36 5266 u8 reserved_at_20[0x10];
e281682b
SM		 5267 u8 op_mod[0x10];
5268
b4ff3a36 5269 u8 reserved_at_40[0x8];
e281682b
SM		 5270 u8 tirn[0x18];
5271
b4ff3a36 5272 u8 reserved_at_60[0x20];
e281682b 5273
d9eea403 5274 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5275
b4ff3a36 5276 u8 reserved_at_c0[0x40];
e281682b
SM		 5277
5278 struct mlx5_ifc_tirc_bits ctx;
5279};
5280
5281struct mlx5_ifc_modify_sq_out_bits {
5282 u8 status[0x8];
b4ff3a36 5283 u8 reserved_at_8[0x18];
e281682b
SM		 5284
5285 u8 syndrome[0x20];
5286
b4ff3a36 5287 u8 reserved_at_40[0x40];
e281682b
SM		 5288};
5289
5290struct mlx5_ifc_modify_sq_in_bits {
5291 u8 opcode[0x10];
b4ff3a36 5292 u8 reserved_at_10[0x10];
e281682b 5293
b4ff3a36 5294 u8 reserved_at_20[0x10];
e281682b
SM		 5295 u8 op_mod[0x10];
5296
5297 u8 sq_state[0x4];
b4ff3a36 5298 u8 reserved_at_44[0x4];
e281682b
SM		 5299 u8 sqn[0x18];
5300
b4ff3a36 5301 u8 reserved_at_60[0x20];
e281682b
SM		 5302
5303 u8 modify_bitmask[0x40];
5304
b4ff3a36 5305 u8 reserved_at_c0[0x40];
e281682b
SM		 5306
5307 struct mlx5_ifc_sqc_bits ctx;
5308};
5309
813f8540
MHY		 5310struct mlx5_ifc_modify_scheduling_element_out_bits {
5311 u8 status[0x8];
5312 u8 reserved_at_8[0x18];
5313
5314 u8 syndrome[0x20];
5315
5316 u8 reserved_at_40[0x1c0];
5317};
5318
5319enum {
5320 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5321 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5322};
5323
5324struct mlx5_ifc_modify_scheduling_element_in_bits {
5325 u8 opcode[0x10];
5326 u8 reserved_at_10[0x10];
5327
5328 u8 reserved_at_20[0x10];
5329 u8 op_mod[0x10];
5330
5331 u8 scheduling_hierarchy[0x8];
5332 u8 reserved_at_48[0x18];
5333
5334 u8 scheduling_element_id[0x20];
5335
5336 u8 reserved_at_80[0x20];
5337
5338 u8 modify_bitmask[0x20];
5339
5340 u8 reserved_at_c0[0x40];
5341
5342 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5343
5344 u8 reserved_at_300[0x100];
5345};
5346
e281682b
SM		 5347struct mlx5_ifc_modify_rqt_out_bits {
5348 u8 status[0x8];
b4ff3a36 5349 u8 reserved_at_8[0x18];
e281682b
SM		 5350
5351 u8 syndrome[0x20];
5352
b4ff3a36 5353 u8 reserved_at_40[0x40];
e281682b
SM		 5354};
5355
5c50368f 5356struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5357 u8 reserved_at_0[0x20];
5c50368f 5358
b4ff3a36 5359 u8 reserved_at_20[0x1f];
5c50368f
AS		 5360 u8 rqn_list[0x1];
5361};
5362
e281682b
SM		 5363struct mlx5_ifc_modify_rqt_in_bits {
5364 u8 opcode[0x10];
b4ff3a36 5365 u8 reserved_at_10[0x10];
e281682b 5366
b4ff3a36 5367 u8 reserved_at_20[0x10];
e281682b
SM		 5368 u8 op_mod[0x10];
5369
b4ff3a36 5370 u8 reserved_at_40[0x8];
e281682b
SM		 5371 u8 rqtn[0x18];
5372
b4ff3a36 5373 u8 reserved_at_60[0x20];
e281682b 5374
5c50368f 5375 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5376
b4ff3a36 5377 u8 reserved_at_c0[0x40];
e281682b
SM		 5378
5379 struct mlx5_ifc_rqtc_bits ctx;
5380};
5381
5382struct mlx5_ifc_modify_rq_out_bits {
5383 u8 status[0x8];
b4ff3a36 5384 u8 reserved_at_8[0x18];
e281682b
SM		 5385
5386 u8 syndrome[0x20];
5387
b4ff3a36 5388 u8 reserved_at_40[0x40];
e281682b
SM		 5389};
5390
83b502a1
AV		 5391enum {
5392 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5393 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5394 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5395};
5396
e281682b
SM		 5397struct mlx5_ifc_modify_rq_in_bits {
5398 u8 opcode[0x10];
b4ff3a36 5399 u8 reserved_at_10[0x10];
e281682b 5400
b4ff3a36 5401 u8 reserved_at_20[0x10];
e281682b
SM		 5402 u8 op_mod[0x10];
5403
5404 u8 rq_state[0x4];
b4ff3a36 5405 u8 reserved_at_44[0x4];
e281682b
SM		 5406 u8 rqn[0x18];
5407
b4ff3a36 5408 u8 reserved_at_60[0x20];
e281682b
SM		 5409
5410 u8 modify_bitmask[0x40];
5411
b4ff3a36 5412 u8 reserved_at_c0[0x40];
e281682b
SM		 5413
5414 struct mlx5_ifc_rqc_bits ctx;
5415};
5416
5417struct mlx5_ifc_modify_rmp_out_bits {
5418 u8 status[0x8];
b4ff3a36 5419 u8 reserved_at_8[0x18];
e281682b
SM		 5420
5421 u8 syndrome[0x20];
5422
b4ff3a36 5423 u8 reserved_at_40[0x40];
e281682b
SM		 5424};
5425
01949d01 5426struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5427 u8 reserved_at_0[0x20];
01949d01 5428
b4ff3a36 5429 u8 reserved_at_20[0x1f];
01949d01
HA		 5430 u8 lwm[0x1];
5431};
5432
e281682b
SM		 5433struct mlx5_ifc_modify_rmp_in_bits {
5434 u8 opcode[0x10];
b4ff3a36 5435 u8 reserved_at_10[0x10];
e281682b 5436
b4ff3a36 5437 u8 reserved_at_20[0x10];
e281682b
SM		 5438 u8 op_mod[0x10];
5439
5440 u8 rmp_state[0x4];
b4ff3a36 5441 u8 reserved_at_44[0x4];
e281682b
SM		 5442 u8 rmpn[0x18];
5443
b4ff3a36 5444 u8 reserved_at_60[0x20];
e281682b 5445
01949d01 5446 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5447
b4ff3a36 5448 u8 reserved_at_c0[0x40];
e281682b
SM		 5449
5450 struct mlx5_ifc_rmpc_bits ctx;
5451};
5452
5453struct mlx5_ifc_modify_nic_vport_context_out_bits {
5454 u8 status[0x8];
b4ff3a36 5455 u8 reserved_at_8[0x18];
e281682b
SM		 5456
5457 u8 syndrome[0x20];
5458
b4ff3a36 5459 u8 reserved_at_40[0x40];
e281682b
SM		 5460};
5461
5462struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5463 u8 reserved_at_0[0x12];
5464 u8 affiliation[0x1];
5465 u8 reserved_at_e[0x1];
bded747b
HN		 5466 u8 disable_uc_local_lb[0x1];
5467 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5468 u8 node_guid[0x1];
5469 u8 port_guid[0x1];
9def7121 5470 u8 min_inline[0x1];
d82b7318
SM		 5471 u8 mtu[0x1];
5472 u8 change_event[0x1];
5473 u8 promisc[0x1];
e281682b
SM		 5474 u8 permanent_address[0x1];
5475 u8 addresses_list[0x1];
5476 u8 roce_en[0x1];
b4ff3a36 5477 u8 reserved_at_1f[0x1];
e281682b
SM		 5478};
5479
5480struct mlx5_ifc_modify_nic_vport_context_in_bits {
5481 u8 opcode[0x10];
b4ff3a36 5482 u8 reserved_at_10[0x10];
e281682b 5483
b4ff3a36 5484 u8 reserved_at_20[0x10];
e281682b
SM		 5485 u8 op_mod[0x10];
5486
5487 u8 other_vport[0x1];
b4ff3a36 5488 u8 reserved_at_41[0xf];
e281682b
SM		 5489 u8 vport_number[0x10];
5490
5491 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5492
b4ff3a36 5493 u8 reserved_at_80[0x780];
e281682b
SM		 5494
5495 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5496};
5497
5498struct mlx5_ifc_modify_hca_vport_context_out_bits {
5499 u8 status[0x8];
b4ff3a36 5500 u8 reserved_at_8[0x18];
e281682b
SM		 5501
5502 u8 syndrome[0x20];
5503
b4ff3a36 5504 u8 reserved_at_40[0x40];
e281682b
SM		 5505};
5506
5507struct mlx5_ifc_modify_hca_vport_context_in_bits {
5508 u8 opcode[0x10];
b4ff3a36 5509 u8 reserved_at_10[0x10];
e281682b 5510
b4ff3a36 5511 u8 reserved_at_20[0x10];
e281682b
SM		 5512 u8 op_mod[0x10];
5513
5514 u8 other_vport[0x1];
b4ff3a36 5515 u8 reserved_at_41[0xb];
707c4602 5516 u8 port_num[0x4];
e281682b
SM		 5517 u8 vport_number[0x10];
5518
b4ff3a36 5519 u8 reserved_at_60[0x20];
e281682b
SM		 5520
5521 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5522};
5523
5524struct mlx5_ifc_modify_cq_out_bits {
5525 u8 status[0x8];
b4ff3a36 5526 u8 reserved_at_8[0x18];
e281682b
SM		 5527
5528 u8 syndrome[0x20];
5529
b4ff3a36 5530 u8 reserved_at_40[0x40];
e281682b
SM		 5531};
5532
5533enum {
5534 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5535 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5536};
5537
5538struct mlx5_ifc_modify_cq_in_bits {
5539 u8 opcode[0x10];
b4ff3a36 5540 u8 reserved_at_10[0x10];
e281682b 5541
b4ff3a36 5542 u8 reserved_at_20[0x10];
e281682b
SM		 5543 u8 op_mod[0x10];
5544
b4ff3a36 5545 u8 reserved_at_40[0x8];
e281682b
SM		 5546 u8 cqn[0x18];
5547
5548 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5549
5550 struct mlx5_ifc_cqc_bits cq_context;
5551
b4ff3a36 5552 u8 reserved_at_280[0x600];
e281682b
SM		 5553
5554 u8 pas[0][0x40];
5555};
5556
5557struct mlx5_ifc_modify_cong_status_out_bits {
5558 u8 status[0x8];
b4ff3a36 5559 u8 reserved_at_8[0x18];
e281682b
SM		 5560
5561 u8 syndrome[0x20];
5562
b4ff3a36 5563 u8 reserved_at_40[0x40];
e281682b
SM		 5564};
5565
5566struct mlx5_ifc_modify_cong_status_in_bits {
5567 u8 opcode[0x10];
b4ff3a36 5568 u8 reserved_at_10[0x10];
e281682b 5569
b4ff3a36 5570 u8 reserved_at_20[0x10];
e281682b
SM		 5571 u8 op_mod[0x10];
5572
b4ff3a36 5573 u8 reserved_at_40[0x18];
e281682b
SM		 5574 u8 priority[0x4];
5575 u8 cong_protocol[0x4];
5576
5577 u8 enable[0x1];
5578 u8 tag_enable[0x1];
b4ff3a36 5579 u8 reserved_at_62[0x1e];
e281682b
SM		 5580};
5581
5582struct mlx5_ifc_modify_cong_params_out_bits {
5583 u8 status[0x8];
b4ff3a36 5584 u8 reserved_at_8[0x18];
e281682b
SM		 5585
5586 u8 syndrome[0x20];
5587
b4ff3a36 5588 u8 reserved_at_40[0x40];
e281682b
SM		 5589};
5590
5591struct mlx5_ifc_modify_cong_params_in_bits {
5592 u8 opcode[0x10];
b4ff3a36 5593 u8 reserved_at_10[0x10];
e281682b 5594
b4ff3a36 5595 u8 reserved_at_20[0x10];
e281682b
SM		 5596 u8 op_mod[0x10];
5597
b4ff3a36 5598 u8 reserved_at_40[0x1c];
e281682b
SM		 5599 u8 cong_protocol[0x4];
5600
5601 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5602
b4ff3a36 5603 u8 reserved_at_80[0x80];
e281682b
SM		 5604
5605 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5606};
5607
5608struct mlx5_ifc_manage_pages_out_bits {
5609 u8 status[0x8];
b4ff3a36 5610 u8 reserved_at_8[0x18];
e281682b
SM		 5611
5612 u8 syndrome[0x20];
5613
5614 u8 output_num_entries[0x20];
5615
b4ff3a36 5616 u8 reserved_at_60[0x20];
e281682b
SM		 5617
5618 u8 pas[0][0x40];
5619};
5620
5621enum {
5622 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5623 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5624 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5625};
5626
5627struct mlx5_ifc_manage_pages_in_bits {
5628 u8 opcode[0x10];
b4ff3a36 5629 u8 reserved_at_10[0x10];
e281682b 5630
b4ff3a36 5631 u8 reserved_at_20[0x10];
e281682b
SM		 5632 u8 op_mod[0x10];
5633
b4ff3a36 5634 u8 reserved_at_40[0x10];
e281682b
SM		 5635 u8 function_id[0x10];
5636
5637 u8 input_num_entries[0x20];
5638
5639 u8 pas[0][0x40];
5640};
5641
5642struct mlx5_ifc_mad_ifc_out_bits {
5643 u8 status[0x8];
b4ff3a36 5644 u8 reserved_at_8[0x18];
e281682b
SM		 5645
5646 u8 syndrome[0x20];
5647
b4ff3a36 5648 u8 reserved_at_40[0x40];
e281682b
SM		 5649
5650 u8 response_mad_packet[256][0x8];
5651};
5652
5653struct mlx5_ifc_mad_ifc_in_bits {
5654 u8 opcode[0x10];
b4ff3a36 5655 u8 reserved_at_10[0x10];
e281682b 5656
b4ff3a36 5657 u8 reserved_at_20[0x10];
e281682b
SM		 5658 u8 op_mod[0x10];
5659
5660 u8 remote_lid[0x10];
b4ff3a36 5661 u8 reserved_at_50[0x8];
e281682b
SM		 5662 u8 port[0x8];
5663
b4ff3a36 5664 u8 reserved_at_60[0x20];
e281682b
SM		 5665
5666 u8 mad[256][0x8];
5667};
5668
5669struct mlx5_ifc_init_hca_out_bits {
5670 u8 status[0x8];
b4ff3a36 5671 u8 reserved_at_8[0x18];
e281682b
SM		 5672
5673 u8 syndrome[0x20];
5674
b4ff3a36 5675 u8 reserved_at_40[0x40];
e281682b
SM		 5676};
5677
5678struct mlx5_ifc_init_hca_in_bits {
5679 u8 opcode[0x10];
b4ff3a36 5680 u8 reserved_at_10[0x10];
e281682b 5681
b4ff3a36 5682 u8 reserved_at_20[0x10];
e281682b
SM		 5683 u8 op_mod[0x10];
5684
b4ff3a36 5685 u8 reserved_at_40[0x40];
8737f818 5686 u8 sw_owner_id[4][0x20];
e281682b
SM		 5687};
5688
5689struct mlx5_ifc_init2rtr_qp_out_bits {
5690 u8 status[0x8];
b4ff3a36 5691 u8 reserved_at_8[0x18];
e281682b
SM		 5692
5693 u8 syndrome[0x20];
5694
b4ff3a36 5695 u8 reserved_at_40[0x40];
e281682b
SM		 5696};
5697
5698struct mlx5_ifc_init2rtr_qp_in_bits {
5699 u8 opcode[0x10];
b4ff3a36 5700 u8 reserved_at_10[0x10];
e281682b 5701
b4ff3a36 5702 u8 reserved_at_20[0x10];
e281682b
SM		 5703 u8 op_mod[0x10];
5704
b4ff3a36 5705 u8 reserved_at_40[0x8];
e281682b
SM		 5706 u8 qpn[0x18];
5707
b4ff3a36 5708 u8 reserved_at_60[0x20];
e281682b
SM		 5709
5710 u8 opt_param_mask[0x20];
5711
b4ff3a36 5712 u8 reserved_at_a0[0x20];
e281682b
SM		 5713
5714 struct mlx5_ifc_qpc_bits qpc;
5715
b4ff3a36 5716 u8 reserved_at_800[0x80];
e281682b
SM		 5717};
5718
5719struct mlx5_ifc_init2init_qp_out_bits {
5720 u8 status[0x8];
b4ff3a36 5721 u8 reserved_at_8[0x18];
e281682b
SM		 5722
5723 u8 syndrome[0x20];
5724
b4ff3a36 5725 u8 reserved_at_40[0x40];
e281682b
SM		 5726};
5727
5728struct mlx5_ifc_init2init_qp_in_bits {
5729 u8 opcode[0x10];
b4ff3a36 5730 u8 reserved_at_10[0x10];
e281682b 5731
b4ff3a36 5732 u8 reserved_at_20[0x10];
e281682b
SM		 5733 u8 op_mod[0x10];
5734
b4ff3a36 5735 u8 reserved_at_40[0x8];
e281682b
SM		 5736 u8 qpn[0x18];
5737
b4ff3a36 5738 u8 reserved_at_60[0x20];
e281682b
SM		 5739
5740 u8 opt_param_mask[0x20];
5741
b4ff3a36 5742 u8 reserved_at_a0[0x20];
e281682b
SM		 5743
5744 struct mlx5_ifc_qpc_bits qpc;
5745
b4ff3a36 5746 u8 reserved_at_800[0x80];
e281682b
SM		 5747};
5748
5749struct mlx5_ifc_get_dropped_packet_log_out_bits {
5750 u8 status[0x8];
b4ff3a36 5751 u8 reserved_at_8[0x18];
e281682b
SM		 5752
5753 u8 syndrome[0x20];
5754
b4ff3a36 5755 u8 reserved_at_40[0x40];
e281682b
SM		 5756
5757 u8 packet_headers_log[128][0x8];
5758
5759 u8 packet_syndrome[64][0x8];
5760};
5761
5762struct mlx5_ifc_get_dropped_packet_log_in_bits {
5763 u8 opcode[0x10];
b4ff3a36 5764 u8 reserved_at_10[0x10];
e281682b 5765
b4ff3a36 5766 u8 reserved_at_20[0x10];
e281682b
SM		 5767 u8 op_mod[0x10];
5768
b4ff3a36 5769 u8 reserved_at_40[0x40];
e281682b
SM		 5770};
5771
5772struct mlx5_ifc_gen_eqe_in_bits {
5773 u8 opcode[0x10];
b4ff3a36 5774 u8 reserved_at_10[0x10];
e281682b 5775
b4ff3a36 5776 u8 reserved_at_20[0x10];
e281682b
SM		 5777 u8 op_mod[0x10];
5778
b4ff3a36 5779 u8 reserved_at_40[0x18];
e281682b
SM		 5780 u8 eq_number[0x8];
5781
b4ff3a36 5782 u8 reserved_at_60[0x20];
e281682b
SM		 5783
5784 u8 eqe[64][0x8];
5785};
5786
5787struct mlx5_ifc_gen_eq_out_bits {
5788 u8 status[0x8];
b4ff3a36 5789 u8 reserved_at_8[0x18];
e281682b
SM		 5790
5791 u8 syndrome[0x20];
5792
b4ff3a36 5793 u8 reserved_at_40[0x40];
e281682b
SM		 5794};
5795
5796struct mlx5_ifc_enable_hca_out_bits {
5797 u8 status[0x8];
b4ff3a36 5798 u8 reserved_at_8[0x18];
e281682b
SM		 5799
5800 u8 syndrome[0x20];
5801
b4ff3a36 5802 u8 reserved_at_40[0x20];
e281682b
SM		 5803};
5804
5805struct mlx5_ifc_enable_hca_in_bits {
5806 u8 opcode[0x10];
b4ff3a36 5807 u8 reserved_at_10[0x10];
e281682b 5808
b4ff3a36 5809 u8 reserved_at_20[0x10];
e281682b
SM		 5810 u8 op_mod[0x10];
5811
b4ff3a36 5812 u8 reserved_at_40[0x10];
e281682b
SM		 5813 u8 function_id[0x10];
5814
b4ff3a36 5815 u8 reserved_at_60[0x20];
e281682b
SM		 5816};
5817
5818struct mlx5_ifc_drain_dct_out_bits {
5819 u8 status[0x8];
b4ff3a36 5820 u8 reserved_at_8[0x18];
e281682b
SM		 5821
5822 u8 syndrome[0x20];
5823
b4ff3a36 5824 u8 reserved_at_40[0x40];
e281682b
SM		 5825};
5826
5827struct mlx5_ifc_drain_dct_in_bits {
5828 u8 opcode[0x10];
b4ff3a36 5829 u8 reserved_at_10[0x10];
e281682b 5830
b4ff3a36 5831 u8 reserved_at_20[0x10];
e281682b
SM		 5832 u8 op_mod[0x10];
5833
b4ff3a36 5834 u8 reserved_at_40[0x8];
e281682b
SM		 5835 u8 dctn[0x18];
5836
b4ff3a36 5837 u8 reserved_at_60[0x20];
e281682b
SM		 5838};
5839
5840struct mlx5_ifc_disable_hca_out_bits {
5841 u8 status[0x8];
b4ff3a36 5842 u8 reserved_at_8[0x18];
e281682b
SM		 5843
5844 u8 syndrome[0x20];
5845
b4ff3a36 5846 u8 reserved_at_40[0x20];
e281682b
SM		 5847};
5848
5849struct mlx5_ifc_disable_hca_in_bits {
5850 u8 opcode[0x10];
b4ff3a36 5851 u8 reserved_at_10[0x10];
e281682b 5852
b4ff3a36 5853 u8 reserved_at_20[0x10];
e281682b
SM		 5854 u8 op_mod[0x10];
5855
b4ff3a36 5856 u8 reserved_at_40[0x10];
e281682b
SM		 5857 u8 function_id[0x10];
5858
b4ff3a36 5859 u8 reserved_at_60[0x20];
e281682b
SM		 5860};
5861
5862struct mlx5_ifc_detach_from_mcg_out_bits {
5863 u8 status[0x8];
b4ff3a36 5864 u8 reserved_at_8[0x18];
e281682b
SM		 5865
5866 u8 syndrome[0x20];
5867
b4ff3a36 5868 u8 reserved_at_40[0x40];
e281682b
SM		 5869};
5870
5871struct mlx5_ifc_detach_from_mcg_in_bits {
5872 u8 opcode[0x10];
b4ff3a36 5873 u8 reserved_at_10[0x10];
e281682b 5874
b4ff3a36 5875 u8 reserved_at_20[0x10];
e281682b
SM		 5876 u8 op_mod[0x10];
5877
b4ff3a36 5878 u8 reserved_at_40[0x8];
e281682b
SM		 5879 u8 qpn[0x18];
5880
b4ff3a36 5881 u8 reserved_at_60[0x20];
e281682b
SM		 5882
5883 u8 multicast_gid[16][0x8];
5884};
5885
7486216b
SM		 5886struct mlx5_ifc_destroy_xrq_out_bits {
5887 u8 status[0x8];
5888 u8 reserved_at_8[0x18];
5889
5890 u8 syndrome[0x20];
5891
5892 u8 reserved_at_40[0x40];
5893};
5894
5895struct mlx5_ifc_destroy_xrq_in_bits {
5896 u8 opcode[0x10];
5897 u8 reserved_at_10[0x10];
5898
5899 u8 reserved_at_20[0x10];
5900 u8 op_mod[0x10];
5901
5902 u8 reserved_at_40[0x8];
5903 u8 xrqn[0x18];
5904
5905 u8 reserved_at_60[0x20];
5906};
5907
e281682b
SM		 5908struct mlx5_ifc_destroy_xrc_srq_out_bits {
5909 u8 status[0x8];
b4ff3a36 5910 u8 reserved_at_8[0x18];
e281682b
SM		 5911
5912 u8 syndrome[0x20];
5913
b4ff3a36 5914 u8 reserved_at_40[0x40];
e281682b
SM		 5915};
5916
5917struct mlx5_ifc_destroy_xrc_srq_in_bits {
5918 u8 opcode[0x10];
b4ff3a36 5919 u8 reserved_at_10[0x10];
e281682b 5920
b4ff3a36 5921 u8 reserved_at_20[0x10];
e281682b
SM		 5922 u8 op_mod[0x10];
5923
b4ff3a36 5924 u8 reserved_at_40[0x8];
e281682b
SM		 5925 u8 xrc_srqn[0x18];
5926
b4ff3a36 5927 u8 reserved_at_60[0x20];
e281682b
SM		 5928};
5929
5930struct mlx5_ifc_destroy_tis_out_bits {
5931 u8 status[0x8];
b4ff3a36 5932 u8 reserved_at_8[0x18];
e281682b
SM		 5933
5934 u8 syndrome[0x20];
5935
b4ff3a36 5936 u8 reserved_at_40[0x40];
e281682b
SM		 5937};
5938
5939struct mlx5_ifc_destroy_tis_in_bits {
5940 u8 opcode[0x10];
b4ff3a36 5941 u8 reserved_at_10[0x10];
e281682b 5942
b4ff3a36 5943 u8 reserved_at_20[0x10];
e281682b
SM		 5944 u8 op_mod[0x10];
5945
b4ff3a36 5946 u8 reserved_at_40[0x8];
e281682b
SM		 5947 u8 tisn[0x18];
5948
b4ff3a36 5949 u8 reserved_at_60[0x20];
e281682b
SM		 5950};
5951
5952struct mlx5_ifc_destroy_tir_out_bits {
5953 u8 status[0x8];
b4ff3a36 5954 u8 reserved_at_8[0x18];
e281682b
SM		 5955
5956 u8 syndrome[0x20];
5957
b4ff3a36 5958 u8 reserved_at_40[0x40];
e281682b
SM		 5959};
5960
5961struct mlx5_ifc_destroy_tir_in_bits {
5962 u8 opcode[0x10];
b4ff3a36 5963 u8 reserved_at_10[0x10];
e281682b 5964
b4ff3a36 5965 u8 reserved_at_20[0x10];
e281682b
SM		 5966 u8 op_mod[0x10];
5967
b4ff3a36 5968 u8 reserved_at_40[0x8];
e281682b
SM		 5969 u8 tirn[0x18];
5970
b4ff3a36 5971 u8 reserved_at_60[0x20];
e281682b
SM		 5972};
5973
5974struct mlx5_ifc_destroy_srq_out_bits {
5975 u8 status[0x8];
b4ff3a36 5976 u8 reserved_at_8[0x18];
e281682b
SM		 5977
5978 u8 syndrome[0x20];
5979
b4ff3a36 5980 u8 reserved_at_40[0x40];
e281682b
SM		 5981};
5982
5983struct mlx5_ifc_destroy_srq_in_bits {
5984 u8 opcode[0x10];
b4ff3a36 5985 u8 reserved_at_10[0x10];
e281682b 5986
b4ff3a36 5987 u8 reserved_at_20[0x10];
e281682b
SM		 5988 u8 op_mod[0x10];
5989
b4ff3a36 5990 u8 reserved_at_40[0x8];
e281682b
SM		 5991 u8 srqn[0x18];
5992
b4ff3a36 5993 u8 reserved_at_60[0x20];
e281682b
SM		 5994};
5995
5996struct mlx5_ifc_destroy_sq_out_bits {
5997 u8 status[0x8];
b4ff3a36 5998 u8 reserved_at_8[0x18];
e281682b
SM		 5999
6000 u8 syndrome[0x20];
6001
b4ff3a36 6002 u8 reserved_at_40[0x40];
e281682b
SM		 6003};
6004
6005struct mlx5_ifc_destroy_sq_in_bits {
6006 u8 opcode[0x10];
b4ff3a36 6007 u8 reserved_at_10[0x10];
e281682b 6008
b4ff3a36 6009 u8 reserved_at_20[0x10];
e281682b
SM		 6010 u8 op_mod[0x10];
6011
b4ff3a36 6012 u8 reserved_at_40[0x8];
e281682b
SM		 6013 u8 sqn[0x18];
6014
b4ff3a36 6015 u8 reserved_at_60[0x20];
e281682b
SM		 6016};
6017
813f8540
MHY		 6018struct mlx5_ifc_destroy_scheduling_element_out_bits {
6019 u8 status[0x8];
6020 u8 reserved_at_8[0x18];
6021
6022 u8 syndrome[0x20];
6023
6024 u8 reserved_at_40[0x1c0];
6025};
6026
6027struct mlx5_ifc_destroy_scheduling_element_in_bits {
6028 u8 opcode[0x10];
6029 u8 reserved_at_10[0x10];
6030
6031 u8 reserved_at_20[0x10];
6032 u8 op_mod[0x10];
6033
6034 u8 scheduling_hierarchy[0x8];
6035 u8 reserved_at_48[0x18];
6036
6037 u8 scheduling_element_id[0x20];
6038
6039 u8 reserved_at_80[0x180];
6040};
6041
e281682b
SM		 6042struct mlx5_ifc_destroy_rqt_out_bits {
6043 u8 status[0x8];
b4ff3a36 6044 u8 reserved_at_8[0x18];
e281682b
SM		 6045
6046 u8 syndrome[0x20];
6047
b4ff3a36 6048 u8 reserved_at_40[0x40];
e281682b
SM		 6049};
6050
6051struct mlx5_ifc_destroy_rqt_in_bits {
6052 u8 opcode[0x10];
b4ff3a36 6053 u8 reserved_at_10[0x10];
e281682b 6054
b4ff3a36 6055 u8 reserved_at_20[0x10];
e281682b
SM		 6056 u8 op_mod[0x10];
6057
b4ff3a36 6058 u8 reserved_at_40[0x8];
e281682b
SM		 6059 u8 rqtn[0x18];
6060
b4ff3a36 6061 u8 reserved_at_60[0x20];
e281682b
SM		 6062};
6063
6064struct mlx5_ifc_destroy_rq_out_bits {
6065 u8 status[0x8];
b4ff3a36 6066 u8 reserved_at_8[0x18];
e281682b
SM		 6067
6068 u8 syndrome[0x20];
6069
b4ff3a36 6070 u8 reserved_at_40[0x40];
e281682b
SM		 6071};
6072
6073struct mlx5_ifc_destroy_rq_in_bits {
6074 u8 opcode[0x10];
b4ff3a36 6075 u8 reserved_at_10[0x10];
e281682b 6076
b4ff3a36 6077 u8 reserved_at_20[0x10];
e281682b
SM		 6078 u8 op_mod[0x10];
6079
b4ff3a36 6080 u8 reserved_at_40[0x8];
e281682b
SM		 6081 u8 rqn[0x18];
6082
b4ff3a36 6083 u8 reserved_at_60[0x20];
e281682b
SM		 6084};
6085
c1e0bfc1
MG		 6086struct mlx5_ifc_set_delay_drop_params_in_bits {
6087 u8 opcode[0x10];
6088 u8 reserved_at_10[0x10];
6089
6090 u8 reserved_at_20[0x10];
6091 u8 op_mod[0x10];
6092
6093 u8 reserved_at_40[0x20];
6094
6095 u8 reserved_at_60[0x10];
6096 u8 delay_drop_timeout[0x10];
6097};
6098
6099struct mlx5_ifc_set_delay_drop_params_out_bits {
6100 u8 status[0x8];
6101 u8 reserved_at_8[0x18];
6102
6103 u8 syndrome[0x20];
6104
6105 u8 reserved_at_40[0x40];
6106};
6107
e281682b
SM		 6108struct mlx5_ifc_destroy_rmp_out_bits {
6109 u8 status[0x8];
b4ff3a36 6110 u8 reserved_at_8[0x18];
e281682b
SM		 6111
6112 u8 syndrome[0x20];
6113
b4ff3a36 6114 u8 reserved_at_40[0x40];
e281682b
SM		 6115};
6116
6117struct mlx5_ifc_destroy_rmp_in_bits {
6118 u8 opcode[0x10];
b4ff3a36 6119 u8 reserved_at_10[0x10];
e281682b 6120
b4ff3a36 6121 u8 reserved_at_20[0x10];
e281682b
SM		 6122 u8 op_mod[0x10];
6123
b4ff3a36 6124 u8 reserved_at_40[0x8];
e281682b
SM		 6125 u8 rmpn[0x18];
6126
b4ff3a36 6127 u8 reserved_at_60[0x20];
e281682b
SM		 6128};
6129
6130struct mlx5_ifc_destroy_qp_out_bits {
6131 u8 status[0x8];
b4ff3a36 6132 u8 reserved_at_8[0x18];
e281682b
SM		 6133
6134 u8 syndrome[0x20];
6135
b4ff3a36 6136 u8 reserved_at_40[0x40];
e281682b
SM		 6137};
6138
6139struct mlx5_ifc_destroy_qp_in_bits {
6140 u8 opcode[0x10];
b4ff3a36 6141 u8 reserved_at_10[0x10];
e281682b 6142
b4ff3a36 6143 u8 reserved_at_20[0x10];
e281682b
SM		 6144 u8 op_mod[0x10];
6145
b4ff3a36 6146 u8 reserved_at_40[0x8];
e281682b
SM		 6147 u8 qpn[0x18];
6148
b4ff3a36 6149 u8 reserved_at_60[0x20];
e281682b
SM		 6150};
6151
6152struct mlx5_ifc_destroy_psv_out_bits {
6153 u8 status[0x8];
b4ff3a36 6154 u8 reserved_at_8[0x18];
e281682b
SM		 6155
6156 u8 syndrome[0x20];
6157
b4ff3a36 6158 u8 reserved_at_40[0x40];
e281682b
SM		 6159};
6160
6161struct mlx5_ifc_destroy_psv_in_bits {
6162 u8 opcode[0x10];
b4ff3a36 6163 u8 reserved_at_10[0x10];
e281682b 6164
b4ff3a36 6165 u8 reserved_at_20[0x10];
e281682b
SM		 6166 u8 op_mod[0x10];
6167
b4ff3a36 6168 u8 reserved_at_40[0x8];
e281682b
SM		 6169 u8 psvn[0x18];
6170
b4ff3a36 6171 u8 reserved_at_60[0x20];
e281682b
SM		 6172};
6173
6174struct mlx5_ifc_destroy_mkey_out_bits {
6175 u8 status[0x8];
b4ff3a36 6176 u8 reserved_at_8[0x18];
e281682b
SM		 6177
6178 u8 syndrome[0x20];
6179
b4ff3a36 6180 u8 reserved_at_40[0x40];
e281682b
SM		 6181};
6182
6183struct mlx5_ifc_destroy_mkey_in_bits {
6184 u8 opcode[0x10];
b4ff3a36 6185 u8 reserved_at_10[0x10];
e281682b 6186
b4ff3a36 6187 u8 reserved_at_20[0x10];
e281682b
SM		 6188 u8 op_mod[0x10];
6189
b4ff3a36 6190 u8 reserved_at_40[0x8];
e281682b
SM		 6191 u8 mkey_index[0x18];
6192
b4ff3a36 6193 u8 reserved_at_60[0x20];
e281682b
SM		 6194};
6195
6196struct mlx5_ifc_destroy_flow_table_out_bits {
6197 u8 status[0x8];
b4ff3a36 6198 u8 reserved_at_8[0x18];
e281682b
SM		 6199
6200 u8 syndrome[0x20];
6201
b4ff3a36 6202 u8 reserved_at_40[0x40];
e281682b
SM		 6203};
6204
6205struct mlx5_ifc_destroy_flow_table_in_bits {
6206 u8 opcode[0x10];
b4ff3a36 6207 u8 reserved_at_10[0x10];
e281682b 6208
b4ff3a36 6209 u8 reserved_at_20[0x10];
e281682b
SM		 6210 u8 op_mod[0x10];
6211
7d5e1423
SM		 6212 u8 other_vport[0x1];
6213 u8 reserved_at_41[0xf];
6214 u8 vport_number[0x10];
6215
6216 u8 reserved_at_60[0x20];
e281682b
SM		 6217
6218 u8 table_type[0x8];
b4ff3a36 6219 u8 reserved_at_88[0x18];
e281682b 6220
b4ff3a36 6221 u8 reserved_at_a0[0x8];
e281682b
SM		 6222 u8 table_id[0x18];
6223
b4ff3a36 6224 u8 reserved_at_c0[0x140];
e281682b
SM		 6225};
6226
6227struct mlx5_ifc_destroy_flow_group_out_bits {
6228 u8 status[0x8];
b4ff3a36 6229 u8 reserved_at_8[0x18];
e281682b
SM		 6230
6231 u8 syndrome[0x20];
6232
b4ff3a36 6233 u8 reserved_at_40[0x40];
e281682b
SM		 6234};
6235
6236struct mlx5_ifc_destroy_flow_group_in_bits {
6237 u8 opcode[0x10];
b4ff3a36 6238 u8 reserved_at_10[0x10];
e281682b 6239
b4ff3a36 6240 u8 reserved_at_20[0x10];
e281682b
SM		 6241 u8 op_mod[0x10];
6242
7d5e1423
SM		 6243 u8 other_vport[0x1];
6244 u8 reserved_at_41[0xf];
6245 u8 vport_number[0x10];
6246
6247 u8 reserved_at_60[0x20];
e281682b
SM		 6248
6249 u8 table_type[0x8];
b4ff3a36 6250 u8 reserved_at_88[0x18];
e281682b 6251
b4ff3a36 6252 u8 reserved_at_a0[0x8];
e281682b
SM		 6253 u8 table_id[0x18];
6254
6255 u8 group_id[0x20];
6256
b4ff3a36 6257 u8 reserved_at_e0[0x120];
e281682b
SM		 6258};
6259
6260struct mlx5_ifc_destroy_eq_out_bits {
6261 u8 status[0x8];
b4ff3a36 6262 u8 reserved_at_8[0x18];
e281682b
SM		 6263
6264 u8 syndrome[0x20];
6265
b4ff3a36 6266 u8 reserved_at_40[0x40];
e281682b
SM		 6267};
6268
6269struct mlx5_ifc_destroy_eq_in_bits {
6270 u8 opcode[0x10];
b4ff3a36 6271 u8 reserved_at_10[0x10];
e281682b 6272
b4ff3a36 6273 u8 reserved_at_20[0x10];
e281682b
SM		 6274 u8 op_mod[0x10];
6275
b4ff3a36 6276 u8 reserved_at_40[0x18];
e281682b
SM		 6277 u8 eq_number[0x8];
6278
b4ff3a36 6279 u8 reserved_at_60[0x20];
e281682b
SM		 6280};
6281
6282struct mlx5_ifc_destroy_dct_out_bits {
6283 u8 status[0x8];
b4ff3a36 6284 u8 reserved_at_8[0x18];
e281682b
SM		 6285
6286 u8 syndrome[0x20];
6287
b4ff3a36 6288 u8 reserved_at_40[0x40];
e281682b
SM		 6289};
6290
6291struct mlx5_ifc_destroy_dct_in_bits {
6292 u8 opcode[0x10];
b4ff3a36 6293 u8 reserved_at_10[0x10];
e281682b 6294
b4ff3a36 6295 u8 reserved_at_20[0x10];
e281682b
SM		 6296 u8 op_mod[0x10];
6297
b4ff3a36 6298 u8 reserved_at_40[0x8];
e281682b
SM		 6299 u8 dctn[0x18];
6300
b4ff3a36 6301 u8 reserved_at_60[0x20];
e281682b
SM		 6302};
6303
6304struct mlx5_ifc_destroy_cq_out_bits {
6305 u8 status[0x8];
b4ff3a36 6306 u8 reserved_at_8[0x18];
e281682b
SM		 6307
6308 u8 syndrome[0x20];
6309
b4ff3a36 6310 u8 reserved_at_40[0x40];
e281682b
SM		 6311};
6312
6313struct mlx5_ifc_destroy_cq_in_bits {
6314 u8 opcode[0x10];
b4ff3a36 6315 u8 reserved_at_10[0x10];
e281682b 6316
b4ff3a36 6317 u8 reserved_at_20[0x10];
e281682b
SM		 6318 u8 op_mod[0x10];
6319
b4ff3a36 6320 u8 reserved_at_40[0x8];
e281682b
SM		 6321 u8 cqn[0x18];
6322
b4ff3a36 6323 u8 reserved_at_60[0x20];
e281682b
SM		 6324};
6325
6326struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6327 u8 status[0x8];
b4ff3a36 6328 u8 reserved_at_8[0x18];
e281682b
SM		 6329
6330 u8 syndrome[0x20];
6331
b4ff3a36 6332 u8 reserved_at_40[0x40];
e281682b
SM		 6333};
6334
6335struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6336 u8 opcode[0x10];
b4ff3a36 6337 u8 reserved_at_10[0x10];
e281682b 6338
b4ff3a36 6339 u8 reserved_at_20[0x10];
e281682b
SM		 6340 u8 op_mod[0x10];
6341
b4ff3a36 6342 u8 reserved_at_40[0x20];
e281682b 6343
b4ff3a36 6344 u8 reserved_at_60[0x10];
e281682b
SM		 6345 u8 vxlan_udp_port[0x10];
6346};
6347
6348struct mlx5_ifc_delete_l2_table_entry_out_bits {
6349 u8 status[0x8];
b4ff3a36 6350 u8 reserved_at_8[0x18];
e281682b
SM		 6351
6352 u8 syndrome[0x20];
6353
b4ff3a36 6354 u8 reserved_at_40[0x40];
e281682b
SM		 6355};
6356
6357struct mlx5_ifc_delete_l2_table_entry_in_bits {
6358 u8 opcode[0x10];
b4ff3a36 6359 u8 reserved_at_10[0x10];
e281682b 6360
b4ff3a36 6361 u8 reserved_at_20[0x10];
e281682b
SM		 6362 u8 op_mod[0x10];
6363
b4ff3a36 6364 u8 reserved_at_40[0x60];
e281682b 6365
b4ff3a36 6366 u8 reserved_at_a0[0x8];
e281682b
SM		 6367 u8 table_index[0x18];
6368
b4ff3a36 6369 u8 reserved_at_c0[0x140];
e281682b
SM		 6370};
6371
6372struct mlx5_ifc_delete_fte_out_bits {
6373 u8 status[0x8];
b4ff3a36 6374 u8 reserved_at_8[0x18];
e281682b
SM		 6375
6376 u8 syndrome[0x20];
6377
b4ff3a36 6378 u8 reserved_at_40[0x40];
e281682b
SM		 6379};
6380
6381struct mlx5_ifc_delete_fte_in_bits {
6382 u8 opcode[0x10];
b4ff3a36 6383 u8 reserved_at_10[0x10];
e281682b 6384
b4ff3a36 6385 u8 reserved_at_20[0x10];
e281682b
SM		 6386 u8 op_mod[0x10];
6387
7d5e1423
SM		 6388 u8 other_vport[0x1];
6389 u8 reserved_at_41[0xf];
6390 u8 vport_number[0x10];
6391
6392 u8 reserved_at_60[0x20];
e281682b
SM		 6393
6394 u8 table_type[0x8];
b4ff3a36 6395 u8 reserved_at_88[0x18];
e281682b 6396
b4ff3a36 6397 u8 reserved_at_a0[0x8];
e281682b
SM		 6398 u8 table_id[0x18];
6399
b4ff3a36 6400 u8 reserved_at_c0[0x40];
e281682b
SM		 6401
6402 u8 flow_index[0x20];
6403
b4ff3a36 6404 u8 reserved_at_120[0xe0];
e281682b
SM		 6405};
6406
6407struct mlx5_ifc_dealloc_xrcd_out_bits {
6408 u8 status[0x8];
b4ff3a36 6409 u8 reserved_at_8[0x18];
e281682b
SM		 6410
6411 u8 syndrome[0x20];
6412
b4ff3a36 6413 u8 reserved_at_40[0x40];
e281682b
SM		 6414};
6415
6416struct mlx5_ifc_dealloc_xrcd_in_bits {
6417 u8 opcode[0x10];
b4ff3a36 6418 u8 reserved_at_10[0x10];
e281682b 6419
b4ff3a36 6420 u8 reserved_at_20[0x10];
e281682b
SM		 6421 u8 op_mod[0x10];
6422
b4ff3a36 6423 u8 reserved_at_40[0x8];
e281682b
SM		 6424 u8 xrcd[0x18];
6425
b4ff3a36 6426 u8 reserved_at_60[0x20];
e281682b
SM		 6427};
6428
6429struct mlx5_ifc_dealloc_uar_out_bits {
6430 u8 status[0x8];
b4ff3a36 6431 u8 reserved_at_8[0x18];
e281682b
SM		 6432
6433 u8 syndrome[0x20];
6434
b4ff3a36 6435 u8 reserved_at_40[0x40];
e281682b
SM		 6436};
6437
6438struct mlx5_ifc_dealloc_uar_in_bits {
6439 u8 opcode[0x10];
b4ff3a36 6440 u8 reserved_at_10[0x10];
e281682b 6441
b4ff3a36 6442 u8 reserved_at_20[0x10];
e281682b
SM		 6443 u8 op_mod[0x10];
6444
b4ff3a36 6445 u8 reserved_at_40[0x8];
e281682b
SM		 6446 u8 uar[0x18];
6447
b4ff3a36 6448 u8 reserved_at_60[0x20];
e281682b
SM		 6449};
6450
6451struct mlx5_ifc_dealloc_transport_domain_out_bits {
6452 u8 status[0x8];
b4ff3a36 6453 u8 reserved_at_8[0x18];
e281682b
SM		 6454
6455 u8 syndrome[0x20];
6456
b4ff3a36 6457 u8 reserved_at_40[0x40];
e281682b
SM		 6458};
6459
6460struct mlx5_ifc_dealloc_transport_domain_in_bits {
6461 u8 opcode[0x10];
b4ff3a36 6462 u8 reserved_at_10[0x10];
e281682b 6463
b4ff3a36 6464 u8 reserved_at_20[0x10];
e281682b
SM		 6465 u8 op_mod[0x10];
6466
b4ff3a36 6467 u8 reserved_at_40[0x8];
e281682b
SM		 6468 u8 transport_domain[0x18];
6469
b4ff3a36 6470 u8 reserved_at_60[0x20];
e281682b
SM		 6471};
6472
6473struct mlx5_ifc_dealloc_q_counter_out_bits {
6474 u8 status[0x8];
b4ff3a36 6475 u8 reserved_at_8[0x18];
e281682b
SM		 6476
6477 u8 syndrome[0x20];
6478
b4ff3a36 6479 u8 reserved_at_40[0x40];
e281682b
SM		 6480};
6481
6482struct mlx5_ifc_dealloc_q_counter_in_bits {
6483 u8 opcode[0x10];
b4ff3a36 6484 u8 reserved_at_10[0x10];
e281682b 6485
b4ff3a36 6486 u8 reserved_at_20[0x10];
e281682b
SM		 6487 u8 op_mod[0x10];
6488
b4ff3a36 6489 u8 reserved_at_40[0x18];
e281682b
SM		 6490 u8 counter_set_id[0x8];
6491
b4ff3a36 6492 u8 reserved_at_60[0x20];
e281682b
SM		 6493};
6494
6495struct mlx5_ifc_dealloc_pd_out_bits {
6496 u8 status[0x8];
b4ff3a36 6497 u8 reserved_at_8[0x18];
e281682b
SM		 6498
6499 u8 syndrome[0x20];
6500
b4ff3a36 6501 u8 reserved_at_40[0x40];
e281682b
SM		 6502};
6503
6504struct mlx5_ifc_dealloc_pd_in_bits {
6505 u8 opcode[0x10];
b4ff3a36 6506 u8 reserved_at_10[0x10];
e281682b 6507
b4ff3a36 6508 u8 reserved_at_20[0x10];
e281682b
SM		 6509 u8 op_mod[0x10];
6510
b4ff3a36 6511 u8 reserved_at_40[0x8];
e281682b
SM		 6512 u8 pd[0x18];
6513
b4ff3a36 6514 u8 reserved_at_60[0x20];
e281682b
SM		 6515};
6516
9dc0b289
AV		 6517struct mlx5_ifc_dealloc_flow_counter_out_bits {
6518 u8 status[0x8];
6519 u8 reserved_at_8[0x18];
6520
6521 u8 syndrome[0x20];
6522
6523 u8 reserved_at_40[0x40];
6524};
6525
6526struct mlx5_ifc_dealloc_flow_counter_in_bits {
6527 u8 opcode[0x10];
6528 u8 reserved_at_10[0x10];
6529
6530 u8 reserved_at_20[0x10];
6531 u8 op_mod[0x10];
6532
a8ffcc74 6533 u8 flow_counter_id[0x20];
9dc0b289
AV		 6534
6535 u8 reserved_at_60[0x20];
6536};
6537
7486216b
SM		 6538struct mlx5_ifc_create_xrq_out_bits {
6539 u8 status[0x8];
6540 u8 reserved_at_8[0x18];
6541
6542 u8 syndrome[0x20];
6543
6544 u8 reserved_at_40[0x8];
6545 u8 xrqn[0x18];
6546
6547 u8 reserved_at_60[0x20];
6548};
6549
6550struct mlx5_ifc_create_xrq_in_bits {
6551 u8 opcode[0x10];
6552 u8 reserved_at_10[0x10];
6553
6554 u8 reserved_at_20[0x10];
6555 u8 op_mod[0x10];
6556
6557 u8 reserved_at_40[0x40];
6558
6559 struct mlx5_ifc_xrqc_bits xrq_context;
6560};
6561
e281682b
SM		 6562struct mlx5_ifc_create_xrc_srq_out_bits {
6563 u8 status[0x8];
b4ff3a36 6564 u8 reserved_at_8[0x18];
e281682b
SM		 6565
6566 u8 syndrome[0x20];
6567
b4ff3a36 6568 u8 reserved_at_40[0x8];
e281682b
SM		 6569 u8 xrc_srqn[0x18];
6570
b4ff3a36 6571 u8 reserved_at_60[0x20];
e281682b
SM		 6572};
6573
6574struct mlx5_ifc_create_xrc_srq_in_bits {
6575 u8 opcode[0x10];
b4ff3a36 6576 u8 reserved_at_10[0x10];
e281682b 6577
b4ff3a36 6578 u8 reserved_at_20[0x10];
e281682b
SM		 6579 u8 op_mod[0x10];
6580
b4ff3a36 6581 u8 reserved_at_40[0x40];
e281682b
SM		 6582
6583 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6584
b4ff3a36 6585 u8 reserved_at_280[0x600];
e281682b
SM		 6586
6587 u8 pas[0][0x40];
6588};
6589
6590struct mlx5_ifc_create_tis_out_bits {
6591 u8 status[0x8];
b4ff3a36 6592 u8 reserved_at_8[0x18];
e281682b
SM		 6593
6594 u8 syndrome[0x20];
6595
b4ff3a36 6596 u8 reserved_at_40[0x8];
e281682b
SM		 6597 u8 tisn[0x18];
6598
b4ff3a36 6599 u8 reserved_at_60[0x20];
e281682b
SM		 6600};
6601
6602struct mlx5_ifc_create_tis_in_bits {
6603 u8 opcode[0x10];
b4ff3a36 6604 u8 reserved_at_10[0x10];
e281682b 6605
b4ff3a36 6606 u8 reserved_at_20[0x10];
e281682b
SM		 6607 u8 op_mod[0x10];
6608
b4ff3a36 6609 u8 reserved_at_40[0xc0];
e281682b
SM		 6610
6611 struct mlx5_ifc_tisc_bits ctx;
6612};
6613
6614struct mlx5_ifc_create_tir_out_bits {
6615 u8 status[0x8];
b4ff3a36 6616 u8 reserved_at_8[0x18];
e281682b
SM		 6617
6618 u8 syndrome[0x20];
6619
b4ff3a36 6620 u8 reserved_at_40[0x8];
e281682b
SM		 6621 u8 tirn[0x18];
6622
b4ff3a36 6623 u8 reserved_at_60[0x20];
e281682b
SM		 6624};
6625
6626struct mlx5_ifc_create_tir_in_bits {
6627 u8 opcode[0x10];
b4ff3a36 6628 u8 reserved_at_10[0x10];
e281682b 6629
b4ff3a36 6630 u8 reserved_at_20[0x10];
e281682b
SM		 6631 u8 op_mod[0x10];
6632
b4ff3a36 6633 u8 reserved_at_40[0xc0];
e281682b
SM		 6634
6635 struct mlx5_ifc_tirc_bits ctx;
6636};
6637
6638struct mlx5_ifc_create_srq_out_bits {
6639 u8 status[0x8];
b4ff3a36 6640 u8 reserved_at_8[0x18];
e281682b
SM		 6641
6642 u8 syndrome[0x20];
6643
b4ff3a36 6644 u8 reserved_at_40[0x8];
e281682b
SM		 6645 u8 srqn[0x18];
6646
b4ff3a36 6647 u8 reserved_at_60[0x20];
e281682b
SM		 6648};
6649
6650struct mlx5_ifc_create_srq_in_bits {
6651 u8 opcode[0x10];
b4ff3a36 6652 u8 reserved_at_10[0x10];
e281682b 6653
b4ff3a36 6654 u8 reserved_at_20[0x10];
e281682b
SM		 6655 u8 op_mod[0x10];
6656
b4ff3a36 6657 u8 reserved_at_40[0x40];
e281682b
SM		 6658
6659 struct mlx5_ifc_srqc_bits srq_context_entry;
6660
b4ff3a36 6661 u8 reserved_at_280[0x600];
e281682b
SM		 6662
6663 u8 pas[0][0x40];
6664};
6665
6666struct mlx5_ifc_create_sq_out_bits {
6667 u8 status[0x8];
b4ff3a36 6668 u8 reserved_at_8[0x18];
e281682b
SM		 6669
6670 u8 syndrome[0x20];
6671
b4ff3a36 6672 u8 reserved_at_40[0x8];
e281682b
SM		 6673 u8 sqn[0x18];
6674
b4ff3a36 6675 u8 reserved_at_60[0x20];
e281682b
SM		 6676};
6677
6678struct mlx5_ifc_create_sq_in_bits {
6679 u8 opcode[0x10];
b4ff3a36 6680 u8 reserved_at_10[0x10];
e281682b 6681
b4ff3a36 6682 u8 reserved_at_20[0x10];
e281682b
SM		 6683 u8 op_mod[0x10];
6684
b4ff3a36 6685 u8 reserved_at_40[0xc0];
e281682b
SM		 6686
6687 struct mlx5_ifc_sqc_bits ctx;
6688};
6689
813f8540
MHY		 6690struct mlx5_ifc_create_scheduling_element_out_bits {
6691 u8 status[0x8];
6692 u8 reserved_at_8[0x18];
6693
6694 u8 syndrome[0x20];
6695
6696 u8 reserved_at_40[0x40];
6697
6698 u8 scheduling_element_id[0x20];
6699
6700 u8 reserved_at_a0[0x160];
6701};
6702
6703struct mlx5_ifc_create_scheduling_element_in_bits {
6704 u8 opcode[0x10];
6705 u8 reserved_at_10[0x10];
6706
6707 u8 reserved_at_20[0x10];
6708 u8 op_mod[0x10];
6709
6710 u8 scheduling_hierarchy[0x8];
6711 u8 reserved_at_48[0x18];
6712
6713 u8 reserved_at_60[0xa0];
6714
6715 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6716
6717 u8 reserved_at_300[0x100];
6718};
6719
e281682b
SM		 6720struct mlx5_ifc_create_rqt_out_bits {
6721 u8 status[0x8];
b4ff3a36 6722 u8 reserved_at_8[0x18];
e281682b
SM		 6723
6724 u8 syndrome[0x20];
6725
b4ff3a36 6726 u8 reserved_at_40[0x8];
e281682b
SM		 6727 u8 rqtn[0x18];
6728
b4ff3a36 6729 u8 reserved_at_60[0x20];
e281682b
SM		 6730};
6731
6732struct mlx5_ifc_create_rqt_in_bits {
6733 u8 opcode[0x10];
b4ff3a36 6734 u8 reserved_at_10[0x10];
e281682b 6735
b4ff3a36 6736 u8 reserved_at_20[0x10];
e281682b
SM		 6737 u8 op_mod[0x10];
6738
b4ff3a36 6739 u8 reserved_at_40[0xc0];
e281682b
SM		 6740
6741 struct mlx5_ifc_rqtc_bits rqt_context;
6742};
6743
6744struct mlx5_ifc_create_rq_out_bits {
6745 u8 status[0x8];
b4ff3a36 6746 u8 reserved_at_8[0x18];
e281682b
SM		 6747
6748 u8 syndrome[0x20];
6749
b4ff3a36 6750 u8 reserved_at_40[0x8];
e281682b
SM		 6751 u8 rqn[0x18];
6752
b4ff3a36 6753 u8 reserved_at_60[0x20];
e281682b
SM		 6754};
6755
6756struct mlx5_ifc_create_rq_in_bits {
6757 u8 opcode[0x10];
b4ff3a36 6758 u8 reserved_at_10[0x10];
e281682b 6759
b4ff3a36 6760 u8 reserved_at_20[0x10];
e281682b
SM		 6761 u8 op_mod[0x10];
6762
b4ff3a36 6763 u8 reserved_at_40[0xc0];
e281682b
SM		 6764
6765 struct mlx5_ifc_rqc_bits ctx;
6766};
6767
6768struct mlx5_ifc_create_rmp_out_bits {
6769 u8 status[0x8];
b4ff3a36 6770 u8 reserved_at_8[0x18];
e281682b
SM		 6771
6772 u8 syndrome[0x20];
6773
b4ff3a36 6774 u8 reserved_at_40[0x8];
e281682b
SM		 6775 u8 rmpn[0x18];
6776
b4ff3a36 6777 u8 reserved_at_60[0x20];
e281682b
SM		 6778};
6779
6780struct mlx5_ifc_create_rmp_in_bits {
6781 u8 opcode[0x10];
b4ff3a36 6782 u8 reserved_at_10[0x10];
e281682b 6783
b4ff3a36 6784 u8 reserved_at_20[0x10];
e281682b
SM		 6785 u8 op_mod[0x10];
6786
b4ff3a36 6787 u8 reserved_at_40[0xc0];
e281682b
SM		 6788
6789 struct mlx5_ifc_rmpc_bits ctx;
6790};
6791
6792struct mlx5_ifc_create_qp_out_bits {
6793 u8 status[0x8];
b4ff3a36 6794 u8 reserved_at_8[0x18];
e281682b
SM		 6795
6796 u8 syndrome[0x20];
6797
b4ff3a36 6798 u8 reserved_at_40[0x8];
e281682b
SM		 6799 u8 qpn[0x18];
6800
b4ff3a36 6801 u8 reserved_at_60[0x20];
e281682b
SM		 6802};
6803
6804struct mlx5_ifc_create_qp_in_bits {
6805 u8 opcode[0x10];
b4ff3a36 6806 u8 reserved_at_10[0x10];
e281682b 6807
b4ff3a36 6808 u8 reserved_at_20[0x10];
e281682b
SM		 6809 u8 op_mod[0x10];
6810
b4ff3a36 6811 u8 reserved_at_40[0x40];
e281682b
SM		 6812
6813 u8 opt_param_mask[0x20];
6814
b4ff3a36 6815 u8 reserved_at_a0[0x20];
e281682b
SM		 6816
6817 struct mlx5_ifc_qpc_bits qpc;
6818
b4ff3a36 6819 u8 reserved_at_800[0x80];
e281682b
SM		 6820
6821 u8 pas[0][0x40];
6822};
6823
6824struct mlx5_ifc_create_psv_out_bits {
6825 u8 status[0x8];
b4ff3a36 6826 u8 reserved_at_8[0x18];
e281682b
SM		 6827
6828 u8 syndrome[0x20];
6829
b4ff3a36 6830 u8 reserved_at_40[0x40];
e281682b 6831
b4ff3a36 6832 u8 reserved_at_80[0x8];
e281682b
SM		 6833 u8 psv0_index[0x18];
6834
b4ff3a36 6835 u8 reserved_at_a0[0x8];
e281682b
SM		 6836 u8 psv1_index[0x18];
6837
b4ff3a36 6838 u8 reserved_at_c0[0x8];
e281682b
SM		 6839 u8 psv2_index[0x18];
6840
b4ff3a36 6841 u8 reserved_at_e0[0x8];
e281682b
SM		 6842 u8 psv3_index[0x18];
6843};
6844
6845struct mlx5_ifc_create_psv_in_bits {
6846 u8 opcode[0x10];
b4ff3a36 6847 u8 reserved_at_10[0x10];
e281682b 6848
b4ff3a36 6849 u8 reserved_at_20[0x10];
e281682b
SM		 6850 u8 op_mod[0x10];
6851
6852 u8 num_psv[0x4];
b4ff3a36 6853 u8 reserved_at_44[0x4];
e281682b
SM		 6854 u8 pd[0x18];
6855
b4ff3a36 6856 u8 reserved_at_60[0x20];
e281682b
SM		 6857};
6858
6859struct mlx5_ifc_create_mkey_out_bits {
6860 u8 status[0x8];
b4ff3a36 6861 u8 reserved_at_8[0x18];
e281682b
SM		 6862
6863 u8 syndrome[0x20];
6864
b4ff3a36 6865 u8 reserved_at_40[0x8];
e281682b
SM		 6866 u8 mkey_index[0x18];
6867
b4ff3a36 6868 u8 reserved_at_60[0x20];
e281682b
SM		 6869};
6870
6871struct mlx5_ifc_create_mkey_in_bits {
6872 u8 opcode[0x10];
b4ff3a36 6873 u8 reserved_at_10[0x10];
e281682b 6874
b4ff3a36 6875 u8 reserved_at_20[0x10];
e281682b
SM		 6876 u8 op_mod[0x10];
6877
b4ff3a36 6878 u8 reserved_at_40[0x20];
e281682b
SM		 6879
6880 u8 pg_access[0x1];
b4ff3a36 6881 u8 reserved_at_61[0x1f];
e281682b
SM		 6882
6883 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6884
b4ff3a36 6885 u8 reserved_at_280[0x80];
e281682b
SM		 6886
6887 u8 translations_octword_actual_size[0x20];
6888
b4ff3a36 6889 u8 reserved_at_320[0x560];
e281682b
SM		 6890
6891 u8 klm_pas_mtt[0][0x20];
6892};
6893
6894struct mlx5_ifc_create_flow_table_out_bits {
6895 u8 status[0x8];
b4ff3a36 6896 u8 reserved_at_8[0x18];
e281682b
SM		 6897
6898 u8 syndrome[0x20];
6899
b4ff3a36 6900 u8 reserved_at_40[0x8];
e281682b
SM		 6901 u8 table_id[0x18];
6902
b4ff3a36 6903 u8 reserved_at_60[0x20];
e281682b
SM		 6904};
6905
0c90e9c6
MG		 6906struct mlx5_ifc_flow_table_context_bits {
6907 u8 encap_en[0x1];
6908 u8 decap_en[0x1];
6909 u8 reserved_at_2[0x2];
6910 u8 table_miss_action[0x4];
6911 u8 level[0x8];
6912 u8 reserved_at_10[0x8];
6913 u8 log_size[0x8];
6914
6915 u8 reserved_at_20[0x8];
6916 u8 table_miss_id[0x18];
6917
6918 u8 reserved_at_40[0x8];
6919 u8 lag_master_next_table_id[0x18];
6920
6921 u8 reserved_at_60[0xe0];
6922};
6923
e281682b
SM		 6924struct mlx5_ifc_create_flow_table_in_bits {
6925 u8 opcode[0x10];
b4ff3a36 6926 u8 reserved_at_10[0x10];
e281682b 6927
b4ff3a36 6928 u8 reserved_at_20[0x10];
e281682b
SM		 6929 u8 op_mod[0x10];
6930
7d5e1423
SM		 6931 u8 other_vport[0x1];
6932 u8 reserved_at_41[0xf];
6933 u8 vport_number[0x10];
6934
6935 u8 reserved_at_60[0x20];
e281682b
SM		 6936
6937 u8 table_type[0x8];
b4ff3a36 6938 u8 reserved_at_88[0x18];
e281682b 6939
b4ff3a36 6940 u8 reserved_at_a0[0x20];
e281682b 6941
0c90e9c6 6942 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6943};
6944
6945struct mlx5_ifc_create_flow_group_out_bits {
6946 u8 status[0x8];
b4ff3a36 6947 u8 reserved_at_8[0x18];
e281682b
SM		 6948
6949 u8 syndrome[0x20];
6950
b4ff3a36 6951 u8 reserved_at_40[0x8];
e281682b
SM		 6952 u8 group_id[0x18];
6953
b4ff3a36 6954 u8 reserved_at_60[0x20];
e281682b
SM		 6955};
6956
6957enum {
6958 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6959 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6960 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6961};
6962
6963struct mlx5_ifc_create_flow_group_in_bits {
6964 u8 opcode[0x10];
b4ff3a36 6965 u8 reserved_at_10[0x10];
e281682b 6966
b4ff3a36 6967 u8 reserved_at_20[0x10];
e281682b
SM		 6968 u8 op_mod[0x10];
6969
7d5e1423
SM		 6970 u8 other_vport[0x1];
6971 u8 reserved_at_41[0xf];
6972 u8 vport_number[0x10];
6973
6974 u8 reserved_at_60[0x20];
e281682b
SM		 6975
6976 u8 table_type[0x8];
b4ff3a36 6977 u8 reserved_at_88[0x18];
e281682b 6978
b4ff3a36 6979 u8 reserved_at_a0[0x8];
e281682b
SM		 6980 u8 table_id[0x18];
6981
3e99df87
SK		 6982 u8 source_eswitch_owner_vhca_id_valid[0x1];
6983
6984 u8 reserved_at_c1[0x1f];
e281682b
SM		 6985
6986 u8 start_flow_index[0x20];
6987
b4ff3a36 6988 u8 reserved_at_100[0x20];
e281682b
SM		 6989
6990 u8 end_flow_index[0x20];
6991
b4ff3a36 6992 u8 reserved_at_140[0xa0];
e281682b 6993
b4ff3a36 6994 u8 reserved_at_1e0[0x18];
e281682b
SM		 6995 u8 match_criteria_enable[0x8];
6996
6997 struct mlx5_ifc_fte_match_param_bits match_criteria;
6998
b4ff3a36 6999 u8 reserved_at_1200[0xe00];
e281682b
SM		 7000};
7001
7002struct mlx5_ifc_create_eq_out_bits {
7003 u8 status[0x8];
b4ff3a36 7004 u8 reserved_at_8[0x18];
e281682b
SM		 7005
7006 u8 syndrome[0x20];
7007
b4ff3a36 7008 u8 reserved_at_40[0x18];
e281682b
SM		 7009 u8 eq_number[0x8];
7010
b4ff3a36 7011 u8 reserved_at_60[0x20];
e281682b
SM		 7012};
7013
7014struct mlx5_ifc_create_eq_in_bits {
7015 u8 opcode[0x10];
b4ff3a36 7016 u8 reserved_at_10[0x10];
e281682b 7017
b4ff3a36 7018 u8 reserved_at_20[0x10];
e281682b
SM		 7019 u8 op_mod[0x10];
7020
b4ff3a36 7021 u8 reserved_at_40[0x40];
e281682b
SM		 7022
7023 struct mlx5_ifc_eqc_bits eq_context_entry;
7024
b4ff3a36 7025 u8 reserved_at_280[0x40];
e281682b
SM		 7026
7027 u8 event_bitmask[0x40];
7028
b4ff3a36 7029 u8 reserved_at_300[0x580];
e281682b
SM		 7030
7031 u8 pas[0][0x40];
7032};
7033
7034struct mlx5_ifc_create_dct_out_bits {
7035 u8 status[0x8];
b4ff3a36 7036 u8 reserved_at_8[0x18];
e281682b
SM		 7037
7038 u8 syndrome[0x20];
7039
b4ff3a36 7040 u8 reserved_at_40[0x8];
e281682b
SM		 7041 u8 dctn[0x18];
7042
b4ff3a36 7043 u8 reserved_at_60[0x20];
e281682b
SM		 7044};
7045
7046struct mlx5_ifc_create_dct_in_bits {
7047 u8 opcode[0x10];
b4ff3a36 7048 u8 reserved_at_10[0x10];
e281682b 7049
b4ff3a36 7050 u8 reserved_at_20[0x10];
e281682b
SM		 7051 u8 op_mod[0x10];
7052
b4ff3a36 7053 u8 reserved_at_40[0x40];
e281682b
SM		 7054
7055 struct mlx5_ifc_dctc_bits dct_context_entry;
7056
b4ff3a36 7057 u8 reserved_at_280[0x180];
e281682b
SM		 7058};
7059
7060struct mlx5_ifc_create_cq_out_bits {
7061 u8 status[0x8];
b4ff3a36 7062 u8 reserved_at_8[0x18];
e281682b
SM		 7063
7064 u8 syndrome[0x20];
7065
b4ff3a36 7066 u8 reserved_at_40[0x8];
e281682b
SM		 7067 u8 cqn[0x18];
7068
b4ff3a36 7069 u8 reserved_at_60[0x20];
e281682b
SM		 7070};
7071
7072struct mlx5_ifc_create_cq_in_bits {
7073 u8 opcode[0x10];
b4ff3a36 7074 u8 reserved_at_10[0x10];
e281682b 7075
b4ff3a36 7076 u8 reserved_at_20[0x10];
e281682b
SM		 7077 u8 op_mod[0x10];
7078
b4ff3a36 7079 u8 reserved_at_40[0x40];
e281682b
SM		 7080
7081 struct mlx5_ifc_cqc_bits cq_context;
7082
b4ff3a36 7083 u8 reserved_at_280[0x600];
e281682b
SM		 7084
7085 u8 pas[0][0x40];
7086};
7087
7088struct mlx5_ifc_config_int_moderation_out_bits {
7089 u8 status[0x8];
b4ff3a36 7090 u8 reserved_at_8[0x18];
e281682b
SM		 7091
7092 u8 syndrome[0x20];
7093
b4ff3a36 7094 u8 reserved_at_40[0x4];
e281682b
SM		 7095 u8 min_delay[0xc];
7096 u8 int_vector[0x10];
7097
b4ff3a36 7098 u8 reserved_at_60[0x20];
e281682b
SM		 7099};
7100
7101enum {
7102 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7103 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7104};
7105
7106struct mlx5_ifc_config_int_moderation_in_bits {
7107 u8 opcode[0x10];
b4ff3a36 7108 u8 reserved_at_10[0x10];
e281682b 7109
b4ff3a36 7110 u8 reserved_at_20[0x10];
e281682b
SM		 7111 u8 op_mod[0x10];
7112
b4ff3a36 7113 u8 reserved_at_40[0x4];
e281682b
SM		 7114 u8 min_delay[0xc];
7115 u8 int_vector[0x10];
7116
b4ff3a36 7117 u8 reserved_at_60[0x20];
e281682b
SM		 7118};
7119
7120struct mlx5_ifc_attach_to_mcg_out_bits {
7121 u8 status[0x8];
b4ff3a36 7122 u8 reserved_at_8[0x18];
e281682b
SM		 7123
7124 u8 syndrome[0x20];
7125
b4ff3a36 7126 u8 reserved_at_40[0x40];
e281682b
SM		 7127};
7128
7129struct mlx5_ifc_attach_to_mcg_in_bits {
7130 u8 opcode[0x10];
b4ff3a36 7131 u8 reserved_at_10[0x10];
e281682b 7132
b4ff3a36 7133 u8 reserved_at_20[0x10];
e281682b
SM		 7134 u8 op_mod[0x10];
7135
b4ff3a36 7136 u8 reserved_at_40[0x8];
e281682b
SM		 7137 u8 qpn[0x18];
7138
b4ff3a36 7139 u8 reserved_at_60[0x20];
e281682b
SM		 7140
7141 u8 multicast_gid[16][0x8];
7142};
7143
7486216b
SM		 7144struct mlx5_ifc_arm_xrq_out_bits {
7145 u8 status[0x8];
7146 u8 reserved_at_8[0x18];
7147
7148 u8 syndrome[0x20];
7149
7150 u8 reserved_at_40[0x40];
7151};
7152
7153struct mlx5_ifc_arm_xrq_in_bits {
7154 u8 opcode[0x10];
7155 u8 reserved_at_10[0x10];
7156
7157 u8 reserved_at_20[0x10];
7158 u8 op_mod[0x10];
7159
7160 u8 reserved_at_40[0x8];
7161 u8 xrqn[0x18];
7162
7163 u8 reserved_at_60[0x10];
7164 u8 lwm[0x10];
7165};
7166
e281682b
SM		 7167struct mlx5_ifc_arm_xrc_srq_out_bits {
7168 u8 status[0x8];
b4ff3a36 7169 u8 reserved_at_8[0x18];
e281682b
SM		 7170
7171 u8 syndrome[0x20];
7172
b4ff3a36 7173 u8 reserved_at_40[0x40];
e281682b
SM		 7174};
7175
7176enum {
7177 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7178};
7179
7180struct mlx5_ifc_arm_xrc_srq_in_bits {
7181 u8 opcode[0x10];
b4ff3a36 7182 u8 reserved_at_10[0x10];
e281682b 7183
b4ff3a36 7184 u8 reserved_at_20[0x10];
e281682b
SM		 7185 u8 op_mod[0x10];
7186
b4ff3a36 7187 u8 reserved_at_40[0x8];
e281682b
SM		 7188 u8 xrc_srqn[0x18];
7189
b4ff3a36 7190 u8 reserved_at_60[0x10];
e281682b
SM		 7191 u8 lwm[0x10];
7192};
7193
7194struct mlx5_ifc_arm_rq_out_bits {
7195 u8 status[0x8];
b4ff3a36 7196 u8 reserved_at_8[0x18];
e281682b
SM		 7197
7198 u8 syndrome[0x20];
7199
b4ff3a36 7200 u8 reserved_at_40[0x40];
e281682b
SM		 7201};
7202
7203enum {
7486216b
SM		 7204 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7205 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7206};
7207
7208struct mlx5_ifc_arm_rq_in_bits {
7209 u8 opcode[0x10];
b4ff3a36 7210 u8 reserved_at_10[0x10];
e281682b 7211
b4ff3a36 7212 u8 reserved_at_20[0x10];
e281682b
SM		 7213 u8 op_mod[0x10];
7214
b4ff3a36 7215 u8 reserved_at_40[0x8];
e281682b
SM		 7216 u8 srq_number[0x18];
7217
b4ff3a36 7218 u8 reserved_at_60[0x10];
e281682b
SM		 7219 u8 lwm[0x10];
7220};
7221
7222struct mlx5_ifc_arm_dct_out_bits {
7223 u8 status[0x8];
b4ff3a36 7224 u8 reserved_at_8[0x18];
e281682b
SM		 7225
7226 u8 syndrome[0x20];
7227
b4ff3a36 7228 u8 reserved_at_40[0x40];
e281682b
SM		 7229};
7230
7231struct mlx5_ifc_arm_dct_in_bits {
7232 u8 opcode[0x10];
b4ff3a36 7233 u8 reserved_at_10[0x10];
e281682b 7234
b4ff3a36 7235 u8 reserved_at_20[0x10];
e281682b
SM		 7236 u8 op_mod[0x10];
7237
b4ff3a36 7238 u8 reserved_at_40[0x8];
e281682b
SM		 7239 u8 dct_number[0x18];
7240
b4ff3a36 7241 u8 reserved_at_60[0x20];
e281682b
SM		 7242};
7243
7244struct mlx5_ifc_alloc_xrcd_out_bits {
7245 u8 status[0x8];
b4ff3a36 7246 u8 reserved_at_8[0x18];
e281682b
SM		 7247
7248 u8 syndrome[0x20];
7249
b4ff3a36 7250 u8 reserved_at_40[0x8];
e281682b
SM		 7251 u8 xrcd[0x18];
7252
b4ff3a36 7253 u8 reserved_at_60[0x20];
e281682b
SM		 7254};
7255
7256struct mlx5_ifc_alloc_xrcd_in_bits {
7257 u8 opcode[0x10];
b4ff3a36 7258 u8 reserved_at_10[0x10];
e281682b 7259
b4ff3a36 7260 u8 reserved_at_20[0x10];
e281682b
SM		 7261 u8 op_mod[0x10];
7262
b4ff3a36 7263 u8 reserved_at_40[0x40];
e281682b
SM		 7264};
7265
7266struct mlx5_ifc_alloc_uar_out_bits {
7267 u8 status[0x8];
b4ff3a36 7268 u8 reserved_at_8[0x18];
e281682b
SM		 7269
7270 u8 syndrome[0x20];
7271
b4ff3a36 7272 u8 reserved_at_40[0x8];
e281682b
SM		 7273 u8 uar[0x18];
7274
b4ff3a36 7275 u8 reserved_at_60[0x20];
e281682b
SM		 7276};
7277
7278struct mlx5_ifc_alloc_uar_in_bits {
7279 u8 opcode[0x10];
b4ff3a36 7280 u8 reserved_at_10[0x10];
e281682b 7281
b4ff3a36 7282 u8 reserved_at_20[0x10];
e281682b
SM		 7283 u8 op_mod[0x10];
7284
b4ff3a36 7285 u8 reserved_at_40[0x40];
e281682b
SM		 7286};
7287
7288struct mlx5_ifc_alloc_transport_domain_out_bits {
7289 u8 status[0x8];
b4ff3a36 7290 u8 reserved_at_8[0x18];
e281682b
SM		 7291
7292 u8 syndrome[0x20];
7293
b4ff3a36 7294 u8 reserved_at_40[0x8];
e281682b
SM		 7295 u8 transport_domain[0x18];
7296
b4ff3a36 7297 u8 reserved_at_60[0x20];
e281682b
SM		 7298};
7299
7300struct mlx5_ifc_alloc_transport_domain_in_bits {
7301 u8 opcode[0x10];
b4ff3a36 7302 u8 reserved_at_10[0x10];
e281682b 7303
b4ff3a36 7304 u8 reserved_at_20[0x10];
e281682b
SM		 7305 u8 op_mod[0x10];
7306
b4ff3a36 7307 u8 reserved_at_40[0x40];
e281682b
SM		 7308};
7309
7310struct mlx5_ifc_alloc_q_counter_out_bits {
7311 u8 status[0x8];
b4ff3a36 7312 u8 reserved_at_8[0x18];
e281682b
SM		 7313
7314 u8 syndrome[0x20];
7315
b4ff3a36 7316 u8 reserved_at_40[0x18];
e281682b
SM		 7317 u8 counter_set_id[0x8];
7318
b4ff3a36 7319 u8 reserved_at_60[0x20];
e281682b
SM		 7320};
7321
7322struct mlx5_ifc_alloc_q_counter_in_bits {
7323 u8 opcode[0x10];
b4ff3a36 7324 u8 reserved_at_10[0x10];
e281682b 7325
b4ff3a36 7326 u8 reserved_at_20[0x10];
e281682b
SM		 7327 u8 op_mod[0x10];
7328
b4ff3a36 7329 u8 reserved_at_40[0x40];
e281682b
SM		 7330};
7331
7332struct mlx5_ifc_alloc_pd_out_bits {
7333 u8 status[0x8];
b4ff3a36 7334 u8 reserved_at_8[0x18];
e281682b
SM		 7335
7336 u8 syndrome[0x20];
7337
b4ff3a36 7338 u8 reserved_at_40[0x8];
e281682b
SM		 7339 u8 pd[0x18];
7340
b4ff3a36 7341 u8 reserved_at_60[0x20];
e281682b
SM		 7342};
7343
7344struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7345 u8 opcode[0x10];
7346 u8 reserved_at_10[0x10];
7347
7348 u8 reserved_at_20[0x10];
7349 u8 op_mod[0x10];
7350
7351 u8 reserved_at_40[0x40];
7352};
7353
7354struct mlx5_ifc_alloc_flow_counter_out_bits {
7355 u8 status[0x8];
7356 u8 reserved_at_8[0x18];
7357
7358 u8 syndrome[0x20];
7359
a8ffcc74 7360 u8 flow_counter_id[0x20];
9dc0b289
AV		 7361
7362 u8 reserved_at_60[0x20];
7363};
7364
7365struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7366 u8 opcode[0x10];
b4ff3a36 7367 u8 reserved_at_10[0x10];
e281682b 7368
b4ff3a36 7369 u8 reserved_at_20[0x10];
e281682b
SM		 7370 u8 op_mod[0x10];
7371
b4ff3a36 7372 u8 reserved_at_40[0x40];
e281682b
SM		 7373};
7374
7375struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7376 u8 status[0x8];
b4ff3a36 7377 u8 reserved_at_8[0x18];
e281682b
SM		 7378
7379 u8 syndrome[0x20];
7380
b4ff3a36 7381 u8 reserved_at_40[0x40];
e281682b
SM		 7382};
7383
7384struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7385 u8 opcode[0x10];
b4ff3a36 7386 u8 reserved_at_10[0x10];
e281682b 7387
b4ff3a36 7388 u8 reserved_at_20[0x10];
e281682b
SM		 7389 u8 op_mod[0x10];
7390
b4ff3a36 7391 u8 reserved_at_40[0x20];
e281682b 7392
b4ff3a36 7393 u8 reserved_at_60[0x10];
e281682b
SM		 7394 u8 vxlan_udp_port[0x10];
7395};
7396
37e92a9d 7397struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7398 u8 status[0x8];
7399 u8 reserved_at_8[0x18];
7400
7401 u8 syndrome[0x20];
7402
7403 u8 reserved_at_40[0x40];
7404};
7405
37e92a9d 7406struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7407 u8 opcode[0x10];
7408 u8 reserved_at_10[0x10];
7409
7410 u8 reserved_at_20[0x10];
7411 u8 op_mod[0x10];
7412
7413 u8 reserved_at_40[0x10];
7414 u8 rate_limit_index[0x10];
7415
7416 u8 reserved_at_60[0x20];
7417
7418 u8 rate_limit[0x20];
37e92a9d 7419
05d3ac97
BW		 7420 u8 burst_upper_bound[0x20];
7421
7422 u8 reserved_at_c0[0x10];
7423 u8 typical_packet_size[0x10];
7424
7425 u8 reserved_at_e0[0x120];
7486216b
SM		 7426};
7427
e281682b
SM		 7428struct mlx5_ifc_access_register_out_bits {
7429 u8 status[0x8];
b4ff3a36 7430 u8 reserved_at_8[0x18];
e281682b
SM		 7431
7432 u8 syndrome[0x20];
7433
b4ff3a36 7434 u8 reserved_at_40[0x40];
e281682b
SM		 7435
7436 u8 register_data[0][0x20];
7437};
7438
7439enum {
7440 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7441 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7442};
7443
7444struct mlx5_ifc_access_register_in_bits {
7445 u8 opcode[0x10];
b4ff3a36 7446 u8 reserved_at_10[0x10];
e281682b 7447
b4ff3a36 7448 u8 reserved_at_20[0x10];
e281682b
SM		 7449 u8 op_mod[0x10];
7450
b4ff3a36 7451 u8 reserved_at_40[0x10];
e281682b
SM		 7452 u8 register_id[0x10];
7453
7454 u8 argument[0x20];
7455
7456 u8 register_data[0][0x20];
7457};
7458
7459struct mlx5_ifc_sltp_reg_bits {
7460 u8 status[0x4];
7461 u8 version[0x4];
7462 u8 local_port[0x8];
7463 u8 pnat[0x2];
b4ff3a36 7464 u8 reserved_at_12[0x2];
e281682b 7465 u8 lane[0x4];
b4ff3a36 7466 u8 reserved_at_18[0x8];
e281682b 7467
b4ff3a36 7468 u8 reserved_at_20[0x20];
e281682b 7469
b4ff3a36 7470 u8 reserved_at_40[0x7];
e281682b
SM		 7471 u8 polarity[0x1];
7472 u8 ob_tap0[0x8];
7473 u8 ob_tap1[0x8];
7474 u8 ob_tap2[0x8];
7475
b4ff3a36 7476 u8 reserved_at_60[0xc];
e281682b
SM		 7477 u8 ob_preemp_mode[0x4];
7478 u8 ob_reg[0x8];
7479 u8 ob_bias[0x8];
7480
b4ff3a36 7481 u8 reserved_at_80[0x20];
e281682b
SM		 7482};
7483
7484struct mlx5_ifc_slrg_reg_bits {
7485 u8 status[0x4];
7486 u8 version[0x4];
7487 u8 local_port[0x8];
7488 u8 pnat[0x2];
b4ff3a36 7489 u8 reserved_at_12[0x2];
e281682b 7490 u8 lane[0x4];
b4ff3a36 7491 u8 reserved_at_18[0x8];
e281682b
SM		 7492
7493 u8 time_to_link_up[0x10];
b4ff3a36 7494 u8 reserved_at_30[0xc];
e281682b
SM		 7495 u8 grade_lane_speed[0x4];
7496
7497 u8 grade_version[0x8];
7498 u8 grade[0x18];
7499
b4ff3a36 7500 u8 reserved_at_60[0x4];
e281682b
SM		 7501 u8 height_grade_type[0x4];
7502 u8 height_grade[0x18];
7503
7504 u8 height_dz[0x10];
7505 u8 height_dv[0x10];
7506
b4ff3a36 7507 u8 reserved_at_a0[0x10];
e281682b
SM		 7508 u8 height_sigma[0x10];
7509
b4ff3a36 7510 u8 reserved_at_c0[0x20];
e281682b 7511
b4ff3a36 7512 u8 reserved_at_e0[0x4];
e281682b
SM		 7513 u8 phase_grade_type[0x4];
7514 u8 phase_grade[0x18];
7515
b4ff3a36 7516 u8 reserved_at_100[0x8];
e281682b 7517 u8 phase_eo_pos[0x8];
b4ff3a36 7518 u8 reserved_at_110[0x8];
e281682b
SM		 7519 u8 phase_eo_neg[0x8];
7520
7521 u8 ffe_set_tested[0x10];
7522 u8 test_errors_per_lane[0x10];
7523};
7524
7525struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7526 u8 reserved_at_0[0x8];
e281682b 7527 u8 local_port[0x8];
b4ff3a36 7528 u8 reserved_at_10[0x10];
e281682b 7529
b4ff3a36 7530 u8 reserved_at_20[0x1c];
e281682b
SM		 7531 u8 vl_hw_cap[0x4];
7532
b4ff3a36 7533 u8 reserved_at_40[0x1c];
e281682b
SM		 7534 u8 vl_admin[0x4];
7535
b4ff3a36 7536 u8 reserved_at_60[0x1c];
e281682b
SM		 7537 u8 vl_operational[0x4];
7538};
7539
7540struct mlx5_ifc_pude_reg_bits {
7541 u8 swid[0x8];
7542 u8 local_port[0x8];
b4ff3a36 7543 u8 reserved_at_10[0x4];
e281682b 7544 u8 admin_status[0x4];
b4ff3a36 7545 u8 reserved_at_18[0x4];
e281682b
SM		 7546 u8 oper_status[0x4];
7547
b4ff3a36 7548 u8 reserved_at_20[0x60];
e281682b
SM		 7549};
7550
7551struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7552 u8 reserved_at_0[0x1];
7486216b 7553 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7554 u8 an_disable_cap[0x1];
7555 u8 reserved_at_3[0x5];
e281682b 7556 u8 local_port[0x8];
b4ff3a36 7557 u8 reserved_at_10[0xd];
e281682b
SM		 7558 u8 proto_mask[0x3];
7559
7486216b
SM		 7560 u8 an_status[0x4];
7561 u8 reserved_at_24[0x3c];
e281682b
SM		 7562
7563 u8 eth_proto_capability[0x20];
7564
7565 u8 ib_link_width_capability[0x10];
7566 u8 ib_proto_capability[0x10];
7567
b4ff3a36 7568 u8 reserved_at_a0[0x20];
e281682b
SM		 7569
7570 u8 eth_proto_admin[0x20];
7571
7572 u8 ib_link_width_admin[0x10];
7573 u8 ib_proto_admin[0x10];
7574
b4ff3a36 7575 u8 reserved_at_100[0x20];
e281682b
SM		 7576
7577 u8 eth_proto_oper[0x20];
7578
7579 u8 ib_link_width_oper[0x10];
7580 u8 ib_proto_oper[0x10];
7581
5b4793f8
EBE		 7582 u8 reserved_at_160[0x1c];
7583 u8 connector_type[0x4];
e281682b
SM		 7584
7585 u8 eth_proto_lp_advertise[0x20];
7586
b4ff3a36 7587 u8 reserved_at_1a0[0x60];
e281682b
SM		 7588};
7589
7d5e1423
SM		 7590struct mlx5_ifc_mlcr_reg_bits {
7591 u8 reserved_at_0[0x8];
7592 u8 local_port[0x8];
7593 u8 reserved_at_10[0x20];
7594
7595 u8 beacon_duration[0x10];
7596 u8 reserved_at_40[0x10];
7597
7598 u8 beacon_remain[0x10];
7599};
7600
e281682b 7601struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7602 u8 reserved_at_0[0x20];
e281682b
SM		 7603
7604 u8 algorithm_options[0x10];
b4ff3a36 7605 u8 reserved_at_30[0x4];
e281682b
SM		 7606 u8 repetitions_mode[0x4];
7607 u8 num_of_repetitions[0x8];
7608
7609 u8 grade_version[0x8];
7610 u8 height_grade_type[0x4];
7611 u8 phase_grade_type[0x4];
7612 u8 height_grade_weight[0x8];
7613 u8 phase_grade_weight[0x8];
7614
7615 u8 gisim_measure_bits[0x10];
7616 u8 adaptive_tap_measure_bits[0x10];
7617
7618 u8 ber_bath_high_error_threshold[0x10];
7619 u8 ber_bath_mid_error_threshold[0x10];
7620
7621 u8 ber_bath_low_error_threshold[0x10];
7622 u8 one_ratio_high_threshold[0x10];
7623
7624 u8 one_ratio_high_mid_threshold[0x10];
7625 u8 one_ratio_low_mid_threshold[0x10];
7626
7627 u8 one_ratio_low_threshold[0x10];
7628 u8 ndeo_error_threshold[0x10];
7629
7630 u8 mixer_offset_step_size[0x10];
b4ff3a36 7631 u8 reserved_at_110[0x8];
e281682b
SM		 7632 u8 mix90_phase_for_voltage_bath[0x8];
7633
7634 u8 mixer_offset_start[0x10];
7635 u8 mixer_offset_end[0x10];
7636
b4ff3a36 7637 u8 reserved_at_140[0x15];
e281682b
SM		 7638 u8 ber_test_time[0xb];
7639};
7640
7641struct mlx5_ifc_pspa_reg_bits {
7642 u8 swid[0x8];
7643 u8 local_port[0x8];
7644 u8 sub_port[0x8];
b4ff3a36 7645 u8 reserved_at_18[0x8];
e281682b 7646
b4ff3a36 7647 u8 reserved_at_20[0x20];
e281682b
SM		 7648};
7649
7650struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7651 u8 reserved_at_0[0x8];
e281682b 7652 u8 local_port[0x8];
b4ff3a36 7653 u8 reserved_at_10[0x5];
e281682b 7654 u8 prio[0x3];
b4ff3a36 7655 u8 reserved_at_18[0x6];
e281682b
SM		 7656 u8 mode[0x2];
7657
b4ff3a36 7658 u8 reserved_at_20[0x20];
e281682b 7659
b4ff3a36 7660 u8 reserved_at_40[0x10];
e281682b
SM		 7661 u8 min_threshold[0x10];
7662
b4ff3a36 7663 u8 reserved_at_60[0x10];
e281682b
SM		 7664 u8 max_threshold[0x10];
7665
b4ff3a36 7666 u8 reserved_at_80[0x10];
e281682b
SM		 7667 u8 mark_probability_denominator[0x10];
7668
b4ff3a36 7669 u8 reserved_at_a0[0x60];
e281682b
SM		 7670};
7671
7672struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7673 u8 reserved_at_0[0x8];
e281682b 7674 u8 local_port[0x8];
b4ff3a36 7675 u8 reserved_at_10[0x10];
e281682b 7676
b4ff3a36 7677 u8 reserved_at_20[0x60];
e281682b 7678
b4ff3a36 7679 u8 reserved_at_80[0x1c];
e281682b
SM		 7680 u8 wrps_admin[0x4];
7681
b4ff3a36 7682 u8 reserved_at_a0[0x1c];
e281682b
SM		 7683 u8 wrps_status[0x4];
7684
b4ff3a36 7685 u8 reserved_at_c0[0x8];
e281682b 7686 u8 up_threshold[0x8];
b4ff3a36 7687 u8 reserved_at_d0[0x8];
e281682b
SM		 7688 u8 down_threshold[0x8];
7689
b4ff3a36 7690 u8 reserved_at_e0[0x20];
e281682b 7691
b4ff3a36 7692 u8 reserved_at_100[0x1c];
e281682b
SM		 7693 u8 srps_admin[0x4];
7694
b4ff3a36 7695 u8 reserved_at_120[0x1c];
e281682b
SM		 7696 u8 srps_status[0x4];
7697
b4ff3a36 7698 u8 reserved_at_140[0x40];
e281682b
SM		 7699};
7700
7701struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7702 u8 reserved_at_0[0x8];
e281682b 7703 u8 local_port[0x8];
b4ff3a36 7704 u8 reserved_at_10[0x10];
e281682b 7705
b4ff3a36 7706 u8 reserved_at_20[0x8];
e281682b 7707 u8 lb_cap[0x8];
b4ff3a36 7708 u8 reserved_at_30[0x8];
e281682b
SM		 7709 u8 lb_en[0x8];
7710};
7711
7712struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7713 u8 reserved_at_0[0x8];
e281682b 7714 u8 local_port[0x8];
b4ff3a36 7715 u8 reserved_at_10[0x10];
e281682b 7716
b4ff3a36 7717 u8 reserved_at_20[0x20];
e281682b
SM		 7718
7719 u8 port_profile_mode[0x8];
7720 u8 static_port_profile[0x8];
7721 u8 active_port_profile[0x8];
b4ff3a36 7722 u8 reserved_at_58[0x8];
e281682b
SM		 7723
7724 u8 retransmission_active[0x8];
7725 u8 fec_mode_active[0x18];
7726
b4ff3a36 7727 u8 reserved_at_80[0x20];
e281682b
SM		 7728};
7729
7730struct mlx5_ifc_ppcnt_reg_bits {
7731 u8 swid[0x8];
7732 u8 local_port[0x8];
7733 u8 pnat[0x2];
b4ff3a36 7734 u8 reserved_at_12[0x8];
e281682b
SM		 7735 u8 grp[0x6];
7736
7737 u8 clr[0x1];
b4ff3a36 7738 u8 reserved_at_21[0x1c];
e281682b
SM		 7739 u8 prio_tc[0x3];
7740
7741 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7742};
7743
8ed1a630
GP		 7744struct mlx5_ifc_mpcnt_reg_bits {
7745 u8 reserved_at_0[0x8];
7746 u8 pcie_index[0x8];
7747 u8 reserved_at_10[0xa];
7748 u8 grp[0x6];
7749
7750 u8 clr[0x1];
7751 u8 reserved_at_21[0x1f];
7752
7753 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7754};
7755
e281682b 7756struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7757 u8 reserved_at_0[0x3];
e281682b 7758 u8 single_mac[0x1];
b4ff3a36 7759 u8 reserved_at_4[0x4];
e281682b
SM		 7760 u8 local_port[0x8];
7761 u8 mac_47_32[0x10];
7762
7763 u8 mac_31_0[0x20];
7764
b4ff3a36 7765 u8 reserved_at_40[0x40];
e281682b
SM		 7766};
7767
7768struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7769 u8 reserved_at_0[0x8];
e281682b 7770 u8 local_port[0x8];
b4ff3a36 7771 u8 reserved_at_10[0x10];
e281682b
SM		 7772
7773 u8 max_mtu[0x10];
b4ff3a36 7774 u8 reserved_at_30[0x10];
e281682b
SM		 7775
7776 u8 admin_mtu[0x10];
b4ff3a36 7777 u8 reserved_at_50[0x10];
e281682b
SM		 7778
7779 u8 oper_mtu[0x10];
b4ff3a36 7780 u8 reserved_at_70[0x10];
e281682b
SM		 7781};
7782
7783struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7784 u8 reserved_at_0[0x8];
e281682b 7785 u8 module[0x8];
b4ff3a36 7786 u8 reserved_at_10[0x10];
e281682b 7787
b4ff3a36 7788 u8 reserved_at_20[0x18];
e281682b
SM		 7789 u8 attenuation_5g[0x8];
7790
b4ff3a36 7791 u8 reserved_at_40[0x18];
e281682b
SM		 7792 u8 attenuation_7g[0x8];
7793
b4ff3a36 7794 u8 reserved_at_60[0x18];
e281682b
SM		 7795 u8 attenuation_12g[0x8];
7796};
7797
7798struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7799 u8 reserved_at_0[0x8];
e281682b 7800 u8 module[0x8];
b4ff3a36 7801 u8 reserved_at_10[0xc];
e281682b
SM		 7802 u8 module_status[0x4];
7803
b4ff3a36 7804 u8 reserved_at_20[0x60];
e281682b
SM		 7805};
7806
7807struct mlx5_ifc_pmpc_reg_bits {
7808 u8 module_state_updated[32][0x8];
7809};
7810
7811struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7812 u8 reserved_at_0[0x4];
e281682b
SM		 7813 u8 mlpn_status[0x4];
7814 u8 local_port[0x8];
b4ff3a36 7815 u8 reserved_at_10[0x10];
e281682b
SM		 7816
7817 u8 e[0x1];
b4ff3a36 7818 u8 reserved_at_21[0x1f];
e281682b
SM		 7819};
7820
7821struct mlx5_ifc_pmlp_reg_bits {
7822 u8 rxtx[0x1];
b4ff3a36 7823 u8 reserved_at_1[0x7];
e281682b 7824 u8 local_port[0x8];
b4ff3a36 7825 u8 reserved_at_10[0x8];
e281682b
SM		 7826 u8 width[0x8];
7827
7828 u8 lane0_module_mapping[0x20];
7829
7830 u8 lane1_module_mapping[0x20];
7831
7832 u8 lane2_module_mapping[0x20];
7833
7834 u8 lane3_module_mapping[0x20];
7835
b4ff3a36 7836 u8 reserved_at_a0[0x160];
e281682b
SM		 7837};
7838
7839struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7840 u8 reserved_at_0[0x8];
e281682b 7841 u8 module[0x8];
b4ff3a36 7842 u8 reserved_at_10[0x4];
e281682b 7843 u8 admin_status[0x4];
b4ff3a36 7844 u8 reserved_at_18[0x4];
e281682b
SM		 7845 u8 oper_status[0x4];
7846
7847 u8 ase[0x1];
7848 u8 ee[0x1];
b4ff3a36 7849 u8 reserved_at_22[0x1c];
e281682b
SM		 7850 u8 e[0x2];
7851
b4ff3a36 7852 u8 reserved_at_40[0x40];
e281682b
SM		 7853};
7854
7855struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7856 u8 reserved_at_0[0x4];
e281682b 7857 u8 profile_id[0xc];
b4ff3a36 7858 u8 reserved_at_10[0x4];
e281682b 7859 u8 proto_mask[0x4];
b4ff3a36 7860 u8 reserved_at_18[0x8];
e281682b 7861
b4ff3a36 7862 u8 reserved_at_20[0x10];
e281682b
SM		 7863 u8 lane_speed[0x10];
7864
b4ff3a36 7865 u8 reserved_at_40[0x17];
e281682b
SM		 7866 u8 lpbf[0x1];
7867 u8 fec_mode_policy[0x8];
7868
7869 u8 retransmission_capability[0x8];
7870 u8 fec_mode_capability[0x18];
7871
7872 u8 retransmission_support_admin[0x8];
7873 u8 fec_mode_support_admin[0x18];
7874
7875 u8 retransmission_request_admin[0x8];
7876 u8 fec_mode_request_admin[0x18];
7877
b4ff3a36 7878 u8 reserved_at_c0[0x80];
e281682b
SM		 7879};
7880
7881struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7882 u8 reserved_at_0[0x8];
e281682b 7883 u8 local_port[0x8];
b4ff3a36 7884 u8 reserved_at_10[0x8];
e281682b
SM		 7885 u8 ib_port[0x8];
7886
b4ff3a36 7887 u8 reserved_at_20[0x60];
e281682b
SM		 7888};
7889
7890struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7891 u8 reserved_at_0[0x8];
e281682b 7892 u8 local_port[0x8];
b4ff3a36 7893 u8 reserved_at_10[0xd];
e281682b
SM		 7894 u8 lbf_mode[0x3];
7895
b4ff3a36 7896 u8 reserved_at_20[0x20];
e281682b
SM		 7897};
7898
7899struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7900 u8 reserved_at_0[0x8];
e281682b 7901 u8 local_port[0x8];
b4ff3a36 7902 u8 reserved_at_10[0x10];
e281682b
SM		 7903
7904 u8 dic[0x1];
b4ff3a36 7905 u8 reserved_at_21[0x19];
e281682b 7906 u8 ipg[0x4];
b4ff3a36 7907 u8 reserved_at_3e[0x2];
e281682b
SM		 7908};
7909
7910struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7911 u8 reserved_at_0[0x8];
e281682b 7912 u8 local_port[0x8];
b4ff3a36 7913 u8 reserved_at_10[0x10];
e281682b 7914
b4ff3a36 7915 u8 reserved_at_20[0xe0];
e281682b
SM		 7916
7917 u8 port_filter[8][0x20];
7918
7919 u8 port_filter_update_en[8][0x20];
7920};
7921
7922struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7923 u8 reserved_at_0[0x8];
e281682b 7924 u8 local_port[0x8];
2afa609f
IK		 7925 u8 reserved_at_10[0xb];
7926 u8 ppan_mask_n[0x1];
7927 u8 minor_stall_mask[0x1];
7928 u8 critical_stall_mask[0x1];
7929 u8 reserved_at_1e[0x2];
e281682b
SM		 7930
7931 u8 ppan[0x4];
b4ff3a36 7932 u8 reserved_at_24[0x4];
e281682b 7933 u8 prio_mask_tx[0x8];
b4ff3a36 7934 u8 reserved_at_30[0x8];
e281682b
SM		 7935 u8 prio_mask_rx[0x8];
7936
7937 u8 pptx[0x1];
7938 u8 aptx[0x1];
2afa609f
IK		 7939 u8 pptx_mask_n[0x1];
7940 u8 reserved_at_43[0x5];
e281682b 7941 u8 pfctx[0x8];
b4ff3a36 7942 u8 reserved_at_50[0x10];
e281682b
SM		 7943
7944 u8 pprx[0x1];
7945 u8 aprx[0x1];
2afa609f
IK		 7946 u8 pprx_mask_n[0x1];
7947 u8 reserved_at_63[0x5];
e281682b 7948 u8 pfcrx[0x8];
b4ff3a36 7949 u8 reserved_at_70[0x10];
e281682b 7950
2afa609f
IK		 7951 u8 device_stall_minor_watermark[0x10];
7952 u8 device_stall_critical_watermark[0x10];
7953
7954 u8 reserved_at_a0[0x60];
e281682b
SM		 7955};
7956
7957struct mlx5_ifc_pelc_reg_bits {
7958 u8 op[0x4];
b4ff3a36 7959 u8 reserved_at_4[0x4];
e281682b 7960 u8 local_port[0x8];
b4ff3a36 7961 u8 reserved_at_10[0x10];
e281682b
SM		 7962
7963 u8 op_admin[0x8];
7964 u8 op_capability[0x8];
7965 u8 op_request[0x8];
7966 u8 op_active[0x8];
7967
7968 u8 admin[0x40];
7969
7970 u8 capability[0x40];
7971
7972 u8 request[0x40];
7973
7974 u8 active[0x40];
7975
b4ff3a36 7976 u8 reserved_at_140[0x80];
e281682b
SM		 7977};
7978
7979struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7980 u8 reserved_at_0[0x8];
e281682b 7981 u8 local_port[0x8];
b4ff3a36 7982 u8 reserved_at_10[0x10];
e281682b 7983
b4ff3a36 7984 u8 reserved_at_20[0xc];
e281682b 7985 u8 error_count[0x4];
b4ff3a36 7986 u8 reserved_at_30[0x10];
e281682b 7987
b4ff3a36 7988 u8 reserved_at_40[0xc];
e281682b 7989 u8 lane[0x4];
b4ff3a36 7990 u8 reserved_at_50[0x8];
e281682b
SM		 7991 u8 error_type[0x8];
7992};
7993
cfdcbcea 7994struct mlx5_ifc_pcam_enhanced_features_bits {
2fcb12df 7995 u8 reserved_at_0[0x76];
cfdcbcea 7996
2fcb12df
IK		 7997 u8 pfcc_mask[0x1];
7998 u8 reserved_at_77[0x4];
2dba0797 7999 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8000 u8 ptys_connector_type[0x1];
8001 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8002 u8 ppcnt_discard_group[0x1];
8003 u8 ppcnt_statistical_group[0x1];
8004};
8005
8006struct mlx5_ifc_pcam_reg_bits {
8007 u8 reserved_at_0[0x8];
8008 u8 feature_group[0x8];
8009 u8 reserved_at_10[0x8];
8010 u8 access_reg_group[0x8];
8011
8012 u8 reserved_at_20[0x20];
8013
8014 union {
8015 u8 reserved_at_0[0x80];
8016 } port_access_reg_cap_mask;
8017
8018 u8 reserved_at_c0[0x80];
8019
8020 union {
8021 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8022 u8 reserved_at_0[0x80];
8023 } feature_cap_mask;
8024
8025 u8 reserved_at_1c0[0xc0];
8026};
8027
8028struct mlx5_ifc_mcam_enhanced_features_bits {
5405fa26
GP		 8029 u8 reserved_at_0[0x7b];
8030 u8 pcie_outbound_stalled[0x1];
efae7f78 8031 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8032 u8 mtpps_enh_out_per_adj[0x1];
8033 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8034 u8 pcie_performance_group[0x1];
8035};
8036
0ab87743
OG		 8037struct mlx5_ifc_mcam_access_reg_bits {
8038 u8 reserved_at_0[0x1c];
8039 u8 mcda[0x1];
8040 u8 mcc[0x1];
8041 u8 mcqi[0x1];
8042 u8 reserved_at_1f[0x1];
8043
8044 u8 regs_95_to_64[0x20];
8045 u8 regs_63_to_32[0x20];
8046 u8 regs_31_to_0[0x20];
8047};
8048
cfdcbcea
GP		 8049struct mlx5_ifc_mcam_reg_bits {
8050 u8 reserved_at_0[0x8];
8051 u8 feature_group[0x8];
8052 u8 reserved_at_10[0x8];
8053 u8 access_reg_group[0x8];
8054
8055 u8 reserved_at_20[0x20];
8056
8057 union {
0ab87743 8058 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8059 u8 reserved_at_0[0x80];
8060 } mng_access_reg_cap_mask;
8061
8062 u8 reserved_at_c0[0x80];
8063
8064 union {
8065 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8066 u8 reserved_at_0[0x80];
8067 } mng_feature_cap_mask;
8068
8069 u8 reserved_at_1c0[0x80];
8070};
8071
c02762eb
HN		 8072struct mlx5_ifc_qcam_access_reg_cap_mask {
8073 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8074 u8 qpdpm[0x1];
8075 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8076 u8 qdpm[0x1];
8077 u8 qpts[0x1];
8078 u8 qcap[0x1];
8079 u8 qcam_access_reg_cap_mask_0[0x1];
8080};
8081
8082struct mlx5_ifc_qcam_qos_feature_cap_mask {
8083 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8084 u8 qpts_trust_both[0x1];
8085};
8086
8087struct mlx5_ifc_qcam_reg_bits {
8088 u8 reserved_at_0[0x8];
8089 u8 feature_group[0x8];
8090 u8 reserved_at_10[0x8];
8091 u8 access_reg_group[0x8];
8092 u8 reserved_at_20[0x20];
8093
8094 union {
8095 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8096 u8 reserved_at_0[0x80];
8097 } qos_access_reg_cap_mask;
8098
8099 u8 reserved_at_c0[0x80];
8100
8101 union {
8102 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8103 u8 reserved_at_0[0x80];
8104 } qos_feature_cap_mask;
8105
8106 u8 reserved_at_1c0[0x80];
8107};
8108
e281682b 8109struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8110 u8 reserved_at_0[0x8];
e281682b 8111 u8 local_port[0x8];
b4ff3a36 8112 u8 reserved_at_10[0x10];
e281682b
SM		 8113
8114 u8 port_capability_mask[4][0x20];
8115};
8116
8117struct mlx5_ifc_paos_reg_bits {
8118 u8 swid[0x8];
8119 u8 local_port[0x8];
b4ff3a36 8120 u8 reserved_at_10[0x4];
e281682b 8121 u8 admin_status[0x4];
b4ff3a36 8122 u8 reserved_at_18[0x4];
e281682b
SM		 8123 u8 oper_status[0x4];
8124
8125 u8 ase[0x1];
8126 u8 ee[0x1];
b4ff3a36 8127 u8 reserved_at_22[0x1c];
e281682b
SM		 8128 u8 e[0x2];
8129
b4ff3a36 8130 u8 reserved_at_40[0x40];
e281682b
SM		 8131};
8132
8133struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8134 u8 reserved_at_0[0x8];
e281682b 8135 u8 opamp_group[0x8];
b4ff3a36 8136 u8 reserved_at_10[0xc];
e281682b
SM		 8137 u8 opamp_group_type[0x4];
8138
8139 u8 start_index[0x10];
b4ff3a36 8140 u8 reserved_at_30[0x4];
e281682b
SM		 8141 u8 num_of_indices[0xc];
8142
8143 u8 index_data[18][0x10];
8144};
8145
7d5e1423
SM		 8146struct mlx5_ifc_pcmr_reg_bits {
8147 u8 reserved_at_0[0x8];
8148 u8 local_port[0x8];
8149 u8 reserved_at_10[0x2e];
8150 u8 fcs_cap[0x1];
8151 u8 reserved_at_3f[0x1f];
8152 u8 fcs_chk[0x1];
8153 u8 reserved_at_5f[0x1];
8154};
8155
e281682b 8156struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8157 u8 reserved_at_0[0x6];
e281682b 8158 u8 rx_lane[0x2];
b4ff3a36 8159 u8 reserved_at_8[0x6];
e281682b 8160 u8 tx_lane[0x2];
b4ff3a36 8161 u8 reserved_at_10[0x8];
e281682b
SM		 8162 u8 module[0x8];
8163};
8164
8165struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8166 u8 reserved_at_0[0x6];
e281682b
SM		 8167 u8 lossy[0x1];
8168 u8 epsb[0x1];
b4ff3a36 8169 u8 reserved_at_8[0xc];
e281682b
SM		 8170 u8 size[0xc];
8171
8172 u8 xoff_threshold[0x10];
8173 u8 xon_threshold[0x10];
8174};
8175
8176struct mlx5_ifc_set_node_in_bits {
8177 u8 node_description[64][0x8];
8178};
8179
8180struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8181 u8 reserved_at_0[0x18];
e281682b
SM		 8182 u8 power_settings_level[0x8];
8183
b4ff3a36 8184 u8 reserved_at_20[0x60];
e281682b
SM		 8185};
8186
8187struct mlx5_ifc_register_host_endianness_bits {
8188 u8 he[0x1];
b4ff3a36 8189 u8 reserved_at_1[0x1f];
e281682b 8190
b4ff3a36 8191 u8 reserved_at_20[0x60];
e281682b
SM		 8192};
8193
8194struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8195 u8 reserved_at_0[0x20];
e281682b
SM		 8196
8197 u8 mkey[0x20];
8198
8199 u8 addressh_63_32[0x20];
8200
8201 u8 addressl_31_0[0x20];
8202};
8203
8204struct mlx5_ifc_ud_adrs_vector_bits {
8205 u8 dc_key[0x40];
8206
8207 u8 ext[0x1];
b4ff3a36 8208 u8 reserved_at_41[0x7];
e281682b
SM		 8209 u8 destination_qp_dct[0x18];
8210
8211 u8 static_rate[0x4];
8212 u8 sl_eth_prio[0x4];
8213 u8 fl[0x1];
8214 u8 mlid[0x7];
8215 u8 rlid_udp_sport[0x10];
8216
b4ff3a36 8217 u8 reserved_at_80[0x20];
e281682b
SM		 8218
8219 u8 rmac_47_16[0x20];
8220
8221 u8 rmac_15_0[0x10];
8222 u8 tclass[0x8];
8223 u8 hop_limit[0x8];
8224
b4ff3a36 8225 u8 reserved_at_e0[0x1];
e281682b 8226 u8 grh[0x1];
b4ff3a36 8227 u8 reserved_at_e2[0x2];
e281682b
SM		 8228 u8 src_addr_index[0x8];
8229 u8 flow_label[0x14];
8230
8231 u8 rgid_rip[16][0x8];
8232};
8233
8234struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8235 u8 reserved_at_0[0x10];
e281682b
SM		 8236 u8 function_id[0x10];
8237
8238 u8 num_pages[0x20];
8239
b4ff3a36 8240 u8 reserved_at_40[0xa0];
e281682b
SM		 8241};
8242
8243struct mlx5_ifc_eqe_bits {
b4ff3a36 8244 u8 reserved_at_0[0x8];
e281682b 8245 u8 event_type[0x8];
b4ff3a36 8246 u8 reserved_at_10[0x8];
e281682b
SM		 8247 u8 event_sub_type[0x8];
8248
b4ff3a36 8249 u8 reserved_at_20[0xe0];
e281682b
SM		 8250
8251 union mlx5_ifc_event_auto_bits event_data;
8252
b4ff3a36 8253 u8 reserved_at_1e0[0x10];
e281682b 8254 u8 signature[0x8];
b4ff3a36 8255 u8 reserved_at_1f8[0x7];
e281682b
SM		 8256 u8 owner[0x1];
8257};
8258
8259enum {
8260 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8261};
8262
8263struct mlx5_ifc_cmd_queue_entry_bits {
8264 u8 type[0x8];
b4ff3a36 8265 u8 reserved_at_8[0x18];
e281682b
SM		 8266
8267 u8 input_length[0x20];
8268
8269 u8 input_mailbox_pointer_63_32[0x20];
8270
8271 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8272 u8 reserved_at_77[0x9];
e281682b
SM		 8273
8274 u8 command_input_inline_data[16][0x8];
8275
8276 u8 command_output_inline_data[16][0x8];
8277
8278 u8 output_mailbox_pointer_63_32[0x20];
8279
8280 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8281 u8 reserved_at_1b7[0x9];
e281682b
SM		 8282
8283 u8 output_length[0x20];
8284
8285 u8 token[0x8];
8286 u8 signature[0x8];
b4ff3a36 8287 u8 reserved_at_1f0[0x8];
e281682b
SM		 8288 u8 status[0x7];
8289 u8 ownership[0x1];
8290};
8291
8292struct mlx5_ifc_cmd_out_bits {
8293 u8 status[0x8];
b4ff3a36 8294 u8 reserved_at_8[0x18];
e281682b
SM		 8295
8296 u8 syndrome[0x20];
8297
8298 u8 command_output[0x20];
8299};
8300
8301struct mlx5_ifc_cmd_in_bits {
8302 u8 opcode[0x10];
b4ff3a36 8303 u8 reserved_at_10[0x10];
e281682b 8304
b4ff3a36 8305 u8 reserved_at_20[0x10];
e281682b
SM		 8306 u8 op_mod[0x10];
8307
8308 u8 command[0][0x20];
8309};
8310
8311struct mlx5_ifc_cmd_if_box_bits {
8312 u8 mailbox_data[512][0x8];
8313
b4ff3a36 8314 u8 reserved_at_1000[0x180];
e281682b
SM		 8315
8316 u8 next_pointer_63_32[0x20];
8317
8318 u8 next_pointer_31_10[0x16];
b4ff3a36 8319 u8 reserved_at_11b6[0xa];
e281682b
SM		 8320
8321 u8 block_number[0x20];
8322
b4ff3a36 8323 u8 reserved_at_11e0[0x8];
e281682b
SM		 8324 u8 token[0x8];
8325 u8 ctrl_signature[0x8];
8326 u8 signature[0x8];
8327};
8328
8329struct mlx5_ifc_mtt_bits {
8330 u8 ptag_63_32[0x20];
8331
8332 u8 ptag_31_8[0x18];
b4ff3a36 8333 u8 reserved_at_38[0x6];
e281682b
SM		 8334 u8 wr_en[0x1];
8335 u8 rd_en[0x1];
8336};
8337
928cfe87
TT		 8338struct mlx5_ifc_query_wol_rol_out_bits {
8339 u8 status[0x8];
8340 u8 reserved_at_8[0x18];
8341
8342 u8 syndrome[0x20];
8343
8344 u8 reserved_at_40[0x10];
8345 u8 rol_mode[0x8];
8346 u8 wol_mode[0x8];
8347
8348 u8 reserved_at_60[0x20];
8349};
8350
8351struct mlx5_ifc_query_wol_rol_in_bits {
8352 u8 opcode[0x10];
8353 u8 reserved_at_10[0x10];
8354
8355 u8 reserved_at_20[0x10];
8356 u8 op_mod[0x10];
8357
8358 u8 reserved_at_40[0x40];
8359};
8360
8361struct mlx5_ifc_set_wol_rol_out_bits {
8362 u8 status[0x8];
8363 u8 reserved_at_8[0x18];
8364
8365 u8 syndrome[0x20];
8366
8367 u8 reserved_at_40[0x40];
8368};
8369
8370struct mlx5_ifc_set_wol_rol_in_bits {
8371 u8 opcode[0x10];
8372 u8 reserved_at_10[0x10];
8373
8374 u8 reserved_at_20[0x10];
8375 u8 op_mod[0x10];
8376
8377 u8 rol_mode_valid[0x1];
8378 u8 wol_mode_valid[0x1];
8379 u8 reserved_at_42[0xe];
8380 u8 rol_mode[0x8];
8381 u8 wol_mode[0x8];
8382
8383 u8 reserved_at_60[0x20];
8384};
8385
e281682b
SM		 8386enum {
8387 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8388 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8389 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8390};
8391
8392enum {
8393 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8394 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8395 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8396};
8397
8398enum {
8399 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8400 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8401 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8402 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8403 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8404 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8405 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8406 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8407 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8408 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8409 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8410};
8411
8412struct mlx5_ifc_initial_seg_bits {
8413 u8 fw_rev_minor[0x10];
8414 u8 fw_rev_major[0x10];
8415
8416 u8 cmd_interface_rev[0x10];
8417 u8 fw_rev_subminor[0x10];
8418
b4ff3a36 8419 u8 reserved_at_40[0x40];
e281682b
SM		 8420
8421 u8 cmdq_phy_addr_63_32[0x20];
8422
8423 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8424 u8 reserved_at_b4[0x2];
e281682b
SM		 8425 u8 nic_interface[0x2];
8426 u8 log_cmdq_size[0x4];
8427 u8 log_cmdq_stride[0x4];
8428
8429 u8 command_doorbell_vector[0x20];
8430
b4ff3a36 8431 u8 reserved_at_e0[0xf00];
e281682b
SM		 8432
8433 u8 initializing[0x1];
b4ff3a36 8434 u8 reserved_at_fe1[0x4];
e281682b 8435 u8 nic_interface_supported[0x3];
b4ff3a36 8436 u8 reserved_at_fe8[0x18];
e281682b
SM		 8437
8438 struct mlx5_ifc_health_buffer_bits health_buffer;
8439
8440 u8 no_dram_nic_offset[0x20];
8441
b4ff3a36 8442 u8 reserved_at_1220[0x6e40];
e281682b 8443
b4ff3a36 8444 u8 reserved_at_8060[0x1f];
e281682b
SM		 8445 u8 clear_int[0x1];
8446
8447 u8 health_syndrome[0x8];
8448 u8 health_counter[0x18];
8449
b4ff3a36 8450 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8451};
8452
f9a1ef72
EE		 8453struct mlx5_ifc_mtpps_reg_bits {
8454 u8 reserved_at_0[0xc];
8455 u8 cap_number_of_pps_pins[0x4];
8456 u8 reserved_at_10[0x4];
8457 u8 cap_max_num_of_pps_in_pins[0x4];
8458 u8 reserved_at_18[0x4];
8459 u8 cap_max_num_of_pps_out_pins[0x4];
8460
8461 u8 reserved_at_20[0x24];
8462 u8 cap_pin_3_mode[0x4];
8463 u8 reserved_at_48[0x4];
8464 u8 cap_pin_2_mode[0x4];
8465 u8 reserved_at_50[0x4];
8466 u8 cap_pin_1_mode[0x4];
8467 u8 reserved_at_58[0x4];
8468 u8 cap_pin_0_mode[0x4];
8469
8470 u8 reserved_at_60[0x4];
8471 u8 cap_pin_7_mode[0x4];
8472 u8 reserved_at_68[0x4];
8473 u8 cap_pin_6_mode[0x4];
8474 u8 reserved_at_70[0x4];
8475 u8 cap_pin_5_mode[0x4];
8476 u8 reserved_at_78[0x4];
8477 u8 cap_pin_4_mode[0x4];
8478
fa367688
EE		 8479 u8 field_select[0x20];
8480 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8481
8482 u8 enable[0x1];
8483 u8 reserved_at_101[0xb];
8484 u8 pattern[0x4];
8485 u8 reserved_at_110[0x4];
8486 u8 pin_mode[0x4];
8487 u8 pin[0x8];
8488
8489 u8 reserved_at_120[0x20];
8490
8491 u8 time_stamp[0x40];
8492
8493 u8 out_pulse_duration[0x10];
8494 u8 out_periodic_adjustment[0x10];
fa367688 8495 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8496
fa367688 8497 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8498};
8499
8500struct mlx5_ifc_mtppse_reg_bits {
8501 u8 reserved_at_0[0x18];
8502 u8 pin[0x8];
8503 u8 event_arm[0x1];
8504 u8 reserved_at_21[0x1b];
8505 u8 event_generation_mode[0x4];
8506 u8 reserved_at_40[0x40];
8507};
8508
47176289
OG		 8509struct mlx5_ifc_mcqi_cap_bits {
8510 u8 supported_info_bitmask[0x20];
8511
8512 u8 component_size[0x20];
8513
8514 u8 max_component_size[0x20];
8515
8516 u8 log_mcda_word_size[0x4];
8517 u8 reserved_at_64[0xc];
8518 u8 mcda_max_write_size[0x10];
8519
8520 u8 rd_en[0x1];
8521 u8 reserved_at_81[0x1];
8522 u8 match_chip_id[0x1];
8523 u8 match_psid[0x1];
8524 u8 check_user_timestamp[0x1];
8525 u8 match_base_guid_mac[0x1];
8526 u8 reserved_at_86[0x1a];
8527};
8528
8529struct mlx5_ifc_mcqi_reg_bits {
8530 u8 read_pending_component[0x1];
8531 u8 reserved_at_1[0xf];
8532 u8 component_index[0x10];
8533
8534 u8 reserved_at_20[0x20];
8535
8536 u8 reserved_at_40[0x1b];
8537 u8 info_type[0x5];
8538
8539 u8 info_size[0x20];
8540
8541 u8 offset[0x20];
8542
8543 u8 reserved_at_a0[0x10];
8544 u8 data_size[0x10];
8545
8546 u8 data[0][0x20];
8547};
8548
8549struct mlx5_ifc_mcc_reg_bits {
8550 u8 reserved_at_0[0x4];
8551 u8 time_elapsed_since_last_cmd[0xc];
8552 u8 reserved_at_10[0x8];
8553 u8 instruction[0x8];
8554
8555 u8 reserved_at_20[0x10];
8556 u8 component_index[0x10];
8557
8558 u8 reserved_at_40[0x8];
8559 u8 update_handle[0x18];
8560
8561 u8 handle_owner_type[0x4];
8562 u8 handle_owner_host_id[0x4];
8563 u8 reserved_at_68[0x1];
8564 u8 control_progress[0x7];
8565 u8 error_code[0x8];
8566 u8 reserved_at_78[0x4];
8567 u8 control_state[0x4];
8568
8569 u8 component_size[0x20];
8570
8571 u8 reserved_at_a0[0x60];
8572};
8573
8574struct mlx5_ifc_mcda_reg_bits {
8575 u8 reserved_at_0[0x8];
8576 u8 update_handle[0x18];
8577
8578 u8 offset[0x20];
8579
8580 u8 reserved_at_40[0x10];
8581 u8 size[0x10];
8582
8583 u8 reserved_at_60[0x20];
8584
8585 u8 data[0][0x20];
8586};
8587
e281682b
SM		 8588union mlx5_ifc_ports_control_registers_document_bits {
8589 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8590 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8591 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8592 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8593 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8594 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8595 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8596 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8597 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8598 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8599 struct mlx5_ifc_paos_reg_bits paos_reg;
8600 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8601 struct mlx5_ifc_peir_reg_bits peir_reg;
8602 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8603 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8604 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8605 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8606 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8607 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8608 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8609 struct mlx5_ifc_plib_reg_bits plib_reg;
8610 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8611 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8612 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8613 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8614 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8615 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8616 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8617 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8618 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8619 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8620 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8621 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8622 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8623 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8624 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8625 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8626 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8627 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8628 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8629 struct mlx5_ifc_pude_reg_bits pude_reg;
8630 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8631 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8632 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8633 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8634 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8635 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8636 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8637 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8638 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8639 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8640 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8641 u8 reserved_at_0[0x60e0];
e281682b
SM		 8642};
8643
8644union mlx5_ifc_debug_enhancements_document_bits {
8645 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8646 u8 reserved_at_0[0x200];
e281682b
SM		 8647};
8648
8649union mlx5_ifc_uplink_pci_interface_document_bits {
8650 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8651 u8 reserved_at_0[0x20060];
b775516b
EC		 8652};
8653
2cc43b49
MG		 8654struct mlx5_ifc_set_flow_table_root_out_bits {
8655 u8 status[0x8];
b4ff3a36 8656 u8 reserved_at_8[0x18];
2cc43b49
MG		 8657
8658 u8 syndrome[0x20];
8659
b4ff3a36 8660 u8 reserved_at_40[0x40];
2cc43b49
MG		 8661};
8662
8663struct mlx5_ifc_set_flow_table_root_in_bits {
8664 u8 opcode[0x10];
b4ff3a36 8665 u8 reserved_at_10[0x10];
2cc43b49 8666
b4ff3a36 8667 u8 reserved_at_20[0x10];
2cc43b49
MG		 8668 u8 op_mod[0x10];
8669
7d5e1423
SM		 8670 u8 other_vport[0x1];
8671 u8 reserved_at_41[0xf];
8672 u8 vport_number[0x10];
8673
8674 u8 reserved_at_60[0x20];
2cc43b49
MG		 8675
8676 u8 table_type[0x8];
b4ff3a36 8677 u8 reserved_at_88[0x18];
2cc43b49 8678
b4ff3a36 8679 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8680 u8 table_id[0x18];
8681
500a3d0d
ES		 8682 u8 reserved_at_c0[0x8];
8683 u8 underlay_qpn[0x18];
8684 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8685};
8686
34a40e68 8687enum {
84df61eb
AH		 8688 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8689 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8690};
8691
8692struct mlx5_ifc_modify_flow_table_out_bits {
8693 u8 status[0x8];
b4ff3a36 8694 u8 reserved_at_8[0x18];
34a40e68
MG		 8695
8696 u8 syndrome[0x20];
8697
b4ff3a36 8698 u8 reserved_at_40[0x40];
34a40e68
MG		 8699};
8700
8701struct mlx5_ifc_modify_flow_table_in_bits {
8702 u8 opcode[0x10];
b4ff3a36 8703 u8 reserved_at_10[0x10];
34a40e68 8704
b4ff3a36 8705 u8 reserved_at_20[0x10];
34a40e68
MG		 8706 u8 op_mod[0x10];
8707
7d5e1423
SM		 8708 u8 other_vport[0x1];
8709 u8 reserved_at_41[0xf];
8710 u8 vport_number[0x10];
34a40e68 8711
b4ff3a36 8712 u8 reserved_at_60[0x10];
34a40e68
MG		 8713 u8 modify_field_select[0x10];
8714
8715 u8 table_type[0x8];
b4ff3a36 8716 u8 reserved_at_88[0x18];
34a40e68 8717
b4ff3a36 8718 u8 reserved_at_a0[0x8];
34a40e68
MG		 8719 u8 table_id[0x18];
8720
0c90e9c6 8721 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8722};
8723
4f3961ee
SM		 8724struct mlx5_ifc_ets_tcn_config_reg_bits {
8725 u8 g[0x1];
8726 u8 b[0x1];
8727 u8 r[0x1];
8728 u8 reserved_at_3[0x9];
8729 u8 group[0x4];
8730 u8 reserved_at_10[0x9];
8731 u8 bw_allocation[0x7];
8732
8733 u8 reserved_at_20[0xc];
8734 u8 max_bw_units[0x4];
8735 u8 reserved_at_30[0x8];
8736 u8 max_bw_value[0x8];
8737};
8738
8739struct mlx5_ifc_ets_global_config_reg_bits {
8740 u8 reserved_at_0[0x2];
8741 u8 r[0x1];
8742 u8 reserved_at_3[0x1d];
8743
8744 u8 reserved_at_20[0xc];
8745 u8 max_bw_units[0x4];
8746 u8 reserved_at_30[0x8];
8747 u8 max_bw_value[0x8];
8748};
8749
8750struct mlx5_ifc_qetc_reg_bits {
8751 u8 reserved_at_0[0x8];
8752 u8 port_number[0x8];
8753 u8 reserved_at_10[0x30];
8754
8755 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8756 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8757};
8758
415a64aa
HN		 8759struct mlx5_ifc_qpdpm_dscp_reg_bits {
8760 u8 e[0x1];
8761 u8 reserved_at_01[0x0b];
8762 u8 prio[0x04];
8763};
8764
8765struct mlx5_ifc_qpdpm_reg_bits {
8766 u8 reserved_at_0[0x8];
8767 u8 local_port[0x8];
8768 u8 reserved_at_10[0x10];
8769 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8770};
8771
8772struct mlx5_ifc_qpts_reg_bits {
8773 u8 reserved_at_0[0x8];
8774 u8 local_port[0x8];
8775 u8 reserved_at_10[0x2d];
8776 u8 trust_state[0x3];
8777};
8778
4f3961ee
SM		 8779struct mlx5_ifc_qtct_reg_bits {
8780 u8 reserved_at_0[0x8];
8781 u8 port_number[0x8];
8782 u8 reserved_at_10[0xd];
8783 u8 prio[0x3];
8784
8785 u8 reserved_at_20[0x1d];
8786 u8 tclass[0x3];
8787};
8788
7d5e1423
SM		 8789struct mlx5_ifc_mcia_reg_bits {
8790 u8 l[0x1];
8791 u8 reserved_at_1[0x7];
8792 u8 module[0x8];
8793 u8 reserved_at_10[0x8];
8794 u8 status[0x8];
8795
8796 u8 i2c_device_address[0x8];
8797 u8 page_number[0x8];
8798 u8 device_address[0x10];
8799
8800 u8 reserved_at_40[0x10];
8801 u8 size[0x10];
8802
8803 u8 reserved_at_60[0x20];
8804
8805 u8 dword_0[0x20];
8806 u8 dword_1[0x20];
8807 u8 dword_2[0x20];
8808 u8 dword_3[0x20];
8809 u8 dword_4[0x20];
8810 u8 dword_5[0x20];
8811 u8 dword_6[0x20];
8812 u8 dword_7[0x20];
8813 u8 dword_8[0x20];
8814 u8 dword_9[0x20];
8815 u8 dword_10[0x20];
8816 u8 dword_11[0x20];
8817};
8818
7486216b
SM		 8819struct mlx5_ifc_dcbx_param_bits {
8820 u8 dcbx_cee_cap[0x1];
8821 u8 dcbx_ieee_cap[0x1];
8822 u8 dcbx_standby_cap[0x1];
8823 u8 reserved_at_0[0x5];
8824 u8 port_number[0x8];
8825 u8 reserved_at_10[0xa];
8826 u8 max_application_table_size[6];
8827 u8 reserved_at_20[0x15];
8828 u8 version_oper[0x3];
8829 u8 reserved_at_38[5];
8830 u8 version_admin[0x3];
8831 u8 willing_admin[0x1];
8832 u8 reserved_at_41[0x3];
8833 u8 pfc_cap_oper[0x4];
8834 u8 reserved_at_48[0x4];
8835 u8 pfc_cap_admin[0x4];
8836 u8 reserved_at_50[0x4];
8837 u8 num_of_tc_oper[0x4];
8838 u8 reserved_at_58[0x4];
8839 u8 num_of_tc_admin[0x4];
8840 u8 remote_willing[0x1];
8841 u8 reserved_at_61[3];
8842 u8 remote_pfc_cap[4];
8843 u8 reserved_at_68[0x14];
8844 u8 remote_num_of_tc[0x4];
8845 u8 reserved_at_80[0x18];
8846 u8 error[0x8];
8847 u8 reserved_at_a0[0x160];
8848};
84df61eb
AH		 8849
8850struct mlx5_ifc_lagc_bits {
8851 u8 reserved_at_0[0x1d];
8852 u8 lag_state[0x3];
8853
8854 u8 reserved_at_20[0x14];
8855 u8 tx_remap_affinity_2[0x4];
8856 u8 reserved_at_38[0x4];
8857 u8 tx_remap_affinity_1[0x4];
8858};
8859
8860struct mlx5_ifc_create_lag_out_bits {
8861 u8 status[0x8];
8862 u8 reserved_at_8[0x18];
8863
8864 u8 syndrome[0x20];
8865
8866 u8 reserved_at_40[0x40];
8867};
8868
8869struct mlx5_ifc_create_lag_in_bits {
8870 u8 opcode[0x10];
8871 u8 reserved_at_10[0x10];
8872
8873 u8 reserved_at_20[0x10];
8874 u8 op_mod[0x10];
8875
8876 struct mlx5_ifc_lagc_bits ctx;
8877};
8878
8879struct mlx5_ifc_modify_lag_out_bits {
8880 u8 status[0x8];
8881 u8 reserved_at_8[0x18];
8882
8883 u8 syndrome[0x20];
8884
8885 u8 reserved_at_40[0x40];
8886};
8887
8888struct mlx5_ifc_modify_lag_in_bits {
8889 u8 opcode[0x10];
8890 u8 reserved_at_10[0x10];
8891
8892 u8 reserved_at_20[0x10];
8893 u8 op_mod[0x10];
8894
8895 u8 reserved_at_40[0x20];
8896 u8 field_select[0x20];
8897
8898 struct mlx5_ifc_lagc_bits ctx;
8899};
8900
8901struct mlx5_ifc_query_lag_out_bits {
8902 u8 status[0x8];
8903 u8 reserved_at_8[0x18];
8904
8905 u8 syndrome[0x20];
8906
8907 u8 reserved_at_40[0x40];
8908
8909 struct mlx5_ifc_lagc_bits ctx;
8910};
8911
8912struct mlx5_ifc_query_lag_in_bits {
8913 u8 opcode[0x10];
8914 u8 reserved_at_10[0x10];
8915
8916 u8 reserved_at_20[0x10];
8917 u8 op_mod[0x10];
8918
8919 u8 reserved_at_40[0x40];
8920};
8921
8922struct mlx5_ifc_destroy_lag_out_bits {
8923 u8 status[0x8];
8924 u8 reserved_at_8[0x18];
8925
8926 u8 syndrome[0x20];
8927
8928 u8 reserved_at_40[0x40];
8929};
8930
8931struct mlx5_ifc_destroy_lag_in_bits {
8932 u8 opcode[0x10];
8933 u8 reserved_at_10[0x10];
8934
8935 u8 reserved_at_20[0x10];
8936 u8 op_mod[0x10];
8937
8938 u8 reserved_at_40[0x40];
8939};
8940
8941struct mlx5_ifc_create_vport_lag_out_bits {
8942 u8 status[0x8];
8943 u8 reserved_at_8[0x18];
8944
8945 u8 syndrome[0x20];
8946
8947 u8 reserved_at_40[0x40];
8948};
8949
8950struct mlx5_ifc_create_vport_lag_in_bits {
8951 u8 opcode[0x10];
8952 u8 reserved_at_10[0x10];
8953
8954 u8 reserved_at_20[0x10];
8955 u8 op_mod[0x10];
8956
8957 u8 reserved_at_40[0x40];
8958};
8959
8960struct mlx5_ifc_destroy_vport_lag_out_bits {
8961 u8 status[0x8];
8962 u8 reserved_at_8[0x18];
8963
8964 u8 syndrome[0x20];
8965
8966 u8 reserved_at_40[0x40];
8967};
8968
8969struct mlx5_ifc_destroy_vport_lag_in_bits {
8970 u8 opcode[0x10];
8971 u8 reserved_at_10[0x10];
8972
8973 u8 reserved_at_20[0x10];
8974 u8 op_mod[0x10];
8975
8976 u8 reserved_at_40[0x40];
8977};
8978
24da0016
AL		 8979struct mlx5_ifc_alloc_memic_in_bits {
8980 u8 opcode[0x10];
8981 u8 reserved_at_10[0x10];
8982
8983 u8 reserved_at_20[0x10];
8984 u8 op_mod[0x10];
8985
8986 u8 reserved_at_30[0x20];
8987
8988 u8 reserved_at_40[0x18];
8989 u8 log_memic_addr_alignment[0x8];
8990
8991 u8 range_start_addr[0x40];
8992
8993 u8 range_size[0x20];
8994
8995 u8 memic_size[0x20];
8996};
8997
8998struct mlx5_ifc_alloc_memic_out_bits {
8999 u8 status[0x8];
9000 u8 reserved_at_8[0x18];
9001
9002 u8 syndrome[0x20];
9003
9004 u8 memic_start_addr[0x40];
9005};
9006
9007struct mlx5_ifc_dealloc_memic_in_bits {
9008 u8 opcode[0x10];
9009 u8 reserved_at_10[0x10];
9010
9011 u8 reserved_at_20[0x10];
9012 u8 op_mod[0x10];
9013
9014 u8 reserved_at_40[0x40];
9015
9016 u8 memic_start_addr[0x40];
9017
9018 u8 memic_size[0x20];
9019
9020 u8 reserved_at_e0[0x20];
9021};
9022
9023struct mlx5_ifc_dealloc_memic_out_bits {
9024 u8 status[0x8];
9025 u8 reserved_at_8[0x18];
9026
9027 u8 syndrome[0x20];
9028
9029 u8 reserved_at_40[0x40];
9030};
9031
d29b796a 9032#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)