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net/mlx5: Expose IP-in-IP TX and RX capability bits
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
66enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71};
72
f91e6d89
EBE		 73enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
59e9e8e4 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
f91e6d89
EBE		 78};
79
38b7ca92 80enum {
2acc7957 81 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 82};
83
9fba2b9b
AL		 84enum {
85 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
86};
87
88enum {
89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
b169e64a 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90fbca59 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
b169e64a
YK		 92};
93
94enum {
95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
8a06a79b 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
e4075c44
YH		 97 MLX5_OBJ_TYPE_MKEY = 0xff01,
98 MLX5_OBJ_TYPE_QP = 0xff02,
99 MLX5_OBJ_TYPE_PSV = 0xff03,
100 MLX5_OBJ_TYPE_RMP = 0xff04,
101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 MLX5_OBJ_TYPE_RQ = 0xff06,
103 MLX5_OBJ_TYPE_SQ = 0xff07,
104 MLX5_OBJ_TYPE_TIR = 0xff08,
105 MLX5_OBJ_TYPE_TIS = 0xff09,
106 MLX5_OBJ_TYPE_DCT = 0xff0a,
107 MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 MLX5_OBJ_TYPE_RQT = 0xff0e,
109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 MLX5_OBJ_TYPE_CQ = 0xff10,
9fba2b9b
AL		 111};
112
d29b796a
EC		 113enum {
114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
116 MLX5_CMD_OP_INIT_HCA = 0x102,
117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
118 MLX5_CMD_OP_ENABLE_HCA = 0x104,
119 MLX5_CMD_OP_DISABLE_HCA = 0x105,
120 MLX5_CMD_OP_QUERY_PAGES = 0x107,
121 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
122 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
124 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
1759d322
PP		 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
127 MLX5_CMD_OP_ALLOC_SF = 0x113,
128 MLX5_CMD_OP_DEALLOC_SF = 0x114,
d29b796a
EC		 129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 136 MLX5_CMD_OP_CREATE_EQ = 0x301,
137 MLX5_CMD_OP_DESTROY_EQ = 0x302,
138 MLX5_CMD_OP_QUERY_EQ = 0x303,
139 MLX5_CMD_OP_GEN_EQE = 0x304,
140 MLX5_CMD_OP_CREATE_CQ = 0x400,
141 MLX5_CMD_OP_DESTROY_CQ = 0x401,
142 MLX5_CMD_OP_QUERY_CQ = 0x402,
143 MLX5_CMD_OP_MODIFY_CQ = 0x403,
144 MLX5_CMD_OP_CREATE_QP = 0x500,
145 MLX5_CMD_OP_DESTROY_QP = 0x501,
146 MLX5_CMD_OP_RST2INIT_QP = 0x502,
147 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
148 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
149 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
151 MLX5_CMD_OP_2ERR_QP = 0x507,
152 MLX5_CMD_OP_2RST_QP = 0x50a,
153 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
156 MLX5_CMD_OP_CREATE_PSV = 0x600,
157 MLX5_CMD_OP_DESTROY_PSV = 0x601,
158 MLX5_CMD_OP_CREATE_SRQ = 0x700,
159 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
160 MLX5_CMD_OP_QUERY_SRQ = 0x702,
161 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 166 MLX5_CMD_OP_CREATE_DCT = 0x710,
167 MLX5_CMD_OP_DESTROY_DCT = 0x711,
168 MLX5_CMD_OP_DRAIN_DCT = 0x712,
169 MLX5_CMD_OP_QUERY_DCT = 0x713,
170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 171 MLX5_CMD_OP_CREATE_XRQ = 0x717,
172 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
173 MLX5_CMD_OP_QUERY_XRQ = 0x719,
174 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
b1635ee6
YH		 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
cd56f929 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
d29b796a
EC		 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 208 MLX5_CMD_OP_ALLOC_PD = 0x800,
209 MLX5_CMD_OP_DEALLOC_PD = 0x801,
210 MLX5_CMD_OP_ALLOC_UAR = 0x802,
211 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
213 MLX5_CMD_OP_ACCESS_REG = 0x805,
214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
217 MLX5_CMD_OP_MAD_IFC = 0x50d,
218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
220 MLX5_CMD_OP_NOP = 0x80d,
221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 237 MLX5_CMD_OP_CREATE_LAG = 0x840,
238 MLX5_CMD_OP_MODIFY_LAG = 0x841,
239 MLX5_CMD_OP_QUERY_LAG = 0x842,
240 MLX5_CMD_OP_DESTROY_LAG = 0x843,
241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 243 MLX5_CMD_OP_CREATE_TIR = 0x900,
244 MLX5_CMD_OP_MODIFY_TIR = 0x901,
245 MLX5_CMD_OP_DESTROY_TIR = 0x902,
246 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 247 MLX5_CMD_OP_CREATE_SQ = 0x904,
248 MLX5_CMD_OP_MODIFY_SQ = 0x905,
249 MLX5_CMD_OP_DESTROY_SQ = 0x906,
250 MLX5_CMD_OP_QUERY_SQ = 0x907,
251 MLX5_CMD_OP_CREATE_RQ = 0x908,
252 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
255 MLX5_CMD_OP_QUERY_RQ = 0x90b,
256 MLX5_CMD_OP_CREATE_RMP = 0x90c,
257 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
258 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
259 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 260 MLX5_CMD_OP_CREATE_TIS = 0x912,
261 MLX5_CMD_OP_MODIFY_TIS = 0x913,
262 MLX5_CMD_OP_DESTROY_TIS = 0x914,
263 MLX5_CMD_OP_QUERY_TIS = 0x915,
264 MLX5_CMD_OP_CREATE_RQT = 0x916,
265 MLX5_CMD_OP_MODIFY_RQT = 0x917,
266 MLX5_CMD_OP_DESTROY_RQT = 0x918,
267 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
d32d7c52 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
349125ba
PP		 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
86d56a1a 304 MLX5_CMD_OP_MAX
e281682b
SM		 305};
306
719598c9
YH		 307/* Valid range for general commands that don't work over an object */
308enum {
309 MLX5_CMD_OP_GENERAL_START = 0xb00,
310 MLX5_CMD_OP_GENERAL_END = 0xd00,
311};
312
e281682b
SM		 313struct mlx5_ifc_flow_table_fields_supported_bits {
314 u8 outer_dmac[0x1];
315 u8 outer_smac[0x1];
316 u8 outer_ether_type[0x1];
19cc7524 317 u8 outer_ip_version[0x1];
e281682b
SM		 318 u8 outer_first_prio[0x1];
319 u8 outer_first_cfi[0x1];
320 u8 outer_first_vid[0x1];
a8ade55f 321 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 322 u8 outer_second_prio[0x1];
323 u8 outer_second_cfi[0x1];
324 u8 outer_second_vid[0x1];
b4ff3a36 325 u8 reserved_at_b[0x1];
e281682b
SM		 326 u8 outer_sip[0x1];
327 u8 outer_dip[0x1];
328 u8 outer_frag[0x1];
329 u8 outer_ip_protocol[0x1];
330 u8 outer_ip_ecn[0x1];
331 u8 outer_ip_dscp[0x1];
332 u8 outer_udp_sport[0x1];
333 u8 outer_udp_dport[0x1];
334 u8 outer_tcp_sport[0x1];
335 u8 outer_tcp_dport[0x1];
336 u8 outer_tcp_flags[0x1];
337 u8 outer_gre_protocol[0x1];
338 u8 outer_gre_key[0x1];
339 u8 outer_vxlan_vni[0x1];
75d90e7d
YK		 340 u8 outer_geneve_vni[0x1];
341 u8 outer_geneve_oam[0x1];
342 u8 outer_geneve_protocol_type[0x1];
343 u8 outer_geneve_opt_len[0x1];
344 u8 reserved_at_1e[0x1];
e281682b
SM		 345 u8 source_eswitch_port[0x1];
346
347 u8 inner_dmac[0x1];
348 u8 inner_smac[0x1];
349 u8 inner_ether_type[0x1];
19cc7524 350 u8 inner_ip_version[0x1];
e281682b
SM		 351 u8 inner_first_prio[0x1];
352 u8 inner_first_cfi[0x1];
353 u8 inner_first_vid[0x1];
b4ff3a36 354 u8 reserved_at_27[0x1];
e281682b
SM		 355 u8 inner_second_prio[0x1];
356 u8 inner_second_cfi[0x1];
357 u8 inner_second_vid[0x1];
b4ff3a36 358 u8 reserved_at_2b[0x1];
e281682b
SM		 359 u8 inner_sip[0x1];
360 u8 inner_dip[0x1];
361 u8 inner_frag[0x1];
362 u8 inner_ip_protocol[0x1];
363 u8 inner_ip_ecn[0x1];
364 u8 inner_ip_dscp[0x1];
365 u8 inner_udp_sport[0x1];
366 u8 inner_udp_dport[0x1];
367 u8 inner_tcp_sport[0x1];
368 u8 inner_tcp_dport[0x1];
369 u8 inner_tcp_flags[0x1];
b4ff3a36 370 u8 reserved_at_37[0x9];
71c6e863 371
b169e64a
YK		 372 u8 geneve_tlv_option_0_data[0x1];
373 u8 reserved_at_41[0x4];
71c6e863
AL		 374 u8 outer_first_mpls_over_udp[0x4];
375 u8 outer_first_mpls_over_gre[0x4];
376 u8 inner_first_mpls[0x4];
377 u8 outer_first_mpls[0x4];
378 u8 reserved_at_55[0x2];
3346c487 379 u8 outer_esp_spi[0x1];
71c6e863 380 u8 reserved_at_58[0x2];
a550ddfc 381 u8 bth_dst_qp[0x1];
822e114b 382 u8 reserved_at_5b[0x5];
e281682b 383
822e114b
PB		 384 u8 reserved_at_60[0x18];
385 u8 metadata_reg_c_7[0x1];
386 u8 metadata_reg_c_6[0x1];
387 u8 metadata_reg_c_5[0x1];
388 u8 metadata_reg_c_4[0x1];
389 u8 metadata_reg_c_3[0x1];
390 u8 metadata_reg_c_2[0x1];
391 u8 metadata_reg_c_1[0x1];
392 u8 metadata_reg_c_0[0x1];
e281682b
SM		 393};
394
395struct mlx5_ifc_flow_table_prop_layout_bits {
396 u8 ft_support[0x1];
9dc0b289
AV		 397 u8 reserved_at_1[0x1];
398 u8 flow_counter[0x1];
26a81453 399 u8 flow_modify_en[0x1];
2cc43b49 400 u8 modify_root[0x1];
34a40e68
MG		 401 u8 identified_miss_table_mode[0x1];
402 u8 flow_table_modify[0x1];
60786f09 403 u8 reformat[0x1];
7adbde20 404 u8 decap[0x1];
0c06897a
OG		 405 u8 reserved_at_9[0x1];
406 u8 pop_vlan[0x1];
407 u8 push_vlan[0x1];
8da6fe2a
JL		 408 u8 reserved_at_c[0x1];
409 u8 pop_vlan_2[0x1];
410 u8 push_vlan_2[0x1];
bea4e1f6 411 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 412 u8 reserved_at_10[0x1];
413 u8 sw_owner[0x1];
bea4e1f6
MB		 414 u8 reformat_l3_tunnel_to_l2[0x1];
415 u8 reformat_l2_to_l3_tunnel[0x1];
416 u8 reformat_and_modify_action[0x1];
822e114b
PB		 417 u8 ignore_flow_level[0x1];
418 u8 reserved_at_16[0x1];
f6f7d6b5 419 u8 table_miss_action_domain[0x1];
c6d4e45d 420 u8 termination_table[0x1];
e0ebd8eb 421 u8 reformat_and_fwd_to_table[0x1];
78fb6122
HN		 422 u8 reserved_at_1a[0x2];
423 u8 ipsec_encrypt[0x1];
424 u8 ipsec_decrypt[0x1];
9d8feb46
AV		 425 u8 sw_owner_v2[0x1];
426 u8 reserved_at_1f[0x1];
78fb6122 427
613f53fe
EC		 428 u8 termination_table_raw_traffic[0x1];
429 u8 reserved_at_21[0x1];
e281682b 430 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 431 u8 log_max_modify_header_context[0x8];
432 u8 max_modify_header_actions[0x8];
e281682b
SM		 433 u8 max_ft_level[0x8];
434
b4ff3a36 435 u8 reserved_at_40[0x20];
e281682b 436
b4ff3a36 437 u8 reserved_at_60[0x18];
e281682b
SM		 438 u8 log_max_ft_num[0x8];
439
b4ff3a36 440 u8 reserved_at_80[0x18];
e281682b
SM		 441 u8 log_max_destination[0x8];
442
16f1c5bb
RS		 443 u8 log_max_flow_counter[0x8];
444 u8 reserved_at_a8[0x10];
e281682b
SM		 445 u8 log_max_flow[0x8];
446
b4ff3a36 447 u8 reserved_at_c0[0x40];
e281682b
SM		 448
449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
450
451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
452};
453
454struct mlx5_ifc_odp_per_transport_service_cap_bits {
455 u8 send[0x1];
456 u8 receive[0x1];
457 u8 write[0x1];
458 u8 read[0x1];
17d2f88f 459 u8 atomic[0x1];
e281682b 460 u8 srq_receive[0x1];
b4ff3a36 461 u8 reserved_at_6[0x1a];
e281682b
SM		 462};
463
464struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
465 u8 smac_47_16[0x20];
466
467 u8 smac_15_0[0x10];
468 u8 ethertype[0x10];
469
470 u8 dmac_47_16[0x20];
471
472 u8 dmac_15_0[0x10];
473 u8 first_prio[0x3];
474 u8 first_cfi[0x1];
475 u8 first_vid[0xc];
476
477 u8 ip_protocol[0x8];
478 u8 ip_dscp[0x6];
479 u8 ip_ecn[0x2];
10543365
MHY		 480 u8 cvlan_tag[0x1];
481 u8 svlan_tag[0x1];
e281682b 482 u8 frag[0x1];
19cc7524 483 u8 ip_version[0x4];
e281682b
SM		 484 u8 tcp_flags[0x9];
485
486 u8 tcp_sport[0x10];
487 u8 tcp_dport[0x10];
488
a8ade55f
OG		 489 u8 reserved_at_c0[0x18];
490 u8 ttl_hoplimit[0x8];
e281682b
SM		 491
492 u8 udp_sport[0x10];
493 u8 udp_dport[0x10];
494
b4d1f032 495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 496
b4d1f032 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 498};
499
5886a96a
OS		 500struct mlx5_ifc_nvgre_key_bits {
501 u8 hi[0x18];
502 u8 lo[0x8];
503};
504
505union mlx5_ifc_gre_key_bits {
506 struct mlx5_ifc_nvgre_key_bits nvgre;
507 u8 key[0x20];
508};
509
e281682b 510struct mlx5_ifc_fte_match_set_misc_bits {
97b5484e 511 u8 gre_c_present[0x1];
d32d7c52 512 u8 reserved_at_1[0x1];
97b5484e
AV		 513 u8 gre_k_present[0x1];
514 u8 gre_s_present[0x1];
515 u8 source_vhca_port[0x4];
7486216b 516 u8 source_sqn[0x18];
e281682b 517
3e99df87 518 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 519 u8 source_port[0x10];
520
521 u8 outer_second_prio[0x3];
522 u8 outer_second_cfi[0x1];
523 u8 outer_second_vid[0xc];
524 u8 inner_second_prio[0x3];
525 u8 inner_second_cfi[0x1];
526 u8 inner_second_vid[0xc];
527
10543365
MHY		 528 u8 outer_second_cvlan_tag[0x1];
529 u8 inner_second_cvlan_tag[0x1];
530 u8 outer_second_svlan_tag[0x1];
531 u8 inner_second_svlan_tag[0x1];
532 u8 reserved_at_64[0xc];
e281682b
SM		 533 u8 gre_protocol[0x10];
534
5886a96a 535 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 536
537 u8 vxlan_vni[0x18];
b4ff3a36 538 u8 reserved_at_b8[0x8];
e281682b 539
75d90e7d
YK		 540 u8 geneve_vni[0x18];
541 u8 reserved_at_d8[0x7];
542 u8 geneve_oam[0x1];
e281682b 543
b4ff3a36 544 u8 reserved_at_e0[0xc];
e281682b
SM		 545 u8 outer_ipv6_flow_label[0x14];
546
b4ff3a36 547 u8 reserved_at_100[0xc];
e281682b
SM		 548 u8 inner_ipv6_flow_label[0x14];
549
75d90e7d
YK		 550 u8 reserved_at_120[0xa];
551 u8 geneve_opt_len[0x6];
552 u8 geneve_protocol_type[0x10];
553
554 u8 reserved_at_140[0x8];
a550ddfc 555 u8 bth_dst_qp[0x18];
3346c487
BP		 556 u8 reserved_at_160[0x20];
557 u8 outer_esp_spi[0x20];
558 u8 reserved_at_1a0[0x60];
e281682b
SM		 559};
560
71c6e863
AL		 561struct mlx5_ifc_fte_match_mpls_bits {
562 u8 mpls_label[0x14];
563 u8 mpls_exp[0x3];
564 u8 mpls_s_bos[0x1];
565 u8 mpls_ttl[0x8];
566};
567
568struct mlx5_ifc_fte_match_set_misc2_bits {
569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
570
571 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
572
573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
574
575 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
576
65c0f2c1
JL		 577 u8 metadata_reg_c_7[0x20];
578
579 u8 metadata_reg_c_6[0x20];
580
581 u8 metadata_reg_c_5[0x20];
582
583 u8 metadata_reg_c_4[0x20];
584
585 u8 metadata_reg_c_3[0x20];
586
587 u8 metadata_reg_c_2[0x20];
588
589 u8 metadata_reg_c_1[0x20];
590
591 u8 metadata_reg_c_0[0x20];
71c6e863
AL		 592
593 u8 metadata_reg_a[0x20];
594
356d411c 595 u8 reserved_at_1a0[0x60];
71c6e863
AL		 596};
597
b169e64a 598struct mlx5_ifc_fte_match_set_misc3_bits {
97b5484e
AV		 599 u8 inner_tcp_seq_num[0x20];
600
601 u8 outer_tcp_seq_num[0x20];
602
603 u8 inner_tcp_ack_num[0x20];
604
605 u8 outer_tcp_ack_num[0x20];
606
607 u8 reserved_at_80[0x8];
608 u8 outer_vxlan_gpe_vni[0x18];
609
610 u8 outer_vxlan_gpe_next_protocol[0x8];
611 u8 outer_vxlan_gpe_flags[0x8];
612 u8 reserved_at_b0[0x10];
613
614 u8 icmp_header_data[0x20];
615
616 u8 icmpv6_header_data[0x20];
617
618 u8 icmp_type[0x8];
619 u8 icmp_code[0x8];
620 u8 icmpv6_type[0x8];
621 u8 icmpv6_code[0x8];
622
b169e64a 623 u8 geneve_tlv_option_0_data[0x20];
97b5484e 624
b169e64a
YK		 625 u8 reserved_at_140[0xc0];
626};
627
7da3ad6c
MS		 628struct mlx5_ifc_fte_match_set_misc4_bits {
629 u8 prog_sample_field_value_0[0x20];
630
631 u8 prog_sample_field_id_0[0x20];
632
633 u8 prog_sample_field_value_1[0x20];
634
635 u8 prog_sample_field_id_1[0x20];
636
637 u8 prog_sample_field_value_2[0x20];
638
639 u8 prog_sample_field_id_2[0x20];
640
641 u8 prog_sample_field_value_3[0x20];
642
643 u8 prog_sample_field_id_3[0x20];
644
645 u8 reserved_at_100[0x100];
646};
647
e281682b
SM		 648struct mlx5_ifc_cmd_pas_bits {
649 u8 pa_h[0x20];
650
651 u8 pa_l[0x14];
b4ff3a36 652 u8 reserved_at_34[0xc];
e281682b
SM		 653};
654
655struct mlx5_ifc_uint64_bits {
656 u8 hi[0x20];
657
658 u8 lo[0x20];
659};
660
661enum {
662 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
663 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
664 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
665 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
666 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
667 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
668 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
669 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
670 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
671 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
672};
673
674struct mlx5_ifc_ads_bits {
675 u8 fl[0x1];
676 u8 free_ar[0x1];
b4ff3a36 677 u8 reserved_at_2[0xe];
e281682b
SM		 678 u8 pkey_index[0x10];
679
b4ff3a36 680 u8 reserved_at_20[0x8];
e281682b
SM		 681 u8 grh[0x1];
682 u8 mlid[0x7];
683 u8 rlid[0x10];
684
685 u8 ack_timeout[0x5];
b4ff3a36 686 u8 reserved_at_45[0x3];
e281682b 687 u8 src_addr_index[0x8];
b4ff3a36 688 u8 reserved_at_50[0x4];
e281682b
SM		 689 u8 stat_rate[0x4];
690 u8 hop_limit[0x8];
691
b4ff3a36 692 u8 reserved_at_60[0x4];
e281682b
SM		 693 u8 tclass[0x8];
694 u8 flow_label[0x14];
695
696 u8 rgid_rip[16][0x8];
697
b4ff3a36 698 u8 reserved_at_100[0x4];
e281682b
SM		 699 u8 f_dscp[0x1];
700 u8 f_ecn[0x1];
b4ff3a36 701 u8 reserved_at_106[0x1];
e281682b
SM		 702 u8 f_eth_prio[0x1];
703 u8 ecn[0x2];
704 u8 dscp[0x6];
705 u8 udp_sport[0x10];
706
707 u8 dei_cfi[0x1];
708 u8 eth_prio[0x3];
709 u8 sl[0x4];
32f69e4b 710 u8 vhca_port_num[0x8];
e281682b
SM		 711 u8 rmac_47_32[0x10];
712
713 u8 rmac_31_0[0x20];
714};
715
716struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 717 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 718 u8 nic_rx_multi_path_tirs_fts[0x1];
719 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
13a7e459
ES		 720 u8 reserved_at_3[0x4];
721 u8 sw_owner_reformat_supported[0x1];
722 u8 reserved_at_8[0x18];
723
bea4e1f6
MB		 724 u8 encap_general_header[0x1];
725 u8 reserved_at_21[0xa];
726 u8 log_max_packet_reformat_context[0x5];
727 u8 reserved_at_30[0x6];
728 u8 max_encap_header_size[0xa];
729 u8 reserved_at_40[0x1c0];
e281682b
SM		 730
731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
732
d83eb50e 733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
e281682b
SM		 734
735 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
736
737 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
738
24670b1a 739 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
e281682b
SM		 740
741 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
742
97b5484e
AV		 743 u8 reserved_at_e00[0x1200];
744
745 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
746
747 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
748
749 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
750
751 u8 reserved_at_20c0[0x5f40];
e281682b
SM		 752};
753
65c0f2c1
JL		 754enum {
755 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
756 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
757 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
758 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
759 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
760 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
761 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
762 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
763};
764
495716b1 765struct mlx5_ifc_flow_table_eswitch_cap_bits {
65c0f2c1 766 u8 fdb_to_vport_reg_c_id[0x8];
822e114b
PB		 767 u8 reserved_at_8[0xd];
768 u8 fdb_modify_header_fwd_to_table[0x1];
769 u8 reserved_at_16[0x1];
65c0f2c1
JL		 770 u8 flow_source[0x1];
771 u8 reserved_at_18[0x2];
b9aa0ba1 772 u8 multi_fdb_encap[0x1];
86f5d0f3 773 u8 egress_acl_forward_to_vport[0x1];
663f146f
VP		 774 u8 fdb_multi_path_to_table[0x1];
775 u8 reserved_at_1d[0x3];
776
777 u8 reserved_at_20[0x1e0];
495716b1
SM		 778
779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
780
781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
782
783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
784
97b5484e
AV		 785 u8 reserved_at_800[0x1000];
786
787 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
788
789 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
790
791 u8 sw_steering_uplink_icm_address_rx[0x40];
792
793 u8 sw_steering_uplink_icm_address_tx[0x40];
794
795 u8 reserved_at_1900[0x6700];
495716b1
SM		 796};
797
8bb957d2
SK		 798enum {
799 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
800 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
801};
802
d6666753
SM		 803struct mlx5_ifc_e_switch_cap_bits {
804 u8 vport_svlan_strip[0x1];
805 u8 vport_cvlan_strip[0x1];
806 u8 vport_svlan_insert[0x1];
807 u8 vport_cvlan_insert_if_not_exist[0x1];
808 u8 vport_cvlan_insert_overwrite[0x1];
65c0f2c1
JL		 809 u8 reserved_at_5[0x3];
810 u8 esw_uplink_ingress_acl[0x1];
811 u8 reserved_at_9[0x10];
6706a3b9
VP		 812 u8 esw_functions_changed[0x1];
813 u8 reserved_at_1a[0x1];
81cd229c 814 u8 ecpf_vport_exists[0x1];
8bb957d2 815 u8 counter_eswitch_affinity[0x1];
a6d04569 816 u8 merged_eswitch[0x1];
23898c76
NO		 817 u8 nic_vport_node_guid_modify[0x1];
818 u8 nic_vport_port_guid_modify[0x1];
d6666753 819
7adbde20
HHZ		 820 u8 vxlan_encap_decap[0x1];
821 u8 nvgre_encap_decap[0x1];
1b115498
EB		 822 u8 reserved_at_22[0x1];
823 u8 log_max_fdb_encap_uplink[0x5];
824 u8 reserved_at_21[0x3];
60786f09 825 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 826 u8 reserved_2b[0x6];
827 u8 max_encap_header_size[0xa];
828
1759d322
PP		 829 u8 reserved_at_40[0xb];
830 u8 log_max_esw_sf[0x5];
831 u8 esw_sf_base_id[0x10];
832
833 u8 reserved_at_60[0x7a0];
7adbde20 834
d6666753
SM		 835};
836
7486216b
SM		 837struct mlx5_ifc_qos_cap_bits {
838 u8 packet_pacing[0x1];
813f8540 839 u8 esw_scheduling[0x1];
c9497c98
MHY		 840 u8 esw_bw_share[0x1];
841 u8 esw_rate_limit[0x1];
05d3ac97
BW		 842 u8 reserved_at_4[0x1];
843 u8 packet_pacing_burst_bound[0x1];
844 u8 packet_pacing_typical_size[0x1];
1326034b
YH		 845 u8 reserved_at_7[0x4];
846 u8 packet_pacing_uid[0x1];
847 u8 reserved_at_c[0x14];
813f8540
MHY		 848
849 u8 reserved_at_20[0x20];
850
7486216b 851 u8 packet_pacing_max_rate[0x20];
813f8540 852
7486216b 853 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 854
855 u8 reserved_at_80[0x10];
7486216b 856 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 857
858 u8 esw_element_type[0x10];
859 u8 esw_tsar_type[0x10];
860
861 u8 reserved_at_c0[0x10];
862 u8 max_qos_para_vport[0x10];
863
864 u8 max_tsar_bw_share[0x20];
865
866 u8 reserved_at_100[0x700];
7486216b
SM		 867};
868
2fcb12df 869struct mlx5_ifc_debug_cap_bits {
0b9055a1
MS		 870 u8 core_dump_general[0x1];
871 u8 core_dump_qp[0x1];
609b8272
AL		 872 u8 reserved_at_2[0x7];
873 u8 resource_dump[0x1];
874 u8 reserved_at_a[0x16];
2fcb12df
IK		 875
876 u8 reserved_at_20[0x2];
877 u8 stall_detect[0x1];
878 u8 reserved_at_23[0x1d];
879
880 u8 reserved_at_40[0x7c0];
881};
882
e281682b
SM		 883struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
884 u8 csum_cap[0x1];
885 u8 vlan_cap[0x1];
886 u8 lro_cap[0x1];
887 u8 lro_psh_flag[0x1];
888 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 889 u8 reserved_at_5[0x2];
890 u8 wqe_vlan_insert[0x1];
66189961 891 u8 self_lb_en_modifiable[0x1];
b4ff3a36 892 u8 reserved_at_9[0x2];
e281682b 893 u8 max_lso_cap[0x5];
c226dc22 894 u8 multi_pkt_send_wqe[0x2];
cff92d7c 895 u8 wqe_inline_mode[0x2];
e281682b 896 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 897 u8 reg_umr_sq[0x1];
898 u8 scatter_fcs[0x1];
050da902 899 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 900 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 901 u8 reserved_at_1c[0x2];
27299841 902 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 903 u8 tunnel_stateless_vxlan[0x1];
904
547eede0
IT		 905 u8 swp[0x1];
906 u8 swp_csum[0x1];
907 u8 swp_lso[0x1];
db849faa 908 u8 cqe_checksum_full[0x1];
41e684ef
AV		 909 u8 tunnel_stateless_geneve_tx[0x1];
910 u8 tunnel_stateless_mpls_over_udp[0x1];
911 u8 tunnel_stateless_mpls_over_gre[0x1];
912 u8 tunnel_stateless_vxlan_gpe[0x1];
913 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
caa18547 914 u8 tunnel_stateless_ip_over_ip[0x1];
2b58f6d9 915 u8 insert_trailer[0x1];
21adf05d
AL		 916 u8 reserved_at_2b[0x1];
917 u8 tunnel_stateless_ip_over_ip_rx[0x1];
918 u8 tunnel_stateless_ip_over_ip_tx[0x1];
919 u8 reserved_at_2e[0x2];
22a65aa8
GP		 920 u8 max_vxlan_udp_ports[0x8];
921 u8 reserved_at_38[0x6];
4d350f1f
MG		 922 u8 max_geneve_opt_len[0x1];
923 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 924
b4ff3a36 925 u8 reserved_at_40[0x10];
e281682b
SM		 926 u8 lro_min_mss_size[0x10];
927
b4ff3a36 928 u8 reserved_at_60[0x120];
e281682b
SM		 929
930 u8 lro_timer_supported_periods[4][0x20];
931
b4ff3a36 932 u8 reserved_at_200[0x600];
e281682b
SM		 933};
934
935struct mlx5_ifc_roce_cap_bits {
936 u8 roce_apm[0x1];
59e9e8e4
MZ		 937 u8 reserved_at_1[0x3];
938 u8 sw_r_roce_src_udp_port[0x1];
939 u8 reserved_at_5[0x1b];
e281682b 940
b4ff3a36 941 u8 reserved_at_20[0x60];
e281682b 942
b4ff3a36 943 u8 reserved_at_80[0xc];
e281682b 944 u8 l3_type[0x4];
b4ff3a36 945 u8 reserved_at_90[0x8];
e281682b
SM		 946 u8 roce_version[0x8];
947
b4ff3a36 948 u8 reserved_at_a0[0x10];
e281682b
SM		 949 u8 r_roce_dest_udp_port[0x10];
950
951 u8 r_roce_max_src_udp_port[0x10];
952 u8 r_roce_min_src_udp_port[0x10];
953
b4ff3a36 954 u8 reserved_at_e0[0x10];
e281682b
SM		 955 u8 roce_address_table_size[0x10];
956
b4ff3a36 957 u8 reserved_at_100[0x700];
e281682b
SM		 958};
959
97b5484e
AV		 960struct mlx5_ifc_sync_steering_in_bits {
961 u8 opcode[0x10];
962 u8 uid[0x10];
963
964 u8 reserved_at_20[0x10];
965 u8 op_mod[0x10];
966
967 u8 reserved_at_40[0xc0];
968};
969
970struct mlx5_ifc_sync_steering_out_bits {
971 u8 status[0x8];
972 u8 reserved_at_8[0x18];
973
974 u8 syndrome[0x20];
975
976 u8 reserved_at_40[0x40];
977};
978
e72bd817
AL		 979struct mlx5_ifc_device_mem_cap_bits {
980 u8 memic[0x1];
981 u8 reserved_at_1[0x1f];
982
983 u8 reserved_at_20[0xb];
984 u8 log_min_memic_alloc_size[0x5];
985 u8 reserved_at_30[0x8];
986 u8 log_max_memic_addr_alignment[0x8];
987
988 u8 memic_bar_start_addr[0x40];
989
990 u8 memic_bar_size[0x20];
991
992 u8 max_memic_size[0x20];
993
9fba2b9b
AL		 994 u8 steering_sw_icm_start_address[0x40];
995
996 u8 reserved_at_100[0x8];
997 u8 log_header_modify_sw_icm_size[0x8];
998 u8 reserved_at_110[0x2];
999 u8 log_sw_icm_alloc_granularity[0x6];
1000 u8 log_steering_sw_icm_size[0x8];
1001
1002 u8 reserved_at_120[0x20];
1003
1004 u8 header_modify_sw_icm_start_address[0x40];
1005
1006 u8 reserved_at_180[0x680];
e72bd817
AL		 1007};
1008
b9a7ba55
YH		 1009struct mlx5_ifc_device_event_cap_bits {
1010 u8 user_affiliated_events[4][0x40];
1011
1012 u8 user_unaffiliated_events[4][0x40];
1013};
1014
8a06a79b
EC		 1015struct mlx5_ifc_virtio_emulation_cap_bits {
1016 u8 desc_tunnel_offload_type[0x1];
1017 u8 eth_frame_offload_type[0x1];
1018 u8 virtio_version_1_0[0x1];
1019 u8 device_features_bits_mask[0xd];
1020 u8 event_mode[0x8];
1021 u8 virtio_queue_type[0x8];
90fbca59 1022
8a06a79b
EC		 1023 u8 max_tunnel_desc[0x10];
1024 u8 reserved_at_30[0x3];
90fbca59
YH		 1025 u8 log_doorbell_stride[0x5];
1026 u8 reserved_at_38[0x3];
1027 u8 log_doorbell_bar_size[0x5];
1028
1029 u8 doorbell_bar_offset[0x40];
1030
8a06a79b
EC		 1031 u8 max_emulated_devices[0x8];
1032 u8 max_num_virtio_queues[0x18];
1033
1034 u8 reserved_at_a0[0x60];
1035
1036 u8 umem_1_buffer_param_a[0x20];
1037
1038 u8 umem_1_buffer_param_b[0x20];
1039
1040 u8 umem_2_buffer_param_a[0x20];
1041
1042 u8 umem_2_buffer_param_b[0x20];
1043
1044 u8 umem_3_buffer_param_a[0x20];
1045
1046 u8 umem_3_buffer_param_b[0x20];
1047
1048 u8 reserved_at_1c0[0x640];
90fbca59
YH		 1049};
1050
e281682b
SM		 1051enum {
1052 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1053 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1054 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1055 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1056 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1057 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1058 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1059 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1060 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1061};
1062
1063enum {
1064 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1065 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1066 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1067 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1068 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1069 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1070 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1071 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1072 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1073};
1074
1075struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 1076 u8 reserved_at_0[0x40];
e281682b 1077
bd10838a 1078 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 1079 u8 reserved_at_42[0x4];
bd10838a 1080 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 1081
b4ff3a36 1082 u8 reserved_at_47[0x19];
e281682b 1083
b4ff3a36 1084 u8 reserved_at_60[0x20];
e281682b 1085
b4ff3a36 1086 u8 reserved_at_80[0x10];
f91e6d89 1087 u8 atomic_operations[0x10];
e281682b 1088
b4ff3a36 1089 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 1090 u8 atomic_size_qp[0x10];
1091
b4ff3a36 1092 u8 reserved_at_c0[0x10];
e281682b
SM		 1093 u8 atomic_size_dc[0x10];
1094
b4ff3a36 1095 u8 reserved_at_e0[0x720];
e281682b
SM		 1096};
1097
1098struct mlx5_ifc_odp_cap_bits {
b4ff3a36 1099 u8 reserved_at_0[0x40];
e281682b
SM		 1100
1101 u8 sig[0x1];
b4ff3a36 1102 u8 reserved_at_41[0x1f];
e281682b 1103
b4ff3a36 1104 u8 reserved_at_60[0x20];
e281682b
SM		 1105
1106 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1107
1108 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1109
1110 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1111
dda7a817
MS		 1112 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1113
00679b63
MG		 1114 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1115
1116 u8 reserved_at_120[0x6E0];
e281682b
SM		 1117};
1118
3f0393a5
SG		 1119struct mlx5_ifc_calc_op {
1120 u8 reserved_at_0[0x10];
1121 u8 reserved_at_10[0x9];
1122 u8 op_swap_endianness[0x1];
1123 u8 op_min[0x1];
1124 u8 op_xor[0x1];
1125 u8 op_or[0x1];
1126 u8 op_and[0x1];
1127 u8 op_max[0x1];
1128 u8 op_add[0x1];
1129};
1130
1131struct mlx5_ifc_vector_calc_cap_bits {
1132 u8 calc_matrix[0x1];
1133 u8 reserved_at_1[0x1f];
1134 u8 reserved_at_20[0x8];
1135 u8 max_vec_count[0x8];
1136 u8 reserved_at_30[0xd];
1137 u8 max_chunk_size[0x3];
1138 struct mlx5_ifc_calc_op calc0;
1139 struct mlx5_ifc_calc_op calc1;
1140 struct mlx5_ifc_calc_op calc2;
1141 struct mlx5_ifc_calc_op calc3;
1142
c74d90c1 1143 u8 reserved_at_c0[0x720];
3f0393a5
SG		 1144};
1145
a12ff35e
EBE		 1146struct mlx5_ifc_tls_cap_bits {
1147 u8 tls_1_2_aes_gcm_128[0x1];
1148 u8 tls_1_3_aes_gcm_128[0x1];
1149 u8 tls_1_2_aes_gcm_256[0x1];
1150 u8 tls_1_3_aes_gcm_256[0x1];
1151 u8 reserved_at_4[0x1c];
1152
1153 u8 reserved_at_20[0x7e0];
1154};
1155
2b58f6d9
RS		 1156struct mlx5_ifc_ipsec_cap_bits {
1157 u8 ipsec_full_offload[0x1];
1158 u8 ipsec_crypto_offload[0x1];
1159 u8 ipsec_esn[0x1];
1160 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1161 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1162 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1163 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1164 u8 reserved_at_7[0x4];
1165 u8 log_max_ipsec_offload[0x5];
1166 u8 reserved_at_10[0x10];
1167
1168 u8 min_log_ipsec_full_replay_window[0x8];
1169 u8 max_log_ipsec_full_replay_window[0x8];
1170 u8 reserved_at_30[0x7d0];
1171};
1172
e281682b
SM		 1173enum {
1174 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1175 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 1176 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 1177 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 1178};
1179
1180enum {
1181 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1182 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1183};
1184
1185enum {
1186 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1187 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1188 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1189 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1190 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1191};
1192
1193enum {
1194 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1195 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1196 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1197 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1198 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1199 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1200};
1201
1202enum {
1203 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1204 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1205};
1206
1207enum {
1208 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1209 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1210 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1211};
1212
1213enum {
1214 MLX5_CAP_PORT_TYPE_IB = 0x0,
1215 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 1216};
1217
1410a90a
MG		 1218enum {
1219 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1220 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1221 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1222};
1223
97b5484e 1224enum {
a18fab48 1225 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
97b5484e
AV		 1226 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1227 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1228 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1229};
1230
9d43faac
YH		 1231enum {
1232 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 1233 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 1234};
1235
8536a6bf
GT		 1236#define MLX5_FC_BULK_SIZE_FACTOR 128
1237
1238enum mlx5_fc_bulk_alloc_bitmask {
1239 MLX5_FC_BULK_128 = (1 << 0),
1240 MLX5_FC_BULK_256 = (1 << 1),
1241 MLX5_FC_BULK_512 = (1 << 2),
1242 MLX5_FC_BULK_1024 = (1 << 3),
1243 MLX5_FC_BULK_2048 = (1 << 4),
1244 MLX5_FC_BULK_4096 = (1 << 5),
1245 MLX5_FC_BULK_8192 = (1 << 6),
1246 MLX5_FC_BULK_16384 = (1 << 7),
1247};
1248
1249#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1250
b775516b 1251struct mlx5_ifc_cmd_hca_cap_bits {
349125ba
PP		 1252 u8 reserved_at_0[0x20];
1253
1254 u8 reserved_at_20[0x3];
1255 u8 event_on_vhca_state_teardown_request[0x1];
1256 u8 event_on_vhca_state_in_use[0x1];
1257 u8 event_on_vhca_state_active[0x1];
1258 u8 event_on_vhca_state_allocated[0x1];
1259 u8 event_on_vhca_state_invalid[0x1];
1260 u8 reserved_at_28[0x8];
32f69e4b
DJ		 1261 u8 vhca_id[0x10];
1262
1263 u8 reserved_at_40[0x40];
b775516b
EC		 1264
1265 u8 log_max_srq_sz[0x8];
1266 u8 log_max_qp_sz[0x8];
b9a7ba55
YH		 1267 u8 event_cap[0x1];
1268 u8 reserved_at_91[0x7];
316793fb
EB		 1269 u8 prio_tag_required[0x1];
1270 u8 reserved_at_99[0x2];
b775516b
EC		 1271 u8 log_max_qp[0x5];
1272
6b646a7e
LR		 1273 u8 reserved_at_a0[0x3];
1274 u8 ece_support[0x1];
1275 u8 reserved_at_a4[0x7];
e281682b 1276 u8 log_max_srq[0x5];
59d2ae1d
EBE		 1277 u8 reserved_at_b0[0x2];
1278 u8 ts_cqe_to_dest_cqn[0x1];
1279 u8 reserved_at_b3[0xd];
b775516b 1280
7d47433c 1281 u8 max_sgl_for_optimized_performance[0x8];
b775516b 1282 u8 log_max_cq_sz[0x8];
042dd05b
ML		 1283 u8 relaxed_ordering_write_umr[0x1];
1284 u8 relaxed_ordering_read_umr[0x1];
1285 u8 reserved_at_d2[0x7];
8a06a79b
EC		 1286 u8 virtio_net_device_emualtion_manager[0x1];
1287 u8 virtio_blk_device_emualtion_manager[0x1];
b775516b
EC		 1288 u8 log_max_cq[0x5];
1289
1290 u8 log_max_eq_sz[0x8];
a880a6dd
MG		 1291 u8 relaxed_ordering_write[0x1];
1292 u8 relaxed_ordering_read[0x1];
b775516b 1293 u8 log_max_mkey[0x6];
b183ee27
LR		 1294 u8 reserved_at_f0[0x8];
1295 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 1296 u8 reserved_at_f9[0x2];
1297 u8 fast_teardown[0x1];
b775516b
EC		 1298 u8 log_max_eq[0x4];
1299
1300 u8 max_indirection[0x8];
bcda1aca 1301 u8 fixed_buffer_size[0x1];
b775516b 1302 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 1303 u8 force_teardown[0x1];
1304 u8 reserved_at_111[0x1];
b775516b 1305 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 1306 u8 umr_extended_translation_offset[0x1];
1307 u8 null_mkey[0x1];
b775516b
EC		 1308 u8 log_max_klm_list_size[0x6];
1309
b4ff3a36 1310 u8 reserved_at_120[0xa];
b775516b 1311 u8 log_max_ra_req_dc[0x6];
b4ff3a36 1312 u8 reserved_at_130[0xa];
b775516b
EC		 1313 u8 log_max_ra_res_dc[0x6];
1314
0e1533bb
EBE		 1315 u8 reserved_at_140[0x6];
1316 u8 release_all_pages[0x1];
1317 u8 reserved_at_147[0x2];
8fd5b75d 1318 u8 roce_accl[0x1];
b775516b 1319 u8 log_max_ra_req_qp[0x6];
b4ff3a36 1320 u8 reserved_at_150[0xa];
b775516b
EC		 1321 u8 log_max_ra_res_qp[0x6];
1322
f32f5bd2 1323 u8 end_pad[0x1];
b775516b
EC		 1324 u8 cc_query_allowed[0x1];
1325 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 1326 u8 start_pad[0x1];
1327 u8 cache_line_128byte[0x1];
f8efee08
MZ		 1328 u8 reserved_at_165[0x4];
1329 u8 rts2rts_qp_counters_set_id[0x1];
30b10e89
MS		 1330 u8 reserved_at_16a[0x2];
1331 u8 vnic_env_int_rq_oob[0x1];
948d3f90
AL		 1332 u8 sbcam_reg[0x1];
1333 u8 reserved_at_16e[0x1];
c02762eb 1334 u8 qcam_reg[0x1];
e281682b 1335 u8 gid_table_size[0x10];
b775516b 1336
e281682b
SM		 1337 u8 out_of_seq_cnt[0x1];
1338 u8 vport_counters[0x1];
7486216b 1339 u8 retransmission_q_counters[0x1];
2fcb12df 1340 u8 debug[0x1];
83b502a1 1341 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1342 u8 rq_delay_drop[0x1];
b775516b
EC		 1343 u8 max_qp_cnt[0xa];
1344 u8 pkey_table_size[0x10];
1345
e281682b
SM		 1346 u8 vport_group_manager[0x1];
1347 u8 vhca_group_manager[0x1];
1348 u8 ib_virt[0x1];
1349 u8 eth_virt[0x1];
61c5b5c9 1350 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1351 u8 ets[0x1];
1352 u8 nic_flow_table[0x1];
0efc8562 1353 u8 eswitch_manager[0x1];
e72bd817 1354 u8 device_memory[0x1];
cfdcbcea
GP		 1355 u8 mcam_reg[0x1];
1356 u8 pcam_reg[0x1];
b775516b 1357 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1358 u8 port_module_event[0x1];
58dcb60a 1359 u8 enhanced_error_q_counters[0x1];
7d5e1423 1360 u8 ports_check[0x1];
7b13558f 1361 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1362 u8 disable_link_up[0x1];
1363 u8 beacon_led[0x1];
e281682b 1364 u8 port_type[0x2];
b775516b
EC		 1365 u8 num_ports[0x8];
1366
f9a1ef72
EE		 1367 u8 reserved_at_1c0[0x1];
1368 u8 pps[0x1];
1369 u8 pps_modify[0x1];
b775516b 1370 u8 log_max_msg[0x5];
e1c9c62b 1371 u8 reserved_at_1c8[0x4];
4f3961ee 1372 u8 max_tc[0x4];
1865ea9a 1373 u8 temp_warn_event[0x1];
7486216b 1374 u8 dcbx[0x1];
246ac981
MG		 1375 u8 general_notification_event[0x1];
1376 u8 reserved_at_1d3[0x2];
e29341fb 1377 u8 fpga[0x1];
928cfe87
TT		 1378 u8 rol_s[0x1];
1379 u8 rol_g[0x1];
e1c9c62b 1380 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1381 u8 wol_s[0x1];
1382 u8 wol_g[0x1];
1383 u8 wol_a[0x1];
1384 u8 wol_b[0x1];
1385 u8 wol_m[0x1];
1386 u8 wol_u[0x1];
1387 u8 wol_p[0x1];
b775516b
EC		 1388
1389 u8 stat_rate_support[0x10];
3df01077
MS		 1390 u8 reserved_at_1f0[0x1];
1391 u8 pci_sync_for_fw_update_event[0x1];
cfc1a89e
MG		 1392 u8 reserved_at_1f2[0x6];
1393 u8 init2_lag_tx_port_affinity[0x1];
1394 u8 reserved_at_1fa[0x3];
e281682b 1395 u8 cqe_version[0x4];
b775516b 1396
e281682b 1397 u8 compact_address_vector[0x1];
7d5e1423 1398 u8 striding_rq[0x1];
500a3d0d
ES		 1399 u8 reserved_at_202[0x1];
1400 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1401 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1402 u8 reserved_at_205[0x1];
1403 u8 repeated_block_disabled[0x1];
1404 u8 umr_modify_entity_size_disabled[0x1];
1405 u8 umr_modify_atomic_disabled[0x1];
1406 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1407 u8 umr_fence[0x2];
94a04d1d
YC		 1408 u8 dc_req_scat_data_cqe[0x1];
1409 u8 reserved_at_20d[0x2];
e281682b 1410 u8 drain_sigerr[0x1];
b775516b
EC		 1411 u8 cmdif_checksum[0x2];
1412 u8 sigerr_cqe[0x1];
e1c9c62b 1413 u8 reserved_at_213[0x1];
b775516b
EC		 1414 u8 wq_signature[0x1];
1415 u8 sctr_data_cqe[0x1];
e1c9c62b 1416 u8 reserved_at_216[0x1];
b775516b
EC		 1417 u8 sho[0x1];
1418 u8 tph[0x1];
1419 u8 rf[0x1];
e281682b 1420 u8 dct[0x1];
7486216b 1421 u8 qos[0x1];
e281682b 1422 u8 eth_net_offloads[0x1];
b775516b
EC		 1423 u8 roce[0x1];
1424 u8 atomic[0x1];
e1c9c62b 1425 u8 reserved_at_21f[0x1];
b775516b
EC		 1426
1427 u8 cq_oi[0x1];
1428 u8 cq_resize[0x1];
1429 u8 cq_moderation[0x1];
e1c9c62b 1430 u8 reserved_at_223[0x3];
e281682b 1431 u8 cq_eq_remap[0x1];
b775516b
EC		 1432 u8 pg[0x1];
1433 u8 block_lb_mc[0x1];
e1c9c62b 1434 u8 reserved_at_229[0x1];
e281682b 1435 u8 scqe_break_moderation[0x1];
7d5e1423 1436 u8 cq_period_start_from_cqe[0x1];
b775516b 1437 u8 cd[0x1];
e1c9c62b 1438 u8 reserved_at_22d[0x1];
b775516b 1439 u8 apm[0x1];
3f0393a5 1440 u8 vector_calc[0x1];
7d5e1423 1441 u8 umr_ptr_rlky[0x1];
d2370e0a 1442 u8 imaicl[0x1];
3fd3c80a
DG		 1443 u8 qp_packet_based[0x1];
1444 u8 reserved_at_233[0x3];
b775516b
EC		 1445 u8 qkv[0x1];
1446 u8 pkv[0x1];
b11a4f9c
HE		 1447 u8 set_deth_sqpn[0x1];
1448 u8 reserved_at_239[0x3];
b775516b
EC		 1449 u8 xrc[0x1];
1450 u8 ud[0x1];
1451 u8 uc[0x1];
1452 u8 rc[0x1];
1453
a6d51b68
EC		 1454 u8 uar_4k[0x1];
1455 u8 reserved_at_241[0x9];
b775516b 1456 u8 uar_sz[0x6];
e1c9c62b 1457 u8 reserved_at_250[0x8];
b775516b
EC		 1458 u8 log_pg_sz[0x8];
1459
1460 u8 bf[0x1];
0dbc6fe0 1461 u8 driver_version[0x1];
e281682b 1462 u8 pad_tx_eth_packet[0x1];
4dca6509
MG		 1463 u8 reserved_at_263[0x3];
1464 u8 mkey_by_name[0x1];
1465 u8 reserved_at_267[0x4];
1466
b775516b 1467 u8 log_bf_reg_size[0x5];
84df61eb 1468
7c4b1ab9
MZ		 1469 u8 reserved_at_270[0x6];
1470 u8 lag_dct[0x2];
1eba383f
MM		 1471 u8 lag_tx_port_affinity[0x1];
1472 u8 reserved_at_279[0x2];
84df61eb
AH		 1473 u8 lag_master[0x1];
1474 u8 num_lag_ports[0x4];
b775516b 1475
e1c9c62b 1476 u8 reserved_at_280[0x10];
b775516b
EC		 1477 u8 max_wqe_sz_sq[0x10];
1478
e1c9c62b 1479 u8 reserved_at_2a0[0x10];
b775516b
EC		 1480 u8 max_wqe_sz_rq[0x10];
1481
a8ffcc74 1482 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1483 u8 max_wqe_sz_sq_dc[0x10];
1484
e1c9c62b 1485 u8 reserved_at_2e0[0x7];
b775516b
EC		 1486 u8 max_qp_mcg[0x19];
1487
8536a6bf
GT		 1488 u8 reserved_at_300[0x10];
1489 u8 flow_counter_bulk_alloc[0x8];
b775516b
EC		 1490 u8 log_max_mcg[0x8];
1491
e1c9c62b 1492 u8 reserved_at_320[0x3];
e281682b 1493 u8 log_max_transport_domain[0x5];
e1c9c62b 1494 u8 reserved_at_328[0x3];
b775516b 1495 u8 log_max_pd[0x5];
e1c9c62b 1496 u8 reserved_at_330[0xb];
b775516b
EC		 1497 u8 log_max_xrcd[0x5];
1498
5c298143 1499 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1500 u8 receive_discard_vport_down[0x1];
1501 u8 transmit_discard_vport_down[0x1];
1502 u8 reserved_at_343[0x5];
a351a1b0 1503 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1504 u8 max_flow_counter_15_0[0x10];
a351a1b0 1505
b775516b 1506
e1c9c62b 1507 u8 reserved_at_360[0x3];
b775516b 1508 u8 log_max_rq[0x5];
e1c9c62b 1509 u8 reserved_at_368[0x3];
b775516b 1510 u8 log_max_sq[0x5];
e1c9c62b 1511 u8 reserved_at_370[0x3];
b775516b 1512 u8 log_max_tir[0x5];
e1c9c62b 1513 u8 reserved_at_378[0x3];
b775516b
EC		 1514 u8 log_max_tis[0x5];
1515
e281682b 1516 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1517 u8 reserved_at_381[0x2];
e281682b 1518 u8 log_max_rmp[0x5];
e1c9c62b 1519 u8 reserved_at_388[0x3];
e281682b 1520 u8 log_max_rqt[0x5];
e1c9c62b 1521 u8 reserved_at_390[0x3];
e281682b 1522 u8 log_max_rqt_size[0x5];
e1c9c62b 1523 u8 reserved_at_398[0x3];
b775516b
EC		 1524 u8 log_max_tis_per_sq[0x5];
1525
619a8f2a
TT		 1526 u8 ext_stride_num_range[0x1];
1527 u8 reserved_at_3a1[0x2];
e281682b 1528 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1529 u8 reserved_at_3a8[0x3];
e281682b 1530 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1531 u8 reserved_at_3b0[0x3];
e281682b 1532 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1533 u8 reserved_at_3b8[0x3];
e281682b
SM		 1534 u8 log_min_stride_sz_sq[0x5];
1535
40817cdb
OG		 1536 u8 hairpin[0x1];
1537 u8 reserved_at_3c1[0x2];
1538 u8 log_max_hairpin_queues[0x5];
1539 u8 reserved_at_3c8[0x3];
1540 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1541 u8 reserved_at_3d0[0x3];
1542 u8 log_max_hairpin_num_packets[0x5];
1543 u8 reserved_at_3d8[0x3];
e281682b
SM		 1544 u8 log_max_wq_sz[0x5];
1545
54f0a411 1546 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1547 u8 disable_local_lb_uc[0x1];
1548 u8 disable_local_lb_mc[0x1];
40817cdb 1549 u8 log_min_hairpin_wq_data_sz[0x5];
349125ba
PP		 1550 u8 reserved_at_3e8[0x2];
1551 u8 vhca_state[0x1];
54f0a411 1552 u8 log_max_vlan_list[0x5];
e1c9c62b 1553 u8 reserved_at_3f0[0x3];
54f0a411 1554 u8 log_max_current_mc_list[0x5];
e1c9c62b 1555 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1556 u8 log_max_current_uc_list[0x5];
1557
38b7ca92
YH		 1558 u8 general_obj_types[0x40];
1559
342ac844
DD		 1560 u8 reserved_at_440[0x20];
1561
61c00cca 1562 u8 reserved_at_460[0x3];
6e3722ba 1563 u8 log_max_uctx[0x5];
2b58f6d9
RS		 1564 u8 reserved_at_468[0x2];
1565 u8 ipsec_offload[0x1];
6e3722ba 1566 u8 log_max_umem[0x5];
342ac844 1567 u8 max_num_eqs[0x10];
54f0a411 1568
61c00cca
TT		 1569 u8 reserved_at_480[0x1];
1570 u8 tls_tx[0x1];
ee5cdf7a 1571 u8 tls_rx[0x1];
e281682b 1572 u8 log_max_l2_table[0x5];
e1c9c62b 1573 u8 reserved_at_488[0x8];
b775516b
EC		 1574 u8 log_uar_page_sz[0x10];
1575
e1c9c62b 1576 u8 reserved_at_4a0[0x20];
048ccca8 1577 u8 device_frequency_mhz[0x20];
b0844444 1578 u8 device_frequency_khz[0x20];
e1c9c62b 1579
a6d51b68
EC		 1580 u8 reserved_at_500[0x20];
1581 u8 num_of_uars_per_page[0x20];
e1c9c62b 1582
e818e255 1583 u8 flex_parser_protocols[0x20];
e1c9c62b 1584
b169e64a
YK		 1585 u8 max_geneve_tlv_options[0x8];
1586 u8 reserved_at_568[0x3];
1587 u8 max_geneve_tlv_option_data_len[0x5];
1588 u8 reserved_at_570[0x10];
e1c9c62b 1589
a12ff35e
EBE		 1590 u8 reserved_at_580[0x33];
1591 u8 log_max_dek[0x5];
1592 u8 reserved_at_5b8[0x4];
ab741b2e 1593 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1594 u8 cqe_128_always[0x1];
1595 u8 cqe_compression_128[0x1];
7d5e1423 1596 u8 cqe_compression[0x1];
b775516b 1597
7d5e1423
SM		 1598 u8 cqe_compression_timeout[0x10];
1599 u8 cqe_compression_max_num[0x10];
b775516b 1600
7486216b
SM		 1601 u8 reserved_at_5e0[0x10];
1602 u8 tag_matching[0x1];
1603 u8 rndv_offload_rc[0x1];
1604 u8 rndv_offload_dc[0x1];
1605 u8 log_tag_matching_list_sz[0x5];
7b13558f 1606 u8 reserved_at_5f8[0x3];
7486216b
SM		 1607 u8 log_max_xrq[0x5];
1608
32f69e4b
DJ		 1609 u8 affiliate_nic_vport_criteria[0x8];
1610 u8 native_port_num[0x8];
1611 u8 num_vhca_ports[0x8];
1612 u8 reserved_at_618[0x6];
1613 u8 sw_owner_id[0x1];
9d43faac
YH		 1614 u8 reserved_at_61f[0x1];
1615
fd4572b3
ED		 1616 u8 max_num_of_monitor_counters[0x10];
1617 u8 num_ppcnt_monitor_counters[0x10];
1618
349125ba 1619 u8 max_num_sf[0x10];
fd4572b3
ED		 1620 u8 num_q_monitor_counters[0x10];
1621
1759d322
PP		 1622 u8 reserved_at_660[0x20];
1623
1624 u8 sf[0x1];
1625 u8 sf_set_partition[0x1];
1626 u8 reserved_at_682[0x1];
1627 u8 log_max_sf[0x5];
1628 u8 reserved_at_688[0x8];
1629 u8 log_min_sf_size[0x8];
1630 u8 max_num_sf_partitions[0x8];
9d43faac
YH		 1631
1632 u8 uctx_cap[0x20];
1633
b169e64a
YK		 1634 u8 reserved_at_6c0[0x4];
1635 u8 flex_parser_id_geneve_tlv_option_0[0x4];
97b5484e
AV		 1636 u8 flex_parser_id_icmp_dw1[0x4];
1637 u8 flex_parser_id_icmp_dw0[0x4];
1638 u8 flex_parser_id_icmpv6_dw1[0x4];
1639 u8 flex_parser_id_icmpv6_dw0[0x4];
1640 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1641 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1642
1643 u8 reserved_at_6e0[0x10];
1759d322
PP		 1644 u8 sf_base_id[0x10];
1645
1dd7382b
MG		 1646 u8 reserved_at_700[0x80];
1647 u8 vhca_tunnel_commands[0x40];
1648 u8 reserved_at_7c0[0x40];
b775516b
EC		 1649};
1650
81848731
SM		 1651enum mlx5_flow_destination_type {
1652 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1653 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1654 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
38730630 1655 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
bd5251db 1656
5f418378 1657 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1658 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
664000b6 1659 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
e281682b 1660};
b775516b 1661
f6f7d6b5
MG		 1662enum mlx5_flow_table_miss_action {
1663 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1664 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1665 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1666};
1667
e281682b
SM		 1668struct mlx5_ifc_dest_format_struct_bits {
1669 u8 destination_type[0x8];
1670 u8 destination_id[0x18];
1b115498 1671
b17f7fc1 1672 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1673 u8 packet_reformat[0x1];
1674 u8 reserved_at_22[0xe];
b17f7fc1 1675 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1676};
1677
9dc0b289 1678struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1679 u8 flow_counter_id[0x20];
9dc0b289
AV		 1680
1681 u8 reserved_at_20[0x20];
1682};
1683
1b115498
EB		 1684struct mlx5_ifc_extended_dest_format_bits {
1685 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1686
1687 u8 packet_reformat_id[0x20];
1688
1689 u8 reserved_at_60[0x20];
1690};
1691
9dc0b289 1692union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
6dfef396 1693 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
9dc0b289 1694 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
9dc0b289
AV		 1695};
1696
e281682b
SM		 1697struct mlx5_ifc_fte_match_param_bits {
1698 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1699
1700 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1701
1702 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1703
71c6e863
AL		 1704 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1705
b169e64a
YK		 1706 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1707
7da3ad6c
MS		 1708 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1709
1710 u8 reserved_at_c00[0x400];
b775516b
EC		 1711};
1712
e281682b
SM		 1713enum {
1714 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1715 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1716 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1717 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1718 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1719};
b775516b 1720
e281682b
SM		 1721struct mlx5_ifc_rx_hash_field_select_bits {
1722 u8 l3_prot_type[0x1];
1723 u8 l4_prot_type[0x1];
1724 u8 selected_fields[0x1e];
1725};
b775516b 1726
e281682b
SM		 1727enum {
1728 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1729 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1730};
1731
e281682b
SM		 1732enum {
1733 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1734 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1735};
1736
1737struct mlx5_ifc_wq_bits {
1738 u8 wq_type[0x4];
1739 u8 wq_signature[0x1];
1740 u8 end_padding_mode[0x2];
1741 u8 cd_slave[0x1];
b4ff3a36 1742 u8 reserved_at_8[0x18];
b775516b 1743
e281682b
SM		 1744 u8 hds_skip_first_sge[0x1];
1745 u8 log2_hds_buf_size[0x3];
b4ff3a36 1746 u8 reserved_at_24[0x7];
e281682b
SM		 1747 u8 page_offset[0x5];
1748 u8 lwm[0x10];
b775516b 1749
b4ff3a36 1750 u8 reserved_at_40[0x8];
e281682b
SM		 1751 u8 pd[0x18];
1752
b4ff3a36 1753 u8 reserved_at_60[0x8];
e281682b
SM		 1754 u8 uar_page[0x18];
1755
1756 u8 dbr_addr[0x40];
1757
1758 u8 hw_counter[0x20];
1759
1760 u8 sw_counter[0x20];
1761
b4ff3a36 1762 u8 reserved_at_100[0xc];
e281682b 1763 u8 log_wq_stride[0x4];
b4ff3a36 1764 u8 reserved_at_110[0x3];
e281682b 1765 u8 log_wq_pg_sz[0x5];
b4ff3a36 1766 u8 reserved_at_118[0x3];
e281682b
SM		 1767 u8 log_wq_sz[0x5];
1768
bd371975
LR		 1769 u8 dbr_umem_valid[0x1];
1770 u8 wq_umem_valid[0x1];
1771 u8 reserved_at_122[0x1];
4d533e0f
OG		 1772 u8 log_hairpin_num_packets[0x5];
1773 u8 reserved_at_128[0x3];
40817cdb 1774 u8 log_hairpin_data_sz[0x5];
40817cdb 1775
619a8f2a
TT		 1776 u8 reserved_at_130[0x4];
1777 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1778 u8 two_byte_shift_en[0x1];
1779 u8 reserved_at_139[0x4];
1780 u8 log_wqe_stride_size[0x3];
1781
1782 u8 reserved_at_140[0x4c0];
b775516b 1783
b6ca09cb 1784 struct mlx5_ifc_cmd_pas_bits pas[];
b775516b
EC		 1785};
1786
e281682b 1787struct mlx5_ifc_rq_num_bits {
b4ff3a36 1788 u8 reserved_at_0[0x8];
e281682b
SM		 1789 u8 rq_num[0x18];
1790};
b775516b 1791
e281682b 1792struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1793 u8 reserved_at_0[0x10];
e281682b 1794 u8 mac_addr_47_32[0x10];
b775516b 1795
e281682b
SM		 1796 u8 mac_addr_31_0[0x20];
1797};
1798
c0046cf7 1799struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1800 u8 reserved_at_0[0x14];
c0046cf7
SM		 1801 u8 vlan[0x0c];
1802
b4ff3a36 1803 u8 reserved_at_20[0x20];
c0046cf7
SM		 1804};
1805
e281682b 1806struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1807 u8 reserved_at_0[0xa0];
e281682b
SM		 1808
1809 u8 min_time_between_cnps[0x20];
1810
b4ff3a36 1811 u8 reserved_at_c0[0x12];
e281682b 1812 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1813 u8 reserved_at_d8[0x4];
1814 u8 cnp_prio_mode[0x1];
e281682b
SM		 1815 u8 cnp_802p_prio[0x3];
1816
b4ff3a36 1817 u8 reserved_at_e0[0x720];
e281682b
SM		 1818};
1819
1820struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1821 u8 reserved_at_0[0x60];
e281682b 1822
b4ff3a36 1823 u8 reserved_at_60[0x4];
e281682b 1824 u8 clamp_tgt_rate[0x1];
b4ff3a36 1825 u8 reserved_at_65[0x3];
e281682b 1826 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1827 u8 reserved_at_69[0x17];
e281682b 1828
b4ff3a36 1829 u8 reserved_at_80[0x20];
e281682b
SM		 1830
1831 u8 rpg_time_reset[0x20];
1832
1833 u8 rpg_byte_reset[0x20];
1834
1835 u8 rpg_threshold[0x20];
1836
1837 u8 rpg_max_rate[0x20];
1838
1839 u8 rpg_ai_rate[0x20];
1840
1841 u8 rpg_hai_rate[0x20];
1842
1843 u8 rpg_gd[0x20];
1844
1845 u8 rpg_min_dec_fac[0x20];
1846
1847 u8 rpg_min_rate[0x20];
1848
b4ff3a36 1849 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1850
1851 u8 rate_to_set_on_first_cnp[0x20];
1852
1853 u8 dce_tcp_g[0x20];
1854
1855 u8 dce_tcp_rtt[0x20];
1856
1857 u8 rate_reduce_monitor_period[0x20];
1858
b4ff3a36 1859 u8 reserved_at_320[0x20];
e281682b
SM		 1860
1861 u8 initial_alpha_value[0x20];
1862
b4ff3a36 1863 u8 reserved_at_360[0x4a0];
e281682b
SM		 1864};
1865
1866struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1867 u8 reserved_at_0[0x80];
e281682b
SM		 1868
1869 u8 rppp_max_rps[0x20];
1870
1871 u8 rpg_time_reset[0x20];
1872
1873 u8 rpg_byte_reset[0x20];
1874
1875 u8 rpg_threshold[0x20];
1876
1877 u8 rpg_max_rate[0x20];
1878
1879 u8 rpg_ai_rate[0x20];
1880
1881 u8 rpg_hai_rate[0x20];
1882
1883 u8 rpg_gd[0x20];
1884
1885 u8 rpg_min_dec_fac[0x20];
1886
1887 u8 rpg_min_rate[0x20];
1888
b4ff3a36 1889 u8 reserved_at_1c0[0x640];
e281682b
SM		 1890};
1891
1892enum {
1893 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1894 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1895 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1896};
1897
1898struct mlx5_ifc_resize_field_select_bits {
1899 u8 resize_field_select[0x20];
1900};
1901
609b8272
AL		 1902struct mlx5_ifc_resource_dump_bits {
1903 u8 more_dump[0x1];
1904 u8 inline_dump[0x1];
1905 u8 reserved_at_2[0xa];
1906 u8 seq_num[0x4];
1907 u8 segment_type[0x10];
1908
1909 u8 reserved_at_20[0x10];
1910 u8 vhca_id[0x10];
1911
1912 u8 index1[0x20];
1913
1914 u8 index2[0x20];
1915
1916 u8 num_of_obj1[0x10];
1917 u8 num_of_obj2[0x10];
1918
1919 u8 reserved_at_a0[0x20];
1920
1921 u8 device_opaque[0x40];
1922
1923 u8 mkey[0x20];
1924
1925 u8 size[0x20];
1926
1927 u8 address[0x40];
1928
1929 u8 inline_data[52][0x20];
1930};
1931
1932struct mlx5_ifc_resource_dump_menu_record_bits {
1933 u8 reserved_at_0[0x4];
1934 u8 num_of_obj2_supports_active[0x1];
1935 u8 num_of_obj2_supports_all[0x1];
1936 u8 must_have_num_of_obj2[0x1];
1937 u8 support_num_of_obj2[0x1];
1938 u8 num_of_obj1_supports_active[0x1];
1939 u8 num_of_obj1_supports_all[0x1];
1940 u8 must_have_num_of_obj1[0x1];
1941 u8 support_num_of_obj1[0x1];
1942 u8 must_have_index2[0x1];
1943 u8 support_index2[0x1];
1944 u8 must_have_index1[0x1];
1945 u8 support_index1[0x1];
1946 u8 segment_type[0x10];
1947
1948 u8 segment_name[4][0x20];
1949
1950 u8 index1_name[4][0x20];
1951
1952 u8 index2_name[4][0x20];
1953};
1954
1955struct mlx5_ifc_resource_dump_segment_header_bits {
1956 u8 length_dw[0x10];
1957 u8 segment_type[0x10];
1958};
1959
1960struct mlx5_ifc_resource_dump_command_segment_bits {
1961 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1962
1963 u8 segment_called[0x10];
1964 u8 vhca_id[0x10];
1965
1966 u8 index1[0x20];
1967
1968 u8 index2[0x20];
1969
1970 u8 num_of_obj1[0x10];
1971 u8 num_of_obj2[0x10];
1972};
1973
1974struct mlx5_ifc_resource_dump_error_segment_bits {
1975 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1976
1977 u8 reserved_at_20[0x10];
1978 u8 syndrome_id[0x10];
1979
1980 u8 reserved_at_40[0x40];
1981
1982 u8 error[8][0x20];
1983};
1984
1985struct mlx5_ifc_resource_dump_info_segment_bits {
1986 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1987
1988 u8 reserved_at_20[0x18];
1989 u8 dump_version[0x8];
1990
1991 u8 hw_version[0x20];
1992
1993 u8 fw_version[0x20];
1994};
1995
1996struct mlx5_ifc_resource_dump_menu_segment_bits {
1997 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1998
1999 u8 reserved_at_20[0x10];
2000 u8 num_of_records[0x10];
2001
b6ca09cb 2002 struct mlx5_ifc_resource_dump_menu_record_bits record[];
609b8272
AL		 2003};
2004
2005struct mlx5_ifc_resource_dump_resource_segment_bits {
2006 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2007
2008 u8 reserved_at_20[0x20];
2009
2010 u8 index1[0x20];
2011
2012 u8 index2[0x20];
2013
b6ca09cb 2014 u8 payload[][0x20];
609b8272
AL		 2015};
2016
2017struct mlx5_ifc_resource_dump_terminate_segment_bits {
2018 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2019};
2020
2021struct mlx5_ifc_menu_resource_dump_response_bits {
2022 struct mlx5_ifc_resource_dump_info_segment_bits info;
2023 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2024 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2025 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2026};
2027
e281682b
SM		 2028enum {
2029 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2030 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2031 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2032 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2033};
2034
2035struct mlx5_ifc_modify_field_select_bits {
2036 u8 modify_field_select[0x20];
2037};
2038
2039struct mlx5_ifc_field_select_r_roce_np_bits {
2040 u8 field_select_r_roce_np[0x20];
2041};
2042
2043struct mlx5_ifc_field_select_r_roce_rp_bits {
2044 u8 field_select_r_roce_rp[0x20];
2045};
2046
2047enum {
2048 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2049 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2050 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2051 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2052 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2053 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2054 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2055 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2056 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2057 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2058};
2059
2060struct mlx5_ifc_field_select_802_1qau_rp_bits {
2061 u8 field_select_8021qaurp[0x20];
2062};
2063
2064struct mlx5_ifc_phys_layer_cntrs_bits {
2065 u8 time_since_last_clear_high[0x20];
2066
2067 u8 time_since_last_clear_low[0x20];
2068
2069 u8 symbol_errors_high[0x20];
2070
2071 u8 symbol_errors_low[0x20];
2072
2073 u8 sync_headers_errors_high[0x20];
2074
2075 u8 sync_headers_errors_low[0x20];
2076
2077 u8 edpl_bip_errors_lane0_high[0x20];
2078
2079 u8 edpl_bip_errors_lane0_low[0x20];
2080
2081 u8 edpl_bip_errors_lane1_high[0x20];
2082
2083 u8 edpl_bip_errors_lane1_low[0x20];
2084
2085 u8 edpl_bip_errors_lane2_high[0x20];
2086
2087 u8 edpl_bip_errors_lane2_low[0x20];
2088
2089 u8 edpl_bip_errors_lane3_high[0x20];
2090
2091 u8 edpl_bip_errors_lane3_low[0x20];
2092
2093 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2094
2095 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2096
2097 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2098
2099 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2100
2101 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2102
2103 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2104
2105 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2106
2107 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2108
2109 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2110
2111 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2112
2113 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2114
2115 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2116
2117 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2118
2119 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2120
2121 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2122
2123 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2124
2125 u8 rs_fec_corrected_blocks_high[0x20];
2126
2127 u8 rs_fec_corrected_blocks_low[0x20];
2128
2129 u8 rs_fec_uncorrectable_blocks_high[0x20];
2130
2131 u8 rs_fec_uncorrectable_blocks_low[0x20];
2132
2133 u8 rs_fec_no_errors_blocks_high[0x20];
2134
2135 u8 rs_fec_no_errors_blocks_low[0x20];
2136
2137 u8 rs_fec_single_error_blocks_high[0x20];
2138
2139 u8 rs_fec_single_error_blocks_low[0x20];
2140
2141 u8 rs_fec_corrected_symbols_total_high[0x20];
2142
2143 u8 rs_fec_corrected_symbols_total_low[0x20];
2144
2145 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2146
2147 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2148
2149 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2150
2151 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2152
2153 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2154
2155 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2156
2157 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2158
2159 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2160
2161 u8 link_down_events[0x20];
2162
2163 u8 successful_recovery_events[0x20];
2164
b4ff3a36 2165 u8 reserved_at_640[0x180];
e281682b
SM		 2166};
2167
d8dc0508
GP		 2168struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2169 u8 time_since_last_clear_high[0x20];
2170
2171 u8 time_since_last_clear_low[0x20];
2172
2173 u8 phy_received_bits_high[0x20];
2174
2175 u8 phy_received_bits_low[0x20];
2176
2177 u8 phy_symbol_errors_high[0x20];
2178
2179 u8 phy_symbol_errors_low[0x20];
2180
2181 u8 phy_corrected_bits_high[0x20];
2182
2183 u8 phy_corrected_bits_low[0x20];
2184
2185 u8 phy_corrected_bits_lane0_high[0x20];
2186
2187 u8 phy_corrected_bits_lane0_low[0x20];
2188
2189 u8 phy_corrected_bits_lane1_high[0x20];
2190
2191 u8 phy_corrected_bits_lane1_low[0x20];
2192
2193 u8 phy_corrected_bits_lane2_high[0x20];
2194
2195 u8 phy_corrected_bits_lane2_low[0x20];
2196
2197 u8 phy_corrected_bits_lane3_high[0x20];
2198
2199 u8 phy_corrected_bits_lane3_low[0x20];
2200
2201 u8 reserved_at_200[0x5c0];
2202};
2203
1c64bf6f
MY		 2204struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2205 u8 symbol_error_counter[0x10];
2206
2207 u8 link_error_recovery_counter[0x8];
2208
2209 u8 link_downed_counter[0x8];
2210
2211 u8 port_rcv_errors[0x10];
2212
2213 u8 port_rcv_remote_physical_errors[0x10];
2214
2215 u8 port_rcv_switch_relay_errors[0x10];
2216
2217 u8 port_xmit_discards[0x10];
2218
2219 u8 port_xmit_constraint_errors[0x8];
2220
2221 u8 port_rcv_constraint_errors[0x8];
2222
2223 u8 reserved_at_70[0x8];
2224
2225 u8 link_overrun_errors[0x8];
2226
2227 u8 reserved_at_80[0x10];
2228
2229 u8 vl_15_dropped[0x10];
2230
133bea04
TW		 2231 u8 reserved_at_a0[0x80];
2232
2233 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 2234};
2235
948d3f90 2236struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
e281682b
SM		 2237 u8 transmit_queue_high[0x20];
2238
2239 u8 transmit_queue_low[0x20];
2240
948d3f90
AL		 2241 u8 no_buffer_discard_uc_high[0x20];
2242
2243 u8 no_buffer_discard_uc_low[0x20];
2244
2245 u8 reserved_at_80[0x740];
2246};
2247
2248struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2249 u8 wred_discard_high[0x20];
2250
2251 u8 wred_discard_low[0x20];
2252
2253 u8 ecn_marked_tc_high[0x20];
2254
2255 u8 ecn_marked_tc_low[0x20];
2256
2257 u8 reserved_at_80[0x740];
e281682b
SM		 2258};
2259
2260struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2261 u8 rx_octets_high[0x20];
2262
2263 u8 rx_octets_low[0x20];
2264
b4ff3a36 2265 u8 reserved_at_40[0xc0];
e281682b
SM		 2266
2267 u8 rx_frames_high[0x20];
2268
2269 u8 rx_frames_low[0x20];
2270
2271 u8 tx_octets_high[0x20];
2272
2273 u8 tx_octets_low[0x20];
2274
b4ff3a36 2275 u8 reserved_at_180[0xc0];
e281682b
SM		 2276
2277 u8 tx_frames_high[0x20];
2278
2279 u8 tx_frames_low[0x20];
2280
2281 u8 rx_pause_high[0x20];
2282
2283 u8 rx_pause_low[0x20];
2284
2285 u8 rx_pause_duration_high[0x20];
2286
2287 u8 rx_pause_duration_low[0x20];
2288
2289 u8 tx_pause_high[0x20];
2290
2291 u8 tx_pause_low[0x20];
2292
2293 u8 tx_pause_duration_high[0x20];
2294
2295 u8 tx_pause_duration_low[0x20];
2296
2297 u8 rx_pause_transition_high[0x20];
2298
2299 u8 rx_pause_transition_low[0x20];
2300
827a8cb2
AL		 2301 u8 rx_discards_high[0x20];
2302
2303 u8 rx_discards_low[0x20];
2fcb12df
IK		 2304
2305 u8 device_stall_minor_watermark_cnt_high[0x20];
2306
2307 u8 device_stall_minor_watermark_cnt_low[0x20];
2308
2309 u8 device_stall_critical_watermark_cnt_high[0x20];
2310
2311 u8 device_stall_critical_watermark_cnt_low[0x20];
2312
2313 u8 reserved_at_480[0x340];
e281682b
SM		 2314};
2315
2316struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2317 u8 port_transmit_wait_high[0x20];
2318
2319 u8 port_transmit_wait_low[0x20];
2320
2dba0797
GP		 2321 u8 reserved_at_40[0x100];
2322
2323 u8 rx_buffer_almost_full_high[0x20];
2324
2325 u8 rx_buffer_almost_full_low[0x20];
2326
2327 u8 rx_buffer_full_high[0x20];
2328
2329 u8 rx_buffer_full_low[0x20];
2330
0af5107c
TB		 2331 u8 rx_icrc_encapsulated_high[0x20];
2332
2333 u8 rx_icrc_encapsulated_low[0x20];
2334
2335 u8 reserved_at_200[0x5c0];
e281682b
SM		 2336};
2337
2338struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2339 u8 dot3stats_alignment_errors_high[0x20];
2340
2341 u8 dot3stats_alignment_errors_low[0x20];
2342
2343 u8 dot3stats_fcs_errors_high[0x20];
2344
2345 u8 dot3stats_fcs_errors_low[0x20];
2346
2347 u8 dot3stats_single_collision_frames_high[0x20];
2348
2349 u8 dot3stats_single_collision_frames_low[0x20];
2350
2351 u8 dot3stats_multiple_collision_frames_high[0x20];
2352
2353 u8 dot3stats_multiple_collision_frames_low[0x20];
2354
2355 u8 dot3stats_sqe_test_errors_high[0x20];
2356
2357 u8 dot3stats_sqe_test_errors_low[0x20];
2358
2359 u8 dot3stats_deferred_transmissions_high[0x20];
2360
2361 u8 dot3stats_deferred_transmissions_low[0x20];
2362
2363 u8 dot3stats_late_collisions_high[0x20];
2364
2365 u8 dot3stats_late_collisions_low[0x20];
2366
2367 u8 dot3stats_excessive_collisions_high[0x20];
2368
2369 u8 dot3stats_excessive_collisions_low[0x20];
2370
2371 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2372
2373 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2374
2375 u8 dot3stats_carrier_sense_errors_high[0x20];
2376
2377 u8 dot3stats_carrier_sense_errors_low[0x20];
2378
2379 u8 dot3stats_frame_too_longs_high[0x20];
2380
2381 u8 dot3stats_frame_too_longs_low[0x20];
2382
2383 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2384
2385 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2386
2387 u8 dot3stats_symbol_errors_high[0x20];
2388
2389 u8 dot3stats_symbol_errors_low[0x20];
2390
2391 u8 dot3control_in_unknown_opcodes_high[0x20];
2392
2393 u8 dot3control_in_unknown_opcodes_low[0x20];
2394
2395 u8 dot3in_pause_frames_high[0x20];
2396
2397 u8 dot3in_pause_frames_low[0x20];
2398
2399 u8 dot3out_pause_frames_high[0x20];
2400
2401 u8 dot3out_pause_frames_low[0x20];
2402
b4ff3a36 2403 u8 reserved_at_400[0x3c0];
e281682b
SM		 2404};
2405
2406struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2407 u8 ether_stats_drop_events_high[0x20];
2408
2409 u8 ether_stats_drop_events_low[0x20];
2410
2411 u8 ether_stats_octets_high[0x20];
2412
2413 u8 ether_stats_octets_low[0x20];
2414
2415 u8 ether_stats_pkts_high[0x20];
2416
2417 u8 ether_stats_pkts_low[0x20];
2418
2419 u8 ether_stats_broadcast_pkts_high[0x20];
2420
2421 u8 ether_stats_broadcast_pkts_low[0x20];
2422
2423 u8 ether_stats_multicast_pkts_high[0x20];
2424
2425 u8 ether_stats_multicast_pkts_low[0x20];
2426
2427 u8 ether_stats_crc_align_errors_high[0x20];
2428
2429 u8 ether_stats_crc_align_errors_low[0x20];
2430
2431 u8 ether_stats_undersize_pkts_high[0x20];
2432
2433 u8 ether_stats_undersize_pkts_low[0x20];
2434
2435 u8 ether_stats_oversize_pkts_high[0x20];
2436
2437 u8 ether_stats_oversize_pkts_low[0x20];
2438
2439 u8 ether_stats_fragments_high[0x20];
2440
2441 u8 ether_stats_fragments_low[0x20];
2442
2443 u8 ether_stats_jabbers_high[0x20];
2444
2445 u8 ether_stats_jabbers_low[0x20];
2446
2447 u8 ether_stats_collisions_high[0x20];
2448
2449 u8 ether_stats_collisions_low[0x20];
2450
2451 u8 ether_stats_pkts64octets_high[0x20];
2452
2453 u8 ether_stats_pkts64octets_low[0x20];
2454
2455 u8 ether_stats_pkts65to127octets_high[0x20];
2456
2457 u8 ether_stats_pkts65to127octets_low[0x20];
2458
2459 u8 ether_stats_pkts128to255octets_high[0x20];
2460
2461 u8 ether_stats_pkts128to255octets_low[0x20];
2462
2463 u8 ether_stats_pkts256to511octets_high[0x20];
2464
2465 u8 ether_stats_pkts256to511octets_low[0x20];
2466
2467 u8 ether_stats_pkts512to1023octets_high[0x20];
2468
2469 u8 ether_stats_pkts512to1023octets_low[0x20];
2470
2471 u8 ether_stats_pkts1024to1518octets_high[0x20];
2472
2473 u8 ether_stats_pkts1024to1518octets_low[0x20];
2474
2475 u8 ether_stats_pkts1519to2047octets_high[0x20];
2476
2477 u8 ether_stats_pkts1519to2047octets_low[0x20];
2478
2479 u8 ether_stats_pkts2048to4095octets_high[0x20];
2480
2481 u8 ether_stats_pkts2048to4095octets_low[0x20];
2482
2483 u8 ether_stats_pkts4096to8191octets_high[0x20];
2484
2485 u8 ether_stats_pkts4096to8191octets_low[0x20];
2486
2487 u8 ether_stats_pkts8192to10239octets_high[0x20];
2488
2489 u8 ether_stats_pkts8192to10239octets_low[0x20];
2490
b4ff3a36 2491 u8 reserved_at_540[0x280];
e281682b
SM		 2492};
2493
2494struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2495 u8 if_in_octets_high[0x20];
2496
2497 u8 if_in_octets_low[0x20];
2498
2499 u8 if_in_ucast_pkts_high[0x20];
2500
2501 u8 if_in_ucast_pkts_low[0x20];
2502
2503 u8 if_in_discards_high[0x20];
2504
2505 u8 if_in_discards_low[0x20];
2506
2507 u8 if_in_errors_high[0x20];
2508
2509 u8 if_in_errors_low[0x20];
2510
2511 u8 if_in_unknown_protos_high[0x20];
2512
2513 u8 if_in_unknown_protos_low[0x20];
2514
2515 u8 if_out_octets_high[0x20];
2516
2517 u8 if_out_octets_low[0x20];
2518
2519 u8 if_out_ucast_pkts_high[0x20];
2520
2521 u8 if_out_ucast_pkts_low[0x20];
2522
2523 u8 if_out_discards_high[0x20];
2524
2525 u8 if_out_discards_low[0x20];
2526
2527 u8 if_out_errors_high[0x20];
2528
2529 u8 if_out_errors_low[0x20];
2530
2531 u8 if_in_multicast_pkts_high[0x20];
2532
2533 u8 if_in_multicast_pkts_low[0x20];
2534
2535 u8 if_in_broadcast_pkts_high[0x20];
2536
2537 u8 if_in_broadcast_pkts_low[0x20];
2538
2539 u8 if_out_multicast_pkts_high[0x20];
2540
2541 u8 if_out_multicast_pkts_low[0x20];
2542
2543 u8 if_out_broadcast_pkts_high[0x20];
2544
2545 u8 if_out_broadcast_pkts_low[0x20];
2546
b4ff3a36 2547 u8 reserved_at_340[0x480];
e281682b
SM		 2548};
2549
2550struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2551 u8 a_frames_transmitted_ok_high[0x20];
2552
2553 u8 a_frames_transmitted_ok_low[0x20];
2554
2555 u8 a_frames_received_ok_high[0x20];
2556
2557 u8 a_frames_received_ok_low[0x20];
2558
2559 u8 a_frame_check_sequence_errors_high[0x20];
2560
2561 u8 a_frame_check_sequence_errors_low[0x20];
2562
2563 u8 a_alignment_errors_high[0x20];
2564
2565 u8 a_alignment_errors_low[0x20];
2566
2567 u8 a_octets_transmitted_ok_high[0x20];
2568
2569 u8 a_octets_transmitted_ok_low[0x20];
2570
2571 u8 a_octets_received_ok_high[0x20];
2572
2573 u8 a_octets_received_ok_low[0x20];
2574
2575 u8 a_multicast_frames_xmitted_ok_high[0x20];
2576
2577 u8 a_multicast_frames_xmitted_ok_low[0x20];
2578
2579 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2580
2581 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2582
2583 u8 a_multicast_frames_received_ok_high[0x20];
2584
2585 u8 a_multicast_frames_received_ok_low[0x20];
2586
2587 u8 a_broadcast_frames_received_ok_high[0x20];
2588
2589 u8 a_broadcast_frames_received_ok_low[0x20];
2590
2591 u8 a_in_range_length_errors_high[0x20];
2592
2593 u8 a_in_range_length_errors_low[0x20];
2594
2595 u8 a_out_of_range_length_field_high[0x20];
2596
2597 u8 a_out_of_range_length_field_low[0x20];
2598
2599 u8 a_frame_too_long_errors_high[0x20];
2600
2601 u8 a_frame_too_long_errors_low[0x20];
2602
2603 u8 a_symbol_error_during_carrier_high[0x20];
2604
2605 u8 a_symbol_error_during_carrier_low[0x20];
2606
2607 u8 a_mac_control_frames_transmitted_high[0x20];
2608
2609 u8 a_mac_control_frames_transmitted_low[0x20];
2610
2611 u8 a_mac_control_frames_received_high[0x20];
2612
2613 u8 a_mac_control_frames_received_low[0x20];
2614
2615 u8 a_unsupported_opcodes_received_high[0x20];
2616
2617 u8 a_unsupported_opcodes_received_low[0x20];
2618
2619 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2620
2621 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2622
2623 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2624
2625 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2626
b4ff3a36 2627 u8 reserved_at_4c0[0x300];
e281682b
SM		 2628};
2629
8ed1a630
GP		 2630struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2631 u8 life_time_counter_high[0x20];
2632
2633 u8 life_time_counter_low[0x20];
2634
2635 u8 rx_errors[0x20];
2636
2637 u8 tx_errors[0x20];
2638
2639 u8 l0_to_recovery_eieos[0x20];
2640
2641 u8 l0_to_recovery_ts[0x20];
2642
2643 u8 l0_to_recovery_framing[0x20];
2644
2645 u8 l0_to_recovery_retrain[0x20];
2646
2647 u8 crc_error_dllp[0x20];
2648
2649 u8 crc_error_tlp[0x20];
2650
efae7f78
EBE		 2651 u8 tx_overflow_buffer_pkt_high[0x20];
2652
2653 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2654
2655 u8 outbound_stalled_reads[0x20];
2656
2657 u8 outbound_stalled_writes[0x20];
2658
2659 u8 outbound_stalled_reads_events[0x20];
2660
2661 u8 outbound_stalled_writes_events[0x20];
2662
2663 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2664};
2665
e281682b
SM		 2666struct mlx5_ifc_cmd_inter_comp_event_bits {
2667 u8 command_completion_vector[0x20];
2668
b4ff3a36 2669 u8 reserved_at_20[0xc0];
e281682b
SM		 2670};
2671
2672struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2673 u8 reserved_at_0[0x18];
e281682b 2674 u8 port_num[0x1];
b4ff3a36 2675 u8 reserved_at_19[0x3];
e281682b
SM		 2676 u8 vl[0x4];
2677
b4ff3a36 2678 u8 reserved_at_20[0xa0];
e281682b
SM		 2679};
2680
2681struct mlx5_ifc_db_bf_congestion_event_bits {
2682 u8 event_subtype[0x8];
b4ff3a36 2683 u8 reserved_at_8[0x8];
e281682b 2684 u8 congestion_level[0x8];
b4ff3a36 2685 u8 reserved_at_18[0x8];
e281682b 2686
b4ff3a36 2687 u8 reserved_at_20[0xa0];
e281682b
SM		 2688};
2689
2690struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2691 u8 reserved_at_0[0x60];
e281682b
SM		 2692
2693 u8 gpio_event_hi[0x20];
2694
2695 u8 gpio_event_lo[0x20];
2696
b4ff3a36 2697 u8 reserved_at_a0[0x40];
e281682b
SM		 2698};
2699
2700struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2701 u8 reserved_at_0[0x40];
e281682b
SM		 2702
2703 u8 port_num[0x4];
b4ff3a36 2704 u8 reserved_at_44[0x1c];
e281682b 2705
b4ff3a36 2706 u8 reserved_at_60[0x80];
e281682b
SM		 2707};
2708
2709struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2710 u8 reserved_at_0[0xe0];
e281682b
SM		 2711};
2712
2713enum {
2714 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2715 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2716};
2717
2718struct mlx5_ifc_cq_error_bits {
b4ff3a36 2719 u8 reserved_at_0[0x8];
e281682b
SM		 2720 u8 cqn[0x18];
2721
b4ff3a36 2722 u8 reserved_at_20[0x20];
e281682b 2723
b4ff3a36 2724 u8 reserved_at_40[0x18];
e281682b
SM		 2725 u8 syndrome[0x8];
2726
b4ff3a36 2727 u8 reserved_at_60[0x80];
e281682b
SM		 2728};
2729
2730struct mlx5_ifc_rdma_page_fault_event_bits {
2731 u8 bytes_committed[0x20];
2732
2733 u8 r_key[0x20];
2734
b4ff3a36 2735 u8 reserved_at_40[0x10];
e281682b
SM		 2736 u8 packet_len[0x10];
2737
2738 u8 rdma_op_len[0x20];
2739
2740 u8 rdma_va[0x40];
2741
b4ff3a36 2742 u8 reserved_at_c0[0x5];
e281682b
SM		 2743 u8 rdma[0x1];
2744 u8 write[0x1];
2745 u8 requestor[0x1];
2746 u8 qp_number[0x18];
2747};
2748
2749struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2750 u8 bytes_committed[0x20];
2751
b4ff3a36 2752 u8 reserved_at_20[0x10];
e281682b
SM		 2753 u8 wqe_index[0x10];
2754
b4ff3a36 2755 u8 reserved_at_40[0x10];
e281682b
SM		 2756 u8 len[0x10];
2757
b4ff3a36 2758 u8 reserved_at_60[0x60];
e281682b 2759
b4ff3a36 2760 u8 reserved_at_c0[0x5];
e281682b
SM		 2761 u8 rdma[0x1];
2762 u8 write_read[0x1];
2763 u8 requestor[0x1];
2764 u8 qpn[0x18];
2765};
2766
2767struct mlx5_ifc_qp_events_bits {
b4ff3a36 2768 u8 reserved_at_0[0xa0];
e281682b
SM		 2769
2770 u8 type[0x8];
b4ff3a36 2771 u8 reserved_at_a8[0x18];
e281682b 2772
b4ff3a36 2773 u8 reserved_at_c0[0x8];
e281682b
SM		 2774 u8 qpn_rqn_sqn[0x18];
2775};
2776
2777struct mlx5_ifc_dct_events_bits {
b4ff3a36 2778 u8 reserved_at_0[0xc0];
e281682b 2779
b4ff3a36 2780 u8 reserved_at_c0[0x8];
e281682b
SM		 2781 u8 dct_number[0x18];
2782};
2783
2784struct mlx5_ifc_comp_event_bits {
b4ff3a36 2785 u8 reserved_at_0[0xc0];
e281682b 2786
b4ff3a36 2787 u8 reserved_at_c0[0x8];
e281682b
SM		 2788 u8 cq_number[0x18];
2789};
2790
2791enum {
2792 MLX5_QPC_STATE_RST = 0x0,
2793 MLX5_QPC_STATE_INIT = 0x1,
2794 MLX5_QPC_STATE_RTR = 0x2,
2795 MLX5_QPC_STATE_RTS = 0x3,
2796 MLX5_QPC_STATE_SQER = 0x4,
2797 MLX5_QPC_STATE_ERR = 0x6,
2798 MLX5_QPC_STATE_SQD = 0x7,
2799 MLX5_QPC_STATE_SUSPENDED = 0x9,
2800};
2801
2802enum {
2803 MLX5_QPC_ST_RC = 0x0,
2804 MLX5_QPC_ST_UC = 0x1,
2805 MLX5_QPC_ST_UD = 0x2,
2806 MLX5_QPC_ST_XRC = 0x3,
2807 MLX5_QPC_ST_DCI = 0x5,
2808 MLX5_QPC_ST_QP0 = 0x7,
2809 MLX5_QPC_ST_QP1 = 0x8,
2810 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2811 MLX5_QPC_ST_REG_UMR = 0xc,
2812};
2813
2814enum {
2815 MLX5_QPC_PM_STATE_ARMED = 0x0,
2816 MLX5_QPC_PM_STATE_REARM = 0x1,
2817 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2818 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2819};
2820
6e44636a
AK		 2821enum {
2822 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2823};
2824
e281682b
SM		 2825enum {
2826 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2827 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2828};
2829
2830enum {
2831 MLX5_QPC_MTU_256_BYTES = 0x1,
2832 MLX5_QPC_MTU_512_BYTES = 0x2,
2833 MLX5_QPC_MTU_1K_BYTES = 0x3,
2834 MLX5_QPC_MTU_2K_BYTES = 0x4,
2835 MLX5_QPC_MTU_4K_BYTES = 0x5,
2836 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2837};
2838
2839enum {
2840 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2841 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2842 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2843 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2844 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2845 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2846 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2847 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2848};
2849
2850enum {
2851 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2852 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2853 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2854};
2855
2856enum {
2857 MLX5_QPC_CS_RES_DISABLE = 0x0,
2858 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2859 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2860};
2861
2862struct mlx5_ifc_qpc_bits {
2863 u8 state[0x4];
84df61eb 2864 u8 lag_tx_port_affinity[0x4];
e281682b 2865 u8 st[0x8];
b4ff3a36 2866 u8 reserved_at_10[0x3];
e281682b 2867 u8 pm_state[0x2];
3fd3c80a
DG		 2868 u8 reserved_at_15[0x1];
2869 u8 req_e2e_credit_mode[0x2];
6e44636a 2870 u8 offload_type[0x4];
e281682b 2871 u8 end_padding_mode[0x2];
b4ff3a36 2872 u8 reserved_at_1e[0x2];
e281682b
SM		 2873
2874 u8 wq_signature[0x1];
2875 u8 block_lb_mc[0x1];
2876 u8 atomic_like_write_en[0x1];
2877 u8 latency_sensitive[0x1];
b4ff3a36 2878 u8 reserved_at_24[0x1];
e281682b 2879 u8 drain_sigerr[0x1];
b4ff3a36 2880 u8 reserved_at_26[0x2];
e281682b
SM		 2881 u8 pd[0x18];
2882
2883 u8 mtu[0x3];
2884 u8 log_msg_max[0x5];
b4ff3a36 2885 u8 reserved_at_48[0x1];
e281682b
SM		 2886 u8 log_rq_size[0x4];
2887 u8 log_rq_stride[0x3];
2888 u8 no_sq[0x1];
2889 u8 log_sq_size[0x4];
b4ff3a36 2890 u8 reserved_at_55[0x6];
e281682b 2891 u8 rlky[0x1];
1015c2e8 2892 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2893
2894 u8 counter_set_id[0x8];
2895 u8 uar_page[0x18];
2896
b4ff3a36 2897 u8 reserved_at_80[0x8];
e281682b
SM		 2898 u8 user_index[0x18];
2899
b4ff3a36 2900 u8 reserved_at_a0[0x3];
e281682b
SM		 2901 u8 log_page_size[0x5];
2902 u8 remote_qpn[0x18];
2903
2904 struct mlx5_ifc_ads_bits primary_address_path;
2905
2906 struct mlx5_ifc_ads_bits secondary_address_path;
2907
2908 u8 log_ack_req_freq[0x4];
b4ff3a36 2909 u8 reserved_at_384[0x4];
e281682b 2910 u8 log_sra_max[0x3];
b4ff3a36 2911 u8 reserved_at_38b[0x2];
e281682b
SM		 2912 u8 retry_count[0x3];
2913 u8 rnr_retry[0x3];
b4ff3a36 2914 u8 reserved_at_393[0x1];
e281682b
SM		 2915 u8 fre[0x1];
2916 u8 cur_rnr_retry[0x3];
2917 u8 cur_retry_count[0x3];
b4ff3a36 2918 u8 reserved_at_39b[0x5];
e281682b 2919
b4ff3a36 2920 u8 reserved_at_3a0[0x20];
e281682b 2921
b4ff3a36 2922 u8 reserved_at_3c0[0x8];
e281682b
SM		 2923 u8 next_send_psn[0x18];
2924
b4ff3a36 2925 u8 reserved_at_3e0[0x8];
e281682b
SM		 2926 u8 cqn_snd[0x18];
2927
09a7d9ec
SM		 2928 u8 reserved_at_400[0x8];
2929 u8 deth_sqpn[0x18];
2930
2931 u8 reserved_at_420[0x20];
e281682b 2932
b4ff3a36 2933 u8 reserved_at_440[0x8];
e281682b
SM		 2934 u8 last_acked_psn[0x18];
2935
b4ff3a36 2936 u8 reserved_at_460[0x8];
e281682b
SM		 2937 u8 ssn[0x18];
2938
b4ff3a36 2939 u8 reserved_at_480[0x8];
e281682b 2940 u8 log_rra_max[0x3];
b4ff3a36 2941 u8 reserved_at_48b[0x1];
e281682b
SM		 2942 u8 atomic_mode[0x4];
2943 u8 rre[0x1];
2944 u8 rwe[0x1];
2945 u8 rae[0x1];
b4ff3a36 2946 u8 reserved_at_493[0x1];
e281682b 2947 u8 page_offset[0x6];
b4ff3a36 2948 u8 reserved_at_49a[0x3];
e281682b
SM		 2949 u8 cd_slave_receive[0x1];
2950 u8 cd_slave_send[0x1];
2951 u8 cd_master[0x1];
2952
b4ff3a36 2953 u8 reserved_at_4a0[0x3];
e281682b
SM		 2954 u8 min_rnr_nak[0x5];
2955 u8 next_rcv_psn[0x18];
2956
b4ff3a36 2957 u8 reserved_at_4c0[0x8];
e281682b
SM		 2958 u8 xrcd[0x18];
2959
b4ff3a36 2960 u8 reserved_at_4e0[0x8];
e281682b
SM		 2961 u8 cqn_rcv[0x18];
2962
2963 u8 dbr_addr[0x40];
2964
2965 u8 q_key[0x20];
2966
b4ff3a36 2967 u8 reserved_at_560[0x5];
e281682b 2968 u8 rq_type[0x3];
7486216b 2969 u8 srqn_rmpn_xrqn[0x18];
e281682b 2970
b4ff3a36 2971 u8 reserved_at_580[0x8];
e281682b
SM		 2972 u8 rmsn[0x18];
2973
2974 u8 hw_sq_wqebb_counter[0x10];
2975 u8 sw_sq_wqebb_counter[0x10];
2976
2977 u8 hw_rq_counter[0x20];
2978
2979 u8 sw_rq_counter[0x20];
2980
b4ff3a36 2981 u8 reserved_at_600[0x20];
e281682b 2982
b4ff3a36 2983 u8 reserved_at_620[0xf];
e281682b
SM		 2984 u8 cgs[0x1];
2985 u8 cs_req[0x8];
2986 u8 cs_res[0x8];
2987
2988 u8 dc_access_key[0x40];
2989
bd371975
LR		 2990 u8 reserved_at_680[0x3];
2991 u8 dbr_umem_valid[0x1];
2992
2993 u8 reserved_at_684[0xbc];
e281682b
SM		 2994};
2995
2996struct mlx5_ifc_roce_addr_layout_bits {
2997 u8 source_l3_address[16][0x8];
2998
b4ff3a36 2999 u8 reserved_at_80[0x3];
e281682b
SM		 3000 u8 vlan_valid[0x1];
3001 u8 vlan_id[0xc];
3002 u8 source_mac_47_32[0x10];
3003
3004 u8 source_mac_31_0[0x20];
3005
b4ff3a36 3006 u8 reserved_at_c0[0x14];
e281682b
SM		 3007 u8 roce_l3_type[0x4];
3008 u8 roce_version[0x8];
3009
b4ff3a36 3010 u8 reserved_at_e0[0x20];
e281682b
SM		 3011};
3012
3013union mlx5_ifc_hca_cap_union_bits {
3014 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3015 struct mlx5_ifc_odp_cap_bits odp_cap;
3016 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3017 struct mlx5_ifc_roce_cap_bits roce_cap;
3018 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3019 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 3020 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 3021 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 3022 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 3023 struct mlx5_ifc_qos_cap_bits qos_cap;
0b9055a1 3024 struct mlx5_ifc_debug_cap_bits debug_cap;
e29341fb 3025 struct mlx5_ifc_fpga_cap_bits fpga_cap;
a12ff35e 3026 struct mlx5_ifc_tls_cap_bits tls_cap;
97b5484e 3027 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
8a06a79b 3028 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
b4ff3a36 3029 u8 reserved_at_0[0x8000];
e281682b
SM		 3030};
3031
3032enum {
3033 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3034 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3035 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 3036 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 3037 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 3038 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 3039 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 3040 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3041 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 3042 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3043 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
78fb6122
HN		 3044 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3045 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
0c06897a
OG		 3046};
3047
65c0f2c1
JL		 3048enum {
3049 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3050 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3051 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3052};
3053
0c06897a
OG		 3054struct mlx5_ifc_vlan_bits {
3055 u8 ethtype[0x10];
3056 u8 prio[0x3];
3057 u8 cfi[0x1];
3058 u8 vid[0xc];
e281682b
SM		 3059};
3060
3061struct mlx5_ifc_flow_context_bits {
0c06897a 3062 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 3063
3064 u8 group_id[0x20];
3065
b4ff3a36 3066 u8 reserved_at_40[0x8];
e281682b
SM		 3067 u8 flow_tag[0x18];
3068
b4ff3a36 3069 u8 reserved_at_60[0x10];
e281682b
SM		 3070 u8 action[0x10];
3071
1b115498 3072 u8 extended_destination[0x1];
65c0f2c1
JL		 3073 u8 reserved_at_81[0x1];
3074 u8 flow_source[0x2];
3075 u8 reserved_at_84[0x4];
e281682b
SM		 3076 u8 destination_list_size[0x18];
3077
9dc0b289
AV		 3078 u8 reserved_at_a0[0x8];
3079 u8 flow_counter_list_size[0x18];
3080
60786f09 3081 u8 packet_reformat_id[0x20];
7adbde20 3082
2a69cb9f
OG		 3083 u8 modify_header_id[0x20];
3084
8da6fe2a
JL		 3085 struct mlx5_ifc_vlan_bits push_vlan_2;
3086
78fb6122
HN		 3087 u8 ipsec_obj_id[0x20];
3088 u8 reserved_at_140[0xc0];
e281682b
SM		 3089
3090 struct mlx5_ifc_fte_match_param_bits match_value;
3091
b4ff3a36 3092 u8 reserved_at_1200[0x600];
e281682b 3093
b6ca09cb 3094 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
e281682b
SM		 3095};
3096
3097enum {
3098 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3099 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3100};
3101
3102struct mlx5_ifc_xrc_srqc_bits {
3103 u8 state[0x4];
3104 u8 log_xrc_srq_size[0x4];
b4ff3a36 3105 u8 reserved_at_8[0x18];
e281682b
SM		 3106
3107 u8 wq_signature[0x1];
3108 u8 cont_srq[0x1];
99b77fef 3109 u8 reserved_at_22[0x1];
e281682b
SM		 3110 u8 rlky[0x1];
3111 u8 basic_cyclic_rcv_wqe[0x1];
3112 u8 log_rq_stride[0x3];
3113 u8 xrcd[0x18];
3114
3115 u8 page_offset[0x6];
99b77fef
YH		 3116 u8 reserved_at_46[0x1];
3117 u8 dbr_umem_valid[0x1];
e281682b
SM		 3118 u8 cqn[0x18];
3119
b4ff3a36 3120 u8 reserved_at_60[0x20];
e281682b
SM		 3121
3122 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 3123 u8 reserved_at_81[0x1];
e281682b
SM		 3124 u8 log_page_size[0x6];
3125 u8 user_index[0x18];
3126
b4ff3a36 3127 u8 reserved_at_a0[0x20];
e281682b 3128
b4ff3a36 3129 u8 reserved_at_c0[0x8];
e281682b
SM		 3130 u8 pd[0x18];
3131
3132 u8 lwm[0x10];
3133 u8 wqe_cnt[0x10];
3134
b4ff3a36 3135 u8 reserved_at_100[0x40];
e281682b
SM		 3136
3137 u8 db_record_addr_h[0x20];
3138
3139 u8 db_record_addr_l[0x1e];
b4ff3a36 3140 u8 reserved_at_17e[0x2];
e281682b 3141
b4ff3a36 3142 u8 reserved_at_180[0x80];
e281682b
SM		 3143};
3144
61c5b5c9
MS		 3145struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3146 u8 counter_error_queues[0x20];
3147
3148 u8 total_error_queues[0x20];
3149
3150 u8 send_queue_priority_update_flow[0x20];
3151
3152 u8 reserved_at_60[0x20];
3153
3154 u8 nic_receive_steering_discard[0x40];
3155
3156 u8 receive_discard_vport_down[0x40];
3157
3158 u8 transmit_discard_vport_down[0x40];
3159
30b10e89
MS		 3160 u8 reserved_at_140[0xa0];
3161
3162 u8 internal_rq_out_of_buffer[0x20];
3163
3164 u8 reserved_at_200[0xe00];
61c5b5c9
MS		 3165};
3166
e281682b
SM		 3167struct mlx5_ifc_traffic_counter_bits {
3168 u8 packets[0x40];
3169
3170 u8 octets[0x40];
3171};
3172
3173struct mlx5_ifc_tisc_bits {
84df61eb 3174 u8 strict_lag_tx_port_affinity[0x1];
a12ff35e 3175 u8 tls_en[0x1];
7761f9ee 3176 u8 reserved_at_2[0x2];
84df61eb
AH		 3177 u8 lag_tx_port_affinity[0x04];
3178
3179 u8 reserved_at_8[0x4];
e281682b 3180 u8 prio[0x4];
b4ff3a36 3181 u8 reserved_at_10[0x10];
e281682b 3182
b4ff3a36 3183 u8 reserved_at_20[0x100];
e281682b 3184
b4ff3a36 3185 u8 reserved_at_120[0x8];
e281682b
SM		 3186 u8 transport_domain[0x18];
3187
500a3d0d
ES		 3188 u8 reserved_at_140[0x8];
3189 u8 underlay_qpn[0x18];
a12ff35e
EBE		 3190
3191 u8 reserved_at_160[0x8];
3192 u8 pd[0x18];
3193
3194 u8 reserved_at_180[0x380];
e281682b
SM		 3195};
3196
3197enum {
3198 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3199 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3200};
3201
3202enum {
3203 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
3204 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
3205};
3206
3207enum {
2be6967c
SM		 3208 MLX5_RX_HASH_FN_NONE = 0x0,
3209 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3210 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 3211};
3212
3213enum {
5d773ff4
MB		 3214 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3215 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 3216};
3217
3218struct mlx5_ifc_tirc_bits {
b4ff3a36 3219 u8 reserved_at_0[0x20];
e281682b
SM		 3220
3221 u8 disp_type[0x4];
ee5cdf7a
TT		 3222 u8 tls_en[0x1];
3223 u8 reserved_at_25[0x1b];
e281682b 3224
b4ff3a36 3225 u8 reserved_at_40[0x40];
e281682b 3226
b4ff3a36 3227 u8 reserved_at_80[0x4];
e281682b
SM		 3228 u8 lro_timeout_period_usecs[0x10];
3229 u8 lro_enable_mask[0x4];
3230 u8 lro_max_ip_payload_size[0x8];
3231
b4ff3a36 3232 u8 reserved_at_a0[0x40];
e281682b 3233
b4ff3a36 3234 u8 reserved_at_e0[0x8];
e281682b
SM		 3235 u8 inline_rqn[0x18];
3236
3237 u8 rx_hash_symmetric[0x1];
b4ff3a36 3238 u8 reserved_at_101[0x1];
e281682b 3239 u8 tunneled_offload_en[0x1];
b4ff3a36 3240 u8 reserved_at_103[0x5];
e281682b
SM		 3241 u8 indirect_table[0x18];
3242
3243 u8 rx_hash_fn[0x4];
b4ff3a36 3244 u8 reserved_at_124[0x2];
e281682b
SM		 3245 u8 self_lb_block[0x2];
3246 u8 transport_domain[0x18];
3247
3248 u8 rx_hash_toeplitz_key[10][0x20];
3249
3250 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3251
3252 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3253
b4ff3a36 3254 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 3255};
3256
3257enum {
3258 MLX5_SRQC_STATE_GOOD = 0x0,
3259 MLX5_SRQC_STATE_ERROR = 0x1,
3260};
3261
3262struct mlx5_ifc_srqc_bits {
3263 u8 state[0x4];
3264 u8 log_srq_size[0x4];
b4ff3a36 3265 u8 reserved_at_8[0x18];
e281682b
SM		 3266
3267 u8 wq_signature[0x1];
3268 u8 cont_srq[0x1];
b4ff3a36 3269 u8 reserved_at_22[0x1];
e281682b 3270 u8 rlky[0x1];
b4ff3a36 3271 u8 reserved_at_24[0x1];
e281682b
SM		 3272 u8 log_rq_stride[0x3];
3273 u8 xrcd[0x18];
3274
3275 u8 page_offset[0x6];
b4ff3a36 3276 u8 reserved_at_46[0x2];
e281682b
SM		 3277 u8 cqn[0x18];
3278
b4ff3a36 3279 u8 reserved_at_60[0x20];
e281682b 3280
b4ff3a36 3281 u8 reserved_at_80[0x2];
e281682b 3282 u8 log_page_size[0x6];
b4ff3a36 3283 u8 reserved_at_88[0x18];
e281682b 3284
b4ff3a36 3285 u8 reserved_at_a0[0x20];
e281682b 3286
b4ff3a36 3287 u8 reserved_at_c0[0x8];
e281682b
SM		 3288 u8 pd[0x18];
3289
3290 u8 lwm[0x10];
3291 u8 wqe_cnt[0x10];
3292
b4ff3a36 3293 u8 reserved_at_100[0x40];
e281682b 3294
01949d01 3295 u8 dbr_addr[0x40];
e281682b 3296
b4ff3a36 3297 u8 reserved_at_180[0x80];
e281682b
SM		 3298};
3299
3300enum {
3301 MLX5_SQC_STATE_RST = 0x0,
3302 MLX5_SQC_STATE_RDY = 0x1,
3303 MLX5_SQC_STATE_ERR = 0x3,
3304};
3305
3306struct mlx5_ifc_sqc_bits {
3307 u8 rlky[0x1];
3308 u8 cd_master[0x1];
3309 u8 fre[0x1];
3310 u8 flush_in_error_en[0x1];
795b609c 3311 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 3312 u8 min_wqe_inline_mode[0x3];
e281682b 3313 u8 state[0x4];
7d5e1423 3314 u8 reg_umr[0x1];
547eede0 3315 u8 allow_swp[0x1];
40817cdb
OG		 3316 u8 hairpin[0x1];
3317 u8 reserved_at_f[0x11];
e281682b 3318
b4ff3a36 3319 u8 reserved_at_20[0x8];
e281682b
SM		 3320 u8 user_index[0x18];
3321
b4ff3a36 3322 u8 reserved_at_40[0x8];
e281682b
SM		 3323 u8 cqn[0x18];
3324
40817cdb
OG		 3325 u8 reserved_at_60[0x8];
3326 u8 hairpin_peer_rq[0x18];
3327
3328 u8 reserved_at_80[0x10];
3329 u8 hairpin_peer_vhca[0x10];
3330
59d2ae1d
EBE		 3331 u8 reserved_at_a0[0x20];
3332
3333 u8 reserved_at_c0[0x8];
3334 u8 ts_cqe_to_dest_cqn[0x18];
e281682b 3335
59d2ae1d 3336 u8 reserved_at_e0[0x10];
7486216b 3337 u8 packet_pacing_rate_limit_index[0x10];
e281682b 3338 u8 tis_lst_sz[0x10];
b4ff3a36 3339 u8 reserved_at_110[0x10];
e281682b 3340
b4ff3a36 3341 u8 reserved_at_120[0x40];
e281682b 3342
b4ff3a36 3343 u8 reserved_at_160[0x8];
e281682b
SM		 3344 u8 tis_num_0[0x18];
3345
3346 struct mlx5_ifc_wq_bits wq;
3347};
3348
813f8540
MHY		 3349enum {
3350 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3351 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3352 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3353 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3354};
3355
6cedde45
EC		 3356enum {
3357 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3358 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3359 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3360 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3361};
3362
813f8540
MHY		 3363struct mlx5_ifc_scheduling_context_bits {
3364 u8 element_type[0x8];
3365 u8 reserved_at_8[0x18];
3366
3367 u8 element_attributes[0x20];
3368
3369 u8 parent_element_id[0x20];
3370
3371 u8 reserved_at_60[0x40];
3372
3373 u8 bw_share[0x20];
3374
3375 u8 max_average_bw[0x20];
3376
3377 u8 reserved_at_e0[0x120];
3378};
3379
e281682b 3380struct mlx5_ifc_rqtc_bits {
8a06a79b 3381 u8 reserved_at_0[0xa0];
e281682b 3382
8a06a79b
EC		 3383 u8 reserved_at_a0[0x5];
3384 u8 list_q_type[0x3];
3385 u8 reserved_at_a8[0x8];
3386 u8 rqt_max_size[0x10];
e281682b 3387
8a06a79b
EC		 3388 u8 rq_vhca_id_format[0x1];
3389 u8 reserved_at_c1[0xf];
3390 u8 rqt_actual_size[0x10];
e281682b 3391
8a06a79b 3392 u8 reserved_at_e0[0x6a0];
e281682b 3393
b6ca09cb 3394 struct mlx5_ifc_rq_num_bits rq_num[];
e281682b
SM		 3395};
3396
3397enum {
3398 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3399 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3400};
3401
3402enum {
3403 MLX5_RQC_STATE_RST = 0x0,
3404 MLX5_RQC_STATE_RDY = 0x1,
3405 MLX5_RQC_STATE_ERR = 0x3,
3406};
3407
3408struct mlx5_ifc_rqc_bits {
3409 u8 rlky[0x1];
03404e8a 3410 u8 delay_drop_en[0x1];
7d5e1423 3411 u8 scatter_fcs[0x1];
e281682b
SM		 3412 u8 vsd[0x1];
3413 u8 mem_rq_type[0x4];
3414 u8 state[0x4];
b4ff3a36 3415 u8 reserved_at_c[0x1];
e281682b 3416 u8 flush_in_error_en[0x1];
40817cdb
OG		 3417 u8 hairpin[0x1];
3418 u8 reserved_at_f[0x11];
e281682b 3419
b4ff3a36 3420 u8 reserved_at_20[0x8];
e281682b
SM		 3421 u8 user_index[0x18];
3422
b4ff3a36 3423 u8 reserved_at_40[0x8];
e281682b
SM		 3424 u8 cqn[0x18];
3425
3426 u8 counter_set_id[0x8];
b4ff3a36 3427 u8 reserved_at_68[0x18];
e281682b 3428
b4ff3a36 3429 u8 reserved_at_80[0x8];
e281682b
SM		 3430 u8 rmpn[0x18];
3431
40817cdb
OG		 3432 u8 reserved_at_a0[0x8];
3433 u8 hairpin_peer_sq[0x18];
3434
3435 u8 reserved_at_c0[0x10];
3436 u8 hairpin_peer_vhca[0x10];
3437
3438 u8 reserved_at_e0[0xa0];
e281682b
SM		 3439
3440 struct mlx5_ifc_wq_bits wq;
3441};
3442
3443enum {
3444 MLX5_RMPC_STATE_RDY = 0x1,
3445 MLX5_RMPC_STATE_ERR = 0x3,
3446};
3447
3448struct mlx5_ifc_rmpc_bits {
b4ff3a36 3449 u8 reserved_at_0[0x8];
e281682b 3450 u8 state[0x4];
b4ff3a36 3451 u8 reserved_at_c[0x14];
e281682b
SM		 3452
3453 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 3454 u8 reserved_at_21[0x1f];
e281682b 3455
b4ff3a36 3456 u8 reserved_at_40[0x140];
e281682b
SM		 3457
3458 struct mlx5_ifc_wq_bits wq;
3459};
3460
e281682b 3461struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 3462 u8 reserved_at_0[0x5];
3463 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 3464 u8 reserved_at_8[0x15];
3465 u8 disable_mc_local_lb[0x1];
3466 u8 disable_uc_local_lb[0x1];
e281682b
SM		 3467 u8 roce_en[0x1];
3468
d82b7318 3469 u8 arm_change_event[0x1];
b4ff3a36 3470 u8 reserved_at_21[0x1a];
d82b7318
SM		 3471 u8 event_on_mtu[0x1];
3472 u8 event_on_promisc_change[0x1];
3473 u8 event_on_vlan_change[0x1];
3474 u8 event_on_mc_address_change[0x1];
3475 u8 event_on_uc_address_change[0x1];
e281682b 3476
32f69e4b
DJ		 3477 u8 reserved_at_40[0xc];
3478
3479 u8 affiliation_criteria[0x4];
3480 u8 affiliated_vhca_id[0x10];
3481
3482 u8 reserved_at_60[0xd0];
d82b7318
SM		 3483
3484 u8 mtu[0x10];
3485
9efa7525
AS		 3486 u8 system_image_guid[0x40];
3487 u8 port_guid[0x40];
3488 u8 node_guid[0x40];
3489
b4ff3a36 3490 u8 reserved_at_200[0x140];
9efa7525 3491 u8 qkey_violation_counter[0x10];
b4ff3a36 3492 u8 reserved_at_350[0x430];
d82b7318
SM		 3493
3494 u8 promisc_uc[0x1];
3495 u8 promisc_mc[0x1];
3496 u8 promisc_all[0x1];
b4ff3a36 3497 u8 reserved_at_783[0x2];
e281682b 3498 u8 allowed_list_type[0x3];
b4ff3a36 3499 u8 reserved_at_788[0xc];
e281682b
SM		 3500 u8 allowed_list_size[0xc];
3501
3502 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3503
b4ff3a36 3504 u8 reserved_at_7e0[0x20];
e281682b 3505
b6ca09cb 3506 u8 current_uc_mac_address[][0x40];
e281682b
SM		 3507};
3508
3509enum {
3510 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3511 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3512 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 3513 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 3514 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 3515 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 3516};
3517
3518struct mlx5_ifc_mkc_bits {
b4ff3a36 3519 u8 reserved_at_0[0x1];
e281682b 3520 u8 free[0x1];
cdbd0d2b
AL		 3521 u8 reserved_at_2[0x1];
3522 u8 access_mode_4_2[0x3];
3523 u8 reserved_at_6[0x7];
3524 u8 relaxed_ordering_write[0x1];
3525 u8 reserved_at_e[0x1];
e281682b
SM		 3526 u8 small_fence_on_rdma_read_response[0x1];
3527 u8 umr_en[0x1];
3528 u8 a[0x1];
3529 u8 rw[0x1];
3530 u8 rr[0x1];
3531 u8 lw[0x1];
3532 u8 lr[0x1];
cdbd0d2b 3533 u8 access_mode_1_0[0x2];
b4ff3a36 3534 u8 reserved_at_18[0x8];
e281682b
SM		 3535
3536 u8 qpn[0x18];
3537 u8 mkey_7_0[0x8];
3538
b4ff3a36 3539 u8 reserved_at_40[0x20];
e281682b
SM		 3540
3541 u8 length64[0x1];
3542 u8 bsf_en[0x1];
3543 u8 sync_umr[0x1];
b4ff3a36 3544 u8 reserved_at_63[0x2];
e281682b 3545 u8 expected_sigerr_count[0x1];
b4ff3a36 3546 u8 reserved_at_66[0x1];
e281682b
SM		 3547 u8 en_rinval[0x1];
3548 u8 pd[0x18];
3549
3550 u8 start_addr[0x40];
3551
3552 u8 len[0x40];
3553
3554 u8 bsf_octword_size[0x20];
3555
b4ff3a36 3556 u8 reserved_at_120[0x80];
e281682b
SM		 3557
3558 u8 translations_octword_size[0x20];
3559
a880a6dd
MG		 3560 u8 reserved_at_1c0[0x19];
3561 u8 relaxed_ordering_read[0x1];
3562 u8 reserved_at_1d9[0x1];
e281682b
SM		 3563 u8 log_page_size[0x5];
3564
b4ff3a36 3565 u8 reserved_at_1e0[0x20];
e281682b
SM		 3566};
3567
3568struct mlx5_ifc_pkey_bits {
b4ff3a36 3569 u8 reserved_at_0[0x10];
e281682b
SM		 3570 u8 pkey[0x10];
3571};
3572
3573struct mlx5_ifc_array128_auto_bits {
3574 u8 array128_auto[16][0x8];
3575};
3576
3577struct mlx5_ifc_hca_vport_context_bits {
3578 u8 field_select[0x20];
3579
b4ff3a36 3580 u8 reserved_at_20[0xe0];
e281682b
SM		 3581
3582 u8 sm_virt_aware[0x1];
3583 u8 has_smi[0x1];
3584 u8 has_raw[0x1];
3585 u8 grh_required[0x1];
b4ff3a36 3586 u8 reserved_at_104[0xc];
707c4602
MD		 3587 u8 port_physical_state[0x4];
3588 u8 vport_state_policy[0x4];
3589 u8 port_state[0x4];
e281682b
SM		 3590 u8 vport_state[0x4];
3591
b4ff3a36 3592 u8 reserved_at_120[0x20];
707c4602
MD		 3593
3594 u8 system_image_guid[0x40];
e281682b
SM		 3595
3596 u8 port_guid[0x40];
3597
3598 u8 node_guid[0x40];
3599
3600 u8 cap_mask1[0x20];
3601
3602 u8 cap_mask1_field_select[0x20];
3603
3604 u8 cap_mask2[0x20];
3605
3606 u8 cap_mask2_field_select[0x20];
3607
b4ff3a36 3608 u8 reserved_at_280[0x80];
e281682b
SM		 3609
3610 u8 lid[0x10];
b4ff3a36 3611 u8 reserved_at_310[0x4];
e281682b
SM		 3612 u8 init_type_reply[0x4];
3613 u8 lmc[0x3];
3614 u8 subnet_timeout[0x5];
3615
3616 u8 sm_lid[0x10];
3617 u8 sm_sl[0x4];
b4ff3a36 3618 u8 reserved_at_334[0xc];
e281682b
SM		 3619
3620 u8 qkey_violation_counter[0x10];
3621 u8 pkey_violation_counter[0x10];
3622
b4ff3a36 3623 u8 reserved_at_360[0xca0];
e281682b
SM		 3624};
3625
d6666753 3626struct mlx5_ifc_esw_vport_context_bits {
65c0f2c1
JL		 3627 u8 fdb_to_vport_reg_c[0x1];
3628 u8 reserved_at_1[0x2];
d6666753
SM		 3629 u8 vport_svlan_strip[0x1];
3630 u8 vport_cvlan_strip[0x1];
3631 u8 vport_svlan_insert[0x1];
3632 u8 vport_cvlan_insert[0x2];
65c0f2c1
JL		 3633 u8 fdb_to_vport_reg_c_id[0x8];
3634 u8 reserved_at_10[0x10];
d6666753 3635
b4ff3a36 3636 u8 reserved_at_20[0x20];
d6666753
SM		 3637
3638 u8 svlan_cfi[0x1];
3639 u8 svlan_pcp[0x3];
3640 u8 svlan_id[0xc];
3641 u8 cvlan_cfi[0x1];
3642 u8 cvlan_pcp[0x3];
3643 u8 cvlan_id[0xc];
3644
97b5484e
AV		 3645 u8 reserved_at_60[0x720];
3646
3647 u8 sw_steering_vport_icm_address_rx[0x40];
3648
3649 u8 sw_steering_vport_icm_address_tx[0x40];
d6666753
SM		 3650};
3651
e281682b
SM		 3652enum {
3653 MLX5_EQC_STATUS_OK = 0x0,
3654 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3655};
3656
3657enum {
3658 MLX5_EQC_ST_ARMED = 0x9,
3659 MLX5_EQC_ST_FIRED = 0xa,
3660};
3661
3662struct mlx5_ifc_eqc_bits {
3663 u8 status[0x4];
b4ff3a36 3664 u8 reserved_at_4[0x9];
e281682b
SM		 3665 u8 ec[0x1];
3666 u8 oi[0x1];
b4ff3a36 3667 u8 reserved_at_f[0x5];
e281682b 3668 u8 st[0x4];
b4ff3a36 3669 u8 reserved_at_18[0x8];
e281682b 3670
b4ff3a36 3671 u8 reserved_at_20[0x20];
e281682b 3672
b4ff3a36 3673 u8 reserved_at_40[0x14];
e281682b 3674 u8 page_offset[0x6];
b4ff3a36 3675 u8 reserved_at_5a[0x6];
e281682b 3676
b4ff3a36 3677 u8 reserved_at_60[0x3];
e281682b
SM		 3678 u8 log_eq_size[0x5];
3679 u8 uar_page[0x18];
3680
b4ff3a36 3681 u8 reserved_at_80[0x20];
e281682b 3682
b4ff3a36 3683 u8 reserved_at_a0[0x18];
e281682b
SM		 3684 u8 intr[0x8];
3685
b4ff3a36 3686 u8 reserved_at_c0[0x3];
e281682b 3687 u8 log_page_size[0x5];
b4ff3a36 3688 u8 reserved_at_c8[0x18];
e281682b 3689
b4ff3a36 3690 u8 reserved_at_e0[0x60];
e281682b 3691
b4ff3a36 3692 u8 reserved_at_140[0x8];
e281682b
SM		 3693 u8 consumer_counter[0x18];
3694
b4ff3a36 3695 u8 reserved_at_160[0x8];
e281682b
SM		 3696 u8 producer_counter[0x18];
3697
b4ff3a36 3698 u8 reserved_at_180[0x80];
e281682b
SM		 3699};
3700
3701enum {
3702 MLX5_DCTC_STATE_ACTIVE = 0x0,
3703 MLX5_DCTC_STATE_DRAINING = 0x1,
3704 MLX5_DCTC_STATE_DRAINED = 0x2,
3705};
3706
3707enum {
3708 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3709 MLX5_DCTC_CS_RES_NA = 0x1,
3710 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3711};
3712
3713enum {
3714 MLX5_DCTC_MTU_256_BYTES = 0x1,
3715 MLX5_DCTC_MTU_512_BYTES = 0x2,
3716 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3717 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3718 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3719};
3720
3721struct mlx5_ifc_dctc_bits {
b4ff3a36 3722 u8 reserved_at_0[0x4];
e281682b 3723 u8 state[0x4];
b4ff3a36 3724 u8 reserved_at_8[0x18];
e281682b 3725
b4ff3a36 3726 u8 reserved_at_20[0x8];
e281682b
SM		 3727 u8 user_index[0x18];
3728
b4ff3a36 3729 u8 reserved_at_40[0x8];
e281682b
SM		 3730 u8 cqn[0x18];
3731
3732 u8 counter_set_id[0x8];
3733 u8 atomic_mode[0x4];
3734 u8 rre[0x1];
3735 u8 rwe[0x1];
3736 u8 rae[0x1];
3737 u8 atomic_like_write_en[0x1];
3738 u8 latency_sensitive[0x1];
3739 u8 rlky[0x1];
3740 u8 free_ar[0x1];
b4ff3a36 3741 u8 reserved_at_73[0xd];
e281682b 3742
b4ff3a36 3743 u8 reserved_at_80[0x8];
e281682b 3744 u8 cs_res[0x8];
b4ff3a36 3745 u8 reserved_at_90[0x3];
e281682b 3746 u8 min_rnr_nak[0x5];
b4ff3a36 3747 u8 reserved_at_98[0x8];
e281682b 3748
b4ff3a36 3749 u8 reserved_at_a0[0x8];
7486216b 3750 u8 srqn_xrqn[0x18];
e281682b 3751
b4ff3a36 3752 u8 reserved_at_c0[0x8];
e281682b
SM		 3753 u8 pd[0x18];
3754
3755 u8 tclass[0x8];
b4ff3a36 3756 u8 reserved_at_e8[0x4];
e281682b
SM		 3757 u8 flow_label[0x14];
3758
3759 u8 dc_access_key[0x40];
3760
b4ff3a36 3761 u8 reserved_at_140[0x5];
e281682b
SM		 3762 u8 mtu[0x3];
3763 u8 port[0x8];
3764 u8 pkey_index[0x10];
3765
b4ff3a36 3766 u8 reserved_at_160[0x8];
e281682b 3767 u8 my_addr_index[0x8];
b4ff3a36 3768 u8 reserved_at_170[0x8];
e281682b
SM		 3769 u8 hop_limit[0x8];
3770
3771 u8 dc_access_key_violation_count[0x20];
3772
b4ff3a36 3773 u8 reserved_at_1a0[0x14];
e281682b
SM		 3774 u8 dei_cfi[0x1];
3775 u8 eth_prio[0x3];
3776 u8 ecn[0x2];
3777 u8 dscp[0x6];
3778
a645a89d
LR		 3779 u8 reserved_at_1c0[0x20];
3780 u8 ece[0x20];
e281682b
SM		 3781};
3782
3783enum {
3784 MLX5_CQC_STATUS_OK = 0x0,
3785 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3786 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3787};
3788
3789enum {
3790 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3791 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3792};
3793
3794enum {
3795 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3796 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3797 MLX5_CQC_ST_FIRED = 0xa,
3798};
3799
7d5e1423
SM		 3800enum {
3801 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3802 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3803 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3804};
3805
e281682b
SM		 3806struct mlx5_ifc_cqc_bits {
3807 u8 status[0x4];
bd371975
LR		 3808 u8 reserved_at_4[0x2];
3809 u8 dbr_umem_valid[0x1];
3810 u8 reserved_at_7[0x1];
e281682b
SM		 3811 u8 cqe_sz[0x3];
3812 u8 cc[0x1];
b4ff3a36 3813 u8 reserved_at_c[0x1];
e281682b
SM		 3814 u8 scqe_break_moderation_en[0x1];
3815 u8 oi[0x1];
7d5e1423
SM		 3816 u8 cq_period_mode[0x2];
3817 u8 cqe_comp_en[0x1];
e281682b
SM		 3818 u8 mini_cqe_res_format[0x2];
3819 u8 st[0x4];
b4ff3a36 3820 u8 reserved_at_18[0x8];
e281682b 3821
b4ff3a36 3822 u8 reserved_at_20[0x20];
e281682b 3823
b4ff3a36 3824 u8 reserved_at_40[0x14];
e281682b 3825 u8 page_offset[0x6];
b4ff3a36 3826 u8 reserved_at_5a[0x6];
e281682b 3827
b4ff3a36 3828 u8 reserved_at_60[0x3];
e281682b
SM		 3829 u8 log_cq_size[0x5];
3830 u8 uar_page[0x18];
3831
b4ff3a36 3832 u8 reserved_at_80[0x4];
e281682b
SM		 3833 u8 cq_period[0xc];
3834 u8 cq_max_count[0x10];
3835
b4ff3a36 3836 u8 reserved_at_a0[0x18];
e281682b
SM		 3837 u8 c_eqn[0x8];
3838
b4ff3a36 3839 u8 reserved_at_c0[0x3];
e281682b 3840 u8 log_page_size[0x5];
b4ff3a36 3841 u8 reserved_at_c8[0x18];
e281682b 3842
b4ff3a36 3843 u8 reserved_at_e0[0x20];
e281682b 3844
b4ff3a36 3845 u8 reserved_at_100[0x8];
e281682b
SM		 3846 u8 last_notified_index[0x18];
3847
b4ff3a36 3848 u8 reserved_at_120[0x8];
e281682b
SM		 3849 u8 last_solicit_index[0x18];
3850
b4ff3a36 3851 u8 reserved_at_140[0x8];
e281682b
SM		 3852 u8 consumer_counter[0x18];
3853
b4ff3a36 3854 u8 reserved_at_160[0x8];
e281682b
SM		 3855 u8 producer_counter[0x18];
3856
b4ff3a36 3857 u8 reserved_at_180[0x40];
e281682b
SM		 3858
3859 u8 dbr_addr[0x40];
3860};
3861
3862union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3863 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3864 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3865 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3866 u8 reserved_at_0[0x800];
e281682b
SM		 3867};
3868
3869struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3870 u8 reserved_at_0[0xc0];
e281682b 3871
b4ff3a36 3872 u8 reserved_at_c0[0x8];
211e6c80
MD		 3873 u8 ieee_vendor_id[0x18];
3874
b4ff3a36 3875 u8 reserved_at_e0[0x10];
e281682b
SM		 3876 u8 vsd_vendor_id[0x10];
3877
3878 u8 vsd[208][0x8];
3879
3880 u8 vsd_contd_psid[16][0x8];
3881};
3882
7486216b
SM		 3883enum {
3884 MLX5_XRQC_STATE_GOOD = 0x0,
3885 MLX5_XRQC_STATE_ERROR = 0x1,
3886};
3887
3888enum {
3889 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3890 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3891};
3892
3893enum {
3894 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3895};
3896
3897struct mlx5_ifc_tag_matching_topology_context_bits {
3898 u8 log_matching_list_sz[0x4];
3899 u8 reserved_at_4[0xc];
3900 u8 append_next_index[0x10];
3901
3902 u8 sw_phase_cnt[0x10];
3903 u8 hw_phase_cnt[0x10];
3904
3905 u8 reserved_at_40[0x40];
3906};
3907
3908struct mlx5_ifc_xrqc_bits {
3909 u8 state[0x4];
3910 u8 rlkey[0x1];
3911 u8 reserved_at_5[0xf];
3912 u8 topology[0x4];
3913 u8 reserved_at_18[0x4];
3914 u8 offload[0x4];
3915
3916 u8 reserved_at_20[0x8];
3917 u8 user_index[0x18];
3918
3919 u8 reserved_at_40[0x8];
3920 u8 cqn[0x18];
3921
3922 u8 reserved_at_60[0xa0];
3923
3924 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3925
6e44636a 3926 u8 reserved_at_180[0x280];
7486216b
SM		 3927
3928 struct mlx5_ifc_wq_bits wq;
3929};
3930
e281682b
SM		 3931union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3932 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3933 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3934 u8 reserved_at_0[0x20];
e281682b
SM		 3935};
3936
3937union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3938 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3939 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3940 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3941 u8 reserved_at_0[0x20];
e281682b
SM		 3942};
3943
3944union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3945 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3946 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3947 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3948 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3949 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3950 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 3951 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3952 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
1c64bf6f 3953 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3954 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3955 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3956 u8 reserved_at_0[0x7c0];
e281682b
SM		 3957};
3958
8ed1a630
GP		 3959union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3960 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3961 u8 reserved_at_0[0x7c0];
3962};
3963
e281682b
SM		 3964union mlx5_ifc_event_auto_bits {
3965 struct mlx5_ifc_comp_event_bits comp_event;
3966 struct mlx5_ifc_dct_events_bits dct_events;
3967 struct mlx5_ifc_qp_events_bits qp_events;
3968 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3969 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3970 struct mlx5_ifc_cq_error_bits cq_error;
3971 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3972 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3973 struct mlx5_ifc_gpio_event_bits gpio_event;
3974 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3975 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3976 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3977 u8 reserved_at_0[0xe0];
e281682b
SM		 3978};
3979
3980struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3981 u8 reserved_at_0[0x100];
e281682b
SM		 3982
3983 u8 assert_existptr[0x20];
3984
3985 u8 assert_callra[0x20];
3986
b4ff3a36 3987 u8 reserved_at_140[0x40];
e281682b
SM		 3988
3989 u8 fw_version[0x20];
3990
3991 u8 hw_id[0x20];
3992
b4ff3a36 3993 u8 reserved_at_1c0[0x20];
e281682b
SM		 3994
3995 u8 irisc_index[0x8];
3996 u8 synd[0x8];
3997 u8 ext_synd[0x10];
3998};
3999
4000struct mlx5_ifc_register_loopback_control_bits {
4001 u8 no_lb[0x1];
b4ff3a36 4002 u8 reserved_at_1[0x7];
e281682b 4003 u8 port[0x8];
b4ff3a36 4004 u8 reserved_at_10[0x10];
e281682b 4005
b4ff3a36 4006 u8 reserved_at_20[0x60];
e281682b
SM		 4007};
4008
813f8540
MHY		 4009struct mlx5_ifc_vport_tc_element_bits {
4010 u8 traffic_class[0x4];
4011 u8 reserved_at_4[0xc];
4012 u8 vport_number[0x10];
4013};
4014
4015struct mlx5_ifc_vport_element_bits {
4016 u8 reserved_at_0[0x10];
4017 u8 vport_number[0x10];
4018};
4019
4020enum {
4021 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4022 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4023 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4024};
4025
4026struct mlx5_ifc_tsar_element_bits {
4027 u8 reserved_at_0[0x8];
4028 u8 tsar_type[0x8];
4029 u8 reserved_at_10[0x10];
4030};
4031
8812c24d
MD		 4032enum {
4033 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4034 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4035};
4036
e281682b
SM		 4037struct mlx5_ifc_teardown_hca_out_bits {
4038 u8 status[0x8];
b4ff3a36 4039 u8 reserved_at_8[0x18];
e281682b
SM		 4040
4041 u8 syndrome[0x20];
4042
8812c24d
MD		 4043 u8 reserved_at_40[0x3f];
4044
fcd29ad1 4045 u8 state[0x1];
e281682b
SM		 4046};
4047
4048enum {
4049 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 4050 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 4051 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 4052};
4053
4054struct mlx5_ifc_teardown_hca_in_bits {
4055 u8 opcode[0x10];
b4ff3a36 4056 u8 reserved_at_10[0x10];
e281682b 4057
b4ff3a36 4058 u8 reserved_at_20[0x10];
e281682b
SM		 4059 u8 op_mod[0x10];
4060
b4ff3a36 4061 u8 reserved_at_40[0x10];
e281682b
SM		 4062 u8 profile[0x10];
4063
b4ff3a36 4064 u8 reserved_at_60[0x20];
e281682b
SM		 4065};
4066
4067struct mlx5_ifc_sqerr2rts_qp_out_bits {
4068 u8 status[0x8];
b4ff3a36 4069 u8 reserved_at_8[0x18];
e281682b
SM		 4070
4071 u8 syndrome[0x20];
4072
b4ff3a36 4073 u8 reserved_at_40[0x40];
e281682b
SM		 4074};
4075
4076struct mlx5_ifc_sqerr2rts_qp_in_bits {
4077 u8 opcode[0x10];
4ac63ec7 4078 u8 uid[0x10];
e281682b 4079
b4ff3a36 4080 u8 reserved_at_20[0x10];
e281682b
SM		 4081 u8 op_mod[0x10];
4082
b4ff3a36 4083 u8 reserved_at_40[0x8];
e281682b
SM		 4084 u8 qpn[0x18];
4085
b4ff3a36 4086 u8 reserved_at_60[0x20];
e281682b
SM		 4087
4088 u8 opt_param_mask[0x20];
4089
b4ff3a36 4090 u8 reserved_at_a0[0x20];
e281682b
SM		 4091
4092 struct mlx5_ifc_qpc_bits qpc;
4093
b4ff3a36 4094 u8 reserved_at_800[0x80];
e281682b
SM		 4095};
4096
4097struct mlx5_ifc_sqd2rts_qp_out_bits {
4098 u8 status[0x8];
b4ff3a36 4099 u8 reserved_at_8[0x18];
e281682b
SM		 4100
4101 u8 syndrome[0x20];
4102
b4ff3a36 4103 u8 reserved_at_40[0x40];
e281682b
SM		 4104};
4105
4106struct mlx5_ifc_sqd2rts_qp_in_bits {
4107 u8 opcode[0x10];
4ac63ec7 4108 u8 uid[0x10];
e281682b 4109
b4ff3a36 4110 u8 reserved_at_20[0x10];
e281682b
SM		 4111 u8 op_mod[0x10];
4112
b4ff3a36 4113 u8 reserved_at_40[0x8];
e281682b
SM		 4114 u8 qpn[0x18];
4115
b4ff3a36 4116 u8 reserved_at_60[0x20];
e281682b
SM		 4117
4118 u8 opt_param_mask[0x20];
4119
b4ff3a36 4120 u8 reserved_at_a0[0x20];
e281682b
SM		 4121
4122 struct mlx5_ifc_qpc_bits qpc;
4123
b4ff3a36 4124 u8 reserved_at_800[0x80];
e281682b
SM		 4125};
4126
4127struct mlx5_ifc_set_roce_address_out_bits {
4128 u8 status[0x8];
b4ff3a36 4129 u8 reserved_at_8[0x18];
e281682b
SM		 4130
4131 u8 syndrome[0x20];
4132
b4ff3a36 4133 u8 reserved_at_40[0x40];
e281682b
SM		 4134};
4135
4136struct mlx5_ifc_set_roce_address_in_bits {
4137 u8 opcode[0x10];
b4ff3a36 4138 u8 reserved_at_10[0x10];
e281682b 4139
b4ff3a36 4140 u8 reserved_at_20[0x10];
e281682b
SM		 4141 u8 op_mod[0x10];
4142
4143 u8 roce_address_index[0x10];
32f69e4b
DJ		 4144 u8 reserved_at_50[0xc];
4145 u8 vhca_port_num[0x4];
e281682b 4146
b4ff3a36 4147 u8 reserved_at_60[0x20];
e281682b
SM		 4148
4149 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4150};
4151
4152struct mlx5_ifc_set_mad_demux_out_bits {
4153 u8 status[0x8];
b4ff3a36 4154 u8 reserved_at_8[0x18];
e281682b
SM		 4155
4156 u8 syndrome[0x20];
4157
b4ff3a36 4158 u8 reserved_at_40[0x40];
e281682b
SM		 4159};
4160
4161enum {
4162 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4163 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4164};
4165
4166struct mlx5_ifc_set_mad_demux_in_bits {
4167 u8 opcode[0x10];
b4ff3a36 4168 u8 reserved_at_10[0x10];
e281682b 4169
b4ff3a36 4170 u8 reserved_at_20[0x10];
e281682b
SM		 4171 u8 op_mod[0x10];
4172
b4ff3a36 4173 u8 reserved_at_40[0x20];
e281682b 4174
b4ff3a36 4175 u8 reserved_at_60[0x6];
e281682b 4176 u8 demux_mode[0x2];
b4ff3a36 4177 u8 reserved_at_68[0x18];
e281682b
SM		 4178};
4179
4180struct mlx5_ifc_set_l2_table_entry_out_bits {
4181 u8 status[0x8];
b4ff3a36 4182 u8 reserved_at_8[0x18];
e281682b
SM		 4183
4184 u8 syndrome[0x20];
4185
b4ff3a36 4186 u8 reserved_at_40[0x40];
e281682b
SM		 4187};
4188
4189struct mlx5_ifc_set_l2_table_entry_in_bits {
4190 u8 opcode[0x10];
b4ff3a36 4191 u8 reserved_at_10[0x10];
e281682b 4192
b4ff3a36 4193 u8 reserved_at_20[0x10];
e281682b
SM		 4194 u8 op_mod[0x10];
4195
b4ff3a36 4196 u8 reserved_at_40[0x60];
e281682b 4197
b4ff3a36 4198 u8 reserved_at_a0[0x8];
e281682b
SM		 4199 u8 table_index[0x18];
4200
b4ff3a36 4201 u8 reserved_at_c0[0x20];
e281682b 4202
b4ff3a36 4203 u8 reserved_at_e0[0x13];
e281682b
SM		 4204 u8 vlan_valid[0x1];
4205 u8 vlan[0xc];
4206
4207 struct mlx5_ifc_mac_address_layout_bits mac_address;
4208
b4ff3a36 4209 u8 reserved_at_140[0xc0];
e281682b
SM		 4210};
4211
4212struct mlx5_ifc_set_issi_out_bits {
4213 u8 status[0x8];
b4ff3a36 4214 u8 reserved_at_8[0x18];
e281682b
SM		 4215
4216 u8 syndrome[0x20];
4217
b4ff3a36 4218 u8 reserved_at_40[0x40];
e281682b
SM		 4219};
4220
4221struct mlx5_ifc_set_issi_in_bits {
4222 u8 opcode[0x10];
b4ff3a36 4223 u8 reserved_at_10[0x10];
e281682b 4224
b4ff3a36 4225 u8 reserved_at_20[0x10];
e281682b
SM		 4226 u8 op_mod[0x10];
4227
b4ff3a36 4228 u8 reserved_at_40[0x10];
e281682b
SM		 4229 u8 current_issi[0x10];
4230
b4ff3a36 4231 u8 reserved_at_60[0x20];
e281682b
SM		 4232};
4233
4234struct mlx5_ifc_set_hca_cap_out_bits {
4235 u8 status[0x8];
b4ff3a36 4236 u8 reserved_at_8[0x18];
e281682b
SM		 4237
4238 u8 syndrome[0x20];
4239
b4ff3a36 4240 u8 reserved_at_40[0x40];
e281682b
SM		 4241};
4242
4243struct mlx5_ifc_set_hca_cap_in_bits {
4244 u8 opcode[0x10];
b4ff3a36 4245 u8 reserved_at_10[0x10];
e281682b 4246
b4ff3a36 4247 u8 reserved_at_20[0x10];
e281682b
SM		 4248 u8 op_mod[0x10];
4249
b4ff3a36 4250 u8 reserved_at_40[0x40];
e281682b
SM		 4251
4252 union mlx5_ifc_hca_cap_union_bits capability;
4253};
4254
26a81453
MG		 4255enum {
4256 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4257 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4258 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2b58f6d9
RS		 4259 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4260 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
26a81453
MG		 4261};
4262
e281682b
SM		 4263struct mlx5_ifc_set_fte_out_bits {
4264 u8 status[0x8];
b4ff3a36 4265 u8 reserved_at_8[0x18];
e281682b
SM		 4266
4267 u8 syndrome[0x20];
4268
b4ff3a36 4269 u8 reserved_at_40[0x40];
e281682b
SM		 4270};
4271
4272struct mlx5_ifc_set_fte_in_bits {
4273 u8 opcode[0x10];
b4ff3a36 4274 u8 reserved_at_10[0x10];
e281682b 4275
b4ff3a36 4276 u8 reserved_at_20[0x10];
e281682b
SM		 4277 u8 op_mod[0x10];
4278
7d5e1423
SM		 4279 u8 other_vport[0x1];
4280 u8 reserved_at_41[0xf];
4281 u8 vport_number[0x10];
4282
4283 u8 reserved_at_60[0x20];
e281682b
SM		 4284
4285 u8 table_type[0x8];
b4ff3a36 4286 u8 reserved_at_88[0x18];
e281682b 4287
b4ff3a36 4288 u8 reserved_at_a0[0x8];
e281682b
SM		 4289 u8 table_id[0x18];
4290
822e114b
PB		 4291 u8 ignore_flow_level[0x1];
4292 u8 reserved_at_c1[0x17];
26a81453
MG		 4293 u8 modify_enable_mask[0x8];
4294
b4ff3a36 4295 u8 reserved_at_e0[0x20];
e281682b
SM		 4296
4297 u8 flow_index[0x20];
4298
b4ff3a36 4299 u8 reserved_at_120[0xe0];
e281682b
SM		 4300
4301 struct mlx5_ifc_flow_context_bits flow_context;
4302};
4303
4304struct mlx5_ifc_rts2rts_qp_out_bits {
4305 u8 status[0x8];
b4ff3a36 4306 u8 reserved_at_8[0x18];
e281682b
SM		 4307
4308 u8 syndrome[0x20];
4309
6b646a7e
LR		 4310 u8 reserved_at_40[0x20];
4311 u8 ece[0x20];
e281682b
SM		 4312};
4313
4314struct mlx5_ifc_rts2rts_qp_in_bits {
4315 u8 opcode[0x10];
4ac63ec7 4316 u8 uid[0x10];
e281682b 4317
b4ff3a36 4318 u8 reserved_at_20[0x10];
e281682b
SM		 4319 u8 op_mod[0x10];
4320
b4ff3a36 4321 u8 reserved_at_40[0x8];
e281682b
SM		 4322 u8 qpn[0x18];
4323
b4ff3a36 4324 u8 reserved_at_60[0x20];
e281682b
SM		 4325
4326 u8 opt_param_mask[0x20];
4327
6b646a7e 4328 u8 ece[0x20];
e281682b
SM		 4329
4330 struct mlx5_ifc_qpc_bits qpc;
4331
b4ff3a36 4332 u8 reserved_at_800[0x80];
e281682b
SM		 4333};
4334
4335struct mlx5_ifc_rtr2rts_qp_out_bits {
4336 u8 status[0x8];
b4ff3a36 4337 u8 reserved_at_8[0x18];
e281682b
SM		 4338
4339 u8 syndrome[0x20];
4340
6b646a7e
LR		 4341 u8 reserved_at_40[0x20];
4342 u8 ece[0x20];
e281682b
SM		 4343};
4344
4345struct mlx5_ifc_rtr2rts_qp_in_bits {
4346 u8 opcode[0x10];
4ac63ec7 4347 u8 uid[0x10];
e281682b 4348
b4ff3a36 4349 u8 reserved_at_20[0x10];
e281682b
SM		 4350 u8 op_mod[0x10];
4351
b4ff3a36 4352 u8 reserved_at_40[0x8];
e281682b
SM		 4353 u8 qpn[0x18];
4354
b4ff3a36 4355 u8 reserved_at_60[0x20];
e281682b
SM		 4356
4357 u8 opt_param_mask[0x20];
4358
6b646a7e 4359 u8 ece[0x20];
e281682b
SM		 4360
4361 struct mlx5_ifc_qpc_bits qpc;
4362
b4ff3a36 4363 u8 reserved_at_800[0x80];
e281682b
SM		 4364};
4365
4366struct mlx5_ifc_rst2init_qp_out_bits {
4367 u8 status[0x8];
b4ff3a36 4368 u8 reserved_at_8[0x18];
e281682b
SM		 4369
4370 u8 syndrome[0x20];
4371
ab183d46
LR		 4372 u8 reserved_at_40[0x20];
4373 u8 ece[0x20];
e281682b
SM		 4374};
4375
4376struct mlx5_ifc_rst2init_qp_in_bits {
4377 u8 opcode[0x10];
4ac63ec7 4378 u8 uid[0x10];
e281682b 4379
b4ff3a36 4380 u8 reserved_at_20[0x10];
e281682b
SM		 4381 u8 op_mod[0x10];
4382
b4ff3a36 4383 u8 reserved_at_40[0x8];
e281682b
SM		 4384 u8 qpn[0x18];
4385
b4ff3a36 4386 u8 reserved_at_60[0x20];
e281682b
SM		 4387
4388 u8 opt_param_mask[0x20];
4389
ab183d46 4390 u8 ece[0x20];
e281682b
SM		 4391
4392 struct mlx5_ifc_qpc_bits qpc;
4393
b4ff3a36 4394 u8 reserved_at_800[0x80];
e281682b
SM		 4395};
4396
7486216b
SM		 4397struct mlx5_ifc_query_xrq_out_bits {
4398 u8 status[0x8];
4399 u8 reserved_at_8[0x18];
4400
4401 u8 syndrome[0x20];
4402
4403 u8 reserved_at_40[0x40];
4404
4405 struct mlx5_ifc_xrqc_bits xrq_context;
4406};
4407
4408struct mlx5_ifc_query_xrq_in_bits {
4409 u8 opcode[0x10];
4410 u8 reserved_at_10[0x10];
4411
4412 u8 reserved_at_20[0x10];
4413 u8 op_mod[0x10];
4414
4415 u8 reserved_at_40[0x8];
4416 u8 xrqn[0x18];
4417
4418 u8 reserved_at_60[0x20];
4419};
4420
e281682b
SM		 4421struct mlx5_ifc_query_xrc_srq_out_bits {
4422 u8 status[0x8];
b4ff3a36 4423 u8 reserved_at_8[0x18];
e281682b
SM		 4424
4425 u8 syndrome[0x20];
4426
b4ff3a36 4427 u8 reserved_at_40[0x40];
e281682b
SM		 4428
4429 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4430
b4ff3a36 4431 u8 reserved_at_280[0x600];
e281682b 4432
b6ca09cb 4433 u8 pas[][0x40];
e281682b
SM		 4434};
4435
4436struct mlx5_ifc_query_xrc_srq_in_bits {
4437 u8 opcode[0x10];
b4ff3a36 4438 u8 reserved_at_10[0x10];
e281682b 4439
b4ff3a36 4440 u8 reserved_at_20[0x10];
e281682b
SM		 4441 u8 op_mod[0x10];
4442
b4ff3a36 4443 u8 reserved_at_40[0x8];
e281682b
SM		 4444 u8 xrc_srqn[0x18];
4445
b4ff3a36 4446 u8 reserved_at_60[0x20];
e281682b
SM		 4447};
4448
4449enum {
4450 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4451 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4452};
4453
4454struct mlx5_ifc_query_vport_state_out_bits {
4455 u8 status[0x8];
b4ff3a36 4456 u8 reserved_at_8[0x18];
e281682b
SM		 4457
4458 u8 syndrome[0x20];
4459
b4ff3a36 4460 u8 reserved_at_40[0x20];
e281682b 4461
b4ff3a36 4462 u8 reserved_at_60[0x18];
e281682b
SM		 4463 u8 admin_state[0x4];
4464 u8 state[0x4];
4465};
4466
4467enum {
cc9c82a8
EBE		 4468 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4469 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
7d0314b1 4470 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
e281682b
SM		 4471};
4472
fd4572b3
ED		 4473struct mlx5_ifc_arm_monitor_counter_in_bits {
4474 u8 opcode[0x10];
4475 u8 uid[0x10];
4476
4477 u8 reserved_at_20[0x10];
4478 u8 op_mod[0x10];
4479
4480 u8 reserved_at_40[0x20];
4481
4482 u8 reserved_at_60[0x20];
4483};
4484
4485struct mlx5_ifc_arm_monitor_counter_out_bits {
4486 u8 status[0x8];
4487 u8 reserved_at_8[0x18];
4488
4489 u8 syndrome[0x20];
4490
4491 u8 reserved_at_40[0x40];
4492};
4493
4494enum {
4495 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4496 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4497};
4498
4499enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 4500 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4501 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4502 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4503 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4504 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4505 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 4506};
4507
4508enum {
4c8b8518 4509 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 4510};
4511
4512struct mlx5_ifc_monitor_counter_output_bits {
4513 u8 reserved_at_0[0x4];
4514 u8 type[0x4];
4515 u8 reserved_at_8[0x8];
4516 u8 counter[0x10];
4517
4518 u8 counter_group_id[0x20];
4519};
4520
4521#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4522#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4523#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4524 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4525
4526struct mlx5_ifc_set_monitor_counter_in_bits {
4527 u8 opcode[0x10];
4528 u8 uid[0x10];
4529
4530 u8 reserved_at_20[0x10];
4531 u8 op_mod[0x10];
4532
4533 u8 reserved_at_40[0x10];
4534 u8 num_of_counters[0x10];
4535
4536 u8 reserved_at_60[0x20];
4537
4538 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4539};
4540
4541struct mlx5_ifc_set_monitor_counter_out_bits {
4542 u8 status[0x8];
4543 u8 reserved_at_8[0x18];
4544
4545 u8 syndrome[0x20];
4546
4547 u8 reserved_at_40[0x40];
4548};
4549
e281682b
SM		 4550struct mlx5_ifc_query_vport_state_in_bits {
4551 u8 opcode[0x10];
b4ff3a36 4552 u8 reserved_at_10[0x10];
e281682b 4553
b4ff3a36 4554 u8 reserved_at_20[0x10];
e281682b
SM		 4555 u8 op_mod[0x10];
4556
4557 u8 other_vport[0x1];
b4ff3a36 4558 u8 reserved_at_41[0xf];
e281682b
SM		 4559 u8 vport_number[0x10];
4560
b4ff3a36 4561 u8 reserved_at_60[0x20];
e281682b
SM		 4562};
4563
61c5b5c9
MS		 4564struct mlx5_ifc_query_vnic_env_out_bits {
4565 u8 status[0x8];
4566 u8 reserved_at_8[0x18];
4567
4568 u8 syndrome[0x20];
4569
4570 u8 reserved_at_40[0x40];
4571
4572 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4573};
4574
4575enum {
4576 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4577};
4578
4579struct mlx5_ifc_query_vnic_env_in_bits {
4580 u8 opcode[0x10];
4581 u8 reserved_at_10[0x10];
4582
4583 u8 reserved_at_20[0x10];
4584 u8 op_mod[0x10];
4585
4586 u8 other_vport[0x1];
4587 u8 reserved_at_41[0xf];
4588 u8 vport_number[0x10];
4589
4590 u8 reserved_at_60[0x20];
4591};
4592
e281682b
SM		 4593struct mlx5_ifc_query_vport_counter_out_bits {
4594 u8 status[0x8];
b4ff3a36 4595 u8 reserved_at_8[0x18];
e281682b
SM		 4596
4597 u8 syndrome[0x20];
4598
b4ff3a36 4599 u8 reserved_at_40[0x40];
e281682b
SM		 4600
4601 struct mlx5_ifc_traffic_counter_bits received_errors;
4602
4603 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4604
4605 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4606
4607 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4608
4609 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4610
4611 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4612
4613 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4614
4615 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4616
4617 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4618
4619 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4620
4621 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4622
4623 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4624
b4ff3a36 4625 u8 reserved_at_680[0xa00];
e281682b
SM		 4626};
4627
4628enum {
4629 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4630};
4631
4632struct mlx5_ifc_query_vport_counter_in_bits {
4633 u8 opcode[0x10];
b4ff3a36 4634 u8 reserved_at_10[0x10];
e281682b 4635
b4ff3a36 4636 u8 reserved_at_20[0x10];
e281682b
SM		 4637 u8 op_mod[0x10];
4638
4639 u8 other_vport[0x1];
b54ba277
MY		 4640 u8 reserved_at_41[0xb];
4641 u8 port_num[0x4];
e281682b
SM		 4642 u8 vport_number[0x10];
4643
b4ff3a36 4644 u8 reserved_at_60[0x60];
e281682b
SM		 4645
4646 u8 clear[0x1];
b4ff3a36 4647 u8 reserved_at_c1[0x1f];
e281682b 4648
b4ff3a36 4649 u8 reserved_at_e0[0x20];
e281682b
SM		 4650};
4651
4652struct mlx5_ifc_query_tis_out_bits {
4653 u8 status[0x8];
b4ff3a36 4654 u8 reserved_at_8[0x18];
e281682b
SM		 4655
4656 u8 syndrome[0x20];
4657
b4ff3a36 4658 u8 reserved_at_40[0x40];
e281682b
SM		 4659
4660 struct mlx5_ifc_tisc_bits tis_context;
4661};
4662
4663struct mlx5_ifc_query_tis_in_bits {
4664 u8 opcode[0x10];
b4ff3a36 4665 u8 reserved_at_10[0x10];
e281682b 4666
b4ff3a36 4667 u8 reserved_at_20[0x10];
e281682b
SM		 4668 u8 op_mod[0x10];
4669
b4ff3a36 4670 u8 reserved_at_40[0x8];
e281682b
SM		 4671 u8 tisn[0x18];
4672
b4ff3a36 4673 u8 reserved_at_60[0x20];
e281682b
SM		 4674};
4675
4676struct mlx5_ifc_query_tir_out_bits {
4677 u8 status[0x8];
b4ff3a36 4678 u8 reserved_at_8[0x18];
e281682b
SM		 4679
4680 u8 syndrome[0x20];
4681
b4ff3a36 4682 u8 reserved_at_40[0xc0];
e281682b
SM		 4683
4684 struct mlx5_ifc_tirc_bits tir_context;
4685};
4686
4687struct mlx5_ifc_query_tir_in_bits {
4688 u8 opcode[0x10];
b4ff3a36 4689 u8 reserved_at_10[0x10];
e281682b 4690
b4ff3a36 4691 u8 reserved_at_20[0x10];
e281682b
SM		 4692 u8 op_mod[0x10];
4693
b4ff3a36 4694 u8 reserved_at_40[0x8];
e281682b
SM		 4695 u8 tirn[0x18];
4696
b4ff3a36 4697 u8 reserved_at_60[0x20];
e281682b
SM		 4698};
4699
4700struct mlx5_ifc_query_srq_out_bits {
4701 u8 status[0x8];
b4ff3a36 4702 u8 reserved_at_8[0x18];
e281682b
SM		 4703
4704 u8 syndrome[0x20];
4705
b4ff3a36 4706 u8 reserved_at_40[0x40];
e281682b
SM		 4707
4708 struct mlx5_ifc_srqc_bits srq_context_entry;
4709
b4ff3a36 4710 u8 reserved_at_280[0x600];
e281682b 4711
b6ca09cb 4712 u8 pas[][0x40];
e281682b
SM		 4713};
4714
4715struct mlx5_ifc_query_srq_in_bits {
4716 u8 opcode[0x10];
b4ff3a36 4717 u8 reserved_at_10[0x10];
e281682b 4718
b4ff3a36 4719 u8 reserved_at_20[0x10];
e281682b
SM		 4720 u8 op_mod[0x10];
4721
b4ff3a36 4722 u8 reserved_at_40[0x8];
e281682b
SM		 4723 u8 srqn[0x18];
4724
b4ff3a36 4725 u8 reserved_at_60[0x20];
e281682b
SM		 4726};
4727
4728struct mlx5_ifc_query_sq_out_bits {
4729 u8 status[0x8];
b4ff3a36 4730 u8 reserved_at_8[0x18];
e281682b
SM		 4731
4732 u8 syndrome[0x20];
4733
b4ff3a36 4734 u8 reserved_at_40[0xc0];
e281682b
SM		 4735
4736 struct mlx5_ifc_sqc_bits sq_context;
4737};
4738
4739struct mlx5_ifc_query_sq_in_bits {
4740 u8 opcode[0x10];
b4ff3a36 4741 u8 reserved_at_10[0x10];
e281682b 4742
b4ff3a36 4743 u8 reserved_at_20[0x10];
e281682b
SM		 4744 u8 op_mod[0x10];
4745
b4ff3a36 4746 u8 reserved_at_40[0x8];
e281682b
SM		 4747 u8 sqn[0x18];
4748
b4ff3a36 4749 u8 reserved_at_60[0x20];
e281682b
SM		 4750};
4751
4752struct mlx5_ifc_query_special_contexts_out_bits {
4753 u8 status[0x8];
b4ff3a36 4754 u8 reserved_at_8[0x18];
e281682b
SM		 4755
4756 u8 syndrome[0x20];
4757
ec22eb53 4758 u8 dump_fill_mkey[0x20];
e281682b
SM		 4759
4760 u8 resd_lkey[0x20];
bcda1aca
AK		 4761
4762 u8 null_mkey[0x20];
4763
4764 u8 reserved_at_a0[0x60];
e281682b
SM		 4765};
4766
4767struct mlx5_ifc_query_special_contexts_in_bits {
4768 u8 opcode[0x10];
b4ff3a36 4769 u8 reserved_at_10[0x10];
e281682b 4770
b4ff3a36 4771 u8 reserved_at_20[0x10];
e281682b
SM		 4772 u8 op_mod[0x10];
4773
b4ff3a36 4774 u8 reserved_at_40[0x40];
e281682b
SM		 4775};
4776
813f8540
MHY		 4777struct mlx5_ifc_query_scheduling_element_out_bits {
4778 u8 opcode[0x10];
4779 u8 reserved_at_10[0x10];
4780
4781 u8 reserved_at_20[0x10];
4782 u8 op_mod[0x10];
4783
4784 u8 reserved_at_40[0xc0];
4785
4786 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4787
4788 u8 reserved_at_300[0x100];
4789};
4790
4791enum {
4792 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4793};
4794
4795struct mlx5_ifc_query_scheduling_element_in_bits {
4796 u8 opcode[0x10];
4797 u8 reserved_at_10[0x10];
4798
4799 u8 reserved_at_20[0x10];
4800 u8 op_mod[0x10];
4801
4802 u8 scheduling_hierarchy[0x8];
4803 u8 reserved_at_48[0x18];
4804
4805 u8 scheduling_element_id[0x20];
4806
4807 u8 reserved_at_80[0x180];
4808};
4809
e281682b
SM		 4810struct mlx5_ifc_query_rqt_out_bits {
4811 u8 status[0x8];
b4ff3a36 4812 u8 reserved_at_8[0x18];
e281682b
SM		 4813
4814 u8 syndrome[0x20];
4815
b4ff3a36 4816 u8 reserved_at_40[0xc0];
e281682b
SM		 4817
4818 struct mlx5_ifc_rqtc_bits rqt_context;
4819};
4820
4821struct mlx5_ifc_query_rqt_in_bits {
4822 u8 opcode[0x10];
b4ff3a36 4823 u8 reserved_at_10[0x10];
e281682b 4824
b4ff3a36 4825 u8 reserved_at_20[0x10];
e281682b
SM		 4826 u8 op_mod[0x10];
4827
b4ff3a36 4828 u8 reserved_at_40[0x8];
e281682b
SM		 4829 u8 rqtn[0x18];
4830
b4ff3a36 4831 u8 reserved_at_60[0x20];
e281682b
SM		 4832};
4833
4834struct mlx5_ifc_query_rq_out_bits {
4835 u8 status[0x8];
b4ff3a36 4836 u8 reserved_at_8[0x18];
e281682b
SM		 4837
4838 u8 syndrome[0x20];
4839
b4ff3a36 4840 u8 reserved_at_40[0xc0];
e281682b
SM		 4841
4842 struct mlx5_ifc_rqc_bits rq_context;
4843};
4844
4845struct mlx5_ifc_query_rq_in_bits {
4846 u8 opcode[0x10];
b4ff3a36 4847 u8 reserved_at_10[0x10];
e281682b 4848
b4ff3a36 4849 u8 reserved_at_20[0x10];
e281682b
SM		 4850 u8 op_mod[0x10];
4851
b4ff3a36 4852 u8 reserved_at_40[0x8];
e281682b
SM		 4853 u8 rqn[0x18];
4854
b4ff3a36 4855 u8 reserved_at_60[0x20];
e281682b
SM		 4856};
4857
4858struct mlx5_ifc_query_roce_address_out_bits {
4859 u8 status[0x8];
b4ff3a36 4860 u8 reserved_at_8[0x18];
e281682b
SM		 4861
4862 u8 syndrome[0x20];
4863
b4ff3a36 4864 u8 reserved_at_40[0x40];
e281682b
SM		 4865
4866 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4867};
4868
4869struct mlx5_ifc_query_roce_address_in_bits {
4870 u8 opcode[0x10];
b4ff3a36 4871 u8 reserved_at_10[0x10];
e281682b 4872
b4ff3a36 4873 u8 reserved_at_20[0x10];
e281682b
SM		 4874 u8 op_mod[0x10];
4875
4876 u8 roce_address_index[0x10];
32f69e4b
DJ		 4877 u8 reserved_at_50[0xc];
4878 u8 vhca_port_num[0x4];
e281682b 4879
b4ff3a36 4880 u8 reserved_at_60[0x20];
e281682b
SM		 4881};
4882
4883struct mlx5_ifc_query_rmp_out_bits {
4884 u8 status[0x8];
b4ff3a36 4885 u8 reserved_at_8[0x18];
e281682b
SM		 4886
4887 u8 syndrome[0x20];
4888
b4ff3a36 4889 u8 reserved_at_40[0xc0];
e281682b
SM		 4890
4891 struct mlx5_ifc_rmpc_bits rmp_context;
4892};
4893
4894struct mlx5_ifc_query_rmp_in_bits {
4895 u8 opcode[0x10];
b4ff3a36 4896 u8 reserved_at_10[0x10];
e281682b 4897
b4ff3a36 4898 u8 reserved_at_20[0x10];
e281682b
SM		 4899 u8 op_mod[0x10];
4900
b4ff3a36 4901 u8 reserved_at_40[0x8];
e281682b
SM		 4902 u8 rmpn[0x18];
4903
b4ff3a36 4904 u8 reserved_at_60[0x20];
e281682b
SM		 4905};
4906
4907struct mlx5_ifc_query_qp_out_bits {
4908 u8 status[0x8];
b4ff3a36 4909 u8 reserved_at_8[0x18];
e281682b
SM		 4910
4911 u8 syndrome[0x20];
4912
6b646a7e
LR		 4913 u8 reserved_at_40[0x20];
4914 u8 ece[0x20];
e281682b
SM		 4915
4916 u8 opt_param_mask[0x20];
4917
b4ff3a36 4918 u8 reserved_at_a0[0x20];
e281682b
SM		 4919
4920 struct mlx5_ifc_qpc_bits qpc;
4921
b4ff3a36 4922 u8 reserved_at_800[0x80];
e281682b 4923
b6ca09cb 4924 u8 pas[][0x40];
e281682b
SM		 4925};
4926
4927struct mlx5_ifc_query_qp_in_bits {
4928 u8 opcode[0x10];
b4ff3a36 4929 u8 reserved_at_10[0x10];
e281682b 4930
b4ff3a36 4931 u8 reserved_at_20[0x10];
e281682b
SM		 4932 u8 op_mod[0x10];
4933
b4ff3a36 4934 u8 reserved_at_40[0x8];
e281682b
SM		 4935 u8 qpn[0x18];
4936
b4ff3a36 4937 u8 reserved_at_60[0x20];
e281682b
SM		 4938};
4939
4940struct mlx5_ifc_query_q_counter_out_bits {
4941 u8 status[0x8];
b4ff3a36 4942 u8 reserved_at_8[0x18];
e281682b
SM		 4943
4944 u8 syndrome[0x20];
4945
b4ff3a36 4946 u8 reserved_at_40[0x40];
e281682b
SM		 4947
4948 u8 rx_write_requests[0x20];
4949
b4ff3a36 4950 u8 reserved_at_a0[0x20];
e281682b
SM		 4951
4952 u8 rx_read_requests[0x20];
4953
b4ff3a36 4954 u8 reserved_at_e0[0x20];
e281682b
SM		 4955
4956 u8 rx_atomic_requests[0x20];
4957
b4ff3a36 4958 u8 reserved_at_120[0x20];
e281682b
SM		 4959
4960 u8 rx_dct_connect[0x20];
4961
b4ff3a36 4962 u8 reserved_at_160[0x20];
e281682b
SM		 4963
4964 u8 out_of_buffer[0x20];
4965
b4ff3a36 4966 u8 reserved_at_1a0[0x20];
e281682b
SM		 4967
4968 u8 out_of_sequence[0x20];
4969
7486216b
SM		 4970 u8 reserved_at_1e0[0x20];
4971
4972 u8 duplicate_request[0x20];
4973
4974 u8 reserved_at_220[0x20];
4975
4976 u8 rnr_nak_retry_err[0x20];
4977
4978 u8 reserved_at_260[0x20];
4979
4980 u8 packet_seq_err[0x20];
4981
4982 u8 reserved_at_2a0[0x20];
4983
4984 u8 implied_nak_seq_err[0x20];
4985
4986 u8 reserved_at_2e0[0x20];
4987
4988 u8 local_ack_timeout_err[0x20];
4989
58dcb60a
PP		 4990 u8 reserved_at_320[0xa0];
4991
4992 u8 resp_local_length_error[0x20];
4993
4994 u8 req_local_length_error[0x20];
4995
4996 u8 resp_local_qp_error[0x20];
4997
4998 u8 local_operation_error[0x20];
4999
5000 u8 resp_local_protection[0x20];
5001
5002 u8 req_local_protection[0x20];
5003
5004 u8 resp_cqe_error[0x20];
5005
5006 u8 req_cqe_error[0x20];
5007
5008 u8 req_mw_binding[0x20];
5009
5010 u8 req_bad_response[0x20];
5011
5012 u8 req_remote_invalid_request[0x20];
5013
5014 u8 resp_remote_invalid_request[0x20];
5015
5016 u8 req_remote_access_errors[0x20];
5017
5018 u8 resp_remote_access_errors[0x20];
5019
5020 u8 req_remote_operation_errors[0x20];
5021
5022 u8 req_transport_retries_exceeded[0x20];
5023
5024 u8 cq_overflow[0x20];
5025
5026 u8 resp_cqe_flush_error[0x20];
5027
5028 u8 req_cqe_flush_error[0x20];
5029
8fd5b75d
LR		 5030 u8 reserved_at_620[0x20];
5031
5032 u8 roce_adp_retrans[0x20];
5033
5034 u8 roce_adp_retrans_to[0x20];
5035
5036 u8 roce_slow_restart[0x20];
5037
5038 u8 roce_slow_restart_cnps[0x20];
5039
5040 u8 roce_slow_restart_trans[0x20];
5041
5042 u8 reserved_at_6e0[0x120];
e281682b
SM		 5043};
5044
5045struct mlx5_ifc_query_q_counter_in_bits {
5046 u8 opcode[0x10];
b4ff3a36 5047 u8 reserved_at_10[0x10];
e281682b 5048
b4ff3a36 5049 u8 reserved_at_20[0x10];
e281682b
SM		 5050 u8 op_mod[0x10];
5051
b4ff3a36 5052 u8 reserved_at_40[0x80];
e281682b
SM		 5053
5054 u8 clear[0x1];
b4ff3a36 5055 u8 reserved_at_c1[0x1f];
e281682b 5056
b4ff3a36 5057 u8 reserved_at_e0[0x18];
e281682b
SM		 5058 u8 counter_set_id[0x8];
5059};
5060
5061struct mlx5_ifc_query_pages_out_bits {
5062 u8 status[0x8];
b4ff3a36 5063 u8 reserved_at_8[0x18];
e281682b
SM		 5064
5065 u8 syndrome[0x20];
5066
591905ba
BW		 5067 u8 embedded_cpu_function[0x1];
5068 u8 reserved_at_41[0xf];
e281682b
SM		 5069 u8 function_id[0x10];
5070
5071 u8 num_pages[0x20];
5072};
5073
5074enum {
5075 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5076 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5077 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5078};
5079
5080struct mlx5_ifc_query_pages_in_bits {
5081 u8 opcode[0x10];
b4ff3a36 5082 u8 reserved_at_10[0x10];
e281682b 5083
b4ff3a36 5084 u8 reserved_at_20[0x10];
e281682b
SM		 5085 u8 op_mod[0x10];
5086
591905ba
BW		 5087 u8 embedded_cpu_function[0x1];
5088 u8 reserved_at_41[0xf];
e281682b
SM		 5089 u8 function_id[0x10];
5090
b4ff3a36 5091 u8 reserved_at_60[0x20];
e281682b
SM		 5092};
5093
5094struct mlx5_ifc_query_nic_vport_context_out_bits {
5095 u8 status[0x8];
b4ff3a36 5096 u8 reserved_at_8[0x18];
e281682b
SM		 5097
5098 u8 syndrome[0x20];
5099
b4ff3a36 5100 u8 reserved_at_40[0x40];
e281682b
SM		 5101
5102 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5103};
5104
5105struct mlx5_ifc_query_nic_vport_context_in_bits {
5106 u8 opcode[0x10];
b4ff3a36 5107 u8 reserved_at_10[0x10];
e281682b 5108
b4ff3a36 5109 u8 reserved_at_20[0x10];
e281682b
SM		 5110 u8 op_mod[0x10];
5111
5112 u8 other_vport[0x1];
b4ff3a36 5113 u8 reserved_at_41[0xf];
e281682b
SM		 5114 u8 vport_number[0x10];
5115
b4ff3a36 5116 u8 reserved_at_60[0x5];
e281682b 5117 u8 allowed_list_type[0x3];
b4ff3a36 5118 u8 reserved_at_68[0x18];
e281682b
SM		 5119};
5120
5121struct mlx5_ifc_query_mkey_out_bits {
5122 u8 status[0x8];
b4ff3a36 5123 u8 reserved_at_8[0x18];
e281682b
SM		 5124
5125 u8 syndrome[0x20];
5126
b4ff3a36 5127 u8 reserved_at_40[0x40];
e281682b
SM		 5128
5129 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5130
b4ff3a36 5131 u8 reserved_at_280[0x600];
e281682b
SM		 5132
5133 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5134
5135 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5136};
5137
5138struct mlx5_ifc_query_mkey_in_bits {
5139 u8 opcode[0x10];
b4ff3a36 5140 u8 reserved_at_10[0x10];
e281682b 5141
b4ff3a36 5142 u8 reserved_at_20[0x10];
e281682b
SM		 5143 u8 op_mod[0x10];
5144
b4ff3a36 5145 u8 reserved_at_40[0x8];
e281682b
SM		 5146 u8 mkey_index[0x18];
5147
5148 u8 pg_access[0x1];
b4ff3a36 5149 u8 reserved_at_61[0x1f];
e281682b
SM		 5150};
5151
5152struct mlx5_ifc_query_mad_demux_out_bits {
5153 u8 status[0x8];
b4ff3a36 5154 u8 reserved_at_8[0x18];
e281682b
SM		 5155
5156 u8 syndrome[0x20];
5157
b4ff3a36 5158 u8 reserved_at_40[0x40];
e281682b
SM		 5159
5160 u8 mad_dumux_parameters_block[0x20];
5161};
5162
5163struct mlx5_ifc_query_mad_demux_in_bits {
5164 u8 opcode[0x10];
b4ff3a36 5165 u8 reserved_at_10[0x10];
e281682b 5166
b4ff3a36 5167 u8 reserved_at_20[0x10];
e281682b
SM		 5168 u8 op_mod[0x10];
5169
b4ff3a36 5170 u8 reserved_at_40[0x40];
e281682b
SM		 5171};
5172
5173struct mlx5_ifc_query_l2_table_entry_out_bits {
5174 u8 status[0x8];
b4ff3a36 5175 u8 reserved_at_8[0x18];
e281682b
SM		 5176
5177 u8 syndrome[0x20];
5178
b4ff3a36 5179 u8 reserved_at_40[0xa0];
e281682b 5180
b4ff3a36 5181 u8 reserved_at_e0[0x13];
e281682b
SM		 5182 u8 vlan_valid[0x1];
5183 u8 vlan[0xc];
5184
5185 struct mlx5_ifc_mac_address_layout_bits mac_address;
5186
b4ff3a36 5187 u8 reserved_at_140[0xc0];
e281682b
SM		 5188};
5189
5190struct mlx5_ifc_query_l2_table_entry_in_bits {
5191 u8 opcode[0x10];
b4ff3a36 5192 u8 reserved_at_10[0x10];
e281682b 5193
b4ff3a36 5194 u8 reserved_at_20[0x10];
e281682b
SM		 5195 u8 op_mod[0x10];
5196
b4ff3a36 5197 u8 reserved_at_40[0x60];
e281682b 5198
b4ff3a36 5199 u8 reserved_at_a0[0x8];
e281682b
SM		 5200 u8 table_index[0x18];
5201
b4ff3a36 5202 u8 reserved_at_c0[0x140];
e281682b
SM		 5203};
5204
5205struct mlx5_ifc_query_issi_out_bits {
5206 u8 status[0x8];
b4ff3a36 5207 u8 reserved_at_8[0x18];
e281682b
SM		 5208
5209 u8 syndrome[0x20];
5210
b4ff3a36 5211 u8 reserved_at_40[0x10];
e281682b
SM		 5212 u8 current_issi[0x10];
5213
b4ff3a36 5214 u8 reserved_at_60[0xa0];
e281682b 5215
b4ff3a36 5216 u8 reserved_at_100[76][0x8];
e281682b
SM		 5217 u8 supported_issi_dw0[0x20];
5218};
5219
5220struct mlx5_ifc_query_issi_in_bits {
5221 u8 opcode[0x10];
b4ff3a36 5222 u8 reserved_at_10[0x10];
e281682b 5223
b4ff3a36 5224 u8 reserved_at_20[0x10];
e281682b
SM		 5225 u8 op_mod[0x10];
5226
b4ff3a36 5227 u8 reserved_at_40[0x40];
e281682b
SM		 5228};
5229
0dbc6fe0
SM		 5230struct mlx5_ifc_set_driver_version_out_bits {
5231 u8 status[0x8];
5232 u8 reserved_0[0x18];
5233
5234 u8 syndrome[0x20];
5235 u8 reserved_1[0x40];
5236};
5237
5238struct mlx5_ifc_set_driver_version_in_bits {
5239 u8 opcode[0x10];
5240 u8 reserved_0[0x10];
5241
5242 u8 reserved_1[0x10];
5243 u8 op_mod[0x10];
5244
5245 u8 reserved_2[0x40];
5246 u8 driver_version[64][0x8];
5247};
5248
e281682b
SM		 5249struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5250 u8 status[0x8];
b4ff3a36 5251 u8 reserved_at_8[0x18];
e281682b
SM		 5252
5253 u8 syndrome[0x20];
5254
b4ff3a36 5255 u8 reserved_at_40[0x40];
e281682b 5256
b6ca09cb 5257 struct mlx5_ifc_pkey_bits pkey[];
e281682b
SM		 5258};
5259
5260struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5261 u8 opcode[0x10];
b4ff3a36 5262 u8 reserved_at_10[0x10];
e281682b 5263
b4ff3a36 5264 u8 reserved_at_20[0x10];
e281682b
SM		 5265 u8 op_mod[0x10];
5266
5267 u8 other_vport[0x1];
b4ff3a36 5268 u8 reserved_at_41[0xb];
707c4602 5269 u8 port_num[0x4];
e281682b
SM		 5270 u8 vport_number[0x10];
5271
b4ff3a36 5272 u8 reserved_at_60[0x10];
e281682b
SM		 5273 u8 pkey_index[0x10];
5274};
5275
eff901d3
EC		 5276enum {
5277 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5278 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5279 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5280};
5281
e281682b
SM		 5282struct mlx5_ifc_query_hca_vport_gid_out_bits {
5283 u8 status[0x8];
b4ff3a36 5284 u8 reserved_at_8[0x18];
e281682b
SM		 5285
5286 u8 syndrome[0x20];
5287
b4ff3a36 5288 u8 reserved_at_40[0x20];
e281682b
SM		 5289
5290 u8 gids_num[0x10];
b4ff3a36 5291 u8 reserved_at_70[0x10];
e281682b 5292
b6ca09cb 5293 struct mlx5_ifc_array128_auto_bits gid[];
e281682b
SM		 5294};
5295
5296struct mlx5_ifc_query_hca_vport_gid_in_bits {
5297 u8 opcode[0x10];
b4ff3a36 5298 u8 reserved_at_10[0x10];
e281682b 5299
b4ff3a36 5300 u8 reserved_at_20[0x10];
e281682b
SM		 5301 u8 op_mod[0x10];
5302
5303 u8 other_vport[0x1];
b4ff3a36 5304 u8 reserved_at_41[0xb];
707c4602 5305 u8 port_num[0x4];
e281682b
SM		 5306 u8 vport_number[0x10];
5307
b4ff3a36 5308 u8 reserved_at_60[0x10];
e281682b
SM		 5309 u8 gid_index[0x10];
5310};
5311
5312struct mlx5_ifc_query_hca_vport_context_out_bits {
5313 u8 status[0x8];
b4ff3a36 5314 u8 reserved_at_8[0x18];
e281682b
SM		 5315
5316 u8 syndrome[0x20];
5317
b4ff3a36 5318 u8 reserved_at_40[0x40];
e281682b
SM		 5319
5320 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5321};
5322
5323struct mlx5_ifc_query_hca_vport_context_in_bits {
5324 u8 opcode[0x10];
b4ff3a36 5325 u8 reserved_at_10[0x10];
e281682b 5326
b4ff3a36 5327 u8 reserved_at_20[0x10];
e281682b
SM		 5328 u8 op_mod[0x10];
5329
5330 u8 other_vport[0x1];
b4ff3a36 5331 u8 reserved_at_41[0xb];
707c4602 5332 u8 port_num[0x4];
e281682b
SM		 5333 u8 vport_number[0x10];
5334
b4ff3a36 5335 u8 reserved_at_60[0x20];
e281682b
SM		 5336};
5337
5338struct mlx5_ifc_query_hca_cap_out_bits {
5339 u8 status[0x8];
b4ff3a36 5340 u8 reserved_at_8[0x18];
e281682b
SM		 5341
5342 u8 syndrome[0x20];
5343
b4ff3a36 5344 u8 reserved_at_40[0x40];
e281682b
SM		 5345
5346 union mlx5_ifc_hca_cap_union_bits capability;
5347};
5348
5349struct mlx5_ifc_query_hca_cap_in_bits {
5350 u8 opcode[0x10];
b4ff3a36 5351 u8 reserved_at_10[0x10];
e281682b 5352
b4ff3a36 5353 u8 reserved_at_20[0x10];
e281682b
SM		 5354 u8 op_mod[0x10];
5355
97b5484e
AV		 5356 u8 other_function[0x1];
5357 u8 reserved_at_41[0xf];
5358 u8 function_id[0x10];
5359
5360 u8 reserved_at_60[0x20];
e281682b
SM		 5361};
5362
97b5484e
AV		 5363struct mlx5_ifc_other_hca_cap_bits {
5364 u8 roce[0x1];
d32d7c52 5365 u8 reserved_at_1[0x27f];
97b5484e
AV		 5366};
5367
5368struct mlx5_ifc_query_other_hca_cap_out_bits {
e281682b 5369 u8 status[0x8];
d32d7c52 5370 u8 reserved_at_8[0x18];
e281682b
SM		 5371
5372 u8 syndrome[0x20];
5373
d32d7c52 5374 u8 reserved_at_40[0x40];
e281682b 5375
97b5484e
AV		 5376 struct mlx5_ifc_other_hca_cap_bits other_capability;
5377};
5378
5379struct mlx5_ifc_query_other_hca_cap_in_bits {
5380 u8 opcode[0x10];
d32d7c52 5381 u8 reserved_at_10[0x10];
97b5484e 5382
d32d7c52 5383 u8 reserved_at_20[0x10];
97b5484e
AV		 5384 u8 op_mod[0x10];
5385
d32d7c52 5386 u8 reserved_at_40[0x10];
97b5484e
AV		 5387 u8 function_id[0x10];
5388
d32d7c52 5389 u8 reserved_at_60[0x20];
97b5484e
AV		 5390};
5391
5392struct mlx5_ifc_modify_other_hca_cap_out_bits {
5393 u8 status[0x8];
d32d7c52 5394 u8 reserved_at_8[0x18];
97b5484e
AV		 5395
5396 u8 syndrome[0x20];
5397
d32d7c52 5398 u8 reserved_at_40[0x40];
97b5484e
AV		 5399};
5400
5401struct mlx5_ifc_modify_other_hca_cap_in_bits {
5402 u8 opcode[0x10];
d32d7c52 5403 u8 reserved_at_10[0x10];
97b5484e 5404
d32d7c52 5405 u8 reserved_at_20[0x10];
97b5484e
AV		 5406 u8 op_mod[0x10];
5407
d32d7c52 5408 u8 reserved_at_40[0x10];
97b5484e
AV		 5409 u8 function_id[0x10];
5410 u8 field_select[0x20];
5411
5412 struct mlx5_ifc_other_hca_cap_bits other_capability;
5413};
5414
5415struct mlx5_ifc_flow_table_context_bits {
5416 u8 reformat_en[0x1];
5417 u8 decap_en[0x1];
5418 u8 sw_owner[0x1];
5419 u8 termination_table[0x1];
5420 u8 table_miss_action[0x4];
e281682b 5421 u8 level[0x8];
97b5484e 5422 u8 reserved_at_10[0x8];
e281682b
SM		 5423 u8 log_size[0x8];
5424
97b5484e
AV		 5425 u8 reserved_at_20[0x8];
5426 u8 table_miss_id[0x18];
5427
5428 u8 reserved_at_40[0x8];
5429 u8 lag_master_next_table_id[0x18];
5430
5431 u8 reserved_at_60[0x60];
5432
5433 u8 sw_owner_icm_root_1[0x40];
5434
5435 u8 sw_owner_icm_root_0[0x40];
5436
5437};
5438
5439struct mlx5_ifc_query_flow_table_out_bits {
5440 u8 status[0x8];
5441 u8 reserved_at_8[0x18];
5442
5443 u8 syndrome[0x20];
5444
5445 u8 reserved_at_40[0x80];
5446
5447 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 5448};
5449
5450struct mlx5_ifc_query_flow_table_in_bits {
5451 u8 opcode[0x10];
b4ff3a36 5452 u8 reserved_at_10[0x10];
e281682b 5453
b4ff3a36 5454 u8 reserved_at_20[0x10];
e281682b
SM		 5455 u8 op_mod[0x10];
5456
b4ff3a36 5457 u8 reserved_at_40[0x40];
e281682b
SM		 5458
5459 u8 table_type[0x8];
b4ff3a36 5460 u8 reserved_at_88[0x18];
e281682b 5461
b4ff3a36 5462 u8 reserved_at_a0[0x8];
e281682b
SM		 5463 u8 table_id[0x18];
5464
b4ff3a36 5465 u8 reserved_at_c0[0x140];
e281682b
SM		 5466};
5467
5468struct mlx5_ifc_query_fte_out_bits {
5469 u8 status[0x8];
b4ff3a36 5470 u8 reserved_at_8[0x18];
e281682b
SM		 5471
5472 u8 syndrome[0x20];
5473
b4ff3a36 5474 u8 reserved_at_40[0x1c0];
e281682b
SM		 5475
5476 struct mlx5_ifc_flow_context_bits flow_context;
5477};
5478
5479struct mlx5_ifc_query_fte_in_bits {
5480 u8 opcode[0x10];
b4ff3a36 5481 u8 reserved_at_10[0x10];
e281682b 5482
b4ff3a36 5483 u8 reserved_at_20[0x10];
e281682b
SM		 5484 u8 op_mod[0x10];
5485
b4ff3a36 5486 u8 reserved_at_40[0x40];
e281682b
SM		 5487
5488 u8 table_type[0x8];
b4ff3a36 5489 u8 reserved_at_88[0x18];
e281682b 5490
b4ff3a36 5491 u8 reserved_at_a0[0x8];
e281682b
SM		 5492 u8 table_id[0x18];
5493
b4ff3a36 5494 u8 reserved_at_c0[0x40];
e281682b
SM		 5495
5496 u8 flow_index[0x20];
5497
b4ff3a36 5498 u8 reserved_at_120[0xe0];
e281682b
SM		 5499};
5500
5501enum {
5502 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5503 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5504 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 5505 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
b169e64a 5506 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
7da3ad6c 5507 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
e281682b
SM		 5508};
5509
5510struct mlx5_ifc_query_flow_group_out_bits {
5511 u8 status[0x8];
b4ff3a36 5512 u8 reserved_at_8[0x18];
e281682b
SM		 5513
5514 u8 syndrome[0x20];
5515
b4ff3a36 5516 u8 reserved_at_40[0xa0];
e281682b
SM		 5517
5518 u8 start_flow_index[0x20];
5519
b4ff3a36 5520 u8 reserved_at_100[0x20];
e281682b
SM		 5521
5522 u8 end_flow_index[0x20];
5523
b4ff3a36 5524 u8 reserved_at_140[0xa0];
e281682b 5525
b4ff3a36 5526 u8 reserved_at_1e0[0x18];
e281682b
SM		 5527 u8 match_criteria_enable[0x8];
5528
5529 struct mlx5_ifc_fte_match_param_bits match_criteria;
5530
b4ff3a36 5531 u8 reserved_at_1200[0xe00];
e281682b
SM		 5532};
5533
5534struct mlx5_ifc_query_flow_group_in_bits {
5535 u8 opcode[0x10];
b4ff3a36 5536 u8 reserved_at_10[0x10];
e281682b 5537
b4ff3a36 5538 u8 reserved_at_20[0x10];
e281682b
SM		 5539 u8 op_mod[0x10];
5540
b4ff3a36 5541 u8 reserved_at_40[0x40];
e281682b
SM		 5542
5543 u8 table_type[0x8];
b4ff3a36 5544 u8 reserved_at_88[0x18];
e281682b 5545
b4ff3a36 5546 u8 reserved_at_a0[0x8];
e281682b
SM		 5547 u8 table_id[0x18];
5548
5549 u8 group_id[0x20];
5550
b4ff3a36 5551 u8 reserved_at_e0[0x120];
e281682b
SM		 5552};
5553
9dc0b289
AV		 5554struct mlx5_ifc_query_flow_counter_out_bits {
5555 u8 status[0x8];
5556 u8 reserved_at_8[0x18];
5557
5558 u8 syndrome[0x20];
5559
5560 u8 reserved_at_40[0x40];
5561
b6ca09cb 5562 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
9dc0b289
AV		 5563};
5564
5565struct mlx5_ifc_query_flow_counter_in_bits {
5566 u8 opcode[0x10];
5567 u8 reserved_at_10[0x10];
5568
5569 u8 reserved_at_20[0x10];
5570 u8 op_mod[0x10];
5571
5572 u8 reserved_at_40[0x80];
5573
5574 u8 clear[0x1];
5575 u8 reserved_at_c1[0xf];
5576 u8 num_of_counters[0x10];
5577
a8ffcc74 5578 u8 flow_counter_id[0x20];
9dc0b289
AV		 5579};
5580
d6666753
SM		 5581struct mlx5_ifc_query_esw_vport_context_out_bits {
5582 u8 status[0x8];
b4ff3a36 5583 u8 reserved_at_8[0x18];
d6666753
SM		 5584
5585 u8 syndrome[0x20];
5586
b4ff3a36 5587 u8 reserved_at_40[0x40];
d6666753
SM		 5588
5589 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5590};
5591
5592struct mlx5_ifc_query_esw_vport_context_in_bits {
5593 u8 opcode[0x10];
b4ff3a36 5594 u8 reserved_at_10[0x10];
d6666753 5595
b4ff3a36 5596 u8 reserved_at_20[0x10];
d6666753
SM		 5597 u8 op_mod[0x10];
5598
5599 u8 other_vport[0x1];
b4ff3a36 5600 u8 reserved_at_41[0xf];
d6666753
SM		 5601 u8 vport_number[0x10];
5602
b4ff3a36 5603 u8 reserved_at_60[0x20];
d6666753
SM		 5604};
5605
5606struct mlx5_ifc_modify_esw_vport_context_out_bits {
5607 u8 status[0x8];
b4ff3a36 5608 u8 reserved_at_8[0x18];
d6666753
SM		 5609
5610 u8 syndrome[0x20];
5611
b4ff3a36 5612 u8 reserved_at_40[0x40];
d6666753
SM		 5613};
5614
5615struct mlx5_ifc_esw_vport_context_fields_select_bits {
65c0f2c1
JL		 5616 u8 reserved_at_0[0x1b];
5617 u8 fdb_to_vport_reg_c_id[0x1];
d6666753
SM		 5618 u8 vport_cvlan_insert[0x1];
5619 u8 vport_svlan_insert[0x1];
5620 u8 vport_cvlan_strip[0x1];
5621 u8 vport_svlan_strip[0x1];
5622};
5623
5624struct mlx5_ifc_modify_esw_vport_context_in_bits {
5625 u8 opcode[0x10];
b4ff3a36 5626 u8 reserved_at_10[0x10];
d6666753 5627
b4ff3a36 5628 u8 reserved_at_20[0x10];
d6666753
SM		 5629 u8 op_mod[0x10];
5630
5631 u8 other_vport[0x1];
b4ff3a36 5632 u8 reserved_at_41[0xf];
d6666753
SM		 5633 u8 vport_number[0x10];
5634
5635 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5636
5637 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5638};
5639
e281682b
SM		 5640struct mlx5_ifc_query_eq_out_bits {
5641 u8 status[0x8];
b4ff3a36 5642 u8 reserved_at_8[0x18];
e281682b
SM		 5643
5644 u8 syndrome[0x20];
5645
b4ff3a36 5646 u8 reserved_at_40[0x40];
e281682b
SM		 5647
5648 struct mlx5_ifc_eqc_bits eq_context_entry;
5649
b4ff3a36 5650 u8 reserved_at_280[0x40];
e281682b
SM		 5651
5652 u8 event_bitmask[0x40];
5653
b4ff3a36 5654 u8 reserved_at_300[0x580];
e281682b 5655
b6ca09cb 5656 u8 pas[][0x40];
e281682b
SM		 5657};
5658
5659struct mlx5_ifc_query_eq_in_bits {
5660 u8 opcode[0x10];
b4ff3a36 5661 u8 reserved_at_10[0x10];
e281682b 5662
b4ff3a36 5663 u8 reserved_at_20[0x10];
e281682b
SM		 5664 u8 op_mod[0x10];
5665
b4ff3a36 5666 u8 reserved_at_40[0x18];
e281682b
SM		 5667 u8 eq_number[0x8];
5668
b4ff3a36 5669 u8 reserved_at_60[0x20];
e281682b
SM		 5670};
5671
60786f09 5672struct mlx5_ifc_packet_reformat_context_in_bits {
7adbde20 5673 u8 reserved_at_0[0x5];
60786f09 5674 u8 reformat_type[0x3];
7adbde20 5675 u8 reserved_at_8[0xe];
60786f09 5676 u8 reformat_data_size[0xa];
7adbde20
HHZ		 5677
5678 u8 reserved_at_20[0x10];
60786f09 5679 u8 reformat_data[2][0x8];
7adbde20 5680
b6ca09cb 5681 u8 more_reformat_data[][0x8];
7adbde20
HHZ		 5682};
5683
60786f09 5684struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 5685 u8 status[0x8];
5686 u8 reserved_at_8[0x18];
5687
5688 u8 syndrome[0x20];
5689
5690 u8 reserved_at_40[0xa0];
5691
b6ca09cb 5692 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7adbde20
HHZ		 5693};
5694
60786f09 5695struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 5696 u8 opcode[0x10];
5697 u8 reserved_at_10[0x10];
5698
5699 u8 reserved_at_20[0x10];
5700 u8 op_mod[0x10];
5701
60786f09 5702 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5703
5704 u8 reserved_at_60[0xa0];
5705};
5706
60786f09 5707struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5708 u8 status[0x8];
5709 u8 reserved_at_8[0x18];
5710
5711 u8 syndrome[0x20];
5712
60786f09 5713 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5714
5715 u8 reserved_at_60[0x20];
5716};
5717
97b5484e 5718enum mlx5_reformat_ctx_type {
60786f09
MB		 5719 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5720 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 5721 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5722 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5723 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
e0e7a386
MB		 5724};
5725
60786f09 5726struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5727 u8 opcode[0x10];
5728 u8 reserved_at_10[0x10];
5729
5730 u8 reserved_at_20[0x10];
5731 u8 op_mod[0x10];
5732
5733 u8 reserved_at_40[0xa0];
5734
60786f09 5735 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 5736};
5737
60786f09 5738struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 5739 u8 status[0x8];
5740 u8 reserved_at_8[0x18];
5741
5742 u8 syndrome[0x20];
5743
5744 u8 reserved_at_40[0x40];
5745};
5746
60786f09 5747struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 5748 u8 opcode[0x10];
5749 u8 reserved_at_10[0x10];
5750
5751 u8 reserved_20[0x10];
5752 u8 op_mod[0x10];
5753
60786f09 5754 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 5755
5756 u8 reserved_60[0x20];
5757};
5758
2a69cb9f
OG		 5759struct mlx5_ifc_set_action_in_bits {
5760 u8 action_type[0x4];
5761 u8 field[0xc];
5762 u8 reserved_at_10[0x3];
5763 u8 offset[0x5];
5764 u8 reserved_at_18[0x3];
5765 u8 length[0x5];
5766
5767 u8 data[0x20];
5768};
5769
5770struct mlx5_ifc_add_action_in_bits {
5771 u8 action_type[0x4];
5772 u8 field[0xc];
5773 u8 reserved_at_10[0x10];
5774
5775 u8 data[0x20];
5776};
5777
31d8bde1
HI		 5778struct mlx5_ifc_copy_action_in_bits {
5779 u8 action_type[0x4];
5780 u8 src_field[0xc];
5781 u8 reserved_at_10[0x3];
5782 u8 src_offset[0x5];
5783 u8 reserved_at_18[0x3];
5784 u8 length[0x5];
5785
5786 u8 reserved_at_20[0x4];
5787 u8 dst_field[0xc];
5788 u8 reserved_at_30[0x3];
5789 u8 dst_offset[0x5];
5790 u8 reserved_at_38[0x8];
5791};
5792
d65dbedf
HN		 5793union mlx5_ifc_set_add_copy_action_in_auto_bits {
5794 struct mlx5_ifc_set_action_in_bits set_action_in;
5795 struct mlx5_ifc_add_action_in_bits add_action_in;
822e114b 5796 struct mlx5_ifc_copy_action_in_bits copy_action_in;
2a69cb9f
OG		 5797 u8 reserved_at_0[0x40];
5798};
5799
5800enum {
5801 MLX5_ACTION_TYPE_SET = 0x1,
5802 MLX5_ACTION_TYPE_ADD = 0x2,
31d8bde1 5803 MLX5_ACTION_TYPE_COPY = 0x3,
2a69cb9f
OG		 5804};
5805
5806enum {
5807 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5808 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5809 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5810 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5811 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5812 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5813 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5814 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5815 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5816 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5817 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5818 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5819 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5820 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5821 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5822 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5823 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5824 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5825 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5826 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5827 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5828 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0eb69bb9 5829 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
0c0316f5 5830 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
97b5484e
AV		 5831 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5832 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
65c0f2c1 5833 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
97b5484e
AV		 5834 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5835 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5836 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5837 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5838 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
822e114b
PB		 5839 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5840 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
97b5484e
AV		 5841 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5842 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
78fb6122 5843 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
2a69cb9f
OG		 5844};
5845
5846struct mlx5_ifc_alloc_modify_header_context_out_bits {
5847 u8 status[0x8];
5848 u8 reserved_at_8[0x18];
5849
5850 u8 syndrome[0x20];
5851
5852 u8 modify_header_id[0x20];
5853
5854 u8 reserved_at_60[0x20];
5855};
5856
5857struct mlx5_ifc_alloc_modify_header_context_in_bits {
5858 u8 opcode[0x10];
5859 u8 reserved_at_10[0x10];
5860
5861 u8 reserved_at_20[0x10];
5862 u8 op_mod[0x10];
5863
5864 u8 reserved_at_40[0x20];
5865
5866 u8 table_type[0x8];
5867 u8 reserved_at_68[0x10];
5868 u8 num_of_actions[0x8];
5869
d65dbedf 5870 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0];
2a69cb9f
OG		 5871};
5872
5873struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5874 u8 status[0x8];
5875 u8 reserved_at_8[0x18];
5876
5877 u8 syndrome[0x20];
5878
5879 u8 reserved_at_40[0x40];
5880};
5881
5882struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5883 u8 opcode[0x10];
5884 u8 reserved_at_10[0x10];
5885
5886 u8 reserved_at_20[0x10];
5887 u8 op_mod[0x10];
5888
5889 u8 modify_header_id[0x20];
5890
5891 u8 reserved_at_60[0x20];
5892};
5893
e281682b
SM		 5894struct mlx5_ifc_query_dct_out_bits {
5895 u8 status[0x8];
b4ff3a36 5896 u8 reserved_at_8[0x18];
e281682b
SM		 5897
5898 u8 syndrome[0x20];
5899
b4ff3a36 5900 u8 reserved_at_40[0x40];
e281682b
SM		 5901
5902 struct mlx5_ifc_dctc_bits dct_context_entry;
5903
b4ff3a36 5904 u8 reserved_at_280[0x180];
e281682b
SM		 5905};
5906
5907struct mlx5_ifc_query_dct_in_bits {
5908 u8 opcode[0x10];
b4ff3a36 5909 u8 reserved_at_10[0x10];
e281682b 5910
b4ff3a36 5911 u8 reserved_at_20[0x10];
e281682b
SM		 5912 u8 op_mod[0x10];
5913
b4ff3a36 5914 u8 reserved_at_40[0x8];
e281682b
SM		 5915 u8 dctn[0x18];
5916
b4ff3a36 5917 u8 reserved_at_60[0x20];
e281682b
SM		 5918};
5919
5920struct mlx5_ifc_query_cq_out_bits {
5921 u8 status[0x8];
b4ff3a36 5922 u8 reserved_at_8[0x18];
e281682b
SM		 5923
5924 u8 syndrome[0x20];
5925
b4ff3a36 5926 u8 reserved_at_40[0x40];
e281682b
SM		 5927
5928 struct mlx5_ifc_cqc_bits cq_context;
5929
b4ff3a36 5930 u8 reserved_at_280[0x600];
e281682b 5931
b6ca09cb 5932 u8 pas[][0x40];
e281682b
SM		 5933};
5934
5935struct mlx5_ifc_query_cq_in_bits {
5936 u8 opcode[0x10];
b4ff3a36 5937 u8 reserved_at_10[0x10];
e281682b 5938
b4ff3a36 5939 u8 reserved_at_20[0x10];
e281682b
SM		 5940 u8 op_mod[0x10];
5941
b4ff3a36 5942 u8 reserved_at_40[0x8];
e281682b
SM		 5943 u8 cqn[0x18];
5944
b4ff3a36 5945 u8 reserved_at_60[0x20];
e281682b
SM		 5946};
5947
5948struct mlx5_ifc_query_cong_status_out_bits {
5949 u8 status[0x8];
b4ff3a36 5950 u8 reserved_at_8[0x18];
e281682b
SM		 5951
5952 u8 syndrome[0x20];
5953
b4ff3a36 5954 u8 reserved_at_40[0x20];
e281682b
SM		 5955
5956 u8 enable[0x1];
5957 u8 tag_enable[0x1];
b4ff3a36 5958 u8 reserved_at_62[0x1e];
e281682b
SM		 5959};
5960
5961struct mlx5_ifc_query_cong_status_in_bits {
5962 u8 opcode[0x10];
b4ff3a36 5963 u8 reserved_at_10[0x10];
e281682b 5964
b4ff3a36 5965 u8 reserved_at_20[0x10];
e281682b
SM		 5966 u8 op_mod[0x10];
5967
b4ff3a36 5968 u8 reserved_at_40[0x18];
e281682b
SM		 5969 u8 priority[0x4];
5970 u8 cong_protocol[0x4];
5971
b4ff3a36 5972 u8 reserved_at_60[0x20];
e281682b
SM		 5973};
5974
5975struct mlx5_ifc_query_cong_statistics_out_bits {
5976 u8 status[0x8];
b4ff3a36 5977 u8 reserved_at_8[0x18];
e281682b
SM		 5978
5979 u8 syndrome[0x20];
5980
b4ff3a36 5981 u8 reserved_at_40[0x40];
e281682b 5982
e1f24a79 5983 u8 rp_cur_flows[0x20];
e281682b
SM		 5984
5985 u8 sum_flows[0x20];
5986
e1f24a79 5987 u8 rp_cnp_ignored_high[0x20];
e281682b 5988
e1f24a79 5989 u8 rp_cnp_ignored_low[0x20];
e281682b 5990
e1f24a79 5991 u8 rp_cnp_handled_high[0x20];
e281682b 5992
e1f24a79 5993 u8 rp_cnp_handled_low[0x20];
e281682b 5994
b4ff3a36 5995 u8 reserved_at_140[0x100];
e281682b
SM		 5996
5997 u8 time_stamp_high[0x20];
5998
5999 u8 time_stamp_low[0x20];
6000
6001 u8 accumulators_period[0x20];
6002
e1f24a79 6003 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 6004
e1f24a79 6005 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 6006
e1f24a79 6007 u8 np_cnp_sent_high[0x20];
e281682b 6008
e1f24a79 6009 u8 np_cnp_sent_low[0x20];
e281682b 6010
b4ff3a36 6011 u8 reserved_at_320[0x560];
e281682b
SM		 6012};
6013
6014struct mlx5_ifc_query_cong_statistics_in_bits {
6015 u8 opcode[0x10];
b4ff3a36 6016 u8 reserved_at_10[0x10];
e281682b 6017
b4ff3a36 6018 u8 reserved_at_20[0x10];
e281682b
SM		 6019 u8 op_mod[0x10];
6020
6021 u8 clear[0x1];
b4ff3a36 6022 u8 reserved_at_41[0x1f];
e281682b 6023
b4ff3a36 6024 u8 reserved_at_60[0x20];
e281682b
SM		 6025};
6026
6027struct mlx5_ifc_query_cong_params_out_bits {
6028 u8 status[0x8];
b4ff3a36 6029 u8 reserved_at_8[0x18];
e281682b
SM		 6030
6031 u8 syndrome[0x20];
6032
b4ff3a36 6033 u8 reserved_at_40[0x40];
e281682b
SM		 6034
6035 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6036};
6037
6038struct mlx5_ifc_query_cong_params_in_bits {
6039 u8 opcode[0x10];
b4ff3a36 6040 u8 reserved_at_10[0x10];
e281682b 6041
b4ff3a36 6042 u8 reserved_at_20[0x10];
e281682b
SM		 6043 u8 op_mod[0x10];
6044
b4ff3a36 6045 u8 reserved_at_40[0x1c];
e281682b
SM		 6046 u8 cong_protocol[0x4];
6047
b4ff3a36 6048 u8 reserved_at_60[0x20];
e281682b
SM		 6049};
6050
6051struct mlx5_ifc_query_adapter_out_bits {
6052 u8 status[0x8];
b4ff3a36 6053 u8 reserved_at_8[0x18];
e281682b
SM		 6054
6055 u8 syndrome[0x20];
6056
b4ff3a36 6057 u8 reserved_at_40[0x40];
e281682b
SM		 6058
6059 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6060};
6061
6062struct mlx5_ifc_query_adapter_in_bits {
6063 u8 opcode[0x10];
b4ff3a36 6064 u8 reserved_at_10[0x10];
e281682b 6065
b4ff3a36 6066 u8 reserved_at_20[0x10];
e281682b
SM		 6067 u8 op_mod[0x10];
6068
b4ff3a36 6069 u8 reserved_at_40[0x40];
e281682b
SM		 6070};
6071
6072struct mlx5_ifc_qp_2rst_out_bits {
6073 u8 status[0x8];
b4ff3a36 6074 u8 reserved_at_8[0x18];
e281682b
SM		 6075
6076 u8 syndrome[0x20];
6077
b4ff3a36 6078 u8 reserved_at_40[0x40];
e281682b
SM		 6079};
6080
6081struct mlx5_ifc_qp_2rst_in_bits {
6082 u8 opcode[0x10];
4ac63ec7 6083 u8 uid[0x10];
e281682b 6084
b4ff3a36 6085 u8 reserved_at_20[0x10];
e281682b
SM		 6086 u8 op_mod[0x10];
6087
b4ff3a36 6088 u8 reserved_at_40[0x8];
e281682b
SM		 6089 u8 qpn[0x18];
6090
b4ff3a36 6091 u8 reserved_at_60[0x20];
e281682b
SM		 6092};
6093
6094struct mlx5_ifc_qp_2err_out_bits {
6095 u8 status[0x8];
b4ff3a36 6096 u8 reserved_at_8[0x18];
e281682b
SM		 6097
6098 u8 syndrome[0x20];
6099
b4ff3a36 6100 u8 reserved_at_40[0x40];
e281682b
SM		 6101};
6102
6103struct mlx5_ifc_qp_2err_in_bits {
6104 u8 opcode[0x10];
4ac63ec7 6105 u8 uid[0x10];
e281682b 6106
b4ff3a36 6107 u8 reserved_at_20[0x10];
e281682b
SM		 6108 u8 op_mod[0x10];
6109
b4ff3a36 6110 u8 reserved_at_40[0x8];
e281682b
SM		 6111 u8 qpn[0x18];
6112
b4ff3a36 6113 u8 reserved_at_60[0x20];
e281682b
SM		 6114};
6115
6116struct mlx5_ifc_page_fault_resume_out_bits {
6117 u8 status[0x8];
b4ff3a36 6118 u8 reserved_at_8[0x18];
e281682b
SM		 6119
6120 u8 syndrome[0x20];
6121
b4ff3a36 6122 u8 reserved_at_40[0x40];
e281682b
SM		 6123};
6124
6125struct mlx5_ifc_page_fault_resume_in_bits {
6126 u8 opcode[0x10];
b4ff3a36 6127 u8 reserved_at_10[0x10];
e281682b 6128
b4ff3a36 6129 u8 reserved_at_20[0x10];
e281682b
SM		 6130 u8 op_mod[0x10];
6131
6132 u8 error[0x1];
b4ff3a36 6133 u8 reserved_at_41[0x4];
223cdc72
AK		 6134 u8 page_fault_type[0x3];
6135 u8 wq_number[0x18];
e281682b 6136
223cdc72
AK		 6137 u8 reserved_at_60[0x8];
6138 u8 token[0x18];
e281682b
SM		 6139};
6140
6141struct mlx5_ifc_nop_out_bits {
6142 u8 status[0x8];
b4ff3a36 6143 u8 reserved_at_8[0x18];
e281682b
SM		 6144
6145 u8 syndrome[0x20];
6146
b4ff3a36 6147 u8 reserved_at_40[0x40];
e281682b
SM		 6148};
6149
6150struct mlx5_ifc_nop_in_bits {
6151 u8 opcode[0x10];
b4ff3a36 6152 u8 reserved_at_10[0x10];
e281682b 6153
b4ff3a36 6154 u8 reserved_at_20[0x10];
e281682b
SM		 6155 u8 op_mod[0x10];
6156
b4ff3a36 6157 u8 reserved_at_40[0x40];
e281682b
SM		 6158};
6159
6160struct mlx5_ifc_modify_vport_state_out_bits {
6161 u8 status[0x8];
b4ff3a36 6162 u8 reserved_at_8[0x18];
e281682b
SM		 6163
6164 u8 syndrome[0x20];
6165
b4ff3a36 6166 u8 reserved_at_40[0x40];
e281682b
SM		 6167};
6168
6169struct mlx5_ifc_modify_vport_state_in_bits {
6170 u8 opcode[0x10];
b4ff3a36 6171 u8 reserved_at_10[0x10];
e281682b 6172
b4ff3a36 6173 u8 reserved_at_20[0x10];
e281682b
SM		 6174 u8 op_mod[0x10];
6175
6176 u8 other_vport[0x1];
b4ff3a36 6177 u8 reserved_at_41[0xf];
e281682b
SM		 6178 u8 vport_number[0x10];
6179
b4ff3a36 6180 u8 reserved_at_60[0x18];
e281682b 6181 u8 admin_state[0x4];
b4ff3a36 6182 u8 reserved_at_7c[0x4];
e281682b
SM		 6183};
6184
6185struct mlx5_ifc_modify_tis_out_bits {
6186 u8 status[0x8];
b4ff3a36 6187 u8 reserved_at_8[0x18];
e281682b
SM		 6188
6189 u8 syndrome[0x20];
6190
b4ff3a36 6191 u8 reserved_at_40[0x40];
e281682b
SM		 6192};
6193
75850d0b 6194struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 6195 u8 reserved_at_0[0x20];
75850d0b 6196
84df61eb
AH		 6197 u8 reserved_at_20[0x1d];
6198 u8 lag_tx_port_affinity[0x1];
6199 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 6200 u8 prio[0x1];
6201};
6202
e281682b
SM		 6203struct mlx5_ifc_modify_tis_in_bits {
6204 u8 opcode[0x10];
bd371975 6205 u8 uid[0x10];
e281682b 6206
b4ff3a36 6207 u8 reserved_at_20[0x10];
e281682b
SM		 6208 u8 op_mod[0x10];
6209
b4ff3a36 6210 u8 reserved_at_40[0x8];
e281682b
SM		 6211 u8 tisn[0x18];
6212
b4ff3a36 6213 u8 reserved_at_60[0x20];
e281682b 6214
75850d0b 6215 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 6216
b4ff3a36 6217 u8 reserved_at_c0[0x40];
e281682b
SM		 6218
6219 struct mlx5_ifc_tisc_bits ctx;
6220};
6221
d9eea403 6222struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 6223 u8 reserved_at_0[0x20];
d9eea403 6224
b4ff3a36 6225 u8 reserved_at_20[0x1b];
66189961 6226 u8 self_lb_en[0x1];
bdfc028d
TT		 6227 u8 reserved_at_3c[0x1];
6228 u8 hash[0x1];
6229 u8 reserved_at_3e[0x1];
d9eea403
AS		 6230 u8 lro[0x1];
6231};
6232
e281682b
SM		 6233struct mlx5_ifc_modify_tir_out_bits {
6234 u8 status[0x8];
b4ff3a36 6235 u8 reserved_at_8[0x18];
e281682b
SM		 6236
6237 u8 syndrome[0x20];
6238
b4ff3a36 6239 u8 reserved_at_40[0x40];
e281682b
SM		 6240};
6241
6242struct mlx5_ifc_modify_tir_in_bits {
6243 u8 opcode[0x10];
bd371975 6244 u8 uid[0x10];
e281682b 6245
b4ff3a36 6246 u8 reserved_at_20[0x10];
e281682b
SM		 6247 u8 op_mod[0x10];
6248
b4ff3a36 6249 u8 reserved_at_40[0x8];
e281682b
SM		 6250 u8 tirn[0x18];
6251
b4ff3a36 6252 u8 reserved_at_60[0x20];
e281682b 6253
d9eea403 6254 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 6255
b4ff3a36 6256 u8 reserved_at_c0[0x40];
e281682b
SM		 6257
6258 struct mlx5_ifc_tirc_bits ctx;
6259};
6260
6261struct mlx5_ifc_modify_sq_out_bits {
6262 u8 status[0x8];
b4ff3a36 6263 u8 reserved_at_8[0x18];
e281682b
SM		 6264
6265 u8 syndrome[0x20];
6266
b4ff3a36 6267 u8 reserved_at_40[0x40];
e281682b
SM		 6268};
6269
6270struct mlx5_ifc_modify_sq_in_bits {
6271 u8 opcode[0x10];
430ae0d5 6272 u8 uid[0x10];
e281682b 6273
b4ff3a36 6274 u8 reserved_at_20[0x10];
e281682b
SM		 6275 u8 op_mod[0x10];
6276
6277 u8 sq_state[0x4];
b4ff3a36 6278 u8 reserved_at_44[0x4];
e281682b
SM		 6279 u8 sqn[0x18];
6280
b4ff3a36 6281 u8 reserved_at_60[0x20];
e281682b
SM		 6282
6283 u8 modify_bitmask[0x40];
6284
b4ff3a36 6285 u8 reserved_at_c0[0x40];
e281682b
SM		 6286
6287 struct mlx5_ifc_sqc_bits ctx;
6288};
6289
813f8540
MHY		 6290struct mlx5_ifc_modify_scheduling_element_out_bits {
6291 u8 status[0x8];
6292 u8 reserved_at_8[0x18];
6293
6294 u8 syndrome[0x20];
6295
6296 u8 reserved_at_40[0x1c0];
6297};
6298
6299enum {
6300 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6301 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6302};
6303
6304struct mlx5_ifc_modify_scheduling_element_in_bits {
6305 u8 opcode[0x10];
6306 u8 reserved_at_10[0x10];
6307
6308 u8 reserved_at_20[0x10];
6309 u8 op_mod[0x10];
6310
6311 u8 scheduling_hierarchy[0x8];
6312 u8 reserved_at_48[0x18];
6313
6314 u8 scheduling_element_id[0x20];
6315
6316 u8 reserved_at_80[0x20];
6317
6318 u8 modify_bitmask[0x20];
6319
6320 u8 reserved_at_c0[0x40];
6321
6322 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6323
6324 u8 reserved_at_300[0x100];
6325};
6326
e281682b
SM		 6327struct mlx5_ifc_modify_rqt_out_bits {
6328 u8 status[0x8];
b4ff3a36 6329 u8 reserved_at_8[0x18];
e281682b
SM		 6330
6331 u8 syndrome[0x20];
6332
b4ff3a36 6333 u8 reserved_at_40[0x40];
e281682b
SM		 6334};
6335
5c50368f 6336struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 6337 u8 reserved_at_0[0x20];
5c50368f 6338
b4ff3a36 6339 u8 reserved_at_20[0x1f];
5c50368f
AS		 6340 u8 rqn_list[0x1];
6341};
6342
e281682b
SM		 6343struct mlx5_ifc_modify_rqt_in_bits {
6344 u8 opcode[0x10];
bd371975 6345 u8 uid[0x10];
e281682b 6346
b4ff3a36 6347 u8 reserved_at_20[0x10];
e281682b
SM		 6348 u8 op_mod[0x10];
6349
b4ff3a36 6350 u8 reserved_at_40[0x8];
e281682b
SM		 6351 u8 rqtn[0x18];
6352
b4ff3a36 6353 u8 reserved_at_60[0x20];
e281682b 6354
5c50368f 6355 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 6356
b4ff3a36 6357 u8 reserved_at_c0[0x40];
e281682b
SM		 6358
6359 struct mlx5_ifc_rqtc_bits ctx;
6360};
6361
6362struct mlx5_ifc_modify_rq_out_bits {
6363 u8 status[0x8];
b4ff3a36 6364 u8 reserved_at_8[0x18];
e281682b
SM		 6365
6366 u8 syndrome[0x20];
6367
b4ff3a36 6368 u8 reserved_at_40[0x40];
e281682b
SM		 6369};
6370
83b502a1
AV		 6371enum {
6372 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 6373 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 6374 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 6375};
6376
e281682b
SM		 6377struct mlx5_ifc_modify_rq_in_bits {
6378 u8 opcode[0x10];
d269b3af 6379 u8 uid[0x10];
e281682b 6380
b4ff3a36 6381 u8 reserved_at_20[0x10];
e281682b
SM		 6382 u8 op_mod[0x10];
6383
6384 u8 rq_state[0x4];
b4ff3a36 6385 u8 reserved_at_44[0x4];
e281682b
SM		 6386 u8 rqn[0x18];
6387
b4ff3a36 6388 u8 reserved_at_60[0x20];
e281682b
SM		 6389
6390 u8 modify_bitmask[0x40];
6391
b4ff3a36 6392 u8 reserved_at_c0[0x40];
e281682b
SM		 6393
6394 struct mlx5_ifc_rqc_bits ctx;
6395};
6396
6397struct mlx5_ifc_modify_rmp_out_bits {
6398 u8 status[0x8];
b4ff3a36 6399 u8 reserved_at_8[0x18];
e281682b
SM		 6400
6401 u8 syndrome[0x20];
6402
b4ff3a36 6403 u8 reserved_at_40[0x40];
e281682b
SM		 6404};
6405
01949d01 6406struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 6407 u8 reserved_at_0[0x20];
01949d01 6408
b4ff3a36 6409 u8 reserved_at_20[0x1f];
01949d01
HA		 6410 u8 lwm[0x1];
6411};
6412
e281682b
SM		 6413struct mlx5_ifc_modify_rmp_in_bits {
6414 u8 opcode[0x10];
a0d8c054 6415 u8 uid[0x10];
e281682b 6416
b4ff3a36 6417 u8 reserved_at_20[0x10];
e281682b
SM		 6418 u8 op_mod[0x10];
6419
6420 u8 rmp_state[0x4];
b4ff3a36 6421 u8 reserved_at_44[0x4];
e281682b
SM		 6422 u8 rmpn[0x18];
6423
b4ff3a36 6424 u8 reserved_at_60[0x20];
e281682b 6425
01949d01 6426 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 6427
b4ff3a36 6428 u8 reserved_at_c0[0x40];
e281682b
SM		 6429
6430 struct mlx5_ifc_rmpc_bits ctx;
6431};
6432
6433struct mlx5_ifc_modify_nic_vport_context_out_bits {
6434 u8 status[0x8];
b4ff3a36 6435 u8 reserved_at_8[0x18];
e281682b
SM		 6436
6437 u8 syndrome[0x20];
6438
b4ff3a36 6439 u8 reserved_at_40[0x40];
e281682b
SM		 6440};
6441
6442struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 6443 u8 reserved_at_0[0x12];
6444 u8 affiliation[0x1];
c74d90c1 6445 u8 reserved_at_13[0x1];
bded747b
HN		 6446 u8 disable_uc_local_lb[0x1];
6447 u8 disable_mc_local_lb[0x1];
23898c76
NO		 6448 u8 node_guid[0x1];
6449 u8 port_guid[0x1];
9def7121 6450 u8 min_inline[0x1];
d82b7318
SM		 6451 u8 mtu[0x1];
6452 u8 change_event[0x1];
6453 u8 promisc[0x1];
e281682b
SM		 6454 u8 permanent_address[0x1];
6455 u8 addresses_list[0x1];
6456 u8 roce_en[0x1];
b4ff3a36 6457 u8 reserved_at_1f[0x1];
e281682b
SM		 6458};
6459
6460struct mlx5_ifc_modify_nic_vport_context_in_bits {
6461 u8 opcode[0x10];
b4ff3a36 6462 u8 reserved_at_10[0x10];
e281682b 6463
b4ff3a36 6464 u8 reserved_at_20[0x10];
e281682b
SM		 6465 u8 op_mod[0x10];
6466
6467 u8 other_vport[0x1];
b4ff3a36 6468 u8 reserved_at_41[0xf];
e281682b
SM		 6469 u8 vport_number[0x10];
6470
6471 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6472
b4ff3a36 6473 u8 reserved_at_80[0x780];
e281682b
SM		 6474
6475 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6476};
6477
6478struct mlx5_ifc_modify_hca_vport_context_out_bits {
6479 u8 status[0x8];
b4ff3a36 6480 u8 reserved_at_8[0x18];
e281682b
SM		 6481
6482 u8 syndrome[0x20];
6483
b4ff3a36 6484 u8 reserved_at_40[0x40];
e281682b
SM		 6485};
6486
6487struct mlx5_ifc_modify_hca_vport_context_in_bits {
6488 u8 opcode[0x10];
b4ff3a36 6489 u8 reserved_at_10[0x10];
e281682b 6490
b4ff3a36 6491 u8 reserved_at_20[0x10];
e281682b
SM		 6492 u8 op_mod[0x10];
6493
6494 u8 other_vport[0x1];
b4ff3a36 6495 u8 reserved_at_41[0xb];
707c4602 6496 u8 port_num[0x4];
e281682b
SM		 6497 u8 vport_number[0x10];
6498
b4ff3a36 6499 u8 reserved_at_60[0x20];
e281682b
SM		 6500
6501 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6502};
6503
6504struct mlx5_ifc_modify_cq_out_bits {
6505 u8 status[0x8];
b4ff3a36 6506 u8 reserved_at_8[0x18];
e281682b
SM		 6507
6508 u8 syndrome[0x20];
6509
b4ff3a36 6510 u8 reserved_at_40[0x40];
e281682b
SM		 6511};
6512
6513enum {
6514 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6515 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6516};
6517
6518struct mlx5_ifc_modify_cq_in_bits {
6519 u8 opcode[0x10];
9ba481e2 6520 u8 uid[0x10];
e281682b 6521
b4ff3a36 6522 u8 reserved_at_20[0x10];
e281682b
SM		 6523 u8 op_mod[0x10];
6524
b4ff3a36 6525 u8 reserved_at_40[0x8];
e281682b
SM		 6526 u8 cqn[0x18];
6527
6528 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6529
6530 struct mlx5_ifc_cqc_bits cq_context;
6531
7a32f296 6532 u8 reserved_at_280[0x60];
bd371975
LR		 6533
6534 u8 cq_umem_valid[0x1];
7a32f296
ES		 6535 u8 reserved_at_2e1[0x1f];
6536
6537 u8 reserved_at_300[0x580];
e281682b 6538
b6ca09cb 6539 u8 pas[][0x40];
e281682b
SM		 6540};
6541
6542struct mlx5_ifc_modify_cong_status_out_bits {
6543 u8 status[0x8];
b4ff3a36 6544 u8 reserved_at_8[0x18];
e281682b
SM		 6545
6546 u8 syndrome[0x20];
6547
b4ff3a36 6548 u8 reserved_at_40[0x40];
e281682b
SM		 6549};
6550
6551struct mlx5_ifc_modify_cong_status_in_bits {
6552 u8 opcode[0x10];
b4ff3a36 6553 u8 reserved_at_10[0x10];
e281682b 6554
b4ff3a36 6555 u8 reserved_at_20[0x10];
e281682b
SM		 6556 u8 op_mod[0x10];
6557
b4ff3a36 6558 u8 reserved_at_40[0x18];
e281682b
SM		 6559 u8 priority[0x4];
6560 u8 cong_protocol[0x4];
6561
6562 u8 enable[0x1];
6563 u8 tag_enable[0x1];
b4ff3a36 6564 u8 reserved_at_62[0x1e];
e281682b
SM		 6565};
6566
6567struct mlx5_ifc_modify_cong_params_out_bits {
6568 u8 status[0x8];
b4ff3a36 6569 u8 reserved_at_8[0x18];
e281682b
SM		 6570
6571 u8 syndrome[0x20];
6572
b4ff3a36 6573 u8 reserved_at_40[0x40];
e281682b
SM		 6574};
6575
6576struct mlx5_ifc_modify_cong_params_in_bits {
6577 u8 opcode[0x10];
b4ff3a36 6578 u8 reserved_at_10[0x10];
e281682b 6579
b4ff3a36 6580 u8 reserved_at_20[0x10];
e281682b
SM		 6581 u8 op_mod[0x10];
6582
b4ff3a36 6583 u8 reserved_at_40[0x1c];
e281682b
SM		 6584 u8 cong_protocol[0x4];
6585
6586 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6587
b4ff3a36 6588 u8 reserved_at_80[0x80];
e281682b
SM		 6589
6590 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6591};
6592
6593struct mlx5_ifc_manage_pages_out_bits {
6594 u8 status[0x8];
b4ff3a36 6595 u8 reserved_at_8[0x18];
e281682b
SM		 6596
6597 u8 syndrome[0x20];
6598
6599 u8 output_num_entries[0x20];
6600
b4ff3a36 6601 u8 reserved_at_60[0x20];
e281682b 6602
b6ca09cb 6603 u8 pas[][0x40];
e281682b
SM		 6604};
6605
6606enum {
6607 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6608 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6609 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6610};
6611
6612struct mlx5_ifc_manage_pages_in_bits {
6613 u8 opcode[0x10];
b4ff3a36 6614 u8 reserved_at_10[0x10];
e281682b 6615
b4ff3a36 6616 u8 reserved_at_20[0x10];
e281682b
SM		 6617 u8 op_mod[0x10];
6618
591905ba
BW		 6619 u8 embedded_cpu_function[0x1];
6620 u8 reserved_at_41[0xf];
e281682b
SM		 6621 u8 function_id[0x10];
6622
6623 u8 input_num_entries[0x20];
6624
b6ca09cb 6625 u8 pas[][0x40];
e281682b
SM		 6626};
6627
6628struct mlx5_ifc_mad_ifc_out_bits {
6629 u8 status[0x8];
b4ff3a36 6630 u8 reserved_at_8[0x18];
e281682b
SM		 6631
6632 u8 syndrome[0x20];
6633
b4ff3a36 6634 u8 reserved_at_40[0x40];
e281682b
SM		 6635
6636 u8 response_mad_packet[256][0x8];
6637};
6638
6639struct mlx5_ifc_mad_ifc_in_bits {
6640 u8 opcode[0x10];
b4ff3a36 6641 u8 reserved_at_10[0x10];
e281682b 6642
b4ff3a36 6643 u8 reserved_at_20[0x10];
e281682b
SM		 6644 u8 op_mod[0x10];
6645
6646 u8 remote_lid[0x10];
b4ff3a36 6647 u8 reserved_at_50[0x8];
e281682b
SM		 6648 u8 port[0x8];
6649
b4ff3a36 6650 u8 reserved_at_60[0x20];
e281682b
SM		 6651
6652 u8 mad[256][0x8];
6653};
6654
6655struct mlx5_ifc_init_hca_out_bits {
6656 u8 status[0x8];
b4ff3a36 6657 u8 reserved_at_8[0x18];
e281682b
SM		 6658
6659 u8 syndrome[0x20];
6660
b4ff3a36 6661 u8 reserved_at_40[0x40];
e281682b
SM		 6662};
6663
6664struct mlx5_ifc_init_hca_in_bits {
6665 u8 opcode[0x10];
b4ff3a36 6666 u8 reserved_at_10[0x10];
e281682b 6667
b4ff3a36 6668 u8 reserved_at_20[0x10];
e281682b
SM		 6669 u8 op_mod[0x10];
6670
b4ff3a36 6671 u8 reserved_at_40[0x40];
8737f818 6672 u8 sw_owner_id[4][0x20];
e281682b
SM		 6673};
6674
6675struct mlx5_ifc_init2rtr_qp_out_bits {
6676 u8 status[0x8];
b4ff3a36 6677 u8 reserved_at_8[0x18];
e281682b
SM		 6678
6679 u8 syndrome[0x20];
6680
6b646a7e
LR		 6681 u8 reserved_at_40[0x20];
6682 u8 ece[0x20];
e281682b
SM		 6683};
6684
6685struct mlx5_ifc_init2rtr_qp_in_bits {
6686 u8 opcode[0x10];
4ac63ec7 6687 u8 uid[0x10];
e281682b 6688
b4ff3a36 6689 u8 reserved_at_20[0x10];
e281682b
SM		 6690 u8 op_mod[0x10];
6691
b4ff3a36 6692 u8 reserved_at_40[0x8];
e281682b
SM		 6693 u8 qpn[0x18];
6694
b4ff3a36 6695 u8 reserved_at_60[0x20];
e281682b
SM		 6696
6697 u8 opt_param_mask[0x20];
6698
6b646a7e 6699 u8 ece[0x20];
e281682b
SM		 6700
6701 struct mlx5_ifc_qpc_bits qpc;
6702
b4ff3a36 6703 u8 reserved_at_800[0x80];
e281682b
SM		 6704};
6705
6706struct mlx5_ifc_init2init_qp_out_bits {
6707 u8 status[0x8];
b4ff3a36 6708 u8 reserved_at_8[0x18];
e281682b
SM		 6709
6710 u8 syndrome[0x20];
6711
ab183d46
LR		 6712 u8 reserved_at_40[0x20];
6713 u8 ece[0x20];
e281682b
SM		 6714};
6715
6716struct mlx5_ifc_init2init_qp_in_bits {
6717 u8 opcode[0x10];
4ac63ec7 6718 u8 uid[0x10];
e281682b 6719
b4ff3a36 6720 u8 reserved_at_20[0x10];
e281682b
SM		 6721 u8 op_mod[0x10];
6722
b4ff3a36 6723 u8 reserved_at_40[0x8];
e281682b
SM		 6724 u8 qpn[0x18];
6725
b4ff3a36 6726 u8 reserved_at_60[0x20];
e281682b
SM		 6727
6728 u8 opt_param_mask[0x20];
6729
ab183d46 6730 u8 ece[0x20];
e281682b
SM		 6731
6732 struct mlx5_ifc_qpc_bits qpc;
6733
b4ff3a36 6734 u8 reserved_at_800[0x80];
e281682b
SM		 6735};
6736
6737struct mlx5_ifc_get_dropped_packet_log_out_bits {
6738 u8 status[0x8];
b4ff3a36 6739 u8 reserved_at_8[0x18];
e281682b
SM		 6740
6741 u8 syndrome[0x20];
6742
b4ff3a36 6743 u8 reserved_at_40[0x40];
e281682b
SM		 6744
6745 u8 packet_headers_log[128][0x8];
6746
6747 u8 packet_syndrome[64][0x8];
6748};
6749
6750struct mlx5_ifc_get_dropped_packet_log_in_bits {
6751 u8 opcode[0x10];
b4ff3a36 6752 u8 reserved_at_10[0x10];
e281682b 6753
b4ff3a36 6754 u8 reserved_at_20[0x10];
e281682b
SM		 6755 u8 op_mod[0x10];
6756
b4ff3a36 6757 u8 reserved_at_40[0x40];
e281682b
SM		 6758};
6759
6760struct mlx5_ifc_gen_eqe_in_bits {
6761 u8 opcode[0x10];
b4ff3a36 6762 u8 reserved_at_10[0x10];
e281682b 6763
b4ff3a36 6764 u8 reserved_at_20[0x10];
e281682b
SM		 6765 u8 op_mod[0x10];
6766
b4ff3a36 6767 u8 reserved_at_40[0x18];
e281682b
SM		 6768 u8 eq_number[0x8];
6769
b4ff3a36 6770 u8 reserved_at_60[0x20];
e281682b
SM		 6771
6772 u8 eqe[64][0x8];
6773};
6774
6775struct mlx5_ifc_gen_eq_out_bits {
6776 u8 status[0x8];
b4ff3a36 6777 u8 reserved_at_8[0x18];
e281682b
SM		 6778
6779 u8 syndrome[0x20];
6780
b4ff3a36 6781 u8 reserved_at_40[0x40];
e281682b
SM		 6782};
6783
6784struct mlx5_ifc_enable_hca_out_bits {
6785 u8 status[0x8];
b4ff3a36 6786 u8 reserved_at_8[0x18];
e281682b
SM		 6787
6788 u8 syndrome[0x20];
6789
b4ff3a36 6790 u8 reserved_at_40[0x20];
e281682b
SM		 6791};
6792
6793struct mlx5_ifc_enable_hca_in_bits {
6794 u8 opcode[0x10];
b4ff3a36 6795 u8 reserved_at_10[0x10];
e281682b 6796
b4ff3a36 6797 u8 reserved_at_20[0x10];
e281682b
SM		 6798 u8 op_mod[0x10];
6799
22e939a9
BW		 6800 u8 embedded_cpu_function[0x1];
6801 u8 reserved_at_41[0xf];
e281682b
SM		 6802 u8 function_id[0x10];
6803
b4ff3a36 6804 u8 reserved_at_60[0x20];
e281682b
SM		 6805};
6806
6807struct mlx5_ifc_drain_dct_out_bits {
6808 u8 status[0x8];
b4ff3a36 6809 u8 reserved_at_8[0x18];
e281682b
SM		 6810
6811 u8 syndrome[0x20];
6812
b4ff3a36 6813 u8 reserved_at_40[0x40];
e281682b
SM		 6814};
6815
6816struct mlx5_ifc_drain_dct_in_bits {
6817 u8 opcode[0x10];
774ea6ee 6818 u8 uid[0x10];
e281682b 6819
b4ff3a36 6820 u8 reserved_at_20[0x10];
e281682b
SM		 6821 u8 op_mod[0x10];
6822
b4ff3a36 6823 u8 reserved_at_40[0x8];
e281682b
SM		 6824 u8 dctn[0x18];
6825
b4ff3a36 6826 u8 reserved_at_60[0x20];
e281682b
SM		 6827};
6828
6829struct mlx5_ifc_disable_hca_out_bits {
6830 u8 status[0x8];
b4ff3a36 6831 u8 reserved_at_8[0x18];
e281682b
SM		 6832
6833 u8 syndrome[0x20];
6834
b4ff3a36 6835 u8 reserved_at_40[0x20];
e281682b
SM		 6836};
6837
6838struct mlx5_ifc_disable_hca_in_bits {
6839 u8 opcode[0x10];
b4ff3a36 6840 u8 reserved_at_10[0x10];
e281682b 6841
b4ff3a36 6842 u8 reserved_at_20[0x10];
e281682b
SM		 6843 u8 op_mod[0x10];
6844
22e939a9
BW		 6845 u8 embedded_cpu_function[0x1];
6846 u8 reserved_at_41[0xf];
e281682b
SM		 6847 u8 function_id[0x10];
6848
b4ff3a36 6849 u8 reserved_at_60[0x20];
e281682b
SM		 6850};
6851
6852struct mlx5_ifc_detach_from_mcg_out_bits {
6853 u8 status[0x8];
b4ff3a36 6854 u8 reserved_at_8[0x18];
e281682b
SM		 6855
6856 u8 syndrome[0x20];
6857
b4ff3a36 6858 u8 reserved_at_40[0x40];
e281682b
SM		 6859};
6860
6861struct mlx5_ifc_detach_from_mcg_in_bits {
6862 u8 opcode[0x10];
bd371975 6863 u8 uid[0x10];
e281682b 6864
b4ff3a36 6865 u8 reserved_at_20[0x10];
e281682b
SM		 6866 u8 op_mod[0x10];
6867
b4ff3a36 6868 u8 reserved_at_40[0x8];
e281682b
SM		 6869 u8 qpn[0x18];
6870
b4ff3a36 6871 u8 reserved_at_60[0x20];
e281682b
SM		 6872
6873 u8 multicast_gid[16][0x8];
6874};
6875
7486216b
SM		 6876struct mlx5_ifc_destroy_xrq_out_bits {
6877 u8 status[0x8];
6878 u8 reserved_at_8[0x18];
6879
6880 u8 syndrome[0x20];
6881
6882 u8 reserved_at_40[0x40];
6883};
6884
6885struct mlx5_ifc_destroy_xrq_in_bits {
6886 u8 opcode[0x10];
a0d8c054 6887 u8 uid[0x10];
7486216b
SM		 6888
6889 u8 reserved_at_20[0x10];
6890 u8 op_mod[0x10];
6891
6892 u8 reserved_at_40[0x8];
6893 u8 xrqn[0x18];
6894
6895 u8 reserved_at_60[0x20];
6896};
6897
e281682b
SM		 6898struct mlx5_ifc_destroy_xrc_srq_out_bits {
6899 u8 status[0x8];
b4ff3a36 6900 u8 reserved_at_8[0x18];
e281682b
SM		 6901
6902 u8 syndrome[0x20];
6903
b4ff3a36 6904 u8 reserved_at_40[0x40];
e281682b
SM		 6905};
6906
6907struct mlx5_ifc_destroy_xrc_srq_in_bits {
6908 u8 opcode[0x10];
a0d8c054 6909 u8 uid[0x10];
e281682b 6910
b4ff3a36 6911 u8 reserved_at_20[0x10];
e281682b
SM		 6912 u8 op_mod[0x10];
6913
b4ff3a36 6914 u8 reserved_at_40[0x8];
e281682b
SM		 6915 u8 xrc_srqn[0x18];
6916
b4ff3a36 6917 u8 reserved_at_60[0x20];
e281682b
SM		 6918};
6919
6920struct mlx5_ifc_destroy_tis_out_bits {
6921 u8 status[0x8];
b4ff3a36 6922 u8 reserved_at_8[0x18];
e281682b
SM		 6923
6924 u8 syndrome[0x20];
6925
b4ff3a36 6926 u8 reserved_at_40[0x40];
e281682b
SM		 6927};
6928
6929struct mlx5_ifc_destroy_tis_in_bits {
6930 u8 opcode[0x10];
bd371975 6931 u8 uid[0x10];
e281682b 6932
b4ff3a36 6933 u8 reserved_at_20[0x10];
e281682b
SM		 6934 u8 op_mod[0x10];
6935
b4ff3a36 6936 u8 reserved_at_40[0x8];
e281682b
SM		 6937 u8 tisn[0x18];
6938
b4ff3a36 6939 u8 reserved_at_60[0x20];
e281682b
SM		 6940};
6941
6942struct mlx5_ifc_destroy_tir_out_bits {
6943 u8 status[0x8];
b4ff3a36 6944 u8 reserved_at_8[0x18];
e281682b
SM		 6945
6946 u8 syndrome[0x20];
6947
b4ff3a36 6948 u8 reserved_at_40[0x40];
e281682b
SM		 6949};
6950
6951struct mlx5_ifc_destroy_tir_in_bits {
6952 u8 opcode[0x10];
bd371975 6953 u8 uid[0x10];
e281682b 6954
b4ff3a36 6955 u8 reserved_at_20[0x10];
e281682b
SM		 6956 u8 op_mod[0x10];
6957
b4ff3a36 6958 u8 reserved_at_40[0x8];
e281682b
SM		 6959 u8 tirn[0x18];
6960
b4ff3a36 6961 u8 reserved_at_60[0x20];
e281682b
SM		 6962};
6963
6964struct mlx5_ifc_destroy_srq_out_bits {
6965 u8 status[0x8];
b4ff3a36 6966 u8 reserved_at_8[0x18];
e281682b
SM		 6967
6968 u8 syndrome[0x20];
6969
b4ff3a36 6970 u8 reserved_at_40[0x40];
e281682b
SM		 6971};
6972
6973struct mlx5_ifc_destroy_srq_in_bits {
6974 u8 opcode[0x10];
a0d8c054 6975 u8 uid[0x10];
e281682b 6976
b4ff3a36 6977 u8 reserved_at_20[0x10];
e281682b
SM		 6978 u8 op_mod[0x10];
6979
b4ff3a36 6980 u8 reserved_at_40[0x8];
e281682b
SM		 6981 u8 srqn[0x18];
6982
b4ff3a36 6983 u8 reserved_at_60[0x20];
e281682b
SM		 6984};
6985
6986struct mlx5_ifc_destroy_sq_out_bits {
6987 u8 status[0x8];
b4ff3a36 6988 u8 reserved_at_8[0x18];
e281682b
SM		 6989
6990 u8 syndrome[0x20];
6991
b4ff3a36 6992 u8 reserved_at_40[0x40];
e281682b
SM		 6993};
6994
6995struct mlx5_ifc_destroy_sq_in_bits {
6996 u8 opcode[0x10];
430ae0d5 6997 u8 uid[0x10];
e281682b 6998
b4ff3a36 6999 u8 reserved_at_20[0x10];
e281682b
SM		 7000 u8 op_mod[0x10];
7001
b4ff3a36 7002 u8 reserved_at_40[0x8];
e281682b
SM		 7003 u8 sqn[0x18];
7004
b4ff3a36 7005 u8 reserved_at_60[0x20];
e281682b
SM		 7006};
7007
813f8540
MHY		 7008struct mlx5_ifc_destroy_scheduling_element_out_bits {
7009 u8 status[0x8];
7010 u8 reserved_at_8[0x18];
7011
7012 u8 syndrome[0x20];
7013
7014 u8 reserved_at_40[0x1c0];
7015};
7016
7017struct mlx5_ifc_destroy_scheduling_element_in_bits {
7018 u8 opcode[0x10];
7019 u8 reserved_at_10[0x10];
7020
7021 u8 reserved_at_20[0x10];
7022 u8 op_mod[0x10];
7023
7024 u8 scheduling_hierarchy[0x8];
7025 u8 reserved_at_48[0x18];
7026
7027 u8 scheduling_element_id[0x20];
7028
7029 u8 reserved_at_80[0x180];
7030};
7031
e281682b
SM		 7032struct mlx5_ifc_destroy_rqt_out_bits {
7033 u8 status[0x8];
b4ff3a36 7034 u8 reserved_at_8[0x18];
e281682b
SM		 7035
7036 u8 syndrome[0x20];
7037
b4ff3a36 7038 u8 reserved_at_40[0x40];
e281682b
SM		 7039};
7040
7041struct mlx5_ifc_destroy_rqt_in_bits {
7042 u8 opcode[0x10];
bd371975 7043 u8 uid[0x10];
e281682b 7044
b4ff3a36 7045 u8 reserved_at_20[0x10];
e281682b
SM		 7046 u8 op_mod[0x10];
7047
b4ff3a36 7048 u8 reserved_at_40[0x8];
e281682b
SM		 7049 u8 rqtn[0x18];
7050
b4ff3a36 7051 u8 reserved_at_60[0x20];
e281682b
SM		 7052};
7053
7054struct mlx5_ifc_destroy_rq_out_bits {
7055 u8 status[0x8];
b4ff3a36 7056 u8 reserved_at_8[0x18];
e281682b
SM		 7057
7058 u8 syndrome[0x20];
7059
b4ff3a36 7060 u8 reserved_at_40[0x40];
e281682b
SM		 7061};
7062
7063struct mlx5_ifc_destroy_rq_in_bits {
7064 u8 opcode[0x10];
d269b3af 7065 u8 uid[0x10];
e281682b 7066
b4ff3a36 7067 u8 reserved_at_20[0x10];
e281682b
SM		 7068 u8 op_mod[0x10];
7069
b4ff3a36 7070 u8 reserved_at_40[0x8];
e281682b
SM		 7071 u8 rqn[0x18];
7072
b4ff3a36 7073 u8 reserved_at_60[0x20];
e281682b
SM		 7074};
7075
c1e0bfc1
MG		 7076struct mlx5_ifc_set_delay_drop_params_in_bits {
7077 u8 opcode[0x10];
7078 u8 reserved_at_10[0x10];
7079
7080 u8 reserved_at_20[0x10];
7081 u8 op_mod[0x10];
7082
7083 u8 reserved_at_40[0x20];
7084
7085 u8 reserved_at_60[0x10];
7086 u8 delay_drop_timeout[0x10];
7087};
7088
7089struct mlx5_ifc_set_delay_drop_params_out_bits {
7090 u8 status[0x8];
7091 u8 reserved_at_8[0x18];
7092
7093 u8 syndrome[0x20];
7094
7095 u8 reserved_at_40[0x40];
7096};
7097
e281682b
SM		 7098struct mlx5_ifc_destroy_rmp_out_bits {
7099 u8 status[0x8];
b4ff3a36 7100 u8 reserved_at_8[0x18];
e281682b
SM		 7101
7102 u8 syndrome[0x20];
7103
b4ff3a36 7104 u8 reserved_at_40[0x40];
e281682b
SM		 7105};
7106
7107struct mlx5_ifc_destroy_rmp_in_bits {
7108 u8 opcode[0x10];
a0d8c054 7109 u8 uid[0x10];
e281682b 7110
b4ff3a36 7111 u8 reserved_at_20[0x10];
e281682b
SM		 7112 u8 op_mod[0x10];
7113
b4ff3a36 7114 u8 reserved_at_40[0x8];
e281682b
SM		 7115 u8 rmpn[0x18];
7116
b4ff3a36 7117 u8 reserved_at_60[0x20];
e281682b
SM		 7118};
7119
7120struct mlx5_ifc_destroy_qp_out_bits {
7121 u8 status[0x8];
b4ff3a36 7122 u8 reserved_at_8[0x18];
e281682b
SM		 7123
7124 u8 syndrome[0x20];
7125
b4ff3a36 7126 u8 reserved_at_40[0x40];
e281682b
SM		 7127};
7128
7129struct mlx5_ifc_destroy_qp_in_bits {
7130 u8 opcode[0x10];
4ac63ec7 7131 u8 uid[0x10];
e281682b 7132
b4ff3a36 7133 u8 reserved_at_20[0x10];
e281682b
SM		 7134 u8 op_mod[0x10];
7135
b4ff3a36 7136 u8 reserved_at_40[0x8];
e281682b
SM		 7137 u8 qpn[0x18];
7138
b4ff3a36 7139 u8 reserved_at_60[0x20];
e281682b
SM		 7140};
7141
7142struct mlx5_ifc_destroy_psv_out_bits {
7143 u8 status[0x8];
b4ff3a36 7144 u8 reserved_at_8[0x18];
e281682b
SM		 7145
7146 u8 syndrome[0x20];
7147
b4ff3a36 7148 u8 reserved_at_40[0x40];
e281682b
SM		 7149};
7150
7151struct mlx5_ifc_destroy_psv_in_bits {
7152 u8 opcode[0x10];
b4ff3a36 7153 u8 reserved_at_10[0x10];
e281682b 7154
b4ff3a36 7155 u8 reserved_at_20[0x10];
e281682b
SM		 7156 u8 op_mod[0x10];
7157
b4ff3a36 7158 u8 reserved_at_40[0x8];
e281682b
SM		 7159 u8 psvn[0x18];
7160
b4ff3a36 7161 u8 reserved_at_60[0x20];
e281682b
SM		 7162};
7163
7164struct mlx5_ifc_destroy_mkey_out_bits {
7165 u8 status[0x8];
b4ff3a36 7166 u8 reserved_at_8[0x18];
e281682b
SM		 7167
7168 u8 syndrome[0x20];
7169
b4ff3a36 7170 u8 reserved_at_40[0x40];
e281682b
SM		 7171};
7172
7173struct mlx5_ifc_destroy_mkey_in_bits {
7174 u8 opcode[0x10];
8a06a79b 7175 u8 uid[0x10];
e281682b 7176
b4ff3a36 7177 u8 reserved_at_20[0x10];
e281682b
SM		 7178 u8 op_mod[0x10];
7179
b4ff3a36 7180 u8 reserved_at_40[0x8];
e281682b
SM		 7181 u8 mkey_index[0x18];
7182
b4ff3a36 7183 u8 reserved_at_60[0x20];
e281682b
SM		 7184};
7185
7186struct mlx5_ifc_destroy_flow_table_out_bits {
7187 u8 status[0x8];
b4ff3a36 7188 u8 reserved_at_8[0x18];
e281682b
SM		 7189
7190 u8 syndrome[0x20];
7191
b4ff3a36 7192 u8 reserved_at_40[0x40];
e281682b
SM		 7193};
7194
7195struct mlx5_ifc_destroy_flow_table_in_bits {
7196 u8 opcode[0x10];
b4ff3a36 7197 u8 reserved_at_10[0x10];
e281682b 7198
b4ff3a36 7199 u8 reserved_at_20[0x10];
e281682b
SM		 7200 u8 op_mod[0x10];
7201
7d5e1423
SM		 7202 u8 other_vport[0x1];
7203 u8 reserved_at_41[0xf];
7204 u8 vport_number[0x10];
7205
7206 u8 reserved_at_60[0x20];
e281682b
SM		 7207
7208 u8 table_type[0x8];
b4ff3a36 7209 u8 reserved_at_88[0x18];
e281682b 7210
b4ff3a36 7211 u8 reserved_at_a0[0x8];
e281682b
SM		 7212 u8 table_id[0x18];
7213
b4ff3a36 7214 u8 reserved_at_c0[0x140];
e281682b
SM		 7215};
7216
7217struct mlx5_ifc_destroy_flow_group_out_bits {
7218 u8 status[0x8];
b4ff3a36 7219 u8 reserved_at_8[0x18];
e281682b
SM		 7220
7221 u8 syndrome[0x20];
7222
b4ff3a36 7223 u8 reserved_at_40[0x40];
e281682b
SM		 7224};
7225
7226struct mlx5_ifc_destroy_flow_group_in_bits {
7227 u8 opcode[0x10];
b4ff3a36 7228 u8 reserved_at_10[0x10];
e281682b 7229
b4ff3a36 7230 u8 reserved_at_20[0x10];
e281682b
SM		 7231 u8 op_mod[0x10];
7232
7d5e1423
SM		 7233 u8 other_vport[0x1];
7234 u8 reserved_at_41[0xf];
7235 u8 vport_number[0x10];
7236
7237 u8 reserved_at_60[0x20];
e281682b
SM		 7238
7239 u8 table_type[0x8];
b4ff3a36 7240 u8 reserved_at_88[0x18];
e281682b 7241
b4ff3a36 7242 u8 reserved_at_a0[0x8];
e281682b
SM		 7243 u8 table_id[0x18];
7244
7245 u8 group_id[0x20];
7246
b4ff3a36 7247 u8 reserved_at_e0[0x120];
e281682b
SM		 7248};
7249
7250struct mlx5_ifc_destroy_eq_out_bits {
7251 u8 status[0x8];
b4ff3a36 7252 u8 reserved_at_8[0x18];
e281682b
SM		 7253
7254 u8 syndrome[0x20];
7255
b4ff3a36 7256 u8 reserved_at_40[0x40];
e281682b
SM		 7257};
7258
7259struct mlx5_ifc_destroy_eq_in_bits {
7260 u8 opcode[0x10];
b4ff3a36 7261 u8 reserved_at_10[0x10];
e281682b 7262
b4ff3a36 7263 u8 reserved_at_20[0x10];
e281682b
SM		 7264 u8 op_mod[0x10];
7265
b4ff3a36 7266 u8 reserved_at_40[0x18];
e281682b
SM		 7267 u8 eq_number[0x8];
7268
b4ff3a36 7269 u8 reserved_at_60[0x20];
e281682b
SM		 7270};
7271
7272struct mlx5_ifc_destroy_dct_out_bits {
7273 u8 status[0x8];
b4ff3a36 7274 u8 reserved_at_8[0x18];
e281682b
SM		 7275
7276 u8 syndrome[0x20];
7277
b4ff3a36 7278 u8 reserved_at_40[0x40];
e281682b
SM		 7279};
7280
7281struct mlx5_ifc_destroy_dct_in_bits {
7282 u8 opcode[0x10];
774ea6ee 7283 u8 uid[0x10];
e281682b 7284
b4ff3a36 7285 u8 reserved_at_20[0x10];
e281682b
SM		 7286 u8 op_mod[0x10];
7287
b4ff3a36 7288 u8 reserved_at_40[0x8];
e281682b
SM		 7289 u8 dctn[0x18];
7290
b4ff3a36 7291 u8 reserved_at_60[0x20];
e281682b
SM		 7292};
7293
7294struct mlx5_ifc_destroy_cq_out_bits {
7295 u8 status[0x8];
b4ff3a36 7296 u8 reserved_at_8[0x18];
e281682b
SM		 7297
7298 u8 syndrome[0x20];
7299
b4ff3a36 7300 u8 reserved_at_40[0x40];
e281682b
SM		 7301};
7302
7303struct mlx5_ifc_destroy_cq_in_bits {
7304 u8 opcode[0x10];
9ba481e2 7305 u8 uid[0x10];
e281682b 7306
b4ff3a36 7307 u8 reserved_at_20[0x10];
e281682b
SM		 7308 u8 op_mod[0x10];
7309
b4ff3a36 7310 u8 reserved_at_40[0x8];
e281682b
SM		 7311 u8 cqn[0x18];
7312
b4ff3a36 7313 u8 reserved_at_60[0x20];
e281682b
SM		 7314};
7315
7316struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7317 u8 status[0x8];
b4ff3a36 7318 u8 reserved_at_8[0x18];
e281682b
SM		 7319
7320 u8 syndrome[0x20];
7321
b4ff3a36 7322 u8 reserved_at_40[0x40];
e281682b
SM		 7323};
7324
7325struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7326 u8 opcode[0x10];
b4ff3a36 7327 u8 reserved_at_10[0x10];
e281682b 7328
b4ff3a36 7329 u8 reserved_at_20[0x10];
e281682b
SM		 7330 u8 op_mod[0x10];
7331
b4ff3a36 7332 u8 reserved_at_40[0x20];
e281682b 7333
b4ff3a36 7334 u8 reserved_at_60[0x10];
e281682b
SM		 7335 u8 vxlan_udp_port[0x10];
7336};
7337
7338struct mlx5_ifc_delete_l2_table_entry_out_bits {
7339 u8 status[0x8];
b4ff3a36 7340 u8 reserved_at_8[0x18];
e281682b
SM		 7341
7342 u8 syndrome[0x20];
7343
b4ff3a36 7344 u8 reserved_at_40[0x40];
e281682b
SM		 7345};
7346
7347struct mlx5_ifc_delete_l2_table_entry_in_bits {
7348 u8 opcode[0x10];
b4ff3a36 7349 u8 reserved_at_10[0x10];
e281682b 7350
b4ff3a36 7351 u8 reserved_at_20[0x10];
e281682b
SM		 7352 u8 op_mod[0x10];
7353
b4ff3a36 7354 u8 reserved_at_40[0x60];
e281682b 7355
b4ff3a36 7356 u8 reserved_at_a0[0x8];
e281682b
SM		 7357 u8 table_index[0x18];
7358
b4ff3a36 7359 u8 reserved_at_c0[0x140];
e281682b
SM		 7360};
7361
7362struct mlx5_ifc_delete_fte_out_bits {
7363 u8 status[0x8];
b4ff3a36 7364 u8 reserved_at_8[0x18];
e281682b
SM		 7365
7366 u8 syndrome[0x20];
7367
b4ff3a36 7368 u8 reserved_at_40[0x40];
e281682b
SM		 7369};
7370
7371struct mlx5_ifc_delete_fte_in_bits {
7372 u8 opcode[0x10];
b4ff3a36 7373 u8 reserved_at_10[0x10];
e281682b 7374
b4ff3a36 7375 u8 reserved_at_20[0x10];
e281682b
SM		 7376 u8 op_mod[0x10];
7377
7d5e1423
SM		 7378 u8 other_vport[0x1];
7379 u8 reserved_at_41[0xf];
7380 u8 vport_number[0x10];
7381
7382 u8 reserved_at_60[0x20];
e281682b
SM		 7383
7384 u8 table_type[0x8];
b4ff3a36 7385 u8 reserved_at_88[0x18];
e281682b 7386
b4ff3a36 7387 u8 reserved_at_a0[0x8];
e281682b
SM		 7388 u8 table_id[0x18];
7389
b4ff3a36 7390 u8 reserved_at_c0[0x40];
e281682b
SM		 7391
7392 u8 flow_index[0x20];
7393
b4ff3a36 7394 u8 reserved_at_120[0xe0];
e281682b
SM		 7395};
7396
7397struct mlx5_ifc_dealloc_xrcd_out_bits {
7398 u8 status[0x8];
b4ff3a36 7399 u8 reserved_at_8[0x18];
e281682b
SM		 7400
7401 u8 syndrome[0x20];
7402
b4ff3a36 7403 u8 reserved_at_40[0x40];
e281682b
SM		 7404};
7405
7406struct mlx5_ifc_dealloc_xrcd_in_bits {
7407 u8 opcode[0x10];
bd371975 7408 u8 uid[0x10];
e281682b 7409
b4ff3a36 7410 u8 reserved_at_20[0x10];
e281682b
SM		 7411 u8 op_mod[0x10];
7412
b4ff3a36 7413 u8 reserved_at_40[0x8];
e281682b
SM		 7414 u8 xrcd[0x18];
7415
b4ff3a36 7416 u8 reserved_at_60[0x20];
e281682b
SM		 7417};
7418
7419struct mlx5_ifc_dealloc_uar_out_bits {
7420 u8 status[0x8];
b4ff3a36 7421 u8 reserved_at_8[0x18];
e281682b
SM		 7422
7423 u8 syndrome[0x20];
7424
b4ff3a36 7425 u8 reserved_at_40[0x40];
e281682b
SM		 7426};
7427
7428struct mlx5_ifc_dealloc_uar_in_bits {
7429 u8 opcode[0x10];
b4ff3a36 7430 u8 reserved_at_10[0x10];
e281682b 7431
b4ff3a36 7432 u8 reserved_at_20[0x10];
e281682b
SM		 7433 u8 op_mod[0x10];
7434
b4ff3a36 7435 u8 reserved_at_40[0x8];
e281682b
SM		 7436 u8 uar[0x18];
7437
b4ff3a36 7438 u8 reserved_at_60[0x20];
e281682b
SM		 7439};
7440
7441struct mlx5_ifc_dealloc_transport_domain_out_bits {
7442 u8 status[0x8];
b4ff3a36 7443 u8 reserved_at_8[0x18];
e281682b
SM		 7444
7445 u8 syndrome[0x20];
7446
b4ff3a36 7447 u8 reserved_at_40[0x40];
e281682b
SM		 7448};
7449
7450struct mlx5_ifc_dealloc_transport_domain_in_bits {
7451 u8 opcode[0x10];
71bef2fd 7452 u8 uid[0x10];
e281682b 7453
b4ff3a36 7454 u8 reserved_at_20[0x10];
e281682b
SM		 7455 u8 op_mod[0x10];
7456
b4ff3a36 7457 u8 reserved_at_40[0x8];
e281682b
SM		 7458 u8 transport_domain[0x18];
7459
b4ff3a36 7460 u8 reserved_at_60[0x20];
e281682b
SM		 7461};
7462
7463struct mlx5_ifc_dealloc_q_counter_out_bits {
7464 u8 status[0x8];
b4ff3a36 7465 u8 reserved_at_8[0x18];
e281682b
SM		 7466
7467 u8 syndrome[0x20];
7468
b4ff3a36 7469 u8 reserved_at_40[0x40];
e281682b
SM		 7470};
7471
7472struct mlx5_ifc_dealloc_q_counter_in_bits {
7473 u8 opcode[0x10];
b4ff3a36 7474 u8 reserved_at_10[0x10];
e281682b 7475
b4ff3a36 7476 u8 reserved_at_20[0x10];
e281682b
SM		 7477 u8 op_mod[0x10];
7478
b4ff3a36 7479 u8 reserved_at_40[0x18];
e281682b
SM		 7480 u8 counter_set_id[0x8];
7481
b4ff3a36 7482 u8 reserved_at_60[0x20];
e281682b
SM		 7483};
7484
7485struct mlx5_ifc_dealloc_pd_out_bits {
7486 u8 status[0x8];
b4ff3a36 7487 u8 reserved_at_8[0x18];
e281682b
SM		 7488
7489 u8 syndrome[0x20];
7490
b4ff3a36 7491 u8 reserved_at_40[0x40];
e281682b
SM		 7492};
7493
7494struct mlx5_ifc_dealloc_pd_in_bits {
7495 u8 opcode[0x10];
bd371975 7496 u8 uid[0x10];
e281682b 7497
b4ff3a36 7498 u8 reserved_at_20[0x10];
e281682b
SM		 7499 u8 op_mod[0x10];
7500
b4ff3a36 7501 u8 reserved_at_40[0x8];
e281682b
SM		 7502 u8 pd[0x18];
7503
b4ff3a36 7504 u8 reserved_at_60[0x20];
e281682b
SM		 7505};
7506
9dc0b289
AV		 7507struct mlx5_ifc_dealloc_flow_counter_out_bits {
7508 u8 status[0x8];
7509 u8 reserved_at_8[0x18];
7510
7511 u8 syndrome[0x20];
7512
7513 u8 reserved_at_40[0x40];
7514};
7515
7516struct mlx5_ifc_dealloc_flow_counter_in_bits {
7517 u8 opcode[0x10];
7518 u8 reserved_at_10[0x10];
7519
7520 u8 reserved_at_20[0x10];
7521 u8 op_mod[0x10];
7522
a8ffcc74 7523 u8 flow_counter_id[0x20];
9dc0b289
AV		 7524
7525 u8 reserved_at_60[0x20];
7526};
7527
7486216b
SM		 7528struct mlx5_ifc_create_xrq_out_bits {
7529 u8 status[0x8];
7530 u8 reserved_at_8[0x18];
7531
7532 u8 syndrome[0x20];
7533
7534 u8 reserved_at_40[0x8];
7535 u8 xrqn[0x18];
7536
7537 u8 reserved_at_60[0x20];
7538};
7539
7540struct mlx5_ifc_create_xrq_in_bits {
7541 u8 opcode[0x10];
a0d8c054 7542 u8 uid[0x10];
7486216b
SM		 7543
7544 u8 reserved_at_20[0x10];
7545 u8 op_mod[0x10];
7546
7547 u8 reserved_at_40[0x40];
7548
7549 struct mlx5_ifc_xrqc_bits xrq_context;
7550};
7551
e281682b
SM		 7552struct mlx5_ifc_create_xrc_srq_out_bits {
7553 u8 status[0x8];
b4ff3a36 7554 u8 reserved_at_8[0x18];
e281682b
SM		 7555
7556 u8 syndrome[0x20];
7557
b4ff3a36 7558 u8 reserved_at_40[0x8];
e281682b
SM		 7559 u8 xrc_srqn[0x18];
7560
b4ff3a36 7561 u8 reserved_at_60[0x20];
e281682b
SM		 7562};
7563
7564struct mlx5_ifc_create_xrc_srq_in_bits {
7565 u8 opcode[0x10];
a0d8c054 7566 u8 uid[0x10];
e281682b 7567
b4ff3a36 7568 u8 reserved_at_20[0x10];
e281682b
SM		 7569 u8 op_mod[0x10];
7570
b4ff3a36 7571 u8 reserved_at_40[0x40];
e281682b
SM		 7572
7573 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7574
99b77fef
YH		 7575 u8 reserved_at_280[0x60];
7576
bd371975 7577 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 7578 u8 reserved_at_2e1[0x1f];
7579
7580 u8 reserved_at_300[0x580];
e281682b 7581
b6ca09cb 7582 u8 pas[][0x40];
e281682b
SM		 7583};
7584
7585struct mlx5_ifc_create_tis_out_bits {
7586 u8 status[0x8];
b4ff3a36 7587 u8 reserved_at_8[0x18];
e281682b
SM		 7588
7589 u8 syndrome[0x20];
7590
b4ff3a36 7591 u8 reserved_at_40[0x8];
e281682b
SM		 7592 u8 tisn[0x18];
7593
b4ff3a36 7594 u8 reserved_at_60[0x20];
e281682b
SM		 7595};
7596
7597struct mlx5_ifc_create_tis_in_bits {
7598 u8 opcode[0x10];
bd371975 7599 u8 uid[0x10];
e281682b 7600
b4ff3a36 7601 u8 reserved_at_20[0x10];
e281682b
SM		 7602 u8 op_mod[0x10];
7603
b4ff3a36 7604 u8 reserved_at_40[0xc0];
e281682b
SM		 7605
7606 struct mlx5_ifc_tisc_bits ctx;
7607};
7608
7609struct mlx5_ifc_create_tir_out_bits {
7610 u8 status[0x8];
3e070470 7611 u8 icm_address_63_40[0x18];
e281682b
SM		 7612
7613 u8 syndrome[0x20];
7614
3e070470 7615 u8 icm_address_39_32[0x8];
e281682b
SM		 7616 u8 tirn[0x18];
7617
3e070470 7618 u8 icm_address_31_0[0x20];
e281682b
SM		 7619};
7620
7621struct mlx5_ifc_create_tir_in_bits {
7622 u8 opcode[0x10];
bd371975 7623 u8 uid[0x10];
e281682b 7624
b4ff3a36 7625 u8 reserved_at_20[0x10];
e281682b
SM		 7626 u8 op_mod[0x10];
7627
b4ff3a36 7628 u8 reserved_at_40[0xc0];
e281682b
SM		 7629
7630 struct mlx5_ifc_tirc_bits ctx;
7631};
7632
7633struct mlx5_ifc_create_srq_out_bits {
7634 u8 status[0x8];
b4ff3a36 7635 u8 reserved_at_8[0x18];
e281682b
SM		 7636
7637 u8 syndrome[0x20];
7638
b4ff3a36 7639 u8 reserved_at_40[0x8];
e281682b
SM		 7640 u8 srqn[0x18];
7641
b4ff3a36 7642 u8 reserved_at_60[0x20];
e281682b
SM		 7643};
7644
7645struct mlx5_ifc_create_srq_in_bits {
7646 u8 opcode[0x10];
a0d8c054 7647 u8 uid[0x10];
e281682b 7648
b4ff3a36 7649 u8 reserved_at_20[0x10];
e281682b
SM		 7650 u8 op_mod[0x10];
7651
b4ff3a36 7652 u8 reserved_at_40[0x40];
e281682b
SM		 7653
7654 struct mlx5_ifc_srqc_bits srq_context_entry;
7655
b4ff3a36 7656 u8 reserved_at_280[0x600];
e281682b 7657
b6ca09cb 7658 u8 pas[][0x40];
e281682b
SM		 7659};
7660
7661struct mlx5_ifc_create_sq_out_bits {
7662 u8 status[0x8];
b4ff3a36 7663 u8 reserved_at_8[0x18];
e281682b
SM		 7664
7665 u8 syndrome[0x20];
7666
b4ff3a36 7667 u8 reserved_at_40[0x8];
e281682b
SM		 7668 u8 sqn[0x18];
7669
b4ff3a36 7670 u8 reserved_at_60[0x20];
e281682b
SM		 7671};
7672
7673struct mlx5_ifc_create_sq_in_bits {
7674 u8 opcode[0x10];
430ae0d5 7675 u8 uid[0x10];
e281682b 7676
b4ff3a36 7677 u8 reserved_at_20[0x10];
e281682b
SM		 7678 u8 op_mod[0x10];
7679
b4ff3a36 7680 u8 reserved_at_40[0xc0];
e281682b
SM		 7681
7682 struct mlx5_ifc_sqc_bits ctx;
7683};
7684
813f8540
MHY		 7685struct mlx5_ifc_create_scheduling_element_out_bits {
7686 u8 status[0x8];
7687 u8 reserved_at_8[0x18];
7688
7689 u8 syndrome[0x20];
7690
7691 u8 reserved_at_40[0x40];
7692
7693 u8 scheduling_element_id[0x20];
7694
7695 u8 reserved_at_a0[0x160];
7696};
7697
7698struct mlx5_ifc_create_scheduling_element_in_bits {
7699 u8 opcode[0x10];
7700 u8 reserved_at_10[0x10];
7701
7702 u8 reserved_at_20[0x10];
7703 u8 op_mod[0x10];
7704
7705 u8 scheduling_hierarchy[0x8];
7706 u8 reserved_at_48[0x18];
7707
7708 u8 reserved_at_60[0xa0];
7709
7710 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7711
7712 u8 reserved_at_300[0x100];
7713};
7714
e281682b
SM		 7715struct mlx5_ifc_create_rqt_out_bits {
7716 u8 status[0x8];
b4ff3a36 7717 u8 reserved_at_8[0x18];
e281682b
SM		 7718
7719 u8 syndrome[0x20];
7720
b4ff3a36 7721 u8 reserved_at_40[0x8];
e281682b
SM		 7722 u8 rqtn[0x18];
7723
b4ff3a36 7724 u8 reserved_at_60[0x20];
e281682b
SM		 7725};
7726
7727struct mlx5_ifc_create_rqt_in_bits {
7728 u8 opcode[0x10];
bd371975 7729 u8 uid[0x10];
e281682b 7730
b4ff3a36 7731 u8 reserved_at_20[0x10];
e281682b
SM		 7732 u8 op_mod[0x10];
7733
b4ff3a36 7734 u8 reserved_at_40[0xc0];
e281682b
SM		 7735
7736 struct mlx5_ifc_rqtc_bits rqt_context;
7737};
7738
7739struct mlx5_ifc_create_rq_out_bits {
7740 u8 status[0x8];
b4ff3a36 7741 u8 reserved_at_8[0x18];
e281682b
SM		 7742
7743 u8 syndrome[0x20];
7744
b4ff3a36 7745 u8 reserved_at_40[0x8];
e281682b
SM		 7746 u8 rqn[0x18];
7747
b4ff3a36 7748 u8 reserved_at_60[0x20];
e281682b
SM		 7749};
7750
7751struct mlx5_ifc_create_rq_in_bits {
7752 u8 opcode[0x10];
d269b3af 7753 u8 uid[0x10];
e281682b 7754
b4ff3a36 7755 u8 reserved_at_20[0x10];
e281682b
SM		 7756 u8 op_mod[0x10];
7757
b4ff3a36 7758 u8 reserved_at_40[0xc0];
e281682b
SM		 7759
7760 struct mlx5_ifc_rqc_bits ctx;
7761};
7762
7763struct mlx5_ifc_create_rmp_out_bits {
7764 u8 status[0x8];
b4ff3a36 7765 u8 reserved_at_8[0x18];
e281682b
SM		 7766
7767 u8 syndrome[0x20];
7768
b4ff3a36 7769 u8 reserved_at_40[0x8];
e281682b
SM		 7770 u8 rmpn[0x18];
7771
b4ff3a36 7772 u8 reserved_at_60[0x20];
e281682b
SM		 7773};
7774
7775struct mlx5_ifc_create_rmp_in_bits {
7776 u8 opcode[0x10];
a0d8c054 7777 u8 uid[0x10];
e281682b 7778
b4ff3a36 7779 u8 reserved_at_20[0x10];
e281682b
SM		 7780 u8 op_mod[0x10];
7781
b4ff3a36 7782 u8 reserved_at_40[0xc0];
e281682b
SM		 7783
7784 struct mlx5_ifc_rmpc_bits ctx;
7785};
7786
7787struct mlx5_ifc_create_qp_out_bits {
7788 u8 status[0x8];
b4ff3a36 7789 u8 reserved_at_8[0x18];
e281682b
SM		 7790
7791 u8 syndrome[0x20];
7792
b4ff3a36 7793 u8 reserved_at_40[0x8];
e281682b
SM		 7794 u8 qpn[0x18];
7795
6b646a7e 7796 u8 ece[0x20];
e281682b
SM		 7797};
7798
7799struct mlx5_ifc_create_qp_in_bits {
7800 u8 opcode[0x10];
4ac63ec7 7801 u8 uid[0x10];
e281682b 7802
b4ff3a36 7803 u8 reserved_at_20[0x10];
e281682b
SM		 7804 u8 op_mod[0x10];
7805
4dca6509
MG		 7806 u8 reserved_at_40[0x8];
7807 u8 input_qpn[0x18];
e281682b 7808
4dca6509 7809 u8 reserved_at_60[0x20];
e281682b
SM		 7810 u8 opt_param_mask[0x20];
7811
6b646a7e 7812 u8 ece[0x20];
e281682b
SM		 7813
7814 struct mlx5_ifc_qpc_bits qpc;
7815
bd371975
LR		 7816 u8 reserved_at_800[0x60];
7817
7818 u8 wq_umem_valid[0x1];
7819 u8 reserved_at_861[0x1f];
e281682b 7820
b6ca09cb 7821 u8 pas[][0x40];
e281682b
SM		 7822};
7823
7824struct mlx5_ifc_create_psv_out_bits {
7825 u8 status[0x8];
b4ff3a36 7826 u8 reserved_at_8[0x18];
e281682b
SM		 7827
7828 u8 syndrome[0x20];
7829
b4ff3a36 7830 u8 reserved_at_40[0x40];
e281682b 7831
b4ff3a36 7832 u8 reserved_at_80[0x8];
e281682b
SM		 7833 u8 psv0_index[0x18];
7834
b4ff3a36 7835 u8 reserved_at_a0[0x8];
e281682b
SM		 7836 u8 psv1_index[0x18];
7837
b4ff3a36 7838 u8 reserved_at_c0[0x8];
e281682b
SM		 7839 u8 psv2_index[0x18];
7840
b4ff3a36 7841 u8 reserved_at_e0[0x8];
e281682b
SM		 7842 u8 psv3_index[0x18];
7843};
7844
7845struct mlx5_ifc_create_psv_in_bits {
7846 u8 opcode[0x10];
b4ff3a36 7847 u8 reserved_at_10[0x10];
e281682b 7848
b4ff3a36 7849 u8 reserved_at_20[0x10];
e281682b
SM		 7850 u8 op_mod[0x10];
7851
7852 u8 num_psv[0x4];
b4ff3a36 7853 u8 reserved_at_44[0x4];
e281682b
SM		 7854 u8 pd[0x18];
7855
b4ff3a36 7856 u8 reserved_at_60[0x20];
e281682b
SM		 7857};
7858
7859struct mlx5_ifc_create_mkey_out_bits {
7860 u8 status[0x8];
b4ff3a36 7861 u8 reserved_at_8[0x18];
e281682b
SM		 7862
7863 u8 syndrome[0x20];
7864
b4ff3a36 7865 u8 reserved_at_40[0x8];
e281682b
SM		 7866 u8 mkey_index[0x18];
7867
b4ff3a36 7868 u8 reserved_at_60[0x20];
e281682b
SM		 7869};
7870
7871struct mlx5_ifc_create_mkey_in_bits {
7872 u8 opcode[0x10];
8a06a79b 7873 u8 uid[0x10];
e281682b 7874
b4ff3a36 7875 u8 reserved_at_20[0x10];
e281682b
SM		 7876 u8 op_mod[0x10];
7877
b4ff3a36 7878 u8 reserved_at_40[0x20];
e281682b
SM		 7879
7880 u8 pg_access[0x1];
bd371975
LR		 7881 u8 mkey_umem_valid[0x1];
7882 u8 reserved_at_62[0x1e];
e281682b
SM		 7883
7884 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7885
b4ff3a36 7886 u8 reserved_at_280[0x80];
e281682b
SM		 7887
7888 u8 translations_octword_actual_size[0x20];
7889
b4ff3a36 7890 u8 reserved_at_320[0x560];
e281682b 7891
b6ca09cb 7892 u8 klm_pas_mtt[][0x20];
e281682b
SM		 7893};
7894
97b5484e
AV		 7895enum {
7896 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7897 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7898 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7899 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7900 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7901 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7902 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7903};
7904
e281682b
SM		 7905struct mlx5_ifc_create_flow_table_out_bits {
7906 u8 status[0x8];
97b5484e 7907 u8 icm_address_63_40[0x18];
e281682b
SM		 7908
7909 u8 syndrome[0x20];
7910
97b5484e 7911 u8 icm_address_39_32[0x8];
e281682b
SM		 7912 u8 table_id[0x18];
7913
97b5484e 7914 u8 icm_address_31_0[0x20];
0c90e9c6
MG		 7915};
7916
e281682b
SM		 7917struct mlx5_ifc_create_flow_table_in_bits {
7918 u8 opcode[0x10];
b4ff3a36 7919 u8 reserved_at_10[0x10];
e281682b 7920
b4ff3a36 7921 u8 reserved_at_20[0x10];
e281682b
SM		 7922 u8 op_mod[0x10];
7923
7d5e1423
SM		 7924 u8 other_vport[0x1];
7925 u8 reserved_at_41[0xf];
7926 u8 vport_number[0x10];
7927
7928 u8 reserved_at_60[0x20];
e281682b
SM		 7929
7930 u8 table_type[0x8];
b4ff3a36 7931 u8 reserved_at_88[0x18];
e281682b 7932
b4ff3a36 7933 u8 reserved_at_a0[0x20];
e281682b 7934
0c90e9c6 7935 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 7936};
7937
7938struct mlx5_ifc_create_flow_group_out_bits {
7939 u8 status[0x8];
b4ff3a36 7940 u8 reserved_at_8[0x18];
e281682b
SM		 7941
7942 u8 syndrome[0x20];
7943
b4ff3a36 7944 u8 reserved_at_40[0x8];
e281682b
SM		 7945 u8 group_id[0x18];
7946
b4ff3a36 7947 u8 reserved_at_60[0x20];
e281682b
SM		 7948};
7949
7950enum {
71c6e863
AL		 7951 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7952 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7953 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7954 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 7955};
7956
7957struct mlx5_ifc_create_flow_group_in_bits {
7958 u8 opcode[0x10];
b4ff3a36 7959 u8 reserved_at_10[0x10];
e281682b 7960
b4ff3a36 7961 u8 reserved_at_20[0x10];
e281682b
SM		 7962 u8 op_mod[0x10];
7963
7d5e1423
SM		 7964 u8 other_vport[0x1];
7965 u8 reserved_at_41[0xf];
7966 u8 vport_number[0x10];
7967
7968 u8 reserved_at_60[0x20];
e281682b
SM		 7969
7970 u8 table_type[0x8];
b4ff3a36 7971 u8 reserved_at_88[0x18];
e281682b 7972
b4ff3a36 7973 u8 reserved_at_a0[0x8];
e281682b
SM		 7974 u8 table_id[0x18];
7975
3e99df87
SK		 7976 u8 source_eswitch_owner_vhca_id_valid[0x1];
7977
7978 u8 reserved_at_c1[0x1f];
e281682b
SM		 7979
7980 u8 start_flow_index[0x20];
7981
b4ff3a36 7982 u8 reserved_at_100[0x20];
e281682b
SM		 7983
7984 u8 end_flow_index[0x20];
7985
b4ff3a36 7986 u8 reserved_at_140[0xa0];
e281682b 7987
b4ff3a36 7988 u8 reserved_at_1e0[0x18];
e281682b
SM		 7989 u8 match_criteria_enable[0x8];
7990
7991 struct mlx5_ifc_fte_match_param_bits match_criteria;
7992
b4ff3a36 7993 u8 reserved_at_1200[0xe00];
e281682b
SM		 7994};
7995
7996struct mlx5_ifc_create_eq_out_bits {
7997 u8 status[0x8];
b4ff3a36 7998 u8 reserved_at_8[0x18];
e281682b
SM		 7999
8000 u8 syndrome[0x20];
8001
b4ff3a36 8002 u8 reserved_at_40[0x18];
e281682b
SM		 8003 u8 eq_number[0x8];
8004
b4ff3a36 8005 u8 reserved_at_60[0x20];
e281682b
SM		 8006};
8007
8008struct mlx5_ifc_create_eq_in_bits {
8009 u8 opcode[0x10];
c191f934 8010 u8 uid[0x10];
e281682b 8011
b4ff3a36 8012 u8 reserved_at_20[0x10];
e281682b
SM		 8013 u8 op_mod[0x10];
8014
b4ff3a36 8015 u8 reserved_at_40[0x40];
e281682b
SM		 8016
8017 struct mlx5_ifc_eqc_bits eq_context_entry;
8018
b4ff3a36 8019 u8 reserved_at_280[0x40];
e281682b 8020
b9a7ba55 8021 u8 event_bitmask[4][0x40];
e281682b 8022
b9a7ba55 8023 u8 reserved_at_3c0[0x4c0];
e281682b 8024
b6ca09cb 8025 u8 pas[][0x40];
e281682b
SM		 8026};
8027
8028struct mlx5_ifc_create_dct_out_bits {
8029 u8 status[0x8];
b4ff3a36 8030 u8 reserved_at_8[0x18];
e281682b
SM		 8031
8032 u8 syndrome[0x20];
8033
b4ff3a36 8034 u8 reserved_at_40[0x8];
e281682b
SM		 8035 u8 dctn[0x18];
8036
a645a89d 8037 u8 ece[0x20];
e281682b
SM		 8038};
8039
8040struct mlx5_ifc_create_dct_in_bits {
8041 u8 opcode[0x10];
774ea6ee 8042 u8 uid[0x10];
e281682b 8043
b4ff3a36 8044 u8 reserved_at_20[0x10];
e281682b
SM		 8045 u8 op_mod[0x10];
8046
b4ff3a36 8047 u8 reserved_at_40[0x40];
e281682b
SM		 8048
8049 struct mlx5_ifc_dctc_bits dct_context_entry;
8050
b4ff3a36 8051 u8 reserved_at_280[0x180];
e281682b
SM		 8052};
8053
8054struct mlx5_ifc_create_cq_out_bits {
8055 u8 status[0x8];
b4ff3a36 8056 u8 reserved_at_8[0x18];
e281682b
SM		 8057
8058 u8 syndrome[0x20];
8059
b4ff3a36 8060 u8 reserved_at_40[0x8];
e281682b
SM		 8061 u8 cqn[0x18];
8062
b4ff3a36 8063 u8 reserved_at_60[0x20];
e281682b
SM		 8064};
8065
8066struct mlx5_ifc_create_cq_in_bits {
8067 u8 opcode[0x10];
9ba481e2 8068 u8 uid[0x10];
e281682b 8069
b4ff3a36 8070 u8 reserved_at_20[0x10];
e281682b
SM		 8071 u8 op_mod[0x10];
8072
b4ff3a36 8073 u8 reserved_at_40[0x40];
e281682b
SM		 8074
8075 struct mlx5_ifc_cqc_bits cq_context;
8076
bd371975
LR		 8077 u8 reserved_at_280[0x60];
8078
8079 u8 cq_umem_valid[0x1];
8080 u8 reserved_at_2e1[0x59f];
e281682b 8081
b6ca09cb 8082 u8 pas[][0x40];
e281682b
SM		 8083};
8084
8085struct mlx5_ifc_config_int_moderation_out_bits {
8086 u8 status[0x8];
b4ff3a36 8087 u8 reserved_at_8[0x18];
e281682b
SM		 8088
8089 u8 syndrome[0x20];
8090
b4ff3a36 8091 u8 reserved_at_40[0x4];
e281682b
SM		 8092 u8 min_delay[0xc];
8093 u8 int_vector[0x10];
8094
b4ff3a36 8095 u8 reserved_at_60[0x20];
e281682b
SM		 8096};
8097
8098enum {
8099 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8100 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8101};
8102
8103struct mlx5_ifc_config_int_moderation_in_bits {
8104 u8 opcode[0x10];
b4ff3a36 8105 u8 reserved_at_10[0x10];
e281682b 8106
b4ff3a36 8107 u8 reserved_at_20[0x10];
e281682b
SM		 8108 u8 op_mod[0x10];
8109
b4ff3a36 8110 u8 reserved_at_40[0x4];
e281682b
SM		 8111 u8 min_delay[0xc];
8112 u8 int_vector[0x10];
8113
b4ff3a36 8114 u8 reserved_at_60[0x20];
e281682b
SM		 8115};
8116
8117struct mlx5_ifc_attach_to_mcg_out_bits {
8118 u8 status[0x8];
b4ff3a36 8119 u8 reserved_at_8[0x18];
e281682b
SM		 8120
8121 u8 syndrome[0x20];
8122
b4ff3a36 8123 u8 reserved_at_40[0x40];
e281682b
SM		 8124};
8125
8126struct mlx5_ifc_attach_to_mcg_in_bits {
8127 u8 opcode[0x10];
bd371975 8128 u8 uid[0x10];
e281682b 8129
b4ff3a36 8130 u8 reserved_at_20[0x10];
e281682b
SM		 8131 u8 op_mod[0x10];
8132
b4ff3a36 8133 u8 reserved_at_40[0x8];
e281682b
SM		 8134 u8 qpn[0x18];
8135
b4ff3a36 8136 u8 reserved_at_60[0x20];
e281682b
SM		 8137
8138 u8 multicast_gid[16][0x8];
8139};
8140
7486216b
SM		 8141struct mlx5_ifc_arm_xrq_out_bits {
8142 u8 status[0x8];
8143 u8 reserved_at_8[0x18];
8144
8145 u8 syndrome[0x20];
8146
8147 u8 reserved_at_40[0x40];
8148};
8149
8150struct mlx5_ifc_arm_xrq_in_bits {
8151 u8 opcode[0x10];
8152 u8 reserved_at_10[0x10];
8153
8154 u8 reserved_at_20[0x10];
8155 u8 op_mod[0x10];
8156
8157 u8 reserved_at_40[0x8];
8158 u8 xrqn[0x18];
8159
8160 u8 reserved_at_60[0x10];
8161 u8 lwm[0x10];
8162};
8163
e281682b
SM		 8164struct mlx5_ifc_arm_xrc_srq_out_bits {
8165 u8 status[0x8];
b4ff3a36 8166 u8 reserved_at_8[0x18];
e281682b
SM		 8167
8168 u8 syndrome[0x20];
8169
b4ff3a36 8170 u8 reserved_at_40[0x40];
e281682b
SM		 8171};
8172
8173enum {
8174 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8175};
8176
8177struct mlx5_ifc_arm_xrc_srq_in_bits {
8178 u8 opcode[0x10];
a0d8c054 8179 u8 uid[0x10];
e281682b 8180
b4ff3a36 8181 u8 reserved_at_20[0x10];
e281682b
SM		 8182 u8 op_mod[0x10];
8183
b4ff3a36 8184 u8 reserved_at_40[0x8];
e281682b
SM		 8185 u8 xrc_srqn[0x18];
8186
b4ff3a36 8187 u8 reserved_at_60[0x10];
e281682b
SM		 8188 u8 lwm[0x10];
8189};
8190
8191struct mlx5_ifc_arm_rq_out_bits {
8192 u8 status[0x8];
b4ff3a36 8193 u8 reserved_at_8[0x18];
e281682b
SM		 8194
8195 u8 syndrome[0x20];
8196
b4ff3a36 8197 u8 reserved_at_40[0x40];
e281682b
SM		 8198};
8199
8200enum {
7486216b
SM		 8201 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8202 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 8203};
8204
8205struct mlx5_ifc_arm_rq_in_bits {
8206 u8 opcode[0x10];
a0d8c054 8207 u8 uid[0x10];
e281682b 8208
b4ff3a36 8209 u8 reserved_at_20[0x10];
e281682b
SM		 8210 u8 op_mod[0x10];
8211
b4ff3a36 8212 u8 reserved_at_40[0x8];
e281682b
SM		 8213 u8 srq_number[0x18];
8214
b4ff3a36 8215 u8 reserved_at_60[0x10];
e281682b
SM		 8216 u8 lwm[0x10];
8217};
8218
8219struct mlx5_ifc_arm_dct_out_bits {
8220 u8 status[0x8];
b4ff3a36 8221 u8 reserved_at_8[0x18];
e281682b
SM		 8222
8223 u8 syndrome[0x20];
8224
b4ff3a36 8225 u8 reserved_at_40[0x40];
e281682b
SM		 8226};
8227
8228struct mlx5_ifc_arm_dct_in_bits {
8229 u8 opcode[0x10];
b4ff3a36 8230 u8 reserved_at_10[0x10];
e281682b 8231
b4ff3a36 8232 u8 reserved_at_20[0x10];
e281682b
SM		 8233 u8 op_mod[0x10];
8234
b4ff3a36 8235 u8 reserved_at_40[0x8];
e281682b
SM		 8236 u8 dct_number[0x18];
8237
b4ff3a36 8238 u8 reserved_at_60[0x20];
e281682b
SM		 8239};
8240
8241struct mlx5_ifc_alloc_xrcd_out_bits {
8242 u8 status[0x8];
b4ff3a36 8243 u8 reserved_at_8[0x18];
e281682b
SM		 8244
8245 u8 syndrome[0x20];
8246
b4ff3a36 8247 u8 reserved_at_40[0x8];
e281682b
SM		 8248 u8 xrcd[0x18];
8249
b4ff3a36 8250 u8 reserved_at_60[0x20];
e281682b
SM		 8251};
8252
8253struct mlx5_ifc_alloc_xrcd_in_bits {
8254 u8 opcode[0x10];
bd371975 8255 u8 uid[0x10];
e281682b 8256
b4ff3a36 8257 u8 reserved_at_20[0x10];
e281682b
SM		 8258 u8 op_mod[0x10];
8259
b4ff3a36 8260 u8 reserved_at_40[0x40];
e281682b
SM		 8261};
8262
8263struct mlx5_ifc_alloc_uar_out_bits {
8264 u8 status[0x8];
b4ff3a36 8265 u8 reserved_at_8[0x18];
e281682b
SM		 8266
8267 u8 syndrome[0x20];
8268
b4ff3a36 8269 u8 reserved_at_40[0x8];
e281682b
SM		 8270 u8 uar[0x18];
8271
b4ff3a36 8272 u8 reserved_at_60[0x20];
e281682b
SM		 8273};
8274
8275struct mlx5_ifc_alloc_uar_in_bits {
8276 u8 opcode[0x10];
b4ff3a36 8277 u8 reserved_at_10[0x10];
e281682b 8278
b4ff3a36 8279 u8 reserved_at_20[0x10];
e281682b
SM		 8280 u8 op_mod[0x10];
8281
b4ff3a36 8282 u8 reserved_at_40[0x40];
e281682b
SM		 8283};
8284
8285struct mlx5_ifc_alloc_transport_domain_out_bits {
8286 u8 status[0x8];
b4ff3a36 8287 u8 reserved_at_8[0x18];
e281682b
SM		 8288
8289 u8 syndrome[0x20];
8290
b4ff3a36 8291 u8 reserved_at_40[0x8];
e281682b
SM		 8292 u8 transport_domain[0x18];
8293
b4ff3a36 8294 u8 reserved_at_60[0x20];
e281682b
SM		 8295};
8296
8297struct mlx5_ifc_alloc_transport_domain_in_bits {
8298 u8 opcode[0x10];
71bef2fd 8299 u8 uid[0x10];
e281682b 8300
b4ff3a36 8301 u8 reserved_at_20[0x10];
e281682b
SM		 8302 u8 op_mod[0x10];
8303
b4ff3a36 8304 u8 reserved_at_40[0x40];
e281682b
SM		 8305};
8306
8307struct mlx5_ifc_alloc_q_counter_out_bits {
8308 u8 status[0x8];
b4ff3a36 8309 u8 reserved_at_8[0x18];
e281682b
SM		 8310
8311 u8 syndrome[0x20];
8312
b4ff3a36 8313 u8 reserved_at_40[0x18];
e281682b
SM		 8314 u8 counter_set_id[0x8];
8315
b4ff3a36 8316 u8 reserved_at_60[0x20];
e281682b
SM		 8317};
8318
8319struct mlx5_ifc_alloc_q_counter_in_bits {
8320 u8 opcode[0x10];
2acc7957 8321 u8 uid[0x10];
e281682b 8322
b4ff3a36 8323 u8 reserved_at_20[0x10];
e281682b
SM		 8324 u8 op_mod[0x10];
8325
b4ff3a36 8326 u8 reserved_at_40[0x40];
e281682b
SM		 8327};
8328
8329struct mlx5_ifc_alloc_pd_out_bits {
8330 u8 status[0x8];
b4ff3a36 8331 u8 reserved_at_8[0x18];
e281682b
SM		 8332
8333 u8 syndrome[0x20];
8334
b4ff3a36 8335 u8 reserved_at_40[0x8];
e281682b
SM		 8336 u8 pd[0x18];
8337
b4ff3a36 8338 u8 reserved_at_60[0x20];
e281682b
SM		 8339};
8340
8341struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 8342 u8 opcode[0x10];
bd371975 8343 u8 uid[0x10];
9dc0b289
AV		 8344
8345 u8 reserved_at_20[0x10];
8346 u8 op_mod[0x10];
8347
8348 u8 reserved_at_40[0x40];
8349};
8350
8351struct mlx5_ifc_alloc_flow_counter_out_bits {
8352 u8 status[0x8];
8353 u8 reserved_at_8[0x18];
8354
8355 u8 syndrome[0x20];
8356
a8ffcc74 8357 u8 flow_counter_id[0x20];
9dc0b289
AV		 8358
8359 u8 reserved_at_60[0x20];
8360};
8361
8362struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 8363 u8 opcode[0x10];
b4ff3a36 8364 u8 reserved_at_10[0x10];
e281682b 8365
b4ff3a36 8366 u8 reserved_at_20[0x10];
e281682b
SM		 8367 u8 op_mod[0x10];
8368
8536a6bf
GT		 8369 u8 reserved_at_40[0x38];
8370 u8 flow_counter_bulk[0x8];
e281682b
SM		 8371};
8372
8373struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8374 u8 status[0x8];
b4ff3a36 8375 u8 reserved_at_8[0x18];
e281682b
SM		 8376
8377 u8 syndrome[0x20];
8378
b4ff3a36 8379 u8 reserved_at_40[0x40];
e281682b
SM		 8380};
8381
8382struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8383 u8 opcode[0x10];
b4ff3a36 8384 u8 reserved_at_10[0x10];
e281682b 8385
b4ff3a36 8386 u8 reserved_at_20[0x10];
e281682b
SM		 8387 u8 op_mod[0x10];
8388
b4ff3a36 8389 u8 reserved_at_40[0x20];
e281682b 8390
b4ff3a36 8391 u8 reserved_at_60[0x10];
e281682b
SM		 8392 u8 vxlan_udp_port[0x10];
8393};
8394
37e92a9d 8395struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 8396 u8 status[0x8];
8397 u8 reserved_at_8[0x18];
8398
8399 u8 syndrome[0x20];
8400
8401 u8 reserved_at_40[0x40];
8402};
8403
1326034b
YH		 8404struct mlx5_ifc_set_pp_rate_limit_context_bits {
8405 u8 rate_limit[0x20];
8406
8407 u8 burst_upper_bound[0x20];
8408
8409 u8 reserved_at_40[0x10];
8410 u8 typical_packet_size[0x10];
8411
8412 u8 reserved_at_60[0x120];
8413};
8414
37e92a9d 8415struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b 8416 u8 opcode[0x10];
1326034b 8417 u8 uid[0x10];
7486216b
SM		 8418
8419 u8 reserved_at_20[0x10];
8420 u8 op_mod[0x10];
8421
8422 u8 reserved_at_40[0x10];
8423 u8 rate_limit_index[0x10];
8424
8425 u8 reserved_at_60[0x20];
8426
1326034b 8427 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
7486216b
SM		 8428};
8429
e281682b
SM		 8430struct mlx5_ifc_access_register_out_bits {
8431 u8 status[0x8];
b4ff3a36 8432 u8 reserved_at_8[0x18];
e281682b
SM		 8433
8434 u8 syndrome[0x20];
8435
b4ff3a36 8436 u8 reserved_at_40[0x40];
e281682b 8437
b6ca09cb 8438 u8 register_data[][0x20];
e281682b
SM		 8439};
8440
8441enum {
8442 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8443 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8444};
8445
8446struct mlx5_ifc_access_register_in_bits {
8447 u8 opcode[0x10];
b4ff3a36 8448 u8 reserved_at_10[0x10];
e281682b 8449
b4ff3a36 8450 u8 reserved_at_20[0x10];
e281682b
SM		 8451 u8 op_mod[0x10];
8452
b4ff3a36 8453 u8 reserved_at_40[0x10];
e281682b
SM		 8454 u8 register_id[0x10];
8455
8456 u8 argument[0x20];
8457
b6ca09cb 8458 u8 register_data[][0x20];
e281682b
SM		 8459};
8460
8461struct mlx5_ifc_sltp_reg_bits {
8462 u8 status[0x4];
8463 u8 version[0x4];
8464 u8 local_port[0x8];
8465 u8 pnat[0x2];
b4ff3a36 8466 u8 reserved_at_12[0x2];
e281682b 8467 u8 lane[0x4];
b4ff3a36 8468 u8 reserved_at_18[0x8];
e281682b 8469
b4ff3a36 8470 u8 reserved_at_20[0x20];
e281682b 8471
b4ff3a36 8472 u8 reserved_at_40[0x7];
e281682b
SM		 8473 u8 polarity[0x1];
8474 u8 ob_tap0[0x8];
8475 u8 ob_tap1[0x8];
8476 u8 ob_tap2[0x8];
8477
b4ff3a36 8478 u8 reserved_at_60[0xc];
e281682b
SM		 8479 u8 ob_preemp_mode[0x4];
8480 u8 ob_reg[0x8];
8481 u8 ob_bias[0x8];
8482
b4ff3a36 8483 u8 reserved_at_80[0x20];
e281682b
SM		 8484};
8485
8486struct mlx5_ifc_slrg_reg_bits {
8487 u8 status[0x4];
8488 u8 version[0x4];
8489 u8 local_port[0x8];
8490 u8 pnat[0x2];
b4ff3a36 8491 u8 reserved_at_12[0x2];
e281682b 8492 u8 lane[0x4];
b4ff3a36 8493 u8 reserved_at_18[0x8];
e281682b
SM		 8494
8495 u8 time_to_link_up[0x10];
b4ff3a36 8496 u8 reserved_at_30[0xc];
e281682b
SM		 8497 u8 grade_lane_speed[0x4];
8498
8499 u8 grade_version[0x8];
8500 u8 grade[0x18];
8501
b4ff3a36 8502 u8 reserved_at_60[0x4];
e281682b
SM		 8503 u8 height_grade_type[0x4];
8504 u8 height_grade[0x18];
8505
8506 u8 height_dz[0x10];
8507 u8 height_dv[0x10];
8508
b4ff3a36 8509 u8 reserved_at_a0[0x10];
e281682b
SM		 8510 u8 height_sigma[0x10];
8511
b4ff3a36 8512 u8 reserved_at_c0[0x20];
e281682b 8513
b4ff3a36 8514 u8 reserved_at_e0[0x4];
e281682b
SM		 8515 u8 phase_grade_type[0x4];
8516 u8 phase_grade[0x18];
8517
b4ff3a36 8518 u8 reserved_at_100[0x8];
e281682b 8519 u8 phase_eo_pos[0x8];
b4ff3a36 8520 u8 reserved_at_110[0x8];
e281682b
SM		 8521 u8 phase_eo_neg[0x8];
8522
8523 u8 ffe_set_tested[0x10];
8524 u8 test_errors_per_lane[0x10];
8525};
8526
8527struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 8528 u8 reserved_at_0[0x8];
e281682b 8529 u8 local_port[0x8];
b4ff3a36 8530 u8 reserved_at_10[0x10];
e281682b 8531
b4ff3a36 8532 u8 reserved_at_20[0x1c];
e281682b
SM		 8533 u8 vl_hw_cap[0x4];
8534
b4ff3a36 8535 u8 reserved_at_40[0x1c];
e281682b
SM		 8536 u8 vl_admin[0x4];
8537
b4ff3a36 8538 u8 reserved_at_60[0x1c];
e281682b
SM		 8539 u8 vl_operational[0x4];
8540};
8541
8542struct mlx5_ifc_pude_reg_bits {
8543 u8 swid[0x8];
8544 u8 local_port[0x8];
b4ff3a36 8545 u8 reserved_at_10[0x4];
e281682b 8546 u8 admin_status[0x4];
b4ff3a36 8547 u8 reserved_at_18[0x4];
e281682b
SM		 8548 u8 oper_status[0x4];
8549
b4ff3a36 8550 u8 reserved_at_20[0x60];
e281682b
SM		 8551};
8552
8553struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 8554 u8 reserved_at_0[0x1];
7486216b 8555 u8 an_disable_admin[0x1];
e7e31ca4
BW		 8556 u8 an_disable_cap[0x1];
8557 u8 reserved_at_3[0x5];
e281682b 8558 u8 local_port[0x8];
b4ff3a36 8559 u8 reserved_at_10[0xd];
e281682b
SM		 8560 u8 proto_mask[0x3];
8561
7486216b 8562 u8 an_status[0x4];
dc392fc5
MB		 8563 u8 reserved_at_24[0xc];
8564 u8 data_rate_oper[0x10];
a0a89989
AL		 8565
8566 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 8567
8568 u8 eth_proto_capability[0x20];
8569
8570 u8 ib_link_width_capability[0x10];
8571 u8 ib_proto_capability[0x10];
8572
a0a89989 8573 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 8574
8575 u8 eth_proto_admin[0x20];
8576
8577 u8 ib_link_width_admin[0x10];
8578 u8 ib_proto_admin[0x10];
8579
a0a89989 8580 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 8581
8582 u8 eth_proto_oper[0x20];
8583
8584 u8 ib_link_width_oper[0x10];
8585 u8 ib_proto_oper[0x10];
8586
5b4793f8
EBE		 8587 u8 reserved_at_160[0x1c];
8588 u8 connector_type[0x4];
e281682b
SM		 8589
8590 u8 eth_proto_lp_advertise[0x20];
8591
b4ff3a36 8592 u8 reserved_at_1a0[0x60];
e281682b
SM		 8593};
8594
7d5e1423
SM		 8595struct mlx5_ifc_mlcr_reg_bits {
8596 u8 reserved_at_0[0x8];
8597 u8 local_port[0x8];
8598 u8 reserved_at_10[0x20];
8599
8600 u8 beacon_duration[0x10];
8601 u8 reserved_at_40[0x10];
8602
8603 u8 beacon_remain[0x10];
8604};
8605
e281682b 8606struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 8607 u8 reserved_at_0[0x20];
e281682b
SM		 8608
8609 u8 algorithm_options[0x10];
b4ff3a36 8610 u8 reserved_at_30[0x4];
e281682b
SM		 8611 u8 repetitions_mode[0x4];
8612 u8 num_of_repetitions[0x8];
8613
8614 u8 grade_version[0x8];
8615 u8 height_grade_type[0x4];
8616 u8 phase_grade_type[0x4];
8617 u8 height_grade_weight[0x8];
8618 u8 phase_grade_weight[0x8];
8619
8620 u8 gisim_measure_bits[0x10];
8621 u8 adaptive_tap_measure_bits[0x10];
8622
8623 u8 ber_bath_high_error_threshold[0x10];
8624 u8 ber_bath_mid_error_threshold[0x10];
8625
8626 u8 ber_bath_low_error_threshold[0x10];
8627 u8 one_ratio_high_threshold[0x10];
8628
8629 u8 one_ratio_high_mid_threshold[0x10];
8630 u8 one_ratio_low_mid_threshold[0x10];
8631
8632 u8 one_ratio_low_threshold[0x10];
8633 u8 ndeo_error_threshold[0x10];
8634
8635 u8 mixer_offset_step_size[0x10];
b4ff3a36 8636 u8 reserved_at_110[0x8];
e281682b
SM		 8637 u8 mix90_phase_for_voltage_bath[0x8];
8638
8639 u8 mixer_offset_start[0x10];
8640 u8 mixer_offset_end[0x10];
8641
b4ff3a36 8642 u8 reserved_at_140[0x15];
e281682b
SM		 8643 u8 ber_test_time[0xb];
8644};
8645
8646struct mlx5_ifc_pspa_reg_bits {
8647 u8 swid[0x8];
8648 u8 local_port[0x8];
8649 u8 sub_port[0x8];
b4ff3a36 8650 u8 reserved_at_18[0x8];
e281682b 8651
b4ff3a36 8652 u8 reserved_at_20[0x20];
e281682b
SM		 8653};
8654
8655struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 8656 u8 reserved_at_0[0x8];
e281682b 8657 u8 local_port[0x8];
b4ff3a36 8658 u8 reserved_at_10[0x5];
e281682b 8659 u8 prio[0x3];
b4ff3a36 8660 u8 reserved_at_18[0x6];
e281682b
SM		 8661 u8 mode[0x2];
8662
b4ff3a36 8663 u8 reserved_at_20[0x20];
e281682b 8664
b4ff3a36 8665 u8 reserved_at_40[0x10];
e281682b
SM		 8666 u8 min_threshold[0x10];
8667
b4ff3a36 8668 u8 reserved_at_60[0x10];
e281682b
SM		 8669 u8 max_threshold[0x10];
8670
b4ff3a36 8671 u8 reserved_at_80[0x10];
e281682b
SM		 8672 u8 mark_probability_denominator[0x10];
8673
b4ff3a36 8674 u8 reserved_at_a0[0x60];
e281682b
SM		 8675};
8676
8677struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 8678 u8 reserved_at_0[0x8];
e281682b 8679 u8 local_port[0x8];
b4ff3a36 8680 u8 reserved_at_10[0x10];
e281682b 8681
b4ff3a36 8682 u8 reserved_at_20[0x60];
e281682b 8683
b4ff3a36 8684 u8 reserved_at_80[0x1c];
e281682b
SM		 8685 u8 wrps_admin[0x4];
8686
b4ff3a36 8687 u8 reserved_at_a0[0x1c];
e281682b
SM		 8688 u8 wrps_status[0x4];
8689
b4ff3a36 8690 u8 reserved_at_c0[0x8];
e281682b 8691 u8 up_threshold[0x8];
b4ff3a36 8692 u8 reserved_at_d0[0x8];
e281682b
SM		 8693 u8 down_threshold[0x8];
8694
b4ff3a36 8695 u8 reserved_at_e0[0x20];
e281682b 8696
b4ff3a36 8697 u8 reserved_at_100[0x1c];
e281682b
SM		 8698 u8 srps_admin[0x4];
8699
b4ff3a36 8700 u8 reserved_at_120[0x1c];
e281682b
SM		 8701 u8 srps_status[0x4];
8702
b4ff3a36 8703 u8 reserved_at_140[0x40];
e281682b
SM		 8704};
8705
8706struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 8707 u8 reserved_at_0[0x8];
e281682b 8708 u8 local_port[0x8];
b4ff3a36 8709 u8 reserved_at_10[0x10];
e281682b 8710
b4ff3a36 8711 u8 reserved_at_20[0x8];
e281682b 8712 u8 lb_cap[0x8];
b4ff3a36 8713 u8 reserved_at_30[0x8];
e281682b
SM		 8714 u8 lb_en[0x8];
8715};
8716
8717struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 8718 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 8719 u8 local_port[0x8];
8720 u8 reserved_at_10[0x10];
e281682b 8721
4b5b9c7d 8722 u8 reserved_at_20[0x20];
e281682b 8723
4b5b9c7d
SA		 8724 u8 port_profile_mode[0x8];
8725 u8 static_port_profile[0x8];
8726 u8 active_port_profile[0x8];
8727 u8 reserved_at_58[0x8];
e281682b 8728
4b5b9c7d
SA		 8729 u8 retransmission_active[0x8];
8730 u8 fec_mode_active[0x18];
e281682b 8731
4b5b9c7d
SA		 8732 u8 rs_fec_correction_bypass_cap[0x4];
8733 u8 reserved_at_84[0x8];
8734 u8 fec_override_cap_56g[0x4];
8735 u8 fec_override_cap_100g[0x4];
8736 u8 fec_override_cap_50g[0x4];
8737 u8 fec_override_cap_25g[0x4];
8738 u8 fec_override_cap_10g_40g[0x4];
8739
8740 u8 rs_fec_correction_bypass_admin[0x4];
8741 u8 reserved_at_a4[0x8];
8742 u8 fec_override_admin_56g[0x4];
8743 u8 fec_override_admin_100g[0x4];
8744 u8 fec_override_admin_50g[0x4];
8745 u8 fec_override_admin_25g[0x4];
8746 u8 fec_override_admin_10g_40g[0x4];
a58837f5
AL		 8747
8748 u8 fec_override_cap_400g_8x[0x10];
8749 u8 fec_override_cap_200g_4x[0x10];
8750
8751 u8 fec_override_cap_100g_2x[0x10];
8752 u8 fec_override_cap_50g_1x[0x10];
8753
8754 u8 fec_override_admin_400g_8x[0x10];
8755 u8 fec_override_admin_200g_4x[0x10];
8756
8757 u8 fec_override_admin_100g_2x[0x10];
8758 u8 fec_override_admin_50g_1x[0x10];
e281682b
SM		 8759};
8760
8761struct mlx5_ifc_ppcnt_reg_bits {
8762 u8 swid[0x8];
8763 u8 local_port[0x8];
8764 u8 pnat[0x2];
b4ff3a36 8765 u8 reserved_at_12[0x8];
e281682b
SM		 8766 u8 grp[0x6];
8767
8768 u8 clr[0x1];
b4ff3a36 8769 u8 reserved_at_21[0x1c];
e281682b
SM		 8770 u8 prio_tc[0x3];
8771
8772 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8773};
8774
4039049b
AL		 8775struct mlx5_ifc_mpein_reg_bits {
8776 u8 reserved_at_0[0x2];
8777 u8 depth[0x6];
8778 u8 pcie_index[0x8];
8779 u8 node[0x8];
8780 u8 reserved_at_18[0x8];
8781
8782 u8 capability_mask[0x20];
8783
8784 u8 reserved_at_40[0x8];
8785 u8 link_width_enabled[0x8];
8786 u8 link_speed_enabled[0x10];
8787
8788 u8 lane0_physical_position[0x8];
8789 u8 link_width_active[0x8];
8790 u8 link_speed_active[0x10];
8791
8792 u8 num_of_pfs[0x10];
8793 u8 num_of_vfs[0x10];
8794
8795 u8 bdf0[0x10];
8796 u8 reserved_at_b0[0x10];
8797
8798 u8 max_read_request_size[0x4];
8799 u8 max_payload_size[0x4];
8800 u8 reserved_at_c8[0x5];
8801 u8 pwr_status[0x3];
8802 u8 port_type[0x4];
8803 u8 reserved_at_d4[0xb];
8804 u8 lane_reversal[0x1];
8805
8806 u8 reserved_at_e0[0x14];
8807 u8 pci_power[0xc];
8808
8809 u8 reserved_at_100[0x20];
8810
8811 u8 device_status[0x10];
8812 u8 port_state[0x8];
8813 u8 reserved_at_138[0x8];
8814
8815 u8 reserved_at_140[0x10];
8816 u8 receiver_detect_result[0x10];
8817
8818 u8 reserved_at_160[0x20];
8819};
8820
8ed1a630
GP		 8821struct mlx5_ifc_mpcnt_reg_bits {
8822 u8 reserved_at_0[0x8];
8823 u8 pcie_index[0x8];
8824 u8 reserved_at_10[0xa];
8825 u8 grp[0x6];
8826
8827 u8 clr[0x1];
8828 u8 reserved_at_21[0x1f];
8829
8830 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8831};
8832
e281682b 8833struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 8834 u8 reserved_at_0[0x3];
e281682b 8835 u8 single_mac[0x1];
b4ff3a36 8836 u8 reserved_at_4[0x4];
e281682b
SM		 8837 u8 local_port[0x8];
8838 u8 mac_47_32[0x10];
8839
8840 u8 mac_31_0[0x20];
8841
b4ff3a36 8842 u8 reserved_at_40[0x40];
e281682b
SM		 8843};
8844
8845struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 8846 u8 reserved_at_0[0x8];
e281682b 8847 u8 local_port[0x8];
b4ff3a36 8848 u8 reserved_at_10[0x10];
e281682b
SM		 8849
8850 u8 max_mtu[0x10];
b4ff3a36 8851 u8 reserved_at_30[0x10];
e281682b
SM		 8852
8853 u8 admin_mtu[0x10];
b4ff3a36 8854 u8 reserved_at_50[0x10];
e281682b
SM		 8855
8856 u8 oper_mtu[0x10];
b4ff3a36 8857 u8 reserved_at_70[0x10];
e281682b
SM		 8858};
8859
8860struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 8861 u8 reserved_at_0[0x8];
e281682b 8862 u8 module[0x8];
b4ff3a36 8863 u8 reserved_at_10[0x10];
e281682b 8864
b4ff3a36 8865 u8 reserved_at_20[0x18];
e281682b
SM		 8866 u8 attenuation_5g[0x8];
8867
b4ff3a36 8868 u8 reserved_at_40[0x18];
e281682b
SM		 8869 u8 attenuation_7g[0x8];
8870
b4ff3a36 8871 u8 reserved_at_60[0x18];
e281682b
SM		 8872 u8 attenuation_12g[0x8];
8873};
8874
8875struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 8876 u8 reserved_at_0[0x8];
e281682b 8877 u8 module[0x8];
b4ff3a36 8878 u8 reserved_at_10[0xc];
e281682b
SM		 8879 u8 module_status[0x4];
8880
b4ff3a36 8881 u8 reserved_at_20[0x60];
e281682b
SM		 8882};
8883
8884struct mlx5_ifc_pmpc_reg_bits {
8885 u8 module_state_updated[32][0x8];
8886};
8887
8888struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 8889 u8 reserved_at_0[0x4];
e281682b
SM		 8890 u8 mlpn_status[0x4];
8891 u8 local_port[0x8];
b4ff3a36 8892 u8 reserved_at_10[0x10];
e281682b
SM		 8893
8894 u8 e[0x1];
b4ff3a36 8895 u8 reserved_at_21[0x1f];
e281682b
SM		 8896};
8897
8898struct mlx5_ifc_pmlp_reg_bits {
8899 u8 rxtx[0x1];
b4ff3a36 8900 u8 reserved_at_1[0x7];
e281682b 8901 u8 local_port[0x8];
b4ff3a36 8902 u8 reserved_at_10[0x8];
e281682b
SM		 8903 u8 width[0x8];
8904
8905 u8 lane0_module_mapping[0x20];
8906
8907 u8 lane1_module_mapping[0x20];
8908
8909 u8 lane2_module_mapping[0x20];
8910
8911 u8 lane3_module_mapping[0x20];
8912
b4ff3a36 8913 u8 reserved_at_a0[0x160];
e281682b
SM		 8914};
8915
8916struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 8917 u8 reserved_at_0[0x8];
e281682b 8918 u8 module[0x8];
b4ff3a36 8919 u8 reserved_at_10[0x4];
e281682b 8920 u8 admin_status[0x4];
b4ff3a36 8921 u8 reserved_at_18[0x4];
e281682b
SM		 8922 u8 oper_status[0x4];
8923
8924 u8 ase[0x1];
8925 u8 ee[0x1];
b4ff3a36 8926 u8 reserved_at_22[0x1c];
e281682b
SM		 8927 u8 e[0x2];
8928
b4ff3a36 8929 u8 reserved_at_40[0x40];
e281682b
SM		 8930};
8931
8932struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 8933 u8 reserved_at_0[0x4];
e281682b 8934 u8 profile_id[0xc];
b4ff3a36 8935 u8 reserved_at_10[0x4];
e281682b 8936 u8 proto_mask[0x4];
b4ff3a36 8937 u8 reserved_at_18[0x8];
e281682b 8938
b4ff3a36 8939 u8 reserved_at_20[0x10];
e281682b
SM		 8940 u8 lane_speed[0x10];
8941
b4ff3a36 8942 u8 reserved_at_40[0x17];
e281682b
SM		 8943 u8 lpbf[0x1];
8944 u8 fec_mode_policy[0x8];
8945
8946 u8 retransmission_capability[0x8];
8947 u8 fec_mode_capability[0x18];
8948
8949 u8 retransmission_support_admin[0x8];
8950 u8 fec_mode_support_admin[0x18];
8951
8952 u8 retransmission_request_admin[0x8];
8953 u8 fec_mode_request_admin[0x18];
8954
b4ff3a36 8955 u8 reserved_at_c0[0x80];
e281682b
SM		 8956};
8957
8958struct mlx5_ifc_plib_reg_bits {
b4ff3a36 8959 u8 reserved_at_0[0x8];
e281682b 8960 u8 local_port[0x8];
b4ff3a36 8961 u8 reserved_at_10[0x8];
e281682b
SM		 8962 u8 ib_port[0x8];
8963
b4ff3a36 8964 u8 reserved_at_20[0x60];
e281682b
SM		 8965};
8966
8967struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 8968 u8 reserved_at_0[0x8];
e281682b 8969 u8 local_port[0x8];
b4ff3a36 8970 u8 reserved_at_10[0xd];
e281682b
SM		 8971 u8 lbf_mode[0x3];
8972
b4ff3a36 8973 u8 reserved_at_20[0x20];
e281682b
SM		 8974};
8975
8976struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 8977 u8 reserved_at_0[0x8];
e281682b 8978 u8 local_port[0x8];
b4ff3a36 8979 u8 reserved_at_10[0x10];
e281682b
SM		 8980
8981 u8 dic[0x1];
b4ff3a36 8982 u8 reserved_at_21[0x19];
e281682b 8983 u8 ipg[0x4];
b4ff3a36 8984 u8 reserved_at_3e[0x2];
e281682b
SM		 8985};
8986
8987struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 8988 u8 reserved_at_0[0x8];
e281682b 8989 u8 local_port[0x8];
b4ff3a36 8990 u8 reserved_at_10[0x10];
e281682b 8991
b4ff3a36 8992 u8 reserved_at_20[0xe0];
e281682b
SM		 8993
8994 u8 port_filter[8][0x20];
8995
8996 u8 port_filter_update_en[8][0x20];
8997};
8998
8999struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 9000 u8 reserved_at_0[0x8];
e281682b 9001 u8 local_port[0x8];
2afa609f
IK		 9002 u8 reserved_at_10[0xb];
9003 u8 ppan_mask_n[0x1];
9004 u8 minor_stall_mask[0x1];
9005 u8 critical_stall_mask[0x1];
9006 u8 reserved_at_1e[0x2];
e281682b
SM		 9007
9008 u8 ppan[0x4];
b4ff3a36 9009 u8 reserved_at_24[0x4];
e281682b 9010 u8 prio_mask_tx[0x8];
b4ff3a36 9011 u8 reserved_at_30[0x8];
e281682b
SM		 9012 u8 prio_mask_rx[0x8];
9013
9014 u8 pptx[0x1];
9015 u8 aptx[0x1];
2afa609f
IK		 9016 u8 pptx_mask_n[0x1];
9017 u8 reserved_at_43[0x5];
e281682b 9018 u8 pfctx[0x8];
b4ff3a36 9019 u8 reserved_at_50[0x10];
e281682b
SM		 9020
9021 u8 pprx[0x1];
9022 u8 aprx[0x1];
2afa609f
IK		 9023 u8 pprx_mask_n[0x1];
9024 u8 reserved_at_63[0x5];
e281682b 9025 u8 pfcrx[0x8];
b4ff3a36 9026 u8 reserved_at_70[0x10];
e281682b 9027
2afa609f
IK		 9028 u8 device_stall_minor_watermark[0x10];
9029 u8 device_stall_critical_watermark[0x10];
9030
9031 u8 reserved_at_a0[0x60];
e281682b
SM		 9032};
9033
9034struct mlx5_ifc_pelc_reg_bits {
9035 u8 op[0x4];
b4ff3a36 9036 u8 reserved_at_4[0x4];
e281682b 9037 u8 local_port[0x8];
b4ff3a36 9038 u8 reserved_at_10[0x10];
e281682b
SM		 9039
9040 u8 op_admin[0x8];
9041 u8 op_capability[0x8];
9042 u8 op_request[0x8];
9043 u8 op_active[0x8];
9044
9045 u8 admin[0x40];
9046
9047 u8 capability[0x40];
9048
9049 u8 request[0x40];
9050
9051 u8 active[0x40];
9052
b4ff3a36 9053 u8 reserved_at_140[0x80];
e281682b
SM		 9054};
9055
9056struct mlx5_ifc_peir_reg_bits {
b4ff3a36 9057 u8 reserved_at_0[0x8];
e281682b 9058 u8 local_port[0x8];
b4ff3a36 9059 u8 reserved_at_10[0x10];
e281682b 9060
b4ff3a36 9061 u8 reserved_at_20[0xc];
e281682b 9062 u8 error_count[0x4];
b4ff3a36 9063 u8 reserved_at_30[0x10];
e281682b 9064
b4ff3a36 9065 u8 reserved_at_40[0xc];
e281682b 9066 u8 lane[0x4];
b4ff3a36 9067 u8 reserved_at_50[0x8];
e281682b
SM		 9068 u8 error_type[0x8];
9069};
9070
5e022dd3
EBE		 9071struct mlx5_ifc_mpegc_reg_bits {
9072 u8 reserved_at_0[0x30];
9073 u8 field_select[0x10];
9074
9075 u8 tx_overflow_sense[0x1];
9076 u8 mark_cqe[0x1];
9077 u8 mark_cnp[0x1];
9078 u8 reserved_at_43[0x1b];
9079 u8 tx_lossy_overflow_oper[0x2];
9080
9081 u8 reserved_at_60[0x100];
9082};
9083
cfdcbcea 9084struct mlx5_ifc_pcam_enhanced_features_bits {
a58837f5
AL		 9085 u8 reserved_at_0[0x68];
9086 u8 fec_50G_per_lane_in_pplm[0x1];
9087 u8 reserved_at_69[0x4];
0af5107c 9088 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 9089 u8 reserved_at_6e[0x4];
9090 u8 ptys_extended_ethernet[0x1];
9091 u8 reserved_at_73[0x3];
2fcb12df 9092 u8 pfcc_mask[0x1];
67daf118
SA		 9093 u8 reserved_at_77[0x3];
9094 u8 per_lane_error_counters[0x1];
2dba0797 9095 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 9096 u8 ptys_connector_type[0x1];
9097 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 9098 u8 ppcnt_discard_group[0x1];
9099 u8 ppcnt_statistical_group[0x1];
9100};
9101
df5f1361
HN		 9102struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9103 u8 port_access_reg_cap_mask_127_to_96[0x20];
9104 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 9105
9106 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9107 u8 pplm[0x1];
9108 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 9109
9110 u8 port_access_reg_cap_mask_31_to_13[0x13];
9111 u8 pbmc[0x1];
9112 u8 pptb[0x1];
75370eb0
ED		 9113 u8 port_access_reg_cap_mask_10_to_09[0x2];
9114 u8 ppcnt[0x1];
9115 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 9116};
9117
cfdcbcea
GP		 9118struct mlx5_ifc_pcam_reg_bits {
9119 u8 reserved_at_0[0x8];
9120 u8 feature_group[0x8];
9121 u8 reserved_at_10[0x8];
9122 u8 access_reg_group[0x8];
9123
9124 u8 reserved_at_20[0x20];
9125
9126 union {
df5f1361 9127 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 9128 u8 reserved_at_0[0x80];
9129 } port_access_reg_cap_mask;
9130
9131 u8 reserved_at_c0[0x80];
9132
9133 union {
9134 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9135 u8 reserved_at_0[0x80];
9136 } feature_cap_mask;
9137
9138 u8 reserved_at_1c0[0xc0];
9139};
9140
9141struct mlx5_ifc_mcam_enhanced_features_bits {
4039049b
AL		 9142 u8 reserved_at_0[0x6e];
9143 u8 pci_status_and_power[0x1];
9144 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 9145 u8 mark_tx_action_cnp[0x1];
9146 u8 mark_tx_action_cqe[0x1];
9147 u8 dynamic_tx_overflow[0x1];
9148 u8 reserved_at_77[0x4];
5405fa26 9149 u8 pcie_outbound_stalled[0x1];
efae7f78 9150 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 9151 u8 mtpps_enh_out_per_adj[0x1];
9152 u8 mtpps_fs[0x1];
cfdcbcea
GP		 9153 u8 pcie_performance_group[0x1];
9154};
9155
0ab87743
OG		 9156struct mlx5_ifc_mcam_access_reg_bits {
9157 u8 reserved_at_0[0x1c];
9158 u8 mcda[0x1];
9159 u8 mcc[0x1];
9160 u8 mcqi[0x1];
a82e0b5b 9161 u8 mcqs[0x1];
0ab87743 9162
5e022dd3
EBE		 9163 u8 regs_95_to_87[0x9];
9164 u8 mpegc[0x1];
9165 u8 regs_85_to_68[0x12];
eff8ea8f
FD		 9166 u8 tracer_registers[0x4];
9167
0ab87743
OG		 9168 u8 regs_63_to_32[0x20];
9169 u8 regs_31_to_0[0x20];
9170};
9171
f397464e
EBE		 9172struct mlx5_ifc_mcam_access_reg_bits1 {
9173 u8 regs_127_to_96[0x20];
9174
9175 u8 regs_95_to_64[0x20];
9176
9177 u8 regs_63_to_32[0x20];
9178
9179 u8 regs_31_to_0[0x20];
9180};
9181
9182struct mlx5_ifc_mcam_access_reg_bits2 {
9183 u8 regs_127_to_99[0x1d];
9184 u8 mirc[0x1];
9185 u8 regs_97_to_96[0x2];
9186
9187 u8 regs_95_to_64[0x20];
9188
9189 u8 regs_63_to_32[0x20];
9190
9191 u8 regs_31_to_0[0x20];
9192};
9193
cfdcbcea
GP		 9194struct mlx5_ifc_mcam_reg_bits {
9195 u8 reserved_at_0[0x8];
9196 u8 feature_group[0x8];
9197 u8 reserved_at_10[0x8];
9198 u8 access_reg_group[0x8];
9199
9200 u8 reserved_at_20[0x20];
9201
9202 union {
0ab87743 9203 struct mlx5_ifc_mcam_access_reg_bits access_regs;
f397464e
EBE		 9204 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9205 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
cfdcbcea
GP		 9206 u8 reserved_at_0[0x80];
9207 } mng_access_reg_cap_mask;
9208
9209 u8 reserved_at_c0[0x80];
9210
9211 union {
9212 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9213 u8 reserved_at_0[0x80];
9214 } mng_feature_cap_mask;
9215
9216 u8 reserved_at_1c0[0x80];
9217};
9218
c02762eb
HN		 9219struct mlx5_ifc_qcam_access_reg_cap_mask {
9220 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9221 u8 qpdpm[0x1];
9222 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9223 u8 qdpm[0x1];
9224 u8 qpts[0x1];
9225 u8 qcap[0x1];
9226 u8 qcam_access_reg_cap_mask_0[0x1];
9227};
9228
9229struct mlx5_ifc_qcam_qos_feature_cap_mask {
9230 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9231 u8 qpts_trust_both[0x1];
9232};
9233
9234struct mlx5_ifc_qcam_reg_bits {
9235 u8 reserved_at_0[0x8];
9236 u8 feature_group[0x8];
9237 u8 reserved_at_10[0x8];
9238 u8 access_reg_group[0x8];
9239 u8 reserved_at_20[0x20];
9240
9241 union {
9242 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9243 u8 reserved_at_0[0x80];
9244 } qos_access_reg_cap_mask;
9245
9246 u8 reserved_at_c0[0x80];
9247
9248 union {
9249 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9250 u8 reserved_at_0[0x80];
9251 } qos_feature_cap_mask;
9252
9253 u8 reserved_at_1c0[0x80];
9254};
9255
0b9055a1
MS		 9256struct mlx5_ifc_core_dump_reg_bits {
9257 u8 reserved_at_0[0x18];
9258 u8 core_dump_type[0x8];
9259
9260 u8 reserved_at_20[0x30];
9261 u8 vhca_id[0x10];
9262
9263 u8 reserved_at_60[0x8];
9264 u8 qpn[0x18];
9265 u8 reserved_at_80[0x180];
9266};
9267
e281682b 9268struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 9269 u8 reserved_at_0[0x8];
e281682b 9270 u8 local_port[0x8];
b4ff3a36 9271 u8 reserved_at_10[0x10];
e281682b
SM		 9272
9273 u8 port_capability_mask[4][0x20];
9274};
9275
9276struct mlx5_ifc_paos_reg_bits {
9277 u8 swid[0x8];
9278 u8 local_port[0x8];
b4ff3a36 9279 u8 reserved_at_10[0x4];
e281682b 9280 u8 admin_status[0x4];
b4ff3a36 9281 u8 reserved_at_18[0x4];
e281682b
SM		 9282 u8 oper_status[0x4];
9283
9284 u8 ase[0x1];
9285 u8 ee[0x1];
b4ff3a36 9286 u8 reserved_at_22[0x1c];
e281682b
SM		 9287 u8 e[0x2];
9288
b4ff3a36 9289 u8 reserved_at_40[0x40];
e281682b
SM		 9290};
9291
9292struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 9293 u8 reserved_at_0[0x8];
e281682b 9294 u8 opamp_group[0x8];
b4ff3a36 9295 u8 reserved_at_10[0xc];
e281682b
SM		 9296 u8 opamp_group_type[0x4];
9297
9298 u8 start_index[0x10];
b4ff3a36 9299 u8 reserved_at_30[0x4];
e281682b
SM		 9300 u8 num_of_indices[0xc];
9301
9302 u8 index_data[18][0x10];
9303};
9304
7d5e1423
SM		 9305struct mlx5_ifc_pcmr_reg_bits {
9306 u8 reserved_at_0[0x8];
9307 u8 local_port[0x8];
0dcaafc0
EB		 9308 u8 reserved_at_10[0x10];
9309 u8 entropy_force_cap[0x1];
9310 u8 entropy_calc_cap[0x1];
9311 u8 entropy_gre_calc_cap[0x1];
9312 u8 reserved_at_23[0x1b];
7d5e1423 9313 u8 fcs_cap[0x1];
0dcaafc0
EB		 9314 u8 reserved_at_3f[0x1];
9315 u8 entropy_force[0x1];
9316 u8 entropy_calc[0x1];
9317 u8 entropy_gre_calc[0x1];
9318 u8 reserved_at_43[0x1b];
7d5e1423
SM		 9319 u8 fcs_chk[0x1];
9320 u8 reserved_at_5f[0x1];
9321};
9322
e281682b 9323struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 9324 u8 reserved_at_0[0x6];
e281682b 9325 u8 rx_lane[0x2];
b4ff3a36 9326 u8 reserved_at_8[0x6];
e281682b 9327 u8 tx_lane[0x2];
b4ff3a36 9328 u8 reserved_at_10[0x8];
e281682b
SM		 9329 u8 module[0x8];
9330};
9331
9332struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 9333 u8 reserved_at_0[0x6];
e281682b
SM		 9334 u8 lossy[0x1];
9335 u8 epsb[0x1];
b4ff3a36 9336 u8 reserved_at_8[0xc];
e281682b
SM		 9337 u8 size[0xc];
9338
9339 u8 xoff_threshold[0x10];
9340 u8 xon_threshold[0x10];
9341};
9342
9343struct mlx5_ifc_set_node_in_bits {
9344 u8 node_description[64][0x8];
9345};
9346
9347struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 9348 u8 reserved_at_0[0x18];
e281682b
SM		 9349 u8 power_settings_level[0x8];
9350
b4ff3a36 9351 u8 reserved_at_20[0x60];
e281682b
SM		 9352};
9353
9354struct mlx5_ifc_register_host_endianness_bits {
9355 u8 he[0x1];
b4ff3a36 9356 u8 reserved_at_1[0x1f];
e281682b 9357
b4ff3a36 9358 u8 reserved_at_20[0x60];
e281682b
SM		 9359};
9360
9361struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 9362 u8 reserved_at_0[0x20];
e281682b
SM		 9363
9364 u8 mkey[0x20];
9365
9366 u8 addressh_63_32[0x20];
9367
9368 u8 addressl_31_0[0x20];
9369};
9370
9371struct mlx5_ifc_ud_adrs_vector_bits {
9372 u8 dc_key[0x40];
9373
9374 u8 ext[0x1];
b4ff3a36 9375 u8 reserved_at_41[0x7];
e281682b
SM		 9376 u8 destination_qp_dct[0x18];
9377
9378 u8 static_rate[0x4];
9379 u8 sl_eth_prio[0x4];
9380 u8 fl[0x1];
9381 u8 mlid[0x7];
9382 u8 rlid_udp_sport[0x10];
9383
b4ff3a36 9384 u8 reserved_at_80[0x20];
e281682b
SM		 9385
9386 u8 rmac_47_16[0x20];
9387
9388 u8 rmac_15_0[0x10];
9389 u8 tclass[0x8];
9390 u8 hop_limit[0x8];
9391
b4ff3a36 9392 u8 reserved_at_e0[0x1];
e281682b 9393 u8 grh[0x1];
b4ff3a36 9394 u8 reserved_at_e2[0x2];
e281682b
SM		 9395 u8 src_addr_index[0x8];
9396 u8 flow_label[0x14];
9397
9398 u8 rgid_rip[16][0x8];
9399};
9400
9401struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 9402 u8 reserved_at_0[0x10];
e281682b
SM		 9403 u8 function_id[0x10];
9404
9405 u8 num_pages[0x20];
9406
b4ff3a36 9407 u8 reserved_at_40[0xa0];
e281682b
SM		 9408};
9409
9410struct mlx5_ifc_eqe_bits {
b4ff3a36 9411 u8 reserved_at_0[0x8];
e281682b 9412 u8 event_type[0x8];
b4ff3a36 9413 u8 reserved_at_10[0x8];
e281682b
SM		 9414 u8 event_sub_type[0x8];
9415
b4ff3a36 9416 u8 reserved_at_20[0xe0];
e281682b
SM		 9417
9418 union mlx5_ifc_event_auto_bits event_data;
9419
b4ff3a36 9420 u8 reserved_at_1e0[0x10];
e281682b 9421 u8 signature[0x8];
b4ff3a36 9422 u8 reserved_at_1f8[0x7];
e281682b
SM		 9423 u8 owner[0x1];
9424};
9425
9426enum {
9427 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9428};
9429
9430struct mlx5_ifc_cmd_queue_entry_bits {
9431 u8 type[0x8];
b4ff3a36 9432 u8 reserved_at_8[0x18];
e281682b
SM		 9433
9434 u8 input_length[0x20];
9435
9436 u8 input_mailbox_pointer_63_32[0x20];
9437
9438 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 9439 u8 reserved_at_77[0x9];
e281682b
SM		 9440
9441 u8 command_input_inline_data[16][0x8];
9442
9443 u8 command_output_inline_data[16][0x8];
9444
9445 u8 output_mailbox_pointer_63_32[0x20];
9446
9447 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 9448 u8 reserved_at_1b7[0x9];
e281682b
SM		 9449
9450 u8 output_length[0x20];
9451
9452 u8 token[0x8];
9453 u8 signature[0x8];
b4ff3a36 9454 u8 reserved_at_1f0[0x8];
e281682b
SM		 9455 u8 status[0x7];
9456 u8 ownership[0x1];
9457};
9458
9459struct mlx5_ifc_cmd_out_bits {
9460 u8 status[0x8];
b4ff3a36 9461 u8 reserved_at_8[0x18];
e281682b
SM		 9462
9463 u8 syndrome[0x20];
9464
9465 u8 command_output[0x20];
9466};
9467
9468struct mlx5_ifc_cmd_in_bits {
9469 u8 opcode[0x10];
b4ff3a36 9470 u8 reserved_at_10[0x10];
e281682b 9471
b4ff3a36 9472 u8 reserved_at_20[0x10];
e281682b
SM		 9473 u8 op_mod[0x10];
9474
b6ca09cb 9475 u8 command[][0x20];
e281682b
SM		 9476};
9477
9478struct mlx5_ifc_cmd_if_box_bits {
9479 u8 mailbox_data[512][0x8];
9480
b4ff3a36 9481 u8 reserved_at_1000[0x180];
e281682b
SM		 9482
9483 u8 next_pointer_63_32[0x20];
9484
9485 u8 next_pointer_31_10[0x16];
b4ff3a36 9486 u8 reserved_at_11b6[0xa];
e281682b
SM		 9487
9488 u8 block_number[0x20];
9489
b4ff3a36 9490 u8 reserved_at_11e0[0x8];
e281682b
SM		 9491 u8 token[0x8];
9492 u8 ctrl_signature[0x8];
9493 u8 signature[0x8];
9494};
9495
9496struct mlx5_ifc_mtt_bits {
9497 u8 ptag_63_32[0x20];
9498
9499 u8 ptag_31_8[0x18];
b4ff3a36 9500 u8 reserved_at_38[0x6];
e281682b
SM		 9501 u8 wr_en[0x1];
9502 u8 rd_en[0x1];
9503};
9504
928cfe87
TT		 9505struct mlx5_ifc_query_wol_rol_out_bits {
9506 u8 status[0x8];
9507 u8 reserved_at_8[0x18];
9508
9509 u8 syndrome[0x20];
9510
9511 u8 reserved_at_40[0x10];
9512 u8 rol_mode[0x8];
9513 u8 wol_mode[0x8];
9514
9515 u8 reserved_at_60[0x20];
9516};
9517
9518struct mlx5_ifc_query_wol_rol_in_bits {
9519 u8 opcode[0x10];
9520 u8 reserved_at_10[0x10];
9521
9522 u8 reserved_at_20[0x10];
9523 u8 op_mod[0x10];
9524
9525 u8 reserved_at_40[0x40];
9526};
9527
9528struct mlx5_ifc_set_wol_rol_out_bits {
9529 u8 status[0x8];
9530 u8 reserved_at_8[0x18];
9531
9532 u8 syndrome[0x20];
9533
9534 u8 reserved_at_40[0x40];
9535};
9536
9537struct mlx5_ifc_set_wol_rol_in_bits {
9538 u8 opcode[0x10];
9539 u8 reserved_at_10[0x10];
9540
9541 u8 reserved_at_20[0x10];
9542 u8 op_mod[0x10];
9543
9544 u8 rol_mode_valid[0x1];
9545 u8 wol_mode_valid[0x1];
9546 u8 reserved_at_42[0xe];
9547 u8 rol_mode[0x8];
9548 u8 wol_mode[0x8];
9549
9550 u8 reserved_at_60[0x20];
9551};
9552
e281682b
SM		 9553enum {
9554 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9555 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9556 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9557};
9558
9559enum {
9560 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9561 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9562 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9563};
9564
9565enum {
9566 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9567 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9568 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9569 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9570 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9571 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9572 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9573 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9574 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9575 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9576 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9577};
9578
9579struct mlx5_ifc_initial_seg_bits {
9580 u8 fw_rev_minor[0x10];
9581 u8 fw_rev_major[0x10];
9582
9583 u8 cmd_interface_rev[0x10];
9584 u8 fw_rev_subminor[0x10];
9585
b4ff3a36 9586 u8 reserved_at_40[0x40];
e281682b
SM		 9587
9588 u8 cmdq_phy_addr_63_32[0x20];
9589
9590 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 9591 u8 reserved_at_b4[0x2];
e281682b
SM		 9592 u8 nic_interface[0x2];
9593 u8 log_cmdq_size[0x4];
9594 u8 log_cmdq_stride[0x4];
9595
9596 u8 command_doorbell_vector[0x20];
9597
b4ff3a36 9598 u8 reserved_at_e0[0xf00];
e281682b
SM		 9599
9600 u8 initializing[0x1];
b4ff3a36 9601 u8 reserved_at_fe1[0x4];
e281682b 9602 u8 nic_interface_supported[0x3];
591905ba
BW		 9603 u8 embedded_cpu[0x1];
9604 u8 reserved_at_fe9[0x17];
e281682b
SM		 9605
9606 struct mlx5_ifc_health_buffer_bits health_buffer;
9607
9608 u8 no_dram_nic_offset[0x20];
9609
b4ff3a36 9610 u8 reserved_at_1220[0x6e40];
e281682b 9611
b4ff3a36 9612 u8 reserved_at_8060[0x1f];
e281682b
SM		 9613 u8 clear_int[0x1];
9614
9615 u8 health_syndrome[0x8];
9616 u8 health_counter[0x18];
9617
b4ff3a36 9618 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 9619};
9620
f9a1ef72
EE		 9621struct mlx5_ifc_mtpps_reg_bits {
9622 u8 reserved_at_0[0xc];
9623 u8 cap_number_of_pps_pins[0x4];
9624 u8 reserved_at_10[0x4];
9625 u8 cap_max_num_of_pps_in_pins[0x4];
9626 u8 reserved_at_18[0x4];
9627 u8 cap_max_num_of_pps_out_pins[0x4];
9628
9629 u8 reserved_at_20[0x24];
9630 u8 cap_pin_3_mode[0x4];
9631 u8 reserved_at_48[0x4];
9632 u8 cap_pin_2_mode[0x4];
9633 u8 reserved_at_50[0x4];
9634 u8 cap_pin_1_mode[0x4];
9635 u8 reserved_at_58[0x4];
9636 u8 cap_pin_0_mode[0x4];
9637
9638 u8 reserved_at_60[0x4];
9639 u8 cap_pin_7_mode[0x4];
9640 u8 reserved_at_68[0x4];
9641 u8 cap_pin_6_mode[0x4];
9642 u8 reserved_at_70[0x4];
9643 u8 cap_pin_5_mode[0x4];
9644 u8 reserved_at_78[0x4];
9645 u8 cap_pin_4_mode[0x4];
9646
fa367688
EE		 9647 u8 field_select[0x20];
9648 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 9649
9650 u8 enable[0x1];
9651 u8 reserved_at_101[0xb];
9652 u8 pattern[0x4];
9653 u8 reserved_at_110[0x4];
9654 u8 pin_mode[0x4];
9655 u8 pin[0x8];
9656
9657 u8 reserved_at_120[0x20];
9658
9659 u8 time_stamp[0x40];
9660
9661 u8 out_pulse_duration[0x10];
9662 u8 out_periodic_adjustment[0x10];
fa367688 9663 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 9664
fa367688 9665 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 9666};
9667
9668struct mlx5_ifc_mtppse_reg_bits {
9669 u8 reserved_at_0[0x18];
9670 u8 pin[0x8];
9671 u8 event_arm[0x1];
9672 u8 reserved_at_21[0x1b];
9673 u8 event_generation_mode[0x4];
9674 u8 reserved_at_40[0x40];
9675};
9676
a82e0b5b
SA		 9677struct mlx5_ifc_mcqs_reg_bits {
9678 u8 last_index_flag[0x1];
9679 u8 reserved_at_1[0x7];
9680 u8 fw_device[0x8];
9681 u8 component_index[0x10];
9682
9683 u8 reserved_at_20[0x10];
9684 u8 identifier[0x10];
9685
9686 u8 reserved_at_40[0x17];
9687 u8 component_status[0x5];
9688 u8 component_update_state[0x4];
9689
9690 u8 last_update_state_changer_type[0x4];
9691 u8 last_update_state_changer_host_id[0x4];
9692 u8 reserved_at_68[0x18];
9693};
9694
47176289
OG		 9695struct mlx5_ifc_mcqi_cap_bits {
9696 u8 supported_info_bitmask[0x20];
9697
9698 u8 component_size[0x20];
9699
9700 u8 max_component_size[0x20];
9701
9702 u8 log_mcda_word_size[0x4];
9703 u8 reserved_at_64[0xc];
9704 u8 mcda_max_write_size[0x10];
9705
9706 u8 rd_en[0x1];
9707 u8 reserved_at_81[0x1];
9708 u8 match_chip_id[0x1];
9709 u8 match_psid[0x1];
9710 u8 check_user_timestamp[0x1];
9711 u8 match_base_guid_mac[0x1];
9712 u8 reserved_at_86[0x1a];
9713};
9714
a82e0b5b
SA		 9715struct mlx5_ifc_mcqi_version_bits {
9716 u8 reserved_at_0[0x2];
9717 u8 build_time_valid[0x1];
9718 u8 user_defined_time_valid[0x1];
9719 u8 reserved_at_4[0x14];
9720 u8 version_string_length[0x8];
9721
9722 u8 version[0x20];
9723
9724 u8 build_time[0x40];
9725
9726 u8 user_defined_time[0x40];
9727
9728 u8 build_tool_version[0x20];
9729
9730 u8 reserved_at_e0[0x20];
9731
9732 u8 version_string[92][0x8];
9733};
9734
9735struct mlx5_ifc_mcqi_activation_method_bits {
9736 u8 pending_server_ac_power_cycle[0x1];
9737 u8 pending_server_dc_power_cycle[0x1];
9738 u8 pending_server_reboot[0x1];
9739 u8 pending_fw_reset[0x1];
9740 u8 auto_activate[0x1];
9741 u8 all_hosts_sync[0x1];
9742 u8 device_hw_reset[0x1];
9743 u8 reserved_at_7[0x19];
9744};
9745
9746union mlx5_ifc_mcqi_reg_data_bits {
9747 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9748 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9749 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9750};
9751
47176289
OG		 9752struct mlx5_ifc_mcqi_reg_bits {
9753 u8 read_pending_component[0x1];
9754 u8 reserved_at_1[0xf];
9755 u8 component_index[0x10];
9756
9757 u8 reserved_at_20[0x20];
9758
9759 u8 reserved_at_40[0x1b];
9760 u8 info_type[0x5];
9761
9762 u8 info_size[0x20];
9763
9764 u8 offset[0x20];
9765
9766 u8 reserved_at_a0[0x10];
9767 u8 data_size[0x10];
9768
b6ca09cb 9769 union mlx5_ifc_mcqi_reg_data_bits data[];
47176289
OG		 9770};
9771
9772struct mlx5_ifc_mcc_reg_bits {
9773 u8 reserved_at_0[0x4];
9774 u8 time_elapsed_since_last_cmd[0xc];
9775 u8 reserved_at_10[0x8];
9776 u8 instruction[0x8];
9777
9778 u8 reserved_at_20[0x10];
9779 u8 component_index[0x10];
9780
9781 u8 reserved_at_40[0x8];
9782 u8 update_handle[0x18];
9783
9784 u8 handle_owner_type[0x4];
9785 u8 handle_owner_host_id[0x4];
9786 u8 reserved_at_68[0x1];
9787 u8 control_progress[0x7];
9788 u8 error_code[0x8];
9789 u8 reserved_at_78[0x4];
9790 u8 control_state[0x4];
9791
9792 u8 component_size[0x20];
9793
9794 u8 reserved_at_a0[0x60];
9795};
9796
9797struct mlx5_ifc_mcda_reg_bits {
9798 u8 reserved_at_0[0x8];
9799 u8 update_handle[0x18];
9800
9801 u8 offset[0x20];
9802
9803 u8 reserved_at_40[0x10];
9804 u8 size[0x10];
9805
9806 u8 reserved_at_60[0x20];
9807
9808 u8 data[0][0x20];
9809};
9810
06939536
MS		 9811enum {
9812 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9813 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9814};
9815
9816enum {
9817 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9818 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9819 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9820};
9821
9822struct mlx5_ifc_mfrl_reg_bits {
9823 u8 reserved_at_0[0x20];
9824
9825 u8 reserved_at_20[0x2];
9826 u8 pci_sync_for_fw_update_start[0x1];
9827 u8 pci_sync_for_fw_update_resp[0x2];
9828 u8 rst_type_sel[0x3];
9829 u8 reserved_at_28[0x8];
9830 u8 reset_type[0x8];
9831 u8 reset_level[0x8];
9832};
9833
bab58ba1
EBE		 9834struct mlx5_ifc_mirc_reg_bits {
9835 u8 reserved_at_0[0x18];
9836 u8 status_code[0x8];
9837
9838 u8 reserved_at_20[0x20];
9839};
9840
e281682b
SM		 9841union mlx5_ifc_ports_control_registers_document_bits {
9842 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9843 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9844 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9845 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9846 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9847 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9848 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 9849 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9850 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
e281682b
SM		 9851 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9852 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9853 struct mlx5_ifc_paos_reg_bits paos_reg;
9854 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9855 struct mlx5_ifc_peir_reg_bits peir_reg;
9856 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9857 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 9858 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 9859 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9860 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9861 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9862 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9863 struct mlx5_ifc_plib_reg_bits plib_reg;
9864 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9865 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9866 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9867 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9868 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9869 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9870 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9871 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9872 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9873 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 9874 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 9875 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 9876 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9877 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9878 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9879 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9880 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9881 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9882 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 9883 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 9884 struct mlx5_ifc_pude_reg_bits pude_reg;
9885 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9886 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9887 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 9888 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9889 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 9890 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 9891 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9892 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 9893 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9894 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9895 struct mlx5_ifc_mcda_reg_bits mcda_reg;
bab58ba1 9896 struct mlx5_ifc_mirc_reg_bits mirc_reg;
06939536 9897 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
b4ff3a36 9898 u8 reserved_at_0[0x60e0];
e281682b
SM		 9899};
9900
9901union mlx5_ifc_debug_enhancements_document_bits {
9902 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 9903 u8 reserved_at_0[0x200];
e281682b
SM		 9904};
9905
9906union mlx5_ifc_uplink_pci_interface_document_bits {
9907 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 9908 u8 reserved_at_0[0x20060];
b775516b
EC		 9909};
9910
2cc43b49
MG		 9911struct mlx5_ifc_set_flow_table_root_out_bits {
9912 u8 status[0x8];
b4ff3a36 9913 u8 reserved_at_8[0x18];
2cc43b49
MG		 9914
9915 u8 syndrome[0x20];
9916
b4ff3a36 9917 u8 reserved_at_40[0x40];
2cc43b49
MG		 9918};
9919
9920struct mlx5_ifc_set_flow_table_root_in_bits {
9921 u8 opcode[0x10];
b4ff3a36 9922 u8 reserved_at_10[0x10];
2cc43b49 9923
b4ff3a36 9924 u8 reserved_at_20[0x10];
2cc43b49
MG		 9925 u8 op_mod[0x10];
9926
7d5e1423
SM		 9927 u8 other_vport[0x1];
9928 u8 reserved_at_41[0xf];
9929 u8 vport_number[0x10];
9930
9931 u8 reserved_at_60[0x20];
2cc43b49
MG		 9932
9933 u8 table_type[0x8];
b4ff3a36 9934 u8 reserved_at_88[0x18];
2cc43b49 9935
b4ff3a36 9936 u8 reserved_at_a0[0x8];
2cc43b49
MG		 9937 u8 table_id[0x18];
9938
500a3d0d
ES		 9939 u8 reserved_at_c0[0x8];
9940 u8 underlay_qpn[0x18];
9941 u8 reserved_at_e0[0x120];
2cc43b49
MG		 9942};
9943
34a40e68 9944enum {
84df61eb
AH		 9945 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9946 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 9947};
9948
9949struct mlx5_ifc_modify_flow_table_out_bits {
9950 u8 status[0x8];
b4ff3a36 9951 u8 reserved_at_8[0x18];
34a40e68
MG		 9952
9953 u8 syndrome[0x20];
9954
b4ff3a36 9955 u8 reserved_at_40[0x40];
34a40e68
MG		 9956};
9957
9958struct mlx5_ifc_modify_flow_table_in_bits {
9959 u8 opcode[0x10];
b4ff3a36 9960 u8 reserved_at_10[0x10];
34a40e68 9961
b4ff3a36 9962 u8 reserved_at_20[0x10];
34a40e68
MG		 9963 u8 op_mod[0x10];
9964
7d5e1423
SM		 9965 u8 other_vport[0x1];
9966 u8 reserved_at_41[0xf];
9967 u8 vport_number[0x10];
34a40e68 9968
b4ff3a36 9969 u8 reserved_at_60[0x10];
34a40e68
MG		 9970 u8 modify_field_select[0x10];
9971
9972 u8 table_type[0x8];
b4ff3a36 9973 u8 reserved_at_88[0x18];
34a40e68 9974
b4ff3a36 9975 u8 reserved_at_a0[0x8];
34a40e68
MG		 9976 u8 table_id[0x18];
9977
0c90e9c6 9978 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 9979};
9980
4f3961ee
SM		 9981struct mlx5_ifc_ets_tcn_config_reg_bits {
9982 u8 g[0x1];
9983 u8 b[0x1];
9984 u8 r[0x1];
9985 u8 reserved_at_3[0x9];
9986 u8 group[0x4];
9987 u8 reserved_at_10[0x9];
9988 u8 bw_allocation[0x7];
9989
9990 u8 reserved_at_20[0xc];
9991 u8 max_bw_units[0x4];
9992 u8 reserved_at_30[0x8];
9993 u8 max_bw_value[0x8];
9994};
9995
9996struct mlx5_ifc_ets_global_config_reg_bits {
9997 u8 reserved_at_0[0x2];
9998 u8 r[0x1];
9999 u8 reserved_at_3[0x1d];
10000
10001 u8 reserved_at_20[0xc];
10002 u8 max_bw_units[0x4];
10003 u8 reserved_at_30[0x8];
10004 u8 max_bw_value[0x8];
10005};
10006
10007struct mlx5_ifc_qetc_reg_bits {
10008 u8 reserved_at_0[0x8];
10009 u8 port_number[0x8];
10010 u8 reserved_at_10[0x30];
10011
10012 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10013 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10014};
10015
415a64aa
HN		 10016struct mlx5_ifc_qpdpm_dscp_reg_bits {
10017 u8 e[0x1];
10018 u8 reserved_at_01[0x0b];
10019 u8 prio[0x04];
10020};
10021
10022struct mlx5_ifc_qpdpm_reg_bits {
10023 u8 reserved_at_0[0x8];
10024 u8 local_port[0x8];
10025 u8 reserved_at_10[0x10];
10026 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10027};
10028
10029struct mlx5_ifc_qpts_reg_bits {
10030 u8 reserved_at_0[0x8];
10031 u8 local_port[0x8];
10032 u8 reserved_at_10[0x2d];
10033 u8 trust_state[0x3];
10034};
10035
50b4a3c2
HN		 10036struct mlx5_ifc_pptb_reg_bits {
10037 u8 reserved_at_0[0x2];
10038 u8 mm[0x2];
10039 u8 reserved_at_4[0x4];
10040 u8 local_port[0x8];
10041 u8 reserved_at_10[0x6];
10042 u8 cm[0x1];
10043 u8 um[0x1];
10044 u8 pm[0x8];
10045
10046 u8 prio_x_buff[0x20];
10047
10048 u8 pm_msb[0x8];
10049 u8 reserved_at_48[0x10];
10050 u8 ctrl_buff[0x4];
10051 u8 untagged_buff[0x4];
10052};
10053
88b3d5c9
EBE		 10054struct mlx5_ifc_sbcam_reg_bits {
10055 u8 reserved_at_0[0x8];
10056 u8 feature_group[0x8];
10057 u8 reserved_at_10[0x8];
10058 u8 access_reg_group[0x8];
10059
10060 u8 reserved_at_20[0x20];
10061
10062 u8 sb_access_reg_cap_mask[4][0x20];
10063
10064 u8 reserved_at_c0[0x80];
10065
10066 u8 sb_feature_cap_mask[4][0x20];
10067
10068 u8 reserved_at_1c0[0x40];
10069
10070 u8 cap_total_buffer_size[0x20];
10071
10072 u8 cap_cell_size[0x10];
10073 u8 cap_max_pg_buffers[0x8];
10074 u8 cap_num_pool_supported[0x8];
10075
10076 u8 reserved_at_240[0x8];
10077 u8 cap_sbsr_stat_size[0x8];
10078 u8 cap_max_tclass_data[0x8];
10079 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10080};
10081
50b4a3c2
HN		 10082struct mlx5_ifc_pbmc_reg_bits {
10083 u8 reserved_at_0[0x8];
10084 u8 local_port[0x8];
10085 u8 reserved_at_10[0x10];
10086
10087 u8 xoff_timer_value[0x10];
10088 u8 xoff_refresh[0x10];
10089
10090 u8 reserved_at_40[0x9];
10091 u8 fullness_threshold[0x7];
10092 u8 port_buffer_size[0x10];
10093
10094 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10095
10096 u8 reserved_at_2e0[0x40];
10097};
10098
4f3961ee
SM		 10099struct mlx5_ifc_qtct_reg_bits {
10100 u8 reserved_at_0[0x8];
10101 u8 port_number[0x8];
10102 u8 reserved_at_10[0xd];
10103 u8 prio[0x3];
10104
10105 u8 reserved_at_20[0x1d];
10106 u8 tclass[0x3];
10107};
10108
7d5e1423
SM		 10109struct mlx5_ifc_mcia_reg_bits {
10110 u8 l[0x1];
10111 u8 reserved_at_1[0x7];
10112 u8 module[0x8];
10113 u8 reserved_at_10[0x8];
10114 u8 status[0x8];
10115
10116 u8 i2c_device_address[0x8];
10117 u8 page_number[0x8];
10118 u8 device_address[0x10];
10119
10120 u8 reserved_at_40[0x10];
10121 u8 size[0x10];
10122
10123 u8 reserved_at_60[0x20];
10124
10125 u8 dword_0[0x20];
10126 u8 dword_1[0x20];
10127 u8 dword_2[0x20];
10128 u8 dword_3[0x20];
10129 u8 dword_4[0x20];
10130 u8 dword_5[0x20];
10131 u8 dword_6[0x20];
10132 u8 dword_7[0x20];
10133 u8 dword_8[0x20];
10134 u8 dword_9[0x20];
10135 u8 dword_10[0x20];
10136 u8 dword_11[0x20];
10137};
10138
7486216b
SM		 10139struct mlx5_ifc_dcbx_param_bits {
10140 u8 dcbx_cee_cap[0x1];
10141 u8 dcbx_ieee_cap[0x1];
10142 u8 dcbx_standby_cap[0x1];
c74d90c1 10143 u8 reserved_at_3[0x5];
7486216b
SM		 10144 u8 port_number[0x8];
10145 u8 reserved_at_10[0xa];
10146 u8 max_application_table_size[6];
10147 u8 reserved_at_20[0x15];
10148 u8 version_oper[0x3];
10149 u8 reserved_at_38[5];
10150 u8 version_admin[0x3];
10151 u8 willing_admin[0x1];
10152 u8 reserved_at_41[0x3];
10153 u8 pfc_cap_oper[0x4];
10154 u8 reserved_at_48[0x4];
10155 u8 pfc_cap_admin[0x4];
10156 u8 reserved_at_50[0x4];
10157 u8 num_of_tc_oper[0x4];
10158 u8 reserved_at_58[0x4];
10159 u8 num_of_tc_admin[0x4];
10160 u8 remote_willing[0x1];
10161 u8 reserved_at_61[3];
10162 u8 remote_pfc_cap[4];
10163 u8 reserved_at_68[0x14];
10164 u8 remote_num_of_tc[0x4];
10165 u8 reserved_at_80[0x18];
10166 u8 error[0x8];
10167 u8 reserved_at_a0[0x160];
10168};
84df61eb
AH		 10169
10170struct mlx5_ifc_lagc_bits {
10171 u8 reserved_at_0[0x1d];
10172 u8 lag_state[0x3];
10173
10174 u8 reserved_at_20[0x14];
10175 u8 tx_remap_affinity_2[0x4];
10176 u8 reserved_at_38[0x4];
10177 u8 tx_remap_affinity_1[0x4];
10178};
10179
10180struct mlx5_ifc_create_lag_out_bits {
10181 u8 status[0x8];
10182 u8 reserved_at_8[0x18];
10183
10184 u8 syndrome[0x20];
10185
10186 u8 reserved_at_40[0x40];
10187};
10188
10189struct mlx5_ifc_create_lag_in_bits {
10190 u8 opcode[0x10];
10191 u8 reserved_at_10[0x10];
10192
10193 u8 reserved_at_20[0x10];
10194 u8 op_mod[0x10];
10195
10196 struct mlx5_ifc_lagc_bits ctx;
10197};
10198
10199struct mlx5_ifc_modify_lag_out_bits {
10200 u8 status[0x8];
10201 u8 reserved_at_8[0x18];
10202
10203 u8 syndrome[0x20];
10204
10205 u8 reserved_at_40[0x40];
10206};
10207
10208struct mlx5_ifc_modify_lag_in_bits {
10209 u8 opcode[0x10];
10210 u8 reserved_at_10[0x10];
10211
10212 u8 reserved_at_20[0x10];
10213 u8 op_mod[0x10];
10214
10215 u8 reserved_at_40[0x20];
10216 u8 field_select[0x20];
10217
10218 struct mlx5_ifc_lagc_bits ctx;
10219};
10220
10221struct mlx5_ifc_query_lag_out_bits {
10222 u8 status[0x8];
10223 u8 reserved_at_8[0x18];
10224
10225 u8 syndrome[0x20];
10226
84df61eb
AH		 10227 struct mlx5_ifc_lagc_bits ctx;
10228};
10229
10230struct mlx5_ifc_query_lag_in_bits {
10231 u8 opcode[0x10];
10232 u8 reserved_at_10[0x10];
10233
10234 u8 reserved_at_20[0x10];
10235 u8 op_mod[0x10];
10236
10237 u8 reserved_at_40[0x40];
10238};
10239
10240struct mlx5_ifc_destroy_lag_out_bits {
10241 u8 status[0x8];
10242 u8 reserved_at_8[0x18];
10243
10244 u8 syndrome[0x20];
10245
10246 u8 reserved_at_40[0x40];
10247};
10248
10249struct mlx5_ifc_destroy_lag_in_bits {
10250 u8 opcode[0x10];
10251 u8 reserved_at_10[0x10];
10252
10253 u8 reserved_at_20[0x10];
10254 u8 op_mod[0x10];
10255
10256 u8 reserved_at_40[0x40];
10257};
10258
10259struct mlx5_ifc_create_vport_lag_out_bits {
10260 u8 status[0x8];
10261 u8 reserved_at_8[0x18];
10262
10263 u8 syndrome[0x20];
10264
10265 u8 reserved_at_40[0x40];
10266};
10267
10268struct mlx5_ifc_create_vport_lag_in_bits {
10269 u8 opcode[0x10];
10270 u8 reserved_at_10[0x10];
10271
10272 u8 reserved_at_20[0x10];
10273 u8 op_mod[0x10];
10274
10275 u8 reserved_at_40[0x40];
10276};
10277
10278struct mlx5_ifc_destroy_vport_lag_out_bits {
10279 u8 status[0x8];
10280 u8 reserved_at_8[0x18];
10281
10282 u8 syndrome[0x20];
10283
10284 u8 reserved_at_40[0x40];
10285};
10286
10287struct mlx5_ifc_destroy_vport_lag_in_bits {
10288 u8 opcode[0x10];
10289 u8 reserved_at_10[0x10];
10290
10291 u8 reserved_at_20[0x10];
10292 u8 op_mod[0x10];
10293
10294 u8 reserved_at_40[0x40];
10295};
10296
24da0016
AL		 10297struct mlx5_ifc_alloc_memic_in_bits {
10298 u8 opcode[0x10];
10299 u8 reserved_at_10[0x10];
10300
10301 u8 reserved_at_20[0x10];
10302 u8 op_mod[0x10];
10303
10304 u8 reserved_at_30[0x20];
10305
10306 u8 reserved_at_40[0x18];
10307 u8 log_memic_addr_alignment[0x8];
10308
10309 u8 range_start_addr[0x40];
10310
10311 u8 range_size[0x20];
10312
10313 u8 memic_size[0x20];
10314};
10315
10316struct mlx5_ifc_alloc_memic_out_bits {
10317 u8 status[0x8];
10318 u8 reserved_at_8[0x18];
10319
10320 u8 syndrome[0x20];
10321
10322 u8 memic_start_addr[0x40];
10323};
10324
10325struct mlx5_ifc_dealloc_memic_in_bits {
10326 u8 opcode[0x10];
10327 u8 reserved_at_10[0x10];
10328
10329 u8 reserved_at_20[0x10];
10330 u8 op_mod[0x10];
10331
10332 u8 reserved_at_40[0x40];
10333
10334 u8 memic_start_addr[0x40];
10335
10336 u8 memic_size[0x20];
10337
10338 u8 reserved_at_e0[0x20];
10339};
10340
10341struct mlx5_ifc_dealloc_memic_out_bits {
10342 u8 status[0x8];
10343 u8 reserved_at_8[0x18];
10344
10345 u8 syndrome[0x20];
10346
10347 u8 reserved_at_40[0x40];
10348};
10349
38b7ca92
YH		 10350struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10351 u8 opcode[0x10];
10352 u8 uid[0x10];
10353
1dd7382b 10354 u8 vhca_tunnel_id[0x10];
38b7ca92
YH		 10355 u8 obj_type[0x10];
10356
10357 u8 obj_id[0x20];
10358
10359 u8 reserved_at_60[0x20];
10360};
10361
10362struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10363 u8 status[0x8];
10364 u8 reserved_at_8[0x18];
10365
10366 u8 syndrome[0x20];
10367
10368 u8 obj_id[0x20];
10369
10370 u8 reserved_at_60[0x20];
10371};
10372
10373struct mlx5_ifc_umem_bits {
6e3722ba 10374 u8 reserved_at_0[0x80];
38b7ca92 10375
6e3722ba 10376 u8 reserved_at_80[0x1b];
38b7ca92
YH		 10377 u8 log_page_size[0x5];
10378
10379 u8 page_offset[0x20];
10380
10381 u8 num_of_mtt[0x40];
10382
b6ca09cb 10383 struct mlx5_ifc_mtt_bits mtt[];
38b7ca92
YH		 10384};
10385
10386struct mlx5_ifc_uctx_bits {
9d43faac
YH		 10387 u8 cap[0x20];
10388
6e3722ba 10389 u8 reserved_at_20[0x160];
38b7ca92
YH		 10390};
10391
9fba2b9b
AL		 10392struct mlx5_ifc_sw_icm_bits {
10393 u8 modify_field_select[0x40];
10394
10395 u8 reserved_at_40[0x18];
10396 u8 log_sw_icm_size[0x8];
10397
10398 u8 reserved_at_60[0x20];
10399
10400 u8 sw_icm_start_addr[0x40];
10401
10402 u8 reserved_at_c0[0x140];
91a40a48 10403};
b169e64a
YK		 10404
10405struct mlx5_ifc_geneve_tlv_option_bits {
10406 u8 modify_field_select[0x40];
10407
10408 u8 reserved_at_40[0x18];
10409 u8 geneve_option_fte_index[0x8];
10410
10411 u8 option_class[0x10];
10412 u8 option_type[0x8];
10413 u8 reserved_at_78[0x3];
10414 u8 option_data_length[0x5];
10415
10416 u8 reserved_at_80[0x180];
9fba2b9b
AL		 10417};
10418
38b7ca92 10419struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 10420 u8 opcode[0x10];
10421 u8 uid[0x10];
10422
10423 u8 reserved_at_20[0x10];
10424 u8 op_mod[0x10];
10425
10426 u8 reserved_at_40[0x40];
10427
10428 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 10429};
10430
8a06a79b
EC		 10431struct mlx5_ifc_create_umem_out_bits {
10432 u8 status[0x8];
10433 u8 reserved_at_8[0x18];
10434
10435 u8 syndrome[0x20];
10436
10437 u8 reserved_at_40[0x8];
10438 u8 umem_id[0x18];
10439
10440 u8 reserved_at_60[0x20];
10441};
10442
10443struct mlx5_ifc_destroy_umem_in_bits {
10444 u8 opcode[0x10];
10445 u8 uid[0x10];
10446
10447 u8 reserved_at_20[0x10];
10448 u8 op_mod[0x10];
10449
10450 u8 reserved_at_40[0x8];
10451 u8 umem_id[0x18];
10452
10453 u8 reserved_at_60[0x20];
10454};
10455
10456struct mlx5_ifc_destroy_umem_out_bits {
10457 u8 status[0x8];
10458 u8 reserved_at_8[0x18];
10459
10460 u8 syndrome[0x20];
10461
10462 u8 reserved_at_40[0x40];
10463};
10464
38b7ca92 10465struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 10466 u8 opcode[0x10];
10467 u8 reserved_at_10[0x10];
10468
10469 u8 reserved_at_20[0x10];
10470 u8 op_mod[0x10];
10471
10472 u8 reserved_at_40[0x40];
10473
10474 struct mlx5_ifc_uctx_bits uctx;
10475};
10476
8a06a79b
EC		 10477struct mlx5_ifc_create_uctx_out_bits {
10478 u8 status[0x8];
10479 u8 reserved_at_8[0x18];
10480
10481 u8 syndrome[0x20];
10482
10483 u8 reserved_at_40[0x10];
10484 u8 uid[0x10];
10485
10486 u8 reserved_at_60[0x20];
10487};
10488
6e3722ba
YH		 10489struct mlx5_ifc_destroy_uctx_in_bits {
10490 u8 opcode[0x10];
10491 u8 reserved_at_10[0x10];
10492
10493 u8 reserved_at_20[0x10];
10494 u8 op_mod[0x10];
10495
10496 u8 reserved_at_40[0x10];
10497 u8 uid[0x10];
10498
10499 u8 reserved_at_60[0x20];
38b7ca92
YH		 10500};
10501
8a06a79b
EC		 10502struct mlx5_ifc_destroy_uctx_out_bits {
10503 u8 status[0x8];
10504 u8 reserved_at_8[0x18];
10505
10506 u8 syndrome[0x20];
10507
10508 u8 reserved_at_40[0x40];
10509};
10510
9fba2b9b
AL		 10511struct mlx5_ifc_create_sw_icm_in_bits {
10512 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10513 struct mlx5_ifc_sw_icm_bits sw_icm;
10514};
10515
b169e64a
YK		 10516struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10517 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10518 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10519};
10520
eff8ea8f
FD		 10521struct mlx5_ifc_mtrc_string_db_param_bits {
10522 u8 string_db_base_address[0x20];
10523
10524 u8 reserved_at_20[0x8];
10525 u8 string_db_size[0x18];
10526};
10527
10528struct mlx5_ifc_mtrc_cap_bits {
10529 u8 trace_owner[0x1];
10530 u8 trace_to_memory[0x1];
10531 u8 reserved_at_2[0x4];
10532 u8 trc_ver[0x2];
10533 u8 reserved_at_8[0x14];
10534 u8 num_string_db[0x4];
10535
10536 u8 first_string_trace[0x8];
10537 u8 num_string_trace[0x8];
10538 u8 reserved_at_30[0x28];
10539
10540 u8 log_max_trace_buffer_size[0x8];
10541
10542 u8 reserved_at_60[0x20];
10543
10544 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10545
10546 u8 reserved_at_280[0x180];
10547};
10548
10549struct mlx5_ifc_mtrc_conf_bits {
10550 u8 reserved_at_0[0x1c];
10551 u8 trace_mode[0x4];
10552 u8 reserved_at_20[0x18];
10553 u8 log_trace_buffer_size[0x8];
10554 u8 trace_mkey[0x20];
10555 u8 reserved_at_60[0x3a0];
10556};
10557
10558struct mlx5_ifc_mtrc_stdb_bits {
10559 u8 string_db_index[0x4];
10560 u8 reserved_at_4[0x4];
10561 u8 read_size[0x18];
10562 u8 start_offset[0x20];
b6ca09cb 10563 u8 string_db_data[];
eff8ea8f
FD		 10564};
10565
10566struct mlx5_ifc_mtrc_ctrl_bits {
10567 u8 trace_status[0x2];
10568 u8 reserved_at_2[0x2];
10569 u8 arm_event[0x1];
10570 u8 reserved_at_5[0xb];
10571 u8 modify_field_select[0x10];
10572 u8 reserved_at_20[0x2b];
10573 u8 current_timestamp52_32[0x15];
10574 u8 current_timestamp31_0[0x20];
10575 u8 reserved_at_80[0x180];
10576};
10577
c3a4e9f1
BW		 10578struct mlx5_ifc_host_params_context_bits {
10579 u8 host_number[0x8];
5ccf2770
BW		 10580 u8 reserved_at_8[0x7];
10581 u8 host_pf_disabled[0x1];
c3a4e9f1
BW		 10582 u8 host_num_of_vfs[0x10];
10583
86eec50b 10584 u8 host_total_vfs[0x10];
c3a4e9f1
BW		 10585 u8 host_pci_bus[0x10];
10586
10587 u8 reserved_at_40[0x10];
10588 u8 host_pci_device[0x10];
10589
10590 u8 reserved_at_60[0x10];
10591 u8 host_pci_function[0x10];
10592
10593 u8 reserved_at_80[0x180];
10594};
10595
cd56f929 10596struct mlx5_ifc_query_esw_functions_in_bits {
c3a4e9f1
BW		 10597 u8 opcode[0x10];
10598 u8 reserved_at_10[0x10];
10599
10600 u8 reserved_at_20[0x10];
10601 u8 op_mod[0x10];
10602
10603 u8 reserved_at_40[0x40];
10604};
10605
cd56f929 10606struct mlx5_ifc_query_esw_functions_out_bits {
c3a4e9f1
BW		 10607 u8 status[0x8];
10608 u8 reserved_at_8[0x18];
10609
10610 u8 syndrome[0x20];
10611
10612 u8 reserved_at_40[0x40];
10613
10614 struct mlx5_ifc_host_params_context_bits host_params_context;
10615
10616 u8 reserved_at_280[0x180];
b6ca09cb 10617 u8 host_sf_enable[][0x40];
1759d322
PP		 10618};
10619
10620struct mlx5_ifc_sf_partition_bits {
10621 u8 reserved_at_0[0x10];
10622 u8 log_num_sf[0x8];
10623 u8 log_sf_bar_size[0x8];
10624};
10625
10626struct mlx5_ifc_query_sf_partitions_out_bits {
10627 u8 status[0x8];
10628 u8 reserved_at_8[0x18];
10629
10630 u8 syndrome[0x20];
10631
10632 u8 reserved_at_40[0x18];
10633 u8 num_sf_partitions[0x8];
10634
10635 u8 reserved_at_60[0x20];
10636
b6ca09cb 10637 struct mlx5_ifc_sf_partition_bits sf_partition[];
1759d322
PP		 10638};
10639
10640struct mlx5_ifc_query_sf_partitions_in_bits {
10641 u8 opcode[0x10];
10642 u8 reserved_at_10[0x10];
10643
10644 u8 reserved_at_20[0x10];
10645 u8 op_mod[0x10];
10646
10647 u8 reserved_at_40[0x40];
10648};
10649
10650struct mlx5_ifc_dealloc_sf_out_bits {
10651 u8 status[0x8];
10652 u8 reserved_at_8[0x18];
10653
10654 u8 syndrome[0x20];
10655
10656 u8 reserved_at_40[0x40];
10657};
10658
10659struct mlx5_ifc_dealloc_sf_in_bits {
10660 u8 opcode[0x10];
10661 u8 reserved_at_10[0x10];
10662
10663 u8 reserved_at_20[0x10];
10664 u8 op_mod[0x10];
10665
10666 u8 reserved_at_40[0x10];
10667 u8 function_id[0x10];
10668
10669 u8 reserved_at_60[0x20];
10670};
10671
10672struct mlx5_ifc_alloc_sf_out_bits {
10673 u8 status[0x8];
10674 u8 reserved_at_8[0x18];
10675
10676 u8 syndrome[0x20];
10677
10678 u8 reserved_at_40[0x40];
10679};
10680
10681struct mlx5_ifc_alloc_sf_in_bits {
10682 u8 opcode[0x10];
10683 u8 reserved_at_10[0x10];
10684
10685 u8 reserved_at_20[0x10];
10686 u8 op_mod[0x10];
10687
10688 u8 reserved_at_40[0x10];
10689 u8 function_id[0x10];
10690
10691 u8 reserved_at_60[0x20];
c3a4e9f1
BW		 10692};
10693
e4075c44
YH		 10694struct mlx5_ifc_affiliated_event_header_bits {
10695 u8 reserved_at_0[0x10];
10696 u8 obj_type[0x10];
10697
10698 u8 obj_id[0x20];
10699};
10700
a12ff35e
EBE		 10701enum {
10702 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
2b58f6d9 10703 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
2a297089 10704 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT(0x20),
a12ff35e
EBE		 10705};
10706
10707enum {
10708 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
2b58f6d9 10709 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
2a297089 10710 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
2b58f6d9
RS		 10711};
10712
10713enum {
10714 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10715 MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10716 MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10717};
10718
10719struct mlx5_ifc_ipsec_obj_bits {
10720 u8 modify_field_select[0x40];
10721 u8 full_offload[0x1];
10722 u8 reserved_at_41[0x1];
10723 u8 esn_en[0x1];
10724 u8 esn_overlap[0x1];
10725 u8 reserved_at_44[0x2];
10726 u8 icv_length[0x2];
10727 u8 reserved_at_48[0x4];
10728 u8 aso_return_reg[0x4];
10729 u8 reserved_at_50[0x10];
10730
10731 u8 esn_msb[0x20];
10732
10733 u8 reserved_at_80[0x8];
10734 u8 dekn[0x18];
10735
10736 u8 salt[0x20];
10737
10738 u8 implicit_iv[0x40];
10739
10740 u8 reserved_at_100[0x700];
10741};
10742
10743struct mlx5_ifc_create_ipsec_obj_in_bits {
10744 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10745 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10746};
10747
10748enum {
10749 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10750 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10751};
10752
10753struct mlx5_ifc_query_ipsec_obj_out_bits {
10754 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10755 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10756};
10757
10758struct mlx5_ifc_modify_ipsec_obj_in_bits {
10759 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10760 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
a12ff35e
EBE		 10761};
10762
10763struct mlx5_ifc_encryption_key_obj_bits {
10764 u8 modify_field_select[0x40];
10765
10766 u8 reserved_at_40[0x14];
10767 u8 key_size[0x4];
10768 u8 reserved_at_58[0x4];
10769 u8 key_type[0x4];
10770
10771 u8 reserved_at_60[0x8];
10772 u8 pd[0x18];
10773
10774 u8 reserved_at_80[0x180];
10775 u8 key[8][0x20];
10776
10777 u8 reserved_at_300[0x500];
10778};
10779
10780struct mlx5_ifc_create_encryption_key_in_bits {
10781 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10782 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10783};
10784
2a297089
CM		 10785struct mlx5_ifc_sampler_obj_bits {
10786 u8 modify_field_select[0x40];
10787
10788 u8 table_type[0x8];
10789 u8 level[0x8];
10790 u8 reserved_at_50[0xf];
10791 u8 ignore_flow_level[0x1];
10792
10793 u8 sample_ratio[0x20];
10794
10795 u8 reserved_at_80[0x8];
10796 u8 sample_table_id[0x18];
10797
10798 u8 reserved_at_a0[0x8];
10799 u8 default_table_id[0x18];
10800
10801 u8 sw_steering_icm_address_rx[0x40];
10802 u8 sw_steering_icm_address_tx[0x40];
10803
10804 u8 reserved_at_140[0xa0];
10805};
10806
10807struct mlx5_ifc_create_sampler_obj_in_bits {
10808 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10809 struct mlx5_ifc_sampler_obj_bits sampler_object;
10810};
10811
a12ff35e
EBE		 10812enum {
10813 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10814 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10815};
10816
10817enum {
bd673da6
SM		 10818 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10819 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
a12ff35e
EBE		 10820};
10821
10822struct mlx5_ifc_tls_static_params_bits {
10823 u8 const_2[0x2];
10824 u8 tls_version[0x4];
10825 u8 const_1[0x2];
10826 u8 reserved_at_8[0x14];
10827 u8 encryption_standard[0x4];
10828
10829 u8 reserved_at_20[0x20];
10830
10831 u8 initial_record_number[0x40];
10832
10833 u8 resync_tcp_sn[0x20];
10834
10835 u8 gcm_iv[0x20];
10836
10837 u8 implicit_iv[0x40];
10838
10839 u8 reserved_at_100[0x8];
10840 u8 dek_index[0x18];
10841
10842 u8 reserved_at_120[0xe0];
10843};
10844
10845struct mlx5_ifc_tls_progress_params_bits {
a12ff35e
EBE		 10846 u8 next_record_tcp_sn[0x20];
10847
10848 u8 hw_resync_tcp_sn[0x20];
10849
10850 u8 record_tracker_state[0x2];
10851 u8 auth_state[0x2];
2d1b69ed 10852 u8 reserved_at_44[0x4];
a12ff35e
EBE		 10853 u8 hw_offset_record_number[0x18];
10854};
10855
1dcb6c36
EC		 10856enum {
10857 MLX5_MTT_PERM_READ = 1 << 0,
10858 MLX5_MTT_PERM_WRITE = 1 << 1,
10859 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
10860};
10861
d29b796a 10862#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)