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net/mlx5e: Explicitly set source e-switch in offloaded TC rules
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 95 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
96 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
d29b796a
EC		 97 MLX5_CMD_OP_CREATE_EQ = 0x301,
98 MLX5_CMD_OP_DESTROY_EQ = 0x302,
99 MLX5_CMD_OP_QUERY_EQ = 0x303,
100 MLX5_CMD_OP_GEN_EQE = 0x304,
101 MLX5_CMD_OP_CREATE_CQ = 0x400,
102 MLX5_CMD_OP_DESTROY_CQ = 0x401,
103 MLX5_CMD_OP_QUERY_CQ = 0x402,
104 MLX5_CMD_OP_MODIFY_CQ = 0x403,
105 MLX5_CMD_OP_CREATE_QP = 0x500,
106 MLX5_CMD_OP_DESTROY_QP = 0x501,
107 MLX5_CMD_OP_RST2INIT_QP = 0x502,
108 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
109 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
110 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
112 MLX5_CMD_OP_2ERR_QP = 0x507,
113 MLX5_CMD_OP_2RST_QP = 0x50a,
114 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
117 MLX5_CMD_OP_CREATE_PSV = 0x600,
118 MLX5_CMD_OP_DESTROY_PSV = 0x601,
119 MLX5_CMD_OP_CREATE_SRQ = 0x700,
120 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
121 MLX5_CMD_OP_QUERY_SRQ = 0x702,
122 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 127 MLX5_CMD_OP_CREATE_DCT = 0x710,
128 MLX5_CMD_OP_DESTROY_DCT = 0x711,
129 MLX5_CMD_OP_DRAIN_DCT = 0x712,
130 MLX5_CMD_OP_QUERY_DCT = 0x713,
131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 132 MLX5_CMD_OP_CREATE_XRQ = 0x717,
133 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
134 MLX5_CMD_OP_QUERY_XRQ = 0x719,
135 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 136 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
137 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 143 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 148 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 149 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
150 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
151 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
152 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
37e92a9d 153 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 154 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 155 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
156 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
157 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
158 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
159 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
160 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 161 MLX5_CMD_OP_ALLOC_PD = 0x800,
162 MLX5_CMD_OP_DEALLOC_PD = 0x801,
163 MLX5_CMD_OP_ALLOC_UAR = 0x802,
164 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
165 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
166 MLX5_CMD_OP_ACCESS_REG = 0x805,
167 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 168 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 169 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
170 MLX5_CMD_OP_MAD_IFC = 0x50d,
171 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
172 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
173 MLX5_CMD_OP_NOP = 0x80d,
174 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
175 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 176 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
177 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
178 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
179 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
180 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
181 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
182 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
183 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
184 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
185 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
186 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
187 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 188 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
189 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 190 MLX5_CMD_OP_CREATE_LAG = 0x840,
191 MLX5_CMD_OP_MODIFY_LAG = 0x841,
192 MLX5_CMD_OP_QUERY_LAG = 0x842,
193 MLX5_CMD_OP_DESTROY_LAG = 0x843,
194 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
195 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 196 MLX5_CMD_OP_CREATE_TIR = 0x900,
197 MLX5_CMD_OP_MODIFY_TIR = 0x901,
198 MLX5_CMD_OP_DESTROY_TIR = 0x902,
199 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 200 MLX5_CMD_OP_CREATE_SQ = 0x904,
201 MLX5_CMD_OP_MODIFY_SQ = 0x905,
202 MLX5_CMD_OP_DESTROY_SQ = 0x906,
203 MLX5_CMD_OP_QUERY_SQ = 0x907,
204 MLX5_CMD_OP_CREATE_RQ = 0x908,
205 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 206 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 207 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
208 MLX5_CMD_OP_QUERY_RQ = 0x90b,
209 MLX5_CMD_OP_CREATE_RMP = 0x90c,
210 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
211 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
212 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 213 MLX5_CMD_OP_CREATE_TIS = 0x912,
214 MLX5_CMD_OP_MODIFY_TIS = 0x913,
215 MLX5_CMD_OP_DESTROY_TIS = 0x914,
216 MLX5_CMD_OP_QUERY_TIS = 0x915,
217 MLX5_CMD_OP_CREATE_RQT = 0x916,
218 MLX5_CMD_OP_MODIFY_RQT = 0x917,
219 MLX5_CMD_OP_DESTROY_RQT = 0x918,
220 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 221 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 222 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
223 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
224 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
225 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
226 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
227 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
228 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
229 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 230 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 231 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
232 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
233 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 234 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 235 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
236 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 237 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
238 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 239 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
240 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
241 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
242 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
243 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 244 MLX5_CMD_OP_MAX
e281682b
SM		 245};
246
247struct mlx5_ifc_flow_table_fields_supported_bits {
248 u8 outer_dmac[0x1];
249 u8 outer_smac[0x1];
250 u8 outer_ether_type[0x1];
19cc7524 251 u8 outer_ip_version[0x1];
e281682b
SM		 252 u8 outer_first_prio[0x1];
253 u8 outer_first_cfi[0x1];
254 u8 outer_first_vid[0x1];
a8ade55f 255 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 256 u8 outer_second_prio[0x1];
257 u8 outer_second_cfi[0x1];
258 u8 outer_second_vid[0x1];
b4ff3a36 259 u8 reserved_at_b[0x1];
e281682b
SM		 260 u8 outer_sip[0x1];
261 u8 outer_dip[0x1];
262 u8 outer_frag[0x1];
263 u8 outer_ip_protocol[0x1];
264 u8 outer_ip_ecn[0x1];
265 u8 outer_ip_dscp[0x1];
266 u8 outer_udp_sport[0x1];
267 u8 outer_udp_dport[0x1];
268 u8 outer_tcp_sport[0x1];
269 u8 outer_tcp_dport[0x1];
270 u8 outer_tcp_flags[0x1];
271 u8 outer_gre_protocol[0x1];
272 u8 outer_gre_key[0x1];
273 u8 outer_vxlan_vni[0x1];
b4ff3a36 274 u8 reserved_at_1a[0x5];
e281682b
SM		 275 u8 source_eswitch_port[0x1];
276
277 u8 inner_dmac[0x1];
278 u8 inner_smac[0x1];
279 u8 inner_ether_type[0x1];
19cc7524 280 u8 inner_ip_version[0x1];
e281682b
SM		 281 u8 inner_first_prio[0x1];
282 u8 inner_first_cfi[0x1];
283 u8 inner_first_vid[0x1];
b4ff3a36 284 u8 reserved_at_27[0x1];
e281682b
SM		 285 u8 inner_second_prio[0x1];
286 u8 inner_second_cfi[0x1];
287 u8 inner_second_vid[0x1];
b4ff3a36 288 u8 reserved_at_2b[0x1];
e281682b
SM		 289 u8 inner_sip[0x1];
290 u8 inner_dip[0x1];
291 u8 inner_frag[0x1];
292 u8 inner_ip_protocol[0x1];
293 u8 inner_ip_ecn[0x1];
294 u8 inner_ip_dscp[0x1];
295 u8 inner_udp_sport[0x1];
296 u8 inner_udp_dport[0x1];
297 u8 inner_tcp_sport[0x1];
298 u8 inner_tcp_dport[0x1];
299 u8 inner_tcp_flags[0x1];
b4ff3a36 300 u8 reserved_at_37[0x9];
3346c487
BP		 301 u8 reserved_at_40[0x17];
302 u8 outer_esp_spi[0x1];
303 u8 reserved_at_58[0x2];
a550ddfc 304 u8 bth_dst_qp[0x1];
e281682b 305
a550ddfc 306 u8 reserved_at_5b[0x25];
e281682b
SM		 307};
308
309struct mlx5_ifc_flow_table_prop_layout_bits {
310 u8 ft_support[0x1];
9dc0b289
AV		 311 u8 reserved_at_1[0x1];
312 u8 flow_counter[0x1];
26a81453 313 u8 flow_modify_en[0x1];
2cc43b49 314 u8 modify_root[0x1];
34a40e68
MG		 315 u8 identified_miss_table_mode[0x1];
316 u8 flow_table_modify[0x1];
7adbde20
HHZ		 317 u8 encap[0x1];
318 u8 decap[0x1];
0c06897a
OG		 319 u8 reserved_at_9[0x1];
320 u8 pop_vlan[0x1];
321 u8 push_vlan[0x1];
322 u8 reserved_at_c[0x14];
e281682b 323
b4ff3a36 324 u8 reserved_at_20[0x2];
e281682b 325 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 326 u8 log_max_modify_header_context[0x8];
327 u8 max_modify_header_actions[0x8];
e281682b
SM		 328 u8 max_ft_level[0x8];
329
b4ff3a36 330 u8 reserved_at_40[0x20];
e281682b 331
b4ff3a36 332 u8 reserved_at_60[0x18];
e281682b
SM		 333 u8 log_max_ft_num[0x8];
334
b4ff3a36 335 u8 reserved_at_80[0x18];
e281682b
SM		 336 u8 log_max_destination[0x8];
337
16f1c5bb
RS		 338 u8 log_max_flow_counter[0x8];
339 u8 reserved_at_a8[0x10];
e281682b
SM		 340 u8 log_max_flow[0x8];
341
b4ff3a36 342 u8 reserved_at_c0[0x40];
e281682b
SM		 343
344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
345
346 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
347};
348
349struct mlx5_ifc_odp_per_transport_service_cap_bits {
350 u8 send[0x1];
351 u8 receive[0x1];
352 u8 write[0x1];
353 u8 read[0x1];
17d2f88f 354 u8 atomic[0x1];
e281682b 355 u8 srq_receive[0x1];
b4ff3a36 356 u8 reserved_at_6[0x1a];
e281682b
SM		 357};
358
b4d1f032 359struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 360 u8 reserved_at_0[0x60];
b4d1f032
MG		 361
362 u8 ipv4[0x20];
363};
364
365struct mlx5_ifc_ipv6_layout_bits {
366 u8 ipv6[16][0x8];
367};
368
369union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
370 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
371 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 372 u8 reserved_at_0[0x80];
b4d1f032
MG		 373};
374
e281682b
SM		 375struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
376 u8 smac_47_16[0x20];
377
378 u8 smac_15_0[0x10];
379 u8 ethertype[0x10];
380
381 u8 dmac_47_16[0x20];
382
383 u8 dmac_15_0[0x10];
384 u8 first_prio[0x3];
385 u8 first_cfi[0x1];
386 u8 first_vid[0xc];
387
388 u8 ip_protocol[0x8];
389 u8 ip_dscp[0x6];
390 u8 ip_ecn[0x2];
10543365
MHY		 391 u8 cvlan_tag[0x1];
392 u8 svlan_tag[0x1];
e281682b 393 u8 frag[0x1];
19cc7524 394 u8 ip_version[0x4];
e281682b
SM		 395 u8 tcp_flags[0x9];
396
397 u8 tcp_sport[0x10];
398 u8 tcp_dport[0x10];
399
a8ade55f
OG		 400 u8 reserved_at_c0[0x18];
401 u8 ttl_hoplimit[0x8];
e281682b
SM		 402
403 u8 udp_sport[0x10];
404 u8 udp_dport[0x10];
405
b4d1f032 406 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 407
b4d1f032 408 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 409};
410
411struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 412 u8 reserved_at_0[0x8];
413 u8 source_sqn[0x18];
e281682b 414
3e99df87 415 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 416 u8 source_port[0x10];
417
418 u8 outer_second_prio[0x3];
419 u8 outer_second_cfi[0x1];
420 u8 outer_second_vid[0xc];
421 u8 inner_second_prio[0x3];
422 u8 inner_second_cfi[0x1];
423 u8 inner_second_vid[0xc];
424
10543365
MHY		 425 u8 outer_second_cvlan_tag[0x1];
426 u8 inner_second_cvlan_tag[0x1];
427 u8 outer_second_svlan_tag[0x1];
428 u8 inner_second_svlan_tag[0x1];
429 u8 reserved_at_64[0xc];
e281682b
SM		 430 u8 gre_protocol[0x10];
431
432 u8 gre_key_h[0x18];
433 u8 gre_key_l[0x8];
434
435 u8 vxlan_vni[0x18];
b4ff3a36 436 u8 reserved_at_b8[0x8];
e281682b 437
b4ff3a36 438 u8 reserved_at_c0[0x20];
e281682b 439
b4ff3a36 440 u8 reserved_at_e0[0xc];
e281682b
SM		 441 u8 outer_ipv6_flow_label[0x14];
442
b4ff3a36 443 u8 reserved_at_100[0xc];
e281682b
SM		 444 u8 inner_ipv6_flow_label[0x14];
445
a550ddfc
YH		 446 u8 reserved_at_120[0x28];
447 u8 bth_dst_qp[0x18];
3346c487
BP		 448 u8 reserved_at_160[0x20];
449 u8 outer_esp_spi[0x20];
450 u8 reserved_at_1a0[0x60];
e281682b
SM		 451};
452
453struct mlx5_ifc_cmd_pas_bits {
454 u8 pa_h[0x20];
455
456 u8 pa_l[0x14];
b4ff3a36 457 u8 reserved_at_34[0xc];
e281682b
SM		 458};
459
460struct mlx5_ifc_uint64_bits {
461 u8 hi[0x20];
462
463 u8 lo[0x20];
464};
465
466enum {
467 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
468 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
469 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
470 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
471 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
472 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
473 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
474 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
475 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
476 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
477};
478
479struct mlx5_ifc_ads_bits {
480 u8 fl[0x1];
481 u8 free_ar[0x1];
b4ff3a36 482 u8 reserved_at_2[0xe];
e281682b
SM		 483 u8 pkey_index[0x10];
484
b4ff3a36 485 u8 reserved_at_20[0x8];
e281682b
SM		 486 u8 grh[0x1];
487 u8 mlid[0x7];
488 u8 rlid[0x10];
489
490 u8 ack_timeout[0x5];
b4ff3a36 491 u8 reserved_at_45[0x3];
e281682b 492 u8 src_addr_index[0x8];
b4ff3a36 493 u8 reserved_at_50[0x4];
e281682b
SM		 494 u8 stat_rate[0x4];
495 u8 hop_limit[0x8];
496
b4ff3a36 497 u8 reserved_at_60[0x4];
e281682b
SM		 498 u8 tclass[0x8];
499 u8 flow_label[0x14];
500
501 u8 rgid_rip[16][0x8];
502
b4ff3a36 503 u8 reserved_at_100[0x4];
e281682b
SM		 504 u8 f_dscp[0x1];
505 u8 f_ecn[0x1];
b4ff3a36 506 u8 reserved_at_106[0x1];
e281682b
SM		 507 u8 f_eth_prio[0x1];
508 u8 ecn[0x2];
509 u8 dscp[0x6];
510 u8 udp_sport[0x10];
511
512 u8 dei_cfi[0x1];
513 u8 eth_prio[0x3];
514 u8 sl[0x4];
32f69e4b 515 u8 vhca_port_num[0x8];
e281682b
SM		 516 u8 rmac_47_32[0x10];
517
518 u8 rmac_31_0[0x20];
519};
520
521struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 522 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 523 u8 nic_rx_multi_path_tirs_fts[0x1];
524 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
525 u8 reserved_at_3[0x1fd];
e281682b
SM		 526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
528
b4ff3a36 529 u8 reserved_at_400[0x200];
e281682b
SM		 530
531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
532
533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
534
b4ff3a36 535 u8 reserved_at_a00[0x200];
e281682b
SM		 536
537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
538
b4ff3a36 539 u8 reserved_at_e00[0x7200];
e281682b
SM		 540};
541
495716b1 542struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 543 u8 reserved_at_0[0x200];
495716b1
SM		 544
545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
546
547 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
548
549 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
550
b4ff3a36 551 u8 reserved_at_800[0x7800];
495716b1
SM		 552};
553
d6666753
SM		 554struct mlx5_ifc_e_switch_cap_bits {
555 u8 vport_svlan_strip[0x1];
556 u8 vport_cvlan_strip[0x1];
557 u8 vport_svlan_insert[0x1];
558 u8 vport_cvlan_insert_if_not_exist[0x1];
559 u8 vport_cvlan_insert_overwrite[0x1];
a6d04569
RD		 560 u8 reserved_at_5[0x18];
561 u8 merged_eswitch[0x1];
23898c76
NO		 562 u8 nic_vport_node_guid_modify[0x1];
563 u8 nic_vport_port_guid_modify[0x1];
d6666753 564
7adbde20
HHZ		 565 u8 vxlan_encap_decap[0x1];
566 u8 nvgre_encap_decap[0x1];
567 u8 reserved_at_22[0x9];
568 u8 log_max_encap_headers[0x5];
569 u8 reserved_2b[0x6];
570 u8 max_encap_header_size[0xa];
571
572 u8 reserved_40[0x7c0];
573
d6666753
SM		 574};
575
7486216b
SM		 576struct mlx5_ifc_qos_cap_bits {
577 u8 packet_pacing[0x1];
813f8540 578 u8 esw_scheduling[0x1];
c9497c98
MHY		 579 u8 esw_bw_share[0x1];
580 u8 esw_rate_limit[0x1];
05d3ac97
BW		 581 u8 reserved_at_4[0x1];
582 u8 packet_pacing_burst_bound[0x1];
583 u8 packet_pacing_typical_size[0x1];
584 u8 reserved_at_7[0x19];
813f8540
MHY		 585
586 u8 reserved_at_20[0x20];
587
7486216b 588 u8 packet_pacing_max_rate[0x20];
813f8540 589
7486216b 590 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 591
592 u8 reserved_at_80[0x10];
7486216b 593 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 594
595 u8 esw_element_type[0x10];
596 u8 esw_tsar_type[0x10];
597
598 u8 reserved_at_c0[0x10];
599 u8 max_qos_para_vport[0x10];
600
601 u8 max_tsar_bw_share[0x20];
602
603 u8 reserved_at_100[0x700];
7486216b
SM		 604};
605
2fcb12df
IK		 606struct mlx5_ifc_debug_cap_bits {
607 u8 reserved_at_0[0x20];
608
609 u8 reserved_at_20[0x2];
610 u8 stall_detect[0x1];
611 u8 reserved_at_23[0x1d];
612
613 u8 reserved_at_40[0x7c0];
614};
615
e281682b
SM		 616struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
617 u8 csum_cap[0x1];
618 u8 vlan_cap[0x1];
619 u8 lro_cap[0x1];
620 u8 lro_psh_flag[0x1];
621 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 622 u8 reserved_at_5[0x2];
623 u8 wqe_vlan_insert[0x1];
66189961 624 u8 self_lb_en_modifiable[0x1];
b4ff3a36 625 u8 reserved_at_9[0x2];
e281682b 626 u8 max_lso_cap[0x5];
c226dc22 627 u8 multi_pkt_send_wqe[0x2];
cff92d7c 628 u8 wqe_inline_mode[0x2];
e281682b 629 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 630 u8 reg_umr_sq[0x1];
631 u8 scatter_fcs[0x1];
050da902 632 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 633 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 634 u8 reserved_at_1c[0x2];
27299841 635 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 636 u8 tunnel_stateless_vxlan[0x1];
637
547eede0
IT		 638 u8 swp[0x1];
639 u8 swp_csum[0x1];
640 u8 swp_lso[0x1];
4d350f1f
MG		 641 u8 reserved_at_23[0x1b];
642 u8 max_geneve_opt_len[0x1];
643 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 644
b4ff3a36 645 u8 reserved_at_40[0x10];
e281682b
SM		 646 u8 lro_min_mss_size[0x10];
647
b4ff3a36 648 u8 reserved_at_60[0x120];
e281682b
SM		 649
650 u8 lro_timer_supported_periods[4][0x20];
651
b4ff3a36 652 u8 reserved_at_200[0x600];
e281682b
SM		 653};
654
655struct mlx5_ifc_roce_cap_bits {
656 u8 roce_apm[0x1];
b4ff3a36 657 u8 reserved_at_1[0x1f];
e281682b 658
b4ff3a36 659 u8 reserved_at_20[0x60];
e281682b 660
b4ff3a36 661 u8 reserved_at_80[0xc];
e281682b 662 u8 l3_type[0x4];
b4ff3a36 663 u8 reserved_at_90[0x8];
e281682b
SM		 664 u8 roce_version[0x8];
665
b4ff3a36 666 u8 reserved_at_a0[0x10];
e281682b
SM		 667 u8 r_roce_dest_udp_port[0x10];
668
669 u8 r_roce_max_src_udp_port[0x10];
670 u8 r_roce_min_src_udp_port[0x10];
671
b4ff3a36 672 u8 reserved_at_e0[0x10];
e281682b
SM		 673 u8 roce_address_table_size[0x10];
674
b4ff3a36 675 u8 reserved_at_100[0x700];
e281682b
SM		 676};
677
e72bd817
AL		 678struct mlx5_ifc_device_mem_cap_bits {
679 u8 memic[0x1];
680 u8 reserved_at_1[0x1f];
681
682 u8 reserved_at_20[0xb];
683 u8 log_min_memic_alloc_size[0x5];
684 u8 reserved_at_30[0x8];
685 u8 log_max_memic_addr_alignment[0x8];
686
687 u8 memic_bar_start_addr[0x40];
688
689 u8 memic_bar_size[0x20];
690
691 u8 max_memic_size[0x20];
692
693 u8 reserved_at_c0[0x740];
694};
695
e281682b
SM		 696enum {
697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
702 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
703 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
704 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
705 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
706};
707
708enum {
709 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
710 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
711 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
712 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
713 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
714 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
715 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
716 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
717 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
718};
719
720struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 721 u8 reserved_at_0[0x40];
e281682b 722
bd10838a 723 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 724 u8 reserved_at_42[0x4];
bd10838a 725 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 726
b4ff3a36 727 u8 reserved_at_47[0x19];
e281682b 728
b4ff3a36 729 u8 reserved_at_60[0x20];
e281682b 730
b4ff3a36 731 u8 reserved_at_80[0x10];
f91e6d89 732 u8 atomic_operations[0x10];
e281682b 733
b4ff3a36 734 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 735 u8 atomic_size_qp[0x10];
736
b4ff3a36 737 u8 reserved_at_c0[0x10];
e281682b
SM		 738 u8 atomic_size_dc[0x10];
739
b4ff3a36 740 u8 reserved_at_e0[0x720];
e281682b
SM		 741};
742
743struct mlx5_ifc_odp_cap_bits {
b4ff3a36 744 u8 reserved_at_0[0x40];
e281682b
SM		 745
746 u8 sig[0x1];
b4ff3a36 747 u8 reserved_at_41[0x1f];
e281682b 748
b4ff3a36 749 u8 reserved_at_60[0x20];
e281682b
SM		 750
751 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
752
753 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
754
755 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
756
b4ff3a36 757 u8 reserved_at_e0[0x720];
e281682b
SM		 758};
759
3f0393a5
SG		 760struct mlx5_ifc_calc_op {
761 u8 reserved_at_0[0x10];
762 u8 reserved_at_10[0x9];
763 u8 op_swap_endianness[0x1];
764 u8 op_min[0x1];
765 u8 op_xor[0x1];
766 u8 op_or[0x1];
767 u8 op_and[0x1];
768 u8 op_max[0x1];
769 u8 op_add[0x1];
770};
771
772struct mlx5_ifc_vector_calc_cap_bits {
773 u8 calc_matrix[0x1];
774 u8 reserved_at_1[0x1f];
775 u8 reserved_at_20[0x8];
776 u8 max_vec_count[0x8];
777 u8 reserved_at_30[0xd];
778 u8 max_chunk_size[0x3];
779 struct mlx5_ifc_calc_op calc0;
780 struct mlx5_ifc_calc_op calc1;
781 struct mlx5_ifc_calc_op calc2;
782 struct mlx5_ifc_calc_op calc3;
783
784 u8 reserved_at_e0[0x720];
785};
786
e281682b
SM		 787enum {
788 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
789 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 790 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 791 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 792};
793
794enum {
795 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
796 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
797};
798
799enum {
800 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
801 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
802 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
803 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
804 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
805};
806
807enum {
808 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
809 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
810 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
811 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
812 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
813 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
814};
815
816enum {
817 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
818 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
819};
820
821enum {
822 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
823 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
824 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
825};
826
827enum {
828 MLX5_CAP_PORT_TYPE_IB = 0x0,
829 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 830};
831
1410a90a
MG		 832enum {
833 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
834 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
835 MLX5_CAP_UMR_FENCE_NONE = 0x2,
836};
837
b775516b 838struct mlx5_ifc_cmd_hca_cap_bits {
32f69e4b
DJ		 839 u8 reserved_at_0[0x30];
840 u8 vhca_id[0x10];
841
842 u8 reserved_at_40[0x40];
b775516b
EC		 843
844 u8 log_max_srq_sz[0x8];
845 u8 log_max_qp_sz[0x8];
b4ff3a36 846 u8 reserved_at_90[0xb];
b775516b
EC		 847 u8 log_max_qp[0x5];
848
b4ff3a36 849 u8 reserved_at_a0[0xb];
e281682b 850 u8 log_max_srq[0x5];
b4ff3a36 851 u8 reserved_at_b0[0x10];
b775516b 852
b4ff3a36 853 u8 reserved_at_c0[0x8];
b775516b 854 u8 log_max_cq_sz[0x8];
b4ff3a36 855 u8 reserved_at_d0[0xb];
b775516b
EC		 856 u8 log_max_cq[0x5];
857
858 u8 log_max_eq_sz[0x8];
b4ff3a36 859 u8 reserved_at_e8[0x2];
b775516b 860 u8 log_max_mkey[0x6];
b4ff3a36 861 u8 reserved_at_f0[0xc];
b775516b
EC		 862 u8 log_max_eq[0x4];
863
864 u8 max_indirection[0x8];
bcda1aca 865 u8 fixed_buffer_size[0x1];
b775516b 866 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 867 u8 force_teardown[0x1];
868 u8 reserved_at_111[0x1];
b775516b 869 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 870 u8 umr_extended_translation_offset[0x1];
871 u8 null_mkey[0x1];
b775516b
EC		 872 u8 log_max_klm_list_size[0x6];
873
b4ff3a36 874 u8 reserved_at_120[0xa];
b775516b 875 u8 log_max_ra_req_dc[0x6];
b4ff3a36 876 u8 reserved_at_130[0xa];
b775516b
EC		 877 u8 log_max_ra_res_dc[0x6];
878
b4ff3a36 879 u8 reserved_at_140[0xa];
b775516b 880 u8 log_max_ra_req_qp[0x6];
b4ff3a36 881 u8 reserved_at_150[0xa];
b775516b
EC		 882 u8 log_max_ra_res_qp[0x6];
883
f32f5bd2 884 u8 end_pad[0x1];
b775516b
EC		 885 u8 cc_query_allowed[0x1];
886 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 887 u8 start_pad[0x1];
888 u8 cache_line_128byte[0x1];
c02762eb
HN		 889 u8 reserved_at_165[0xa];
890 u8 qcam_reg[0x1];
e281682b 891 u8 gid_table_size[0x10];
b775516b 892
e281682b
SM		 893 u8 out_of_seq_cnt[0x1];
894 u8 vport_counters[0x1];
7486216b 895 u8 retransmission_q_counters[0x1];
2fcb12df 896 u8 debug[0x1];
83b502a1 897 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 898 u8 rq_delay_drop[0x1];
b775516b
EC		 899 u8 max_qp_cnt[0xa];
900 u8 pkey_table_size[0x10];
901
e281682b
SM		 902 u8 vport_group_manager[0x1];
903 u8 vhca_group_manager[0x1];
904 u8 ib_virt[0x1];
905 u8 eth_virt[0x1];
61c5b5c9 906 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 907 u8 ets[0x1];
908 u8 nic_flow_table[0x1];
54f0a411 909 u8 eswitch_flow_table[0x1];
e72bd817 910 u8 device_memory[0x1];
cfdcbcea
GP		 911 u8 mcam_reg[0x1];
912 u8 pcam_reg[0x1];
b775516b 913 u8 local_ca_ack_delay[0x5];
4ce3bf2f 914 u8 port_module_event[0x1];
58dcb60a 915 u8 enhanced_error_q_counters[0x1];
7d5e1423 916 u8 ports_check[0x1];
7b13558f 917 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 918 u8 disable_link_up[0x1];
919 u8 beacon_led[0x1];
e281682b 920 u8 port_type[0x2];
b775516b
EC		 921 u8 num_ports[0x8];
922
f9a1ef72
EE		 923 u8 reserved_at_1c0[0x1];
924 u8 pps[0x1];
925 u8 pps_modify[0x1];
b775516b 926 u8 log_max_msg[0x5];
e1c9c62b 927 u8 reserved_at_1c8[0x4];
4f3961ee 928 u8 max_tc[0x4];
7486216b
SM		 929 u8 reserved_at_1d0[0x1];
930 u8 dcbx[0x1];
246ac981
MG		 931 u8 general_notification_event[0x1];
932 u8 reserved_at_1d3[0x2];
e29341fb 933 u8 fpga[0x1];
928cfe87
TT		 934 u8 rol_s[0x1];
935 u8 rol_g[0x1];
e1c9c62b 936 u8 reserved_at_1d8[0x1];
928cfe87
TT		 937 u8 wol_s[0x1];
938 u8 wol_g[0x1];
939 u8 wol_a[0x1];
940 u8 wol_b[0x1];
941 u8 wol_m[0x1];
942 u8 wol_u[0x1];
943 u8 wol_p[0x1];
b775516b
EC		 944
945 u8 stat_rate_support[0x10];
e1c9c62b 946 u8 reserved_at_1f0[0xc];
e281682b 947 u8 cqe_version[0x4];
b775516b 948
e281682b 949 u8 compact_address_vector[0x1];
7d5e1423 950 u8 striding_rq[0x1];
500a3d0d
ES		 951 u8 reserved_at_202[0x1];
952 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 953 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 954 u8 reserved_at_205[0x1];
955 u8 repeated_block_disabled[0x1];
956 u8 umr_modify_entity_size_disabled[0x1];
957 u8 umr_modify_atomic_disabled[0x1];
958 u8 umr_indirect_mkey_disabled[0x1];
1410a90a
MG		 959 u8 umr_fence[0x2];
960 u8 reserved_at_20c[0x3];
e281682b 961 u8 drain_sigerr[0x1];
b775516b
EC		 962 u8 cmdif_checksum[0x2];
963 u8 sigerr_cqe[0x1];
e1c9c62b 964 u8 reserved_at_213[0x1];
b775516b
EC		 965 u8 wq_signature[0x1];
966 u8 sctr_data_cqe[0x1];
e1c9c62b 967 u8 reserved_at_216[0x1];
b775516b
EC		 968 u8 sho[0x1];
969 u8 tph[0x1];
970 u8 rf[0x1];
e281682b 971 u8 dct[0x1];
7486216b 972 u8 qos[0x1];
e281682b 973 u8 eth_net_offloads[0x1];
b775516b
EC		 974 u8 roce[0x1];
975 u8 atomic[0x1];
e1c9c62b 976 u8 reserved_at_21f[0x1];
b775516b
EC		 977
978 u8 cq_oi[0x1];
979 u8 cq_resize[0x1];
980 u8 cq_moderation[0x1];
e1c9c62b 981 u8 reserved_at_223[0x3];
e281682b 982 u8 cq_eq_remap[0x1];
b775516b
EC		 983 u8 pg[0x1];
984 u8 block_lb_mc[0x1];
e1c9c62b 985 u8 reserved_at_229[0x1];
e281682b 986 u8 scqe_break_moderation[0x1];
7d5e1423 987 u8 cq_period_start_from_cqe[0x1];
b775516b 988 u8 cd[0x1];
e1c9c62b 989 u8 reserved_at_22d[0x1];
b775516b 990 u8 apm[0x1];
3f0393a5 991 u8 vector_calc[0x1];
7d5e1423 992 u8 umr_ptr_rlky[0x1];
d2370e0a 993 u8 imaicl[0x1];
e1c9c62b 994 u8 reserved_at_232[0x4];
b775516b
EC		 995 u8 qkv[0x1];
996 u8 pkv[0x1];
b11a4f9c
HE		 997 u8 set_deth_sqpn[0x1];
998 u8 reserved_at_239[0x3];
b775516b
EC		 999 u8 xrc[0x1];
1000 u8 ud[0x1];
1001 u8 uc[0x1];
1002 u8 rc[0x1];
1003
a6d51b68
EC		 1004 u8 uar_4k[0x1];
1005 u8 reserved_at_241[0x9];
b775516b 1006 u8 uar_sz[0x6];
e1c9c62b 1007 u8 reserved_at_250[0x8];
b775516b
EC		 1008 u8 log_pg_sz[0x8];
1009
1010 u8 bf[0x1];
0dbc6fe0 1011 u8 driver_version[0x1];
e281682b 1012 u8 pad_tx_eth_packet[0x1];
e1c9c62b 1013 u8 reserved_at_263[0x8];
b775516b 1014 u8 log_bf_reg_size[0x5];
84df61eb
AH		 1015
1016 u8 reserved_at_270[0xb];
1017 u8 lag_master[0x1];
1018 u8 num_lag_ports[0x4];
b775516b 1019
e1c9c62b 1020 u8 reserved_at_280[0x10];
b775516b
EC		 1021 u8 max_wqe_sz_sq[0x10];
1022
e1c9c62b 1023 u8 reserved_at_2a0[0x10];
b775516b
EC		 1024 u8 max_wqe_sz_rq[0x10];
1025
a8ffcc74 1026 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1027 u8 max_wqe_sz_sq_dc[0x10];
1028
e1c9c62b 1029 u8 reserved_at_2e0[0x7];
b775516b
EC		 1030 u8 max_qp_mcg[0x19];
1031
e1c9c62b 1032 u8 reserved_at_300[0x18];
b775516b
EC		 1033 u8 log_max_mcg[0x8];
1034
e1c9c62b 1035 u8 reserved_at_320[0x3];
e281682b 1036 u8 log_max_transport_domain[0x5];
e1c9c62b 1037 u8 reserved_at_328[0x3];
b775516b 1038 u8 log_max_pd[0x5];
e1c9c62b 1039 u8 reserved_at_330[0xb];
b775516b
EC		 1040 u8 log_max_xrcd[0x5];
1041
5c298143 1042 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1043 u8 receive_discard_vport_down[0x1];
1044 u8 transmit_discard_vport_down[0x1];
1045 u8 reserved_at_343[0x5];
a351a1b0 1046 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1047 u8 max_flow_counter_15_0[0x10];
a351a1b0 1048
b775516b 1049
e1c9c62b 1050 u8 reserved_at_360[0x3];
b775516b 1051 u8 log_max_rq[0x5];
e1c9c62b 1052 u8 reserved_at_368[0x3];
b775516b 1053 u8 log_max_sq[0x5];
e1c9c62b 1054 u8 reserved_at_370[0x3];
b775516b 1055 u8 log_max_tir[0x5];
e1c9c62b 1056 u8 reserved_at_378[0x3];
b775516b
EC		 1057 u8 log_max_tis[0x5];
1058
e281682b 1059 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1060 u8 reserved_at_381[0x2];
e281682b 1061 u8 log_max_rmp[0x5];
e1c9c62b 1062 u8 reserved_at_388[0x3];
e281682b 1063 u8 log_max_rqt[0x5];
e1c9c62b 1064 u8 reserved_at_390[0x3];
e281682b 1065 u8 log_max_rqt_size[0x5];
e1c9c62b 1066 u8 reserved_at_398[0x3];
b775516b
EC		 1067 u8 log_max_tis_per_sq[0x5];
1068
619a8f2a
TT		 1069 u8 ext_stride_num_range[0x1];
1070 u8 reserved_at_3a1[0x2];
e281682b 1071 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1072 u8 reserved_at_3a8[0x3];
e281682b 1073 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1074 u8 reserved_at_3b0[0x3];
e281682b 1075 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1076 u8 reserved_at_3b8[0x3];
e281682b
SM		 1077 u8 log_min_stride_sz_sq[0x5];
1078
40817cdb
OG		 1079 u8 hairpin[0x1];
1080 u8 reserved_at_3c1[0x2];
1081 u8 log_max_hairpin_queues[0x5];
1082 u8 reserved_at_3c8[0x3];
1083 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1084 u8 reserved_at_3d0[0x3];
1085 u8 log_max_hairpin_num_packets[0x5];
1086 u8 reserved_at_3d8[0x3];
e281682b
SM		 1087 u8 log_max_wq_sz[0x5];
1088
54f0a411 1089 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1090 u8 disable_local_lb_uc[0x1];
1091 u8 disable_local_lb_mc[0x1];
40817cdb
OG		 1092 u8 log_min_hairpin_wq_data_sz[0x5];
1093 u8 reserved_at_3e8[0x3];
54f0a411 1094 u8 log_max_vlan_list[0x5];
e1c9c62b 1095 u8 reserved_at_3f0[0x3];
54f0a411 1096 u8 log_max_current_mc_list[0x5];
e1c9c62b 1097 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1098 u8 log_max_current_uc_list[0x5];
1099
e1c9c62b 1100 u8 reserved_at_400[0x80];
54f0a411 1101
e1c9c62b 1102 u8 reserved_at_480[0x3];
e281682b 1103 u8 log_max_l2_table[0x5];
e1c9c62b 1104 u8 reserved_at_488[0x8];
b775516b
EC		 1105 u8 log_uar_page_sz[0x10];
1106
e1c9c62b 1107 u8 reserved_at_4a0[0x20];
048ccca8 1108 u8 device_frequency_mhz[0x20];
b0844444 1109 u8 device_frequency_khz[0x20];
e1c9c62b 1110
a6d51b68
EC		 1111 u8 reserved_at_500[0x20];
1112 u8 num_of_uars_per_page[0x20];
1113 u8 reserved_at_540[0x40];
e1c9c62b 1114
0ff8e79c
GL		 1115 u8 reserved_at_580[0x3d];
1116 u8 cqe_128_always[0x1];
1117 u8 cqe_compression_128[0x1];
7d5e1423 1118 u8 cqe_compression[0x1];
b775516b 1119
7d5e1423
SM		 1120 u8 cqe_compression_timeout[0x10];
1121 u8 cqe_compression_max_num[0x10];
b775516b 1122
7486216b
SM		 1123 u8 reserved_at_5e0[0x10];
1124 u8 tag_matching[0x1];
1125 u8 rndv_offload_rc[0x1];
1126 u8 rndv_offload_dc[0x1];
1127 u8 log_tag_matching_list_sz[0x5];
7b13558f 1128 u8 reserved_at_5f8[0x3];
7486216b
SM		 1129 u8 log_max_xrq[0x5];
1130
32f69e4b
DJ		 1131 u8 affiliate_nic_vport_criteria[0x8];
1132 u8 native_port_num[0x8];
1133 u8 num_vhca_ports[0x8];
1134 u8 reserved_at_618[0x6];
1135 u8 sw_owner_id[0x1];
8737f818 1136 u8 reserved_at_61f[0x1e1];
b775516b
EC		 1137};
1138
81848731
SM		 1139enum mlx5_flow_destination_type {
1140 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1141 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1142 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db 1143
5f418378 1144 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
bd5251db 1145 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1146};
b775516b 1147
e281682b
SM		 1148struct mlx5_ifc_dest_format_struct_bits {
1149 u8 destination_type[0x8];
1150 u8 destination_id[0x18];
b17f7fc1
SK		 1151 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1152 u8 reserved_at_21[0xf];
1153 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1154};
1155
9dc0b289 1156struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1157 u8 flow_counter_id[0x20];
9dc0b289
AV		 1158
1159 u8 reserved_at_20[0x20];
1160};
1161
1162union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1163 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1164 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1165 u8 reserved_at_0[0x40];
1166};
1167
e281682b
SM		 1168struct mlx5_ifc_fte_match_param_bits {
1169 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1170
1171 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1172
1173 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1174
b4ff3a36 1175 u8 reserved_at_600[0xa00];
b775516b
EC		 1176};
1177
e281682b
SM		 1178enum {
1179 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1180 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1181 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1182 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1183 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1184};
b775516b 1185
e281682b
SM		 1186struct mlx5_ifc_rx_hash_field_select_bits {
1187 u8 l3_prot_type[0x1];
1188 u8 l4_prot_type[0x1];
1189 u8 selected_fields[0x1e];
1190};
b775516b 1191
e281682b
SM		 1192enum {
1193 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1194 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1195};
1196
e281682b
SM		 1197enum {
1198 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1199 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1200};
1201
1202struct mlx5_ifc_wq_bits {
1203 u8 wq_type[0x4];
1204 u8 wq_signature[0x1];
1205 u8 end_padding_mode[0x2];
1206 u8 cd_slave[0x1];
b4ff3a36 1207 u8 reserved_at_8[0x18];
b775516b 1208
e281682b
SM		 1209 u8 hds_skip_first_sge[0x1];
1210 u8 log2_hds_buf_size[0x3];
b4ff3a36 1211 u8 reserved_at_24[0x7];
e281682b
SM		 1212 u8 page_offset[0x5];
1213 u8 lwm[0x10];
b775516b 1214
b4ff3a36 1215 u8 reserved_at_40[0x8];
e281682b
SM		 1216 u8 pd[0x18];
1217
b4ff3a36 1218 u8 reserved_at_60[0x8];
e281682b
SM		 1219 u8 uar_page[0x18];
1220
1221 u8 dbr_addr[0x40];
1222
1223 u8 hw_counter[0x20];
1224
1225 u8 sw_counter[0x20];
1226
b4ff3a36 1227 u8 reserved_at_100[0xc];
e281682b 1228 u8 log_wq_stride[0x4];
b4ff3a36 1229 u8 reserved_at_110[0x3];
e281682b 1230 u8 log_wq_pg_sz[0x5];
b4ff3a36 1231 u8 reserved_at_118[0x3];
e281682b
SM		 1232 u8 log_wq_sz[0x5];
1233
4d533e0f
OG		 1234 u8 reserved_at_120[0x3];
1235 u8 log_hairpin_num_packets[0x5];
1236 u8 reserved_at_128[0x3];
40817cdb 1237 u8 log_hairpin_data_sz[0x5];
40817cdb 1238
619a8f2a
TT		 1239 u8 reserved_at_130[0x4];
1240 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 1241 u8 two_byte_shift_en[0x1];
1242 u8 reserved_at_139[0x4];
1243 u8 log_wqe_stride_size[0x3];
1244
1245 u8 reserved_at_140[0x4c0];
b775516b 1246
e281682b 1247 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1248};
1249
e281682b 1250struct mlx5_ifc_rq_num_bits {
b4ff3a36 1251 u8 reserved_at_0[0x8];
e281682b
SM		 1252 u8 rq_num[0x18];
1253};
b775516b 1254
e281682b 1255struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1256 u8 reserved_at_0[0x10];
e281682b 1257 u8 mac_addr_47_32[0x10];
b775516b 1258
e281682b
SM		 1259 u8 mac_addr_31_0[0x20];
1260};
1261
c0046cf7 1262struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1263 u8 reserved_at_0[0x14];
c0046cf7
SM		 1264 u8 vlan[0x0c];
1265
b4ff3a36 1266 u8 reserved_at_20[0x20];
c0046cf7
SM		 1267};
1268
e281682b 1269struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1270 u8 reserved_at_0[0xa0];
e281682b
SM		 1271
1272 u8 min_time_between_cnps[0x20];
1273
b4ff3a36 1274 u8 reserved_at_c0[0x12];
e281682b 1275 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1276 u8 reserved_at_d8[0x4];
1277 u8 cnp_prio_mode[0x1];
e281682b
SM		 1278 u8 cnp_802p_prio[0x3];
1279
b4ff3a36 1280 u8 reserved_at_e0[0x720];
e281682b
SM		 1281};
1282
1283struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1284 u8 reserved_at_0[0x60];
e281682b 1285
b4ff3a36 1286 u8 reserved_at_60[0x4];
e281682b 1287 u8 clamp_tgt_rate[0x1];
b4ff3a36 1288 u8 reserved_at_65[0x3];
e281682b 1289 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1290 u8 reserved_at_69[0x17];
e281682b 1291
b4ff3a36 1292 u8 reserved_at_80[0x20];
e281682b
SM		 1293
1294 u8 rpg_time_reset[0x20];
1295
1296 u8 rpg_byte_reset[0x20];
1297
1298 u8 rpg_threshold[0x20];
1299
1300 u8 rpg_max_rate[0x20];
1301
1302 u8 rpg_ai_rate[0x20];
1303
1304 u8 rpg_hai_rate[0x20];
1305
1306 u8 rpg_gd[0x20];
1307
1308 u8 rpg_min_dec_fac[0x20];
1309
1310 u8 rpg_min_rate[0x20];
1311
b4ff3a36 1312 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1313
1314 u8 rate_to_set_on_first_cnp[0x20];
1315
1316 u8 dce_tcp_g[0x20];
1317
1318 u8 dce_tcp_rtt[0x20];
1319
1320 u8 rate_reduce_monitor_period[0x20];
1321
b4ff3a36 1322 u8 reserved_at_320[0x20];
e281682b
SM		 1323
1324 u8 initial_alpha_value[0x20];
1325
b4ff3a36 1326 u8 reserved_at_360[0x4a0];
e281682b
SM		 1327};
1328
1329struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1330 u8 reserved_at_0[0x80];
e281682b
SM		 1331
1332 u8 rppp_max_rps[0x20];
1333
1334 u8 rpg_time_reset[0x20];
1335
1336 u8 rpg_byte_reset[0x20];
1337
1338 u8 rpg_threshold[0x20];
1339
1340 u8 rpg_max_rate[0x20];
1341
1342 u8 rpg_ai_rate[0x20];
1343
1344 u8 rpg_hai_rate[0x20];
1345
1346 u8 rpg_gd[0x20];
1347
1348 u8 rpg_min_dec_fac[0x20];
1349
1350 u8 rpg_min_rate[0x20];
1351
b4ff3a36 1352 u8 reserved_at_1c0[0x640];
e281682b
SM		 1353};
1354
1355enum {
1356 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1357 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1358 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1359};
1360
1361struct mlx5_ifc_resize_field_select_bits {
1362 u8 resize_field_select[0x20];
1363};
1364
1365enum {
1366 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1367 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1368 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1369 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1370};
1371
1372struct mlx5_ifc_modify_field_select_bits {
1373 u8 modify_field_select[0x20];
1374};
1375
1376struct mlx5_ifc_field_select_r_roce_np_bits {
1377 u8 field_select_r_roce_np[0x20];
1378};
1379
1380struct mlx5_ifc_field_select_r_roce_rp_bits {
1381 u8 field_select_r_roce_rp[0x20];
1382};
1383
1384enum {
1385 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1386 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1387 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1388 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1389 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1390 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1391 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1392 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1393 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1394 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1395};
1396
1397struct mlx5_ifc_field_select_802_1qau_rp_bits {
1398 u8 field_select_8021qaurp[0x20];
1399};
1400
1401struct mlx5_ifc_phys_layer_cntrs_bits {
1402 u8 time_since_last_clear_high[0x20];
1403
1404 u8 time_since_last_clear_low[0x20];
1405
1406 u8 symbol_errors_high[0x20];
1407
1408 u8 symbol_errors_low[0x20];
1409
1410 u8 sync_headers_errors_high[0x20];
1411
1412 u8 sync_headers_errors_low[0x20];
1413
1414 u8 edpl_bip_errors_lane0_high[0x20];
1415
1416 u8 edpl_bip_errors_lane0_low[0x20];
1417
1418 u8 edpl_bip_errors_lane1_high[0x20];
1419
1420 u8 edpl_bip_errors_lane1_low[0x20];
1421
1422 u8 edpl_bip_errors_lane2_high[0x20];
1423
1424 u8 edpl_bip_errors_lane2_low[0x20];
1425
1426 u8 edpl_bip_errors_lane3_high[0x20];
1427
1428 u8 edpl_bip_errors_lane3_low[0x20];
1429
1430 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1431
1432 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1433
1434 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1435
1436 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1437
1438 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1439
1440 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1441
1442 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1443
1444 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1445
1446 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1447
1448 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1449
1450 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1451
1452 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1453
1454 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1455
1456 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1457
1458 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1459
1460 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1461
1462 u8 rs_fec_corrected_blocks_high[0x20];
1463
1464 u8 rs_fec_corrected_blocks_low[0x20];
1465
1466 u8 rs_fec_uncorrectable_blocks_high[0x20];
1467
1468 u8 rs_fec_uncorrectable_blocks_low[0x20];
1469
1470 u8 rs_fec_no_errors_blocks_high[0x20];
1471
1472 u8 rs_fec_no_errors_blocks_low[0x20];
1473
1474 u8 rs_fec_single_error_blocks_high[0x20];
1475
1476 u8 rs_fec_single_error_blocks_low[0x20];
1477
1478 u8 rs_fec_corrected_symbols_total_high[0x20];
1479
1480 u8 rs_fec_corrected_symbols_total_low[0x20];
1481
1482 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1483
1484 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1485
1486 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1487
1488 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1489
1490 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1491
1492 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1493
1494 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1495
1496 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1497
1498 u8 link_down_events[0x20];
1499
1500 u8 successful_recovery_events[0x20];
1501
b4ff3a36 1502 u8 reserved_at_640[0x180];
e281682b
SM		 1503};
1504
d8dc0508
GP		 1505struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1506 u8 time_since_last_clear_high[0x20];
1507
1508 u8 time_since_last_clear_low[0x20];
1509
1510 u8 phy_received_bits_high[0x20];
1511
1512 u8 phy_received_bits_low[0x20];
1513
1514 u8 phy_symbol_errors_high[0x20];
1515
1516 u8 phy_symbol_errors_low[0x20];
1517
1518 u8 phy_corrected_bits_high[0x20];
1519
1520 u8 phy_corrected_bits_low[0x20];
1521
1522 u8 phy_corrected_bits_lane0_high[0x20];
1523
1524 u8 phy_corrected_bits_lane0_low[0x20];
1525
1526 u8 phy_corrected_bits_lane1_high[0x20];
1527
1528 u8 phy_corrected_bits_lane1_low[0x20];
1529
1530 u8 phy_corrected_bits_lane2_high[0x20];
1531
1532 u8 phy_corrected_bits_lane2_low[0x20];
1533
1534 u8 phy_corrected_bits_lane3_high[0x20];
1535
1536 u8 phy_corrected_bits_lane3_low[0x20];
1537
1538 u8 reserved_at_200[0x5c0];
1539};
1540
1c64bf6f
MY		 1541struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1542 u8 symbol_error_counter[0x10];
1543
1544 u8 link_error_recovery_counter[0x8];
1545
1546 u8 link_downed_counter[0x8];
1547
1548 u8 port_rcv_errors[0x10];
1549
1550 u8 port_rcv_remote_physical_errors[0x10];
1551
1552 u8 port_rcv_switch_relay_errors[0x10];
1553
1554 u8 port_xmit_discards[0x10];
1555
1556 u8 port_xmit_constraint_errors[0x8];
1557
1558 u8 port_rcv_constraint_errors[0x8];
1559
1560 u8 reserved_at_70[0x8];
1561
1562 u8 link_overrun_errors[0x8];
1563
1564 u8 reserved_at_80[0x10];
1565
1566 u8 vl_15_dropped[0x10];
1567
133bea04
TW		 1568 u8 reserved_at_a0[0x80];
1569
1570 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1571};
1572
e281682b
SM		 1573struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1574 u8 transmit_queue_high[0x20];
1575
1576 u8 transmit_queue_low[0x20];
1577
b4ff3a36 1578 u8 reserved_at_40[0x780];
e281682b
SM		 1579};
1580
1581struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1582 u8 rx_octets_high[0x20];
1583
1584 u8 rx_octets_low[0x20];
1585
b4ff3a36 1586 u8 reserved_at_40[0xc0];
e281682b
SM		 1587
1588 u8 rx_frames_high[0x20];
1589
1590 u8 rx_frames_low[0x20];
1591
1592 u8 tx_octets_high[0x20];
1593
1594 u8 tx_octets_low[0x20];
1595
b4ff3a36 1596 u8 reserved_at_180[0xc0];
e281682b
SM		 1597
1598 u8 tx_frames_high[0x20];
1599
1600 u8 tx_frames_low[0x20];
1601
1602 u8 rx_pause_high[0x20];
1603
1604 u8 rx_pause_low[0x20];
1605
1606 u8 rx_pause_duration_high[0x20];
1607
1608 u8 rx_pause_duration_low[0x20];
1609
1610 u8 tx_pause_high[0x20];
1611
1612 u8 tx_pause_low[0x20];
1613
1614 u8 tx_pause_duration_high[0x20];
1615
1616 u8 tx_pause_duration_low[0x20];
1617
1618 u8 rx_pause_transition_high[0x20];
1619
1620 u8 rx_pause_transition_low[0x20];
1621
2fcb12df
IK		 1622 u8 reserved_at_3c0[0x40];
1623
1624 u8 device_stall_minor_watermark_cnt_high[0x20];
1625
1626 u8 device_stall_minor_watermark_cnt_low[0x20];
1627
1628 u8 device_stall_critical_watermark_cnt_high[0x20];
1629
1630 u8 device_stall_critical_watermark_cnt_low[0x20];
1631
1632 u8 reserved_at_480[0x340];
e281682b
SM		 1633};
1634
1635struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1636 u8 port_transmit_wait_high[0x20];
1637
1638 u8 port_transmit_wait_low[0x20];
1639
2dba0797
GP		 1640 u8 reserved_at_40[0x100];
1641
1642 u8 rx_buffer_almost_full_high[0x20];
1643
1644 u8 rx_buffer_almost_full_low[0x20];
1645
1646 u8 rx_buffer_full_high[0x20];
1647
1648 u8 rx_buffer_full_low[0x20];
1649
1650 u8 reserved_at_1c0[0x600];
e281682b
SM		 1651};
1652
1653struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1654 u8 dot3stats_alignment_errors_high[0x20];
1655
1656 u8 dot3stats_alignment_errors_low[0x20];
1657
1658 u8 dot3stats_fcs_errors_high[0x20];
1659
1660 u8 dot3stats_fcs_errors_low[0x20];
1661
1662 u8 dot3stats_single_collision_frames_high[0x20];
1663
1664 u8 dot3stats_single_collision_frames_low[0x20];
1665
1666 u8 dot3stats_multiple_collision_frames_high[0x20];
1667
1668 u8 dot3stats_multiple_collision_frames_low[0x20];
1669
1670 u8 dot3stats_sqe_test_errors_high[0x20];
1671
1672 u8 dot3stats_sqe_test_errors_low[0x20];
1673
1674 u8 dot3stats_deferred_transmissions_high[0x20];
1675
1676 u8 dot3stats_deferred_transmissions_low[0x20];
1677
1678 u8 dot3stats_late_collisions_high[0x20];
1679
1680 u8 dot3stats_late_collisions_low[0x20];
1681
1682 u8 dot3stats_excessive_collisions_high[0x20];
1683
1684 u8 dot3stats_excessive_collisions_low[0x20];
1685
1686 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1687
1688 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1689
1690 u8 dot3stats_carrier_sense_errors_high[0x20];
1691
1692 u8 dot3stats_carrier_sense_errors_low[0x20];
1693
1694 u8 dot3stats_frame_too_longs_high[0x20];
1695
1696 u8 dot3stats_frame_too_longs_low[0x20];
1697
1698 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1699
1700 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1701
1702 u8 dot3stats_symbol_errors_high[0x20];
1703
1704 u8 dot3stats_symbol_errors_low[0x20];
1705
1706 u8 dot3control_in_unknown_opcodes_high[0x20];
1707
1708 u8 dot3control_in_unknown_opcodes_low[0x20];
1709
1710 u8 dot3in_pause_frames_high[0x20];
1711
1712 u8 dot3in_pause_frames_low[0x20];
1713
1714 u8 dot3out_pause_frames_high[0x20];
1715
1716 u8 dot3out_pause_frames_low[0x20];
1717
b4ff3a36 1718 u8 reserved_at_400[0x3c0];
e281682b
SM		 1719};
1720
1721struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1722 u8 ether_stats_drop_events_high[0x20];
1723
1724 u8 ether_stats_drop_events_low[0x20];
1725
1726 u8 ether_stats_octets_high[0x20];
1727
1728 u8 ether_stats_octets_low[0x20];
1729
1730 u8 ether_stats_pkts_high[0x20];
1731
1732 u8 ether_stats_pkts_low[0x20];
1733
1734 u8 ether_stats_broadcast_pkts_high[0x20];
1735
1736 u8 ether_stats_broadcast_pkts_low[0x20];
1737
1738 u8 ether_stats_multicast_pkts_high[0x20];
1739
1740 u8 ether_stats_multicast_pkts_low[0x20];
1741
1742 u8 ether_stats_crc_align_errors_high[0x20];
1743
1744 u8 ether_stats_crc_align_errors_low[0x20];
1745
1746 u8 ether_stats_undersize_pkts_high[0x20];
1747
1748 u8 ether_stats_undersize_pkts_low[0x20];
1749
1750 u8 ether_stats_oversize_pkts_high[0x20];
1751
1752 u8 ether_stats_oversize_pkts_low[0x20];
1753
1754 u8 ether_stats_fragments_high[0x20];
1755
1756 u8 ether_stats_fragments_low[0x20];
1757
1758 u8 ether_stats_jabbers_high[0x20];
1759
1760 u8 ether_stats_jabbers_low[0x20];
1761
1762 u8 ether_stats_collisions_high[0x20];
1763
1764 u8 ether_stats_collisions_low[0x20];
1765
1766 u8 ether_stats_pkts64octets_high[0x20];
1767
1768 u8 ether_stats_pkts64octets_low[0x20];
1769
1770 u8 ether_stats_pkts65to127octets_high[0x20];
1771
1772 u8 ether_stats_pkts65to127octets_low[0x20];
1773
1774 u8 ether_stats_pkts128to255octets_high[0x20];
1775
1776 u8 ether_stats_pkts128to255octets_low[0x20];
1777
1778 u8 ether_stats_pkts256to511octets_high[0x20];
1779
1780 u8 ether_stats_pkts256to511octets_low[0x20];
1781
1782 u8 ether_stats_pkts512to1023octets_high[0x20];
1783
1784 u8 ether_stats_pkts512to1023octets_low[0x20];
1785
1786 u8 ether_stats_pkts1024to1518octets_high[0x20];
1787
1788 u8 ether_stats_pkts1024to1518octets_low[0x20];
1789
1790 u8 ether_stats_pkts1519to2047octets_high[0x20];
1791
1792 u8 ether_stats_pkts1519to2047octets_low[0x20];
1793
1794 u8 ether_stats_pkts2048to4095octets_high[0x20];
1795
1796 u8 ether_stats_pkts2048to4095octets_low[0x20];
1797
1798 u8 ether_stats_pkts4096to8191octets_high[0x20];
1799
1800 u8 ether_stats_pkts4096to8191octets_low[0x20];
1801
1802 u8 ether_stats_pkts8192to10239octets_high[0x20];
1803
1804 u8 ether_stats_pkts8192to10239octets_low[0x20];
1805
b4ff3a36 1806 u8 reserved_at_540[0x280];
e281682b
SM		 1807};
1808
1809struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1810 u8 if_in_octets_high[0x20];
1811
1812 u8 if_in_octets_low[0x20];
1813
1814 u8 if_in_ucast_pkts_high[0x20];
1815
1816 u8 if_in_ucast_pkts_low[0x20];
1817
1818 u8 if_in_discards_high[0x20];
1819
1820 u8 if_in_discards_low[0x20];
1821
1822 u8 if_in_errors_high[0x20];
1823
1824 u8 if_in_errors_low[0x20];
1825
1826 u8 if_in_unknown_protos_high[0x20];
1827
1828 u8 if_in_unknown_protos_low[0x20];
1829
1830 u8 if_out_octets_high[0x20];
1831
1832 u8 if_out_octets_low[0x20];
1833
1834 u8 if_out_ucast_pkts_high[0x20];
1835
1836 u8 if_out_ucast_pkts_low[0x20];
1837
1838 u8 if_out_discards_high[0x20];
1839
1840 u8 if_out_discards_low[0x20];
1841
1842 u8 if_out_errors_high[0x20];
1843
1844 u8 if_out_errors_low[0x20];
1845
1846 u8 if_in_multicast_pkts_high[0x20];
1847
1848 u8 if_in_multicast_pkts_low[0x20];
1849
1850 u8 if_in_broadcast_pkts_high[0x20];
1851
1852 u8 if_in_broadcast_pkts_low[0x20];
1853
1854 u8 if_out_multicast_pkts_high[0x20];
1855
1856 u8 if_out_multicast_pkts_low[0x20];
1857
1858 u8 if_out_broadcast_pkts_high[0x20];
1859
1860 u8 if_out_broadcast_pkts_low[0x20];
1861
b4ff3a36 1862 u8 reserved_at_340[0x480];
e281682b
SM		 1863};
1864
1865struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1866 u8 a_frames_transmitted_ok_high[0x20];
1867
1868 u8 a_frames_transmitted_ok_low[0x20];
1869
1870 u8 a_frames_received_ok_high[0x20];
1871
1872 u8 a_frames_received_ok_low[0x20];
1873
1874 u8 a_frame_check_sequence_errors_high[0x20];
1875
1876 u8 a_frame_check_sequence_errors_low[0x20];
1877
1878 u8 a_alignment_errors_high[0x20];
1879
1880 u8 a_alignment_errors_low[0x20];
1881
1882 u8 a_octets_transmitted_ok_high[0x20];
1883
1884 u8 a_octets_transmitted_ok_low[0x20];
1885
1886 u8 a_octets_received_ok_high[0x20];
1887
1888 u8 a_octets_received_ok_low[0x20];
1889
1890 u8 a_multicast_frames_xmitted_ok_high[0x20];
1891
1892 u8 a_multicast_frames_xmitted_ok_low[0x20];
1893
1894 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1895
1896 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1897
1898 u8 a_multicast_frames_received_ok_high[0x20];
1899
1900 u8 a_multicast_frames_received_ok_low[0x20];
1901
1902 u8 a_broadcast_frames_received_ok_high[0x20];
1903
1904 u8 a_broadcast_frames_received_ok_low[0x20];
1905
1906 u8 a_in_range_length_errors_high[0x20];
1907
1908 u8 a_in_range_length_errors_low[0x20];
1909
1910 u8 a_out_of_range_length_field_high[0x20];
1911
1912 u8 a_out_of_range_length_field_low[0x20];
1913
1914 u8 a_frame_too_long_errors_high[0x20];
1915
1916 u8 a_frame_too_long_errors_low[0x20];
1917
1918 u8 a_symbol_error_during_carrier_high[0x20];
1919
1920 u8 a_symbol_error_during_carrier_low[0x20];
1921
1922 u8 a_mac_control_frames_transmitted_high[0x20];
1923
1924 u8 a_mac_control_frames_transmitted_low[0x20];
1925
1926 u8 a_mac_control_frames_received_high[0x20];
1927
1928 u8 a_mac_control_frames_received_low[0x20];
1929
1930 u8 a_unsupported_opcodes_received_high[0x20];
1931
1932 u8 a_unsupported_opcodes_received_low[0x20];
1933
1934 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1935
1936 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1937
1938 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1939
1940 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1941
b4ff3a36 1942 u8 reserved_at_4c0[0x300];
e281682b
SM		 1943};
1944
8ed1a630
GP		 1945struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1946 u8 life_time_counter_high[0x20];
1947
1948 u8 life_time_counter_low[0x20];
1949
1950 u8 rx_errors[0x20];
1951
1952 u8 tx_errors[0x20];
1953
1954 u8 l0_to_recovery_eieos[0x20];
1955
1956 u8 l0_to_recovery_ts[0x20];
1957
1958 u8 l0_to_recovery_framing[0x20];
1959
1960 u8 l0_to_recovery_retrain[0x20];
1961
1962 u8 crc_error_dllp[0x20];
1963
1964 u8 crc_error_tlp[0x20];
1965
efae7f78
EBE		 1966 u8 tx_overflow_buffer_pkt_high[0x20];
1967
1968 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 1969
1970 u8 outbound_stalled_reads[0x20];
1971
1972 u8 outbound_stalled_writes[0x20];
1973
1974 u8 outbound_stalled_reads_events[0x20];
1975
1976 u8 outbound_stalled_writes_events[0x20];
1977
1978 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 1979};
1980
e281682b
SM		 1981struct mlx5_ifc_cmd_inter_comp_event_bits {
1982 u8 command_completion_vector[0x20];
1983
b4ff3a36 1984 u8 reserved_at_20[0xc0];
e281682b
SM		 1985};
1986
1987struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1988 u8 reserved_at_0[0x18];
e281682b 1989 u8 port_num[0x1];
b4ff3a36 1990 u8 reserved_at_19[0x3];
e281682b
SM		 1991 u8 vl[0x4];
1992
b4ff3a36 1993 u8 reserved_at_20[0xa0];
e281682b
SM		 1994};
1995
1996struct mlx5_ifc_db_bf_congestion_event_bits {
1997 u8 event_subtype[0x8];
b4ff3a36 1998 u8 reserved_at_8[0x8];
e281682b 1999 u8 congestion_level[0x8];
b4ff3a36 2000 u8 reserved_at_18[0x8];
e281682b 2001
b4ff3a36 2002 u8 reserved_at_20[0xa0];
e281682b
SM		 2003};
2004
2005struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2006 u8 reserved_at_0[0x60];
e281682b
SM		 2007
2008 u8 gpio_event_hi[0x20];
2009
2010 u8 gpio_event_lo[0x20];
2011
b4ff3a36 2012 u8 reserved_at_a0[0x40];
e281682b
SM		 2013};
2014
2015struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2016 u8 reserved_at_0[0x40];
e281682b
SM		 2017
2018 u8 port_num[0x4];
b4ff3a36 2019 u8 reserved_at_44[0x1c];
e281682b 2020
b4ff3a36 2021 u8 reserved_at_60[0x80];
e281682b
SM		 2022};
2023
2024struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2025 u8 reserved_at_0[0xe0];
e281682b
SM		 2026};
2027
2028enum {
2029 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2030 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2031};
2032
2033struct mlx5_ifc_cq_error_bits {
b4ff3a36 2034 u8 reserved_at_0[0x8];
e281682b
SM		 2035 u8 cqn[0x18];
2036
b4ff3a36 2037 u8 reserved_at_20[0x20];
e281682b 2038
b4ff3a36 2039 u8 reserved_at_40[0x18];
e281682b
SM		 2040 u8 syndrome[0x8];
2041
b4ff3a36 2042 u8 reserved_at_60[0x80];
e281682b
SM		 2043};
2044
2045struct mlx5_ifc_rdma_page_fault_event_bits {
2046 u8 bytes_committed[0x20];
2047
2048 u8 r_key[0x20];
2049
b4ff3a36 2050 u8 reserved_at_40[0x10];
e281682b
SM		 2051 u8 packet_len[0x10];
2052
2053 u8 rdma_op_len[0x20];
2054
2055 u8 rdma_va[0x40];
2056
b4ff3a36 2057 u8 reserved_at_c0[0x5];
e281682b
SM		 2058 u8 rdma[0x1];
2059 u8 write[0x1];
2060 u8 requestor[0x1];
2061 u8 qp_number[0x18];
2062};
2063
2064struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2065 u8 bytes_committed[0x20];
2066
b4ff3a36 2067 u8 reserved_at_20[0x10];
e281682b
SM		 2068 u8 wqe_index[0x10];
2069
b4ff3a36 2070 u8 reserved_at_40[0x10];
e281682b
SM		 2071 u8 len[0x10];
2072
b4ff3a36 2073 u8 reserved_at_60[0x60];
e281682b 2074
b4ff3a36 2075 u8 reserved_at_c0[0x5];
e281682b
SM		 2076 u8 rdma[0x1];
2077 u8 write_read[0x1];
2078 u8 requestor[0x1];
2079 u8 qpn[0x18];
2080};
2081
2082struct mlx5_ifc_qp_events_bits {
b4ff3a36 2083 u8 reserved_at_0[0xa0];
e281682b
SM		 2084
2085 u8 type[0x8];
b4ff3a36 2086 u8 reserved_at_a8[0x18];
e281682b 2087
b4ff3a36 2088 u8 reserved_at_c0[0x8];
e281682b
SM		 2089 u8 qpn_rqn_sqn[0x18];
2090};
2091
2092struct mlx5_ifc_dct_events_bits {
b4ff3a36 2093 u8 reserved_at_0[0xc0];
e281682b 2094
b4ff3a36 2095 u8 reserved_at_c0[0x8];
e281682b
SM		 2096 u8 dct_number[0x18];
2097};
2098
2099struct mlx5_ifc_comp_event_bits {
b4ff3a36 2100 u8 reserved_at_0[0xc0];
e281682b 2101
b4ff3a36 2102 u8 reserved_at_c0[0x8];
e281682b
SM		 2103 u8 cq_number[0x18];
2104};
2105
2106enum {
2107 MLX5_QPC_STATE_RST = 0x0,
2108 MLX5_QPC_STATE_INIT = 0x1,
2109 MLX5_QPC_STATE_RTR = 0x2,
2110 MLX5_QPC_STATE_RTS = 0x3,
2111 MLX5_QPC_STATE_SQER = 0x4,
2112 MLX5_QPC_STATE_ERR = 0x6,
2113 MLX5_QPC_STATE_SQD = 0x7,
2114 MLX5_QPC_STATE_SUSPENDED = 0x9,
2115};
2116
2117enum {
2118 MLX5_QPC_ST_RC = 0x0,
2119 MLX5_QPC_ST_UC = 0x1,
2120 MLX5_QPC_ST_UD = 0x2,
2121 MLX5_QPC_ST_XRC = 0x3,
2122 MLX5_QPC_ST_DCI = 0x5,
2123 MLX5_QPC_ST_QP0 = 0x7,
2124 MLX5_QPC_ST_QP1 = 0x8,
2125 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2126 MLX5_QPC_ST_REG_UMR = 0xc,
2127};
2128
2129enum {
2130 MLX5_QPC_PM_STATE_ARMED = 0x0,
2131 MLX5_QPC_PM_STATE_REARM = 0x1,
2132 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2133 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2134};
2135
6e44636a
AK		 2136enum {
2137 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2138};
2139
e281682b
SM		 2140enum {
2141 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2142 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2143};
2144
2145enum {
2146 MLX5_QPC_MTU_256_BYTES = 0x1,
2147 MLX5_QPC_MTU_512_BYTES = 0x2,
2148 MLX5_QPC_MTU_1K_BYTES = 0x3,
2149 MLX5_QPC_MTU_2K_BYTES = 0x4,
2150 MLX5_QPC_MTU_4K_BYTES = 0x5,
2151 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2152};
2153
2154enum {
2155 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2156 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2157 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2158 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2159 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2160 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2161 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2162 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2163};
2164
2165enum {
2166 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2167 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2168 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2169};
2170
2171enum {
2172 MLX5_QPC_CS_RES_DISABLE = 0x0,
2173 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2174 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2175};
2176
2177struct mlx5_ifc_qpc_bits {
2178 u8 state[0x4];
84df61eb 2179 u8 lag_tx_port_affinity[0x4];
e281682b 2180 u8 st[0x8];
b4ff3a36 2181 u8 reserved_at_10[0x3];
e281682b 2182 u8 pm_state[0x2];
6e44636a
AK		 2183 u8 reserved_at_15[0x3];
2184 u8 offload_type[0x4];
e281682b 2185 u8 end_padding_mode[0x2];
b4ff3a36 2186 u8 reserved_at_1e[0x2];
e281682b
SM		 2187
2188 u8 wq_signature[0x1];
2189 u8 block_lb_mc[0x1];
2190 u8 atomic_like_write_en[0x1];
2191 u8 latency_sensitive[0x1];
b4ff3a36 2192 u8 reserved_at_24[0x1];
e281682b 2193 u8 drain_sigerr[0x1];
b4ff3a36 2194 u8 reserved_at_26[0x2];
e281682b
SM		 2195 u8 pd[0x18];
2196
2197 u8 mtu[0x3];
2198 u8 log_msg_max[0x5];
b4ff3a36 2199 u8 reserved_at_48[0x1];
e281682b
SM		 2200 u8 log_rq_size[0x4];
2201 u8 log_rq_stride[0x3];
2202 u8 no_sq[0x1];
2203 u8 log_sq_size[0x4];
b4ff3a36 2204 u8 reserved_at_55[0x6];
e281682b 2205 u8 rlky[0x1];
1015c2e8 2206 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2207
2208 u8 counter_set_id[0x8];
2209 u8 uar_page[0x18];
2210
b4ff3a36 2211 u8 reserved_at_80[0x8];
e281682b
SM		 2212 u8 user_index[0x18];
2213
b4ff3a36 2214 u8 reserved_at_a0[0x3];
e281682b
SM		 2215 u8 log_page_size[0x5];
2216 u8 remote_qpn[0x18];
2217
2218 struct mlx5_ifc_ads_bits primary_address_path;
2219
2220 struct mlx5_ifc_ads_bits secondary_address_path;
2221
2222 u8 log_ack_req_freq[0x4];
b4ff3a36 2223 u8 reserved_at_384[0x4];
e281682b 2224 u8 log_sra_max[0x3];
b4ff3a36 2225 u8 reserved_at_38b[0x2];
e281682b
SM		 2226 u8 retry_count[0x3];
2227 u8 rnr_retry[0x3];
b4ff3a36 2228 u8 reserved_at_393[0x1];
e281682b
SM		 2229 u8 fre[0x1];
2230 u8 cur_rnr_retry[0x3];
2231 u8 cur_retry_count[0x3];
b4ff3a36 2232 u8 reserved_at_39b[0x5];
e281682b 2233
b4ff3a36 2234 u8 reserved_at_3a0[0x20];
e281682b 2235
b4ff3a36 2236 u8 reserved_at_3c0[0x8];
e281682b
SM		 2237 u8 next_send_psn[0x18];
2238
b4ff3a36 2239 u8 reserved_at_3e0[0x8];
e281682b
SM		 2240 u8 cqn_snd[0x18];
2241
09a7d9ec
SM		 2242 u8 reserved_at_400[0x8];
2243 u8 deth_sqpn[0x18];
2244
2245 u8 reserved_at_420[0x20];
e281682b 2246
b4ff3a36 2247 u8 reserved_at_440[0x8];
e281682b
SM		 2248 u8 last_acked_psn[0x18];
2249
b4ff3a36 2250 u8 reserved_at_460[0x8];
e281682b
SM		 2251 u8 ssn[0x18];
2252
b4ff3a36 2253 u8 reserved_at_480[0x8];
e281682b 2254 u8 log_rra_max[0x3];
b4ff3a36 2255 u8 reserved_at_48b[0x1];
e281682b
SM		 2256 u8 atomic_mode[0x4];
2257 u8 rre[0x1];
2258 u8 rwe[0x1];
2259 u8 rae[0x1];
b4ff3a36 2260 u8 reserved_at_493[0x1];
e281682b 2261 u8 page_offset[0x6];
b4ff3a36 2262 u8 reserved_at_49a[0x3];
e281682b
SM		 2263 u8 cd_slave_receive[0x1];
2264 u8 cd_slave_send[0x1];
2265 u8 cd_master[0x1];
2266
b4ff3a36 2267 u8 reserved_at_4a0[0x3];
e281682b
SM		 2268 u8 min_rnr_nak[0x5];
2269 u8 next_rcv_psn[0x18];
2270
b4ff3a36 2271 u8 reserved_at_4c0[0x8];
e281682b
SM		 2272 u8 xrcd[0x18];
2273
b4ff3a36 2274 u8 reserved_at_4e0[0x8];
e281682b
SM		 2275 u8 cqn_rcv[0x18];
2276
2277 u8 dbr_addr[0x40];
2278
2279 u8 q_key[0x20];
2280
b4ff3a36 2281 u8 reserved_at_560[0x5];
e281682b 2282 u8 rq_type[0x3];
7486216b 2283 u8 srqn_rmpn_xrqn[0x18];
e281682b 2284
b4ff3a36 2285 u8 reserved_at_580[0x8];
e281682b
SM		 2286 u8 rmsn[0x18];
2287
2288 u8 hw_sq_wqebb_counter[0x10];
2289 u8 sw_sq_wqebb_counter[0x10];
2290
2291 u8 hw_rq_counter[0x20];
2292
2293 u8 sw_rq_counter[0x20];
2294
b4ff3a36 2295 u8 reserved_at_600[0x20];
e281682b 2296
b4ff3a36 2297 u8 reserved_at_620[0xf];
e281682b
SM		 2298 u8 cgs[0x1];
2299 u8 cs_req[0x8];
2300 u8 cs_res[0x8];
2301
2302 u8 dc_access_key[0x40];
2303
b4ff3a36 2304 u8 reserved_at_680[0xc0];
e281682b
SM		 2305};
2306
2307struct mlx5_ifc_roce_addr_layout_bits {
2308 u8 source_l3_address[16][0x8];
2309
b4ff3a36 2310 u8 reserved_at_80[0x3];
e281682b
SM		 2311 u8 vlan_valid[0x1];
2312 u8 vlan_id[0xc];
2313 u8 source_mac_47_32[0x10];
2314
2315 u8 source_mac_31_0[0x20];
2316
b4ff3a36 2317 u8 reserved_at_c0[0x14];
e281682b
SM		 2318 u8 roce_l3_type[0x4];
2319 u8 roce_version[0x8];
2320
b4ff3a36 2321 u8 reserved_at_e0[0x20];
e281682b
SM		 2322};
2323
2324union mlx5_ifc_hca_cap_union_bits {
2325 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2326 struct mlx5_ifc_odp_cap_bits odp_cap;
2327 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2328 struct mlx5_ifc_roce_cap_bits roce_cap;
2329 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2330 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2331 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2332 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2333 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2334 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2335 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2336 u8 reserved_at_0[0x8000];
e281682b
SM		 2337};
2338
2339enum {
2340 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2341 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2342 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2343 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2344 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2345 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2346 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 2347 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2348 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2349};
2350
2351struct mlx5_ifc_vlan_bits {
2352 u8 ethtype[0x10];
2353 u8 prio[0x3];
2354 u8 cfi[0x1];
2355 u8 vid[0xc];
e281682b
SM		 2356};
2357
2358struct mlx5_ifc_flow_context_bits {
0c06897a 2359 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 2360
2361 u8 group_id[0x20];
2362
b4ff3a36 2363 u8 reserved_at_40[0x8];
e281682b
SM		 2364 u8 flow_tag[0x18];
2365
b4ff3a36 2366 u8 reserved_at_60[0x10];
e281682b
SM		 2367 u8 action[0x10];
2368
b4ff3a36 2369 u8 reserved_at_80[0x8];
e281682b
SM		 2370 u8 destination_list_size[0x18];
2371
9dc0b289
AV		 2372 u8 reserved_at_a0[0x8];
2373 u8 flow_counter_list_size[0x18];
2374
7adbde20
HHZ		 2375 u8 encap_id[0x20];
2376
2a69cb9f
OG		 2377 u8 modify_header_id[0x20];
2378
2379 u8 reserved_at_100[0x100];
e281682b
SM		 2380
2381 struct mlx5_ifc_fte_match_param_bits match_value;
2382
b4ff3a36 2383 u8 reserved_at_1200[0x600];
e281682b 2384
9dc0b289 2385 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2386};
2387
2388enum {
2389 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2390 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2391};
2392
2393struct mlx5_ifc_xrc_srqc_bits {
2394 u8 state[0x4];
2395 u8 log_xrc_srq_size[0x4];
b4ff3a36 2396 u8 reserved_at_8[0x18];
e281682b
SM		 2397
2398 u8 wq_signature[0x1];
2399 u8 cont_srq[0x1];
b4ff3a36 2400 u8 reserved_at_22[0x1];
e281682b
SM		 2401 u8 rlky[0x1];
2402 u8 basic_cyclic_rcv_wqe[0x1];
2403 u8 log_rq_stride[0x3];
2404 u8 xrcd[0x18];
2405
2406 u8 page_offset[0x6];
b4ff3a36 2407 u8 reserved_at_46[0x2];
e281682b
SM		 2408 u8 cqn[0x18];
2409
b4ff3a36 2410 u8 reserved_at_60[0x20];
e281682b
SM		 2411
2412 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2413 u8 reserved_at_81[0x1];
e281682b
SM		 2414 u8 log_page_size[0x6];
2415 u8 user_index[0x18];
2416
b4ff3a36 2417 u8 reserved_at_a0[0x20];
e281682b 2418
b4ff3a36 2419 u8 reserved_at_c0[0x8];
e281682b
SM		 2420 u8 pd[0x18];
2421
2422 u8 lwm[0x10];
2423 u8 wqe_cnt[0x10];
2424
b4ff3a36 2425 u8 reserved_at_100[0x40];
e281682b
SM		 2426
2427 u8 db_record_addr_h[0x20];
2428
2429 u8 db_record_addr_l[0x1e];
b4ff3a36 2430 u8 reserved_at_17e[0x2];
e281682b 2431
b4ff3a36 2432 u8 reserved_at_180[0x80];
e281682b
SM		 2433};
2434
61c5b5c9
MS		 2435struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2436 u8 counter_error_queues[0x20];
2437
2438 u8 total_error_queues[0x20];
2439
2440 u8 send_queue_priority_update_flow[0x20];
2441
2442 u8 reserved_at_60[0x20];
2443
2444 u8 nic_receive_steering_discard[0x40];
2445
2446 u8 receive_discard_vport_down[0x40];
2447
2448 u8 transmit_discard_vport_down[0x40];
2449
2450 u8 reserved_at_140[0xec0];
2451};
2452
e281682b
SM		 2453struct mlx5_ifc_traffic_counter_bits {
2454 u8 packets[0x40];
2455
2456 u8 octets[0x40];
2457};
2458
2459struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2460 u8 strict_lag_tx_port_affinity[0x1];
2461 u8 reserved_at_1[0x3];
2462 u8 lag_tx_port_affinity[0x04];
2463
2464 u8 reserved_at_8[0x4];
e281682b 2465 u8 prio[0x4];
b4ff3a36 2466 u8 reserved_at_10[0x10];
e281682b 2467
b4ff3a36 2468 u8 reserved_at_20[0x100];
e281682b 2469
b4ff3a36 2470 u8 reserved_at_120[0x8];
e281682b
SM		 2471 u8 transport_domain[0x18];
2472
500a3d0d
ES		 2473 u8 reserved_at_140[0x8];
2474 u8 underlay_qpn[0x18];
2475 u8 reserved_at_160[0x3a0];
e281682b
SM		 2476};
2477
2478enum {
2479 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2480 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2481};
2482
2483enum {
2484 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2485 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2486};
2487
2488enum {
2be6967c
SM		 2489 MLX5_RX_HASH_FN_NONE = 0x0,
2490 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2491 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2492};
2493
2494enum {
2495 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2496 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2497};
2498
2499struct mlx5_ifc_tirc_bits {
b4ff3a36 2500 u8 reserved_at_0[0x20];
e281682b
SM		 2501
2502 u8 disp_type[0x4];
b4ff3a36 2503 u8 reserved_at_24[0x1c];
e281682b 2504
b4ff3a36 2505 u8 reserved_at_40[0x40];
e281682b 2506
b4ff3a36 2507 u8 reserved_at_80[0x4];
e281682b
SM		 2508 u8 lro_timeout_period_usecs[0x10];
2509 u8 lro_enable_mask[0x4];
2510 u8 lro_max_ip_payload_size[0x8];
2511
b4ff3a36 2512 u8 reserved_at_a0[0x40];
e281682b 2513
b4ff3a36 2514 u8 reserved_at_e0[0x8];
e281682b
SM		 2515 u8 inline_rqn[0x18];
2516
2517 u8 rx_hash_symmetric[0x1];
b4ff3a36 2518 u8 reserved_at_101[0x1];
e281682b 2519 u8 tunneled_offload_en[0x1];
b4ff3a36 2520 u8 reserved_at_103[0x5];
e281682b
SM		 2521 u8 indirect_table[0x18];
2522
2523 u8 rx_hash_fn[0x4];
b4ff3a36 2524 u8 reserved_at_124[0x2];
e281682b
SM		 2525 u8 self_lb_block[0x2];
2526 u8 transport_domain[0x18];
2527
2528 u8 rx_hash_toeplitz_key[10][0x20];
2529
2530 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2531
2532 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2533
b4ff3a36 2534 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2535};
2536
2537enum {
2538 MLX5_SRQC_STATE_GOOD = 0x0,
2539 MLX5_SRQC_STATE_ERROR = 0x1,
2540};
2541
2542struct mlx5_ifc_srqc_bits {
2543 u8 state[0x4];
2544 u8 log_srq_size[0x4];
b4ff3a36 2545 u8 reserved_at_8[0x18];
e281682b
SM		 2546
2547 u8 wq_signature[0x1];
2548 u8 cont_srq[0x1];
b4ff3a36 2549 u8 reserved_at_22[0x1];
e281682b 2550 u8 rlky[0x1];
b4ff3a36 2551 u8 reserved_at_24[0x1];
e281682b
SM		 2552 u8 log_rq_stride[0x3];
2553 u8 xrcd[0x18];
2554
2555 u8 page_offset[0x6];
b4ff3a36 2556 u8 reserved_at_46[0x2];
e281682b
SM		 2557 u8 cqn[0x18];
2558
b4ff3a36 2559 u8 reserved_at_60[0x20];
e281682b 2560
b4ff3a36 2561 u8 reserved_at_80[0x2];
e281682b 2562 u8 log_page_size[0x6];
b4ff3a36 2563 u8 reserved_at_88[0x18];
e281682b 2564
b4ff3a36 2565 u8 reserved_at_a0[0x20];
e281682b 2566
b4ff3a36 2567 u8 reserved_at_c0[0x8];
e281682b
SM		 2568 u8 pd[0x18];
2569
2570 u8 lwm[0x10];
2571 u8 wqe_cnt[0x10];
2572
b4ff3a36 2573 u8 reserved_at_100[0x40];
e281682b 2574
01949d01 2575 u8 dbr_addr[0x40];
e281682b 2576
b4ff3a36 2577 u8 reserved_at_180[0x80];
e281682b
SM		 2578};
2579
2580enum {
2581 MLX5_SQC_STATE_RST = 0x0,
2582 MLX5_SQC_STATE_RDY = 0x1,
2583 MLX5_SQC_STATE_ERR = 0x3,
2584};
2585
2586struct mlx5_ifc_sqc_bits {
2587 u8 rlky[0x1];
2588 u8 cd_master[0x1];
2589 u8 fre[0x1];
2590 u8 flush_in_error_en[0x1];
795b609c 2591 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2592 u8 min_wqe_inline_mode[0x3];
e281682b 2593 u8 state[0x4];
7d5e1423 2594 u8 reg_umr[0x1];
547eede0 2595 u8 allow_swp[0x1];
40817cdb
OG		 2596 u8 hairpin[0x1];
2597 u8 reserved_at_f[0x11];
e281682b 2598
b4ff3a36 2599 u8 reserved_at_20[0x8];
e281682b
SM		 2600 u8 user_index[0x18];
2601
b4ff3a36 2602 u8 reserved_at_40[0x8];
e281682b
SM		 2603 u8 cqn[0x18];
2604
40817cdb
OG		 2605 u8 reserved_at_60[0x8];
2606 u8 hairpin_peer_rq[0x18];
2607
2608 u8 reserved_at_80[0x10];
2609 u8 hairpin_peer_vhca[0x10];
2610
2611 u8 reserved_at_a0[0x50];
e281682b 2612
7486216b 2613 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2614 u8 tis_lst_sz[0x10];
b4ff3a36 2615 u8 reserved_at_110[0x10];
e281682b 2616
b4ff3a36 2617 u8 reserved_at_120[0x40];
e281682b 2618
b4ff3a36 2619 u8 reserved_at_160[0x8];
e281682b
SM		 2620 u8 tis_num_0[0x18];
2621
2622 struct mlx5_ifc_wq_bits wq;
2623};
2624
813f8540
MHY		 2625enum {
2626 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2627 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2628 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2629 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2630};
2631
2632struct mlx5_ifc_scheduling_context_bits {
2633 u8 element_type[0x8];
2634 u8 reserved_at_8[0x18];
2635
2636 u8 element_attributes[0x20];
2637
2638 u8 parent_element_id[0x20];
2639
2640 u8 reserved_at_60[0x40];
2641
2642 u8 bw_share[0x20];
2643
2644 u8 max_average_bw[0x20];
2645
2646 u8 reserved_at_e0[0x120];
2647};
2648
e281682b 2649struct mlx5_ifc_rqtc_bits {
b4ff3a36 2650 u8 reserved_at_0[0xa0];
e281682b 2651
b4ff3a36 2652 u8 reserved_at_a0[0x10];
e281682b
SM		 2653 u8 rqt_max_size[0x10];
2654
b4ff3a36 2655 u8 reserved_at_c0[0x10];
e281682b
SM		 2656 u8 rqt_actual_size[0x10];
2657
b4ff3a36 2658 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2659
2660 struct mlx5_ifc_rq_num_bits rq_num[0];
2661};
2662
2663enum {
2664 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2665 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2666};
2667
2668enum {
2669 MLX5_RQC_STATE_RST = 0x0,
2670 MLX5_RQC_STATE_RDY = 0x1,
2671 MLX5_RQC_STATE_ERR = 0x3,
2672};
2673
2674struct mlx5_ifc_rqc_bits {
2675 u8 rlky[0x1];
03404e8a 2676 u8 delay_drop_en[0x1];
7d5e1423 2677 u8 scatter_fcs[0x1];
e281682b
SM		 2678 u8 vsd[0x1];
2679 u8 mem_rq_type[0x4];
2680 u8 state[0x4];
b4ff3a36 2681 u8 reserved_at_c[0x1];
e281682b 2682 u8 flush_in_error_en[0x1];
40817cdb
OG		 2683 u8 hairpin[0x1];
2684 u8 reserved_at_f[0x11];
e281682b 2685
b4ff3a36 2686 u8 reserved_at_20[0x8];
e281682b
SM		 2687 u8 user_index[0x18];
2688
b4ff3a36 2689 u8 reserved_at_40[0x8];
e281682b
SM		 2690 u8 cqn[0x18];
2691
2692 u8 counter_set_id[0x8];
b4ff3a36 2693 u8 reserved_at_68[0x18];
e281682b 2694
b4ff3a36 2695 u8 reserved_at_80[0x8];
e281682b
SM		 2696 u8 rmpn[0x18];
2697
40817cdb
OG		 2698 u8 reserved_at_a0[0x8];
2699 u8 hairpin_peer_sq[0x18];
2700
2701 u8 reserved_at_c0[0x10];
2702 u8 hairpin_peer_vhca[0x10];
2703
2704 u8 reserved_at_e0[0xa0];
e281682b
SM		 2705
2706 struct mlx5_ifc_wq_bits wq;
2707};
2708
2709enum {
2710 MLX5_RMPC_STATE_RDY = 0x1,
2711 MLX5_RMPC_STATE_ERR = 0x3,
2712};
2713
2714struct mlx5_ifc_rmpc_bits {
b4ff3a36 2715 u8 reserved_at_0[0x8];
e281682b 2716 u8 state[0x4];
b4ff3a36 2717 u8 reserved_at_c[0x14];
e281682b
SM		 2718
2719 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2720 u8 reserved_at_21[0x1f];
e281682b 2721
b4ff3a36 2722 u8 reserved_at_40[0x140];
e281682b
SM		 2723
2724 struct mlx5_ifc_wq_bits wq;
2725};
2726
e281682b 2727struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2728 u8 reserved_at_0[0x5];
2729 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2730 u8 reserved_at_8[0x15];
2731 u8 disable_mc_local_lb[0x1];
2732 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2733 u8 roce_en[0x1];
2734
d82b7318 2735 u8 arm_change_event[0x1];
b4ff3a36 2736 u8 reserved_at_21[0x1a];
d82b7318
SM		 2737 u8 event_on_mtu[0x1];
2738 u8 event_on_promisc_change[0x1];
2739 u8 event_on_vlan_change[0x1];
2740 u8 event_on_mc_address_change[0x1];
2741 u8 event_on_uc_address_change[0x1];
e281682b 2742
32f69e4b
DJ		 2743 u8 reserved_at_40[0xc];
2744
2745 u8 affiliation_criteria[0x4];
2746 u8 affiliated_vhca_id[0x10];
2747
2748 u8 reserved_at_60[0xd0];
d82b7318
SM		 2749
2750 u8 mtu[0x10];
2751
9efa7525
AS		 2752 u8 system_image_guid[0x40];
2753 u8 port_guid[0x40];
2754 u8 node_guid[0x40];
2755
b4ff3a36 2756 u8 reserved_at_200[0x140];
9efa7525 2757 u8 qkey_violation_counter[0x10];
b4ff3a36 2758 u8 reserved_at_350[0x430];
d82b7318
SM		 2759
2760 u8 promisc_uc[0x1];
2761 u8 promisc_mc[0x1];
2762 u8 promisc_all[0x1];
b4ff3a36 2763 u8 reserved_at_783[0x2];
e281682b 2764 u8 allowed_list_type[0x3];
b4ff3a36 2765 u8 reserved_at_788[0xc];
e281682b
SM		 2766 u8 allowed_list_size[0xc];
2767
2768 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2769
b4ff3a36 2770 u8 reserved_at_7e0[0x20];
e281682b
SM		 2771
2772 u8 current_uc_mac_address[0][0x40];
2773};
2774
2775enum {
2776 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2777 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2778 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2779 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
cdbd0d2b 2780 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 2781};
2782
2783struct mlx5_ifc_mkc_bits {
b4ff3a36 2784 u8 reserved_at_0[0x1];
e281682b 2785 u8 free[0x1];
cdbd0d2b
AL		 2786 u8 reserved_at_2[0x1];
2787 u8 access_mode_4_2[0x3];
2788 u8 reserved_at_6[0x7];
2789 u8 relaxed_ordering_write[0x1];
2790 u8 reserved_at_e[0x1];
e281682b
SM		 2791 u8 small_fence_on_rdma_read_response[0x1];
2792 u8 umr_en[0x1];
2793 u8 a[0x1];
2794 u8 rw[0x1];
2795 u8 rr[0x1];
2796 u8 lw[0x1];
2797 u8 lr[0x1];
cdbd0d2b 2798 u8 access_mode_1_0[0x2];
b4ff3a36 2799 u8 reserved_at_18[0x8];
e281682b
SM		 2800
2801 u8 qpn[0x18];
2802 u8 mkey_7_0[0x8];
2803
b4ff3a36 2804 u8 reserved_at_40[0x20];
e281682b
SM		 2805
2806 u8 length64[0x1];
2807 u8 bsf_en[0x1];
2808 u8 sync_umr[0x1];
b4ff3a36 2809 u8 reserved_at_63[0x2];
e281682b 2810 u8 expected_sigerr_count[0x1];
b4ff3a36 2811 u8 reserved_at_66[0x1];
e281682b
SM		 2812 u8 en_rinval[0x1];
2813 u8 pd[0x18];
2814
2815 u8 start_addr[0x40];
2816
2817 u8 len[0x40];
2818
2819 u8 bsf_octword_size[0x20];
2820
b4ff3a36 2821 u8 reserved_at_120[0x80];
e281682b
SM		 2822
2823 u8 translations_octword_size[0x20];
2824
b4ff3a36 2825 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2826 u8 log_page_size[0x5];
2827
b4ff3a36 2828 u8 reserved_at_1e0[0x20];
e281682b
SM		 2829};
2830
2831struct mlx5_ifc_pkey_bits {
b4ff3a36 2832 u8 reserved_at_0[0x10];
e281682b
SM		 2833 u8 pkey[0x10];
2834};
2835
2836struct mlx5_ifc_array128_auto_bits {
2837 u8 array128_auto[16][0x8];
2838};
2839
2840struct mlx5_ifc_hca_vport_context_bits {
2841 u8 field_select[0x20];
2842
b4ff3a36 2843 u8 reserved_at_20[0xe0];
e281682b
SM		 2844
2845 u8 sm_virt_aware[0x1];
2846 u8 has_smi[0x1];
2847 u8 has_raw[0x1];
2848 u8 grh_required[0x1];
b4ff3a36 2849 u8 reserved_at_104[0xc];
707c4602
MD		 2850 u8 port_physical_state[0x4];
2851 u8 vport_state_policy[0x4];
2852 u8 port_state[0x4];
e281682b
SM		 2853 u8 vport_state[0x4];
2854
b4ff3a36 2855 u8 reserved_at_120[0x20];
707c4602
MD		 2856
2857 u8 system_image_guid[0x40];
e281682b
SM		 2858
2859 u8 port_guid[0x40];
2860
2861 u8 node_guid[0x40];
2862
2863 u8 cap_mask1[0x20];
2864
2865 u8 cap_mask1_field_select[0x20];
2866
2867 u8 cap_mask2[0x20];
2868
2869 u8 cap_mask2_field_select[0x20];
2870
b4ff3a36 2871 u8 reserved_at_280[0x80];
e281682b
SM		 2872
2873 u8 lid[0x10];
b4ff3a36 2874 u8 reserved_at_310[0x4];
e281682b
SM		 2875 u8 init_type_reply[0x4];
2876 u8 lmc[0x3];
2877 u8 subnet_timeout[0x5];
2878
2879 u8 sm_lid[0x10];
2880 u8 sm_sl[0x4];
b4ff3a36 2881 u8 reserved_at_334[0xc];
e281682b
SM		 2882
2883 u8 qkey_violation_counter[0x10];
2884 u8 pkey_violation_counter[0x10];
2885
b4ff3a36 2886 u8 reserved_at_360[0xca0];
e281682b
SM		 2887};
2888
d6666753 2889struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2890 u8 reserved_at_0[0x3];
d6666753
SM		 2891 u8 vport_svlan_strip[0x1];
2892 u8 vport_cvlan_strip[0x1];
2893 u8 vport_svlan_insert[0x1];
2894 u8 vport_cvlan_insert[0x2];
b4ff3a36 2895 u8 reserved_at_8[0x18];
d6666753 2896
b4ff3a36 2897 u8 reserved_at_20[0x20];
d6666753
SM		 2898
2899 u8 svlan_cfi[0x1];
2900 u8 svlan_pcp[0x3];
2901 u8 svlan_id[0xc];
2902 u8 cvlan_cfi[0x1];
2903 u8 cvlan_pcp[0x3];
2904 u8 cvlan_id[0xc];
2905
b4ff3a36 2906 u8 reserved_at_60[0x7a0];
d6666753
SM		 2907};
2908
e281682b
SM		 2909enum {
2910 MLX5_EQC_STATUS_OK = 0x0,
2911 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2912};
2913
2914enum {
2915 MLX5_EQC_ST_ARMED = 0x9,
2916 MLX5_EQC_ST_FIRED = 0xa,
2917};
2918
2919struct mlx5_ifc_eqc_bits {
2920 u8 status[0x4];
b4ff3a36 2921 u8 reserved_at_4[0x9];
e281682b
SM		 2922 u8 ec[0x1];
2923 u8 oi[0x1];
b4ff3a36 2924 u8 reserved_at_f[0x5];
e281682b 2925 u8 st[0x4];
b4ff3a36 2926 u8 reserved_at_18[0x8];
e281682b 2927
b4ff3a36 2928 u8 reserved_at_20[0x20];
e281682b 2929
b4ff3a36 2930 u8 reserved_at_40[0x14];
e281682b 2931 u8 page_offset[0x6];
b4ff3a36 2932 u8 reserved_at_5a[0x6];
e281682b 2933
b4ff3a36 2934 u8 reserved_at_60[0x3];
e281682b
SM		 2935 u8 log_eq_size[0x5];
2936 u8 uar_page[0x18];
2937
b4ff3a36 2938 u8 reserved_at_80[0x20];
e281682b 2939
b4ff3a36 2940 u8 reserved_at_a0[0x18];
e281682b
SM		 2941 u8 intr[0x8];
2942
b4ff3a36 2943 u8 reserved_at_c0[0x3];
e281682b 2944 u8 log_page_size[0x5];
b4ff3a36 2945 u8 reserved_at_c8[0x18];
e281682b 2946
b4ff3a36 2947 u8 reserved_at_e0[0x60];
e281682b 2948
b4ff3a36 2949 u8 reserved_at_140[0x8];
e281682b
SM		 2950 u8 consumer_counter[0x18];
2951
b4ff3a36 2952 u8 reserved_at_160[0x8];
e281682b
SM		 2953 u8 producer_counter[0x18];
2954
b4ff3a36 2955 u8 reserved_at_180[0x80];
e281682b
SM		 2956};
2957
2958enum {
2959 MLX5_DCTC_STATE_ACTIVE = 0x0,
2960 MLX5_DCTC_STATE_DRAINING = 0x1,
2961 MLX5_DCTC_STATE_DRAINED = 0x2,
2962};
2963
2964enum {
2965 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2966 MLX5_DCTC_CS_RES_NA = 0x1,
2967 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2968};
2969
2970enum {
2971 MLX5_DCTC_MTU_256_BYTES = 0x1,
2972 MLX5_DCTC_MTU_512_BYTES = 0x2,
2973 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2974 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2975 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2976};
2977
2978struct mlx5_ifc_dctc_bits {
b4ff3a36 2979 u8 reserved_at_0[0x4];
e281682b 2980 u8 state[0x4];
b4ff3a36 2981 u8 reserved_at_8[0x18];
e281682b 2982
b4ff3a36 2983 u8 reserved_at_20[0x8];
e281682b
SM		 2984 u8 user_index[0x18];
2985
b4ff3a36 2986 u8 reserved_at_40[0x8];
e281682b
SM		 2987 u8 cqn[0x18];
2988
2989 u8 counter_set_id[0x8];
2990 u8 atomic_mode[0x4];
2991 u8 rre[0x1];
2992 u8 rwe[0x1];
2993 u8 rae[0x1];
2994 u8 atomic_like_write_en[0x1];
2995 u8 latency_sensitive[0x1];
2996 u8 rlky[0x1];
2997 u8 free_ar[0x1];
b4ff3a36 2998 u8 reserved_at_73[0xd];
e281682b 2999
b4ff3a36 3000 u8 reserved_at_80[0x8];
e281682b 3001 u8 cs_res[0x8];
b4ff3a36 3002 u8 reserved_at_90[0x3];
e281682b 3003 u8 min_rnr_nak[0x5];
b4ff3a36 3004 u8 reserved_at_98[0x8];
e281682b 3005
b4ff3a36 3006 u8 reserved_at_a0[0x8];
7486216b 3007 u8 srqn_xrqn[0x18];
e281682b 3008
b4ff3a36 3009 u8 reserved_at_c0[0x8];
e281682b
SM		 3010 u8 pd[0x18];
3011
3012 u8 tclass[0x8];
b4ff3a36 3013 u8 reserved_at_e8[0x4];
e281682b
SM		 3014 u8 flow_label[0x14];
3015
3016 u8 dc_access_key[0x40];
3017
b4ff3a36 3018 u8 reserved_at_140[0x5];
e281682b
SM		 3019 u8 mtu[0x3];
3020 u8 port[0x8];
3021 u8 pkey_index[0x10];
3022
b4ff3a36 3023 u8 reserved_at_160[0x8];
e281682b 3024 u8 my_addr_index[0x8];
b4ff3a36 3025 u8 reserved_at_170[0x8];
e281682b
SM		 3026 u8 hop_limit[0x8];
3027
3028 u8 dc_access_key_violation_count[0x20];
3029
b4ff3a36 3030 u8 reserved_at_1a0[0x14];
e281682b
SM		 3031 u8 dei_cfi[0x1];
3032 u8 eth_prio[0x3];
3033 u8 ecn[0x2];
3034 u8 dscp[0x6];
3035
b4ff3a36 3036 u8 reserved_at_1c0[0x40];
e281682b
SM		 3037};
3038
3039enum {
3040 MLX5_CQC_STATUS_OK = 0x0,
3041 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3042 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3043};
3044
3045enum {
3046 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3047 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3048};
3049
3050enum {
3051 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3052 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3053 MLX5_CQC_ST_FIRED = 0xa,
3054};
3055
7d5e1423
SM		 3056enum {
3057 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3058 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 3059 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 3060};
3061
e281682b
SM		 3062struct mlx5_ifc_cqc_bits {
3063 u8 status[0x4];
b4ff3a36 3064 u8 reserved_at_4[0x4];
e281682b
SM		 3065 u8 cqe_sz[0x3];
3066 u8 cc[0x1];
b4ff3a36 3067 u8 reserved_at_c[0x1];
e281682b
SM		 3068 u8 scqe_break_moderation_en[0x1];
3069 u8 oi[0x1];
7d5e1423
SM		 3070 u8 cq_period_mode[0x2];
3071 u8 cqe_comp_en[0x1];
e281682b
SM		 3072 u8 mini_cqe_res_format[0x2];
3073 u8 st[0x4];
b4ff3a36 3074 u8 reserved_at_18[0x8];
e281682b 3075
b4ff3a36 3076 u8 reserved_at_20[0x20];
e281682b 3077
b4ff3a36 3078 u8 reserved_at_40[0x14];
e281682b 3079 u8 page_offset[0x6];
b4ff3a36 3080 u8 reserved_at_5a[0x6];
e281682b 3081
b4ff3a36 3082 u8 reserved_at_60[0x3];
e281682b
SM		 3083 u8 log_cq_size[0x5];
3084 u8 uar_page[0x18];
3085
b4ff3a36 3086 u8 reserved_at_80[0x4];
e281682b
SM		 3087 u8 cq_period[0xc];
3088 u8 cq_max_count[0x10];
3089
b4ff3a36 3090 u8 reserved_at_a0[0x18];
e281682b
SM		 3091 u8 c_eqn[0x8];
3092
b4ff3a36 3093 u8 reserved_at_c0[0x3];
e281682b 3094 u8 log_page_size[0x5];
b4ff3a36 3095 u8 reserved_at_c8[0x18];
e281682b 3096
b4ff3a36 3097 u8 reserved_at_e0[0x20];
e281682b 3098
b4ff3a36 3099 u8 reserved_at_100[0x8];
e281682b
SM		 3100 u8 last_notified_index[0x18];
3101
b4ff3a36 3102 u8 reserved_at_120[0x8];
e281682b
SM		 3103 u8 last_solicit_index[0x18];
3104
b4ff3a36 3105 u8 reserved_at_140[0x8];
e281682b
SM		 3106 u8 consumer_counter[0x18];
3107
b4ff3a36 3108 u8 reserved_at_160[0x8];
e281682b
SM		 3109 u8 producer_counter[0x18];
3110
b4ff3a36 3111 u8 reserved_at_180[0x40];
e281682b
SM		 3112
3113 u8 dbr_addr[0x40];
3114};
3115
3116union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3117 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3118 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3119 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 3120 u8 reserved_at_0[0x800];
e281682b
SM		 3121};
3122
3123struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 3124 u8 reserved_at_0[0xc0];
e281682b 3125
b4ff3a36 3126 u8 reserved_at_c0[0x8];
211e6c80
MD		 3127 u8 ieee_vendor_id[0x18];
3128
b4ff3a36 3129 u8 reserved_at_e0[0x10];
e281682b
SM		 3130 u8 vsd_vendor_id[0x10];
3131
3132 u8 vsd[208][0x8];
3133
3134 u8 vsd_contd_psid[16][0x8];
3135};
3136
7486216b
SM		 3137enum {
3138 MLX5_XRQC_STATE_GOOD = 0x0,
3139 MLX5_XRQC_STATE_ERROR = 0x1,
3140};
3141
3142enum {
3143 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3144 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3145};
3146
3147enum {
3148 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3149};
3150
3151struct mlx5_ifc_tag_matching_topology_context_bits {
3152 u8 log_matching_list_sz[0x4];
3153 u8 reserved_at_4[0xc];
3154 u8 append_next_index[0x10];
3155
3156 u8 sw_phase_cnt[0x10];
3157 u8 hw_phase_cnt[0x10];
3158
3159 u8 reserved_at_40[0x40];
3160};
3161
3162struct mlx5_ifc_xrqc_bits {
3163 u8 state[0x4];
3164 u8 rlkey[0x1];
3165 u8 reserved_at_5[0xf];
3166 u8 topology[0x4];
3167 u8 reserved_at_18[0x4];
3168 u8 offload[0x4];
3169
3170 u8 reserved_at_20[0x8];
3171 u8 user_index[0x18];
3172
3173 u8 reserved_at_40[0x8];
3174 u8 cqn[0x18];
3175
3176 u8 reserved_at_60[0xa0];
3177
3178 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3179
6e44636a 3180 u8 reserved_at_180[0x280];
7486216b
SM		 3181
3182 struct mlx5_ifc_wq_bits wq;
3183};
3184
e281682b
SM		 3185union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3186 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3187 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3188 u8 reserved_at_0[0x20];
e281682b
SM		 3189};
3190
3191union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3192 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3193 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3194 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3195 u8 reserved_at_0[0x20];
e281682b
SM		 3196};
3197
3198union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3199 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3200 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3201 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3202 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3203 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3204 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3205 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3206 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3207 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3208 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3209 u8 reserved_at_0[0x7c0];
e281682b
SM		 3210};
3211
8ed1a630
GP		 3212union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3213 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3214 u8 reserved_at_0[0x7c0];
3215};
3216
e281682b
SM		 3217union mlx5_ifc_event_auto_bits {
3218 struct mlx5_ifc_comp_event_bits comp_event;
3219 struct mlx5_ifc_dct_events_bits dct_events;
3220 struct mlx5_ifc_qp_events_bits qp_events;
3221 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3222 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3223 struct mlx5_ifc_cq_error_bits cq_error;
3224 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3225 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3226 struct mlx5_ifc_gpio_event_bits gpio_event;
3227 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3228 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3229 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3230 u8 reserved_at_0[0xe0];
e281682b
SM		 3231};
3232
3233struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3234 u8 reserved_at_0[0x100];
e281682b
SM		 3235
3236 u8 assert_existptr[0x20];
3237
3238 u8 assert_callra[0x20];
3239
b4ff3a36 3240 u8 reserved_at_140[0x40];
e281682b
SM		 3241
3242 u8 fw_version[0x20];
3243
3244 u8 hw_id[0x20];
3245
b4ff3a36 3246 u8 reserved_at_1c0[0x20];
e281682b
SM		 3247
3248 u8 irisc_index[0x8];
3249 u8 synd[0x8];
3250 u8 ext_synd[0x10];
3251};
3252
3253struct mlx5_ifc_register_loopback_control_bits {
3254 u8 no_lb[0x1];
b4ff3a36 3255 u8 reserved_at_1[0x7];
e281682b 3256 u8 port[0x8];
b4ff3a36 3257 u8 reserved_at_10[0x10];
e281682b 3258
b4ff3a36 3259 u8 reserved_at_20[0x60];
e281682b
SM		 3260};
3261
813f8540
MHY		 3262struct mlx5_ifc_vport_tc_element_bits {
3263 u8 traffic_class[0x4];
3264 u8 reserved_at_4[0xc];
3265 u8 vport_number[0x10];
3266};
3267
3268struct mlx5_ifc_vport_element_bits {
3269 u8 reserved_at_0[0x10];
3270 u8 vport_number[0x10];
3271};
3272
3273enum {
3274 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3275 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3276 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3277};
3278
3279struct mlx5_ifc_tsar_element_bits {
3280 u8 reserved_at_0[0x8];
3281 u8 tsar_type[0x8];
3282 u8 reserved_at_10[0x10];
3283};
3284
8812c24d
MD		 3285enum {
3286 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3287 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3288};
3289
e281682b
SM		 3290struct mlx5_ifc_teardown_hca_out_bits {
3291 u8 status[0x8];
b4ff3a36 3292 u8 reserved_at_8[0x18];
e281682b
SM		 3293
3294 u8 syndrome[0x20];
3295
8812c24d
MD		 3296 u8 reserved_at_40[0x3f];
3297
3298 u8 force_state[0x1];
e281682b
SM		 3299};
3300
3301enum {
3302 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3303 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3304};
3305
3306struct mlx5_ifc_teardown_hca_in_bits {
3307 u8 opcode[0x10];
b4ff3a36 3308 u8 reserved_at_10[0x10];
e281682b 3309
b4ff3a36 3310 u8 reserved_at_20[0x10];
e281682b
SM		 3311 u8 op_mod[0x10];
3312
b4ff3a36 3313 u8 reserved_at_40[0x10];
e281682b
SM		 3314 u8 profile[0x10];
3315
b4ff3a36 3316 u8 reserved_at_60[0x20];
e281682b
SM		 3317};
3318
3319struct mlx5_ifc_sqerr2rts_qp_out_bits {
3320 u8 status[0x8];
b4ff3a36 3321 u8 reserved_at_8[0x18];
e281682b
SM		 3322
3323 u8 syndrome[0x20];
3324
b4ff3a36 3325 u8 reserved_at_40[0x40];
e281682b
SM		 3326};
3327
3328struct mlx5_ifc_sqerr2rts_qp_in_bits {
3329 u8 opcode[0x10];
b4ff3a36 3330 u8 reserved_at_10[0x10];
e281682b 3331
b4ff3a36 3332 u8 reserved_at_20[0x10];
e281682b
SM		 3333 u8 op_mod[0x10];
3334
b4ff3a36 3335 u8 reserved_at_40[0x8];
e281682b
SM		 3336 u8 qpn[0x18];
3337
b4ff3a36 3338 u8 reserved_at_60[0x20];
e281682b
SM		 3339
3340 u8 opt_param_mask[0x20];
3341
b4ff3a36 3342 u8 reserved_at_a0[0x20];
e281682b
SM		 3343
3344 struct mlx5_ifc_qpc_bits qpc;
3345
b4ff3a36 3346 u8 reserved_at_800[0x80];
e281682b
SM		 3347};
3348
3349struct mlx5_ifc_sqd2rts_qp_out_bits {
3350 u8 status[0x8];
b4ff3a36 3351 u8 reserved_at_8[0x18];
e281682b
SM		 3352
3353 u8 syndrome[0x20];
3354
b4ff3a36 3355 u8 reserved_at_40[0x40];
e281682b
SM		 3356};
3357
3358struct mlx5_ifc_sqd2rts_qp_in_bits {
3359 u8 opcode[0x10];
b4ff3a36 3360 u8 reserved_at_10[0x10];
e281682b 3361
b4ff3a36 3362 u8 reserved_at_20[0x10];
e281682b
SM		 3363 u8 op_mod[0x10];
3364
b4ff3a36 3365 u8 reserved_at_40[0x8];
e281682b
SM		 3366 u8 qpn[0x18];
3367
b4ff3a36 3368 u8 reserved_at_60[0x20];
e281682b
SM		 3369
3370 u8 opt_param_mask[0x20];
3371
b4ff3a36 3372 u8 reserved_at_a0[0x20];
e281682b
SM		 3373
3374 struct mlx5_ifc_qpc_bits qpc;
3375
b4ff3a36 3376 u8 reserved_at_800[0x80];
e281682b
SM		 3377};
3378
3379struct mlx5_ifc_set_roce_address_out_bits {
3380 u8 status[0x8];
b4ff3a36 3381 u8 reserved_at_8[0x18];
e281682b
SM		 3382
3383 u8 syndrome[0x20];
3384
b4ff3a36 3385 u8 reserved_at_40[0x40];
e281682b
SM		 3386};
3387
3388struct mlx5_ifc_set_roce_address_in_bits {
3389 u8 opcode[0x10];
b4ff3a36 3390 u8 reserved_at_10[0x10];
e281682b 3391
b4ff3a36 3392 u8 reserved_at_20[0x10];
e281682b
SM		 3393 u8 op_mod[0x10];
3394
3395 u8 roce_address_index[0x10];
32f69e4b
DJ		 3396 u8 reserved_at_50[0xc];
3397 u8 vhca_port_num[0x4];
e281682b 3398
b4ff3a36 3399 u8 reserved_at_60[0x20];
e281682b
SM		 3400
3401 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3402};
3403
3404struct mlx5_ifc_set_mad_demux_out_bits {
3405 u8 status[0x8];
b4ff3a36 3406 u8 reserved_at_8[0x18];
e281682b
SM		 3407
3408 u8 syndrome[0x20];
3409
b4ff3a36 3410 u8 reserved_at_40[0x40];
e281682b
SM		 3411};
3412
3413enum {
3414 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3415 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3416};
3417
3418struct mlx5_ifc_set_mad_demux_in_bits {
3419 u8 opcode[0x10];
b4ff3a36 3420 u8 reserved_at_10[0x10];
e281682b 3421
b4ff3a36 3422 u8 reserved_at_20[0x10];
e281682b
SM		 3423 u8 op_mod[0x10];
3424
b4ff3a36 3425 u8 reserved_at_40[0x20];
e281682b 3426
b4ff3a36 3427 u8 reserved_at_60[0x6];
e281682b 3428 u8 demux_mode[0x2];
b4ff3a36 3429 u8 reserved_at_68[0x18];
e281682b
SM		 3430};
3431
3432struct mlx5_ifc_set_l2_table_entry_out_bits {
3433 u8 status[0x8];
b4ff3a36 3434 u8 reserved_at_8[0x18];
e281682b
SM		 3435
3436 u8 syndrome[0x20];
3437
b4ff3a36 3438 u8 reserved_at_40[0x40];
e281682b
SM		 3439};
3440
3441struct mlx5_ifc_set_l2_table_entry_in_bits {
3442 u8 opcode[0x10];
b4ff3a36 3443 u8 reserved_at_10[0x10];
e281682b 3444
b4ff3a36 3445 u8 reserved_at_20[0x10];
e281682b
SM		 3446 u8 op_mod[0x10];
3447
b4ff3a36 3448 u8 reserved_at_40[0x60];
e281682b 3449
b4ff3a36 3450 u8 reserved_at_a0[0x8];
e281682b
SM		 3451 u8 table_index[0x18];
3452
b4ff3a36 3453 u8 reserved_at_c0[0x20];
e281682b 3454
b4ff3a36 3455 u8 reserved_at_e0[0x13];
e281682b
SM		 3456 u8 vlan_valid[0x1];
3457 u8 vlan[0xc];
3458
3459 struct mlx5_ifc_mac_address_layout_bits mac_address;
3460
b4ff3a36 3461 u8 reserved_at_140[0xc0];
e281682b
SM		 3462};
3463
3464struct mlx5_ifc_set_issi_out_bits {
3465 u8 status[0x8];
b4ff3a36 3466 u8 reserved_at_8[0x18];
e281682b
SM		 3467
3468 u8 syndrome[0x20];
3469
b4ff3a36 3470 u8 reserved_at_40[0x40];
e281682b
SM		 3471};
3472
3473struct mlx5_ifc_set_issi_in_bits {
3474 u8 opcode[0x10];
b4ff3a36 3475 u8 reserved_at_10[0x10];
e281682b 3476
b4ff3a36 3477 u8 reserved_at_20[0x10];
e281682b
SM		 3478 u8 op_mod[0x10];
3479
b4ff3a36 3480 u8 reserved_at_40[0x10];
e281682b
SM		 3481 u8 current_issi[0x10];
3482
b4ff3a36 3483 u8 reserved_at_60[0x20];
e281682b
SM		 3484};
3485
3486struct mlx5_ifc_set_hca_cap_out_bits {
3487 u8 status[0x8];
b4ff3a36 3488 u8 reserved_at_8[0x18];
e281682b
SM		 3489
3490 u8 syndrome[0x20];
3491
b4ff3a36 3492 u8 reserved_at_40[0x40];
e281682b
SM		 3493};
3494
3495struct mlx5_ifc_set_hca_cap_in_bits {
3496 u8 opcode[0x10];
b4ff3a36 3497 u8 reserved_at_10[0x10];
e281682b 3498
b4ff3a36 3499 u8 reserved_at_20[0x10];
e281682b
SM		 3500 u8 op_mod[0x10];
3501
b4ff3a36 3502 u8 reserved_at_40[0x40];
e281682b
SM		 3503
3504 union mlx5_ifc_hca_cap_union_bits capability;
3505};
3506
26a81453
MG		 3507enum {
3508 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3509 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3510 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3511 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3512};
3513
e281682b
SM		 3514struct mlx5_ifc_set_fte_out_bits {
3515 u8 status[0x8];
b4ff3a36 3516 u8 reserved_at_8[0x18];
e281682b
SM		 3517
3518 u8 syndrome[0x20];
3519
b4ff3a36 3520 u8 reserved_at_40[0x40];
e281682b
SM		 3521};
3522
3523struct mlx5_ifc_set_fte_in_bits {
3524 u8 opcode[0x10];
b4ff3a36 3525 u8 reserved_at_10[0x10];
e281682b 3526
b4ff3a36 3527 u8 reserved_at_20[0x10];
e281682b
SM		 3528 u8 op_mod[0x10];
3529
7d5e1423
SM		 3530 u8 other_vport[0x1];
3531 u8 reserved_at_41[0xf];
3532 u8 vport_number[0x10];
3533
3534 u8 reserved_at_60[0x20];
e281682b
SM		 3535
3536 u8 table_type[0x8];
b4ff3a36 3537 u8 reserved_at_88[0x18];
e281682b 3538
b4ff3a36 3539 u8 reserved_at_a0[0x8];
e281682b
SM		 3540 u8 table_id[0x18];
3541
b4ff3a36 3542 u8 reserved_at_c0[0x18];
26a81453
MG		 3543 u8 modify_enable_mask[0x8];
3544
b4ff3a36 3545 u8 reserved_at_e0[0x20];
e281682b
SM		 3546
3547 u8 flow_index[0x20];
3548
b4ff3a36 3549 u8 reserved_at_120[0xe0];
e281682b
SM		 3550
3551 struct mlx5_ifc_flow_context_bits flow_context;
3552};
3553
3554struct mlx5_ifc_rts2rts_qp_out_bits {
3555 u8 status[0x8];
b4ff3a36 3556 u8 reserved_at_8[0x18];
e281682b
SM		 3557
3558 u8 syndrome[0x20];
3559
b4ff3a36 3560 u8 reserved_at_40[0x40];
e281682b
SM		 3561};
3562
3563struct mlx5_ifc_rts2rts_qp_in_bits {
3564 u8 opcode[0x10];
b4ff3a36 3565 u8 reserved_at_10[0x10];
e281682b 3566
b4ff3a36 3567 u8 reserved_at_20[0x10];
e281682b
SM		 3568 u8 op_mod[0x10];
3569
b4ff3a36 3570 u8 reserved_at_40[0x8];
e281682b
SM		 3571 u8 qpn[0x18];
3572
b4ff3a36 3573 u8 reserved_at_60[0x20];
e281682b
SM		 3574
3575 u8 opt_param_mask[0x20];
3576
b4ff3a36 3577 u8 reserved_at_a0[0x20];
e281682b
SM		 3578
3579 struct mlx5_ifc_qpc_bits qpc;
3580
b4ff3a36 3581 u8 reserved_at_800[0x80];
e281682b
SM		 3582};
3583
3584struct mlx5_ifc_rtr2rts_qp_out_bits {
3585 u8 status[0x8];
b4ff3a36 3586 u8 reserved_at_8[0x18];
e281682b
SM		 3587
3588 u8 syndrome[0x20];
3589
b4ff3a36 3590 u8 reserved_at_40[0x40];
e281682b
SM		 3591};
3592
3593struct mlx5_ifc_rtr2rts_qp_in_bits {
3594 u8 opcode[0x10];
b4ff3a36 3595 u8 reserved_at_10[0x10];
e281682b 3596
b4ff3a36 3597 u8 reserved_at_20[0x10];
e281682b
SM		 3598 u8 op_mod[0x10];
3599
b4ff3a36 3600 u8 reserved_at_40[0x8];
e281682b
SM		 3601 u8 qpn[0x18];
3602
b4ff3a36 3603 u8 reserved_at_60[0x20];
e281682b
SM		 3604
3605 u8 opt_param_mask[0x20];
3606
b4ff3a36 3607 u8 reserved_at_a0[0x20];
e281682b
SM		 3608
3609 struct mlx5_ifc_qpc_bits qpc;
3610
b4ff3a36 3611 u8 reserved_at_800[0x80];
e281682b
SM		 3612};
3613
3614struct mlx5_ifc_rst2init_qp_out_bits {
3615 u8 status[0x8];
b4ff3a36 3616 u8 reserved_at_8[0x18];
e281682b
SM		 3617
3618 u8 syndrome[0x20];
3619
b4ff3a36 3620 u8 reserved_at_40[0x40];
e281682b
SM		 3621};
3622
3623struct mlx5_ifc_rst2init_qp_in_bits {
3624 u8 opcode[0x10];
b4ff3a36 3625 u8 reserved_at_10[0x10];
e281682b 3626
b4ff3a36 3627 u8 reserved_at_20[0x10];
e281682b
SM		 3628 u8 op_mod[0x10];
3629
b4ff3a36 3630 u8 reserved_at_40[0x8];
e281682b
SM		 3631 u8 qpn[0x18];
3632
b4ff3a36 3633 u8 reserved_at_60[0x20];
e281682b
SM		 3634
3635 u8 opt_param_mask[0x20];
3636
b4ff3a36 3637 u8 reserved_at_a0[0x20];
e281682b
SM		 3638
3639 struct mlx5_ifc_qpc_bits qpc;
3640
b4ff3a36 3641 u8 reserved_at_800[0x80];
e281682b
SM		 3642};
3643
7486216b
SM		 3644struct mlx5_ifc_query_xrq_out_bits {
3645 u8 status[0x8];
3646 u8 reserved_at_8[0x18];
3647
3648 u8 syndrome[0x20];
3649
3650 u8 reserved_at_40[0x40];
3651
3652 struct mlx5_ifc_xrqc_bits xrq_context;
3653};
3654
3655struct mlx5_ifc_query_xrq_in_bits {
3656 u8 opcode[0x10];
3657 u8 reserved_at_10[0x10];
3658
3659 u8 reserved_at_20[0x10];
3660 u8 op_mod[0x10];
3661
3662 u8 reserved_at_40[0x8];
3663 u8 xrqn[0x18];
3664
3665 u8 reserved_at_60[0x20];
3666};
3667
e281682b
SM		 3668struct mlx5_ifc_query_xrc_srq_out_bits {
3669 u8 status[0x8];
b4ff3a36 3670 u8 reserved_at_8[0x18];
e281682b
SM		 3671
3672 u8 syndrome[0x20];
3673
b4ff3a36 3674 u8 reserved_at_40[0x40];
e281682b
SM		 3675
3676 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3677
b4ff3a36 3678 u8 reserved_at_280[0x600];
e281682b
SM		 3679
3680 u8 pas[0][0x40];
3681};
3682
3683struct mlx5_ifc_query_xrc_srq_in_bits {
3684 u8 opcode[0x10];
b4ff3a36 3685 u8 reserved_at_10[0x10];
e281682b 3686
b4ff3a36 3687 u8 reserved_at_20[0x10];
e281682b
SM		 3688 u8 op_mod[0x10];
3689
b4ff3a36 3690 u8 reserved_at_40[0x8];
e281682b
SM		 3691 u8 xrc_srqn[0x18];
3692
b4ff3a36 3693 u8 reserved_at_60[0x20];
e281682b
SM		 3694};
3695
3696enum {
3697 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3698 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3699};
3700
3701struct mlx5_ifc_query_vport_state_out_bits {
3702 u8 status[0x8];
b4ff3a36 3703 u8 reserved_at_8[0x18];
e281682b
SM		 3704
3705 u8 syndrome[0x20];
3706
b4ff3a36 3707 u8 reserved_at_40[0x20];
e281682b 3708
b4ff3a36 3709 u8 reserved_at_60[0x18];
e281682b
SM		 3710 u8 admin_state[0x4];
3711 u8 state[0x4];
3712};
3713
3714enum {
3715 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3716 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3717};
3718
3719struct mlx5_ifc_query_vport_state_in_bits {
3720 u8 opcode[0x10];
b4ff3a36 3721 u8 reserved_at_10[0x10];
e281682b 3722
b4ff3a36 3723 u8 reserved_at_20[0x10];
e281682b
SM		 3724 u8 op_mod[0x10];
3725
3726 u8 other_vport[0x1];
b4ff3a36 3727 u8 reserved_at_41[0xf];
e281682b
SM		 3728 u8 vport_number[0x10];
3729
b4ff3a36 3730 u8 reserved_at_60[0x20];
e281682b
SM		 3731};
3732
61c5b5c9
MS		 3733struct mlx5_ifc_query_vnic_env_out_bits {
3734 u8 status[0x8];
3735 u8 reserved_at_8[0x18];
3736
3737 u8 syndrome[0x20];
3738
3739 u8 reserved_at_40[0x40];
3740
3741 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3742};
3743
3744enum {
3745 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3746};
3747
3748struct mlx5_ifc_query_vnic_env_in_bits {
3749 u8 opcode[0x10];
3750 u8 reserved_at_10[0x10];
3751
3752 u8 reserved_at_20[0x10];
3753 u8 op_mod[0x10];
3754
3755 u8 other_vport[0x1];
3756 u8 reserved_at_41[0xf];
3757 u8 vport_number[0x10];
3758
3759 u8 reserved_at_60[0x20];
3760};
3761
e281682b
SM		 3762struct mlx5_ifc_query_vport_counter_out_bits {
3763 u8 status[0x8];
b4ff3a36 3764 u8 reserved_at_8[0x18];
e281682b
SM		 3765
3766 u8 syndrome[0x20];
3767
b4ff3a36 3768 u8 reserved_at_40[0x40];
e281682b
SM		 3769
3770 struct mlx5_ifc_traffic_counter_bits received_errors;
3771
3772 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3773
3774 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3775
3776 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3777
3778 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3779
3780 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3781
3782 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3783
3784 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3785
3786 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3787
3788 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3789
3790 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3791
3792 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3793
b4ff3a36 3794 u8 reserved_at_680[0xa00];
e281682b
SM		 3795};
3796
3797enum {
3798 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3799};
3800
3801struct mlx5_ifc_query_vport_counter_in_bits {
3802 u8 opcode[0x10];
b4ff3a36 3803 u8 reserved_at_10[0x10];
e281682b 3804
b4ff3a36 3805 u8 reserved_at_20[0x10];
e281682b
SM		 3806 u8 op_mod[0x10];
3807
3808 u8 other_vport[0x1];
b54ba277
MY		 3809 u8 reserved_at_41[0xb];
3810 u8 port_num[0x4];
e281682b
SM		 3811 u8 vport_number[0x10];
3812
b4ff3a36 3813 u8 reserved_at_60[0x60];
e281682b
SM		 3814
3815 u8 clear[0x1];
b4ff3a36 3816 u8 reserved_at_c1[0x1f];
e281682b 3817
b4ff3a36 3818 u8 reserved_at_e0[0x20];
e281682b
SM		 3819};
3820
3821struct mlx5_ifc_query_tis_out_bits {
3822 u8 status[0x8];
b4ff3a36 3823 u8 reserved_at_8[0x18];
e281682b
SM		 3824
3825 u8 syndrome[0x20];
3826
b4ff3a36 3827 u8 reserved_at_40[0x40];
e281682b
SM		 3828
3829 struct mlx5_ifc_tisc_bits tis_context;
3830};
3831
3832struct mlx5_ifc_query_tis_in_bits {
3833 u8 opcode[0x10];
b4ff3a36 3834 u8 reserved_at_10[0x10];
e281682b 3835
b4ff3a36 3836 u8 reserved_at_20[0x10];
e281682b
SM		 3837 u8 op_mod[0x10];
3838
b4ff3a36 3839 u8 reserved_at_40[0x8];
e281682b
SM		 3840 u8 tisn[0x18];
3841
b4ff3a36 3842 u8 reserved_at_60[0x20];
e281682b
SM		 3843};
3844
3845struct mlx5_ifc_query_tir_out_bits {
3846 u8 status[0x8];
b4ff3a36 3847 u8 reserved_at_8[0x18];
e281682b
SM		 3848
3849 u8 syndrome[0x20];
3850
b4ff3a36 3851 u8 reserved_at_40[0xc0];
e281682b
SM		 3852
3853 struct mlx5_ifc_tirc_bits tir_context;
3854};
3855
3856struct mlx5_ifc_query_tir_in_bits {
3857 u8 opcode[0x10];
b4ff3a36 3858 u8 reserved_at_10[0x10];
e281682b 3859
b4ff3a36 3860 u8 reserved_at_20[0x10];
e281682b
SM		 3861 u8 op_mod[0x10];
3862
b4ff3a36 3863 u8 reserved_at_40[0x8];
e281682b
SM		 3864 u8 tirn[0x18];
3865
b4ff3a36 3866 u8 reserved_at_60[0x20];
e281682b
SM		 3867};
3868
3869struct mlx5_ifc_query_srq_out_bits {
3870 u8 status[0x8];
b4ff3a36 3871 u8 reserved_at_8[0x18];
e281682b
SM		 3872
3873 u8 syndrome[0x20];
3874
b4ff3a36 3875 u8 reserved_at_40[0x40];
e281682b
SM		 3876
3877 struct mlx5_ifc_srqc_bits srq_context_entry;
3878
b4ff3a36 3879 u8 reserved_at_280[0x600];
e281682b
SM		 3880
3881 u8 pas[0][0x40];
3882};
3883
3884struct mlx5_ifc_query_srq_in_bits {
3885 u8 opcode[0x10];
b4ff3a36 3886 u8 reserved_at_10[0x10];
e281682b 3887
b4ff3a36 3888 u8 reserved_at_20[0x10];
e281682b
SM		 3889 u8 op_mod[0x10];
3890
b4ff3a36 3891 u8 reserved_at_40[0x8];
e281682b
SM		 3892 u8 srqn[0x18];
3893
b4ff3a36 3894 u8 reserved_at_60[0x20];
e281682b
SM		 3895};
3896
3897struct mlx5_ifc_query_sq_out_bits {
3898 u8 status[0x8];
b4ff3a36 3899 u8 reserved_at_8[0x18];
e281682b
SM		 3900
3901 u8 syndrome[0x20];
3902
b4ff3a36 3903 u8 reserved_at_40[0xc0];
e281682b
SM		 3904
3905 struct mlx5_ifc_sqc_bits sq_context;
3906};
3907
3908struct mlx5_ifc_query_sq_in_bits {
3909 u8 opcode[0x10];
b4ff3a36 3910 u8 reserved_at_10[0x10];
e281682b 3911
b4ff3a36 3912 u8 reserved_at_20[0x10];
e281682b
SM		 3913 u8 op_mod[0x10];
3914
b4ff3a36 3915 u8 reserved_at_40[0x8];
e281682b
SM		 3916 u8 sqn[0x18];
3917
b4ff3a36 3918 u8 reserved_at_60[0x20];
e281682b
SM		 3919};
3920
3921struct mlx5_ifc_query_special_contexts_out_bits {
3922 u8 status[0x8];
b4ff3a36 3923 u8 reserved_at_8[0x18];
e281682b
SM		 3924
3925 u8 syndrome[0x20];
3926
ec22eb53 3927 u8 dump_fill_mkey[0x20];
e281682b
SM		 3928
3929 u8 resd_lkey[0x20];
bcda1aca
AK		 3930
3931 u8 null_mkey[0x20];
3932
3933 u8 reserved_at_a0[0x60];
e281682b
SM		 3934};
3935
3936struct mlx5_ifc_query_special_contexts_in_bits {
3937 u8 opcode[0x10];
b4ff3a36 3938 u8 reserved_at_10[0x10];
e281682b 3939
b4ff3a36 3940 u8 reserved_at_20[0x10];
e281682b
SM		 3941 u8 op_mod[0x10];
3942
b4ff3a36 3943 u8 reserved_at_40[0x40];
e281682b
SM		 3944};
3945
813f8540
MHY		 3946struct mlx5_ifc_query_scheduling_element_out_bits {
3947 u8 opcode[0x10];
3948 u8 reserved_at_10[0x10];
3949
3950 u8 reserved_at_20[0x10];
3951 u8 op_mod[0x10];
3952
3953 u8 reserved_at_40[0xc0];
3954
3955 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3956
3957 u8 reserved_at_300[0x100];
3958};
3959
3960enum {
3961 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3962};
3963
3964struct mlx5_ifc_query_scheduling_element_in_bits {
3965 u8 opcode[0x10];
3966 u8 reserved_at_10[0x10];
3967
3968 u8 reserved_at_20[0x10];
3969 u8 op_mod[0x10];
3970
3971 u8 scheduling_hierarchy[0x8];
3972 u8 reserved_at_48[0x18];
3973
3974 u8 scheduling_element_id[0x20];
3975
3976 u8 reserved_at_80[0x180];
3977};
3978
e281682b
SM		 3979struct mlx5_ifc_query_rqt_out_bits {
3980 u8 status[0x8];
b4ff3a36 3981 u8 reserved_at_8[0x18];
e281682b
SM		 3982
3983 u8 syndrome[0x20];
3984
b4ff3a36 3985 u8 reserved_at_40[0xc0];
e281682b
SM		 3986
3987 struct mlx5_ifc_rqtc_bits rqt_context;
3988};
3989
3990struct mlx5_ifc_query_rqt_in_bits {
3991 u8 opcode[0x10];
b4ff3a36 3992 u8 reserved_at_10[0x10];
e281682b 3993
b4ff3a36 3994 u8 reserved_at_20[0x10];
e281682b
SM		 3995 u8 op_mod[0x10];
3996
b4ff3a36 3997 u8 reserved_at_40[0x8];
e281682b
SM		 3998 u8 rqtn[0x18];
3999
b4ff3a36 4000 u8 reserved_at_60[0x20];
e281682b
SM		 4001};
4002
4003struct mlx5_ifc_query_rq_out_bits {
4004 u8 status[0x8];
b4ff3a36 4005 u8 reserved_at_8[0x18];
e281682b
SM		 4006
4007 u8 syndrome[0x20];
4008
b4ff3a36 4009 u8 reserved_at_40[0xc0];
e281682b
SM		 4010
4011 struct mlx5_ifc_rqc_bits rq_context;
4012};
4013
4014struct mlx5_ifc_query_rq_in_bits {
4015 u8 opcode[0x10];
b4ff3a36 4016 u8 reserved_at_10[0x10];
e281682b 4017
b4ff3a36 4018 u8 reserved_at_20[0x10];
e281682b
SM		 4019 u8 op_mod[0x10];
4020
b4ff3a36 4021 u8 reserved_at_40[0x8];
e281682b
SM		 4022 u8 rqn[0x18];
4023
b4ff3a36 4024 u8 reserved_at_60[0x20];
e281682b
SM		 4025};
4026
4027struct mlx5_ifc_query_roce_address_out_bits {
4028 u8 status[0x8];
b4ff3a36 4029 u8 reserved_at_8[0x18];
e281682b
SM		 4030
4031 u8 syndrome[0x20];
4032
b4ff3a36 4033 u8 reserved_at_40[0x40];
e281682b
SM		 4034
4035 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4036};
4037
4038struct mlx5_ifc_query_roce_address_in_bits {
4039 u8 opcode[0x10];
b4ff3a36 4040 u8 reserved_at_10[0x10];
e281682b 4041
b4ff3a36 4042 u8 reserved_at_20[0x10];
e281682b
SM		 4043 u8 op_mod[0x10];
4044
4045 u8 roce_address_index[0x10];
32f69e4b
DJ		 4046 u8 reserved_at_50[0xc];
4047 u8 vhca_port_num[0x4];
e281682b 4048
b4ff3a36 4049 u8 reserved_at_60[0x20];
e281682b
SM		 4050};
4051
4052struct mlx5_ifc_query_rmp_out_bits {
4053 u8 status[0x8];
b4ff3a36 4054 u8 reserved_at_8[0x18];
e281682b
SM		 4055
4056 u8 syndrome[0x20];
4057
b4ff3a36 4058 u8 reserved_at_40[0xc0];
e281682b
SM		 4059
4060 struct mlx5_ifc_rmpc_bits rmp_context;
4061};
4062
4063struct mlx5_ifc_query_rmp_in_bits {
4064 u8 opcode[0x10];
b4ff3a36 4065 u8 reserved_at_10[0x10];
e281682b 4066
b4ff3a36 4067 u8 reserved_at_20[0x10];
e281682b
SM		 4068 u8 op_mod[0x10];
4069
b4ff3a36 4070 u8 reserved_at_40[0x8];
e281682b
SM		 4071 u8 rmpn[0x18];
4072
b4ff3a36 4073 u8 reserved_at_60[0x20];
e281682b
SM		 4074};
4075
4076struct mlx5_ifc_query_qp_out_bits {
4077 u8 status[0x8];
b4ff3a36 4078 u8 reserved_at_8[0x18];
e281682b
SM		 4079
4080 u8 syndrome[0x20];
4081
b4ff3a36 4082 u8 reserved_at_40[0x40];
e281682b
SM		 4083
4084 u8 opt_param_mask[0x20];
4085
b4ff3a36 4086 u8 reserved_at_a0[0x20];
e281682b
SM		 4087
4088 struct mlx5_ifc_qpc_bits qpc;
4089
b4ff3a36 4090 u8 reserved_at_800[0x80];
e281682b
SM		 4091
4092 u8 pas[0][0x40];
4093};
4094
4095struct mlx5_ifc_query_qp_in_bits {
4096 u8 opcode[0x10];
b4ff3a36 4097 u8 reserved_at_10[0x10];
e281682b 4098
b4ff3a36 4099 u8 reserved_at_20[0x10];
e281682b
SM		 4100 u8 op_mod[0x10];
4101
b4ff3a36 4102 u8 reserved_at_40[0x8];
e281682b
SM		 4103 u8 qpn[0x18];
4104
b4ff3a36 4105 u8 reserved_at_60[0x20];
e281682b
SM		 4106};
4107
4108struct mlx5_ifc_query_q_counter_out_bits {
4109 u8 status[0x8];
b4ff3a36 4110 u8 reserved_at_8[0x18];
e281682b
SM		 4111
4112 u8 syndrome[0x20];
4113
b4ff3a36 4114 u8 reserved_at_40[0x40];
e281682b
SM		 4115
4116 u8 rx_write_requests[0x20];
4117
b4ff3a36 4118 u8 reserved_at_a0[0x20];
e281682b
SM		 4119
4120 u8 rx_read_requests[0x20];
4121
b4ff3a36 4122 u8 reserved_at_e0[0x20];
e281682b
SM		 4123
4124 u8 rx_atomic_requests[0x20];
4125
b4ff3a36 4126 u8 reserved_at_120[0x20];
e281682b
SM		 4127
4128 u8 rx_dct_connect[0x20];
4129
b4ff3a36 4130 u8 reserved_at_160[0x20];
e281682b
SM		 4131
4132 u8 out_of_buffer[0x20];
4133
b4ff3a36 4134 u8 reserved_at_1a0[0x20];
e281682b
SM		 4135
4136 u8 out_of_sequence[0x20];
4137
7486216b
SM		 4138 u8 reserved_at_1e0[0x20];
4139
4140 u8 duplicate_request[0x20];
4141
4142 u8 reserved_at_220[0x20];
4143
4144 u8 rnr_nak_retry_err[0x20];
4145
4146 u8 reserved_at_260[0x20];
4147
4148 u8 packet_seq_err[0x20];
4149
4150 u8 reserved_at_2a0[0x20];
4151
4152 u8 implied_nak_seq_err[0x20];
4153
4154 u8 reserved_at_2e0[0x20];
4155
4156 u8 local_ack_timeout_err[0x20];
4157
58dcb60a
PP		 4158 u8 reserved_at_320[0xa0];
4159
4160 u8 resp_local_length_error[0x20];
4161
4162 u8 req_local_length_error[0x20];
4163
4164 u8 resp_local_qp_error[0x20];
4165
4166 u8 local_operation_error[0x20];
4167
4168 u8 resp_local_protection[0x20];
4169
4170 u8 req_local_protection[0x20];
4171
4172 u8 resp_cqe_error[0x20];
4173
4174 u8 req_cqe_error[0x20];
4175
4176 u8 req_mw_binding[0x20];
4177
4178 u8 req_bad_response[0x20];
4179
4180 u8 req_remote_invalid_request[0x20];
4181
4182 u8 resp_remote_invalid_request[0x20];
4183
4184 u8 req_remote_access_errors[0x20];
4185
4186 u8 resp_remote_access_errors[0x20];
4187
4188 u8 req_remote_operation_errors[0x20];
4189
4190 u8 req_transport_retries_exceeded[0x20];
4191
4192 u8 cq_overflow[0x20];
4193
4194 u8 resp_cqe_flush_error[0x20];
4195
4196 u8 req_cqe_flush_error[0x20];
4197
4198 u8 reserved_at_620[0x1e0];
e281682b
SM		 4199};
4200
4201struct mlx5_ifc_query_q_counter_in_bits {
4202 u8 opcode[0x10];
b4ff3a36 4203 u8 reserved_at_10[0x10];
e281682b 4204
b4ff3a36 4205 u8 reserved_at_20[0x10];
e281682b
SM		 4206 u8 op_mod[0x10];
4207
b4ff3a36 4208 u8 reserved_at_40[0x80];
e281682b
SM		 4209
4210 u8 clear[0x1];
b4ff3a36 4211 u8 reserved_at_c1[0x1f];
e281682b 4212
b4ff3a36 4213 u8 reserved_at_e0[0x18];
e281682b
SM		 4214 u8 counter_set_id[0x8];
4215};
4216
4217struct mlx5_ifc_query_pages_out_bits {
4218 u8 status[0x8];
b4ff3a36 4219 u8 reserved_at_8[0x18];
e281682b
SM		 4220
4221 u8 syndrome[0x20];
4222
b4ff3a36 4223 u8 reserved_at_40[0x10];
e281682b
SM		 4224 u8 function_id[0x10];
4225
4226 u8 num_pages[0x20];
4227};
4228
4229enum {
4230 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4231 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4232 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4233};
4234
4235struct mlx5_ifc_query_pages_in_bits {
4236 u8 opcode[0x10];
b4ff3a36 4237 u8 reserved_at_10[0x10];
e281682b 4238
b4ff3a36 4239 u8 reserved_at_20[0x10];
e281682b
SM		 4240 u8 op_mod[0x10];
4241
b4ff3a36 4242 u8 reserved_at_40[0x10];
e281682b
SM		 4243 u8 function_id[0x10];
4244
b4ff3a36 4245 u8 reserved_at_60[0x20];
e281682b
SM		 4246};
4247
4248struct mlx5_ifc_query_nic_vport_context_out_bits {
4249 u8 status[0x8];
b4ff3a36 4250 u8 reserved_at_8[0x18];
e281682b
SM		 4251
4252 u8 syndrome[0x20];
4253
b4ff3a36 4254 u8 reserved_at_40[0x40];
e281682b
SM		 4255
4256 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4257};
4258
4259struct mlx5_ifc_query_nic_vport_context_in_bits {
4260 u8 opcode[0x10];
b4ff3a36 4261 u8 reserved_at_10[0x10];
e281682b 4262
b4ff3a36 4263 u8 reserved_at_20[0x10];
e281682b
SM		 4264 u8 op_mod[0x10];
4265
4266 u8 other_vport[0x1];
b4ff3a36 4267 u8 reserved_at_41[0xf];
e281682b
SM		 4268 u8 vport_number[0x10];
4269
b4ff3a36 4270 u8 reserved_at_60[0x5];
e281682b 4271 u8 allowed_list_type[0x3];
b4ff3a36 4272 u8 reserved_at_68[0x18];
e281682b
SM		 4273};
4274
4275struct mlx5_ifc_query_mkey_out_bits {
4276 u8 status[0x8];
b4ff3a36 4277 u8 reserved_at_8[0x18];
e281682b
SM		 4278
4279 u8 syndrome[0x20];
4280
b4ff3a36 4281 u8 reserved_at_40[0x40];
e281682b
SM		 4282
4283 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4284
b4ff3a36 4285 u8 reserved_at_280[0x600];
e281682b
SM		 4286
4287 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4288
4289 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4290};
4291
4292struct mlx5_ifc_query_mkey_in_bits {
4293 u8 opcode[0x10];
b4ff3a36 4294 u8 reserved_at_10[0x10];
e281682b 4295
b4ff3a36 4296 u8 reserved_at_20[0x10];
e281682b
SM		 4297 u8 op_mod[0x10];
4298
b4ff3a36 4299 u8 reserved_at_40[0x8];
e281682b
SM		 4300 u8 mkey_index[0x18];
4301
4302 u8 pg_access[0x1];
b4ff3a36 4303 u8 reserved_at_61[0x1f];
e281682b
SM		 4304};
4305
4306struct mlx5_ifc_query_mad_demux_out_bits {
4307 u8 status[0x8];
b4ff3a36 4308 u8 reserved_at_8[0x18];
e281682b
SM		 4309
4310 u8 syndrome[0x20];
4311
b4ff3a36 4312 u8 reserved_at_40[0x40];
e281682b
SM		 4313
4314 u8 mad_dumux_parameters_block[0x20];
4315};
4316
4317struct mlx5_ifc_query_mad_demux_in_bits {
4318 u8 opcode[0x10];
b4ff3a36 4319 u8 reserved_at_10[0x10];
e281682b 4320
b4ff3a36 4321 u8 reserved_at_20[0x10];
e281682b
SM		 4322 u8 op_mod[0x10];
4323
b4ff3a36 4324 u8 reserved_at_40[0x40];
e281682b
SM		 4325};
4326
4327struct mlx5_ifc_query_l2_table_entry_out_bits {
4328 u8 status[0x8];
b4ff3a36 4329 u8 reserved_at_8[0x18];
e281682b
SM		 4330
4331 u8 syndrome[0x20];
4332
b4ff3a36 4333 u8 reserved_at_40[0xa0];
e281682b 4334
b4ff3a36 4335 u8 reserved_at_e0[0x13];
e281682b
SM		 4336 u8 vlan_valid[0x1];
4337 u8 vlan[0xc];
4338
4339 struct mlx5_ifc_mac_address_layout_bits mac_address;
4340
b4ff3a36 4341 u8 reserved_at_140[0xc0];
e281682b
SM		 4342};
4343
4344struct mlx5_ifc_query_l2_table_entry_in_bits {
4345 u8 opcode[0x10];
b4ff3a36 4346 u8 reserved_at_10[0x10];
e281682b 4347
b4ff3a36 4348 u8 reserved_at_20[0x10];
e281682b
SM		 4349 u8 op_mod[0x10];
4350
b4ff3a36 4351 u8 reserved_at_40[0x60];
e281682b 4352
b4ff3a36 4353 u8 reserved_at_a0[0x8];
e281682b
SM		 4354 u8 table_index[0x18];
4355
b4ff3a36 4356 u8 reserved_at_c0[0x140];
e281682b
SM		 4357};
4358
4359struct mlx5_ifc_query_issi_out_bits {
4360 u8 status[0x8];
b4ff3a36 4361 u8 reserved_at_8[0x18];
e281682b
SM		 4362
4363 u8 syndrome[0x20];
4364
b4ff3a36 4365 u8 reserved_at_40[0x10];
e281682b
SM		 4366 u8 current_issi[0x10];
4367
b4ff3a36 4368 u8 reserved_at_60[0xa0];
e281682b 4369
b4ff3a36 4370 u8 reserved_at_100[76][0x8];
e281682b
SM		 4371 u8 supported_issi_dw0[0x20];
4372};
4373
4374struct mlx5_ifc_query_issi_in_bits {
4375 u8 opcode[0x10];
b4ff3a36 4376 u8 reserved_at_10[0x10];
e281682b 4377
b4ff3a36 4378 u8 reserved_at_20[0x10];
e281682b
SM		 4379 u8 op_mod[0x10];
4380
b4ff3a36 4381 u8 reserved_at_40[0x40];
e281682b
SM		 4382};
4383
0dbc6fe0
SM		 4384struct mlx5_ifc_set_driver_version_out_bits {
4385 u8 status[0x8];
4386 u8 reserved_0[0x18];
4387
4388 u8 syndrome[0x20];
4389 u8 reserved_1[0x40];
4390};
4391
4392struct mlx5_ifc_set_driver_version_in_bits {
4393 u8 opcode[0x10];
4394 u8 reserved_0[0x10];
4395
4396 u8 reserved_1[0x10];
4397 u8 op_mod[0x10];
4398
4399 u8 reserved_2[0x40];
4400 u8 driver_version[64][0x8];
4401};
4402
e281682b
SM		 4403struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4404 u8 status[0x8];
b4ff3a36 4405 u8 reserved_at_8[0x18];
e281682b
SM		 4406
4407 u8 syndrome[0x20];
4408
b4ff3a36 4409 u8 reserved_at_40[0x40];
e281682b
SM		 4410
4411 struct mlx5_ifc_pkey_bits pkey[0];
4412};
4413
4414struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4415 u8 opcode[0x10];
b4ff3a36 4416 u8 reserved_at_10[0x10];
e281682b 4417
b4ff3a36 4418 u8 reserved_at_20[0x10];
e281682b
SM		 4419 u8 op_mod[0x10];
4420
4421 u8 other_vport[0x1];
b4ff3a36 4422 u8 reserved_at_41[0xb];
707c4602 4423 u8 port_num[0x4];
e281682b
SM		 4424 u8 vport_number[0x10];
4425
b4ff3a36 4426 u8 reserved_at_60[0x10];
e281682b
SM		 4427 u8 pkey_index[0x10];
4428};
4429
eff901d3
EC		 4430enum {
4431 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4432 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4433 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4434};
4435
e281682b
SM		 4436struct mlx5_ifc_query_hca_vport_gid_out_bits {
4437 u8 status[0x8];
b4ff3a36 4438 u8 reserved_at_8[0x18];
e281682b
SM		 4439
4440 u8 syndrome[0x20];
4441
b4ff3a36 4442 u8 reserved_at_40[0x20];
e281682b
SM		 4443
4444 u8 gids_num[0x10];
b4ff3a36 4445 u8 reserved_at_70[0x10];
e281682b
SM		 4446
4447 struct mlx5_ifc_array128_auto_bits gid[0];
4448};
4449
4450struct mlx5_ifc_query_hca_vport_gid_in_bits {
4451 u8 opcode[0x10];
b4ff3a36 4452 u8 reserved_at_10[0x10];
e281682b 4453
b4ff3a36 4454 u8 reserved_at_20[0x10];
e281682b
SM		 4455 u8 op_mod[0x10];
4456
4457 u8 other_vport[0x1];
b4ff3a36 4458 u8 reserved_at_41[0xb];
707c4602 4459 u8 port_num[0x4];
e281682b
SM		 4460 u8 vport_number[0x10];
4461
b4ff3a36 4462 u8 reserved_at_60[0x10];
e281682b
SM		 4463 u8 gid_index[0x10];
4464};
4465
4466struct mlx5_ifc_query_hca_vport_context_out_bits {
4467 u8 status[0x8];
b4ff3a36 4468 u8 reserved_at_8[0x18];
e281682b
SM		 4469
4470 u8 syndrome[0x20];
4471
b4ff3a36 4472 u8 reserved_at_40[0x40];
e281682b
SM		 4473
4474 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4475};
4476
4477struct mlx5_ifc_query_hca_vport_context_in_bits {
4478 u8 opcode[0x10];
b4ff3a36 4479 u8 reserved_at_10[0x10];
e281682b 4480
b4ff3a36 4481 u8 reserved_at_20[0x10];
e281682b
SM		 4482 u8 op_mod[0x10];
4483
4484 u8 other_vport[0x1];
b4ff3a36 4485 u8 reserved_at_41[0xb];
707c4602 4486 u8 port_num[0x4];
e281682b
SM		 4487 u8 vport_number[0x10];
4488
b4ff3a36 4489 u8 reserved_at_60[0x20];
e281682b
SM		 4490};
4491
4492struct mlx5_ifc_query_hca_cap_out_bits {
4493 u8 status[0x8];
b4ff3a36 4494 u8 reserved_at_8[0x18];
e281682b
SM		 4495
4496 u8 syndrome[0x20];
4497
b4ff3a36 4498 u8 reserved_at_40[0x40];
e281682b
SM		 4499
4500 union mlx5_ifc_hca_cap_union_bits capability;
4501};
4502
4503struct mlx5_ifc_query_hca_cap_in_bits {
4504 u8 opcode[0x10];
b4ff3a36 4505 u8 reserved_at_10[0x10];
e281682b 4506
b4ff3a36 4507 u8 reserved_at_20[0x10];
e281682b
SM		 4508 u8 op_mod[0x10];
4509
b4ff3a36 4510 u8 reserved_at_40[0x40];
e281682b
SM		 4511};
4512
4513struct mlx5_ifc_query_flow_table_out_bits {
4514 u8 status[0x8];
b4ff3a36 4515 u8 reserved_at_8[0x18];
e281682b
SM		 4516
4517 u8 syndrome[0x20];
4518
b4ff3a36 4519 u8 reserved_at_40[0x80];
e281682b 4520
b4ff3a36 4521 u8 reserved_at_c0[0x8];
e281682b 4522 u8 level[0x8];
b4ff3a36 4523 u8 reserved_at_d0[0x8];
e281682b
SM		 4524 u8 log_size[0x8];
4525
b4ff3a36 4526 u8 reserved_at_e0[0x120];
e281682b
SM		 4527};
4528
4529struct mlx5_ifc_query_flow_table_in_bits {
4530 u8 opcode[0x10];
b4ff3a36 4531 u8 reserved_at_10[0x10];
e281682b 4532
b4ff3a36 4533 u8 reserved_at_20[0x10];
e281682b
SM		 4534 u8 op_mod[0x10];
4535
b4ff3a36 4536 u8 reserved_at_40[0x40];
e281682b
SM		 4537
4538 u8 table_type[0x8];
b4ff3a36 4539 u8 reserved_at_88[0x18];
e281682b 4540
b4ff3a36 4541 u8 reserved_at_a0[0x8];
e281682b
SM		 4542 u8 table_id[0x18];
4543
b4ff3a36 4544 u8 reserved_at_c0[0x140];
e281682b
SM		 4545};
4546
4547struct mlx5_ifc_query_fte_out_bits {
4548 u8 status[0x8];
b4ff3a36 4549 u8 reserved_at_8[0x18];
e281682b
SM		 4550
4551 u8 syndrome[0x20];
4552
b4ff3a36 4553 u8 reserved_at_40[0x1c0];
e281682b
SM		 4554
4555 struct mlx5_ifc_flow_context_bits flow_context;
4556};
4557
4558struct mlx5_ifc_query_fte_in_bits {
4559 u8 opcode[0x10];
b4ff3a36 4560 u8 reserved_at_10[0x10];
e281682b 4561
b4ff3a36 4562 u8 reserved_at_20[0x10];
e281682b
SM		 4563 u8 op_mod[0x10];
4564
b4ff3a36 4565 u8 reserved_at_40[0x40];
e281682b
SM		 4566
4567 u8 table_type[0x8];
b4ff3a36 4568 u8 reserved_at_88[0x18];
e281682b 4569
b4ff3a36 4570 u8 reserved_at_a0[0x8];
e281682b
SM		 4571 u8 table_id[0x18];
4572
b4ff3a36 4573 u8 reserved_at_c0[0x40];
e281682b
SM		 4574
4575 u8 flow_index[0x20];
4576
b4ff3a36 4577 u8 reserved_at_120[0xe0];
e281682b
SM		 4578};
4579
4580enum {
4581 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4582 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4583 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4584};
4585
4586struct mlx5_ifc_query_flow_group_out_bits {
4587 u8 status[0x8];
b4ff3a36 4588 u8 reserved_at_8[0x18];
e281682b
SM		 4589
4590 u8 syndrome[0x20];
4591
b4ff3a36 4592 u8 reserved_at_40[0xa0];
e281682b
SM		 4593
4594 u8 start_flow_index[0x20];
4595
b4ff3a36 4596 u8 reserved_at_100[0x20];
e281682b
SM		 4597
4598 u8 end_flow_index[0x20];
4599
b4ff3a36 4600 u8 reserved_at_140[0xa0];
e281682b 4601
b4ff3a36 4602 u8 reserved_at_1e0[0x18];
e281682b
SM		 4603 u8 match_criteria_enable[0x8];
4604
4605 struct mlx5_ifc_fte_match_param_bits match_criteria;
4606
b4ff3a36 4607 u8 reserved_at_1200[0xe00];
e281682b
SM		 4608};
4609
4610struct mlx5_ifc_query_flow_group_in_bits {
4611 u8 opcode[0x10];
b4ff3a36 4612 u8 reserved_at_10[0x10];
e281682b 4613
b4ff3a36 4614 u8 reserved_at_20[0x10];
e281682b
SM		 4615 u8 op_mod[0x10];
4616
b4ff3a36 4617 u8 reserved_at_40[0x40];
e281682b
SM		 4618
4619 u8 table_type[0x8];
b4ff3a36 4620 u8 reserved_at_88[0x18];
e281682b 4621
b4ff3a36 4622 u8 reserved_at_a0[0x8];
e281682b
SM		 4623 u8 table_id[0x18];
4624
4625 u8 group_id[0x20];
4626
b4ff3a36 4627 u8 reserved_at_e0[0x120];
e281682b
SM		 4628};
4629
9dc0b289
AV		 4630struct mlx5_ifc_query_flow_counter_out_bits {
4631 u8 status[0x8];
4632 u8 reserved_at_8[0x18];
4633
4634 u8 syndrome[0x20];
4635
4636 u8 reserved_at_40[0x40];
4637
4638 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4639};
4640
4641struct mlx5_ifc_query_flow_counter_in_bits {
4642 u8 opcode[0x10];
4643 u8 reserved_at_10[0x10];
4644
4645 u8 reserved_at_20[0x10];
4646 u8 op_mod[0x10];
4647
4648 u8 reserved_at_40[0x80];
4649
4650 u8 clear[0x1];
4651 u8 reserved_at_c1[0xf];
4652 u8 num_of_counters[0x10];
4653
a8ffcc74 4654 u8 flow_counter_id[0x20];
9dc0b289
AV		 4655};
4656
d6666753
SM		 4657struct mlx5_ifc_query_esw_vport_context_out_bits {
4658 u8 status[0x8];
b4ff3a36 4659 u8 reserved_at_8[0x18];
d6666753
SM		 4660
4661 u8 syndrome[0x20];
4662
b4ff3a36 4663 u8 reserved_at_40[0x40];
d6666753
SM		 4664
4665 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4666};
4667
4668struct mlx5_ifc_query_esw_vport_context_in_bits {
4669 u8 opcode[0x10];
b4ff3a36 4670 u8 reserved_at_10[0x10];
d6666753 4671
b4ff3a36 4672 u8 reserved_at_20[0x10];
d6666753
SM		 4673 u8 op_mod[0x10];
4674
4675 u8 other_vport[0x1];
b4ff3a36 4676 u8 reserved_at_41[0xf];
d6666753
SM		 4677 u8 vport_number[0x10];
4678
b4ff3a36 4679 u8 reserved_at_60[0x20];
d6666753
SM		 4680};
4681
4682struct mlx5_ifc_modify_esw_vport_context_out_bits {
4683 u8 status[0x8];
b4ff3a36 4684 u8 reserved_at_8[0x18];
d6666753
SM		 4685
4686 u8 syndrome[0x20];
4687
b4ff3a36 4688 u8 reserved_at_40[0x40];
d6666753
SM		 4689};
4690
4691struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4692 u8 reserved_at_0[0x1c];
d6666753
SM		 4693 u8 vport_cvlan_insert[0x1];
4694 u8 vport_svlan_insert[0x1];
4695 u8 vport_cvlan_strip[0x1];
4696 u8 vport_svlan_strip[0x1];
4697};
4698
4699struct mlx5_ifc_modify_esw_vport_context_in_bits {
4700 u8 opcode[0x10];
b4ff3a36 4701 u8 reserved_at_10[0x10];
d6666753 4702
b4ff3a36 4703 u8 reserved_at_20[0x10];
d6666753
SM		 4704 u8 op_mod[0x10];
4705
4706 u8 other_vport[0x1];
b4ff3a36 4707 u8 reserved_at_41[0xf];
d6666753
SM		 4708 u8 vport_number[0x10];
4709
4710 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4711
4712 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4713};
4714
e281682b
SM		 4715struct mlx5_ifc_query_eq_out_bits {
4716 u8 status[0x8];
b4ff3a36 4717 u8 reserved_at_8[0x18];
e281682b
SM		 4718
4719 u8 syndrome[0x20];
4720
b4ff3a36 4721 u8 reserved_at_40[0x40];
e281682b
SM		 4722
4723 struct mlx5_ifc_eqc_bits eq_context_entry;
4724
b4ff3a36 4725 u8 reserved_at_280[0x40];
e281682b
SM		 4726
4727 u8 event_bitmask[0x40];
4728
b4ff3a36 4729 u8 reserved_at_300[0x580];
e281682b
SM		 4730
4731 u8 pas[0][0x40];
4732};
4733
4734struct mlx5_ifc_query_eq_in_bits {
4735 u8 opcode[0x10];
b4ff3a36 4736 u8 reserved_at_10[0x10];
e281682b 4737
b4ff3a36 4738 u8 reserved_at_20[0x10];
e281682b
SM		 4739 u8 op_mod[0x10];
4740
b4ff3a36 4741 u8 reserved_at_40[0x18];
e281682b
SM		 4742 u8 eq_number[0x8];
4743
b4ff3a36 4744 u8 reserved_at_60[0x20];
e281682b
SM		 4745};
4746
7adbde20
HHZ		 4747struct mlx5_ifc_encap_header_in_bits {
4748 u8 reserved_at_0[0x5];
4749 u8 header_type[0x3];
4750 u8 reserved_at_8[0xe];
4751 u8 encap_header_size[0xa];
4752
4753 u8 reserved_at_20[0x10];
4754 u8 encap_header[2][0x8];
4755
4756 u8 more_encap_header[0][0x8];
4757};
4758
4759struct mlx5_ifc_query_encap_header_out_bits {
4760 u8 status[0x8];
4761 u8 reserved_at_8[0x18];
4762
4763 u8 syndrome[0x20];
4764
4765 u8 reserved_at_40[0xa0];
4766
4767 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4768};
4769
4770struct mlx5_ifc_query_encap_header_in_bits {
4771 u8 opcode[0x10];
4772 u8 reserved_at_10[0x10];
4773
4774 u8 reserved_at_20[0x10];
4775 u8 op_mod[0x10];
4776
4777 u8 encap_id[0x20];
4778
4779 u8 reserved_at_60[0xa0];
4780};
4781
4782struct mlx5_ifc_alloc_encap_header_out_bits {
4783 u8 status[0x8];
4784 u8 reserved_at_8[0x18];
4785
4786 u8 syndrome[0x20];
4787
4788 u8 encap_id[0x20];
4789
4790 u8 reserved_at_60[0x20];
4791};
4792
4793struct mlx5_ifc_alloc_encap_header_in_bits {
4794 u8 opcode[0x10];
4795 u8 reserved_at_10[0x10];
4796
4797 u8 reserved_at_20[0x10];
4798 u8 op_mod[0x10];
4799
4800 u8 reserved_at_40[0xa0];
4801
4802 struct mlx5_ifc_encap_header_in_bits encap_header;
4803};
4804
4805struct mlx5_ifc_dealloc_encap_header_out_bits {
4806 u8 status[0x8];
4807 u8 reserved_at_8[0x18];
4808
4809 u8 syndrome[0x20];
4810
4811 u8 reserved_at_40[0x40];
4812};
4813
4814struct mlx5_ifc_dealloc_encap_header_in_bits {
4815 u8 opcode[0x10];
4816 u8 reserved_at_10[0x10];
4817
4818 u8 reserved_20[0x10];
4819 u8 op_mod[0x10];
4820
4821 u8 encap_id[0x20];
4822
4823 u8 reserved_60[0x20];
4824};
4825
2a69cb9f
OG		 4826struct mlx5_ifc_set_action_in_bits {
4827 u8 action_type[0x4];
4828 u8 field[0xc];
4829 u8 reserved_at_10[0x3];
4830 u8 offset[0x5];
4831 u8 reserved_at_18[0x3];
4832 u8 length[0x5];
4833
4834 u8 data[0x20];
4835};
4836
4837struct mlx5_ifc_add_action_in_bits {
4838 u8 action_type[0x4];
4839 u8 field[0xc];
4840 u8 reserved_at_10[0x10];
4841
4842 u8 data[0x20];
4843};
4844
4845union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4846 struct mlx5_ifc_set_action_in_bits set_action_in;
4847 struct mlx5_ifc_add_action_in_bits add_action_in;
4848 u8 reserved_at_0[0x40];
4849};
4850
4851enum {
4852 MLX5_ACTION_TYPE_SET = 0x1,
4853 MLX5_ACTION_TYPE_ADD = 0x2,
4854};
4855
4856enum {
4857 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4858 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4859 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4860 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4861 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4862 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4863 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4864 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4865 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4866 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4867 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4868 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4869 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4870 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4871 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4872 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4873 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4874 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4875 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4876 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4877 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4878 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4879 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4880};
4881
4882struct mlx5_ifc_alloc_modify_header_context_out_bits {
4883 u8 status[0x8];
4884 u8 reserved_at_8[0x18];
4885
4886 u8 syndrome[0x20];
4887
4888 u8 modify_header_id[0x20];
4889
4890 u8 reserved_at_60[0x20];
4891};
4892
4893struct mlx5_ifc_alloc_modify_header_context_in_bits {
4894 u8 opcode[0x10];
4895 u8 reserved_at_10[0x10];
4896
4897 u8 reserved_at_20[0x10];
4898 u8 op_mod[0x10];
4899
4900 u8 reserved_at_40[0x20];
4901
4902 u8 table_type[0x8];
4903 u8 reserved_at_68[0x10];
4904 u8 num_of_actions[0x8];
4905
4906 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4907};
4908
4909struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4910 u8 status[0x8];
4911 u8 reserved_at_8[0x18];
4912
4913 u8 syndrome[0x20];
4914
4915 u8 reserved_at_40[0x40];
4916};
4917
4918struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4919 u8 opcode[0x10];
4920 u8 reserved_at_10[0x10];
4921
4922 u8 reserved_at_20[0x10];
4923 u8 op_mod[0x10];
4924
4925 u8 modify_header_id[0x20];
4926
4927 u8 reserved_at_60[0x20];
4928};
4929
e281682b
SM		 4930struct mlx5_ifc_query_dct_out_bits {
4931 u8 status[0x8];
b4ff3a36 4932 u8 reserved_at_8[0x18];
e281682b
SM		 4933
4934 u8 syndrome[0x20];
4935
b4ff3a36 4936 u8 reserved_at_40[0x40];
e281682b
SM		 4937
4938 struct mlx5_ifc_dctc_bits dct_context_entry;
4939
b4ff3a36 4940 u8 reserved_at_280[0x180];
e281682b
SM		 4941};
4942
4943struct mlx5_ifc_query_dct_in_bits {
4944 u8 opcode[0x10];
b4ff3a36 4945 u8 reserved_at_10[0x10];
e281682b 4946
b4ff3a36 4947 u8 reserved_at_20[0x10];
e281682b
SM		 4948 u8 op_mod[0x10];
4949
b4ff3a36 4950 u8 reserved_at_40[0x8];
e281682b
SM		 4951 u8 dctn[0x18];
4952
b4ff3a36 4953 u8 reserved_at_60[0x20];
e281682b
SM		 4954};
4955
4956struct mlx5_ifc_query_cq_out_bits {
4957 u8 status[0x8];
b4ff3a36 4958 u8 reserved_at_8[0x18];
e281682b
SM		 4959
4960 u8 syndrome[0x20];
4961
b4ff3a36 4962 u8 reserved_at_40[0x40];
e281682b
SM		 4963
4964 struct mlx5_ifc_cqc_bits cq_context;
4965
b4ff3a36 4966 u8 reserved_at_280[0x600];
e281682b
SM		 4967
4968 u8 pas[0][0x40];
4969};
4970
4971struct mlx5_ifc_query_cq_in_bits {
4972 u8 opcode[0x10];
b4ff3a36 4973 u8 reserved_at_10[0x10];
e281682b 4974
b4ff3a36 4975 u8 reserved_at_20[0x10];
e281682b
SM		 4976 u8 op_mod[0x10];
4977
b4ff3a36 4978 u8 reserved_at_40[0x8];
e281682b
SM		 4979 u8 cqn[0x18];
4980
b4ff3a36 4981 u8 reserved_at_60[0x20];
e281682b
SM		 4982};
4983
4984struct mlx5_ifc_query_cong_status_out_bits {
4985 u8 status[0x8];
b4ff3a36 4986 u8 reserved_at_8[0x18];
e281682b
SM		 4987
4988 u8 syndrome[0x20];
4989
b4ff3a36 4990 u8 reserved_at_40[0x20];
e281682b
SM		 4991
4992 u8 enable[0x1];
4993 u8 tag_enable[0x1];
b4ff3a36 4994 u8 reserved_at_62[0x1e];
e281682b
SM		 4995};
4996
4997struct mlx5_ifc_query_cong_status_in_bits {
4998 u8 opcode[0x10];
b4ff3a36 4999 u8 reserved_at_10[0x10];
e281682b 5000
b4ff3a36 5001 u8 reserved_at_20[0x10];
e281682b
SM		 5002 u8 op_mod[0x10];
5003
b4ff3a36 5004 u8 reserved_at_40[0x18];
e281682b
SM		 5005 u8 priority[0x4];
5006 u8 cong_protocol[0x4];
5007
b4ff3a36 5008 u8 reserved_at_60[0x20];
e281682b
SM		 5009};
5010
5011struct mlx5_ifc_query_cong_statistics_out_bits {
5012 u8 status[0x8];
b4ff3a36 5013 u8 reserved_at_8[0x18];
e281682b
SM		 5014
5015 u8 syndrome[0x20];
5016
b4ff3a36 5017 u8 reserved_at_40[0x40];
e281682b 5018
e1f24a79 5019 u8 rp_cur_flows[0x20];
e281682b
SM		 5020
5021 u8 sum_flows[0x20];
5022
e1f24a79 5023 u8 rp_cnp_ignored_high[0x20];
e281682b 5024
e1f24a79 5025 u8 rp_cnp_ignored_low[0x20];
e281682b 5026
e1f24a79 5027 u8 rp_cnp_handled_high[0x20];
e281682b 5028
e1f24a79 5029 u8 rp_cnp_handled_low[0x20];
e281682b 5030
b4ff3a36 5031 u8 reserved_at_140[0x100];
e281682b
SM		 5032
5033 u8 time_stamp_high[0x20];
5034
5035 u8 time_stamp_low[0x20];
5036
5037 u8 accumulators_period[0x20];
5038
e1f24a79 5039 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 5040
e1f24a79 5041 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 5042
e1f24a79 5043 u8 np_cnp_sent_high[0x20];
e281682b 5044
e1f24a79 5045 u8 np_cnp_sent_low[0x20];
e281682b 5046
b4ff3a36 5047 u8 reserved_at_320[0x560];
e281682b
SM		 5048};
5049
5050struct mlx5_ifc_query_cong_statistics_in_bits {
5051 u8 opcode[0x10];
b4ff3a36 5052 u8 reserved_at_10[0x10];
e281682b 5053
b4ff3a36 5054 u8 reserved_at_20[0x10];
e281682b
SM		 5055 u8 op_mod[0x10];
5056
5057 u8 clear[0x1];
b4ff3a36 5058 u8 reserved_at_41[0x1f];
e281682b 5059
b4ff3a36 5060 u8 reserved_at_60[0x20];
e281682b
SM		 5061};
5062
5063struct mlx5_ifc_query_cong_params_out_bits {
5064 u8 status[0x8];
b4ff3a36 5065 u8 reserved_at_8[0x18];
e281682b
SM		 5066
5067 u8 syndrome[0x20];
5068
b4ff3a36 5069 u8 reserved_at_40[0x40];
e281682b
SM		 5070
5071 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5072};
5073
5074struct mlx5_ifc_query_cong_params_in_bits {
5075 u8 opcode[0x10];
b4ff3a36 5076 u8 reserved_at_10[0x10];
e281682b 5077
b4ff3a36 5078 u8 reserved_at_20[0x10];
e281682b
SM		 5079 u8 op_mod[0x10];
5080
b4ff3a36 5081 u8 reserved_at_40[0x1c];
e281682b
SM		 5082 u8 cong_protocol[0x4];
5083
b4ff3a36 5084 u8 reserved_at_60[0x20];
e281682b
SM		 5085};
5086
5087struct mlx5_ifc_query_adapter_out_bits {
5088 u8 status[0x8];
b4ff3a36 5089 u8 reserved_at_8[0x18];
e281682b
SM		 5090
5091 u8 syndrome[0x20];
5092
b4ff3a36 5093 u8 reserved_at_40[0x40];
e281682b
SM		 5094
5095 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5096};
5097
5098struct mlx5_ifc_query_adapter_in_bits {
5099 u8 opcode[0x10];
b4ff3a36 5100 u8 reserved_at_10[0x10];
e281682b 5101
b4ff3a36 5102 u8 reserved_at_20[0x10];
e281682b
SM		 5103 u8 op_mod[0x10];
5104
b4ff3a36 5105 u8 reserved_at_40[0x40];
e281682b
SM		 5106};
5107
5108struct mlx5_ifc_qp_2rst_out_bits {
5109 u8 status[0x8];
b4ff3a36 5110 u8 reserved_at_8[0x18];
e281682b
SM		 5111
5112 u8 syndrome[0x20];
5113
b4ff3a36 5114 u8 reserved_at_40[0x40];
e281682b
SM		 5115};
5116
5117struct mlx5_ifc_qp_2rst_in_bits {
5118 u8 opcode[0x10];
b4ff3a36 5119 u8 reserved_at_10[0x10];
e281682b 5120
b4ff3a36 5121 u8 reserved_at_20[0x10];
e281682b
SM		 5122 u8 op_mod[0x10];
5123
b4ff3a36 5124 u8 reserved_at_40[0x8];
e281682b
SM		 5125 u8 qpn[0x18];
5126
b4ff3a36 5127 u8 reserved_at_60[0x20];
e281682b
SM		 5128};
5129
5130struct mlx5_ifc_qp_2err_out_bits {
5131 u8 status[0x8];
b4ff3a36 5132 u8 reserved_at_8[0x18];
e281682b
SM		 5133
5134 u8 syndrome[0x20];
5135
b4ff3a36 5136 u8 reserved_at_40[0x40];
e281682b
SM		 5137};
5138
5139struct mlx5_ifc_qp_2err_in_bits {
5140 u8 opcode[0x10];
b4ff3a36 5141 u8 reserved_at_10[0x10];
e281682b 5142
b4ff3a36 5143 u8 reserved_at_20[0x10];
e281682b
SM		 5144 u8 op_mod[0x10];
5145
b4ff3a36 5146 u8 reserved_at_40[0x8];
e281682b
SM		 5147 u8 qpn[0x18];
5148
b4ff3a36 5149 u8 reserved_at_60[0x20];
e281682b
SM		 5150};
5151
5152struct mlx5_ifc_page_fault_resume_out_bits {
5153 u8 status[0x8];
b4ff3a36 5154 u8 reserved_at_8[0x18];
e281682b
SM		 5155
5156 u8 syndrome[0x20];
5157
b4ff3a36 5158 u8 reserved_at_40[0x40];
e281682b
SM		 5159};
5160
5161struct mlx5_ifc_page_fault_resume_in_bits {
5162 u8 opcode[0x10];
b4ff3a36 5163 u8 reserved_at_10[0x10];
e281682b 5164
b4ff3a36 5165 u8 reserved_at_20[0x10];
e281682b
SM		 5166 u8 op_mod[0x10];
5167
5168 u8 error[0x1];
b4ff3a36 5169 u8 reserved_at_41[0x4];
223cdc72
AK		 5170 u8 page_fault_type[0x3];
5171 u8 wq_number[0x18];
e281682b 5172
223cdc72
AK		 5173 u8 reserved_at_60[0x8];
5174 u8 token[0x18];
e281682b
SM		 5175};
5176
5177struct mlx5_ifc_nop_out_bits {
5178 u8 status[0x8];
b4ff3a36 5179 u8 reserved_at_8[0x18];
e281682b
SM		 5180
5181 u8 syndrome[0x20];
5182
b4ff3a36 5183 u8 reserved_at_40[0x40];
e281682b
SM		 5184};
5185
5186struct mlx5_ifc_nop_in_bits {
5187 u8 opcode[0x10];
b4ff3a36 5188 u8 reserved_at_10[0x10];
e281682b 5189
b4ff3a36 5190 u8 reserved_at_20[0x10];
e281682b
SM		 5191 u8 op_mod[0x10];
5192
b4ff3a36 5193 u8 reserved_at_40[0x40];
e281682b
SM		 5194};
5195
5196struct mlx5_ifc_modify_vport_state_out_bits {
5197 u8 status[0x8];
b4ff3a36 5198 u8 reserved_at_8[0x18];
e281682b
SM		 5199
5200 u8 syndrome[0x20];
5201
b4ff3a36 5202 u8 reserved_at_40[0x40];
e281682b
SM		 5203};
5204
5205struct mlx5_ifc_modify_vport_state_in_bits {
5206 u8 opcode[0x10];
b4ff3a36 5207 u8 reserved_at_10[0x10];
e281682b 5208
b4ff3a36 5209 u8 reserved_at_20[0x10];
e281682b
SM		 5210 u8 op_mod[0x10];
5211
5212 u8 other_vport[0x1];
b4ff3a36 5213 u8 reserved_at_41[0xf];
e281682b
SM		 5214 u8 vport_number[0x10];
5215
b4ff3a36 5216 u8 reserved_at_60[0x18];
e281682b 5217 u8 admin_state[0x4];
b4ff3a36 5218 u8 reserved_at_7c[0x4];
e281682b
SM		 5219};
5220
5221struct mlx5_ifc_modify_tis_out_bits {
5222 u8 status[0x8];
b4ff3a36 5223 u8 reserved_at_8[0x18];
e281682b
SM		 5224
5225 u8 syndrome[0x20];
5226
b4ff3a36 5227 u8 reserved_at_40[0x40];
e281682b
SM		 5228};
5229
75850d0b 5230struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5231 u8 reserved_at_0[0x20];
75850d0b 5232
84df61eb
AH		 5233 u8 reserved_at_20[0x1d];
5234 u8 lag_tx_port_affinity[0x1];
5235 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5236 u8 prio[0x1];
5237};
5238
e281682b
SM		 5239struct mlx5_ifc_modify_tis_in_bits {
5240 u8 opcode[0x10];
b4ff3a36 5241 u8 reserved_at_10[0x10];
e281682b 5242
b4ff3a36 5243 u8 reserved_at_20[0x10];
e281682b
SM		 5244 u8 op_mod[0x10];
5245
b4ff3a36 5246 u8 reserved_at_40[0x8];
e281682b
SM		 5247 u8 tisn[0x18];
5248
b4ff3a36 5249 u8 reserved_at_60[0x20];
e281682b 5250
75850d0b 5251 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5252
b4ff3a36 5253 u8 reserved_at_c0[0x40];
e281682b
SM		 5254
5255 struct mlx5_ifc_tisc_bits ctx;
5256};
5257
d9eea403 5258struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5259 u8 reserved_at_0[0x20];
d9eea403 5260
b4ff3a36 5261 u8 reserved_at_20[0x1b];
66189961 5262 u8 self_lb_en[0x1];
bdfc028d
TT		 5263 u8 reserved_at_3c[0x1];
5264 u8 hash[0x1];
5265 u8 reserved_at_3e[0x1];
d9eea403
AS		 5266 u8 lro[0x1];
5267};
5268
e281682b
SM		 5269struct mlx5_ifc_modify_tir_out_bits {
5270 u8 status[0x8];
b4ff3a36 5271 u8 reserved_at_8[0x18];
e281682b
SM		 5272
5273 u8 syndrome[0x20];
5274
b4ff3a36 5275 u8 reserved_at_40[0x40];
e281682b
SM		 5276};
5277
5278struct mlx5_ifc_modify_tir_in_bits {
5279 u8 opcode[0x10];
b4ff3a36 5280 u8 reserved_at_10[0x10];
e281682b 5281
b4ff3a36 5282 u8 reserved_at_20[0x10];
e281682b
SM		 5283 u8 op_mod[0x10];
5284
b4ff3a36 5285 u8 reserved_at_40[0x8];
e281682b
SM		 5286 u8 tirn[0x18];
5287
b4ff3a36 5288 u8 reserved_at_60[0x20];
e281682b 5289
d9eea403 5290 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5291
b4ff3a36 5292 u8 reserved_at_c0[0x40];
e281682b
SM		 5293
5294 struct mlx5_ifc_tirc_bits ctx;
5295};
5296
5297struct mlx5_ifc_modify_sq_out_bits {
5298 u8 status[0x8];
b4ff3a36 5299 u8 reserved_at_8[0x18];
e281682b
SM		 5300
5301 u8 syndrome[0x20];
5302
b4ff3a36 5303 u8 reserved_at_40[0x40];
e281682b
SM		 5304};
5305
5306struct mlx5_ifc_modify_sq_in_bits {
5307 u8 opcode[0x10];
b4ff3a36 5308 u8 reserved_at_10[0x10];
e281682b 5309
b4ff3a36 5310 u8 reserved_at_20[0x10];
e281682b
SM		 5311 u8 op_mod[0x10];
5312
5313 u8 sq_state[0x4];
b4ff3a36 5314 u8 reserved_at_44[0x4];
e281682b
SM		 5315 u8 sqn[0x18];
5316
b4ff3a36 5317 u8 reserved_at_60[0x20];
e281682b
SM		 5318
5319 u8 modify_bitmask[0x40];
5320
b4ff3a36 5321 u8 reserved_at_c0[0x40];
e281682b
SM		 5322
5323 struct mlx5_ifc_sqc_bits ctx;
5324};
5325
813f8540
MHY		 5326struct mlx5_ifc_modify_scheduling_element_out_bits {
5327 u8 status[0x8];
5328 u8 reserved_at_8[0x18];
5329
5330 u8 syndrome[0x20];
5331
5332 u8 reserved_at_40[0x1c0];
5333};
5334
5335enum {
5336 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5337 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5338};
5339
5340struct mlx5_ifc_modify_scheduling_element_in_bits {
5341 u8 opcode[0x10];
5342 u8 reserved_at_10[0x10];
5343
5344 u8 reserved_at_20[0x10];
5345 u8 op_mod[0x10];
5346
5347 u8 scheduling_hierarchy[0x8];
5348 u8 reserved_at_48[0x18];
5349
5350 u8 scheduling_element_id[0x20];
5351
5352 u8 reserved_at_80[0x20];
5353
5354 u8 modify_bitmask[0x20];
5355
5356 u8 reserved_at_c0[0x40];
5357
5358 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5359
5360 u8 reserved_at_300[0x100];
5361};
5362
e281682b
SM		 5363struct mlx5_ifc_modify_rqt_out_bits {
5364 u8 status[0x8];
b4ff3a36 5365 u8 reserved_at_8[0x18];
e281682b
SM		 5366
5367 u8 syndrome[0x20];
5368
b4ff3a36 5369 u8 reserved_at_40[0x40];
e281682b
SM		 5370};
5371
5c50368f 5372struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5373 u8 reserved_at_0[0x20];
5c50368f 5374
b4ff3a36 5375 u8 reserved_at_20[0x1f];
5c50368f
AS		 5376 u8 rqn_list[0x1];
5377};
5378
e281682b
SM		 5379struct mlx5_ifc_modify_rqt_in_bits {
5380 u8 opcode[0x10];
b4ff3a36 5381 u8 reserved_at_10[0x10];
e281682b 5382
b4ff3a36 5383 u8 reserved_at_20[0x10];
e281682b
SM		 5384 u8 op_mod[0x10];
5385
b4ff3a36 5386 u8 reserved_at_40[0x8];
e281682b
SM		 5387 u8 rqtn[0x18];
5388
b4ff3a36 5389 u8 reserved_at_60[0x20];
e281682b 5390
5c50368f 5391 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5392
b4ff3a36 5393 u8 reserved_at_c0[0x40];
e281682b
SM		 5394
5395 struct mlx5_ifc_rqtc_bits ctx;
5396};
5397
5398struct mlx5_ifc_modify_rq_out_bits {
5399 u8 status[0x8];
b4ff3a36 5400 u8 reserved_at_8[0x18];
e281682b
SM		 5401
5402 u8 syndrome[0x20];
5403
b4ff3a36 5404 u8 reserved_at_40[0x40];
e281682b
SM		 5405};
5406
83b502a1
AV		 5407enum {
5408 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5409 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5410 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5411};
5412
e281682b
SM		 5413struct mlx5_ifc_modify_rq_in_bits {
5414 u8 opcode[0x10];
b4ff3a36 5415 u8 reserved_at_10[0x10];
e281682b 5416
b4ff3a36 5417 u8 reserved_at_20[0x10];
e281682b
SM		 5418 u8 op_mod[0x10];
5419
5420 u8 rq_state[0x4];
b4ff3a36 5421 u8 reserved_at_44[0x4];
e281682b
SM		 5422 u8 rqn[0x18];
5423
b4ff3a36 5424 u8 reserved_at_60[0x20];
e281682b
SM		 5425
5426 u8 modify_bitmask[0x40];
5427
b4ff3a36 5428 u8 reserved_at_c0[0x40];
e281682b
SM		 5429
5430 struct mlx5_ifc_rqc_bits ctx;
5431};
5432
5433struct mlx5_ifc_modify_rmp_out_bits {
5434 u8 status[0x8];
b4ff3a36 5435 u8 reserved_at_8[0x18];
e281682b
SM		 5436
5437 u8 syndrome[0x20];
5438
b4ff3a36 5439 u8 reserved_at_40[0x40];
e281682b
SM		 5440};
5441
01949d01 5442struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5443 u8 reserved_at_0[0x20];
01949d01 5444
b4ff3a36 5445 u8 reserved_at_20[0x1f];
01949d01
HA		 5446 u8 lwm[0x1];
5447};
5448
e281682b
SM		 5449struct mlx5_ifc_modify_rmp_in_bits {
5450 u8 opcode[0x10];
b4ff3a36 5451 u8 reserved_at_10[0x10];
e281682b 5452
b4ff3a36 5453 u8 reserved_at_20[0x10];
e281682b
SM		 5454 u8 op_mod[0x10];
5455
5456 u8 rmp_state[0x4];
b4ff3a36 5457 u8 reserved_at_44[0x4];
e281682b
SM		 5458 u8 rmpn[0x18];
5459
b4ff3a36 5460 u8 reserved_at_60[0x20];
e281682b 5461
01949d01 5462 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5463
b4ff3a36 5464 u8 reserved_at_c0[0x40];
e281682b
SM		 5465
5466 struct mlx5_ifc_rmpc_bits ctx;
5467};
5468
5469struct mlx5_ifc_modify_nic_vport_context_out_bits {
5470 u8 status[0x8];
b4ff3a36 5471 u8 reserved_at_8[0x18];
e281682b
SM		 5472
5473 u8 syndrome[0x20];
5474
b4ff3a36 5475 u8 reserved_at_40[0x40];
e281682b
SM		 5476};
5477
5478struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 5479 u8 reserved_at_0[0x12];
5480 u8 affiliation[0x1];
5481 u8 reserved_at_e[0x1];
bded747b
HN		 5482 u8 disable_uc_local_lb[0x1];
5483 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5484 u8 node_guid[0x1];
5485 u8 port_guid[0x1];
9def7121 5486 u8 min_inline[0x1];
d82b7318
SM		 5487 u8 mtu[0x1];
5488 u8 change_event[0x1];
5489 u8 promisc[0x1];
e281682b
SM		 5490 u8 permanent_address[0x1];
5491 u8 addresses_list[0x1];
5492 u8 roce_en[0x1];
b4ff3a36 5493 u8 reserved_at_1f[0x1];
e281682b
SM		 5494};
5495
5496struct mlx5_ifc_modify_nic_vport_context_in_bits {
5497 u8 opcode[0x10];
b4ff3a36 5498 u8 reserved_at_10[0x10];
e281682b 5499
b4ff3a36 5500 u8 reserved_at_20[0x10];
e281682b
SM		 5501 u8 op_mod[0x10];
5502
5503 u8 other_vport[0x1];
b4ff3a36 5504 u8 reserved_at_41[0xf];
e281682b
SM		 5505 u8 vport_number[0x10];
5506
5507 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5508
b4ff3a36 5509 u8 reserved_at_80[0x780];
e281682b
SM		 5510
5511 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5512};
5513
5514struct mlx5_ifc_modify_hca_vport_context_out_bits {
5515 u8 status[0x8];
b4ff3a36 5516 u8 reserved_at_8[0x18];
e281682b
SM		 5517
5518 u8 syndrome[0x20];
5519
b4ff3a36 5520 u8 reserved_at_40[0x40];
e281682b
SM		 5521};
5522
5523struct mlx5_ifc_modify_hca_vport_context_in_bits {
5524 u8 opcode[0x10];
b4ff3a36 5525 u8 reserved_at_10[0x10];
e281682b 5526
b4ff3a36 5527 u8 reserved_at_20[0x10];
e281682b
SM		 5528 u8 op_mod[0x10];
5529
5530 u8 other_vport[0x1];
b4ff3a36 5531 u8 reserved_at_41[0xb];
707c4602 5532 u8 port_num[0x4];
e281682b
SM		 5533 u8 vport_number[0x10];
5534
b4ff3a36 5535 u8 reserved_at_60[0x20];
e281682b
SM		 5536
5537 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5538};
5539
5540struct mlx5_ifc_modify_cq_out_bits {
5541 u8 status[0x8];
b4ff3a36 5542 u8 reserved_at_8[0x18];
e281682b
SM		 5543
5544 u8 syndrome[0x20];
5545
b4ff3a36 5546 u8 reserved_at_40[0x40];
e281682b
SM		 5547};
5548
5549enum {
5550 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5551 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5552};
5553
5554struct mlx5_ifc_modify_cq_in_bits {
5555 u8 opcode[0x10];
b4ff3a36 5556 u8 reserved_at_10[0x10];
e281682b 5557
b4ff3a36 5558 u8 reserved_at_20[0x10];
e281682b
SM		 5559 u8 op_mod[0x10];
5560
b4ff3a36 5561 u8 reserved_at_40[0x8];
e281682b
SM		 5562 u8 cqn[0x18];
5563
5564 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5565
5566 struct mlx5_ifc_cqc_bits cq_context;
5567
b4ff3a36 5568 u8 reserved_at_280[0x600];
e281682b
SM		 5569
5570 u8 pas[0][0x40];
5571};
5572
5573struct mlx5_ifc_modify_cong_status_out_bits {
5574 u8 status[0x8];
b4ff3a36 5575 u8 reserved_at_8[0x18];
e281682b
SM		 5576
5577 u8 syndrome[0x20];
5578
b4ff3a36 5579 u8 reserved_at_40[0x40];
e281682b
SM		 5580};
5581
5582struct mlx5_ifc_modify_cong_status_in_bits {
5583 u8 opcode[0x10];
b4ff3a36 5584 u8 reserved_at_10[0x10];
e281682b 5585
b4ff3a36 5586 u8 reserved_at_20[0x10];
e281682b
SM		 5587 u8 op_mod[0x10];
5588
b4ff3a36 5589 u8 reserved_at_40[0x18];
e281682b
SM		 5590 u8 priority[0x4];
5591 u8 cong_protocol[0x4];
5592
5593 u8 enable[0x1];
5594 u8 tag_enable[0x1];
b4ff3a36 5595 u8 reserved_at_62[0x1e];
e281682b
SM		 5596};
5597
5598struct mlx5_ifc_modify_cong_params_out_bits {
5599 u8 status[0x8];
b4ff3a36 5600 u8 reserved_at_8[0x18];
e281682b
SM		 5601
5602 u8 syndrome[0x20];
5603
b4ff3a36 5604 u8 reserved_at_40[0x40];
e281682b
SM		 5605};
5606
5607struct mlx5_ifc_modify_cong_params_in_bits {
5608 u8 opcode[0x10];
b4ff3a36 5609 u8 reserved_at_10[0x10];
e281682b 5610
b4ff3a36 5611 u8 reserved_at_20[0x10];
e281682b
SM		 5612 u8 op_mod[0x10];
5613
b4ff3a36 5614 u8 reserved_at_40[0x1c];
e281682b
SM		 5615 u8 cong_protocol[0x4];
5616
5617 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5618
b4ff3a36 5619 u8 reserved_at_80[0x80];
e281682b
SM		 5620
5621 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5622};
5623
5624struct mlx5_ifc_manage_pages_out_bits {
5625 u8 status[0x8];
b4ff3a36 5626 u8 reserved_at_8[0x18];
e281682b
SM		 5627
5628 u8 syndrome[0x20];
5629
5630 u8 output_num_entries[0x20];
5631
b4ff3a36 5632 u8 reserved_at_60[0x20];
e281682b
SM		 5633
5634 u8 pas[0][0x40];
5635};
5636
5637enum {
5638 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5639 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5640 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5641};
5642
5643struct mlx5_ifc_manage_pages_in_bits {
5644 u8 opcode[0x10];
b4ff3a36 5645 u8 reserved_at_10[0x10];
e281682b 5646
b4ff3a36 5647 u8 reserved_at_20[0x10];
e281682b
SM		 5648 u8 op_mod[0x10];
5649
b4ff3a36 5650 u8 reserved_at_40[0x10];
e281682b
SM		 5651 u8 function_id[0x10];
5652
5653 u8 input_num_entries[0x20];
5654
5655 u8 pas[0][0x40];
5656};
5657
5658struct mlx5_ifc_mad_ifc_out_bits {
5659 u8 status[0x8];
b4ff3a36 5660 u8 reserved_at_8[0x18];
e281682b
SM		 5661
5662 u8 syndrome[0x20];
5663
b4ff3a36 5664 u8 reserved_at_40[0x40];
e281682b
SM		 5665
5666 u8 response_mad_packet[256][0x8];
5667};
5668
5669struct mlx5_ifc_mad_ifc_in_bits {
5670 u8 opcode[0x10];
b4ff3a36 5671 u8 reserved_at_10[0x10];
e281682b 5672
b4ff3a36 5673 u8 reserved_at_20[0x10];
e281682b
SM		 5674 u8 op_mod[0x10];
5675
5676 u8 remote_lid[0x10];
b4ff3a36 5677 u8 reserved_at_50[0x8];
e281682b
SM		 5678 u8 port[0x8];
5679
b4ff3a36 5680 u8 reserved_at_60[0x20];
e281682b
SM		 5681
5682 u8 mad[256][0x8];
5683};
5684
5685struct mlx5_ifc_init_hca_out_bits {
5686 u8 status[0x8];
b4ff3a36 5687 u8 reserved_at_8[0x18];
e281682b
SM		 5688
5689 u8 syndrome[0x20];
5690
b4ff3a36 5691 u8 reserved_at_40[0x40];
e281682b
SM		 5692};
5693
5694struct mlx5_ifc_init_hca_in_bits {
5695 u8 opcode[0x10];
b4ff3a36 5696 u8 reserved_at_10[0x10];
e281682b 5697
b4ff3a36 5698 u8 reserved_at_20[0x10];
e281682b
SM		 5699 u8 op_mod[0x10];
5700
b4ff3a36 5701 u8 reserved_at_40[0x40];
8737f818 5702 u8 sw_owner_id[4][0x20];
e281682b
SM		 5703};
5704
5705struct mlx5_ifc_init2rtr_qp_out_bits {
5706 u8 status[0x8];
b4ff3a36 5707 u8 reserved_at_8[0x18];
e281682b
SM		 5708
5709 u8 syndrome[0x20];
5710
b4ff3a36 5711 u8 reserved_at_40[0x40];
e281682b
SM		 5712};
5713
5714struct mlx5_ifc_init2rtr_qp_in_bits {
5715 u8 opcode[0x10];
b4ff3a36 5716 u8 reserved_at_10[0x10];
e281682b 5717
b4ff3a36 5718 u8 reserved_at_20[0x10];
e281682b
SM		 5719 u8 op_mod[0x10];
5720
b4ff3a36 5721 u8 reserved_at_40[0x8];
e281682b
SM		 5722 u8 qpn[0x18];
5723
b4ff3a36 5724 u8 reserved_at_60[0x20];
e281682b
SM		 5725
5726 u8 opt_param_mask[0x20];
5727
b4ff3a36 5728 u8 reserved_at_a0[0x20];
e281682b
SM		 5729
5730 struct mlx5_ifc_qpc_bits qpc;
5731
b4ff3a36 5732 u8 reserved_at_800[0x80];
e281682b
SM		 5733};
5734
5735struct mlx5_ifc_init2init_qp_out_bits {
5736 u8 status[0x8];
b4ff3a36 5737 u8 reserved_at_8[0x18];
e281682b
SM		 5738
5739 u8 syndrome[0x20];
5740
b4ff3a36 5741 u8 reserved_at_40[0x40];
e281682b
SM		 5742};
5743
5744struct mlx5_ifc_init2init_qp_in_bits {
5745 u8 opcode[0x10];
b4ff3a36 5746 u8 reserved_at_10[0x10];
e281682b 5747
b4ff3a36 5748 u8 reserved_at_20[0x10];
e281682b
SM		 5749 u8 op_mod[0x10];
5750
b4ff3a36 5751 u8 reserved_at_40[0x8];
e281682b
SM		 5752 u8 qpn[0x18];
5753
b4ff3a36 5754 u8 reserved_at_60[0x20];
e281682b
SM		 5755
5756 u8 opt_param_mask[0x20];
5757
b4ff3a36 5758 u8 reserved_at_a0[0x20];
e281682b
SM		 5759
5760 struct mlx5_ifc_qpc_bits qpc;
5761
b4ff3a36 5762 u8 reserved_at_800[0x80];
e281682b
SM		 5763};
5764
5765struct mlx5_ifc_get_dropped_packet_log_out_bits {
5766 u8 status[0x8];
b4ff3a36 5767 u8 reserved_at_8[0x18];
e281682b
SM		 5768
5769 u8 syndrome[0x20];
5770
b4ff3a36 5771 u8 reserved_at_40[0x40];
e281682b
SM		 5772
5773 u8 packet_headers_log[128][0x8];
5774
5775 u8 packet_syndrome[64][0x8];
5776};
5777
5778struct mlx5_ifc_get_dropped_packet_log_in_bits {
5779 u8 opcode[0x10];
b4ff3a36 5780 u8 reserved_at_10[0x10];
e281682b 5781
b4ff3a36 5782 u8 reserved_at_20[0x10];
e281682b
SM		 5783 u8 op_mod[0x10];
5784
b4ff3a36 5785 u8 reserved_at_40[0x40];
e281682b
SM		 5786};
5787
5788struct mlx5_ifc_gen_eqe_in_bits {
5789 u8 opcode[0x10];
b4ff3a36 5790 u8 reserved_at_10[0x10];
e281682b 5791
b4ff3a36 5792 u8 reserved_at_20[0x10];
e281682b
SM		 5793 u8 op_mod[0x10];
5794
b4ff3a36 5795 u8 reserved_at_40[0x18];
e281682b
SM		 5796 u8 eq_number[0x8];
5797
b4ff3a36 5798 u8 reserved_at_60[0x20];
e281682b
SM		 5799
5800 u8 eqe[64][0x8];
5801};
5802
5803struct mlx5_ifc_gen_eq_out_bits {
5804 u8 status[0x8];
b4ff3a36 5805 u8 reserved_at_8[0x18];
e281682b
SM		 5806
5807 u8 syndrome[0x20];
5808
b4ff3a36 5809 u8 reserved_at_40[0x40];
e281682b
SM		 5810};
5811
5812struct mlx5_ifc_enable_hca_out_bits {
5813 u8 status[0x8];
b4ff3a36 5814 u8 reserved_at_8[0x18];
e281682b
SM		 5815
5816 u8 syndrome[0x20];
5817
b4ff3a36 5818 u8 reserved_at_40[0x20];
e281682b
SM		 5819};
5820
5821struct mlx5_ifc_enable_hca_in_bits {
5822 u8 opcode[0x10];
b4ff3a36 5823 u8 reserved_at_10[0x10];
e281682b 5824
b4ff3a36 5825 u8 reserved_at_20[0x10];
e281682b
SM		 5826 u8 op_mod[0x10];
5827
b4ff3a36 5828 u8 reserved_at_40[0x10];
e281682b
SM		 5829 u8 function_id[0x10];
5830
b4ff3a36 5831 u8 reserved_at_60[0x20];
e281682b
SM		 5832};
5833
5834struct mlx5_ifc_drain_dct_out_bits {
5835 u8 status[0x8];
b4ff3a36 5836 u8 reserved_at_8[0x18];
e281682b
SM		 5837
5838 u8 syndrome[0x20];
5839
b4ff3a36 5840 u8 reserved_at_40[0x40];
e281682b
SM		 5841};
5842
5843struct mlx5_ifc_drain_dct_in_bits {
5844 u8 opcode[0x10];
b4ff3a36 5845 u8 reserved_at_10[0x10];
e281682b 5846
b4ff3a36 5847 u8 reserved_at_20[0x10];
e281682b
SM		 5848 u8 op_mod[0x10];
5849
b4ff3a36 5850 u8 reserved_at_40[0x8];
e281682b
SM		 5851 u8 dctn[0x18];
5852
b4ff3a36 5853 u8 reserved_at_60[0x20];
e281682b
SM		 5854};
5855
5856struct mlx5_ifc_disable_hca_out_bits {
5857 u8 status[0x8];
b4ff3a36 5858 u8 reserved_at_8[0x18];
e281682b
SM		 5859
5860 u8 syndrome[0x20];
5861
b4ff3a36 5862 u8 reserved_at_40[0x20];
e281682b
SM		 5863};
5864
5865struct mlx5_ifc_disable_hca_in_bits {
5866 u8 opcode[0x10];
b4ff3a36 5867 u8 reserved_at_10[0x10];
e281682b 5868
b4ff3a36 5869 u8 reserved_at_20[0x10];
e281682b
SM		 5870 u8 op_mod[0x10];
5871
b4ff3a36 5872 u8 reserved_at_40[0x10];
e281682b
SM		 5873 u8 function_id[0x10];
5874
b4ff3a36 5875 u8 reserved_at_60[0x20];
e281682b
SM		 5876};
5877
5878struct mlx5_ifc_detach_from_mcg_out_bits {
5879 u8 status[0x8];
b4ff3a36 5880 u8 reserved_at_8[0x18];
e281682b
SM		 5881
5882 u8 syndrome[0x20];
5883
b4ff3a36 5884 u8 reserved_at_40[0x40];
e281682b
SM		 5885};
5886
5887struct mlx5_ifc_detach_from_mcg_in_bits {
5888 u8 opcode[0x10];
b4ff3a36 5889 u8 reserved_at_10[0x10];
e281682b 5890
b4ff3a36 5891 u8 reserved_at_20[0x10];
e281682b
SM		 5892 u8 op_mod[0x10];
5893
b4ff3a36 5894 u8 reserved_at_40[0x8];
e281682b
SM		 5895 u8 qpn[0x18];
5896
b4ff3a36 5897 u8 reserved_at_60[0x20];
e281682b
SM		 5898
5899 u8 multicast_gid[16][0x8];
5900};
5901
7486216b
SM		 5902struct mlx5_ifc_destroy_xrq_out_bits {
5903 u8 status[0x8];
5904 u8 reserved_at_8[0x18];
5905
5906 u8 syndrome[0x20];
5907
5908 u8 reserved_at_40[0x40];
5909};
5910
5911struct mlx5_ifc_destroy_xrq_in_bits {
5912 u8 opcode[0x10];
5913 u8 reserved_at_10[0x10];
5914
5915 u8 reserved_at_20[0x10];
5916 u8 op_mod[0x10];
5917
5918 u8 reserved_at_40[0x8];
5919 u8 xrqn[0x18];
5920
5921 u8 reserved_at_60[0x20];
5922};
5923
e281682b
SM		 5924struct mlx5_ifc_destroy_xrc_srq_out_bits {
5925 u8 status[0x8];
b4ff3a36 5926 u8 reserved_at_8[0x18];
e281682b
SM		 5927
5928 u8 syndrome[0x20];
5929
b4ff3a36 5930 u8 reserved_at_40[0x40];
e281682b
SM		 5931};
5932
5933struct mlx5_ifc_destroy_xrc_srq_in_bits {
5934 u8 opcode[0x10];
b4ff3a36 5935 u8 reserved_at_10[0x10];
e281682b 5936
b4ff3a36 5937 u8 reserved_at_20[0x10];
e281682b
SM		 5938 u8 op_mod[0x10];
5939
b4ff3a36 5940 u8 reserved_at_40[0x8];
e281682b
SM		 5941 u8 xrc_srqn[0x18];
5942
b4ff3a36 5943 u8 reserved_at_60[0x20];
e281682b
SM		 5944};
5945
5946struct mlx5_ifc_destroy_tis_out_bits {
5947 u8 status[0x8];
b4ff3a36 5948 u8 reserved_at_8[0x18];
e281682b
SM		 5949
5950 u8 syndrome[0x20];
5951
b4ff3a36 5952 u8 reserved_at_40[0x40];
e281682b
SM		 5953};
5954
5955struct mlx5_ifc_destroy_tis_in_bits {
5956 u8 opcode[0x10];
b4ff3a36 5957 u8 reserved_at_10[0x10];
e281682b 5958
b4ff3a36 5959 u8 reserved_at_20[0x10];
e281682b
SM		 5960 u8 op_mod[0x10];
5961
b4ff3a36 5962 u8 reserved_at_40[0x8];
e281682b
SM		 5963 u8 tisn[0x18];
5964
b4ff3a36 5965 u8 reserved_at_60[0x20];
e281682b
SM		 5966};
5967
5968struct mlx5_ifc_destroy_tir_out_bits {
5969 u8 status[0x8];
b4ff3a36 5970 u8 reserved_at_8[0x18];
e281682b
SM		 5971
5972 u8 syndrome[0x20];
5973
b4ff3a36 5974 u8 reserved_at_40[0x40];
e281682b
SM		 5975};
5976
5977struct mlx5_ifc_destroy_tir_in_bits {
5978 u8 opcode[0x10];
b4ff3a36 5979 u8 reserved_at_10[0x10];
e281682b 5980
b4ff3a36 5981 u8 reserved_at_20[0x10];
e281682b
SM		 5982 u8 op_mod[0x10];
5983
b4ff3a36 5984 u8 reserved_at_40[0x8];
e281682b
SM		 5985 u8 tirn[0x18];
5986
b4ff3a36 5987 u8 reserved_at_60[0x20];
e281682b
SM		 5988};
5989
5990struct mlx5_ifc_destroy_srq_out_bits {
5991 u8 status[0x8];
b4ff3a36 5992 u8 reserved_at_8[0x18];
e281682b
SM		 5993
5994 u8 syndrome[0x20];
5995
b4ff3a36 5996 u8 reserved_at_40[0x40];
e281682b
SM		 5997};
5998
5999struct mlx5_ifc_destroy_srq_in_bits {
6000 u8 opcode[0x10];
b4ff3a36 6001 u8 reserved_at_10[0x10];
e281682b 6002
b4ff3a36 6003 u8 reserved_at_20[0x10];
e281682b
SM		 6004 u8 op_mod[0x10];
6005
b4ff3a36 6006 u8 reserved_at_40[0x8];
e281682b
SM		 6007 u8 srqn[0x18];
6008
b4ff3a36 6009 u8 reserved_at_60[0x20];
e281682b
SM		 6010};
6011
6012struct mlx5_ifc_destroy_sq_out_bits {
6013 u8 status[0x8];
b4ff3a36 6014 u8 reserved_at_8[0x18];
e281682b
SM		 6015
6016 u8 syndrome[0x20];
6017
b4ff3a36 6018 u8 reserved_at_40[0x40];
e281682b
SM		 6019};
6020
6021struct mlx5_ifc_destroy_sq_in_bits {
6022 u8 opcode[0x10];
b4ff3a36 6023 u8 reserved_at_10[0x10];
e281682b 6024
b4ff3a36 6025 u8 reserved_at_20[0x10];
e281682b
SM		 6026 u8 op_mod[0x10];
6027
b4ff3a36 6028 u8 reserved_at_40[0x8];
e281682b
SM		 6029 u8 sqn[0x18];
6030
b4ff3a36 6031 u8 reserved_at_60[0x20];
e281682b
SM		 6032};
6033
813f8540
MHY		 6034struct mlx5_ifc_destroy_scheduling_element_out_bits {
6035 u8 status[0x8];
6036 u8 reserved_at_8[0x18];
6037
6038 u8 syndrome[0x20];
6039
6040 u8 reserved_at_40[0x1c0];
6041};
6042
6043struct mlx5_ifc_destroy_scheduling_element_in_bits {
6044 u8 opcode[0x10];
6045 u8 reserved_at_10[0x10];
6046
6047 u8 reserved_at_20[0x10];
6048 u8 op_mod[0x10];
6049
6050 u8 scheduling_hierarchy[0x8];
6051 u8 reserved_at_48[0x18];
6052
6053 u8 scheduling_element_id[0x20];
6054
6055 u8 reserved_at_80[0x180];
6056};
6057
e281682b
SM		 6058struct mlx5_ifc_destroy_rqt_out_bits {
6059 u8 status[0x8];
b4ff3a36 6060 u8 reserved_at_8[0x18];
e281682b
SM		 6061
6062 u8 syndrome[0x20];
6063
b4ff3a36 6064 u8 reserved_at_40[0x40];
e281682b
SM		 6065};
6066
6067struct mlx5_ifc_destroy_rqt_in_bits {
6068 u8 opcode[0x10];
b4ff3a36 6069 u8 reserved_at_10[0x10];
e281682b 6070
b4ff3a36 6071 u8 reserved_at_20[0x10];
e281682b
SM		 6072 u8 op_mod[0x10];
6073
b4ff3a36 6074 u8 reserved_at_40[0x8];
e281682b
SM		 6075 u8 rqtn[0x18];
6076
b4ff3a36 6077 u8 reserved_at_60[0x20];
e281682b
SM		 6078};
6079
6080struct mlx5_ifc_destroy_rq_out_bits {
6081 u8 status[0x8];
b4ff3a36 6082 u8 reserved_at_8[0x18];
e281682b
SM		 6083
6084 u8 syndrome[0x20];
6085
b4ff3a36 6086 u8 reserved_at_40[0x40];
e281682b
SM		 6087};
6088
6089struct mlx5_ifc_destroy_rq_in_bits {
6090 u8 opcode[0x10];
b4ff3a36 6091 u8 reserved_at_10[0x10];
e281682b 6092
b4ff3a36 6093 u8 reserved_at_20[0x10];
e281682b
SM		 6094 u8 op_mod[0x10];
6095
b4ff3a36 6096 u8 reserved_at_40[0x8];
e281682b
SM		 6097 u8 rqn[0x18];
6098
b4ff3a36 6099 u8 reserved_at_60[0x20];
e281682b
SM		 6100};
6101
c1e0bfc1
MG		 6102struct mlx5_ifc_set_delay_drop_params_in_bits {
6103 u8 opcode[0x10];
6104 u8 reserved_at_10[0x10];
6105
6106 u8 reserved_at_20[0x10];
6107 u8 op_mod[0x10];
6108
6109 u8 reserved_at_40[0x20];
6110
6111 u8 reserved_at_60[0x10];
6112 u8 delay_drop_timeout[0x10];
6113};
6114
6115struct mlx5_ifc_set_delay_drop_params_out_bits {
6116 u8 status[0x8];
6117 u8 reserved_at_8[0x18];
6118
6119 u8 syndrome[0x20];
6120
6121 u8 reserved_at_40[0x40];
6122};
6123
e281682b
SM		 6124struct mlx5_ifc_destroy_rmp_out_bits {
6125 u8 status[0x8];
b4ff3a36 6126 u8 reserved_at_8[0x18];
e281682b
SM		 6127
6128 u8 syndrome[0x20];
6129
b4ff3a36 6130 u8 reserved_at_40[0x40];
e281682b
SM		 6131};
6132
6133struct mlx5_ifc_destroy_rmp_in_bits {
6134 u8 opcode[0x10];
b4ff3a36 6135 u8 reserved_at_10[0x10];
e281682b 6136
b4ff3a36 6137 u8 reserved_at_20[0x10];
e281682b
SM		 6138 u8 op_mod[0x10];
6139
b4ff3a36 6140 u8 reserved_at_40[0x8];
e281682b
SM		 6141 u8 rmpn[0x18];
6142
b4ff3a36 6143 u8 reserved_at_60[0x20];
e281682b
SM		 6144};
6145
6146struct mlx5_ifc_destroy_qp_out_bits {
6147 u8 status[0x8];
b4ff3a36 6148 u8 reserved_at_8[0x18];
e281682b
SM		 6149
6150 u8 syndrome[0x20];
6151
b4ff3a36 6152 u8 reserved_at_40[0x40];
e281682b
SM		 6153};
6154
6155struct mlx5_ifc_destroy_qp_in_bits {
6156 u8 opcode[0x10];
b4ff3a36 6157 u8 reserved_at_10[0x10];
e281682b 6158
b4ff3a36 6159 u8 reserved_at_20[0x10];
e281682b
SM		 6160 u8 op_mod[0x10];
6161
b4ff3a36 6162 u8 reserved_at_40[0x8];
e281682b
SM		 6163 u8 qpn[0x18];
6164
b4ff3a36 6165 u8 reserved_at_60[0x20];
e281682b
SM		 6166};
6167
6168struct mlx5_ifc_destroy_psv_out_bits {
6169 u8 status[0x8];
b4ff3a36 6170 u8 reserved_at_8[0x18];
e281682b
SM		 6171
6172 u8 syndrome[0x20];
6173
b4ff3a36 6174 u8 reserved_at_40[0x40];
e281682b
SM		 6175};
6176
6177struct mlx5_ifc_destroy_psv_in_bits {
6178 u8 opcode[0x10];
b4ff3a36 6179 u8 reserved_at_10[0x10];
e281682b 6180
b4ff3a36 6181 u8 reserved_at_20[0x10];
e281682b
SM		 6182 u8 op_mod[0x10];
6183
b4ff3a36 6184 u8 reserved_at_40[0x8];
e281682b
SM		 6185 u8 psvn[0x18];
6186
b4ff3a36 6187 u8 reserved_at_60[0x20];
e281682b
SM		 6188};
6189
6190struct mlx5_ifc_destroy_mkey_out_bits {
6191 u8 status[0x8];
b4ff3a36 6192 u8 reserved_at_8[0x18];
e281682b
SM		 6193
6194 u8 syndrome[0x20];
6195
b4ff3a36 6196 u8 reserved_at_40[0x40];
e281682b
SM		 6197};
6198
6199struct mlx5_ifc_destroy_mkey_in_bits {
6200 u8 opcode[0x10];
b4ff3a36 6201 u8 reserved_at_10[0x10];
e281682b 6202
b4ff3a36 6203 u8 reserved_at_20[0x10];
e281682b
SM		 6204 u8 op_mod[0x10];
6205
b4ff3a36 6206 u8 reserved_at_40[0x8];
e281682b
SM		 6207 u8 mkey_index[0x18];
6208
b4ff3a36 6209 u8 reserved_at_60[0x20];
e281682b
SM		 6210};
6211
6212struct mlx5_ifc_destroy_flow_table_out_bits {
6213 u8 status[0x8];
b4ff3a36 6214 u8 reserved_at_8[0x18];
e281682b
SM		 6215
6216 u8 syndrome[0x20];
6217
b4ff3a36 6218 u8 reserved_at_40[0x40];
e281682b
SM		 6219};
6220
6221struct mlx5_ifc_destroy_flow_table_in_bits {
6222 u8 opcode[0x10];
b4ff3a36 6223 u8 reserved_at_10[0x10];
e281682b 6224
b4ff3a36 6225 u8 reserved_at_20[0x10];
e281682b
SM		 6226 u8 op_mod[0x10];
6227
7d5e1423
SM		 6228 u8 other_vport[0x1];
6229 u8 reserved_at_41[0xf];
6230 u8 vport_number[0x10];
6231
6232 u8 reserved_at_60[0x20];
e281682b
SM		 6233
6234 u8 table_type[0x8];
b4ff3a36 6235 u8 reserved_at_88[0x18];
e281682b 6236
b4ff3a36 6237 u8 reserved_at_a0[0x8];
e281682b
SM		 6238 u8 table_id[0x18];
6239
b4ff3a36 6240 u8 reserved_at_c0[0x140];
e281682b
SM		 6241};
6242
6243struct mlx5_ifc_destroy_flow_group_out_bits {
6244 u8 status[0x8];
b4ff3a36 6245 u8 reserved_at_8[0x18];
e281682b
SM		 6246
6247 u8 syndrome[0x20];
6248
b4ff3a36 6249 u8 reserved_at_40[0x40];
e281682b
SM		 6250};
6251
6252struct mlx5_ifc_destroy_flow_group_in_bits {
6253 u8 opcode[0x10];
b4ff3a36 6254 u8 reserved_at_10[0x10];
e281682b 6255
b4ff3a36 6256 u8 reserved_at_20[0x10];
e281682b
SM		 6257 u8 op_mod[0x10];
6258
7d5e1423
SM		 6259 u8 other_vport[0x1];
6260 u8 reserved_at_41[0xf];
6261 u8 vport_number[0x10];
6262
6263 u8 reserved_at_60[0x20];
e281682b
SM		 6264
6265 u8 table_type[0x8];
b4ff3a36 6266 u8 reserved_at_88[0x18];
e281682b 6267
b4ff3a36 6268 u8 reserved_at_a0[0x8];
e281682b
SM		 6269 u8 table_id[0x18];
6270
6271 u8 group_id[0x20];
6272
b4ff3a36 6273 u8 reserved_at_e0[0x120];
e281682b
SM		 6274};
6275
6276struct mlx5_ifc_destroy_eq_out_bits {
6277 u8 status[0x8];
b4ff3a36 6278 u8 reserved_at_8[0x18];
e281682b
SM		 6279
6280 u8 syndrome[0x20];
6281
b4ff3a36 6282 u8 reserved_at_40[0x40];
e281682b
SM		 6283};
6284
6285struct mlx5_ifc_destroy_eq_in_bits {
6286 u8 opcode[0x10];
b4ff3a36 6287 u8 reserved_at_10[0x10];
e281682b 6288
b4ff3a36 6289 u8 reserved_at_20[0x10];
e281682b
SM		 6290 u8 op_mod[0x10];
6291
b4ff3a36 6292 u8 reserved_at_40[0x18];
e281682b
SM		 6293 u8 eq_number[0x8];
6294
b4ff3a36 6295 u8 reserved_at_60[0x20];
e281682b
SM		 6296};
6297
6298struct mlx5_ifc_destroy_dct_out_bits {
6299 u8 status[0x8];
b4ff3a36 6300 u8 reserved_at_8[0x18];
e281682b
SM		 6301
6302 u8 syndrome[0x20];
6303
b4ff3a36 6304 u8 reserved_at_40[0x40];
e281682b
SM		 6305};
6306
6307struct mlx5_ifc_destroy_dct_in_bits {
6308 u8 opcode[0x10];
b4ff3a36 6309 u8 reserved_at_10[0x10];
e281682b 6310
b4ff3a36 6311 u8 reserved_at_20[0x10];
e281682b
SM		 6312 u8 op_mod[0x10];
6313
b4ff3a36 6314 u8 reserved_at_40[0x8];
e281682b
SM		 6315 u8 dctn[0x18];
6316
b4ff3a36 6317 u8 reserved_at_60[0x20];
e281682b
SM		 6318};
6319
6320struct mlx5_ifc_destroy_cq_out_bits {
6321 u8 status[0x8];
b4ff3a36 6322 u8 reserved_at_8[0x18];
e281682b
SM		 6323
6324 u8 syndrome[0x20];
6325
b4ff3a36 6326 u8 reserved_at_40[0x40];
e281682b
SM		 6327};
6328
6329struct mlx5_ifc_destroy_cq_in_bits {
6330 u8 opcode[0x10];
b4ff3a36 6331 u8 reserved_at_10[0x10];
e281682b 6332
b4ff3a36 6333 u8 reserved_at_20[0x10];
e281682b
SM		 6334 u8 op_mod[0x10];
6335
b4ff3a36 6336 u8 reserved_at_40[0x8];
e281682b
SM		 6337 u8 cqn[0x18];
6338
b4ff3a36 6339 u8 reserved_at_60[0x20];
e281682b
SM		 6340};
6341
6342struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6343 u8 status[0x8];
b4ff3a36 6344 u8 reserved_at_8[0x18];
e281682b
SM		 6345
6346 u8 syndrome[0x20];
6347
b4ff3a36 6348 u8 reserved_at_40[0x40];
e281682b
SM		 6349};
6350
6351struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6352 u8 opcode[0x10];
b4ff3a36 6353 u8 reserved_at_10[0x10];
e281682b 6354
b4ff3a36 6355 u8 reserved_at_20[0x10];
e281682b
SM		 6356 u8 op_mod[0x10];
6357
b4ff3a36 6358 u8 reserved_at_40[0x20];
e281682b 6359
b4ff3a36 6360 u8 reserved_at_60[0x10];
e281682b
SM		 6361 u8 vxlan_udp_port[0x10];
6362};
6363
6364struct mlx5_ifc_delete_l2_table_entry_out_bits {
6365 u8 status[0x8];
b4ff3a36 6366 u8 reserved_at_8[0x18];
e281682b
SM		 6367
6368 u8 syndrome[0x20];
6369
b4ff3a36 6370 u8 reserved_at_40[0x40];
e281682b
SM		 6371};
6372
6373struct mlx5_ifc_delete_l2_table_entry_in_bits {
6374 u8 opcode[0x10];
b4ff3a36 6375 u8 reserved_at_10[0x10];
e281682b 6376
b4ff3a36 6377 u8 reserved_at_20[0x10];
e281682b
SM		 6378 u8 op_mod[0x10];
6379
b4ff3a36 6380 u8 reserved_at_40[0x60];
e281682b 6381
b4ff3a36 6382 u8 reserved_at_a0[0x8];
e281682b
SM		 6383 u8 table_index[0x18];
6384
b4ff3a36 6385 u8 reserved_at_c0[0x140];
e281682b
SM		 6386};
6387
6388struct mlx5_ifc_delete_fte_out_bits {
6389 u8 status[0x8];
b4ff3a36 6390 u8 reserved_at_8[0x18];
e281682b
SM		 6391
6392 u8 syndrome[0x20];
6393
b4ff3a36 6394 u8 reserved_at_40[0x40];
e281682b
SM		 6395};
6396
6397struct mlx5_ifc_delete_fte_in_bits {
6398 u8 opcode[0x10];
b4ff3a36 6399 u8 reserved_at_10[0x10];
e281682b 6400
b4ff3a36 6401 u8 reserved_at_20[0x10];
e281682b
SM		 6402 u8 op_mod[0x10];
6403
7d5e1423
SM		 6404 u8 other_vport[0x1];
6405 u8 reserved_at_41[0xf];
6406 u8 vport_number[0x10];
6407
6408 u8 reserved_at_60[0x20];
e281682b
SM		 6409
6410 u8 table_type[0x8];
b4ff3a36 6411 u8 reserved_at_88[0x18];
e281682b 6412
b4ff3a36 6413 u8 reserved_at_a0[0x8];
e281682b
SM		 6414 u8 table_id[0x18];
6415
b4ff3a36 6416 u8 reserved_at_c0[0x40];
e281682b
SM		 6417
6418 u8 flow_index[0x20];
6419
b4ff3a36 6420 u8 reserved_at_120[0xe0];
e281682b
SM		 6421};
6422
6423struct mlx5_ifc_dealloc_xrcd_out_bits {
6424 u8 status[0x8];
b4ff3a36 6425 u8 reserved_at_8[0x18];
e281682b
SM		 6426
6427 u8 syndrome[0x20];
6428
b4ff3a36 6429 u8 reserved_at_40[0x40];
e281682b
SM		 6430};
6431
6432struct mlx5_ifc_dealloc_xrcd_in_bits {
6433 u8 opcode[0x10];
b4ff3a36 6434 u8 reserved_at_10[0x10];
e281682b 6435
b4ff3a36 6436 u8 reserved_at_20[0x10];
e281682b
SM		 6437 u8 op_mod[0x10];
6438
b4ff3a36 6439 u8 reserved_at_40[0x8];
e281682b
SM		 6440 u8 xrcd[0x18];
6441
b4ff3a36 6442 u8 reserved_at_60[0x20];
e281682b
SM		 6443};
6444
6445struct mlx5_ifc_dealloc_uar_out_bits {
6446 u8 status[0x8];
b4ff3a36 6447 u8 reserved_at_8[0x18];
e281682b
SM		 6448
6449 u8 syndrome[0x20];
6450
b4ff3a36 6451 u8 reserved_at_40[0x40];
e281682b
SM		 6452};
6453
6454struct mlx5_ifc_dealloc_uar_in_bits {
6455 u8 opcode[0x10];
b4ff3a36 6456 u8 reserved_at_10[0x10];
e281682b 6457
b4ff3a36 6458 u8 reserved_at_20[0x10];
e281682b
SM		 6459 u8 op_mod[0x10];
6460
b4ff3a36 6461 u8 reserved_at_40[0x8];
e281682b
SM		 6462 u8 uar[0x18];
6463
b4ff3a36 6464 u8 reserved_at_60[0x20];
e281682b
SM		 6465};
6466
6467struct mlx5_ifc_dealloc_transport_domain_out_bits {
6468 u8 status[0x8];
b4ff3a36 6469 u8 reserved_at_8[0x18];
e281682b
SM		 6470
6471 u8 syndrome[0x20];
6472
b4ff3a36 6473 u8 reserved_at_40[0x40];
e281682b
SM		 6474};
6475
6476struct mlx5_ifc_dealloc_transport_domain_in_bits {
6477 u8 opcode[0x10];
b4ff3a36 6478 u8 reserved_at_10[0x10];
e281682b 6479
b4ff3a36 6480 u8 reserved_at_20[0x10];
e281682b
SM		 6481 u8 op_mod[0x10];
6482
b4ff3a36 6483 u8 reserved_at_40[0x8];
e281682b
SM		 6484 u8 transport_domain[0x18];
6485
b4ff3a36 6486 u8 reserved_at_60[0x20];
e281682b
SM		 6487};
6488
6489struct mlx5_ifc_dealloc_q_counter_out_bits {
6490 u8 status[0x8];
b4ff3a36 6491 u8 reserved_at_8[0x18];
e281682b
SM		 6492
6493 u8 syndrome[0x20];
6494
b4ff3a36 6495 u8 reserved_at_40[0x40];
e281682b
SM		 6496};
6497
6498struct mlx5_ifc_dealloc_q_counter_in_bits {
6499 u8 opcode[0x10];
b4ff3a36 6500 u8 reserved_at_10[0x10];
e281682b 6501
b4ff3a36 6502 u8 reserved_at_20[0x10];
e281682b
SM		 6503 u8 op_mod[0x10];
6504
b4ff3a36 6505 u8 reserved_at_40[0x18];
e281682b
SM		 6506 u8 counter_set_id[0x8];
6507
b4ff3a36 6508 u8 reserved_at_60[0x20];
e281682b
SM		 6509};
6510
6511struct mlx5_ifc_dealloc_pd_out_bits {
6512 u8 status[0x8];
b4ff3a36 6513 u8 reserved_at_8[0x18];
e281682b
SM		 6514
6515 u8 syndrome[0x20];
6516
b4ff3a36 6517 u8 reserved_at_40[0x40];
e281682b
SM		 6518};
6519
6520struct mlx5_ifc_dealloc_pd_in_bits {
6521 u8 opcode[0x10];
b4ff3a36 6522 u8 reserved_at_10[0x10];
e281682b 6523
b4ff3a36 6524 u8 reserved_at_20[0x10];
e281682b
SM		 6525 u8 op_mod[0x10];
6526
b4ff3a36 6527 u8 reserved_at_40[0x8];
e281682b
SM		 6528 u8 pd[0x18];
6529
b4ff3a36 6530 u8 reserved_at_60[0x20];
e281682b
SM		 6531};
6532
9dc0b289
AV		 6533struct mlx5_ifc_dealloc_flow_counter_out_bits {
6534 u8 status[0x8];
6535 u8 reserved_at_8[0x18];
6536
6537 u8 syndrome[0x20];
6538
6539 u8 reserved_at_40[0x40];
6540};
6541
6542struct mlx5_ifc_dealloc_flow_counter_in_bits {
6543 u8 opcode[0x10];
6544 u8 reserved_at_10[0x10];
6545
6546 u8 reserved_at_20[0x10];
6547 u8 op_mod[0x10];
6548
a8ffcc74 6549 u8 flow_counter_id[0x20];
9dc0b289
AV		 6550
6551 u8 reserved_at_60[0x20];
6552};
6553
7486216b
SM		 6554struct mlx5_ifc_create_xrq_out_bits {
6555 u8 status[0x8];
6556 u8 reserved_at_8[0x18];
6557
6558 u8 syndrome[0x20];
6559
6560 u8 reserved_at_40[0x8];
6561 u8 xrqn[0x18];
6562
6563 u8 reserved_at_60[0x20];
6564};
6565
6566struct mlx5_ifc_create_xrq_in_bits {
6567 u8 opcode[0x10];
6568 u8 reserved_at_10[0x10];
6569
6570 u8 reserved_at_20[0x10];
6571 u8 op_mod[0x10];
6572
6573 u8 reserved_at_40[0x40];
6574
6575 struct mlx5_ifc_xrqc_bits xrq_context;
6576};
6577
e281682b
SM		 6578struct mlx5_ifc_create_xrc_srq_out_bits {
6579 u8 status[0x8];
b4ff3a36 6580 u8 reserved_at_8[0x18];
e281682b
SM		 6581
6582 u8 syndrome[0x20];
6583
b4ff3a36 6584 u8 reserved_at_40[0x8];
e281682b
SM		 6585 u8 xrc_srqn[0x18];
6586
b4ff3a36 6587 u8 reserved_at_60[0x20];
e281682b
SM		 6588};
6589
6590struct mlx5_ifc_create_xrc_srq_in_bits {
6591 u8 opcode[0x10];
b4ff3a36 6592 u8 reserved_at_10[0x10];
e281682b 6593
b4ff3a36 6594 u8 reserved_at_20[0x10];
e281682b
SM		 6595 u8 op_mod[0x10];
6596
b4ff3a36 6597 u8 reserved_at_40[0x40];
e281682b
SM		 6598
6599 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6600
b4ff3a36 6601 u8 reserved_at_280[0x600];
e281682b
SM		 6602
6603 u8 pas[0][0x40];
6604};
6605
6606struct mlx5_ifc_create_tis_out_bits {
6607 u8 status[0x8];
b4ff3a36 6608 u8 reserved_at_8[0x18];
e281682b
SM		 6609
6610 u8 syndrome[0x20];
6611
b4ff3a36 6612 u8 reserved_at_40[0x8];
e281682b
SM		 6613 u8 tisn[0x18];
6614
b4ff3a36 6615 u8 reserved_at_60[0x20];
e281682b
SM		 6616};
6617
6618struct mlx5_ifc_create_tis_in_bits {
6619 u8 opcode[0x10];
b4ff3a36 6620 u8 reserved_at_10[0x10];
e281682b 6621
b4ff3a36 6622 u8 reserved_at_20[0x10];
e281682b
SM		 6623 u8 op_mod[0x10];
6624
b4ff3a36 6625 u8 reserved_at_40[0xc0];
e281682b
SM		 6626
6627 struct mlx5_ifc_tisc_bits ctx;
6628};
6629
6630struct mlx5_ifc_create_tir_out_bits {
6631 u8 status[0x8];
b4ff3a36 6632 u8 reserved_at_8[0x18];
e281682b
SM		 6633
6634 u8 syndrome[0x20];
6635
b4ff3a36 6636 u8 reserved_at_40[0x8];
e281682b
SM		 6637 u8 tirn[0x18];
6638
b4ff3a36 6639 u8 reserved_at_60[0x20];
e281682b
SM		 6640};
6641
6642struct mlx5_ifc_create_tir_in_bits {
6643 u8 opcode[0x10];
b4ff3a36 6644 u8 reserved_at_10[0x10];
e281682b 6645
b4ff3a36 6646 u8 reserved_at_20[0x10];
e281682b
SM		 6647 u8 op_mod[0x10];
6648
b4ff3a36 6649 u8 reserved_at_40[0xc0];
e281682b
SM		 6650
6651 struct mlx5_ifc_tirc_bits ctx;
6652};
6653
6654struct mlx5_ifc_create_srq_out_bits {
6655 u8 status[0x8];
b4ff3a36 6656 u8 reserved_at_8[0x18];
e281682b
SM		 6657
6658 u8 syndrome[0x20];
6659
b4ff3a36 6660 u8 reserved_at_40[0x8];
e281682b
SM		 6661 u8 srqn[0x18];
6662
b4ff3a36 6663 u8 reserved_at_60[0x20];
e281682b
SM		 6664};
6665
6666struct mlx5_ifc_create_srq_in_bits {
6667 u8 opcode[0x10];
b4ff3a36 6668 u8 reserved_at_10[0x10];
e281682b 6669
b4ff3a36 6670 u8 reserved_at_20[0x10];
e281682b
SM		 6671 u8 op_mod[0x10];
6672
b4ff3a36 6673 u8 reserved_at_40[0x40];
e281682b
SM		 6674
6675 struct mlx5_ifc_srqc_bits srq_context_entry;
6676
b4ff3a36 6677 u8 reserved_at_280[0x600];
e281682b
SM		 6678
6679 u8 pas[0][0x40];
6680};
6681
6682struct mlx5_ifc_create_sq_out_bits {
6683 u8 status[0x8];
b4ff3a36 6684 u8 reserved_at_8[0x18];
e281682b
SM		 6685
6686 u8 syndrome[0x20];
6687
b4ff3a36 6688 u8 reserved_at_40[0x8];
e281682b
SM		 6689 u8 sqn[0x18];
6690
b4ff3a36 6691 u8 reserved_at_60[0x20];
e281682b
SM		 6692};
6693
6694struct mlx5_ifc_create_sq_in_bits {
6695 u8 opcode[0x10];
b4ff3a36 6696 u8 reserved_at_10[0x10];
e281682b 6697
b4ff3a36 6698 u8 reserved_at_20[0x10];
e281682b
SM		 6699 u8 op_mod[0x10];
6700
b4ff3a36 6701 u8 reserved_at_40[0xc0];
e281682b
SM		 6702
6703 struct mlx5_ifc_sqc_bits ctx;
6704};
6705
813f8540
MHY		 6706struct mlx5_ifc_create_scheduling_element_out_bits {
6707 u8 status[0x8];
6708 u8 reserved_at_8[0x18];
6709
6710 u8 syndrome[0x20];
6711
6712 u8 reserved_at_40[0x40];
6713
6714 u8 scheduling_element_id[0x20];
6715
6716 u8 reserved_at_a0[0x160];
6717};
6718
6719struct mlx5_ifc_create_scheduling_element_in_bits {
6720 u8 opcode[0x10];
6721 u8 reserved_at_10[0x10];
6722
6723 u8 reserved_at_20[0x10];
6724 u8 op_mod[0x10];
6725
6726 u8 scheduling_hierarchy[0x8];
6727 u8 reserved_at_48[0x18];
6728
6729 u8 reserved_at_60[0xa0];
6730
6731 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6732
6733 u8 reserved_at_300[0x100];
6734};
6735
e281682b
SM		 6736struct mlx5_ifc_create_rqt_out_bits {
6737 u8 status[0x8];
b4ff3a36 6738 u8 reserved_at_8[0x18];
e281682b
SM		 6739
6740 u8 syndrome[0x20];
6741
b4ff3a36 6742 u8 reserved_at_40[0x8];
e281682b
SM		 6743 u8 rqtn[0x18];
6744
b4ff3a36 6745 u8 reserved_at_60[0x20];
e281682b
SM		 6746};
6747
6748struct mlx5_ifc_create_rqt_in_bits {
6749 u8 opcode[0x10];
b4ff3a36 6750 u8 reserved_at_10[0x10];
e281682b 6751
b4ff3a36 6752 u8 reserved_at_20[0x10];
e281682b
SM		 6753 u8 op_mod[0x10];
6754
b4ff3a36 6755 u8 reserved_at_40[0xc0];
e281682b
SM		 6756
6757 struct mlx5_ifc_rqtc_bits rqt_context;
6758};
6759
6760struct mlx5_ifc_create_rq_out_bits {
6761 u8 status[0x8];
b4ff3a36 6762 u8 reserved_at_8[0x18];
e281682b
SM		 6763
6764 u8 syndrome[0x20];
6765
b4ff3a36 6766 u8 reserved_at_40[0x8];
e281682b
SM		 6767 u8 rqn[0x18];
6768
b4ff3a36 6769 u8 reserved_at_60[0x20];
e281682b
SM		 6770};
6771
6772struct mlx5_ifc_create_rq_in_bits {
6773 u8 opcode[0x10];
b4ff3a36 6774 u8 reserved_at_10[0x10];
e281682b 6775
b4ff3a36 6776 u8 reserved_at_20[0x10];
e281682b
SM		 6777 u8 op_mod[0x10];
6778
b4ff3a36 6779 u8 reserved_at_40[0xc0];
e281682b
SM		 6780
6781 struct mlx5_ifc_rqc_bits ctx;
6782};
6783
6784struct mlx5_ifc_create_rmp_out_bits {
6785 u8 status[0x8];
b4ff3a36 6786 u8 reserved_at_8[0x18];
e281682b
SM		 6787
6788 u8 syndrome[0x20];
6789
b4ff3a36 6790 u8 reserved_at_40[0x8];
e281682b
SM		 6791 u8 rmpn[0x18];
6792
b4ff3a36 6793 u8 reserved_at_60[0x20];
e281682b
SM		 6794};
6795
6796struct mlx5_ifc_create_rmp_in_bits {
6797 u8 opcode[0x10];
b4ff3a36 6798 u8 reserved_at_10[0x10];
e281682b 6799
b4ff3a36 6800 u8 reserved_at_20[0x10];
e281682b
SM		 6801 u8 op_mod[0x10];
6802
b4ff3a36 6803 u8 reserved_at_40[0xc0];
e281682b
SM		 6804
6805 struct mlx5_ifc_rmpc_bits ctx;
6806};
6807
6808struct mlx5_ifc_create_qp_out_bits {
6809 u8 status[0x8];
b4ff3a36 6810 u8 reserved_at_8[0x18];
e281682b
SM		 6811
6812 u8 syndrome[0x20];
6813
b4ff3a36 6814 u8 reserved_at_40[0x8];
e281682b
SM		 6815 u8 qpn[0x18];
6816
b4ff3a36 6817 u8 reserved_at_60[0x20];
e281682b
SM		 6818};
6819
6820struct mlx5_ifc_create_qp_in_bits {
6821 u8 opcode[0x10];
b4ff3a36 6822 u8 reserved_at_10[0x10];
e281682b 6823
b4ff3a36 6824 u8 reserved_at_20[0x10];
e281682b
SM		 6825 u8 op_mod[0x10];
6826
b4ff3a36 6827 u8 reserved_at_40[0x40];
e281682b
SM		 6828
6829 u8 opt_param_mask[0x20];
6830
b4ff3a36 6831 u8 reserved_at_a0[0x20];
e281682b
SM		 6832
6833 struct mlx5_ifc_qpc_bits qpc;
6834
b4ff3a36 6835 u8 reserved_at_800[0x80];
e281682b
SM		 6836
6837 u8 pas[0][0x40];
6838};
6839
6840struct mlx5_ifc_create_psv_out_bits {
6841 u8 status[0x8];
b4ff3a36 6842 u8 reserved_at_8[0x18];
e281682b
SM		 6843
6844 u8 syndrome[0x20];
6845
b4ff3a36 6846 u8 reserved_at_40[0x40];
e281682b 6847
b4ff3a36 6848 u8 reserved_at_80[0x8];
e281682b
SM		 6849 u8 psv0_index[0x18];
6850
b4ff3a36 6851 u8 reserved_at_a0[0x8];
e281682b
SM		 6852 u8 psv1_index[0x18];
6853
b4ff3a36 6854 u8 reserved_at_c0[0x8];
e281682b
SM		 6855 u8 psv2_index[0x18];
6856
b4ff3a36 6857 u8 reserved_at_e0[0x8];
e281682b
SM		 6858 u8 psv3_index[0x18];
6859};
6860
6861struct mlx5_ifc_create_psv_in_bits {
6862 u8 opcode[0x10];
b4ff3a36 6863 u8 reserved_at_10[0x10];
e281682b 6864
b4ff3a36 6865 u8 reserved_at_20[0x10];
e281682b
SM		 6866 u8 op_mod[0x10];
6867
6868 u8 num_psv[0x4];
b4ff3a36 6869 u8 reserved_at_44[0x4];
e281682b
SM		 6870 u8 pd[0x18];
6871
b4ff3a36 6872 u8 reserved_at_60[0x20];
e281682b
SM		 6873};
6874
6875struct mlx5_ifc_create_mkey_out_bits {
6876 u8 status[0x8];
b4ff3a36 6877 u8 reserved_at_8[0x18];
e281682b
SM		 6878
6879 u8 syndrome[0x20];
6880
b4ff3a36 6881 u8 reserved_at_40[0x8];
e281682b
SM		 6882 u8 mkey_index[0x18];
6883
b4ff3a36 6884 u8 reserved_at_60[0x20];
e281682b
SM		 6885};
6886
6887struct mlx5_ifc_create_mkey_in_bits {
6888 u8 opcode[0x10];
b4ff3a36 6889 u8 reserved_at_10[0x10];
e281682b 6890
b4ff3a36 6891 u8 reserved_at_20[0x10];
e281682b
SM		 6892 u8 op_mod[0x10];
6893
b4ff3a36 6894 u8 reserved_at_40[0x20];
e281682b
SM		 6895
6896 u8 pg_access[0x1];
b4ff3a36 6897 u8 reserved_at_61[0x1f];
e281682b
SM		 6898
6899 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6900
b4ff3a36 6901 u8 reserved_at_280[0x80];
e281682b
SM		 6902
6903 u8 translations_octword_actual_size[0x20];
6904
b4ff3a36 6905 u8 reserved_at_320[0x560];
e281682b
SM		 6906
6907 u8 klm_pas_mtt[0][0x20];
6908};
6909
6910struct mlx5_ifc_create_flow_table_out_bits {
6911 u8 status[0x8];
b4ff3a36 6912 u8 reserved_at_8[0x18];
e281682b
SM		 6913
6914 u8 syndrome[0x20];
6915
b4ff3a36 6916 u8 reserved_at_40[0x8];
e281682b
SM		 6917 u8 table_id[0x18];
6918
b4ff3a36 6919 u8 reserved_at_60[0x20];
e281682b
SM		 6920};
6921
0c90e9c6
MG		 6922struct mlx5_ifc_flow_table_context_bits {
6923 u8 encap_en[0x1];
6924 u8 decap_en[0x1];
6925 u8 reserved_at_2[0x2];
6926 u8 table_miss_action[0x4];
6927 u8 level[0x8];
6928 u8 reserved_at_10[0x8];
6929 u8 log_size[0x8];
6930
6931 u8 reserved_at_20[0x8];
6932 u8 table_miss_id[0x18];
6933
6934 u8 reserved_at_40[0x8];
6935 u8 lag_master_next_table_id[0x18];
6936
6937 u8 reserved_at_60[0xe0];
6938};
6939
e281682b
SM		 6940struct mlx5_ifc_create_flow_table_in_bits {
6941 u8 opcode[0x10];
b4ff3a36 6942 u8 reserved_at_10[0x10];
e281682b 6943
b4ff3a36 6944 u8 reserved_at_20[0x10];
e281682b
SM		 6945 u8 op_mod[0x10];
6946
7d5e1423
SM		 6947 u8 other_vport[0x1];
6948 u8 reserved_at_41[0xf];
6949 u8 vport_number[0x10];
6950
6951 u8 reserved_at_60[0x20];
e281682b
SM		 6952
6953 u8 table_type[0x8];
b4ff3a36 6954 u8 reserved_at_88[0x18];
e281682b 6955
b4ff3a36 6956 u8 reserved_at_a0[0x20];
e281682b 6957
0c90e9c6 6958 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6959};
6960
6961struct mlx5_ifc_create_flow_group_out_bits {
6962 u8 status[0x8];
b4ff3a36 6963 u8 reserved_at_8[0x18];
e281682b
SM		 6964
6965 u8 syndrome[0x20];
6966
b4ff3a36 6967 u8 reserved_at_40[0x8];
e281682b
SM		 6968 u8 group_id[0x18];
6969
b4ff3a36 6970 u8 reserved_at_60[0x20];
e281682b
SM		 6971};
6972
6973enum {
6974 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6975 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6976 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6977};
6978
6979struct mlx5_ifc_create_flow_group_in_bits {
6980 u8 opcode[0x10];
b4ff3a36 6981 u8 reserved_at_10[0x10];
e281682b 6982
b4ff3a36 6983 u8 reserved_at_20[0x10];
e281682b
SM		 6984 u8 op_mod[0x10];
6985
7d5e1423
SM		 6986 u8 other_vport[0x1];
6987 u8 reserved_at_41[0xf];
6988 u8 vport_number[0x10];
6989
6990 u8 reserved_at_60[0x20];
e281682b
SM		 6991
6992 u8 table_type[0x8];
b4ff3a36 6993 u8 reserved_at_88[0x18];
e281682b 6994
b4ff3a36 6995 u8 reserved_at_a0[0x8];
e281682b
SM		 6996 u8 table_id[0x18];
6997
3e99df87
SK		 6998 u8 source_eswitch_owner_vhca_id_valid[0x1];
6999
7000 u8 reserved_at_c1[0x1f];
e281682b
SM		 7001
7002 u8 start_flow_index[0x20];
7003
b4ff3a36 7004 u8 reserved_at_100[0x20];
e281682b
SM		 7005
7006 u8 end_flow_index[0x20];
7007
b4ff3a36 7008 u8 reserved_at_140[0xa0];
e281682b 7009
b4ff3a36 7010 u8 reserved_at_1e0[0x18];
e281682b
SM		 7011 u8 match_criteria_enable[0x8];
7012
7013 struct mlx5_ifc_fte_match_param_bits match_criteria;
7014
b4ff3a36 7015 u8 reserved_at_1200[0xe00];
e281682b
SM		 7016};
7017
7018struct mlx5_ifc_create_eq_out_bits {
7019 u8 status[0x8];
b4ff3a36 7020 u8 reserved_at_8[0x18];
e281682b
SM		 7021
7022 u8 syndrome[0x20];
7023
b4ff3a36 7024 u8 reserved_at_40[0x18];
e281682b
SM		 7025 u8 eq_number[0x8];
7026
b4ff3a36 7027 u8 reserved_at_60[0x20];
e281682b
SM		 7028};
7029
7030struct mlx5_ifc_create_eq_in_bits {
7031 u8 opcode[0x10];
b4ff3a36 7032 u8 reserved_at_10[0x10];
e281682b 7033
b4ff3a36 7034 u8 reserved_at_20[0x10];
e281682b
SM		 7035 u8 op_mod[0x10];
7036
b4ff3a36 7037 u8 reserved_at_40[0x40];
e281682b
SM		 7038
7039 struct mlx5_ifc_eqc_bits eq_context_entry;
7040
b4ff3a36 7041 u8 reserved_at_280[0x40];
e281682b
SM		 7042
7043 u8 event_bitmask[0x40];
7044
b4ff3a36 7045 u8 reserved_at_300[0x580];
e281682b
SM		 7046
7047 u8 pas[0][0x40];
7048};
7049
7050struct mlx5_ifc_create_dct_out_bits {
7051 u8 status[0x8];
b4ff3a36 7052 u8 reserved_at_8[0x18];
e281682b
SM		 7053
7054 u8 syndrome[0x20];
7055
b4ff3a36 7056 u8 reserved_at_40[0x8];
e281682b
SM		 7057 u8 dctn[0x18];
7058
b4ff3a36 7059 u8 reserved_at_60[0x20];
e281682b
SM		 7060};
7061
7062struct mlx5_ifc_create_dct_in_bits {
7063 u8 opcode[0x10];
b4ff3a36 7064 u8 reserved_at_10[0x10];
e281682b 7065
b4ff3a36 7066 u8 reserved_at_20[0x10];
e281682b
SM		 7067 u8 op_mod[0x10];
7068
b4ff3a36 7069 u8 reserved_at_40[0x40];
e281682b
SM		 7070
7071 struct mlx5_ifc_dctc_bits dct_context_entry;
7072
b4ff3a36 7073 u8 reserved_at_280[0x180];
e281682b
SM		 7074};
7075
7076struct mlx5_ifc_create_cq_out_bits {
7077 u8 status[0x8];
b4ff3a36 7078 u8 reserved_at_8[0x18];
e281682b
SM		 7079
7080 u8 syndrome[0x20];
7081
b4ff3a36 7082 u8 reserved_at_40[0x8];
e281682b
SM		 7083 u8 cqn[0x18];
7084
b4ff3a36 7085 u8 reserved_at_60[0x20];
e281682b
SM		 7086};
7087
7088struct mlx5_ifc_create_cq_in_bits {
7089 u8 opcode[0x10];
b4ff3a36 7090 u8 reserved_at_10[0x10];
e281682b 7091
b4ff3a36 7092 u8 reserved_at_20[0x10];
e281682b
SM		 7093 u8 op_mod[0x10];
7094
b4ff3a36 7095 u8 reserved_at_40[0x40];
e281682b
SM		 7096
7097 struct mlx5_ifc_cqc_bits cq_context;
7098
b4ff3a36 7099 u8 reserved_at_280[0x600];
e281682b
SM		 7100
7101 u8 pas[0][0x40];
7102};
7103
7104struct mlx5_ifc_config_int_moderation_out_bits {
7105 u8 status[0x8];
b4ff3a36 7106 u8 reserved_at_8[0x18];
e281682b
SM		 7107
7108 u8 syndrome[0x20];
7109
b4ff3a36 7110 u8 reserved_at_40[0x4];
e281682b
SM		 7111 u8 min_delay[0xc];
7112 u8 int_vector[0x10];
7113
b4ff3a36 7114 u8 reserved_at_60[0x20];
e281682b
SM		 7115};
7116
7117enum {
7118 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7119 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7120};
7121
7122struct mlx5_ifc_config_int_moderation_in_bits {
7123 u8 opcode[0x10];
b4ff3a36 7124 u8 reserved_at_10[0x10];
e281682b 7125
b4ff3a36 7126 u8 reserved_at_20[0x10];
e281682b
SM		 7127 u8 op_mod[0x10];
7128
b4ff3a36 7129 u8 reserved_at_40[0x4];
e281682b
SM		 7130 u8 min_delay[0xc];
7131 u8 int_vector[0x10];
7132
b4ff3a36 7133 u8 reserved_at_60[0x20];
e281682b
SM		 7134};
7135
7136struct mlx5_ifc_attach_to_mcg_out_bits {
7137 u8 status[0x8];
b4ff3a36 7138 u8 reserved_at_8[0x18];
e281682b
SM		 7139
7140 u8 syndrome[0x20];
7141
b4ff3a36 7142 u8 reserved_at_40[0x40];
e281682b
SM		 7143};
7144
7145struct mlx5_ifc_attach_to_mcg_in_bits {
7146 u8 opcode[0x10];
b4ff3a36 7147 u8 reserved_at_10[0x10];
e281682b 7148
b4ff3a36 7149 u8 reserved_at_20[0x10];
e281682b
SM		 7150 u8 op_mod[0x10];
7151
b4ff3a36 7152 u8 reserved_at_40[0x8];
e281682b
SM		 7153 u8 qpn[0x18];
7154
b4ff3a36 7155 u8 reserved_at_60[0x20];
e281682b
SM		 7156
7157 u8 multicast_gid[16][0x8];
7158};
7159
7486216b
SM		 7160struct mlx5_ifc_arm_xrq_out_bits {
7161 u8 status[0x8];
7162 u8 reserved_at_8[0x18];
7163
7164 u8 syndrome[0x20];
7165
7166 u8 reserved_at_40[0x40];
7167};
7168
7169struct mlx5_ifc_arm_xrq_in_bits {
7170 u8 opcode[0x10];
7171 u8 reserved_at_10[0x10];
7172
7173 u8 reserved_at_20[0x10];
7174 u8 op_mod[0x10];
7175
7176 u8 reserved_at_40[0x8];
7177 u8 xrqn[0x18];
7178
7179 u8 reserved_at_60[0x10];
7180 u8 lwm[0x10];
7181};
7182
e281682b
SM		 7183struct mlx5_ifc_arm_xrc_srq_out_bits {
7184 u8 status[0x8];
b4ff3a36 7185 u8 reserved_at_8[0x18];
e281682b
SM		 7186
7187 u8 syndrome[0x20];
7188
b4ff3a36 7189 u8 reserved_at_40[0x40];
e281682b
SM		 7190};
7191
7192enum {
7193 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7194};
7195
7196struct mlx5_ifc_arm_xrc_srq_in_bits {
7197 u8 opcode[0x10];
b4ff3a36 7198 u8 reserved_at_10[0x10];
e281682b 7199
b4ff3a36 7200 u8 reserved_at_20[0x10];
e281682b
SM		 7201 u8 op_mod[0x10];
7202
b4ff3a36 7203 u8 reserved_at_40[0x8];
e281682b
SM		 7204 u8 xrc_srqn[0x18];
7205
b4ff3a36 7206 u8 reserved_at_60[0x10];
e281682b
SM		 7207 u8 lwm[0x10];
7208};
7209
7210struct mlx5_ifc_arm_rq_out_bits {
7211 u8 status[0x8];
b4ff3a36 7212 u8 reserved_at_8[0x18];
e281682b
SM		 7213
7214 u8 syndrome[0x20];
7215
b4ff3a36 7216 u8 reserved_at_40[0x40];
e281682b
SM		 7217};
7218
7219enum {
7486216b
SM		 7220 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7221 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7222};
7223
7224struct mlx5_ifc_arm_rq_in_bits {
7225 u8 opcode[0x10];
b4ff3a36 7226 u8 reserved_at_10[0x10];
e281682b 7227
b4ff3a36 7228 u8 reserved_at_20[0x10];
e281682b
SM		 7229 u8 op_mod[0x10];
7230
b4ff3a36 7231 u8 reserved_at_40[0x8];
e281682b
SM		 7232 u8 srq_number[0x18];
7233
b4ff3a36 7234 u8 reserved_at_60[0x10];
e281682b
SM		 7235 u8 lwm[0x10];
7236};
7237
7238struct mlx5_ifc_arm_dct_out_bits {
7239 u8 status[0x8];
b4ff3a36 7240 u8 reserved_at_8[0x18];
e281682b
SM		 7241
7242 u8 syndrome[0x20];
7243
b4ff3a36 7244 u8 reserved_at_40[0x40];
e281682b
SM		 7245};
7246
7247struct mlx5_ifc_arm_dct_in_bits {
7248 u8 opcode[0x10];
b4ff3a36 7249 u8 reserved_at_10[0x10];
e281682b 7250
b4ff3a36 7251 u8 reserved_at_20[0x10];
e281682b
SM		 7252 u8 op_mod[0x10];
7253
b4ff3a36 7254 u8 reserved_at_40[0x8];
e281682b
SM		 7255 u8 dct_number[0x18];
7256
b4ff3a36 7257 u8 reserved_at_60[0x20];
e281682b
SM		 7258};
7259
7260struct mlx5_ifc_alloc_xrcd_out_bits {
7261 u8 status[0x8];
b4ff3a36 7262 u8 reserved_at_8[0x18];
e281682b
SM		 7263
7264 u8 syndrome[0x20];
7265
b4ff3a36 7266 u8 reserved_at_40[0x8];
e281682b
SM		 7267 u8 xrcd[0x18];
7268
b4ff3a36 7269 u8 reserved_at_60[0x20];
e281682b
SM		 7270};
7271
7272struct mlx5_ifc_alloc_xrcd_in_bits {
7273 u8 opcode[0x10];
b4ff3a36 7274 u8 reserved_at_10[0x10];
e281682b 7275
b4ff3a36 7276 u8 reserved_at_20[0x10];
e281682b
SM		 7277 u8 op_mod[0x10];
7278
b4ff3a36 7279 u8 reserved_at_40[0x40];
e281682b
SM		 7280};
7281
7282struct mlx5_ifc_alloc_uar_out_bits {
7283 u8 status[0x8];
b4ff3a36 7284 u8 reserved_at_8[0x18];
e281682b
SM		 7285
7286 u8 syndrome[0x20];
7287
b4ff3a36 7288 u8 reserved_at_40[0x8];
e281682b
SM		 7289 u8 uar[0x18];
7290
b4ff3a36 7291 u8 reserved_at_60[0x20];
e281682b
SM		 7292};
7293
7294struct mlx5_ifc_alloc_uar_in_bits {
7295 u8 opcode[0x10];
b4ff3a36 7296 u8 reserved_at_10[0x10];
e281682b 7297
b4ff3a36 7298 u8 reserved_at_20[0x10];
e281682b
SM		 7299 u8 op_mod[0x10];
7300
b4ff3a36 7301 u8 reserved_at_40[0x40];
e281682b
SM		 7302};
7303
7304struct mlx5_ifc_alloc_transport_domain_out_bits {
7305 u8 status[0x8];
b4ff3a36 7306 u8 reserved_at_8[0x18];
e281682b
SM		 7307
7308 u8 syndrome[0x20];
7309
b4ff3a36 7310 u8 reserved_at_40[0x8];
e281682b
SM		 7311 u8 transport_domain[0x18];
7312
b4ff3a36 7313 u8 reserved_at_60[0x20];
e281682b
SM		 7314};
7315
7316struct mlx5_ifc_alloc_transport_domain_in_bits {
7317 u8 opcode[0x10];
b4ff3a36 7318 u8 reserved_at_10[0x10];
e281682b 7319
b4ff3a36 7320 u8 reserved_at_20[0x10];
e281682b
SM		 7321 u8 op_mod[0x10];
7322
b4ff3a36 7323 u8 reserved_at_40[0x40];
e281682b
SM		 7324};
7325
7326struct mlx5_ifc_alloc_q_counter_out_bits {
7327 u8 status[0x8];
b4ff3a36 7328 u8 reserved_at_8[0x18];
e281682b
SM		 7329
7330 u8 syndrome[0x20];
7331
b4ff3a36 7332 u8 reserved_at_40[0x18];
e281682b
SM		 7333 u8 counter_set_id[0x8];
7334
b4ff3a36 7335 u8 reserved_at_60[0x20];
e281682b
SM		 7336};
7337
7338struct mlx5_ifc_alloc_q_counter_in_bits {
7339 u8 opcode[0x10];
b4ff3a36 7340 u8 reserved_at_10[0x10];
e281682b 7341
b4ff3a36 7342 u8 reserved_at_20[0x10];
e281682b
SM		 7343 u8 op_mod[0x10];
7344
b4ff3a36 7345 u8 reserved_at_40[0x40];
e281682b
SM		 7346};
7347
7348struct mlx5_ifc_alloc_pd_out_bits {
7349 u8 status[0x8];
b4ff3a36 7350 u8 reserved_at_8[0x18];
e281682b
SM		 7351
7352 u8 syndrome[0x20];
7353
b4ff3a36 7354 u8 reserved_at_40[0x8];
e281682b
SM		 7355 u8 pd[0x18];
7356
b4ff3a36 7357 u8 reserved_at_60[0x20];
e281682b
SM		 7358};
7359
7360struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7361 u8 opcode[0x10];
7362 u8 reserved_at_10[0x10];
7363
7364 u8 reserved_at_20[0x10];
7365 u8 op_mod[0x10];
7366
7367 u8 reserved_at_40[0x40];
7368};
7369
7370struct mlx5_ifc_alloc_flow_counter_out_bits {
7371 u8 status[0x8];
7372 u8 reserved_at_8[0x18];
7373
7374 u8 syndrome[0x20];
7375
a8ffcc74 7376 u8 flow_counter_id[0x20];
9dc0b289
AV		 7377
7378 u8 reserved_at_60[0x20];
7379};
7380
7381struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7382 u8 opcode[0x10];
b4ff3a36 7383 u8 reserved_at_10[0x10];
e281682b 7384
b4ff3a36 7385 u8 reserved_at_20[0x10];
e281682b
SM		 7386 u8 op_mod[0x10];
7387
b4ff3a36 7388 u8 reserved_at_40[0x40];
e281682b
SM		 7389};
7390
7391struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7392 u8 status[0x8];
b4ff3a36 7393 u8 reserved_at_8[0x18];
e281682b
SM		 7394
7395 u8 syndrome[0x20];
7396
b4ff3a36 7397 u8 reserved_at_40[0x40];
e281682b
SM		 7398};
7399
7400struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7401 u8 opcode[0x10];
b4ff3a36 7402 u8 reserved_at_10[0x10];
e281682b 7403
b4ff3a36 7404 u8 reserved_at_20[0x10];
e281682b
SM		 7405 u8 op_mod[0x10];
7406
b4ff3a36 7407 u8 reserved_at_40[0x20];
e281682b 7408
b4ff3a36 7409 u8 reserved_at_60[0x10];
e281682b
SM		 7410 u8 vxlan_udp_port[0x10];
7411};
7412
37e92a9d 7413struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7414 u8 status[0x8];
7415 u8 reserved_at_8[0x18];
7416
7417 u8 syndrome[0x20];
7418
7419 u8 reserved_at_40[0x40];
7420};
7421
37e92a9d 7422struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7423 u8 opcode[0x10];
7424 u8 reserved_at_10[0x10];
7425
7426 u8 reserved_at_20[0x10];
7427 u8 op_mod[0x10];
7428
7429 u8 reserved_at_40[0x10];
7430 u8 rate_limit_index[0x10];
7431
7432 u8 reserved_at_60[0x20];
7433
7434 u8 rate_limit[0x20];
37e92a9d 7435
05d3ac97
BW		 7436 u8 burst_upper_bound[0x20];
7437
7438 u8 reserved_at_c0[0x10];
7439 u8 typical_packet_size[0x10];
7440
7441 u8 reserved_at_e0[0x120];
7486216b
SM		 7442};
7443
e281682b
SM		 7444struct mlx5_ifc_access_register_out_bits {
7445 u8 status[0x8];
b4ff3a36 7446 u8 reserved_at_8[0x18];
e281682b
SM		 7447
7448 u8 syndrome[0x20];
7449
b4ff3a36 7450 u8 reserved_at_40[0x40];
e281682b
SM		 7451
7452 u8 register_data[0][0x20];
7453};
7454
7455enum {
7456 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7457 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7458};
7459
7460struct mlx5_ifc_access_register_in_bits {
7461 u8 opcode[0x10];
b4ff3a36 7462 u8 reserved_at_10[0x10];
e281682b 7463
b4ff3a36 7464 u8 reserved_at_20[0x10];
e281682b
SM		 7465 u8 op_mod[0x10];
7466
b4ff3a36 7467 u8 reserved_at_40[0x10];
e281682b
SM		 7468 u8 register_id[0x10];
7469
7470 u8 argument[0x20];
7471
7472 u8 register_data[0][0x20];
7473};
7474
7475struct mlx5_ifc_sltp_reg_bits {
7476 u8 status[0x4];
7477 u8 version[0x4];
7478 u8 local_port[0x8];
7479 u8 pnat[0x2];
b4ff3a36 7480 u8 reserved_at_12[0x2];
e281682b 7481 u8 lane[0x4];
b4ff3a36 7482 u8 reserved_at_18[0x8];
e281682b 7483
b4ff3a36 7484 u8 reserved_at_20[0x20];
e281682b 7485
b4ff3a36 7486 u8 reserved_at_40[0x7];
e281682b
SM		 7487 u8 polarity[0x1];
7488 u8 ob_tap0[0x8];
7489 u8 ob_tap1[0x8];
7490 u8 ob_tap2[0x8];
7491
b4ff3a36 7492 u8 reserved_at_60[0xc];
e281682b
SM		 7493 u8 ob_preemp_mode[0x4];
7494 u8 ob_reg[0x8];
7495 u8 ob_bias[0x8];
7496
b4ff3a36 7497 u8 reserved_at_80[0x20];
e281682b
SM		 7498};
7499
7500struct mlx5_ifc_slrg_reg_bits {
7501 u8 status[0x4];
7502 u8 version[0x4];
7503 u8 local_port[0x8];
7504 u8 pnat[0x2];
b4ff3a36 7505 u8 reserved_at_12[0x2];
e281682b 7506 u8 lane[0x4];
b4ff3a36 7507 u8 reserved_at_18[0x8];
e281682b
SM		 7508
7509 u8 time_to_link_up[0x10];
b4ff3a36 7510 u8 reserved_at_30[0xc];
e281682b
SM		 7511 u8 grade_lane_speed[0x4];
7512
7513 u8 grade_version[0x8];
7514 u8 grade[0x18];
7515
b4ff3a36 7516 u8 reserved_at_60[0x4];
e281682b
SM		 7517 u8 height_grade_type[0x4];
7518 u8 height_grade[0x18];
7519
7520 u8 height_dz[0x10];
7521 u8 height_dv[0x10];
7522
b4ff3a36 7523 u8 reserved_at_a0[0x10];
e281682b
SM		 7524 u8 height_sigma[0x10];
7525
b4ff3a36 7526 u8 reserved_at_c0[0x20];
e281682b 7527
b4ff3a36 7528 u8 reserved_at_e0[0x4];
e281682b
SM		 7529 u8 phase_grade_type[0x4];
7530 u8 phase_grade[0x18];
7531
b4ff3a36 7532 u8 reserved_at_100[0x8];
e281682b 7533 u8 phase_eo_pos[0x8];
b4ff3a36 7534 u8 reserved_at_110[0x8];
e281682b
SM		 7535 u8 phase_eo_neg[0x8];
7536
7537 u8 ffe_set_tested[0x10];
7538 u8 test_errors_per_lane[0x10];
7539};
7540
7541struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7542 u8 reserved_at_0[0x8];
e281682b 7543 u8 local_port[0x8];
b4ff3a36 7544 u8 reserved_at_10[0x10];
e281682b 7545
b4ff3a36 7546 u8 reserved_at_20[0x1c];
e281682b
SM		 7547 u8 vl_hw_cap[0x4];
7548
b4ff3a36 7549 u8 reserved_at_40[0x1c];
e281682b
SM		 7550 u8 vl_admin[0x4];
7551
b4ff3a36 7552 u8 reserved_at_60[0x1c];
e281682b
SM		 7553 u8 vl_operational[0x4];
7554};
7555
7556struct mlx5_ifc_pude_reg_bits {
7557 u8 swid[0x8];
7558 u8 local_port[0x8];
b4ff3a36 7559 u8 reserved_at_10[0x4];
e281682b 7560 u8 admin_status[0x4];
b4ff3a36 7561 u8 reserved_at_18[0x4];
e281682b
SM		 7562 u8 oper_status[0x4];
7563
b4ff3a36 7564 u8 reserved_at_20[0x60];
e281682b
SM		 7565};
7566
7567struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7568 u8 reserved_at_0[0x1];
7486216b 7569 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7570 u8 an_disable_cap[0x1];
7571 u8 reserved_at_3[0x5];
e281682b 7572 u8 local_port[0x8];
b4ff3a36 7573 u8 reserved_at_10[0xd];
e281682b
SM		 7574 u8 proto_mask[0x3];
7575
7486216b
SM		 7576 u8 an_status[0x4];
7577 u8 reserved_at_24[0x3c];
e281682b
SM		 7578
7579 u8 eth_proto_capability[0x20];
7580
7581 u8 ib_link_width_capability[0x10];
7582 u8 ib_proto_capability[0x10];
7583
b4ff3a36 7584 u8 reserved_at_a0[0x20];
e281682b
SM		 7585
7586 u8 eth_proto_admin[0x20];
7587
7588 u8 ib_link_width_admin[0x10];
7589 u8 ib_proto_admin[0x10];
7590
b4ff3a36 7591 u8 reserved_at_100[0x20];
e281682b
SM		 7592
7593 u8 eth_proto_oper[0x20];
7594
7595 u8 ib_link_width_oper[0x10];
7596 u8 ib_proto_oper[0x10];
7597
5b4793f8
EBE		 7598 u8 reserved_at_160[0x1c];
7599 u8 connector_type[0x4];
e281682b
SM		 7600
7601 u8 eth_proto_lp_advertise[0x20];
7602
b4ff3a36 7603 u8 reserved_at_1a0[0x60];
e281682b
SM		 7604};
7605
7d5e1423
SM		 7606struct mlx5_ifc_mlcr_reg_bits {
7607 u8 reserved_at_0[0x8];
7608 u8 local_port[0x8];
7609 u8 reserved_at_10[0x20];
7610
7611 u8 beacon_duration[0x10];
7612 u8 reserved_at_40[0x10];
7613
7614 u8 beacon_remain[0x10];
7615};
7616
e281682b 7617struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7618 u8 reserved_at_0[0x20];
e281682b
SM		 7619
7620 u8 algorithm_options[0x10];
b4ff3a36 7621 u8 reserved_at_30[0x4];
e281682b
SM		 7622 u8 repetitions_mode[0x4];
7623 u8 num_of_repetitions[0x8];
7624
7625 u8 grade_version[0x8];
7626 u8 height_grade_type[0x4];
7627 u8 phase_grade_type[0x4];
7628 u8 height_grade_weight[0x8];
7629 u8 phase_grade_weight[0x8];
7630
7631 u8 gisim_measure_bits[0x10];
7632 u8 adaptive_tap_measure_bits[0x10];
7633
7634 u8 ber_bath_high_error_threshold[0x10];
7635 u8 ber_bath_mid_error_threshold[0x10];
7636
7637 u8 ber_bath_low_error_threshold[0x10];
7638 u8 one_ratio_high_threshold[0x10];
7639
7640 u8 one_ratio_high_mid_threshold[0x10];
7641 u8 one_ratio_low_mid_threshold[0x10];
7642
7643 u8 one_ratio_low_threshold[0x10];
7644 u8 ndeo_error_threshold[0x10];
7645
7646 u8 mixer_offset_step_size[0x10];
b4ff3a36 7647 u8 reserved_at_110[0x8];
e281682b
SM		 7648 u8 mix90_phase_for_voltage_bath[0x8];
7649
7650 u8 mixer_offset_start[0x10];
7651 u8 mixer_offset_end[0x10];
7652
b4ff3a36 7653 u8 reserved_at_140[0x15];
e281682b
SM		 7654 u8 ber_test_time[0xb];
7655};
7656
7657struct mlx5_ifc_pspa_reg_bits {
7658 u8 swid[0x8];
7659 u8 local_port[0x8];
7660 u8 sub_port[0x8];
b4ff3a36 7661 u8 reserved_at_18[0x8];
e281682b 7662
b4ff3a36 7663 u8 reserved_at_20[0x20];
e281682b
SM		 7664};
7665
7666struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7667 u8 reserved_at_0[0x8];
e281682b 7668 u8 local_port[0x8];
b4ff3a36 7669 u8 reserved_at_10[0x5];
e281682b 7670 u8 prio[0x3];
b4ff3a36 7671 u8 reserved_at_18[0x6];
e281682b
SM		 7672 u8 mode[0x2];
7673
b4ff3a36 7674 u8 reserved_at_20[0x20];
e281682b 7675
b4ff3a36 7676 u8 reserved_at_40[0x10];
e281682b
SM		 7677 u8 min_threshold[0x10];
7678
b4ff3a36 7679 u8 reserved_at_60[0x10];
e281682b
SM		 7680 u8 max_threshold[0x10];
7681
b4ff3a36 7682 u8 reserved_at_80[0x10];
e281682b
SM		 7683 u8 mark_probability_denominator[0x10];
7684
b4ff3a36 7685 u8 reserved_at_a0[0x60];
e281682b
SM		 7686};
7687
7688struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7689 u8 reserved_at_0[0x8];
e281682b 7690 u8 local_port[0x8];
b4ff3a36 7691 u8 reserved_at_10[0x10];
e281682b 7692
b4ff3a36 7693 u8 reserved_at_20[0x60];
e281682b 7694
b4ff3a36 7695 u8 reserved_at_80[0x1c];
e281682b
SM		 7696 u8 wrps_admin[0x4];
7697
b4ff3a36 7698 u8 reserved_at_a0[0x1c];
e281682b
SM		 7699 u8 wrps_status[0x4];
7700
b4ff3a36 7701 u8 reserved_at_c0[0x8];
e281682b 7702 u8 up_threshold[0x8];
b4ff3a36 7703 u8 reserved_at_d0[0x8];
e281682b
SM		 7704 u8 down_threshold[0x8];
7705
b4ff3a36 7706 u8 reserved_at_e0[0x20];
e281682b 7707
b4ff3a36 7708 u8 reserved_at_100[0x1c];
e281682b
SM		 7709 u8 srps_admin[0x4];
7710
b4ff3a36 7711 u8 reserved_at_120[0x1c];
e281682b
SM		 7712 u8 srps_status[0x4];
7713
b4ff3a36 7714 u8 reserved_at_140[0x40];
e281682b
SM		 7715};
7716
7717struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7718 u8 reserved_at_0[0x8];
e281682b 7719 u8 local_port[0x8];
b4ff3a36 7720 u8 reserved_at_10[0x10];
e281682b 7721
b4ff3a36 7722 u8 reserved_at_20[0x8];
e281682b 7723 u8 lb_cap[0x8];
b4ff3a36 7724 u8 reserved_at_30[0x8];
e281682b
SM		 7725 u8 lb_en[0x8];
7726};
7727
7728struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7729 u8 reserved_at_0[0x8];
e281682b 7730 u8 local_port[0x8];
b4ff3a36 7731 u8 reserved_at_10[0x10];
e281682b 7732
b4ff3a36 7733 u8 reserved_at_20[0x20];
e281682b
SM		 7734
7735 u8 port_profile_mode[0x8];
7736 u8 static_port_profile[0x8];
7737 u8 active_port_profile[0x8];
b4ff3a36 7738 u8 reserved_at_58[0x8];
e281682b
SM		 7739
7740 u8 retransmission_active[0x8];
7741 u8 fec_mode_active[0x18];
7742
b4ff3a36 7743 u8 reserved_at_80[0x20];
e281682b
SM		 7744};
7745
7746struct mlx5_ifc_ppcnt_reg_bits {
7747 u8 swid[0x8];
7748 u8 local_port[0x8];
7749 u8 pnat[0x2];
b4ff3a36 7750 u8 reserved_at_12[0x8];
e281682b
SM		 7751 u8 grp[0x6];
7752
7753 u8 clr[0x1];
b4ff3a36 7754 u8 reserved_at_21[0x1c];
e281682b
SM		 7755 u8 prio_tc[0x3];
7756
7757 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7758};
7759
8ed1a630
GP		 7760struct mlx5_ifc_mpcnt_reg_bits {
7761 u8 reserved_at_0[0x8];
7762 u8 pcie_index[0x8];
7763 u8 reserved_at_10[0xa];
7764 u8 grp[0x6];
7765
7766 u8 clr[0x1];
7767 u8 reserved_at_21[0x1f];
7768
7769 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7770};
7771
e281682b 7772struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7773 u8 reserved_at_0[0x3];
e281682b 7774 u8 single_mac[0x1];
b4ff3a36 7775 u8 reserved_at_4[0x4];
e281682b
SM		 7776 u8 local_port[0x8];
7777 u8 mac_47_32[0x10];
7778
7779 u8 mac_31_0[0x20];
7780
b4ff3a36 7781 u8 reserved_at_40[0x40];
e281682b
SM		 7782};
7783
7784struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7785 u8 reserved_at_0[0x8];
e281682b 7786 u8 local_port[0x8];
b4ff3a36 7787 u8 reserved_at_10[0x10];
e281682b
SM		 7788
7789 u8 max_mtu[0x10];
b4ff3a36 7790 u8 reserved_at_30[0x10];
e281682b
SM		 7791
7792 u8 admin_mtu[0x10];
b4ff3a36 7793 u8 reserved_at_50[0x10];
e281682b
SM		 7794
7795 u8 oper_mtu[0x10];
b4ff3a36 7796 u8 reserved_at_70[0x10];
e281682b
SM		 7797};
7798
7799struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7800 u8 reserved_at_0[0x8];
e281682b 7801 u8 module[0x8];
b4ff3a36 7802 u8 reserved_at_10[0x10];
e281682b 7803
b4ff3a36 7804 u8 reserved_at_20[0x18];
e281682b
SM		 7805 u8 attenuation_5g[0x8];
7806
b4ff3a36 7807 u8 reserved_at_40[0x18];
e281682b
SM		 7808 u8 attenuation_7g[0x8];
7809
b4ff3a36 7810 u8 reserved_at_60[0x18];
e281682b
SM		 7811 u8 attenuation_12g[0x8];
7812};
7813
7814struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7815 u8 reserved_at_0[0x8];
e281682b 7816 u8 module[0x8];
b4ff3a36 7817 u8 reserved_at_10[0xc];
e281682b
SM		 7818 u8 module_status[0x4];
7819
b4ff3a36 7820 u8 reserved_at_20[0x60];
e281682b
SM		 7821};
7822
7823struct mlx5_ifc_pmpc_reg_bits {
7824 u8 module_state_updated[32][0x8];
7825};
7826
7827struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7828 u8 reserved_at_0[0x4];
e281682b
SM		 7829 u8 mlpn_status[0x4];
7830 u8 local_port[0x8];
b4ff3a36 7831 u8 reserved_at_10[0x10];
e281682b
SM		 7832
7833 u8 e[0x1];
b4ff3a36 7834 u8 reserved_at_21[0x1f];
e281682b
SM		 7835};
7836
7837struct mlx5_ifc_pmlp_reg_bits {
7838 u8 rxtx[0x1];
b4ff3a36 7839 u8 reserved_at_1[0x7];
e281682b 7840 u8 local_port[0x8];
b4ff3a36 7841 u8 reserved_at_10[0x8];
e281682b
SM		 7842 u8 width[0x8];
7843
7844 u8 lane0_module_mapping[0x20];
7845
7846 u8 lane1_module_mapping[0x20];
7847
7848 u8 lane2_module_mapping[0x20];
7849
7850 u8 lane3_module_mapping[0x20];
7851
b4ff3a36 7852 u8 reserved_at_a0[0x160];
e281682b
SM		 7853};
7854
7855struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7856 u8 reserved_at_0[0x8];
e281682b 7857 u8 module[0x8];
b4ff3a36 7858 u8 reserved_at_10[0x4];
e281682b 7859 u8 admin_status[0x4];
b4ff3a36 7860 u8 reserved_at_18[0x4];
e281682b
SM		 7861 u8 oper_status[0x4];
7862
7863 u8 ase[0x1];
7864 u8 ee[0x1];
b4ff3a36 7865 u8 reserved_at_22[0x1c];
e281682b
SM		 7866 u8 e[0x2];
7867
b4ff3a36 7868 u8 reserved_at_40[0x40];
e281682b
SM		 7869};
7870
7871struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7872 u8 reserved_at_0[0x4];
e281682b 7873 u8 profile_id[0xc];
b4ff3a36 7874 u8 reserved_at_10[0x4];
e281682b 7875 u8 proto_mask[0x4];
b4ff3a36 7876 u8 reserved_at_18[0x8];
e281682b 7877
b4ff3a36 7878 u8 reserved_at_20[0x10];
e281682b
SM		 7879 u8 lane_speed[0x10];
7880
b4ff3a36 7881 u8 reserved_at_40[0x17];
e281682b
SM		 7882 u8 lpbf[0x1];
7883 u8 fec_mode_policy[0x8];
7884
7885 u8 retransmission_capability[0x8];
7886 u8 fec_mode_capability[0x18];
7887
7888 u8 retransmission_support_admin[0x8];
7889 u8 fec_mode_support_admin[0x18];
7890
7891 u8 retransmission_request_admin[0x8];
7892 u8 fec_mode_request_admin[0x18];
7893
b4ff3a36 7894 u8 reserved_at_c0[0x80];
e281682b
SM		 7895};
7896
7897struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7898 u8 reserved_at_0[0x8];
e281682b 7899 u8 local_port[0x8];
b4ff3a36 7900 u8 reserved_at_10[0x8];
e281682b
SM		 7901 u8 ib_port[0x8];
7902
b4ff3a36 7903 u8 reserved_at_20[0x60];
e281682b
SM		 7904};
7905
7906struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7907 u8 reserved_at_0[0x8];
e281682b 7908 u8 local_port[0x8];
b4ff3a36 7909 u8 reserved_at_10[0xd];
e281682b
SM		 7910 u8 lbf_mode[0x3];
7911
b4ff3a36 7912 u8 reserved_at_20[0x20];
e281682b
SM		 7913};
7914
7915struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7916 u8 reserved_at_0[0x8];
e281682b 7917 u8 local_port[0x8];
b4ff3a36 7918 u8 reserved_at_10[0x10];
e281682b
SM		 7919
7920 u8 dic[0x1];
b4ff3a36 7921 u8 reserved_at_21[0x19];
e281682b 7922 u8 ipg[0x4];
b4ff3a36 7923 u8 reserved_at_3e[0x2];
e281682b
SM		 7924};
7925
7926struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7927 u8 reserved_at_0[0x8];
e281682b 7928 u8 local_port[0x8];
b4ff3a36 7929 u8 reserved_at_10[0x10];
e281682b 7930
b4ff3a36 7931 u8 reserved_at_20[0xe0];
e281682b
SM		 7932
7933 u8 port_filter[8][0x20];
7934
7935 u8 port_filter_update_en[8][0x20];
7936};
7937
7938struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7939 u8 reserved_at_0[0x8];
e281682b 7940 u8 local_port[0x8];
2afa609f
IK		 7941 u8 reserved_at_10[0xb];
7942 u8 ppan_mask_n[0x1];
7943 u8 minor_stall_mask[0x1];
7944 u8 critical_stall_mask[0x1];
7945 u8 reserved_at_1e[0x2];
e281682b
SM		 7946
7947 u8 ppan[0x4];
b4ff3a36 7948 u8 reserved_at_24[0x4];
e281682b 7949 u8 prio_mask_tx[0x8];
b4ff3a36 7950 u8 reserved_at_30[0x8];
e281682b
SM		 7951 u8 prio_mask_rx[0x8];
7952
7953 u8 pptx[0x1];
7954 u8 aptx[0x1];
2afa609f
IK		 7955 u8 pptx_mask_n[0x1];
7956 u8 reserved_at_43[0x5];
e281682b 7957 u8 pfctx[0x8];
b4ff3a36 7958 u8 reserved_at_50[0x10];
e281682b
SM		 7959
7960 u8 pprx[0x1];
7961 u8 aprx[0x1];
2afa609f
IK		 7962 u8 pprx_mask_n[0x1];
7963 u8 reserved_at_63[0x5];
e281682b 7964 u8 pfcrx[0x8];
b4ff3a36 7965 u8 reserved_at_70[0x10];
e281682b 7966
2afa609f
IK		 7967 u8 device_stall_minor_watermark[0x10];
7968 u8 device_stall_critical_watermark[0x10];
7969
7970 u8 reserved_at_a0[0x60];
e281682b
SM		 7971};
7972
7973struct mlx5_ifc_pelc_reg_bits {
7974 u8 op[0x4];
b4ff3a36 7975 u8 reserved_at_4[0x4];
e281682b 7976 u8 local_port[0x8];
b4ff3a36 7977 u8 reserved_at_10[0x10];
e281682b
SM		 7978
7979 u8 op_admin[0x8];
7980 u8 op_capability[0x8];
7981 u8 op_request[0x8];
7982 u8 op_active[0x8];
7983
7984 u8 admin[0x40];
7985
7986 u8 capability[0x40];
7987
7988 u8 request[0x40];
7989
7990 u8 active[0x40];
7991
b4ff3a36 7992 u8 reserved_at_140[0x80];
e281682b
SM		 7993};
7994
7995struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7996 u8 reserved_at_0[0x8];
e281682b 7997 u8 local_port[0x8];
b4ff3a36 7998 u8 reserved_at_10[0x10];
e281682b 7999
b4ff3a36 8000 u8 reserved_at_20[0xc];
e281682b 8001 u8 error_count[0x4];
b4ff3a36 8002 u8 reserved_at_30[0x10];
e281682b 8003
b4ff3a36 8004 u8 reserved_at_40[0xc];
e281682b 8005 u8 lane[0x4];
b4ff3a36 8006 u8 reserved_at_50[0x8];
e281682b
SM		 8007 u8 error_type[0x8];
8008};
8009
cfdcbcea 8010struct mlx5_ifc_pcam_enhanced_features_bits {
2fcb12df 8011 u8 reserved_at_0[0x76];
cfdcbcea 8012
2fcb12df
IK		 8013 u8 pfcc_mask[0x1];
8014 u8 reserved_at_77[0x4];
2dba0797 8015 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 8016 u8 ptys_connector_type[0x1];
8017 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 8018 u8 ppcnt_discard_group[0x1];
8019 u8 ppcnt_statistical_group[0x1];
8020};
8021
8022struct mlx5_ifc_pcam_reg_bits {
8023 u8 reserved_at_0[0x8];
8024 u8 feature_group[0x8];
8025 u8 reserved_at_10[0x8];
8026 u8 access_reg_group[0x8];
8027
8028 u8 reserved_at_20[0x20];
8029
8030 union {
8031 u8 reserved_at_0[0x80];
8032 } port_access_reg_cap_mask;
8033
8034 u8 reserved_at_c0[0x80];
8035
8036 union {
8037 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8038 u8 reserved_at_0[0x80];
8039 } feature_cap_mask;
8040
8041 u8 reserved_at_1c0[0xc0];
8042};
8043
8044struct mlx5_ifc_mcam_enhanced_features_bits {
5405fa26
GP		 8045 u8 reserved_at_0[0x7b];
8046 u8 pcie_outbound_stalled[0x1];
efae7f78 8047 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 8048 u8 mtpps_enh_out_per_adj[0x1];
8049 u8 mtpps_fs[0x1];
cfdcbcea
GP		 8050 u8 pcie_performance_group[0x1];
8051};
8052
0ab87743
OG		 8053struct mlx5_ifc_mcam_access_reg_bits {
8054 u8 reserved_at_0[0x1c];
8055 u8 mcda[0x1];
8056 u8 mcc[0x1];
8057 u8 mcqi[0x1];
8058 u8 reserved_at_1f[0x1];
8059
8060 u8 regs_95_to_64[0x20];
8061 u8 regs_63_to_32[0x20];
8062 u8 regs_31_to_0[0x20];
8063};
8064
cfdcbcea
GP		 8065struct mlx5_ifc_mcam_reg_bits {
8066 u8 reserved_at_0[0x8];
8067 u8 feature_group[0x8];
8068 u8 reserved_at_10[0x8];
8069 u8 access_reg_group[0x8];
8070
8071 u8 reserved_at_20[0x20];
8072
8073 union {
0ab87743 8074 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 8075 u8 reserved_at_0[0x80];
8076 } mng_access_reg_cap_mask;
8077
8078 u8 reserved_at_c0[0x80];
8079
8080 union {
8081 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8082 u8 reserved_at_0[0x80];
8083 } mng_feature_cap_mask;
8084
8085 u8 reserved_at_1c0[0x80];
8086};
8087
c02762eb
HN		 8088struct mlx5_ifc_qcam_access_reg_cap_mask {
8089 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8090 u8 qpdpm[0x1];
8091 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8092 u8 qdpm[0x1];
8093 u8 qpts[0x1];
8094 u8 qcap[0x1];
8095 u8 qcam_access_reg_cap_mask_0[0x1];
8096};
8097
8098struct mlx5_ifc_qcam_qos_feature_cap_mask {
8099 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8100 u8 qpts_trust_both[0x1];
8101};
8102
8103struct mlx5_ifc_qcam_reg_bits {
8104 u8 reserved_at_0[0x8];
8105 u8 feature_group[0x8];
8106 u8 reserved_at_10[0x8];
8107 u8 access_reg_group[0x8];
8108 u8 reserved_at_20[0x20];
8109
8110 union {
8111 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8112 u8 reserved_at_0[0x80];
8113 } qos_access_reg_cap_mask;
8114
8115 u8 reserved_at_c0[0x80];
8116
8117 union {
8118 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8119 u8 reserved_at_0[0x80];
8120 } qos_feature_cap_mask;
8121
8122 u8 reserved_at_1c0[0x80];
8123};
8124
e281682b 8125struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 8126 u8 reserved_at_0[0x8];
e281682b 8127 u8 local_port[0x8];
b4ff3a36 8128 u8 reserved_at_10[0x10];
e281682b
SM		 8129
8130 u8 port_capability_mask[4][0x20];
8131};
8132
8133struct mlx5_ifc_paos_reg_bits {
8134 u8 swid[0x8];
8135 u8 local_port[0x8];
b4ff3a36 8136 u8 reserved_at_10[0x4];
e281682b 8137 u8 admin_status[0x4];
b4ff3a36 8138 u8 reserved_at_18[0x4];
e281682b
SM		 8139 u8 oper_status[0x4];
8140
8141 u8 ase[0x1];
8142 u8 ee[0x1];
b4ff3a36 8143 u8 reserved_at_22[0x1c];
e281682b
SM		 8144 u8 e[0x2];
8145
b4ff3a36 8146 u8 reserved_at_40[0x40];
e281682b
SM		 8147};
8148
8149struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 8150 u8 reserved_at_0[0x8];
e281682b 8151 u8 opamp_group[0x8];
b4ff3a36 8152 u8 reserved_at_10[0xc];
e281682b
SM		 8153 u8 opamp_group_type[0x4];
8154
8155 u8 start_index[0x10];
b4ff3a36 8156 u8 reserved_at_30[0x4];
e281682b
SM		 8157 u8 num_of_indices[0xc];
8158
8159 u8 index_data[18][0x10];
8160};
8161
7d5e1423
SM		 8162struct mlx5_ifc_pcmr_reg_bits {
8163 u8 reserved_at_0[0x8];
8164 u8 local_port[0x8];
8165 u8 reserved_at_10[0x2e];
8166 u8 fcs_cap[0x1];
8167 u8 reserved_at_3f[0x1f];
8168 u8 fcs_chk[0x1];
8169 u8 reserved_at_5f[0x1];
8170};
8171
e281682b 8172struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 8173 u8 reserved_at_0[0x6];
e281682b 8174 u8 rx_lane[0x2];
b4ff3a36 8175 u8 reserved_at_8[0x6];
e281682b 8176 u8 tx_lane[0x2];
b4ff3a36 8177 u8 reserved_at_10[0x8];
e281682b
SM		 8178 u8 module[0x8];
8179};
8180
8181struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8182 u8 reserved_at_0[0x6];
e281682b
SM		 8183 u8 lossy[0x1];
8184 u8 epsb[0x1];
b4ff3a36 8185 u8 reserved_at_8[0xc];
e281682b
SM		 8186 u8 size[0xc];
8187
8188 u8 xoff_threshold[0x10];
8189 u8 xon_threshold[0x10];
8190};
8191
8192struct mlx5_ifc_set_node_in_bits {
8193 u8 node_description[64][0x8];
8194};
8195
8196struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8197 u8 reserved_at_0[0x18];
e281682b
SM		 8198 u8 power_settings_level[0x8];
8199
b4ff3a36 8200 u8 reserved_at_20[0x60];
e281682b
SM		 8201};
8202
8203struct mlx5_ifc_register_host_endianness_bits {
8204 u8 he[0x1];
b4ff3a36 8205 u8 reserved_at_1[0x1f];
e281682b 8206
b4ff3a36 8207 u8 reserved_at_20[0x60];
e281682b
SM		 8208};
8209
8210struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8211 u8 reserved_at_0[0x20];
e281682b
SM		 8212
8213 u8 mkey[0x20];
8214
8215 u8 addressh_63_32[0x20];
8216
8217 u8 addressl_31_0[0x20];
8218};
8219
8220struct mlx5_ifc_ud_adrs_vector_bits {
8221 u8 dc_key[0x40];
8222
8223 u8 ext[0x1];
b4ff3a36 8224 u8 reserved_at_41[0x7];
e281682b
SM		 8225 u8 destination_qp_dct[0x18];
8226
8227 u8 static_rate[0x4];
8228 u8 sl_eth_prio[0x4];
8229 u8 fl[0x1];
8230 u8 mlid[0x7];
8231 u8 rlid_udp_sport[0x10];
8232
b4ff3a36 8233 u8 reserved_at_80[0x20];
e281682b
SM		 8234
8235 u8 rmac_47_16[0x20];
8236
8237 u8 rmac_15_0[0x10];
8238 u8 tclass[0x8];
8239 u8 hop_limit[0x8];
8240
b4ff3a36 8241 u8 reserved_at_e0[0x1];
e281682b 8242 u8 grh[0x1];
b4ff3a36 8243 u8 reserved_at_e2[0x2];
e281682b
SM		 8244 u8 src_addr_index[0x8];
8245 u8 flow_label[0x14];
8246
8247 u8 rgid_rip[16][0x8];
8248};
8249
8250struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8251 u8 reserved_at_0[0x10];
e281682b
SM		 8252 u8 function_id[0x10];
8253
8254 u8 num_pages[0x20];
8255
b4ff3a36 8256 u8 reserved_at_40[0xa0];
e281682b
SM		 8257};
8258
8259struct mlx5_ifc_eqe_bits {
b4ff3a36 8260 u8 reserved_at_0[0x8];
e281682b 8261 u8 event_type[0x8];
b4ff3a36 8262 u8 reserved_at_10[0x8];
e281682b
SM		 8263 u8 event_sub_type[0x8];
8264
b4ff3a36 8265 u8 reserved_at_20[0xe0];
e281682b
SM		 8266
8267 union mlx5_ifc_event_auto_bits event_data;
8268
b4ff3a36 8269 u8 reserved_at_1e0[0x10];
e281682b 8270 u8 signature[0x8];
b4ff3a36 8271 u8 reserved_at_1f8[0x7];
e281682b
SM		 8272 u8 owner[0x1];
8273};
8274
8275enum {
8276 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8277};
8278
8279struct mlx5_ifc_cmd_queue_entry_bits {
8280 u8 type[0x8];
b4ff3a36 8281 u8 reserved_at_8[0x18];
e281682b
SM		 8282
8283 u8 input_length[0x20];
8284
8285 u8 input_mailbox_pointer_63_32[0x20];
8286
8287 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8288 u8 reserved_at_77[0x9];
e281682b
SM		 8289
8290 u8 command_input_inline_data[16][0x8];
8291
8292 u8 command_output_inline_data[16][0x8];
8293
8294 u8 output_mailbox_pointer_63_32[0x20];
8295
8296 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8297 u8 reserved_at_1b7[0x9];
e281682b
SM		 8298
8299 u8 output_length[0x20];
8300
8301 u8 token[0x8];
8302 u8 signature[0x8];
b4ff3a36 8303 u8 reserved_at_1f0[0x8];
e281682b
SM		 8304 u8 status[0x7];
8305 u8 ownership[0x1];
8306};
8307
8308struct mlx5_ifc_cmd_out_bits {
8309 u8 status[0x8];
b4ff3a36 8310 u8 reserved_at_8[0x18];
e281682b
SM		 8311
8312 u8 syndrome[0x20];
8313
8314 u8 command_output[0x20];
8315};
8316
8317struct mlx5_ifc_cmd_in_bits {
8318 u8 opcode[0x10];
b4ff3a36 8319 u8 reserved_at_10[0x10];
e281682b 8320
b4ff3a36 8321 u8 reserved_at_20[0x10];
e281682b
SM		 8322 u8 op_mod[0x10];
8323
8324 u8 command[0][0x20];
8325};
8326
8327struct mlx5_ifc_cmd_if_box_bits {
8328 u8 mailbox_data[512][0x8];
8329
b4ff3a36 8330 u8 reserved_at_1000[0x180];
e281682b
SM		 8331
8332 u8 next_pointer_63_32[0x20];
8333
8334 u8 next_pointer_31_10[0x16];
b4ff3a36 8335 u8 reserved_at_11b6[0xa];
e281682b
SM		 8336
8337 u8 block_number[0x20];
8338
b4ff3a36 8339 u8 reserved_at_11e0[0x8];
e281682b
SM		 8340 u8 token[0x8];
8341 u8 ctrl_signature[0x8];
8342 u8 signature[0x8];
8343};
8344
8345struct mlx5_ifc_mtt_bits {
8346 u8 ptag_63_32[0x20];
8347
8348 u8 ptag_31_8[0x18];
b4ff3a36 8349 u8 reserved_at_38[0x6];
e281682b
SM		 8350 u8 wr_en[0x1];
8351 u8 rd_en[0x1];
8352};
8353
928cfe87
TT		 8354struct mlx5_ifc_query_wol_rol_out_bits {
8355 u8 status[0x8];
8356 u8 reserved_at_8[0x18];
8357
8358 u8 syndrome[0x20];
8359
8360 u8 reserved_at_40[0x10];
8361 u8 rol_mode[0x8];
8362 u8 wol_mode[0x8];
8363
8364 u8 reserved_at_60[0x20];
8365};
8366
8367struct mlx5_ifc_query_wol_rol_in_bits {
8368 u8 opcode[0x10];
8369 u8 reserved_at_10[0x10];
8370
8371 u8 reserved_at_20[0x10];
8372 u8 op_mod[0x10];
8373
8374 u8 reserved_at_40[0x40];
8375};
8376
8377struct mlx5_ifc_set_wol_rol_out_bits {
8378 u8 status[0x8];
8379 u8 reserved_at_8[0x18];
8380
8381 u8 syndrome[0x20];
8382
8383 u8 reserved_at_40[0x40];
8384};
8385
8386struct mlx5_ifc_set_wol_rol_in_bits {
8387 u8 opcode[0x10];
8388 u8 reserved_at_10[0x10];
8389
8390 u8 reserved_at_20[0x10];
8391 u8 op_mod[0x10];
8392
8393 u8 rol_mode_valid[0x1];
8394 u8 wol_mode_valid[0x1];
8395 u8 reserved_at_42[0xe];
8396 u8 rol_mode[0x8];
8397 u8 wol_mode[0x8];
8398
8399 u8 reserved_at_60[0x20];
8400};
8401
e281682b
SM		 8402enum {
8403 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8404 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8405 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8406};
8407
8408enum {
8409 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8410 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8411 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8412};
8413
8414enum {
8415 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8416 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8417 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8426};
8427
8428struct mlx5_ifc_initial_seg_bits {
8429 u8 fw_rev_minor[0x10];
8430 u8 fw_rev_major[0x10];
8431
8432 u8 cmd_interface_rev[0x10];
8433 u8 fw_rev_subminor[0x10];
8434
b4ff3a36 8435 u8 reserved_at_40[0x40];
e281682b
SM		 8436
8437 u8 cmdq_phy_addr_63_32[0x20];
8438
8439 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8440 u8 reserved_at_b4[0x2];
e281682b
SM		 8441 u8 nic_interface[0x2];
8442 u8 log_cmdq_size[0x4];
8443 u8 log_cmdq_stride[0x4];
8444
8445 u8 command_doorbell_vector[0x20];
8446
b4ff3a36 8447 u8 reserved_at_e0[0xf00];
e281682b
SM		 8448
8449 u8 initializing[0x1];
b4ff3a36 8450 u8 reserved_at_fe1[0x4];
e281682b 8451 u8 nic_interface_supported[0x3];
b4ff3a36 8452 u8 reserved_at_fe8[0x18];
e281682b
SM		 8453
8454 struct mlx5_ifc_health_buffer_bits health_buffer;
8455
8456 u8 no_dram_nic_offset[0x20];
8457
b4ff3a36 8458 u8 reserved_at_1220[0x6e40];
e281682b 8459
b4ff3a36 8460 u8 reserved_at_8060[0x1f];
e281682b
SM		 8461 u8 clear_int[0x1];
8462
8463 u8 health_syndrome[0x8];
8464 u8 health_counter[0x18];
8465
b4ff3a36 8466 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8467};
8468
f9a1ef72
EE		 8469struct mlx5_ifc_mtpps_reg_bits {
8470 u8 reserved_at_0[0xc];
8471 u8 cap_number_of_pps_pins[0x4];
8472 u8 reserved_at_10[0x4];
8473 u8 cap_max_num_of_pps_in_pins[0x4];
8474 u8 reserved_at_18[0x4];
8475 u8 cap_max_num_of_pps_out_pins[0x4];
8476
8477 u8 reserved_at_20[0x24];
8478 u8 cap_pin_3_mode[0x4];
8479 u8 reserved_at_48[0x4];
8480 u8 cap_pin_2_mode[0x4];
8481 u8 reserved_at_50[0x4];
8482 u8 cap_pin_1_mode[0x4];
8483 u8 reserved_at_58[0x4];
8484 u8 cap_pin_0_mode[0x4];
8485
8486 u8 reserved_at_60[0x4];
8487 u8 cap_pin_7_mode[0x4];
8488 u8 reserved_at_68[0x4];
8489 u8 cap_pin_6_mode[0x4];
8490 u8 reserved_at_70[0x4];
8491 u8 cap_pin_5_mode[0x4];
8492 u8 reserved_at_78[0x4];
8493 u8 cap_pin_4_mode[0x4];
8494
fa367688
EE		 8495 u8 field_select[0x20];
8496 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8497
8498 u8 enable[0x1];
8499 u8 reserved_at_101[0xb];
8500 u8 pattern[0x4];
8501 u8 reserved_at_110[0x4];
8502 u8 pin_mode[0x4];
8503 u8 pin[0x8];
8504
8505 u8 reserved_at_120[0x20];
8506
8507 u8 time_stamp[0x40];
8508
8509 u8 out_pulse_duration[0x10];
8510 u8 out_periodic_adjustment[0x10];
fa367688 8511 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8512
fa367688 8513 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8514};
8515
8516struct mlx5_ifc_mtppse_reg_bits {
8517 u8 reserved_at_0[0x18];
8518 u8 pin[0x8];
8519 u8 event_arm[0x1];
8520 u8 reserved_at_21[0x1b];
8521 u8 event_generation_mode[0x4];
8522 u8 reserved_at_40[0x40];
8523};
8524
47176289
OG		 8525struct mlx5_ifc_mcqi_cap_bits {
8526 u8 supported_info_bitmask[0x20];
8527
8528 u8 component_size[0x20];
8529
8530 u8 max_component_size[0x20];
8531
8532 u8 log_mcda_word_size[0x4];
8533 u8 reserved_at_64[0xc];
8534 u8 mcda_max_write_size[0x10];
8535
8536 u8 rd_en[0x1];
8537 u8 reserved_at_81[0x1];
8538 u8 match_chip_id[0x1];
8539 u8 match_psid[0x1];
8540 u8 check_user_timestamp[0x1];
8541 u8 match_base_guid_mac[0x1];
8542 u8 reserved_at_86[0x1a];
8543};
8544
8545struct mlx5_ifc_mcqi_reg_bits {
8546 u8 read_pending_component[0x1];
8547 u8 reserved_at_1[0xf];
8548 u8 component_index[0x10];
8549
8550 u8 reserved_at_20[0x20];
8551
8552 u8 reserved_at_40[0x1b];
8553 u8 info_type[0x5];
8554
8555 u8 info_size[0x20];
8556
8557 u8 offset[0x20];
8558
8559 u8 reserved_at_a0[0x10];
8560 u8 data_size[0x10];
8561
8562 u8 data[0][0x20];
8563};
8564
8565struct mlx5_ifc_mcc_reg_bits {
8566 u8 reserved_at_0[0x4];
8567 u8 time_elapsed_since_last_cmd[0xc];
8568 u8 reserved_at_10[0x8];
8569 u8 instruction[0x8];
8570
8571 u8 reserved_at_20[0x10];
8572 u8 component_index[0x10];
8573
8574 u8 reserved_at_40[0x8];
8575 u8 update_handle[0x18];
8576
8577 u8 handle_owner_type[0x4];
8578 u8 handle_owner_host_id[0x4];
8579 u8 reserved_at_68[0x1];
8580 u8 control_progress[0x7];
8581 u8 error_code[0x8];
8582 u8 reserved_at_78[0x4];
8583 u8 control_state[0x4];
8584
8585 u8 component_size[0x20];
8586
8587 u8 reserved_at_a0[0x60];
8588};
8589
8590struct mlx5_ifc_mcda_reg_bits {
8591 u8 reserved_at_0[0x8];
8592 u8 update_handle[0x18];
8593
8594 u8 offset[0x20];
8595
8596 u8 reserved_at_40[0x10];
8597 u8 size[0x10];
8598
8599 u8 reserved_at_60[0x20];
8600
8601 u8 data[0][0x20];
8602};
8603
e281682b
SM		 8604union mlx5_ifc_ports_control_registers_document_bits {
8605 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8606 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8607 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8608 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8609 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8610 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8611 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8612 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8613 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8614 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8615 struct mlx5_ifc_paos_reg_bits paos_reg;
8616 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8617 struct mlx5_ifc_peir_reg_bits peir_reg;
8618 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8619 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8620 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8621 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8622 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8623 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8624 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8625 struct mlx5_ifc_plib_reg_bits plib_reg;
8626 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8627 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8628 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8629 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8630 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8631 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8632 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8633 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8634 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8635 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8636 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8637 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8638 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8639 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8640 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8641 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8642 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8643 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8644 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8645 struct mlx5_ifc_pude_reg_bits pude_reg;
8646 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8647 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8648 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8649 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8650 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8651 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8652 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8653 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8654 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8655 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8656 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8657 u8 reserved_at_0[0x60e0];
e281682b
SM		 8658};
8659
8660union mlx5_ifc_debug_enhancements_document_bits {
8661 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8662 u8 reserved_at_0[0x200];
e281682b
SM		 8663};
8664
8665union mlx5_ifc_uplink_pci_interface_document_bits {
8666 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8667 u8 reserved_at_0[0x20060];
b775516b
EC		 8668};
8669
2cc43b49
MG		 8670struct mlx5_ifc_set_flow_table_root_out_bits {
8671 u8 status[0x8];
b4ff3a36 8672 u8 reserved_at_8[0x18];
2cc43b49
MG		 8673
8674 u8 syndrome[0x20];
8675
b4ff3a36 8676 u8 reserved_at_40[0x40];
2cc43b49
MG		 8677};
8678
8679struct mlx5_ifc_set_flow_table_root_in_bits {
8680 u8 opcode[0x10];
b4ff3a36 8681 u8 reserved_at_10[0x10];
2cc43b49 8682
b4ff3a36 8683 u8 reserved_at_20[0x10];
2cc43b49
MG		 8684 u8 op_mod[0x10];
8685
7d5e1423
SM		 8686 u8 other_vport[0x1];
8687 u8 reserved_at_41[0xf];
8688 u8 vport_number[0x10];
8689
8690 u8 reserved_at_60[0x20];
2cc43b49
MG		 8691
8692 u8 table_type[0x8];
b4ff3a36 8693 u8 reserved_at_88[0x18];
2cc43b49 8694
b4ff3a36 8695 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8696 u8 table_id[0x18];
8697
500a3d0d
ES		 8698 u8 reserved_at_c0[0x8];
8699 u8 underlay_qpn[0x18];
8700 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8701};
8702
34a40e68 8703enum {
84df61eb
AH		 8704 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8705 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8706};
8707
8708struct mlx5_ifc_modify_flow_table_out_bits {
8709 u8 status[0x8];
b4ff3a36 8710 u8 reserved_at_8[0x18];
34a40e68
MG		 8711
8712 u8 syndrome[0x20];
8713
b4ff3a36 8714 u8 reserved_at_40[0x40];
34a40e68
MG		 8715};
8716
8717struct mlx5_ifc_modify_flow_table_in_bits {
8718 u8 opcode[0x10];
b4ff3a36 8719 u8 reserved_at_10[0x10];
34a40e68 8720
b4ff3a36 8721 u8 reserved_at_20[0x10];
34a40e68
MG		 8722 u8 op_mod[0x10];
8723
7d5e1423
SM		 8724 u8 other_vport[0x1];
8725 u8 reserved_at_41[0xf];
8726 u8 vport_number[0x10];
34a40e68 8727
b4ff3a36 8728 u8 reserved_at_60[0x10];
34a40e68
MG		 8729 u8 modify_field_select[0x10];
8730
8731 u8 table_type[0x8];
b4ff3a36 8732 u8 reserved_at_88[0x18];
34a40e68 8733
b4ff3a36 8734 u8 reserved_at_a0[0x8];
34a40e68
MG		 8735 u8 table_id[0x18];
8736
0c90e9c6 8737 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8738};
8739
4f3961ee
SM		 8740struct mlx5_ifc_ets_tcn_config_reg_bits {
8741 u8 g[0x1];
8742 u8 b[0x1];
8743 u8 r[0x1];
8744 u8 reserved_at_3[0x9];
8745 u8 group[0x4];
8746 u8 reserved_at_10[0x9];
8747 u8 bw_allocation[0x7];
8748
8749 u8 reserved_at_20[0xc];
8750 u8 max_bw_units[0x4];
8751 u8 reserved_at_30[0x8];
8752 u8 max_bw_value[0x8];
8753};
8754
8755struct mlx5_ifc_ets_global_config_reg_bits {
8756 u8 reserved_at_0[0x2];
8757 u8 r[0x1];
8758 u8 reserved_at_3[0x1d];
8759
8760 u8 reserved_at_20[0xc];
8761 u8 max_bw_units[0x4];
8762 u8 reserved_at_30[0x8];
8763 u8 max_bw_value[0x8];
8764};
8765
8766struct mlx5_ifc_qetc_reg_bits {
8767 u8 reserved_at_0[0x8];
8768 u8 port_number[0x8];
8769 u8 reserved_at_10[0x30];
8770
8771 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8772 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8773};
8774
415a64aa
HN		 8775struct mlx5_ifc_qpdpm_dscp_reg_bits {
8776 u8 e[0x1];
8777 u8 reserved_at_01[0x0b];
8778 u8 prio[0x04];
8779};
8780
8781struct mlx5_ifc_qpdpm_reg_bits {
8782 u8 reserved_at_0[0x8];
8783 u8 local_port[0x8];
8784 u8 reserved_at_10[0x10];
8785 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8786};
8787
8788struct mlx5_ifc_qpts_reg_bits {
8789 u8 reserved_at_0[0x8];
8790 u8 local_port[0x8];
8791 u8 reserved_at_10[0x2d];
8792 u8 trust_state[0x3];
8793};
8794
4f3961ee
SM		 8795struct mlx5_ifc_qtct_reg_bits {
8796 u8 reserved_at_0[0x8];
8797 u8 port_number[0x8];
8798 u8 reserved_at_10[0xd];
8799 u8 prio[0x3];
8800
8801 u8 reserved_at_20[0x1d];
8802 u8 tclass[0x3];
8803};
8804
7d5e1423
SM		 8805struct mlx5_ifc_mcia_reg_bits {
8806 u8 l[0x1];
8807 u8 reserved_at_1[0x7];
8808 u8 module[0x8];
8809 u8 reserved_at_10[0x8];
8810 u8 status[0x8];
8811
8812 u8 i2c_device_address[0x8];
8813 u8 page_number[0x8];
8814 u8 device_address[0x10];
8815
8816 u8 reserved_at_40[0x10];
8817 u8 size[0x10];
8818
8819 u8 reserved_at_60[0x20];
8820
8821 u8 dword_0[0x20];
8822 u8 dword_1[0x20];
8823 u8 dword_2[0x20];
8824 u8 dword_3[0x20];
8825 u8 dword_4[0x20];
8826 u8 dword_5[0x20];
8827 u8 dword_6[0x20];
8828 u8 dword_7[0x20];
8829 u8 dword_8[0x20];
8830 u8 dword_9[0x20];
8831 u8 dword_10[0x20];
8832 u8 dword_11[0x20];
8833};
8834
7486216b
SM		 8835struct mlx5_ifc_dcbx_param_bits {
8836 u8 dcbx_cee_cap[0x1];
8837 u8 dcbx_ieee_cap[0x1];
8838 u8 dcbx_standby_cap[0x1];
8839 u8 reserved_at_0[0x5];
8840 u8 port_number[0x8];
8841 u8 reserved_at_10[0xa];
8842 u8 max_application_table_size[6];
8843 u8 reserved_at_20[0x15];
8844 u8 version_oper[0x3];
8845 u8 reserved_at_38[5];
8846 u8 version_admin[0x3];
8847 u8 willing_admin[0x1];
8848 u8 reserved_at_41[0x3];
8849 u8 pfc_cap_oper[0x4];
8850 u8 reserved_at_48[0x4];
8851 u8 pfc_cap_admin[0x4];
8852 u8 reserved_at_50[0x4];
8853 u8 num_of_tc_oper[0x4];
8854 u8 reserved_at_58[0x4];
8855 u8 num_of_tc_admin[0x4];
8856 u8 remote_willing[0x1];
8857 u8 reserved_at_61[3];
8858 u8 remote_pfc_cap[4];
8859 u8 reserved_at_68[0x14];
8860 u8 remote_num_of_tc[0x4];
8861 u8 reserved_at_80[0x18];
8862 u8 error[0x8];
8863 u8 reserved_at_a0[0x160];
8864};
84df61eb
AH		 8865
8866struct mlx5_ifc_lagc_bits {
8867 u8 reserved_at_0[0x1d];
8868 u8 lag_state[0x3];
8869
8870 u8 reserved_at_20[0x14];
8871 u8 tx_remap_affinity_2[0x4];
8872 u8 reserved_at_38[0x4];
8873 u8 tx_remap_affinity_1[0x4];
8874};
8875
8876struct mlx5_ifc_create_lag_out_bits {
8877 u8 status[0x8];
8878 u8 reserved_at_8[0x18];
8879
8880 u8 syndrome[0x20];
8881
8882 u8 reserved_at_40[0x40];
8883};
8884
8885struct mlx5_ifc_create_lag_in_bits {
8886 u8 opcode[0x10];
8887 u8 reserved_at_10[0x10];
8888
8889 u8 reserved_at_20[0x10];
8890 u8 op_mod[0x10];
8891
8892 struct mlx5_ifc_lagc_bits ctx;
8893};
8894
8895struct mlx5_ifc_modify_lag_out_bits {
8896 u8 status[0x8];
8897 u8 reserved_at_8[0x18];
8898
8899 u8 syndrome[0x20];
8900
8901 u8 reserved_at_40[0x40];
8902};
8903
8904struct mlx5_ifc_modify_lag_in_bits {
8905 u8 opcode[0x10];
8906 u8 reserved_at_10[0x10];
8907
8908 u8 reserved_at_20[0x10];
8909 u8 op_mod[0x10];
8910
8911 u8 reserved_at_40[0x20];
8912 u8 field_select[0x20];
8913
8914 struct mlx5_ifc_lagc_bits ctx;
8915};
8916
8917struct mlx5_ifc_query_lag_out_bits {
8918 u8 status[0x8];
8919 u8 reserved_at_8[0x18];
8920
8921 u8 syndrome[0x20];
8922
8923 u8 reserved_at_40[0x40];
8924
8925 struct mlx5_ifc_lagc_bits ctx;
8926};
8927
8928struct mlx5_ifc_query_lag_in_bits {
8929 u8 opcode[0x10];
8930 u8 reserved_at_10[0x10];
8931
8932 u8 reserved_at_20[0x10];
8933 u8 op_mod[0x10];
8934
8935 u8 reserved_at_40[0x40];
8936};
8937
8938struct mlx5_ifc_destroy_lag_out_bits {
8939 u8 status[0x8];
8940 u8 reserved_at_8[0x18];
8941
8942 u8 syndrome[0x20];
8943
8944 u8 reserved_at_40[0x40];
8945};
8946
8947struct mlx5_ifc_destroy_lag_in_bits {
8948 u8 opcode[0x10];
8949 u8 reserved_at_10[0x10];
8950
8951 u8 reserved_at_20[0x10];
8952 u8 op_mod[0x10];
8953
8954 u8 reserved_at_40[0x40];
8955};
8956
8957struct mlx5_ifc_create_vport_lag_out_bits {
8958 u8 status[0x8];
8959 u8 reserved_at_8[0x18];
8960
8961 u8 syndrome[0x20];
8962
8963 u8 reserved_at_40[0x40];
8964};
8965
8966struct mlx5_ifc_create_vport_lag_in_bits {
8967 u8 opcode[0x10];
8968 u8 reserved_at_10[0x10];
8969
8970 u8 reserved_at_20[0x10];
8971 u8 op_mod[0x10];
8972
8973 u8 reserved_at_40[0x40];
8974};
8975
8976struct mlx5_ifc_destroy_vport_lag_out_bits {
8977 u8 status[0x8];
8978 u8 reserved_at_8[0x18];
8979
8980 u8 syndrome[0x20];
8981
8982 u8 reserved_at_40[0x40];
8983};
8984
8985struct mlx5_ifc_destroy_vport_lag_in_bits {
8986 u8 opcode[0x10];
8987 u8 reserved_at_10[0x10];
8988
8989 u8 reserved_at_20[0x10];
8990 u8 op_mod[0x10];
8991
8992 u8 reserved_at_40[0x40];
8993};
8994
24da0016
AL		 8995struct mlx5_ifc_alloc_memic_in_bits {
8996 u8 opcode[0x10];
8997 u8 reserved_at_10[0x10];
8998
8999 u8 reserved_at_20[0x10];
9000 u8 op_mod[0x10];
9001
9002 u8 reserved_at_30[0x20];
9003
9004 u8 reserved_at_40[0x18];
9005 u8 log_memic_addr_alignment[0x8];
9006
9007 u8 range_start_addr[0x40];
9008
9009 u8 range_size[0x20];
9010
9011 u8 memic_size[0x20];
9012};
9013
9014struct mlx5_ifc_alloc_memic_out_bits {
9015 u8 status[0x8];
9016 u8 reserved_at_8[0x18];
9017
9018 u8 syndrome[0x20];
9019
9020 u8 memic_start_addr[0x40];
9021};
9022
9023struct mlx5_ifc_dealloc_memic_in_bits {
9024 u8 opcode[0x10];
9025 u8 reserved_at_10[0x10];
9026
9027 u8 reserved_at_20[0x10];
9028 u8 op_mod[0x10];
9029
9030 u8 reserved_at_40[0x40];
9031
9032 u8 memic_start_addr[0x40];
9033
9034 u8 memic_size[0x20];
9035
9036 u8 reserved_at_e0[0x20];
9037};
9038
9039struct mlx5_ifc_dealloc_memic_out_bits {
9040 u8 status[0x8];
9041 u8 reserved_at_8[0x18];
9042
9043 u8 syndrome[0x20];
9044
9045 u8 reserved_at_40[0x40];
9046};
9047
d29b796a 9048#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)