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Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox...
[linux-block.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
1f0cf89b 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
e281682b
SM		 64};
65
f91e6d89
EBE		 66enum {
67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
46861e3e 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
f91e6d89 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
59e9e8e4 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
8d1ac895 71 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25,
f91e6d89
EBE		 72};
73
38b7ca92 74enum {
2acc7957 75 MLX5_SHARED_RESOURCE_UID = 0xffff,
38b7ca92
YH		 76};
77
9fba2b9b
AL		 78enum {
79 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
80};
81
82enum {
83 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
b169e64a 84 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90fbca59 85 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
8385c51f 86 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
b169e64a
YK		 87};
88
89enum {
90 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
8a06a79b 91 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
1892a3d4 92 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
e7e2519e 93 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
a1be74c5 94 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
e4075c44
YH		 95 MLX5_OBJ_TYPE_MKEY = 0xff01,
96 MLX5_OBJ_TYPE_QP = 0xff02,
97 MLX5_OBJ_TYPE_PSV = 0xff03,
98 MLX5_OBJ_TYPE_RMP = 0xff04,
99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
100 MLX5_OBJ_TYPE_RQ = 0xff06,
101 MLX5_OBJ_TYPE_SQ = 0xff07,
102 MLX5_OBJ_TYPE_TIR = 0xff08,
103 MLX5_OBJ_TYPE_TIS = 0xff09,
104 MLX5_OBJ_TYPE_DCT = 0xff0a,
105 MLX5_OBJ_TYPE_XRQ = 0xff0b,
106 MLX5_OBJ_TYPE_RQT = 0xff0e,
107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
108 MLX5_OBJ_TYPE_CQ = 0xff10,
9fba2b9b
AL		 109};
110
d29b796a
EC		 111enum {
112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
114 MLX5_CMD_OP_INIT_HCA = 0x102,
115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
116 MLX5_CMD_OP_ENABLE_HCA = 0x104,
117 MLX5_CMD_OP_DISABLE_HCA = 0x105,
118 MLX5_CMD_OP_QUERY_PAGES = 0x107,
119 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
120 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 121 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
122 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
1759d322
PP		 124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
125 MLX5_CMD_OP_ALLOC_SF = 0x113,
126 MLX5_CMD_OP_DEALLOC_SF = 0x114,
adfdaff3
YH		 127 MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
128 MLX5_CMD_OP_RESUME_VHCA = 0x116,
129 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
130 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
131 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
d29b796a
EC		 132 MLX5_CMD_OP_CREATE_MKEY = 0x200,
133 MLX5_CMD_OP_QUERY_MKEY = 0x201,
134 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
135 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
136 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
24da0016
AL		 137 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
138 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
63f9c44b 139 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
d29b796a
EC		 140 MLX5_CMD_OP_CREATE_EQ = 0x301,
141 MLX5_CMD_OP_DESTROY_EQ = 0x302,
142 MLX5_CMD_OP_QUERY_EQ = 0x303,
143 MLX5_CMD_OP_GEN_EQE = 0x304,
144 MLX5_CMD_OP_CREATE_CQ = 0x400,
145 MLX5_CMD_OP_DESTROY_CQ = 0x401,
146 MLX5_CMD_OP_QUERY_CQ = 0x402,
147 MLX5_CMD_OP_MODIFY_CQ = 0x403,
148 MLX5_CMD_OP_CREATE_QP = 0x500,
149 MLX5_CMD_OP_DESTROY_QP = 0x501,
150 MLX5_CMD_OP_RST2INIT_QP = 0x502,
151 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
152 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
153 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
154 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
155 MLX5_CMD_OP_2ERR_QP = 0x507,
156 MLX5_CMD_OP_2RST_QP = 0x50a,
157 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 158 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 159 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
160 MLX5_CMD_OP_CREATE_PSV = 0x600,
161 MLX5_CMD_OP_DESTROY_PSV = 0x601,
162 MLX5_CMD_OP_CREATE_SRQ = 0x700,
163 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
164 MLX5_CMD_OP_QUERY_SRQ = 0x702,
165 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 166 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
167 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
168 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
169 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 170 MLX5_CMD_OP_CREATE_DCT = 0x710,
171 MLX5_CMD_OP_DESTROY_DCT = 0x711,
172 MLX5_CMD_OP_DRAIN_DCT = 0x712,
173 MLX5_CMD_OP_QUERY_DCT = 0x713,
174 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 175 MLX5_CMD_OP_CREATE_XRQ = 0x717,
176 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
177 MLX5_CMD_OP_QUERY_XRQ = 0x719,
178 MLX5_CMD_OP_ARM_XRQ = 0x71a,
719598c9
YH		 179 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
180 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
181 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
b1635ee6
YH		 182 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
183 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
cd56f929 184 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
d29b796a
EC		 185 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
186 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
187 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
188 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
189 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
190 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 191 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 192 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 193 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
194 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
195 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
196 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
61c5b5c9 197 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
d29b796a
EC		 198 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
199 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
200 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
201 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
fd4572b3
ED		 202 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
203 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
37e92a9d 204 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 205 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 206 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
207 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
208 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
209 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
210 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
211 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 212 MLX5_CMD_OP_ALLOC_PD = 0x800,
213 MLX5_CMD_OP_DEALLOC_PD = 0x801,
214 MLX5_CMD_OP_ALLOC_UAR = 0x802,
215 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
216 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
217 MLX5_CMD_OP_ACCESS_REG = 0x805,
218 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 219 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 220 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
221 MLX5_CMD_OP_MAD_IFC = 0x50d,
222 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
223 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
224 MLX5_CMD_OP_NOP = 0x80d,
225 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
226 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 227 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
228 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
229 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
230 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
231 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
232 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
233 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
234 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
235 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
236 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
237 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
238 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 239 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
240 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 241 MLX5_CMD_OP_CREATE_LAG = 0x840,
242 MLX5_CMD_OP_MODIFY_LAG = 0x841,
243 MLX5_CMD_OP_QUERY_LAG = 0x842,
244 MLX5_CMD_OP_DESTROY_LAG = 0x843,
245 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
246 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 247 MLX5_CMD_OP_CREATE_TIR = 0x900,
248 MLX5_CMD_OP_MODIFY_TIR = 0x901,
249 MLX5_CMD_OP_DESTROY_TIR = 0x902,
250 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 251 MLX5_CMD_OP_CREATE_SQ = 0x904,
252 MLX5_CMD_OP_MODIFY_SQ = 0x905,
253 MLX5_CMD_OP_DESTROY_SQ = 0x906,
254 MLX5_CMD_OP_QUERY_SQ = 0x907,
255 MLX5_CMD_OP_CREATE_RQ = 0x908,
256 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 257 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 258 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
259 MLX5_CMD_OP_QUERY_RQ = 0x90b,
260 MLX5_CMD_OP_CREATE_RMP = 0x90c,
261 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
262 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
263 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 264 MLX5_CMD_OP_CREATE_TIS = 0x912,
265 MLX5_CMD_OP_MODIFY_TIS = 0x913,
266 MLX5_CMD_OP_DESTROY_TIS = 0x914,
267 MLX5_CMD_OP_QUERY_TIS = 0x915,
268 MLX5_CMD_OP_CREATE_RQT = 0x916,
269 MLX5_CMD_OP_MODIFY_RQT = 0x917,
270 MLX5_CMD_OP_DESTROY_RQT = 0x918,
271 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 272 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 273 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
274 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
275 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
276 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
277 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
278 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
279 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
280 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 281 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 282 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
283 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
284 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 285 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
60786f09
MB		 286 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
287 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
719598c9 288 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
2a69cb9f
OG		 289 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
290 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
e662e14d 291 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
6062118d
IT		 292 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
293 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
294 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
295 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
296 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
38b7ca92 297 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
e662e14d
YH		 298 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
299 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
38b7ca92 300 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
6e3722ba
YH		 301 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
302 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
303 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
304 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
d32d7c52 305 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
349125ba
PP		 306 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
307 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
86d56a1a 308 MLX5_CMD_OP_MAX
e281682b
SM		 309};
310
719598c9
YH		 311/* Valid range for general commands that don't work over an object */
312enum {
313 MLX5_CMD_OP_GENERAL_START = 0xb00,
314 MLX5_CMD_OP_GENERAL_END = 0xd00,
315};
316
e281682b
SM		 317struct mlx5_ifc_flow_table_fields_supported_bits {
318 u8 outer_dmac[0x1];
319 u8 outer_smac[0x1];
320 u8 outer_ether_type[0x1];
19cc7524 321 u8 outer_ip_version[0x1];
e281682b
SM		 322 u8 outer_first_prio[0x1];
323 u8 outer_first_cfi[0x1];
324 u8 outer_first_vid[0x1];
a8ade55f 325 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 326 u8 outer_second_prio[0x1];
327 u8 outer_second_cfi[0x1];
328 u8 outer_second_vid[0x1];
b4ff3a36 329 u8 reserved_at_b[0x1];
e281682b
SM		 330 u8 outer_sip[0x1];
331 u8 outer_dip[0x1];
332 u8 outer_frag[0x1];
333 u8 outer_ip_protocol[0x1];
334 u8 outer_ip_ecn[0x1];
335 u8 outer_ip_dscp[0x1];
336 u8 outer_udp_sport[0x1];
337 u8 outer_udp_dport[0x1];
338 u8 outer_tcp_sport[0x1];
339 u8 outer_tcp_dport[0x1];
340 u8 outer_tcp_flags[0x1];
341 u8 outer_gre_protocol[0x1];
342 u8 outer_gre_key[0x1];
343 u8 outer_vxlan_vni[0x1];
75d90e7d
YK		 344 u8 outer_geneve_vni[0x1];
345 u8 outer_geneve_oam[0x1];
346 u8 outer_geneve_protocol_type[0x1];
347 u8 outer_geneve_opt_len[0x1];
8208461d 348 u8 source_vhca_port[0x1];
e281682b
SM		 349 u8 source_eswitch_port[0x1];
350
351 u8 inner_dmac[0x1];
352 u8 inner_smac[0x1];
353 u8 inner_ether_type[0x1];
19cc7524 354 u8 inner_ip_version[0x1];
e281682b
SM		 355 u8 inner_first_prio[0x1];
356 u8 inner_first_cfi[0x1];
357 u8 inner_first_vid[0x1];
b4ff3a36 358 u8 reserved_at_27[0x1];
e281682b
SM		 359 u8 inner_second_prio[0x1];
360 u8 inner_second_cfi[0x1];
361 u8 inner_second_vid[0x1];
b4ff3a36 362 u8 reserved_at_2b[0x1];
e281682b
SM		 363 u8 inner_sip[0x1];
364 u8 inner_dip[0x1];
365 u8 inner_frag[0x1];
366 u8 inner_ip_protocol[0x1];
367 u8 inner_ip_ecn[0x1];
368 u8 inner_ip_dscp[0x1];
369 u8 inner_udp_sport[0x1];
370 u8 inner_udp_dport[0x1];
371 u8 inner_tcp_sport[0x1];
372 u8 inner_tcp_dport[0x1];
373 u8 inner_tcp_flags[0x1];
b4ff3a36 374 u8 reserved_at_37[0x9];
71c6e863 375
b169e64a 376 u8 geneve_tlv_option_0_data[0x1];
f59464e2
YK		 377 u8 geneve_tlv_option_0_exist[0x1];
378 u8 reserved_at_42[0x3];
71c6e863
AL		 379 u8 outer_first_mpls_over_udp[0x4];
380 u8 outer_first_mpls_over_gre[0x4];
381 u8 inner_first_mpls[0x4];
382 u8 outer_first_mpls[0x4];
383 u8 reserved_at_55[0x2];
3346c487 384 u8 outer_esp_spi[0x1];
71c6e863 385 u8 reserved_at_58[0x2];
a550ddfc 386 u8 bth_dst_qp[0x1];
822e114b 387 u8 reserved_at_5b[0x5];
e281682b 388
822e114b
PB		 389 u8 reserved_at_60[0x18];
390 u8 metadata_reg_c_7[0x1];
391 u8 metadata_reg_c_6[0x1];
392 u8 metadata_reg_c_5[0x1];
393 u8 metadata_reg_c_4[0x1];
394 u8 metadata_reg_c_3[0x1];
395 u8 metadata_reg_c_2[0x1];
396 u8 metadata_reg_c_1[0x1];
397 u8 metadata_reg_c_0[0x1];
e281682b
SM		 398};
399
8208461d
AL		 400struct mlx5_ifc_flow_table_fields_supported_2_bits {
401 u8 reserved_at_0[0xe];
402 u8 bth_opcode[0x1];
403 u8 reserved_at_f[0x11];
404
405 u8 reserved_at_20[0x60];
406};
407
e281682b
SM		 408struct mlx5_ifc_flow_table_prop_layout_bits {
409 u8 ft_support[0x1];
9dc0b289
AV		 410 u8 reserved_at_1[0x1];
411 u8 flow_counter[0x1];
26a81453 412 u8 flow_modify_en[0x1];
2cc43b49 413 u8 modify_root[0x1];
34a40e68
MG		 414 u8 identified_miss_table_mode[0x1];
415 u8 flow_table_modify[0x1];
60786f09 416 u8 reformat[0x1];
7adbde20 417 u8 decap[0x1];
0c06897a
OG		 418 u8 reserved_at_9[0x1];
419 u8 pop_vlan[0x1];
420 u8 push_vlan[0x1];
8da6fe2a
JL		 421 u8 reserved_at_c[0x1];
422 u8 pop_vlan_2[0x1];
423 u8 push_vlan_2[0x1];
bea4e1f6 424 u8 reformat_and_vlan_action[0x1];
9fba2b9b
AL		 425 u8 reserved_at_10[0x1];
426 u8 sw_owner[0x1];
bea4e1f6
MB		 427 u8 reformat_l3_tunnel_to_l2[0x1];
428 u8 reformat_l2_to_l3_tunnel[0x1];
429 u8 reformat_and_modify_action[0x1];
822e114b
PB		 430 u8 ignore_flow_level[0x1];
431 u8 reserved_at_16[0x1];
f6f7d6b5 432 u8 table_miss_action_domain[0x1];
c6d4e45d 433 u8 termination_table[0x1];
e0ebd8eb 434 u8 reformat_and_fwd_to_table[0x1];
78fb6122
HN		 435 u8 reserved_at_1a[0x2];
436 u8 ipsec_encrypt[0x1];
437 u8 ipsec_decrypt[0x1];
9d8feb46
AV		 438 u8 sw_owner_v2[0x1];
439 u8 reserved_at_1f[0x1];
78fb6122 440
613f53fe
EC		 441 u8 termination_table_raw_traffic[0x1];
442 u8 reserved_at_21[0x1];
e281682b 443 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 444 u8 log_max_modify_header_context[0x8];
445 u8 max_modify_header_actions[0x8];
e281682b
SM		 446 u8 max_ft_level[0x8];
447
f5d23ee1
JL		 448 u8 reserved_at_40[0x6];
449 u8 execute_aso[0x1];
450 u8 reserved_at_47[0x19];
e281682b 451
67133eaa
YK		 452 u8 reserved_at_60[0x2];
453 u8 reformat_insert[0x1];
454 u8 reformat_remove[0x1];
8385c51f
LN		 455 u8 macsec_encrypt[0x1];
456 u8 macsec_decrypt[0x1];
457 u8 reserved_at_66[0x2];
458 u8 reformat_add_macsec[0x1];
459 u8 reformat_remove_macsec[0x1];
460 u8 reserved_at_6a[0xe];
e281682b
SM		 461 u8 log_max_ft_num[0x8];
462
a14587df
RS		 463 u8 reserved_at_80[0x10];
464 u8 log_max_flow_counter[0x8];
e281682b
SM		 465 u8 log_max_destination[0x8];
466
a14587df 467 u8 reserved_at_a0[0x18];
e281682b
SM		 468 u8 log_max_flow[0x8];
469
b4ff3a36 470 u8 reserved_at_c0[0x40];
e281682b
SM		 471
472 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
473
474 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
475};
476
477struct mlx5_ifc_odp_per_transport_service_cap_bits {
478 u8 send[0x1];
479 u8 receive[0x1];
480 u8 write[0x1];
481 u8 read[0x1];
17d2f88f 482 u8 atomic[0x1];
e281682b 483 u8 srq_receive[0x1];
b4ff3a36 484 u8 reserved_at_6[0x1a];
e281682b
SM		 485};
486
9175d810
LR		 487struct mlx5_ifc_ipv4_layout_bits {
488 u8 reserved_at_0[0x60];
489
490 u8 ipv4[0x20];
491};
492
493struct mlx5_ifc_ipv6_layout_bits {
494 u8 ipv6[16][0x8];
495};
496
497union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
500 u8 reserved_at_0[0x80];
501};
502
e281682b
SM		 503struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
504 u8 smac_47_16[0x20];
505
506 u8 smac_15_0[0x10];
507 u8 ethertype[0x10];
508
509 u8 dmac_47_16[0x20];
510
511 u8 dmac_15_0[0x10];
512 u8 first_prio[0x3];
513 u8 first_cfi[0x1];
514 u8 first_vid[0xc];
515
516 u8 ip_protocol[0x8];
517 u8 ip_dscp[0x6];
518 u8 ip_ecn[0x2];
10543365
MHY		 519 u8 cvlan_tag[0x1];
520 u8 svlan_tag[0x1];
e281682b 521 u8 frag[0x1];
19cc7524 522 u8 ip_version[0x4];
e281682b
SM		 523 u8 tcp_flags[0x9];
524
525 u8 tcp_sport[0x10];
526 u8 tcp_dport[0x10];
527
5c422bfa
YK		 528 u8 reserved_at_c0[0x10];
529 u8 ipv4_ihl[0x4];
530 u8 reserved_at_c4[0x4];
531
a8ade55f 532 u8 ttl_hoplimit[0x8];
e281682b
SM		 533
534 u8 udp_sport[0x10];
535 u8 udp_dport[0x10];
536
b4d1f032 537 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 538
b4d1f032 539 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 540};
541
5886a96a
OS		 542struct mlx5_ifc_nvgre_key_bits {
543 u8 hi[0x18];
544 u8 lo[0x8];
545};
546
547union mlx5_ifc_gre_key_bits {
548 struct mlx5_ifc_nvgre_key_bits nvgre;
549 u8 key[0x20];
550};
551
e281682b 552struct mlx5_ifc_fte_match_set_misc_bits {
97b5484e 553 u8 gre_c_present[0x1];
d32d7c52 554 u8 reserved_at_1[0x1];
97b5484e
AV		 555 u8 gre_k_present[0x1];
556 u8 gre_s_present[0x1];
557 u8 source_vhca_port[0x4];
7486216b 558 u8 source_sqn[0x18];
e281682b 559
3e99df87 560 u8 source_eswitch_owner_vhca_id[0x10];
e281682b
SM		 561 u8 source_port[0x10];
562
563 u8 outer_second_prio[0x3];
564 u8 outer_second_cfi[0x1];
565 u8 outer_second_vid[0xc];
566 u8 inner_second_prio[0x3];
567 u8 inner_second_cfi[0x1];
568 u8 inner_second_vid[0xc];
569
10543365
MHY		 570 u8 outer_second_cvlan_tag[0x1];
571 u8 inner_second_cvlan_tag[0x1];
572 u8 outer_second_svlan_tag[0x1];
573 u8 inner_second_svlan_tag[0x1];
574 u8 reserved_at_64[0xc];
e281682b
SM		 575 u8 gre_protocol[0x10];
576
5886a96a 577 union mlx5_ifc_gre_key_bits gre_key;
e281682b
SM		 578
579 u8 vxlan_vni[0x18];
8208461d 580 u8 bth_opcode[0x8];
e281682b 581
75d90e7d 582 u8 geneve_vni[0x18];
f59464e2
YK		 583 u8 reserved_at_d8[0x6];
584 u8 geneve_tlv_option_0_exist[0x1];
75d90e7d 585 u8 geneve_oam[0x1];
e281682b 586
b4ff3a36 587 u8 reserved_at_e0[0xc];
e281682b
SM		 588 u8 outer_ipv6_flow_label[0x14];
589
b4ff3a36 590 u8 reserved_at_100[0xc];
e281682b
SM		 591 u8 inner_ipv6_flow_label[0x14];
592
75d90e7d
YK		 593 u8 reserved_at_120[0xa];
594 u8 geneve_opt_len[0x6];
595 u8 geneve_protocol_type[0x10];
596
597 u8 reserved_at_140[0x8];
a550ddfc 598 u8 bth_dst_qp[0x18];
3346c487
BP		 599 u8 reserved_at_160[0x20];
600 u8 outer_esp_spi[0x20];
601 u8 reserved_at_1a0[0x60];
e281682b
SM		 602};
603
71c6e863
AL		 604struct mlx5_ifc_fte_match_mpls_bits {
605 u8 mpls_label[0x14];
606 u8 mpls_exp[0x3];
607 u8 mpls_s_bos[0x1];
608 u8 mpls_ttl[0x8];
609};
610
611struct mlx5_ifc_fte_match_set_misc2_bits {
612 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
613
614 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
615
616 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
617
618 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
619
65c0f2c1
JL		 620 u8 metadata_reg_c_7[0x20];
621
622 u8 metadata_reg_c_6[0x20];
623
624 u8 metadata_reg_c_5[0x20];
625
626 u8 metadata_reg_c_4[0x20];
627
628 u8 metadata_reg_c_3[0x20];
629
630 u8 metadata_reg_c_2[0x20];
631
632 u8 metadata_reg_c_1[0x20];
633
634 u8 metadata_reg_c_0[0x20];
71c6e863
AL		 635
636 u8 metadata_reg_a[0x20];
637
8385c51f
LN		 638 u8 reserved_at_1a0[0x8];
639
640 u8 macsec_syndrome[0x8];
641
642 u8 reserved_at_1b0[0x50];
71c6e863
AL		 643};
644
b169e64a 645struct mlx5_ifc_fte_match_set_misc3_bits {
97b5484e
AV		 646 u8 inner_tcp_seq_num[0x20];
647
648 u8 outer_tcp_seq_num[0x20];
649
650 u8 inner_tcp_ack_num[0x20];
651
652 u8 outer_tcp_ack_num[0x20];
653
654 u8 reserved_at_80[0x8];
655 u8 outer_vxlan_gpe_vni[0x18];
656
657 u8 outer_vxlan_gpe_next_protocol[0x8];
658 u8 outer_vxlan_gpe_flags[0x8];
659 u8 reserved_at_b0[0x10];
660
661 u8 icmp_header_data[0x20];
662
663 u8 icmpv6_header_data[0x20];
664
665 u8 icmp_type[0x8];
666 u8 icmp_code[0x8];
667 u8 icmpv6_type[0x8];
668 u8 icmpv6_code[0x8];
669
b169e64a 670 u8 geneve_tlv_option_0_data[0x20];
97b5484e 671
704cfecd
YK		 672 u8 gtpu_teid[0x20];
673
674 u8 gtpu_msg_type[0x8];
675 u8 gtpu_msg_flags[0x8];
676 u8 reserved_at_170[0x10];
677
678 u8 gtpu_dw_2[0x20];
679
680 u8 gtpu_first_ext_dw_0[0x20];
681
682 u8 gtpu_dw_0[0x20];
683
684 u8 reserved_at_1e0[0x20];
b169e64a
YK		 685};
686
7da3ad6c
MS		 687struct mlx5_ifc_fte_match_set_misc4_bits {
688 u8 prog_sample_field_value_0[0x20];
689
690 u8 prog_sample_field_id_0[0x20];
691
692 u8 prog_sample_field_value_1[0x20];
693
694 u8 prog_sample_field_id_1[0x20];
695
696 u8 prog_sample_field_value_2[0x20];
697
698 u8 prog_sample_field_id_2[0x20];
699
700 u8 prog_sample_field_value_3[0x20];
701
702 u8 prog_sample_field_id_3[0x20];
703
704 u8 reserved_at_100[0x100];
705};
706
0f2a6c3b
MS		 707struct mlx5_ifc_fte_match_set_misc5_bits {
708 u8 macsec_tag_0[0x20];
709
710 u8 macsec_tag_1[0x20];
711
712 u8 macsec_tag_2[0x20];
713
714 u8 macsec_tag_3[0x20];
715
716 u8 tunnel_header_0[0x20];
717
718 u8 tunnel_header_1[0x20];
719
720 u8 tunnel_header_2[0x20];
721
722 u8 tunnel_header_3[0x20];
723
724 u8 reserved_at_100[0x100];
725};
726
e281682b
SM		 727struct mlx5_ifc_cmd_pas_bits {
728 u8 pa_h[0x20];
729
730 u8 pa_l[0x14];
b4ff3a36 731 u8 reserved_at_34[0xc];
e281682b
SM		 732};
733
734struct mlx5_ifc_uint64_bits {
735 u8 hi[0x20];
736
737 u8 lo[0x20];
738};
739
740enum {
741 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
742 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
743 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
744 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
745 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
746 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
747 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
748 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
749 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
750 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
751};
752
753struct mlx5_ifc_ads_bits {
754 u8 fl[0x1];
755 u8 free_ar[0x1];
b4ff3a36 756 u8 reserved_at_2[0xe];
e281682b
SM		 757 u8 pkey_index[0x10];
758
b4ff3a36 759 u8 reserved_at_20[0x8];
e281682b
SM		 760 u8 grh[0x1];
761 u8 mlid[0x7];
762 u8 rlid[0x10];
763
764 u8 ack_timeout[0x5];
b4ff3a36 765 u8 reserved_at_45[0x3];
e281682b 766 u8 src_addr_index[0x8];
b4ff3a36 767 u8 reserved_at_50[0x4];
e281682b
SM		 768 u8 stat_rate[0x4];
769 u8 hop_limit[0x8];
770
b4ff3a36 771 u8 reserved_at_60[0x4];
e281682b
SM		 772 u8 tclass[0x8];
773 u8 flow_label[0x14];
774
775 u8 rgid_rip[16][0x8];
776
b4ff3a36 777 u8 reserved_at_100[0x4];
e281682b
SM		 778 u8 f_dscp[0x1];
779 u8 f_ecn[0x1];
b4ff3a36 780 u8 reserved_at_106[0x1];
e281682b
SM		 781 u8 f_eth_prio[0x1];
782 u8 ecn[0x2];
783 u8 dscp[0x6];
784 u8 udp_sport[0x10];
785
786 u8 dei_cfi[0x1];
787 u8 eth_prio[0x3];
788 u8 sl[0x4];
32f69e4b 789 u8 vhca_port_num[0x8];
e281682b
SM		 790 u8 rmac_47_32[0x10];
791
792 u8 rmac_31_0[0x20];
793};
794
795struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 796 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 797 u8 nic_rx_multi_path_tirs_fts[0x1];
798 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
13a7e459
ES		 799 u8 reserved_at_3[0x4];
800 u8 sw_owner_reformat_supported[0x1];
801 u8 reserved_at_8[0x18];
802
bea4e1f6
MB		 803 u8 encap_general_header[0x1];
804 u8 reserved_at_21[0xa];
805 u8 log_max_packet_reformat_context[0x5];
806 u8 reserved_at_30[0x6];
807 u8 max_encap_header_size[0xa];
808 u8 reserved_at_40[0x1c0];
e281682b
SM		 809
810 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
811
d83eb50e 812 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
e281682b
SM		 813
814 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
815
816 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
817
24670b1a 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
e281682b
SM		 819
820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
821
8208461d
AL		 822 u8 reserved_at_e00[0x700];
823
824 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
825
826 u8 reserved_at_1580[0x280];
827
828 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
829
830 u8 reserved_at_1880[0x780];
97b5484e
AV		 831
832 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
833
834 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
835
836 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
837
838 u8 reserved_at_20c0[0x5f40];
e281682b
SM		 839};
840
425a563a
MG		 841struct mlx5_ifc_port_selection_cap_bits {
842 u8 reserved_at_0[0x10];
843 u8 port_select_flow_table[0x1];
8d1ac895
LC		 844 u8 reserved_at_11[0x1];
845 u8 port_select_flow_table_bypass[0x1];
846 u8 reserved_at_13[0xd];
425a563a
MG		 847
848 u8 reserved_at_20[0x1e0];
849
850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
851
852 u8 reserved_at_400[0x7c00];
853};
854
65c0f2c1
JL		 855enum {
856 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
857 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
858 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
859 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
860 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
861 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
862 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
863 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
864};
865
495716b1 866struct mlx5_ifc_flow_table_eswitch_cap_bits {
65c0f2c1 867 u8 fdb_to_vport_reg_c_id[0x8];
822e114b
PB		 868 u8 reserved_at_8[0xd];
869 u8 fdb_modify_header_fwd_to_table[0x1];
4ff725e1 870 u8 fdb_ipv4_ttl_modify[0x1];
65c0f2c1
JL		 871 u8 flow_source[0x1];
872 u8 reserved_at_18[0x2];
b9aa0ba1 873 u8 multi_fdb_encap[0x1];
86f5d0f3 874 u8 egress_acl_forward_to_vport[0x1];
663f146f
VP		 875 u8 fdb_multi_path_to_table[0x1];
876 u8 reserved_at_1d[0x3];
877
878 u8 reserved_at_20[0x1e0];
495716b1
SM		 879
880 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
881
882 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
883
884 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
885
97b5484e
AV		 886 u8 reserved_at_800[0x1000];
887
888 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
889
890 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
891
892 u8 sw_steering_uplink_icm_address_rx[0x40];
893
894 u8 sw_steering_uplink_icm_address_tx[0x40];
895
896 u8 reserved_at_1900[0x6700];
495716b1
SM		 897};
898
8bb957d2
SK		 899enum {
900 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
901 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
902};
903
d6666753
SM		 904struct mlx5_ifc_e_switch_cap_bits {
905 u8 vport_svlan_strip[0x1];
906 u8 vport_cvlan_strip[0x1];
907 u8 vport_svlan_insert[0x1];
908 u8 vport_cvlan_insert_if_not_exist[0x1];
909 u8 vport_cvlan_insert_overwrite[0x1];
c3e666f1
MB		 910 u8 reserved_at_5[0x2];
911 u8 esw_shared_ingress_acl[0x1];
65c0f2c1 912 u8 esw_uplink_ingress_acl[0x1];
c3e666f1
MB		 913 u8 root_ft_on_other_esw[0x1];
914 u8 reserved_at_a[0xf];
6706a3b9
VP		 915 u8 esw_functions_changed[0x1];
916 u8 reserved_at_1a[0x1];
81cd229c 917 u8 ecpf_vport_exists[0x1];
8bb957d2 918 u8 counter_eswitch_affinity[0x1];
a6d04569 919 u8 merged_eswitch[0x1];
23898c76
NO		 920 u8 nic_vport_node_guid_modify[0x1];
921 u8 nic_vport_port_guid_modify[0x1];
d6666753 922
7adbde20
HHZ		 923 u8 vxlan_encap_decap[0x1];
924 u8 nvgre_encap_decap[0x1];
1b115498
EB		 925 u8 reserved_at_22[0x1];
926 u8 log_max_fdb_encap_uplink[0x5];
927 u8 reserved_at_21[0x3];
60786f09 928 u8 log_max_packet_reformat_context[0x5];
7adbde20
HHZ		 929 u8 reserved_2b[0x6];
930 u8 max_encap_header_size[0xa];
931
1759d322
PP		 932 u8 reserved_at_40[0xb];
933 u8 log_max_esw_sf[0x5];
934 u8 esw_sf_base_id[0x10];
935
936 u8 reserved_at_60[0x7a0];
7adbde20 937
d6666753
SM		 938};
939
7486216b
SM		 940struct mlx5_ifc_qos_cap_bits {
941 u8 packet_pacing[0x1];
813f8540 942 u8 esw_scheduling[0x1];
c9497c98
MHY		 943 u8 esw_bw_share[0x1];
944 u8 esw_rate_limit[0x1];
05d3ac97
BW		 945 u8 reserved_at_4[0x1];
946 u8 packet_pacing_burst_bound[0x1];
947 u8 packet_pacing_typical_size[0x1];
214baf22
MM		 948 u8 reserved_at_7[0x1];
949 u8 nic_sq_scheduling[0x1];
950 u8 nic_bw_share[0x1];
951 u8 nic_rate_limit[0x1];
1326034b 952 u8 packet_pacing_uid[0x1];
1ae258f8
DL		 953 u8 log_esw_max_sched_depth[0x4];
954 u8 reserved_at_10[0x10];
813f8540 955
214baf22
MM		 956 u8 reserved_at_20[0xb];
957 u8 log_max_qos_nic_queue_group[0x5];
958 u8 reserved_at_30[0x10];
813f8540 959
7486216b 960 u8 packet_pacing_max_rate[0x20];
813f8540 961
7486216b 962 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 963
964 u8 reserved_at_80[0x10];
7486216b 965 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 966
967 u8 esw_element_type[0x10];
968 u8 esw_tsar_type[0x10];
969
970 u8 reserved_at_c0[0x10];
971 u8 max_qos_para_vport[0x10];
972
973 u8 max_tsar_bw_share[0x20];
974
f5d23ee1
JL		 975 u8 reserved_at_100[0x20];
976
977 u8 reserved_at_120[0x3];
978 u8 log_meter_aso_granularity[0x5];
979 u8 reserved_at_128[0x3];
980 u8 log_meter_aso_max_alloc[0x5];
981 u8 reserved_at_130[0x3];
982 u8 log_max_num_meter_aso[0x5];
983 u8 reserved_at_138[0x8];
984
985 u8 reserved_at_140[0x6c0];
7486216b
SM		 986};
987
2fcb12df 988struct mlx5_ifc_debug_cap_bits {
0b9055a1
MS		 989 u8 core_dump_general[0x1];
990 u8 core_dump_qp[0x1];
609b8272
AL		 991 u8 reserved_at_2[0x7];
992 u8 resource_dump[0x1];
993 u8 reserved_at_a[0x16];
2fcb12df
IK		 994
995 u8 reserved_at_20[0x2];
996 u8 stall_detect[0x1];
997 u8 reserved_at_23[0x1d];
998
999 u8 reserved_at_40[0x7c0];
1000};
1001
e281682b
SM		 1002struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1003 u8 csum_cap[0x1];
1004 u8 vlan_cap[0x1];
1005 u8 lro_cap[0x1];
1006 u8 lro_psh_flag[0x1];
1007 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 1008 u8 reserved_at_5[0x2];
1009 u8 wqe_vlan_insert[0x1];
66189961 1010 u8 self_lb_en_modifiable[0x1];
b4ff3a36 1011 u8 reserved_at_9[0x2];
e281682b 1012 u8 max_lso_cap[0x5];
c226dc22 1013 u8 multi_pkt_send_wqe[0x2];
cff92d7c 1014 u8 wqe_inline_mode[0x2];
e281682b 1015 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 1016 u8 reg_umr_sq[0x1];
1017 u8 scatter_fcs[0x1];
050da902 1018 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 1019 u8 tunnel_lso_const_out_ip_id[0x1];
26ab7b38
MM		 1020 u8 tunnel_lro_gre[0x1];
1021 u8 tunnel_lro_vxlan[0x1];
27299841 1022 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 1023 u8 tunnel_stateless_vxlan[0x1];
1024
547eede0
IT		 1025 u8 swp[0x1];
1026 u8 swp_csum[0x1];
1027 u8 swp_lso[0x1];
db849faa 1028 u8 cqe_checksum_full[0x1];
41e684ef
AV		 1029 u8 tunnel_stateless_geneve_tx[0x1];
1030 u8 tunnel_stateless_mpls_over_udp[0x1];
1031 u8 tunnel_stateless_mpls_over_gre[0x1];
1032 u8 tunnel_stateless_vxlan_gpe[0x1];
1033 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
caa18547 1034 u8 tunnel_stateless_ip_over_ip[0x1];
2b58f6d9 1035 u8 insert_trailer[0x1];
21adf05d
AL		 1036 u8 reserved_at_2b[0x1];
1037 u8 tunnel_stateless_ip_over_ip_rx[0x1];
1038 u8 tunnel_stateless_ip_over_ip_tx[0x1];
1039 u8 reserved_at_2e[0x2];
22a65aa8
GP		 1040 u8 max_vxlan_udp_ports[0x8];
1041 u8 reserved_at_38[0x6];
4d350f1f
MG		 1042 u8 max_geneve_opt_len[0x1];
1043 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 1044
b4ff3a36 1045 u8 reserved_at_40[0x10];
e281682b
SM		 1046 u8 lro_min_mss_size[0x10];
1047
b4ff3a36 1048 u8 reserved_at_60[0x120];
e281682b
SM		 1049
1050 u8 lro_timer_supported_periods[4][0x20];
1051
b4ff3a36 1052 u8 reserved_at_200[0x600];
e281682b
SM		 1053};
1054
a6a217dd 1055enum {
9a1ac95a
AL		 1056 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1057 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1058 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
a6a217dd
AL		 1059};
1060
e281682b
SM		 1061struct mlx5_ifc_roce_cap_bits {
1062 u8 roce_apm[0x1];
59e9e8e4
MZ		 1063 u8 reserved_at_1[0x3];
1064 u8 sw_r_roce_src_udp_port[0x1];
7304d603
YK		 1065 u8 fl_rc_qp_when_roce_disabled[0x1];
1066 u8 fl_rc_qp_when_roce_enabled[0x1];
1067 u8 reserved_at_7[0x17];
a6a217dd 1068 u8 qp_ts_format[0x2];
e281682b 1069
b4ff3a36 1070 u8 reserved_at_20[0x60];
e281682b 1071
b4ff3a36 1072 u8 reserved_at_80[0xc];
e281682b 1073 u8 l3_type[0x4];
b4ff3a36 1074 u8 reserved_at_90[0x8];
e281682b
SM		 1075 u8 roce_version[0x8];
1076
b4ff3a36 1077 u8 reserved_at_a0[0x10];
e281682b
SM		 1078 u8 r_roce_dest_udp_port[0x10];
1079
1080 u8 r_roce_max_src_udp_port[0x10];
1081 u8 r_roce_min_src_udp_port[0x10];
1082
b4ff3a36 1083 u8 reserved_at_e0[0x10];
e281682b
SM		 1084 u8 roce_address_table_size[0x10];
1085
b4ff3a36 1086 u8 reserved_at_100[0x700];
e281682b
SM		 1087};
1088
97b5484e
AV		 1089struct mlx5_ifc_sync_steering_in_bits {
1090 u8 opcode[0x10];
1091 u8 uid[0x10];
1092
1093 u8 reserved_at_20[0x10];
1094 u8 op_mod[0x10];
1095
1096 u8 reserved_at_40[0xc0];
1097};
1098
1099struct mlx5_ifc_sync_steering_out_bits {
1100 u8 status[0x8];
1101 u8 reserved_at_8[0x18];
1102
1103 u8 syndrome[0x20];
1104
1105 u8 reserved_at_40[0x40];
1106};
1107
e72bd817
AL		 1108struct mlx5_ifc_device_mem_cap_bits {
1109 u8 memic[0x1];
1110 u8 reserved_at_1[0x1f];
1111
1112 u8 reserved_at_20[0xb];
1113 u8 log_min_memic_alloc_size[0x5];
1114 u8 reserved_at_30[0x8];
1115 u8 log_max_memic_addr_alignment[0x8];
1116
1117 u8 memic_bar_start_addr[0x40];
1118
1119 u8 memic_bar_size[0x20];
1120
1121 u8 max_memic_size[0x20];
1122
9fba2b9b
AL		 1123 u8 steering_sw_icm_start_address[0x40];
1124
1125 u8 reserved_at_100[0x8];
1126 u8 log_header_modify_sw_icm_size[0x8];
1127 u8 reserved_at_110[0x2];
1128 u8 log_sw_icm_alloc_granularity[0x6];
1129 u8 log_steering_sw_icm_size[0x8];
1130
795e10b4
YK		 1131 u8 reserved_at_120[0x18];
1132 u8 log_header_modify_pattern_sw_icm_size[0x8];
9fba2b9b
AL		 1133
1134 u8 header_modify_sw_icm_start_address[0x40];
1135
795e10b4
YK		 1136 u8 reserved_at_180[0x40];
1137
1138 u8 header_modify_pattern_sw_icm_start_address[0x40];
63f9c44b
MG		 1139
1140 u8 memic_operations[0x20];
1141
1142 u8 reserved_at_220[0x5e0];
e72bd817
AL		 1143};
1144
b9a7ba55
YH		 1145struct mlx5_ifc_device_event_cap_bits {
1146 u8 user_affiliated_events[4][0x40];
1147
1148 u8 user_unaffiliated_events[4][0x40];
1149};
1150
8a06a79b
EC		 1151struct mlx5_ifc_virtio_emulation_cap_bits {
1152 u8 desc_tunnel_offload_type[0x1];
1153 u8 eth_frame_offload_type[0x1];
1154 u8 virtio_version_1_0[0x1];
1155 u8 device_features_bits_mask[0xd];
1156 u8 event_mode[0x8];
1157 u8 virtio_queue_type[0x8];
90fbca59 1158
8a06a79b
EC		 1159 u8 max_tunnel_desc[0x10];
1160 u8 reserved_at_30[0x3];
90fbca59
YH		 1161 u8 log_doorbell_stride[0x5];
1162 u8 reserved_at_38[0x3];
1163 u8 log_doorbell_bar_size[0x5];
1164
1165 u8 doorbell_bar_offset[0x40];
1166
8a06a79b
EC		 1167 u8 max_emulated_devices[0x8];
1168 u8 max_num_virtio_queues[0x18];
1169
1170 u8 reserved_at_a0[0x60];
1171
1172 u8 umem_1_buffer_param_a[0x20];
1173
1174 u8 umem_1_buffer_param_b[0x20];
1175
1176 u8 umem_2_buffer_param_a[0x20];
1177
1178 u8 umem_2_buffer_param_b[0x20];
1179
1180 u8 umem_3_buffer_param_a[0x20];
1181
1182 u8 umem_3_buffer_param_b[0x20];
1183
1184 u8 reserved_at_1c0[0x640];
90fbca59
YH		 1185};
1186
e281682b
SM		 1187enum {
1188 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1189 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1190 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1191 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1192 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1193 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1194 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1195 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1196 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1197};
1198
1199enum {
1200 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1203 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1204 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1205 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1209};
1210
1211struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 1212 u8 reserved_at_0[0x40];
e281682b 1213
bd10838a 1214 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 1215 u8 reserved_at_42[0x4];
bd10838a 1216 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 1217
b4ff3a36 1218 u8 reserved_at_47[0x19];
e281682b 1219
b4ff3a36 1220 u8 reserved_at_60[0x20];
e281682b 1221
b4ff3a36 1222 u8 reserved_at_80[0x10];
f91e6d89 1223 u8 atomic_operations[0x10];
e281682b 1224
b4ff3a36 1225 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 1226 u8 atomic_size_qp[0x10];
1227
b4ff3a36 1228 u8 reserved_at_c0[0x10];
e281682b
SM		 1229 u8 atomic_size_dc[0x10];
1230
b4ff3a36 1231 u8 reserved_at_e0[0x720];
e281682b
SM		 1232};
1233
1234struct mlx5_ifc_odp_cap_bits {
b4ff3a36 1235 u8 reserved_at_0[0x40];
e281682b
SM		 1236
1237 u8 sig[0x1];
b4ff3a36 1238 u8 reserved_at_41[0x1f];
e281682b 1239
b4ff3a36 1240 u8 reserved_at_60[0x20];
e281682b
SM		 1241
1242 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1243
1244 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1245
1246 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1247
dda7a817
MS		 1248 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1249
00679b63
MG		 1250 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1251
1252 u8 reserved_at_120[0x6E0];
e281682b
SM		 1253};
1254
3f0393a5
SG		 1255struct mlx5_ifc_calc_op {
1256 u8 reserved_at_0[0x10];
1257 u8 reserved_at_10[0x9];
1258 u8 op_swap_endianness[0x1];
1259 u8 op_min[0x1];
1260 u8 op_xor[0x1];
1261 u8 op_or[0x1];
1262 u8 op_and[0x1];
1263 u8 op_max[0x1];
1264 u8 op_add[0x1];
1265};
1266
1267struct mlx5_ifc_vector_calc_cap_bits {
1268 u8 calc_matrix[0x1];
1269 u8 reserved_at_1[0x1f];
1270 u8 reserved_at_20[0x8];
1271 u8 max_vec_count[0x8];
1272 u8 reserved_at_30[0xd];
1273 u8 max_chunk_size[0x3];
1274 struct mlx5_ifc_calc_op calc0;
1275 struct mlx5_ifc_calc_op calc1;
1276 struct mlx5_ifc_calc_op calc2;
1277 struct mlx5_ifc_calc_op calc3;
1278
c74d90c1 1279 u8 reserved_at_c0[0x720];
3f0393a5
SG		 1280};
1281
a12ff35e
EBE		 1282struct mlx5_ifc_tls_cap_bits {
1283 u8 tls_1_2_aes_gcm_128[0x1];
1284 u8 tls_1_3_aes_gcm_128[0x1];
1285 u8 tls_1_2_aes_gcm_256[0x1];
1286 u8 tls_1_3_aes_gcm_256[0x1];
1287 u8 reserved_at_4[0x1c];
1288
1289 u8 reserved_at_20[0x7e0];
1290};
1291
2b58f6d9
RS		 1292struct mlx5_ifc_ipsec_cap_bits {
1293 u8 ipsec_full_offload[0x1];
1294 u8 ipsec_crypto_offload[0x1];
1295 u8 ipsec_esn[0x1];
1296 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1297 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1298 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1299 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1300 u8 reserved_at_7[0x4];
1301 u8 log_max_ipsec_offload[0x5];
1302 u8 reserved_at_10[0x10];
1303
1304 u8 min_log_ipsec_full_replay_window[0x8];
1305 u8 max_log_ipsec_full_replay_window[0x8];
1306 u8 reserved_at_30[0x7d0];
1307};
1308
8385c51f
LN		 1309struct mlx5_ifc_macsec_cap_bits {
1310 u8 macsec_epn[0x1];
1311 u8 reserved_at_1[0x2];
1312 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1313 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1314 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1315 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1316 u8 reserved_at_7[0x4];
1317 u8 log_max_macsec_offload[0x5];
1318 u8 reserved_at_10[0x10];
1319
1320 u8 min_log_macsec_full_replay_window[0x8];
1321 u8 max_log_macsec_full_replay_window[0x8];
1322 u8 reserved_at_30[0x10];
1323
1324 u8 reserved_at_40[0x7c0];
1325};
1326
e281682b
SM		 1327enum {
1328 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1329 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 1330 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 1331 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 1332};
1333
1334enum {
1335 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1336 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1337};
1338
1339enum {
1340 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1341 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1342 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1343 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1344 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1345};
1346
1347enum {
1348 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1349 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1350 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1351 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1352 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1353 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1354};
1355
1356enum {
1357 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1358 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1359};
1360
1361enum {
1362 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1363 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1364 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1365};
1366
1367enum {
1368 MLX5_CAP_PORT_TYPE_IB = 0x0,
1369 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 1370};
1371
1410a90a
MG		 1372enum {
1373 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1374 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1375 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1376};
1377
97b5484e 1378enum {
a18fab48 1379 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
704cfecd 1380 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
c3fb0e28 1381 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
97b5484e
AV		 1382 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1383 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1384 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
704cfecd
YK		 1385 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1386 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1387 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1388 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1389 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1390 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
97b5484e
AV		 1391};
1392
9d43faac
YH		 1393enum {
1394 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
9fba2b9b 1395 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
9d43faac
YH		 1396};
1397
8536a6bf
GT		 1398#define MLX5_FC_BULK_SIZE_FACTOR 128
1399
1400enum mlx5_fc_bulk_alloc_bitmask {
1401 MLX5_FC_BULK_128 = (1 << 0),
1402 MLX5_FC_BULK_256 = (1 << 1),
1403 MLX5_FC_BULK_512 = (1 << 2),
1404 MLX5_FC_BULK_1024 = (1 << 3),
1405 MLX5_FC_BULK_2048 = (1 << 4),
1406 MLX5_FC_BULK_4096 = (1 << 5),
1407 MLX5_FC_BULK_8192 = (1 << 6),
1408 MLX5_FC_BULK_16384 = (1 << 7),
1409};
1410
1411#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1412
216214c6
YK		 1413#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1414
d421e466
YK		 1415enum {
1416 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1417 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
6862c787 1418 MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
d421e466
YK		 1419};
1420
b775516b 1421struct mlx5_ifc_cmd_hca_cap_bits {
f484da84
MB		 1422 u8 reserved_at_0[0x10];
1423 u8 shared_object_to_user_object_allowed[0x1];
1424 u8 reserved_at_13[0xe];
959af556 1425 u8 vhca_resource_manager[0x1];
349125ba 1426
67133eaa 1427 u8 hca_cap_2[0x1];
94db3317 1428 u8 create_lag_when_not_master_up[0x1];
4b2c5fa9 1429 u8 dtor[0x1];
349125ba
PP		 1430 u8 event_on_vhca_state_teardown_request[0x1];
1431 u8 event_on_vhca_state_in_use[0x1];
1432 u8 event_on_vhca_state_active[0x1];
1433 u8 event_on_vhca_state_allocated[0x1];
1434 u8 event_on_vhca_state_invalid[0x1];
1435 u8 reserved_at_28[0x8];
32f69e4b
DJ		 1436 u8 vhca_id[0x10];
1437
1438 u8 reserved_at_40[0x40];
b775516b
EC		 1439
1440 u8 log_max_srq_sz[0x8];
1441 u8 log_max_qp_sz[0x8];
b9a7ba55 1442 u8 event_cap[0x1];
aeacb52a
YK		 1443 u8 reserved_at_91[0x2];
1444 u8 isolate_vl_tc_new[0x1];
1445 u8 reserved_at_94[0x4];
316793fb
EB		 1446 u8 prio_tag_required[0x1];
1447 u8 reserved_at_99[0x2];
b775516b
EC		 1448 u8 log_max_qp[0x5];
1449
6b646a7e
LR		 1450 u8 reserved_at_a0[0x3];
1451 u8 ece_support[0x1];
838b00a2
PB		 1452 u8 reserved_at_a4[0x5];
1453 u8 reg_c_preserve[0x1];
1454 u8 reserved_at_aa[0x1];
e281682b 1455 u8 log_max_srq[0x5];
9c9be85f
AL		 1456 u8 reserved_at_b0[0x1];
1457 u8 uplink_follow[0x1];
59d2ae1d 1458 u8 ts_cqe_to_dest_cqn[0x1];
7025329d
BBI		 1459 u8 reserved_at_b3[0x7];
1460 u8 shampo[0x1];
1461 u8 reserved_at_bb[0x5];
b775516b 1462
7d47433c 1463 u8 max_sgl_for_optimized_performance[0x8];
b775516b 1464 u8 log_max_cq_sz[0x8];
042dd05b
ML		 1465 u8 relaxed_ordering_write_umr[0x1];
1466 u8 relaxed_ordering_read_umr[0x1];
1467 u8 reserved_at_d2[0x7];
8a06a79b
EC		 1468 u8 virtio_net_device_emualtion_manager[0x1];
1469 u8 virtio_blk_device_emualtion_manager[0x1];
b775516b
EC		 1470 u8 log_max_cq[0x5];
1471
1472 u8 log_max_eq_sz[0x8];
a880a6dd
MG		 1473 u8 relaxed_ordering_write[0x1];
1474 u8 relaxed_ordering_read[0x1];
b775516b 1475 u8 log_max_mkey[0x6];
b183ee27
LR		 1476 u8 reserved_at_f0[0x8];
1477 u8 dump_fill_mkey[0x1];
fcd29ad1
FD		 1478 u8 reserved_at_f9[0x2];
1479 u8 fast_teardown[0x1];
b775516b
EC		 1480 u8 log_max_eq[0x4];
1481
1482 u8 max_indirection[0x8];
bcda1aca 1483 u8 fixed_buffer_size[0x1];
b775516b 1484 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 1485 u8 force_teardown[0x1];
1486 u8 reserved_at_111[0x1];
b775516b 1487 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 1488 u8 umr_extended_translation_offset[0x1];
1489 u8 null_mkey[0x1];
b775516b
EC		 1490 u8 log_max_klm_list_size[0x6];
1491
b4ff3a36 1492 u8 reserved_at_120[0xa];
b775516b 1493 u8 log_max_ra_req_dc[0x6];
3e94e61b
SM		 1494 u8 reserved_at_130[0x9];
1495 u8 vnic_env_cq_overrun[0x1];
b775516b
EC		 1496 u8 log_max_ra_res_dc[0x6];
1497
d2cb8dda 1498 u8 reserved_at_140[0x5];
0e1533bb 1499 u8 release_all_pages[0x1];
d2cb8dda 1500 u8 must_not_use[0x1];
0e1533bb 1501 u8 reserved_at_147[0x2];
8fd5b75d 1502 u8 roce_accl[0x1];
b775516b 1503 u8 log_max_ra_req_qp[0x6];
b4ff3a36 1504 u8 reserved_at_150[0xa];
b775516b
EC		 1505 u8 log_max_ra_res_qp[0x6];
1506
f32f5bd2 1507 u8 end_pad[0x1];
b775516b
EC		 1508 u8 cc_query_allowed[0x1];
1509 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 1510 u8 start_pad[0x1];
1511 u8 cache_line_128byte[0x1];
f8efee08
MZ		 1512 u8 reserved_at_165[0x4];
1513 u8 rts2rts_qp_counters_set_id[0x1];
30b10e89
MS		 1514 u8 reserved_at_16a[0x2];
1515 u8 vnic_env_int_rq_oob[0x1];
948d3f90
AL		 1516 u8 sbcam_reg[0x1];
1517 u8 reserved_at_16e[0x1];
c02762eb 1518 u8 qcam_reg[0x1];
e281682b 1519 u8 gid_table_size[0x10];
b775516b 1520
e281682b
SM		 1521 u8 out_of_seq_cnt[0x1];
1522 u8 vport_counters[0x1];
7486216b 1523 u8 retransmission_q_counters[0x1];
2fcb12df 1524 u8 debug[0x1];
83b502a1 1525 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 1526 u8 rq_delay_drop[0x1];
b775516b
EC		 1527 u8 max_qp_cnt[0xa];
1528 u8 pkey_table_size[0x10];
1529
e281682b
SM		 1530 u8 vport_group_manager[0x1];
1531 u8 vhca_group_manager[0x1];
1532 u8 ib_virt[0x1];
1533 u8 eth_virt[0x1];
61c5b5c9 1534 u8 vnic_env_queue_counters[0x1];
e281682b
SM		 1535 u8 ets[0x1];
1536 u8 nic_flow_table[0x1];
0efc8562 1537 u8 eswitch_manager[0x1];
e72bd817 1538 u8 device_memory[0x1];
cfdcbcea
GP		 1539 u8 mcam_reg[0x1];
1540 u8 pcam_reg[0x1];
b775516b 1541 u8 local_ca_ack_delay[0x5];
4ce3bf2f 1542 u8 port_module_event[0x1];
58dcb60a 1543 u8 enhanced_error_q_counters[0x1];
7d5e1423 1544 u8 ports_check[0x1];
7b13558f 1545 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 1546 u8 disable_link_up[0x1];
1547 u8 beacon_led[0x1];
e281682b 1548 u8 port_type[0x2];
b775516b
EC		 1549 u8 num_ports[0x8];
1550
f9a1ef72
EE		 1551 u8 reserved_at_1c0[0x1];
1552 u8 pps[0x1];
1553 u8 pps_modify[0x1];
b775516b 1554 u8 log_max_msg[0x5];
e1c9c62b 1555 u8 reserved_at_1c8[0x4];
4f3961ee 1556 u8 max_tc[0x4];
1865ea9a 1557 u8 temp_warn_event[0x1];
7486216b 1558 u8 dcbx[0x1];
246ac981
MG		 1559 u8 general_notification_event[0x1];
1560 u8 reserved_at_1d3[0x2];
e29341fb 1561 u8 fpga[0x1];
928cfe87
TT		 1562 u8 rol_s[0x1];
1563 u8 rol_g[0x1];
e1c9c62b 1564 u8 reserved_at_1d8[0x1];
928cfe87
TT		 1565 u8 wol_s[0x1];
1566 u8 wol_g[0x1];
1567 u8 wol_a[0x1];
1568 u8 wol_b[0x1];
1569 u8 wol_m[0x1];
1570 u8 wol_u[0x1];
1571 u8 wol_p[0x1];
b775516b
EC		 1572
1573 u8 stat_rate_support[0x10];
3df01077
MS		 1574 u8 reserved_at_1f0[0x1];
1575 u8 pci_sync_for_fw_update_event[0x1];
cfc1a89e
MG		 1576 u8 reserved_at_1f2[0x6];
1577 u8 init2_lag_tx_port_affinity[0x1];
1578 u8 reserved_at_1fa[0x3];
e281682b 1579 u8 cqe_version[0x4];
b775516b 1580
e281682b 1581 u8 compact_address_vector[0x1];
7d5e1423 1582 u8 striding_rq[0x1];
500a3d0d
ES		 1583 u8 reserved_at_202[0x1];
1584 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 1585 u8 ipoib_basic_offloads[0x1];
c8d75a98
MD		 1586 u8 reserved_at_205[0x1];
1587 u8 repeated_block_disabled[0x1];
1588 u8 umr_modify_entity_size_disabled[0x1];
1589 u8 umr_modify_atomic_disabled[0x1];
1590 u8 umr_indirect_mkey_disabled[0x1];
1410a90a 1591 u8 umr_fence[0x2];
94a04d1d
YC		 1592 u8 dc_req_scat_data_cqe[0x1];
1593 u8 reserved_at_20d[0x2];
e281682b 1594 u8 drain_sigerr[0x1];
b775516b
EC		 1595 u8 cmdif_checksum[0x2];
1596 u8 sigerr_cqe[0x1];
e1c9c62b 1597 u8 reserved_at_213[0x1];
b775516b
EC		 1598 u8 wq_signature[0x1];
1599 u8 sctr_data_cqe[0x1];
e1c9c62b 1600 u8 reserved_at_216[0x1];
b775516b
EC		 1601 u8 sho[0x1];
1602 u8 tph[0x1];
1603 u8 rf[0x1];
e281682b 1604 u8 dct[0x1];
7486216b 1605 u8 qos[0x1];
e281682b 1606 u8 eth_net_offloads[0x1];
b775516b
EC		 1607 u8 roce[0x1];
1608 u8 atomic[0x1];
e1c9c62b 1609 u8 reserved_at_21f[0x1];
b775516b
EC		 1610
1611 u8 cq_oi[0x1];
1612 u8 cq_resize[0x1];
1613 u8 cq_moderation[0x1];
e1c9c62b 1614 u8 reserved_at_223[0x3];
e281682b 1615 u8 cq_eq_remap[0x1];
b775516b
EC		 1616 u8 pg[0x1];
1617 u8 block_lb_mc[0x1];
e1c9c62b 1618 u8 reserved_at_229[0x1];
e281682b 1619 u8 scqe_break_moderation[0x1];
7d5e1423 1620 u8 cq_period_start_from_cqe[0x1];
b775516b 1621 u8 cd[0x1];
e1c9c62b 1622 u8 reserved_at_22d[0x1];
b775516b 1623 u8 apm[0x1];
3f0393a5 1624 u8 vector_calc[0x1];
7d5e1423 1625 u8 umr_ptr_rlky[0x1];
d2370e0a 1626 u8 imaicl[0x1];
3fd3c80a
DG		 1627 u8 qp_packet_based[0x1];
1628 u8 reserved_at_233[0x3];
b775516b
EC		 1629 u8 qkv[0x1];
1630 u8 pkv[0x1];
b11a4f9c
HE		 1631 u8 set_deth_sqpn[0x1];
1632 u8 reserved_at_239[0x3];
b775516b
EC		 1633 u8 xrc[0x1];
1634 u8 ud[0x1];
1635 u8 uc[0x1];
1636 u8 rc[0x1];
1637
a6d51b68
EC		 1638 u8 uar_4k[0x1];
1639 u8 reserved_at_241[0x9];
b775516b 1640 u8 uar_sz[0x6];
425a563a
MG		 1641 u8 port_selection_cap[0x1];
1642 u8 reserved_at_248[0x1];
e13cd45d
EC		 1643 u8 umem_uid_0[0x1];
1644 u8 reserved_at_250[0x5];
b775516b
EC		 1645 u8 log_pg_sz[0x8];
1646
1647 u8 bf[0x1];
0dbc6fe0 1648 u8 driver_version[0x1];
e281682b 1649 u8 pad_tx_eth_packet[0x1];
4dca6509
MG		 1650 u8 reserved_at_263[0x3];
1651 u8 mkey_by_name[0x1];
1652 u8 reserved_at_267[0x4];
1653
b775516b 1654 u8 log_bf_reg_size[0x5];
84df61eb 1655
7c4b1ab9
MZ		 1656 u8 reserved_at_270[0x6];
1657 u8 lag_dct[0x2];
1eba383f 1658 u8 lag_tx_port_affinity[0x1];
c3e666f1
MB		 1659 u8 lag_native_fdb_selection[0x1];
1660 u8 reserved_at_27a[0x1];
84df61eb
AH		 1661 u8 lag_master[0x1];
1662 u8 num_lag_ports[0x4];
b775516b 1663
e1c9c62b 1664 u8 reserved_at_280[0x10];
b775516b
EC		 1665 u8 max_wqe_sz_sq[0x10];
1666
e1c9c62b 1667 u8 reserved_at_2a0[0x10];
b775516b
EC		 1668 u8 max_wqe_sz_rq[0x10];
1669
a8ffcc74 1670 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 1671 u8 max_wqe_sz_sq_dc[0x10];
1672
e1c9c62b 1673 u8 reserved_at_2e0[0x7];
b775516b
EC		 1674 u8 max_qp_mcg[0x19];
1675
8536a6bf
GT		 1676 u8 reserved_at_300[0x10];
1677 u8 flow_counter_bulk_alloc[0x8];
b775516b
EC		 1678 u8 log_max_mcg[0x8];
1679
e1c9c62b 1680 u8 reserved_at_320[0x3];
e281682b 1681 u8 log_max_transport_domain[0x5];
e1c9c62b 1682 u8 reserved_at_328[0x3];
b775516b 1683 u8 log_max_pd[0x5];
e1c9c62b 1684 u8 reserved_at_330[0xb];
b775516b
EC		 1685 u8 log_max_xrcd[0x5];
1686
5c298143 1687 u8 nic_receive_steering_discard[0x1];
aaabd078
MS		 1688 u8 receive_discard_vport_down[0x1];
1689 u8 transmit_discard_vport_down[0x1];
3e94e61b
SM		 1690 u8 eq_overrun_count[0x1];
1691 u8 reserved_at_344[0x1];
1692 u8 invalid_command_count[0x1];
1693 u8 quota_exceeded_count[0x1];
1694 u8 reserved_at_347[0x1];
a351a1b0 1695 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 1696 u8 max_flow_counter_15_0[0x10];
a351a1b0 1697
b775516b 1698
e1c9c62b 1699 u8 reserved_at_360[0x3];
b775516b 1700 u8 log_max_rq[0x5];
e1c9c62b 1701 u8 reserved_at_368[0x3];
b775516b 1702 u8 log_max_sq[0x5];
e1c9c62b 1703 u8 reserved_at_370[0x3];
b775516b 1704 u8 log_max_tir[0x5];
e1c9c62b 1705 u8 reserved_at_378[0x3];
b775516b
EC		 1706 u8 log_max_tis[0x5];
1707
e281682b 1708 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1709 u8 reserved_at_381[0x2];
e281682b 1710 u8 log_max_rmp[0x5];
e1c9c62b 1711 u8 reserved_at_388[0x3];
e281682b 1712 u8 log_max_rqt[0x5];
e1c9c62b 1713 u8 reserved_at_390[0x3];
e281682b 1714 u8 log_max_rqt_size[0x5];
e1c9c62b 1715 u8 reserved_at_398[0x3];
b775516b
EC		 1716 u8 log_max_tis_per_sq[0x5];
1717
619a8f2a 1718 u8 ext_stride_num_range[0x1];
fbfa97b4 1719 u8 roce_rw_supported[0x1];
685b1afd 1720 u8 log_max_current_uc_list_wr_supported[0x1];
e281682b 1721 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1722 u8 reserved_at_3a8[0x3];
e281682b 1723 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1724 u8 reserved_at_3b0[0x3];
e281682b 1725 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1726 u8 reserved_at_3b8[0x3];
e281682b
SM		 1727 u8 log_min_stride_sz_sq[0x5];
1728
40817cdb
OG		 1729 u8 hairpin[0x1];
1730 u8 reserved_at_3c1[0x2];
1731 u8 log_max_hairpin_queues[0x5];
1732 u8 reserved_at_3c8[0x3];
1733 u8 log_max_hairpin_wq_data_sz[0x5];
4d533e0f
OG		 1734 u8 reserved_at_3d0[0x3];
1735 u8 log_max_hairpin_num_packets[0x5];
1736 u8 reserved_at_3d8[0x3];
e281682b
SM		 1737 u8 log_max_wq_sz[0x5];
1738
54f0a411 1739 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1740 u8 disable_local_lb_uc[0x1];
1741 u8 disable_local_lb_mc[0x1];
40817cdb 1742 u8 log_min_hairpin_wq_data_sz[0x5];
349125ba
PP		 1743 u8 reserved_at_3e8[0x2];
1744 u8 vhca_state[0x1];
54f0a411 1745 u8 log_max_vlan_list[0x5];
e1c9c62b 1746 u8 reserved_at_3f0[0x3];
54f0a411 1747 u8 log_max_current_mc_list[0x5];
e1c9c62b 1748 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1749 u8 log_max_current_uc_list[0x5];
1750
38b7ca92
YH		 1751 u8 general_obj_types[0x40];
1752
a6a217dd
AL		 1753 u8 sq_ts_format[0x2];
1754 u8 rq_ts_format[0x2];
d421e466
YK		 1755 u8 steering_format_version[0x4];
1756 u8 create_qp_start_hint[0x18];
342ac844 1757
61c00cca 1758 u8 reserved_at_460[0x3];
6e3722ba 1759 u8 log_max_uctx[0x5];
2b58f6d9
RS		 1760 u8 reserved_at_468[0x2];
1761 u8 ipsec_offload[0x1];
6e3722ba 1762 u8 log_max_umem[0x5];
342ac844 1763 u8 max_num_eqs[0x10];
54f0a411 1764
61c00cca
TT		 1765 u8 reserved_at_480[0x1];
1766 u8 tls_tx[0x1];
ee5cdf7a 1767 u8 tls_rx[0x1];
e281682b 1768 u8 log_max_l2_table[0x5];
e1c9c62b 1769 u8 reserved_at_488[0x8];
b775516b
EC		 1770 u8 log_uar_page_sz[0x10];
1771
e1c9c62b 1772 u8 reserved_at_4a0[0x20];
048ccca8 1773 u8 device_frequency_mhz[0x20];
b0844444 1774 u8 device_frequency_khz[0x20];
e1c9c62b 1775
a6d51b68
EC		 1776 u8 reserved_at_500[0x20];
1777 u8 num_of_uars_per_page[0x20];
e1c9c62b 1778
e818e255 1779 u8 flex_parser_protocols[0x20];
e1c9c62b 1780
b169e64a
YK		 1781 u8 max_geneve_tlv_options[0x8];
1782 u8 reserved_at_568[0x3];
1783 u8 max_geneve_tlv_option_data_len[0x5];
a1be74c5
YH		 1784 u8 reserved_at_570[0x9];
1785 u8 adv_virtualization[0x1];
1786 u8 reserved_at_57a[0x6];
e1c9c62b 1787
96cd2dd6
LN		 1788 u8 reserved_at_580[0xb];
1789 u8 log_max_dci_stream_channels[0x5];
1790 u8 reserved_at_590[0x3];
1791 u8 log_max_dci_errored_streams[0x5];
1792 u8 reserved_at_598[0x8];
1793
cdcdce94
OL		 1794 u8 reserved_at_5a0[0x10];
1795 u8 enhanced_cqe_compression[0x1];
1796 u8 reserved_at_5b1[0x2];
a12ff35e
EBE		 1797 u8 log_max_dek[0x5];
1798 u8 reserved_at_5b8[0x4];
ab741b2e 1799 u8 mini_cqe_resp_stride_index[0x1];
0ff8e79c
GL		 1800 u8 cqe_128_always[0x1];
1801 u8 cqe_compression_128[0x1];
7d5e1423 1802 u8 cqe_compression[0x1];
b775516b 1803
7d5e1423
SM		 1804 u8 cqe_compression_timeout[0x10];
1805 u8 cqe_compression_max_num[0x10];
b775516b 1806
704cfecd
YK		 1807 u8 reserved_at_5e0[0x8];
1808 u8 flex_parser_id_gtpu_dw_0[0x4];
1809 u8 reserved_at_5ec[0x4];
7486216b
SM		 1810 u8 tag_matching[0x1];
1811 u8 rndv_offload_rc[0x1];
1812 u8 rndv_offload_dc[0x1];
1813 u8 log_tag_matching_list_sz[0x5];
7b13558f 1814 u8 reserved_at_5f8[0x3];
7486216b
SM		 1815 u8 log_max_xrq[0x5];
1816
32f69e4b
DJ		 1817 u8 affiliate_nic_vport_criteria[0x8];
1818 u8 native_port_num[0x8];
1819 u8 num_vhca_ports[0x8];
704cfecd
YK		 1820 u8 flex_parser_id_gtpu_teid[0x4];
1821 u8 reserved_at_61c[0x2];
32f69e4b 1822 u8 sw_owner_id[0x1];
9d43faac
YH		 1823 u8 reserved_at_61f[0x1];
1824
fd4572b3
ED		 1825 u8 max_num_of_monitor_counters[0x10];
1826 u8 num_ppcnt_monitor_counters[0x10];
1827
349125ba 1828 u8 max_num_sf[0x10];
fd4572b3
ED		 1829 u8 num_q_monitor_counters[0x10];
1830
1759d322
PP		 1831 u8 reserved_at_660[0x20];
1832
1833 u8 sf[0x1];
1834 u8 sf_set_partition[0x1];
1835 u8 reserved_at_682[0x1];
1836 u8 log_max_sf[0x5];
7232c132 1837 u8 apu[0x1];
adfdaff3
YH		 1838 u8 reserved_at_689[0x4];
1839 u8 migration[0x1];
1840 u8 reserved_at_68e[0x2];
1759d322
PP		 1841 u8 log_min_sf_size[0x8];
1842 u8 max_num_sf_partitions[0x8];
9d43faac
YH		 1843
1844 u8 uctx_cap[0x20];
1845
b169e64a
YK		 1846 u8 reserved_at_6c0[0x4];
1847 u8 flex_parser_id_geneve_tlv_option_0[0x4];
97b5484e
AV		 1848 u8 flex_parser_id_icmp_dw1[0x4];
1849 u8 flex_parser_id_icmp_dw0[0x4];
1850 u8 flex_parser_id_icmpv6_dw1[0x4];
1851 u8 flex_parser_id_icmpv6_dw0[0x4];
1852 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1853 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1854
e7e2519e 1855 u8 max_num_match_definer[0x10];
1759d322
PP		 1856 u8 sf_base_id[0x10];
1857
704cfecd
YK		 1858 u8 flex_parser_id_gtpu_dw_2[0x4];
1859 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
0b989c1e
LR		 1860 u8 num_total_dynamic_vf_msix[0x18];
1861 u8 reserved_at_720[0x14];
1862 u8 dynamic_msix_table_size[0xc];
1863 u8 reserved_at_740[0xc];
1864 u8 min_dynamic_vf_msix_table_size[0x4];
1865 u8 reserved_at_750[0x4];
1866 u8 max_dynamic_vf_msix_table_size[0xc];
1867
1868 u8 reserved_at_760[0x20];
1dd7382b 1869 u8 vhca_tunnel_commands[0x40];
e7e2519e 1870 u8 match_definer_format_supported[0x40];
b775516b
EC		 1871};
1872
67133eaa
YK		 1873struct mlx5_ifc_cmd_hca_cap_2_bits {
1874 u8 reserved_at_0[0xa0];
1875
1876 u8 max_reformat_insert_size[0x8];
1877 u8 max_reformat_insert_offset[0x8];
1878 u8 max_reformat_remove_size[0x8];
1879 u8 max_reformat_remove_offset[0x8];
1880
0372c546
YH		 1881 u8 reserved_at_c0[0x160];
1882
1883 u8 reserved_at_220[0x1];
1884 u8 sw_vhca_id_valid[0x1];
1885 u8 sw_vhca_id[0xe];
1886 u8 reserved_at_230[0x10];
1887
2e5e4185
AL		 1888 u8 reserved_at_240[0xb];
1889 u8 ts_cqe_metadata_size2wqe_counter[0x5];
1890 u8 reserved_at_250[0x10];
1891
1892 u8 reserved_at_260[0x5a0];
67133eaa
YK		 1893};
1894
d639af62
MB		 1895enum mlx5_ifc_flow_destination_type {
1896 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1897 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1898 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
1899 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1900 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
e281682b 1901};
b775516b 1902
f6f7d6b5
MG		 1903enum mlx5_flow_table_miss_action {
1904 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1905 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1906 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1907};
1908
e281682b
SM		 1909struct mlx5_ifc_dest_format_struct_bits {
1910 u8 destination_type[0x8];
1911 u8 destination_id[0x18];
1b115498 1912
b17f7fc1 1913 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1b115498
EB		 1914 u8 packet_reformat[0x1];
1915 u8 reserved_at_22[0xe];
b17f7fc1 1916 u8 destination_eswitch_owner_vhca_id[0x10];
e281682b
SM		 1917};
1918
9dc0b289 1919struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1920 u8 flow_counter_id[0x20];
9dc0b289
AV		 1921
1922 u8 reserved_at_20[0x20];
1923};
1924
1b115498
EB		 1925struct mlx5_ifc_extended_dest_format_bits {
1926 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1927
1928 u8 packet_reformat_id[0x20];
1929
1930 u8 reserved_at_60[0x20];
1931};
1932
9dc0b289 1933union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
6dfef396 1934 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
9dc0b289 1935 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
9dc0b289
AV		 1936};
1937
e281682b
SM		 1938struct mlx5_ifc_fte_match_param_bits {
1939 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1940
1941 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1942
1943 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1944
71c6e863
AL		 1945 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1946
b169e64a
YK		 1947 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1948
7da3ad6c
MS		 1949 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1950
0f2a6c3b
MS		 1951 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1952
1953 u8 reserved_at_e00[0x200];
b775516b
EC		 1954};
1955
e281682b
SM		 1956enum {
1957 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1958 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1959 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1960 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1961 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1962};
b775516b 1963
e281682b
SM		 1964struct mlx5_ifc_rx_hash_field_select_bits {
1965 u8 l3_prot_type[0x1];
1966 u8 l4_prot_type[0x1];
1967 u8 selected_fields[0x1e];
1968};
b775516b 1969
e281682b
SM		 1970enum {
1971 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1972 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1973};
1974
e281682b
SM		 1975enum {
1976 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1977 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1978};
1979
1980struct mlx5_ifc_wq_bits {
1981 u8 wq_type[0x4];
1982 u8 wq_signature[0x1];
1983 u8 end_padding_mode[0x2];
1984 u8 cd_slave[0x1];
b4ff3a36 1985 u8 reserved_at_8[0x18];
b775516b 1986
e281682b
SM		 1987 u8 hds_skip_first_sge[0x1];
1988 u8 log2_hds_buf_size[0x3];
b4ff3a36 1989 u8 reserved_at_24[0x7];
e281682b
SM		 1990 u8 page_offset[0x5];
1991 u8 lwm[0x10];
b775516b 1992
b4ff3a36 1993 u8 reserved_at_40[0x8];
e281682b
SM		 1994 u8 pd[0x18];
1995
b4ff3a36 1996 u8 reserved_at_60[0x8];
e281682b
SM		 1997 u8 uar_page[0x18];
1998
1999 u8 dbr_addr[0x40];
2000
2001 u8 hw_counter[0x20];
2002
2003 u8 sw_counter[0x20];
2004
b4ff3a36 2005 u8 reserved_at_100[0xc];
e281682b 2006 u8 log_wq_stride[0x4];
b4ff3a36 2007 u8 reserved_at_110[0x3];
e281682b 2008 u8 log_wq_pg_sz[0x5];
b4ff3a36 2009 u8 reserved_at_118[0x3];
e281682b
SM		 2010 u8 log_wq_sz[0x5];
2011
bd371975
LR		 2012 u8 dbr_umem_valid[0x1];
2013 u8 wq_umem_valid[0x1];
2014 u8 reserved_at_122[0x1];
4d533e0f
OG		 2015 u8 log_hairpin_num_packets[0x5];
2016 u8 reserved_at_128[0x3];
40817cdb 2017 u8 log_hairpin_data_sz[0x5];
40817cdb 2018
619a8f2a
TT		 2019 u8 reserved_at_130[0x4];
2020 u8 log_wqe_num_of_strides[0x4];
7d5e1423
SM		 2021 u8 two_byte_shift_en[0x1];
2022 u8 reserved_at_139[0x4];
2023 u8 log_wqe_stride_size[0x3];
2024
7025329d
BBI		 2025 u8 reserved_at_140[0x80];
2026
2027 u8 headers_mkey[0x20];
2028
2029 u8 shampo_enable[0x1];
2030 u8 reserved_at_1e1[0x4];
2031 u8 log_reservation_size[0x3];
2032 u8 reserved_at_1e8[0x5];
2033 u8 log_max_num_of_packets_per_reservation[0x3];
2034 u8 reserved_at_1f0[0x6];
2035 u8 log_headers_entry_size[0x2];
2036 u8 reserved_at_1f8[0x4];
2037 u8 log_headers_buffer_entry_num[0x4];
2038
2039 u8 reserved_at_200[0x400];
b775516b 2040
b6ca09cb 2041 struct mlx5_ifc_cmd_pas_bits pas[];
b775516b
EC		 2042};
2043
e281682b 2044struct mlx5_ifc_rq_num_bits {
b4ff3a36 2045 u8 reserved_at_0[0x8];
e281682b
SM		 2046 u8 rq_num[0x18];
2047};
b775516b 2048
e281682b 2049struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 2050 u8 reserved_at_0[0x10];
e281682b 2051 u8 mac_addr_47_32[0x10];
b775516b 2052
e281682b
SM		 2053 u8 mac_addr_31_0[0x20];
2054};
2055
c0046cf7 2056struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 2057 u8 reserved_at_0[0x14];
c0046cf7
SM		 2058 u8 vlan[0x0c];
2059
b4ff3a36 2060 u8 reserved_at_20[0x20];
c0046cf7
SM		 2061};
2062
e281682b 2063struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 2064 u8 reserved_at_0[0xa0];
e281682b
SM		 2065
2066 u8 min_time_between_cnps[0x20];
2067
b4ff3a36 2068 u8 reserved_at_c0[0x12];
e281682b 2069 u8 cnp_dscp[0x6];
4a2da0b8
PP		 2070 u8 reserved_at_d8[0x4];
2071 u8 cnp_prio_mode[0x1];
e281682b
SM		 2072 u8 cnp_802p_prio[0x3];
2073
b4ff3a36 2074 u8 reserved_at_e0[0x720];
e281682b
SM		 2075};
2076
2077struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 2078 u8 reserved_at_0[0x60];
e281682b 2079
b4ff3a36 2080 u8 reserved_at_60[0x4];
e281682b 2081 u8 clamp_tgt_rate[0x1];
b4ff3a36 2082 u8 reserved_at_65[0x3];
e281682b 2083 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 2084 u8 reserved_at_69[0x17];
e281682b 2085
b4ff3a36 2086 u8 reserved_at_80[0x20];
e281682b
SM		 2087
2088 u8 rpg_time_reset[0x20];
2089
2090 u8 rpg_byte_reset[0x20];
2091
2092 u8 rpg_threshold[0x20];
2093
2094 u8 rpg_max_rate[0x20];
2095
2096 u8 rpg_ai_rate[0x20];
2097
2098 u8 rpg_hai_rate[0x20];
2099
2100 u8 rpg_gd[0x20];
2101
2102 u8 rpg_min_dec_fac[0x20];
2103
2104 u8 rpg_min_rate[0x20];
2105
b4ff3a36 2106 u8 reserved_at_1c0[0xe0];
e281682b
SM		 2107
2108 u8 rate_to_set_on_first_cnp[0x20];
2109
2110 u8 dce_tcp_g[0x20];
2111
2112 u8 dce_tcp_rtt[0x20];
2113
2114 u8 rate_reduce_monitor_period[0x20];
2115
b4ff3a36 2116 u8 reserved_at_320[0x20];
e281682b
SM		 2117
2118 u8 initial_alpha_value[0x20];
2119
b4ff3a36 2120 u8 reserved_at_360[0x4a0];
e281682b
SM		 2121};
2122
2123struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 2124 u8 reserved_at_0[0x80];
e281682b
SM		 2125
2126 u8 rppp_max_rps[0x20];
2127
2128 u8 rpg_time_reset[0x20];
2129
2130 u8 rpg_byte_reset[0x20];
2131
2132 u8 rpg_threshold[0x20];
2133
2134 u8 rpg_max_rate[0x20];
2135
2136 u8 rpg_ai_rate[0x20];
2137
2138 u8 rpg_hai_rate[0x20];
2139
2140 u8 rpg_gd[0x20];
2141
2142 u8 rpg_min_dec_fac[0x20];
2143
2144 u8 rpg_min_rate[0x20];
2145
b4ff3a36 2146 u8 reserved_at_1c0[0x640];
e281682b
SM		 2147};
2148
2149enum {
2150 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2151 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2152 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2153};
2154
2155struct mlx5_ifc_resize_field_select_bits {
2156 u8 resize_field_select[0x20];
2157};
2158
609b8272
AL		 2159struct mlx5_ifc_resource_dump_bits {
2160 u8 more_dump[0x1];
2161 u8 inline_dump[0x1];
2162 u8 reserved_at_2[0xa];
2163 u8 seq_num[0x4];
2164 u8 segment_type[0x10];
2165
2166 u8 reserved_at_20[0x10];
2167 u8 vhca_id[0x10];
2168
2169 u8 index1[0x20];
2170
2171 u8 index2[0x20];
2172
2173 u8 num_of_obj1[0x10];
2174 u8 num_of_obj2[0x10];
2175
2176 u8 reserved_at_a0[0x20];
2177
2178 u8 device_opaque[0x40];
2179
2180 u8 mkey[0x20];
2181
2182 u8 size[0x20];
2183
2184 u8 address[0x40];
2185
2186 u8 inline_data[52][0x20];
2187};
2188
2189struct mlx5_ifc_resource_dump_menu_record_bits {
2190 u8 reserved_at_0[0x4];
2191 u8 num_of_obj2_supports_active[0x1];
2192 u8 num_of_obj2_supports_all[0x1];
2193 u8 must_have_num_of_obj2[0x1];
2194 u8 support_num_of_obj2[0x1];
2195 u8 num_of_obj1_supports_active[0x1];
2196 u8 num_of_obj1_supports_all[0x1];
2197 u8 must_have_num_of_obj1[0x1];
2198 u8 support_num_of_obj1[0x1];
2199 u8 must_have_index2[0x1];
2200 u8 support_index2[0x1];
2201 u8 must_have_index1[0x1];
2202 u8 support_index1[0x1];
2203 u8 segment_type[0x10];
2204
2205 u8 segment_name[4][0x20];
2206
2207 u8 index1_name[4][0x20];
2208
2209 u8 index2_name[4][0x20];
2210};
2211
2212struct mlx5_ifc_resource_dump_segment_header_bits {
2213 u8 length_dw[0x10];
2214 u8 segment_type[0x10];
2215};
2216
2217struct mlx5_ifc_resource_dump_command_segment_bits {
2218 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2219
2220 u8 segment_called[0x10];
2221 u8 vhca_id[0x10];
2222
2223 u8 index1[0x20];
2224
2225 u8 index2[0x20];
2226
2227 u8 num_of_obj1[0x10];
2228 u8 num_of_obj2[0x10];
2229};
2230
2231struct mlx5_ifc_resource_dump_error_segment_bits {
2232 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2233
2234 u8 reserved_at_20[0x10];
2235 u8 syndrome_id[0x10];
2236
2237 u8 reserved_at_40[0x40];
2238
2239 u8 error[8][0x20];
2240};
2241
2242struct mlx5_ifc_resource_dump_info_segment_bits {
2243 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2244
2245 u8 reserved_at_20[0x18];
2246 u8 dump_version[0x8];
2247
2248 u8 hw_version[0x20];
2249
2250 u8 fw_version[0x20];
2251};
2252
2253struct mlx5_ifc_resource_dump_menu_segment_bits {
2254 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2255
2256 u8 reserved_at_20[0x10];
2257 u8 num_of_records[0x10];
2258
b6ca09cb 2259 struct mlx5_ifc_resource_dump_menu_record_bits record[];
609b8272
AL		 2260};
2261
2262struct mlx5_ifc_resource_dump_resource_segment_bits {
2263 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2264
2265 u8 reserved_at_20[0x20];
2266
2267 u8 index1[0x20];
2268
2269 u8 index2[0x20];
2270
b6ca09cb 2271 u8 payload[][0x20];
609b8272
AL		 2272};
2273
2274struct mlx5_ifc_resource_dump_terminate_segment_bits {
2275 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2276};
2277
2278struct mlx5_ifc_menu_resource_dump_response_bits {
2279 struct mlx5_ifc_resource_dump_info_segment_bits info;
2280 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2281 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2282 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2283};
2284
e281682b
SM		 2285enum {
2286 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2287 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2288 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2289 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2290};
2291
2292struct mlx5_ifc_modify_field_select_bits {
2293 u8 modify_field_select[0x20];
2294};
2295
2296struct mlx5_ifc_field_select_r_roce_np_bits {
2297 u8 field_select_r_roce_np[0x20];
2298};
2299
2300struct mlx5_ifc_field_select_r_roce_rp_bits {
2301 u8 field_select_r_roce_rp[0x20];
2302};
2303
2304enum {
2305 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2306 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2307 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2308 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2309 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2310 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2311 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2312 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2315};
2316
2317struct mlx5_ifc_field_select_802_1qau_rp_bits {
2318 u8 field_select_8021qaurp[0x20];
2319};
2320
2321struct mlx5_ifc_phys_layer_cntrs_bits {
2322 u8 time_since_last_clear_high[0x20];
2323
2324 u8 time_since_last_clear_low[0x20];
2325
2326 u8 symbol_errors_high[0x20];
2327
2328 u8 symbol_errors_low[0x20];
2329
2330 u8 sync_headers_errors_high[0x20];
2331
2332 u8 sync_headers_errors_low[0x20];
2333
2334 u8 edpl_bip_errors_lane0_high[0x20];
2335
2336 u8 edpl_bip_errors_lane0_low[0x20];
2337
2338 u8 edpl_bip_errors_lane1_high[0x20];
2339
2340 u8 edpl_bip_errors_lane1_low[0x20];
2341
2342 u8 edpl_bip_errors_lane2_high[0x20];
2343
2344 u8 edpl_bip_errors_lane2_low[0x20];
2345
2346 u8 edpl_bip_errors_lane3_high[0x20];
2347
2348 u8 edpl_bip_errors_lane3_low[0x20];
2349
2350 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2351
2352 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2353
2354 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2355
2356 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2357
2358 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2359
2360 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2361
2362 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2363
2364 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2365
2366 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2367
2368 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2369
2370 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2371
2372 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2373
2374 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2375
2376 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2377
2378 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2379
2380 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2381
2382 u8 rs_fec_corrected_blocks_high[0x20];
2383
2384 u8 rs_fec_corrected_blocks_low[0x20];
2385
2386 u8 rs_fec_uncorrectable_blocks_high[0x20];
2387
2388 u8 rs_fec_uncorrectable_blocks_low[0x20];
2389
2390 u8 rs_fec_no_errors_blocks_high[0x20];
2391
2392 u8 rs_fec_no_errors_blocks_low[0x20];
2393
2394 u8 rs_fec_single_error_blocks_high[0x20];
2395
2396 u8 rs_fec_single_error_blocks_low[0x20];
2397
2398 u8 rs_fec_corrected_symbols_total_high[0x20];
2399
2400 u8 rs_fec_corrected_symbols_total_low[0x20];
2401
2402 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2403
2404 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2405
2406 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2407
2408 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2409
2410 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2411
2412 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2413
2414 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2415
2416 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2417
2418 u8 link_down_events[0x20];
2419
2420 u8 successful_recovery_events[0x20];
2421
b4ff3a36 2422 u8 reserved_at_640[0x180];
e281682b
SM		 2423};
2424
d8dc0508
GP		 2425struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2426 u8 time_since_last_clear_high[0x20];
2427
2428 u8 time_since_last_clear_low[0x20];
2429
2430 u8 phy_received_bits_high[0x20];
2431
2432 u8 phy_received_bits_low[0x20];
2433
2434 u8 phy_symbol_errors_high[0x20];
2435
2436 u8 phy_symbol_errors_low[0x20];
2437
2438 u8 phy_corrected_bits_high[0x20];
2439
2440 u8 phy_corrected_bits_low[0x20];
2441
2442 u8 phy_corrected_bits_lane0_high[0x20];
2443
2444 u8 phy_corrected_bits_lane0_low[0x20];
2445
2446 u8 phy_corrected_bits_lane1_high[0x20];
2447
2448 u8 phy_corrected_bits_lane1_low[0x20];
2449
2450 u8 phy_corrected_bits_lane2_high[0x20];
2451
2452 u8 phy_corrected_bits_lane2_low[0x20];
2453
2454 u8 phy_corrected_bits_lane3_high[0x20];
2455
2456 u8 phy_corrected_bits_lane3_low[0x20];
2457
2458 u8 reserved_at_200[0x5c0];
2459};
2460
1c64bf6f
MY		 2461struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2462 u8 symbol_error_counter[0x10];
2463
2464 u8 link_error_recovery_counter[0x8];
2465
2466 u8 link_downed_counter[0x8];
2467
2468 u8 port_rcv_errors[0x10];
2469
2470 u8 port_rcv_remote_physical_errors[0x10];
2471
2472 u8 port_rcv_switch_relay_errors[0x10];
2473
2474 u8 port_xmit_discards[0x10];
2475
2476 u8 port_xmit_constraint_errors[0x8];
2477
2478 u8 port_rcv_constraint_errors[0x8];
2479
2480 u8 reserved_at_70[0x8];
2481
2482 u8 link_overrun_errors[0x8];
2483
2484 u8 reserved_at_80[0x10];
2485
2486 u8 vl_15_dropped[0x10];
2487
133bea04
TW		 2488 u8 reserved_at_a0[0x80];
2489
2490 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 2491};
2492
948d3f90 2493struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
e281682b
SM		 2494 u8 transmit_queue_high[0x20];
2495
2496 u8 transmit_queue_low[0x20];
2497
948d3f90
AL		 2498 u8 no_buffer_discard_uc_high[0x20];
2499
2500 u8 no_buffer_discard_uc_low[0x20];
2501
2502 u8 reserved_at_80[0x740];
2503};
2504
2505struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2506 u8 wred_discard_high[0x20];
2507
2508 u8 wred_discard_low[0x20];
2509
2510 u8 ecn_marked_tc_high[0x20];
2511
2512 u8 ecn_marked_tc_low[0x20];
2513
2514 u8 reserved_at_80[0x740];
e281682b
SM		 2515};
2516
2517struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2518 u8 rx_octets_high[0x20];
2519
2520 u8 rx_octets_low[0x20];
2521
b4ff3a36 2522 u8 reserved_at_40[0xc0];
e281682b
SM		 2523
2524 u8 rx_frames_high[0x20];
2525
2526 u8 rx_frames_low[0x20];
2527
2528 u8 tx_octets_high[0x20];
2529
2530 u8 tx_octets_low[0x20];
2531
b4ff3a36 2532 u8 reserved_at_180[0xc0];
e281682b
SM		 2533
2534 u8 tx_frames_high[0x20];
2535
2536 u8 tx_frames_low[0x20];
2537
2538 u8 rx_pause_high[0x20];
2539
2540 u8 rx_pause_low[0x20];
2541
2542 u8 rx_pause_duration_high[0x20];
2543
2544 u8 rx_pause_duration_low[0x20];
2545
2546 u8 tx_pause_high[0x20];
2547
2548 u8 tx_pause_low[0x20];
2549
2550 u8 tx_pause_duration_high[0x20];
2551
2552 u8 tx_pause_duration_low[0x20];
2553
2554 u8 rx_pause_transition_high[0x20];
2555
2556 u8 rx_pause_transition_low[0x20];
2557
827a8cb2
AL		 2558 u8 rx_discards_high[0x20];
2559
2560 u8 rx_discards_low[0x20];
2fcb12df
IK		 2561
2562 u8 device_stall_minor_watermark_cnt_high[0x20];
2563
2564 u8 device_stall_minor_watermark_cnt_low[0x20];
2565
2566 u8 device_stall_critical_watermark_cnt_high[0x20];
2567
2568 u8 device_stall_critical_watermark_cnt_low[0x20];
2569
2570 u8 reserved_at_480[0x340];
e281682b
SM		 2571};
2572
2573struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2574 u8 port_transmit_wait_high[0x20];
2575
2576 u8 port_transmit_wait_low[0x20];
2577
2dba0797
GP		 2578 u8 reserved_at_40[0x100];
2579
2580 u8 rx_buffer_almost_full_high[0x20];
2581
2582 u8 rx_buffer_almost_full_low[0x20];
2583
2584 u8 rx_buffer_full_high[0x20];
2585
2586 u8 rx_buffer_full_low[0x20];
2587
0af5107c
TB		 2588 u8 rx_icrc_encapsulated_high[0x20];
2589
2590 u8 rx_icrc_encapsulated_low[0x20];
2591
2592 u8 reserved_at_200[0x5c0];
e281682b
SM		 2593};
2594
2595struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2596 u8 dot3stats_alignment_errors_high[0x20];
2597
2598 u8 dot3stats_alignment_errors_low[0x20];
2599
2600 u8 dot3stats_fcs_errors_high[0x20];
2601
2602 u8 dot3stats_fcs_errors_low[0x20];
2603
2604 u8 dot3stats_single_collision_frames_high[0x20];
2605
2606 u8 dot3stats_single_collision_frames_low[0x20];
2607
2608 u8 dot3stats_multiple_collision_frames_high[0x20];
2609
2610 u8 dot3stats_multiple_collision_frames_low[0x20];
2611
2612 u8 dot3stats_sqe_test_errors_high[0x20];
2613
2614 u8 dot3stats_sqe_test_errors_low[0x20];
2615
2616 u8 dot3stats_deferred_transmissions_high[0x20];
2617
2618 u8 dot3stats_deferred_transmissions_low[0x20];
2619
2620 u8 dot3stats_late_collisions_high[0x20];
2621
2622 u8 dot3stats_late_collisions_low[0x20];
2623
2624 u8 dot3stats_excessive_collisions_high[0x20];
2625
2626 u8 dot3stats_excessive_collisions_low[0x20];
2627
2628 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2629
2630 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2631
2632 u8 dot3stats_carrier_sense_errors_high[0x20];
2633
2634 u8 dot3stats_carrier_sense_errors_low[0x20];
2635
2636 u8 dot3stats_frame_too_longs_high[0x20];
2637
2638 u8 dot3stats_frame_too_longs_low[0x20];
2639
2640 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2641
2642 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2643
2644 u8 dot3stats_symbol_errors_high[0x20];
2645
2646 u8 dot3stats_symbol_errors_low[0x20];
2647
2648 u8 dot3control_in_unknown_opcodes_high[0x20];
2649
2650 u8 dot3control_in_unknown_opcodes_low[0x20];
2651
2652 u8 dot3in_pause_frames_high[0x20];
2653
2654 u8 dot3in_pause_frames_low[0x20];
2655
2656 u8 dot3out_pause_frames_high[0x20];
2657
2658 u8 dot3out_pause_frames_low[0x20];
2659
b4ff3a36 2660 u8 reserved_at_400[0x3c0];
e281682b
SM		 2661};
2662
2663struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2664 u8 ether_stats_drop_events_high[0x20];
2665
2666 u8 ether_stats_drop_events_low[0x20];
2667
2668 u8 ether_stats_octets_high[0x20];
2669
2670 u8 ether_stats_octets_low[0x20];
2671
2672 u8 ether_stats_pkts_high[0x20];
2673
2674 u8 ether_stats_pkts_low[0x20];
2675
2676 u8 ether_stats_broadcast_pkts_high[0x20];
2677
2678 u8 ether_stats_broadcast_pkts_low[0x20];
2679
2680 u8 ether_stats_multicast_pkts_high[0x20];
2681
2682 u8 ether_stats_multicast_pkts_low[0x20];
2683
2684 u8 ether_stats_crc_align_errors_high[0x20];
2685
2686 u8 ether_stats_crc_align_errors_low[0x20];
2687
2688 u8 ether_stats_undersize_pkts_high[0x20];
2689
2690 u8 ether_stats_undersize_pkts_low[0x20];
2691
2692 u8 ether_stats_oversize_pkts_high[0x20];
2693
2694 u8 ether_stats_oversize_pkts_low[0x20];
2695
2696 u8 ether_stats_fragments_high[0x20];
2697
2698 u8 ether_stats_fragments_low[0x20];
2699
2700 u8 ether_stats_jabbers_high[0x20];
2701
2702 u8 ether_stats_jabbers_low[0x20];
2703
2704 u8 ether_stats_collisions_high[0x20];
2705
2706 u8 ether_stats_collisions_low[0x20];
2707
2708 u8 ether_stats_pkts64octets_high[0x20];
2709
2710 u8 ether_stats_pkts64octets_low[0x20];
2711
2712 u8 ether_stats_pkts65to127octets_high[0x20];
2713
2714 u8 ether_stats_pkts65to127octets_low[0x20];
2715
2716 u8 ether_stats_pkts128to255octets_high[0x20];
2717
2718 u8 ether_stats_pkts128to255octets_low[0x20];
2719
2720 u8 ether_stats_pkts256to511octets_high[0x20];
2721
2722 u8 ether_stats_pkts256to511octets_low[0x20];
2723
2724 u8 ether_stats_pkts512to1023octets_high[0x20];
2725
2726 u8 ether_stats_pkts512to1023octets_low[0x20];
2727
2728 u8 ether_stats_pkts1024to1518octets_high[0x20];
2729
2730 u8 ether_stats_pkts1024to1518octets_low[0x20];
2731
2732 u8 ether_stats_pkts1519to2047octets_high[0x20];
2733
2734 u8 ether_stats_pkts1519to2047octets_low[0x20];
2735
2736 u8 ether_stats_pkts2048to4095octets_high[0x20];
2737
2738 u8 ether_stats_pkts2048to4095octets_low[0x20];
2739
2740 u8 ether_stats_pkts4096to8191octets_high[0x20];
2741
2742 u8 ether_stats_pkts4096to8191octets_low[0x20];
2743
2744 u8 ether_stats_pkts8192to10239octets_high[0x20];
2745
2746 u8 ether_stats_pkts8192to10239octets_low[0x20];
2747
b4ff3a36 2748 u8 reserved_at_540[0x280];
e281682b
SM		 2749};
2750
2751struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2752 u8 if_in_octets_high[0x20];
2753
2754 u8 if_in_octets_low[0x20];
2755
2756 u8 if_in_ucast_pkts_high[0x20];
2757
2758 u8 if_in_ucast_pkts_low[0x20];
2759
2760 u8 if_in_discards_high[0x20];
2761
2762 u8 if_in_discards_low[0x20];
2763
2764 u8 if_in_errors_high[0x20];
2765
2766 u8 if_in_errors_low[0x20];
2767
2768 u8 if_in_unknown_protos_high[0x20];
2769
2770 u8 if_in_unknown_protos_low[0x20];
2771
2772 u8 if_out_octets_high[0x20];
2773
2774 u8 if_out_octets_low[0x20];
2775
2776 u8 if_out_ucast_pkts_high[0x20];
2777
2778 u8 if_out_ucast_pkts_low[0x20];
2779
2780 u8 if_out_discards_high[0x20];
2781
2782 u8 if_out_discards_low[0x20];
2783
2784 u8 if_out_errors_high[0x20];
2785
2786 u8 if_out_errors_low[0x20];
2787
2788 u8 if_in_multicast_pkts_high[0x20];
2789
2790 u8 if_in_multicast_pkts_low[0x20];
2791
2792 u8 if_in_broadcast_pkts_high[0x20];
2793
2794 u8 if_in_broadcast_pkts_low[0x20];
2795
2796 u8 if_out_multicast_pkts_high[0x20];
2797
2798 u8 if_out_multicast_pkts_low[0x20];
2799
2800 u8 if_out_broadcast_pkts_high[0x20];
2801
2802 u8 if_out_broadcast_pkts_low[0x20];
2803
b4ff3a36 2804 u8 reserved_at_340[0x480];
e281682b
SM		 2805};
2806
2807struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2808 u8 a_frames_transmitted_ok_high[0x20];
2809
2810 u8 a_frames_transmitted_ok_low[0x20];
2811
2812 u8 a_frames_received_ok_high[0x20];
2813
2814 u8 a_frames_received_ok_low[0x20];
2815
2816 u8 a_frame_check_sequence_errors_high[0x20];
2817
2818 u8 a_frame_check_sequence_errors_low[0x20];
2819
2820 u8 a_alignment_errors_high[0x20];
2821
2822 u8 a_alignment_errors_low[0x20];
2823
2824 u8 a_octets_transmitted_ok_high[0x20];
2825
2826 u8 a_octets_transmitted_ok_low[0x20];
2827
2828 u8 a_octets_received_ok_high[0x20];
2829
2830 u8 a_octets_received_ok_low[0x20];
2831
2832 u8 a_multicast_frames_xmitted_ok_high[0x20];
2833
2834 u8 a_multicast_frames_xmitted_ok_low[0x20];
2835
2836 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2837
2838 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2839
2840 u8 a_multicast_frames_received_ok_high[0x20];
2841
2842 u8 a_multicast_frames_received_ok_low[0x20];
2843
2844 u8 a_broadcast_frames_received_ok_high[0x20];
2845
2846 u8 a_broadcast_frames_received_ok_low[0x20];
2847
2848 u8 a_in_range_length_errors_high[0x20];
2849
2850 u8 a_in_range_length_errors_low[0x20];
2851
2852 u8 a_out_of_range_length_field_high[0x20];
2853
2854 u8 a_out_of_range_length_field_low[0x20];
2855
2856 u8 a_frame_too_long_errors_high[0x20];
2857
2858 u8 a_frame_too_long_errors_low[0x20];
2859
2860 u8 a_symbol_error_during_carrier_high[0x20];
2861
2862 u8 a_symbol_error_during_carrier_low[0x20];
2863
2864 u8 a_mac_control_frames_transmitted_high[0x20];
2865
2866 u8 a_mac_control_frames_transmitted_low[0x20];
2867
2868 u8 a_mac_control_frames_received_high[0x20];
2869
2870 u8 a_mac_control_frames_received_low[0x20];
2871
2872 u8 a_unsupported_opcodes_received_high[0x20];
2873
2874 u8 a_unsupported_opcodes_received_low[0x20];
2875
2876 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2877
2878 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2879
2880 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2881
2882 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2883
b4ff3a36 2884 u8 reserved_at_4c0[0x300];
e281682b
SM		 2885};
2886
8ed1a630
GP		 2887struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2888 u8 life_time_counter_high[0x20];
2889
2890 u8 life_time_counter_low[0x20];
2891
2892 u8 rx_errors[0x20];
2893
2894 u8 tx_errors[0x20];
2895
2896 u8 l0_to_recovery_eieos[0x20];
2897
2898 u8 l0_to_recovery_ts[0x20];
2899
2900 u8 l0_to_recovery_framing[0x20];
2901
2902 u8 l0_to_recovery_retrain[0x20];
2903
2904 u8 crc_error_dllp[0x20];
2905
2906 u8 crc_error_tlp[0x20];
2907
efae7f78
EBE		 2908 u8 tx_overflow_buffer_pkt_high[0x20];
2909
2910 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 2911
2912 u8 outbound_stalled_reads[0x20];
2913
2914 u8 outbound_stalled_writes[0x20];
2915
2916 u8 outbound_stalled_reads_events[0x20];
2917
2918 u8 outbound_stalled_writes_events[0x20];
2919
2920 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 2921};
2922
e281682b
SM		 2923struct mlx5_ifc_cmd_inter_comp_event_bits {
2924 u8 command_completion_vector[0x20];
2925
b4ff3a36 2926 u8 reserved_at_20[0xc0];
e281682b
SM		 2927};
2928
2929struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 2930 u8 reserved_at_0[0x18];
e281682b 2931 u8 port_num[0x1];
b4ff3a36 2932 u8 reserved_at_19[0x3];
e281682b
SM		 2933 u8 vl[0x4];
2934
b4ff3a36 2935 u8 reserved_at_20[0xa0];
e281682b
SM		 2936};
2937
2938struct mlx5_ifc_db_bf_congestion_event_bits {
2939 u8 event_subtype[0x8];
b4ff3a36 2940 u8 reserved_at_8[0x8];
e281682b 2941 u8 congestion_level[0x8];
b4ff3a36 2942 u8 reserved_at_18[0x8];
e281682b 2943
b4ff3a36 2944 u8 reserved_at_20[0xa0];
e281682b
SM		 2945};
2946
2947struct mlx5_ifc_gpio_event_bits {
b4ff3a36 2948 u8 reserved_at_0[0x60];
e281682b
SM		 2949
2950 u8 gpio_event_hi[0x20];
2951
2952 u8 gpio_event_lo[0x20];
2953
b4ff3a36 2954 u8 reserved_at_a0[0x40];
e281682b
SM		 2955};
2956
2957struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 2958 u8 reserved_at_0[0x40];
e281682b
SM		 2959
2960 u8 port_num[0x4];
b4ff3a36 2961 u8 reserved_at_44[0x1c];
e281682b 2962
b4ff3a36 2963 u8 reserved_at_60[0x80];
e281682b
SM		 2964};
2965
2966struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 2967 u8 reserved_at_0[0xe0];
e281682b
SM		 2968};
2969
4b2c5fa9
AT		 2970struct mlx5_ifc_default_timeout_bits {
2971 u8 to_multiplier[0x3];
2972 u8 reserved_at_3[0x9];
2973 u8 to_value[0x14];
2974};
2975
2976struct mlx5_ifc_dtor_reg_bits {
2977 u8 reserved_at_0[0x20];
2978
2979 struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2980
2981 u8 reserved_at_40[0x60];
2982
2983 struct mlx5_ifc_default_timeout_bits health_poll_to;
2984
2985 struct mlx5_ifc_default_timeout_bits full_crdump_to;
2986
2987 struct mlx5_ifc_default_timeout_bits fw_reset_to;
2988
2989 struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2990
2991 struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2992
2993 struct mlx5_ifc_default_timeout_bits tear_down_to;
2994
2995 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2996
2997 struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2998
2999 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3000
3001 u8 reserved_at_1c0[0x40];
3002};
3003
e281682b
SM		 3004enum {
3005 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
3006 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
3007};
3008
3009struct mlx5_ifc_cq_error_bits {
b4ff3a36 3010 u8 reserved_at_0[0x8];
e281682b
SM		 3011 u8 cqn[0x18];
3012
b4ff3a36 3013 u8 reserved_at_20[0x20];
e281682b 3014
b4ff3a36 3015 u8 reserved_at_40[0x18];
e281682b
SM		 3016 u8 syndrome[0x8];
3017
b4ff3a36 3018 u8 reserved_at_60[0x80];
e281682b
SM		 3019};
3020
3021struct mlx5_ifc_rdma_page_fault_event_bits {
3022 u8 bytes_committed[0x20];
3023
3024 u8 r_key[0x20];
3025
b4ff3a36 3026 u8 reserved_at_40[0x10];
e281682b
SM		 3027 u8 packet_len[0x10];
3028
3029 u8 rdma_op_len[0x20];
3030
3031 u8 rdma_va[0x40];
3032
b4ff3a36 3033 u8 reserved_at_c0[0x5];
e281682b
SM		 3034 u8 rdma[0x1];
3035 u8 write[0x1];
3036 u8 requestor[0x1];
3037 u8 qp_number[0x18];
3038};
3039
3040struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3041 u8 bytes_committed[0x20];
3042
b4ff3a36 3043 u8 reserved_at_20[0x10];
e281682b
SM		 3044 u8 wqe_index[0x10];
3045
b4ff3a36 3046 u8 reserved_at_40[0x10];
e281682b
SM		 3047 u8 len[0x10];
3048
b4ff3a36 3049 u8 reserved_at_60[0x60];
e281682b 3050
b4ff3a36 3051 u8 reserved_at_c0[0x5];
e281682b
SM		 3052 u8 rdma[0x1];
3053 u8 write_read[0x1];
3054 u8 requestor[0x1];
3055 u8 qpn[0x18];
3056};
3057
3058struct mlx5_ifc_qp_events_bits {
b4ff3a36 3059 u8 reserved_at_0[0xa0];
e281682b
SM		 3060
3061 u8 type[0x8];
b4ff3a36 3062 u8 reserved_at_a8[0x18];
e281682b 3063
b4ff3a36 3064 u8 reserved_at_c0[0x8];
e281682b
SM		 3065 u8 qpn_rqn_sqn[0x18];
3066};
3067
3068struct mlx5_ifc_dct_events_bits {
b4ff3a36 3069 u8 reserved_at_0[0xc0];
e281682b 3070
b4ff3a36 3071 u8 reserved_at_c0[0x8];
e281682b
SM		 3072 u8 dct_number[0x18];
3073};
3074
3075struct mlx5_ifc_comp_event_bits {
b4ff3a36 3076 u8 reserved_at_0[0xc0];
e281682b 3077
b4ff3a36 3078 u8 reserved_at_c0[0x8];
e281682b
SM		 3079 u8 cq_number[0x18];
3080};
3081
3082enum {
3083 MLX5_QPC_STATE_RST = 0x0,
3084 MLX5_QPC_STATE_INIT = 0x1,
3085 MLX5_QPC_STATE_RTR = 0x2,
3086 MLX5_QPC_STATE_RTS = 0x3,
3087 MLX5_QPC_STATE_SQER = 0x4,
3088 MLX5_QPC_STATE_ERR = 0x6,
3089 MLX5_QPC_STATE_SQD = 0x7,
3090 MLX5_QPC_STATE_SUSPENDED = 0x9,
3091};
3092
3093enum {
3094 MLX5_QPC_ST_RC = 0x0,
3095 MLX5_QPC_ST_UC = 0x1,
3096 MLX5_QPC_ST_UD = 0x2,
3097 MLX5_QPC_ST_XRC = 0x3,
3098 MLX5_QPC_ST_DCI = 0x5,
3099 MLX5_QPC_ST_QP0 = 0x7,
3100 MLX5_QPC_ST_QP1 = 0x8,
3101 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3102 MLX5_QPC_ST_REG_UMR = 0xc,
3103};
3104
3105enum {
3106 MLX5_QPC_PM_STATE_ARMED = 0x0,
3107 MLX5_QPC_PM_STATE_REARM = 0x1,
3108 MLX5_QPC_PM_STATE_RESERVED = 0x2,
3109 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3110};
3111
6e44636a
AK		 3112enum {
3113 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3114};
3115
e281682b
SM		 3116enum {
3117 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3118 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3119};
3120
3121enum {
3122 MLX5_QPC_MTU_256_BYTES = 0x1,
3123 MLX5_QPC_MTU_512_BYTES = 0x2,
3124 MLX5_QPC_MTU_1K_BYTES = 0x3,
3125 MLX5_QPC_MTU_2K_BYTES = 0x4,
3126 MLX5_QPC_MTU_4K_BYTES = 0x5,
3127 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3128};
3129
3130enum {
3131 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3132 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3133 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3134 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3135 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3136 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3137 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3138 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3139};
3140
3141enum {
3142 MLX5_QPC_CS_REQ_DISABLE = 0x0,
3143 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3144 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3145};
3146
3147enum {
3148 MLX5_QPC_CS_RES_DISABLE = 0x0,
3149 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3150 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3151};
3152
a6a217dd 3153enum {
9a1ac95a
AL		 3154 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3155 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3156 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
a6a217dd
AL		 3157};
3158
e281682b
SM		 3159struct mlx5_ifc_qpc_bits {
3160 u8 state[0x4];
84df61eb 3161 u8 lag_tx_port_affinity[0x4];
e281682b 3162 u8 st[0x8];
7304d603
YK		 3163 u8 reserved_at_10[0x2];
3164 u8 isolate_vl_tc[0x1];
e281682b 3165 u8 pm_state[0x2];
3fd3c80a
DG		 3166 u8 reserved_at_15[0x1];
3167 u8 req_e2e_credit_mode[0x2];
6e44636a 3168 u8 offload_type[0x4];
e281682b 3169 u8 end_padding_mode[0x2];
b4ff3a36 3170 u8 reserved_at_1e[0x2];
e281682b
SM		 3171
3172 u8 wq_signature[0x1];
3173 u8 block_lb_mc[0x1];
3174 u8 atomic_like_write_en[0x1];
3175 u8 latency_sensitive[0x1];
b4ff3a36 3176 u8 reserved_at_24[0x1];
e281682b 3177 u8 drain_sigerr[0x1];
b4ff3a36 3178 u8 reserved_at_26[0x2];
e281682b
SM		 3179 u8 pd[0x18];
3180
3181 u8 mtu[0x3];
3182 u8 log_msg_max[0x5];
b4ff3a36 3183 u8 reserved_at_48[0x1];
e281682b
SM		 3184 u8 log_rq_size[0x4];
3185 u8 log_rq_stride[0x3];
3186 u8 no_sq[0x1];
3187 u8 log_sq_size[0x4];
a6a217dd
AL		 3188 u8 reserved_at_55[0x3];
3189 u8 ts_format[0x2];
3190 u8 reserved_at_5a[0x1];
e281682b 3191 u8 rlky[0x1];
1015c2e8 3192 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 3193
3194 u8 counter_set_id[0x8];
3195 u8 uar_page[0x18];
3196
b4ff3a36 3197 u8 reserved_at_80[0x8];
e281682b
SM		 3198 u8 user_index[0x18];
3199
b4ff3a36 3200 u8 reserved_at_a0[0x3];
e281682b
SM		 3201 u8 log_page_size[0x5];
3202 u8 remote_qpn[0x18];
3203
3204 struct mlx5_ifc_ads_bits primary_address_path;
3205
3206 struct mlx5_ifc_ads_bits secondary_address_path;
3207
3208 u8 log_ack_req_freq[0x4];
b4ff3a36 3209 u8 reserved_at_384[0x4];
e281682b 3210 u8 log_sra_max[0x3];
b4ff3a36 3211 u8 reserved_at_38b[0x2];
e281682b
SM		 3212 u8 retry_count[0x3];
3213 u8 rnr_retry[0x3];
b4ff3a36 3214 u8 reserved_at_393[0x1];
e281682b
SM		 3215 u8 fre[0x1];
3216 u8 cur_rnr_retry[0x3];
3217 u8 cur_retry_count[0x3];
b4ff3a36 3218 u8 reserved_at_39b[0x5];
e281682b 3219
b4ff3a36 3220 u8 reserved_at_3a0[0x20];
e281682b 3221
b4ff3a36 3222 u8 reserved_at_3c0[0x8];
e281682b
SM		 3223 u8 next_send_psn[0x18];
3224
96cd2dd6
LN		 3225 u8 reserved_at_3e0[0x3];
3226 u8 log_num_dci_stream_channels[0x5];
e281682b
SM		 3227 u8 cqn_snd[0x18];
3228
96cd2dd6
LN		 3229 u8 reserved_at_400[0x3];
3230 u8 log_num_dci_errored_streams[0x5];
09a7d9ec
SM		 3231 u8 deth_sqpn[0x18];
3232
3233 u8 reserved_at_420[0x20];
e281682b 3234
b4ff3a36 3235 u8 reserved_at_440[0x8];
e281682b
SM		 3236 u8 last_acked_psn[0x18];
3237
b4ff3a36 3238 u8 reserved_at_460[0x8];
e281682b
SM		 3239 u8 ssn[0x18];
3240
b4ff3a36 3241 u8 reserved_at_480[0x8];
e281682b 3242 u8 log_rra_max[0x3];
b4ff3a36 3243 u8 reserved_at_48b[0x1];
e281682b
SM		 3244 u8 atomic_mode[0x4];
3245 u8 rre[0x1];
3246 u8 rwe[0x1];
3247 u8 rae[0x1];
b4ff3a36 3248 u8 reserved_at_493[0x1];
e281682b 3249 u8 page_offset[0x6];
b4ff3a36 3250 u8 reserved_at_49a[0x3];
e281682b
SM		 3251 u8 cd_slave_receive[0x1];
3252 u8 cd_slave_send[0x1];
3253 u8 cd_master[0x1];
3254
b4ff3a36 3255 u8 reserved_at_4a0[0x3];
e281682b
SM		 3256 u8 min_rnr_nak[0x5];
3257 u8 next_rcv_psn[0x18];
3258
b4ff3a36 3259 u8 reserved_at_4c0[0x8];
e281682b
SM		 3260 u8 xrcd[0x18];
3261
b4ff3a36 3262 u8 reserved_at_4e0[0x8];
e281682b
SM		 3263 u8 cqn_rcv[0x18];
3264
3265 u8 dbr_addr[0x40];
3266
3267 u8 q_key[0x20];
3268
b4ff3a36 3269 u8 reserved_at_560[0x5];
e281682b 3270 u8 rq_type[0x3];
7486216b 3271 u8 srqn_rmpn_xrqn[0x18];
e281682b 3272
b4ff3a36 3273 u8 reserved_at_580[0x8];
e281682b
SM		 3274 u8 rmsn[0x18];
3275
3276 u8 hw_sq_wqebb_counter[0x10];
3277 u8 sw_sq_wqebb_counter[0x10];
3278
3279 u8 hw_rq_counter[0x20];
3280
3281 u8 sw_rq_counter[0x20];
3282
b4ff3a36 3283 u8 reserved_at_600[0x20];
e281682b 3284
b4ff3a36 3285 u8 reserved_at_620[0xf];
e281682b
SM		 3286 u8 cgs[0x1];
3287 u8 cs_req[0x8];
3288 u8 cs_res[0x8];
3289
3290 u8 dc_access_key[0x40];
3291
bd371975
LR		 3292 u8 reserved_at_680[0x3];
3293 u8 dbr_umem_valid[0x1];
3294
3295 u8 reserved_at_684[0xbc];
e281682b
SM		 3296};
3297
3298struct mlx5_ifc_roce_addr_layout_bits {
3299 u8 source_l3_address[16][0x8];
3300
b4ff3a36 3301 u8 reserved_at_80[0x3];
e281682b
SM		 3302 u8 vlan_valid[0x1];
3303 u8 vlan_id[0xc];
3304 u8 source_mac_47_32[0x10];
3305
3306 u8 source_mac_31_0[0x20];
3307
b4ff3a36 3308 u8 reserved_at_c0[0x14];
e281682b
SM		 3309 u8 roce_l3_type[0x4];
3310 u8 roce_version[0x8];
3311
b4ff3a36 3312 u8 reserved_at_e0[0x20];
e281682b
SM		 3313};
3314
7025329d
BBI		 3315struct mlx5_ifc_shampo_cap_bits {
3316 u8 reserved_at_0[0x3];
3317 u8 shampo_log_max_reservation_size[0x5];
3318 u8 reserved_at_8[0x3];
3319 u8 shampo_log_min_reservation_size[0x5];
3320 u8 shampo_min_mss_size[0x10];
3321
3322 u8 reserved_at_20[0x3];
3323 u8 shampo_max_log_headers_entry_size[0x5];
3324 u8 reserved_at_28[0x18];
3325
3326 u8 reserved_at_40[0x7c0];
3327};
3328
e281682b
SM		 3329union mlx5_ifc_hca_cap_union_bits {
3330 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
67133eaa 3331 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
e281682b
SM		 3332 struct mlx5_ifc_odp_cap_bits odp_cap;
3333 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3334 struct mlx5_ifc_roce_cap_bits roce_cap;
3335 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3336 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 3337 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 3338 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
425a563a 3339 struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3f0393a5 3340 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 3341 struct mlx5_ifc_qos_cap_bits qos_cap;
0b9055a1 3342 struct mlx5_ifc_debug_cap_bits debug_cap;
e29341fb 3343 struct mlx5_ifc_fpga_cap_bits fpga_cap;
a12ff35e 3344 struct mlx5_ifc_tls_cap_bits tls_cap;
97b5484e 3345 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
8a06a79b 3346 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
7025329d 3347 struct mlx5_ifc_shampo_cap_bits shampo_cap;
8385c51f 3348 struct mlx5_ifc_macsec_cap_bits macsec_cap;
b4ff3a36 3349 u8 reserved_at_0[0x8000];
e281682b
SM		 3350};
3351
3352enum {
3353 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3354 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3355 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 3356 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
60786f09 3357 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
7adbde20 3358 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 3359 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
0c06897a
OG		 3360 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3361 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
8da6fe2a
JL		 3362 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3363 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
e227ee99
LN		 3364 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3365 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
f5d23ee1 3366 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
0c06897a
OG		 3367};
3368
65c0f2c1
JL		 3369enum {
3370 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3371 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3372 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3373};
3374
e227ee99
LN		 3375enum {
3376 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0,
8385c51f 3377 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1,
e227ee99
LN		 3378};
3379
0c06897a
OG		 3380struct mlx5_ifc_vlan_bits {
3381 u8 ethtype[0x10];
3382 u8 prio[0x3];
3383 u8 cfi[0x1];
3384 u8 vid[0xc];
e281682b
SM		 3385};
3386
f5d23ee1
JL		 3387enum {
3388 MLX5_FLOW_METER_COLOR_RED = 0x0,
3389 MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
3390 MLX5_FLOW_METER_COLOR_GREEN = 0x2,
3391 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3392};
3393
3394enum {
3395 MLX5_EXE_ASO_FLOW_METER = 0x2,
3396};
3397
3398struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3399 u8 return_reg_id[0x4];
3400 u8 aso_type[0x4];
3401 u8 reserved_at_8[0x14];
3402 u8 action[0x1];
3403 u8 init_color[0x2];
3404 u8 meter_id[0x1];
3405};
3406
3407union mlx5_ifc_exe_aso_ctrl {
3408 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3409};
3410
3411struct mlx5_ifc_execute_aso_bits {
3412 u8 valid[0x1];
3413 u8 reserved_at_1[0x7];
3414 u8 aso_object_id[0x18];
3415
3416 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3417};
3418
e281682b 3419struct mlx5_ifc_flow_context_bits {
0c06897a 3420 struct mlx5_ifc_vlan_bits push_vlan;
e281682b
SM		 3421
3422 u8 group_id[0x20];
3423
b4ff3a36 3424 u8 reserved_at_40[0x8];
e281682b
SM		 3425 u8 flow_tag[0x18];
3426
b4ff3a36 3427 u8 reserved_at_60[0x10];
e281682b
SM		 3428 u8 action[0x10];
3429
1b115498 3430 u8 extended_destination[0x1];
65c0f2c1
JL		 3431 u8 reserved_at_81[0x1];
3432 u8 flow_source[0x2];
e227ee99 3433 u8 encrypt_decrypt_type[0x4];
e281682b
SM		 3434 u8 destination_list_size[0x18];
3435
9dc0b289
AV		 3436 u8 reserved_at_a0[0x8];
3437 u8 flow_counter_list_size[0x18];
3438
60786f09 3439 u8 packet_reformat_id[0x20];
7adbde20 3440
2a69cb9f
OG		 3441 u8 modify_header_id[0x20];
3442
8da6fe2a
JL		 3443 struct mlx5_ifc_vlan_bits push_vlan_2;
3444
e227ee99 3445 u8 encrypt_decrypt_obj_id[0x20];
78fb6122 3446 u8 reserved_at_140[0xc0];
e281682b
SM		 3447
3448 struct mlx5_ifc_fte_match_param_bits match_value;
3449
f5d23ee1
JL		 3450 struct mlx5_ifc_execute_aso_bits execute_aso[4];
3451
3452 u8 reserved_at_1300[0x500];
e281682b 3453
b6ca09cb 3454 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
e281682b
SM		 3455};
3456
3457enum {
3458 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3459 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3460};
3461
3462struct mlx5_ifc_xrc_srqc_bits {
3463 u8 state[0x4];
3464 u8 log_xrc_srq_size[0x4];
b4ff3a36 3465 u8 reserved_at_8[0x18];
e281682b
SM		 3466
3467 u8 wq_signature[0x1];
3468 u8 cont_srq[0x1];
99b77fef 3469 u8 reserved_at_22[0x1];
e281682b
SM		 3470 u8 rlky[0x1];
3471 u8 basic_cyclic_rcv_wqe[0x1];
3472 u8 log_rq_stride[0x3];
3473 u8 xrcd[0x18];
3474
3475 u8 page_offset[0x6];
99b77fef
YH		 3476 u8 reserved_at_46[0x1];
3477 u8 dbr_umem_valid[0x1];
e281682b
SM		 3478 u8 cqn[0x18];
3479
b4ff3a36 3480 u8 reserved_at_60[0x20];
e281682b
SM		 3481
3482 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 3483 u8 reserved_at_81[0x1];
e281682b
SM		 3484 u8 log_page_size[0x6];
3485 u8 user_index[0x18];
3486
b4ff3a36 3487 u8 reserved_at_a0[0x20];
e281682b 3488
b4ff3a36 3489 u8 reserved_at_c0[0x8];
e281682b
SM		 3490 u8 pd[0x18];
3491
3492 u8 lwm[0x10];
3493 u8 wqe_cnt[0x10];
3494
b4ff3a36 3495 u8 reserved_at_100[0x40];
e281682b
SM		 3496
3497 u8 db_record_addr_h[0x20];
3498
3499 u8 db_record_addr_l[0x1e];
b4ff3a36 3500 u8 reserved_at_17e[0x2];
e281682b 3501
b4ff3a36 3502 u8 reserved_at_180[0x80];
e281682b
SM		 3503};
3504
61c5b5c9
MS		 3505struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3506 u8 counter_error_queues[0x20];
3507
3508 u8 total_error_queues[0x20];
3509
3510 u8 send_queue_priority_update_flow[0x20];
3511
3512 u8 reserved_at_60[0x20];
3513
3514 u8 nic_receive_steering_discard[0x40];
3515
3516 u8 receive_discard_vport_down[0x40];
3517
3518 u8 transmit_discard_vport_down[0x40];
3519
3e94e61b
SM		 3520 u8 async_eq_overrun[0x20];
3521
3522 u8 comp_eq_overrun[0x20];
3523
3524 u8 reserved_at_180[0x20];
3525
3526 u8 invalid_command[0x20];
3527
3528 u8 quota_exceeded_command[0x20];
30b10e89
MS		 3529
3530 u8 internal_rq_out_of_buffer[0x20];
3531
3e94e61b
SM		 3532 u8 cq_overrun[0x20];
3533
3534 u8 reserved_at_220[0xde0];
61c5b5c9
MS		 3535};
3536
e281682b
SM		 3537struct mlx5_ifc_traffic_counter_bits {
3538 u8 packets[0x40];
3539
3540 u8 octets[0x40];
3541};
3542
3543struct mlx5_ifc_tisc_bits {
84df61eb 3544 u8 strict_lag_tx_port_affinity[0x1];
a12ff35e 3545 u8 tls_en[0x1];
7761f9ee 3546 u8 reserved_at_2[0x2];
84df61eb
AH		 3547 u8 lag_tx_port_affinity[0x04];
3548
3549 u8 reserved_at_8[0x4];
e281682b 3550 u8 prio[0x4];
b4ff3a36 3551 u8 reserved_at_10[0x10];
e281682b 3552
b4ff3a36 3553 u8 reserved_at_20[0x100];
e281682b 3554
b4ff3a36 3555 u8 reserved_at_120[0x8];
e281682b
SM		 3556 u8 transport_domain[0x18];
3557
500a3d0d
ES		 3558 u8 reserved_at_140[0x8];
3559 u8 underlay_qpn[0x18];
a12ff35e
EBE		 3560
3561 u8 reserved_at_160[0x8];
3562 u8 pd[0x18];
3563
3564 u8 reserved_at_180[0x380];
e281682b
SM		 3565};
3566
3567enum {
3568 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3569 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3570};
3571
3572enum {
50f477fe
BBI		 3573 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3574 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
e281682b
SM		 3575};
3576
3577enum {
2be6967c
SM		 3578 MLX5_RX_HASH_FN_NONE = 0x0,
3579 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3580 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 3581};
3582
3583enum {
5d773ff4
MB		 3584 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3585 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
e281682b
SM		 3586};
3587
3588struct mlx5_ifc_tirc_bits {
b4ff3a36 3589 u8 reserved_at_0[0x20];
e281682b
SM		 3590
3591 u8 disp_type[0x4];
ee5cdf7a
TT		 3592 u8 tls_en[0x1];
3593 u8 reserved_at_25[0x1b];
e281682b 3594
b4ff3a36 3595 u8 reserved_at_40[0x40];
e281682b 3596
b4ff3a36 3597 u8 reserved_at_80[0x4];
e281682b 3598 u8 lro_timeout_period_usecs[0x10];
50f477fe 3599 u8 packet_merge_mask[0x4];
e281682b
SM		 3600 u8 lro_max_ip_payload_size[0x8];
3601
b4ff3a36 3602 u8 reserved_at_a0[0x40];
e281682b 3603
b4ff3a36 3604 u8 reserved_at_e0[0x8];
e281682b
SM		 3605 u8 inline_rqn[0x18];
3606
3607 u8 rx_hash_symmetric[0x1];
b4ff3a36 3608 u8 reserved_at_101[0x1];
e281682b 3609 u8 tunneled_offload_en[0x1];
b4ff3a36 3610 u8 reserved_at_103[0x5];
e281682b
SM		 3611 u8 indirect_table[0x18];
3612
3613 u8 rx_hash_fn[0x4];
b4ff3a36 3614 u8 reserved_at_124[0x2];
e281682b
SM		 3615 u8 self_lb_block[0x2];
3616 u8 transport_domain[0x18];
3617
3618 u8 rx_hash_toeplitz_key[10][0x20];
3619
3620 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3621
3622 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3623
b4ff3a36 3624 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 3625};
3626
3627enum {
3628 MLX5_SRQC_STATE_GOOD = 0x0,
3629 MLX5_SRQC_STATE_ERROR = 0x1,
3630};
3631
3632struct mlx5_ifc_srqc_bits {
3633 u8 state[0x4];
3634 u8 log_srq_size[0x4];
b4ff3a36 3635 u8 reserved_at_8[0x18];
e281682b
SM		 3636
3637 u8 wq_signature[0x1];
3638 u8 cont_srq[0x1];
b4ff3a36 3639 u8 reserved_at_22[0x1];
e281682b 3640 u8 rlky[0x1];
b4ff3a36 3641 u8 reserved_at_24[0x1];
e281682b
SM		 3642 u8 log_rq_stride[0x3];
3643 u8 xrcd[0x18];
3644
3645 u8 page_offset[0x6];
b4ff3a36 3646 u8 reserved_at_46[0x2];
e281682b
SM		 3647 u8 cqn[0x18];
3648
b4ff3a36 3649 u8 reserved_at_60[0x20];
e281682b 3650
b4ff3a36 3651 u8 reserved_at_80[0x2];
e281682b 3652 u8 log_page_size[0x6];
b4ff3a36 3653 u8 reserved_at_88[0x18];
e281682b 3654
b4ff3a36 3655 u8 reserved_at_a0[0x20];
e281682b 3656
b4ff3a36 3657 u8 reserved_at_c0[0x8];
e281682b
SM		 3658 u8 pd[0x18];
3659
3660 u8 lwm[0x10];
3661 u8 wqe_cnt[0x10];
3662
b4ff3a36 3663 u8 reserved_at_100[0x40];
e281682b 3664
01949d01 3665 u8 dbr_addr[0x40];
e281682b 3666
b4ff3a36 3667 u8 reserved_at_180[0x80];
e281682b
SM		 3668};
3669
3670enum {
3671 MLX5_SQC_STATE_RST = 0x0,
3672 MLX5_SQC_STATE_RDY = 0x1,
3673 MLX5_SQC_STATE_ERR = 0x3,
3674};
3675
3676struct mlx5_ifc_sqc_bits {
3677 u8 rlky[0x1];
3678 u8 cd_master[0x1];
3679 u8 fre[0x1];
3680 u8 flush_in_error_en[0x1];
795b609c 3681 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 3682 u8 min_wqe_inline_mode[0x3];
e281682b 3683 u8 state[0x4];
7d5e1423 3684 u8 reg_umr[0x1];
547eede0 3685 u8 allow_swp[0x1];
40817cdb 3686 u8 hairpin[0x1];
a6a217dd
AL		 3687 u8 reserved_at_f[0xb];
3688 u8 ts_format[0x2];
3689 u8 reserved_at_1c[0x4];
e281682b 3690
b4ff3a36 3691 u8 reserved_at_20[0x8];
e281682b
SM		 3692 u8 user_index[0x18];
3693
b4ff3a36 3694 u8 reserved_at_40[0x8];
e281682b
SM		 3695 u8 cqn[0x18];
3696
40817cdb
OG		 3697 u8 reserved_at_60[0x8];
3698 u8 hairpin_peer_rq[0x18];
3699
3700 u8 reserved_at_80[0x10];
3701 u8 hairpin_peer_vhca[0x10];
3702
59d2ae1d 3703 u8 reserved_at_a0[0x20];
e281682b 3704
59d2ae1d
EBE		 3705 u8 reserved_at_c0[0x8];
3706 u8 ts_cqe_to_dest_cqn[0x18];
e281682b 3707
59d2ae1d 3708 u8 reserved_at_e0[0x10];
7486216b 3709 u8 packet_pacing_rate_limit_index[0x10];
e281682b 3710 u8 tis_lst_sz[0x10];
214baf22 3711 u8 qos_queue_group_id[0x10];
e281682b 3712
b4ff3a36 3713 u8 reserved_at_120[0x40];
e281682b 3714
b4ff3a36 3715 u8 reserved_at_160[0x8];
e281682b
SM		 3716 u8 tis_num_0[0x18];
3717
3718 struct mlx5_ifc_wq_bits wq;
3719};
3720
813f8540
MHY		 3721enum {
3722 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3723 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3724 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3725 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
214baf22 3726 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
813f8540
MHY		 3727};
3728
6cedde45
EC		 3729enum {
3730 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3731 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3732 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3733 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3734};
3735
813f8540
MHY		 3736struct mlx5_ifc_scheduling_context_bits {
3737 u8 element_type[0x8];
3738 u8 reserved_at_8[0x18];
3739
3740 u8 element_attributes[0x20];
3741
3742 u8 parent_element_id[0x20];
3743
3744 u8 reserved_at_60[0x40];
3745
3746 u8 bw_share[0x20];
3747
3748 u8 max_average_bw[0x20];
3749
3750 u8 reserved_at_e0[0x120];
3751};
3752
e281682b 3753struct mlx5_ifc_rqtc_bits {
8a06a79b 3754 u8 reserved_at_0[0xa0];
e281682b 3755
8a06a79b
EC		 3756 u8 reserved_at_a0[0x5];
3757 u8 list_q_type[0x3];
3758 u8 reserved_at_a8[0x8];
3759 u8 rqt_max_size[0x10];
e281682b 3760
8a06a79b
EC		 3761 u8 rq_vhca_id_format[0x1];
3762 u8 reserved_at_c1[0xf];
3763 u8 rqt_actual_size[0x10];
e281682b 3764
8a06a79b 3765 u8 reserved_at_e0[0x6a0];
e281682b 3766
b6ca09cb 3767 struct mlx5_ifc_rq_num_bits rq_num[];
e281682b
SM		 3768};
3769
3770enum {
3771 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3772 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3773};
3774
3775enum {
3776 MLX5_RQC_STATE_RST = 0x0,
3777 MLX5_RQC_STATE_RDY = 0x1,
3778 MLX5_RQC_STATE_ERR = 0x3,
3779};
3780
7025329d
BBI		 3781enum {
3782 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3783 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3784 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3785};
3786
3787enum {
3788 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3789 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3790 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3791};
3792
e281682b
SM		 3793struct mlx5_ifc_rqc_bits {
3794 u8 rlky[0x1];
03404e8a 3795 u8 delay_drop_en[0x1];
7d5e1423 3796 u8 scatter_fcs[0x1];
e281682b
SM		 3797 u8 vsd[0x1];
3798 u8 mem_rq_type[0x4];
3799 u8 state[0x4];
b4ff3a36 3800 u8 reserved_at_c[0x1];
e281682b 3801 u8 flush_in_error_en[0x1];
40817cdb 3802 u8 hairpin[0x1];
a6a217dd
AL		 3803 u8 reserved_at_f[0xb];
3804 u8 ts_format[0x2];
3805 u8 reserved_at_1c[0x4];
e281682b 3806
b4ff3a36 3807 u8 reserved_at_20[0x8];
e281682b
SM		 3808 u8 user_index[0x18];
3809
b4ff3a36 3810 u8 reserved_at_40[0x8];
e281682b
SM		 3811 u8 cqn[0x18];
3812
3813 u8 counter_set_id[0x8];
b4ff3a36 3814 u8 reserved_at_68[0x18];
e281682b 3815
b4ff3a36 3816 u8 reserved_at_80[0x8];
e281682b
SM		 3817 u8 rmpn[0x18];
3818
40817cdb
OG		 3819 u8 reserved_at_a0[0x8];
3820 u8 hairpin_peer_sq[0x18];
3821
3822 u8 reserved_at_c0[0x10];
3823 u8 hairpin_peer_vhca[0x10];
3824
7025329d
BBI		 3825 u8 reserved_at_e0[0x46];
3826 u8 shampo_no_match_alignment_granularity[0x2];
3827 u8 reserved_at_128[0x6];
3828 u8 shampo_match_criteria_type[0x2];
3829 u8 reservation_timeout[0x10];
3830
3831 u8 reserved_at_140[0x40];
e281682b
SM		 3832
3833 struct mlx5_ifc_wq_bits wq;
3834};
3835
3836enum {
3837 MLX5_RMPC_STATE_RDY = 0x1,
3838 MLX5_RMPC_STATE_ERR = 0x3,
3839};
3840
3841struct mlx5_ifc_rmpc_bits {
b4ff3a36 3842 u8 reserved_at_0[0x8];
e281682b 3843 u8 state[0x4];
b4ff3a36 3844 u8 reserved_at_c[0x14];
e281682b
SM		 3845
3846 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 3847 u8 reserved_at_21[0x1f];
e281682b 3848
b4ff3a36 3849 u8 reserved_at_40[0x140];
e281682b
SM		 3850
3851 struct mlx5_ifc_wq_bits wq;
3852};
3853
0372c546
YH		 3854enum {
3855 VHCA_ID_TYPE_HW = 0,
3856 VHCA_ID_TYPE_SW = 1,
3857};
3858
e281682b 3859struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 3860 u8 reserved_at_0[0x5];
3861 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 3862 u8 reserved_at_8[0x15];
3863 u8 disable_mc_local_lb[0x1];
3864 u8 disable_uc_local_lb[0x1];
e281682b
SM		 3865 u8 roce_en[0x1];
3866
d82b7318 3867 u8 arm_change_event[0x1];
b4ff3a36 3868 u8 reserved_at_21[0x1a];
d82b7318
SM		 3869 u8 event_on_mtu[0x1];
3870 u8 event_on_promisc_change[0x1];
3871 u8 event_on_vlan_change[0x1];
3872 u8 event_on_mc_address_change[0x1];
3873 u8 event_on_uc_address_change[0x1];
e281682b 3874
0372c546
YH		 3875 u8 vhca_id_type[0x1];
3876 u8 reserved_at_41[0xb];
32f69e4b
DJ		 3877 u8 affiliation_criteria[0x4];
3878 u8 affiliated_vhca_id[0x10];
3879
3880 u8 reserved_at_60[0xd0];
d82b7318
SM		 3881
3882 u8 mtu[0x10];
3883
9efa7525
AS		 3884 u8 system_image_guid[0x40];
3885 u8 port_guid[0x40];
3886 u8 node_guid[0x40];
3887
b4ff3a36 3888 u8 reserved_at_200[0x140];
9efa7525 3889 u8 qkey_violation_counter[0x10];
b4ff3a36 3890 u8 reserved_at_350[0x430];
d82b7318
SM		 3891
3892 u8 promisc_uc[0x1];
3893 u8 promisc_mc[0x1];
3894 u8 promisc_all[0x1];
b4ff3a36 3895 u8 reserved_at_783[0x2];
e281682b 3896 u8 allowed_list_type[0x3];
b4ff3a36 3897 u8 reserved_at_788[0xc];
e281682b
SM		 3898 u8 allowed_list_size[0xc];
3899
3900 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3901
b4ff3a36 3902 u8 reserved_at_7e0[0x20];
e281682b 3903
b6ca09cb 3904 u8 current_uc_mac_address[][0x40];
e281682b
SM		 3905};
3906
3907enum {
3908 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3909 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3910 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 3911 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
9fba2b9b 3912 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
cdbd0d2b 3913 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
e281682b
SM		 3914};
3915
3916struct mlx5_ifc_mkc_bits {
b4ff3a36 3917 u8 reserved_at_0[0x1];
e281682b 3918 u8 free[0x1];
cdbd0d2b
AL		 3919 u8 reserved_at_2[0x1];
3920 u8 access_mode_4_2[0x3];
3921 u8 reserved_at_6[0x7];
3922 u8 relaxed_ordering_write[0x1];
3923 u8 reserved_at_e[0x1];
e281682b
SM		 3924 u8 small_fence_on_rdma_read_response[0x1];
3925 u8 umr_en[0x1];
3926 u8 a[0x1];
3927 u8 rw[0x1];
3928 u8 rr[0x1];
3929 u8 lw[0x1];
3930 u8 lr[0x1];
cdbd0d2b 3931 u8 access_mode_1_0[0x2];
b4ff3a36 3932 u8 reserved_at_18[0x8];
e281682b
SM		 3933
3934 u8 qpn[0x18];
3935 u8 mkey_7_0[0x8];
3936
b4ff3a36 3937 u8 reserved_at_40[0x20];
e281682b
SM		 3938
3939 u8 length64[0x1];
3940 u8 bsf_en[0x1];
3941 u8 sync_umr[0x1];
b4ff3a36 3942 u8 reserved_at_63[0x2];
e281682b 3943 u8 expected_sigerr_count[0x1];
b4ff3a36 3944 u8 reserved_at_66[0x1];
e281682b
SM		 3945 u8 en_rinval[0x1];
3946 u8 pd[0x18];
3947
3948 u8 start_addr[0x40];
3949
3950 u8 len[0x40];
3951
3952 u8 bsf_octword_size[0x20];
3953
b4ff3a36 3954 u8 reserved_at_120[0x80];
e281682b
SM		 3955
3956 u8 translations_octword_size[0x20];
3957
a880a6dd
MG		 3958 u8 reserved_at_1c0[0x19];
3959 u8 relaxed_ordering_read[0x1];
3960 u8 reserved_at_1d9[0x1];
e281682b
SM		 3961 u8 log_page_size[0x5];
3962
b4ff3a36 3963 u8 reserved_at_1e0[0x20];
e281682b
SM		 3964};
3965
3966struct mlx5_ifc_pkey_bits {
b4ff3a36 3967 u8 reserved_at_0[0x10];
e281682b
SM		 3968 u8 pkey[0x10];
3969};
3970
3971struct mlx5_ifc_array128_auto_bits {
3972 u8 array128_auto[16][0x8];
3973};
3974
3975struct mlx5_ifc_hca_vport_context_bits {
3976 u8 field_select[0x20];
3977
b4ff3a36 3978 u8 reserved_at_20[0xe0];
e281682b
SM		 3979
3980 u8 sm_virt_aware[0x1];
3981 u8 has_smi[0x1];
3982 u8 has_raw[0x1];
3983 u8 grh_required[0x1];
b4ff3a36 3984 u8 reserved_at_104[0xc];
707c4602
MD		 3985 u8 port_physical_state[0x4];
3986 u8 vport_state_policy[0x4];
3987 u8 port_state[0x4];
e281682b
SM		 3988 u8 vport_state[0x4];
3989
b4ff3a36 3990 u8 reserved_at_120[0x20];
707c4602
MD		 3991
3992 u8 system_image_guid[0x40];
e281682b
SM		 3993
3994 u8 port_guid[0x40];
3995
3996 u8 node_guid[0x40];
3997
3998 u8 cap_mask1[0x20];
3999
4000 u8 cap_mask1_field_select[0x20];
4001
4002 u8 cap_mask2[0x20];
4003
4004 u8 cap_mask2_field_select[0x20];
4005
b4ff3a36 4006 u8 reserved_at_280[0x80];
e281682b
SM		 4007
4008 u8 lid[0x10];
b4ff3a36 4009 u8 reserved_at_310[0x4];
e281682b
SM		 4010 u8 init_type_reply[0x4];
4011 u8 lmc[0x3];
4012 u8 subnet_timeout[0x5];
4013
4014 u8 sm_lid[0x10];
4015 u8 sm_sl[0x4];
b4ff3a36 4016 u8 reserved_at_334[0xc];
e281682b
SM		 4017
4018 u8 qkey_violation_counter[0x10];
4019 u8 pkey_violation_counter[0x10];
4020
b4ff3a36 4021 u8 reserved_at_360[0xca0];
e281682b
SM		 4022};
4023
d6666753 4024struct mlx5_ifc_esw_vport_context_bits {
65c0f2c1
JL		 4025 u8 fdb_to_vport_reg_c[0x1];
4026 u8 reserved_at_1[0x2];
d6666753
SM		 4027 u8 vport_svlan_strip[0x1];
4028 u8 vport_cvlan_strip[0x1];
4029 u8 vport_svlan_insert[0x1];
4030 u8 vport_cvlan_insert[0x2];
65c0f2c1
JL		 4031 u8 fdb_to_vport_reg_c_id[0x8];
4032 u8 reserved_at_10[0x10];
d6666753 4033
b4ff3a36 4034 u8 reserved_at_20[0x20];
d6666753
SM		 4035
4036 u8 svlan_cfi[0x1];
4037 u8 svlan_pcp[0x3];
4038 u8 svlan_id[0xc];
4039 u8 cvlan_cfi[0x1];
4040 u8 cvlan_pcp[0x3];
4041 u8 cvlan_id[0xc];
4042
97b5484e
AV		 4043 u8 reserved_at_60[0x720];
4044
4045 u8 sw_steering_vport_icm_address_rx[0x40];
4046
4047 u8 sw_steering_vport_icm_address_tx[0x40];
d6666753
SM		 4048};
4049
e281682b
SM		 4050enum {
4051 MLX5_EQC_STATUS_OK = 0x0,
4052 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
4053};
4054
4055enum {
4056 MLX5_EQC_ST_ARMED = 0x9,
4057 MLX5_EQC_ST_FIRED = 0xa,
4058};
4059
4060struct mlx5_ifc_eqc_bits {
4061 u8 status[0x4];
b4ff3a36 4062 u8 reserved_at_4[0x9];
e281682b
SM		 4063 u8 ec[0x1];
4064 u8 oi[0x1];
b4ff3a36 4065 u8 reserved_at_f[0x5];
e281682b 4066 u8 st[0x4];
b4ff3a36 4067 u8 reserved_at_18[0x8];
e281682b 4068
b4ff3a36 4069 u8 reserved_at_20[0x20];
e281682b 4070
b4ff3a36 4071 u8 reserved_at_40[0x14];
e281682b 4072 u8 page_offset[0x6];
b4ff3a36 4073 u8 reserved_at_5a[0x6];
e281682b 4074
b4ff3a36 4075 u8 reserved_at_60[0x3];
e281682b
SM		 4076 u8 log_eq_size[0x5];
4077 u8 uar_page[0x18];
4078
b4ff3a36 4079 u8 reserved_at_80[0x20];
e281682b 4080
3af26495
SD		 4081 u8 reserved_at_a0[0x14];
4082 u8 intr[0xc];
e281682b 4083
b4ff3a36 4084 u8 reserved_at_c0[0x3];
e281682b 4085 u8 log_page_size[0x5];
b4ff3a36 4086 u8 reserved_at_c8[0x18];
e281682b 4087
b4ff3a36 4088 u8 reserved_at_e0[0x60];
e281682b 4089
b4ff3a36 4090 u8 reserved_at_140[0x8];
e281682b
SM		 4091 u8 consumer_counter[0x18];
4092
b4ff3a36 4093 u8 reserved_at_160[0x8];
e281682b
SM		 4094 u8 producer_counter[0x18];
4095
b4ff3a36 4096 u8 reserved_at_180[0x80];
e281682b
SM		 4097};
4098
4099enum {
4100 MLX5_DCTC_STATE_ACTIVE = 0x0,
4101 MLX5_DCTC_STATE_DRAINING = 0x1,
4102 MLX5_DCTC_STATE_DRAINED = 0x2,
4103};
4104
4105enum {
4106 MLX5_DCTC_CS_RES_DISABLE = 0x0,
4107 MLX5_DCTC_CS_RES_NA = 0x1,
4108 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
4109};
4110
4111enum {
4112 MLX5_DCTC_MTU_256_BYTES = 0x1,
4113 MLX5_DCTC_MTU_512_BYTES = 0x2,
4114 MLX5_DCTC_MTU_1K_BYTES = 0x3,
4115 MLX5_DCTC_MTU_2K_BYTES = 0x4,
4116 MLX5_DCTC_MTU_4K_BYTES = 0x5,
4117};
4118
4119struct mlx5_ifc_dctc_bits {
b4ff3a36 4120 u8 reserved_at_0[0x4];
e281682b 4121 u8 state[0x4];
b4ff3a36 4122 u8 reserved_at_8[0x18];
e281682b 4123
b4ff3a36 4124 u8 reserved_at_20[0x8];
e281682b
SM		 4125 u8 user_index[0x18];
4126
b4ff3a36 4127 u8 reserved_at_40[0x8];
e281682b
SM		 4128 u8 cqn[0x18];
4129
4130 u8 counter_set_id[0x8];
4131 u8 atomic_mode[0x4];
4132 u8 rre[0x1];
4133 u8 rwe[0x1];
4134 u8 rae[0x1];
4135 u8 atomic_like_write_en[0x1];
4136 u8 latency_sensitive[0x1];
4137 u8 rlky[0x1];
4138 u8 free_ar[0x1];
b4ff3a36 4139 u8 reserved_at_73[0xd];
e281682b 4140
b4ff3a36 4141 u8 reserved_at_80[0x8];
e281682b 4142 u8 cs_res[0x8];
b4ff3a36 4143 u8 reserved_at_90[0x3];
e281682b 4144 u8 min_rnr_nak[0x5];
b4ff3a36 4145 u8 reserved_at_98[0x8];
e281682b 4146
b4ff3a36 4147 u8 reserved_at_a0[0x8];
7486216b 4148 u8 srqn_xrqn[0x18];
e281682b 4149
b4ff3a36 4150 u8 reserved_at_c0[0x8];
e281682b
SM		 4151 u8 pd[0x18];
4152
4153 u8 tclass[0x8];
b4ff3a36 4154 u8 reserved_at_e8[0x4];
e281682b
SM		 4155 u8 flow_label[0x14];
4156
4157 u8 dc_access_key[0x40];
4158
b4ff3a36 4159 u8 reserved_at_140[0x5];
e281682b
SM		 4160 u8 mtu[0x3];
4161 u8 port[0x8];
4162 u8 pkey_index[0x10];
4163
b4ff3a36 4164 u8 reserved_at_160[0x8];
e281682b 4165 u8 my_addr_index[0x8];
b4ff3a36 4166 u8 reserved_at_170[0x8];
e281682b
SM		 4167 u8 hop_limit[0x8];
4168
4169 u8 dc_access_key_violation_count[0x20];
4170
b4ff3a36 4171 u8 reserved_at_1a0[0x14];
e281682b
SM		 4172 u8 dei_cfi[0x1];
4173 u8 eth_prio[0x3];
4174 u8 ecn[0x2];
4175 u8 dscp[0x6];
4176
a645a89d
LR		 4177 u8 reserved_at_1c0[0x20];
4178 u8 ece[0x20];
e281682b
SM		 4179};
4180
4181enum {
4182 MLX5_CQC_STATUS_OK = 0x0,
4183 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4184 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4185};
4186
4187enum {
4188 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4189 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4190};
4191
4192enum {
4193 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4194 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4195 MLX5_CQC_ST_FIRED = 0xa,
4196};
4197
7d5e1423
SM		 4198enum {
4199 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4200 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 4201 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 4202};
4203
e281682b
SM		 4204struct mlx5_ifc_cqc_bits {
4205 u8 status[0x4];
bd371975
LR		 4206 u8 reserved_at_4[0x2];
4207 u8 dbr_umem_valid[0x1];
616d5769 4208 u8 apu_cq[0x1];
e281682b
SM		 4209 u8 cqe_sz[0x3];
4210 u8 cc[0x1];
b4ff3a36 4211 u8 reserved_at_c[0x1];
e281682b
SM		 4212 u8 scqe_break_moderation_en[0x1];
4213 u8 oi[0x1];
7d5e1423
SM		 4214 u8 cq_period_mode[0x2];
4215 u8 cqe_comp_en[0x1];
e281682b
SM		 4216 u8 mini_cqe_res_format[0x2];
4217 u8 st[0x4];
cdcdce94
OL		 4218 u8 reserved_at_18[0x6];
4219 u8 cqe_compression_layout[0x2];
e281682b 4220
b4ff3a36 4221 u8 reserved_at_20[0x20];
e281682b 4222
b4ff3a36 4223 u8 reserved_at_40[0x14];
e281682b 4224 u8 page_offset[0x6];
b4ff3a36 4225 u8 reserved_at_5a[0x6];
e281682b 4226
b4ff3a36 4227 u8 reserved_at_60[0x3];
e281682b
SM		 4228 u8 log_cq_size[0x5];
4229 u8 uar_page[0x18];
4230
b4ff3a36 4231 u8 reserved_at_80[0x4];
e281682b
SM		 4232 u8 cq_period[0xc];
4233 u8 cq_max_count[0x10];
4234
616d5769 4235 u8 c_eqn_or_apu_element[0x20];
e281682b 4236
b4ff3a36 4237 u8 reserved_at_c0[0x3];
e281682b 4238 u8 log_page_size[0x5];
b4ff3a36 4239 u8 reserved_at_c8[0x18];
e281682b 4240
b4ff3a36 4241 u8 reserved_at_e0[0x20];
e281682b 4242
b4ff3a36 4243 u8 reserved_at_100[0x8];
e281682b
SM		 4244 u8 last_notified_index[0x18];
4245
b4ff3a36 4246 u8 reserved_at_120[0x8];
e281682b
SM		 4247 u8 last_solicit_index[0x18];
4248
b4ff3a36 4249 u8 reserved_at_140[0x8];
e281682b
SM		 4250 u8 consumer_counter[0x18];
4251
b4ff3a36 4252 u8 reserved_at_160[0x8];
e281682b
SM		 4253 u8 producer_counter[0x18];
4254
b4ff3a36 4255 u8 reserved_at_180[0x40];
e281682b
SM		 4256
4257 u8 dbr_addr[0x40];
4258};
4259
4260union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4261 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4262 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4263 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 4264 u8 reserved_at_0[0x800];
e281682b
SM		 4265};
4266
4267struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 4268 u8 reserved_at_0[0xc0];
e281682b 4269
b4ff3a36 4270 u8 reserved_at_c0[0x8];
211e6c80
MD		 4271 u8 ieee_vendor_id[0x18];
4272
b4ff3a36 4273 u8 reserved_at_e0[0x10];
e281682b
SM		 4274 u8 vsd_vendor_id[0x10];
4275
4276 u8 vsd[208][0x8];
4277
4278 u8 vsd_contd_psid[16][0x8];
4279};
4280
7486216b
SM		 4281enum {
4282 MLX5_XRQC_STATE_GOOD = 0x0,
4283 MLX5_XRQC_STATE_ERROR = 0x1,
4284};
4285
4286enum {
4287 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4288 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4289};
4290
4291enum {
4292 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4293};
4294
4295struct mlx5_ifc_tag_matching_topology_context_bits {
4296 u8 log_matching_list_sz[0x4];
4297 u8 reserved_at_4[0xc];
4298 u8 append_next_index[0x10];
4299
4300 u8 sw_phase_cnt[0x10];
4301 u8 hw_phase_cnt[0x10];
4302
4303 u8 reserved_at_40[0x40];
4304};
4305
4306struct mlx5_ifc_xrqc_bits {
4307 u8 state[0x4];
4308 u8 rlkey[0x1];
4309 u8 reserved_at_5[0xf];
4310 u8 topology[0x4];
4311 u8 reserved_at_18[0x4];
4312 u8 offload[0x4];
4313
4314 u8 reserved_at_20[0x8];
4315 u8 user_index[0x18];
4316
4317 u8 reserved_at_40[0x8];
4318 u8 cqn[0x18];
4319
4320 u8 reserved_at_60[0xa0];
4321
4322 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4323
6e44636a 4324 u8 reserved_at_180[0x280];
7486216b
SM		 4325
4326 struct mlx5_ifc_wq_bits wq;
4327};
4328
e281682b
SM		 4329union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4330 struct mlx5_ifc_modify_field_select_bits modify_field_select;
4331 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 4332 u8 reserved_at_0[0x20];
e281682b
SM		 4333};
4334
4335union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4336 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4337 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4338 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 4339 u8 reserved_at_0[0x20];
e281682b
SM		 4340};
4341
4342union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4343 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4344 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4345 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4346 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4347 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4348 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 4349 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4350 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
1c64bf6f 4351 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 4352 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 4353 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 4354 u8 reserved_at_0[0x7c0];
e281682b
SM		 4355};
4356
8ed1a630
GP		 4357union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4358 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4359 u8 reserved_at_0[0x7c0];
4360};
4361
e281682b
SM		 4362union mlx5_ifc_event_auto_bits {
4363 struct mlx5_ifc_comp_event_bits comp_event;
4364 struct mlx5_ifc_dct_events_bits dct_events;
4365 struct mlx5_ifc_qp_events_bits qp_events;
4366 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4367 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4368 struct mlx5_ifc_cq_error_bits cq_error;
4369 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4370 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4371 struct mlx5_ifc_gpio_event_bits gpio_event;
4372 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4373 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4374 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 4375 u8 reserved_at_0[0xe0];
e281682b
SM		 4376};
4377
4378struct mlx5_ifc_health_buffer_bits {
b4ff3a36 4379 u8 reserved_at_0[0x100];
e281682b
SM		 4380
4381 u8 assert_existptr[0x20];
4382
4383 u8 assert_callra[0x20];
4384
cb464ba5
AL		 4385 u8 reserved_at_140[0x20];
4386
4387 u8 time[0x20];
e281682b
SM		 4388
4389 u8 fw_version[0x20];
4390
4391 u8 hw_id[0x20];
4392
cb464ba5
AL		 4393 u8 rfr[0x1];
4394 u8 reserved_at_1c1[0x3];
4395 u8 valid[0x1];
4396 u8 severity[0x3];
4397 u8 reserved_at_1c8[0x18];
e281682b
SM		 4398
4399 u8 irisc_index[0x8];
4400 u8 synd[0x8];
4401 u8 ext_synd[0x10];
4402};
4403
4404struct mlx5_ifc_register_loopback_control_bits {
4405 u8 no_lb[0x1];
b4ff3a36 4406 u8 reserved_at_1[0x7];
e281682b 4407 u8 port[0x8];
b4ff3a36 4408 u8 reserved_at_10[0x10];
e281682b 4409
b4ff3a36 4410 u8 reserved_at_20[0x60];
e281682b
SM		 4411};
4412
813f8540
MHY		 4413struct mlx5_ifc_vport_tc_element_bits {
4414 u8 traffic_class[0x4];
4415 u8 reserved_at_4[0xc];
4416 u8 vport_number[0x10];
4417};
4418
4419struct mlx5_ifc_vport_element_bits {
4420 u8 reserved_at_0[0x10];
4421 u8 vport_number[0x10];
4422};
4423
4424enum {
4425 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4426 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4427 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4428};
4429
4430struct mlx5_ifc_tsar_element_bits {
4431 u8 reserved_at_0[0x8];
4432 u8 tsar_type[0x8];
4433 u8 reserved_at_10[0x10];
4434};
4435
8812c24d
MD		 4436enum {
4437 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4438 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4439};
4440
e281682b
SM		 4441struct mlx5_ifc_teardown_hca_out_bits {
4442 u8 status[0x8];
b4ff3a36 4443 u8 reserved_at_8[0x18];
e281682b
SM		 4444
4445 u8 syndrome[0x20];
4446
8812c24d
MD		 4447 u8 reserved_at_40[0x3f];
4448
fcd29ad1 4449 u8 state[0x1];
e281682b
SM		 4450};
4451
4452enum {
4453 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 4454 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
fcd29ad1 4455 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
e281682b
SM		 4456};
4457
4458struct mlx5_ifc_teardown_hca_in_bits {
4459 u8 opcode[0x10];
b4ff3a36 4460 u8 reserved_at_10[0x10];
e281682b 4461
b4ff3a36 4462 u8 reserved_at_20[0x10];
e281682b
SM		 4463 u8 op_mod[0x10];
4464
b4ff3a36 4465 u8 reserved_at_40[0x10];
e281682b
SM		 4466 u8 profile[0x10];
4467
b4ff3a36 4468 u8 reserved_at_60[0x20];
e281682b
SM		 4469};
4470
4471struct mlx5_ifc_sqerr2rts_qp_out_bits {
4472 u8 status[0x8];
b4ff3a36 4473 u8 reserved_at_8[0x18];
e281682b
SM		 4474
4475 u8 syndrome[0x20];
4476
b4ff3a36 4477 u8 reserved_at_40[0x40];
e281682b
SM		 4478};
4479
4480struct mlx5_ifc_sqerr2rts_qp_in_bits {
4481 u8 opcode[0x10];
4ac63ec7 4482 u8 uid[0x10];
e281682b 4483
b4ff3a36 4484 u8 reserved_at_20[0x10];
e281682b
SM		 4485 u8 op_mod[0x10];
4486
b4ff3a36 4487 u8 reserved_at_40[0x8];
e281682b
SM		 4488 u8 qpn[0x18];
4489
b4ff3a36 4490 u8 reserved_at_60[0x20];
e281682b
SM		 4491
4492 u8 opt_param_mask[0x20];
4493
b4ff3a36 4494 u8 reserved_at_a0[0x20];
e281682b
SM		 4495
4496 struct mlx5_ifc_qpc_bits qpc;
4497
b4ff3a36 4498 u8 reserved_at_800[0x80];
e281682b
SM		 4499};
4500
4501struct mlx5_ifc_sqd2rts_qp_out_bits {
4502 u8 status[0x8];
b4ff3a36 4503 u8 reserved_at_8[0x18];
e281682b
SM		 4504
4505 u8 syndrome[0x20];
4506
b4ff3a36 4507 u8 reserved_at_40[0x40];
e281682b
SM		 4508};
4509
4510struct mlx5_ifc_sqd2rts_qp_in_bits {
4511 u8 opcode[0x10];
4ac63ec7 4512 u8 uid[0x10];
e281682b 4513
b4ff3a36 4514 u8 reserved_at_20[0x10];
e281682b
SM		 4515 u8 op_mod[0x10];
4516
b4ff3a36 4517 u8 reserved_at_40[0x8];
e281682b
SM		 4518 u8 qpn[0x18];
4519
b4ff3a36 4520 u8 reserved_at_60[0x20];
e281682b
SM		 4521
4522 u8 opt_param_mask[0x20];
4523
b4ff3a36 4524 u8 reserved_at_a0[0x20];
e281682b
SM		 4525
4526 struct mlx5_ifc_qpc_bits qpc;
4527
b4ff3a36 4528 u8 reserved_at_800[0x80];
e281682b
SM		 4529};
4530
4531struct mlx5_ifc_set_roce_address_out_bits {
4532 u8 status[0x8];
b4ff3a36 4533 u8 reserved_at_8[0x18];
e281682b
SM		 4534
4535 u8 syndrome[0x20];
4536
b4ff3a36 4537 u8 reserved_at_40[0x40];
e281682b
SM		 4538};
4539
4540struct mlx5_ifc_set_roce_address_in_bits {
4541 u8 opcode[0x10];
b4ff3a36 4542 u8 reserved_at_10[0x10];
e281682b 4543
b4ff3a36 4544 u8 reserved_at_20[0x10];
e281682b
SM		 4545 u8 op_mod[0x10];
4546
4547 u8 roce_address_index[0x10];
32f69e4b
DJ		 4548 u8 reserved_at_50[0xc];
4549 u8 vhca_port_num[0x4];
e281682b 4550
b4ff3a36 4551 u8 reserved_at_60[0x20];
e281682b
SM		 4552
4553 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4554};
4555
4556struct mlx5_ifc_set_mad_demux_out_bits {
4557 u8 status[0x8];
b4ff3a36 4558 u8 reserved_at_8[0x18];
e281682b
SM		 4559
4560 u8 syndrome[0x20];
4561
b4ff3a36 4562 u8 reserved_at_40[0x40];
e281682b
SM		 4563};
4564
4565enum {
4566 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4567 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4568};
4569
4570struct mlx5_ifc_set_mad_demux_in_bits {
4571 u8 opcode[0x10];
b4ff3a36 4572 u8 reserved_at_10[0x10];
e281682b 4573
b4ff3a36 4574 u8 reserved_at_20[0x10];
e281682b
SM		 4575 u8 op_mod[0x10];
4576
b4ff3a36 4577 u8 reserved_at_40[0x20];
e281682b 4578
b4ff3a36 4579 u8 reserved_at_60[0x6];
e281682b 4580 u8 demux_mode[0x2];
b4ff3a36 4581 u8 reserved_at_68[0x18];
e281682b
SM		 4582};
4583
4584struct mlx5_ifc_set_l2_table_entry_out_bits {
4585 u8 status[0x8];
b4ff3a36 4586 u8 reserved_at_8[0x18];
e281682b
SM		 4587
4588 u8 syndrome[0x20];
4589
b4ff3a36 4590 u8 reserved_at_40[0x40];
e281682b
SM		 4591};
4592
4593struct mlx5_ifc_set_l2_table_entry_in_bits {
4594 u8 opcode[0x10];
b4ff3a36 4595 u8 reserved_at_10[0x10];
e281682b 4596
b4ff3a36 4597 u8 reserved_at_20[0x10];
e281682b
SM		 4598 u8 op_mod[0x10];
4599
b4ff3a36 4600 u8 reserved_at_40[0x60];
e281682b 4601
b4ff3a36 4602 u8 reserved_at_a0[0x8];
e281682b
SM		 4603 u8 table_index[0x18];
4604
b4ff3a36 4605 u8 reserved_at_c0[0x20];
e281682b 4606
b4ff3a36 4607 u8 reserved_at_e0[0x13];
e281682b
SM		 4608 u8 vlan_valid[0x1];
4609 u8 vlan[0xc];
4610
4611 struct mlx5_ifc_mac_address_layout_bits mac_address;
4612
b4ff3a36 4613 u8 reserved_at_140[0xc0];
e281682b
SM		 4614};
4615
4616struct mlx5_ifc_set_issi_out_bits {
4617 u8 status[0x8];
b4ff3a36 4618 u8 reserved_at_8[0x18];
e281682b
SM		 4619
4620 u8 syndrome[0x20];
4621
b4ff3a36 4622 u8 reserved_at_40[0x40];
e281682b
SM		 4623};
4624
4625struct mlx5_ifc_set_issi_in_bits {
4626 u8 opcode[0x10];
b4ff3a36 4627 u8 reserved_at_10[0x10];
e281682b 4628
b4ff3a36 4629 u8 reserved_at_20[0x10];
e281682b
SM		 4630 u8 op_mod[0x10];
4631
b4ff3a36 4632 u8 reserved_at_40[0x10];
e281682b
SM		 4633 u8 current_issi[0x10];
4634
b4ff3a36 4635 u8 reserved_at_60[0x20];
e281682b
SM		 4636};
4637
4638struct mlx5_ifc_set_hca_cap_out_bits {
4639 u8 status[0x8];
b4ff3a36 4640 u8 reserved_at_8[0x18];
e281682b
SM		 4641
4642 u8 syndrome[0x20];
4643
b4ff3a36 4644 u8 reserved_at_40[0x40];
e281682b
SM		 4645};
4646
4647struct mlx5_ifc_set_hca_cap_in_bits {
4648 u8 opcode[0x10];
b4ff3a36 4649 u8 reserved_at_10[0x10];
e281682b 4650
b4ff3a36 4651 u8 reserved_at_20[0x10];
e281682b
SM		 4652 u8 op_mod[0x10];
4653
959af556
YH		 4654 u8 other_function[0x1];
4655 u8 reserved_at_41[0xf];
4656 u8 function_id[0x10];
4657
4658 u8 reserved_at_60[0x20];
e281682b
SM		 4659
4660 union mlx5_ifc_hca_cap_union_bits capability;
4661};
4662
26a81453
MG		 4663enum {
4664 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4665 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4666 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2b58f6d9
RS		 4667 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4668 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
26a81453
MG		 4669};
4670
e281682b
SM		 4671struct mlx5_ifc_set_fte_out_bits {
4672 u8 status[0x8];
b4ff3a36 4673 u8 reserved_at_8[0x18];
e281682b
SM		 4674
4675 u8 syndrome[0x20];
4676
b4ff3a36 4677 u8 reserved_at_40[0x40];
e281682b
SM		 4678};
4679
4680struct mlx5_ifc_set_fte_in_bits {
4681 u8 opcode[0x10];
b4ff3a36 4682 u8 reserved_at_10[0x10];
e281682b 4683
b4ff3a36 4684 u8 reserved_at_20[0x10];
e281682b
SM		 4685 u8 op_mod[0x10];
4686
7d5e1423
SM		 4687 u8 other_vport[0x1];
4688 u8 reserved_at_41[0xf];
4689 u8 vport_number[0x10];
4690
4691 u8 reserved_at_60[0x20];
e281682b
SM		 4692
4693 u8 table_type[0x8];
b4ff3a36 4694 u8 reserved_at_88[0x18];
e281682b 4695
b4ff3a36 4696 u8 reserved_at_a0[0x8];
e281682b
SM		 4697 u8 table_id[0x18];
4698
822e114b
PB		 4699 u8 ignore_flow_level[0x1];
4700 u8 reserved_at_c1[0x17];
26a81453
MG		 4701 u8 modify_enable_mask[0x8];
4702
b4ff3a36 4703 u8 reserved_at_e0[0x20];
e281682b
SM		 4704
4705 u8 flow_index[0x20];
4706
b4ff3a36 4707 u8 reserved_at_120[0xe0];
e281682b
SM		 4708
4709 struct mlx5_ifc_flow_context_bits flow_context;
4710};
4711
4712struct mlx5_ifc_rts2rts_qp_out_bits {
4713 u8 status[0x8];
b4ff3a36 4714 u8 reserved_at_8[0x18];
e281682b
SM		 4715
4716 u8 syndrome[0x20];
4717
6b646a7e
LR		 4718 u8 reserved_at_40[0x20];
4719 u8 ece[0x20];
e281682b
SM		 4720};
4721
4722struct mlx5_ifc_rts2rts_qp_in_bits {
4723 u8 opcode[0x10];
4ac63ec7 4724 u8 uid[0x10];
e281682b 4725
b4ff3a36 4726 u8 reserved_at_20[0x10];
e281682b
SM		 4727 u8 op_mod[0x10];
4728
b4ff3a36 4729 u8 reserved_at_40[0x8];
e281682b
SM		 4730 u8 qpn[0x18];
4731
b4ff3a36 4732 u8 reserved_at_60[0x20];
e281682b
SM		 4733
4734 u8 opt_param_mask[0x20];
4735
6b646a7e 4736 u8 ece[0x20];
e281682b
SM		 4737
4738 struct mlx5_ifc_qpc_bits qpc;
4739
b4ff3a36 4740 u8 reserved_at_800[0x80];
e281682b
SM		 4741};
4742
4743struct mlx5_ifc_rtr2rts_qp_out_bits {
4744 u8 status[0x8];
b4ff3a36 4745 u8 reserved_at_8[0x18];
e281682b
SM		 4746
4747 u8 syndrome[0x20];
4748
6b646a7e
LR		 4749 u8 reserved_at_40[0x20];
4750 u8 ece[0x20];
e281682b
SM		 4751};
4752
4753struct mlx5_ifc_rtr2rts_qp_in_bits {
4754 u8 opcode[0x10];
4ac63ec7 4755 u8 uid[0x10];
e281682b 4756
b4ff3a36 4757 u8 reserved_at_20[0x10];
e281682b
SM		 4758 u8 op_mod[0x10];
4759
b4ff3a36 4760 u8 reserved_at_40[0x8];
e281682b
SM		 4761 u8 qpn[0x18];
4762
b4ff3a36 4763 u8 reserved_at_60[0x20];
e281682b
SM		 4764
4765 u8 opt_param_mask[0x20];
4766
6b646a7e 4767 u8 ece[0x20];
e281682b
SM		 4768
4769 struct mlx5_ifc_qpc_bits qpc;
4770
b4ff3a36 4771 u8 reserved_at_800[0x80];
e281682b
SM		 4772};
4773
4774struct mlx5_ifc_rst2init_qp_out_bits {
4775 u8 status[0x8];
b4ff3a36 4776 u8 reserved_at_8[0x18];
e281682b
SM		 4777
4778 u8 syndrome[0x20];
4779
ab183d46
LR		 4780 u8 reserved_at_40[0x20];
4781 u8 ece[0x20];
e281682b
SM		 4782};
4783
4784struct mlx5_ifc_rst2init_qp_in_bits {
4785 u8 opcode[0x10];
4ac63ec7 4786 u8 uid[0x10];
e281682b 4787
b4ff3a36 4788 u8 reserved_at_20[0x10];
e281682b
SM		 4789 u8 op_mod[0x10];
4790
b4ff3a36 4791 u8 reserved_at_40[0x8];
e281682b
SM		 4792 u8 qpn[0x18];
4793
b4ff3a36 4794 u8 reserved_at_60[0x20];
e281682b
SM		 4795
4796 u8 opt_param_mask[0x20];
4797
ab183d46 4798 u8 ece[0x20];
e281682b
SM		 4799
4800 struct mlx5_ifc_qpc_bits qpc;
4801
b4ff3a36 4802 u8 reserved_at_800[0x80];
e281682b
SM		 4803};
4804
7486216b
SM		 4805struct mlx5_ifc_query_xrq_out_bits {
4806 u8 status[0x8];
4807 u8 reserved_at_8[0x18];
4808
4809 u8 syndrome[0x20];
4810
4811 u8 reserved_at_40[0x40];
4812
4813 struct mlx5_ifc_xrqc_bits xrq_context;
4814};
4815
4816struct mlx5_ifc_query_xrq_in_bits {
4817 u8 opcode[0x10];
4818 u8 reserved_at_10[0x10];
4819
4820 u8 reserved_at_20[0x10];
4821 u8 op_mod[0x10];
4822
4823 u8 reserved_at_40[0x8];
4824 u8 xrqn[0x18];
4825
4826 u8 reserved_at_60[0x20];
4827};
4828
e281682b
SM		 4829struct mlx5_ifc_query_xrc_srq_out_bits {
4830 u8 status[0x8];
b4ff3a36 4831 u8 reserved_at_8[0x18];
e281682b
SM		 4832
4833 u8 syndrome[0x20];
4834
b4ff3a36 4835 u8 reserved_at_40[0x40];
e281682b
SM		 4836
4837 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4838
b4ff3a36 4839 u8 reserved_at_280[0x600];
e281682b 4840
b6ca09cb 4841 u8 pas[][0x40];
e281682b
SM		 4842};
4843
4844struct mlx5_ifc_query_xrc_srq_in_bits {
4845 u8 opcode[0x10];
b4ff3a36 4846 u8 reserved_at_10[0x10];
e281682b 4847
b4ff3a36 4848 u8 reserved_at_20[0x10];
e281682b
SM		 4849 u8 op_mod[0x10];
4850
b4ff3a36 4851 u8 reserved_at_40[0x8];
e281682b
SM		 4852 u8 xrc_srqn[0x18];
4853
b4ff3a36 4854 u8 reserved_at_60[0x20];
e281682b
SM		 4855};
4856
4857enum {
4858 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4859 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4860};
4861
4862struct mlx5_ifc_query_vport_state_out_bits {
4863 u8 status[0x8];
b4ff3a36 4864 u8 reserved_at_8[0x18];
e281682b
SM		 4865
4866 u8 syndrome[0x20];
4867
b4ff3a36 4868 u8 reserved_at_40[0x20];
e281682b 4869
b4ff3a36 4870 u8 reserved_at_60[0x18];
e281682b
SM		 4871 u8 admin_state[0x4];
4872 u8 state[0x4];
4873};
4874
4875enum {
cc9c82a8
EBE		 4876 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4877 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
7d0314b1 4878 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
e281682b
SM		 4879};
4880
fd4572b3
ED		 4881struct mlx5_ifc_arm_monitor_counter_in_bits {
4882 u8 opcode[0x10];
4883 u8 uid[0x10];
4884
4885 u8 reserved_at_20[0x10];
4886 u8 op_mod[0x10];
4887
4888 u8 reserved_at_40[0x20];
4889
4890 u8 reserved_at_60[0x20];
4891};
4892
4893struct mlx5_ifc_arm_monitor_counter_out_bits {
4894 u8 status[0x8];
4895 u8 reserved_at_8[0x18];
4896
4897 u8 syndrome[0x20];
4898
4899 u8 reserved_at_40[0x40];
4900};
4901
4902enum {
4903 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4904 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4905};
4906
4907enum mlx5_monitor_counter_ppcnt {
4c8b8518
SM		 4908 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4909 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4910 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4911 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4912 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4913 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
fd4572b3
ED		 4914};
4915
4916enum {
4c8b8518 4917 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
fd4572b3
ED		 4918};
4919
4920struct mlx5_ifc_monitor_counter_output_bits {
4921 u8 reserved_at_0[0x4];
4922 u8 type[0x4];
4923 u8 reserved_at_8[0x8];
4924 u8 counter[0x10];
4925
4926 u8 counter_group_id[0x20];
4927};
4928
4929#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4930#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4931#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4932 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4933
4934struct mlx5_ifc_set_monitor_counter_in_bits {
4935 u8 opcode[0x10];
4936 u8 uid[0x10];
4937
4938 u8 reserved_at_20[0x10];
4939 u8 op_mod[0x10];
4940
4941 u8 reserved_at_40[0x10];
4942 u8 num_of_counters[0x10];
4943
4944 u8 reserved_at_60[0x20];
4945
4946 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4947};
4948
4949struct mlx5_ifc_set_monitor_counter_out_bits {
4950 u8 status[0x8];
4951 u8 reserved_at_8[0x18];
4952
4953 u8 syndrome[0x20];
4954
4955 u8 reserved_at_40[0x40];
4956};
4957
e281682b
SM		 4958struct mlx5_ifc_query_vport_state_in_bits {
4959 u8 opcode[0x10];
b4ff3a36 4960 u8 reserved_at_10[0x10];
e281682b 4961
b4ff3a36 4962 u8 reserved_at_20[0x10];
e281682b
SM		 4963 u8 op_mod[0x10];
4964
4965 u8 other_vport[0x1];
b4ff3a36 4966 u8 reserved_at_41[0xf];
e281682b
SM		 4967 u8 vport_number[0x10];
4968
b4ff3a36 4969 u8 reserved_at_60[0x20];
e281682b
SM		 4970};
4971
61c5b5c9
MS		 4972struct mlx5_ifc_query_vnic_env_out_bits {
4973 u8 status[0x8];
4974 u8 reserved_at_8[0x18];
4975
4976 u8 syndrome[0x20];
4977
4978 u8 reserved_at_40[0x40];
4979
4980 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4981};
4982
4983enum {
4984 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4985};
4986
4987struct mlx5_ifc_query_vnic_env_in_bits {
4988 u8 opcode[0x10];
4989 u8 reserved_at_10[0x10];
4990
4991 u8 reserved_at_20[0x10];
4992 u8 op_mod[0x10];
4993
4994 u8 other_vport[0x1];
4995 u8 reserved_at_41[0xf];
4996 u8 vport_number[0x10];
4997
4998 u8 reserved_at_60[0x20];
4999};
5000
e281682b
SM		 5001struct mlx5_ifc_query_vport_counter_out_bits {
5002 u8 status[0x8];
b4ff3a36 5003 u8 reserved_at_8[0x18];
e281682b
SM		 5004
5005 u8 syndrome[0x20];
5006
b4ff3a36 5007 u8 reserved_at_40[0x40];
e281682b
SM		 5008
5009 struct mlx5_ifc_traffic_counter_bits received_errors;
5010
5011 struct mlx5_ifc_traffic_counter_bits transmit_errors;
5012
5013 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5014
5015 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5016
5017 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5018
5019 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5020
5021 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5022
5023 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5024
5025 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5026
5027 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5028
5029 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5030
5031 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5032
b4ff3a36 5033 u8 reserved_at_680[0xa00];
e281682b
SM		 5034};
5035
5036enum {
5037 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
5038};
5039
5040struct mlx5_ifc_query_vport_counter_in_bits {
5041 u8 opcode[0x10];
b4ff3a36 5042 u8 reserved_at_10[0x10];
e281682b 5043
b4ff3a36 5044 u8 reserved_at_20[0x10];
e281682b
SM		 5045 u8 op_mod[0x10];
5046
5047 u8 other_vport[0x1];
b54ba277
MY		 5048 u8 reserved_at_41[0xb];
5049 u8 port_num[0x4];
e281682b
SM		 5050 u8 vport_number[0x10];
5051
b4ff3a36 5052 u8 reserved_at_60[0x60];
e281682b
SM		 5053
5054 u8 clear[0x1];
b4ff3a36 5055 u8 reserved_at_c1[0x1f];
e281682b 5056
b4ff3a36 5057 u8 reserved_at_e0[0x20];
e281682b
SM		 5058};
5059
5060struct mlx5_ifc_query_tis_out_bits {
5061 u8 status[0x8];
b4ff3a36 5062 u8 reserved_at_8[0x18];
e281682b
SM		 5063
5064 u8 syndrome[0x20];
5065
b4ff3a36 5066 u8 reserved_at_40[0x40];
e281682b
SM		 5067
5068 struct mlx5_ifc_tisc_bits tis_context;
5069};
5070
5071struct mlx5_ifc_query_tis_in_bits {
5072 u8 opcode[0x10];
b4ff3a36 5073 u8 reserved_at_10[0x10];
e281682b 5074
b4ff3a36 5075 u8 reserved_at_20[0x10];
e281682b
SM		 5076 u8 op_mod[0x10];
5077
b4ff3a36 5078 u8 reserved_at_40[0x8];
e281682b
SM		 5079 u8 tisn[0x18];
5080
b4ff3a36 5081 u8 reserved_at_60[0x20];
e281682b
SM		 5082};
5083
5084struct mlx5_ifc_query_tir_out_bits {
5085 u8 status[0x8];
b4ff3a36 5086 u8 reserved_at_8[0x18];
e281682b
SM		 5087
5088 u8 syndrome[0x20];
5089
b4ff3a36 5090 u8 reserved_at_40[0xc0];
e281682b
SM		 5091
5092 struct mlx5_ifc_tirc_bits tir_context;
5093};
5094
5095struct mlx5_ifc_query_tir_in_bits {
5096 u8 opcode[0x10];
b4ff3a36 5097 u8 reserved_at_10[0x10];
e281682b 5098
b4ff3a36 5099 u8 reserved_at_20[0x10];
e281682b
SM		 5100 u8 op_mod[0x10];
5101
b4ff3a36 5102 u8 reserved_at_40[0x8];
e281682b
SM		 5103 u8 tirn[0x18];
5104
b4ff3a36 5105 u8 reserved_at_60[0x20];
e281682b
SM		 5106};
5107
5108struct mlx5_ifc_query_srq_out_bits {
5109 u8 status[0x8];
b4ff3a36 5110 u8 reserved_at_8[0x18];
e281682b
SM		 5111
5112 u8 syndrome[0x20];
5113
b4ff3a36 5114 u8 reserved_at_40[0x40];
e281682b
SM		 5115
5116 struct mlx5_ifc_srqc_bits srq_context_entry;
5117
b4ff3a36 5118 u8 reserved_at_280[0x600];
e281682b 5119
b6ca09cb 5120 u8 pas[][0x40];
e281682b
SM		 5121};
5122
5123struct mlx5_ifc_query_srq_in_bits {
5124 u8 opcode[0x10];
b4ff3a36 5125 u8 reserved_at_10[0x10];
e281682b 5126
b4ff3a36 5127 u8 reserved_at_20[0x10];
e281682b
SM		 5128 u8 op_mod[0x10];
5129
b4ff3a36 5130 u8 reserved_at_40[0x8];
e281682b
SM		 5131 u8 srqn[0x18];
5132
b4ff3a36 5133 u8 reserved_at_60[0x20];
e281682b
SM		 5134};
5135
5136struct mlx5_ifc_query_sq_out_bits {
5137 u8 status[0x8];
b4ff3a36 5138 u8 reserved_at_8[0x18];
e281682b
SM		 5139
5140 u8 syndrome[0x20];
5141
b4ff3a36 5142 u8 reserved_at_40[0xc0];
e281682b
SM		 5143
5144 struct mlx5_ifc_sqc_bits sq_context;
5145};
5146
5147struct mlx5_ifc_query_sq_in_bits {
5148 u8 opcode[0x10];
b4ff3a36 5149 u8 reserved_at_10[0x10];
e281682b 5150
b4ff3a36 5151 u8 reserved_at_20[0x10];
e281682b
SM		 5152 u8 op_mod[0x10];
5153
b4ff3a36 5154 u8 reserved_at_40[0x8];
e281682b
SM		 5155 u8 sqn[0x18];
5156
b4ff3a36 5157 u8 reserved_at_60[0x20];
e281682b
SM		 5158};
5159
5160struct mlx5_ifc_query_special_contexts_out_bits {
5161 u8 status[0x8];
b4ff3a36 5162 u8 reserved_at_8[0x18];
e281682b
SM		 5163
5164 u8 syndrome[0x20];
5165
ec22eb53 5166 u8 dump_fill_mkey[0x20];
e281682b
SM		 5167
5168 u8 resd_lkey[0x20];
bcda1aca
AK		 5169
5170 u8 null_mkey[0x20];
5171
5172 u8 reserved_at_a0[0x60];
e281682b
SM		 5173};
5174
5175struct mlx5_ifc_query_special_contexts_in_bits {
5176 u8 opcode[0x10];
b4ff3a36 5177 u8 reserved_at_10[0x10];
e281682b 5178
b4ff3a36 5179 u8 reserved_at_20[0x10];
e281682b
SM		 5180 u8 op_mod[0x10];
5181
b4ff3a36 5182 u8 reserved_at_40[0x40];
e281682b
SM		 5183};
5184
813f8540
MHY		 5185struct mlx5_ifc_query_scheduling_element_out_bits {
5186 u8 opcode[0x10];
5187 u8 reserved_at_10[0x10];
5188
5189 u8 reserved_at_20[0x10];
5190 u8 op_mod[0x10];
5191
5192 u8 reserved_at_40[0xc0];
5193
5194 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5195
5196 u8 reserved_at_300[0x100];
5197};
5198
5199enum {
5200 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
214baf22 5201 SCHEDULING_HIERARCHY_NIC = 0x3,
813f8540
MHY		 5202};
5203
5204struct mlx5_ifc_query_scheduling_element_in_bits {
5205 u8 opcode[0x10];
5206 u8 reserved_at_10[0x10];
5207
5208 u8 reserved_at_20[0x10];
5209 u8 op_mod[0x10];
5210
5211 u8 scheduling_hierarchy[0x8];
5212 u8 reserved_at_48[0x18];
5213
5214 u8 scheduling_element_id[0x20];
5215
5216 u8 reserved_at_80[0x180];
5217};
5218
e281682b
SM		 5219struct mlx5_ifc_query_rqt_out_bits {
5220 u8 status[0x8];
b4ff3a36 5221 u8 reserved_at_8[0x18];
e281682b
SM		 5222
5223 u8 syndrome[0x20];
5224
b4ff3a36 5225 u8 reserved_at_40[0xc0];
e281682b
SM		 5226
5227 struct mlx5_ifc_rqtc_bits rqt_context;
5228};
5229
5230struct mlx5_ifc_query_rqt_in_bits {
5231 u8 opcode[0x10];
b4ff3a36 5232 u8 reserved_at_10[0x10];
e281682b 5233
b4ff3a36 5234 u8 reserved_at_20[0x10];
e281682b
SM		 5235 u8 op_mod[0x10];
5236
b4ff3a36 5237 u8 reserved_at_40[0x8];
e281682b
SM		 5238 u8 rqtn[0x18];
5239
b4ff3a36 5240 u8 reserved_at_60[0x20];
e281682b
SM		 5241};
5242
5243struct mlx5_ifc_query_rq_out_bits {
5244 u8 status[0x8];
b4ff3a36 5245 u8 reserved_at_8[0x18];
e281682b
SM		 5246
5247 u8 syndrome[0x20];
5248
b4ff3a36 5249 u8 reserved_at_40[0xc0];
e281682b
SM		 5250
5251 struct mlx5_ifc_rqc_bits rq_context;
5252};
5253
5254struct mlx5_ifc_query_rq_in_bits {
5255 u8 opcode[0x10];
b4ff3a36 5256 u8 reserved_at_10[0x10];
e281682b 5257
b4ff3a36 5258 u8 reserved_at_20[0x10];
e281682b
SM		 5259 u8 op_mod[0x10];
5260
b4ff3a36 5261 u8 reserved_at_40[0x8];
e281682b
SM		 5262 u8 rqn[0x18];
5263
b4ff3a36 5264 u8 reserved_at_60[0x20];
e281682b
SM		 5265};
5266
5267struct mlx5_ifc_query_roce_address_out_bits {
5268 u8 status[0x8];
b4ff3a36 5269 u8 reserved_at_8[0x18];
e281682b
SM		 5270
5271 u8 syndrome[0x20];
5272
b4ff3a36 5273 u8 reserved_at_40[0x40];
e281682b
SM		 5274
5275 struct mlx5_ifc_roce_addr_layout_bits roce_address;
5276};
5277
5278struct mlx5_ifc_query_roce_address_in_bits {
5279 u8 opcode[0x10];
b4ff3a36 5280 u8 reserved_at_10[0x10];
e281682b 5281
b4ff3a36 5282 u8 reserved_at_20[0x10];
e281682b
SM		 5283 u8 op_mod[0x10];
5284
5285 u8 roce_address_index[0x10];
32f69e4b
DJ		 5286 u8 reserved_at_50[0xc];
5287 u8 vhca_port_num[0x4];
e281682b 5288
b4ff3a36 5289 u8 reserved_at_60[0x20];
e281682b
SM		 5290};
5291
5292struct mlx5_ifc_query_rmp_out_bits {
5293 u8 status[0x8];
b4ff3a36 5294 u8 reserved_at_8[0x18];
e281682b
SM		 5295
5296 u8 syndrome[0x20];
5297
b4ff3a36 5298 u8 reserved_at_40[0xc0];
e281682b
SM		 5299
5300 struct mlx5_ifc_rmpc_bits rmp_context;
5301};
5302
5303struct mlx5_ifc_query_rmp_in_bits {
5304 u8 opcode[0x10];
b4ff3a36 5305 u8 reserved_at_10[0x10];
e281682b 5306
b4ff3a36 5307 u8 reserved_at_20[0x10];
e281682b
SM		 5308 u8 op_mod[0x10];
5309
b4ff3a36 5310 u8 reserved_at_40[0x8];
e281682b
SM		 5311 u8 rmpn[0x18];
5312
b4ff3a36 5313 u8 reserved_at_60[0x20];
e281682b
SM		 5314};
5315
5316struct mlx5_ifc_query_qp_out_bits {
5317 u8 status[0x8];
b4ff3a36 5318 u8 reserved_at_8[0x18];
e281682b
SM		 5319
5320 u8 syndrome[0x20];
5321
3fc2a9e8 5322 u8 reserved_at_40[0x40];
e281682b
SM		 5323
5324 u8 opt_param_mask[0x20];
5325
3fc2a9e8 5326 u8 ece[0x20];
e281682b
SM		 5327
5328 struct mlx5_ifc_qpc_bits qpc;
5329
b4ff3a36 5330 u8 reserved_at_800[0x80];
e281682b 5331
b6ca09cb 5332 u8 pas[][0x40];
e281682b
SM		 5333};
5334
5335struct mlx5_ifc_query_qp_in_bits {
5336 u8 opcode[0x10];
b4ff3a36 5337 u8 reserved_at_10[0x10];
e281682b 5338
b4ff3a36 5339 u8 reserved_at_20[0x10];
e281682b
SM		 5340 u8 op_mod[0x10];
5341
b4ff3a36 5342 u8 reserved_at_40[0x8];
e281682b
SM		 5343 u8 qpn[0x18];
5344
b4ff3a36 5345 u8 reserved_at_60[0x20];
e281682b
SM		 5346};
5347
5348struct mlx5_ifc_query_q_counter_out_bits {
5349 u8 status[0x8];
b4ff3a36 5350 u8 reserved_at_8[0x18];
e281682b
SM		 5351
5352 u8 syndrome[0x20];
5353
b4ff3a36 5354 u8 reserved_at_40[0x40];
e281682b
SM		 5355
5356 u8 rx_write_requests[0x20];
5357
b4ff3a36 5358 u8 reserved_at_a0[0x20];
e281682b
SM		 5359
5360 u8 rx_read_requests[0x20];
5361
b4ff3a36 5362 u8 reserved_at_e0[0x20];
e281682b
SM		 5363
5364 u8 rx_atomic_requests[0x20];
5365
b4ff3a36 5366 u8 reserved_at_120[0x20];
e281682b
SM		 5367
5368 u8 rx_dct_connect[0x20];
5369
b4ff3a36 5370 u8 reserved_at_160[0x20];
e281682b
SM		 5371
5372 u8 out_of_buffer[0x20];
5373
b4ff3a36 5374 u8 reserved_at_1a0[0x20];
e281682b
SM		 5375
5376 u8 out_of_sequence[0x20];
5377
7486216b
SM		 5378 u8 reserved_at_1e0[0x20];
5379
5380 u8 duplicate_request[0x20];
5381
5382 u8 reserved_at_220[0x20];
5383
5384 u8 rnr_nak_retry_err[0x20];
5385
5386 u8 reserved_at_260[0x20];
5387
5388 u8 packet_seq_err[0x20];
5389
5390 u8 reserved_at_2a0[0x20];
5391
5392 u8 implied_nak_seq_err[0x20];
5393
5394 u8 reserved_at_2e0[0x20];
5395
5396 u8 local_ack_timeout_err[0x20];
5397
58dcb60a
PP		 5398 u8 reserved_at_320[0xa0];
5399
5400 u8 resp_local_length_error[0x20];
5401
5402 u8 req_local_length_error[0x20];
5403
5404 u8 resp_local_qp_error[0x20];
5405
5406 u8 local_operation_error[0x20];
5407
5408 u8 resp_local_protection[0x20];
5409
5410 u8 req_local_protection[0x20];
5411
5412 u8 resp_cqe_error[0x20];
5413
5414 u8 req_cqe_error[0x20];
5415
5416 u8 req_mw_binding[0x20];
5417
5418 u8 req_bad_response[0x20];
5419
5420 u8 req_remote_invalid_request[0x20];
5421
5422 u8 resp_remote_invalid_request[0x20];
5423
5424 u8 req_remote_access_errors[0x20];
5425
5426 u8 resp_remote_access_errors[0x20];
5427
5428 u8 req_remote_operation_errors[0x20];
5429
5430 u8 req_transport_retries_exceeded[0x20];
5431
5432 u8 cq_overflow[0x20];
5433
5434 u8 resp_cqe_flush_error[0x20];
5435
5436 u8 req_cqe_flush_error[0x20];
5437
8fd5b75d
LR		 5438 u8 reserved_at_620[0x20];
5439
5440 u8 roce_adp_retrans[0x20];
5441
5442 u8 roce_adp_retrans_to[0x20];
5443
5444 u8 roce_slow_restart[0x20];
5445
5446 u8 roce_slow_restart_cnps[0x20];
5447
5448 u8 roce_slow_restart_trans[0x20];
5449
5450 u8 reserved_at_6e0[0x120];
e281682b
SM		 5451};
5452
5453struct mlx5_ifc_query_q_counter_in_bits {
5454 u8 opcode[0x10];
b4ff3a36 5455 u8 reserved_at_10[0x10];
e281682b 5456
b4ff3a36 5457 u8 reserved_at_20[0x10];
e281682b
SM		 5458 u8 op_mod[0x10];
5459
b4ff3a36 5460 u8 reserved_at_40[0x80];
e281682b
SM		 5461
5462 u8 clear[0x1];
b4ff3a36 5463 u8 reserved_at_c1[0x1f];
e281682b 5464
b4ff3a36 5465 u8 reserved_at_e0[0x18];
e281682b
SM		 5466 u8 counter_set_id[0x8];
5467};
5468
5469struct mlx5_ifc_query_pages_out_bits {
5470 u8 status[0x8];
b4ff3a36 5471 u8 reserved_at_8[0x18];
e281682b
SM		 5472
5473 u8 syndrome[0x20];
5474
591905ba
BW		 5475 u8 embedded_cpu_function[0x1];
5476 u8 reserved_at_41[0xf];
e281682b
SM		 5477 u8 function_id[0x10];
5478
5479 u8 num_pages[0x20];
5480};
5481
5482enum {
5483 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5484 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5485 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5486};
5487
5488struct mlx5_ifc_query_pages_in_bits {
5489 u8 opcode[0x10];
b4ff3a36 5490 u8 reserved_at_10[0x10];
e281682b 5491
b4ff3a36 5492 u8 reserved_at_20[0x10];
e281682b
SM		 5493 u8 op_mod[0x10];
5494
591905ba
BW		 5495 u8 embedded_cpu_function[0x1];
5496 u8 reserved_at_41[0xf];
e281682b
SM		 5497 u8 function_id[0x10];
5498
b4ff3a36 5499 u8 reserved_at_60[0x20];
e281682b
SM		 5500};
5501
5502struct mlx5_ifc_query_nic_vport_context_out_bits {
5503 u8 status[0x8];
b4ff3a36 5504 u8 reserved_at_8[0x18];
e281682b
SM		 5505
5506 u8 syndrome[0x20];
5507
b4ff3a36 5508 u8 reserved_at_40[0x40];
e281682b
SM		 5509
5510 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5511};
5512
5513struct mlx5_ifc_query_nic_vport_context_in_bits {
5514 u8 opcode[0x10];
b4ff3a36 5515 u8 reserved_at_10[0x10];
e281682b 5516
b4ff3a36 5517 u8 reserved_at_20[0x10];
e281682b
SM		 5518 u8 op_mod[0x10];
5519
5520 u8 other_vport[0x1];
b4ff3a36 5521 u8 reserved_at_41[0xf];
e281682b
SM		 5522 u8 vport_number[0x10];
5523
b4ff3a36 5524 u8 reserved_at_60[0x5];
e281682b 5525 u8 allowed_list_type[0x3];
b4ff3a36 5526 u8 reserved_at_68[0x18];
e281682b
SM		 5527};
5528
5529struct mlx5_ifc_query_mkey_out_bits {
5530 u8 status[0x8];
b4ff3a36 5531 u8 reserved_at_8[0x18];
e281682b
SM		 5532
5533 u8 syndrome[0x20];
5534
b4ff3a36 5535 u8 reserved_at_40[0x40];
e281682b
SM		 5536
5537 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5538
b4ff3a36 5539 u8 reserved_at_280[0x600];
e281682b
SM		 5540
5541 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5542
5543 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5544};
5545
5546struct mlx5_ifc_query_mkey_in_bits {
5547 u8 opcode[0x10];
b4ff3a36 5548 u8 reserved_at_10[0x10];
e281682b 5549
b4ff3a36 5550 u8 reserved_at_20[0x10];
e281682b
SM		 5551 u8 op_mod[0x10];
5552
b4ff3a36 5553 u8 reserved_at_40[0x8];
e281682b
SM		 5554 u8 mkey_index[0x18];
5555
5556 u8 pg_access[0x1];
b4ff3a36 5557 u8 reserved_at_61[0x1f];
e281682b
SM		 5558};
5559
5560struct mlx5_ifc_query_mad_demux_out_bits {
5561 u8 status[0x8];
b4ff3a36 5562 u8 reserved_at_8[0x18];
e281682b
SM		 5563
5564 u8 syndrome[0x20];
5565
b4ff3a36 5566 u8 reserved_at_40[0x40];
e281682b
SM		 5567
5568 u8 mad_dumux_parameters_block[0x20];
5569};
5570
5571struct mlx5_ifc_query_mad_demux_in_bits {
5572 u8 opcode[0x10];
b4ff3a36 5573 u8 reserved_at_10[0x10];
e281682b 5574
b4ff3a36 5575 u8 reserved_at_20[0x10];
e281682b
SM		 5576 u8 op_mod[0x10];
5577
b4ff3a36 5578 u8 reserved_at_40[0x40];
e281682b
SM		 5579};
5580
5581struct mlx5_ifc_query_l2_table_entry_out_bits {
5582 u8 status[0x8];
b4ff3a36 5583 u8 reserved_at_8[0x18];
e281682b
SM		 5584
5585 u8 syndrome[0x20];
5586
b4ff3a36 5587 u8 reserved_at_40[0xa0];
e281682b 5588
b4ff3a36 5589 u8 reserved_at_e0[0x13];
e281682b
SM		 5590 u8 vlan_valid[0x1];
5591 u8 vlan[0xc];
5592
5593 struct mlx5_ifc_mac_address_layout_bits mac_address;
5594
b4ff3a36 5595 u8 reserved_at_140[0xc0];
e281682b
SM		 5596};
5597
5598struct mlx5_ifc_query_l2_table_entry_in_bits {
5599 u8 opcode[0x10];
b4ff3a36 5600 u8 reserved_at_10[0x10];
e281682b 5601
b4ff3a36 5602 u8 reserved_at_20[0x10];
e281682b
SM		 5603 u8 op_mod[0x10];
5604
b4ff3a36 5605 u8 reserved_at_40[0x60];
e281682b 5606
b4ff3a36 5607 u8 reserved_at_a0[0x8];
e281682b
SM		 5608 u8 table_index[0x18];
5609
b4ff3a36 5610 u8 reserved_at_c0[0x140];
e281682b
SM		 5611};
5612
5613struct mlx5_ifc_query_issi_out_bits {
5614 u8 status[0x8];
b4ff3a36 5615 u8 reserved_at_8[0x18];
e281682b
SM		 5616
5617 u8 syndrome[0x20];
5618
b4ff3a36 5619 u8 reserved_at_40[0x10];
e281682b
SM		 5620 u8 current_issi[0x10];
5621
b4ff3a36 5622 u8 reserved_at_60[0xa0];
e281682b 5623
b4ff3a36 5624 u8 reserved_at_100[76][0x8];
e281682b
SM		 5625 u8 supported_issi_dw0[0x20];
5626};
5627
5628struct mlx5_ifc_query_issi_in_bits {
5629 u8 opcode[0x10];
b4ff3a36 5630 u8 reserved_at_10[0x10];
e281682b 5631
b4ff3a36 5632 u8 reserved_at_20[0x10];
e281682b
SM		 5633 u8 op_mod[0x10];
5634
b4ff3a36 5635 u8 reserved_at_40[0x40];
e281682b
SM		 5636};
5637
0dbc6fe0
SM		 5638struct mlx5_ifc_set_driver_version_out_bits {
5639 u8 status[0x8];
5640 u8 reserved_0[0x18];
5641
5642 u8 syndrome[0x20];
5643 u8 reserved_1[0x40];
5644};
5645
5646struct mlx5_ifc_set_driver_version_in_bits {
5647 u8 opcode[0x10];
5648 u8 reserved_0[0x10];
5649
5650 u8 reserved_1[0x10];
5651 u8 op_mod[0x10];
5652
5653 u8 reserved_2[0x40];
5654 u8 driver_version[64][0x8];
5655};
5656
e281682b
SM		 5657struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5658 u8 status[0x8];
b4ff3a36 5659 u8 reserved_at_8[0x18];
e281682b
SM		 5660
5661 u8 syndrome[0x20];
5662
b4ff3a36 5663 u8 reserved_at_40[0x40];
e281682b 5664
b6ca09cb 5665 struct mlx5_ifc_pkey_bits pkey[];
e281682b
SM		 5666};
5667
5668struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5669 u8 opcode[0x10];
b4ff3a36 5670 u8 reserved_at_10[0x10];
e281682b 5671
b4ff3a36 5672 u8 reserved_at_20[0x10];
e281682b
SM		 5673 u8 op_mod[0x10];
5674
5675 u8 other_vport[0x1];
b4ff3a36 5676 u8 reserved_at_41[0xb];
707c4602 5677 u8 port_num[0x4];
e281682b
SM		 5678 u8 vport_number[0x10];
5679
b4ff3a36 5680 u8 reserved_at_60[0x10];
e281682b
SM		 5681 u8 pkey_index[0x10];
5682};
5683
eff901d3
EC		 5684enum {
5685 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5686 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5687 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5688};
5689
e281682b
SM		 5690struct mlx5_ifc_query_hca_vport_gid_out_bits {
5691 u8 status[0x8];
b4ff3a36 5692 u8 reserved_at_8[0x18];
e281682b
SM		 5693
5694 u8 syndrome[0x20];
5695
b4ff3a36 5696 u8 reserved_at_40[0x20];
e281682b
SM		 5697
5698 u8 gids_num[0x10];
b4ff3a36 5699 u8 reserved_at_70[0x10];
e281682b 5700
b6ca09cb 5701 struct mlx5_ifc_array128_auto_bits gid[];
e281682b
SM		 5702};
5703
5704struct mlx5_ifc_query_hca_vport_gid_in_bits {
5705 u8 opcode[0x10];
b4ff3a36 5706 u8 reserved_at_10[0x10];
e281682b 5707
b4ff3a36 5708 u8 reserved_at_20[0x10];
e281682b
SM		 5709 u8 op_mod[0x10];
5710
5711 u8 other_vport[0x1];
b4ff3a36 5712 u8 reserved_at_41[0xb];
707c4602 5713 u8 port_num[0x4];
e281682b
SM		 5714 u8 vport_number[0x10];
5715
b4ff3a36 5716 u8 reserved_at_60[0x10];
e281682b
SM		 5717 u8 gid_index[0x10];
5718};
5719
5720struct mlx5_ifc_query_hca_vport_context_out_bits {
5721 u8 status[0x8];
b4ff3a36 5722 u8 reserved_at_8[0x18];
e281682b
SM		 5723
5724 u8 syndrome[0x20];
5725
b4ff3a36 5726 u8 reserved_at_40[0x40];
e281682b
SM		 5727
5728 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5729};
5730
5731struct mlx5_ifc_query_hca_vport_context_in_bits {
5732 u8 opcode[0x10];
b4ff3a36 5733 u8 reserved_at_10[0x10];
e281682b 5734
b4ff3a36 5735 u8 reserved_at_20[0x10];
e281682b
SM		 5736 u8 op_mod[0x10];
5737
5738 u8 other_vport[0x1];
b4ff3a36 5739 u8 reserved_at_41[0xb];
707c4602 5740 u8 port_num[0x4];
e281682b
SM		 5741 u8 vport_number[0x10];
5742
b4ff3a36 5743 u8 reserved_at_60[0x20];
e281682b
SM		 5744};
5745
5746struct mlx5_ifc_query_hca_cap_out_bits {
5747 u8 status[0x8];
b4ff3a36 5748 u8 reserved_at_8[0x18];
e281682b
SM		 5749
5750 u8 syndrome[0x20];
5751
b4ff3a36 5752 u8 reserved_at_40[0x40];
e281682b
SM		 5753
5754 union mlx5_ifc_hca_cap_union_bits capability;
5755};
5756
5757struct mlx5_ifc_query_hca_cap_in_bits {
5758 u8 opcode[0x10];
b4ff3a36 5759 u8 reserved_at_10[0x10];
e281682b 5760
b4ff3a36 5761 u8 reserved_at_20[0x10];
e281682b
SM		 5762 u8 op_mod[0x10];
5763
97b5484e
AV		 5764 u8 other_function[0x1];
5765 u8 reserved_at_41[0xf];
5766 u8 function_id[0x10];
5767
5768 u8 reserved_at_60[0x20];
e281682b
SM		 5769};
5770
97b5484e
AV		 5771struct mlx5_ifc_other_hca_cap_bits {
5772 u8 roce[0x1];
d32d7c52 5773 u8 reserved_at_1[0x27f];
97b5484e
AV		 5774};
5775
5776struct mlx5_ifc_query_other_hca_cap_out_bits {
e281682b 5777 u8 status[0x8];
d32d7c52 5778 u8 reserved_at_8[0x18];
e281682b
SM		 5779
5780 u8 syndrome[0x20];
5781
d32d7c52 5782 u8 reserved_at_40[0x40];
e281682b 5783
97b5484e
AV		 5784 struct mlx5_ifc_other_hca_cap_bits other_capability;
5785};
5786
5787struct mlx5_ifc_query_other_hca_cap_in_bits {
5788 u8 opcode[0x10];
d32d7c52 5789 u8 reserved_at_10[0x10];
97b5484e 5790
d32d7c52 5791 u8 reserved_at_20[0x10];
97b5484e
AV		 5792 u8 op_mod[0x10];
5793
d32d7c52 5794 u8 reserved_at_40[0x10];
97b5484e
AV		 5795 u8 function_id[0x10];
5796
d32d7c52 5797 u8 reserved_at_60[0x20];
97b5484e
AV		 5798};
5799
5800struct mlx5_ifc_modify_other_hca_cap_out_bits {
5801 u8 status[0x8];
d32d7c52 5802 u8 reserved_at_8[0x18];
97b5484e
AV		 5803
5804 u8 syndrome[0x20];
5805
d32d7c52 5806 u8 reserved_at_40[0x40];
97b5484e
AV		 5807};
5808
5809struct mlx5_ifc_modify_other_hca_cap_in_bits {
5810 u8 opcode[0x10];
d32d7c52 5811 u8 reserved_at_10[0x10];
97b5484e 5812
d32d7c52 5813 u8 reserved_at_20[0x10];
97b5484e
AV		 5814 u8 op_mod[0x10];
5815
d32d7c52 5816 u8 reserved_at_40[0x10];
97b5484e
AV		 5817 u8 function_id[0x10];
5818 u8 field_select[0x20];
5819
5820 struct mlx5_ifc_other_hca_cap_bits other_capability;
5821};
5822
5823struct mlx5_ifc_flow_table_context_bits {
5824 u8 reformat_en[0x1];
5825 u8 decap_en[0x1];
5826 u8 sw_owner[0x1];
5827 u8 termination_table[0x1];
5828 u8 table_miss_action[0x4];
e281682b 5829 u8 level[0x8];
97b5484e 5830 u8 reserved_at_10[0x8];
e281682b
SM		 5831 u8 log_size[0x8];
5832
97b5484e
AV		 5833 u8 reserved_at_20[0x8];
5834 u8 table_miss_id[0x18];
5835
5836 u8 reserved_at_40[0x8];
5837 u8 lag_master_next_table_id[0x18];
5838
5839 u8 reserved_at_60[0x60];
5840
5841 u8 sw_owner_icm_root_1[0x40];
5842
5843 u8 sw_owner_icm_root_0[0x40];
5844
5845};
5846
5847struct mlx5_ifc_query_flow_table_out_bits {
5848 u8 status[0x8];
5849 u8 reserved_at_8[0x18];
5850
5851 u8 syndrome[0x20];
5852
5853 u8 reserved_at_40[0x80];
5854
5855 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 5856};
5857
5858struct mlx5_ifc_query_flow_table_in_bits {
5859 u8 opcode[0x10];
b4ff3a36 5860 u8 reserved_at_10[0x10];
e281682b 5861
b4ff3a36 5862 u8 reserved_at_20[0x10];
e281682b
SM		 5863 u8 op_mod[0x10];
5864
b4ff3a36 5865 u8 reserved_at_40[0x40];
e281682b
SM		 5866
5867 u8 table_type[0x8];
b4ff3a36 5868 u8 reserved_at_88[0x18];
e281682b 5869
b4ff3a36 5870 u8 reserved_at_a0[0x8];
e281682b
SM		 5871 u8 table_id[0x18];
5872
b4ff3a36 5873 u8 reserved_at_c0[0x140];
e281682b
SM		 5874};
5875
5876struct mlx5_ifc_query_fte_out_bits {
5877 u8 status[0x8];
b4ff3a36 5878 u8 reserved_at_8[0x18];
e281682b
SM		 5879
5880 u8 syndrome[0x20];
5881
b4ff3a36 5882 u8 reserved_at_40[0x1c0];
e281682b
SM		 5883
5884 struct mlx5_ifc_flow_context_bits flow_context;
5885};
5886
5887struct mlx5_ifc_query_fte_in_bits {
5888 u8 opcode[0x10];
b4ff3a36 5889 u8 reserved_at_10[0x10];
e281682b 5890
b4ff3a36 5891 u8 reserved_at_20[0x10];
e281682b
SM		 5892 u8 op_mod[0x10];
5893
b4ff3a36 5894 u8 reserved_at_40[0x40];
e281682b
SM		 5895
5896 u8 table_type[0x8];
b4ff3a36 5897 u8 reserved_at_88[0x18];
e281682b 5898
b4ff3a36 5899 u8 reserved_at_a0[0x8];
e281682b
SM		 5900 u8 table_id[0x18];
5901
b4ff3a36 5902 u8 reserved_at_c0[0x40];
e281682b
SM		 5903
5904 u8 flow_index[0x20];
5905
b4ff3a36 5906 u8 reserved_at_120[0xe0];
e281682b
SM		 5907};
5908
e7e2519e
MG		 5909struct mlx5_ifc_match_definer_format_0_bits {
5910 u8 reserved_at_0[0x100];
5911
5912 u8 metadata_reg_c_0[0x20];
5913
5914 u8 metadata_reg_c_1[0x20];
5915
5916 u8 outer_dmac_47_16[0x20];
5917
5918 u8 outer_dmac_15_0[0x10];
5919 u8 outer_ethertype[0x10];
5920
5921 u8 reserved_at_180[0x1];
5922 u8 sx_sniffer[0x1];
5923 u8 functional_lb[0x1];
5924 u8 outer_ip_frag[0x1];
5925 u8 outer_qp_type[0x2];
5926 u8 outer_encap_type[0x2];
5927 u8 port_number[0x2];
5928 u8 outer_l3_type[0x2];
5929 u8 outer_l4_type[0x2];
5930 u8 outer_first_vlan_type[0x2];
5931 u8 outer_first_vlan_prio[0x3];
5932 u8 outer_first_vlan_cfi[0x1];
5933 u8 outer_first_vlan_vid[0xc];
5934
5935 u8 outer_l4_type_ext[0x4];
5936 u8 reserved_at_1a4[0x2];
5937 u8 outer_ipsec_layer[0x2];
5938 u8 outer_l2_type[0x2];
5939 u8 force_lb[0x1];
5940 u8 outer_l2_ok[0x1];
5941 u8 outer_l3_ok[0x1];
5942 u8 outer_l4_ok[0x1];
5943 u8 outer_second_vlan_type[0x2];
5944 u8 outer_second_vlan_prio[0x3];
5945 u8 outer_second_vlan_cfi[0x1];
5946 u8 outer_second_vlan_vid[0xc];
5947
5948 u8 outer_smac_47_16[0x20];
5949
5950 u8 outer_smac_15_0[0x10];
5951 u8 inner_ipv4_checksum_ok[0x1];
5952 u8 inner_l4_checksum_ok[0x1];
5953 u8 outer_ipv4_checksum_ok[0x1];
5954 u8 outer_l4_checksum_ok[0x1];
5955 u8 inner_l3_ok[0x1];
5956 u8 inner_l4_ok[0x1];
5957 u8 outer_l3_ok_duplicate[0x1];
5958 u8 outer_l4_ok_duplicate[0x1];
5959 u8 outer_tcp_cwr[0x1];
5960 u8 outer_tcp_ece[0x1];
5961 u8 outer_tcp_urg[0x1];
5962 u8 outer_tcp_ack[0x1];
5963 u8 outer_tcp_psh[0x1];
5964 u8 outer_tcp_rst[0x1];
5965 u8 outer_tcp_syn[0x1];
5966 u8 outer_tcp_fin[0x1];
5967};
5968
5969struct mlx5_ifc_match_definer_format_22_bits {
5970 u8 reserved_at_0[0x100];
5971
5972 u8 outer_ip_src_addr[0x20];
5973
5974 u8 outer_ip_dest_addr[0x20];
5975
5976 u8 outer_l4_sport[0x10];
5977 u8 outer_l4_dport[0x10];
5978
5979 u8 reserved_at_160[0x1];
5980 u8 sx_sniffer[0x1];
5981 u8 functional_lb[0x1];
5982 u8 outer_ip_frag[0x1];
5983 u8 outer_qp_type[0x2];
5984 u8 outer_encap_type[0x2];
5985 u8 port_number[0x2];
5986 u8 outer_l3_type[0x2];
5987 u8 outer_l4_type[0x2];
5988 u8 outer_first_vlan_type[0x2];
5989 u8 outer_first_vlan_prio[0x3];
5990 u8 outer_first_vlan_cfi[0x1];
5991 u8 outer_first_vlan_vid[0xc];
5992
5993 u8 metadata_reg_c_0[0x20];
5994
5995 u8 outer_dmac_47_16[0x20];
5996
5997 u8 outer_smac_47_16[0x20];
5998
5999 u8 outer_smac_15_0[0x10];
6000 u8 outer_dmac_15_0[0x10];
6001};
6002
6003struct mlx5_ifc_match_definer_format_23_bits {
6004 u8 reserved_at_0[0x100];
6005
6006 u8 inner_ip_src_addr[0x20];
6007
6008 u8 inner_ip_dest_addr[0x20];
6009
6010 u8 inner_l4_sport[0x10];
6011 u8 inner_l4_dport[0x10];
6012
6013 u8 reserved_at_160[0x1];
6014 u8 sx_sniffer[0x1];
6015 u8 functional_lb[0x1];
6016 u8 inner_ip_frag[0x1];
6017 u8 inner_qp_type[0x2];
6018 u8 inner_encap_type[0x2];
6019 u8 port_number[0x2];
6020 u8 inner_l3_type[0x2];
6021 u8 inner_l4_type[0x2];
6022 u8 inner_first_vlan_type[0x2];
6023 u8 inner_first_vlan_prio[0x3];
6024 u8 inner_first_vlan_cfi[0x1];
6025 u8 inner_first_vlan_vid[0xc];
6026
6027 u8 tunnel_header_0[0x20];
6028
6029 u8 inner_dmac_47_16[0x20];
6030
6031 u8 inner_smac_47_16[0x20];
6032
6033 u8 inner_smac_15_0[0x10];
6034 u8 inner_dmac_15_0[0x10];
6035};
6036
6037struct mlx5_ifc_match_definer_format_29_bits {
6038 u8 reserved_at_0[0xc0];
6039
6040 u8 outer_ip_dest_addr[0x80];
6041
6042 u8 outer_ip_src_addr[0x80];
6043
6044 u8 outer_l4_sport[0x10];
6045 u8 outer_l4_dport[0x10];
6046
6047 u8 reserved_at_1e0[0x20];
6048};
6049
6050struct mlx5_ifc_match_definer_format_30_bits {
6051 u8 reserved_at_0[0xa0];
6052
6053 u8 outer_ip_dest_addr[0x80];
6054
6055 u8 outer_ip_src_addr[0x80];
6056
6057 u8 outer_dmac_47_16[0x20];
6058
6059 u8 outer_smac_47_16[0x20];
6060
6061 u8 outer_smac_15_0[0x10];
6062 u8 outer_dmac_15_0[0x10];
6063};
6064
6065struct mlx5_ifc_match_definer_format_31_bits {
6066 u8 reserved_at_0[0xc0];
6067
6068 u8 inner_ip_dest_addr[0x80];
6069
6070 u8 inner_ip_src_addr[0x80];
6071
6072 u8 inner_l4_sport[0x10];
6073 u8 inner_l4_dport[0x10];
6074
6075 u8 reserved_at_1e0[0x20];
6076};
6077
6078struct mlx5_ifc_match_definer_format_32_bits {
6079 u8 reserved_at_0[0xa0];
6080
6081 u8 inner_ip_dest_addr[0x80];
6082
6083 u8 inner_ip_src_addr[0x80];
6084
6085 u8 inner_dmac_47_16[0x20];
6086
6087 u8 inner_smac_47_16[0x20];
6088
6089 u8 inner_smac_15_0[0x10];
6090 u8 inner_dmac_15_0[0x10];
6091};
6092
6093struct mlx5_ifc_match_definer_bits {
6094 u8 modify_field_select[0x40];
6095
6096 u8 reserved_at_40[0x40];
6097
6098 u8 reserved_at_80[0x10];
6099 u8 format_id[0x10];
6100
6101 u8 reserved_at_a0[0x160];
6102
6103 u8 match_mask[16][0x20];
6104};
6105
6106struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6107 u8 opcode[0x10];
6108 u8 uid[0x10];
6109
6110 u8 vhca_tunnel_id[0x10];
6111 u8 obj_type[0x10];
6112
6113 u8 obj_id[0x20];
6114
f5d23ee1
JL		 6115 u8 reserved_at_60[0x3];
6116 u8 log_obj_range[0x5];
6117 u8 reserved_at_68[0x18];
e7e2519e
MG		 6118};
6119
6120struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6121 u8 status[0x8];
6122 u8 reserved_at_8[0x18];
6123
6124 u8 syndrome[0x20];
6125
6126 u8 obj_id[0x20];
6127
6128 u8 reserved_at_60[0x20];
6129};
6130
6131struct mlx5_ifc_create_match_definer_in_bits {
6132 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6133
6134 struct mlx5_ifc_match_definer_bits obj_context;
6135};
6136
6137struct mlx5_ifc_create_match_definer_out_bits {
6138 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6139};
6140
e281682b
SM		 6141enum {
6142 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6143 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6144 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4c8b8518 6145 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
b169e64a 6146 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
7da3ad6c 6147 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
0f2a6c3b 6148 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
e281682b
SM		 6149};
6150
6151struct mlx5_ifc_query_flow_group_out_bits {
6152 u8 status[0x8];
b4ff3a36 6153 u8 reserved_at_8[0x18];
e281682b
SM		 6154
6155 u8 syndrome[0x20];
6156
b4ff3a36 6157 u8 reserved_at_40[0xa0];
e281682b
SM		 6158
6159 u8 start_flow_index[0x20];
6160
b4ff3a36 6161 u8 reserved_at_100[0x20];
e281682b
SM		 6162
6163 u8 end_flow_index[0x20];
6164
b4ff3a36 6165 u8 reserved_at_140[0xa0];
e281682b 6166
b4ff3a36 6167 u8 reserved_at_1e0[0x18];
e281682b
SM		 6168 u8 match_criteria_enable[0x8];
6169
6170 struct mlx5_ifc_fte_match_param_bits match_criteria;
6171
b4ff3a36 6172 u8 reserved_at_1200[0xe00];
e281682b
SM		 6173};
6174
6175struct mlx5_ifc_query_flow_group_in_bits {
6176 u8 opcode[0x10];
b4ff3a36 6177 u8 reserved_at_10[0x10];
e281682b 6178
b4ff3a36 6179 u8 reserved_at_20[0x10];
e281682b
SM		 6180 u8 op_mod[0x10];
6181
b4ff3a36 6182 u8 reserved_at_40[0x40];
e281682b
SM		 6183
6184 u8 table_type[0x8];
b4ff3a36 6185 u8 reserved_at_88[0x18];
e281682b 6186
b4ff3a36 6187 u8 reserved_at_a0[0x8];
e281682b
SM		 6188 u8 table_id[0x18];
6189
6190 u8 group_id[0x20];
6191
b4ff3a36 6192 u8 reserved_at_e0[0x120];
e281682b
SM		 6193};
6194
9dc0b289
AV		 6195struct mlx5_ifc_query_flow_counter_out_bits {
6196 u8 status[0x8];
6197 u8 reserved_at_8[0x18];
6198
6199 u8 syndrome[0x20];
6200
6201 u8 reserved_at_40[0x40];
6202
b6ca09cb 6203 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
9dc0b289
AV		 6204};
6205
6206struct mlx5_ifc_query_flow_counter_in_bits {
6207 u8 opcode[0x10];
6208 u8 reserved_at_10[0x10];
6209
6210 u8 reserved_at_20[0x10];
6211 u8 op_mod[0x10];
6212
6213 u8 reserved_at_40[0x80];
6214
6215 u8 clear[0x1];
6216 u8 reserved_at_c1[0xf];
6217 u8 num_of_counters[0x10];
6218
a8ffcc74 6219 u8 flow_counter_id[0x20];
9dc0b289
AV		 6220};
6221
d6666753
SM		 6222struct mlx5_ifc_query_esw_vport_context_out_bits {
6223 u8 status[0x8];
b4ff3a36 6224 u8 reserved_at_8[0x18];
d6666753
SM		 6225
6226 u8 syndrome[0x20];
6227
b4ff3a36 6228 u8 reserved_at_40[0x40];
d6666753
SM		 6229
6230 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6231};
6232
6233struct mlx5_ifc_query_esw_vport_context_in_bits {
6234 u8 opcode[0x10];
b4ff3a36 6235 u8 reserved_at_10[0x10];
d6666753 6236
b4ff3a36 6237 u8 reserved_at_20[0x10];
d6666753
SM		 6238 u8 op_mod[0x10];
6239
6240 u8 other_vport[0x1];
b4ff3a36 6241 u8 reserved_at_41[0xf];
d6666753
SM		 6242 u8 vport_number[0x10];
6243
b4ff3a36 6244 u8 reserved_at_60[0x20];
d6666753
SM		 6245};
6246
6247struct mlx5_ifc_modify_esw_vport_context_out_bits {
6248 u8 status[0x8];
b4ff3a36 6249 u8 reserved_at_8[0x18];
d6666753
SM		 6250
6251 u8 syndrome[0x20];
6252
b4ff3a36 6253 u8 reserved_at_40[0x40];
d6666753
SM		 6254};
6255
6256struct mlx5_ifc_esw_vport_context_fields_select_bits {
65c0f2c1
JL		 6257 u8 reserved_at_0[0x1b];
6258 u8 fdb_to_vport_reg_c_id[0x1];
d6666753
SM		 6259 u8 vport_cvlan_insert[0x1];
6260 u8 vport_svlan_insert[0x1];
6261 u8 vport_cvlan_strip[0x1];
6262 u8 vport_svlan_strip[0x1];
6263};
6264
6265struct mlx5_ifc_modify_esw_vport_context_in_bits {
6266 u8 opcode[0x10];
b4ff3a36 6267 u8 reserved_at_10[0x10];
d6666753 6268
b4ff3a36 6269 u8 reserved_at_20[0x10];
d6666753
SM		 6270 u8 op_mod[0x10];
6271
6272 u8 other_vport[0x1];
b4ff3a36 6273 u8 reserved_at_41[0xf];
d6666753
SM		 6274 u8 vport_number[0x10];
6275
6276 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6277
6278 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6279};
6280
e281682b
SM		 6281struct mlx5_ifc_query_eq_out_bits {
6282 u8 status[0x8];
b4ff3a36 6283 u8 reserved_at_8[0x18];
e281682b
SM		 6284
6285 u8 syndrome[0x20];
6286
b4ff3a36 6287 u8 reserved_at_40[0x40];
e281682b
SM		 6288
6289 struct mlx5_ifc_eqc_bits eq_context_entry;
6290
b4ff3a36 6291 u8 reserved_at_280[0x40];
e281682b
SM		 6292
6293 u8 event_bitmask[0x40];
6294
b4ff3a36 6295 u8 reserved_at_300[0x580];
e281682b 6296
b6ca09cb 6297 u8 pas[][0x40];
e281682b
SM		 6298};
6299
6300struct mlx5_ifc_query_eq_in_bits {
6301 u8 opcode[0x10];
b4ff3a36 6302 u8 reserved_at_10[0x10];
e281682b 6303
b4ff3a36 6304 u8 reserved_at_20[0x10];
e281682b
SM		 6305 u8 op_mod[0x10];
6306
b4ff3a36 6307 u8 reserved_at_40[0x18];
e281682b
SM		 6308 u8 eq_number[0x8];
6309
b4ff3a36 6310 u8 reserved_at_60[0x20];
e281682b
SM		 6311};
6312
60786f09 6313struct mlx5_ifc_packet_reformat_context_in_bits {
67133eaa
YK		 6314 u8 reformat_type[0x8];
6315 u8 reserved_at_8[0x4];
6316 u8 reformat_param_0[0x4];
6317 u8 reserved_at_10[0x6];
60786f09 6318 u8 reformat_data_size[0xa];
7adbde20 6319
67133eaa
YK		 6320 u8 reformat_param_1[0x8];
6321 u8 reserved_at_28[0x8];
60786f09 6322 u8 reformat_data[2][0x8];
7adbde20 6323
b6ca09cb 6324 u8 more_reformat_data[][0x8];
7adbde20
HHZ		 6325};
6326
60786f09 6327struct mlx5_ifc_query_packet_reformat_context_out_bits {
7adbde20
HHZ		 6328 u8 status[0x8];
6329 u8 reserved_at_8[0x18];
6330
6331 u8 syndrome[0x20];
6332
6333 u8 reserved_at_40[0xa0];
6334
b6ca09cb 6335 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7adbde20
HHZ		 6336};
6337
60786f09 6338struct mlx5_ifc_query_packet_reformat_context_in_bits {
7adbde20
HHZ		 6339 u8 opcode[0x10];
6340 u8 reserved_at_10[0x10];
6341
6342 u8 reserved_at_20[0x10];
6343 u8 op_mod[0x10];
6344
60786f09 6345 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6346
6347 u8 reserved_at_60[0xa0];
6348};
6349
60786f09 6350struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 6351 u8 status[0x8];
6352 u8 reserved_at_8[0x18];
6353
6354 u8 syndrome[0x20];
6355
60786f09 6356 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6357
6358 u8 reserved_at_60[0x20];
6359};
6360
67133eaa
YK		 6361enum {
6362 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6363 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6364 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6365};
6366
97b5484e 6367enum mlx5_reformat_ctx_type {
60786f09
MB		 6368 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6369 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
bea4e1f6
MB		 6370 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6371 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6372 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
67133eaa
YK		 6373 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6374 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
8385c51f
LN		 6375 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6376 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
e0e7a386
MB		 6377};
6378
60786f09 6379struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 6380 u8 opcode[0x10];
6381 u8 reserved_at_10[0x10];
6382
6383 u8 reserved_at_20[0x10];
6384 u8 op_mod[0x10];
6385
6386 u8 reserved_at_40[0xa0];
6387
60786f09 6388 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7adbde20
HHZ		 6389};
6390
60786f09 6391struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7adbde20
HHZ		 6392 u8 status[0x8];
6393 u8 reserved_at_8[0x18];
6394
6395 u8 syndrome[0x20];
6396
6397 u8 reserved_at_40[0x40];
6398};
6399
60786f09 6400struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7adbde20
HHZ		 6401 u8 opcode[0x10];
6402 u8 reserved_at_10[0x10];
6403
6404 u8 reserved_20[0x10];
6405 u8 op_mod[0x10];
6406
60786f09 6407 u8 packet_reformat_id[0x20];
7adbde20
HHZ		 6408
6409 u8 reserved_60[0x20];
6410};
6411
2a69cb9f
OG		 6412struct mlx5_ifc_set_action_in_bits {
6413 u8 action_type[0x4];
6414 u8 field[0xc];
6415 u8 reserved_at_10[0x3];
6416 u8 offset[0x5];
6417 u8 reserved_at_18[0x3];
6418 u8 length[0x5];
6419
6420 u8 data[0x20];
6421};
6422
6423struct mlx5_ifc_add_action_in_bits {
6424 u8 action_type[0x4];
6425 u8 field[0xc];
6426 u8 reserved_at_10[0x10];
6427
6428 u8 data[0x20];
6429};
6430
31d8bde1
HI		 6431struct mlx5_ifc_copy_action_in_bits {
6432 u8 action_type[0x4];
6433 u8 src_field[0xc];
6434 u8 reserved_at_10[0x3];
6435 u8 src_offset[0x5];
6436 u8 reserved_at_18[0x3];
6437 u8 length[0x5];
6438
6439 u8 reserved_at_20[0x4];
6440 u8 dst_field[0xc];
6441 u8 reserved_at_30[0x3];
6442 u8 dst_offset[0x5];
6443 u8 reserved_at_38[0x8];
6444};
6445
d65dbedf
HN		 6446union mlx5_ifc_set_add_copy_action_in_auto_bits {
6447 struct mlx5_ifc_set_action_in_bits set_action_in;
6448 struct mlx5_ifc_add_action_in_bits add_action_in;
822e114b 6449 struct mlx5_ifc_copy_action_in_bits copy_action_in;
2a69cb9f
OG		 6450 u8 reserved_at_0[0x40];
6451};
6452
6453enum {
6454 MLX5_ACTION_TYPE_SET = 0x1,
6455 MLX5_ACTION_TYPE_ADD = 0x2,
31d8bde1 6456 MLX5_ACTION_TYPE_COPY = 0x3,
2a69cb9f
OG		 6457};
6458
6459enum {
6460 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6461 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6462 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6463 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6464 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6465 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6466 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6467 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6468 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6469 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6470 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6471 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6472 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6473 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6474 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6475 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6476 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6477 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6478 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6479 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6480 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6481 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0eb69bb9 6482 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
0c0316f5 6483 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
97b5484e
AV		 6484 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6485 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
65c0f2c1 6486 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
97b5484e
AV		 6487 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6488 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6489 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6490 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6491 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
822e114b
PB		 6492 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6493 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
97b5484e
AV		 6494 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6495 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
78fb6122 6496 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
67133eaa
YK		 6497 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6498 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
2a69cb9f
OG		 6499};
6500
6501struct mlx5_ifc_alloc_modify_header_context_out_bits {
6502 u8 status[0x8];
6503 u8 reserved_at_8[0x18];
6504
6505 u8 syndrome[0x20];
6506
6507 u8 modify_header_id[0x20];
6508
6509 u8 reserved_at_60[0x20];
6510};
6511
6512struct mlx5_ifc_alloc_modify_header_context_in_bits {
6513 u8 opcode[0x10];
6514 u8 reserved_at_10[0x10];
6515
6516 u8 reserved_at_20[0x10];
6517 u8 op_mod[0x10];
6518
6519 u8 reserved_at_40[0x20];
6520
6521 u8 table_type[0x8];
6522 u8 reserved_at_68[0x10];
6523 u8 num_of_actions[0x8];
6524
29056207 6525 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
2a69cb9f
OG		 6526};
6527
6528struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6529 u8 status[0x8];
6530 u8 reserved_at_8[0x18];
6531
6532 u8 syndrome[0x20];
6533
6534 u8 reserved_at_40[0x40];
6535};
6536
6537struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6538 u8 opcode[0x10];
6539 u8 reserved_at_10[0x10];
6540
6541 u8 reserved_at_20[0x10];
6542 u8 op_mod[0x10];
6543
6544 u8 modify_header_id[0x20];
6545
6546 u8 reserved_at_60[0x20];
6547};
6548
ab0da5a5
YH		 6549struct mlx5_ifc_query_modify_header_context_in_bits {
6550 u8 opcode[0x10];
6551 u8 uid[0x10];
6552
6553 u8 reserved_at_20[0x10];
6554 u8 op_mod[0x10];
6555
6556 u8 modify_header_id[0x20];
6557
6558 u8 reserved_at_60[0xa0];
6559};
6560
e281682b
SM		 6561struct mlx5_ifc_query_dct_out_bits {
6562 u8 status[0x8];
b4ff3a36 6563 u8 reserved_at_8[0x18];
e281682b
SM		 6564
6565 u8 syndrome[0x20];
6566
b4ff3a36 6567 u8 reserved_at_40[0x40];
e281682b
SM		 6568
6569 struct mlx5_ifc_dctc_bits dct_context_entry;
6570
b4ff3a36 6571 u8 reserved_at_280[0x180];
e281682b
SM		 6572};
6573
6574struct mlx5_ifc_query_dct_in_bits {
6575 u8 opcode[0x10];
b4ff3a36 6576 u8 reserved_at_10[0x10];
e281682b 6577
b4ff3a36 6578 u8 reserved_at_20[0x10];
e281682b
SM		 6579 u8 op_mod[0x10];
6580
b4ff3a36 6581 u8 reserved_at_40[0x8];
e281682b
SM		 6582 u8 dctn[0x18];
6583
b4ff3a36 6584 u8 reserved_at_60[0x20];
e281682b
SM		 6585};
6586
6587struct mlx5_ifc_query_cq_out_bits {
6588 u8 status[0x8];
b4ff3a36 6589 u8 reserved_at_8[0x18];
e281682b
SM		 6590
6591 u8 syndrome[0x20];
6592
b4ff3a36 6593 u8 reserved_at_40[0x40];
e281682b
SM		 6594
6595 struct mlx5_ifc_cqc_bits cq_context;
6596
b4ff3a36 6597 u8 reserved_at_280[0x600];
e281682b 6598
b6ca09cb 6599 u8 pas[][0x40];
e281682b
SM		 6600};
6601
6602struct mlx5_ifc_query_cq_in_bits {
6603 u8 opcode[0x10];
b4ff3a36 6604 u8 reserved_at_10[0x10];
e281682b 6605
b4ff3a36 6606 u8 reserved_at_20[0x10];
e281682b
SM		 6607 u8 op_mod[0x10];
6608
b4ff3a36 6609 u8 reserved_at_40[0x8];
e281682b
SM		 6610 u8 cqn[0x18];
6611
b4ff3a36 6612 u8 reserved_at_60[0x20];
e281682b
SM		 6613};
6614
6615struct mlx5_ifc_query_cong_status_out_bits {
6616 u8 status[0x8];
b4ff3a36 6617 u8 reserved_at_8[0x18];
e281682b
SM		 6618
6619 u8 syndrome[0x20];
6620
b4ff3a36 6621 u8 reserved_at_40[0x20];
e281682b
SM		 6622
6623 u8 enable[0x1];
6624 u8 tag_enable[0x1];
b4ff3a36 6625 u8 reserved_at_62[0x1e];
e281682b
SM		 6626};
6627
6628struct mlx5_ifc_query_cong_status_in_bits {
6629 u8 opcode[0x10];
b4ff3a36 6630 u8 reserved_at_10[0x10];
e281682b 6631
b4ff3a36 6632 u8 reserved_at_20[0x10];
e281682b
SM		 6633 u8 op_mod[0x10];
6634
b4ff3a36 6635 u8 reserved_at_40[0x18];
e281682b
SM		 6636 u8 priority[0x4];
6637 u8 cong_protocol[0x4];
6638
b4ff3a36 6639 u8 reserved_at_60[0x20];
e281682b
SM		 6640};
6641
6642struct mlx5_ifc_query_cong_statistics_out_bits {
6643 u8 status[0x8];
b4ff3a36 6644 u8 reserved_at_8[0x18];
e281682b
SM		 6645
6646 u8 syndrome[0x20];
6647
b4ff3a36 6648 u8 reserved_at_40[0x40];
e281682b 6649
e1f24a79 6650 u8 rp_cur_flows[0x20];
e281682b
SM		 6651
6652 u8 sum_flows[0x20];
6653
e1f24a79 6654 u8 rp_cnp_ignored_high[0x20];
e281682b 6655
e1f24a79 6656 u8 rp_cnp_ignored_low[0x20];
e281682b 6657
e1f24a79 6658 u8 rp_cnp_handled_high[0x20];
e281682b 6659
e1f24a79 6660 u8 rp_cnp_handled_low[0x20];
e281682b 6661
b4ff3a36 6662 u8 reserved_at_140[0x100];
e281682b
SM		 6663
6664 u8 time_stamp_high[0x20];
6665
6666 u8 time_stamp_low[0x20];
6667
6668 u8 accumulators_period[0x20];
6669
e1f24a79 6670 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 6671
e1f24a79 6672 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 6673
e1f24a79 6674 u8 np_cnp_sent_high[0x20];
e281682b 6675
e1f24a79 6676 u8 np_cnp_sent_low[0x20];
e281682b 6677
b4ff3a36 6678 u8 reserved_at_320[0x560];
e281682b
SM		 6679};
6680
6681struct mlx5_ifc_query_cong_statistics_in_bits {
6682 u8 opcode[0x10];
b4ff3a36 6683 u8 reserved_at_10[0x10];
e281682b 6684
b4ff3a36 6685 u8 reserved_at_20[0x10];
e281682b
SM		 6686 u8 op_mod[0x10];
6687
6688 u8 clear[0x1];
b4ff3a36 6689 u8 reserved_at_41[0x1f];
e281682b 6690
b4ff3a36 6691 u8 reserved_at_60[0x20];
e281682b
SM		 6692};
6693
6694struct mlx5_ifc_query_cong_params_out_bits {
6695 u8 status[0x8];
b4ff3a36 6696 u8 reserved_at_8[0x18];
e281682b
SM		 6697
6698 u8 syndrome[0x20];
6699
b4ff3a36 6700 u8 reserved_at_40[0x40];
e281682b
SM		 6701
6702 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6703};
6704
6705struct mlx5_ifc_query_cong_params_in_bits {
6706 u8 opcode[0x10];
b4ff3a36 6707 u8 reserved_at_10[0x10];
e281682b 6708
b4ff3a36 6709 u8 reserved_at_20[0x10];
e281682b
SM		 6710 u8 op_mod[0x10];
6711
b4ff3a36 6712 u8 reserved_at_40[0x1c];
e281682b
SM		 6713 u8 cong_protocol[0x4];
6714
b4ff3a36 6715 u8 reserved_at_60[0x20];
e281682b
SM		 6716};
6717
6718struct mlx5_ifc_query_adapter_out_bits {
6719 u8 status[0x8];
b4ff3a36 6720 u8 reserved_at_8[0x18];
e281682b
SM		 6721
6722 u8 syndrome[0x20];
6723
b4ff3a36 6724 u8 reserved_at_40[0x40];
e281682b
SM		 6725
6726 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6727};
6728
6729struct mlx5_ifc_query_adapter_in_bits {
6730 u8 opcode[0x10];
b4ff3a36 6731 u8 reserved_at_10[0x10];
e281682b 6732
b4ff3a36 6733 u8 reserved_at_20[0x10];
e281682b
SM		 6734 u8 op_mod[0x10];
6735
b4ff3a36 6736 u8 reserved_at_40[0x40];
e281682b
SM		 6737};
6738
6739struct mlx5_ifc_qp_2rst_out_bits {
6740 u8 status[0x8];
b4ff3a36 6741 u8 reserved_at_8[0x18];
e281682b
SM		 6742
6743 u8 syndrome[0x20];
6744
b4ff3a36 6745 u8 reserved_at_40[0x40];
e281682b
SM		 6746};
6747
6748struct mlx5_ifc_qp_2rst_in_bits {
6749 u8 opcode[0x10];
4ac63ec7 6750 u8 uid[0x10];
e281682b 6751
b4ff3a36 6752 u8 reserved_at_20[0x10];
e281682b
SM		 6753 u8 op_mod[0x10];
6754
b4ff3a36 6755 u8 reserved_at_40[0x8];
e281682b
SM		 6756 u8 qpn[0x18];
6757
b4ff3a36 6758 u8 reserved_at_60[0x20];
e281682b
SM		 6759};
6760
6761struct mlx5_ifc_qp_2err_out_bits {
6762 u8 status[0x8];
b4ff3a36 6763 u8 reserved_at_8[0x18];
e281682b
SM		 6764
6765 u8 syndrome[0x20];
6766
b4ff3a36 6767 u8 reserved_at_40[0x40];
e281682b
SM		 6768};
6769
6770struct mlx5_ifc_qp_2err_in_bits {
6771 u8 opcode[0x10];
4ac63ec7 6772 u8 uid[0x10];
e281682b 6773
b4ff3a36 6774 u8 reserved_at_20[0x10];
e281682b
SM		 6775 u8 op_mod[0x10];
6776
b4ff3a36 6777 u8 reserved_at_40[0x8];
e281682b
SM		 6778 u8 qpn[0x18];
6779
b4ff3a36 6780 u8 reserved_at_60[0x20];
e281682b
SM		 6781};
6782
6783struct mlx5_ifc_page_fault_resume_out_bits {
6784 u8 status[0x8];
b4ff3a36 6785 u8 reserved_at_8[0x18];
e281682b
SM		 6786
6787 u8 syndrome[0x20];
6788
b4ff3a36 6789 u8 reserved_at_40[0x40];
e281682b
SM		 6790};
6791
6792struct mlx5_ifc_page_fault_resume_in_bits {
6793 u8 opcode[0x10];
b4ff3a36 6794 u8 reserved_at_10[0x10];
e281682b 6795
b4ff3a36 6796 u8 reserved_at_20[0x10];
e281682b
SM		 6797 u8 op_mod[0x10];
6798
6799 u8 error[0x1];
b4ff3a36 6800 u8 reserved_at_41[0x4];
223cdc72
AK		 6801 u8 page_fault_type[0x3];
6802 u8 wq_number[0x18];
e281682b 6803
223cdc72
AK		 6804 u8 reserved_at_60[0x8];
6805 u8 token[0x18];
e281682b
SM		 6806};
6807
6808struct mlx5_ifc_nop_out_bits {
6809 u8 status[0x8];
b4ff3a36 6810 u8 reserved_at_8[0x18];
e281682b
SM		 6811
6812 u8 syndrome[0x20];
6813
b4ff3a36 6814 u8 reserved_at_40[0x40];
e281682b
SM		 6815};
6816
6817struct mlx5_ifc_nop_in_bits {
6818 u8 opcode[0x10];
b4ff3a36 6819 u8 reserved_at_10[0x10];
e281682b 6820
b4ff3a36 6821 u8 reserved_at_20[0x10];
e281682b
SM		 6822 u8 op_mod[0x10];
6823
b4ff3a36 6824 u8 reserved_at_40[0x40];
e281682b
SM		 6825};
6826
6827struct mlx5_ifc_modify_vport_state_out_bits {
6828 u8 status[0x8];
b4ff3a36 6829 u8 reserved_at_8[0x18];
e281682b
SM		 6830
6831 u8 syndrome[0x20];
6832
b4ff3a36 6833 u8 reserved_at_40[0x40];
e281682b
SM		 6834};
6835
6836struct mlx5_ifc_modify_vport_state_in_bits {
6837 u8 opcode[0x10];
b4ff3a36 6838 u8 reserved_at_10[0x10];
e281682b 6839
b4ff3a36 6840 u8 reserved_at_20[0x10];
e281682b
SM		 6841 u8 op_mod[0x10];
6842
6843 u8 other_vport[0x1];
b4ff3a36 6844 u8 reserved_at_41[0xf];
e281682b
SM		 6845 u8 vport_number[0x10];
6846
b4ff3a36 6847 u8 reserved_at_60[0x18];
e281682b 6848 u8 admin_state[0x4];
b4ff3a36 6849 u8 reserved_at_7c[0x4];
e281682b
SM		 6850};
6851
6852struct mlx5_ifc_modify_tis_out_bits {
6853 u8 status[0x8];
b4ff3a36 6854 u8 reserved_at_8[0x18];
e281682b
SM		 6855
6856 u8 syndrome[0x20];
6857
b4ff3a36 6858 u8 reserved_at_40[0x40];
e281682b
SM		 6859};
6860
75850d0b 6861struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 6862 u8 reserved_at_0[0x20];
75850d0b 6863
84df61eb
AH		 6864 u8 reserved_at_20[0x1d];
6865 u8 lag_tx_port_affinity[0x1];
6866 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 6867 u8 prio[0x1];
6868};
6869
e281682b
SM		 6870struct mlx5_ifc_modify_tis_in_bits {
6871 u8 opcode[0x10];
bd371975 6872 u8 uid[0x10];
e281682b 6873
b4ff3a36 6874 u8 reserved_at_20[0x10];
e281682b
SM		 6875 u8 op_mod[0x10];
6876
b4ff3a36 6877 u8 reserved_at_40[0x8];
e281682b
SM		 6878 u8 tisn[0x18];
6879
b4ff3a36 6880 u8 reserved_at_60[0x20];
e281682b 6881
75850d0b 6882 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 6883
b4ff3a36 6884 u8 reserved_at_c0[0x40];
e281682b
SM		 6885
6886 struct mlx5_ifc_tisc_bits ctx;
6887};
6888
d9eea403 6889struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 6890 u8 reserved_at_0[0x20];
d9eea403 6891
b4ff3a36 6892 u8 reserved_at_20[0x1b];
66189961 6893 u8 self_lb_en[0x1];
bdfc028d
TT		 6894 u8 reserved_at_3c[0x1];
6895 u8 hash[0x1];
6896 u8 reserved_at_3e[0x1];
eaee12f0 6897 u8 packet_merge[0x1];
d9eea403
AS		 6898};
6899
e281682b
SM		 6900struct mlx5_ifc_modify_tir_out_bits {
6901 u8 status[0x8];
b4ff3a36 6902 u8 reserved_at_8[0x18];
e281682b
SM		 6903
6904 u8 syndrome[0x20];
6905
b4ff3a36 6906 u8 reserved_at_40[0x40];
e281682b
SM		 6907};
6908
6909struct mlx5_ifc_modify_tir_in_bits {
6910 u8 opcode[0x10];
bd371975 6911 u8 uid[0x10];
e281682b 6912
b4ff3a36 6913 u8 reserved_at_20[0x10];
e281682b
SM		 6914 u8 op_mod[0x10];
6915
b4ff3a36 6916 u8 reserved_at_40[0x8];
e281682b
SM		 6917 u8 tirn[0x18];
6918
b4ff3a36 6919 u8 reserved_at_60[0x20];
e281682b 6920
d9eea403 6921 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 6922
b4ff3a36 6923 u8 reserved_at_c0[0x40];
e281682b
SM		 6924
6925 struct mlx5_ifc_tirc_bits ctx;
6926};
6927
6928struct mlx5_ifc_modify_sq_out_bits {
6929 u8 status[0x8];
b4ff3a36 6930 u8 reserved_at_8[0x18];
e281682b
SM		 6931
6932 u8 syndrome[0x20];
6933
b4ff3a36 6934 u8 reserved_at_40[0x40];
e281682b
SM		 6935};
6936
6937struct mlx5_ifc_modify_sq_in_bits {
6938 u8 opcode[0x10];
430ae0d5 6939 u8 uid[0x10];
e281682b 6940
b4ff3a36 6941 u8 reserved_at_20[0x10];
e281682b
SM		 6942 u8 op_mod[0x10];
6943
6944 u8 sq_state[0x4];
b4ff3a36 6945 u8 reserved_at_44[0x4];
e281682b
SM		 6946 u8 sqn[0x18];
6947
b4ff3a36 6948 u8 reserved_at_60[0x20];
e281682b
SM		 6949
6950 u8 modify_bitmask[0x40];
6951
b4ff3a36 6952 u8 reserved_at_c0[0x40];
e281682b
SM		 6953
6954 struct mlx5_ifc_sqc_bits ctx;
6955};
6956
813f8540
MHY		 6957struct mlx5_ifc_modify_scheduling_element_out_bits {
6958 u8 status[0x8];
6959 u8 reserved_at_8[0x18];
6960
6961 u8 syndrome[0x20];
6962
6963 u8 reserved_at_40[0x1c0];
6964};
6965
6966enum {
6967 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6968 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6969};
6970
6971struct mlx5_ifc_modify_scheduling_element_in_bits {
6972 u8 opcode[0x10];
6973 u8 reserved_at_10[0x10];
6974
6975 u8 reserved_at_20[0x10];
6976 u8 op_mod[0x10];
6977
6978 u8 scheduling_hierarchy[0x8];
6979 u8 reserved_at_48[0x18];
6980
6981 u8 scheduling_element_id[0x20];
6982
6983 u8 reserved_at_80[0x20];
6984
6985 u8 modify_bitmask[0x20];
6986
6987 u8 reserved_at_c0[0x40];
6988
6989 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6990
6991 u8 reserved_at_300[0x100];
6992};
6993
e281682b
SM		 6994struct mlx5_ifc_modify_rqt_out_bits {
6995 u8 status[0x8];
b4ff3a36 6996 u8 reserved_at_8[0x18];
e281682b
SM		 6997
6998 u8 syndrome[0x20];
6999
b4ff3a36 7000 u8 reserved_at_40[0x40];
e281682b
SM		 7001};
7002
5c50368f 7003struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 7004 u8 reserved_at_0[0x20];
5c50368f 7005
b4ff3a36 7006 u8 reserved_at_20[0x1f];
5c50368f
AS		 7007 u8 rqn_list[0x1];
7008};
7009
e281682b
SM		 7010struct mlx5_ifc_modify_rqt_in_bits {
7011 u8 opcode[0x10];
bd371975 7012 u8 uid[0x10];
e281682b 7013
b4ff3a36 7014 u8 reserved_at_20[0x10];
e281682b
SM		 7015 u8 op_mod[0x10];
7016
b4ff3a36 7017 u8 reserved_at_40[0x8];
e281682b
SM		 7018 u8 rqtn[0x18];
7019
b4ff3a36 7020 u8 reserved_at_60[0x20];
e281682b 7021
5c50368f 7022 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 7023
b4ff3a36 7024 u8 reserved_at_c0[0x40];
e281682b
SM		 7025
7026 struct mlx5_ifc_rqtc_bits ctx;
7027};
7028
7029struct mlx5_ifc_modify_rq_out_bits {
7030 u8 status[0x8];
b4ff3a36 7031 u8 reserved_at_8[0x18];
e281682b
SM		 7032
7033 u8 syndrome[0x20];
7034
b4ff3a36 7035 u8 reserved_at_40[0x40];
e281682b
SM		 7036};
7037
83b502a1
AV		 7038enum {
7039 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 7040 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 7041 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 7042};
7043
e281682b
SM		 7044struct mlx5_ifc_modify_rq_in_bits {
7045 u8 opcode[0x10];
d269b3af 7046 u8 uid[0x10];
e281682b 7047
b4ff3a36 7048 u8 reserved_at_20[0x10];
e281682b
SM		 7049 u8 op_mod[0x10];
7050
7051 u8 rq_state[0x4];
b4ff3a36 7052 u8 reserved_at_44[0x4];
e281682b
SM		 7053 u8 rqn[0x18];
7054
b4ff3a36 7055 u8 reserved_at_60[0x20];
e281682b
SM		 7056
7057 u8 modify_bitmask[0x40];
7058
b4ff3a36 7059 u8 reserved_at_c0[0x40];
e281682b
SM		 7060
7061 struct mlx5_ifc_rqc_bits ctx;
7062};
7063
7064struct mlx5_ifc_modify_rmp_out_bits {
7065 u8 status[0x8];
b4ff3a36 7066 u8 reserved_at_8[0x18];
e281682b
SM		 7067
7068 u8 syndrome[0x20];
7069
b4ff3a36 7070 u8 reserved_at_40[0x40];
e281682b
SM		 7071};
7072
01949d01 7073struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 7074 u8 reserved_at_0[0x20];
01949d01 7075
b4ff3a36 7076 u8 reserved_at_20[0x1f];
01949d01
HA		 7077 u8 lwm[0x1];
7078};
7079
e281682b
SM		 7080struct mlx5_ifc_modify_rmp_in_bits {
7081 u8 opcode[0x10];
a0d8c054 7082 u8 uid[0x10];
e281682b 7083
b4ff3a36 7084 u8 reserved_at_20[0x10];
e281682b
SM		 7085 u8 op_mod[0x10];
7086
7087 u8 rmp_state[0x4];
b4ff3a36 7088 u8 reserved_at_44[0x4];
e281682b
SM		 7089 u8 rmpn[0x18];
7090
b4ff3a36 7091 u8 reserved_at_60[0x20];
e281682b 7092
01949d01 7093 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 7094
b4ff3a36 7095 u8 reserved_at_c0[0x40];
e281682b
SM		 7096
7097 struct mlx5_ifc_rmpc_bits ctx;
7098};
7099
7100struct mlx5_ifc_modify_nic_vport_context_out_bits {
7101 u8 status[0x8];
b4ff3a36 7102 u8 reserved_at_8[0x18];
e281682b
SM		 7103
7104 u8 syndrome[0x20];
7105
b4ff3a36 7106 u8 reserved_at_40[0x40];
e281682b
SM		 7107};
7108
7109struct mlx5_ifc_modify_nic_vport_field_select_bits {
32f69e4b
DJ		 7110 u8 reserved_at_0[0x12];
7111 u8 affiliation[0x1];
c74d90c1 7112 u8 reserved_at_13[0x1];
bded747b
HN		 7113 u8 disable_uc_local_lb[0x1];
7114 u8 disable_mc_local_lb[0x1];
23898c76
NO		 7115 u8 node_guid[0x1];
7116 u8 port_guid[0x1];
9def7121 7117 u8 min_inline[0x1];
d82b7318
SM		 7118 u8 mtu[0x1];
7119 u8 change_event[0x1];
7120 u8 promisc[0x1];
e281682b
SM		 7121 u8 permanent_address[0x1];
7122 u8 addresses_list[0x1];
7123 u8 roce_en[0x1];
b4ff3a36 7124 u8 reserved_at_1f[0x1];
e281682b
SM		 7125};
7126
7127struct mlx5_ifc_modify_nic_vport_context_in_bits {
7128 u8 opcode[0x10];
b4ff3a36 7129 u8 reserved_at_10[0x10];
e281682b 7130
b4ff3a36 7131 u8 reserved_at_20[0x10];
e281682b
SM		 7132 u8 op_mod[0x10];
7133
7134 u8 other_vport[0x1];
b4ff3a36 7135 u8 reserved_at_41[0xf];
e281682b
SM		 7136 u8 vport_number[0x10];
7137
7138 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7139
b4ff3a36 7140 u8 reserved_at_80[0x780];
e281682b
SM		 7141
7142 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7143};
7144
7145struct mlx5_ifc_modify_hca_vport_context_out_bits {
7146 u8 status[0x8];
b4ff3a36 7147 u8 reserved_at_8[0x18];
e281682b
SM		 7148
7149 u8 syndrome[0x20];
7150
b4ff3a36 7151 u8 reserved_at_40[0x40];
e281682b
SM		 7152};
7153
7154struct mlx5_ifc_modify_hca_vport_context_in_bits {
7155 u8 opcode[0x10];
b4ff3a36 7156 u8 reserved_at_10[0x10];
e281682b 7157
b4ff3a36 7158 u8 reserved_at_20[0x10];
e281682b
SM		 7159 u8 op_mod[0x10];
7160
7161 u8 other_vport[0x1];
b4ff3a36 7162 u8 reserved_at_41[0xb];
707c4602 7163 u8 port_num[0x4];
e281682b
SM		 7164 u8 vport_number[0x10];
7165
b4ff3a36 7166 u8 reserved_at_60[0x20];
e281682b
SM		 7167
7168 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7169};
7170
7171struct mlx5_ifc_modify_cq_out_bits {
7172 u8 status[0x8];
b4ff3a36 7173 u8 reserved_at_8[0x18];
e281682b
SM		 7174
7175 u8 syndrome[0x20];
7176
b4ff3a36 7177 u8 reserved_at_40[0x40];
e281682b
SM		 7178};
7179
7180enum {
7181 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7182 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7183};
7184
7185struct mlx5_ifc_modify_cq_in_bits {
7186 u8 opcode[0x10];
9ba481e2 7187 u8 uid[0x10];
e281682b 7188
b4ff3a36 7189 u8 reserved_at_20[0x10];
e281682b
SM		 7190 u8 op_mod[0x10];
7191
b4ff3a36 7192 u8 reserved_at_40[0x8];
e281682b
SM		 7193 u8 cqn[0x18];
7194
7195 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7196
7197 struct mlx5_ifc_cqc_bits cq_context;
7198
7a32f296 7199 u8 reserved_at_280[0x60];
bd371975
LR		 7200
7201 u8 cq_umem_valid[0x1];
7a32f296
ES		 7202 u8 reserved_at_2e1[0x1f];
7203
7204 u8 reserved_at_300[0x580];
e281682b 7205
b6ca09cb 7206 u8 pas[][0x40];
e281682b
SM		 7207};
7208
7209struct mlx5_ifc_modify_cong_status_out_bits {
7210 u8 status[0x8];
b4ff3a36 7211 u8 reserved_at_8[0x18];
e281682b
SM		 7212
7213 u8 syndrome[0x20];
7214
b4ff3a36 7215 u8 reserved_at_40[0x40];
e281682b
SM		 7216};
7217
7218struct mlx5_ifc_modify_cong_status_in_bits {
7219 u8 opcode[0x10];
b4ff3a36 7220 u8 reserved_at_10[0x10];
e281682b 7221
b4ff3a36 7222 u8 reserved_at_20[0x10];
e281682b
SM		 7223 u8 op_mod[0x10];
7224
b4ff3a36 7225 u8 reserved_at_40[0x18];
e281682b
SM		 7226 u8 priority[0x4];
7227 u8 cong_protocol[0x4];
7228
7229 u8 enable[0x1];
7230 u8 tag_enable[0x1];
b4ff3a36 7231 u8 reserved_at_62[0x1e];
e281682b
SM		 7232};
7233
7234struct mlx5_ifc_modify_cong_params_out_bits {
7235 u8 status[0x8];
b4ff3a36 7236 u8 reserved_at_8[0x18];
e281682b
SM		 7237
7238 u8 syndrome[0x20];
7239
b4ff3a36 7240 u8 reserved_at_40[0x40];
e281682b
SM		 7241};
7242
7243struct mlx5_ifc_modify_cong_params_in_bits {
7244 u8 opcode[0x10];
b4ff3a36 7245 u8 reserved_at_10[0x10];
e281682b 7246
b4ff3a36 7247 u8 reserved_at_20[0x10];
e281682b
SM		 7248 u8 op_mod[0x10];
7249
b4ff3a36 7250 u8 reserved_at_40[0x1c];
e281682b
SM		 7251 u8 cong_protocol[0x4];
7252
7253 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7254
b4ff3a36 7255 u8 reserved_at_80[0x80];
e281682b
SM		 7256
7257 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7258};
7259
7260struct mlx5_ifc_manage_pages_out_bits {
7261 u8 status[0x8];
b4ff3a36 7262 u8 reserved_at_8[0x18];
e281682b
SM		 7263
7264 u8 syndrome[0x20];
7265
7266 u8 output_num_entries[0x20];
7267
b4ff3a36 7268 u8 reserved_at_60[0x20];
e281682b 7269
b6ca09cb 7270 u8 pas[][0x40];
e281682b
SM		 7271};
7272
7273enum {
7274 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7275 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7276 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7277};
7278
7279struct mlx5_ifc_manage_pages_in_bits {
7280 u8 opcode[0x10];
b4ff3a36 7281 u8 reserved_at_10[0x10];
e281682b 7282
b4ff3a36 7283 u8 reserved_at_20[0x10];
e281682b
SM		 7284 u8 op_mod[0x10];
7285
591905ba
BW		 7286 u8 embedded_cpu_function[0x1];
7287 u8 reserved_at_41[0xf];
e281682b
SM		 7288 u8 function_id[0x10];
7289
7290 u8 input_num_entries[0x20];
7291
b6ca09cb 7292 u8 pas[][0x40];
e281682b
SM		 7293};
7294
7295struct mlx5_ifc_mad_ifc_out_bits {
7296 u8 status[0x8];
b4ff3a36 7297 u8 reserved_at_8[0x18];
e281682b
SM		 7298
7299 u8 syndrome[0x20];
7300
b4ff3a36 7301 u8 reserved_at_40[0x40];
e281682b
SM		 7302
7303 u8 response_mad_packet[256][0x8];
7304};
7305
7306struct mlx5_ifc_mad_ifc_in_bits {
7307 u8 opcode[0x10];
b4ff3a36 7308 u8 reserved_at_10[0x10];
e281682b 7309
b4ff3a36 7310 u8 reserved_at_20[0x10];
e281682b
SM		 7311 u8 op_mod[0x10];
7312
7313 u8 remote_lid[0x10];
b4ff3a36 7314 u8 reserved_at_50[0x8];
e281682b
SM		 7315 u8 port[0x8];
7316
b4ff3a36 7317 u8 reserved_at_60[0x20];
e281682b
SM		 7318
7319 u8 mad[256][0x8];
7320};
7321
7322struct mlx5_ifc_init_hca_out_bits {
7323 u8 status[0x8];
b4ff3a36 7324 u8 reserved_at_8[0x18];
e281682b
SM		 7325
7326 u8 syndrome[0x20];
7327
b4ff3a36 7328 u8 reserved_at_40[0x40];
e281682b
SM		 7329};
7330
7331struct mlx5_ifc_init_hca_in_bits {
7332 u8 opcode[0x10];
b4ff3a36 7333 u8 reserved_at_10[0x10];
e281682b 7334
b4ff3a36 7335 u8 reserved_at_20[0x10];
e281682b
SM		 7336 u8 op_mod[0x10];
7337
0372c546
YH		 7338 u8 reserved_at_40[0x20];
7339
7340 u8 reserved_at_60[0x2];
7341 u8 sw_vhca_id[0xe];
7342 u8 reserved_at_70[0x10];
7343
8737f818 7344 u8 sw_owner_id[4][0x20];
e281682b
SM		 7345};
7346
7347struct mlx5_ifc_init2rtr_qp_out_bits {
7348 u8 status[0x8];
b4ff3a36 7349 u8 reserved_at_8[0x18];
e281682b
SM		 7350
7351 u8 syndrome[0x20];
7352
6b646a7e
LR		 7353 u8 reserved_at_40[0x20];
7354 u8 ece[0x20];
e281682b
SM		 7355};
7356
7357struct mlx5_ifc_init2rtr_qp_in_bits {
7358 u8 opcode[0x10];
4ac63ec7 7359 u8 uid[0x10];
e281682b 7360
b4ff3a36 7361 u8 reserved_at_20[0x10];
e281682b
SM		 7362 u8 op_mod[0x10];
7363
b4ff3a36 7364 u8 reserved_at_40[0x8];
e281682b
SM		 7365 u8 qpn[0x18];
7366
b4ff3a36 7367 u8 reserved_at_60[0x20];
e281682b
SM		 7368
7369 u8 opt_param_mask[0x20];
7370
6b646a7e 7371 u8 ece[0x20];
e281682b
SM		 7372
7373 struct mlx5_ifc_qpc_bits qpc;
7374
b4ff3a36 7375 u8 reserved_at_800[0x80];
e281682b
SM		 7376};
7377
7378struct mlx5_ifc_init2init_qp_out_bits {
7379 u8 status[0x8];
b4ff3a36 7380 u8 reserved_at_8[0x18];
e281682b
SM		 7381
7382 u8 syndrome[0x20];
7383
ab183d46
LR		 7384 u8 reserved_at_40[0x20];
7385 u8 ece[0x20];
e281682b
SM		 7386};
7387
7388struct mlx5_ifc_init2init_qp_in_bits {
7389 u8 opcode[0x10];
4ac63ec7 7390 u8 uid[0x10];
e281682b 7391
b4ff3a36 7392 u8 reserved_at_20[0x10];
e281682b
SM		 7393 u8 op_mod[0x10];
7394
b4ff3a36 7395 u8 reserved_at_40[0x8];
e281682b
SM		 7396 u8 qpn[0x18];
7397
b4ff3a36 7398 u8 reserved_at_60[0x20];
e281682b
SM		 7399
7400 u8 opt_param_mask[0x20];
7401
ab183d46 7402 u8 ece[0x20];
e281682b
SM		 7403
7404 struct mlx5_ifc_qpc_bits qpc;
7405
b4ff3a36 7406 u8 reserved_at_800[0x80];
e281682b
SM		 7407};
7408
7409struct mlx5_ifc_get_dropped_packet_log_out_bits {
7410 u8 status[0x8];
b4ff3a36 7411 u8 reserved_at_8[0x18];
e281682b
SM		 7412
7413 u8 syndrome[0x20];
7414
b4ff3a36 7415 u8 reserved_at_40[0x40];
e281682b
SM		 7416
7417 u8 packet_headers_log[128][0x8];
7418
7419 u8 packet_syndrome[64][0x8];
7420};
7421
7422struct mlx5_ifc_get_dropped_packet_log_in_bits {
7423 u8 opcode[0x10];
b4ff3a36 7424 u8 reserved_at_10[0x10];
e281682b 7425
b4ff3a36 7426 u8 reserved_at_20[0x10];
e281682b
SM		 7427 u8 op_mod[0x10];
7428
b4ff3a36 7429 u8 reserved_at_40[0x40];
e281682b
SM		 7430};
7431
7432struct mlx5_ifc_gen_eqe_in_bits {
7433 u8 opcode[0x10];
b4ff3a36 7434 u8 reserved_at_10[0x10];
e281682b 7435
b4ff3a36 7436 u8 reserved_at_20[0x10];
e281682b
SM		 7437 u8 op_mod[0x10];
7438
b4ff3a36 7439 u8 reserved_at_40[0x18];
e281682b
SM		 7440 u8 eq_number[0x8];
7441
b4ff3a36 7442 u8 reserved_at_60[0x20];
e281682b
SM		 7443
7444 u8 eqe[64][0x8];
7445};
7446
7447struct mlx5_ifc_gen_eq_out_bits {
7448 u8 status[0x8];
b4ff3a36 7449 u8 reserved_at_8[0x18];
e281682b
SM		 7450
7451 u8 syndrome[0x20];
7452
b4ff3a36 7453 u8 reserved_at_40[0x40];
e281682b
SM		 7454};
7455
7456struct mlx5_ifc_enable_hca_out_bits {
7457 u8 status[0x8];
b4ff3a36 7458 u8 reserved_at_8[0x18];
e281682b
SM		 7459
7460 u8 syndrome[0x20];
7461
b4ff3a36 7462 u8 reserved_at_40[0x20];
e281682b
SM		 7463};
7464
7465struct mlx5_ifc_enable_hca_in_bits {
7466 u8 opcode[0x10];
b4ff3a36 7467 u8 reserved_at_10[0x10];
e281682b 7468
b4ff3a36 7469 u8 reserved_at_20[0x10];
e281682b
SM		 7470 u8 op_mod[0x10];
7471
22e939a9
BW		 7472 u8 embedded_cpu_function[0x1];
7473 u8 reserved_at_41[0xf];
e281682b
SM		 7474 u8 function_id[0x10];
7475
b4ff3a36 7476 u8 reserved_at_60[0x20];
e281682b
SM		 7477};
7478
7479struct mlx5_ifc_drain_dct_out_bits {
7480 u8 status[0x8];
b4ff3a36 7481 u8 reserved_at_8[0x18];
e281682b
SM		 7482
7483 u8 syndrome[0x20];
7484
b4ff3a36 7485 u8 reserved_at_40[0x40];
e281682b
SM		 7486};
7487
7488struct mlx5_ifc_drain_dct_in_bits {
7489 u8 opcode[0x10];
774ea6ee 7490 u8 uid[0x10];
e281682b 7491
b4ff3a36 7492 u8 reserved_at_20[0x10];
e281682b
SM		 7493 u8 op_mod[0x10];
7494
b4ff3a36 7495 u8 reserved_at_40[0x8];
e281682b
SM		 7496 u8 dctn[0x18];
7497
b4ff3a36 7498 u8 reserved_at_60[0x20];
e281682b
SM		 7499};
7500
7501struct mlx5_ifc_disable_hca_out_bits {
7502 u8 status[0x8];
b4ff3a36 7503 u8 reserved_at_8[0x18];
e281682b
SM		 7504
7505 u8 syndrome[0x20];
7506
b4ff3a36 7507 u8 reserved_at_40[0x20];
e281682b
SM		 7508};
7509
7510struct mlx5_ifc_disable_hca_in_bits {
7511 u8 opcode[0x10];
b4ff3a36 7512 u8 reserved_at_10[0x10];
e281682b 7513
b4ff3a36 7514 u8 reserved_at_20[0x10];
e281682b
SM		 7515 u8 op_mod[0x10];
7516
22e939a9
BW		 7517 u8 embedded_cpu_function[0x1];
7518 u8 reserved_at_41[0xf];
e281682b
SM		 7519 u8 function_id[0x10];
7520
b4ff3a36 7521 u8 reserved_at_60[0x20];
e281682b
SM		 7522};
7523
7524struct mlx5_ifc_detach_from_mcg_out_bits {
7525 u8 status[0x8];
b4ff3a36 7526 u8 reserved_at_8[0x18];
e281682b
SM		 7527
7528 u8 syndrome[0x20];
7529
b4ff3a36 7530 u8 reserved_at_40[0x40];
e281682b
SM		 7531};
7532
7533struct mlx5_ifc_detach_from_mcg_in_bits {
7534 u8 opcode[0x10];
bd371975 7535 u8 uid[0x10];
e281682b 7536
b4ff3a36 7537 u8 reserved_at_20[0x10];
e281682b
SM		 7538 u8 op_mod[0x10];
7539
b4ff3a36 7540 u8 reserved_at_40[0x8];
e281682b
SM		 7541 u8 qpn[0x18];
7542
b4ff3a36 7543 u8 reserved_at_60[0x20];
e281682b
SM		 7544
7545 u8 multicast_gid[16][0x8];
7546};
7547
7486216b
SM		 7548struct mlx5_ifc_destroy_xrq_out_bits {
7549 u8 status[0x8];
7550 u8 reserved_at_8[0x18];
7551
7552 u8 syndrome[0x20];
7553
7554 u8 reserved_at_40[0x40];
7555};
7556
7557struct mlx5_ifc_destroy_xrq_in_bits {
7558 u8 opcode[0x10];
a0d8c054 7559 u8 uid[0x10];
7486216b
SM		 7560
7561 u8 reserved_at_20[0x10];
7562 u8 op_mod[0x10];
7563
7564 u8 reserved_at_40[0x8];
7565 u8 xrqn[0x18];
7566
7567 u8 reserved_at_60[0x20];
7568};
7569
e281682b
SM		 7570struct mlx5_ifc_destroy_xrc_srq_out_bits {
7571 u8 status[0x8];
b4ff3a36 7572 u8 reserved_at_8[0x18];
e281682b
SM		 7573
7574 u8 syndrome[0x20];
7575
b4ff3a36 7576 u8 reserved_at_40[0x40];
e281682b
SM		 7577};
7578
7579struct mlx5_ifc_destroy_xrc_srq_in_bits {
7580 u8 opcode[0x10];
a0d8c054 7581 u8 uid[0x10];
e281682b 7582
b4ff3a36 7583 u8 reserved_at_20[0x10];
e281682b
SM		 7584 u8 op_mod[0x10];
7585
b4ff3a36 7586 u8 reserved_at_40[0x8];
e281682b
SM		 7587 u8 xrc_srqn[0x18];
7588
b4ff3a36 7589 u8 reserved_at_60[0x20];
e281682b
SM		 7590};
7591
7592struct mlx5_ifc_destroy_tis_out_bits {
7593 u8 status[0x8];
b4ff3a36 7594 u8 reserved_at_8[0x18];
e281682b
SM		 7595
7596 u8 syndrome[0x20];
7597
b4ff3a36 7598 u8 reserved_at_40[0x40];
e281682b
SM		 7599};
7600
7601struct mlx5_ifc_destroy_tis_in_bits {
7602 u8 opcode[0x10];
bd371975 7603 u8 uid[0x10];
e281682b 7604
b4ff3a36 7605 u8 reserved_at_20[0x10];
e281682b
SM		 7606 u8 op_mod[0x10];
7607
b4ff3a36 7608 u8 reserved_at_40[0x8];
e281682b
SM		 7609 u8 tisn[0x18];
7610
b4ff3a36 7611 u8 reserved_at_60[0x20];
e281682b
SM		 7612};
7613
7614struct mlx5_ifc_destroy_tir_out_bits {
7615 u8 status[0x8];
b4ff3a36 7616 u8 reserved_at_8[0x18];
e281682b
SM		 7617
7618 u8 syndrome[0x20];
7619
b4ff3a36 7620 u8 reserved_at_40[0x40];
e281682b
SM		 7621};
7622
7623struct mlx5_ifc_destroy_tir_in_bits {
7624 u8 opcode[0x10];
bd371975 7625 u8 uid[0x10];
e281682b 7626
b4ff3a36 7627 u8 reserved_at_20[0x10];
e281682b
SM		 7628 u8 op_mod[0x10];
7629
b4ff3a36 7630 u8 reserved_at_40[0x8];
e281682b
SM		 7631 u8 tirn[0x18];
7632
b4ff3a36 7633 u8 reserved_at_60[0x20];
e281682b
SM		 7634};
7635
7636struct mlx5_ifc_destroy_srq_out_bits {
7637 u8 status[0x8];
b4ff3a36 7638 u8 reserved_at_8[0x18];
e281682b
SM		 7639
7640 u8 syndrome[0x20];
7641
b4ff3a36 7642 u8 reserved_at_40[0x40];
e281682b
SM		 7643};
7644
7645struct mlx5_ifc_destroy_srq_in_bits {
7646 u8 opcode[0x10];
a0d8c054 7647 u8 uid[0x10];
e281682b 7648
b4ff3a36 7649 u8 reserved_at_20[0x10];
e281682b
SM		 7650 u8 op_mod[0x10];
7651
b4ff3a36 7652 u8 reserved_at_40[0x8];
e281682b
SM		 7653 u8 srqn[0x18];
7654
b4ff3a36 7655 u8 reserved_at_60[0x20];
e281682b
SM		 7656};
7657
7658struct mlx5_ifc_destroy_sq_out_bits {
7659 u8 status[0x8];
b4ff3a36 7660 u8 reserved_at_8[0x18];
e281682b
SM		 7661
7662 u8 syndrome[0x20];
7663
b4ff3a36 7664 u8 reserved_at_40[0x40];
e281682b
SM		 7665};
7666
7667struct mlx5_ifc_destroy_sq_in_bits {
7668 u8 opcode[0x10];
430ae0d5 7669 u8 uid[0x10];
e281682b 7670
b4ff3a36 7671 u8 reserved_at_20[0x10];
e281682b
SM		 7672 u8 op_mod[0x10];
7673
b4ff3a36 7674 u8 reserved_at_40[0x8];
e281682b
SM		 7675 u8 sqn[0x18];
7676
b4ff3a36 7677 u8 reserved_at_60[0x20];
e281682b
SM		 7678};
7679
813f8540
MHY		 7680struct mlx5_ifc_destroy_scheduling_element_out_bits {
7681 u8 status[0x8];
7682 u8 reserved_at_8[0x18];
7683
7684 u8 syndrome[0x20];
7685
7686 u8 reserved_at_40[0x1c0];
7687};
7688
7689struct mlx5_ifc_destroy_scheduling_element_in_bits {
7690 u8 opcode[0x10];
7691 u8 reserved_at_10[0x10];
7692
7693 u8 reserved_at_20[0x10];
7694 u8 op_mod[0x10];
7695
7696 u8 scheduling_hierarchy[0x8];
7697 u8 reserved_at_48[0x18];
7698
7699 u8 scheduling_element_id[0x20];
7700
7701 u8 reserved_at_80[0x180];
7702};
7703
e281682b
SM		 7704struct mlx5_ifc_destroy_rqt_out_bits {
7705 u8 status[0x8];
b4ff3a36 7706 u8 reserved_at_8[0x18];
e281682b
SM		 7707
7708 u8 syndrome[0x20];
7709
b4ff3a36 7710 u8 reserved_at_40[0x40];
e281682b
SM		 7711};
7712
7713struct mlx5_ifc_destroy_rqt_in_bits {
7714 u8 opcode[0x10];
bd371975 7715 u8 uid[0x10];
e281682b 7716
b4ff3a36 7717 u8 reserved_at_20[0x10];
e281682b
SM		 7718 u8 op_mod[0x10];
7719
b4ff3a36 7720 u8 reserved_at_40[0x8];
e281682b
SM		 7721 u8 rqtn[0x18];
7722
b4ff3a36 7723 u8 reserved_at_60[0x20];
e281682b
SM		 7724};
7725
7726struct mlx5_ifc_destroy_rq_out_bits {
7727 u8 status[0x8];
b4ff3a36 7728 u8 reserved_at_8[0x18];
e281682b
SM		 7729
7730 u8 syndrome[0x20];
7731
b4ff3a36 7732 u8 reserved_at_40[0x40];
e281682b
SM		 7733};
7734
7735struct mlx5_ifc_destroy_rq_in_bits {
7736 u8 opcode[0x10];
d269b3af 7737 u8 uid[0x10];
e281682b 7738
b4ff3a36 7739 u8 reserved_at_20[0x10];
e281682b
SM		 7740 u8 op_mod[0x10];
7741
b4ff3a36 7742 u8 reserved_at_40[0x8];
e281682b
SM		 7743 u8 rqn[0x18];
7744
b4ff3a36 7745 u8 reserved_at_60[0x20];
e281682b
SM		 7746};
7747
c1e0bfc1
MG		 7748struct mlx5_ifc_set_delay_drop_params_in_bits {
7749 u8 opcode[0x10];
7750 u8 reserved_at_10[0x10];
7751
7752 u8 reserved_at_20[0x10];
7753 u8 op_mod[0x10];
7754
7755 u8 reserved_at_40[0x20];
7756
7757 u8 reserved_at_60[0x10];
7758 u8 delay_drop_timeout[0x10];
7759};
7760
7761struct mlx5_ifc_set_delay_drop_params_out_bits {
7762 u8 status[0x8];
7763 u8 reserved_at_8[0x18];
7764
7765 u8 syndrome[0x20];
7766
7767 u8 reserved_at_40[0x40];
7768};
7769
e281682b
SM		 7770struct mlx5_ifc_destroy_rmp_out_bits {
7771 u8 status[0x8];
b4ff3a36 7772 u8 reserved_at_8[0x18];
e281682b
SM		 7773
7774 u8 syndrome[0x20];
7775
b4ff3a36 7776 u8 reserved_at_40[0x40];
e281682b
SM		 7777};
7778
7779struct mlx5_ifc_destroy_rmp_in_bits {
7780 u8 opcode[0x10];
a0d8c054 7781 u8 uid[0x10];
e281682b 7782
b4ff3a36 7783 u8 reserved_at_20[0x10];
e281682b
SM		 7784 u8 op_mod[0x10];
7785
b4ff3a36 7786 u8 reserved_at_40[0x8];
e281682b
SM		 7787 u8 rmpn[0x18];
7788
b4ff3a36 7789 u8 reserved_at_60[0x20];
e281682b
SM		 7790};
7791
7792struct mlx5_ifc_destroy_qp_out_bits {
7793 u8 status[0x8];
b4ff3a36 7794 u8 reserved_at_8[0x18];
e281682b
SM		 7795
7796 u8 syndrome[0x20];
7797
b4ff3a36 7798 u8 reserved_at_40[0x40];
e281682b
SM		 7799};
7800
7801struct mlx5_ifc_destroy_qp_in_bits {
7802 u8 opcode[0x10];
4ac63ec7 7803 u8 uid[0x10];
e281682b 7804
b4ff3a36 7805 u8 reserved_at_20[0x10];
e281682b
SM		 7806 u8 op_mod[0x10];
7807
b4ff3a36 7808 u8 reserved_at_40[0x8];
e281682b
SM		 7809 u8 qpn[0x18];
7810
b4ff3a36 7811 u8 reserved_at_60[0x20];
e281682b
SM		 7812};
7813
7814struct mlx5_ifc_destroy_psv_out_bits {
7815 u8 status[0x8];
b4ff3a36 7816 u8 reserved_at_8[0x18];
e281682b
SM		 7817
7818 u8 syndrome[0x20];
7819
b4ff3a36 7820 u8 reserved_at_40[0x40];
e281682b
SM		 7821};
7822
7823struct mlx5_ifc_destroy_psv_in_bits {
7824 u8 opcode[0x10];
b4ff3a36 7825 u8 reserved_at_10[0x10];
e281682b 7826
b4ff3a36 7827 u8 reserved_at_20[0x10];
e281682b
SM		 7828 u8 op_mod[0x10];
7829
b4ff3a36 7830 u8 reserved_at_40[0x8];
e281682b
SM		 7831 u8 psvn[0x18];
7832
b4ff3a36 7833 u8 reserved_at_60[0x20];
e281682b
SM		 7834};
7835
7836struct mlx5_ifc_destroy_mkey_out_bits {
7837 u8 status[0x8];
b4ff3a36 7838 u8 reserved_at_8[0x18];
e281682b
SM		 7839
7840 u8 syndrome[0x20];
7841
b4ff3a36 7842 u8 reserved_at_40[0x40];
e281682b
SM		 7843};
7844
7845struct mlx5_ifc_destroy_mkey_in_bits {
7846 u8 opcode[0x10];
8a06a79b 7847 u8 uid[0x10];
e281682b 7848
b4ff3a36 7849 u8 reserved_at_20[0x10];
e281682b
SM		 7850 u8 op_mod[0x10];
7851
b4ff3a36 7852 u8 reserved_at_40[0x8];
e281682b
SM		 7853 u8 mkey_index[0x18];
7854
b4ff3a36 7855 u8 reserved_at_60[0x20];
e281682b
SM		 7856};
7857
7858struct mlx5_ifc_destroy_flow_table_out_bits {
7859 u8 status[0x8];
b4ff3a36 7860 u8 reserved_at_8[0x18];
e281682b
SM		 7861
7862 u8 syndrome[0x20];
7863
b4ff3a36 7864 u8 reserved_at_40[0x40];
e281682b
SM		 7865};
7866
7867struct mlx5_ifc_destroy_flow_table_in_bits {
7868 u8 opcode[0x10];
b4ff3a36 7869 u8 reserved_at_10[0x10];
e281682b 7870
b4ff3a36 7871 u8 reserved_at_20[0x10];
e281682b
SM		 7872 u8 op_mod[0x10];
7873
7d5e1423
SM		 7874 u8 other_vport[0x1];
7875 u8 reserved_at_41[0xf];
7876 u8 vport_number[0x10];
7877
7878 u8 reserved_at_60[0x20];
e281682b
SM		 7879
7880 u8 table_type[0x8];
b4ff3a36 7881 u8 reserved_at_88[0x18];
e281682b 7882
b4ff3a36 7883 u8 reserved_at_a0[0x8];
e281682b
SM		 7884 u8 table_id[0x18];
7885
b4ff3a36 7886 u8 reserved_at_c0[0x140];
e281682b
SM		 7887};
7888
7889struct mlx5_ifc_destroy_flow_group_out_bits {
7890 u8 status[0x8];
b4ff3a36 7891 u8 reserved_at_8[0x18];
e281682b
SM		 7892
7893 u8 syndrome[0x20];
7894
b4ff3a36 7895 u8 reserved_at_40[0x40];
e281682b
SM		 7896};
7897
7898struct mlx5_ifc_destroy_flow_group_in_bits {
7899 u8 opcode[0x10];
b4ff3a36 7900 u8 reserved_at_10[0x10];
e281682b 7901
b4ff3a36 7902 u8 reserved_at_20[0x10];
e281682b
SM		 7903 u8 op_mod[0x10];
7904
7d5e1423
SM		 7905 u8 other_vport[0x1];
7906 u8 reserved_at_41[0xf];
7907 u8 vport_number[0x10];
7908
7909 u8 reserved_at_60[0x20];
e281682b
SM		 7910
7911 u8 table_type[0x8];
b4ff3a36 7912 u8 reserved_at_88[0x18];
e281682b 7913
b4ff3a36 7914 u8 reserved_at_a0[0x8];
e281682b
SM		 7915 u8 table_id[0x18];
7916
7917 u8 group_id[0x20];
7918
b4ff3a36 7919 u8 reserved_at_e0[0x120];
e281682b
SM		 7920};
7921
7922struct mlx5_ifc_destroy_eq_out_bits {
7923 u8 status[0x8];
b4ff3a36 7924 u8 reserved_at_8[0x18];
e281682b
SM		 7925
7926 u8 syndrome[0x20];
7927
b4ff3a36 7928 u8 reserved_at_40[0x40];
e281682b
SM		 7929};
7930
7931struct mlx5_ifc_destroy_eq_in_bits {
7932 u8 opcode[0x10];
b4ff3a36 7933 u8 reserved_at_10[0x10];
e281682b 7934
b4ff3a36 7935 u8 reserved_at_20[0x10];
e281682b
SM		 7936 u8 op_mod[0x10];
7937
b4ff3a36 7938 u8 reserved_at_40[0x18];
e281682b
SM		 7939 u8 eq_number[0x8];
7940
b4ff3a36 7941 u8 reserved_at_60[0x20];
e281682b
SM		 7942};
7943
7944struct mlx5_ifc_destroy_dct_out_bits {
7945 u8 status[0x8];
b4ff3a36 7946 u8 reserved_at_8[0x18];
e281682b
SM		 7947
7948 u8 syndrome[0x20];
7949
b4ff3a36 7950 u8 reserved_at_40[0x40];
e281682b
SM		 7951};
7952
7953struct mlx5_ifc_destroy_dct_in_bits {
7954 u8 opcode[0x10];
774ea6ee 7955 u8 uid[0x10];
e281682b 7956
b4ff3a36 7957 u8 reserved_at_20[0x10];
e281682b
SM		 7958 u8 op_mod[0x10];
7959
b4ff3a36 7960 u8 reserved_at_40[0x8];
e281682b
SM		 7961 u8 dctn[0x18];
7962
b4ff3a36 7963 u8 reserved_at_60[0x20];
e281682b
SM		 7964};
7965
7966struct mlx5_ifc_destroy_cq_out_bits {
7967 u8 status[0x8];
b4ff3a36 7968 u8 reserved_at_8[0x18];
e281682b
SM		 7969
7970 u8 syndrome[0x20];
7971
b4ff3a36 7972 u8 reserved_at_40[0x40];
e281682b
SM		 7973};
7974
7975struct mlx5_ifc_destroy_cq_in_bits {
7976 u8 opcode[0x10];
9ba481e2 7977 u8 uid[0x10];
e281682b 7978
b4ff3a36 7979 u8 reserved_at_20[0x10];
e281682b
SM		 7980 u8 op_mod[0x10];
7981
b4ff3a36 7982 u8 reserved_at_40[0x8];
e281682b
SM		 7983 u8 cqn[0x18];
7984
b4ff3a36 7985 u8 reserved_at_60[0x20];
e281682b
SM		 7986};
7987
7988struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7989 u8 status[0x8];
b4ff3a36 7990 u8 reserved_at_8[0x18];
e281682b
SM		 7991
7992 u8 syndrome[0x20];
7993
b4ff3a36 7994 u8 reserved_at_40[0x40];
e281682b
SM		 7995};
7996
7997struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7998 u8 opcode[0x10];
b4ff3a36 7999 u8 reserved_at_10[0x10];
e281682b 8000
b4ff3a36 8001 u8 reserved_at_20[0x10];
e281682b
SM		 8002 u8 op_mod[0x10];
8003
b4ff3a36 8004 u8 reserved_at_40[0x20];
e281682b 8005
b4ff3a36 8006 u8 reserved_at_60[0x10];
e281682b
SM		 8007 u8 vxlan_udp_port[0x10];
8008};
8009
8010struct mlx5_ifc_delete_l2_table_entry_out_bits {
8011 u8 status[0x8];
b4ff3a36 8012 u8 reserved_at_8[0x18];
e281682b
SM		 8013
8014 u8 syndrome[0x20];
8015
b4ff3a36 8016 u8 reserved_at_40[0x40];
e281682b
SM		 8017};
8018
8019struct mlx5_ifc_delete_l2_table_entry_in_bits {
8020 u8 opcode[0x10];
b4ff3a36 8021 u8 reserved_at_10[0x10];
e281682b 8022
b4ff3a36 8023 u8 reserved_at_20[0x10];
e281682b
SM		 8024 u8 op_mod[0x10];
8025
b4ff3a36 8026 u8 reserved_at_40[0x60];
e281682b 8027
b4ff3a36 8028 u8 reserved_at_a0[0x8];
e281682b
SM		 8029 u8 table_index[0x18];
8030
b4ff3a36 8031 u8 reserved_at_c0[0x140];
e281682b
SM		 8032};
8033
8034struct mlx5_ifc_delete_fte_out_bits {
8035 u8 status[0x8];
b4ff3a36 8036 u8 reserved_at_8[0x18];
e281682b
SM		 8037
8038 u8 syndrome[0x20];
8039
b4ff3a36 8040 u8 reserved_at_40[0x40];
e281682b
SM		 8041};
8042
8043struct mlx5_ifc_delete_fte_in_bits {
8044 u8 opcode[0x10];
b4ff3a36 8045 u8 reserved_at_10[0x10];
e281682b 8046
b4ff3a36 8047 u8 reserved_at_20[0x10];
e281682b
SM		 8048 u8 op_mod[0x10];
8049
7d5e1423
SM		 8050 u8 other_vport[0x1];
8051 u8 reserved_at_41[0xf];
8052 u8 vport_number[0x10];
8053
8054 u8 reserved_at_60[0x20];
e281682b
SM		 8055
8056 u8 table_type[0x8];
b4ff3a36 8057 u8 reserved_at_88[0x18];
e281682b 8058
b4ff3a36 8059 u8 reserved_at_a0[0x8];
e281682b
SM		 8060 u8 table_id[0x18];
8061
b4ff3a36 8062 u8 reserved_at_c0[0x40];
e281682b
SM		 8063
8064 u8 flow_index[0x20];
8065
b4ff3a36 8066 u8 reserved_at_120[0xe0];
e281682b
SM		 8067};
8068
8069struct mlx5_ifc_dealloc_xrcd_out_bits {
8070 u8 status[0x8];
b4ff3a36 8071 u8 reserved_at_8[0x18];
e281682b
SM		 8072
8073 u8 syndrome[0x20];
8074
b4ff3a36 8075 u8 reserved_at_40[0x40];
e281682b
SM		 8076};
8077
8078struct mlx5_ifc_dealloc_xrcd_in_bits {
8079 u8 opcode[0x10];
bd371975 8080 u8 uid[0x10];
e281682b 8081
b4ff3a36 8082 u8 reserved_at_20[0x10];
e281682b
SM		 8083 u8 op_mod[0x10];
8084
b4ff3a36 8085 u8 reserved_at_40[0x8];
e281682b
SM		 8086 u8 xrcd[0x18];
8087
b4ff3a36 8088 u8 reserved_at_60[0x20];
e281682b
SM		 8089};
8090
8091struct mlx5_ifc_dealloc_uar_out_bits {
8092 u8 status[0x8];
b4ff3a36 8093 u8 reserved_at_8[0x18];
e281682b
SM		 8094
8095 u8 syndrome[0x20];
8096
b4ff3a36 8097 u8 reserved_at_40[0x40];
e281682b
SM		 8098};
8099
8100struct mlx5_ifc_dealloc_uar_in_bits {
8101 u8 opcode[0x10];
8de1e9b0 8102 u8 uid[0x10];
e281682b 8103
b4ff3a36 8104 u8 reserved_at_20[0x10];
e281682b
SM		 8105 u8 op_mod[0x10];
8106
b4ff3a36 8107 u8 reserved_at_40[0x8];
e281682b
SM		 8108 u8 uar[0x18];
8109
b4ff3a36 8110 u8 reserved_at_60[0x20];
e281682b
SM		 8111};
8112
8113struct mlx5_ifc_dealloc_transport_domain_out_bits {
8114 u8 status[0x8];
b4ff3a36 8115 u8 reserved_at_8[0x18];
e281682b
SM		 8116
8117 u8 syndrome[0x20];
8118
b4ff3a36 8119 u8 reserved_at_40[0x40];
e281682b
SM		 8120};
8121
8122struct mlx5_ifc_dealloc_transport_domain_in_bits {
8123 u8 opcode[0x10];
71bef2fd 8124 u8 uid[0x10];
e281682b 8125
b4ff3a36 8126 u8 reserved_at_20[0x10];
e281682b
SM		 8127 u8 op_mod[0x10];
8128
b4ff3a36 8129 u8 reserved_at_40[0x8];
e281682b
SM		 8130 u8 transport_domain[0x18];
8131
b4ff3a36 8132 u8 reserved_at_60[0x20];
e281682b
SM		 8133};
8134
8135struct mlx5_ifc_dealloc_q_counter_out_bits {
8136 u8 status[0x8];
b4ff3a36 8137 u8 reserved_at_8[0x18];
e281682b
SM		 8138
8139 u8 syndrome[0x20];
8140
b4ff3a36 8141 u8 reserved_at_40[0x40];
e281682b
SM		 8142};
8143
8144struct mlx5_ifc_dealloc_q_counter_in_bits {
8145 u8 opcode[0x10];
b4ff3a36 8146 u8 reserved_at_10[0x10];
e281682b 8147
b4ff3a36 8148 u8 reserved_at_20[0x10];
e281682b
SM		 8149 u8 op_mod[0x10];
8150
b4ff3a36 8151 u8 reserved_at_40[0x18];
e281682b
SM		 8152 u8 counter_set_id[0x8];
8153
b4ff3a36 8154 u8 reserved_at_60[0x20];
e281682b
SM		 8155};
8156
8157struct mlx5_ifc_dealloc_pd_out_bits {
8158 u8 status[0x8];
b4ff3a36 8159 u8 reserved_at_8[0x18];
e281682b
SM		 8160
8161 u8 syndrome[0x20];
8162
b4ff3a36 8163 u8 reserved_at_40[0x40];
e281682b
SM		 8164};
8165
8166struct mlx5_ifc_dealloc_pd_in_bits {
8167 u8 opcode[0x10];
bd371975 8168 u8 uid[0x10];
e281682b 8169
b4ff3a36 8170 u8 reserved_at_20[0x10];
e281682b
SM		 8171 u8 op_mod[0x10];
8172
b4ff3a36 8173 u8 reserved_at_40[0x8];
e281682b
SM		 8174 u8 pd[0x18];
8175
b4ff3a36 8176 u8 reserved_at_60[0x20];
e281682b
SM		 8177};
8178
9dc0b289
AV		 8179struct mlx5_ifc_dealloc_flow_counter_out_bits {
8180 u8 status[0x8];
8181 u8 reserved_at_8[0x18];
8182
8183 u8 syndrome[0x20];
8184
8185 u8 reserved_at_40[0x40];
8186};
8187
8188struct mlx5_ifc_dealloc_flow_counter_in_bits {
8189 u8 opcode[0x10];
8190 u8 reserved_at_10[0x10];
8191
8192 u8 reserved_at_20[0x10];
8193 u8 op_mod[0x10];
8194
a8ffcc74 8195 u8 flow_counter_id[0x20];
9dc0b289
AV		 8196
8197 u8 reserved_at_60[0x20];
8198};
8199
7486216b
SM		 8200struct mlx5_ifc_create_xrq_out_bits {
8201 u8 status[0x8];
8202 u8 reserved_at_8[0x18];
8203
8204 u8 syndrome[0x20];
8205
8206 u8 reserved_at_40[0x8];
8207 u8 xrqn[0x18];
8208
8209 u8 reserved_at_60[0x20];
8210};
8211
8212struct mlx5_ifc_create_xrq_in_bits {
8213 u8 opcode[0x10];
a0d8c054 8214 u8 uid[0x10];
7486216b
SM		 8215
8216 u8 reserved_at_20[0x10];
8217 u8 op_mod[0x10];
8218
8219 u8 reserved_at_40[0x40];
8220
8221 struct mlx5_ifc_xrqc_bits xrq_context;
8222};
8223
e281682b
SM		 8224struct mlx5_ifc_create_xrc_srq_out_bits {
8225 u8 status[0x8];
b4ff3a36 8226 u8 reserved_at_8[0x18];
e281682b
SM		 8227
8228 u8 syndrome[0x20];
8229
b4ff3a36 8230 u8 reserved_at_40[0x8];
e281682b
SM		 8231 u8 xrc_srqn[0x18];
8232
b4ff3a36 8233 u8 reserved_at_60[0x20];
e281682b
SM		 8234};
8235
8236struct mlx5_ifc_create_xrc_srq_in_bits {
8237 u8 opcode[0x10];
a0d8c054 8238 u8 uid[0x10];
e281682b 8239
b4ff3a36 8240 u8 reserved_at_20[0x10];
e281682b
SM		 8241 u8 op_mod[0x10];
8242
b4ff3a36 8243 u8 reserved_at_40[0x40];
e281682b
SM		 8244
8245 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8246
99b77fef
YH		 8247 u8 reserved_at_280[0x60];
8248
bd371975 8249 u8 xrc_srq_umem_valid[0x1];
99b77fef
YH		 8250 u8 reserved_at_2e1[0x1f];
8251
8252 u8 reserved_at_300[0x580];
e281682b 8253
b6ca09cb 8254 u8 pas[][0x40];
e281682b
SM		 8255};
8256
8257struct mlx5_ifc_create_tis_out_bits {
8258 u8 status[0x8];
b4ff3a36 8259 u8 reserved_at_8[0x18];
e281682b
SM		 8260
8261 u8 syndrome[0x20];
8262
b4ff3a36 8263 u8 reserved_at_40[0x8];
e281682b
SM		 8264 u8 tisn[0x18];
8265
b4ff3a36 8266 u8 reserved_at_60[0x20];
e281682b
SM		 8267};
8268
8269struct mlx5_ifc_create_tis_in_bits {
8270 u8 opcode[0x10];
bd371975 8271 u8 uid[0x10];
e281682b 8272
b4ff3a36 8273 u8 reserved_at_20[0x10];
e281682b
SM		 8274 u8 op_mod[0x10];
8275
b4ff3a36 8276 u8 reserved_at_40[0xc0];
e281682b
SM		 8277
8278 struct mlx5_ifc_tisc_bits ctx;
8279};
8280
8281struct mlx5_ifc_create_tir_out_bits {
8282 u8 status[0x8];
3e070470 8283 u8 icm_address_63_40[0x18];
e281682b
SM		 8284
8285 u8 syndrome[0x20];
8286
3e070470 8287 u8 icm_address_39_32[0x8];
e281682b
SM		 8288 u8 tirn[0x18];
8289
3e070470 8290 u8 icm_address_31_0[0x20];
e281682b
SM		 8291};
8292
8293struct mlx5_ifc_create_tir_in_bits {
8294 u8 opcode[0x10];
bd371975 8295 u8 uid[0x10];
e281682b 8296
b4ff3a36 8297 u8 reserved_at_20[0x10];
e281682b
SM		 8298 u8 op_mod[0x10];
8299
b4ff3a36 8300 u8 reserved_at_40[0xc0];
e281682b
SM		 8301
8302 struct mlx5_ifc_tirc_bits ctx;
8303};
8304
8305struct mlx5_ifc_create_srq_out_bits {
8306 u8 status[0x8];
b4ff3a36 8307 u8 reserved_at_8[0x18];
e281682b
SM		 8308
8309 u8 syndrome[0x20];
8310
b4ff3a36 8311 u8 reserved_at_40[0x8];
e281682b
SM		 8312 u8 srqn[0x18];
8313
b4ff3a36 8314 u8 reserved_at_60[0x20];
e281682b
SM		 8315};
8316
8317struct mlx5_ifc_create_srq_in_bits {
8318 u8 opcode[0x10];
a0d8c054 8319 u8 uid[0x10];
e281682b 8320
b4ff3a36 8321 u8 reserved_at_20[0x10];
e281682b
SM		 8322 u8 op_mod[0x10];
8323
b4ff3a36 8324 u8 reserved_at_40[0x40];
e281682b
SM		 8325
8326 struct mlx5_ifc_srqc_bits srq_context_entry;
8327
b4ff3a36 8328 u8 reserved_at_280[0x600];
e281682b 8329
b6ca09cb 8330 u8 pas[][0x40];
e281682b
SM		 8331};
8332
8333struct mlx5_ifc_create_sq_out_bits {
8334 u8 status[0x8];
b4ff3a36 8335 u8 reserved_at_8[0x18];
e281682b
SM		 8336
8337 u8 syndrome[0x20];
8338
b4ff3a36 8339 u8 reserved_at_40[0x8];
e281682b
SM		 8340 u8 sqn[0x18];
8341
b4ff3a36 8342 u8 reserved_at_60[0x20];
e281682b
SM		 8343};
8344
8345struct mlx5_ifc_create_sq_in_bits {
8346 u8 opcode[0x10];
430ae0d5 8347 u8 uid[0x10];
e281682b 8348
b4ff3a36 8349 u8 reserved_at_20[0x10];
e281682b
SM		 8350 u8 op_mod[0x10];
8351
b4ff3a36 8352 u8 reserved_at_40[0xc0];
e281682b
SM		 8353
8354 struct mlx5_ifc_sqc_bits ctx;
8355};
8356
813f8540
MHY		 8357struct mlx5_ifc_create_scheduling_element_out_bits {
8358 u8 status[0x8];
8359 u8 reserved_at_8[0x18];
8360
8361 u8 syndrome[0x20];
8362
8363 u8 reserved_at_40[0x40];
8364
8365 u8 scheduling_element_id[0x20];
8366
8367 u8 reserved_at_a0[0x160];
8368};
8369
8370struct mlx5_ifc_create_scheduling_element_in_bits {
8371 u8 opcode[0x10];
8372 u8 reserved_at_10[0x10];
8373
8374 u8 reserved_at_20[0x10];
8375 u8 op_mod[0x10];
8376
8377 u8 scheduling_hierarchy[0x8];
8378 u8 reserved_at_48[0x18];
8379
8380 u8 reserved_at_60[0xa0];
8381
8382 struct mlx5_ifc_scheduling_context_bits scheduling_context;
8383
8384 u8 reserved_at_300[0x100];
8385};
8386
e281682b
SM		 8387struct mlx5_ifc_create_rqt_out_bits {
8388 u8 status[0x8];
b4ff3a36 8389 u8 reserved_at_8[0x18];
e281682b
SM		 8390
8391 u8 syndrome[0x20];
8392
b4ff3a36 8393 u8 reserved_at_40[0x8];
e281682b
SM		 8394 u8 rqtn[0x18];
8395
b4ff3a36 8396 u8 reserved_at_60[0x20];
e281682b
SM		 8397};
8398
8399struct mlx5_ifc_create_rqt_in_bits {
8400 u8 opcode[0x10];
bd371975 8401 u8 uid[0x10];
e281682b 8402
b4ff3a36 8403 u8 reserved_at_20[0x10];
e281682b
SM		 8404 u8 op_mod[0x10];
8405
b4ff3a36 8406 u8 reserved_at_40[0xc0];
e281682b
SM		 8407
8408 struct mlx5_ifc_rqtc_bits rqt_context;
8409};
8410
8411struct mlx5_ifc_create_rq_out_bits {
8412 u8 status[0x8];
b4ff3a36 8413 u8 reserved_at_8[0x18];
e281682b
SM		 8414
8415 u8 syndrome[0x20];
8416
b4ff3a36 8417 u8 reserved_at_40[0x8];
e281682b
SM		 8418 u8 rqn[0x18];
8419
b4ff3a36 8420 u8 reserved_at_60[0x20];
e281682b
SM		 8421};
8422
8423struct mlx5_ifc_create_rq_in_bits {
8424 u8 opcode[0x10];
d269b3af 8425 u8 uid[0x10];
e281682b 8426
b4ff3a36 8427 u8 reserved_at_20[0x10];
e281682b
SM		 8428 u8 op_mod[0x10];
8429
b4ff3a36 8430 u8 reserved_at_40[0xc0];
e281682b
SM		 8431
8432 struct mlx5_ifc_rqc_bits ctx;
8433};
8434
8435struct mlx5_ifc_create_rmp_out_bits {
8436 u8 status[0x8];
b4ff3a36 8437 u8 reserved_at_8[0x18];
e281682b
SM		 8438
8439 u8 syndrome[0x20];
8440
b4ff3a36 8441 u8 reserved_at_40[0x8];
e281682b
SM		 8442 u8 rmpn[0x18];
8443
b4ff3a36 8444 u8 reserved_at_60[0x20];
e281682b
SM		 8445};
8446
8447struct mlx5_ifc_create_rmp_in_bits {
8448 u8 opcode[0x10];
a0d8c054 8449 u8 uid[0x10];
e281682b 8450
b4ff3a36 8451 u8 reserved_at_20[0x10];
e281682b
SM		 8452 u8 op_mod[0x10];
8453
b4ff3a36 8454 u8 reserved_at_40[0xc0];
e281682b
SM		 8455
8456 struct mlx5_ifc_rmpc_bits ctx;
8457};
8458
8459struct mlx5_ifc_create_qp_out_bits {
8460 u8 status[0x8];
b4ff3a36 8461 u8 reserved_at_8[0x18];
e281682b
SM		 8462
8463 u8 syndrome[0x20];
8464
b4ff3a36 8465 u8 reserved_at_40[0x8];
e281682b
SM		 8466 u8 qpn[0x18];
8467
6b646a7e 8468 u8 ece[0x20];
e281682b
SM		 8469};
8470
8471struct mlx5_ifc_create_qp_in_bits {
8472 u8 opcode[0x10];
4ac63ec7 8473 u8 uid[0x10];
e281682b 8474
b4ff3a36 8475 u8 reserved_at_20[0x10];
e281682b
SM		 8476 u8 op_mod[0x10];
8477
4dca6509
MG		 8478 u8 reserved_at_40[0x8];
8479 u8 input_qpn[0x18];
e281682b 8480
4dca6509 8481 u8 reserved_at_60[0x20];
e281682b
SM		 8482 u8 opt_param_mask[0x20];
8483
6b646a7e 8484 u8 ece[0x20];
e281682b
SM		 8485
8486 struct mlx5_ifc_qpc_bits qpc;
8487
bd371975
LR		 8488 u8 reserved_at_800[0x60];
8489
8490 u8 wq_umem_valid[0x1];
8491 u8 reserved_at_861[0x1f];
e281682b 8492
b6ca09cb 8493 u8 pas[][0x40];
e281682b
SM		 8494};
8495
8496struct mlx5_ifc_create_psv_out_bits {
8497 u8 status[0x8];
b4ff3a36 8498 u8 reserved_at_8[0x18];
e281682b
SM		 8499
8500 u8 syndrome[0x20];
8501
b4ff3a36 8502 u8 reserved_at_40[0x40];
e281682b 8503
b4ff3a36 8504 u8 reserved_at_80[0x8];
e281682b
SM		 8505 u8 psv0_index[0x18];
8506
b4ff3a36 8507 u8 reserved_at_a0[0x8];
e281682b
SM		 8508 u8 psv1_index[0x18];
8509
b4ff3a36 8510 u8 reserved_at_c0[0x8];
e281682b
SM		 8511 u8 psv2_index[0x18];
8512
b4ff3a36 8513 u8 reserved_at_e0[0x8];
e281682b
SM		 8514 u8 psv3_index[0x18];
8515};
8516
8517struct mlx5_ifc_create_psv_in_bits {
8518 u8 opcode[0x10];
b4ff3a36 8519 u8 reserved_at_10[0x10];
e281682b 8520
b4ff3a36 8521 u8 reserved_at_20[0x10];
e281682b
SM		 8522 u8 op_mod[0x10];
8523
8524 u8 num_psv[0x4];
b4ff3a36 8525 u8 reserved_at_44[0x4];
e281682b
SM		 8526 u8 pd[0x18];
8527
b4ff3a36 8528 u8 reserved_at_60[0x20];
e281682b
SM		 8529};
8530
8531struct mlx5_ifc_create_mkey_out_bits {
8532 u8 status[0x8];
b4ff3a36 8533 u8 reserved_at_8[0x18];
e281682b
SM		 8534
8535 u8 syndrome[0x20];
8536
b4ff3a36 8537 u8 reserved_at_40[0x8];
e281682b
SM		 8538 u8 mkey_index[0x18];
8539
b4ff3a36 8540 u8 reserved_at_60[0x20];
e281682b
SM		 8541};
8542
8543struct mlx5_ifc_create_mkey_in_bits {
8544 u8 opcode[0x10];
8a06a79b 8545 u8 uid[0x10];
e281682b 8546
b4ff3a36 8547 u8 reserved_at_20[0x10];
e281682b
SM		 8548 u8 op_mod[0x10];
8549
b4ff3a36 8550 u8 reserved_at_40[0x20];
e281682b
SM		 8551
8552 u8 pg_access[0x1];
bd371975
LR		 8553 u8 mkey_umem_valid[0x1];
8554 u8 reserved_at_62[0x1e];
e281682b
SM		 8555
8556 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8557
b4ff3a36 8558 u8 reserved_at_280[0x80];
e281682b
SM		 8559
8560 u8 translations_octword_actual_size[0x20];
8561
b4ff3a36 8562 u8 reserved_at_320[0x560];
e281682b 8563
b6ca09cb 8564 u8 klm_pas_mtt[][0x20];
e281682b
SM		 8565};
8566
97b5484e
AV		 8567enum {
8568 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8569 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8570 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8571 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8572 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8573 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8574 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8575};
8576
e281682b
SM		 8577struct mlx5_ifc_create_flow_table_out_bits {
8578 u8 status[0x8];
97b5484e 8579 u8 icm_address_63_40[0x18];
e281682b
SM		 8580
8581 u8 syndrome[0x20];
8582
97b5484e 8583 u8 icm_address_39_32[0x8];
e281682b
SM		 8584 u8 table_id[0x18];
8585
97b5484e 8586 u8 icm_address_31_0[0x20];
0c90e9c6
MG		 8587};
8588
e281682b
SM		 8589struct mlx5_ifc_create_flow_table_in_bits {
8590 u8 opcode[0x10];
f484da84 8591 u8 uid[0x10];
e281682b 8592
b4ff3a36 8593 u8 reserved_at_20[0x10];
e281682b
SM		 8594 u8 op_mod[0x10];
8595
7d5e1423
SM		 8596 u8 other_vport[0x1];
8597 u8 reserved_at_41[0xf];
8598 u8 vport_number[0x10];
8599
8600 u8 reserved_at_60[0x20];
e281682b
SM		 8601
8602 u8 table_type[0x8];
b4ff3a36 8603 u8 reserved_at_88[0x18];
e281682b 8604
b4ff3a36 8605 u8 reserved_at_a0[0x20];
e281682b 8606
0c90e9c6 8607 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 8608};
8609
8610struct mlx5_ifc_create_flow_group_out_bits {
8611 u8 status[0x8];
b4ff3a36 8612 u8 reserved_at_8[0x18];
e281682b
SM		 8613
8614 u8 syndrome[0x20];
8615
b4ff3a36 8616 u8 reserved_at_40[0x8];
e281682b
SM		 8617 u8 group_id[0x18];
8618
b4ff3a36 8619 u8 reserved_at_60[0x20];
e281682b
SM		 8620};
8621
e7e2519e
MG		 8622enum {
8623 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8624 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8625};
8626
e281682b 8627enum {
71c6e863
AL		 8628 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8629 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8630 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8631 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
e281682b
SM		 8632};
8633
8634struct mlx5_ifc_create_flow_group_in_bits {
8635 u8 opcode[0x10];
b4ff3a36 8636 u8 reserved_at_10[0x10];
e281682b 8637
b4ff3a36 8638 u8 reserved_at_20[0x10];
e281682b
SM		 8639 u8 op_mod[0x10];
8640
7d5e1423
SM		 8641 u8 other_vport[0x1];
8642 u8 reserved_at_41[0xf];
8643 u8 vport_number[0x10];
8644
8645 u8 reserved_at_60[0x20];
e281682b
SM		 8646
8647 u8 table_type[0x8];
e7e2519e
MG		 8648 u8 reserved_at_88[0x4];
8649 u8 group_type[0x4];
8650 u8 reserved_at_90[0x10];
e281682b 8651
b4ff3a36 8652 u8 reserved_at_a0[0x8];
e281682b
SM		 8653 u8 table_id[0x18];
8654
3e99df87
SK		 8655 u8 source_eswitch_owner_vhca_id_valid[0x1];
8656
8657 u8 reserved_at_c1[0x1f];
e281682b
SM		 8658
8659 u8 start_flow_index[0x20];
8660
b4ff3a36 8661 u8 reserved_at_100[0x20];
e281682b
SM		 8662
8663 u8 end_flow_index[0x20];
8664
e7e2519e
MG		 8665 u8 reserved_at_140[0x10];
8666 u8 match_definer_id[0x10];
8667
8668 u8 reserved_at_160[0x80];
e281682b 8669
b4ff3a36 8670 u8 reserved_at_1e0[0x18];
e281682b
SM		 8671 u8 match_criteria_enable[0x8];
8672
8673 struct mlx5_ifc_fte_match_param_bits match_criteria;
8674
b4ff3a36 8675 u8 reserved_at_1200[0xe00];
e281682b
SM		 8676};
8677
8678struct mlx5_ifc_create_eq_out_bits {
8679 u8 status[0x8];
b4ff3a36 8680 u8 reserved_at_8[0x18];
e281682b
SM		 8681
8682 u8 syndrome[0x20];
8683
b4ff3a36 8684 u8 reserved_at_40[0x18];
e281682b
SM		 8685 u8 eq_number[0x8];
8686
b4ff3a36 8687 u8 reserved_at_60[0x20];
e281682b
SM		 8688};
8689
8690struct mlx5_ifc_create_eq_in_bits {
8691 u8 opcode[0x10];
c191f934 8692 u8 uid[0x10];
e281682b 8693
b4ff3a36 8694 u8 reserved_at_20[0x10];
e281682b
SM		 8695 u8 op_mod[0x10];
8696
b4ff3a36 8697 u8 reserved_at_40[0x40];
e281682b
SM		 8698
8699 struct mlx5_ifc_eqc_bits eq_context_entry;
8700
b4ff3a36 8701 u8 reserved_at_280[0x40];
e281682b 8702
b9a7ba55 8703 u8 event_bitmask[4][0x40];
e281682b 8704
b9a7ba55 8705 u8 reserved_at_3c0[0x4c0];
e281682b 8706
b6ca09cb 8707 u8 pas[][0x40];
e281682b
SM		 8708};
8709
8710struct mlx5_ifc_create_dct_out_bits {
8711 u8 status[0x8];
b4ff3a36 8712 u8 reserved_at_8[0x18];
e281682b
SM		 8713
8714 u8 syndrome[0x20];
8715
b4ff3a36 8716 u8 reserved_at_40[0x8];
e281682b
SM		 8717 u8 dctn[0x18];
8718
a645a89d 8719 u8 ece[0x20];
e281682b
SM		 8720};
8721
8722struct mlx5_ifc_create_dct_in_bits {
8723 u8 opcode[0x10];
774ea6ee 8724 u8 uid[0x10];
e281682b 8725
b4ff3a36 8726 u8 reserved_at_20[0x10];
e281682b
SM		 8727 u8 op_mod[0x10];
8728
b4ff3a36 8729 u8 reserved_at_40[0x40];
e281682b
SM		 8730
8731 struct mlx5_ifc_dctc_bits dct_context_entry;
8732
b4ff3a36 8733 u8 reserved_at_280[0x180];
e281682b
SM		 8734};
8735
8736struct mlx5_ifc_create_cq_out_bits {
8737 u8 status[0x8];
b4ff3a36 8738 u8 reserved_at_8[0x18];
e281682b
SM		 8739
8740 u8 syndrome[0x20];
8741
b4ff3a36 8742 u8 reserved_at_40[0x8];
e281682b
SM		 8743 u8 cqn[0x18];
8744
b4ff3a36 8745 u8 reserved_at_60[0x20];
e281682b
SM		 8746};
8747
8748struct mlx5_ifc_create_cq_in_bits {
8749 u8 opcode[0x10];
9ba481e2 8750 u8 uid[0x10];
e281682b 8751
b4ff3a36 8752 u8 reserved_at_20[0x10];
e281682b
SM		 8753 u8 op_mod[0x10];
8754
b4ff3a36 8755 u8 reserved_at_40[0x40];
e281682b
SM		 8756
8757 struct mlx5_ifc_cqc_bits cq_context;
8758
bd371975
LR		 8759 u8 reserved_at_280[0x60];
8760
8761 u8 cq_umem_valid[0x1];
8762 u8 reserved_at_2e1[0x59f];
e281682b 8763
b6ca09cb 8764 u8 pas[][0x40];
e281682b
SM		 8765};
8766
8767struct mlx5_ifc_config_int_moderation_out_bits {
8768 u8 status[0x8];
b4ff3a36 8769 u8 reserved_at_8[0x18];
e281682b
SM		 8770
8771 u8 syndrome[0x20];
8772
b4ff3a36 8773 u8 reserved_at_40[0x4];
e281682b
SM		 8774 u8 min_delay[0xc];
8775 u8 int_vector[0x10];
8776
b4ff3a36 8777 u8 reserved_at_60[0x20];
e281682b
SM		 8778};
8779
8780enum {
8781 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8782 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8783};
8784
8785struct mlx5_ifc_config_int_moderation_in_bits {
8786 u8 opcode[0x10];
b4ff3a36 8787 u8 reserved_at_10[0x10];
e281682b 8788
b4ff3a36 8789 u8 reserved_at_20[0x10];
e281682b
SM		 8790 u8 op_mod[0x10];
8791
b4ff3a36 8792 u8 reserved_at_40[0x4];
e281682b
SM		 8793 u8 min_delay[0xc];
8794 u8 int_vector[0x10];
8795
b4ff3a36 8796 u8 reserved_at_60[0x20];
e281682b
SM		 8797};
8798
8799struct mlx5_ifc_attach_to_mcg_out_bits {
8800 u8 status[0x8];
b4ff3a36 8801 u8 reserved_at_8[0x18];
e281682b
SM		 8802
8803 u8 syndrome[0x20];
8804
b4ff3a36 8805 u8 reserved_at_40[0x40];
e281682b
SM		 8806};
8807
8808struct mlx5_ifc_attach_to_mcg_in_bits {
8809 u8 opcode[0x10];
bd371975 8810 u8 uid[0x10];
e281682b 8811
b4ff3a36 8812 u8 reserved_at_20[0x10];
e281682b
SM		 8813 u8 op_mod[0x10];
8814
b4ff3a36 8815 u8 reserved_at_40[0x8];
e281682b
SM		 8816 u8 qpn[0x18];
8817
b4ff3a36 8818 u8 reserved_at_60[0x20];
e281682b
SM		 8819
8820 u8 multicast_gid[16][0x8];
8821};
8822
7486216b
SM		 8823struct mlx5_ifc_arm_xrq_out_bits {
8824 u8 status[0x8];
8825 u8 reserved_at_8[0x18];
8826
8827 u8 syndrome[0x20];
8828
8829 u8 reserved_at_40[0x40];
8830};
8831
8832struct mlx5_ifc_arm_xrq_in_bits {
8833 u8 opcode[0x10];
8834 u8 reserved_at_10[0x10];
8835
8836 u8 reserved_at_20[0x10];
8837 u8 op_mod[0x10];
8838
8839 u8 reserved_at_40[0x8];
8840 u8 xrqn[0x18];
8841
8842 u8 reserved_at_60[0x10];
8843 u8 lwm[0x10];
8844};
8845
e281682b
SM		 8846struct mlx5_ifc_arm_xrc_srq_out_bits {
8847 u8 status[0x8];
b4ff3a36 8848 u8 reserved_at_8[0x18];
e281682b
SM		 8849
8850 u8 syndrome[0x20];
8851
b4ff3a36 8852 u8 reserved_at_40[0x40];
e281682b
SM		 8853};
8854
8855enum {
8856 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8857};
8858
8859struct mlx5_ifc_arm_xrc_srq_in_bits {
8860 u8 opcode[0x10];
a0d8c054 8861 u8 uid[0x10];
e281682b 8862
b4ff3a36 8863 u8 reserved_at_20[0x10];
e281682b
SM		 8864 u8 op_mod[0x10];
8865
b4ff3a36 8866 u8 reserved_at_40[0x8];
e281682b
SM		 8867 u8 xrc_srqn[0x18];
8868
b4ff3a36 8869 u8 reserved_at_60[0x10];
e281682b
SM		 8870 u8 lwm[0x10];
8871};
8872
8873struct mlx5_ifc_arm_rq_out_bits {
8874 u8 status[0x8];
b4ff3a36 8875 u8 reserved_at_8[0x18];
e281682b
SM		 8876
8877 u8 syndrome[0x20];
8878
b4ff3a36 8879 u8 reserved_at_40[0x40];
e281682b
SM		 8880};
8881
8882enum {
7486216b
SM		 8883 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8884 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 8885};
8886
8887struct mlx5_ifc_arm_rq_in_bits {
8888 u8 opcode[0x10];
a0d8c054 8889 u8 uid[0x10];
e281682b 8890
b4ff3a36 8891 u8 reserved_at_20[0x10];
e281682b
SM		 8892 u8 op_mod[0x10];
8893
b4ff3a36 8894 u8 reserved_at_40[0x8];
e281682b
SM		 8895 u8 srq_number[0x18];
8896
b4ff3a36 8897 u8 reserved_at_60[0x10];
e281682b
SM		 8898 u8 lwm[0x10];
8899};
8900
8901struct mlx5_ifc_arm_dct_out_bits {
8902 u8 status[0x8];
b4ff3a36 8903 u8 reserved_at_8[0x18];
e281682b
SM		 8904
8905 u8 syndrome[0x20];
8906
b4ff3a36 8907 u8 reserved_at_40[0x40];
e281682b
SM		 8908};
8909
8910struct mlx5_ifc_arm_dct_in_bits {
8911 u8 opcode[0x10];
b4ff3a36 8912 u8 reserved_at_10[0x10];
e281682b 8913
b4ff3a36 8914 u8 reserved_at_20[0x10];
e281682b
SM		 8915 u8 op_mod[0x10];
8916
b4ff3a36 8917 u8 reserved_at_40[0x8];
e281682b
SM		 8918 u8 dct_number[0x18];
8919
b4ff3a36 8920 u8 reserved_at_60[0x20];
e281682b
SM		 8921};
8922
8923struct mlx5_ifc_alloc_xrcd_out_bits {
8924 u8 status[0x8];
b4ff3a36 8925 u8 reserved_at_8[0x18];
e281682b
SM		 8926
8927 u8 syndrome[0x20];
8928
b4ff3a36 8929 u8 reserved_at_40[0x8];
e281682b
SM		 8930 u8 xrcd[0x18];
8931
b4ff3a36 8932 u8 reserved_at_60[0x20];
e281682b
SM		 8933};
8934
8935struct mlx5_ifc_alloc_xrcd_in_bits {
8936 u8 opcode[0x10];
bd371975 8937 u8 uid[0x10];
e281682b 8938
b4ff3a36 8939 u8 reserved_at_20[0x10];
e281682b
SM		 8940 u8 op_mod[0x10];
8941
b4ff3a36 8942 u8 reserved_at_40[0x40];
e281682b
SM		 8943};
8944
8945struct mlx5_ifc_alloc_uar_out_bits {
8946 u8 status[0x8];
b4ff3a36 8947 u8 reserved_at_8[0x18];
e281682b
SM		 8948
8949 u8 syndrome[0x20];
8950
b4ff3a36 8951 u8 reserved_at_40[0x8];
e281682b
SM		 8952 u8 uar[0x18];
8953
b4ff3a36 8954 u8 reserved_at_60[0x20];
e281682b
SM		 8955};
8956
8957struct mlx5_ifc_alloc_uar_in_bits {
8958 u8 opcode[0x10];
8de1e9b0 8959 u8 uid[0x10];
e281682b 8960
b4ff3a36 8961 u8 reserved_at_20[0x10];
e281682b
SM		 8962 u8 op_mod[0x10];
8963
b4ff3a36 8964 u8 reserved_at_40[0x40];
e281682b
SM		 8965};
8966
8967struct mlx5_ifc_alloc_transport_domain_out_bits {
8968 u8 status[0x8];
b4ff3a36 8969 u8 reserved_at_8[0x18];
e281682b
SM		 8970
8971 u8 syndrome[0x20];
8972
b4ff3a36 8973 u8 reserved_at_40[0x8];
e281682b
SM		 8974 u8 transport_domain[0x18];
8975
b4ff3a36 8976 u8 reserved_at_60[0x20];
e281682b
SM		 8977};
8978
8979struct mlx5_ifc_alloc_transport_domain_in_bits {
8980 u8 opcode[0x10];
71bef2fd 8981 u8 uid[0x10];
e281682b 8982
b4ff3a36 8983 u8 reserved_at_20[0x10];
e281682b
SM		 8984 u8 op_mod[0x10];
8985
b4ff3a36 8986 u8 reserved_at_40[0x40];
e281682b
SM		 8987};
8988
8989struct mlx5_ifc_alloc_q_counter_out_bits {
8990 u8 status[0x8];
b4ff3a36 8991 u8 reserved_at_8[0x18];
e281682b
SM		 8992
8993 u8 syndrome[0x20];
8994
b4ff3a36 8995 u8 reserved_at_40[0x18];
e281682b
SM		 8996 u8 counter_set_id[0x8];
8997
b4ff3a36 8998 u8 reserved_at_60[0x20];
e281682b
SM		 8999};
9000
9001struct mlx5_ifc_alloc_q_counter_in_bits {
9002 u8 opcode[0x10];
2acc7957 9003 u8 uid[0x10];
e281682b 9004
b4ff3a36 9005 u8 reserved_at_20[0x10];
e281682b
SM		 9006 u8 op_mod[0x10];
9007
b4ff3a36 9008 u8 reserved_at_40[0x40];
e281682b
SM		 9009};
9010
9011struct mlx5_ifc_alloc_pd_out_bits {
9012 u8 status[0x8];
b4ff3a36 9013 u8 reserved_at_8[0x18];
e281682b
SM		 9014
9015 u8 syndrome[0x20];
9016
b4ff3a36 9017 u8 reserved_at_40[0x8];
e281682b
SM		 9018 u8 pd[0x18];
9019
b4ff3a36 9020 u8 reserved_at_60[0x20];
e281682b
SM		 9021};
9022
9023struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289 9024 u8 opcode[0x10];
bd371975 9025 u8 uid[0x10];
9dc0b289
AV		 9026
9027 u8 reserved_at_20[0x10];
9028 u8 op_mod[0x10];
9029
9030 u8 reserved_at_40[0x40];
9031};
9032
9033struct mlx5_ifc_alloc_flow_counter_out_bits {
9034 u8 status[0x8];
9035 u8 reserved_at_8[0x18];
9036
9037 u8 syndrome[0x20];
9038
a8ffcc74 9039 u8 flow_counter_id[0x20];
9dc0b289
AV		 9040
9041 u8 reserved_at_60[0x20];
9042};
9043
9044struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 9045 u8 opcode[0x10];
b4ff3a36 9046 u8 reserved_at_10[0x10];
e281682b 9047
b4ff3a36 9048 u8 reserved_at_20[0x10];
e281682b
SM		 9049 u8 op_mod[0x10];
9050
8536a6bf
GT		 9051 u8 reserved_at_40[0x38];
9052 u8 flow_counter_bulk[0x8];
e281682b
SM		 9053};
9054
9055struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9056 u8 status[0x8];
b4ff3a36 9057 u8 reserved_at_8[0x18];
e281682b
SM		 9058
9059 u8 syndrome[0x20];
9060
b4ff3a36 9061 u8 reserved_at_40[0x40];
e281682b
SM		 9062};
9063
9064struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9065 u8 opcode[0x10];
b4ff3a36 9066 u8 reserved_at_10[0x10];
e281682b 9067
b4ff3a36 9068 u8 reserved_at_20[0x10];
e281682b
SM		 9069 u8 op_mod[0x10];
9070
b4ff3a36 9071 u8 reserved_at_40[0x20];
e281682b 9072
b4ff3a36 9073 u8 reserved_at_60[0x10];
e281682b
SM		 9074 u8 vxlan_udp_port[0x10];
9075};
9076
37e92a9d 9077struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 9078 u8 status[0x8];
9079 u8 reserved_at_8[0x18];
9080
9081 u8 syndrome[0x20];
9082
9083 u8 reserved_at_40[0x40];
9084};
9085
1326034b
YH		 9086struct mlx5_ifc_set_pp_rate_limit_context_bits {
9087 u8 rate_limit[0x20];
9088
9089 u8 burst_upper_bound[0x20];
9090
9091 u8 reserved_at_40[0x10];
9092 u8 typical_packet_size[0x10];
9093
9094 u8 reserved_at_60[0x120];
9095};
9096
37e92a9d 9097struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b 9098 u8 opcode[0x10];
1326034b 9099 u8 uid[0x10];
7486216b
SM		 9100
9101 u8 reserved_at_20[0x10];
9102 u8 op_mod[0x10];
9103
9104 u8 reserved_at_40[0x10];
9105 u8 rate_limit_index[0x10];
9106
9107 u8 reserved_at_60[0x20];
9108
1326034b 9109 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
7486216b
SM		 9110};
9111
e281682b
SM		 9112struct mlx5_ifc_access_register_out_bits {
9113 u8 status[0x8];
b4ff3a36 9114 u8 reserved_at_8[0x18];
e281682b
SM		 9115
9116 u8 syndrome[0x20];
9117
b4ff3a36 9118 u8 reserved_at_40[0x40];
e281682b 9119
b6ca09cb 9120 u8 register_data[][0x20];
e281682b
SM		 9121};
9122
9123enum {
9124 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
9125 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
9126};
9127
9128struct mlx5_ifc_access_register_in_bits {
9129 u8 opcode[0x10];
b4ff3a36 9130 u8 reserved_at_10[0x10];
e281682b 9131
b4ff3a36 9132 u8 reserved_at_20[0x10];
e281682b
SM		 9133 u8 op_mod[0x10];
9134
b4ff3a36 9135 u8 reserved_at_40[0x10];
e281682b
SM		 9136 u8 register_id[0x10];
9137
9138 u8 argument[0x20];
9139
b6ca09cb 9140 u8 register_data[][0x20];
e281682b
SM		 9141};
9142
9143struct mlx5_ifc_sltp_reg_bits {
9144 u8 status[0x4];
9145 u8 version[0x4];
9146 u8 local_port[0x8];
9147 u8 pnat[0x2];
b4ff3a36 9148 u8 reserved_at_12[0x2];
e281682b 9149 u8 lane[0x4];
b4ff3a36 9150 u8 reserved_at_18[0x8];
e281682b 9151
b4ff3a36 9152 u8 reserved_at_20[0x20];
e281682b 9153
b4ff3a36 9154 u8 reserved_at_40[0x7];
e281682b
SM		 9155 u8 polarity[0x1];
9156 u8 ob_tap0[0x8];
9157 u8 ob_tap1[0x8];
9158 u8 ob_tap2[0x8];
9159
b4ff3a36 9160 u8 reserved_at_60[0xc];
e281682b
SM		 9161 u8 ob_preemp_mode[0x4];
9162 u8 ob_reg[0x8];
9163 u8 ob_bias[0x8];
9164
b4ff3a36 9165 u8 reserved_at_80[0x20];
e281682b
SM		 9166};
9167
9168struct mlx5_ifc_slrg_reg_bits {
9169 u8 status[0x4];
9170 u8 version[0x4];
9171 u8 local_port[0x8];
9172 u8 pnat[0x2];
b4ff3a36 9173 u8 reserved_at_12[0x2];
e281682b 9174 u8 lane[0x4];
b4ff3a36 9175 u8 reserved_at_18[0x8];
e281682b
SM		 9176
9177 u8 time_to_link_up[0x10];
b4ff3a36 9178 u8 reserved_at_30[0xc];
e281682b
SM		 9179 u8 grade_lane_speed[0x4];
9180
9181 u8 grade_version[0x8];
9182 u8 grade[0x18];
9183
b4ff3a36 9184 u8 reserved_at_60[0x4];
e281682b
SM		 9185 u8 height_grade_type[0x4];
9186 u8 height_grade[0x18];
9187
9188 u8 height_dz[0x10];
9189 u8 height_dv[0x10];
9190
b4ff3a36 9191 u8 reserved_at_a0[0x10];
e281682b
SM		 9192 u8 height_sigma[0x10];
9193
b4ff3a36 9194 u8 reserved_at_c0[0x20];
e281682b 9195
b4ff3a36 9196 u8 reserved_at_e0[0x4];
e281682b
SM		 9197 u8 phase_grade_type[0x4];
9198 u8 phase_grade[0x18];
9199
b4ff3a36 9200 u8 reserved_at_100[0x8];
e281682b 9201 u8 phase_eo_pos[0x8];
b4ff3a36 9202 u8 reserved_at_110[0x8];
e281682b
SM		 9203 u8 phase_eo_neg[0x8];
9204
9205 u8 ffe_set_tested[0x10];
9206 u8 test_errors_per_lane[0x10];
9207};
9208
9209struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 9210 u8 reserved_at_0[0x8];
e281682b 9211 u8 local_port[0x8];
b4ff3a36 9212 u8 reserved_at_10[0x10];
e281682b 9213
b4ff3a36 9214 u8 reserved_at_20[0x1c];
e281682b
SM		 9215 u8 vl_hw_cap[0x4];
9216
b4ff3a36 9217 u8 reserved_at_40[0x1c];
e281682b
SM		 9218 u8 vl_admin[0x4];
9219
b4ff3a36 9220 u8 reserved_at_60[0x1c];
e281682b
SM		 9221 u8 vl_operational[0x4];
9222};
9223
9224struct mlx5_ifc_pude_reg_bits {
9225 u8 swid[0x8];
9226 u8 local_port[0x8];
b4ff3a36 9227 u8 reserved_at_10[0x4];
e281682b 9228 u8 admin_status[0x4];
b4ff3a36 9229 u8 reserved_at_18[0x4];
e281682b
SM		 9230 u8 oper_status[0x4];
9231
b4ff3a36 9232 u8 reserved_at_20[0x60];
e281682b
SM		 9233};
9234
9235struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 9236 u8 reserved_at_0[0x1];
7486216b 9237 u8 an_disable_admin[0x1];
e7e31ca4
BW		 9238 u8 an_disable_cap[0x1];
9239 u8 reserved_at_3[0x5];
e281682b 9240 u8 local_port[0x8];
b4ff3a36 9241 u8 reserved_at_10[0xd];
e281682b
SM		 9242 u8 proto_mask[0x3];
9243
7486216b 9244 u8 an_status[0x4];
dc392fc5
MB		 9245 u8 reserved_at_24[0xc];
9246 u8 data_rate_oper[0x10];
a0a89989
AL		 9247
9248 u8 ext_eth_proto_capability[0x20];
e281682b
SM		 9249
9250 u8 eth_proto_capability[0x20];
9251
9252 u8 ib_link_width_capability[0x10];
9253 u8 ib_proto_capability[0x10];
9254
a0a89989 9255 u8 ext_eth_proto_admin[0x20];
e281682b
SM		 9256
9257 u8 eth_proto_admin[0x20];
9258
9259 u8 ib_link_width_admin[0x10];
9260 u8 ib_proto_admin[0x10];
9261
a0a89989 9262 u8 ext_eth_proto_oper[0x20];
e281682b
SM		 9263
9264 u8 eth_proto_oper[0x20];
9265
9266 u8 ib_link_width_oper[0x10];
9267 u8 ib_proto_oper[0x10];
9268
5b4793f8
EBE		 9269 u8 reserved_at_160[0x1c];
9270 u8 connector_type[0x4];
e281682b
SM		 9271
9272 u8 eth_proto_lp_advertise[0x20];
9273
b4ff3a36 9274 u8 reserved_at_1a0[0x60];
e281682b
SM		 9275};
9276
7d5e1423
SM		 9277struct mlx5_ifc_mlcr_reg_bits {
9278 u8 reserved_at_0[0x8];
9279 u8 local_port[0x8];
9280 u8 reserved_at_10[0x20];
9281
9282 u8 beacon_duration[0x10];
9283 u8 reserved_at_40[0x10];
9284
9285 u8 beacon_remain[0x10];
9286};
9287
e281682b 9288struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 9289 u8 reserved_at_0[0x20];
e281682b
SM		 9290
9291 u8 algorithm_options[0x10];
b4ff3a36 9292 u8 reserved_at_30[0x4];
e281682b
SM		 9293 u8 repetitions_mode[0x4];
9294 u8 num_of_repetitions[0x8];
9295
9296 u8 grade_version[0x8];
9297 u8 height_grade_type[0x4];
9298 u8 phase_grade_type[0x4];
9299 u8 height_grade_weight[0x8];
9300 u8 phase_grade_weight[0x8];
9301
9302 u8 gisim_measure_bits[0x10];
9303 u8 adaptive_tap_measure_bits[0x10];
9304
9305 u8 ber_bath_high_error_threshold[0x10];
9306 u8 ber_bath_mid_error_threshold[0x10];
9307
9308 u8 ber_bath_low_error_threshold[0x10];
9309 u8 one_ratio_high_threshold[0x10];
9310
9311 u8 one_ratio_high_mid_threshold[0x10];
9312 u8 one_ratio_low_mid_threshold[0x10];
9313
9314 u8 one_ratio_low_threshold[0x10];
9315 u8 ndeo_error_threshold[0x10];
9316
9317 u8 mixer_offset_step_size[0x10];
b4ff3a36 9318 u8 reserved_at_110[0x8];
e281682b
SM		 9319 u8 mix90_phase_for_voltage_bath[0x8];
9320
9321 u8 mixer_offset_start[0x10];
9322 u8 mixer_offset_end[0x10];
9323
b4ff3a36 9324 u8 reserved_at_140[0x15];
e281682b
SM		 9325 u8 ber_test_time[0xb];
9326};
9327
9328struct mlx5_ifc_pspa_reg_bits {
9329 u8 swid[0x8];
9330 u8 local_port[0x8];
9331 u8 sub_port[0x8];
b4ff3a36 9332 u8 reserved_at_18[0x8];
e281682b 9333
b4ff3a36 9334 u8 reserved_at_20[0x20];
e281682b
SM		 9335};
9336
9337struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 9338 u8 reserved_at_0[0x8];
e281682b 9339 u8 local_port[0x8];
b4ff3a36 9340 u8 reserved_at_10[0x5];
e281682b 9341 u8 prio[0x3];
b4ff3a36 9342 u8 reserved_at_18[0x6];
e281682b
SM		 9343 u8 mode[0x2];
9344
b4ff3a36 9345 u8 reserved_at_20[0x20];
e281682b 9346
b4ff3a36 9347 u8 reserved_at_40[0x10];
e281682b
SM		 9348 u8 min_threshold[0x10];
9349
b4ff3a36 9350 u8 reserved_at_60[0x10];
e281682b
SM		 9351 u8 max_threshold[0x10];
9352
b4ff3a36 9353 u8 reserved_at_80[0x10];
e281682b
SM		 9354 u8 mark_probability_denominator[0x10];
9355
b4ff3a36 9356 u8 reserved_at_a0[0x60];
e281682b
SM		 9357};
9358
9359struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 9360 u8 reserved_at_0[0x8];
e281682b 9361 u8 local_port[0x8];
b4ff3a36 9362 u8 reserved_at_10[0x10];
e281682b 9363
b4ff3a36 9364 u8 reserved_at_20[0x60];
e281682b 9365
b4ff3a36 9366 u8 reserved_at_80[0x1c];
e281682b
SM		 9367 u8 wrps_admin[0x4];
9368
b4ff3a36 9369 u8 reserved_at_a0[0x1c];
e281682b
SM		 9370 u8 wrps_status[0x4];
9371
b4ff3a36 9372 u8 reserved_at_c0[0x8];
e281682b 9373 u8 up_threshold[0x8];
b4ff3a36 9374 u8 reserved_at_d0[0x8];
e281682b
SM		 9375 u8 down_threshold[0x8];
9376
b4ff3a36 9377 u8 reserved_at_e0[0x20];
e281682b 9378
b4ff3a36 9379 u8 reserved_at_100[0x1c];
e281682b
SM		 9380 u8 srps_admin[0x4];
9381
b4ff3a36 9382 u8 reserved_at_120[0x1c];
e281682b
SM		 9383 u8 srps_status[0x4];
9384
b4ff3a36 9385 u8 reserved_at_140[0x40];
e281682b
SM		 9386};
9387
9388struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 9389 u8 reserved_at_0[0x8];
e281682b 9390 u8 local_port[0x8];
b4ff3a36 9391 u8 reserved_at_10[0x10];
e281682b 9392
b4ff3a36 9393 u8 reserved_at_20[0x8];
e281682b 9394 u8 lb_cap[0x8];
b4ff3a36 9395 u8 reserved_at_30[0x8];
e281682b
SM		 9396 u8 lb_en[0x8];
9397};
9398
9399struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 9400 u8 reserved_at_0[0x8];
4b5b9c7d
SA		 9401 u8 local_port[0x8];
9402 u8 reserved_at_10[0x10];
e281682b 9403
4b5b9c7d 9404 u8 reserved_at_20[0x20];
e281682b 9405
4b5b9c7d
SA		 9406 u8 port_profile_mode[0x8];
9407 u8 static_port_profile[0x8];
9408 u8 active_port_profile[0x8];
9409 u8 reserved_at_58[0x8];
e281682b 9410
4b5b9c7d
SA		 9411 u8 retransmission_active[0x8];
9412 u8 fec_mode_active[0x18];
e281682b 9413
4b5b9c7d
SA		 9414 u8 rs_fec_correction_bypass_cap[0x4];
9415 u8 reserved_at_84[0x8];
9416 u8 fec_override_cap_56g[0x4];
9417 u8 fec_override_cap_100g[0x4];
9418 u8 fec_override_cap_50g[0x4];
9419 u8 fec_override_cap_25g[0x4];
9420 u8 fec_override_cap_10g_40g[0x4];
9421
9422 u8 rs_fec_correction_bypass_admin[0x4];
9423 u8 reserved_at_a4[0x8];
9424 u8 fec_override_admin_56g[0x4];
9425 u8 fec_override_admin_100g[0x4];
9426 u8 fec_override_admin_50g[0x4];
9427 u8 fec_override_admin_25g[0x4];
9428 u8 fec_override_admin_10g_40g[0x4];
a58837f5
AL		 9429
9430 u8 fec_override_cap_400g_8x[0x10];
9431 u8 fec_override_cap_200g_4x[0x10];
9432
9433 u8 fec_override_cap_100g_2x[0x10];
9434 u8 fec_override_cap_50g_1x[0x10];
9435
9436 u8 fec_override_admin_400g_8x[0x10];
9437 u8 fec_override_admin_200g_4x[0x10];
9438
9439 u8 fec_override_admin_100g_2x[0x10];
9440 u8 fec_override_admin_50g_1x[0x10];
ce28f0fd
AL		 9441
9442 u8 reserved_at_140[0x140];
e281682b
SM		 9443};
9444
9445struct mlx5_ifc_ppcnt_reg_bits {
9446 u8 swid[0x8];
9447 u8 local_port[0x8];
9448 u8 pnat[0x2];
b4ff3a36 9449 u8 reserved_at_12[0x8];
e281682b
SM		 9450 u8 grp[0x6];
9451
9452 u8 clr[0x1];
b4ff3a36 9453 u8 reserved_at_21[0x1c];
e281682b
SM		 9454 u8 prio_tc[0x3];
9455
9456 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9457};
9458
4039049b
AL		 9459struct mlx5_ifc_mpein_reg_bits {
9460 u8 reserved_at_0[0x2];
9461 u8 depth[0x6];
9462 u8 pcie_index[0x8];
9463 u8 node[0x8];
9464 u8 reserved_at_18[0x8];
9465
9466 u8 capability_mask[0x20];
9467
9468 u8 reserved_at_40[0x8];
9469 u8 link_width_enabled[0x8];
9470 u8 link_speed_enabled[0x10];
9471
9472 u8 lane0_physical_position[0x8];
9473 u8 link_width_active[0x8];
9474 u8 link_speed_active[0x10];
9475
9476 u8 num_of_pfs[0x10];
9477 u8 num_of_vfs[0x10];
9478
9479 u8 bdf0[0x10];
9480 u8 reserved_at_b0[0x10];
9481
9482 u8 max_read_request_size[0x4];
9483 u8 max_payload_size[0x4];
9484 u8 reserved_at_c8[0x5];
9485 u8 pwr_status[0x3];
9486 u8 port_type[0x4];
9487 u8 reserved_at_d4[0xb];
9488 u8 lane_reversal[0x1];
9489
9490 u8 reserved_at_e0[0x14];
9491 u8 pci_power[0xc];
9492
9493 u8 reserved_at_100[0x20];
9494
9495 u8 device_status[0x10];
9496 u8 port_state[0x8];
9497 u8 reserved_at_138[0x8];
9498
9499 u8 reserved_at_140[0x10];
9500 u8 receiver_detect_result[0x10];
9501
9502 u8 reserved_at_160[0x20];
9503};
9504
8ed1a630
GP		 9505struct mlx5_ifc_mpcnt_reg_bits {
9506 u8 reserved_at_0[0x8];
9507 u8 pcie_index[0x8];
9508 u8 reserved_at_10[0xa];
9509 u8 grp[0x6];
9510
9511 u8 clr[0x1];
9512 u8 reserved_at_21[0x1f];
9513
9514 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9515};
9516
e281682b 9517struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 9518 u8 reserved_at_0[0x3];
e281682b 9519 u8 single_mac[0x1];
b4ff3a36 9520 u8 reserved_at_4[0x4];
e281682b
SM		 9521 u8 local_port[0x8];
9522 u8 mac_47_32[0x10];
9523
9524 u8 mac_31_0[0x20];
9525
b4ff3a36 9526 u8 reserved_at_40[0x40];
e281682b
SM		 9527};
9528
9529struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 9530 u8 reserved_at_0[0x8];
e281682b 9531 u8 local_port[0x8];
b4ff3a36 9532 u8 reserved_at_10[0x10];
e281682b
SM		 9533
9534 u8 max_mtu[0x10];
b4ff3a36 9535 u8 reserved_at_30[0x10];
e281682b
SM		 9536
9537 u8 admin_mtu[0x10];
b4ff3a36 9538 u8 reserved_at_50[0x10];
e281682b
SM		 9539
9540 u8 oper_mtu[0x10];
b4ff3a36 9541 u8 reserved_at_70[0x10];
e281682b
SM		 9542};
9543
9544struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 9545 u8 reserved_at_0[0x8];
e281682b 9546 u8 module[0x8];
b4ff3a36 9547 u8 reserved_at_10[0x10];
e281682b 9548
b4ff3a36 9549 u8 reserved_at_20[0x18];
e281682b
SM		 9550 u8 attenuation_5g[0x8];
9551
b4ff3a36 9552 u8 reserved_at_40[0x18];
e281682b
SM		 9553 u8 attenuation_7g[0x8];
9554
b4ff3a36 9555 u8 reserved_at_60[0x18];
e281682b
SM		 9556 u8 attenuation_12g[0x8];
9557};
9558
9559struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 9560 u8 reserved_at_0[0x8];
e281682b 9561 u8 module[0x8];
b4ff3a36 9562 u8 reserved_at_10[0xc];
e281682b
SM		 9563 u8 module_status[0x4];
9564
b4ff3a36 9565 u8 reserved_at_20[0x60];
e281682b
SM		 9566};
9567
9568struct mlx5_ifc_pmpc_reg_bits {
9569 u8 module_state_updated[32][0x8];
9570};
9571
9572struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 9573 u8 reserved_at_0[0x4];
e281682b
SM		 9574 u8 mlpn_status[0x4];
9575 u8 local_port[0x8];
b4ff3a36 9576 u8 reserved_at_10[0x10];
e281682b
SM		 9577
9578 u8 e[0x1];
b4ff3a36 9579 u8 reserved_at_21[0x1f];
e281682b
SM		 9580};
9581
9582struct mlx5_ifc_pmlp_reg_bits {
9583 u8 rxtx[0x1];
b4ff3a36 9584 u8 reserved_at_1[0x7];
e281682b 9585 u8 local_port[0x8];
b4ff3a36 9586 u8 reserved_at_10[0x8];
e281682b
SM		 9587 u8 width[0x8];
9588
9589 u8 lane0_module_mapping[0x20];
9590
9591 u8 lane1_module_mapping[0x20];
9592
9593 u8 lane2_module_mapping[0x20];
9594
9595 u8 lane3_module_mapping[0x20];
9596
b4ff3a36 9597 u8 reserved_at_a0[0x160];
e281682b
SM		 9598};
9599
9600struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 9601 u8 reserved_at_0[0x8];
e281682b 9602 u8 module[0x8];
b4ff3a36 9603 u8 reserved_at_10[0x4];
e281682b 9604 u8 admin_status[0x4];
b4ff3a36 9605 u8 reserved_at_18[0x4];
e281682b
SM		 9606 u8 oper_status[0x4];
9607
9608 u8 ase[0x1];
9609 u8 ee[0x1];
b4ff3a36 9610 u8 reserved_at_22[0x1c];
e281682b
SM		 9611 u8 e[0x2];
9612
b4ff3a36 9613 u8 reserved_at_40[0x40];
e281682b
SM		 9614};
9615
9616struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 9617 u8 reserved_at_0[0x4];
e281682b 9618 u8 profile_id[0xc];
b4ff3a36 9619 u8 reserved_at_10[0x4];
e281682b 9620 u8 proto_mask[0x4];
b4ff3a36 9621 u8 reserved_at_18[0x8];
e281682b 9622
b4ff3a36 9623 u8 reserved_at_20[0x10];
e281682b
SM		 9624 u8 lane_speed[0x10];
9625
b4ff3a36 9626 u8 reserved_at_40[0x17];
e281682b
SM		 9627 u8 lpbf[0x1];
9628 u8 fec_mode_policy[0x8];
9629
9630 u8 retransmission_capability[0x8];
9631 u8 fec_mode_capability[0x18];
9632
9633 u8 retransmission_support_admin[0x8];
9634 u8 fec_mode_support_admin[0x18];
9635
9636 u8 retransmission_request_admin[0x8];
9637 u8 fec_mode_request_admin[0x18];
9638
b4ff3a36 9639 u8 reserved_at_c0[0x80];
e281682b
SM		 9640};
9641
9642struct mlx5_ifc_plib_reg_bits {
b4ff3a36 9643 u8 reserved_at_0[0x8];
e281682b 9644 u8 local_port[0x8];
b4ff3a36 9645 u8 reserved_at_10[0x8];
e281682b
SM		 9646 u8 ib_port[0x8];
9647
b4ff3a36 9648 u8 reserved_at_20[0x60];
e281682b
SM		 9649};
9650
9651struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 9652 u8 reserved_at_0[0x8];
e281682b 9653 u8 local_port[0x8];
b4ff3a36 9654 u8 reserved_at_10[0xd];
e281682b
SM		 9655 u8 lbf_mode[0x3];
9656
b4ff3a36 9657 u8 reserved_at_20[0x20];
e281682b
SM		 9658};
9659
9660struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 9661 u8 reserved_at_0[0x8];
e281682b 9662 u8 local_port[0x8];
b4ff3a36 9663 u8 reserved_at_10[0x10];
e281682b
SM		 9664
9665 u8 dic[0x1];
b4ff3a36 9666 u8 reserved_at_21[0x19];
e281682b 9667 u8 ipg[0x4];
b4ff3a36 9668 u8 reserved_at_3e[0x2];
e281682b
SM		 9669};
9670
9671struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 9672 u8 reserved_at_0[0x8];
e281682b 9673 u8 local_port[0x8];
b4ff3a36 9674 u8 reserved_at_10[0x10];
e281682b 9675
b4ff3a36 9676 u8 reserved_at_20[0xe0];
e281682b
SM		 9677
9678 u8 port_filter[8][0x20];
9679
9680 u8 port_filter_update_en[8][0x20];
9681};
9682
9683struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 9684 u8 reserved_at_0[0x8];
e281682b 9685 u8 local_port[0x8];
2afa609f
IK		 9686 u8 reserved_at_10[0xb];
9687 u8 ppan_mask_n[0x1];
9688 u8 minor_stall_mask[0x1];
9689 u8 critical_stall_mask[0x1];
9690 u8 reserved_at_1e[0x2];
e281682b
SM		 9691
9692 u8 ppan[0x4];
b4ff3a36 9693 u8 reserved_at_24[0x4];
e281682b 9694 u8 prio_mask_tx[0x8];
b4ff3a36 9695 u8 reserved_at_30[0x8];
e281682b
SM		 9696 u8 prio_mask_rx[0x8];
9697
9698 u8 pptx[0x1];
9699 u8 aptx[0x1];
2afa609f
IK		 9700 u8 pptx_mask_n[0x1];
9701 u8 reserved_at_43[0x5];
e281682b 9702 u8 pfctx[0x8];
b4ff3a36 9703 u8 reserved_at_50[0x10];
e281682b
SM		 9704
9705 u8 pprx[0x1];
9706 u8 aprx[0x1];
2afa609f
IK		 9707 u8 pprx_mask_n[0x1];
9708 u8 reserved_at_63[0x5];
e281682b 9709 u8 pfcrx[0x8];
b4ff3a36 9710 u8 reserved_at_70[0x10];
e281682b 9711
2afa609f
IK		 9712 u8 device_stall_minor_watermark[0x10];
9713 u8 device_stall_critical_watermark[0x10];
9714
9715 u8 reserved_at_a0[0x60];
e281682b
SM		 9716};
9717
9718struct mlx5_ifc_pelc_reg_bits {
9719 u8 op[0x4];
b4ff3a36 9720 u8 reserved_at_4[0x4];
e281682b 9721 u8 local_port[0x8];
b4ff3a36 9722 u8 reserved_at_10[0x10];
e281682b
SM		 9723
9724 u8 op_admin[0x8];
9725 u8 op_capability[0x8];
9726 u8 op_request[0x8];
9727 u8 op_active[0x8];
9728
9729 u8 admin[0x40];
9730
9731 u8 capability[0x40];
9732
9733 u8 request[0x40];
9734
9735 u8 active[0x40];
9736
b4ff3a36 9737 u8 reserved_at_140[0x80];
e281682b
SM		 9738};
9739
9740struct mlx5_ifc_peir_reg_bits {
b4ff3a36 9741 u8 reserved_at_0[0x8];
e281682b 9742 u8 local_port[0x8];
b4ff3a36 9743 u8 reserved_at_10[0x10];
e281682b 9744
b4ff3a36 9745 u8 reserved_at_20[0xc];
e281682b 9746 u8 error_count[0x4];
b4ff3a36 9747 u8 reserved_at_30[0x10];
e281682b 9748
b4ff3a36 9749 u8 reserved_at_40[0xc];
e281682b 9750 u8 lane[0x4];
b4ff3a36 9751 u8 reserved_at_50[0x8];
e281682b
SM		 9752 u8 error_type[0x8];
9753};
9754
5e022dd3
EBE		 9755struct mlx5_ifc_mpegc_reg_bits {
9756 u8 reserved_at_0[0x30];
9757 u8 field_select[0x10];
9758
9759 u8 tx_overflow_sense[0x1];
9760 u8 mark_cqe[0x1];
9761 u8 mark_cnp[0x1];
9762 u8 reserved_at_43[0x1b];
9763 u8 tx_lossy_overflow_oper[0x2];
9764
9765 u8 reserved_at_60[0x100];
9766};
9767
ae02d415
EBE		 9768enum {
9769 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
9770 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
9771 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
9772};
9773
9774struct mlx5_ifc_mtutc_reg_bits {
9775 u8 reserved_at_0[0x1c];
9776 u8 operation[0x4];
9777
9778 u8 freq_adjustment[0x20];
9779
9780 u8 reserved_at_40[0x40];
9781
9782 u8 utc_sec[0x20];
9783
9784 u8 reserved_at_a0[0x2];
9785 u8 utc_nsec[0x1e];
9786
9787 u8 time_adjustment[0x20];
9788};
9789
cfdcbcea 9790struct mlx5_ifc_pcam_enhanced_features_bits {
a58837f5
AL		 9791 u8 reserved_at_0[0x68];
9792 u8 fec_50G_per_lane_in_pplm[0x1];
9793 u8 reserved_at_69[0x4];
0af5107c 9794 u8 rx_icrc_encapsulated_counter[0x1];
a0a89989
AL		 9795 u8 reserved_at_6e[0x4];
9796 u8 ptys_extended_ethernet[0x1];
9797 u8 reserved_at_73[0x3];
2fcb12df 9798 u8 pfcc_mask[0x1];
67daf118
SA		 9799 u8 reserved_at_77[0x3];
9800 u8 per_lane_error_counters[0x1];
2dba0797 9801 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 9802 u8 ptys_connector_type[0x1];
9803 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 9804 u8 ppcnt_discard_group[0x1];
9805 u8 ppcnt_statistical_group[0x1];
9806};
9807
df5f1361
HN		 9808struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9809 u8 port_access_reg_cap_mask_127_to_96[0x20];
9810 u8 port_access_reg_cap_mask_95_to_64[0x20];
4b5b9c7d
SA		 9811
9812 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9813 u8 pplm[0x1];
9814 u8 port_access_reg_cap_mask_34_to_32[0x3];
df5f1361
HN		 9815
9816 u8 port_access_reg_cap_mask_31_to_13[0x13];
9817 u8 pbmc[0x1];
9818 u8 pptb[0x1];
75370eb0
ED		 9819 u8 port_access_reg_cap_mask_10_to_09[0x2];
9820 u8 ppcnt[0x1];
9821 u8 port_access_reg_cap_mask_07_to_00[0x8];
df5f1361
HN		 9822};
9823
cfdcbcea
GP		 9824struct mlx5_ifc_pcam_reg_bits {
9825 u8 reserved_at_0[0x8];
9826 u8 feature_group[0x8];
9827 u8 reserved_at_10[0x8];
9828 u8 access_reg_group[0x8];
9829
9830 u8 reserved_at_20[0x20];
9831
9832 union {
df5f1361 9833 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
cfdcbcea
GP		 9834 u8 reserved_at_0[0x80];
9835 } port_access_reg_cap_mask;
9836
9837 u8 reserved_at_c0[0x80];
9838
9839 union {
9840 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9841 u8 reserved_at_0[0x80];
9842 } feature_cap_mask;
9843
9844 u8 reserved_at_1c0[0xc0];
9845};
9846
9847struct mlx5_ifc_mcam_enhanced_features_bits {
271907ee
GP		 9848 u8 reserved_at_0[0x5d];
9849 u8 mcia_32dwords[0x1];
976a859c
AL		 9850 u8 out_pulse_duration_ns[0x1];
9851 u8 npps_period[0x1];
9852 u8 reserved_at_60[0xa];
72fb3b60 9853 u8 reset_state[0x1];
ae02d415
EBE		 9854 u8 ptpcyc2realtime_modify[0x1];
9855 u8 reserved_at_6c[0x2];
4039049b
AL		 9856 u8 pci_status_and_power[0x1];
9857 u8 reserved_at_6f[0x5];
5e022dd3
EBE		 9858 u8 mark_tx_action_cnp[0x1];
9859 u8 mark_tx_action_cqe[0x1];
9860 u8 dynamic_tx_overflow[0x1];
9861 u8 reserved_at_77[0x4];
5405fa26 9862 u8 pcie_outbound_stalled[0x1];
efae7f78 9863 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 9864 u8 mtpps_enh_out_per_adj[0x1];
9865 u8 mtpps_fs[0x1];
cfdcbcea
GP		 9866 u8 pcie_performance_group[0x1];
9867};
9868
0ab87743
OG		 9869struct mlx5_ifc_mcam_access_reg_bits {
9870 u8 reserved_at_0[0x1c];
9871 u8 mcda[0x1];
9872 u8 mcc[0x1];
9873 u8 mcqi[0x1];
a82e0b5b 9874 u8 mcqs[0x1];
0ab87743 9875
5e022dd3
EBE		 9876 u8 regs_95_to_87[0x9];
9877 u8 mpegc[0x1];
ae02d415
EBE		 9878 u8 mtutc[0x1];
9879 u8 regs_84_to_68[0x11];
eff8ea8f
FD		 9880 u8 tracer_registers[0x4];
9881
502e82b9
AL		 9882 u8 regs_63_to_46[0x12];
9883 u8 mrtc[0x1];
9884 u8 regs_44_to_32[0xd];
9885
0ab87743
OG		 9886 u8 regs_31_to_0[0x20];
9887};
9888
f397464e
EBE		 9889struct mlx5_ifc_mcam_access_reg_bits1 {
9890 u8 regs_127_to_96[0x20];
9891
9892 u8 regs_95_to_64[0x20];
9893
9894 u8 regs_63_to_32[0x20];
9895
9896 u8 regs_31_to_0[0x20];
9897};
9898
9899struct mlx5_ifc_mcam_access_reg_bits2 {
9900 u8 regs_127_to_99[0x1d];
9901 u8 mirc[0x1];
9902 u8 regs_97_to_96[0x2];
9903
9904 u8 regs_95_to_64[0x20];
9905
9906 u8 regs_63_to_32[0x20];
9907
9908 u8 regs_31_to_0[0x20];
9909};
9910
cfdcbcea
GP		 9911struct mlx5_ifc_mcam_reg_bits {
9912 u8 reserved_at_0[0x8];
9913 u8 feature_group[0x8];
9914 u8 reserved_at_10[0x8];
9915 u8 access_reg_group[0x8];
9916
9917 u8 reserved_at_20[0x20];
9918
9919 union {
0ab87743 9920 struct mlx5_ifc_mcam_access_reg_bits access_regs;
f397464e
EBE		 9921 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9922 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
cfdcbcea
GP		 9923 u8 reserved_at_0[0x80];
9924 } mng_access_reg_cap_mask;
9925
9926 u8 reserved_at_c0[0x80];
9927
9928 union {
9929 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9930 u8 reserved_at_0[0x80];
9931 } mng_feature_cap_mask;
9932
9933 u8 reserved_at_1c0[0x80];
9934};
9935
c02762eb
HN		 9936struct mlx5_ifc_qcam_access_reg_cap_mask {
9937 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9938 u8 qpdpm[0x1];
9939 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9940 u8 qdpm[0x1];
9941 u8 qpts[0x1];
9942 u8 qcap[0x1];
9943 u8 qcam_access_reg_cap_mask_0[0x1];
9944};
9945
9946struct mlx5_ifc_qcam_qos_feature_cap_mask {
9947 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9948 u8 qpts_trust_both[0x1];
9949};
9950
9951struct mlx5_ifc_qcam_reg_bits {
9952 u8 reserved_at_0[0x8];
9953 u8 feature_group[0x8];
9954 u8 reserved_at_10[0x8];
9955 u8 access_reg_group[0x8];
9956 u8 reserved_at_20[0x20];
9957
9958 union {
9959 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9960 u8 reserved_at_0[0x80];
9961 } qos_access_reg_cap_mask;
9962
9963 u8 reserved_at_c0[0x80];
9964
9965 union {
9966 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9967 u8 reserved_at_0[0x80];
9968 } qos_feature_cap_mask;
9969
9970 u8 reserved_at_1c0[0x80];
9971};
9972
0b9055a1
MS		 9973struct mlx5_ifc_core_dump_reg_bits {
9974 u8 reserved_at_0[0x18];
9975 u8 core_dump_type[0x8];
9976
9977 u8 reserved_at_20[0x30];
9978 u8 vhca_id[0x10];
9979
9980 u8 reserved_at_60[0x8];
9981 u8 qpn[0x18];
9982 u8 reserved_at_80[0x180];
9983};
9984
e281682b 9985struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 9986 u8 reserved_at_0[0x8];
e281682b 9987 u8 local_port[0x8];
b4ff3a36 9988 u8 reserved_at_10[0x10];
e281682b
SM		 9989
9990 u8 port_capability_mask[4][0x20];
9991};
9992
9993struct mlx5_ifc_paos_reg_bits {
9994 u8 swid[0x8];
9995 u8 local_port[0x8];
b4ff3a36 9996 u8 reserved_at_10[0x4];
e281682b 9997 u8 admin_status[0x4];
b4ff3a36 9998 u8 reserved_at_18[0x4];
e281682b
SM		 9999 u8 oper_status[0x4];
10000
10001 u8 ase[0x1];
10002 u8 ee[0x1];
b4ff3a36 10003 u8 reserved_at_22[0x1c];
e281682b
SM		 10004 u8 e[0x2];
10005
b4ff3a36 10006 u8 reserved_at_40[0x40];
e281682b
SM		 10007};
10008
10009struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 10010 u8 reserved_at_0[0x8];
e281682b 10011 u8 opamp_group[0x8];
b4ff3a36 10012 u8 reserved_at_10[0xc];
e281682b
SM		 10013 u8 opamp_group_type[0x4];
10014
10015 u8 start_index[0x10];
b4ff3a36 10016 u8 reserved_at_30[0x4];
e281682b
SM		 10017 u8 num_of_indices[0xc];
10018
10019 u8 index_data[18][0x10];
10020};
10021
7d5e1423
SM		 10022struct mlx5_ifc_pcmr_reg_bits {
10023 u8 reserved_at_0[0x8];
10024 u8 local_port[0x8];
0dcaafc0 10025 u8 reserved_at_10[0x10];
0bc73ad4 10026
0dcaafc0
EB		 10027 u8 entropy_force_cap[0x1];
10028 u8 entropy_calc_cap[0x1];
10029 u8 entropy_gre_calc_cap[0x1];
0bc73ad4
AL		 10030 u8 reserved_at_23[0xf];
10031 u8 rx_ts_over_crc_cap[0x1];
10032 u8 reserved_at_33[0xb];
7d5e1423 10033 u8 fcs_cap[0x1];
0dcaafc0 10034 u8 reserved_at_3f[0x1];
0bc73ad4 10035
0dcaafc0
EB		 10036 u8 entropy_force[0x1];
10037 u8 entropy_calc[0x1];
10038 u8 entropy_gre_calc[0x1];
0bc73ad4
AL		 10039 u8 reserved_at_43[0xf];
10040 u8 rx_ts_over_crc[0x1];
10041 u8 reserved_at_53[0xb];
7d5e1423
SM		 10042 u8 fcs_chk[0x1];
10043 u8 reserved_at_5f[0x1];
10044};
10045
e281682b 10046struct mlx5_ifc_lane_2_module_mapping_bits {
fcb610a8
GP		 10047 u8 reserved_at_0[0x4];
10048 u8 rx_lane[0x4];
10049 u8 reserved_at_8[0x4];
10050 u8 tx_lane[0x4];
b4ff3a36 10051 u8 reserved_at_10[0x8];
e281682b
SM		 10052 u8 module[0x8];
10053};
10054
10055struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 10056 u8 reserved_at_0[0x6];
e281682b
SM		 10057 u8 lossy[0x1];
10058 u8 epsb[0x1];
ac77998b
MK		 10059 u8 reserved_at_8[0x8];
10060 u8 size[0x10];
e281682b
SM		 10061
10062 u8 xoff_threshold[0x10];
10063 u8 xon_threshold[0x10];
10064};
10065
10066struct mlx5_ifc_set_node_in_bits {
10067 u8 node_description[64][0x8];
10068};
10069
10070struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 10071 u8 reserved_at_0[0x18];
e281682b
SM		 10072 u8 power_settings_level[0x8];
10073
b4ff3a36 10074 u8 reserved_at_20[0x60];
e281682b
SM		 10075};
10076
10077struct mlx5_ifc_register_host_endianness_bits {
10078 u8 he[0x1];
b4ff3a36 10079 u8 reserved_at_1[0x1f];
e281682b 10080
b4ff3a36 10081 u8 reserved_at_20[0x60];
e281682b
SM		 10082};
10083
10084struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 10085 u8 reserved_at_0[0x20];
e281682b
SM		 10086
10087 u8 mkey[0x20];
10088
10089 u8 addressh_63_32[0x20];
10090
10091 u8 addressl_31_0[0x20];
10092};
10093
10094struct mlx5_ifc_ud_adrs_vector_bits {
10095 u8 dc_key[0x40];
10096
10097 u8 ext[0x1];
b4ff3a36 10098 u8 reserved_at_41[0x7];
e281682b
SM		 10099 u8 destination_qp_dct[0x18];
10100
10101 u8 static_rate[0x4];
10102 u8 sl_eth_prio[0x4];
10103 u8 fl[0x1];
10104 u8 mlid[0x7];
10105 u8 rlid_udp_sport[0x10];
10106
b4ff3a36 10107 u8 reserved_at_80[0x20];
e281682b
SM		 10108
10109 u8 rmac_47_16[0x20];
10110
10111 u8 rmac_15_0[0x10];
10112 u8 tclass[0x8];
10113 u8 hop_limit[0x8];
10114
b4ff3a36 10115 u8 reserved_at_e0[0x1];
e281682b 10116 u8 grh[0x1];
b4ff3a36 10117 u8 reserved_at_e2[0x2];
e281682b
SM		 10118 u8 src_addr_index[0x8];
10119 u8 flow_label[0x14];
10120
10121 u8 rgid_rip[16][0x8];
10122};
10123
10124struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 10125 u8 reserved_at_0[0x10];
e281682b
SM		 10126 u8 function_id[0x10];
10127
10128 u8 num_pages[0x20];
10129
b4ff3a36 10130 u8 reserved_at_40[0xa0];
e281682b
SM		 10131};
10132
10133struct mlx5_ifc_eqe_bits {
b4ff3a36 10134 u8 reserved_at_0[0x8];
e281682b 10135 u8 event_type[0x8];
b4ff3a36 10136 u8 reserved_at_10[0x8];
e281682b
SM		 10137 u8 event_sub_type[0x8];
10138
b4ff3a36 10139 u8 reserved_at_20[0xe0];
e281682b
SM		 10140
10141 union mlx5_ifc_event_auto_bits event_data;
10142
b4ff3a36 10143 u8 reserved_at_1e0[0x10];
e281682b 10144 u8 signature[0x8];
b4ff3a36 10145 u8 reserved_at_1f8[0x7];
e281682b
SM		 10146 u8 owner[0x1];
10147};
10148
10149enum {
10150 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10151};
10152
10153struct mlx5_ifc_cmd_queue_entry_bits {
10154 u8 type[0x8];
b4ff3a36 10155 u8 reserved_at_8[0x18];
e281682b
SM		 10156
10157 u8 input_length[0x20];
10158
10159 u8 input_mailbox_pointer_63_32[0x20];
10160
10161 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 10162 u8 reserved_at_77[0x9];
e281682b
SM		 10163
10164 u8 command_input_inline_data[16][0x8];
10165
10166 u8 command_output_inline_data[16][0x8];
10167
10168 u8 output_mailbox_pointer_63_32[0x20];
10169
10170 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 10171 u8 reserved_at_1b7[0x9];
e281682b
SM		 10172
10173 u8 output_length[0x20];
10174
10175 u8 token[0x8];
10176 u8 signature[0x8];
b4ff3a36 10177 u8 reserved_at_1f0[0x8];
e281682b
SM		 10178 u8 status[0x7];
10179 u8 ownership[0x1];
10180};
10181
10182struct mlx5_ifc_cmd_out_bits {
10183 u8 status[0x8];
b4ff3a36 10184 u8 reserved_at_8[0x18];
e281682b
SM		 10185
10186 u8 syndrome[0x20];
10187
10188 u8 command_output[0x20];
10189};
10190
10191struct mlx5_ifc_cmd_in_bits {
10192 u8 opcode[0x10];
b4ff3a36 10193 u8 reserved_at_10[0x10];
e281682b 10194
b4ff3a36 10195 u8 reserved_at_20[0x10];
e281682b
SM		 10196 u8 op_mod[0x10];
10197
b6ca09cb 10198 u8 command[][0x20];
e281682b
SM		 10199};
10200
10201struct mlx5_ifc_cmd_if_box_bits {
10202 u8 mailbox_data[512][0x8];
10203
b4ff3a36 10204 u8 reserved_at_1000[0x180];
e281682b
SM		 10205
10206 u8 next_pointer_63_32[0x20];
10207
10208 u8 next_pointer_31_10[0x16];
b4ff3a36 10209 u8 reserved_at_11b6[0xa];
e281682b
SM		 10210
10211 u8 block_number[0x20];
10212
b4ff3a36 10213 u8 reserved_at_11e0[0x8];
e281682b
SM		 10214 u8 token[0x8];
10215 u8 ctrl_signature[0x8];
10216 u8 signature[0x8];
10217};
10218
10219struct mlx5_ifc_mtt_bits {
10220 u8 ptag_63_32[0x20];
10221
10222 u8 ptag_31_8[0x18];
b4ff3a36 10223 u8 reserved_at_38[0x6];
e281682b
SM		 10224 u8 wr_en[0x1];
10225 u8 rd_en[0x1];
10226};
10227
928cfe87
TT		 10228struct mlx5_ifc_query_wol_rol_out_bits {
10229 u8 status[0x8];
10230 u8 reserved_at_8[0x18];
10231
10232 u8 syndrome[0x20];
10233
10234 u8 reserved_at_40[0x10];
10235 u8 rol_mode[0x8];
10236 u8 wol_mode[0x8];
10237
10238 u8 reserved_at_60[0x20];
10239};
10240
10241struct mlx5_ifc_query_wol_rol_in_bits {
10242 u8 opcode[0x10];
10243 u8 reserved_at_10[0x10];
10244
10245 u8 reserved_at_20[0x10];
10246 u8 op_mod[0x10];
10247
10248 u8 reserved_at_40[0x40];
10249};
10250
10251struct mlx5_ifc_set_wol_rol_out_bits {
10252 u8 status[0x8];
10253 u8 reserved_at_8[0x18];
10254
10255 u8 syndrome[0x20];
10256
10257 u8 reserved_at_40[0x40];
10258};
10259
10260struct mlx5_ifc_set_wol_rol_in_bits {
10261 u8 opcode[0x10];
10262 u8 reserved_at_10[0x10];
10263
10264 u8 reserved_at_20[0x10];
10265 u8 op_mod[0x10];
10266
10267 u8 rol_mode_valid[0x1];
10268 u8 wol_mode_valid[0x1];
10269 u8 reserved_at_42[0xe];
10270 u8 rol_mode[0x8];
10271 u8 wol_mode[0x8];
10272
10273 u8 reserved_at_60[0x20];
10274};
10275
e281682b
SM		 10276enum {
10277 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10278 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10279 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10280};
10281
10282enum {
10283 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10284 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10285 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10286};
10287
10288enum {
10289 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10290 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10291 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10292 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10293 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10294 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10295 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10296 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10297 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10298 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10299 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10300};
10301
10302struct mlx5_ifc_initial_seg_bits {
10303 u8 fw_rev_minor[0x10];
10304 u8 fw_rev_major[0x10];
10305
10306 u8 cmd_interface_rev[0x10];
10307 u8 fw_rev_subminor[0x10];
10308
b4ff3a36 10309 u8 reserved_at_40[0x40];
e281682b
SM		 10310
10311 u8 cmdq_phy_addr_63_32[0x20];
10312
10313 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 10314 u8 reserved_at_b4[0x2];
e281682b
SM		 10315 u8 nic_interface[0x2];
10316 u8 log_cmdq_size[0x4];
10317 u8 log_cmdq_stride[0x4];
10318
10319 u8 command_doorbell_vector[0x20];
10320
b4ff3a36 10321 u8 reserved_at_e0[0xf00];
e281682b
SM		 10322
10323 u8 initializing[0x1];
b4ff3a36 10324 u8 reserved_at_fe1[0x4];
e281682b 10325 u8 nic_interface_supported[0x3];
591905ba
BW		 10326 u8 embedded_cpu[0x1];
10327 u8 reserved_at_fe9[0x17];
e281682b
SM		 10328
10329 struct mlx5_ifc_health_buffer_bits health_buffer;
10330
10331 u8 no_dram_nic_offset[0x20];
10332
b4ff3a36 10333 u8 reserved_at_1220[0x6e40];
e281682b 10334
b4ff3a36 10335 u8 reserved_at_8060[0x1f];
e281682b
SM		 10336 u8 clear_int[0x1];
10337
10338 u8 health_syndrome[0x8];
10339 u8 health_counter[0x18];
10340
b4ff3a36 10341 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 10342};
10343
f9a1ef72
EE		 10344struct mlx5_ifc_mtpps_reg_bits {
10345 u8 reserved_at_0[0xc];
10346 u8 cap_number_of_pps_pins[0x4];
10347 u8 reserved_at_10[0x4];
10348 u8 cap_max_num_of_pps_in_pins[0x4];
10349 u8 reserved_at_18[0x4];
10350 u8 cap_max_num_of_pps_out_pins[0x4];
10351
976a859c
AL		 10352 u8 reserved_at_20[0x13];
10353 u8 cap_log_min_npps_period[0x5];
10354 u8 reserved_at_38[0x3];
10355 u8 cap_log_min_out_pulse_duration_ns[0x5];
10356
10357 u8 reserved_at_40[0x4];
f9a1ef72
EE		 10358 u8 cap_pin_3_mode[0x4];
10359 u8 reserved_at_48[0x4];
10360 u8 cap_pin_2_mode[0x4];
10361 u8 reserved_at_50[0x4];
10362 u8 cap_pin_1_mode[0x4];
10363 u8 reserved_at_58[0x4];
10364 u8 cap_pin_0_mode[0x4];
10365
10366 u8 reserved_at_60[0x4];
10367 u8 cap_pin_7_mode[0x4];
10368 u8 reserved_at_68[0x4];
10369 u8 cap_pin_6_mode[0x4];
10370 u8 reserved_at_70[0x4];
10371 u8 cap_pin_5_mode[0x4];
10372 u8 reserved_at_78[0x4];
10373 u8 cap_pin_4_mode[0x4];
10374
fa367688 10375 u8 field_select[0x20];
976a859c
AL		 10376 u8 reserved_at_a0[0x20];
10377
10378 u8 npps_period[0x40];
f9a1ef72
EE		 10379
10380 u8 enable[0x1];
10381 u8 reserved_at_101[0xb];
10382 u8 pattern[0x4];
10383 u8 reserved_at_110[0x4];
10384 u8 pin_mode[0x4];
10385 u8 pin[0x8];
10386
976a859c
AL		 10387 u8 reserved_at_120[0x2];
10388 u8 out_pulse_duration_ns[0x1e];
f9a1ef72
EE		 10389
10390 u8 time_stamp[0x40];
10391
10392 u8 out_pulse_duration[0x10];
10393 u8 out_periodic_adjustment[0x10];
fa367688 10394 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 10395
fa367688 10396 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 10397};
10398
10399struct mlx5_ifc_mtppse_reg_bits {
10400 u8 reserved_at_0[0x18];
10401 u8 pin[0x8];
10402 u8 event_arm[0x1];
10403 u8 reserved_at_21[0x1b];
10404 u8 event_generation_mode[0x4];
10405 u8 reserved_at_40[0x40];
10406};
10407
a82e0b5b
SA		 10408struct mlx5_ifc_mcqs_reg_bits {
10409 u8 last_index_flag[0x1];
10410 u8 reserved_at_1[0x7];
10411 u8 fw_device[0x8];
10412 u8 component_index[0x10];
10413
10414 u8 reserved_at_20[0x10];
10415 u8 identifier[0x10];
10416
10417 u8 reserved_at_40[0x17];
10418 u8 component_status[0x5];
10419 u8 component_update_state[0x4];
10420
10421 u8 last_update_state_changer_type[0x4];
10422 u8 last_update_state_changer_host_id[0x4];
10423 u8 reserved_at_68[0x18];
10424};
10425
47176289
OG		 10426struct mlx5_ifc_mcqi_cap_bits {
10427 u8 supported_info_bitmask[0x20];
10428
10429 u8 component_size[0x20];
10430
10431 u8 max_component_size[0x20];
10432
10433 u8 log_mcda_word_size[0x4];
10434 u8 reserved_at_64[0xc];
10435 u8 mcda_max_write_size[0x10];
10436
10437 u8 rd_en[0x1];
10438 u8 reserved_at_81[0x1];
10439 u8 match_chip_id[0x1];
10440 u8 match_psid[0x1];
10441 u8 check_user_timestamp[0x1];
10442 u8 match_base_guid_mac[0x1];
10443 u8 reserved_at_86[0x1a];
10444};
10445
a82e0b5b
SA		 10446struct mlx5_ifc_mcqi_version_bits {
10447 u8 reserved_at_0[0x2];
10448 u8 build_time_valid[0x1];
10449 u8 user_defined_time_valid[0x1];
10450 u8 reserved_at_4[0x14];
10451 u8 version_string_length[0x8];
10452
10453 u8 version[0x20];
10454
10455 u8 build_time[0x40];
10456
10457 u8 user_defined_time[0x40];
10458
10459 u8 build_tool_version[0x20];
10460
10461 u8 reserved_at_e0[0x20];
10462
10463 u8 version_string[92][0x8];
10464};
10465
10466struct mlx5_ifc_mcqi_activation_method_bits {
10467 u8 pending_server_ac_power_cycle[0x1];
10468 u8 pending_server_dc_power_cycle[0x1];
10469 u8 pending_server_reboot[0x1];
10470 u8 pending_fw_reset[0x1];
10471 u8 auto_activate[0x1];
10472 u8 all_hosts_sync[0x1];
10473 u8 device_hw_reset[0x1];
10474 u8 reserved_at_7[0x19];
10475};
10476
10477union mlx5_ifc_mcqi_reg_data_bits {
10478 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
10479 struct mlx5_ifc_mcqi_version_bits mcqi_version;
10480 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10481};
10482
47176289
OG		 10483struct mlx5_ifc_mcqi_reg_bits {
10484 u8 read_pending_component[0x1];
10485 u8 reserved_at_1[0xf];
10486 u8 component_index[0x10];
10487
10488 u8 reserved_at_20[0x20];
10489
10490 u8 reserved_at_40[0x1b];
10491 u8 info_type[0x5];
10492
10493 u8 info_size[0x20];
10494
10495 u8 offset[0x20];
10496
10497 u8 reserved_at_a0[0x10];
10498 u8 data_size[0x10];
10499
b6ca09cb 10500 union mlx5_ifc_mcqi_reg_data_bits data[];
47176289
OG		 10501};
10502
10503struct mlx5_ifc_mcc_reg_bits {
10504 u8 reserved_at_0[0x4];
10505 u8 time_elapsed_since_last_cmd[0xc];
10506 u8 reserved_at_10[0x8];
10507 u8 instruction[0x8];
10508
10509 u8 reserved_at_20[0x10];
10510 u8 component_index[0x10];
10511
10512 u8 reserved_at_40[0x8];
10513 u8 update_handle[0x18];
10514
10515 u8 handle_owner_type[0x4];
10516 u8 handle_owner_host_id[0x4];
10517 u8 reserved_at_68[0x1];
10518 u8 control_progress[0x7];
10519 u8 error_code[0x8];
10520 u8 reserved_at_78[0x4];
10521 u8 control_state[0x4];
10522
10523 u8 component_size[0x20];
10524
10525 u8 reserved_at_a0[0x60];
10526};
10527
10528struct mlx5_ifc_mcda_reg_bits {
10529 u8 reserved_at_0[0x8];
10530 u8 update_handle[0x18];
10531
10532 u8 offset[0x20];
10533
10534 u8 reserved_at_40[0x10];
10535 u8 size[0x10];
10536
10537 u8 reserved_at_60[0x20];
10538
29056207 10539 u8 data[][0x20];
47176289
OG		 10540};
10541
72fb3b60
MS		 10542enum {
10543 MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10544 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10545 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10546 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10547 MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10548};
10549
06939536
MS		 10550enum {
10551 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10552 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10553};
10554
10555enum {
10556 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10557 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10558 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10559};
10560
10561struct mlx5_ifc_mfrl_reg_bits {
10562 u8 reserved_at_0[0x20];
10563
10564 u8 reserved_at_20[0x2];
10565 u8 pci_sync_for_fw_update_start[0x1];
10566 u8 pci_sync_for_fw_update_resp[0x2];
10567 u8 rst_type_sel[0x3];
72fb3b60
MS		 10568 u8 reserved_at_28[0x4];
10569 u8 reset_state[0x4];
06939536
MS		 10570 u8 reset_type[0x8];
10571 u8 reset_level[0x8];
10572};
10573
bab58ba1
EBE		 10574struct mlx5_ifc_mirc_reg_bits {
10575 u8 reserved_at_0[0x18];
10576 u8 status_code[0x8];
10577
10578 u8 reserved_at_20[0x20];
10579};
10580
36830159
MT		 10581struct mlx5_ifc_pddr_monitor_opcode_bits {
10582 u8 reserved_at_0[0x10];
10583 u8 monitor_opcode[0x10];
10584};
10585
10586union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10587 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10588 u8 reserved_at_0[0x20];
10589};
10590
10591enum {
10592 /* Monitor opcodes */
10593 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10594};
10595
10596struct mlx5_ifc_pddr_troubleshooting_page_bits {
10597 u8 reserved_at_0[0x10];
10598 u8 group_opcode[0x10];
10599
10600 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10601
10602 u8 reserved_at_40[0x20];
10603
10604 u8 status_message[59][0x20];
10605};
10606
10607union mlx5_ifc_pddr_reg_page_data_auto_bits {
10608 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10609 u8 reserved_at_0[0x7c0];
10610};
10611
10612enum {
10613 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
10614};
10615
10616struct mlx5_ifc_pddr_reg_bits {
10617 u8 reserved_at_0[0x8];
10618 u8 local_port[0x8];
10619 u8 pnat[0x2];
10620 u8 reserved_at_12[0xe];
10621
10622 u8 reserved_at_20[0x18];
10623 u8 page_select[0x8];
10624
10625 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10626};
10627
5a1023de
AL		 10628struct mlx5_ifc_mrtc_reg_bits {
10629 u8 time_synced[0x1];
10630 u8 reserved_at_1[0x1f];
10631
10632 u8 reserved_at_20[0x20];
10633
10634 u8 time_h[0x20];
10635
10636 u8 time_l[0x20];
10637};
10638
e281682b
SM		 10639union mlx5_ifc_ports_control_registers_document_bits {
10640 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10641 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10642 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10643 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10644 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10645 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10646 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
948d3f90
AL		 10647 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10648 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
e281682b
SM		 10649 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10650 struct mlx5_ifc_pamp_reg_bits pamp_reg;
10651 struct mlx5_ifc_paos_reg_bits paos_reg;
10652 struct mlx5_ifc_pcap_reg_bits pcap_reg;
36830159
MT		 10653 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10654 struct mlx5_ifc_pddr_reg_bits pddr_reg;
10655 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
e281682b
SM		 10656 struct mlx5_ifc_peir_reg_bits peir_reg;
10657 struct mlx5_ifc_pelc_reg_bits pelc_reg;
10658 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 10659 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 10660 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10661 struct mlx5_ifc_pifr_reg_bits pifr_reg;
10662 struct mlx5_ifc_pipg_reg_bits pipg_reg;
10663 struct mlx5_ifc_plbf_reg_bits plbf_reg;
10664 struct mlx5_ifc_plib_reg_bits plib_reg;
10665 struct mlx5_ifc_plpc_reg_bits plpc_reg;
10666 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10667 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10668 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10669 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10670 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10671 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10672 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10673 struct mlx5_ifc_ppad_reg_bits ppad_reg;
10674 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
4039049b 10675 struct mlx5_ifc_mpein_reg_bits mpein_reg;
8ed1a630 10676 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 10677 struct mlx5_ifc_pplm_reg_bits pplm_reg;
10678 struct mlx5_ifc_pplr_reg_bits pplr_reg;
10679 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10680 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10681 struct mlx5_ifc_pspa_reg_bits pspa_reg;
10682 struct mlx5_ifc_ptas_reg_bits ptas_reg;
10683 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 10684 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 10685 struct mlx5_ifc_pude_reg_bits pude_reg;
10686 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10687 struct mlx5_ifc_slrg_reg_bits slrg_reg;
10688 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 10689 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10690 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 10691 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 10692 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10693 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 10694 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10695 struct mlx5_ifc_mcc_reg_bits mcc_reg;
10696 struct mlx5_ifc_mcda_reg_bits mcda_reg;
bab58ba1 10697 struct mlx5_ifc_mirc_reg_bits mirc_reg;
06939536 10698 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
ae02d415 10699 struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
5a1023de 10700 struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
b4ff3a36 10701 u8 reserved_at_0[0x60e0];
e281682b
SM		 10702};
10703
10704union mlx5_ifc_debug_enhancements_document_bits {
10705 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 10706 u8 reserved_at_0[0x200];
e281682b
SM		 10707};
10708
10709union mlx5_ifc_uplink_pci_interface_document_bits {
10710 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 10711 u8 reserved_at_0[0x20060];
b775516b
EC		 10712};
10713
2cc43b49
MG		 10714struct mlx5_ifc_set_flow_table_root_out_bits {
10715 u8 status[0x8];
b4ff3a36 10716 u8 reserved_at_8[0x18];
2cc43b49
MG		 10717
10718 u8 syndrome[0x20];
10719
b4ff3a36 10720 u8 reserved_at_40[0x40];
2cc43b49
MG		 10721};
10722
10723struct mlx5_ifc_set_flow_table_root_in_bits {
10724 u8 opcode[0x10];
b4ff3a36 10725 u8 reserved_at_10[0x10];
2cc43b49 10726
b4ff3a36 10727 u8 reserved_at_20[0x10];
2cc43b49
MG		 10728 u8 op_mod[0x10];
10729
7d5e1423
SM		 10730 u8 other_vport[0x1];
10731 u8 reserved_at_41[0xf];
10732 u8 vport_number[0x10];
10733
10734 u8 reserved_at_60[0x20];
2cc43b49
MG		 10735
10736 u8 table_type[0x8];
c3e666f1
MB		 10737 u8 reserved_at_88[0x7];
10738 u8 table_of_other_vport[0x1];
10739 u8 table_vport_number[0x10];
2cc43b49 10740
b4ff3a36 10741 u8 reserved_at_a0[0x8];
2cc43b49
MG		 10742 u8 table_id[0x18];
10743
500a3d0d
ES		 10744 u8 reserved_at_c0[0x8];
10745 u8 underlay_qpn[0x18];
c3e666f1
MB		 10746 u8 table_eswitch_owner_vhca_id_valid[0x1];
10747 u8 reserved_at_e1[0xf];
10748 u8 table_eswitch_owner_vhca_id[0x10];
10749 u8 reserved_at_100[0x100];
2cc43b49
MG		 10750};
10751
34a40e68 10752enum {
84df61eb
AH		 10753 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
10754 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 10755};
10756
10757struct mlx5_ifc_modify_flow_table_out_bits {
10758 u8 status[0x8];
b4ff3a36 10759 u8 reserved_at_8[0x18];
34a40e68
MG		 10760
10761 u8 syndrome[0x20];
10762
b4ff3a36 10763 u8 reserved_at_40[0x40];
34a40e68
MG		 10764};
10765
10766struct mlx5_ifc_modify_flow_table_in_bits {
10767 u8 opcode[0x10];
b4ff3a36 10768 u8 reserved_at_10[0x10];
34a40e68 10769
b4ff3a36 10770 u8 reserved_at_20[0x10];
34a40e68
MG		 10771 u8 op_mod[0x10];
10772
7d5e1423
SM		 10773 u8 other_vport[0x1];
10774 u8 reserved_at_41[0xf];
10775 u8 vport_number[0x10];
34a40e68 10776
b4ff3a36 10777 u8 reserved_at_60[0x10];
34a40e68
MG		 10778 u8 modify_field_select[0x10];
10779
10780 u8 table_type[0x8];
b4ff3a36 10781 u8 reserved_at_88[0x18];
34a40e68 10782
b4ff3a36 10783 u8 reserved_at_a0[0x8];
34a40e68
MG		 10784 u8 table_id[0x18];
10785
0c90e9c6 10786 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 10787};
10788
4f3961ee
SM		 10789struct mlx5_ifc_ets_tcn_config_reg_bits {
10790 u8 g[0x1];
10791 u8 b[0x1];
10792 u8 r[0x1];
10793 u8 reserved_at_3[0x9];
10794 u8 group[0x4];
10795 u8 reserved_at_10[0x9];
10796 u8 bw_allocation[0x7];
10797
10798 u8 reserved_at_20[0xc];
10799 u8 max_bw_units[0x4];
10800 u8 reserved_at_30[0x8];
10801 u8 max_bw_value[0x8];
10802};
10803
10804struct mlx5_ifc_ets_global_config_reg_bits {
10805 u8 reserved_at_0[0x2];
10806 u8 r[0x1];
10807 u8 reserved_at_3[0x1d];
10808
10809 u8 reserved_at_20[0xc];
10810 u8 max_bw_units[0x4];
10811 u8 reserved_at_30[0x8];
10812 u8 max_bw_value[0x8];
10813};
10814
10815struct mlx5_ifc_qetc_reg_bits {
10816 u8 reserved_at_0[0x8];
10817 u8 port_number[0x8];
10818 u8 reserved_at_10[0x30];
10819
10820 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10821 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10822};
10823
415a64aa
HN		 10824struct mlx5_ifc_qpdpm_dscp_reg_bits {
10825 u8 e[0x1];
10826 u8 reserved_at_01[0x0b];
10827 u8 prio[0x04];
10828};
10829
10830struct mlx5_ifc_qpdpm_reg_bits {
10831 u8 reserved_at_0[0x8];
10832 u8 local_port[0x8];
10833 u8 reserved_at_10[0x10];
10834 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10835};
10836
10837struct mlx5_ifc_qpts_reg_bits {
10838 u8 reserved_at_0[0x8];
10839 u8 local_port[0x8];
10840 u8 reserved_at_10[0x2d];
10841 u8 trust_state[0x3];
10842};
10843
50b4a3c2
HN		 10844struct mlx5_ifc_pptb_reg_bits {
10845 u8 reserved_at_0[0x2];
10846 u8 mm[0x2];
10847 u8 reserved_at_4[0x4];
10848 u8 local_port[0x8];
10849 u8 reserved_at_10[0x6];
10850 u8 cm[0x1];
10851 u8 um[0x1];
10852 u8 pm[0x8];
10853
10854 u8 prio_x_buff[0x20];
10855
10856 u8 pm_msb[0x8];
10857 u8 reserved_at_48[0x10];
10858 u8 ctrl_buff[0x4];
10859 u8 untagged_buff[0x4];
10860};
10861
88b3d5c9
EBE		 10862struct mlx5_ifc_sbcam_reg_bits {
10863 u8 reserved_at_0[0x8];
10864 u8 feature_group[0x8];
10865 u8 reserved_at_10[0x8];
10866 u8 access_reg_group[0x8];
10867
10868 u8 reserved_at_20[0x20];
10869
10870 u8 sb_access_reg_cap_mask[4][0x20];
10871
10872 u8 reserved_at_c0[0x80];
10873
10874 u8 sb_feature_cap_mask[4][0x20];
10875
10876 u8 reserved_at_1c0[0x40];
10877
10878 u8 cap_total_buffer_size[0x20];
10879
10880 u8 cap_cell_size[0x10];
10881 u8 cap_max_pg_buffers[0x8];
10882 u8 cap_num_pool_supported[0x8];
10883
10884 u8 reserved_at_240[0x8];
10885 u8 cap_sbsr_stat_size[0x8];
10886 u8 cap_max_tclass_data[0x8];
10887 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10888};
10889
50b4a3c2
HN		 10890struct mlx5_ifc_pbmc_reg_bits {
10891 u8 reserved_at_0[0x8];
10892 u8 local_port[0x8];
10893 u8 reserved_at_10[0x10];
10894
10895 u8 xoff_timer_value[0x10];
10896 u8 xoff_refresh[0x10];
10897
10898 u8 reserved_at_40[0x9];
10899 u8 fullness_threshold[0x7];
10900 u8 port_buffer_size[0x10];
10901
10902 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10903
534b1204 10904 u8 reserved_at_2e0[0x80];
50b4a3c2
HN		 10905};
10906
4f3961ee
SM		 10907struct mlx5_ifc_qtct_reg_bits {
10908 u8 reserved_at_0[0x8];
10909 u8 port_number[0x8];
10910 u8 reserved_at_10[0xd];
10911 u8 prio[0x3];
10912
10913 u8 reserved_at_20[0x1d];
10914 u8 tclass[0x3];
10915};
10916
7d5e1423
SM		 10917struct mlx5_ifc_mcia_reg_bits {
10918 u8 l[0x1];
10919 u8 reserved_at_1[0x7];
10920 u8 module[0x8];
10921 u8 reserved_at_10[0x8];
10922 u8 status[0x8];
10923
10924 u8 i2c_device_address[0x8];
10925 u8 page_number[0x8];
10926 u8 device_address[0x10];
10927
10928 u8 reserved_at_40[0x10];
10929 u8 size[0x10];
10930
10931 u8 reserved_at_60[0x20];
10932
10933 u8 dword_0[0x20];
10934 u8 dword_1[0x20];
10935 u8 dword_2[0x20];
10936 u8 dword_3[0x20];
10937 u8 dword_4[0x20];
10938 u8 dword_5[0x20];
10939 u8 dword_6[0x20];
10940 u8 dword_7[0x20];
10941 u8 dword_8[0x20];
10942 u8 dword_9[0x20];
10943 u8 dword_10[0x20];
10944 u8 dword_11[0x20];
10945};
10946
7486216b
SM		 10947struct mlx5_ifc_dcbx_param_bits {
10948 u8 dcbx_cee_cap[0x1];
10949 u8 dcbx_ieee_cap[0x1];
10950 u8 dcbx_standby_cap[0x1];
c74d90c1 10951 u8 reserved_at_3[0x5];
7486216b
SM		 10952 u8 port_number[0x8];
10953 u8 reserved_at_10[0xa];
10954 u8 max_application_table_size[6];
10955 u8 reserved_at_20[0x15];
10956 u8 version_oper[0x3];
10957 u8 reserved_at_38[5];
10958 u8 version_admin[0x3];
10959 u8 willing_admin[0x1];
10960 u8 reserved_at_41[0x3];
10961 u8 pfc_cap_oper[0x4];
10962 u8 reserved_at_48[0x4];
10963 u8 pfc_cap_admin[0x4];
10964 u8 reserved_at_50[0x4];
10965 u8 num_of_tc_oper[0x4];
10966 u8 reserved_at_58[0x4];
10967 u8 num_of_tc_admin[0x4];
10968 u8 remote_willing[0x1];
10969 u8 reserved_at_61[3];
10970 u8 remote_pfc_cap[4];
10971 u8 reserved_at_68[0x14];
10972 u8 remote_num_of_tc[0x4];
10973 u8 reserved_at_80[0x18];
10974 u8 error[0x8];
10975 u8 reserved_at_a0[0x160];
10976};
84df61eb 10977
425a563a
MG		 10978enum {
10979 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
94db3317
EC		 10980 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
10981 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
425a563a
MG		 10982};
10983
84df61eb 10984struct mlx5_ifc_lagc_bits {
c3e666f1 10985 u8 fdb_selection_mode[0x1];
425a563a
MG		 10986 u8 reserved_at_1[0x14];
10987 u8 port_select_mode[0x3];
10988 u8 reserved_at_18[0x5];
84df61eb
AH		 10989 u8 lag_state[0x3];
10990
8d1ac895
LC		 10991 u8 reserved_at_20[0xc];
10992 u8 active_port[0x4];
10993 u8 reserved_at_30[0x4];
84df61eb
AH		 10994 u8 tx_remap_affinity_2[0x4];
10995 u8 reserved_at_38[0x4];
10996 u8 tx_remap_affinity_1[0x4];
10997};
10998
10999struct mlx5_ifc_create_lag_out_bits {
11000 u8 status[0x8];
11001 u8 reserved_at_8[0x18];
11002
11003 u8 syndrome[0x20];
11004
11005 u8 reserved_at_40[0x40];
11006};
11007
11008struct mlx5_ifc_create_lag_in_bits {
11009 u8 opcode[0x10];
11010 u8 reserved_at_10[0x10];
11011
11012 u8 reserved_at_20[0x10];
11013 u8 op_mod[0x10];
11014
11015 struct mlx5_ifc_lagc_bits ctx;
11016};
11017
11018struct mlx5_ifc_modify_lag_out_bits {
11019 u8 status[0x8];
11020 u8 reserved_at_8[0x18];
11021
11022 u8 syndrome[0x20];
11023
11024 u8 reserved_at_40[0x40];
11025};
11026
11027struct mlx5_ifc_modify_lag_in_bits {
11028 u8 opcode[0x10];
11029 u8 reserved_at_10[0x10];
11030
11031 u8 reserved_at_20[0x10];
11032 u8 op_mod[0x10];
11033
11034 u8 reserved_at_40[0x20];
11035 u8 field_select[0x20];
11036
11037 struct mlx5_ifc_lagc_bits ctx;
11038};
11039
11040struct mlx5_ifc_query_lag_out_bits {
11041 u8 status[0x8];
11042 u8 reserved_at_8[0x18];
11043
11044 u8 syndrome[0x20];
11045
84df61eb
AH		 11046 struct mlx5_ifc_lagc_bits ctx;
11047};
11048
11049struct mlx5_ifc_query_lag_in_bits {
11050 u8 opcode[0x10];
11051 u8 reserved_at_10[0x10];
11052
11053 u8 reserved_at_20[0x10];
11054 u8 op_mod[0x10];
11055
11056 u8 reserved_at_40[0x40];
11057};
11058
11059struct mlx5_ifc_destroy_lag_out_bits {
11060 u8 status[0x8];
11061 u8 reserved_at_8[0x18];
11062
11063 u8 syndrome[0x20];
11064
11065 u8 reserved_at_40[0x40];
11066};
11067
11068struct mlx5_ifc_destroy_lag_in_bits {
11069 u8 opcode[0x10];
11070 u8 reserved_at_10[0x10];
11071
11072 u8 reserved_at_20[0x10];
11073 u8 op_mod[0x10];
11074
11075 u8 reserved_at_40[0x40];
11076};
11077
11078struct mlx5_ifc_create_vport_lag_out_bits {
11079 u8 status[0x8];
11080 u8 reserved_at_8[0x18];
11081
11082 u8 syndrome[0x20];
11083
11084 u8 reserved_at_40[0x40];
11085};
11086
11087struct mlx5_ifc_create_vport_lag_in_bits {
11088 u8 opcode[0x10];
11089 u8 reserved_at_10[0x10];
11090
11091 u8 reserved_at_20[0x10];
11092 u8 op_mod[0x10];
11093
11094 u8 reserved_at_40[0x40];
11095};
11096
11097struct mlx5_ifc_destroy_vport_lag_out_bits {
11098 u8 status[0x8];
11099 u8 reserved_at_8[0x18];
11100
11101 u8 syndrome[0x20];
11102
11103 u8 reserved_at_40[0x40];
11104};
11105
11106struct mlx5_ifc_destroy_vport_lag_in_bits {
11107 u8 opcode[0x10];
11108 u8 reserved_at_10[0x10];
11109
11110 u8 reserved_at_20[0x10];
11111 u8 op_mod[0x10];
11112
11113 u8 reserved_at_40[0x40];
11114};
11115
63f9c44b
MG		 11116enum {
11117 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11118 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11119};
11120
11121struct mlx5_ifc_modify_memic_in_bits {
11122 u8 opcode[0x10];
11123 u8 uid[0x10];
11124
11125 u8 reserved_at_20[0x10];
11126 u8 op_mod[0x10];
11127
11128 u8 reserved_at_40[0x20];
11129
11130 u8 reserved_at_60[0x18];
11131 u8 memic_operation_type[0x8];
11132
11133 u8 memic_start_addr[0x40];
11134
11135 u8 reserved_at_c0[0x140];
11136};
11137
11138struct mlx5_ifc_modify_memic_out_bits {
11139 u8 status[0x8];
11140 u8 reserved_at_8[0x18];
11141
11142 u8 syndrome[0x20];
11143
11144 u8 reserved_at_40[0x40];
11145
11146 u8 memic_operation_addr[0x40];
11147
11148 u8 reserved_at_c0[0x140];
11149};
11150
24da0016
AL		 11151struct mlx5_ifc_alloc_memic_in_bits {
11152 u8 opcode[0x10];
11153 u8 reserved_at_10[0x10];
11154
11155 u8 reserved_at_20[0x10];
11156 u8 op_mod[0x10];
11157
11158 u8 reserved_at_30[0x20];
11159
11160 u8 reserved_at_40[0x18];
11161 u8 log_memic_addr_alignment[0x8];
11162
11163 u8 range_start_addr[0x40];
11164
11165 u8 range_size[0x20];
11166
11167 u8 memic_size[0x20];
11168};
11169
11170struct mlx5_ifc_alloc_memic_out_bits {
11171 u8 status[0x8];
11172 u8 reserved_at_8[0x18];
11173
11174 u8 syndrome[0x20];
11175
11176 u8 memic_start_addr[0x40];
11177};
11178
11179struct mlx5_ifc_dealloc_memic_in_bits {
11180 u8 opcode[0x10];
11181 u8 reserved_at_10[0x10];
11182
11183 u8 reserved_at_20[0x10];
11184 u8 op_mod[0x10];
11185
11186 u8 reserved_at_40[0x40];
11187
11188 u8 memic_start_addr[0x40];
11189
11190 u8 memic_size[0x20];
11191
11192 u8 reserved_at_e0[0x20];
11193};
11194
11195struct mlx5_ifc_dealloc_memic_out_bits {
11196 u8 status[0x8];
11197 u8 reserved_at_8[0x18];
11198
11199 u8 syndrome[0x20];
11200
11201 u8 reserved_at_40[0x40];
11202};
11203
38b7ca92 11204struct mlx5_ifc_umem_bits {
6e3722ba 11205 u8 reserved_at_0[0x80];
38b7ca92 11206
6e3722ba 11207 u8 reserved_at_80[0x1b];
38b7ca92
YH		 11208 u8 log_page_size[0x5];
11209
11210 u8 page_offset[0x20];
11211
11212 u8 num_of_mtt[0x40];
11213
b6ca09cb 11214 struct mlx5_ifc_mtt_bits mtt[];
38b7ca92
YH		 11215};
11216
11217struct mlx5_ifc_uctx_bits {
9d43faac
YH		 11218 u8 cap[0x20];
11219
6e3722ba 11220 u8 reserved_at_20[0x160];
38b7ca92
YH		 11221};
11222
9fba2b9b
AL		 11223struct mlx5_ifc_sw_icm_bits {
11224 u8 modify_field_select[0x40];
11225
11226 u8 reserved_at_40[0x18];
11227 u8 log_sw_icm_size[0x8];
11228
11229 u8 reserved_at_60[0x20];
11230
11231 u8 sw_icm_start_addr[0x40];
11232
11233 u8 reserved_at_c0[0x140];
91a40a48 11234};
b169e64a
YK		 11235
11236struct mlx5_ifc_geneve_tlv_option_bits {
11237 u8 modify_field_select[0x40];
11238
11239 u8 reserved_at_40[0x18];
11240 u8 geneve_option_fte_index[0x8];
11241
11242 u8 option_class[0x10];
11243 u8 option_type[0x8];
11244 u8 reserved_at_78[0x3];
11245 u8 option_data_length[0x5];
11246
11247 u8 reserved_at_80[0x180];
9fba2b9b
AL		 11248};
11249
38b7ca92 11250struct mlx5_ifc_create_umem_in_bits {
6e3722ba
YH		 11251 u8 opcode[0x10];
11252 u8 uid[0x10];
11253
11254 u8 reserved_at_20[0x10];
11255 u8 op_mod[0x10];
11256
11257 u8 reserved_at_40[0x40];
11258
11259 struct mlx5_ifc_umem_bits umem;
38b7ca92
YH		 11260};
11261
8a06a79b
EC		 11262struct mlx5_ifc_create_umem_out_bits {
11263 u8 status[0x8];
11264 u8 reserved_at_8[0x18];
11265
11266 u8 syndrome[0x20];
11267
11268 u8 reserved_at_40[0x8];
11269 u8 umem_id[0x18];
11270
11271 u8 reserved_at_60[0x20];
11272};
11273
11274struct mlx5_ifc_destroy_umem_in_bits {
11275 u8 opcode[0x10];
11276 u8 uid[0x10];
11277
11278 u8 reserved_at_20[0x10];
11279 u8 op_mod[0x10];
11280
11281 u8 reserved_at_40[0x8];
11282 u8 umem_id[0x18];
11283
11284 u8 reserved_at_60[0x20];
11285};
11286
11287struct mlx5_ifc_destroy_umem_out_bits {
11288 u8 status[0x8];
11289 u8 reserved_at_8[0x18];
11290
11291 u8 syndrome[0x20];
11292
11293 u8 reserved_at_40[0x40];
11294};
11295
38b7ca92 11296struct mlx5_ifc_create_uctx_in_bits {
6e3722ba
YH		 11297 u8 opcode[0x10];
11298 u8 reserved_at_10[0x10];
11299
11300 u8 reserved_at_20[0x10];
11301 u8 op_mod[0x10];
11302
11303 u8 reserved_at_40[0x40];
11304
11305 struct mlx5_ifc_uctx_bits uctx;
11306};
11307
8a06a79b
EC		 11308struct mlx5_ifc_create_uctx_out_bits {
11309 u8 status[0x8];
11310 u8 reserved_at_8[0x18];
11311
11312 u8 syndrome[0x20];
11313
11314 u8 reserved_at_40[0x10];
11315 u8 uid[0x10];
11316
11317 u8 reserved_at_60[0x20];
11318};
11319
6e3722ba
YH		 11320struct mlx5_ifc_destroy_uctx_in_bits {
11321 u8 opcode[0x10];
11322 u8 reserved_at_10[0x10];
11323
11324 u8 reserved_at_20[0x10];
11325 u8 op_mod[0x10];
11326
11327 u8 reserved_at_40[0x10];
11328 u8 uid[0x10];
11329
11330 u8 reserved_at_60[0x20];
38b7ca92
YH		 11331};
11332
8a06a79b
EC		 11333struct mlx5_ifc_destroy_uctx_out_bits {
11334 u8 status[0x8];
11335 u8 reserved_at_8[0x18];
11336
11337 u8 syndrome[0x20];
11338
11339 u8 reserved_at_40[0x40];
11340};
11341
9fba2b9b
AL		 11342struct mlx5_ifc_create_sw_icm_in_bits {
11343 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11344 struct mlx5_ifc_sw_icm_bits sw_icm;
11345};
11346
b169e64a
YK		 11347struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11348 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11349 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
11350};
11351
eff8ea8f
FD		 11352struct mlx5_ifc_mtrc_string_db_param_bits {
11353 u8 string_db_base_address[0x20];
11354
11355 u8 reserved_at_20[0x8];
11356 u8 string_db_size[0x18];
11357};
11358
11359struct mlx5_ifc_mtrc_cap_bits {
11360 u8 trace_owner[0x1];
11361 u8 trace_to_memory[0x1];
11362 u8 reserved_at_2[0x4];
11363 u8 trc_ver[0x2];
11364 u8 reserved_at_8[0x14];
11365 u8 num_string_db[0x4];
11366
11367 u8 first_string_trace[0x8];
11368 u8 num_string_trace[0x8];
11369 u8 reserved_at_30[0x28];
11370
11371 u8 log_max_trace_buffer_size[0x8];
11372
11373 u8 reserved_at_60[0x20];
11374
11375 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11376
11377 u8 reserved_at_280[0x180];
11378};
11379
11380struct mlx5_ifc_mtrc_conf_bits {
11381 u8 reserved_at_0[0x1c];
11382 u8 trace_mode[0x4];
11383 u8 reserved_at_20[0x18];
11384 u8 log_trace_buffer_size[0x8];
11385 u8 trace_mkey[0x20];
11386 u8 reserved_at_60[0x3a0];
11387};
11388
11389struct mlx5_ifc_mtrc_stdb_bits {
11390 u8 string_db_index[0x4];
11391 u8 reserved_at_4[0x4];
11392 u8 read_size[0x18];
11393 u8 start_offset[0x20];
b6ca09cb 11394 u8 string_db_data[];
eff8ea8f
FD		 11395};
11396
11397struct mlx5_ifc_mtrc_ctrl_bits {
11398 u8 trace_status[0x2];
11399 u8 reserved_at_2[0x2];
11400 u8 arm_event[0x1];
11401 u8 reserved_at_5[0xb];
11402 u8 modify_field_select[0x10];
11403 u8 reserved_at_20[0x2b];
11404 u8 current_timestamp52_32[0x15];
11405 u8 current_timestamp31_0[0x20];
11406 u8 reserved_at_80[0x180];
11407};
11408
c3a4e9f1
BW		 11409struct mlx5_ifc_host_params_context_bits {
11410 u8 host_number[0x8];
5ccf2770
BW		 11411 u8 reserved_at_8[0x7];
11412 u8 host_pf_disabled[0x1];
c3a4e9f1
BW		 11413 u8 host_num_of_vfs[0x10];
11414
86eec50b 11415 u8 host_total_vfs[0x10];
c3a4e9f1
BW		 11416 u8 host_pci_bus[0x10];
11417
11418 u8 reserved_at_40[0x10];
11419 u8 host_pci_device[0x10];
11420
11421 u8 reserved_at_60[0x10];
11422 u8 host_pci_function[0x10];
11423
11424 u8 reserved_at_80[0x180];
11425};
11426
cd56f929 11427struct mlx5_ifc_query_esw_functions_in_bits {
c3a4e9f1
BW		 11428 u8 opcode[0x10];
11429 u8 reserved_at_10[0x10];
11430
11431 u8 reserved_at_20[0x10];
11432 u8 op_mod[0x10];
11433
11434 u8 reserved_at_40[0x40];
11435};
11436
cd56f929 11437struct mlx5_ifc_query_esw_functions_out_bits {
c3a4e9f1
BW		 11438 u8 status[0x8];
11439 u8 reserved_at_8[0x18];
11440
11441 u8 syndrome[0x20];
11442
11443 u8 reserved_at_40[0x40];
11444
11445 struct mlx5_ifc_host_params_context_bits host_params_context;
11446
11447 u8 reserved_at_280[0x180];
b6ca09cb 11448 u8 host_sf_enable[][0x40];
1759d322
PP		 11449};
11450
11451struct mlx5_ifc_sf_partition_bits {
11452 u8 reserved_at_0[0x10];
11453 u8 log_num_sf[0x8];
11454 u8 log_sf_bar_size[0x8];
11455};
11456
11457struct mlx5_ifc_query_sf_partitions_out_bits {
11458 u8 status[0x8];
11459 u8 reserved_at_8[0x18];
11460
11461 u8 syndrome[0x20];
11462
11463 u8 reserved_at_40[0x18];
11464 u8 num_sf_partitions[0x8];
11465
11466 u8 reserved_at_60[0x20];
11467
b6ca09cb 11468 struct mlx5_ifc_sf_partition_bits sf_partition[];
1759d322
PP		 11469};
11470
11471struct mlx5_ifc_query_sf_partitions_in_bits {
11472 u8 opcode[0x10];
11473 u8 reserved_at_10[0x10];
11474
11475 u8 reserved_at_20[0x10];
11476 u8 op_mod[0x10];
11477
11478 u8 reserved_at_40[0x40];
11479};
11480
11481struct mlx5_ifc_dealloc_sf_out_bits {
11482 u8 status[0x8];
11483 u8 reserved_at_8[0x18];
11484
11485 u8 syndrome[0x20];
11486
11487 u8 reserved_at_40[0x40];
11488};
11489
11490struct mlx5_ifc_dealloc_sf_in_bits {
11491 u8 opcode[0x10];
11492 u8 reserved_at_10[0x10];
11493
11494 u8 reserved_at_20[0x10];
11495 u8 op_mod[0x10];
11496
11497 u8 reserved_at_40[0x10];
11498 u8 function_id[0x10];
11499
11500 u8 reserved_at_60[0x20];
11501};
11502
11503struct mlx5_ifc_alloc_sf_out_bits {
11504 u8 status[0x8];
11505 u8 reserved_at_8[0x18];
11506
11507 u8 syndrome[0x20];
11508
11509 u8 reserved_at_40[0x40];
11510};
11511
11512struct mlx5_ifc_alloc_sf_in_bits {
11513 u8 opcode[0x10];
11514 u8 reserved_at_10[0x10];
11515
11516 u8 reserved_at_20[0x10];
11517 u8 op_mod[0x10];
11518
11519 u8 reserved_at_40[0x10];
11520 u8 function_id[0x10];
11521
11522 u8 reserved_at_60[0x20];
c3a4e9f1
BW		 11523};
11524
e4075c44
YH		 11525struct mlx5_ifc_affiliated_event_header_bits {
11526 u8 reserved_at_0[0x10];
11527 u8 obj_type[0x10];
11528
11529 u8 obj_id[0x20];
11530};
11531
a12ff35e 11532enum {
49e27134
PP		 11533 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11534 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11535 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
f5d23ee1 11536 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
a12ff35e
EBE		 11537};
11538
11539enum {
11540 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
2b58f6d9 11541 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
2a297089 11542 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
f5d23ee1 11543 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
8385c51f 11544 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
2b58f6d9
RS		 11545};
11546
11547enum {
11548 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
2b58f6d9
RS		 11549};
11550
11551struct mlx5_ifc_ipsec_obj_bits {
11552 u8 modify_field_select[0x40];
11553 u8 full_offload[0x1];
11554 u8 reserved_at_41[0x1];
11555 u8 esn_en[0x1];
11556 u8 esn_overlap[0x1];
11557 u8 reserved_at_44[0x2];
11558 u8 icv_length[0x2];
11559 u8 reserved_at_48[0x4];
11560 u8 aso_return_reg[0x4];
11561 u8 reserved_at_50[0x10];
11562
11563 u8 esn_msb[0x20];
11564
11565 u8 reserved_at_80[0x8];
11566 u8 dekn[0x18];
11567
11568 u8 salt[0x20];
11569
11570 u8 implicit_iv[0x40];
11571
11572 u8 reserved_at_100[0x700];
11573};
11574
11575struct mlx5_ifc_create_ipsec_obj_in_bits {
11576 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11577 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11578};
11579
11580enum {
11581 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11582 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11583};
11584
11585struct mlx5_ifc_query_ipsec_obj_out_bits {
11586 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11587 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11588};
11589
11590struct mlx5_ifc_modify_ipsec_obj_in_bits {
11591 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11592 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
a12ff35e
EBE		 11593};
11594
23cc83c6
EH		 11595enum {
11596 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
11597};
11598
11599enum {
11600 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0,
11601 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1,
11602 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11603 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11604};
11605
11606#define MLX5_MACSEC_ASO_INC_SN 0x2
11607#define MLX5_MACSEC_ASO_REG_C_4_5 0x2
11608
8385c51f
LN		 11609struct mlx5_ifc_macsec_aso_bits {
11610 u8 valid[0x1];
11611 u8 reserved_at_1[0x1];
11612 u8 mode[0x2];
11613 u8 window_size[0x2];
11614 u8 soft_lifetime_arm[0x1];
11615 u8 hard_lifetime_arm[0x1];
11616 u8 remove_flow_enable[0x1];
11617 u8 epn_event_arm[0x1];
11618 u8 reserved_at_a[0x16];
11619
11620 u8 remove_flow_packet_count[0x20];
11621
11622 u8 remove_flow_soft_lifetime[0x20];
11623
11624 u8 reserved_at_60[0x80];
11625
11626 u8 mode_parameter[0x20];
11627
11628 u8 replay_protection_window[8][0x20];
11629};
11630
11631struct mlx5_ifc_macsec_offload_obj_bits {
11632 u8 modify_field_select[0x40];
11633
11634 u8 confidentiality_en[0x1];
11635 u8 reserved_at_41[0x1];
21803630
EH		 11636 u8 epn_en[0x1];
11637 u8 epn_overlap[0x1];
8385c51f
LN		 11638 u8 reserved_at_44[0x2];
11639 u8 confidentiality_offset[0x2];
11640 u8 reserved_at_48[0x4];
11641 u8 aso_return_reg[0x4];
11642 u8 reserved_at_50[0x10];
11643
21803630 11644 u8 epn_msb[0x20];
8385c51f
LN		 11645
11646 u8 reserved_at_80[0x8];
11647 u8 dekn[0x18];
11648
11649 u8 reserved_at_a0[0x20];
11650
11651 u8 sci[0x40];
11652
11653 u8 reserved_at_100[0x8];
11654 u8 macsec_aso_access_pd[0x18];
11655
11656 u8 reserved_at_120[0x60];
11657
11658 u8 salt[3][0x20];
11659
11660 u8 reserved_at_1e0[0x20];
11661
11662 struct mlx5_ifc_macsec_aso_bits macsec_aso;
11663};
11664
11665struct mlx5_ifc_create_macsec_obj_in_bits {
11666 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11667 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11668};
11669
23cc83c6
EH		 11670struct mlx5_ifc_modify_macsec_obj_in_bits {
11671 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11672 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11673};
11674
11675enum {
11676 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
11677 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
11678};
11679
11680struct mlx5_ifc_query_macsec_obj_out_bits {
11681 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11682 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11683};
11684
a12ff35e
EBE		 11685struct mlx5_ifc_encryption_key_obj_bits {
11686 u8 modify_field_select[0x40];
11687
11688 u8 reserved_at_40[0x14];
11689 u8 key_size[0x4];
11690 u8 reserved_at_58[0x4];
11691 u8 key_type[0x4];
11692
11693 u8 reserved_at_60[0x8];
11694 u8 pd[0x18];
11695
11696 u8 reserved_at_80[0x180];
11697 u8 key[8][0x20];
11698
11699 u8 reserved_at_300[0x500];
11700};
11701
11702struct mlx5_ifc_create_encryption_key_in_bits {
11703 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11704 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11705};
11706
f5d23ee1
JL		 11707enum {
11708 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0,
11709 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1,
11710 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2,
11711 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3,
11712};
11713
11714struct mlx5_ifc_flow_meter_parameters_bits {
11715 u8 valid[0x1];
11716 u8 bucket_overflow[0x1];
11717 u8 start_color[0x2];
11718 u8 both_buckets_on_green[0x1];
11719 u8 reserved_at_5[0x1];
11720 u8 meter_mode[0x2];
11721 u8 reserved_at_8[0x18];
11722
11723 u8 reserved_at_20[0x20];
11724
11725 u8 reserved_at_40[0x3];
11726 u8 cbs_exponent[0x5];
11727 u8 cbs_mantissa[0x8];
11728 u8 reserved_at_50[0x3];
11729 u8 cir_exponent[0x5];
11730 u8 cir_mantissa[0x8];
11731
11732 u8 reserved_at_60[0x20];
11733
11734 u8 reserved_at_80[0x3];
11735 u8 ebs_exponent[0x5];
11736 u8 ebs_mantissa[0x8];
11737 u8 reserved_at_90[0x3];
11738 u8 eir_exponent[0x5];
11739 u8 eir_mantissa[0x8];
11740
11741 u8 reserved_at_a0[0x60];
11742};
11743
11744struct mlx5_ifc_flow_meter_aso_obj_bits {
11745 u8 modify_field_select[0x40];
11746
11747 u8 reserved_at_40[0x40];
11748
11749 u8 reserved_at_80[0x8];
11750 u8 meter_aso_access_pd[0x18];
11751
11752 u8 reserved_at_a0[0x160];
11753
11754 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
11755};
11756
11757struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
11758 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11759 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
11760};
11761
2a297089
CM		 11762struct mlx5_ifc_sampler_obj_bits {
11763 u8 modify_field_select[0x40];
11764
11765 u8 table_type[0x8];
11766 u8 level[0x8];
11767 u8 reserved_at_50[0xf];
11768 u8 ignore_flow_level[0x1];
11769
11770 u8 sample_ratio[0x20];
11771
11772 u8 reserved_at_80[0x8];
11773 u8 sample_table_id[0x18];
11774
11775 u8 reserved_at_a0[0x8];
11776 u8 default_table_id[0x18];
11777
11778 u8 sw_steering_icm_address_rx[0x40];
11779 u8 sw_steering_icm_address_tx[0x40];
11780
11781 u8 reserved_at_140[0xa0];
11782};
11783
11784struct mlx5_ifc_create_sampler_obj_in_bits {
11785 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11786 struct mlx5_ifc_sampler_obj_bits sampler_object;
11787};
11788
1ab6dc35
YK		 11789struct mlx5_ifc_query_sampler_obj_out_bits {
11790 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11791 struct mlx5_ifc_sampler_obj_bits sampler_object;
11792};
11793
a12ff35e
EBE		 11794enum {
11795 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11796 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11797};
11798
11799enum {
bd673da6
SM		 11800 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11801 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
8385c51f 11802 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4,
a12ff35e
EBE		 11803};
11804
11805struct mlx5_ifc_tls_static_params_bits {
11806 u8 const_2[0x2];
11807 u8 tls_version[0x4];
11808 u8 const_1[0x2];
11809 u8 reserved_at_8[0x14];
11810 u8 encryption_standard[0x4];
11811
11812 u8 reserved_at_20[0x20];
11813
11814 u8 initial_record_number[0x40];
11815
11816 u8 resync_tcp_sn[0x20];
11817
11818 u8 gcm_iv[0x20];
11819
11820 u8 implicit_iv[0x40];
11821
11822 u8 reserved_at_100[0x8];
11823 u8 dek_index[0x18];
11824
11825 u8 reserved_at_120[0xe0];
11826};
11827
11828struct mlx5_ifc_tls_progress_params_bits {
a12ff35e
EBE		 11829 u8 next_record_tcp_sn[0x20];
11830
11831 u8 hw_resync_tcp_sn[0x20];
11832
11833 u8 record_tracker_state[0x2];
11834 u8 auth_state[0x2];
2d1b69ed 11835 u8 reserved_at_44[0x4];
a12ff35e
EBE		 11836 u8 hw_offset_record_number[0x18];
11837};
11838
1dcb6c36
EC		 11839enum {
11840 MLX5_MTT_PERM_READ = 1 << 0,
11841 MLX5_MTT_PERM_WRITE = 1 << 1,
11842 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11843};
11844
adfdaff3
YH		 11845enum {
11846 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
11847 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
11848};
11849
11850struct mlx5_ifc_suspend_vhca_in_bits {
11851 u8 opcode[0x10];
11852 u8 uid[0x10];
11853
11854 u8 reserved_at_20[0x10];
11855 u8 op_mod[0x10];
11856
11857 u8 reserved_at_40[0x10];
11858 u8 vhca_id[0x10];
11859
11860 u8 reserved_at_60[0x20];
11861};
11862
11863struct mlx5_ifc_suspend_vhca_out_bits {
11864 u8 status[0x8];
11865 u8 reserved_at_8[0x18];
11866
11867 u8 syndrome[0x20];
11868
11869 u8 reserved_at_40[0x40];
11870};
11871
11872enum {
11873 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
11874 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
11875};
11876
11877struct mlx5_ifc_resume_vhca_in_bits {
11878 u8 opcode[0x10];
11879 u8 uid[0x10];
11880
11881 u8 reserved_at_20[0x10];
11882 u8 op_mod[0x10];
11883
11884 u8 reserved_at_40[0x10];
11885 u8 vhca_id[0x10];
11886
11887 u8 reserved_at_60[0x20];
11888};
11889
11890struct mlx5_ifc_resume_vhca_out_bits {
11891 u8 status[0x8];
11892 u8 reserved_at_8[0x18];
11893
11894 u8 syndrome[0x20];
11895
11896 u8 reserved_at_40[0x40];
11897};
11898
11899struct mlx5_ifc_query_vhca_migration_state_in_bits {
11900 u8 opcode[0x10];
11901 u8 uid[0x10];
11902
11903 u8 reserved_at_20[0x10];
11904 u8 op_mod[0x10];
11905
11906 u8 reserved_at_40[0x10];
11907 u8 vhca_id[0x10];
11908
11909 u8 reserved_at_60[0x20];
11910};
11911
11912struct mlx5_ifc_query_vhca_migration_state_out_bits {
11913 u8 status[0x8];
11914 u8 reserved_at_8[0x18];
11915
11916 u8 syndrome[0x20];
11917
11918 u8 reserved_at_40[0x40];
11919
11920 u8 required_umem_size[0x20];
11921
11922 u8 reserved_at_a0[0x160];
11923};
11924
11925struct mlx5_ifc_save_vhca_state_in_bits {
11926 u8 opcode[0x10];
11927 u8 uid[0x10];
11928
11929 u8 reserved_at_20[0x10];
11930 u8 op_mod[0x10];
11931
11932 u8 reserved_at_40[0x10];
11933 u8 vhca_id[0x10];
11934
11935 u8 reserved_at_60[0x20];
11936
11937 u8 va[0x40];
11938
11939 u8 mkey[0x20];
11940
11941 u8 size[0x20];
11942};
11943
11944struct mlx5_ifc_save_vhca_state_out_bits {
11945 u8 status[0x8];
11946 u8 reserved_at_8[0x18];
11947
11948 u8 syndrome[0x20];
11949
11950 u8 actual_image_size[0x20];
11951
11952 u8 reserved_at_60[0x20];
11953};
11954
11955struct mlx5_ifc_load_vhca_state_in_bits {
11956 u8 opcode[0x10];
11957 u8 uid[0x10];
11958
11959 u8 reserved_at_20[0x10];
11960 u8 op_mod[0x10];
11961
11962 u8 reserved_at_40[0x10];
11963 u8 vhca_id[0x10];
11964
11965 u8 reserved_at_60[0x20];
11966
11967 u8 va[0x40];
11968
11969 u8 mkey[0x20];
11970
11971 u8 size[0x20];
11972};
11973
11974struct mlx5_ifc_load_vhca_state_out_bits {
11975 u8 status[0x8];
11976 u8 reserved_at_8[0x18];
11977
11978 u8 syndrome[0x20];
11979
11980 u8 reserved_at_40[0x40];
11981};
11982
a1be74c5
YH		 11983struct mlx5_ifc_adv_virtualization_cap_bits {
11984 u8 reserved_at_0[0x3];
11985 u8 pg_track_log_max_num[0x5];
11986 u8 pg_track_max_num_range[0x8];
11987 u8 pg_track_log_min_addr_space[0x8];
11988 u8 pg_track_log_max_addr_space[0x8];
11989
11990 u8 reserved_at_20[0x3];
11991 u8 pg_track_log_min_msg_size[0x5];
11992 u8 reserved_at_28[0x3];
11993 u8 pg_track_log_max_msg_size[0x5];
11994 u8 reserved_at_30[0x3];
11995 u8 pg_track_log_min_page_size[0x5];
11996 u8 reserved_at_38[0x3];
11997 u8 pg_track_log_max_page_size[0x5];
11998
11999 u8 reserved_at_40[0x7c0];
12000};
12001
12002struct mlx5_ifc_page_track_report_entry_bits {
12003 u8 dirty_address_high[0x20];
12004
12005 u8 dirty_address_low[0x20];
12006};
12007
12008enum {
12009 MLX5_PAGE_TRACK_STATE_TRACKING,
12010 MLX5_PAGE_TRACK_STATE_REPORTING,
12011 MLX5_PAGE_TRACK_STATE_ERROR,
12012};
12013
12014struct mlx5_ifc_page_track_range_bits {
12015 u8 start_address[0x40];
12016
12017 u8 length[0x40];
12018};
12019
12020struct mlx5_ifc_page_track_bits {
12021 u8 modify_field_select[0x40];
12022
12023 u8 reserved_at_40[0x10];
12024 u8 vhca_id[0x10];
12025
12026 u8 reserved_at_60[0x20];
12027
12028 u8 state[0x4];
12029 u8 track_type[0x4];
12030 u8 log_addr_space_size[0x8];
12031 u8 reserved_at_90[0x3];
12032 u8 log_page_size[0x5];
12033 u8 reserved_at_98[0x3];
12034 u8 log_msg_size[0x5];
12035
12036 u8 reserved_at_a0[0x8];
12037 u8 reporting_qpn[0x18];
12038
12039 u8 reserved_at_c0[0x18];
12040 u8 num_ranges[0x8];
12041
12042 u8 reserved_at_e0[0x20];
12043
12044 u8 range_start_address[0x40];
12045
12046 u8 length[0x40];
12047
12048 struct mlx5_ifc_page_track_range_bits track_range[0];
12049};
12050
12051struct mlx5_ifc_create_page_track_obj_in_bits {
12052 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12053 struct mlx5_ifc_page_track_bits obj_context;
12054};
12055
12056struct mlx5_ifc_modify_page_track_obj_in_bits {
12057 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12058 struct mlx5_ifc_page_track_bits obj_context;
12059};
12060
d29b796a 12061#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)