[linux-block.git] / include / linux / mlx5 / eswitch.h

/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
 * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
 */

#ifndef _MLX5_ESWITCH_
#define _MLX5_ESWITCH_

#include <linux/mlx5/driver.h>
#include <net/devlink.h>

#define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager)

enum {
	MLX5_ESWITCH_LEGACY,
	MLX5_ESWITCH_OFFLOADS
};

enum {
	REP_ETH,
	REP_IB,
	NUM_REP_TYPES,
};

enum {
	REP_UNREGISTERED,
	REP_REGISTERED,
	REP_LOADED,
};

enum mlx5_switchdev_event {
	MLX5_SWITCHDEV_EVENT_PAIR,
	MLX5_SWITCHDEV_EVENT_UNPAIR,
};

struct mlx5_eswitch_rep;
struct mlx5_eswitch_rep_ops {
	int (*load)(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep *rep);
	void (*unload)(struct mlx5_eswitch_rep *rep);
	void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep);
	int (*event)(struct mlx5_eswitch *esw,
		     struct mlx5_eswitch_rep *rep,
		     enum mlx5_switchdev_event event,
		     void *data);
};

struct mlx5_eswitch_rep_data {
	void *priv;
	atomic_t state;
};

struct mlx5_eswitch_rep {
	struct mlx5_eswitch_rep_data rep_data[NUM_REP_TYPES];
	u16		       vport;
	u16		       vlan;
	/* Only IB rep is using vport_index */
	u16		       vport_index;
	u32		       vlan_refcount;
	struct                 mlx5_eswitch *esw;
};

void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
				      const struct mlx5_eswitch_rep_ops *ops,
				      u8 rep_type);
void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type);
void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
				 u16 vport_num,
				 u8 rep_type);
struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
						u16 vport_num);
void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type);
struct mlx5_flow_handle *
mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
				    struct mlx5_eswitch *from_esw,
				    struct mlx5_eswitch_rep *rep, u32 sqn);

#ifdef CONFIG_MLX5_ESWITCH
enum devlink_eswitch_encap_mode
mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);

bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw);
bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw);

/* Reg C0 usage:
 * Reg C0 = < ESW_PFNUM_BITS(4) | ESW_VPORT BITS(12) | ESW_REG_C0_OBJ(16) >
 *
 * Highest 4 bits of the reg c0 is the PF_NUM (range 0-15), 12 bits of
 * unique non-zero vport id (range 1-4095). The rest (lowest 16 bits) is left
 * for user data objects managed by a common mapping context.
 * PFNUM + VPORT comprise the SOURCE_PORT matching.
 */
#define ESW_VPORT_BITS 12
#define ESW_PFNUM_BITS 4
#define ESW_SOURCE_PORT_METADATA_BITS (ESW_PFNUM_BITS + ESW_VPORT_BITS)
#define ESW_SOURCE_PORT_METADATA_OFFSET (32 - ESW_SOURCE_PORT_METADATA_BITS)
#define ESW_REG_C0_USER_DATA_METADATA_BITS (32 - ESW_SOURCE_PORT_METADATA_BITS)
#define ESW_REG_C0_USER_DATA_METADATA_MASK GENMASK(ESW_REG_C0_USER_DATA_METADATA_BITS - 1, 0)

static inline u32 mlx5_eswitch_get_vport_metadata_mask(void)
{
	return GENMASK(31, 32 - ESW_SOURCE_PORT_METADATA_BITS);
}

u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
					      u16 vport_num);
u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
					    u16 vport_num);

/* Reg C1 usage:
 * Reg C1 = < Reserved(1) | ESW_TUN_ID(12) | ESW_TUN_OPTS(11) | ESW_ZONE_ID(8) >
 *
 * Highest bit is reserved for other offloads as marker bit, next 12 bits of reg c1
 * is the encapsulation tunnel id, next 11 bits is encapsulation tunnel options,
 * and the lowest 8 bits are used for zone id.
 *
 * Zone id is used to restore CT flow when packet misses on chain.
 *
 * Tunnel id and options are used together to restore the tunnel info metadata
 * on miss and to support inner header rewrite by means of implicit chain 0
 * flows.
 */
#define ESW_RESERVED_BITS 1
#define ESW_ZONE_ID_BITS 8
#define ESW_TUN_OPTS_BITS 11
#define ESW_TUN_ID_BITS 12
#define ESW_TUN_OPTS_OFFSET ESW_ZONE_ID_BITS
#define ESW_TUN_OFFSET ESW_TUN_OPTS_OFFSET
#define ESW_ZONE_ID_MASK GENMASK(ESW_ZONE_ID_BITS - 1, 0)
#define ESW_TUN_OPTS_MASK GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, ESW_TUN_OPTS_OFFSET)
#define ESW_TUN_MASK GENMASK(31 - ESW_RESERVED_BITS, ESW_TUN_OFFSET)
#define ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT 0 /* 0 is not a valid tunnel id */
#define ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT
/* 0x7FF is a reserved mapping */
#define ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT GENMASK(ESW_TUN_OPTS_BITS - 1, 0)
#define ESW_TUN_SLOW_TABLE_GOTO_VPORT ((ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT << ESW_TUN_OPTS_BITS) | \
				       ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT)
#define ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK ESW_TUN_OPTS_MASK
/* 0x7FE is a reserved mapping for bridge ingress push vlan mark */
#define ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN (ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT - 1)
#define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN ((ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN << \
					   ESW_TUN_OPTS_BITS) | \
					  ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN)
#define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN_MARK \
	GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, \
		ESW_TUN_OPTS_OFFSET + 1)

u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev);
u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev);
struct mlx5_core_dev *mlx5_eswitch_get_core_dev(struct mlx5_eswitch *esw);

#else  /* CONFIG_MLX5_ESWITCH */

static inline u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev)
{
	return MLX5_ESWITCH_LEGACY;
}

static inline enum devlink_eswitch_encap_mode
mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev)
{
	return DEVLINK_ESWITCH_ENCAP_MODE_NONE;
}

static inline bool
mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
{
	return false;
};

static inline bool
mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
{
	return false;
};

static inline u32
mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, u16 vport_num)
{
	return 0;
};

static inline u32
mlx5_eswitch_get_vport_metadata_mask(void)
{
	return 0;
}

static inline u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev)
{
	return 0;
}

static inline struct mlx5_core_dev *mlx5_eswitch_get_core_dev(struct mlx5_eswitch *esw)
{
	return NULL;
}

#endif /* CONFIG_MLX5_ESWITCH */

static inline bool is_mdev_legacy_mode(struct mlx5_core_dev *dev)
{
	return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_LEGACY;
}

static inline bool is_mdev_switchdev_mode(struct mlx5_core_dev *dev)
{
	return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_OFFLOADS;
}

#endif
Commit	Line	Data
57cbd893 MB	1	/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
	2	/*
	3	* Copyright (c) 2018 Mellanox Technologies. All rights reserved.
	4	*/
	5
	6	#ifndef _MLX5_ESWITCH_
	7	#define _MLX5_ESWITCH_
	8
	9	#include <linux/mlx5/driver.h>
82b11f07	10	#include <net/devlink.h>
57cbd893	11
0efc8562 OG	12	#define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager)
0efc8562 OG	13
57cbd893	14	enum {
f6455de0 BW	15	MLX5_ESWITCH_LEGACY,
f6455de0 BW	16	MLX5_ESWITCH_OFFLOADS
57cbd893 MB	17	};
	18
	19	enum {
	20	REP_ETH,
5e65b02c	21	REP_IB,
57cbd893 MB	22	NUM_REP_TYPES,
	23	};
	24
f121e0ea BW	25	enum {
	26	REP_UNREGISTERED,
	27	REP_REGISTERED,
	28	REP_LOADED,
	29	};
	30
c8e6a9e6 MB	31	enum mlx5_switchdev_event {
	32	MLX5_SWITCHDEV_EVENT_PAIR,
	33	MLX5_SWITCHDEV_EVENT_UNPAIR,
	34	};
	35
57cbd893	36	struct mlx5_eswitch_rep;
8693115a PP	37	struct mlx5_eswitch_rep_ops {
	38	int (load)(struct mlx5_core_dev dev, struct mlx5_eswitch_rep *rep);
	39	void (unload)(struct mlx5_eswitch_rep rep);
	40	void (get_proto_dev)(struct mlx5_eswitch_rep *rep);
c8e6a9e6 MB	41	int (event)(struct mlx5_eswitch esw,
	42	struct mlx5_eswitch_rep *rep,
	43	enum mlx5_switchdev_event event,
	44	void *data);
8693115a PP	45	};
	46
	47	struct mlx5_eswitch_rep_data {
	48	void *priv;
	49	atomic_t state;
57cbd893 MB	50	};
	51
	52	struct mlx5_eswitch_rep {
8693115a	53	struct mlx5_eswitch_rep_data rep_data[NUM_REP_TYPES];
57cbd893	54	u16 vport;
57cbd893	55	u16 vlan;
2f69e591 BW	56	/* Only IB rep is using vport_index */
2f69e591 BW	57	u16 vport_index;
57cbd893	58	u32 vlan_refcount;
59c904c8	59	struct mlx5_eswitch *esw;
57cbd893 MB	60	};
57cbd893 MB	61
f8e8fa02	62	void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a	63	const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 BW	64	u8 rep_type);
f8e8fa02 BW	65	void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type);
57cbd893	66	void mlx5_eswitch_get_proto_dev(struct mlx5_eswitch esw,
02f3afd9	67	u16 vport_num,
57cbd893 MB	68	u8 rep_type);
57cbd893 MB	69	struct mlx5_eswitch_rep mlx5_eswitch_vport_rep(struct mlx5_eswitch esw,
02f3afd9	70	u16 vport_num);
57cbd893	71	void mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch esw, u8 rep_type);
57cbd893	72	struct mlx5_flow_handle *
3a46f4fb	73	mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
979bf468	74	struct mlx5_eswitch *from_esw,
3a46f4fb	75	struct mlx5_eswitch_rep *rep, u32 sqn);
82b11f07 MG	76
	77	#ifdef CONFIG_MLX5_ESWITCH
	78	enum devlink_eswitch_encap_mode
	79	mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);
7445cfb1	80
5b7cb745	81	bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw);
7445cfb1	82	bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw);
0f0d3827 PB	83
0f0d3827 PB	84	/* Reg C0 usage:
a91d98a0	85	* Reg C0 = < ESW_PFNUM_BITS(4) \| ESW_VPORT BITS(12) \| ESW_REG_C0_OBJ(16) >
0f0d3827	86	*
7cd7becd	87	* Highest 4 bits of the reg c0 is the PF_NUM (range 0-15), 12 bits of
7cd7becd	88	* unique non-zero vport id (range 1-4095). The rest (lowest 16 bits) is left
a91d98a0	89	* for user data objects managed by a common mapping context.
7cd7becd	90	* PFNUM + VPORT comprise the SOURCE_PORT matching.
0f0d3827	91	*/
7cd7becd	92	#define ESW_VPORT_BITS 12
	93	#define ESW_PFNUM_BITS 4
	94	#define ESW_SOURCE_PORT_METADATA_BITS (ESW_PFNUM_BITS + ESW_VPORT_BITS)
0f0d3827	95	#define ESW_SOURCE_PORT_METADATA_OFFSET (32 - ESW_SOURCE_PORT_METADATA_BITS)
a91d98a0 CM	96	#define ESW_REG_C0_USER_DATA_METADATA_BITS (32 - ESW_SOURCE_PORT_METADATA_BITS)
a91d98a0 CM	97	#define ESW_REG_C0_USER_DATA_METADATA_MASK GENMASK(ESW_REG_C0_USER_DATA_METADATA_BITS - 1, 0)
0f0d3827 PB	98
	99	static inline u32 mlx5_eswitch_get_vport_metadata_mask(void)
	100	{
	101	return GENMASK(31, 32 - ESW_SOURCE_PORT_METADATA_BITS);
	102	}
	103
	104	u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1	105	u16 vport_num);
10742efc VB	106	u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
10742efc VB	107	u16 vport_num);
48d216e5 VB	108
48d216e5 VB	109	/* Reg C1 usage:
b973cf32	110	* Reg C1 = < Reserved(1) \| ESW_TUN_ID(12) \| ESW_TUN_OPTS(11) \| ESW_ZONE_ID(8) >
48d216e5	111	*
b973cf32 HN	112	* Highest bit is reserved for other offloads as marker bit, next 12 bits of reg c1
	113	* is the encapsulation tunnel id, next 11 bits is encapsulation tunnel options,
	114	* and the lowest 8 bits are used for zone id.
48d216e5 VB	115	*
	116	* Zone id is used to restore CT flow when packet misses on chain.
	117	*
	118	* Tunnel id and options are used together to restore the tunnel info metadata
	119	* on miss and to support inner header rewrite by means of implicit chain 0
	120	* flows.
	121	*/
b973cf32	122	#define ESW_RESERVED_BITS 1
48d216e5	123	#define ESW_ZONE_ID_BITS 8
b973cf32	124	#define ESW_TUN_OPTS_BITS 11
48d216e5	125	#define ESW_TUN_ID_BITS 12
8e404fef VB	126	#define ESW_TUN_OPTS_OFFSET ESW_ZONE_ID_BITS
8e404fef VB	127	#define ESW_TUN_OFFSET ESW_TUN_OPTS_OFFSET
48d216e5	128	#define ESW_ZONE_ID_MASK GENMASK(ESW_ZONE_ID_BITS - 1, 0)
b973cf32 HN	129	#define ESW_TUN_OPTS_MASK GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, ESW_TUN_OPTS_OFFSET)
b973cf32 HN	130	#define ESW_TUN_MASK GENMASK(31 - ESW_RESERVED_BITS, ESW_TUN_OFFSET)
8e404fef	131	#define ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT 0 /* 0 is not a valid tunnel id */
5249001d	132	#define ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT
b973cf32 HN	133	/* 0x7FF is a reserved mapping */
b973cf32 HN	134	#define ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT GENMASK(ESW_TUN_OPTS_BITS - 1, 0)
8e404fef VB	135	#define ESW_TUN_SLOW_TABLE_GOTO_VPORT ((ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT << ESW_TUN_OPTS_BITS) \| \
	136	ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT)
	137	#define ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK ESW_TUN_OPTS_MASK
5249001d VB	138	/* 0x7FE is a reserved mapping for bridge ingress push vlan mark */
	139	#define ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN (ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT - 1)
	140	#define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN ((ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN << \
	141	ESW_TUN_OPTS_BITS) \| \
	142	ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN)
	143	#define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN_MARK \
	144	GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, \
	145	ESW_TUN_OPTS_OFFSET + 1)
48d216e5	146
d7751d64	147	u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev);
06ec5acc	148	u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev);
97a8a8c1	149	struct mlx5_core_dev mlx5_eswitch_get_core_dev(struct mlx5_eswitch esw);
06ec5acc	150
82b11f07	151	#else /* CONFIG_MLX5_ESWITCH */
f813cb50	152
d7751d64	153	static inline u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev)
f813cb50	154	{
f019679e	155	return MLX5_ESWITCH_LEGACY;
f813cb50 MG	156	}
f813cb50 MG	157
82b11f07 MG	158	static inline enum devlink_eswitch_encap_mode
	159	mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev)
	160	{
	161	return DEVLINK_ESWITCH_ENCAP_MODE_NONE;
	162	}
7445cfb1	163
5b7cb745 PB	164	static inline bool
	165	mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
	166	{
	167	return false;
	168	};
	169
7445cfb1 JL	170	static inline bool
	171	mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
	172	{
	173	return false;
	174	};
	175
	176	static inline u32
6308a5f0	177	mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, u16 vport_num)
7445cfb1 JL	178	{
	179	return 0;
	180	};
0f0d3827 PB	181
	182	static inline u32
	183	mlx5_eswitch_get_vport_metadata_mask(void)
	184	{
	185	return 0;
	186	}
06ec5acc PP	187
	188	static inline u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev)
	189	{
	190	return 0;
	191	}
	192
97a8a8c1 MB	193	static inline struct mlx5_core_dev mlx5_eswitch_get_core_dev(struct mlx5_eswitch esw)
	194	{
	195	return NULL;
	196	}
	197
82b11f07	198	#endif /* CONFIG_MLX5_ESWITCH */
2752b823	199
f019679e CM	200	static inline bool is_mdev_legacy_mode(struct mlx5_core_dev *dev)
	201	{
	202	return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_LEGACY;
	203	}
	204
e8711402 LR	205	static inline bool is_mdev_switchdev_mode(struct mlx5_core_dev *dev)
	206	{
	207	return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_OFFLOADS;
	208	}
06ec5acc	209
57cbd893	210	#endif