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IB/mlx5: Advertise atomic capabilities in query device
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
48enum {
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
51};
52
53enum {
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
56 */
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
59};
60
61enum {
62 CMD_OWNER_SW = 0x0,
63 CMD_OWNER_HW = 0x1,
64 CMD_STATUS_SUCCESS = 0,
65};
66
67enum mlx5_sqp_t {
68 MLX5_SQP_SMI = 0,
69 MLX5_SQP_GSI = 1,
70 MLX5_SQP_IEEE_1588 = 2,
71 MLX5_SQP_SNIFFER = 3,
72 MLX5_SQP_SYNC_UMR = 4,
73};
74
75enum {
76 MLX5_MAX_PORTS = 2,
77};
78
79enum {
80 MLX5_EQ_VEC_PAGES = 0,
81 MLX5_EQ_VEC_CMD = 1,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
84};
85
86enum {
db058a18 87 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 88};
89
90enum {
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
99};
100
e126ba97
EC		 101enum {
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
3c2d18ef 106 MLX5_REG_PFCC = 0x5007,
efea389d 107 MLX5_REG_PPCNT = 0x5008,
e126ba97
EC		 108 MLX5_REG_PMAOS = 0x5012,
109 MLX5_REG_PUDE = 0x5009,
110 MLX5_REG_PMPE = 0x5010,
111 MLX5_REG_PELC = 0x500e,
a124d13e 112 MLX5_REG_PVLC = 0x500f,
e126ba97
EC		 113 MLX5_REG_PMLP = 0, /* TBD */
114 MLX5_REG_NODE_DESC = 0x6001,
115 MLX5_REG_HOST_ENDIANNESS = 0x7004,
116};
117
da7525d2
EBE		 118enum {
119 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
120 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
121};
122
e420f0c0
HE		 123enum mlx5_page_fault_resume_flags {
124 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
125 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
126 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
127 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
128};
129
e126ba97
EC		 130enum dbg_rsc_type {
131 MLX5_DBG_RSC_QP,
132 MLX5_DBG_RSC_EQ,
133 MLX5_DBG_RSC_CQ,
134};
135
136struct mlx5_field_desc {
137 struct dentry *dent;
138 int i;
139};
140
141struct mlx5_rsc_debug {
142 struct mlx5_core_dev *dev;
143 void *object;
144 enum dbg_rsc_type type;
145 struct dentry *root;
146 struct mlx5_field_desc fields[0];
147};
148
149enum mlx5_dev_event {
150 MLX5_DEV_EVENT_SYS_ERROR,
151 MLX5_DEV_EVENT_PORT_UP,
152 MLX5_DEV_EVENT_PORT_DOWN,
153 MLX5_DEV_EVENT_PORT_INITIALIZED,
154 MLX5_DEV_EVENT_LID_CHANGE,
155 MLX5_DEV_EVENT_PKEY_CHANGE,
156 MLX5_DEV_EVENT_GUID_CHANGE,
157 MLX5_DEV_EVENT_CLIENT_REREG,
158};
159
4c916a79 160enum mlx5_port_status {
6fa1bcab
AS		 161 MLX5_PORT_UP = 1,
162 MLX5_PORT_DOWN = 2,
4c916a79
RS		 163};
164
e126ba97
EC		 165struct mlx5_uuar_info {
166 struct mlx5_uar *uars;
167 int num_uars;
168 int num_low_latency_uuars;
169 unsigned long *bitmap;
170 unsigned int *count;
171 struct mlx5_bf *bfs;
172
173 /*
174 * protect uuar allocation data structs
175 */
176 struct mutex lock;
78c0f98c 177 u32 ver;
e126ba97
EC		 178};
179
180struct mlx5_bf {
181 void __iomem *reg;
182 void __iomem *regreg;
183 int buf_size;
184 struct mlx5_uar *uar;
185 unsigned long offset;
186 int need_lock;
187 /* protect blue flame buffer selection when needed
188 */
189 spinlock_t lock;
190
191 /* serialize 64 bit writes when done as two 32 bit accesses
192 */
193 spinlock_t lock32;
194 int uuarn;
195};
196
197struct mlx5_cmd_first {
198 __be32 data[4];
199};
200
201struct mlx5_cmd_msg {
202 struct list_head list;
203 struct cache_ent *cache;
204 u32 len;
205 struct mlx5_cmd_first first;
206 struct mlx5_cmd_mailbox *next;
207};
208
209struct mlx5_cmd_debug {
210 struct dentry *dbg_root;
211 struct dentry *dbg_in;
212 struct dentry *dbg_out;
213 struct dentry *dbg_outlen;
214 struct dentry *dbg_status;
215 struct dentry *dbg_run;
216 void *in_msg;
217 void *out_msg;
218 u8 status;
219 u16 inlen;
220 u16 outlen;
221};
222
223struct cache_ent {
224 /* protect block chain allocations
225 */
226 spinlock_t lock;
227 struct list_head head;
228};
229
230struct cmd_msg_cache {
231 struct cache_ent large;
232 struct cache_ent med;
233
234};
235
236struct mlx5_cmd_stats {
237 u64 sum;
238 u64 n;
239 struct dentry *root;
240 struct dentry *avg;
241 struct dentry *count;
242 /* protect command average calculations */
243 spinlock_t lock;
244};
245
246struct mlx5_cmd {
64599cca
EC		 247 void *cmd_alloc_buf;
248 dma_addr_t alloc_dma;
249 int alloc_size;
e126ba97
EC		 250 void *cmd_buf;
251 dma_addr_t dma;
252 u16 cmdif_rev;
253 u8 log_sz;
254 u8 log_stride;
255 int max_reg_cmds;
256 int events;
257 u32 __iomem *vector;
258
259 /* protect command queue allocations
260 */
261 spinlock_t alloc_lock;
262
263 /* protect token allocations
264 */
265 spinlock_t token_lock;
266 u8 token;
267 unsigned long bitmask;
268 char wq_name[MLX5_CMD_WQ_MAX_NAME];
269 struct workqueue_struct *wq;
270 struct semaphore sem;
271 struct semaphore pages_sem;
272 int mode;
273 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
274 struct pci_pool *pool;
275 struct mlx5_cmd_debug dbg;
276 struct cmd_msg_cache cache;
277 int checksum_disabled;
278 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
279};
280
281struct mlx5_port_caps {
282 int gid_table_len;
283 int pkey_table_len;
938fe83c 284 u8 ext_port_cap;
e126ba97
EC		 285};
286
287struct mlx5_cmd_mailbox {
288 void *buf;
289 dma_addr_t dma;
290 struct mlx5_cmd_mailbox *next;
291};
292
293struct mlx5_buf_list {
294 void *buf;
295 dma_addr_t map;
296};
297
298struct mlx5_buf {
299 struct mlx5_buf_list direct;
e126ba97 300 int npages;
e126ba97 301 int size;
f241e749 302 u8 page_shift;
e126ba97
EC		 303};
304
305struct mlx5_eq {
306 struct mlx5_core_dev *dev;
307 __be32 __iomem *doorbell;
308 u32 cons_index;
309 struct mlx5_buf buf;
310 int size;
311 u8 irqn;
312 u8 eqn;
313 int nent;
314 u64 mask;
e126ba97
EC		 315 struct list_head list;
316 int index;
317 struct mlx5_rsc_debug *dbg;
318};
319
3121e3c4
SG		 320struct mlx5_core_psv {
321 u32 psv_idx;
322 struct psv_layout {
323 u32 pd;
324 u16 syndrome;
325 u16 reserved;
326 u16 bg;
327 u16 app_tag;
328 u32 ref_tag;
329 } psv;
330};
331
332struct mlx5_core_sig_ctx {
333 struct mlx5_core_psv psv_memory;
334 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 335 struct ib_sig_err err_item;
336 bool sig_status_checked;
337 bool sig_err_exists;
338 u32 sigerr_count;
3121e3c4 339};
e126ba97
EC		 340
341struct mlx5_core_mr {
342 u64 iova;
343 u64 size;
344 u32 key;
345 u32 pd;
e126ba97
EC		 346};
347
5903325a
EC		 348enum mlx5_res_type {
349 MLX5_RES_QP,
01949d01
HA		 350 MLX5_RES_SRQ,
351 MLX5_RES_XSRQ,
5903325a
EC		 352};
353
354struct mlx5_core_rsc_common {
355 enum mlx5_res_type res;
356 atomic_t refcount;
357 struct completion free;
358};
359
e126ba97 360struct mlx5_core_srq {
01949d01 361 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC		 362 u32 srqn;
363 int max;
364 int max_gs;
365 int max_avail_gather;
366 int wqe_shift;
367 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
368
369 atomic_t refcount;
370 struct completion free;
371};
372
373struct mlx5_eq_table {
374 void __iomem *update_ci;
375 void __iomem *update_arm_ci;
233d05d2 376 struct list_head comp_eqs_list;
e126ba97
EC		 377 struct mlx5_eq pages_eq;
378 struct mlx5_eq async_eq;
379 struct mlx5_eq cmd_eq;
e126ba97
EC		 380 int num_comp_vectors;
381 /* protect EQs list
382 */
383 spinlock_t lock;
384};
385
386struct mlx5_uar {
387 u32 index;
388 struct list_head bf_list;
389 unsigned free_bf_bmap;
88a85f99 390 void __iomem *bf_map;
e126ba97
EC		 391 void __iomem *map;
392};
393
394
395struct mlx5_core_health {
396 struct health_buffer __iomem *health;
397 __be32 __iomem *health_counter;
398 struct timer_list timer;
e126ba97
EC		 399 u32 prev;
400 int miss_counter;
fd76ee4d 401 bool sick;
ac6ea6e8
EC		 402 struct workqueue_struct *wq;
403 struct work_struct work;
e126ba97
EC		 404};
405
406struct mlx5_cq_table {
407 /* protect radix tree
408 */
409 spinlock_t lock;
410 struct radix_tree_root tree;
411};
412
413struct mlx5_qp_table {
414 /* protect radix tree
415 */
416 spinlock_t lock;
417 struct radix_tree_root tree;
418};
419
420struct mlx5_srq_table {
421 /* protect radix tree
422 */
423 spinlock_t lock;
424 struct radix_tree_root tree;
425};
426
3bcdb17a
SG		 427struct mlx5_mr_table {
428 /* protect radix tree
429 */
430 rwlock_t lock;
431 struct radix_tree_root tree;
432};
433
db058a18
SM		 434struct mlx5_irq_info {
435 cpumask_var_t mask;
436 char name[MLX5_MAX_IRQ_NAME];
437};
438
e126ba97
EC		 439struct mlx5_priv {
440 char name[MLX5_MAX_NAME_LEN];
441 struct mlx5_eq_table eq_table;
db058a18
SM		 442 struct msix_entry *msix_arr;
443 struct mlx5_irq_info *irq_info;
e126ba97
EC		 444 struct mlx5_uuar_info uuari;
445 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
446
88a85f99
AS		 447 struct io_mapping *bf_mapping;
448
e126ba97
EC		 449 /* pages stuff */
450 struct workqueue_struct *pg_wq;
451 struct rb_root page_root;
452 int fw_pages;
6aec21f6 453 atomic_t reg_pages;
bf0bf77f 454 struct list_head free_list;
e126ba97
EC		 455
456 struct mlx5_core_health health;
457
458 struct mlx5_srq_table srq_table;
459
460 /* start: qp staff */
461 struct mlx5_qp_table qp_table;
462 struct dentry *qp_debugfs;
463 struct dentry *eq_debugfs;
464 struct dentry *cq_debugfs;
465 struct dentry *cmdif_debugfs;
466 /* end: qp staff */
467
468 /* start: cq staff */
469 struct mlx5_cq_table cq_table;
470 /* end: cq staff */
471
3bcdb17a
SG		 472 /* start: mr staff */
473 struct mlx5_mr_table mr_table;
474 /* end: mr staff */
475
e126ba97 476 /* start: alloc staff */
311c7c71
SM		 477 /* protect buffer alocation according to numa node */
478 struct mutex alloc_mutex;
479 int numa_node;
480
e126ba97
EC		 481 struct mutex pgdir_mutex;
482 struct list_head pgdir_list;
483 /* end: alloc staff */
484 struct dentry *dbg_root;
485
486 /* protect mkey key part */
487 spinlock_t mkey_lock;
488 u8 mkey_key;
9603b61d
JM		 489
490 struct list_head dev_list;
491 struct list_head ctx_list;
492 spinlock_t ctx_lock;
e126ba97
EC		 493};
494
89d44f0a
MD		 495enum mlx5_device_state {
496 MLX5_DEVICE_STATE_UP,
497 MLX5_DEVICE_STATE_INTERNAL_ERROR,
498};
499
500enum mlx5_interface_state {
501 MLX5_INTERFACE_STATE_DOWN,
502 MLX5_INTERFACE_STATE_UP,
503};
504
505enum mlx5_pci_status {
506 MLX5_PCI_STATUS_DISABLED,
507 MLX5_PCI_STATUS_ENABLED,
508};
509
e126ba97
EC		 510struct mlx5_core_dev {
511 struct pci_dev *pdev;
89d44f0a
MD		 512 /* sync pci state */
513 struct mutex pci_status_mutex;
514 enum mlx5_pci_status pci_status;
e126ba97
EC		 515 u8 rev_id;
516 char board_id[MLX5_BOARD_ID_LEN];
517 struct mlx5_cmd cmd;
938fe83c
SM		 518 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
519 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
520 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 521 phys_addr_t iseg_base;
522 struct mlx5_init_seg __iomem *iseg;
89d44f0a
MD		 523 enum mlx5_device_state state;
524 /* sync interface state */
525 struct mutex intf_state_mutex;
526 enum mlx5_interface_state interface_state;
e126ba97
EC		 527 void (*event) (struct mlx5_core_dev *dev,
528 enum mlx5_dev_event event,
4d2f9bbb 529 unsigned long param);
e126ba97
EC		 530 struct mlx5_priv priv;
531 struct mlx5_profile *profile;
532 atomic_t num_qps;
f62b8bb8 533 u32 issi;
e126ba97
EC		 534};
535
536struct mlx5_db {
537 __be32 *db;
538 union {
539 struct mlx5_db_pgdir *pgdir;
540 struct mlx5_ib_user_db_page *user_page;
541 } u;
542 dma_addr_t dma;
543 int index;
544};
545
546enum {
547 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
548};
549
550enum {
551 MLX5_COMP_EQ_SIZE = 1024,
552};
553
adb0c954
SM		 554enum {
555 MLX5_PTYS_IB = 1 << 0,
556 MLX5_PTYS_EN = 1 << 2,
557};
558
e126ba97
EC		 559struct mlx5_db_pgdir {
560 struct list_head list;
561 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
562 __be32 *db_page;
563 dma_addr_t db_dma;
564};
565
566typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
567
568struct mlx5_cmd_work_ent {
569 struct mlx5_cmd_msg *in;
570 struct mlx5_cmd_msg *out;
746b5583
EC		 571 void *uout;
572 int uout_size;
e126ba97
EC		 573 mlx5_cmd_cbk_t callback;
574 void *context;
746b5583 575 int idx;
e126ba97
EC		 576 struct completion done;
577 struct mlx5_cmd *cmd;
578 struct work_struct work;
579 struct mlx5_cmd_layout *lay;
580 int ret;
581 int page_queue;
582 u8 status;
583 u8 token;
14a70046
TG		 584 u64 ts1;
585 u64 ts2;
746b5583 586 u16 op;
e126ba97
EC		 587};
588
589struct mlx5_pas {
590 u64 pa;
591 u8 log_sz;
592};
593
707c4602
MD		 594enum port_state_policy {
595 MLX5_AAA_000
596};
597
598enum phy_port_state {
599 MLX5_AAA_111
600};
601
602struct mlx5_hca_vport_context {
603 u32 field_select;
604 bool sm_virt_aware;
605 bool has_smi;
606 bool has_raw;
607 enum port_state_policy policy;
608 enum phy_port_state phys_state;
609 enum ib_port_state vport_state;
610 u8 port_physical_state;
611 u64 sys_image_guid;
612 u64 port_guid;
613 u64 node_guid;
614 u32 cap_mask1;
615 u32 cap_mask1_perm;
616 u32 cap_mask2;
617 u32 cap_mask2_perm;
618 u16 lid;
619 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
620 u8 lmc;
621 u8 subnet_timeout;
622 u16 sm_lid;
623 u8 sm_sl;
624 u16 qkey_violation_counter;
625 u16 pkey_violation_counter;
626 bool grh_required;
627};
628
e126ba97
EC		 629static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
630{
e126ba97 631 return buf->direct.buf + offset;
e126ba97
EC		 632}
633
634extern struct workqueue_struct *mlx5_core_wq;
635
636#define STRUCT_FIELD(header, field) \
637 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
638 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
639
e126ba97
EC		 640static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
641{
642 return pci_get_drvdata(pdev);
643}
644
645extern struct dentry *mlx5_debugfs_root;
646
647static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
648{
649 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
650}
651
652static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
653{
654 return ioread32be(&dev->iseg->fw_rev) >> 16;
655}
656
657static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
658{
659 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
660}
661
662static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
663{
664 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
665}
666
667static inline void *mlx5_vzalloc(unsigned long size)
668{
669 void *rtn;
670
671 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
672 if (!rtn)
673 rtn = vzalloc(size);
674 return rtn;
675}
676
3bcdb17a
SG		 677static inline u32 mlx5_base_mkey(const u32 key)
678{
679 return key & 0xffffff00u;
680}
681
e126ba97
EC		 682int mlx5_cmd_init(struct mlx5_core_dev *dev);
683void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
684void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
685void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
686int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 687int mlx5_cmd_status_to_err_v2(void *ptr);
938fe83c
SM		 688int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
689 enum mlx5_cap_mode cap_mode);
e126ba97
EC		 690int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
691 int out_size);
746b5583
EC		 692int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
693 void *out, int out_size, mlx5_cmd_cbk_t callback,
694 void *context);
e126ba97
EC		 695int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
696int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
697int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
698int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
e281682b
SM		 699int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
700void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
ac6ea6e8
EC		 701void mlx5_health_cleanup(struct mlx5_core_dev *dev);
702int mlx5_health_init(struct mlx5_core_dev *dev);
e126ba97
EC		 703void mlx5_start_health_poll(struct mlx5_core_dev *dev);
704void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
311c7c71
SM		 705int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
706 struct mlx5_buf *buf, int node);
64ffaa21 707int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 708void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
709struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
710 gfp_t flags, int npages);
711void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
712 struct mlx5_cmd_mailbox *head);
713int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
01949d01
HA		 714 struct mlx5_create_srq_mbox_in *in, int inlen,
715 int is_xrc);
e126ba97
EC		 716int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
717int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
718 struct mlx5_query_srq_mbox_out *out);
719int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
720 u16 lwm, int is_srq);
3bcdb17a
SG		 721void mlx5_init_mr_table(struct mlx5_core_dev *dev);
722void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 723int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 724 struct mlx5_create_mkey_mbox_in *in, int inlen,
725 mlx5_cmd_cbk_t callback, void *context,
726 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 727int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
728int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
729 struct mlx5_query_mkey_mbox_out *out, int outlen);
730int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
731 u32 *mkey);
732int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
733int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
a97e2d86 734int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
f241e749 735 u16 opmod, u8 port);
e126ba97
EC		 736void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
737void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
738int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
739void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
740void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 741 s32 npages);
cd23b14b 742int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC		 743int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
744void mlx5_register_debugfs(void);
745void mlx5_unregister_debugfs(void);
746int mlx5_eq_init(struct mlx5_core_dev *dev);
747void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
748void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
749void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 750void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e420f0c0
HE		 751#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
752void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
753#endif
e126ba97
EC		 754void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
755struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
020446e0 756void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
e126ba97
EC		 757void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
758int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
759 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
760int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
761int mlx5_start_eqs(struct mlx5_core_dev *dev);
762int mlx5_stop_eqs(struct mlx5_core_dev *dev);
233d05d2 763int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
e126ba97
EC		 764int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
765int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
766
767int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
768void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
769int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
770 int size_in, void *data_out, int size_out,
771 u16 reg_num, int arg, int write);
adb0c954 772
f241e749 773int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
adb0c954 774int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
a05bdefa 775 int ptys_size, int proto_mask, u8 local_port);
adb0c954
SM		 776int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
777 u32 *proto_cap, int proto_mask);
778int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
779 u32 *proto_admin, int proto_mask);
a124d13e
MD		 780int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
781 u8 *link_width_oper, u8 local_port);
782int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
783 u8 *proto_oper, int proto_mask,
784 u8 local_port);
adb0c954
SM		 785int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
786 int proto_mask);
6fa1bcab
AS		 787int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
788 enum mlx5_port_status status);
789int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
790 enum mlx5_port_status *status);
e126ba97 791
facc9699
SM		 792int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);
793void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port);
794void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
795 u8 port);
796
a124d13e
MD		 797int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
798 u8 *vl_hw_cap, u8 local_port);
e126ba97 799
3c2d18ef
AS		 800int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
801int mlx5_query_port_pause(struct mlx5_core_dev *dev,
802 u32 *rx_pause, u32 *tx_pause);
803
e126ba97
EC		 804int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
805void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
806int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
807 struct mlx5_query_eq_mbox_out *out, int outlen);
808int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
809void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
810int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
811void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
812int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
311c7c71
SM		 813int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
814 int node);
e126ba97
EC		 815void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
816
e126ba97
EC		 817const char *mlx5_command_str(int command);
818int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
819void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 820int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
821 int npsvs, u32 *sig_index);
822int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 823void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE		 824int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
825 struct mlx5_odp_caps *odp_caps);
e126ba97 826
e3297246
EC		 827static inline int fw_initializing(struct mlx5_core_dev *dev)
828{
829 return ioread32be(&dev->iseg->initializing) >> 31;
830}
831
e126ba97
EC		 832static inline u32 mlx5_mkey_to_idx(u32 mkey)
833{
834 return mkey >> 8;
835}
836
837static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
838{
839 return mkey_idx << 8;
840}
841
746b5583
EC		 842static inline u8 mlx5_mkey_variant(u32 mkey)
843{
844 return mkey & 0xff;
845}
846
e126ba97
EC		 847enum {
848 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 849 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC		 850};
851
852enum {
853 MAX_MR_CACHE_ENTRIES = 16,
854};
855
64613d94
SM		 856enum {
857 MLX5_INTERFACE_PROTOCOL_IB = 0,
858 MLX5_INTERFACE_PROTOCOL_ETH = 1,
859};
860
9603b61d
JM		 861struct mlx5_interface {
862 void * (*add)(struct mlx5_core_dev *dev);
863 void (*remove)(struct mlx5_core_dev *dev, void *context);
864 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 865 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 866 void * (*get_dev)(void *context);
867 int protocol;
9603b61d
JM		 868 struct list_head list;
869};
870
64613d94 871void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM		 872int mlx5_register_interface(struct mlx5_interface *intf);
873void mlx5_unregister_interface(struct mlx5_interface *intf);
211e6c80 874int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
9603b61d 875
e126ba97
EC		 876struct mlx5_profile {
877 u64 mask;
f241e749 878 u8 log_max_qp;
e126ba97
EC		 879 struct {
880 int size;
881 int limit;
882 } mr_cache[MAX_MR_CACHE_ENTRIES];
883};
884
707c4602
MD		 885static inline int mlx5_get_gid_table_len(u16 param)
886{
887 if (param > 4) {
888 pr_warn("gid table length is zero\n");
889 return 0;
890 }
891
892 return 8 * (1 << param);
893}
894
020446e0
EC		 895enum {
896 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
897};
898
e126ba97 899#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)