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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
43a335e0 | 44 | #include <linux/workqueue.h> |
d9aaed83 | 45 | #include <linux/mempool.h> |
94c6825e | 46 | #include <linux/interrupt.h> |
6ecde51d | 47 | |
e126ba97 EC |
48 | #include <linux/mlx5/device.h> |
49 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 50 | #include <linux/mlx5/srq.h> |
e126ba97 EC |
51 | |
52 | enum { | |
53 | MLX5_BOARD_ID_LEN = 64, | |
54 | MLX5_MAX_NAME_LEN = 16, | |
55 | }; | |
56 | ||
57 | enum { | |
58 | /* one minute for the sake of bringup. Generally, commands must always | |
59 | * complete and we may need to increase this timeout value | |
60 | */ | |
6b6c07bd | 61 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
62 | MLX5_CMD_WQ_MAX_NAME = 32, |
63 | }; | |
64 | ||
65 | enum { | |
66 | CMD_OWNER_SW = 0x0, | |
67 | CMD_OWNER_HW = 0x1, | |
68 | CMD_STATUS_SUCCESS = 0, | |
69 | }; | |
70 | ||
71 | enum mlx5_sqp_t { | |
72 | MLX5_SQP_SMI = 0, | |
73 | MLX5_SQP_GSI = 1, | |
74 | MLX5_SQP_IEEE_1588 = 2, | |
75 | MLX5_SQP_SNIFFER = 3, | |
76 | MLX5_SQP_SYNC_UMR = 4, | |
77 | }; | |
78 | ||
79 | enum { | |
80 | MLX5_MAX_PORTS = 2, | |
81 | }; | |
82 | ||
83 | enum { | |
84 | MLX5_EQ_VEC_PAGES = 0, | |
85 | MLX5_EQ_VEC_CMD = 1, | |
86 | MLX5_EQ_VEC_ASYNC = 2, | |
d9aaed83 | 87 | MLX5_EQ_VEC_PFAULT = 3, |
e126ba97 EC |
88 | MLX5_EQ_VEC_COMP_BASE, |
89 | }; | |
90 | ||
91 | enum { | |
db058a18 | 92 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
93 | }; |
94 | ||
95 | enum { | |
96 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
97 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
98 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
99 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
100 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
101 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
102 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
103 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
104 | }; | |
105 | ||
e126ba97 | 106 | enum { |
4f3961ee SM |
107 | MLX5_REG_QETCR = 0x4005, |
108 | MLX5_REG_QTCT = 0x400a, | |
341c5ee2 HN |
109 | MLX5_REG_DCBX_PARAM = 0x4020, |
110 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
111 | MLX5_REG_FPGA_CAP = 0x4022, |
112 | MLX5_REG_FPGA_CTRL = 0x4023, | |
e126ba97 EC |
113 | MLX5_REG_PCAP = 0x5001, |
114 | MLX5_REG_PMTU = 0x5003, | |
115 | MLX5_REG_PTYS = 0x5004, | |
116 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 117 | MLX5_REG_PFCC = 0x5007, |
efea389d | 118 | MLX5_REG_PPCNT = 0x5008, |
e126ba97 EC |
119 | MLX5_REG_PMAOS = 0x5012, |
120 | MLX5_REG_PUDE = 0x5009, | |
121 | MLX5_REG_PMPE = 0x5010, | |
122 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 123 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 124 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 125 | MLX5_REG_PMLP = 0x5002, |
cfdcbcea | 126 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
127 | MLX5_REG_NODE_DESC = 0x6001, |
128 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 129 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 130 | MLX5_REG_MLCR = 0x902b, |
8ed1a630 | 131 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
132 | MLX5_REG_MTPPS = 0x9053, |
133 | MLX5_REG_MTPPSE = 0x9054, | |
cfdcbcea | 134 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
135 | }; |
136 | ||
341c5ee2 HN |
137 | enum mlx5_dcbx_oper_mode { |
138 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
139 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
140 | }; | |
141 | ||
da7525d2 EBE |
142 | enum { |
143 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
144 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
145 | }; | |
146 | ||
e420f0c0 HE |
147 | enum mlx5_page_fault_resume_flags { |
148 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
149 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
150 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
151 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
152 | }; | |
153 | ||
e126ba97 EC |
154 | enum dbg_rsc_type { |
155 | MLX5_DBG_RSC_QP, | |
156 | MLX5_DBG_RSC_EQ, | |
157 | MLX5_DBG_RSC_CQ, | |
158 | }; | |
159 | ||
160 | struct mlx5_field_desc { | |
161 | struct dentry *dent; | |
162 | int i; | |
163 | }; | |
164 | ||
165 | struct mlx5_rsc_debug { | |
166 | struct mlx5_core_dev *dev; | |
167 | void *object; | |
168 | enum dbg_rsc_type type; | |
169 | struct dentry *root; | |
170 | struct mlx5_field_desc fields[0]; | |
171 | }; | |
172 | ||
173 | enum mlx5_dev_event { | |
174 | MLX5_DEV_EVENT_SYS_ERROR, | |
175 | MLX5_DEV_EVENT_PORT_UP, | |
176 | MLX5_DEV_EVENT_PORT_DOWN, | |
177 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
178 | MLX5_DEV_EVENT_LID_CHANGE, | |
179 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
180 | MLX5_DEV_EVENT_GUID_CHANGE, | |
181 | MLX5_DEV_EVENT_CLIENT_REREG, | |
f9a1ef72 | 182 | MLX5_DEV_EVENT_PPS, |
e126ba97 EC |
183 | }; |
184 | ||
4c916a79 | 185 | enum mlx5_port_status { |
6fa1bcab AS |
186 | MLX5_PORT_UP = 1, |
187 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
188 | }; |
189 | ||
d9aaed83 AK |
190 | enum mlx5_eq_type { |
191 | MLX5_EQ_TYPE_COMP, | |
192 | MLX5_EQ_TYPE_ASYNC, | |
193 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
194 | MLX5_EQ_TYPE_PF, | |
195 | #endif | |
196 | }; | |
197 | ||
2f5ff264 | 198 | struct mlx5_bfreg_info { |
b037c29a | 199 | u32 *sys_pages; |
2f5ff264 | 200 | int num_low_latency_bfregs; |
e126ba97 | 201 | unsigned int *count; |
e126ba97 EC |
202 | |
203 | /* | |
2f5ff264 | 204 | * protect bfreg allocation data structs |
e126ba97 EC |
205 | */ |
206 | struct mutex lock; | |
78c0f98c | 207 | u32 ver; |
b037c29a EC |
208 | bool lib_uar_4k; |
209 | u32 num_sys_pages; | |
e126ba97 EC |
210 | }; |
211 | ||
212 | struct mlx5_cmd_first { | |
213 | __be32 data[4]; | |
214 | }; | |
215 | ||
216 | struct mlx5_cmd_msg { | |
217 | struct list_head list; | |
0ac3ea70 | 218 | struct cmd_msg_cache *parent; |
e126ba97 EC |
219 | u32 len; |
220 | struct mlx5_cmd_first first; | |
221 | struct mlx5_cmd_mailbox *next; | |
222 | }; | |
223 | ||
224 | struct mlx5_cmd_debug { | |
225 | struct dentry *dbg_root; | |
226 | struct dentry *dbg_in; | |
227 | struct dentry *dbg_out; | |
228 | struct dentry *dbg_outlen; | |
229 | struct dentry *dbg_status; | |
230 | struct dentry *dbg_run; | |
231 | void *in_msg; | |
232 | void *out_msg; | |
233 | u8 status; | |
234 | u16 inlen; | |
235 | u16 outlen; | |
236 | }; | |
237 | ||
0ac3ea70 | 238 | struct cmd_msg_cache { |
e126ba97 EC |
239 | /* protect block chain allocations |
240 | */ | |
241 | spinlock_t lock; | |
242 | struct list_head head; | |
0ac3ea70 MHY |
243 | unsigned int max_inbox_size; |
244 | unsigned int num_ent; | |
e126ba97 EC |
245 | }; |
246 | ||
0ac3ea70 MHY |
247 | enum { |
248 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
249 | }; |
250 | ||
251 | struct mlx5_cmd_stats { | |
252 | u64 sum; | |
253 | u64 n; | |
254 | struct dentry *root; | |
255 | struct dentry *avg; | |
256 | struct dentry *count; | |
257 | /* protect command average calculations */ | |
258 | spinlock_t lock; | |
259 | }; | |
260 | ||
261 | struct mlx5_cmd { | |
64599cca EC |
262 | void *cmd_alloc_buf; |
263 | dma_addr_t alloc_dma; | |
264 | int alloc_size; | |
e126ba97 EC |
265 | void *cmd_buf; |
266 | dma_addr_t dma; | |
267 | u16 cmdif_rev; | |
268 | u8 log_sz; | |
269 | u8 log_stride; | |
270 | int max_reg_cmds; | |
271 | int events; | |
272 | u32 __iomem *vector; | |
273 | ||
274 | /* protect command queue allocations | |
275 | */ | |
276 | spinlock_t alloc_lock; | |
277 | ||
278 | /* protect token allocations | |
279 | */ | |
280 | spinlock_t token_lock; | |
281 | u8 token; | |
282 | unsigned long bitmask; | |
283 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
284 | struct workqueue_struct *wq; | |
285 | struct semaphore sem; | |
286 | struct semaphore pages_sem; | |
287 | int mode; | |
288 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
289 | struct pci_pool *pool; | |
290 | struct mlx5_cmd_debug dbg; | |
0ac3ea70 | 291 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
292 | int checksum_disabled; |
293 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
294 | }; | |
295 | ||
296 | struct mlx5_port_caps { | |
297 | int gid_table_len; | |
298 | int pkey_table_len; | |
938fe83c | 299 | u8 ext_port_cap; |
c43f1112 | 300 | bool has_smi; |
e126ba97 EC |
301 | }; |
302 | ||
303 | struct mlx5_cmd_mailbox { | |
304 | void *buf; | |
305 | dma_addr_t dma; | |
306 | struct mlx5_cmd_mailbox *next; | |
307 | }; | |
308 | ||
309 | struct mlx5_buf_list { | |
310 | void *buf; | |
311 | dma_addr_t map; | |
312 | }; | |
313 | ||
314 | struct mlx5_buf { | |
315 | struct mlx5_buf_list direct; | |
e126ba97 | 316 | int npages; |
e126ba97 | 317 | int size; |
f241e749 | 318 | u8 page_shift; |
e126ba97 EC |
319 | }; |
320 | ||
1c1b5228 TT |
321 | struct mlx5_frag_buf { |
322 | struct mlx5_buf_list *frags; | |
323 | int npages; | |
324 | int size; | |
325 | u8 page_shift; | |
326 | }; | |
327 | ||
94c6825e MB |
328 | struct mlx5_eq_tasklet { |
329 | struct list_head list; | |
330 | struct list_head process_list; | |
331 | struct tasklet_struct task; | |
332 | /* lock on completion tasklet list */ | |
333 | spinlock_t lock; | |
334 | }; | |
335 | ||
d9aaed83 AK |
336 | struct mlx5_eq_pagefault { |
337 | struct work_struct work; | |
338 | /* Pagefaults lock */ | |
339 | spinlock_t lock; | |
340 | struct workqueue_struct *wq; | |
341 | mempool_t *pool; | |
342 | }; | |
343 | ||
e126ba97 EC |
344 | struct mlx5_eq { |
345 | struct mlx5_core_dev *dev; | |
346 | __be32 __iomem *doorbell; | |
347 | u32 cons_index; | |
348 | struct mlx5_buf buf; | |
349 | int size; | |
0b6e26ce | 350 | unsigned int irqn; |
e126ba97 EC |
351 | u8 eqn; |
352 | int nent; | |
353 | u64 mask; | |
e126ba97 EC |
354 | struct list_head list; |
355 | int index; | |
356 | struct mlx5_rsc_debug *dbg; | |
d9aaed83 AK |
357 | enum mlx5_eq_type type; |
358 | union { | |
359 | struct mlx5_eq_tasklet tasklet_ctx; | |
360 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
361 | struct mlx5_eq_pagefault pf_ctx; | |
362 | #endif | |
363 | }; | |
e126ba97 EC |
364 | }; |
365 | ||
3121e3c4 SG |
366 | struct mlx5_core_psv { |
367 | u32 psv_idx; | |
368 | struct psv_layout { | |
369 | u32 pd; | |
370 | u16 syndrome; | |
371 | u16 reserved; | |
372 | u16 bg; | |
373 | u16 app_tag; | |
374 | u32 ref_tag; | |
375 | } psv; | |
376 | }; | |
377 | ||
378 | struct mlx5_core_sig_ctx { | |
379 | struct mlx5_core_psv psv_memory; | |
380 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
381 | struct ib_sig_err err_item; |
382 | bool sig_status_checked; | |
383 | bool sig_err_exists; | |
384 | u32 sigerr_count; | |
3121e3c4 | 385 | }; |
e126ba97 | 386 | |
aa8e08d2 AK |
387 | enum { |
388 | MLX5_MKEY_MR = 1, | |
389 | MLX5_MKEY_MW, | |
390 | }; | |
391 | ||
a606b0f6 | 392 | struct mlx5_core_mkey { |
e126ba97 EC |
393 | u64 iova; |
394 | u64 size; | |
395 | u32 key; | |
396 | u32 pd; | |
aa8e08d2 | 397 | u32 type; |
e126ba97 EC |
398 | }; |
399 | ||
d9aaed83 AK |
400 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
401 | ||
5903325a | 402 | enum mlx5_res_type { |
e2013b21 | 403 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
404 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
405 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
406 | MLX5_RES_SRQ = 3, | |
407 | MLX5_RES_XSRQ = 4, | |
5903325a EC |
408 | }; |
409 | ||
410 | struct mlx5_core_rsc_common { | |
411 | enum mlx5_res_type res; | |
412 | atomic_t refcount; | |
413 | struct completion free; | |
414 | }; | |
415 | ||
e126ba97 | 416 | struct mlx5_core_srq { |
01949d01 | 417 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
418 | u32 srqn; |
419 | int max; | |
420 | int max_gs; | |
421 | int max_avail_gather; | |
422 | int wqe_shift; | |
423 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
424 | ||
425 | atomic_t refcount; | |
426 | struct completion free; | |
427 | }; | |
428 | ||
429 | struct mlx5_eq_table { | |
430 | void __iomem *update_ci; | |
431 | void __iomem *update_arm_ci; | |
233d05d2 | 432 | struct list_head comp_eqs_list; |
e126ba97 EC |
433 | struct mlx5_eq pages_eq; |
434 | struct mlx5_eq async_eq; | |
435 | struct mlx5_eq cmd_eq; | |
d9aaed83 AK |
436 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
437 | struct mlx5_eq pfault_eq; | |
438 | #endif | |
e126ba97 EC |
439 | int num_comp_vectors; |
440 | /* protect EQs list | |
441 | */ | |
442 | spinlock_t lock; | |
443 | }; | |
444 | ||
a6d51b68 | 445 | struct mlx5_uars_page { |
e126ba97 | 446 | void __iomem *map; |
a6d51b68 EC |
447 | bool wc; |
448 | u32 index; | |
449 | struct list_head list; | |
450 | unsigned int bfregs; | |
451 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
452 | unsigned long *fp_bitmap; | |
453 | unsigned int reg_avail; | |
454 | unsigned int fp_avail; | |
455 | struct kref ref_count; | |
456 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
457 | }; |
458 | ||
a6d51b68 EC |
459 | struct mlx5_bfreg_head { |
460 | /* protect blue flame registers allocations */ | |
461 | struct mutex lock; | |
462 | struct list_head list; | |
463 | }; | |
464 | ||
465 | struct mlx5_bfreg_data { | |
466 | struct mlx5_bfreg_head reg_head; | |
467 | struct mlx5_bfreg_head wc_head; | |
468 | }; | |
469 | ||
470 | struct mlx5_sq_bfreg { | |
471 | void __iomem *map; | |
472 | struct mlx5_uars_page *up; | |
473 | bool wc; | |
474 | u32 index; | |
475 | unsigned int offset; | |
476 | }; | |
e126ba97 EC |
477 | |
478 | struct mlx5_core_health { | |
479 | struct health_buffer __iomem *health; | |
480 | __be32 __iomem *health_counter; | |
481 | struct timer_list timer; | |
e126ba97 EC |
482 | u32 prev; |
483 | int miss_counter; | |
fd76ee4d | 484 | bool sick; |
05ac2c0b MHY |
485 | /* wq spinlock to synchronize draining */ |
486 | spinlock_t wq_lock; | |
ac6ea6e8 | 487 | struct workqueue_struct *wq; |
05ac2c0b | 488 | unsigned long flags; |
ac6ea6e8 | 489 | struct work_struct work; |
04c0c1ab | 490 | struct delayed_work recover_work; |
e126ba97 EC |
491 | }; |
492 | ||
493 | struct mlx5_cq_table { | |
494 | /* protect radix tree | |
495 | */ | |
496 | spinlock_t lock; | |
497 | struct radix_tree_root tree; | |
498 | }; | |
499 | ||
500 | struct mlx5_qp_table { | |
501 | /* protect radix tree | |
502 | */ | |
503 | spinlock_t lock; | |
504 | struct radix_tree_root tree; | |
505 | }; | |
506 | ||
507 | struct mlx5_srq_table { | |
508 | /* protect radix tree | |
509 | */ | |
510 | spinlock_t lock; | |
511 | struct radix_tree_root tree; | |
512 | }; | |
513 | ||
a606b0f6 | 514 | struct mlx5_mkey_table { |
3bcdb17a SG |
515 | /* protect radix tree |
516 | */ | |
517 | rwlock_t lock; | |
518 | struct radix_tree_root tree; | |
519 | }; | |
520 | ||
fc50db98 EC |
521 | struct mlx5_vf_context { |
522 | int enabled; | |
523 | }; | |
524 | ||
525 | struct mlx5_core_sriov { | |
526 | struct mlx5_vf_context *vfs_ctx; | |
527 | int num_vfs; | |
528 | int enabled_vfs; | |
529 | }; | |
530 | ||
db058a18 SM |
531 | struct mlx5_irq_info { |
532 | cpumask_var_t mask; | |
533 | char name[MLX5_MAX_IRQ_NAME]; | |
534 | }; | |
535 | ||
43a335e0 | 536 | struct mlx5_fc_stats { |
29cc6679 | 537 | struct rb_root counters; |
43a335e0 AV |
538 | struct list_head addlist; |
539 | /* protect addlist add/splice operations */ | |
540 | spinlock_t addlist_lock; | |
541 | ||
542 | struct workqueue_struct *wq; | |
543 | struct delayed_work work; | |
544 | unsigned long next_query; | |
f6dfb4c3 | 545 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
546 | }; |
547 | ||
073bb189 | 548 | struct mlx5_eswitch; |
7907f23a | 549 | struct mlx5_lag; |
d9aaed83 | 550 | struct mlx5_pagefault; |
073bb189 | 551 | |
1466cc5b YP |
552 | struct mlx5_rl_entry { |
553 | u32 rate; | |
554 | u16 index; | |
555 | u16 refcount; | |
556 | }; | |
557 | ||
558 | struct mlx5_rl_table { | |
559 | /* protect rate limit table */ | |
560 | struct mutex rl_lock; | |
561 | u16 max_size; | |
562 | u32 max_rate; | |
563 | u32 min_rate; | |
564 | struct mlx5_rl_entry *rl_entry; | |
565 | }; | |
566 | ||
d4eb4cd7 HN |
567 | enum port_module_event_status_type { |
568 | MLX5_MODULE_STATUS_PLUGGED = 0x1, | |
569 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, | |
570 | MLX5_MODULE_STATUS_ERROR = 0x3, | |
571 | MLX5_MODULE_STATUS_NUM = 0x3, | |
572 | }; | |
573 | ||
574 | enum port_module_event_error_type { | |
575 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, | |
576 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, | |
577 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, | |
578 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, | |
579 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, | |
580 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, | |
581 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, | |
582 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, | |
583 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, | |
584 | MLX5_MODULE_EVENT_ERROR_NUM, | |
585 | }; | |
586 | ||
587 | struct mlx5_port_module_event_stats { | |
588 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; | |
589 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; | |
590 | }; | |
591 | ||
e126ba97 EC |
592 | struct mlx5_priv { |
593 | char name[MLX5_MAX_NAME_LEN]; | |
594 | struct mlx5_eq_table eq_table; | |
db058a18 SM |
595 | struct msix_entry *msix_arr; |
596 | struct mlx5_irq_info *irq_info; | |
e126ba97 EC |
597 | |
598 | /* pages stuff */ | |
599 | struct workqueue_struct *pg_wq; | |
600 | struct rb_root page_root; | |
601 | int fw_pages; | |
6aec21f6 | 602 | atomic_t reg_pages; |
bf0bf77f | 603 | struct list_head free_list; |
fc50db98 | 604 | int vfs_pages; |
e126ba97 EC |
605 | |
606 | struct mlx5_core_health health; | |
607 | ||
608 | struct mlx5_srq_table srq_table; | |
609 | ||
610 | /* start: qp staff */ | |
611 | struct mlx5_qp_table qp_table; | |
612 | struct dentry *qp_debugfs; | |
613 | struct dentry *eq_debugfs; | |
614 | struct dentry *cq_debugfs; | |
615 | struct dentry *cmdif_debugfs; | |
616 | /* end: qp staff */ | |
617 | ||
618 | /* start: cq staff */ | |
619 | struct mlx5_cq_table cq_table; | |
620 | /* end: cq staff */ | |
621 | ||
a606b0f6 MB |
622 | /* start: mkey staff */ |
623 | struct mlx5_mkey_table mkey_table; | |
624 | /* end: mkey staff */ | |
3bcdb17a | 625 | |
e126ba97 | 626 | /* start: alloc staff */ |
311c7c71 SM |
627 | /* protect buffer alocation according to numa node */ |
628 | struct mutex alloc_mutex; | |
629 | int numa_node; | |
630 | ||
e126ba97 EC |
631 | struct mutex pgdir_mutex; |
632 | struct list_head pgdir_list; | |
633 | /* end: alloc staff */ | |
634 | struct dentry *dbg_root; | |
635 | ||
636 | /* protect mkey key part */ | |
637 | spinlock_t mkey_lock; | |
638 | u8 mkey_key; | |
9603b61d JM |
639 | |
640 | struct list_head dev_list; | |
641 | struct list_head ctx_list; | |
642 | spinlock_t ctx_lock; | |
073bb189 | 643 | |
fba53f7b | 644 | struct mlx5_flow_steering *steering; |
073bb189 | 645 | struct mlx5_eswitch *eswitch; |
fc50db98 | 646 | struct mlx5_core_sriov sriov; |
7907f23a | 647 | struct mlx5_lag *lag; |
fc50db98 | 648 | unsigned long pci_dev_data; |
43a335e0 | 649 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 650 | struct mlx5_rl_table rl_table; |
d4eb4cd7 HN |
651 | |
652 | struct mlx5_port_module_event_stats pme_stats; | |
d9aaed83 AK |
653 | |
654 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
655 | void (*pfault)(struct mlx5_core_dev *dev, | |
656 | void *context, | |
657 | struct mlx5_pagefault *pfault); | |
658 | void *pfault_ctx; | |
659 | struct srcu_struct pfault_srcu; | |
660 | #endif | |
a6d51b68 | 661 | struct mlx5_bfreg_data bfregs; |
01187175 | 662 | struct mlx5_uars_page *uar; |
e126ba97 EC |
663 | }; |
664 | ||
89d44f0a MD |
665 | enum mlx5_device_state { |
666 | MLX5_DEVICE_STATE_UP, | |
667 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
668 | }; | |
669 | ||
670 | enum mlx5_interface_state { | |
5fc7197d MD |
671 | MLX5_INTERFACE_STATE_DOWN = BIT(0), |
672 | MLX5_INTERFACE_STATE_UP = BIT(1), | |
673 | MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), | |
89d44f0a MD |
674 | }; |
675 | ||
676 | enum mlx5_pci_status { | |
677 | MLX5_PCI_STATUS_DISABLED, | |
678 | MLX5_PCI_STATUS_ENABLED, | |
679 | }; | |
680 | ||
d9aaed83 AK |
681 | enum mlx5_pagefault_type_flags { |
682 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
683 | MLX5_PFAULT_WRITE = 1 << 1, | |
684 | MLX5_PFAULT_RDMA = 1 << 2, | |
685 | }; | |
686 | ||
687 | /* Contains the details of a pagefault. */ | |
688 | struct mlx5_pagefault { | |
689 | u32 bytes_committed; | |
690 | u32 token; | |
691 | u8 event_subtype; | |
692 | u8 type; | |
693 | union { | |
694 | /* Initiator or send message responder pagefault details. */ | |
695 | struct { | |
696 | /* Received packet size, only valid for responders. */ | |
697 | u32 packet_size; | |
698 | /* | |
699 | * Number of resource holding WQE, depends on type. | |
700 | */ | |
701 | u32 wq_num; | |
702 | /* | |
703 | * WQE index. Refers to either the send queue or | |
704 | * receive queue, according to event_subtype. | |
705 | */ | |
706 | u16 wqe_index; | |
707 | } wqe; | |
708 | /* RDMA responder pagefault details */ | |
709 | struct { | |
710 | u32 r_key; | |
711 | /* | |
712 | * Received packet size, minimal size page fault | |
713 | * resolution required for forward progress. | |
714 | */ | |
715 | u32 packet_size; | |
716 | u32 rdma_op_len; | |
717 | u64 rdma_va; | |
718 | } rdma; | |
719 | }; | |
720 | ||
721 | struct mlx5_eq *eq; | |
722 | struct work_struct work; | |
723 | }; | |
724 | ||
b50d292b HHZ |
725 | struct mlx5_td { |
726 | struct list_head tirs_list; | |
727 | u32 tdn; | |
728 | }; | |
729 | ||
730 | struct mlx5e_resources { | |
b50d292b HHZ |
731 | u32 pdn; |
732 | struct mlx5_td td; | |
733 | struct mlx5_core_mkey mkey; | |
aff26157 | 734 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
735 | }; |
736 | ||
e126ba97 EC |
737 | struct mlx5_core_dev { |
738 | struct pci_dev *pdev; | |
89d44f0a MD |
739 | /* sync pci state */ |
740 | struct mutex pci_status_mutex; | |
741 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
742 | u8 rev_id; |
743 | char board_id[MLX5_BOARD_ID_LEN]; | |
744 | struct mlx5_cmd cmd; | |
938fe83c | 745 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 746 | struct { |
701052c5 GP |
747 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
748 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
749 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
750 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
751 | } caps; | |
e126ba97 EC |
752 | phys_addr_t iseg_base; |
753 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
754 | enum mlx5_device_state state; |
755 | /* sync interface state */ | |
756 | struct mutex intf_state_mutex; | |
5fc7197d | 757 | unsigned long intf_state; |
e126ba97 EC |
758 | void (*event) (struct mlx5_core_dev *dev, |
759 | enum mlx5_dev_event event, | |
4d2f9bbb | 760 | unsigned long param); |
e126ba97 EC |
761 | struct mlx5_priv priv; |
762 | struct mlx5_profile *profile; | |
763 | atomic_t num_qps; | |
f62b8bb8 | 764 | u32 issi; |
b50d292b | 765 | struct mlx5e_resources mlx5e_res; |
e29341fb IT |
766 | #ifdef CONFIG_MLX5_FPGA |
767 | struct mlx5_fpga_device *fpga; | |
768 | #endif | |
5a7b27eb MG |
769 | #ifdef CONFIG_RFS_ACCEL |
770 | struct cpu_rmap *rmap; | |
771 | #endif | |
e126ba97 EC |
772 | }; |
773 | ||
774 | struct mlx5_db { | |
775 | __be32 *db; | |
776 | union { | |
777 | struct mlx5_db_pgdir *pgdir; | |
778 | struct mlx5_ib_user_db_page *user_page; | |
779 | } u; | |
780 | dma_addr_t dma; | |
781 | int index; | |
782 | }; | |
783 | ||
e126ba97 EC |
784 | enum { |
785 | MLX5_COMP_EQ_SIZE = 1024, | |
786 | }; | |
787 | ||
adb0c954 SM |
788 | enum { |
789 | MLX5_PTYS_IB = 1 << 0, | |
790 | MLX5_PTYS_EN = 1 << 2, | |
791 | }; | |
792 | ||
e126ba97 EC |
793 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
794 | ||
73dd3a48 MHY |
795 | enum { |
796 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
797 | }; | |
798 | ||
e126ba97 | 799 | struct mlx5_cmd_work_ent { |
73dd3a48 | 800 | unsigned long state; |
e126ba97 EC |
801 | struct mlx5_cmd_msg *in; |
802 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
803 | void *uout; |
804 | int uout_size; | |
e126ba97 | 805 | mlx5_cmd_cbk_t callback; |
65ee6708 | 806 | struct delayed_work cb_timeout_work; |
e126ba97 | 807 | void *context; |
746b5583 | 808 | int idx; |
e126ba97 EC |
809 | struct completion done; |
810 | struct mlx5_cmd *cmd; | |
811 | struct work_struct work; | |
812 | struct mlx5_cmd_layout *lay; | |
813 | int ret; | |
814 | int page_queue; | |
815 | u8 status; | |
816 | u8 token; | |
14a70046 TG |
817 | u64 ts1; |
818 | u64 ts2; | |
746b5583 | 819 | u16 op; |
4525abea | 820 | bool polling; |
e126ba97 EC |
821 | }; |
822 | ||
823 | struct mlx5_pas { | |
824 | u64 pa; | |
825 | u8 log_sz; | |
826 | }; | |
827 | ||
707c4602 | 828 | enum port_state_policy { |
eff901d3 EC |
829 | MLX5_POLICY_DOWN = 0, |
830 | MLX5_POLICY_UP = 1, | |
831 | MLX5_POLICY_FOLLOW = 2, | |
832 | MLX5_POLICY_INVALID = 0xffffffff | |
707c4602 MD |
833 | }; |
834 | ||
835 | enum phy_port_state { | |
836 | MLX5_AAA_111 | |
837 | }; | |
838 | ||
839 | struct mlx5_hca_vport_context { | |
840 | u32 field_select; | |
841 | bool sm_virt_aware; | |
842 | bool has_smi; | |
843 | bool has_raw; | |
844 | enum port_state_policy policy; | |
845 | enum phy_port_state phys_state; | |
846 | enum ib_port_state vport_state; | |
847 | u8 port_physical_state; | |
848 | u64 sys_image_guid; | |
849 | u64 port_guid; | |
850 | u64 node_guid; | |
851 | u32 cap_mask1; | |
852 | u32 cap_mask1_perm; | |
853 | u32 cap_mask2; | |
854 | u32 cap_mask2_perm; | |
855 | u16 lid; | |
856 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
857 | u8 lmc; | |
858 | u8 subnet_timeout; | |
859 | u16 sm_lid; | |
860 | u8 sm_sl; | |
861 | u16 qkey_violation_counter; | |
862 | u16 pkey_violation_counter; | |
863 | bool grh_required; | |
864 | }; | |
865 | ||
e126ba97 EC |
866 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
867 | { | |
e126ba97 | 868 | return buf->direct.buf + offset; |
e126ba97 EC |
869 | } |
870 | ||
871 | extern struct workqueue_struct *mlx5_core_wq; | |
872 | ||
873 | #define STRUCT_FIELD(header, field) \ | |
874 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
875 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
876 | ||
e126ba97 EC |
877 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
878 | { | |
879 | return pci_get_drvdata(pdev); | |
880 | } | |
881 | ||
882 | extern struct dentry *mlx5_debugfs_root; | |
883 | ||
884 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
885 | { | |
886 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
887 | } | |
888 | ||
889 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
890 | { | |
891 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
892 | } | |
893 | ||
894 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
895 | { | |
896 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
897 | } | |
898 | ||
899 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
900 | { | |
901 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
902 | } | |
903 | ||
3bcdb17a SG |
904 | static inline u32 mlx5_base_mkey(const u32 key) |
905 | { | |
906 | return key & 0xffffff00u; | |
907 | } | |
908 | ||
e126ba97 EC |
909 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
910 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
911 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
912 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 913 | |
e126ba97 EC |
914 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
915 | int out_size); | |
746b5583 EC |
916 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
917 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
918 | void *context); | |
4525abea MD |
919 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
920 | void *out, int out_size); | |
c4f287c4 SM |
921 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
922 | ||
923 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
924 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
925 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
926 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
927 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
928 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
929 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
05ac2c0b | 930 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 931 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
311c7c71 SM |
932 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
933 | struct mlx5_buf *buf, int node); | |
64ffaa21 | 934 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 | 935 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
1c1b5228 TT |
936 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
937 | struct mlx5_frag_buf *buf, int node); | |
938 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
939 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
940 | gfp_t flags, int npages); | |
941 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
942 | struct mlx5_cmd_mailbox *head); | |
943 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 944 | struct mlx5_srq_attr *in); |
e126ba97 EC |
945 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
946 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 947 | struct mlx5_srq_attr *out); |
e126ba97 EC |
948 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
949 | u16 lwm, int is_srq); | |
a606b0f6 MB |
950 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
951 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
952 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
953 | struct mlx5_core_mkey *mkey, | |
954 | u32 *in, int inlen, | |
955 | u32 *out, int outlen, | |
956 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
957 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
958 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 959 | u32 *in, int inlen); |
a606b0f6 MB |
960 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
961 | struct mlx5_core_mkey *mkey); | |
962 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 963 | u32 *out, int outlen); |
a606b0f6 | 964 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, |
e126ba97 EC |
965 | u32 *mkey); |
966 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
967 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 968 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 969 | u16 opmod, u8 port); |
e126ba97 EC |
970 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
971 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
972 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
973 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
974 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 975 | s32 npages); |
cd23b14b | 976 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
977 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
978 | void mlx5_register_debugfs(void); | |
979 | void mlx5_unregister_debugfs(void); | |
980 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
981 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
982 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
1c1b5228 | 983 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
e126ba97 | 984 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); |
5903325a | 985 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e126ba97 EC |
986 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
987 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
73dd3a48 | 988 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); |
e126ba97 EC |
989 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
990 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
d9aaed83 | 991 | int nent, u64 mask, const char *name, |
01187175 | 992 | enum mlx5_eq_type type); |
e126ba97 EC |
993 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
994 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
995 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
0b6e26ce DT |
996 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
997 | unsigned int *irqn); | |
e126ba97 EC |
998 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
999 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
1000 | ||
1001 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
1002 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1003 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
1004 | int size_in, void *data_out, int size_out, | |
1005 | u16 reg_num, int arg, int write); | |
adb0c954 | 1006 | |
e126ba97 EC |
1007 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
1008 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
1009 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
73b626c1 | 1010 | u32 *out, int outlen); |
e126ba97 EC |
1011 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); |
1012 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1013 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
1014 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1015 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
311c7c71 SM |
1016 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
1017 | int node); | |
e126ba97 EC |
1018 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
1019 | ||
e126ba97 EC |
1020 | const char *mlx5_command_str(int command); |
1021 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
1022 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
1023 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
1024 | int npsvs, u32 *sig_index); | |
1025 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1026 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1027 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1028 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1029 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1030 | u8 port_num, void *out, size_t sz); | |
d9aaed83 AK |
1031 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1032 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, | |
1033 | u32 wq_num, u8 type, int error); | |
1034 | #endif | |
e126ba97 | 1035 | |
1466cc5b YP |
1036 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1037 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
1038 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); | |
1039 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); | |
1040 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); | |
a6d51b68 EC |
1041 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1042 | bool map_wc, bool fast_path); | |
1043 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1044 | |
e3297246 EC |
1045 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1046 | { | |
1047 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1048 | } | |
1049 | ||
e126ba97 EC |
1050 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1051 | { | |
1052 | return mkey >> 8; | |
1053 | } | |
1054 | ||
1055 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1056 | { | |
1057 | return mkey_idx << 8; | |
1058 | } | |
1059 | ||
746b5583 EC |
1060 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1061 | { | |
1062 | return mkey & 0xff; | |
1063 | } | |
1064 | ||
e126ba97 EC |
1065 | enum { |
1066 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1067 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1068 | }; |
1069 | ||
1070 | enum { | |
49780d42 | 1071 | MAX_UMR_CACHE_ENTRY = 20, |
81713d37 AK |
1072 | MLX5_IMR_MTT_CACHE_ENTRY, |
1073 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1074 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1075 | }; |
1076 | ||
64613d94 SM |
1077 | enum { |
1078 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1079 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1080 | }; | |
1081 | ||
9603b61d JM |
1082 | struct mlx5_interface { |
1083 | void * (*add)(struct mlx5_core_dev *dev); | |
1084 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1085 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1086 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 1087 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1088 | enum mlx5_dev_event event, unsigned long param); |
d9aaed83 AK |
1089 | void (*pfault)(struct mlx5_core_dev *dev, |
1090 | void *context, | |
1091 | struct mlx5_pagefault *pfault); | |
64613d94 SM |
1092 | void * (*get_dev)(void *context); |
1093 | int protocol; | |
9603b61d JM |
1094 | struct list_head list; |
1095 | }; | |
1096 | ||
64613d94 | 1097 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
1098 | int mlx5_register_interface(struct mlx5_interface *intf); |
1099 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 1100 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1101 | |
3bc34f3b AH |
1102 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1103 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 1104 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1105 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
01187175 EC |
1106 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1107 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1108 | |
693dfd5a ES |
1109 | #ifndef CONFIG_MLX5_CORE_IPOIB |
1110 | static inline | |
1111 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1112 | struct ib_device *ibdev, | |
1113 | const char *name, | |
1114 | void (*setup)(struct net_device *)) | |
1115 | { | |
1116 | return ERR_PTR(-EOPNOTSUPP); | |
1117 | } | |
1118 | ||
1119 | static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {} | |
1120 | #else | |
1121 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1122 | struct ib_device *ibdev, | |
1123 | const char *name, | |
1124 | void (*setup)(struct net_device *)); | |
1125 | void mlx5_rdma_netdev_free(struct net_device *netdev); | |
1126 | #endif /* CONFIG_MLX5_CORE_IPOIB */ | |
1127 | ||
e126ba97 EC |
1128 | struct mlx5_profile { |
1129 | u64 mask; | |
f241e749 | 1130 | u8 log_max_qp; |
e126ba97 EC |
1131 | struct { |
1132 | int size; | |
1133 | int limit; | |
1134 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1135 | }; | |
1136 | ||
fc50db98 EC |
1137 | enum { |
1138 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1139 | }; | |
1140 | ||
1141 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1142 | { | |
1143 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1144 | } | |
1145 | ||
707c4602 MD |
1146 | static inline int mlx5_get_gid_table_len(u16 param) |
1147 | { | |
1148 | if (param > 4) { | |
1149 | pr_warn("gid table length is zero\n"); | |
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | return 8 * (1 << param); | |
1154 | } | |
1155 | ||
1466cc5b YP |
1156 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1157 | { | |
1158 | return !!(dev->priv.rl_table.max_size); | |
1159 | } | |
1160 | ||
020446e0 EC |
1161 | enum { |
1162 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1163 | }; | |
1164 | ||
e126ba97 | 1165 | #endif /* MLX5_DRIVER_H */ |