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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
43a335e0 | 44 | #include <linux/workqueue.h> |
d9aaed83 | 45 | #include <linux/mempool.h> |
94c6825e | 46 | #include <linux/interrupt.h> |
52ec462e | 47 | #include <linux/idr.h> |
6ecde51d | 48 | |
e126ba97 EC |
49 | #include <linux/mlx5/device.h> |
50 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 51 | #include <linux/mlx5/srq.h> |
7c39afb3 FD |
52 | #include <linux/timecounter.h> |
53 | #include <linux/ptp_clock_kernel.h> | |
e126ba97 EC |
54 | |
55 | enum { | |
56 | MLX5_BOARD_ID_LEN = 64, | |
57 | MLX5_MAX_NAME_LEN = 16, | |
58 | }; | |
59 | ||
60 | enum { | |
61 | /* one minute for the sake of bringup. Generally, commands must always | |
62 | * complete and we may need to increase this timeout value | |
63 | */ | |
6b6c07bd | 64 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
65 | MLX5_CMD_WQ_MAX_NAME = 32, |
66 | }; | |
67 | ||
68 | enum { | |
69 | CMD_OWNER_SW = 0x0, | |
70 | CMD_OWNER_HW = 0x1, | |
71 | CMD_STATUS_SUCCESS = 0, | |
72 | }; | |
73 | ||
74 | enum mlx5_sqp_t { | |
75 | MLX5_SQP_SMI = 0, | |
76 | MLX5_SQP_GSI = 1, | |
77 | MLX5_SQP_IEEE_1588 = 2, | |
78 | MLX5_SQP_SNIFFER = 3, | |
79 | MLX5_SQP_SYNC_UMR = 4, | |
80 | }; | |
81 | ||
82 | enum { | |
83 | MLX5_MAX_PORTS = 2, | |
84 | }; | |
85 | ||
86 | enum { | |
87 | MLX5_EQ_VEC_PAGES = 0, | |
88 | MLX5_EQ_VEC_CMD = 1, | |
89 | MLX5_EQ_VEC_ASYNC = 2, | |
d9aaed83 | 90 | MLX5_EQ_VEC_PFAULT = 3, |
e126ba97 EC |
91 | MLX5_EQ_VEC_COMP_BASE, |
92 | }; | |
93 | ||
94 | enum { | |
db058a18 | 95 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
96 | }; |
97 | ||
98 | enum { | |
99 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
100 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
101 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
102 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
103 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
104 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
105 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
106 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
107 | }; | |
108 | ||
e126ba97 | 109 | enum { |
415a64aa | 110 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
111 | MLX5_REG_QETCR = 0x4005, |
112 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 113 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 114 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
115 | MLX5_REG_DCBX_PARAM = 0x4020, |
116 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
117 | MLX5_REG_FPGA_CAP = 0x4022, |
118 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 119 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
e126ba97 EC |
120 | MLX5_REG_PCAP = 0x5001, |
121 | MLX5_REG_PMTU = 0x5003, | |
122 | MLX5_REG_PTYS = 0x5004, | |
123 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 124 | MLX5_REG_PFCC = 0x5007, |
efea389d | 125 | MLX5_REG_PPCNT = 0x5008, |
e126ba97 EC |
126 | MLX5_REG_PMAOS = 0x5012, |
127 | MLX5_REG_PUDE = 0x5009, | |
128 | MLX5_REG_PMPE = 0x5010, | |
129 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 130 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 131 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 132 | MLX5_REG_PMLP = 0x5002, |
cfdcbcea | 133 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
134 | MLX5_REG_NODE_DESC = 0x6001, |
135 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 136 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 137 | MLX5_REG_MLCR = 0x902b, |
8ed1a630 | 138 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
139 | MLX5_REG_MTPPS = 0x9053, |
140 | MLX5_REG_MTPPSE = 0x9054, | |
47176289 OG |
141 | MLX5_REG_MCQI = 0x9061, |
142 | MLX5_REG_MCC = 0x9062, | |
143 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 144 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
145 | }; |
146 | ||
415a64aa HN |
147 | enum mlx5_qpts_trust_state { |
148 | MLX5_QPTS_TRUST_PCP = 1, | |
149 | MLX5_QPTS_TRUST_DSCP = 2, | |
150 | }; | |
151 | ||
341c5ee2 HN |
152 | enum mlx5_dcbx_oper_mode { |
153 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
154 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
155 | }; | |
156 | ||
57cda166 MS |
157 | enum mlx5_dct_atomic_mode { |
158 | MLX5_ATOMIC_MODE_DCT_OFF = 20, | |
159 | MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, | |
160 | MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, | |
161 | MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, | |
162 | }; | |
163 | ||
da7525d2 EBE |
164 | enum { |
165 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
166 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
167 | }; | |
168 | ||
e420f0c0 HE |
169 | enum mlx5_page_fault_resume_flags { |
170 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
171 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
172 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
173 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
174 | }; | |
175 | ||
e126ba97 EC |
176 | enum dbg_rsc_type { |
177 | MLX5_DBG_RSC_QP, | |
178 | MLX5_DBG_RSC_EQ, | |
179 | MLX5_DBG_RSC_CQ, | |
180 | }; | |
181 | ||
7ecf6d8f BW |
182 | enum port_state_policy { |
183 | MLX5_POLICY_DOWN = 0, | |
184 | MLX5_POLICY_UP = 1, | |
185 | MLX5_POLICY_FOLLOW = 2, | |
186 | MLX5_POLICY_INVALID = 0xffffffff | |
187 | }; | |
188 | ||
e126ba97 EC |
189 | struct mlx5_field_desc { |
190 | struct dentry *dent; | |
191 | int i; | |
192 | }; | |
193 | ||
194 | struct mlx5_rsc_debug { | |
195 | struct mlx5_core_dev *dev; | |
196 | void *object; | |
197 | enum dbg_rsc_type type; | |
198 | struct dentry *root; | |
199 | struct mlx5_field_desc fields[0]; | |
200 | }; | |
201 | ||
202 | enum mlx5_dev_event { | |
203 | MLX5_DEV_EVENT_SYS_ERROR, | |
204 | MLX5_DEV_EVENT_PORT_UP, | |
205 | MLX5_DEV_EVENT_PORT_DOWN, | |
206 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
207 | MLX5_DEV_EVENT_LID_CHANGE, | |
208 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
209 | MLX5_DEV_EVENT_GUID_CHANGE, | |
210 | MLX5_DEV_EVENT_CLIENT_REREG, | |
f9a1ef72 | 211 | MLX5_DEV_EVENT_PPS, |
246ac981 | 212 | MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, |
e126ba97 EC |
213 | }; |
214 | ||
4c916a79 | 215 | enum mlx5_port_status { |
6fa1bcab AS |
216 | MLX5_PORT_UP = 1, |
217 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
218 | }; |
219 | ||
d9aaed83 AK |
220 | enum mlx5_eq_type { |
221 | MLX5_EQ_TYPE_COMP, | |
222 | MLX5_EQ_TYPE_ASYNC, | |
223 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
224 | MLX5_EQ_TYPE_PF, | |
225 | #endif | |
226 | }; | |
227 | ||
2f5ff264 | 228 | struct mlx5_bfreg_info { |
b037c29a | 229 | u32 *sys_pages; |
2f5ff264 | 230 | int num_low_latency_bfregs; |
e126ba97 | 231 | unsigned int *count; |
e126ba97 EC |
232 | |
233 | /* | |
2f5ff264 | 234 | * protect bfreg allocation data structs |
e126ba97 EC |
235 | */ |
236 | struct mutex lock; | |
78c0f98c | 237 | u32 ver; |
b037c29a EC |
238 | bool lib_uar_4k; |
239 | u32 num_sys_pages; | |
31a78a5a YH |
240 | u32 num_static_sys_pages; |
241 | u32 total_num_bfregs; | |
242 | u32 num_dyn_bfregs; | |
e126ba97 EC |
243 | }; |
244 | ||
245 | struct mlx5_cmd_first { | |
246 | __be32 data[4]; | |
247 | }; | |
248 | ||
249 | struct mlx5_cmd_msg { | |
250 | struct list_head list; | |
0ac3ea70 | 251 | struct cmd_msg_cache *parent; |
e126ba97 EC |
252 | u32 len; |
253 | struct mlx5_cmd_first first; | |
254 | struct mlx5_cmd_mailbox *next; | |
255 | }; | |
256 | ||
257 | struct mlx5_cmd_debug { | |
258 | struct dentry *dbg_root; | |
259 | struct dentry *dbg_in; | |
260 | struct dentry *dbg_out; | |
261 | struct dentry *dbg_outlen; | |
262 | struct dentry *dbg_status; | |
263 | struct dentry *dbg_run; | |
264 | void *in_msg; | |
265 | void *out_msg; | |
266 | u8 status; | |
267 | u16 inlen; | |
268 | u16 outlen; | |
269 | }; | |
270 | ||
0ac3ea70 | 271 | struct cmd_msg_cache { |
e126ba97 EC |
272 | /* protect block chain allocations |
273 | */ | |
274 | spinlock_t lock; | |
275 | struct list_head head; | |
0ac3ea70 MHY |
276 | unsigned int max_inbox_size; |
277 | unsigned int num_ent; | |
e126ba97 EC |
278 | }; |
279 | ||
0ac3ea70 MHY |
280 | enum { |
281 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
282 | }; |
283 | ||
284 | struct mlx5_cmd_stats { | |
285 | u64 sum; | |
286 | u64 n; | |
287 | struct dentry *root; | |
288 | struct dentry *avg; | |
289 | struct dentry *count; | |
290 | /* protect command average calculations */ | |
291 | spinlock_t lock; | |
292 | }; | |
293 | ||
294 | struct mlx5_cmd { | |
64599cca EC |
295 | void *cmd_alloc_buf; |
296 | dma_addr_t alloc_dma; | |
297 | int alloc_size; | |
e126ba97 EC |
298 | void *cmd_buf; |
299 | dma_addr_t dma; | |
300 | u16 cmdif_rev; | |
301 | u8 log_sz; | |
302 | u8 log_stride; | |
303 | int max_reg_cmds; | |
304 | int events; | |
305 | u32 __iomem *vector; | |
306 | ||
307 | /* protect command queue allocations | |
308 | */ | |
309 | spinlock_t alloc_lock; | |
310 | ||
311 | /* protect token allocations | |
312 | */ | |
313 | spinlock_t token_lock; | |
314 | u8 token; | |
315 | unsigned long bitmask; | |
316 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
317 | struct workqueue_struct *wq; | |
318 | struct semaphore sem; | |
319 | struct semaphore pages_sem; | |
320 | int mode; | |
321 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 322 | struct dma_pool *pool; |
e126ba97 | 323 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 324 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
325 | int checksum_disabled; |
326 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
327 | }; | |
328 | ||
329 | struct mlx5_port_caps { | |
330 | int gid_table_len; | |
331 | int pkey_table_len; | |
938fe83c | 332 | u8 ext_port_cap; |
c43f1112 | 333 | bool has_smi; |
e126ba97 EC |
334 | }; |
335 | ||
336 | struct mlx5_cmd_mailbox { | |
337 | void *buf; | |
338 | dma_addr_t dma; | |
339 | struct mlx5_cmd_mailbox *next; | |
340 | }; | |
341 | ||
342 | struct mlx5_buf_list { | |
343 | void *buf; | |
344 | dma_addr_t map; | |
345 | }; | |
346 | ||
347 | struct mlx5_buf { | |
348 | struct mlx5_buf_list direct; | |
e126ba97 | 349 | int npages; |
e126ba97 | 350 | int size; |
f241e749 | 351 | u8 page_shift; |
e126ba97 EC |
352 | }; |
353 | ||
1c1b5228 TT |
354 | struct mlx5_frag_buf { |
355 | struct mlx5_buf_list *frags; | |
356 | int npages; | |
357 | int size; | |
358 | u8 page_shift; | |
359 | }; | |
360 | ||
94c6825e MB |
361 | struct mlx5_eq_tasklet { |
362 | struct list_head list; | |
363 | struct list_head process_list; | |
364 | struct tasklet_struct task; | |
365 | /* lock on completion tasklet list */ | |
366 | spinlock_t lock; | |
367 | }; | |
368 | ||
d9aaed83 AK |
369 | struct mlx5_eq_pagefault { |
370 | struct work_struct work; | |
371 | /* Pagefaults lock */ | |
372 | spinlock_t lock; | |
373 | struct workqueue_struct *wq; | |
374 | mempool_t *pool; | |
375 | }; | |
376 | ||
e126ba97 EC |
377 | struct mlx5_eq { |
378 | struct mlx5_core_dev *dev; | |
379 | __be32 __iomem *doorbell; | |
380 | u32 cons_index; | |
381 | struct mlx5_buf buf; | |
382 | int size; | |
0b6e26ce | 383 | unsigned int irqn; |
e126ba97 EC |
384 | u8 eqn; |
385 | int nent; | |
386 | u64 mask; | |
e126ba97 EC |
387 | struct list_head list; |
388 | int index; | |
389 | struct mlx5_rsc_debug *dbg; | |
d9aaed83 AK |
390 | enum mlx5_eq_type type; |
391 | union { | |
392 | struct mlx5_eq_tasklet tasklet_ctx; | |
393 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
394 | struct mlx5_eq_pagefault pf_ctx; | |
395 | #endif | |
396 | }; | |
e126ba97 EC |
397 | }; |
398 | ||
3121e3c4 SG |
399 | struct mlx5_core_psv { |
400 | u32 psv_idx; | |
401 | struct psv_layout { | |
402 | u32 pd; | |
403 | u16 syndrome; | |
404 | u16 reserved; | |
405 | u16 bg; | |
406 | u16 app_tag; | |
407 | u32 ref_tag; | |
408 | } psv; | |
409 | }; | |
410 | ||
411 | struct mlx5_core_sig_ctx { | |
412 | struct mlx5_core_psv psv_memory; | |
413 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
414 | struct ib_sig_err err_item; |
415 | bool sig_status_checked; | |
416 | bool sig_err_exists; | |
417 | u32 sigerr_count; | |
3121e3c4 | 418 | }; |
e126ba97 | 419 | |
aa8e08d2 AK |
420 | enum { |
421 | MLX5_MKEY_MR = 1, | |
422 | MLX5_MKEY_MW, | |
423 | }; | |
424 | ||
a606b0f6 | 425 | struct mlx5_core_mkey { |
e126ba97 EC |
426 | u64 iova; |
427 | u64 size; | |
428 | u32 key; | |
429 | u32 pd; | |
aa8e08d2 | 430 | u32 type; |
e126ba97 EC |
431 | }; |
432 | ||
d9aaed83 AK |
433 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
434 | ||
5903325a | 435 | enum mlx5_res_type { |
e2013b21 | 436 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
437 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
438 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
439 | MLX5_RES_SRQ = 3, | |
440 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 441 | MLX5_RES_XRQ = 5, |
57cda166 | 442 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
443 | }; |
444 | ||
445 | struct mlx5_core_rsc_common { | |
446 | enum mlx5_res_type res; | |
447 | atomic_t refcount; | |
448 | struct completion free; | |
449 | }; | |
450 | ||
e126ba97 | 451 | struct mlx5_core_srq { |
01949d01 | 452 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
453 | u32 srqn; |
454 | int max; | |
455 | int max_gs; | |
456 | int max_avail_gather; | |
457 | int wqe_shift; | |
458 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
459 | ||
460 | atomic_t refcount; | |
461 | struct completion free; | |
462 | }; | |
463 | ||
464 | struct mlx5_eq_table { | |
465 | void __iomem *update_ci; | |
466 | void __iomem *update_arm_ci; | |
233d05d2 | 467 | struct list_head comp_eqs_list; |
e126ba97 EC |
468 | struct mlx5_eq pages_eq; |
469 | struct mlx5_eq async_eq; | |
470 | struct mlx5_eq cmd_eq; | |
d9aaed83 AK |
471 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
472 | struct mlx5_eq pfault_eq; | |
473 | #endif | |
e126ba97 EC |
474 | int num_comp_vectors; |
475 | /* protect EQs list | |
476 | */ | |
477 | spinlock_t lock; | |
478 | }; | |
479 | ||
a6d51b68 | 480 | struct mlx5_uars_page { |
e126ba97 | 481 | void __iomem *map; |
a6d51b68 EC |
482 | bool wc; |
483 | u32 index; | |
484 | struct list_head list; | |
485 | unsigned int bfregs; | |
486 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
487 | unsigned long *fp_bitmap; | |
488 | unsigned int reg_avail; | |
489 | unsigned int fp_avail; | |
490 | struct kref ref_count; | |
491 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
492 | }; |
493 | ||
a6d51b68 EC |
494 | struct mlx5_bfreg_head { |
495 | /* protect blue flame registers allocations */ | |
496 | struct mutex lock; | |
497 | struct list_head list; | |
498 | }; | |
499 | ||
500 | struct mlx5_bfreg_data { | |
501 | struct mlx5_bfreg_head reg_head; | |
502 | struct mlx5_bfreg_head wc_head; | |
503 | }; | |
504 | ||
505 | struct mlx5_sq_bfreg { | |
506 | void __iomem *map; | |
507 | struct mlx5_uars_page *up; | |
508 | bool wc; | |
509 | u32 index; | |
510 | unsigned int offset; | |
511 | }; | |
e126ba97 EC |
512 | |
513 | struct mlx5_core_health { | |
514 | struct health_buffer __iomem *health; | |
515 | __be32 __iomem *health_counter; | |
516 | struct timer_list timer; | |
e126ba97 EC |
517 | u32 prev; |
518 | int miss_counter; | |
fd76ee4d | 519 | bool sick; |
05ac2c0b MHY |
520 | /* wq spinlock to synchronize draining */ |
521 | spinlock_t wq_lock; | |
ac6ea6e8 | 522 | struct workqueue_struct *wq; |
05ac2c0b | 523 | unsigned long flags; |
ac6ea6e8 | 524 | struct work_struct work; |
04c0c1ab | 525 | struct delayed_work recover_work; |
e126ba97 EC |
526 | }; |
527 | ||
528 | struct mlx5_cq_table { | |
529 | /* protect radix tree | |
530 | */ | |
531 | spinlock_t lock; | |
532 | struct radix_tree_root tree; | |
533 | }; | |
534 | ||
535 | struct mlx5_qp_table { | |
536 | /* protect radix tree | |
537 | */ | |
538 | spinlock_t lock; | |
539 | struct radix_tree_root tree; | |
540 | }; | |
541 | ||
542 | struct mlx5_srq_table { | |
543 | /* protect radix tree | |
544 | */ | |
545 | spinlock_t lock; | |
546 | struct radix_tree_root tree; | |
547 | }; | |
548 | ||
a606b0f6 | 549 | struct mlx5_mkey_table { |
3bcdb17a SG |
550 | /* protect radix tree |
551 | */ | |
552 | rwlock_t lock; | |
553 | struct radix_tree_root tree; | |
554 | }; | |
555 | ||
fc50db98 EC |
556 | struct mlx5_vf_context { |
557 | int enabled; | |
7ecf6d8f BW |
558 | u64 port_guid; |
559 | u64 node_guid; | |
560 | enum port_state_policy policy; | |
fc50db98 EC |
561 | }; |
562 | ||
563 | struct mlx5_core_sriov { | |
564 | struct mlx5_vf_context *vfs_ctx; | |
565 | int num_vfs; | |
566 | int enabled_vfs; | |
567 | }; | |
568 | ||
db058a18 | 569 | struct mlx5_irq_info { |
db058a18 SM |
570 | char name[MLX5_MAX_IRQ_NAME]; |
571 | }; | |
572 | ||
43a335e0 | 573 | struct mlx5_fc_stats { |
29cc6679 | 574 | struct rb_root counters; |
43a335e0 AV |
575 | struct list_head addlist; |
576 | /* protect addlist add/splice operations */ | |
577 | spinlock_t addlist_lock; | |
578 | ||
579 | struct workqueue_struct *wq; | |
580 | struct delayed_work work; | |
581 | unsigned long next_query; | |
f6dfb4c3 | 582 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
583 | }; |
584 | ||
eeb66cdb | 585 | struct mlx5_mpfs; |
073bb189 | 586 | struct mlx5_eswitch; |
7907f23a | 587 | struct mlx5_lag; |
d9aaed83 | 588 | struct mlx5_pagefault; |
073bb189 | 589 | |
1466cc5b YP |
590 | struct mlx5_rl_entry { |
591 | u32 rate; | |
592 | u16 index; | |
593 | u16 refcount; | |
594 | }; | |
595 | ||
596 | struct mlx5_rl_table { | |
597 | /* protect rate limit table */ | |
598 | struct mutex rl_lock; | |
599 | u16 max_size; | |
600 | u32 max_rate; | |
601 | u32 min_rate; | |
602 | struct mlx5_rl_entry *rl_entry; | |
603 | }; | |
604 | ||
d4eb4cd7 HN |
605 | enum port_module_event_status_type { |
606 | MLX5_MODULE_STATUS_PLUGGED = 0x1, | |
607 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, | |
608 | MLX5_MODULE_STATUS_ERROR = 0x3, | |
609 | MLX5_MODULE_STATUS_NUM = 0x3, | |
610 | }; | |
611 | ||
612 | enum port_module_event_error_type { | |
613 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, | |
614 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, | |
615 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, | |
616 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, | |
617 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, | |
618 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, | |
619 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, | |
620 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, | |
621 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, | |
622 | MLX5_MODULE_EVENT_ERROR_NUM, | |
623 | }; | |
624 | ||
625 | struct mlx5_port_module_event_stats { | |
626 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; | |
627 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; | |
628 | }; | |
629 | ||
e126ba97 EC |
630 | struct mlx5_priv { |
631 | char name[MLX5_MAX_NAME_LEN]; | |
632 | struct mlx5_eq_table eq_table; | |
db058a18 | 633 | struct mlx5_irq_info *irq_info; |
e126ba97 EC |
634 | |
635 | /* pages stuff */ | |
636 | struct workqueue_struct *pg_wq; | |
637 | struct rb_root page_root; | |
638 | int fw_pages; | |
6aec21f6 | 639 | atomic_t reg_pages; |
bf0bf77f | 640 | struct list_head free_list; |
fc50db98 | 641 | int vfs_pages; |
e126ba97 EC |
642 | |
643 | struct mlx5_core_health health; | |
644 | ||
645 | struct mlx5_srq_table srq_table; | |
646 | ||
647 | /* start: qp staff */ | |
648 | struct mlx5_qp_table qp_table; | |
649 | struct dentry *qp_debugfs; | |
650 | struct dentry *eq_debugfs; | |
651 | struct dentry *cq_debugfs; | |
652 | struct dentry *cmdif_debugfs; | |
653 | /* end: qp staff */ | |
654 | ||
655 | /* start: cq staff */ | |
656 | struct mlx5_cq_table cq_table; | |
657 | /* end: cq staff */ | |
658 | ||
a606b0f6 MB |
659 | /* start: mkey staff */ |
660 | struct mlx5_mkey_table mkey_table; | |
661 | /* end: mkey staff */ | |
3bcdb17a | 662 | |
e126ba97 | 663 | /* start: alloc staff */ |
311c7c71 SM |
664 | /* protect buffer alocation according to numa node */ |
665 | struct mutex alloc_mutex; | |
666 | int numa_node; | |
667 | ||
e126ba97 EC |
668 | struct mutex pgdir_mutex; |
669 | struct list_head pgdir_list; | |
670 | /* end: alloc staff */ | |
671 | struct dentry *dbg_root; | |
672 | ||
673 | /* protect mkey key part */ | |
674 | spinlock_t mkey_lock; | |
675 | u8 mkey_key; | |
9603b61d JM |
676 | |
677 | struct list_head dev_list; | |
678 | struct list_head ctx_list; | |
679 | spinlock_t ctx_lock; | |
073bb189 | 680 | |
97834eba ES |
681 | struct list_head waiting_events_list; |
682 | bool is_accum_events; | |
683 | ||
fba53f7b | 684 | struct mlx5_flow_steering *steering; |
eeb66cdb | 685 | struct mlx5_mpfs *mpfs; |
073bb189 | 686 | struct mlx5_eswitch *eswitch; |
fc50db98 | 687 | struct mlx5_core_sriov sriov; |
7907f23a | 688 | struct mlx5_lag *lag; |
fc50db98 | 689 | unsigned long pci_dev_data; |
43a335e0 | 690 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 691 | struct mlx5_rl_table rl_table; |
d4eb4cd7 HN |
692 | |
693 | struct mlx5_port_module_event_stats pme_stats; | |
d9aaed83 AK |
694 | |
695 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
696 | void (*pfault)(struct mlx5_core_dev *dev, | |
697 | void *context, | |
698 | struct mlx5_pagefault *pfault); | |
699 | void *pfault_ctx; | |
700 | struct srcu_struct pfault_srcu; | |
701 | #endif | |
a6d51b68 | 702 | struct mlx5_bfreg_data bfregs; |
01187175 | 703 | struct mlx5_uars_page *uar; |
e126ba97 EC |
704 | }; |
705 | ||
89d44f0a MD |
706 | enum mlx5_device_state { |
707 | MLX5_DEVICE_STATE_UP, | |
708 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
709 | }; | |
710 | ||
711 | enum mlx5_interface_state { | |
b3cb5388 | 712 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
713 | }; |
714 | ||
715 | enum mlx5_pci_status { | |
716 | MLX5_PCI_STATUS_DISABLED, | |
717 | MLX5_PCI_STATUS_ENABLED, | |
718 | }; | |
719 | ||
d9aaed83 AK |
720 | enum mlx5_pagefault_type_flags { |
721 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
722 | MLX5_PFAULT_WRITE = 1 << 1, | |
723 | MLX5_PFAULT_RDMA = 1 << 2, | |
724 | }; | |
725 | ||
726 | /* Contains the details of a pagefault. */ | |
727 | struct mlx5_pagefault { | |
728 | u32 bytes_committed; | |
729 | u32 token; | |
730 | u8 event_subtype; | |
731 | u8 type; | |
732 | union { | |
733 | /* Initiator or send message responder pagefault details. */ | |
734 | struct { | |
735 | /* Received packet size, only valid for responders. */ | |
736 | u32 packet_size; | |
737 | /* | |
738 | * Number of resource holding WQE, depends on type. | |
739 | */ | |
740 | u32 wq_num; | |
741 | /* | |
742 | * WQE index. Refers to either the send queue or | |
743 | * receive queue, according to event_subtype. | |
744 | */ | |
745 | u16 wqe_index; | |
746 | } wqe; | |
747 | /* RDMA responder pagefault details */ | |
748 | struct { | |
749 | u32 r_key; | |
750 | /* | |
751 | * Received packet size, minimal size page fault | |
752 | * resolution required for forward progress. | |
753 | */ | |
754 | u32 packet_size; | |
755 | u32 rdma_op_len; | |
756 | u64 rdma_va; | |
757 | } rdma; | |
758 | }; | |
759 | ||
760 | struct mlx5_eq *eq; | |
761 | struct work_struct work; | |
762 | }; | |
763 | ||
b50d292b HHZ |
764 | struct mlx5_td { |
765 | struct list_head tirs_list; | |
766 | u32 tdn; | |
767 | }; | |
768 | ||
769 | struct mlx5e_resources { | |
b50d292b HHZ |
770 | u32 pdn; |
771 | struct mlx5_td td; | |
772 | struct mlx5_core_mkey mkey; | |
aff26157 | 773 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
774 | }; |
775 | ||
52ec462e IT |
776 | #define MLX5_MAX_RESERVED_GIDS 8 |
777 | ||
778 | struct mlx5_rsvd_gids { | |
779 | unsigned int start; | |
780 | unsigned int count; | |
781 | struct ida ida; | |
782 | }; | |
783 | ||
7c39afb3 FD |
784 | #define MAX_PIN_NUM 8 |
785 | struct mlx5_pps { | |
786 | u8 pin_caps[MAX_PIN_NUM]; | |
787 | struct work_struct out_work; | |
788 | u64 start[MAX_PIN_NUM]; | |
789 | u8 enabled; | |
790 | }; | |
791 | ||
792 | struct mlx5_clock { | |
793 | rwlock_t lock; | |
794 | struct cyclecounter cycles; | |
795 | struct timecounter tc; | |
796 | struct hwtstamp_config hwtstamp_config; | |
797 | u32 nominal_c_mult; | |
798 | unsigned long overflow_period; | |
799 | struct delayed_work overflow_work; | |
800 | struct ptp_clock *ptp; | |
801 | struct ptp_clock_info ptp_info; | |
802 | struct mlx5_pps pps_info; | |
803 | }; | |
804 | ||
e126ba97 EC |
805 | struct mlx5_core_dev { |
806 | struct pci_dev *pdev; | |
89d44f0a MD |
807 | /* sync pci state */ |
808 | struct mutex pci_status_mutex; | |
809 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
810 | u8 rev_id; |
811 | char board_id[MLX5_BOARD_ID_LEN]; | |
812 | struct mlx5_cmd cmd; | |
938fe83c | 813 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 814 | struct { |
701052c5 GP |
815 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
816 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
817 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
818 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 819 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 820 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
71862561 | 821 | } caps; |
e126ba97 EC |
822 | phys_addr_t iseg_base; |
823 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
824 | enum mlx5_device_state state; |
825 | /* sync interface state */ | |
826 | struct mutex intf_state_mutex; | |
5fc7197d | 827 | unsigned long intf_state; |
e126ba97 EC |
828 | void (*event) (struct mlx5_core_dev *dev, |
829 | enum mlx5_dev_event event, | |
4d2f9bbb | 830 | unsigned long param); |
e126ba97 EC |
831 | struct mlx5_priv priv; |
832 | struct mlx5_profile *profile; | |
833 | atomic_t num_qps; | |
f62b8bb8 | 834 | u32 issi; |
b50d292b | 835 | struct mlx5e_resources mlx5e_res; |
52ec462e IT |
836 | struct { |
837 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 838 | u32 roce_en; |
52ec462e | 839 | } roce; |
e29341fb IT |
840 | #ifdef CONFIG_MLX5_FPGA |
841 | struct mlx5_fpga_device *fpga; | |
842 | #endif | |
5a7b27eb MG |
843 | #ifdef CONFIG_RFS_ACCEL |
844 | struct cpu_rmap *rmap; | |
845 | #endif | |
7c39afb3 | 846 | struct mlx5_clock clock; |
e126ba97 EC |
847 | }; |
848 | ||
849 | struct mlx5_db { | |
850 | __be32 *db; | |
851 | union { | |
852 | struct mlx5_db_pgdir *pgdir; | |
853 | struct mlx5_ib_user_db_page *user_page; | |
854 | } u; | |
855 | dma_addr_t dma; | |
856 | int index; | |
857 | }; | |
858 | ||
e126ba97 EC |
859 | enum { |
860 | MLX5_COMP_EQ_SIZE = 1024, | |
861 | }; | |
862 | ||
adb0c954 SM |
863 | enum { |
864 | MLX5_PTYS_IB = 1 << 0, | |
865 | MLX5_PTYS_EN = 1 << 2, | |
866 | }; | |
867 | ||
e126ba97 EC |
868 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
869 | ||
73dd3a48 MHY |
870 | enum { |
871 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
872 | }; | |
873 | ||
e126ba97 | 874 | struct mlx5_cmd_work_ent { |
73dd3a48 | 875 | unsigned long state; |
e126ba97 EC |
876 | struct mlx5_cmd_msg *in; |
877 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
878 | void *uout; |
879 | int uout_size; | |
e126ba97 | 880 | mlx5_cmd_cbk_t callback; |
65ee6708 | 881 | struct delayed_work cb_timeout_work; |
e126ba97 | 882 | void *context; |
746b5583 | 883 | int idx; |
e126ba97 EC |
884 | struct completion done; |
885 | struct mlx5_cmd *cmd; | |
886 | struct work_struct work; | |
887 | struct mlx5_cmd_layout *lay; | |
888 | int ret; | |
889 | int page_queue; | |
890 | u8 status; | |
891 | u8 token; | |
14a70046 TG |
892 | u64 ts1; |
893 | u64 ts2; | |
746b5583 | 894 | u16 op; |
4525abea | 895 | bool polling; |
e126ba97 EC |
896 | }; |
897 | ||
898 | struct mlx5_pas { | |
899 | u64 pa; | |
900 | u8 log_sz; | |
901 | }; | |
902 | ||
707c4602 MD |
903 | enum phy_port_state { |
904 | MLX5_AAA_111 | |
905 | }; | |
906 | ||
907 | struct mlx5_hca_vport_context { | |
908 | u32 field_select; | |
909 | bool sm_virt_aware; | |
910 | bool has_smi; | |
911 | bool has_raw; | |
912 | enum port_state_policy policy; | |
913 | enum phy_port_state phys_state; | |
914 | enum ib_port_state vport_state; | |
915 | u8 port_physical_state; | |
916 | u64 sys_image_guid; | |
917 | u64 port_guid; | |
918 | u64 node_guid; | |
919 | u32 cap_mask1; | |
920 | u32 cap_mask1_perm; | |
921 | u32 cap_mask2; | |
922 | u32 cap_mask2_perm; | |
923 | u16 lid; | |
924 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
925 | u8 lmc; | |
926 | u8 subnet_timeout; | |
927 | u16 sm_lid; | |
928 | u8 sm_sl; | |
929 | u16 qkey_violation_counter; | |
930 | u16 pkey_violation_counter; | |
931 | bool grh_required; | |
932 | }; | |
933 | ||
e126ba97 EC |
934 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
935 | { | |
e126ba97 | 936 | return buf->direct.buf + offset; |
e126ba97 EC |
937 | } |
938 | ||
e126ba97 EC |
939 | #define STRUCT_FIELD(header, field) \ |
940 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
941 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
942 | ||
e126ba97 EC |
943 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
944 | { | |
945 | return pci_get_drvdata(pdev); | |
946 | } | |
947 | ||
948 | extern struct dentry *mlx5_debugfs_root; | |
949 | ||
950 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
951 | { | |
952 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
953 | } | |
954 | ||
955 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
956 | { | |
957 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
958 | } | |
959 | ||
960 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
961 | { | |
962 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
963 | } | |
964 | ||
965 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
966 | { | |
967 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
968 | } | |
969 | ||
3bcdb17a SG |
970 | static inline u32 mlx5_base_mkey(const u32 key) |
971 | { | |
972 | return key & 0xffffff00u; | |
973 | } | |
974 | ||
e126ba97 EC |
975 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
976 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
977 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
978 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 979 | |
e126ba97 EC |
980 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
981 | int out_size); | |
746b5583 EC |
982 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
983 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
984 | void *context); | |
4525abea MD |
985 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
986 | void *out, int out_size); | |
c4f287c4 SM |
987 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
988 | ||
989 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
990 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
991 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
992 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
993 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
994 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
995 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
05ac2c0b | 996 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 997 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
2a0165a0 | 998 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
311c7c71 SM |
999 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
1000 | struct mlx5_buf *buf, int node); | |
64ffaa21 | 1001 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 | 1002 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
1c1b5228 TT |
1003 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
1004 | struct mlx5_frag_buf *buf, int node); | |
1005 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
1006 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
1007 | gfp_t flags, int npages); | |
1008 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
1009 | struct mlx5_cmd_mailbox *head); | |
1010 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 1011 | struct mlx5_srq_attr *in); |
e126ba97 EC |
1012 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
1013 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 1014 | struct mlx5_srq_attr *out); |
e126ba97 EC |
1015 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
1016 | u16 lwm, int is_srq); | |
a606b0f6 MB |
1017 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
1018 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
1019 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
1020 | struct mlx5_core_mkey *mkey, | |
1021 | u32 *in, int inlen, | |
1022 | u32 *out, int outlen, | |
1023 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
1024 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
1025 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1026 | u32 *in, int inlen); |
a606b0f6 MB |
1027 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
1028 | struct mlx5_core_mkey *mkey); | |
1029 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1030 | u32 *out, int outlen); |
a606b0f6 | 1031 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, |
e126ba97 EC |
1032 | u32 *mkey); |
1033 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
1034 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 1035 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 1036 | u16 opmod, u8 port); |
e126ba97 EC |
1037 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
1038 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
1039 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
1040 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
1041 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 1042 | s32 npages); |
cd23b14b | 1043 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
1044 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
1045 | void mlx5_register_debugfs(void); | |
1046 | void mlx5_unregister_debugfs(void); | |
1047 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
1048 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
1049 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
1c1b5228 | 1050 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
e126ba97 | 1051 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); |
5903325a | 1052 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e126ba97 EC |
1053 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
1054 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
73dd3a48 | 1055 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); |
e126ba97 EC |
1056 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
1057 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
d9aaed83 | 1058 | int nent, u64 mask, const char *name, |
01187175 | 1059 | enum mlx5_eq_type type); |
e126ba97 EC |
1060 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
1061 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
1062 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
0b6e26ce DT |
1063 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
1064 | unsigned int *irqn); | |
e126ba97 EC |
1065 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
1066 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
1067 | ||
1068 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
1069 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1070 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
1071 | int size_in, void *data_out, int size_out, | |
1072 | u16 reg_num, int arg, int write); | |
adb0c954 | 1073 | |
e126ba97 EC |
1074 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
1075 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
1076 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
73b626c1 | 1077 | u32 *out, int outlen); |
e126ba97 EC |
1078 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); |
1079 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1080 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
1081 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1082 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
311c7c71 SM |
1083 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
1084 | int node); | |
e126ba97 EC |
1085 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
1086 | ||
e126ba97 EC |
1087 | const char *mlx5_command_str(int command); |
1088 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
1089 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
1090 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
1091 | int npsvs, u32 *sig_index); | |
1092 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1093 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1094 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1095 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1096 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1097 | u8 port_num, void *out, size_t sz); | |
d9aaed83 AK |
1098 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1099 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, | |
1100 | u32 wq_num, u8 type, int error); | |
1101 | #endif | |
e126ba97 | 1102 | |
1466cc5b YP |
1103 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1104 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
1105 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); | |
1106 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); | |
1107 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); | |
a6d51b68 EC |
1108 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1109 | bool map_wc, bool fast_path); | |
1110 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1111 | |
52ec462e IT |
1112 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1113 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1114 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
1115 | const u8 *mac, bool vlan, u16 vlan_id); | |
1116 | ||
e3297246 EC |
1117 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1118 | { | |
1119 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1120 | } | |
1121 | ||
e126ba97 EC |
1122 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1123 | { | |
1124 | return mkey >> 8; | |
1125 | } | |
1126 | ||
1127 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1128 | { | |
1129 | return mkey_idx << 8; | |
1130 | } | |
1131 | ||
746b5583 EC |
1132 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1133 | { | |
1134 | return mkey & 0xff; | |
1135 | } | |
1136 | ||
e126ba97 EC |
1137 | enum { |
1138 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1139 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1140 | }; |
1141 | ||
1142 | enum { | |
8b7ff7f3 | 1143 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1144 | MLX5_IMR_MTT_CACHE_ENTRY, |
1145 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1146 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1147 | }; |
1148 | ||
64613d94 SM |
1149 | enum { |
1150 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1151 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1152 | }; | |
1153 | ||
9603b61d JM |
1154 | struct mlx5_interface { |
1155 | void * (*add)(struct mlx5_core_dev *dev); | |
1156 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1157 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1158 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 1159 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1160 | enum mlx5_dev_event event, unsigned long param); |
d9aaed83 AK |
1161 | void (*pfault)(struct mlx5_core_dev *dev, |
1162 | void *context, | |
1163 | struct mlx5_pagefault *pfault); | |
64613d94 SM |
1164 | void * (*get_dev)(void *context); |
1165 | int protocol; | |
9603b61d JM |
1166 | struct list_head list; |
1167 | }; | |
1168 | ||
64613d94 | 1169 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
1170 | int mlx5_register_interface(struct mlx5_interface *intf); |
1171 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 1172 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1173 | |
3bc34f3b AH |
1174 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1175 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 1176 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1177 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1178 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1179 | u64 *values, | |
1180 | int num_counters, | |
1181 | size_t *offsets); | |
01187175 EC |
1182 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1183 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1184 | |
693dfd5a ES |
1185 | #ifndef CONFIG_MLX5_CORE_IPOIB |
1186 | static inline | |
1187 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1188 | struct ib_device *ibdev, | |
1189 | const char *name, | |
1190 | void (*setup)(struct net_device *)) | |
1191 | { | |
1192 | return ERR_PTR(-EOPNOTSUPP); | |
1193 | } | |
1194 | ||
1195 | static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {} | |
1196 | #else | |
1197 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1198 | struct ib_device *ibdev, | |
1199 | const char *name, | |
1200 | void (*setup)(struct net_device *)); | |
1201 | void mlx5_rdma_netdev_free(struct net_device *netdev); | |
1202 | #endif /* CONFIG_MLX5_CORE_IPOIB */ | |
1203 | ||
e126ba97 EC |
1204 | struct mlx5_profile { |
1205 | u64 mask; | |
f241e749 | 1206 | u8 log_max_qp; |
e126ba97 EC |
1207 | struct { |
1208 | int size; | |
1209 | int limit; | |
1210 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1211 | }; | |
1212 | ||
fc50db98 EC |
1213 | enum { |
1214 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1215 | }; | |
1216 | ||
1217 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1218 | { | |
1219 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1220 | } | |
1221 | ||
707c4602 MD |
1222 | static inline int mlx5_get_gid_table_len(u16 param) |
1223 | { | |
1224 | if (param > 4) { | |
1225 | pr_warn("gid table length is zero\n"); | |
1226 | return 0; | |
1227 | } | |
1228 | ||
1229 | return 8 * (1 << param); | |
1230 | } | |
1231 | ||
1466cc5b YP |
1232 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1233 | { | |
1234 | return !!(dev->priv.rl_table.max_size); | |
1235 | } | |
1236 | ||
32f69e4b DJ |
1237 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1238 | { | |
1239 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1240 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1241 | } | |
1242 | ||
1243 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1244 | { | |
1245 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1246 | } | |
1247 | ||
1248 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1249 | { | |
1250 | return mlx5_core_is_mp_slave(dev) || | |
1251 | mlx5_core_is_mp_master(dev); | |
1252 | } | |
1253 | ||
7fd8aefb DJ |
1254 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1255 | { | |
32f69e4b DJ |
1256 | if (!mlx5_core_mp_enabled(dev)) |
1257 | return 1; | |
1258 | ||
1259 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1260 | } |
1261 | ||
020446e0 EC |
1262 | enum { |
1263 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1264 | }; | |
1265 | ||
a435393a SG |
1266 | static inline const struct cpumask * |
1267 | mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector) | |
1268 | { | |
1269 | return pci_irq_get_affinity(dev->pdev, MLX5_EQ_VEC_COMP_BASE + vector); | |
1270 | } | |
1271 | ||
e126ba97 | 1272 | #endif /* MLX5_DRIVER_H */ |