Commit | Line | Data |
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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 EC |
43 | #include <linux/vmalloc.h> |
44 | #include <linux/radix-tree.h> | |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
6ecde51d | 49 | |
e126ba97 EC |
50 | #include <linux/mlx5/device.h> |
51 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 52 | #include <linux/mlx5/srq.h> |
7c39afb3 FD |
53 | #include <linux/timecounter.h> |
54 | #include <linux/ptp_clock_kernel.h> | |
e126ba97 EC |
55 | |
56 | enum { | |
57 | MLX5_BOARD_ID_LEN = 64, | |
58 | MLX5_MAX_NAME_LEN = 16, | |
59 | }; | |
60 | ||
61 | enum { | |
62 | /* one minute for the sake of bringup. Generally, commands must always | |
63 | * complete and we may need to increase this timeout value | |
64 | */ | |
6b6c07bd | 65 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
66 | MLX5_CMD_WQ_MAX_NAME = 32, |
67 | }; | |
68 | ||
69 | enum { | |
70 | CMD_OWNER_SW = 0x0, | |
71 | CMD_OWNER_HW = 0x1, | |
72 | CMD_STATUS_SUCCESS = 0, | |
73 | }; | |
74 | ||
75 | enum mlx5_sqp_t { | |
76 | MLX5_SQP_SMI = 0, | |
77 | MLX5_SQP_GSI = 1, | |
78 | MLX5_SQP_IEEE_1588 = 2, | |
79 | MLX5_SQP_SNIFFER = 3, | |
80 | MLX5_SQP_SYNC_UMR = 4, | |
81 | }; | |
82 | ||
83 | enum { | |
84 | MLX5_MAX_PORTS = 2, | |
85 | }; | |
86 | ||
e126ba97 | 87 | enum { |
a60109dc YC |
88 | MLX5_ATOMIC_MODE_OFFSET = 16, |
89 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
90 | MLX5_ATOMIC_MODE_CX = 2, | |
91 | MLX5_ATOMIC_MODE_8B = 3, | |
92 | MLX5_ATOMIC_MODE_16B = 4, | |
93 | MLX5_ATOMIC_MODE_32B = 5, | |
94 | MLX5_ATOMIC_MODE_64B = 6, | |
95 | MLX5_ATOMIC_MODE_128B = 7, | |
96 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
97 | }; |
98 | ||
e126ba97 | 99 | enum { |
415a64aa | 100 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
101 | MLX5_REG_QETCR = 0x4005, |
102 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 103 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 104 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
105 | MLX5_REG_DCBX_PARAM = 0x4020, |
106 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
107 | MLX5_REG_FPGA_CAP = 0x4022, |
108 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 109 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
e126ba97 EC |
110 | MLX5_REG_PCAP = 0x5001, |
111 | MLX5_REG_PMTU = 0x5003, | |
112 | MLX5_REG_PTYS = 0x5004, | |
113 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 114 | MLX5_REG_PFCC = 0x5007, |
efea389d | 115 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
116 | MLX5_REG_PPTB = 0x500b, |
117 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
118 | MLX5_REG_PMAOS = 0x5012, |
119 | MLX5_REG_PUDE = 0x5009, | |
120 | MLX5_REG_PMPE = 0x5010, | |
121 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 122 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 123 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 124 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 125 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 126 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
127 | MLX5_REG_NODE_DESC = 0x6001, |
128 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 129 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 130 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
131 | MLX5_REG_MTRC_CAP = 0x9040, |
132 | MLX5_REG_MTRC_CONF = 0x9041, | |
133 | MLX5_REG_MTRC_STDB = 0x9042, | |
134 | MLX5_REG_MTRC_CTRL = 0x9043, | |
8ed1a630 | 135 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
136 | MLX5_REG_MTPPS = 0x9053, |
137 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 138 | MLX5_REG_MPEGC = 0x9056, |
47176289 OG |
139 | MLX5_REG_MCQI = 0x9061, |
140 | MLX5_REG_MCC = 0x9062, | |
141 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 142 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
143 | }; |
144 | ||
415a64aa HN |
145 | enum mlx5_qpts_trust_state { |
146 | MLX5_QPTS_TRUST_PCP = 1, | |
147 | MLX5_QPTS_TRUST_DSCP = 2, | |
148 | }; | |
149 | ||
341c5ee2 HN |
150 | enum mlx5_dcbx_oper_mode { |
151 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
152 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
153 | }; | |
154 | ||
da7525d2 EBE |
155 | enum { |
156 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
157 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
158 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
159 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
160 | }; |
161 | ||
e420f0c0 HE |
162 | enum mlx5_page_fault_resume_flags { |
163 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
164 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
165 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
166 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
167 | }; | |
168 | ||
e126ba97 EC |
169 | enum dbg_rsc_type { |
170 | MLX5_DBG_RSC_QP, | |
171 | MLX5_DBG_RSC_EQ, | |
172 | MLX5_DBG_RSC_CQ, | |
173 | }; | |
174 | ||
7ecf6d8f BW |
175 | enum port_state_policy { |
176 | MLX5_POLICY_DOWN = 0, | |
177 | MLX5_POLICY_UP = 1, | |
178 | MLX5_POLICY_FOLLOW = 2, | |
179 | MLX5_POLICY_INVALID = 0xffffffff | |
180 | }; | |
181 | ||
e126ba97 EC |
182 | struct mlx5_field_desc { |
183 | struct dentry *dent; | |
184 | int i; | |
185 | }; | |
186 | ||
187 | struct mlx5_rsc_debug { | |
188 | struct mlx5_core_dev *dev; | |
189 | void *object; | |
190 | enum dbg_rsc_type type; | |
191 | struct dentry *root; | |
192 | struct mlx5_field_desc fields[0]; | |
193 | }; | |
194 | ||
195 | enum mlx5_dev_event { | |
196 | MLX5_DEV_EVENT_SYS_ERROR, | |
197 | MLX5_DEV_EVENT_PORT_UP, | |
198 | MLX5_DEV_EVENT_PORT_DOWN, | |
199 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
200 | MLX5_DEV_EVENT_LID_CHANGE, | |
201 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
202 | MLX5_DEV_EVENT_GUID_CHANGE, | |
203 | MLX5_DEV_EVENT_CLIENT_REREG, | |
f9a1ef72 | 204 | MLX5_DEV_EVENT_PPS, |
246ac981 | 205 | MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, |
e126ba97 EC |
206 | }; |
207 | ||
4c916a79 | 208 | enum mlx5_port_status { |
6fa1bcab AS |
209 | MLX5_PORT_UP = 1, |
210 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
211 | }; |
212 | ||
2f5ff264 | 213 | struct mlx5_bfreg_info { |
b037c29a | 214 | u32 *sys_pages; |
2f5ff264 | 215 | int num_low_latency_bfregs; |
e126ba97 | 216 | unsigned int *count; |
e126ba97 EC |
217 | |
218 | /* | |
2f5ff264 | 219 | * protect bfreg allocation data structs |
e126ba97 EC |
220 | */ |
221 | struct mutex lock; | |
78c0f98c | 222 | u32 ver; |
b037c29a EC |
223 | bool lib_uar_4k; |
224 | u32 num_sys_pages; | |
31a78a5a YH |
225 | u32 num_static_sys_pages; |
226 | u32 total_num_bfregs; | |
227 | u32 num_dyn_bfregs; | |
e126ba97 EC |
228 | }; |
229 | ||
230 | struct mlx5_cmd_first { | |
231 | __be32 data[4]; | |
232 | }; | |
233 | ||
234 | struct mlx5_cmd_msg { | |
235 | struct list_head list; | |
0ac3ea70 | 236 | struct cmd_msg_cache *parent; |
e126ba97 EC |
237 | u32 len; |
238 | struct mlx5_cmd_first first; | |
239 | struct mlx5_cmd_mailbox *next; | |
240 | }; | |
241 | ||
242 | struct mlx5_cmd_debug { | |
243 | struct dentry *dbg_root; | |
244 | struct dentry *dbg_in; | |
245 | struct dentry *dbg_out; | |
246 | struct dentry *dbg_outlen; | |
247 | struct dentry *dbg_status; | |
248 | struct dentry *dbg_run; | |
249 | void *in_msg; | |
250 | void *out_msg; | |
251 | u8 status; | |
252 | u16 inlen; | |
253 | u16 outlen; | |
254 | }; | |
255 | ||
0ac3ea70 | 256 | struct cmd_msg_cache { |
e126ba97 EC |
257 | /* protect block chain allocations |
258 | */ | |
259 | spinlock_t lock; | |
260 | struct list_head head; | |
0ac3ea70 MHY |
261 | unsigned int max_inbox_size; |
262 | unsigned int num_ent; | |
e126ba97 EC |
263 | }; |
264 | ||
0ac3ea70 MHY |
265 | enum { |
266 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
267 | }; |
268 | ||
269 | struct mlx5_cmd_stats { | |
270 | u64 sum; | |
271 | u64 n; | |
272 | struct dentry *root; | |
273 | struct dentry *avg; | |
274 | struct dentry *count; | |
275 | /* protect command average calculations */ | |
276 | spinlock_t lock; | |
277 | }; | |
278 | ||
279 | struct mlx5_cmd { | |
64599cca EC |
280 | void *cmd_alloc_buf; |
281 | dma_addr_t alloc_dma; | |
282 | int alloc_size; | |
e126ba97 EC |
283 | void *cmd_buf; |
284 | dma_addr_t dma; | |
285 | u16 cmdif_rev; | |
286 | u8 log_sz; | |
287 | u8 log_stride; | |
288 | int max_reg_cmds; | |
289 | int events; | |
290 | u32 __iomem *vector; | |
291 | ||
292 | /* protect command queue allocations | |
293 | */ | |
294 | spinlock_t alloc_lock; | |
295 | ||
296 | /* protect token allocations | |
297 | */ | |
298 | spinlock_t token_lock; | |
299 | u8 token; | |
300 | unsigned long bitmask; | |
301 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
302 | struct workqueue_struct *wq; | |
303 | struct semaphore sem; | |
304 | struct semaphore pages_sem; | |
305 | int mode; | |
306 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 307 | struct dma_pool *pool; |
e126ba97 | 308 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 309 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
310 | int checksum_disabled; |
311 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
312 | }; | |
313 | ||
314 | struct mlx5_port_caps { | |
315 | int gid_table_len; | |
316 | int pkey_table_len; | |
938fe83c | 317 | u8 ext_port_cap; |
c43f1112 | 318 | bool has_smi; |
e126ba97 EC |
319 | }; |
320 | ||
321 | struct mlx5_cmd_mailbox { | |
322 | void *buf; | |
323 | dma_addr_t dma; | |
324 | struct mlx5_cmd_mailbox *next; | |
325 | }; | |
326 | ||
327 | struct mlx5_buf_list { | |
328 | void *buf; | |
329 | dma_addr_t map; | |
330 | }; | |
331 | ||
1c1b5228 TT |
332 | struct mlx5_frag_buf { |
333 | struct mlx5_buf_list *frags; | |
334 | int npages; | |
335 | int size; | |
336 | u8 page_shift; | |
337 | }; | |
338 | ||
388ca8be | 339 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 340 | struct mlx5_buf_list *frags; |
388ca8be | 341 | u32 sz_m1; |
8d71e818 | 342 | u16 frag_sz_m1; |
a0903622 | 343 | u16 strides_offset; |
388ca8be YC |
344 | u8 log_sz; |
345 | u8 log_stride; | |
346 | u8 log_frag_strides; | |
347 | }; | |
348 | ||
3121e3c4 SG |
349 | struct mlx5_core_psv { |
350 | u32 psv_idx; | |
351 | struct psv_layout { | |
352 | u32 pd; | |
353 | u16 syndrome; | |
354 | u16 reserved; | |
355 | u16 bg; | |
356 | u16 app_tag; | |
357 | u32 ref_tag; | |
358 | } psv; | |
359 | }; | |
360 | ||
361 | struct mlx5_core_sig_ctx { | |
362 | struct mlx5_core_psv psv_memory; | |
363 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
364 | struct ib_sig_err err_item; |
365 | bool sig_status_checked; | |
366 | bool sig_err_exists; | |
367 | u32 sigerr_count; | |
3121e3c4 | 368 | }; |
e126ba97 | 369 | |
aa8e08d2 AK |
370 | enum { |
371 | MLX5_MKEY_MR = 1, | |
372 | MLX5_MKEY_MW, | |
373 | }; | |
374 | ||
a606b0f6 | 375 | struct mlx5_core_mkey { |
e126ba97 EC |
376 | u64 iova; |
377 | u64 size; | |
378 | u32 key; | |
379 | u32 pd; | |
aa8e08d2 | 380 | u32 type; |
e126ba97 EC |
381 | }; |
382 | ||
d9aaed83 AK |
383 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
384 | ||
5903325a | 385 | enum mlx5_res_type { |
e2013b21 | 386 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
387 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
388 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
389 | MLX5_RES_SRQ = 3, | |
390 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 391 | MLX5_RES_XRQ = 5, |
57cda166 | 392 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
393 | }; |
394 | ||
395 | struct mlx5_core_rsc_common { | |
396 | enum mlx5_res_type res; | |
397 | atomic_t refcount; | |
398 | struct completion free; | |
399 | }; | |
400 | ||
e126ba97 | 401 | struct mlx5_core_srq { |
01949d01 | 402 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
403 | u32 srqn; |
404 | int max; | |
c2b37f76 BP |
405 | size_t max_gs; |
406 | size_t max_avail_gather; | |
e126ba97 EC |
407 | int wqe_shift; |
408 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
409 | ||
410 | atomic_t refcount; | |
411 | struct completion free; | |
a0d8c054 | 412 | u16 uid; |
e126ba97 EC |
413 | }; |
414 | ||
a6d51b68 | 415 | struct mlx5_uars_page { |
e126ba97 | 416 | void __iomem *map; |
a6d51b68 EC |
417 | bool wc; |
418 | u32 index; | |
419 | struct list_head list; | |
420 | unsigned int bfregs; | |
421 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
422 | unsigned long *fp_bitmap; | |
423 | unsigned int reg_avail; | |
424 | unsigned int fp_avail; | |
425 | struct kref ref_count; | |
426 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
427 | }; |
428 | ||
a6d51b68 EC |
429 | struct mlx5_bfreg_head { |
430 | /* protect blue flame registers allocations */ | |
431 | struct mutex lock; | |
432 | struct list_head list; | |
433 | }; | |
434 | ||
435 | struct mlx5_bfreg_data { | |
436 | struct mlx5_bfreg_head reg_head; | |
437 | struct mlx5_bfreg_head wc_head; | |
438 | }; | |
439 | ||
440 | struct mlx5_sq_bfreg { | |
441 | void __iomem *map; | |
442 | struct mlx5_uars_page *up; | |
443 | bool wc; | |
444 | u32 index; | |
445 | unsigned int offset; | |
446 | }; | |
e126ba97 EC |
447 | |
448 | struct mlx5_core_health { | |
449 | struct health_buffer __iomem *health; | |
450 | __be32 __iomem *health_counter; | |
451 | struct timer_list timer; | |
e126ba97 EC |
452 | u32 prev; |
453 | int miss_counter; | |
fd76ee4d | 454 | bool sick; |
05ac2c0b MHY |
455 | /* wq spinlock to synchronize draining */ |
456 | spinlock_t wq_lock; | |
ac6ea6e8 | 457 | struct workqueue_struct *wq; |
05ac2c0b | 458 | unsigned long flags; |
ac6ea6e8 | 459 | struct work_struct work; |
04c0c1ab | 460 | struct delayed_work recover_work; |
e126ba97 EC |
461 | }; |
462 | ||
e126ba97 EC |
463 | struct mlx5_qp_table { |
464 | /* protect radix tree | |
465 | */ | |
466 | spinlock_t lock; | |
467 | struct radix_tree_root tree; | |
468 | }; | |
469 | ||
470 | struct mlx5_srq_table { | |
471 | /* protect radix tree | |
472 | */ | |
473 | spinlock_t lock; | |
474 | struct radix_tree_root tree; | |
475 | }; | |
476 | ||
a606b0f6 | 477 | struct mlx5_mkey_table { |
3bcdb17a SG |
478 | /* protect radix tree |
479 | */ | |
480 | rwlock_t lock; | |
481 | struct radix_tree_root tree; | |
482 | }; | |
483 | ||
fc50db98 EC |
484 | struct mlx5_vf_context { |
485 | int enabled; | |
7ecf6d8f BW |
486 | u64 port_guid; |
487 | u64 node_guid; | |
488 | enum port_state_policy policy; | |
fc50db98 EC |
489 | }; |
490 | ||
491 | struct mlx5_core_sriov { | |
492 | struct mlx5_vf_context *vfs_ctx; | |
493 | int num_vfs; | |
494 | int enabled_vfs; | |
495 | }; | |
496 | ||
43a335e0 | 497 | struct mlx5_fc_stats { |
12d6066c VB |
498 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
499 | struct idr counters_idr; | |
9aff93d7 | 500 | struct list_head counters; |
83033688 | 501 | struct llist_head addlist; |
6e5e2283 | 502 | struct llist_head dellist; |
43a335e0 AV |
503 | |
504 | struct workqueue_struct *wq; | |
505 | struct delayed_work work; | |
506 | unsigned long next_query; | |
f6dfb4c3 | 507 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
508 | }; |
509 | ||
eeb66cdb | 510 | struct mlx5_mpfs; |
073bb189 | 511 | struct mlx5_eswitch; |
7907f23a | 512 | struct mlx5_lag; |
f2f3df55 | 513 | struct mlx5_eq_table; |
073bb189 | 514 | |
05d3ac97 BW |
515 | struct mlx5_rate_limit { |
516 | u32 rate; | |
517 | u32 max_burst_sz; | |
518 | u16 typical_pkt_sz; | |
519 | }; | |
520 | ||
1466cc5b | 521 | struct mlx5_rl_entry { |
05d3ac97 | 522 | struct mlx5_rate_limit rl; |
1466cc5b YP |
523 | u16 index; |
524 | u16 refcount; | |
525 | }; | |
526 | ||
527 | struct mlx5_rl_table { | |
528 | /* protect rate limit table */ | |
529 | struct mutex rl_lock; | |
530 | u16 max_size; | |
531 | u32 max_rate; | |
532 | u32 min_rate; | |
533 | struct mlx5_rl_entry *rl_entry; | |
534 | }; | |
535 | ||
d4eb4cd7 HN |
536 | enum port_module_event_status_type { |
537 | MLX5_MODULE_STATUS_PLUGGED = 0x1, | |
538 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, | |
539 | MLX5_MODULE_STATUS_ERROR = 0x3, | |
540 | MLX5_MODULE_STATUS_NUM = 0x3, | |
541 | }; | |
542 | ||
543 | enum port_module_event_error_type { | |
544 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, | |
545 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, | |
546 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, | |
547 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, | |
548 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, | |
549 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, | |
550 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, | |
551 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, | |
552 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, | |
553 | MLX5_MODULE_EVENT_ERROR_NUM, | |
554 | }; | |
555 | ||
556 | struct mlx5_port_module_event_stats { | |
557 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; | |
558 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; | |
559 | }; | |
560 | ||
e126ba97 EC |
561 | struct mlx5_priv { |
562 | char name[MLX5_MAX_NAME_LEN]; | |
f2f3df55 | 563 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
564 | |
565 | /* pages stuff */ | |
566 | struct workqueue_struct *pg_wq; | |
567 | struct rb_root page_root; | |
568 | int fw_pages; | |
6aec21f6 | 569 | atomic_t reg_pages; |
bf0bf77f | 570 | struct list_head free_list; |
fc50db98 | 571 | int vfs_pages; |
e126ba97 EC |
572 | |
573 | struct mlx5_core_health health; | |
574 | ||
575 | struct mlx5_srq_table srq_table; | |
576 | ||
577 | /* start: qp staff */ | |
578 | struct mlx5_qp_table qp_table; | |
579 | struct dentry *qp_debugfs; | |
580 | struct dentry *eq_debugfs; | |
581 | struct dentry *cq_debugfs; | |
582 | struct dentry *cmdif_debugfs; | |
583 | /* end: qp staff */ | |
584 | ||
a606b0f6 MB |
585 | /* start: mkey staff */ |
586 | struct mlx5_mkey_table mkey_table; | |
587 | /* end: mkey staff */ | |
3bcdb17a | 588 | |
e126ba97 | 589 | /* start: alloc staff */ |
311c7c71 SM |
590 | /* protect buffer alocation according to numa node */ |
591 | struct mutex alloc_mutex; | |
592 | int numa_node; | |
593 | ||
e126ba97 EC |
594 | struct mutex pgdir_mutex; |
595 | struct list_head pgdir_list; | |
596 | /* end: alloc staff */ | |
597 | struct dentry *dbg_root; | |
598 | ||
599 | /* protect mkey key part */ | |
600 | spinlock_t mkey_lock; | |
601 | u8 mkey_key; | |
9603b61d JM |
602 | |
603 | struct list_head dev_list; | |
604 | struct list_head ctx_list; | |
605 | spinlock_t ctx_lock; | |
073bb189 | 606 | |
97834eba ES |
607 | struct list_head waiting_events_list; |
608 | bool is_accum_events; | |
609 | ||
fba53f7b | 610 | struct mlx5_flow_steering *steering; |
eeb66cdb | 611 | struct mlx5_mpfs *mpfs; |
073bb189 | 612 | struct mlx5_eswitch *eswitch; |
fc50db98 | 613 | struct mlx5_core_sriov sriov; |
7907f23a | 614 | struct mlx5_lag *lag; |
fc50db98 | 615 | unsigned long pci_dev_data; |
43a335e0 | 616 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 617 | struct mlx5_rl_table rl_table; |
d4eb4cd7 HN |
618 | |
619 | struct mlx5_port_module_event_stats pme_stats; | |
d9aaed83 | 620 | |
a6d51b68 | 621 | struct mlx5_bfreg_data bfregs; |
01187175 | 622 | struct mlx5_uars_page *uar; |
e126ba97 EC |
623 | }; |
624 | ||
89d44f0a MD |
625 | enum mlx5_device_state { |
626 | MLX5_DEVICE_STATE_UP, | |
627 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
628 | }; | |
629 | ||
630 | enum mlx5_interface_state { | |
b3cb5388 | 631 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
632 | }; |
633 | ||
634 | enum mlx5_pci_status { | |
635 | MLX5_PCI_STATUS_DISABLED, | |
636 | MLX5_PCI_STATUS_ENABLED, | |
637 | }; | |
638 | ||
d9aaed83 AK |
639 | enum mlx5_pagefault_type_flags { |
640 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
641 | MLX5_PFAULT_WRITE = 1 << 1, | |
642 | MLX5_PFAULT_RDMA = 1 << 2, | |
643 | }; | |
644 | ||
b50d292b HHZ |
645 | struct mlx5_td { |
646 | struct list_head tirs_list; | |
647 | u32 tdn; | |
648 | }; | |
649 | ||
650 | struct mlx5e_resources { | |
b50d292b HHZ |
651 | u32 pdn; |
652 | struct mlx5_td td; | |
653 | struct mlx5_core_mkey mkey; | |
aff26157 | 654 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
655 | }; |
656 | ||
52ec462e IT |
657 | #define MLX5_MAX_RESERVED_GIDS 8 |
658 | ||
659 | struct mlx5_rsvd_gids { | |
660 | unsigned int start; | |
661 | unsigned int count; | |
662 | struct ida ida; | |
663 | }; | |
664 | ||
7c39afb3 FD |
665 | #define MAX_PIN_NUM 8 |
666 | struct mlx5_pps { | |
667 | u8 pin_caps[MAX_PIN_NUM]; | |
668 | struct work_struct out_work; | |
669 | u64 start[MAX_PIN_NUM]; | |
670 | u8 enabled; | |
671 | }; | |
672 | ||
673 | struct mlx5_clock { | |
64109f1d | 674 | seqlock_t lock; |
7c39afb3 FD |
675 | struct cyclecounter cycles; |
676 | struct timecounter tc; | |
677 | struct hwtstamp_config hwtstamp_config; | |
678 | u32 nominal_c_mult; | |
679 | unsigned long overflow_period; | |
680 | struct delayed_work overflow_work; | |
24d33d2c | 681 | struct mlx5_core_dev *mdev; |
7c39afb3 FD |
682 | struct ptp_clock *ptp; |
683 | struct ptp_clock_info ptp_info; | |
684 | struct mlx5_pps pps_info; | |
685 | }; | |
686 | ||
f53aaa31 | 687 | struct mlx5_fw_tracer; |
358aa5ce | 688 | struct mlx5_vxlan; |
f53aaa31 | 689 | |
e126ba97 EC |
690 | struct mlx5_core_dev { |
691 | struct pci_dev *pdev; | |
89d44f0a MD |
692 | /* sync pci state */ |
693 | struct mutex pci_status_mutex; | |
694 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
695 | u8 rev_id; |
696 | char board_id[MLX5_BOARD_ID_LEN]; | |
697 | struct mlx5_cmd cmd; | |
938fe83c | 698 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 699 | struct { |
701052c5 GP |
700 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
701 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
702 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
703 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 704 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 705 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
71862561 | 706 | } caps; |
59c9d35e | 707 | u64 sys_image_guid; |
e126ba97 EC |
708 | phys_addr_t iseg_base; |
709 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
710 | enum mlx5_device_state state; |
711 | /* sync interface state */ | |
712 | struct mutex intf_state_mutex; | |
5fc7197d | 713 | unsigned long intf_state; |
e126ba97 EC |
714 | void (*event) (struct mlx5_core_dev *dev, |
715 | enum mlx5_dev_event event, | |
4d2f9bbb | 716 | unsigned long param); |
e126ba97 EC |
717 | struct mlx5_priv priv; |
718 | struct mlx5_profile *profile; | |
719 | atomic_t num_qps; | |
f62b8bb8 | 720 | u32 issi; |
b50d292b | 721 | struct mlx5e_resources mlx5e_res; |
358aa5ce | 722 | struct mlx5_vxlan *vxlan; |
52ec462e IT |
723 | struct { |
724 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 725 | u32 roce_en; |
52ec462e | 726 | } roce; |
e29341fb IT |
727 | #ifdef CONFIG_MLX5_FPGA |
728 | struct mlx5_fpga_device *fpga; | |
5a7b27eb | 729 | #endif |
7c39afb3 | 730 | struct mlx5_clock clock; |
24d33d2c FD |
731 | struct mlx5_ib_clock_info *clock_info; |
732 | struct page *clock_info_page; | |
f53aaa31 | 733 | struct mlx5_fw_tracer *tracer; |
e126ba97 EC |
734 | }; |
735 | ||
736 | struct mlx5_db { | |
737 | __be32 *db; | |
738 | union { | |
739 | struct mlx5_db_pgdir *pgdir; | |
740 | struct mlx5_ib_user_db_page *user_page; | |
741 | } u; | |
742 | dma_addr_t dma; | |
743 | int index; | |
744 | }; | |
745 | ||
e126ba97 EC |
746 | enum { |
747 | MLX5_COMP_EQ_SIZE = 1024, | |
748 | }; | |
749 | ||
adb0c954 SM |
750 | enum { |
751 | MLX5_PTYS_IB = 1 << 0, | |
752 | MLX5_PTYS_EN = 1 << 2, | |
753 | }; | |
754 | ||
e126ba97 EC |
755 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
756 | ||
73dd3a48 MHY |
757 | enum { |
758 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
759 | }; | |
760 | ||
e126ba97 | 761 | struct mlx5_cmd_work_ent { |
73dd3a48 | 762 | unsigned long state; |
e126ba97 EC |
763 | struct mlx5_cmd_msg *in; |
764 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
765 | void *uout; |
766 | int uout_size; | |
e126ba97 | 767 | mlx5_cmd_cbk_t callback; |
65ee6708 | 768 | struct delayed_work cb_timeout_work; |
e126ba97 | 769 | void *context; |
746b5583 | 770 | int idx; |
e126ba97 EC |
771 | struct completion done; |
772 | struct mlx5_cmd *cmd; | |
773 | struct work_struct work; | |
774 | struct mlx5_cmd_layout *lay; | |
775 | int ret; | |
776 | int page_queue; | |
777 | u8 status; | |
778 | u8 token; | |
14a70046 TG |
779 | u64 ts1; |
780 | u64 ts2; | |
746b5583 | 781 | u16 op; |
4525abea | 782 | bool polling; |
e126ba97 EC |
783 | }; |
784 | ||
785 | struct mlx5_pas { | |
786 | u64 pa; | |
787 | u8 log_sz; | |
788 | }; | |
789 | ||
707c4602 MD |
790 | enum phy_port_state { |
791 | MLX5_AAA_111 | |
792 | }; | |
793 | ||
794 | struct mlx5_hca_vport_context { | |
795 | u32 field_select; | |
796 | bool sm_virt_aware; | |
797 | bool has_smi; | |
798 | bool has_raw; | |
799 | enum port_state_policy policy; | |
800 | enum phy_port_state phys_state; | |
801 | enum ib_port_state vport_state; | |
802 | u8 port_physical_state; | |
803 | u64 sys_image_guid; | |
804 | u64 port_guid; | |
805 | u64 node_guid; | |
806 | u32 cap_mask1; | |
807 | u32 cap_mask1_perm; | |
808 | u32 cap_mask2; | |
809 | u32 cap_mask2_perm; | |
810 | u16 lid; | |
811 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
812 | u8 lmc; | |
813 | u8 subnet_timeout; | |
814 | u16 sm_lid; | |
815 | u8 sm_sl; | |
816 | u16 qkey_violation_counter; | |
817 | u16 pkey_violation_counter; | |
818 | bool grh_required; | |
819 | }; | |
820 | ||
388ca8be | 821 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 822 | { |
388ca8be | 823 | return buf->frags->buf + offset; |
e126ba97 EC |
824 | } |
825 | ||
e126ba97 EC |
826 | #define STRUCT_FIELD(header, field) \ |
827 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
828 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
829 | ||
e126ba97 EC |
830 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
831 | { | |
832 | return pci_get_drvdata(pdev); | |
833 | } | |
834 | ||
835 | extern struct dentry *mlx5_debugfs_root; | |
836 | ||
837 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
838 | { | |
839 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
840 | } | |
841 | ||
842 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
843 | { | |
844 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
845 | } | |
846 | ||
847 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
848 | { | |
849 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
850 | } | |
851 | ||
852 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
853 | { | |
854 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
855 | } | |
856 | ||
3bcdb17a SG |
857 | static inline u32 mlx5_base_mkey(const u32 key) |
858 | { | |
859 | return key & 0xffffff00u; | |
860 | } | |
861 | ||
4972e6fa TT |
862 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
863 | u8 log_stride, u8 log_sz, | |
a0903622 | 864 | u16 strides_offset, |
d7037ad7 | 865 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 866 | { |
4972e6fa | 867 | fbc->frags = frags; |
3a2f7033 TT |
868 | fbc->log_stride = log_stride; |
869 | fbc->log_sz = log_sz; | |
388ca8be YC |
870 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
871 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
872 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
873 | fbc->strides_offset = strides_offset; |
874 | } | |
875 | ||
4972e6fa TT |
876 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
877 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
878 | struct mlx5_frag_buf_ctrl *fbc) |
879 | { | |
4972e6fa | 880 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
881 | } |
882 | ||
388ca8be YC |
883 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
884 | u32 ix) | |
885 | { | |
d7037ad7 TT |
886 | unsigned int frag; |
887 | ||
888 | ix += fbc->strides_offset; | |
889 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 890 | |
4972e6fa | 891 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
892 | } |
893 | ||
37fdffb2 TT |
894 | static inline u32 |
895 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
896 | { | |
897 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
898 | ||
899 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
900 | } | |
901 | ||
e126ba97 EC |
902 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
903 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
904 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
905 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 906 | |
e126ba97 EC |
907 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
908 | int out_size); | |
746b5583 EC |
909 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
910 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
911 | void *context); | |
4525abea MD |
912 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
913 | void *out, int out_size); | |
c4f287c4 SM |
914 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
915 | ||
916 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
917 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
918 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
919 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
920 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 921 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 922 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 923 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 924 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
2a0165a0 | 925 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
311c7c71 | 926 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
388ca8be YC |
927 | struct mlx5_frag_buf *buf, int node); |
928 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, | |
929 | int size, struct mlx5_frag_buf *buf); | |
930 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
931 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
932 | struct mlx5_frag_buf *buf, int node); | |
933 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
934 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
935 | gfp_t flags, int npages); | |
936 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
937 | struct mlx5_cmd_mailbox *head); | |
938 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 939 | struct mlx5_srq_attr *in); |
e126ba97 EC |
940 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
941 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 942 | struct mlx5_srq_attr *out); |
e126ba97 EC |
943 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
944 | u16 lwm, int is_srq); | |
a606b0f6 MB |
945 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
946 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
947 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
948 | struct mlx5_core_mkey *mkey, | |
949 | u32 *in, int inlen, | |
950 | u32 *out, int outlen, | |
951 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
952 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
953 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 954 | u32 *in, int inlen); |
a606b0f6 MB |
955 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
956 | struct mlx5_core_mkey *mkey); | |
957 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 958 | u32 *out, int outlen); |
e126ba97 EC |
959 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
960 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 961 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 962 | u16 opmod, u8 port); |
e126ba97 EC |
963 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
964 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
965 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
966 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
967 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 968 | s32 npages); |
cd23b14b | 969 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
970 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
971 | void mlx5_register_debugfs(void); | |
972 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
973 | |
974 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 975 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
5903325a | 976 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e126ba97 EC |
977 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
978 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
0b6e26ce DT |
979 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
980 | unsigned int *irqn); | |
e126ba97 EC |
981 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
982 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
983 | ||
984 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
985 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
986 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
987 | int size_in, void *data_out, int size_out, | |
988 | u16 reg_num, int arg, int write); | |
adb0c954 | 989 | |
e126ba97 | 990 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
991 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
992 | int node); | |
e126ba97 EC |
993 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
994 | ||
e126ba97 EC |
995 | const char *mlx5_command_str(int command); |
996 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
997 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
998 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
999 | int npsvs, u32 *sig_index); | |
1000 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1001 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1002 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1003 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1004 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1005 | u8 port_num, void *out, size_t sz); | |
d9aaed83 AK |
1006 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1007 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, | |
1008 | u32 wq_num, u8 type, int error); | |
1009 | #endif | |
e126ba97 | 1010 | |
1466cc5b YP |
1011 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1012 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
1013 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
1014 | struct mlx5_rate_limit *rl); | |
1015 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 1016 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
05d3ac97 BW |
1017 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
1018 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
1019 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1020 | bool map_wc, bool fast_path); | |
1021 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1022 | |
f2f3df55 SM |
1023 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
1024 | struct cpumask * | |
1025 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
1026 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1027 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1028 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1029 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1030 | |
e3297246 EC |
1031 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1032 | { | |
1033 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1034 | } | |
1035 | ||
e126ba97 EC |
1036 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1037 | { | |
1038 | return mkey >> 8; | |
1039 | } | |
1040 | ||
1041 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1042 | { | |
1043 | return mkey_idx << 8; | |
1044 | } | |
1045 | ||
746b5583 EC |
1046 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1047 | { | |
1048 | return mkey & 0xff; | |
1049 | } | |
1050 | ||
e126ba97 EC |
1051 | enum { |
1052 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1053 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1054 | }; |
1055 | ||
1056 | enum { | |
8b7ff7f3 | 1057 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1058 | MLX5_IMR_MTT_CACHE_ENTRY, |
1059 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1060 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1061 | }; |
1062 | ||
64613d94 SM |
1063 | enum { |
1064 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1065 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1066 | }; | |
1067 | ||
9603b61d JM |
1068 | struct mlx5_interface { |
1069 | void * (*add)(struct mlx5_core_dev *dev); | |
1070 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1071 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1072 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 1073 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1074 | enum mlx5_dev_event event, unsigned long param); |
64613d94 SM |
1075 | void * (*get_dev)(void *context); |
1076 | int protocol; | |
9603b61d JM |
1077 | struct list_head list; |
1078 | }; | |
1079 | ||
64613d94 | 1080 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
1081 | int mlx5_register_interface(struct mlx5_interface *intf); |
1082 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 1083 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1084 | |
3bc34f3b AH |
1085 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1086 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 1087 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1088 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1089 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1090 | u64 *values, | |
1091 | int num_counters, | |
1092 | size_t *offsets); | |
01187175 EC |
1093 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1094 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1095 | |
f6a8a19b | 1096 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1097 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1098 | struct ib_device *ibdev, | |
1099 | const char *name, | |
1100 | void (*setup)(struct net_device *)); | |
693dfd5a | 1101 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1102 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1103 | struct ib_device *device, | |
1104 | struct rdma_netdev_alloc_params *params); | |
693dfd5a | 1105 | |
e126ba97 EC |
1106 | struct mlx5_profile { |
1107 | u64 mask; | |
f241e749 | 1108 | u8 log_max_qp; |
e126ba97 EC |
1109 | struct { |
1110 | int size; | |
1111 | int limit; | |
1112 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1113 | }; | |
1114 | ||
fc50db98 EC |
1115 | enum { |
1116 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1117 | }; | |
1118 | ||
1119 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1120 | { | |
1121 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1122 | } | |
1123 | ||
57cbd893 MB |
1124 | #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) |
1125 | #define MLX5_VPORT_MANAGER(mdev) \ | |
1126 | (MLX5_CAP_GEN(mdev, vport_group_manager) && \ | |
1127 | (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ | |
1128 | mlx5_core_is_pf(mdev)) | |
1129 | ||
707c4602 MD |
1130 | static inline int mlx5_get_gid_table_len(u16 param) |
1131 | { | |
1132 | if (param > 4) { | |
1133 | pr_warn("gid table length is zero\n"); | |
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | return 8 * (1 << param); | |
1138 | } | |
1139 | ||
1466cc5b YP |
1140 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1141 | { | |
1142 | return !!(dev->priv.rl_table.max_size); | |
1143 | } | |
1144 | ||
32f69e4b DJ |
1145 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1146 | { | |
1147 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1148 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1149 | } | |
1150 | ||
1151 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1152 | { | |
1153 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1154 | } | |
1155 | ||
1156 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1157 | { | |
1158 | return mlx5_core_is_mp_slave(dev) || | |
1159 | mlx5_core_is_mp_master(dev); | |
1160 | } | |
1161 | ||
7fd8aefb DJ |
1162 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1163 | { | |
32f69e4b DJ |
1164 | if (!mlx5_core_mp_enabled(dev)) |
1165 | return 1; | |
1166 | ||
1167 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1168 | } |
1169 | ||
020446e0 EC |
1170 | enum { |
1171 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1172 | }; | |
1173 | ||
e126ba97 | 1174 | #endif /* MLX5_DRIVER_H */ |