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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 EC |
43 | #include <linux/vmalloc.h> |
44 | #include <linux/radix-tree.h> | |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
6ecde51d | 49 | |
e126ba97 EC |
50 | #include <linux/mlx5/device.h> |
51 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 52 | #include <linux/mlx5/srq.h> |
7c39afb3 FD |
53 | #include <linux/timecounter.h> |
54 | #include <linux/ptp_clock_kernel.h> | |
e126ba97 EC |
55 | |
56 | enum { | |
57 | MLX5_BOARD_ID_LEN = 64, | |
58 | MLX5_MAX_NAME_LEN = 16, | |
59 | }; | |
60 | ||
61 | enum { | |
62 | /* one minute for the sake of bringup. Generally, commands must always | |
63 | * complete and we may need to increase this timeout value | |
64 | */ | |
6b6c07bd | 65 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
66 | MLX5_CMD_WQ_MAX_NAME = 32, |
67 | }; | |
68 | ||
69 | enum { | |
70 | CMD_OWNER_SW = 0x0, | |
71 | CMD_OWNER_HW = 0x1, | |
72 | CMD_STATUS_SUCCESS = 0, | |
73 | }; | |
74 | ||
75 | enum mlx5_sqp_t { | |
76 | MLX5_SQP_SMI = 0, | |
77 | MLX5_SQP_GSI = 1, | |
78 | MLX5_SQP_IEEE_1588 = 2, | |
79 | MLX5_SQP_SNIFFER = 3, | |
80 | MLX5_SQP_SYNC_UMR = 4, | |
81 | }; | |
82 | ||
83 | enum { | |
84 | MLX5_MAX_PORTS = 2, | |
85 | }; | |
86 | ||
87 | enum { | |
88 | MLX5_EQ_VEC_PAGES = 0, | |
89 | MLX5_EQ_VEC_CMD = 1, | |
90 | MLX5_EQ_VEC_ASYNC = 2, | |
d9aaed83 | 91 | MLX5_EQ_VEC_PFAULT = 3, |
e126ba97 EC |
92 | MLX5_EQ_VEC_COMP_BASE, |
93 | }; | |
94 | ||
95 | enum { | |
db058a18 | 96 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
97 | }; |
98 | ||
99 | enum { | |
100 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
101 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
102 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
103 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
104 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
105 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
106 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
107 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
108 | }; | |
109 | ||
e126ba97 | 110 | enum { |
415a64aa | 111 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
112 | MLX5_REG_QETCR = 0x4005, |
113 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 114 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 115 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
116 | MLX5_REG_DCBX_PARAM = 0x4020, |
117 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
118 | MLX5_REG_FPGA_CAP = 0x4022, |
119 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 120 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
e126ba97 EC |
121 | MLX5_REG_PCAP = 0x5001, |
122 | MLX5_REG_PMTU = 0x5003, | |
123 | MLX5_REG_PTYS = 0x5004, | |
124 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 125 | MLX5_REG_PFCC = 0x5007, |
efea389d | 126 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
127 | MLX5_REG_PPTB = 0x500b, |
128 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
129 | MLX5_REG_PMAOS = 0x5012, |
130 | MLX5_REG_PUDE = 0x5009, | |
131 | MLX5_REG_PMPE = 0x5010, | |
132 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 133 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 134 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 135 | MLX5_REG_PMLP = 0x5002, |
cfdcbcea | 136 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
137 | MLX5_REG_NODE_DESC = 0x6001, |
138 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 139 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 140 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
141 | MLX5_REG_MTRC_CAP = 0x9040, |
142 | MLX5_REG_MTRC_CONF = 0x9041, | |
143 | MLX5_REG_MTRC_STDB = 0x9042, | |
144 | MLX5_REG_MTRC_CTRL = 0x9043, | |
8ed1a630 | 145 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
146 | MLX5_REG_MTPPS = 0x9053, |
147 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 148 | MLX5_REG_MPEGC = 0x9056, |
47176289 OG |
149 | MLX5_REG_MCQI = 0x9061, |
150 | MLX5_REG_MCC = 0x9062, | |
151 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 152 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
153 | }; |
154 | ||
415a64aa HN |
155 | enum mlx5_qpts_trust_state { |
156 | MLX5_QPTS_TRUST_PCP = 1, | |
157 | MLX5_QPTS_TRUST_DSCP = 2, | |
158 | }; | |
159 | ||
341c5ee2 HN |
160 | enum mlx5_dcbx_oper_mode { |
161 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
162 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
163 | }; | |
164 | ||
57cda166 MS |
165 | enum mlx5_dct_atomic_mode { |
166 | MLX5_ATOMIC_MODE_DCT_OFF = 20, | |
167 | MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, | |
168 | MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, | |
169 | MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, | |
170 | }; | |
171 | ||
da7525d2 EBE |
172 | enum { |
173 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
174 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
175 | }; | |
176 | ||
e420f0c0 HE |
177 | enum mlx5_page_fault_resume_flags { |
178 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
179 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
180 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
181 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
182 | }; | |
183 | ||
e126ba97 EC |
184 | enum dbg_rsc_type { |
185 | MLX5_DBG_RSC_QP, | |
186 | MLX5_DBG_RSC_EQ, | |
187 | MLX5_DBG_RSC_CQ, | |
188 | }; | |
189 | ||
7ecf6d8f BW |
190 | enum port_state_policy { |
191 | MLX5_POLICY_DOWN = 0, | |
192 | MLX5_POLICY_UP = 1, | |
193 | MLX5_POLICY_FOLLOW = 2, | |
194 | MLX5_POLICY_INVALID = 0xffffffff | |
195 | }; | |
196 | ||
e126ba97 EC |
197 | struct mlx5_field_desc { |
198 | struct dentry *dent; | |
199 | int i; | |
200 | }; | |
201 | ||
202 | struct mlx5_rsc_debug { | |
203 | struct mlx5_core_dev *dev; | |
204 | void *object; | |
205 | enum dbg_rsc_type type; | |
206 | struct dentry *root; | |
207 | struct mlx5_field_desc fields[0]; | |
208 | }; | |
209 | ||
210 | enum mlx5_dev_event { | |
211 | MLX5_DEV_EVENT_SYS_ERROR, | |
212 | MLX5_DEV_EVENT_PORT_UP, | |
213 | MLX5_DEV_EVENT_PORT_DOWN, | |
214 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
215 | MLX5_DEV_EVENT_LID_CHANGE, | |
216 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
217 | MLX5_DEV_EVENT_GUID_CHANGE, | |
218 | MLX5_DEV_EVENT_CLIENT_REREG, | |
f9a1ef72 | 219 | MLX5_DEV_EVENT_PPS, |
246ac981 | 220 | MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, |
e126ba97 EC |
221 | }; |
222 | ||
4c916a79 | 223 | enum mlx5_port_status { |
6fa1bcab AS |
224 | MLX5_PORT_UP = 1, |
225 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
226 | }; |
227 | ||
d9aaed83 AK |
228 | enum mlx5_eq_type { |
229 | MLX5_EQ_TYPE_COMP, | |
230 | MLX5_EQ_TYPE_ASYNC, | |
231 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
232 | MLX5_EQ_TYPE_PF, | |
233 | #endif | |
234 | }; | |
235 | ||
2f5ff264 | 236 | struct mlx5_bfreg_info { |
b037c29a | 237 | u32 *sys_pages; |
2f5ff264 | 238 | int num_low_latency_bfregs; |
e126ba97 | 239 | unsigned int *count; |
e126ba97 EC |
240 | |
241 | /* | |
2f5ff264 | 242 | * protect bfreg allocation data structs |
e126ba97 EC |
243 | */ |
244 | struct mutex lock; | |
78c0f98c | 245 | u32 ver; |
b037c29a EC |
246 | bool lib_uar_4k; |
247 | u32 num_sys_pages; | |
31a78a5a YH |
248 | u32 num_static_sys_pages; |
249 | u32 total_num_bfregs; | |
250 | u32 num_dyn_bfregs; | |
e126ba97 EC |
251 | }; |
252 | ||
253 | struct mlx5_cmd_first { | |
254 | __be32 data[4]; | |
255 | }; | |
256 | ||
257 | struct mlx5_cmd_msg { | |
258 | struct list_head list; | |
0ac3ea70 | 259 | struct cmd_msg_cache *parent; |
e126ba97 EC |
260 | u32 len; |
261 | struct mlx5_cmd_first first; | |
262 | struct mlx5_cmd_mailbox *next; | |
263 | }; | |
264 | ||
265 | struct mlx5_cmd_debug { | |
266 | struct dentry *dbg_root; | |
267 | struct dentry *dbg_in; | |
268 | struct dentry *dbg_out; | |
269 | struct dentry *dbg_outlen; | |
270 | struct dentry *dbg_status; | |
271 | struct dentry *dbg_run; | |
272 | void *in_msg; | |
273 | void *out_msg; | |
274 | u8 status; | |
275 | u16 inlen; | |
276 | u16 outlen; | |
277 | }; | |
278 | ||
0ac3ea70 | 279 | struct cmd_msg_cache { |
e126ba97 EC |
280 | /* protect block chain allocations |
281 | */ | |
282 | spinlock_t lock; | |
283 | struct list_head head; | |
0ac3ea70 MHY |
284 | unsigned int max_inbox_size; |
285 | unsigned int num_ent; | |
e126ba97 EC |
286 | }; |
287 | ||
0ac3ea70 MHY |
288 | enum { |
289 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
290 | }; |
291 | ||
292 | struct mlx5_cmd_stats { | |
293 | u64 sum; | |
294 | u64 n; | |
295 | struct dentry *root; | |
296 | struct dentry *avg; | |
297 | struct dentry *count; | |
298 | /* protect command average calculations */ | |
299 | spinlock_t lock; | |
300 | }; | |
301 | ||
302 | struct mlx5_cmd { | |
64599cca EC |
303 | void *cmd_alloc_buf; |
304 | dma_addr_t alloc_dma; | |
305 | int alloc_size; | |
e126ba97 EC |
306 | void *cmd_buf; |
307 | dma_addr_t dma; | |
308 | u16 cmdif_rev; | |
309 | u8 log_sz; | |
310 | u8 log_stride; | |
311 | int max_reg_cmds; | |
312 | int events; | |
313 | u32 __iomem *vector; | |
314 | ||
315 | /* protect command queue allocations | |
316 | */ | |
317 | spinlock_t alloc_lock; | |
318 | ||
319 | /* protect token allocations | |
320 | */ | |
321 | spinlock_t token_lock; | |
322 | u8 token; | |
323 | unsigned long bitmask; | |
324 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
325 | struct workqueue_struct *wq; | |
326 | struct semaphore sem; | |
327 | struct semaphore pages_sem; | |
328 | int mode; | |
329 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 330 | struct dma_pool *pool; |
e126ba97 | 331 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 332 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
333 | int checksum_disabled; |
334 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
335 | }; | |
336 | ||
337 | struct mlx5_port_caps { | |
338 | int gid_table_len; | |
339 | int pkey_table_len; | |
938fe83c | 340 | u8 ext_port_cap; |
c43f1112 | 341 | bool has_smi; |
e126ba97 EC |
342 | }; |
343 | ||
344 | struct mlx5_cmd_mailbox { | |
345 | void *buf; | |
346 | dma_addr_t dma; | |
347 | struct mlx5_cmd_mailbox *next; | |
348 | }; | |
349 | ||
350 | struct mlx5_buf_list { | |
351 | void *buf; | |
352 | dma_addr_t map; | |
353 | }; | |
354 | ||
1c1b5228 TT |
355 | struct mlx5_frag_buf { |
356 | struct mlx5_buf_list *frags; | |
357 | int npages; | |
358 | int size; | |
359 | u8 page_shift; | |
360 | }; | |
361 | ||
388ca8be YC |
362 | struct mlx5_frag_buf_ctrl { |
363 | struct mlx5_frag_buf frag_buf; | |
364 | u32 sz_m1; | |
365 | u32 frag_sz_m1; | |
d7037ad7 | 366 | u32 strides_offset; |
388ca8be YC |
367 | u8 log_sz; |
368 | u8 log_stride; | |
369 | u8 log_frag_strides; | |
370 | }; | |
371 | ||
94c6825e MB |
372 | struct mlx5_eq_tasklet { |
373 | struct list_head list; | |
374 | struct list_head process_list; | |
375 | struct tasklet_struct task; | |
376 | /* lock on completion tasklet list */ | |
377 | spinlock_t lock; | |
378 | }; | |
379 | ||
d9aaed83 AK |
380 | struct mlx5_eq_pagefault { |
381 | struct work_struct work; | |
382 | /* Pagefaults lock */ | |
383 | spinlock_t lock; | |
384 | struct workqueue_struct *wq; | |
385 | mempool_t *pool; | |
386 | }; | |
387 | ||
02d92f79 SM |
388 | struct mlx5_cq_table { |
389 | /* protect radix tree */ | |
390 | spinlock_t lock; | |
391 | struct radix_tree_root tree; | |
392 | }; | |
393 | ||
e126ba97 EC |
394 | struct mlx5_eq { |
395 | struct mlx5_core_dev *dev; | |
02d92f79 | 396 | struct mlx5_cq_table cq_table; |
e126ba97 EC |
397 | __be32 __iomem *doorbell; |
398 | u32 cons_index; | |
388ca8be | 399 | struct mlx5_frag_buf buf; |
e126ba97 | 400 | int size; |
0b6e26ce | 401 | unsigned int irqn; |
e126ba97 EC |
402 | u8 eqn; |
403 | int nent; | |
404 | u64 mask; | |
e126ba97 EC |
405 | struct list_head list; |
406 | int index; | |
407 | struct mlx5_rsc_debug *dbg; | |
d9aaed83 AK |
408 | enum mlx5_eq_type type; |
409 | union { | |
410 | struct mlx5_eq_tasklet tasklet_ctx; | |
411 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
412 | struct mlx5_eq_pagefault pf_ctx; | |
413 | #endif | |
414 | }; | |
e126ba97 EC |
415 | }; |
416 | ||
3121e3c4 SG |
417 | struct mlx5_core_psv { |
418 | u32 psv_idx; | |
419 | struct psv_layout { | |
420 | u32 pd; | |
421 | u16 syndrome; | |
422 | u16 reserved; | |
423 | u16 bg; | |
424 | u16 app_tag; | |
425 | u32 ref_tag; | |
426 | } psv; | |
427 | }; | |
428 | ||
429 | struct mlx5_core_sig_ctx { | |
430 | struct mlx5_core_psv psv_memory; | |
431 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
432 | struct ib_sig_err err_item; |
433 | bool sig_status_checked; | |
434 | bool sig_err_exists; | |
435 | u32 sigerr_count; | |
3121e3c4 | 436 | }; |
e126ba97 | 437 | |
aa8e08d2 AK |
438 | enum { |
439 | MLX5_MKEY_MR = 1, | |
440 | MLX5_MKEY_MW, | |
441 | }; | |
442 | ||
a606b0f6 | 443 | struct mlx5_core_mkey { |
e126ba97 EC |
444 | u64 iova; |
445 | u64 size; | |
446 | u32 key; | |
447 | u32 pd; | |
aa8e08d2 | 448 | u32 type; |
e126ba97 EC |
449 | }; |
450 | ||
d9aaed83 AK |
451 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
452 | ||
5903325a | 453 | enum mlx5_res_type { |
e2013b21 | 454 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
455 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
456 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
457 | MLX5_RES_SRQ = 3, | |
458 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 459 | MLX5_RES_XRQ = 5, |
57cda166 | 460 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
461 | }; |
462 | ||
463 | struct mlx5_core_rsc_common { | |
464 | enum mlx5_res_type res; | |
465 | atomic_t refcount; | |
466 | struct completion free; | |
467 | }; | |
468 | ||
e126ba97 | 469 | struct mlx5_core_srq { |
01949d01 | 470 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
471 | u32 srqn; |
472 | int max; | |
c2b37f76 BP |
473 | size_t max_gs; |
474 | size_t max_avail_gather; | |
e126ba97 EC |
475 | int wqe_shift; |
476 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
477 | ||
478 | atomic_t refcount; | |
479 | struct completion free; | |
480 | }; | |
481 | ||
482 | struct mlx5_eq_table { | |
483 | void __iomem *update_ci; | |
484 | void __iomem *update_arm_ci; | |
233d05d2 | 485 | struct list_head comp_eqs_list; |
e126ba97 EC |
486 | struct mlx5_eq pages_eq; |
487 | struct mlx5_eq async_eq; | |
488 | struct mlx5_eq cmd_eq; | |
d9aaed83 AK |
489 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
490 | struct mlx5_eq pfault_eq; | |
491 | #endif | |
e126ba97 EC |
492 | int num_comp_vectors; |
493 | /* protect EQs list | |
494 | */ | |
495 | spinlock_t lock; | |
496 | }; | |
497 | ||
a6d51b68 | 498 | struct mlx5_uars_page { |
e126ba97 | 499 | void __iomem *map; |
a6d51b68 EC |
500 | bool wc; |
501 | u32 index; | |
502 | struct list_head list; | |
503 | unsigned int bfregs; | |
504 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
505 | unsigned long *fp_bitmap; | |
506 | unsigned int reg_avail; | |
507 | unsigned int fp_avail; | |
508 | struct kref ref_count; | |
509 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
510 | }; |
511 | ||
a6d51b68 EC |
512 | struct mlx5_bfreg_head { |
513 | /* protect blue flame registers allocations */ | |
514 | struct mutex lock; | |
515 | struct list_head list; | |
516 | }; | |
517 | ||
518 | struct mlx5_bfreg_data { | |
519 | struct mlx5_bfreg_head reg_head; | |
520 | struct mlx5_bfreg_head wc_head; | |
521 | }; | |
522 | ||
523 | struct mlx5_sq_bfreg { | |
524 | void __iomem *map; | |
525 | struct mlx5_uars_page *up; | |
526 | bool wc; | |
527 | u32 index; | |
528 | unsigned int offset; | |
529 | }; | |
e126ba97 EC |
530 | |
531 | struct mlx5_core_health { | |
532 | struct health_buffer __iomem *health; | |
533 | __be32 __iomem *health_counter; | |
534 | struct timer_list timer; | |
e126ba97 EC |
535 | u32 prev; |
536 | int miss_counter; | |
fd76ee4d | 537 | bool sick; |
05ac2c0b MHY |
538 | /* wq spinlock to synchronize draining */ |
539 | spinlock_t wq_lock; | |
ac6ea6e8 | 540 | struct workqueue_struct *wq; |
05ac2c0b | 541 | unsigned long flags; |
ac6ea6e8 | 542 | struct work_struct work; |
04c0c1ab | 543 | struct delayed_work recover_work; |
e126ba97 EC |
544 | }; |
545 | ||
e126ba97 EC |
546 | struct mlx5_qp_table { |
547 | /* protect radix tree | |
548 | */ | |
549 | spinlock_t lock; | |
550 | struct radix_tree_root tree; | |
551 | }; | |
552 | ||
553 | struct mlx5_srq_table { | |
554 | /* protect radix tree | |
555 | */ | |
556 | spinlock_t lock; | |
557 | struct radix_tree_root tree; | |
558 | }; | |
559 | ||
a606b0f6 | 560 | struct mlx5_mkey_table { |
3bcdb17a SG |
561 | /* protect radix tree |
562 | */ | |
563 | rwlock_t lock; | |
564 | struct radix_tree_root tree; | |
565 | }; | |
566 | ||
fc50db98 EC |
567 | struct mlx5_vf_context { |
568 | int enabled; | |
7ecf6d8f BW |
569 | u64 port_guid; |
570 | u64 node_guid; | |
571 | enum port_state_policy policy; | |
fc50db98 EC |
572 | }; |
573 | ||
574 | struct mlx5_core_sriov { | |
575 | struct mlx5_vf_context *vfs_ctx; | |
576 | int num_vfs; | |
577 | int enabled_vfs; | |
578 | }; | |
579 | ||
db058a18 | 580 | struct mlx5_irq_info { |
231243c8 | 581 | cpumask_var_t mask; |
db058a18 SM |
582 | char name[MLX5_MAX_IRQ_NAME]; |
583 | }; | |
584 | ||
43a335e0 | 585 | struct mlx5_fc_stats { |
9aff93d7 | 586 | struct list_head counters; |
83033688 | 587 | struct llist_head addlist; |
6e5e2283 | 588 | struct llist_head dellist; |
43a335e0 AV |
589 | |
590 | struct workqueue_struct *wq; | |
591 | struct delayed_work work; | |
592 | unsigned long next_query; | |
f6dfb4c3 | 593 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
594 | }; |
595 | ||
eeb66cdb | 596 | struct mlx5_mpfs; |
073bb189 | 597 | struct mlx5_eswitch; |
7907f23a | 598 | struct mlx5_lag; |
d9aaed83 | 599 | struct mlx5_pagefault; |
073bb189 | 600 | |
05d3ac97 BW |
601 | struct mlx5_rate_limit { |
602 | u32 rate; | |
603 | u32 max_burst_sz; | |
604 | u16 typical_pkt_sz; | |
605 | }; | |
606 | ||
1466cc5b | 607 | struct mlx5_rl_entry { |
05d3ac97 | 608 | struct mlx5_rate_limit rl; |
1466cc5b YP |
609 | u16 index; |
610 | u16 refcount; | |
611 | }; | |
612 | ||
613 | struct mlx5_rl_table { | |
614 | /* protect rate limit table */ | |
615 | struct mutex rl_lock; | |
616 | u16 max_size; | |
617 | u32 max_rate; | |
618 | u32 min_rate; | |
619 | struct mlx5_rl_entry *rl_entry; | |
620 | }; | |
621 | ||
d4eb4cd7 HN |
622 | enum port_module_event_status_type { |
623 | MLX5_MODULE_STATUS_PLUGGED = 0x1, | |
624 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, | |
625 | MLX5_MODULE_STATUS_ERROR = 0x3, | |
626 | MLX5_MODULE_STATUS_NUM = 0x3, | |
627 | }; | |
628 | ||
629 | enum port_module_event_error_type { | |
630 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, | |
631 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, | |
632 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, | |
633 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, | |
634 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, | |
635 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, | |
636 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, | |
637 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, | |
638 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, | |
639 | MLX5_MODULE_EVENT_ERROR_NUM, | |
640 | }; | |
641 | ||
642 | struct mlx5_port_module_event_stats { | |
643 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; | |
644 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; | |
645 | }; | |
646 | ||
e126ba97 EC |
647 | struct mlx5_priv { |
648 | char name[MLX5_MAX_NAME_LEN]; | |
649 | struct mlx5_eq_table eq_table; | |
db058a18 | 650 | struct mlx5_irq_info *irq_info; |
e126ba97 EC |
651 | |
652 | /* pages stuff */ | |
653 | struct workqueue_struct *pg_wq; | |
654 | struct rb_root page_root; | |
655 | int fw_pages; | |
6aec21f6 | 656 | atomic_t reg_pages; |
bf0bf77f | 657 | struct list_head free_list; |
fc50db98 | 658 | int vfs_pages; |
e126ba97 EC |
659 | |
660 | struct mlx5_core_health health; | |
661 | ||
662 | struct mlx5_srq_table srq_table; | |
663 | ||
664 | /* start: qp staff */ | |
665 | struct mlx5_qp_table qp_table; | |
666 | struct dentry *qp_debugfs; | |
667 | struct dentry *eq_debugfs; | |
668 | struct dentry *cq_debugfs; | |
669 | struct dentry *cmdif_debugfs; | |
670 | /* end: qp staff */ | |
671 | ||
a606b0f6 MB |
672 | /* start: mkey staff */ |
673 | struct mlx5_mkey_table mkey_table; | |
674 | /* end: mkey staff */ | |
3bcdb17a | 675 | |
e126ba97 | 676 | /* start: alloc staff */ |
311c7c71 SM |
677 | /* protect buffer alocation according to numa node */ |
678 | struct mutex alloc_mutex; | |
679 | int numa_node; | |
680 | ||
e126ba97 EC |
681 | struct mutex pgdir_mutex; |
682 | struct list_head pgdir_list; | |
683 | /* end: alloc staff */ | |
684 | struct dentry *dbg_root; | |
685 | ||
686 | /* protect mkey key part */ | |
687 | spinlock_t mkey_lock; | |
688 | u8 mkey_key; | |
9603b61d JM |
689 | |
690 | struct list_head dev_list; | |
691 | struct list_head ctx_list; | |
692 | spinlock_t ctx_lock; | |
073bb189 | 693 | |
97834eba ES |
694 | struct list_head waiting_events_list; |
695 | bool is_accum_events; | |
696 | ||
fba53f7b | 697 | struct mlx5_flow_steering *steering; |
eeb66cdb | 698 | struct mlx5_mpfs *mpfs; |
073bb189 | 699 | struct mlx5_eswitch *eswitch; |
fc50db98 | 700 | struct mlx5_core_sriov sriov; |
7907f23a | 701 | struct mlx5_lag *lag; |
fc50db98 | 702 | unsigned long pci_dev_data; |
43a335e0 | 703 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 704 | struct mlx5_rl_table rl_table; |
d4eb4cd7 HN |
705 | |
706 | struct mlx5_port_module_event_stats pme_stats; | |
d9aaed83 AK |
707 | |
708 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
709 | void (*pfault)(struct mlx5_core_dev *dev, | |
710 | void *context, | |
711 | struct mlx5_pagefault *pfault); | |
712 | void *pfault_ctx; | |
713 | struct srcu_struct pfault_srcu; | |
714 | #endif | |
a6d51b68 | 715 | struct mlx5_bfreg_data bfregs; |
01187175 | 716 | struct mlx5_uars_page *uar; |
e126ba97 EC |
717 | }; |
718 | ||
89d44f0a MD |
719 | enum mlx5_device_state { |
720 | MLX5_DEVICE_STATE_UP, | |
721 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
722 | }; | |
723 | ||
724 | enum mlx5_interface_state { | |
b3cb5388 | 725 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
726 | }; |
727 | ||
728 | enum mlx5_pci_status { | |
729 | MLX5_PCI_STATUS_DISABLED, | |
730 | MLX5_PCI_STATUS_ENABLED, | |
731 | }; | |
732 | ||
d9aaed83 AK |
733 | enum mlx5_pagefault_type_flags { |
734 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
735 | MLX5_PFAULT_WRITE = 1 << 1, | |
736 | MLX5_PFAULT_RDMA = 1 << 2, | |
737 | }; | |
738 | ||
739 | /* Contains the details of a pagefault. */ | |
740 | struct mlx5_pagefault { | |
741 | u32 bytes_committed; | |
742 | u32 token; | |
743 | u8 event_subtype; | |
744 | u8 type; | |
745 | union { | |
746 | /* Initiator or send message responder pagefault details. */ | |
747 | struct { | |
748 | /* Received packet size, only valid for responders. */ | |
749 | u32 packet_size; | |
750 | /* | |
751 | * Number of resource holding WQE, depends on type. | |
752 | */ | |
753 | u32 wq_num; | |
754 | /* | |
755 | * WQE index. Refers to either the send queue or | |
756 | * receive queue, according to event_subtype. | |
757 | */ | |
758 | u16 wqe_index; | |
759 | } wqe; | |
760 | /* RDMA responder pagefault details */ | |
761 | struct { | |
762 | u32 r_key; | |
763 | /* | |
764 | * Received packet size, minimal size page fault | |
765 | * resolution required for forward progress. | |
766 | */ | |
767 | u32 packet_size; | |
768 | u32 rdma_op_len; | |
769 | u64 rdma_va; | |
770 | } rdma; | |
771 | }; | |
772 | ||
773 | struct mlx5_eq *eq; | |
774 | struct work_struct work; | |
775 | }; | |
776 | ||
b50d292b HHZ |
777 | struct mlx5_td { |
778 | struct list_head tirs_list; | |
779 | u32 tdn; | |
780 | }; | |
781 | ||
782 | struct mlx5e_resources { | |
b50d292b HHZ |
783 | u32 pdn; |
784 | struct mlx5_td td; | |
785 | struct mlx5_core_mkey mkey; | |
aff26157 | 786 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
787 | }; |
788 | ||
52ec462e IT |
789 | #define MLX5_MAX_RESERVED_GIDS 8 |
790 | ||
791 | struct mlx5_rsvd_gids { | |
792 | unsigned int start; | |
793 | unsigned int count; | |
794 | struct ida ida; | |
795 | }; | |
796 | ||
7c39afb3 FD |
797 | #define MAX_PIN_NUM 8 |
798 | struct mlx5_pps { | |
799 | u8 pin_caps[MAX_PIN_NUM]; | |
800 | struct work_struct out_work; | |
801 | u64 start[MAX_PIN_NUM]; | |
802 | u8 enabled; | |
803 | }; | |
804 | ||
805 | struct mlx5_clock { | |
806 | rwlock_t lock; | |
807 | struct cyclecounter cycles; | |
808 | struct timecounter tc; | |
809 | struct hwtstamp_config hwtstamp_config; | |
810 | u32 nominal_c_mult; | |
811 | unsigned long overflow_period; | |
812 | struct delayed_work overflow_work; | |
24d33d2c | 813 | struct mlx5_core_dev *mdev; |
7c39afb3 FD |
814 | struct ptp_clock *ptp; |
815 | struct ptp_clock_info ptp_info; | |
816 | struct mlx5_pps pps_info; | |
817 | }; | |
818 | ||
f53aaa31 | 819 | struct mlx5_fw_tracer; |
358aa5ce | 820 | struct mlx5_vxlan; |
f53aaa31 | 821 | |
e126ba97 EC |
822 | struct mlx5_core_dev { |
823 | struct pci_dev *pdev; | |
89d44f0a MD |
824 | /* sync pci state */ |
825 | struct mutex pci_status_mutex; | |
826 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
827 | u8 rev_id; |
828 | char board_id[MLX5_BOARD_ID_LEN]; | |
829 | struct mlx5_cmd cmd; | |
938fe83c | 830 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 831 | struct { |
701052c5 GP |
832 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
833 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
834 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
835 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 836 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 837 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
71862561 | 838 | } caps; |
e126ba97 EC |
839 | phys_addr_t iseg_base; |
840 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
841 | enum mlx5_device_state state; |
842 | /* sync interface state */ | |
843 | struct mutex intf_state_mutex; | |
5fc7197d | 844 | unsigned long intf_state; |
e126ba97 EC |
845 | void (*event) (struct mlx5_core_dev *dev, |
846 | enum mlx5_dev_event event, | |
4d2f9bbb | 847 | unsigned long param); |
e126ba97 EC |
848 | struct mlx5_priv priv; |
849 | struct mlx5_profile *profile; | |
850 | atomic_t num_qps; | |
f62b8bb8 | 851 | u32 issi; |
b50d292b | 852 | struct mlx5e_resources mlx5e_res; |
358aa5ce | 853 | struct mlx5_vxlan *vxlan; |
52ec462e IT |
854 | struct { |
855 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 856 | u32 roce_en; |
52ec462e | 857 | } roce; |
e29341fb IT |
858 | #ifdef CONFIG_MLX5_FPGA |
859 | struct mlx5_fpga_device *fpga; | |
860 | #endif | |
5a7b27eb MG |
861 | #ifdef CONFIG_RFS_ACCEL |
862 | struct cpu_rmap *rmap; | |
863 | #endif | |
7c39afb3 | 864 | struct mlx5_clock clock; |
24d33d2c FD |
865 | struct mlx5_ib_clock_info *clock_info; |
866 | struct page *clock_info_page; | |
f53aaa31 | 867 | struct mlx5_fw_tracer *tracer; |
e126ba97 EC |
868 | }; |
869 | ||
870 | struct mlx5_db { | |
871 | __be32 *db; | |
872 | union { | |
873 | struct mlx5_db_pgdir *pgdir; | |
874 | struct mlx5_ib_user_db_page *user_page; | |
875 | } u; | |
876 | dma_addr_t dma; | |
877 | int index; | |
878 | }; | |
879 | ||
e126ba97 EC |
880 | enum { |
881 | MLX5_COMP_EQ_SIZE = 1024, | |
882 | }; | |
883 | ||
adb0c954 SM |
884 | enum { |
885 | MLX5_PTYS_IB = 1 << 0, | |
886 | MLX5_PTYS_EN = 1 << 2, | |
887 | }; | |
888 | ||
e126ba97 EC |
889 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
890 | ||
73dd3a48 MHY |
891 | enum { |
892 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
893 | }; | |
894 | ||
e126ba97 | 895 | struct mlx5_cmd_work_ent { |
73dd3a48 | 896 | unsigned long state; |
e126ba97 EC |
897 | struct mlx5_cmd_msg *in; |
898 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
899 | void *uout; |
900 | int uout_size; | |
e126ba97 | 901 | mlx5_cmd_cbk_t callback; |
65ee6708 | 902 | struct delayed_work cb_timeout_work; |
e126ba97 | 903 | void *context; |
746b5583 | 904 | int idx; |
e126ba97 EC |
905 | struct completion done; |
906 | struct mlx5_cmd *cmd; | |
907 | struct work_struct work; | |
908 | struct mlx5_cmd_layout *lay; | |
909 | int ret; | |
910 | int page_queue; | |
911 | u8 status; | |
912 | u8 token; | |
14a70046 TG |
913 | u64 ts1; |
914 | u64 ts2; | |
746b5583 | 915 | u16 op; |
4525abea | 916 | bool polling; |
e126ba97 EC |
917 | }; |
918 | ||
919 | struct mlx5_pas { | |
920 | u64 pa; | |
921 | u8 log_sz; | |
922 | }; | |
923 | ||
707c4602 MD |
924 | enum phy_port_state { |
925 | MLX5_AAA_111 | |
926 | }; | |
927 | ||
928 | struct mlx5_hca_vport_context { | |
929 | u32 field_select; | |
930 | bool sm_virt_aware; | |
931 | bool has_smi; | |
932 | bool has_raw; | |
933 | enum port_state_policy policy; | |
934 | enum phy_port_state phys_state; | |
935 | enum ib_port_state vport_state; | |
936 | u8 port_physical_state; | |
937 | u64 sys_image_guid; | |
938 | u64 port_guid; | |
939 | u64 node_guid; | |
940 | u32 cap_mask1; | |
941 | u32 cap_mask1_perm; | |
942 | u32 cap_mask2; | |
943 | u32 cap_mask2_perm; | |
944 | u16 lid; | |
945 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
946 | u8 lmc; | |
947 | u8 subnet_timeout; | |
948 | u16 sm_lid; | |
949 | u8 sm_sl; | |
950 | u16 qkey_violation_counter; | |
951 | u16 pkey_violation_counter; | |
952 | bool grh_required; | |
953 | }; | |
954 | ||
388ca8be | 955 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 956 | { |
388ca8be | 957 | return buf->frags->buf + offset; |
e126ba97 EC |
958 | } |
959 | ||
e126ba97 EC |
960 | #define STRUCT_FIELD(header, field) \ |
961 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
962 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
963 | ||
e126ba97 EC |
964 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
965 | { | |
966 | return pci_get_drvdata(pdev); | |
967 | } | |
968 | ||
969 | extern struct dentry *mlx5_debugfs_root; | |
970 | ||
971 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
972 | { | |
973 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
974 | } | |
975 | ||
976 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
977 | { | |
978 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
979 | } | |
980 | ||
981 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
982 | { | |
983 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
984 | } | |
985 | ||
986 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
987 | { | |
988 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
989 | } | |
990 | ||
3bcdb17a SG |
991 | static inline u32 mlx5_base_mkey(const u32 key) |
992 | { | |
993 | return key & 0xffffff00u; | |
994 | } | |
995 | ||
d7037ad7 TT |
996 | static inline void mlx5_fill_fbc_offset(u8 log_stride, u8 log_sz, |
997 | u32 strides_offset, | |
998 | struct mlx5_frag_buf_ctrl *fbc) | |
388ca8be | 999 | { |
3a2f7033 TT |
1000 | fbc->log_stride = log_stride; |
1001 | fbc->log_sz = log_sz; | |
388ca8be YC |
1002 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
1003 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
1004 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
1005 | fbc->strides_offset = strides_offset; |
1006 | } | |
1007 | ||
1008 | static inline void mlx5_fill_fbc(u8 log_stride, u8 log_sz, | |
1009 | struct mlx5_frag_buf_ctrl *fbc) | |
1010 | { | |
1011 | mlx5_fill_fbc_offset(log_stride, log_sz, 0, fbc); | |
388ca8be YC |
1012 | } |
1013 | ||
3a2f7033 TT |
1014 | static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc, |
1015 | void *cqc) | |
1016 | { | |
1017 | mlx5_fill_fbc(6 + MLX5_GET(cqc, cqc, cqe_sz), | |
1018 | MLX5_GET(cqc, cqc, log_cq_size), | |
1019 | fbc); | |
1020 | } | |
1021 | ||
388ca8be YC |
1022 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
1023 | u32 ix) | |
1024 | { | |
d7037ad7 TT |
1025 | unsigned int frag; |
1026 | ||
1027 | ix += fbc->strides_offset; | |
1028 | frag = ix >> fbc->log_frag_strides; | |
388ca8be YC |
1029 | |
1030 | return fbc->frag_buf.frags[frag].buf + | |
1031 | ((fbc->frag_sz_m1 & ix) << fbc->log_stride); | |
1032 | } | |
1033 | ||
e126ba97 EC |
1034 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
1035 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
1036 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
1037 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 1038 | |
e126ba97 EC |
1039 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
1040 | int out_size); | |
746b5583 EC |
1041 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
1042 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
1043 | void *context); | |
4525abea MD |
1044 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
1045 | void *out, int out_size); | |
c4f287c4 SM |
1046 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
1047 | ||
1048 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
1049 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
1050 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
1051 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
1052 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
1053 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
1054 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
05ac2c0b | 1055 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 1056 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
2a0165a0 | 1057 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
311c7c71 | 1058 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
388ca8be YC |
1059 | struct mlx5_frag_buf *buf, int node); |
1060 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, | |
1061 | int size, struct mlx5_frag_buf *buf); | |
1062 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
1063 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
1064 | struct mlx5_frag_buf *buf, int node); | |
1065 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
1066 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
1067 | gfp_t flags, int npages); | |
1068 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
1069 | struct mlx5_cmd_mailbox *head); | |
1070 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 1071 | struct mlx5_srq_attr *in); |
e126ba97 EC |
1072 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
1073 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 1074 | struct mlx5_srq_attr *out); |
e126ba97 EC |
1075 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
1076 | u16 lwm, int is_srq); | |
a606b0f6 MB |
1077 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
1078 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
1079 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
1080 | struct mlx5_core_mkey *mkey, | |
1081 | u32 *in, int inlen, | |
1082 | u32 *out, int outlen, | |
1083 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
1084 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
1085 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1086 | u32 *in, int inlen); |
a606b0f6 MB |
1087 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
1088 | struct mlx5_core_mkey *mkey); | |
1089 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1090 | u32 *out, int outlen); |
e126ba97 EC |
1091 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
1092 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 1093 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 1094 | u16 opmod, u8 port); |
e126ba97 EC |
1095 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
1096 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
1097 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
1098 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
1099 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 1100 | s32 npages); |
cd23b14b | 1101 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
1102 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
1103 | void mlx5_register_debugfs(void); | |
1104 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
1105 | |
1106 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 1107 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
5903325a | 1108 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e126ba97 EC |
1109 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
1110 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
0b6e26ce DT |
1111 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
1112 | unsigned int *irqn); | |
e126ba97 EC |
1113 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
1114 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
1115 | ||
1116 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
1117 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1118 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
1119 | int size_in, void *data_out, int size_out, | |
1120 | u16 reg_num, int arg, int write); | |
adb0c954 | 1121 | |
e126ba97 | 1122 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
1123 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
1124 | int node); | |
e126ba97 EC |
1125 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
1126 | ||
e126ba97 EC |
1127 | const char *mlx5_command_str(int command); |
1128 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
1129 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
1130 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
1131 | int npsvs, u32 *sig_index); | |
1132 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1133 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1134 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1135 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1136 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1137 | u8 port_num, void *out, size_t sz); | |
d9aaed83 AK |
1138 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1139 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, | |
1140 | u32 wq_num, u8 type, int error); | |
1141 | #endif | |
e126ba97 | 1142 | |
1466cc5b YP |
1143 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1144 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
1145 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
1146 | struct mlx5_rate_limit *rl); | |
1147 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 1148 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
05d3ac97 BW |
1149 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
1150 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
1151 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1152 | bool map_wc, bool fast_path); | |
1153 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1154 | |
52ec462e IT |
1155 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1156 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1157 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1158 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1159 | |
e3297246 EC |
1160 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1161 | { | |
1162 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1163 | } | |
1164 | ||
e126ba97 EC |
1165 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1166 | { | |
1167 | return mkey >> 8; | |
1168 | } | |
1169 | ||
1170 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1171 | { | |
1172 | return mkey_idx << 8; | |
1173 | } | |
1174 | ||
746b5583 EC |
1175 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1176 | { | |
1177 | return mkey & 0xff; | |
1178 | } | |
1179 | ||
e126ba97 EC |
1180 | enum { |
1181 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1182 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1183 | }; |
1184 | ||
1185 | enum { | |
8b7ff7f3 | 1186 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1187 | MLX5_IMR_MTT_CACHE_ENTRY, |
1188 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1189 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1190 | }; |
1191 | ||
64613d94 SM |
1192 | enum { |
1193 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1194 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1195 | }; | |
1196 | ||
9603b61d JM |
1197 | struct mlx5_interface { |
1198 | void * (*add)(struct mlx5_core_dev *dev); | |
1199 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1200 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1201 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 1202 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1203 | enum mlx5_dev_event event, unsigned long param); |
d9aaed83 AK |
1204 | void (*pfault)(struct mlx5_core_dev *dev, |
1205 | void *context, | |
1206 | struct mlx5_pagefault *pfault); | |
64613d94 SM |
1207 | void * (*get_dev)(void *context); |
1208 | int protocol; | |
9603b61d JM |
1209 | struct list_head list; |
1210 | }; | |
1211 | ||
64613d94 | 1212 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
1213 | int mlx5_register_interface(struct mlx5_interface *intf); |
1214 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 1215 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1216 | |
3bc34f3b AH |
1217 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1218 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 1219 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1220 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1221 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1222 | u64 *values, | |
1223 | int num_counters, | |
1224 | size_t *offsets); | |
01187175 EC |
1225 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1226 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1227 | |
693dfd5a ES |
1228 | #ifndef CONFIG_MLX5_CORE_IPOIB |
1229 | static inline | |
1230 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1231 | struct ib_device *ibdev, | |
1232 | const char *name, | |
1233 | void (*setup)(struct net_device *)) | |
1234 | { | |
1235 | return ERR_PTR(-EOPNOTSUPP); | |
1236 | } | |
693dfd5a ES |
1237 | #else |
1238 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1239 | struct ib_device *ibdev, | |
1240 | const char *name, | |
1241 | void (*setup)(struct net_device *)); | |
693dfd5a ES |
1242 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
1243 | ||
e126ba97 EC |
1244 | struct mlx5_profile { |
1245 | u64 mask; | |
f241e749 | 1246 | u8 log_max_qp; |
e126ba97 EC |
1247 | struct { |
1248 | int size; | |
1249 | int limit; | |
1250 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1251 | }; | |
1252 | ||
fc50db98 EC |
1253 | enum { |
1254 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1255 | }; | |
1256 | ||
1257 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1258 | { | |
1259 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1260 | } | |
1261 | ||
57cbd893 MB |
1262 | #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) |
1263 | #define MLX5_VPORT_MANAGER(mdev) \ | |
1264 | (MLX5_CAP_GEN(mdev, vport_group_manager) && \ | |
1265 | (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ | |
1266 | mlx5_core_is_pf(mdev)) | |
1267 | ||
707c4602 MD |
1268 | static inline int mlx5_get_gid_table_len(u16 param) |
1269 | { | |
1270 | if (param > 4) { | |
1271 | pr_warn("gid table length is zero\n"); | |
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | return 8 * (1 << param); | |
1276 | } | |
1277 | ||
1466cc5b YP |
1278 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1279 | { | |
1280 | return !!(dev->priv.rl_table.max_size); | |
1281 | } | |
1282 | ||
32f69e4b DJ |
1283 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1284 | { | |
1285 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1286 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1287 | } | |
1288 | ||
1289 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1290 | { | |
1291 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1292 | } | |
1293 | ||
1294 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1295 | { | |
1296 | return mlx5_core_is_mp_slave(dev) || | |
1297 | mlx5_core_is_mp_master(dev); | |
1298 | } | |
1299 | ||
7fd8aefb DJ |
1300 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1301 | { | |
32f69e4b DJ |
1302 | if (!mlx5_core_mp_enabled(dev)) |
1303 | return 1; | |
1304 | ||
1305 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1306 | } |
1307 | ||
020446e0 EC |
1308 | enum { |
1309 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1310 | }; | |
1311 | ||
a435393a | 1312 | static inline const struct cpumask * |
6082d9c9 | 1313 | mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector) |
a435393a | 1314 | { |
e3ca3488 | 1315 | return dev->priv.irq_info[vector].mask; |
a435393a SG |
1316 | } |
1317 | ||
e126ba97 | 1318 | #endif /* MLX5_DRIVER_H */ |