Commit | Line | Data |
---|---|---|
e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 EC |
43 | #include <linux/vmalloc.h> |
44 | #include <linux/radix-tree.h> | |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
20902be4 | 49 | #include <linux/notifier.h> |
6ecde51d | 50 | |
e126ba97 EC |
51 | #include <linux/mlx5/device.h> |
52 | #include <linux/mlx5/doorbell.h> | |
41069256 | 53 | #include <linux/mlx5/eq.h> |
7c39afb3 FD |
54 | #include <linux/timecounter.h> |
55 | #include <linux/ptp_clock_kernel.h> | |
e126ba97 EC |
56 | |
57 | enum { | |
58 | MLX5_BOARD_ID_LEN = 64, | |
e126ba97 EC |
59 | }; |
60 | ||
61 | enum { | |
62 | /* one minute for the sake of bringup. Generally, commands must always | |
63 | * complete and we may need to increase this timeout value | |
64 | */ | |
6b6c07bd | 65 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
66 | MLX5_CMD_WQ_MAX_NAME = 32, |
67 | }; | |
68 | ||
69 | enum { | |
70 | CMD_OWNER_SW = 0x0, | |
71 | CMD_OWNER_HW = 0x1, | |
72 | CMD_STATUS_SUCCESS = 0, | |
73 | }; | |
74 | ||
75 | enum mlx5_sqp_t { | |
76 | MLX5_SQP_SMI = 0, | |
77 | MLX5_SQP_GSI = 1, | |
78 | MLX5_SQP_IEEE_1588 = 2, | |
79 | MLX5_SQP_SNIFFER = 3, | |
80 | MLX5_SQP_SYNC_UMR = 4, | |
81 | }; | |
82 | ||
83 | enum { | |
84 | MLX5_MAX_PORTS = 2, | |
85 | }; | |
86 | ||
e126ba97 | 87 | enum { |
a60109dc YC |
88 | MLX5_ATOMIC_MODE_OFFSET = 16, |
89 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
90 | MLX5_ATOMIC_MODE_CX = 2, | |
91 | MLX5_ATOMIC_MODE_8B = 3, | |
92 | MLX5_ATOMIC_MODE_16B = 4, | |
93 | MLX5_ATOMIC_MODE_32B = 5, | |
94 | MLX5_ATOMIC_MODE_64B = 6, | |
95 | MLX5_ATOMIC_MODE_128B = 7, | |
96 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
97 | }; |
98 | ||
e126ba97 | 99 | enum { |
415a64aa | 100 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
101 | MLX5_REG_QETCR = 0x4005, |
102 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 103 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 104 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
105 | MLX5_REG_DCBX_PARAM = 0x4020, |
106 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
107 | MLX5_REG_FPGA_CAP = 0x4022, |
108 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 109 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
0b9055a1 | 110 | MLX5_REG_CORE_DUMP = 0x402e, |
e126ba97 EC |
111 | MLX5_REG_PCAP = 0x5001, |
112 | MLX5_REG_PMTU = 0x5003, | |
113 | MLX5_REG_PTYS = 0x5004, | |
114 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 115 | MLX5_REG_PFCC = 0x5007, |
efea389d | 116 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
117 | MLX5_REG_PPTB = 0x500b, |
118 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
119 | MLX5_REG_PMAOS = 0x5012, |
120 | MLX5_REG_PUDE = 0x5009, | |
121 | MLX5_REG_PMPE = 0x5010, | |
122 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 123 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 124 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 125 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 126 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 127 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
128 | MLX5_REG_NODE_DESC = 0x6001, |
129 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 130 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 131 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
132 | MLX5_REG_MTRC_CAP = 0x9040, |
133 | MLX5_REG_MTRC_CONF = 0x9041, | |
134 | MLX5_REG_MTRC_STDB = 0x9042, | |
135 | MLX5_REG_MTRC_CTRL = 0x9043, | |
4039049b | 136 | MLX5_REG_MPEIN = 0x9050, |
8ed1a630 | 137 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
138 | MLX5_REG_MTPPS = 0x9053, |
139 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 140 | MLX5_REG_MPEGC = 0x9056, |
47176289 OG |
141 | MLX5_REG_MCQI = 0x9061, |
142 | MLX5_REG_MCC = 0x9062, | |
143 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 144 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
145 | }; |
146 | ||
415a64aa HN |
147 | enum mlx5_qpts_trust_state { |
148 | MLX5_QPTS_TRUST_PCP = 1, | |
149 | MLX5_QPTS_TRUST_DSCP = 2, | |
150 | }; | |
151 | ||
341c5ee2 HN |
152 | enum mlx5_dcbx_oper_mode { |
153 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
154 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
155 | }; | |
156 | ||
da7525d2 EBE |
157 | enum { |
158 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
159 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
160 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
161 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
162 | }; |
163 | ||
e420f0c0 HE |
164 | enum mlx5_page_fault_resume_flags { |
165 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
166 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
167 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
168 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
169 | }; | |
170 | ||
e126ba97 EC |
171 | enum dbg_rsc_type { |
172 | MLX5_DBG_RSC_QP, | |
173 | MLX5_DBG_RSC_EQ, | |
174 | MLX5_DBG_RSC_CQ, | |
175 | }; | |
176 | ||
7ecf6d8f BW |
177 | enum port_state_policy { |
178 | MLX5_POLICY_DOWN = 0, | |
179 | MLX5_POLICY_UP = 1, | |
180 | MLX5_POLICY_FOLLOW = 2, | |
181 | MLX5_POLICY_INVALID = 0xffffffff | |
182 | }; | |
183 | ||
e126ba97 EC |
184 | struct mlx5_field_desc { |
185 | struct dentry *dent; | |
186 | int i; | |
187 | }; | |
188 | ||
189 | struct mlx5_rsc_debug { | |
190 | struct mlx5_core_dev *dev; | |
191 | void *object; | |
192 | enum dbg_rsc_type type; | |
193 | struct dentry *root; | |
194 | struct mlx5_field_desc fields[0]; | |
195 | }; | |
196 | ||
197 | enum mlx5_dev_event { | |
58d180b3 | 198 | MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ |
6997b1c9 | 199 | MLX5_DEV_EVENT_PORT_AFFINITY = 129, |
e126ba97 EC |
200 | }; |
201 | ||
4c916a79 | 202 | enum mlx5_port_status { |
6fa1bcab AS |
203 | MLX5_PORT_UP = 1, |
204 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
205 | }; |
206 | ||
2f5ff264 | 207 | struct mlx5_bfreg_info { |
b037c29a | 208 | u32 *sys_pages; |
2f5ff264 | 209 | int num_low_latency_bfregs; |
e126ba97 | 210 | unsigned int *count; |
e126ba97 EC |
211 | |
212 | /* | |
2f5ff264 | 213 | * protect bfreg allocation data structs |
e126ba97 EC |
214 | */ |
215 | struct mutex lock; | |
78c0f98c | 216 | u32 ver; |
b037c29a EC |
217 | bool lib_uar_4k; |
218 | u32 num_sys_pages; | |
31a78a5a YH |
219 | u32 num_static_sys_pages; |
220 | u32 total_num_bfregs; | |
221 | u32 num_dyn_bfregs; | |
e126ba97 EC |
222 | }; |
223 | ||
224 | struct mlx5_cmd_first { | |
225 | __be32 data[4]; | |
226 | }; | |
227 | ||
228 | struct mlx5_cmd_msg { | |
229 | struct list_head list; | |
0ac3ea70 | 230 | struct cmd_msg_cache *parent; |
e126ba97 EC |
231 | u32 len; |
232 | struct mlx5_cmd_first first; | |
233 | struct mlx5_cmd_mailbox *next; | |
234 | }; | |
235 | ||
236 | struct mlx5_cmd_debug { | |
237 | struct dentry *dbg_root; | |
238 | struct dentry *dbg_in; | |
239 | struct dentry *dbg_out; | |
240 | struct dentry *dbg_outlen; | |
241 | struct dentry *dbg_status; | |
242 | struct dentry *dbg_run; | |
243 | void *in_msg; | |
244 | void *out_msg; | |
245 | u8 status; | |
246 | u16 inlen; | |
247 | u16 outlen; | |
248 | }; | |
249 | ||
0ac3ea70 | 250 | struct cmd_msg_cache { |
e126ba97 EC |
251 | /* protect block chain allocations |
252 | */ | |
253 | spinlock_t lock; | |
254 | struct list_head head; | |
0ac3ea70 MHY |
255 | unsigned int max_inbox_size; |
256 | unsigned int num_ent; | |
e126ba97 EC |
257 | }; |
258 | ||
0ac3ea70 MHY |
259 | enum { |
260 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
261 | }; |
262 | ||
263 | struct mlx5_cmd_stats { | |
264 | u64 sum; | |
265 | u64 n; | |
266 | struct dentry *root; | |
267 | struct dentry *avg; | |
268 | struct dentry *count; | |
269 | /* protect command average calculations */ | |
270 | spinlock_t lock; | |
271 | }; | |
272 | ||
273 | struct mlx5_cmd { | |
71edc69c SM |
274 | struct mlx5_nb nb; |
275 | ||
64599cca EC |
276 | void *cmd_alloc_buf; |
277 | dma_addr_t alloc_dma; | |
278 | int alloc_size; | |
e126ba97 EC |
279 | void *cmd_buf; |
280 | dma_addr_t dma; | |
281 | u16 cmdif_rev; | |
282 | u8 log_sz; | |
283 | u8 log_stride; | |
284 | int max_reg_cmds; | |
285 | int events; | |
286 | u32 __iomem *vector; | |
287 | ||
288 | /* protect command queue allocations | |
289 | */ | |
290 | spinlock_t alloc_lock; | |
291 | ||
292 | /* protect token allocations | |
293 | */ | |
294 | spinlock_t token_lock; | |
295 | u8 token; | |
296 | unsigned long bitmask; | |
297 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
298 | struct workqueue_struct *wq; | |
299 | struct semaphore sem; | |
300 | struct semaphore pages_sem; | |
301 | int mode; | |
302 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 303 | struct dma_pool *pool; |
e126ba97 | 304 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 305 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
306 | int checksum_disabled; |
307 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
308 | }; | |
309 | ||
310 | struct mlx5_port_caps { | |
311 | int gid_table_len; | |
312 | int pkey_table_len; | |
938fe83c | 313 | u8 ext_port_cap; |
c43f1112 | 314 | bool has_smi; |
e126ba97 EC |
315 | }; |
316 | ||
317 | struct mlx5_cmd_mailbox { | |
318 | void *buf; | |
319 | dma_addr_t dma; | |
320 | struct mlx5_cmd_mailbox *next; | |
321 | }; | |
322 | ||
323 | struct mlx5_buf_list { | |
324 | void *buf; | |
325 | dma_addr_t map; | |
326 | }; | |
327 | ||
1c1b5228 TT |
328 | struct mlx5_frag_buf { |
329 | struct mlx5_buf_list *frags; | |
330 | int npages; | |
331 | int size; | |
332 | u8 page_shift; | |
333 | }; | |
334 | ||
388ca8be | 335 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 336 | struct mlx5_buf_list *frags; |
388ca8be | 337 | u32 sz_m1; |
8d71e818 | 338 | u16 frag_sz_m1; |
a0903622 | 339 | u16 strides_offset; |
388ca8be YC |
340 | u8 log_sz; |
341 | u8 log_stride; | |
342 | u8 log_frag_strides; | |
343 | }; | |
344 | ||
3121e3c4 SG |
345 | struct mlx5_core_psv { |
346 | u32 psv_idx; | |
347 | struct psv_layout { | |
348 | u32 pd; | |
349 | u16 syndrome; | |
350 | u16 reserved; | |
351 | u16 bg; | |
352 | u16 app_tag; | |
353 | u32 ref_tag; | |
354 | } psv; | |
355 | }; | |
356 | ||
357 | struct mlx5_core_sig_ctx { | |
358 | struct mlx5_core_psv psv_memory; | |
359 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
360 | struct ib_sig_err err_item; |
361 | bool sig_status_checked; | |
362 | bool sig_err_exists; | |
363 | u32 sigerr_count; | |
3121e3c4 | 364 | }; |
e126ba97 | 365 | |
aa8e08d2 AK |
366 | enum { |
367 | MLX5_MKEY_MR = 1, | |
368 | MLX5_MKEY_MW, | |
534fd7aa | 369 | MLX5_MKEY_INDIRECT_DEVX, |
aa8e08d2 AK |
370 | }; |
371 | ||
a606b0f6 | 372 | struct mlx5_core_mkey { |
e126ba97 EC |
373 | u64 iova; |
374 | u64 size; | |
375 | u32 key; | |
376 | u32 pd; | |
aa8e08d2 | 377 | u32 type; |
e126ba97 EC |
378 | }; |
379 | ||
d9aaed83 AK |
380 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
381 | ||
5903325a | 382 | enum mlx5_res_type { |
e2013b21 | 383 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
384 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
385 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
386 | MLX5_RES_SRQ = 3, | |
387 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 388 | MLX5_RES_XRQ = 5, |
57cda166 | 389 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
390 | }; |
391 | ||
392 | struct mlx5_core_rsc_common { | |
393 | enum mlx5_res_type res; | |
394 | atomic_t refcount; | |
395 | struct completion free; | |
396 | }; | |
397 | ||
a6d51b68 | 398 | struct mlx5_uars_page { |
e126ba97 | 399 | void __iomem *map; |
a6d51b68 EC |
400 | bool wc; |
401 | u32 index; | |
402 | struct list_head list; | |
403 | unsigned int bfregs; | |
404 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
405 | unsigned long *fp_bitmap; | |
406 | unsigned int reg_avail; | |
407 | unsigned int fp_avail; | |
408 | struct kref ref_count; | |
409 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
410 | }; |
411 | ||
a6d51b68 EC |
412 | struct mlx5_bfreg_head { |
413 | /* protect blue flame registers allocations */ | |
414 | struct mutex lock; | |
415 | struct list_head list; | |
416 | }; | |
417 | ||
418 | struct mlx5_bfreg_data { | |
419 | struct mlx5_bfreg_head reg_head; | |
420 | struct mlx5_bfreg_head wc_head; | |
421 | }; | |
422 | ||
423 | struct mlx5_sq_bfreg { | |
424 | void __iomem *map; | |
425 | struct mlx5_uars_page *up; | |
426 | bool wc; | |
427 | u32 index; | |
428 | unsigned int offset; | |
429 | }; | |
e126ba97 EC |
430 | |
431 | struct mlx5_core_health { | |
432 | struct health_buffer __iomem *health; | |
433 | __be32 __iomem *health_counter; | |
434 | struct timer_list timer; | |
e126ba97 EC |
435 | u32 prev; |
436 | int miss_counter; | |
fd76ee4d | 437 | bool sick; |
8b9d8baa | 438 | u32 crdump_size; |
05ac2c0b MHY |
439 | /* wq spinlock to synchronize draining */ |
440 | spinlock_t wq_lock; | |
ac6ea6e8 | 441 | struct workqueue_struct *wq; |
05ac2c0b | 442 | unsigned long flags; |
ac6ea6e8 | 443 | struct work_struct work; |
04c0c1ab | 444 | struct delayed_work recover_work; |
e126ba97 EC |
445 | }; |
446 | ||
e126ba97 | 447 | struct mlx5_qp_table { |
451be51c | 448 | struct notifier_block nb; |
221c14f3 | 449 | |
e126ba97 EC |
450 | /* protect radix tree |
451 | */ | |
452 | spinlock_t lock; | |
453 | struct radix_tree_root tree; | |
454 | }; | |
455 | ||
a606b0f6 | 456 | struct mlx5_mkey_table { |
3bcdb17a SG |
457 | /* protect radix tree |
458 | */ | |
459 | rwlock_t lock; | |
460 | struct radix_tree_root tree; | |
461 | }; | |
462 | ||
fc50db98 EC |
463 | struct mlx5_vf_context { |
464 | int enabled; | |
7ecf6d8f BW |
465 | u64 port_guid; |
466 | u64 node_guid; | |
467 | enum port_state_policy policy; | |
fc50db98 EC |
468 | }; |
469 | ||
470 | struct mlx5_core_sriov { | |
471 | struct mlx5_vf_context *vfs_ctx; | |
472 | int num_vfs; | |
473 | int enabled_vfs; | |
474 | }; | |
475 | ||
43a335e0 | 476 | struct mlx5_fc_stats { |
12d6066c VB |
477 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
478 | struct idr counters_idr; | |
9aff93d7 | 479 | struct list_head counters; |
83033688 | 480 | struct llist_head addlist; |
6e5e2283 | 481 | struct llist_head dellist; |
43a335e0 AV |
482 | |
483 | struct workqueue_struct *wq; | |
484 | struct delayed_work work; | |
485 | unsigned long next_query; | |
f6dfb4c3 | 486 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
487 | }; |
488 | ||
69c1280b | 489 | struct mlx5_events; |
eeb66cdb | 490 | struct mlx5_mpfs; |
073bb189 | 491 | struct mlx5_eswitch; |
7907f23a | 492 | struct mlx5_lag; |
fadd59fc | 493 | struct mlx5_devcom; |
f2f3df55 | 494 | struct mlx5_eq_table; |
073bb189 | 495 | |
05d3ac97 BW |
496 | struct mlx5_rate_limit { |
497 | u32 rate; | |
498 | u32 max_burst_sz; | |
499 | u16 typical_pkt_sz; | |
500 | }; | |
501 | ||
1466cc5b | 502 | struct mlx5_rl_entry { |
05d3ac97 | 503 | struct mlx5_rate_limit rl; |
1466cc5b YP |
504 | u16 index; |
505 | u16 refcount; | |
506 | }; | |
507 | ||
508 | struct mlx5_rl_table { | |
509 | /* protect rate limit table */ | |
510 | struct mutex rl_lock; | |
511 | u16 max_size; | |
512 | u32 max_rate; | |
513 | u32 min_rate; | |
514 | struct mlx5_rl_entry *rl_entry; | |
515 | }; | |
516 | ||
80f09dfc MG |
517 | struct mlx5_core_roce { |
518 | struct mlx5_flow_table *ft; | |
519 | struct mlx5_flow_group *fg; | |
520 | struct mlx5_flow_handle *allow_rule; | |
521 | }; | |
522 | ||
e126ba97 | 523 | struct mlx5_priv { |
f2f3df55 | 524 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
525 | |
526 | /* pages stuff */ | |
0cf53c12 | 527 | struct mlx5_nb pg_nb; |
e126ba97 EC |
528 | struct workqueue_struct *pg_wq; |
529 | struct rb_root page_root; | |
530 | int fw_pages; | |
6aec21f6 | 531 | atomic_t reg_pages; |
bf0bf77f | 532 | struct list_head free_list; |
fc50db98 | 533 | int vfs_pages; |
591905ba | 534 | int peer_pf_pages; |
e126ba97 EC |
535 | |
536 | struct mlx5_core_health health; | |
537 | ||
e126ba97 EC |
538 | /* start: qp staff */ |
539 | struct mlx5_qp_table qp_table; | |
540 | struct dentry *qp_debugfs; | |
541 | struct dentry *eq_debugfs; | |
542 | struct dentry *cq_debugfs; | |
543 | struct dentry *cmdif_debugfs; | |
544 | /* end: qp staff */ | |
545 | ||
a606b0f6 MB |
546 | /* start: mkey staff */ |
547 | struct mlx5_mkey_table mkey_table; | |
548 | /* end: mkey staff */ | |
3bcdb17a | 549 | |
e126ba97 | 550 | /* start: alloc staff */ |
311c7c71 SM |
551 | /* protect buffer alocation according to numa node */ |
552 | struct mutex alloc_mutex; | |
553 | int numa_node; | |
554 | ||
e126ba97 EC |
555 | struct mutex pgdir_mutex; |
556 | struct list_head pgdir_list; | |
557 | /* end: alloc staff */ | |
558 | struct dentry *dbg_root; | |
559 | ||
560 | /* protect mkey key part */ | |
561 | spinlock_t mkey_lock; | |
562 | u8 mkey_key; | |
9603b61d JM |
563 | |
564 | struct list_head dev_list; | |
565 | struct list_head ctx_list; | |
566 | spinlock_t ctx_lock; | |
02039fb6 | 567 | struct mlx5_events *events; |
97834eba | 568 | |
fba53f7b | 569 | struct mlx5_flow_steering *steering; |
eeb66cdb | 570 | struct mlx5_mpfs *mpfs; |
073bb189 | 571 | struct mlx5_eswitch *eswitch; |
fc50db98 | 572 | struct mlx5_core_sriov sriov; |
7907f23a | 573 | struct mlx5_lag *lag; |
fadd59fc | 574 | struct mlx5_devcom *devcom; |
fc50db98 | 575 | unsigned long pci_dev_data; |
80f09dfc | 576 | struct mlx5_core_roce roce; |
43a335e0 | 577 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 578 | struct mlx5_rl_table rl_table; |
d4eb4cd7 | 579 | |
a6d51b68 | 580 | struct mlx5_bfreg_data bfregs; |
01187175 | 581 | struct mlx5_uars_page *uar; |
e126ba97 EC |
582 | }; |
583 | ||
89d44f0a MD |
584 | enum mlx5_device_state { |
585 | MLX5_DEVICE_STATE_UP, | |
586 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
587 | }; | |
588 | ||
589 | enum mlx5_interface_state { | |
b3cb5388 | 590 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
591 | }; |
592 | ||
593 | enum mlx5_pci_status { | |
594 | MLX5_PCI_STATUS_DISABLED, | |
595 | MLX5_PCI_STATUS_ENABLED, | |
596 | }; | |
597 | ||
d9aaed83 AK |
598 | enum mlx5_pagefault_type_flags { |
599 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
600 | MLX5_PFAULT_WRITE = 1 << 1, | |
601 | MLX5_PFAULT_RDMA = 1 << 2, | |
602 | }; | |
603 | ||
b50d292b | 604 | struct mlx5_td { |
80a2a902 YA |
605 | /* protects tirs list changes while tirs refresh */ |
606 | struct mutex list_lock; | |
b50d292b HHZ |
607 | struct list_head tirs_list; |
608 | u32 tdn; | |
609 | }; | |
610 | ||
611 | struct mlx5e_resources { | |
b50d292b HHZ |
612 | u32 pdn; |
613 | struct mlx5_td td; | |
614 | struct mlx5_core_mkey mkey; | |
aff26157 | 615 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
616 | }; |
617 | ||
52ec462e IT |
618 | #define MLX5_MAX_RESERVED_GIDS 8 |
619 | ||
620 | struct mlx5_rsvd_gids { | |
621 | unsigned int start; | |
622 | unsigned int count; | |
623 | struct ida ida; | |
624 | }; | |
625 | ||
7c39afb3 FD |
626 | #define MAX_PIN_NUM 8 |
627 | struct mlx5_pps { | |
628 | u8 pin_caps[MAX_PIN_NUM]; | |
629 | struct work_struct out_work; | |
630 | u64 start[MAX_PIN_NUM]; | |
631 | u8 enabled; | |
632 | }; | |
633 | ||
634 | struct mlx5_clock { | |
41069256 SM |
635 | struct mlx5_core_dev *mdev; |
636 | struct mlx5_nb pps_nb; | |
64109f1d | 637 | seqlock_t lock; |
7c39afb3 FD |
638 | struct cyclecounter cycles; |
639 | struct timecounter tc; | |
640 | struct hwtstamp_config hwtstamp_config; | |
641 | u32 nominal_c_mult; | |
642 | unsigned long overflow_period; | |
643 | struct delayed_work overflow_work; | |
644 | struct ptp_clock *ptp; | |
645 | struct ptp_clock_info ptp_info; | |
646 | struct mlx5_pps pps_info; | |
647 | }; | |
648 | ||
f53aaa31 | 649 | struct mlx5_fw_tracer; |
358aa5ce | 650 | struct mlx5_vxlan; |
0ccc171e | 651 | struct mlx5_geneve; |
f53aaa31 | 652 | |
e126ba97 | 653 | struct mlx5_core_dev { |
27b942fb | 654 | struct device *device; |
e126ba97 | 655 | struct pci_dev *pdev; |
89d44f0a MD |
656 | /* sync pci state */ |
657 | struct mutex pci_status_mutex; | |
658 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
659 | u8 rev_id; |
660 | char board_id[MLX5_BOARD_ID_LEN]; | |
661 | struct mlx5_cmd cmd; | |
938fe83c | 662 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 663 | struct { |
701052c5 GP |
664 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
665 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
666 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
667 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 668 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 669 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
591905ba | 670 | u8 embedded_cpu; |
71862561 | 671 | } caps; |
59c9d35e | 672 | u64 sys_image_guid; |
e126ba97 EC |
673 | phys_addr_t iseg_base; |
674 | struct mlx5_init_seg __iomem *iseg; | |
aa8106f1 | 675 | phys_addr_t bar_addr; |
89d44f0a MD |
676 | enum mlx5_device_state state; |
677 | /* sync interface state */ | |
678 | struct mutex intf_state_mutex; | |
5fc7197d | 679 | unsigned long intf_state; |
e126ba97 EC |
680 | struct mlx5_priv priv; |
681 | struct mlx5_profile *profile; | |
682 | atomic_t num_qps; | |
f62b8bb8 | 683 | u32 issi; |
b50d292b | 684 | struct mlx5e_resources mlx5e_res; |
358aa5ce | 685 | struct mlx5_vxlan *vxlan; |
0ccc171e | 686 | struct mlx5_geneve *geneve; |
52ec462e IT |
687 | struct { |
688 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 689 | u32 roce_en; |
52ec462e | 690 | } roce; |
e29341fb IT |
691 | #ifdef CONFIG_MLX5_FPGA |
692 | struct mlx5_fpga_device *fpga; | |
5a7b27eb | 693 | #endif |
7c39afb3 | 694 | struct mlx5_clock clock; |
24d33d2c | 695 | struct mlx5_ib_clock_info *clock_info; |
f53aaa31 | 696 | struct mlx5_fw_tracer *tracer; |
b25bbc2f | 697 | u32 vsc_addr; |
e126ba97 EC |
698 | }; |
699 | ||
700 | struct mlx5_db { | |
701 | __be32 *db; | |
702 | union { | |
703 | struct mlx5_db_pgdir *pgdir; | |
704 | struct mlx5_ib_user_db_page *user_page; | |
705 | } u; | |
706 | dma_addr_t dma; | |
707 | int index; | |
708 | }; | |
709 | ||
e126ba97 EC |
710 | enum { |
711 | MLX5_COMP_EQ_SIZE = 1024, | |
712 | }; | |
713 | ||
adb0c954 SM |
714 | enum { |
715 | MLX5_PTYS_IB = 1 << 0, | |
716 | MLX5_PTYS_EN = 1 << 2, | |
717 | }; | |
718 | ||
e126ba97 EC |
719 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
720 | ||
73dd3a48 MHY |
721 | enum { |
722 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
723 | }; | |
724 | ||
e126ba97 | 725 | struct mlx5_cmd_work_ent { |
73dd3a48 | 726 | unsigned long state; |
e126ba97 EC |
727 | struct mlx5_cmd_msg *in; |
728 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
729 | void *uout; |
730 | int uout_size; | |
e126ba97 | 731 | mlx5_cmd_cbk_t callback; |
65ee6708 | 732 | struct delayed_work cb_timeout_work; |
e126ba97 | 733 | void *context; |
746b5583 | 734 | int idx; |
e126ba97 EC |
735 | struct completion done; |
736 | struct mlx5_cmd *cmd; | |
737 | struct work_struct work; | |
738 | struct mlx5_cmd_layout *lay; | |
739 | int ret; | |
740 | int page_queue; | |
741 | u8 status; | |
742 | u8 token; | |
14a70046 TG |
743 | u64 ts1; |
744 | u64 ts2; | |
746b5583 | 745 | u16 op; |
4525abea | 746 | bool polling; |
e126ba97 EC |
747 | }; |
748 | ||
749 | struct mlx5_pas { | |
750 | u64 pa; | |
751 | u8 log_sz; | |
752 | }; | |
753 | ||
707c4602 MD |
754 | enum phy_port_state { |
755 | MLX5_AAA_111 | |
756 | }; | |
757 | ||
758 | struct mlx5_hca_vport_context { | |
759 | u32 field_select; | |
760 | bool sm_virt_aware; | |
761 | bool has_smi; | |
762 | bool has_raw; | |
763 | enum port_state_policy policy; | |
764 | enum phy_port_state phys_state; | |
765 | enum ib_port_state vport_state; | |
766 | u8 port_physical_state; | |
767 | u64 sys_image_guid; | |
768 | u64 port_guid; | |
769 | u64 node_guid; | |
770 | u32 cap_mask1; | |
771 | u32 cap_mask1_perm; | |
4106a758 MG |
772 | u16 cap_mask2; |
773 | u16 cap_mask2_perm; | |
707c4602 MD |
774 | u16 lid; |
775 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
776 | u8 lmc; | |
777 | u8 subnet_timeout; | |
778 | u16 sm_lid; | |
779 | u8 sm_sl; | |
780 | u16 qkey_violation_counter; | |
781 | u16 pkey_violation_counter; | |
782 | bool grh_required; | |
783 | }; | |
784 | ||
388ca8be | 785 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 786 | { |
388ca8be | 787 | return buf->frags->buf + offset; |
e126ba97 EC |
788 | } |
789 | ||
e126ba97 EC |
790 | #define STRUCT_FIELD(header, field) \ |
791 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
792 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
793 | ||
e126ba97 EC |
794 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
795 | { | |
796 | return pci_get_drvdata(pdev); | |
797 | } | |
798 | ||
799 | extern struct dentry *mlx5_debugfs_root; | |
800 | ||
801 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
802 | { | |
803 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
804 | } | |
805 | ||
806 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
807 | { | |
808 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
809 | } | |
810 | ||
811 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
812 | { | |
813 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
814 | } | |
815 | ||
816 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
817 | { | |
818 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
819 | } | |
820 | ||
3bcdb17a SG |
821 | static inline u32 mlx5_base_mkey(const u32 key) |
822 | { | |
823 | return key & 0xffffff00u; | |
824 | } | |
825 | ||
4972e6fa TT |
826 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
827 | u8 log_stride, u8 log_sz, | |
a0903622 | 828 | u16 strides_offset, |
d7037ad7 | 829 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 830 | { |
4972e6fa | 831 | fbc->frags = frags; |
3a2f7033 TT |
832 | fbc->log_stride = log_stride; |
833 | fbc->log_sz = log_sz; | |
388ca8be YC |
834 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
835 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
836 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
837 | fbc->strides_offset = strides_offset; |
838 | } | |
839 | ||
4972e6fa TT |
840 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
841 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
842 | struct mlx5_frag_buf_ctrl *fbc) |
843 | { | |
4972e6fa | 844 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
845 | } |
846 | ||
388ca8be YC |
847 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
848 | u32 ix) | |
849 | { | |
d7037ad7 TT |
850 | unsigned int frag; |
851 | ||
852 | ix += fbc->strides_offset; | |
853 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 854 | |
4972e6fa | 855 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
856 | } |
857 | ||
37fdffb2 TT |
858 | static inline u32 |
859 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
860 | { | |
861 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
862 | ||
863 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
864 | } | |
865 | ||
e126ba97 EC |
866 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
867 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
868 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
869 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 870 | |
e355477e JG |
871 | struct mlx5_async_ctx { |
872 | struct mlx5_core_dev *dev; | |
873 | atomic_t num_inflight; | |
874 | struct wait_queue_head wait; | |
875 | }; | |
876 | ||
877 | struct mlx5_async_work; | |
878 | ||
879 | typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); | |
880 | ||
881 | struct mlx5_async_work { | |
882 | struct mlx5_async_ctx *ctx; | |
883 | mlx5_async_cbk_t user_callback; | |
884 | }; | |
885 | ||
886 | void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, | |
887 | struct mlx5_async_ctx *ctx); | |
888 | void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); | |
889 | int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, | |
890 | void *out, int out_size, mlx5_async_cbk_t callback, | |
891 | struct mlx5_async_work *work); | |
892 | ||
e126ba97 EC |
893 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
894 | int out_size); | |
4525abea MD |
895 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
896 | void *out, int out_size); | |
c4f287c4 SM |
897 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
898 | ||
899 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
900 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
901 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
52c368dc | 902 | void mlx5_health_flush(struct mlx5_core_dev *dev); |
ac6ea6e8 EC |
903 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
904 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 905 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 906 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 907 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 908 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
2a0165a0 | 909 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
311c7c71 | 910 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
388ca8be YC |
911 | struct mlx5_frag_buf *buf, int node); |
912 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, | |
913 | int size, struct mlx5_frag_buf *buf); | |
914 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
915 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
916 | struct mlx5_frag_buf *buf, int node); | |
917 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
918 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
919 | gfp_t flags, int npages); | |
920 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
921 | struct mlx5_cmd_mailbox *head); | |
a606b0f6 MB |
922 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
923 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
924 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
925 | struct mlx5_core_mkey *mkey, | |
e355477e JG |
926 | struct mlx5_async_ctx *async_ctx, u32 *in, |
927 | int inlen, u32 *out, int outlen, | |
928 | mlx5_async_cbk_t callback, | |
929 | struct mlx5_async_work *context); | |
a606b0f6 MB |
930 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
931 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 932 | u32 *in, int inlen); |
a606b0f6 MB |
933 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
934 | struct mlx5_core_mkey *mkey); | |
935 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 936 | u32 *out, int outlen); |
e126ba97 EC |
937 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
938 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
0cf53c12 | 939 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
e126ba97 | 940 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
0cf53c12 | 941 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
e126ba97 EC |
942 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
943 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
591905ba | 944 | s32 npages, bool ec_function); |
cd23b14b | 945 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
946 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
947 | void mlx5_register_debugfs(void); | |
948 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
949 | |
950 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 951 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
0b6e26ce DT |
952 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
953 | unsigned int *irqn); | |
e126ba97 EC |
954 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
955 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
956 | ||
957 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
958 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
959 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
960 | int size_in, void *data_out, int size_out, | |
961 | u16 reg_num, int arg, int write); | |
adb0c954 | 962 | |
e126ba97 | 963 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
964 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
965 | int node); | |
e126ba97 EC |
966 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
967 | ||
e126ba97 EC |
968 | const char *mlx5_command_str(int command); |
969 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
970 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
971 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
972 | int npsvs, u32 *sig_index); | |
973 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 974 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
975 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
976 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
977 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
978 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 979 | |
1466cc5b YP |
980 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
981 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
982 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
983 | struct mlx5_rate_limit *rl); | |
984 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 985 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
05d3ac97 BW |
986 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
987 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
988 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
989 | bool map_wc, bool fast_path); | |
990 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 991 | |
f2f3df55 SM |
992 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
993 | struct cpumask * | |
994 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
995 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
996 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
997 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 998 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 999 | |
e3297246 EC |
1000 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1001 | { | |
1002 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1003 | } | |
1004 | ||
e126ba97 EC |
1005 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1006 | { | |
1007 | return mkey >> 8; | |
1008 | } | |
1009 | ||
1010 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1011 | { | |
1012 | return mkey_idx << 8; | |
1013 | } | |
1014 | ||
746b5583 EC |
1015 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1016 | { | |
1017 | return mkey & 0xff; | |
1018 | } | |
1019 | ||
e126ba97 EC |
1020 | enum { |
1021 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1022 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1023 | }; |
1024 | ||
1025 | enum { | |
8b7ff7f3 | 1026 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1027 | MLX5_IMR_MTT_CACHE_ENTRY, |
1028 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1029 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1030 | }; |
1031 | ||
64613d94 SM |
1032 | enum { |
1033 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1034 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1035 | }; | |
1036 | ||
9603b61d JM |
1037 | struct mlx5_interface { |
1038 | void * (*add)(struct mlx5_core_dev *dev); | |
1039 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1040 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1041 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
64613d94 | 1042 | int protocol; |
9603b61d JM |
1043 | struct list_head list; |
1044 | }; | |
1045 | ||
1046 | int mlx5_register_interface(struct mlx5_interface *intf); | |
1047 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
20902be4 SM |
1048 | int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
1049 | int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
1050 | ||
211e6c80 | 1051 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1052 | |
3bc34f3b AH |
1053 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1054 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7c34ec19 AH |
1055 | bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); |
1056 | bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); | |
724b509c | 1057 | bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); |
7907f23a | 1058 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1059 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1060 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1061 | u64 *values, | |
1062 | int num_counters, | |
1063 | size_t *offsets); | |
01187175 EC |
1064 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1065 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1066 | |
f6a8a19b | 1067 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1068 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1069 | struct ib_device *ibdev, | |
1070 | const char *name, | |
1071 | void (*setup)(struct net_device *)); | |
693dfd5a | 1072 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1073 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1074 | struct ib_device *device, | |
1075 | struct rdma_netdev_alloc_params *params); | |
693dfd5a | 1076 | |
e126ba97 EC |
1077 | struct mlx5_profile { |
1078 | u64 mask; | |
f241e749 | 1079 | u8 log_max_qp; |
e126ba97 EC |
1080 | struct { |
1081 | int size; | |
1082 | int limit; | |
1083 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1084 | }; | |
1085 | ||
fc50db98 EC |
1086 | enum { |
1087 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1088 | }; | |
1089 | ||
1090 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1091 | { | |
1092 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1093 | } | |
1094 | ||
591905ba BW |
1095 | static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) |
1096 | { | |
1097 | return dev->caps.embedded_cpu; | |
1098 | } | |
1099 | ||
7f0d11c7 BW |
1100 | static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev) |
1101 | { | |
1102 | return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); | |
1103 | } | |
1104 | ||
81cd229c BW |
1105 | static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev) |
1106 | { | |
1107 | return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); | |
1108 | } | |
1109 | ||
feb39369 BW |
1110 | #define MLX5_HOST_PF_MAX_VFS (127u) |
1111 | static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev) | |
1112 | { | |
1113 | if (mlx5_core_is_ecpf_esw_manager(dev)) | |
1114 | return MLX5_HOST_PF_MAX_VFS; | |
1115 | else | |
1116 | return pci_sriov_get_totalvfs(dev->pdev); | |
1117 | } | |
1118 | ||
707c4602 MD |
1119 | static inline int mlx5_get_gid_table_len(u16 param) |
1120 | { | |
1121 | if (param > 4) { | |
1122 | pr_warn("gid table length is zero\n"); | |
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | return 8 * (1 << param); | |
1127 | } | |
1128 | ||
1466cc5b YP |
1129 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1130 | { | |
1131 | return !!(dev->priv.rl_table.max_size); | |
1132 | } | |
1133 | ||
32f69e4b DJ |
1134 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1135 | { | |
1136 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1137 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1138 | } | |
1139 | ||
1140 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1141 | { | |
1142 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1143 | } | |
1144 | ||
1145 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1146 | { | |
1147 | return mlx5_core_is_mp_slave(dev) || | |
1148 | mlx5_core_is_mp_master(dev); | |
1149 | } | |
1150 | ||
7fd8aefb DJ |
1151 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1152 | { | |
32f69e4b DJ |
1153 | if (!mlx5_core_mp_enabled(dev)) |
1154 | return 1; | |
1155 | ||
1156 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1157 | } |
1158 | ||
020446e0 EC |
1159 | enum { |
1160 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1161 | }; | |
1162 | ||
e126ba97 | 1163 | #endif /* MLX5_DRIVER_H */ |