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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
43a335e0 | 44 | #include <linux/workqueue.h> |
d9aaed83 | 45 | #include <linux/mempool.h> |
94c6825e | 46 | #include <linux/interrupt.h> |
6ecde51d | 47 | |
e126ba97 EC |
48 | #include <linux/mlx5/device.h> |
49 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 50 | #include <linux/mlx5/srq.h> |
e126ba97 EC |
51 | |
52 | enum { | |
53 | MLX5_BOARD_ID_LEN = 64, | |
54 | MLX5_MAX_NAME_LEN = 16, | |
55 | }; | |
56 | ||
57 | enum { | |
58 | /* one minute for the sake of bringup. Generally, commands must always | |
59 | * complete and we may need to increase this timeout value | |
60 | */ | |
6b6c07bd | 61 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
62 | MLX5_CMD_WQ_MAX_NAME = 32, |
63 | }; | |
64 | ||
65 | enum { | |
66 | CMD_OWNER_SW = 0x0, | |
67 | CMD_OWNER_HW = 0x1, | |
68 | CMD_STATUS_SUCCESS = 0, | |
69 | }; | |
70 | ||
71 | enum mlx5_sqp_t { | |
72 | MLX5_SQP_SMI = 0, | |
73 | MLX5_SQP_GSI = 1, | |
74 | MLX5_SQP_IEEE_1588 = 2, | |
75 | MLX5_SQP_SNIFFER = 3, | |
76 | MLX5_SQP_SYNC_UMR = 4, | |
77 | }; | |
78 | ||
79 | enum { | |
80 | MLX5_MAX_PORTS = 2, | |
81 | }; | |
82 | ||
83 | enum { | |
84 | MLX5_EQ_VEC_PAGES = 0, | |
85 | MLX5_EQ_VEC_CMD = 1, | |
86 | MLX5_EQ_VEC_ASYNC = 2, | |
d9aaed83 | 87 | MLX5_EQ_VEC_PFAULT = 3, |
e126ba97 EC |
88 | MLX5_EQ_VEC_COMP_BASE, |
89 | }; | |
90 | ||
91 | enum { | |
db058a18 | 92 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
93 | }; |
94 | ||
95 | enum { | |
96 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
97 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
98 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
99 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
100 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
101 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
102 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
103 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
104 | }; | |
105 | ||
e126ba97 | 106 | enum { |
4f3961ee SM |
107 | MLX5_REG_QETCR = 0x4005, |
108 | MLX5_REG_QTCT = 0x400a, | |
341c5ee2 HN |
109 | MLX5_REG_DCBX_PARAM = 0x4020, |
110 | MLX5_REG_DCBX_APP = 0x4021, | |
e126ba97 EC |
111 | MLX5_REG_PCAP = 0x5001, |
112 | MLX5_REG_PMTU = 0x5003, | |
113 | MLX5_REG_PTYS = 0x5004, | |
114 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 115 | MLX5_REG_PFCC = 0x5007, |
efea389d | 116 | MLX5_REG_PPCNT = 0x5008, |
e126ba97 EC |
117 | MLX5_REG_PMAOS = 0x5012, |
118 | MLX5_REG_PUDE = 0x5009, | |
119 | MLX5_REG_PMPE = 0x5010, | |
120 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 121 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 122 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 123 | MLX5_REG_PMLP = 0x5002, |
e126ba97 EC |
124 | MLX5_REG_NODE_DESC = 0x6001, |
125 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 126 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 127 | MLX5_REG_MLCR = 0x902b, |
f9a1ef72 EE |
128 | MLX5_REG_MTPPS = 0x9053, |
129 | MLX5_REG_MTPPSE = 0x9054, | |
e126ba97 EC |
130 | }; |
131 | ||
341c5ee2 HN |
132 | enum mlx5_dcbx_oper_mode { |
133 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
134 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
135 | }; | |
136 | ||
da7525d2 EBE |
137 | enum { |
138 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
139 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
140 | }; | |
141 | ||
e420f0c0 HE |
142 | enum mlx5_page_fault_resume_flags { |
143 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
144 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
145 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
146 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
147 | }; | |
148 | ||
e126ba97 EC |
149 | enum dbg_rsc_type { |
150 | MLX5_DBG_RSC_QP, | |
151 | MLX5_DBG_RSC_EQ, | |
152 | MLX5_DBG_RSC_CQ, | |
153 | }; | |
154 | ||
155 | struct mlx5_field_desc { | |
156 | struct dentry *dent; | |
157 | int i; | |
158 | }; | |
159 | ||
160 | struct mlx5_rsc_debug { | |
161 | struct mlx5_core_dev *dev; | |
162 | void *object; | |
163 | enum dbg_rsc_type type; | |
164 | struct dentry *root; | |
165 | struct mlx5_field_desc fields[0]; | |
166 | }; | |
167 | ||
168 | enum mlx5_dev_event { | |
169 | MLX5_DEV_EVENT_SYS_ERROR, | |
170 | MLX5_DEV_EVENT_PORT_UP, | |
171 | MLX5_DEV_EVENT_PORT_DOWN, | |
172 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
173 | MLX5_DEV_EVENT_LID_CHANGE, | |
174 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
175 | MLX5_DEV_EVENT_GUID_CHANGE, | |
176 | MLX5_DEV_EVENT_CLIENT_REREG, | |
f9a1ef72 | 177 | MLX5_DEV_EVENT_PPS, |
e126ba97 EC |
178 | }; |
179 | ||
4c916a79 | 180 | enum mlx5_port_status { |
6fa1bcab AS |
181 | MLX5_PORT_UP = 1, |
182 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
183 | }; |
184 | ||
d9aaed83 AK |
185 | enum mlx5_eq_type { |
186 | MLX5_EQ_TYPE_COMP, | |
187 | MLX5_EQ_TYPE_ASYNC, | |
188 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
189 | MLX5_EQ_TYPE_PF, | |
190 | #endif | |
191 | }; | |
192 | ||
2f5ff264 | 193 | struct mlx5_bfreg_info { |
b037c29a | 194 | u32 *sys_pages; |
2f5ff264 | 195 | int num_low_latency_bfregs; |
e126ba97 | 196 | unsigned int *count; |
e126ba97 EC |
197 | |
198 | /* | |
2f5ff264 | 199 | * protect bfreg allocation data structs |
e126ba97 EC |
200 | */ |
201 | struct mutex lock; | |
78c0f98c | 202 | u32 ver; |
b037c29a EC |
203 | bool lib_uar_4k; |
204 | u32 num_sys_pages; | |
e126ba97 EC |
205 | }; |
206 | ||
207 | struct mlx5_cmd_first { | |
208 | __be32 data[4]; | |
209 | }; | |
210 | ||
211 | struct mlx5_cmd_msg { | |
212 | struct list_head list; | |
0ac3ea70 | 213 | struct cmd_msg_cache *parent; |
e126ba97 EC |
214 | u32 len; |
215 | struct mlx5_cmd_first first; | |
216 | struct mlx5_cmd_mailbox *next; | |
217 | }; | |
218 | ||
219 | struct mlx5_cmd_debug { | |
220 | struct dentry *dbg_root; | |
221 | struct dentry *dbg_in; | |
222 | struct dentry *dbg_out; | |
223 | struct dentry *dbg_outlen; | |
224 | struct dentry *dbg_status; | |
225 | struct dentry *dbg_run; | |
226 | void *in_msg; | |
227 | void *out_msg; | |
228 | u8 status; | |
229 | u16 inlen; | |
230 | u16 outlen; | |
231 | }; | |
232 | ||
0ac3ea70 | 233 | struct cmd_msg_cache { |
e126ba97 EC |
234 | /* protect block chain allocations |
235 | */ | |
236 | spinlock_t lock; | |
237 | struct list_head head; | |
0ac3ea70 MHY |
238 | unsigned int max_inbox_size; |
239 | unsigned int num_ent; | |
e126ba97 EC |
240 | }; |
241 | ||
0ac3ea70 MHY |
242 | enum { |
243 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
244 | }; |
245 | ||
246 | struct mlx5_cmd_stats { | |
247 | u64 sum; | |
248 | u64 n; | |
249 | struct dentry *root; | |
250 | struct dentry *avg; | |
251 | struct dentry *count; | |
252 | /* protect command average calculations */ | |
253 | spinlock_t lock; | |
254 | }; | |
255 | ||
256 | struct mlx5_cmd { | |
64599cca EC |
257 | void *cmd_alloc_buf; |
258 | dma_addr_t alloc_dma; | |
259 | int alloc_size; | |
e126ba97 EC |
260 | void *cmd_buf; |
261 | dma_addr_t dma; | |
262 | u16 cmdif_rev; | |
263 | u8 log_sz; | |
264 | u8 log_stride; | |
265 | int max_reg_cmds; | |
266 | int events; | |
267 | u32 __iomem *vector; | |
268 | ||
269 | /* protect command queue allocations | |
270 | */ | |
271 | spinlock_t alloc_lock; | |
272 | ||
273 | /* protect token allocations | |
274 | */ | |
275 | spinlock_t token_lock; | |
276 | u8 token; | |
277 | unsigned long bitmask; | |
278 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
279 | struct workqueue_struct *wq; | |
280 | struct semaphore sem; | |
281 | struct semaphore pages_sem; | |
282 | int mode; | |
283 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
284 | struct pci_pool *pool; | |
285 | struct mlx5_cmd_debug dbg; | |
0ac3ea70 | 286 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
287 | int checksum_disabled; |
288 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
289 | }; | |
290 | ||
291 | struct mlx5_port_caps { | |
292 | int gid_table_len; | |
293 | int pkey_table_len; | |
938fe83c | 294 | u8 ext_port_cap; |
e126ba97 EC |
295 | }; |
296 | ||
297 | struct mlx5_cmd_mailbox { | |
298 | void *buf; | |
299 | dma_addr_t dma; | |
300 | struct mlx5_cmd_mailbox *next; | |
301 | }; | |
302 | ||
303 | struct mlx5_buf_list { | |
304 | void *buf; | |
305 | dma_addr_t map; | |
306 | }; | |
307 | ||
308 | struct mlx5_buf { | |
309 | struct mlx5_buf_list direct; | |
e126ba97 | 310 | int npages; |
e126ba97 | 311 | int size; |
f241e749 | 312 | u8 page_shift; |
e126ba97 EC |
313 | }; |
314 | ||
1c1b5228 TT |
315 | struct mlx5_frag_buf { |
316 | struct mlx5_buf_list *frags; | |
317 | int npages; | |
318 | int size; | |
319 | u8 page_shift; | |
320 | }; | |
321 | ||
94c6825e MB |
322 | struct mlx5_eq_tasklet { |
323 | struct list_head list; | |
324 | struct list_head process_list; | |
325 | struct tasklet_struct task; | |
326 | /* lock on completion tasklet list */ | |
327 | spinlock_t lock; | |
328 | }; | |
329 | ||
d9aaed83 AK |
330 | struct mlx5_eq_pagefault { |
331 | struct work_struct work; | |
332 | /* Pagefaults lock */ | |
333 | spinlock_t lock; | |
334 | struct workqueue_struct *wq; | |
335 | mempool_t *pool; | |
336 | }; | |
337 | ||
e126ba97 EC |
338 | struct mlx5_eq { |
339 | struct mlx5_core_dev *dev; | |
340 | __be32 __iomem *doorbell; | |
341 | u32 cons_index; | |
342 | struct mlx5_buf buf; | |
343 | int size; | |
0b6e26ce | 344 | unsigned int irqn; |
e126ba97 EC |
345 | u8 eqn; |
346 | int nent; | |
347 | u64 mask; | |
e126ba97 EC |
348 | struct list_head list; |
349 | int index; | |
350 | struct mlx5_rsc_debug *dbg; | |
d9aaed83 AK |
351 | enum mlx5_eq_type type; |
352 | union { | |
353 | struct mlx5_eq_tasklet tasklet_ctx; | |
354 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
355 | struct mlx5_eq_pagefault pf_ctx; | |
356 | #endif | |
357 | }; | |
e126ba97 EC |
358 | }; |
359 | ||
3121e3c4 SG |
360 | struct mlx5_core_psv { |
361 | u32 psv_idx; | |
362 | struct psv_layout { | |
363 | u32 pd; | |
364 | u16 syndrome; | |
365 | u16 reserved; | |
366 | u16 bg; | |
367 | u16 app_tag; | |
368 | u32 ref_tag; | |
369 | } psv; | |
370 | }; | |
371 | ||
372 | struct mlx5_core_sig_ctx { | |
373 | struct mlx5_core_psv psv_memory; | |
374 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
375 | struct ib_sig_err err_item; |
376 | bool sig_status_checked; | |
377 | bool sig_err_exists; | |
378 | u32 sigerr_count; | |
3121e3c4 | 379 | }; |
e126ba97 | 380 | |
aa8e08d2 AK |
381 | enum { |
382 | MLX5_MKEY_MR = 1, | |
383 | MLX5_MKEY_MW, | |
384 | }; | |
385 | ||
a606b0f6 | 386 | struct mlx5_core_mkey { |
e126ba97 EC |
387 | u64 iova; |
388 | u64 size; | |
389 | u32 key; | |
390 | u32 pd; | |
aa8e08d2 | 391 | u32 type; |
e126ba97 EC |
392 | }; |
393 | ||
d9aaed83 AK |
394 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
395 | ||
5903325a | 396 | enum mlx5_res_type { |
e2013b21 | 397 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
398 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
399 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
400 | MLX5_RES_SRQ = 3, | |
401 | MLX5_RES_XSRQ = 4, | |
5903325a EC |
402 | }; |
403 | ||
404 | struct mlx5_core_rsc_common { | |
405 | enum mlx5_res_type res; | |
406 | atomic_t refcount; | |
407 | struct completion free; | |
408 | }; | |
409 | ||
e126ba97 | 410 | struct mlx5_core_srq { |
01949d01 | 411 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
412 | u32 srqn; |
413 | int max; | |
414 | int max_gs; | |
415 | int max_avail_gather; | |
416 | int wqe_shift; | |
417 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
418 | ||
419 | atomic_t refcount; | |
420 | struct completion free; | |
421 | }; | |
422 | ||
423 | struct mlx5_eq_table { | |
424 | void __iomem *update_ci; | |
425 | void __iomem *update_arm_ci; | |
233d05d2 | 426 | struct list_head comp_eqs_list; |
e126ba97 EC |
427 | struct mlx5_eq pages_eq; |
428 | struct mlx5_eq async_eq; | |
429 | struct mlx5_eq cmd_eq; | |
d9aaed83 AK |
430 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
431 | struct mlx5_eq pfault_eq; | |
432 | #endif | |
e126ba97 EC |
433 | int num_comp_vectors; |
434 | /* protect EQs list | |
435 | */ | |
436 | spinlock_t lock; | |
437 | }; | |
438 | ||
a6d51b68 | 439 | struct mlx5_uars_page { |
e126ba97 | 440 | void __iomem *map; |
a6d51b68 EC |
441 | bool wc; |
442 | u32 index; | |
443 | struct list_head list; | |
444 | unsigned int bfregs; | |
445 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
446 | unsigned long *fp_bitmap; | |
447 | unsigned int reg_avail; | |
448 | unsigned int fp_avail; | |
449 | struct kref ref_count; | |
450 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
451 | }; |
452 | ||
a6d51b68 EC |
453 | struct mlx5_bfreg_head { |
454 | /* protect blue flame registers allocations */ | |
455 | struct mutex lock; | |
456 | struct list_head list; | |
457 | }; | |
458 | ||
459 | struct mlx5_bfreg_data { | |
460 | struct mlx5_bfreg_head reg_head; | |
461 | struct mlx5_bfreg_head wc_head; | |
462 | }; | |
463 | ||
464 | struct mlx5_sq_bfreg { | |
465 | void __iomem *map; | |
466 | struct mlx5_uars_page *up; | |
467 | bool wc; | |
468 | u32 index; | |
469 | unsigned int offset; | |
470 | }; | |
e126ba97 EC |
471 | |
472 | struct mlx5_core_health { | |
473 | struct health_buffer __iomem *health; | |
474 | __be32 __iomem *health_counter; | |
475 | struct timer_list timer; | |
e126ba97 EC |
476 | u32 prev; |
477 | int miss_counter; | |
fd76ee4d | 478 | bool sick; |
05ac2c0b MHY |
479 | /* wq spinlock to synchronize draining */ |
480 | spinlock_t wq_lock; | |
ac6ea6e8 | 481 | struct workqueue_struct *wq; |
05ac2c0b | 482 | unsigned long flags; |
ac6ea6e8 | 483 | struct work_struct work; |
04c0c1ab | 484 | struct delayed_work recover_work; |
e126ba97 EC |
485 | }; |
486 | ||
487 | struct mlx5_cq_table { | |
488 | /* protect radix tree | |
489 | */ | |
490 | spinlock_t lock; | |
491 | struct radix_tree_root tree; | |
492 | }; | |
493 | ||
494 | struct mlx5_qp_table { | |
495 | /* protect radix tree | |
496 | */ | |
497 | spinlock_t lock; | |
498 | struct radix_tree_root tree; | |
499 | }; | |
500 | ||
501 | struct mlx5_srq_table { | |
502 | /* protect radix tree | |
503 | */ | |
504 | spinlock_t lock; | |
505 | struct radix_tree_root tree; | |
506 | }; | |
507 | ||
a606b0f6 | 508 | struct mlx5_mkey_table { |
3bcdb17a SG |
509 | /* protect radix tree |
510 | */ | |
511 | rwlock_t lock; | |
512 | struct radix_tree_root tree; | |
513 | }; | |
514 | ||
fc50db98 EC |
515 | struct mlx5_vf_context { |
516 | int enabled; | |
517 | }; | |
518 | ||
519 | struct mlx5_core_sriov { | |
520 | struct mlx5_vf_context *vfs_ctx; | |
521 | int num_vfs; | |
522 | int enabled_vfs; | |
523 | }; | |
524 | ||
db058a18 SM |
525 | struct mlx5_irq_info { |
526 | cpumask_var_t mask; | |
527 | char name[MLX5_MAX_IRQ_NAME]; | |
528 | }; | |
529 | ||
43a335e0 | 530 | struct mlx5_fc_stats { |
29cc6679 | 531 | struct rb_root counters; |
43a335e0 AV |
532 | struct list_head addlist; |
533 | /* protect addlist add/splice operations */ | |
534 | spinlock_t addlist_lock; | |
535 | ||
536 | struct workqueue_struct *wq; | |
537 | struct delayed_work work; | |
538 | unsigned long next_query; | |
539 | }; | |
540 | ||
073bb189 | 541 | struct mlx5_eswitch; |
7907f23a | 542 | struct mlx5_lag; |
d9aaed83 | 543 | struct mlx5_pagefault; |
073bb189 | 544 | |
1466cc5b YP |
545 | struct mlx5_rl_entry { |
546 | u32 rate; | |
547 | u16 index; | |
548 | u16 refcount; | |
549 | }; | |
550 | ||
551 | struct mlx5_rl_table { | |
552 | /* protect rate limit table */ | |
553 | struct mutex rl_lock; | |
554 | u16 max_size; | |
555 | u32 max_rate; | |
556 | u32 min_rate; | |
557 | struct mlx5_rl_entry *rl_entry; | |
558 | }; | |
559 | ||
d4eb4cd7 HN |
560 | enum port_module_event_status_type { |
561 | MLX5_MODULE_STATUS_PLUGGED = 0x1, | |
562 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, | |
563 | MLX5_MODULE_STATUS_ERROR = 0x3, | |
564 | MLX5_MODULE_STATUS_NUM = 0x3, | |
565 | }; | |
566 | ||
567 | enum port_module_event_error_type { | |
568 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, | |
569 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, | |
570 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, | |
571 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, | |
572 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, | |
573 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, | |
574 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, | |
575 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, | |
576 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, | |
577 | MLX5_MODULE_EVENT_ERROR_NUM, | |
578 | }; | |
579 | ||
580 | struct mlx5_port_module_event_stats { | |
581 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; | |
582 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; | |
583 | }; | |
584 | ||
e126ba97 EC |
585 | struct mlx5_priv { |
586 | char name[MLX5_MAX_NAME_LEN]; | |
587 | struct mlx5_eq_table eq_table; | |
db058a18 SM |
588 | struct msix_entry *msix_arr; |
589 | struct mlx5_irq_info *irq_info; | |
e126ba97 EC |
590 | |
591 | /* pages stuff */ | |
592 | struct workqueue_struct *pg_wq; | |
593 | struct rb_root page_root; | |
594 | int fw_pages; | |
6aec21f6 | 595 | atomic_t reg_pages; |
bf0bf77f | 596 | struct list_head free_list; |
fc50db98 | 597 | int vfs_pages; |
e126ba97 EC |
598 | |
599 | struct mlx5_core_health health; | |
600 | ||
601 | struct mlx5_srq_table srq_table; | |
602 | ||
603 | /* start: qp staff */ | |
604 | struct mlx5_qp_table qp_table; | |
605 | struct dentry *qp_debugfs; | |
606 | struct dentry *eq_debugfs; | |
607 | struct dentry *cq_debugfs; | |
608 | struct dentry *cmdif_debugfs; | |
609 | /* end: qp staff */ | |
610 | ||
611 | /* start: cq staff */ | |
612 | struct mlx5_cq_table cq_table; | |
613 | /* end: cq staff */ | |
614 | ||
a606b0f6 MB |
615 | /* start: mkey staff */ |
616 | struct mlx5_mkey_table mkey_table; | |
617 | /* end: mkey staff */ | |
3bcdb17a | 618 | |
e126ba97 | 619 | /* start: alloc staff */ |
311c7c71 SM |
620 | /* protect buffer alocation according to numa node */ |
621 | struct mutex alloc_mutex; | |
622 | int numa_node; | |
623 | ||
e126ba97 EC |
624 | struct mutex pgdir_mutex; |
625 | struct list_head pgdir_list; | |
626 | /* end: alloc staff */ | |
627 | struct dentry *dbg_root; | |
628 | ||
629 | /* protect mkey key part */ | |
630 | spinlock_t mkey_lock; | |
631 | u8 mkey_key; | |
9603b61d JM |
632 | |
633 | struct list_head dev_list; | |
634 | struct list_head ctx_list; | |
635 | spinlock_t ctx_lock; | |
073bb189 | 636 | |
fba53f7b | 637 | struct mlx5_flow_steering *steering; |
073bb189 | 638 | struct mlx5_eswitch *eswitch; |
fc50db98 | 639 | struct mlx5_core_sriov sriov; |
7907f23a | 640 | struct mlx5_lag *lag; |
fc50db98 | 641 | unsigned long pci_dev_data; |
43a335e0 | 642 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 643 | struct mlx5_rl_table rl_table; |
d4eb4cd7 HN |
644 | |
645 | struct mlx5_port_module_event_stats pme_stats; | |
d9aaed83 AK |
646 | |
647 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
648 | void (*pfault)(struct mlx5_core_dev *dev, | |
649 | void *context, | |
650 | struct mlx5_pagefault *pfault); | |
651 | void *pfault_ctx; | |
652 | struct srcu_struct pfault_srcu; | |
653 | #endif | |
a6d51b68 | 654 | struct mlx5_bfreg_data bfregs; |
01187175 | 655 | struct mlx5_uars_page *uar; |
e126ba97 EC |
656 | }; |
657 | ||
89d44f0a MD |
658 | enum mlx5_device_state { |
659 | MLX5_DEVICE_STATE_UP, | |
660 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
661 | }; | |
662 | ||
663 | enum mlx5_interface_state { | |
5fc7197d MD |
664 | MLX5_INTERFACE_STATE_DOWN = BIT(0), |
665 | MLX5_INTERFACE_STATE_UP = BIT(1), | |
666 | MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), | |
89d44f0a MD |
667 | }; |
668 | ||
669 | enum mlx5_pci_status { | |
670 | MLX5_PCI_STATUS_DISABLED, | |
671 | MLX5_PCI_STATUS_ENABLED, | |
672 | }; | |
673 | ||
d9aaed83 AK |
674 | enum mlx5_pagefault_type_flags { |
675 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
676 | MLX5_PFAULT_WRITE = 1 << 1, | |
677 | MLX5_PFAULT_RDMA = 1 << 2, | |
678 | }; | |
679 | ||
680 | /* Contains the details of a pagefault. */ | |
681 | struct mlx5_pagefault { | |
682 | u32 bytes_committed; | |
683 | u32 token; | |
684 | u8 event_subtype; | |
685 | u8 type; | |
686 | union { | |
687 | /* Initiator or send message responder pagefault details. */ | |
688 | struct { | |
689 | /* Received packet size, only valid for responders. */ | |
690 | u32 packet_size; | |
691 | /* | |
692 | * Number of resource holding WQE, depends on type. | |
693 | */ | |
694 | u32 wq_num; | |
695 | /* | |
696 | * WQE index. Refers to either the send queue or | |
697 | * receive queue, according to event_subtype. | |
698 | */ | |
699 | u16 wqe_index; | |
700 | } wqe; | |
701 | /* RDMA responder pagefault details */ | |
702 | struct { | |
703 | u32 r_key; | |
704 | /* | |
705 | * Received packet size, minimal size page fault | |
706 | * resolution required for forward progress. | |
707 | */ | |
708 | u32 packet_size; | |
709 | u32 rdma_op_len; | |
710 | u64 rdma_va; | |
711 | } rdma; | |
712 | }; | |
713 | ||
714 | struct mlx5_eq *eq; | |
715 | struct work_struct work; | |
716 | }; | |
717 | ||
b50d292b HHZ |
718 | struct mlx5_td { |
719 | struct list_head tirs_list; | |
720 | u32 tdn; | |
721 | }; | |
722 | ||
723 | struct mlx5e_resources { | |
b50d292b HHZ |
724 | u32 pdn; |
725 | struct mlx5_td td; | |
726 | struct mlx5_core_mkey mkey; | |
727 | }; | |
728 | ||
e126ba97 EC |
729 | struct mlx5_core_dev { |
730 | struct pci_dev *pdev; | |
89d44f0a MD |
731 | /* sync pci state */ |
732 | struct mutex pci_status_mutex; | |
733 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
734 | u8 rev_id; |
735 | char board_id[MLX5_BOARD_ID_LEN]; | |
736 | struct mlx5_cmd cmd; | |
938fe83c SM |
737 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
738 | u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
739 | u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
e126ba97 EC |
740 | phys_addr_t iseg_base; |
741 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
742 | enum mlx5_device_state state; |
743 | /* sync interface state */ | |
744 | struct mutex intf_state_mutex; | |
5fc7197d | 745 | unsigned long intf_state; |
e126ba97 EC |
746 | void (*event) (struct mlx5_core_dev *dev, |
747 | enum mlx5_dev_event event, | |
4d2f9bbb | 748 | unsigned long param); |
e126ba97 EC |
749 | struct mlx5_priv priv; |
750 | struct mlx5_profile *profile; | |
751 | atomic_t num_qps; | |
f62b8bb8 | 752 | u32 issi; |
b50d292b | 753 | struct mlx5e_resources mlx5e_res; |
5a7b27eb MG |
754 | #ifdef CONFIG_RFS_ACCEL |
755 | struct cpu_rmap *rmap; | |
756 | #endif | |
e126ba97 EC |
757 | }; |
758 | ||
759 | struct mlx5_db { | |
760 | __be32 *db; | |
761 | union { | |
762 | struct mlx5_db_pgdir *pgdir; | |
763 | struct mlx5_ib_user_db_page *user_page; | |
764 | } u; | |
765 | dma_addr_t dma; | |
766 | int index; | |
767 | }; | |
768 | ||
e126ba97 EC |
769 | enum { |
770 | MLX5_COMP_EQ_SIZE = 1024, | |
771 | }; | |
772 | ||
adb0c954 SM |
773 | enum { |
774 | MLX5_PTYS_IB = 1 << 0, | |
775 | MLX5_PTYS_EN = 1 << 2, | |
776 | }; | |
777 | ||
e126ba97 EC |
778 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
779 | ||
780 | struct mlx5_cmd_work_ent { | |
781 | struct mlx5_cmd_msg *in; | |
782 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
783 | void *uout; |
784 | int uout_size; | |
e126ba97 | 785 | mlx5_cmd_cbk_t callback; |
65ee6708 | 786 | struct delayed_work cb_timeout_work; |
e126ba97 | 787 | void *context; |
746b5583 | 788 | int idx; |
e126ba97 EC |
789 | struct completion done; |
790 | struct mlx5_cmd *cmd; | |
791 | struct work_struct work; | |
792 | struct mlx5_cmd_layout *lay; | |
793 | int ret; | |
794 | int page_queue; | |
795 | u8 status; | |
796 | u8 token; | |
14a70046 TG |
797 | u64 ts1; |
798 | u64 ts2; | |
746b5583 | 799 | u16 op; |
e126ba97 EC |
800 | }; |
801 | ||
802 | struct mlx5_pas { | |
803 | u64 pa; | |
804 | u8 log_sz; | |
805 | }; | |
806 | ||
707c4602 | 807 | enum port_state_policy { |
eff901d3 EC |
808 | MLX5_POLICY_DOWN = 0, |
809 | MLX5_POLICY_UP = 1, | |
810 | MLX5_POLICY_FOLLOW = 2, | |
811 | MLX5_POLICY_INVALID = 0xffffffff | |
707c4602 MD |
812 | }; |
813 | ||
814 | enum phy_port_state { | |
815 | MLX5_AAA_111 | |
816 | }; | |
817 | ||
818 | struct mlx5_hca_vport_context { | |
819 | u32 field_select; | |
820 | bool sm_virt_aware; | |
821 | bool has_smi; | |
822 | bool has_raw; | |
823 | enum port_state_policy policy; | |
824 | enum phy_port_state phys_state; | |
825 | enum ib_port_state vport_state; | |
826 | u8 port_physical_state; | |
827 | u64 sys_image_guid; | |
828 | u64 port_guid; | |
829 | u64 node_guid; | |
830 | u32 cap_mask1; | |
831 | u32 cap_mask1_perm; | |
832 | u32 cap_mask2; | |
833 | u32 cap_mask2_perm; | |
834 | u16 lid; | |
835 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
836 | u8 lmc; | |
837 | u8 subnet_timeout; | |
838 | u16 sm_lid; | |
839 | u8 sm_sl; | |
840 | u16 qkey_violation_counter; | |
841 | u16 pkey_violation_counter; | |
842 | bool grh_required; | |
843 | }; | |
844 | ||
e126ba97 EC |
845 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
846 | { | |
e126ba97 | 847 | return buf->direct.buf + offset; |
e126ba97 EC |
848 | } |
849 | ||
850 | extern struct workqueue_struct *mlx5_core_wq; | |
851 | ||
852 | #define STRUCT_FIELD(header, field) \ | |
853 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
854 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
855 | ||
e126ba97 EC |
856 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
857 | { | |
858 | return pci_get_drvdata(pdev); | |
859 | } | |
860 | ||
861 | extern struct dentry *mlx5_debugfs_root; | |
862 | ||
863 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
864 | { | |
865 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
866 | } | |
867 | ||
868 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
869 | { | |
870 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
871 | } | |
872 | ||
873 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
874 | { | |
875 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
876 | } | |
877 | ||
878 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
879 | { | |
880 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
881 | } | |
882 | ||
883 | static inline void *mlx5_vzalloc(unsigned long size) | |
884 | { | |
885 | void *rtn; | |
886 | ||
887 | rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); | |
888 | if (!rtn) | |
889 | rtn = vzalloc(size); | |
890 | return rtn; | |
891 | } | |
892 | ||
3bcdb17a SG |
893 | static inline u32 mlx5_base_mkey(const u32 key) |
894 | { | |
895 | return key & 0xffffff00u; | |
896 | } | |
897 | ||
e126ba97 EC |
898 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
899 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
900 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
901 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 902 | |
e126ba97 EC |
903 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
904 | int out_size); | |
746b5583 EC |
905 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
906 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
907 | void *context); | |
c4f287c4 SM |
908 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
909 | ||
910 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
911 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
912 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
913 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
914 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
915 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
916 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
05ac2c0b | 917 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
311c7c71 SM |
918 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
919 | struct mlx5_buf *buf, int node); | |
64ffaa21 | 920 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 | 921 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
1c1b5228 TT |
922 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
923 | struct mlx5_frag_buf *buf, int node); | |
924 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
925 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
926 | gfp_t flags, int npages); | |
927 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
928 | struct mlx5_cmd_mailbox *head); | |
929 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 930 | struct mlx5_srq_attr *in); |
e126ba97 EC |
931 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
932 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 933 | struct mlx5_srq_attr *out); |
e126ba97 EC |
934 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
935 | u16 lwm, int is_srq); | |
a606b0f6 MB |
936 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
937 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
938 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
939 | struct mlx5_core_mkey *mkey, | |
940 | u32 *in, int inlen, | |
941 | u32 *out, int outlen, | |
942 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
943 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
944 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 945 | u32 *in, int inlen); |
a606b0f6 MB |
946 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
947 | struct mlx5_core_mkey *mkey); | |
948 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 949 | u32 *out, int outlen); |
a606b0f6 | 950 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, |
e126ba97 EC |
951 | u32 *mkey); |
952 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
953 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 954 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 955 | u16 opmod, u8 port); |
e126ba97 EC |
956 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
957 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
958 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
959 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
960 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 961 | s32 npages); |
cd23b14b | 962 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
963 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
964 | void mlx5_register_debugfs(void); | |
965 | void mlx5_unregister_debugfs(void); | |
966 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
967 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
968 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
1c1b5228 | 969 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
e126ba97 | 970 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); |
5903325a | 971 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e126ba97 EC |
972 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
973 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
020446e0 | 974 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); |
e126ba97 EC |
975 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
976 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
d9aaed83 | 977 | int nent, u64 mask, const char *name, |
01187175 | 978 | enum mlx5_eq_type type); |
e126ba97 EC |
979 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
980 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
981 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
0b6e26ce DT |
982 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
983 | unsigned int *irqn); | |
e126ba97 EC |
984 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
985 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
986 | ||
987 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
988 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
989 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
990 | int size_in, void *data_out, int size_out, | |
991 | u16 reg_num, int arg, int write); | |
adb0c954 | 992 | |
e126ba97 EC |
993 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
994 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
995 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
73b626c1 | 996 | u32 *out, int outlen); |
e126ba97 EC |
997 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); |
998 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
999 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
1000 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1001 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
311c7c71 SM |
1002 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
1003 | int node); | |
e126ba97 EC |
1004 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
1005 | ||
e126ba97 EC |
1006 | const char *mlx5_command_str(int command); |
1007 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
1008 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
1009 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
1010 | int npsvs, u32 *sig_index); | |
1011 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1012 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1013 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1014 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1015 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1016 | u8 port_num, void *out, size_t sz); | |
d9aaed83 AK |
1017 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1018 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, | |
1019 | u32 wq_num, u8 type, int error); | |
1020 | #endif | |
e126ba97 | 1021 | |
1466cc5b YP |
1022 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1023 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
1024 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); | |
1025 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); | |
1026 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); | |
a6d51b68 EC |
1027 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1028 | bool map_wc, bool fast_path); | |
1029 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1030 | |
e3297246 EC |
1031 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1032 | { | |
1033 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1034 | } | |
1035 | ||
e126ba97 EC |
1036 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1037 | { | |
1038 | return mkey >> 8; | |
1039 | } | |
1040 | ||
1041 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1042 | { | |
1043 | return mkey_idx << 8; | |
1044 | } | |
1045 | ||
746b5583 EC |
1046 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1047 | { | |
1048 | return mkey & 0xff; | |
1049 | } | |
1050 | ||
e126ba97 EC |
1051 | enum { |
1052 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1053 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1054 | }; |
1055 | ||
1056 | enum { | |
7d0cc6ed | 1057 | MAX_MR_CACHE_ENTRIES = 21, |
e126ba97 EC |
1058 | }; |
1059 | ||
64613d94 SM |
1060 | enum { |
1061 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1062 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1063 | }; | |
1064 | ||
9603b61d JM |
1065 | struct mlx5_interface { |
1066 | void * (*add)(struct mlx5_core_dev *dev); | |
1067 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1068 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1069 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 1070 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1071 | enum mlx5_dev_event event, unsigned long param); |
d9aaed83 AK |
1072 | void (*pfault)(struct mlx5_core_dev *dev, |
1073 | void *context, | |
1074 | struct mlx5_pagefault *pfault); | |
64613d94 SM |
1075 | void * (*get_dev)(void *context); |
1076 | int protocol; | |
9603b61d JM |
1077 | struct list_head list; |
1078 | }; | |
1079 | ||
64613d94 | 1080 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
1081 | int mlx5_register_interface(struct mlx5_interface *intf); |
1082 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 1083 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1084 | |
3bc34f3b AH |
1085 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1086 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 1087 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1088 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
01187175 EC |
1089 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1090 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1091 | |
e126ba97 EC |
1092 | struct mlx5_profile { |
1093 | u64 mask; | |
f241e749 | 1094 | u8 log_max_qp; |
e126ba97 EC |
1095 | struct { |
1096 | int size; | |
1097 | int limit; | |
1098 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1099 | }; | |
1100 | ||
fc50db98 EC |
1101 | enum { |
1102 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1103 | }; | |
1104 | ||
1105 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1106 | { | |
1107 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1108 | } | |
1109 | ||
707c4602 MD |
1110 | static inline int mlx5_get_gid_table_len(u16 param) |
1111 | { | |
1112 | if (param > 4) { | |
1113 | pr_warn("gid table length is zero\n"); | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | return 8 * (1 << param); | |
1118 | } | |
1119 | ||
1466cc5b YP |
1120 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1121 | { | |
1122 | return !!(dev->priv.rl_table.max_size); | |
1123 | } | |
1124 | ||
020446e0 EC |
1125 | enum { |
1126 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1127 | }; | |
1128 | ||
e126ba97 | 1129 | #endif /* MLX5_DRIVER_H */ |