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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
43a335e0 | 44 | #include <linux/workqueue.h> |
d9aaed83 | 45 | #include <linux/mempool.h> |
94c6825e | 46 | #include <linux/interrupt.h> |
52ec462e | 47 | #include <linux/idr.h> |
6ecde51d | 48 | |
e126ba97 EC |
49 | #include <linux/mlx5/device.h> |
50 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 51 | #include <linux/mlx5/srq.h> |
7c39afb3 FD |
52 | #include <linux/timecounter.h> |
53 | #include <linux/ptp_clock_kernel.h> | |
e126ba97 EC |
54 | |
55 | enum { | |
56 | MLX5_BOARD_ID_LEN = 64, | |
57 | MLX5_MAX_NAME_LEN = 16, | |
58 | }; | |
59 | ||
60 | enum { | |
61 | /* one minute for the sake of bringup. Generally, commands must always | |
62 | * complete and we may need to increase this timeout value | |
63 | */ | |
6b6c07bd | 64 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
65 | MLX5_CMD_WQ_MAX_NAME = 32, |
66 | }; | |
67 | ||
68 | enum { | |
69 | CMD_OWNER_SW = 0x0, | |
70 | CMD_OWNER_HW = 0x1, | |
71 | CMD_STATUS_SUCCESS = 0, | |
72 | }; | |
73 | ||
74 | enum mlx5_sqp_t { | |
75 | MLX5_SQP_SMI = 0, | |
76 | MLX5_SQP_GSI = 1, | |
77 | MLX5_SQP_IEEE_1588 = 2, | |
78 | MLX5_SQP_SNIFFER = 3, | |
79 | MLX5_SQP_SYNC_UMR = 4, | |
80 | }; | |
81 | ||
82 | enum { | |
83 | MLX5_MAX_PORTS = 2, | |
84 | }; | |
85 | ||
86 | enum { | |
87 | MLX5_EQ_VEC_PAGES = 0, | |
88 | MLX5_EQ_VEC_CMD = 1, | |
89 | MLX5_EQ_VEC_ASYNC = 2, | |
d9aaed83 | 90 | MLX5_EQ_VEC_PFAULT = 3, |
e126ba97 EC |
91 | MLX5_EQ_VEC_COMP_BASE, |
92 | }; | |
93 | ||
94 | enum { | |
db058a18 | 95 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
96 | }; |
97 | ||
98 | enum { | |
99 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
100 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
101 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
102 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
103 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
104 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
105 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
106 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
107 | }; | |
108 | ||
e126ba97 | 109 | enum { |
415a64aa | 110 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
111 | MLX5_REG_QETCR = 0x4005, |
112 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 113 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 114 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
115 | MLX5_REG_DCBX_PARAM = 0x4020, |
116 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
117 | MLX5_REG_FPGA_CAP = 0x4022, |
118 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 119 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
e126ba97 EC |
120 | MLX5_REG_PCAP = 0x5001, |
121 | MLX5_REG_PMTU = 0x5003, | |
122 | MLX5_REG_PTYS = 0x5004, | |
123 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 124 | MLX5_REG_PFCC = 0x5007, |
efea389d | 125 | MLX5_REG_PPCNT = 0x5008, |
e126ba97 EC |
126 | MLX5_REG_PMAOS = 0x5012, |
127 | MLX5_REG_PUDE = 0x5009, | |
128 | MLX5_REG_PMPE = 0x5010, | |
129 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 130 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 131 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 132 | MLX5_REG_PMLP = 0x5002, |
cfdcbcea | 133 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
134 | MLX5_REG_NODE_DESC = 0x6001, |
135 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 136 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 137 | MLX5_REG_MLCR = 0x902b, |
8ed1a630 | 138 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
139 | MLX5_REG_MTPPS = 0x9053, |
140 | MLX5_REG_MTPPSE = 0x9054, | |
47176289 OG |
141 | MLX5_REG_MCQI = 0x9061, |
142 | MLX5_REG_MCC = 0x9062, | |
143 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 144 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
145 | }; |
146 | ||
415a64aa HN |
147 | enum mlx5_qpts_trust_state { |
148 | MLX5_QPTS_TRUST_PCP = 1, | |
149 | MLX5_QPTS_TRUST_DSCP = 2, | |
150 | }; | |
151 | ||
341c5ee2 HN |
152 | enum mlx5_dcbx_oper_mode { |
153 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
154 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
155 | }; | |
156 | ||
da7525d2 EBE |
157 | enum { |
158 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
159 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
160 | }; | |
161 | ||
e420f0c0 HE |
162 | enum mlx5_page_fault_resume_flags { |
163 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
164 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
165 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
166 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
167 | }; | |
168 | ||
e126ba97 EC |
169 | enum dbg_rsc_type { |
170 | MLX5_DBG_RSC_QP, | |
171 | MLX5_DBG_RSC_EQ, | |
172 | MLX5_DBG_RSC_CQ, | |
173 | }; | |
174 | ||
7ecf6d8f BW |
175 | enum port_state_policy { |
176 | MLX5_POLICY_DOWN = 0, | |
177 | MLX5_POLICY_UP = 1, | |
178 | MLX5_POLICY_FOLLOW = 2, | |
179 | MLX5_POLICY_INVALID = 0xffffffff | |
180 | }; | |
181 | ||
e126ba97 EC |
182 | struct mlx5_field_desc { |
183 | struct dentry *dent; | |
184 | int i; | |
185 | }; | |
186 | ||
187 | struct mlx5_rsc_debug { | |
188 | struct mlx5_core_dev *dev; | |
189 | void *object; | |
190 | enum dbg_rsc_type type; | |
191 | struct dentry *root; | |
192 | struct mlx5_field_desc fields[0]; | |
193 | }; | |
194 | ||
195 | enum mlx5_dev_event { | |
196 | MLX5_DEV_EVENT_SYS_ERROR, | |
197 | MLX5_DEV_EVENT_PORT_UP, | |
198 | MLX5_DEV_EVENT_PORT_DOWN, | |
199 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
200 | MLX5_DEV_EVENT_LID_CHANGE, | |
201 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
202 | MLX5_DEV_EVENT_GUID_CHANGE, | |
203 | MLX5_DEV_EVENT_CLIENT_REREG, | |
f9a1ef72 | 204 | MLX5_DEV_EVENT_PPS, |
246ac981 | 205 | MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, |
e126ba97 EC |
206 | }; |
207 | ||
4c916a79 | 208 | enum mlx5_port_status { |
6fa1bcab AS |
209 | MLX5_PORT_UP = 1, |
210 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
211 | }; |
212 | ||
d9aaed83 AK |
213 | enum mlx5_eq_type { |
214 | MLX5_EQ_TYPE_COMP, | |
215 | MLX5_EQ_TYPE_ASYNC, | |
216 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
217 | MLX5_EQ_TYPE_PF, | |
218 | #endif | |
219 | }; | |
220 | ||
2f5ff264 | 221 | struct mlx5_bfreg_info { |
b037c29a | 222 | u32 *sys_pages; |
2f5ff264 | 223 | int num_low_latency_bfregs; |
e126ba97 | 224 | unsigned int *count; |
e126ba97 EC |
225 | |
226 | /* | |
2f5ff264 | 227 | * protect bfreg allocation data structs |
e126ba97 EC |
228 | */ |
229 | struct mutex lock; | |
78c0f98c | 230 | u32 ver; |
b037c29a EC |
231 | bool lib_uar_4k; |
232 | u32 num_sys_pages; | |
e126ba97 EC |
233 | }; |
234 | ||
235 | struct mlx5_cmd_first { | |
236 | __be32 data[4]; | |
237 | }; | |
238 | ||
239 | struct mlx5_cmd_msg { | |
240 | struct list_head list; | |
0ac3ea70 | 241 | struct cmd_msg_cache *parent; |
e126ba97 EC |
242 | u32 len; |
243 | struct mlx5_cmd_first first; | |
244 | struct mlx5_cmd_mailbox *next; | |
245 | }; | |
246 | ||
247 | struct mlx5_cmd_debug { | |
248 | struct dentry *dbg_root; | |
249 | struct dentry *dbg_in; | |
250 | struct dentry *dbg_out; | |
251 | struct dentry *dbg_outlen; | |
252 | struct dentry *dbg_status; | |
253 | struct dentry *dbg_run; | |
254 | void *in_msg; | |
255 | void *out_msg; | |
256 | u8 status; | |
257 | u16 inlen; | |
258 | u16 outlen; | |
259 | }; | |
260 | ||
0ac3ea70 | 261 | struct cmd_msg_cache { |
e126ba97 EC |
262 | /* protect block chain allocations |
263 | */ | |
264 | spinlock_t lock; | |
265 | struct list_head head; | |
0ac3ea70 MHY |
266 | unsigned int max_inbox_size; |
267 | unsigned int num_ent; | |
e126ba97 EC |
268 | }; |
269 | ||
0ac3ea70 MHY |
270 | enum { |
271 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
272 | }; |
273 | ||
274 | struct mlx5_cmd_stats { | |
275 | u64 sum; | |
276 | u64 n; | |
277 | struct dentry *root; | |
278 | struct dentry *avg; | |
279 | struct dentry *count; | |
280 | /* protect command average calculations */ | |
281 | spinlock_t lock; | |
282 | }; | |
283 | ||
284 | struct mlx5_cmd { | |
64599cca EC |
285 | void *cmd_alloc_buf; |
286 | dma_addr_t alloc_dma; | |
287 | int alloc_size; | |
e126ba97 EC |
288 | void *cmd_buf; |
289 | dma_addr_t dma; | |
290 | u16 cmdif_rev; | |
291 | u8 log_sz; | |
292 | u8 log_stride; | |
293 | int max_reg_cmds; | |
294 | int events; | |
295 | u32 __iomem *vector; | |
296 | ||
297 | /* protect command queue allocations | |
298 | */ | |
299 | spinlock_t alloc_lock; | |
300 | ||
301 | /* protect token allocations | |
302 | */ | |
303 | spinlock_t token_lock; | |
304 | u8 token; | |
305 | unsigned long bitmask; | |
306 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
307 | struct workqueue_struct *wq; | |
308 | struct semaphore sem; | |
309 | struct semaphore pages_sem; | |
310 | int mode; | |
311 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 312 | struct dma_pool *pool; |
e126ba97 | 313 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 314 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
315 | int checksum_disabled; |
316 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
317 | }; | |
318 | ||
319 | struct mlx5_port_caps { | |
320 | int gid_table_len; | |
321 | int pkey_table_len; | |
938fe83c | 322 | u8 ext_port_cap; |
c43f1112 | 323 | bool has_smi; |
e126ba97 EC |
324 | }; |
325 | ||
326 | struct mlx5_cmd_mailbox { | |
327 | void *buf; | |
328 | dma_addr_t dma; | |
329 | struct mlx5_cmd_mailbox *next; | |
330 | }; | |
331 | ||
332 | struct mlx5_buf_list { | |
333 | void *buf; | |
334 | dma_addr_t map; | |
335 | }; | |
336 | ||
337 | struct mlx5_buf { | |
338 | struct mlx5_buf_list direct; | |
e126ba97 | 339 | int npages; |
e126ba97 | 340 | int size; |
f241e749 | 341 | u8 page_shift; |
e126ba97 EC |
342 | }; |
343 | ||
1c1b5228 TT |
344 | struct mlx5_frag_buf { |
345 | struct mlx5_buf_list *frags; | |
346 | int npages; | |
347 | int size; | |
348 | u8 page_shift; | |
349 | }; | |
350 | ||
94c6825e MB |
351 | struct mlx5_eq_tasklet { |
352 | struct list_head list; | |
353 | struct list_head process_list; | |
354 | struct tasklet_struct task; | |
355 | /* lock on completion tasklet list */ | |
356 | spinlock_t lock; | |
357 | }; | |
358 | ||
d9aaed83 AK |
359 | struct mlx5_eq_pagefault { |
360 | struct work_struct work; | |
361 | /* Pagefaults lock */ | |
362 | spinlock_t lock; | |
363 | struct workqueue_struct *wq; | |
364 | mempool_t *pool; | |
365 | }; | |
366 | ||
e126ba97 EC |
367 | struct mlx5_eq { |
368 | struct mlx5_core_dev *dev; | |
369 | __be32 __iomem *doorbell; | |
370 | u32 cons_index; | |
371 | struct mlx5_buf buf; | |
372 | int size; | |
0b6e26ce | 373 | unsigned int irqn; |
e126ba97 EC |
374 | u8 eqn; |
375 | int nent; | |
376 | u64 mask; | |
e126ba97 EC |
377 | struct list_head list; |
378 | int index; | |
379 | struct mlx5_rsc_debug *dbg; | |
d9aaed83 AK |
380 | enum mlx5_eq_type type; |
381 | union { | |
382 | struct mlx5_eq_tasklet tasklet_ctx; | |
383 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
384 | struct mlx5_eq_pagefault pf_ctx; | |
385 | #endif | |
386 | }; | |
e126ba97 EC |
387 | }; |
388 | ||
3121e3c4 SG |
389 | struct mlx5_core_psv { |
390 | u32 psv_idx; | |
391 | struct psv_layout { | |
392 | u32 pd; | |
393 | u16 syndrome; | |
394 | u16 reserved; | |
395 | u16 bg; | |
396 | u16 app_tag; | |
397 | u32 ref_tag; | |
398 | } psv; | |
399 | }; | |
400 | ||
401 | struct mlx5_core_sig_ctx { | |
402 | struct mlx5_core_psv psv_memory; | |
403 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
404 | struct ib_sig_err err_item; |
405 | bool sig_status_checked; | |
406 | bool sig_err_exists; | |
407 | u32 sigerr_count; | |
3121e3c4 | 408 | }; |
e126ba97 | 409 | |
aa8e08d2 AK |
410 | enum { |
411 | MLX5_MKEY_MR = 1, | |
412 | MLX5_MKEY_MW, | |
413 | }; | |
414 | ||
a606b0f6 | 415 | struct mlx5_core_mkey { |
e126ba97 EC |
416 | u64 iova; |
417 | u64 size; | |
418 | u32 key; | |
419 | u32 pd; | |
aa8e08d2 | 420 | u32 type; |
e126ba97 EC |
421 | }; |
422 | ||
d9aaed83 AK |
423 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
424 | ||
5903325a | 425 | enum mlx5_res_type { |
e2013b21 | 426 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
427 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
428 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
429 | MLX5_RES_SRQ = 3, | |
430 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 431 | MLX5_RES_XRQ = 5, |
5903325a EC |
432 | }; |
433 | ||
434 | struct mlx5_core_rsc_common { | |
435 | enum mlx5_res_type res; | |
436 | atomic_t refcount; | |
437 | struct completion free; | |
438 | }; | |
439 | ||
e126ba97 | 440 | struct mlx5_core_srq { |
01949d01 | 441 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
442 | u32 srqn; |
443 | int max; | |
444 | int max_gs; | |
445 | int max_avail_gather; | |
446 | int wqe_shift; | |
447 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
448 | ||
449 | atomic_t refcount; | |
450 | struct completion free; | |
451 | }; | |
452 | ||
453 | struct mlx5_eq_table { | |
454 | void __iomem *update_ci; | |
455 | void __iomem *update_arm_ci; | |
233d05d2 | 456 | struct list_head comp_eqs_list; |
e126ba97 EC |
457 | struct mlx5_eq pages_eq; |
458 | struct mlx5_eq async_eq; | |
459 | struct mlx5_eq cmd_eq; | |
d9aaed83 AK |
460 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
461 | struct mlx5_eq pfault_eq; | |
462 | #endif | |
e126ba97 EC |
463 | int num_comp_vectors; |
464 | /* protect EQs list | |
465 | */ | |
466 | spinlock_t lock; | |
467 | }; | |
468 | ||
a6d51b68 | 469 | struct mlx5_uars_page { |
e126ba97 | 470 | void __iomem *map; |
a6d51b68 EC |
471 | bool wc; |
472 | u32 index; | |
473 | struct list_head list; | |
474 | unsigned int bfregs; | |
475 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
476 | unsigned long *fp_bitmap; | |
477 | unsigned int reg_avail; | |
478 | unsigned int fp_avail; | |
479 | struct kref ref_count; | |
480 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
481 | }; |
482 | ||
a6d51b68 EC |
483 | struct mlx5_bfreg_head { |
484 | /* protect blue flame registers allocations */ | |
485 | struct mutex lock; | |
486 | struct list_head list; | |
487 | }; | |
488 | ||
489 | struct mlx5_bfreg_data { | |
490 | struct mlx5_bfreg_head reg_head; | |
491 | struct mlx5_bfreg_head wc_head; | |
492 | }; | |
493 | ||
494 | struct mlx5_sq_bfreg { | |
495 | void __iomem *map; | |
496 | struct mlx5_uars_page *up; | |
497 | bool wc; | |
498 | u32 index; | |
499 | unsigned int offset; | |
500 | }; | |
e126ba97 EC |
501 | |
502 | struct mlx5_core_health { | |
503 | struct health_buffer __iomem *health; | |
504 | __be32 __iomem *health_counter; | |
505 | struct timer_list timer; | |
e126ba97 EC |
506 | u32 prev; |
507 | int miss_counter; | |
fd76ee4d | 508 | bool sick; |
05ac2c0b MHY |
509 | /* wq spinlock to synchronize draining */ |
510 | spinlock_t wq_lock; | |
ac6ea6e8 | 511 | struct workqueue_struct *wq; |
05ac2c0b | 512 | unsigned long flags; |
ac6ea6e8 | 513 | struct work_struct work; |
04c0c1ab | 514 | struct delayed_work recover_work; |
e126ba97 EC |
515 | }; |
516 | ||
517 | struct mlx5_cq_table { | |
518 | /* protect radix tree | |
519 | */ | |
520 | spinlock_t lock; | |
521 | struct radix_tree_root tree; | |
522 | }; | |
523 | ||
524 | struct mlx5_qp_table { | |
525 | /* protect radix tree | |
526 | */ | |
527 | spinlock_t lock; | |
528 | struct radix_tree_root tree; | |
529 | }; | |
530 | ||
531 | struct mlx5_srq_table { | |
532 | /* protect radix tree | |
533 | */ | |
534 | spinlock_t lock; | |
535 | struct radix_tree_root tree; | |
536 | }; | |
537 | ||
a606b0f6 | 538 | struct mlx5_mkey_table { |
3bcdb17a SG |
539 | /* protect radix tree |
540 | */ | |
541 | rwlock_t lock; | |
542 | struct radix_tree_root tree; | |
543 | }; | |
544 | ||
fc50db98 EC |
545 | struct mlx5_vf_context { |
546 | int enabled; | |
7ecf6d8f BW |
547 | u64 port_guid; |
548 | u64 node_guid; | |
549 | enum port_state_policy policy; | |
fc50db98 EC |
550 | }; |
551 | ||
552 | struct mlx5_core_sriov { | |
553 | struct mlx5_vf_context *vfs_ctx; | |
554 | int num_vfs; | |
555 | int enabled_vfs; | |
556 | }; | |
557 | ||
db058a18 | 558 | struct mlx5_irq_info { |
231243c8 | 559 | cpumask_var_t mask; |
db058a18 SM |
560 | char name[MLX5_MAX_IRQ_NAME]; |
561 | }; | |
562 | ||
43a335e0 | 563 | struct mlx5_fc_stats { |
29cc6679 | 564 | struct rb_root counters; |
43a335e0 AV |
565 | struct list_head addlist; |
566 | /* protect addlist add/splice operations */ | |
567 | spinlock_t addlist_lock; | |
568 | ||
569 | struct workqueue_struct *wq; | |
570 | struct delayed_work work; | |
571 | unsigned long next_query; | |
f6dfb4c3 | 572 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
573 | }; |
574 | ||
eeb66cdb | 575 | struct mlx5_mpfs; |
073bb189 | 576 | struct mlx5_eswitch; |
7907f23a | 577 | struct mlx5_lag; |
d9aaed83 | 578 | struct mlx5_pagefault; |
073bb189 | 579 | |
1466cc5b YP |
580 | struct mlx5_rl_entry { |
581 | u32 rate; | |
582 | u16 index; | |
583 | u16 refcount; | |
584 | }; | |
585 | ||
586 | struct mlx5_rl_table { | |
587 | /* protect rate limit table */ | |
588 | struct mutex rl_lock; | |
589 | u16 max_size; | |
590 | u32 max_rate; | |
591 | u32 min_rate; | |
592 | struct mlx5_rl_entry *rl_entry; | |
593 | }; | |
594 | ||
d4eb4cd7 HN |
595 | enum port_module_event_status_type { |
596 | MLX5_MODULE_STATUS_PLUGGED = 0x1, | |
597 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, | |
598 | MLX5_MODULE_STATUS_ERROR = 0x3, | |
599 | MLX5_MODULE_STATUS_NUM = 0x3, | |
600 | }; | |
601 | ||
602 | enum port_module_event_error_type { | |
603 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, | |
604 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, | |
605 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, | |
606 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, | |
607 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, | |
608 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, | |
609 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, | |
610 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, | |
611 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, | |
612 | MLX5_MODULE_EVENT_ERROR_NUM, | |
613 | }; | |
614 | ||
615 | struct mlx5_port_module_event_stats { | |
616 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; | |
617 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; | |
618 | }; | |
619 | ||
e126ba97 EC |
620 | struct mlx5_priv { |
621 | char name[MLX5_MAX_NAME_LEN]; | |
622 | struct mlx5_eq_table eq_table; | |
db058a18 | 623 | struct mlx5_irq_info *irq_info; |
e126ba97 EC |
624 | |
625 | /* pages stuff */ | |
626 | struct workqueue_struct *pg_wq; | |
627 | struct rb_root page_root; | |
628 | int fw_pages; | |
6aec21f6 | 629 | atomic_t reg_pages; |
bf0bf77f | 630 | struct list_head free_list; |
fc50db98 | 631 | int vfs_pages; |
e126ba97 EC |
632 | |
633 | struct mlx5_core_health health; | |
634 | ||
635 | struct mlx5_srq_table srq_table; | |
636 | ||
637 | /* start: qp staff */ | |
638 | struct mlx5_qp_table qp_table; | |
639 | struct dentry *qp_debugfs; | |
640 | struct dentry *eq_debugfs; | |
641 | struct dentry *cq_debugfs; | |
642 | struct dentry *cmdif_debugfs; | |
643 | /* end: qp staff */ | |
644 | ||
645 | /* start: cq staff */ | |
646 | struct mlx5_cq_table cq_table; | |
647 | /* end: cq staff */ | |
648 | ||
a606b0f6 MB |
649 | /* start: mkey staff */ |
650 | struct mlx5_mkey_table mkey_table; | |
651 | /* end: mkey staff */ | |
3bcdb17a | 652 | |
e126ba97 | 653 | /* start: alloc staff */ |
311c7c71 SM |
654 | /* protect buffer alocation according to numa node */ |
655 | struct mutex alloc_mutex; | |
656 | int numa_node; | |
657 | ||
e126ba97 EC |
658 | struct mutex pgdir_mutex; |
659 | struct list_head pgdir_list; | |
660 | /* end: alloc staff */ | |
661 | struct dentry *dbg_root; | |
662 | ||
663 | /* protect mkey key part */ | |
664 | spinlock_t mkey_lock; | |
665 | u8 mkey_key; | |
9603b61d JM |
666 | |
667 | struct list_head dev_list; | |
668 | struct list_head ctx_list; | |
669 | spinlock_t ctx_lock; | |
073bb189 | 670 | |
97834eba ES |
671 | struct list_head waiting_events_list; |
672 | bool is_accum_events; | |
673 | ||
fba53f7b | 674 | struct mlx5_flow_steering *steering; |
eeb66cdb | 675 | struct mlx5_mpfs *mpfs; |
073bb189 | 676 | struct mlx5_eswitch *eswitch; |
fc50db98 | 677 | struct mlx5_core_sriov sriov; |
7907f23a | 678 | struct mlx5_lag *lag; |
fc50db98 | 679 | unsigned long pci_dev_data; |
43a335e0 | 680 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 681 | struct mlx5_rl_table rl_table; |
d4eb4cd7 HN |
682 | |
683 | struct mlx5_port_module_event_stats pme_stats; | |
d9aaed83 AK |
684 | |
685 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
686 | void (*pfault)(struct mlx5_core_dev *dev, | |
687 | void *context, | |
688 | struct mlx5_pagefault *pfault); | |
689 | void *pfault_ctx; | |
690 | struct srcu_struct pfault_srcu; | |
691 | #endif | |
a6d51b68 | 692 | struct mlx5_bfreg_data bfregs; |
01187175 | 693 | struct mlx5_uars_page *uar; |
e126ba97 EC |
694 | }; |
695 | ||
89d44f0a MD |
696 | enum mlx5_device_state { |
697 | MLX5_DEVICE_STATE_UP, | |
698 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
699 | }; | |
700 | ||
701 | enum mlx5_interface_state { | |
b3cb5388 | 702 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
703 | }; |
704 | ||
705 | enum mlx5_pci_status { | |
706 | MLX5_PCI_STATUS_DISABLED, | |
707 | MLX5_PCI_STATUS_ENABLED, | |
708 | }; | |
709 | ||
d9aaed83 AK |
710 | enum mlx5_pagefault_type_flags { |
711 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
712 | MLX5_PFAULT_WRITE = 1 << 1, | |
713 | MLX5_PFAULT_RDMA = 1 << 2, | |
714 | }; | |
715 | ||
716 | /* Contains the details of a pagefault. */ | |
717 | struct mlx5_pagefault { | |
718 | u32 bytes_committed; | |
719 | u32 token; | |
720 | u8 event_subtype; | |
721 | u8 type; | |
722 | union { | |
723 | /* Initiator or send message responder pagefault details. */ | |
724 | struct { | |
725 | /* Received packet size, only valid for responders. */ | |
726 | u32 packet_size; | |
727 | /* | |
728 | * Number of resource holding WQE, depends on type. | |
729 | */ | |
730 | u32 wq_num; | |
731 | /* | |
732 | * WQE index. Refers to either the send queue or | |
733 | * receive queue, according to event_subtype. | |
734 | */ | |
735 | u16 wqe_index; | |
736 | } wqe; | |
737 | /* RDMA responder pagefault details */ | |
738 | struct { | |
739 | u32 r_key; | |
740 | /* | |
741 | * Received packet size, minimal size page fault | |
742 | * resolution required for forward progress. | |
743 | */ | |
744 | u32 packet_size; | |
745 | u32 rdma_op_len; | |
746 | u64 rdma_va; | |
747 | } rdma; | |
748 | }; | |
749 | ||
750 | struct mlx5_eq *eq; | |
751 | struct work_struct work; | |
752 | }; | |
753 | ||
b50d292b HHZ |
754 | struct mlx5_td { |
755 | struct list_head tirs_list; | |
756 | u32 tdn; | |
757 | }; | |
758 | ||
759 | struct mlx5e_resources { | |
b50d292b HHZ |
760 | u32 pdn; |
761 | struct mlx5_td td; | |
762 | struct mlx5_core_mkey mkey; | |
aff26157 | 763 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
764 | }; |
765 | ||
52ec462e IT |
766 | #define MLX5_MAX_RESERVED_GIDS 8 |
767 | ||
768 | struct mlx5_rsvd_gids { | |
769 | unsigned int start; | |
770 | unsigned int count; | |
771 | struct ida ida; | |
772 | }; | |
773 | ||
7c39afb3 FD |
774 | #define MAX_PIN_NUM 8 |
775 | struct mlx5_pps { | |
776 | u8 pin_caps[MAX_PIN_NUM]; | |
777 | struct work_struct out_work; | |
778 | u64 start[MAX_PIN_NUM]; | |
779 | u8 enabled; | |
780 | }; | |
781 | ||
782 | struct mlx5_clock { | |
783 | rwlock_t lock; | |
784 | struct cyclecounter cycles; | |
785 | struct timecounter tc; | |
786 | struct hwtstamp_config hwtstamp_config; | |
787 | u32 nominal_c_mult; | |
788 | unsigned long overflow_period; | |
789 | struct delayed_work overflow_work; | |
790 | struct ptp_clock *ptp; | |
791 | struct ptp_clock_info ptp_info; | |
792 | struct mlx5_pps pps_info; | |
793 | }; | |
794 | ||
e126ba97 EC |
795 | struct mlx5_core_dev { |
796 | struct pci_dev *pdev; | |
89d44f0a MD |
797 | /* sync pci state */ |
798 | struct mutex pci_status_mutex; | |
799 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
800 | u8 rev_id; |
801 | char board_id[MLX5_BOARD_ID_LEN]; | |
802 | struct mlx5_cmd cmd; | |
938fe83c | 803 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 804 | struct { |
701052c5 GP |
805 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
806 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
807 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
808 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 809 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 810 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
71862561 | 811 | } caps; |
e126ba97 EC |
812 | phys_addr_t iseg_base; |
813 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
814 | enum mlx5_device_state state; |
815 | /* sync interface state */ | |
816 | struct mutex intf_state_mutex; | |
5fc7197d | 817 | unsigned long intf_state; |
e126ba97 EC |
818 | void (*event) (struct mlx5_core_dev *dev, |
819 | enum mlx5_dev_event event, | |
4d2f9bbb | 820 | unsigned long param); |
e126ba97 EC |
821 | struct mlx5_priv priv; |
822 | struct mlx5_profile *profile; | |
823 | atomic_t num_qps; | |
f62b8bb8 | 824 | u32 issi; |
b50d292b | 825 | struct mlx5e_resources mlx5e_res; |
52ec462e IT |
826 | struct { |
827 | struct mlx5_rsvd_gids reserved_gids; | |
a6f7d2af | 828 | atomic_t roce_en; |
52ec462e | 829 | } roce; |
e29341fb IT |
830 | #ifdef CONFIG_MLX5_FPGA |
831 | struct mlx5_fpga_device *fpga; | |
832 | #endif | |
5a7b27eb MG |
833 | #ifdef CONFIG_RFS_ACCEL |
834 | struct cpu_rmap *rmap; | |
835 | #endif | |
7c39afb3 | 836 | struct mlx5_clock clock; |
e126ba97 EC |
837 | }; |
838 | ||
839 | struct mlx5_db { | |
840 | __be32 *db; | |
841 | union { | |
842 | struct mlx5_db_pgdir *pgdir; | |
843 | struct mlx5_ib_user_db_page *user_page; | |
844 | } u; | |
845 | dma_addr_t dma; | |
846 | int index; | |
847 | }; | |
848 | ||
e126ba97 EC |
849 | enum { |
850 | MLX5_COMP_EQ_SIZE = 1024, | |
851 | }; | |
852 | ||
adb0c954 SM |
853 | enum { |
854 | MLX5_PTYS_IB = 1 << 0, | |
855 | MLX5_PTYS_EN = 1 << 2, | |
856 | }; | |
857 | ||
e126ba97 EC |
858 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
859 | ||
73dd3a48 MHY |
860 | enum { |
861 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
862 | }; | |
863 | ||
e126ba97 | 864 | struct mlx5_cmd_work_ent { |
73dd3a48 | 865 | unsigned long state; |
e126ba97 EC |
866 | struct mlx5_cmd_msg *in; |
867 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
868 | void *uout; |
869 | int uout_size; | |
e126ba97 | 870 | mlx5_cmd_cbk_t callback; |
65ee6708 | 871 | struct delayed_work cb_timeout_work; |
e126ba97 | 872 | void *context; |
746b5583 | 873 | int idx; |
e126ba97 EC |
874 | struct completion done; |
875 | struct mlx5_cmd *cmd; | |
876 | struct work_struct work; | |
877 | struct mlx5_cmd_layout *lay; | |
878 | int ret; | |
879 | int page_queue; | |
880 | u8 status; | |
881 | u8 token; | |
14a70046 TG |
882 | u64 ts1; |
883 | u64 ts2; | |
746b5583 | 884 | u16 op; |
4525abea | 885 | bool polling; |
e126ba97 EC |
886 | }; |
887 | ||
888 | struct mlx5_pas { | |
889 | u64 pa; | |
890 | u8 log_sz; | |
891 | }; | |
892 | ||
707c4602 MD |
893 | enum phy_port_state { |
894 | MLX5_AAA_111 | |
895 | }; | |
896 | ||
897 | struct mlx5_hca_vport_context { | |
898 | u32 field_select; | |
899 | bool sm_virt_aware; | |
900 | bool has_smi; | |
901 | bool has_raw; | |
902 | enum port_state_policy policy; | |
903 | enum phy_port_state phys_state; | |
904 | enum ib_port_state vport_state; | |
905 | u8 port_physical_state; | |
906 | u64 sys_image_guid; | |
907 | u64 port_guid; | |
908 | u64 node_guid; | |
909 | u32 cap_mask1; | |
910 | u32 cap_mask1_perm; | |
911 | u32 cap_mask2; | |
912 | u32 cap_mask2_perm; | |
913 | u16 lid; | |
914 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
915 | u8 lmc; | |
916 | u8 subnet_timeout; | |
917 | u16 sm_lid; | |
918 | u8 sm_sl; | |
919 | u16 qkey_violation_counter; | |
920 | u16 pkey_violation_counter; | |
921 | bool grh_required; | |
922 | }; | |
923 | ||
e126ba97 EC |
924 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
925 | { | |
e126ba97 | 926 | return buf->direct.buf + offset; |
e126ba97 EC |
927 | } |
928 | ||
e126ba97 EC |
929 | #define STRUCT_FIELD(header, field) \ |
930 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
931 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
932 | ||
e126ba97 EC |
933 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
934 | { | |
935 | return pci_get_drvdata(pdev); | |
936 | } | |
937 | ||
938 | extern struct dentry *mlx5_debugfs_root; | |
939 | ||
940 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
941 | { | |
942 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
943 | } | |
944 | ||
945 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
946 | { | |
947 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
948 | } | |
949 | ||
950 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
951 | { | |
952 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
953 | } | |
954 | ||
955 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
956 | { | |
957 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
958 | } | |
959 | ||
3bcdb17a SG |
960 | static inline u32 mlx5_base_mkey(const u32 key) |
961 | { | |
962 | return key & 0xffffff00u; | |
963 | } | |
964 | ||
e126ba97 EC |
965 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
966 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
967 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
968 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 969 | |
e126ba97 EC |
970 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
971 | int out_size); | |
746b5583 EC |
972 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
973 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
974 | void *context); | |
4525abea MD |
975 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
976 | void *out, int out_size); | |
c4f287c4 SM |
977 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
978 | ||
979 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
980 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
981 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
982 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
983 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
984 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
985 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
05ac2c0b | 986 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 987 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
2a0165a0 | 988 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
311c7c71 SM |
989 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
990 | struct mlx5_buf *buf, int node); | |
64ffaa21 | 991 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 | 992 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
1c1b5228 TT |
993 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
994 | struct mlx5_frag_buf *buf, int node); | |
995 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
996 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
997 | gfp_t flags, int npages); | |
998 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
999 | struct mlx5_cmd_mailbox *head); | |
1000 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 1001 | struct mlx5_srq_attr *in); |
e126ba97 EC |
1002 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
1003 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 1004 | struct mlx5_srq_attr *out); |
e126ba97 EC |
1005 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
1006 | u16 lwm, int is_srq); | |
a606b0f6 MB |
1007 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
1008 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
1009 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
1010 | struct mlx5_core_mkey *mkey, | |
1011 | u32 *in, int inlen, | |
1012 | u32 *out, int outlen, | |
1013 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
1014 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
1015 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1016 | u32 *in, int inlen); |
a606b0f6 MB |
1017 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
1018 | struct mlx5_core_mkey *mkey); | |
1019 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1020 | u32 *out, int outlen); |
a606b0f6 | 1021 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, |
e126ba97 EC |
1022 | u32 *mkey); |
1023 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
1024 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 1025 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 1026 | u16 opmod, u8 port); |
e126ba97 EC |
1027 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
1028 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
1029 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
1030 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
1031 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 1032 | s32 npages); |
cd23b14b | 1033 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
1034 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
1035 | void mlx5_register_debugfs(void); | |
1036 | void mlx5_unregister_debugfs(void); | |
1037 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
1038 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
1039 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
1c1b5228 | 1040 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
e126ba97 | 1041 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); |
5903325a | 1042 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e126ba97 EC |
1043 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
1044 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
73dd3a48 | 1045 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); |
e126ba97 EC |
1046 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
1047 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
d9aaed83 | 1048 | int nent, u64 mask, const char *name, |
01187175 | 1049 | enum mlx5_eq_type type); |
e126ba97 EC |
1050 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
1051 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
d6b2785c | 1052 | void mlx5_stop_eqs(struct mlx5_core_dev *dev); |
0b6e26ce DT |
1053 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
1054 | unsigned int *irqn); | |
e126ba97 EC |
1055 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
1056 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
1057 | ||
1058 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
1059 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1060 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
1061 | int size_in, void *data_out, int size_out, | |
1062 | u16 reg_num, int arg, int write); | |
adb0c954 | 1063 | |
e126ba97 EC |
1064 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
1065 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
1066 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
73b626c1 | 1067 | u32 *out, int outlen); |
e126ba97 EC |
1068 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); |
1069 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1070 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
1071 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1072 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
311c7c71 SM |
1073 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
1074 | int node); | |
e126ba97 EC |
1075 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
1076 | ||
e126ba97 EC |
1077 | const char *mlx5_command_str(int command); |
1078 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
1079 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
1080 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
1081 | int npsvs, u32 *sig_index); | |
1082 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1083 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1084 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1085 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1086 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1087 | u8 port_num, void *out, size_t sz); | |
d9aaed83 AK |
1088 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1089 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, | |
1090 | u32 wq_num, u8 type, int error); | |
1091 | #endif | |
e126ba97 | 1092 | |
1466cc5b YP |
1093 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1094 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
1095 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); | |
1096 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); | |
1097 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); | |
a6d51b68 EC |
1098 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1099 | bool map_wc, bool fast_path); | |
1100 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1101 | |
52ec462e IT |
1102 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1103 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1104 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
1105 | const u8 *mac, bool vlan, u16 vlan_id); | |
1106 | ||
e3297246 EC |
1107 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1108 | { | |
1109 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1110 | } | |
1111 | ||
e126ba97 EC |
1112 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1113 | { | |
1114 | return mkey >> 8; | |
1115 | } | |
1116 | ||
1117 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1118 | { | |
1119 | return mkey_idx << 8; | |
1120 | } | |
1121 | ||
746b5583 EC |
1122 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1123 | { | |
1124 | return mkey & 0xff; | |
1125 | } | |
1126 | ||
e126ba97 EC |
1127 | enum { |
1128 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1129 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1130 | }; |
1131 | ||
1132 | enum { | |
8b7ff7f3 | 1133 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1134 | MLX5_IMR_MTT_CACHE_ENTRY, |
1135 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1136 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1137 | }; |
1138 | ||
64613d94 SM |
1139 | enum { |
1140 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1141 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1142 | }; | |
1143 | ||
9603b61d JM |
1144 | struct mlx5_interface { |
1145 | void * (*add)(struct mlx5_core_dev *dev); | |
1146 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1147 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1148 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 1149 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1150 | enum mlx5_dev_event event, unsigned long param); |
d9aaed83 AK |
1151 | void (*pfault)(struct mlx5_core_dev *dev, |
1152 | void *context, | |
1153 | struct mlx5_pagefault *pfault); | |
64613d94 SM |
1154 | void * (*get_dev)(void *context); |
1155 | int protocol; | |
9603b61d JM |
1156 | struct list_head list; |
1157 | }; | |
1158 | ||
64613d94 | 1159 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
1160 | int mlx5_register_interface(struct mlx5_interface *intf); |
1161 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 1162 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1163 | |
3bc34f3b AH |
1164 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1165 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 1166 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1167 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1168 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1169 | u64 *values, | |
1170 | int num_counters, | |
1171 | size_t *offsets); | |
01187175 EC |
1172 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1173 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1174 | |
693dfd5a ES |
1175 | #ifndef CONFIG_MLX5_CORE_IPOIB |
1176 | static inline | |
1177 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1178 | struct ib_device *ibdev, | |
1179 | const char *name, | |
1180 | void (*setup)(struct net_device *)) | |
1181 | { | |
1182 | return ERR_PTR(-EOPNOTSUPP); | |
1183 | } | |
1184 | ||
1185 | static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {} | |
1186 | #else | |
1187 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1188 | struct ib_device *ibdev, | |
1189 | const char *name, | |
1190 | void (*setup)(struct net_device *)); | |
1191 | void mlx5_rdma_netdev_free(struct net_device *netdev); | |
1192 | #endif /* CONFIG_MLX5_CORE_IPOIB */ | |
1193 | ||
e126ba97 EC |
1194 | struct mlx5_profile { |
1195 | u64 mask; | |
f241e749 | 1196 | u8 log_max_qp; |
e126ba97 EC |
1197 | struct { |
1198 | int size; | |
1199 | int limit; | |
1200 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1201 | }; | |
1202 | ||
fc50db98 EC |
1203 | enum { |
1204 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1205 | }; | |
1206 | ||
1207 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1208 | { | |
1209 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1210 | } | |
1211 | ||
707c4602 MD |
1212 | static inline int mlx5_get_gid_table_len(u16 param) |
1213 | { | |
1214 | if (param > 4) { | |
1215 | pr_warn("gid table length is zero\n"); | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | return 8 * (1 << param); | |
1220 | } | |
1221 | ||
1466cc5b YP |
1222 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1223 | { | |
1224 | return !!(dev->priv.rl_table.max_size); | |
1225 | } | |
1226 | ||
020446e0 EC |
1227 | enum { |
1228 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1229 | }; | |
1230 | ||
a435393a SG |
1231 | static inline const struct cpumask * |
1232 | mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector) | |
1233 | { | |
1234 | return pci_irq_get_affinity(dev->pdev, MLX5_EQ_VEC_COMP_BASE + vector); | |
1235 | } | |
1236 | ||
e126ba97 | 1237 | #endif /* MLX5_DRIVER_H */ |