Commit | Line | Data |
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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
43a335e0 | 44 | #include <linux/workqueue.h> |
94c6825e | 45 | #include <linux/interrupt.h> |
6ecde51d | 46 | |
e126ba97 EC |
47 | #include <linux/mlx5/device.h> |
48 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 49 | #include <linux/mlx5/srq.h> |
e126ba97 EC |
50 | |
51 | enum { | |
52 | MLX5_BOARD_ID_LEN = 64, | |
53 | MLX5_MAX_NAME_LEN = 16, | |
54 | }; | |
55 | ||
56 | enum { | |
57 | /* one minute for the sake of bringup. Generally, commands must always | |
58 | * complete and we may need to increase this timeout value | |
59 | */ | |
6b6c07bd | 60 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
61 | MLX5_CMD_WQ_MAX_NAME = 32, |
62 | }; | |
63 | ||
64 | enum { | |
65 | CMD_OWNER_SW = 0x0, | |
66 | CMD_OWNER_HW = 0x1, | |
67 | CMD_STATUS_SUCCESS = 0, | |
68 | }; | |
69 | ||
70 | enum mlx5_sqp_t { | |
71 | MLX5_SQP_SMI = 0, | |
72 | MLX5_SQP_GSI = 1, | |
73 | MLX5_SQP_IEEE_1588 = 2, | |
74 | MLX5_SQP_SNIFFER = 3, | |
75 | MLX5_SQP_SYNC_UMR = 4, | |
76 | }; | |
77 | ||
78 | enum { | |
79 | MLX5_MAX_PORTS = 2, | |
80 | }; | |
81 | ||
82 | enum { | |
83 | MLX5_EQ_VEC_PAGES = 0, | |
84 | MLX5_EQ_VEC_CMD = 1, | |
85 | MLX5_EQ_VEC_ASYNC = 2, | |
86 | MLX5_EQ_VEC_COMP_BASE, | |
87 | }; | |
88 | ||
89 | enum { | |
db058a18 | 90 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
91 | }; |
92 | ||
93 | enum { | |
94 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
95 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
96 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
97 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
98 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
99 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
100 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
101 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
102 | }; | |
103 | ||
e126ba97 | 104 | enum { |
4f3961ee SM |
105 | MLX5_REG_QETCR = 0x4005, |
106 | MLX5_REG_QTCT = 0x400a, | |
e126ba97 EC |
107 | MLX5_REG_PCAP = 0x5001, |
108 | MLX5_REG_PMTU = 0x5003, | |
109 | MLX5_REG_PTYS = 0x5004, | |
110 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 111 | MLX5_REG_PFCC = 0x5007, |
efea389d | 112 | MLX5_REG_PPCNT = 0x5008, |
e126ba97 EC |
113 | MLX5_REG_PMAOS = 0x5012, |
114 | MLX5_REG_PUDE = 0x5009, | |
115 | MLX5_REG_PMPE = 0x5010, | |
116 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 117 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 118 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 119 | MLX5_REG_PMLP = 0x5002, |
e126ba97 EC |
120 | MLX5_REG_NODE_DESC = 0x6001, |
121 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 122 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 123 | MLX5_REG_MLCR = 0x902b, |
e126ba97 EC |
124 | }; |
125 | ||
da7525d2 EBE |
126 | enum { |
127 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
128 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
129 | }; | |
130 | ||
e420f0c0 HE |
131 | enum mlx5_page_fault_resume_flags { |
132 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
133 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
134 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
135 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
136 | }; | |
137 | ||
e126ba97 EC |
138 | enum dbg_rsc_type { |
139 | MLX5_DBG_RSC_QP, | |
140 | MLX5_DBG_RSC_EQ, | |
141 | MLX5_DBG_RSC_CQ, | |
142 | }; | |
143 | ||
144 | struct mlx5_field_desc { | |
145 | struct dentry *dent; | |
146 | int i; | |
147 | }; | |
148 | ||
149 | struct mlx5_rsc_debug { | |
150 | struct mlx5_core_dev *dev; | |
151 | void *object; | |
152 | enum dbg_rsc_type type; | |
153 | struct dentry *root; | |
154 | struct mlx5_field_desc fields[0]; | |
155 | }; | |
156 | ||
157 | enum mlx5_dev_event { | |
158 | MLX5_DEV_EVENT_SYS_ERROR, | |
159 | MLX5_DEV_EVENT_PORT_UP, | |
160 | MLX5_DEV_EVENT_PORT_DOWN, | |
161 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
162 | MLX5_DEV_EVENT_LID_CHANGE, | |
163 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
164 | MLX5_DEV_EVENT_GUID_CHANGE, | |
165 | MLX5_DEV_EVENT_CLIENT_REREG, | |
166 | }; | |
167 | ||
4c916a79 | 168 | enum mlx5_port_status { |
6fa1bcab AS |
169 | MLX5_PORT_UP = 1, |
170 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
171 | }; |
172 | ||
e126ba97 EC |
173 | struct mlx5_uuar_info { |
174 | struct mlx5_uar *uars; | |
175 | int num_uars; | |
176 | int num_low_latency_uuars; | |
177 | unsigned long *bitmap; | |
178 | unsigned int *count; | |
179 | struct mlx5_bf *bfs; | |
180 | ||
181 | /* | |
182 | * protect uuar allocation data structs | |
183 | */ | |
184 | struct mutex lock; | |
78c0f98c | 185 | u32 ver; |
e126ba97 EC |
186 | }; |
187 | ||
188 | struct mlx5_bf { | |
189 | void __iomem *reg; | |
190 | void __iomem *regreg; | |
191 | int buf_size; | |
192 | struct mlx5_uar *uar; | |
193 | unsigned long offset; | |
194 | int need_lock; | |
195 | /* protect blue flame buffer selection when needed | |
196 | */ | |
197 | spinlock_t lock; | |
198 | ||
199 | /* serialize 64 bit writes when done as two 32 bit accesses | |
200 | */ | |
201 | spinlock_t lock32; | |
202 | int uuarn; | |
203 | }; | |
204 | ||
205 | struct mlx5_cmd_first { | |
206 | __be32 data[4]; | |
207 | }; | |
208 | ||
209 | struct mlx5_cmd_msg { | |
210 | struct list_head list; | |
211 | struct cache_ent *cache; | |
212 | u32 len; | |
213 | struct mlx5_cmd_first first; | |
214 | struct mlx5_cmd_mailbox *next; | |
215 | }; | |
216 | ||
217 | struct mlx5_cmd_debug { | |
218 | struct dentry *dbg_root; | |
219 | struct dentry *dbg_in; | |
220 | struct dentry *dbg_out; | |
221 | struct dentry *dbg_outlen; | |
222 | struct dentry *dbg_status; | |
223 | struct dentry *dbg_run; | |
224 | void *in_msg; | |
225 | void *out_msg; | |
226 | u8 status; | |
227 | u16 inlen; | |
228 | u16 outlen; | |
229 | }; | |
230 | ||
231 | struct cache_ent { | |
232 | /* protect block chain allocations | |
233 | */ | |
234 | spinlock_t lock; | |
235 | struct list_head head; | |
236 | }; | |
237 | ||
238 | struct cmd_msg_cache { | |
239 | struct cache_ent large; | |
240 | struct cache_ent med; | |
241 | ||
242 | }; | |
243 | ||
244 | struct mlx5_cmd_stats { | |
245 | u64 sum; | |
246 | u64 n; | |
247 | struct dentry *root; | |
248 | struct dentry *avg; | |
249 | struct dentry *count; | |
250 | /* protect command average calculations */ | |
251 | spinlock_t lock; | |
252 | }; | |
253 | ||
254 | struct mlx5_cmd { | |
64599cca EC |
255 | void *cmd_alloc_buf; |
256 | dma_addr_t alloc_dma; | |
257 | int alloc_size; | |
e126ba97 EC |
258 | void *cmd_buf; |
259 | dma_addr_t dma; | |
260 | u16 cmdif_rev; | |
261 | u8 log_sz; | |
262 | u8 log_stride; | |
263 | int max_reg_cmds; | |
264 | int events; | |
265 | u32 __iomem *vector; | |
266 | ||
267 | /* protect command queue allocations | |
268 | */ | |
269 | spinlock_t alloc_lock; | |
270 | ||
271 | /* protect token allocations | |
272 | */ | |
273 | spinlock_t token_lock; | |
274 | u8 token; | |
275 | unsigned long bitmask; | |
276 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
277 | struct workqueue_struct *wq; | |
278 | struct semaphore sem; | |
279 | struct semaphore pages_sem; | |
280 | int mode; | |
281 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
282 | struct pci_pool *pool; | |
283 | struct mlx5_cmd_debug dbg; | |
284 | struct cmd_msg_cache cache; | |
285 | int checksum_disabled; | |
286 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
287 | }; | |
288 | ||
289 | struct mlx5_port_caps { | |
290 | int gid_table_len; | |
291 | int pkey_table_len; | |
938fe83c | 292 | u8 ext_port_cap; |
e126ba97 EC |
293 | }; |
294 | ||
295 | struct mlx5_cmd_mailbox { | |
296 | void *buf; | |
297 | dma_addr_t dma; | |
298 | struct mlx5_cmd_mailbox *next; | |
299 | }; | |
300 | ||
301 | struct mlx5_buf_list { | |
302 | void *buf; | |
303 | dma_addr_t map; | |
304 | }; | |
305 | ||
306 | struct mlx5_buf { | |
307 | struct mlx5_buf_list direct; | |
e126ba97 | 308 | int npages; |
e126ba97 | 309 | int size; |
f241e749 | 310 | u8 page_shift; |
e126ba97 EC |
311 | }; |
312 | ||
94c6825e MB |
313 | struct mlx5_eq_tasklet { |
314 | struct list_head list; | |
315 | struct list_head process_list; | |
316 | struct tasklet_struct task; | |
317 | /* lock on completion tasklet list */ | |
318 | spinlock_t lock; | |
319 | }; | |
320 | ||
e126ba97 EC |
321 | struct mlx5_eq { |
322 | struct mlx5_core_dev *dev; | |
323 | __be32 __iomem *doorbell; | |
324 | u32 cons_index; | |
325 | struct mlx5_buf buf; | |
326 | int size; | |
0b6e26ce | 327 | unsigned int irqn; |
e126ba97 EC |
328 | u8 eqn; |
329 | int nent; | |
330 | u64 mask; | |
e126ba97 EC |
331 | struct list_head list; |
332 | int index; | |
333 | struct mlx5_rsc_debug *dbg; | |
94c6825e | 334 | struct mlx5_eq_tasklet tasklet_ctx; |
e126ba97 EC |
335 | }; |
336 | ||
3121e3c4 SG |
337 | struct mlx5_core_psv { |
338 | u32 psv_idx; | |
339 | struct psv_layout { | |
340 | u32 pd; | |
341 | u16 syndrome; | |
342 | u16 reserved; | |
343 | u16 bg; | |
344 | u16 app_tag; | |
345 | u32 ref_tag; | |
346 | } psv; | |
347 | }; | |
348 | ||
349 | struct mlx5_core_sig_ctx { | |
350 | struct mlx5_core_psv psv_memory; | |
351 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
352 | struct ib_sig_err err_item; |
353 | bool sig_status_checked; | |
354 | bool sig_err_exists; | |
355 | u32 sigerr_count; | |
3121e3c4 | 356 | }; |
e126ba97 | 357 | |
a606b0f6 | 358 | struct mlx5_core_mkey { |
e126ba97 EC |
359 | u64 iova; |
360 | u64 size; | |
361 | u32 key; | |
362 | u32 pd; | |
e126ba97 EC |
363 | }; |
364 | ||
5903325a | 365 | enum mlx5_res_type { |
e2013b21 | 366 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
367 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
368 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
369 | MLX5_RES_SRQ = 3, | |
370 | MLX5_RES_XSRQ = 4, | |
5903325a EC |
371 | }; |
372 | ||
373 | struct mlx5_core_rsc_common { | |
374 | enum mlx5_res_type res; | |
375 | atomic_t refcount; | |
376 | struct completion free; | |
377 | }; | |
378 | ||
e126ba97 | 379 | struct mlx5_core_srq { |
01949d01 | 380 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
381 | u32 srqn; |
382 | int max; | |
383 | int max_gs; | |
384 | int max_avail_gather; | |
385 | int wqe_shift; | |
386 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
387 | ||
388 | atomic_t refcount; | |
389 | struct completion free; | |
390 | }; | |
391 | ||
392 | struct mlx5_eq_table { | |
393 | void __iomem *update_ci; | |
394 | void __iomem *update_arm_ci; | |
233d05d2 | 395 | struct list_head comp_eqs_list; |
e126ba97 EC |
396 | struct mlx5_eq pages_eq; |
397 | struct mlx5_eq async_eq; | |
398 | struct mlx5_eq cmd_eq; | |
e126ba97 EC |
399 | int num_comp_vectors; |
400 | /* protect EQs list | |
401 | */ | |
402 | spinlock_t lock; | |
403 | }; | |
404 | ||
405 | struct mlx5_uar { | |
406 | u32 index; | |
407 | struct list_head bf_list; | |
408 | unsigned free_bf_bmap; | |
88a85f99 | 409 | void __iomem *bf_map; |
e126ba97 EC |
410 | void __iomem *map; |
411 | }; | |
412 | ||
413 | ||
414 | struct mlx5_core_health { | |
415 | struct health_buffer __iomem *health; | |
416 | __be32 __iomem *health_counter; | |
417 | struct timer_list timer; | |
e126ba97 EC |
418 | u32 prev; |
419 | int miss_counter; | |
fd76ee4d | 420 | bool sick; |
ac6ea6e8 EC |
421 | struct workqueue_struct *wq; |
422 | struct work_struct work; | |
e126ba97 EC |
423 | }; |
424 | ||
425 | struct mlx5_cq_table { | |
426 | /* protect radix tree | |
427 | */ | |
428 | spinlock_t lock; | |
429 | struct radix_tree_root tree; | |
430 | }; | |
431 | ||
432 | struct mlx5_qp_table { | |
433 | /* protect radix tree | |
434 | */ | |
435 | spinlock_t lock; | |
436 | struct radix_tree_root tree; | |
437 | }; | |
438 | ||
439 | struct mlx5_srq_table { | |
440 | /* protect radix tree | |
441 | */ | |
442 | spinlock_t lock; | |
443 | struct radix_tree_root tree; | |
444 | }; | |
445 | ||
a606b0f6 | 446 | struct mlx5_mkey_table { |
3bcdb17a SG |
447 | /* protect radix tree |
448 | */ | |
449 | rwlock_t lock; | |
450 | struct radix_tree_root tree; | |
451 | }; | |
452 | ||
fc50db98 EC |
453 | struct mlx5_vf_context { |
454 | int enabled; | |
455 | }; | |
456 | ||
457 | struct mlx5_core_sriov { | |
458 | struct mlx5_vf_context *vfs_ctx; | |
459 | int num_vfs; | |
460 | int enabled_vfs; | |
461 | }; | |
462 | ||
db058a18 SM |
463 | struct mlx5_irq_info { |
464 | cpumask_var_t mask; | |
465 | char name[MLX5_MAX_IRQ_NAME]; | |
466 | }; | |
467 | ||
43a335e0 | 468 | struct mlx5_fc_stats { |
29cc6679 | 469 | struct rb_root counters; |
43a335e0 AV |
470 | struct list_head addlist; |
471 | /* protect addlist add/splice operations */ | |
472 | spinlock_t addlist_lock; | |
473 | ||
474 | struct workqueue_struct *wq; | |
475 | struct delayed_work work; | |
476 | unsigned long next_query; | |
477 | }; | |
478 | ||
073bb189 | 479 | struct mlx5_eswitch; |
7907f23a | 480 | struct mlx5_lag; |
073bb189 | 481 | |
1466cc5b YP |
482 | struct mlx5_rl_entry { |
483 | u32 rate; | |
484 | u16 index; | |
485 | u16 refcount; | |
486 | }; | |
487 | ||
488 | struct mlx5_rl_table { | |
489 | /* protect rate limit table */ | |
490 | struct mutex rl_lock; | |
491 | u16 max_size; | |
492 | u32 max_rate; | |
493 | u32 min_rate; | |
494 | struct mlx5_rl_entry *rl_entry; | |
495 | }; | |
496 | ||
e126ba97 EC |
497 | struct mlx5_priv { |
498 | char name[MLX5_MAX_NAME_LEN]; | |
499 | struct mlx5_eq_table eq_table; | |
db058a18 SM |
500 | struct msix_entry *msix_arr; |
501 | struct mlx5_irq_info *irq_info; | |
e126ba97 EC |
502 | struct mlx5_uuar_info uuari; |
503 | MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); | |
504 | ||
505 | /* pages stuff */ | |
506 | struct workqueue_struct *pg_wq; | |
507 | struct rb_root page_root; | |
508 | int fw_pages; | |
6aec21f6 | 509 | atomic_t reg_pages; |
bf0bf77f | 510 | struct list_head free_list; |
fc50db98 | 511 | int vfs_pages; |
e126ba97 EC |
512 | |
513 | struct mlx5_core_health health; | |
514 | ||
515 | struct mlx5_srq_table srq_table; | |
516 | ||
517 | /* start: qp staff */ | |
518 | struct mlx5_qp_table qp_table; | |
519 | struct dentry *qp_debugfs; | |
520 | struct dentry *eq_debugfs; | |
521 | struct dentry *cq_debugfs; | |
522 | struct dentry *cmdif_debugfs; | |
523 | /* end: qp staff */ | |
524 | ||
525 | /* start: cq staff */ | |
526 | struct mlx5_cq_table cq_table; | |
527 | /* end: cq staff */ | |
528 | ||
a606b0f6 MB |
529 | /* start: mkey staff */ |
530 | struct mlx5_mkey_table mkey_table; | |
531 | /* end: mkey staff */ | |
3bcdb17a | 532 | |
e126ba97 | 533 | /* start: alloc staff */ |
311c7c71 SM |
534 | /* protect buffer alocation according to numa node */ |
535 | struct mutex alloc_mutex; | |
536 | int numa_node; | |
537 | ||
e126ba97 EC |
538 | struct mutex pgdir_mutex; |
539 | struct list_head pgdir_list; | |
540 | /* end: alloc staff */ | |
541 | struct dentry *dbg_root; | |
542 | ||
543 | /* protect mkey key part */ | |
544 | spinlock_t mkey_lock; | |
545 | u8 mkey_key; | |
9603b61d JM |
546 | |
547 | struct list_head dev_list; | |
548 | struct list_head ctx_list; | |
549 | spinlock_t ctx_lock; | |
073bb189 | 550 | |
fba53f7b | 551 | struct mlx5_flow_steering *steering; |
073bb189 | 552 | struct mlx5_eswitch *eswitch; |
fc50db98 | 553 | struct mlx5_core_sriov sriov; |
7907f23a | 554 | struct mlx5_lag *lag; |
fc50db98 | 555 | unsigned long pci_dev_data; |
43a335e0 | 556 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 557 | struct mlx5_rl_table rl_table; |
e126ba97 EC |
558 | }; |
559 | ||
89d44f0a MD |
560 | enum mlx5_device_state { |
561 | MLX5_DEVICE_STATE_UP, | |
562 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
563 | }; | |
564 | ||
565 | enum mlx5_interface_state { | |
5fc7197d MD |
566 | MLX5_INTERFACE_STATE_DOWN = BIT(0), |
567 | MLX5_INTERFACE_STATE_UP = BIT(1), | |
568 | MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), | |
89d44f0a MD |
569 | }; |
570 | ||
571 | enum mlx5_pci_status { | |
572 | MLX5_PCI_STATUS_DISABLED, | |
573 | MLX5_PCI_STATUS_ENABLED, | |
574 | }; | |
575 | ||
b50d292b HHZ |
576 | struct mlx5_td { |
577 | struct list_head tirs_list; | |
578 | u32 tdn; | |
579 | }; | |
580 | ||
581 | struct mlx5e_resources { | |
582 | struct mlx5_uar cq_uar; | |
583 | u32 pdn; | |
584 | struct mlx5_td td; | |
585 | struct mlx5_core_mkey mkey; | |
586 | }; | |
587 | ||
e126ba97 EC |
588 | struct mlx5_core_dev { |
589 | struct pci_dev *pdev; | |
89d44f0a MD |
590 | /* sync pci state */ |
591 | struct mutex pci_status_mutex; | |
592 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
593 | u8 rev_id; |
594 | char board_id[MLX5_BOARD_ID_LEN]; | |
595 | struct mlx5_cmd cmd; | |
938fe83c SM |
596 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
597 | u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
598 | u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
e126ba97 EC |
599 | phys_addr_t iseg_base; |
600 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
601 | enum mlx5_device_state state; |
602 | /* sync interface state */ | |
603 | struct mutex intf_state_mutex; | |
5fc7197d | 604 | unsigned long intf_state; |
e126ba97 EC |
605 | void (*event) (struct mlx5_core_dev *dev, |
606 | enum mlx5_dev_event event, | |
4d2f9bbb | 607 | unsigned long param); |
e126ba97 EC |
608 | struct mlx5_priv priv; |
609 | struct mlx5_profile *profile; | |
610 | atomic_t num_qps; | |
f62b8bb8 | 611 | u32 issi; |
b50d292b | 612 | struct mlx5e_resources mlx5e_res; |
5a7b27eb MG |
613 | #ifdef CONFIG_RFS_ACCEL |
614 | struct cpu_rmap *rmap; | |
615 | #endif | |
e126ba97 EC |
616 | }; |
617 | ||
618 | struct mlx5_db { | |
619 | __be32 *db; | |
620 | union { | |
621 | struct mlx5_db_pgdir *pgdir; | |
622 | struct mlx5_ib_user_db_page *user_page; | |
623 | } u; | |
624 | dma_addr_t dma; | |
625 | int index; | |
626 | }; | |
627 | ||
628 | enum { | |
629 | MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, | |
630 | }; | |
631 | ||
632 | enum { | |
633 | MLX5_COMP_EQ_SIZE = 1024, | |
634 | }; | |
635 | ||
adb0c954 SM |
636 | enum { |
637 | MLX5_PTYS_IB = 1 << 0, | |
638 | MLX5_PTYS_EN = 1 << 2, | |
639 | }; | |
640 | ||
e126ba97 EC |
641 | struct mlx5_db_pgdir { |
642 | struct list_head list; | |
643 | DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); | |
644 | __be32 *db_page; | |
645 | dma_addr_t db_dma; | |
646 | }; | |
647 | ||
648 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); | |
649 | ||
650 | struct mlx5_cmd_work_ent { | |
651 | struct mlx5_cmd_msg *in; | |
652 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
653 | void *uout; |
654 | int uout_size; | |
e126ba97 | 655 | mlx5_cmd_cbk_t callback; |
65ee6708 | 656 | struct delayed_work cb_timeout_work; |
e126ba97 | 657 | void *context; |
746b5583 | 658 | int idx; |
e126ba97 EC |
659 | struct completion done; |
660 | struct mlx5_cmd *cmd; | |
661 | struct work_struct work; | |
662 | struct mlx5_cmd_layout *lay; | |
663 | int ret; | |
664 | int page_queue; | |
665 | u8 status; | |
666 | u8 token; | |
14a70046 TG |
667 | u64 ts1; |
668 | u64 ts2; | |
746b5583 | 669 | u16 op; |
e126ba97 EC |
670 | }; |
671 | ||
672 | struct mlx5_pas { | |
673 | u64 pa; | |
674 | u8 log_sz; | |
675 | }; | |
676 | ||
707c4602 | 677 | enum port_state_policy { |
eff901d3 EC |
678 | MLX5_POLICY_DOWN = 0, |
679 | MLX5_POLICY_UP = 1, | |
680 | MLX5_POLICY_FOLLOW = 2, | |
681 | MLX5_POLICY_INVALID = 0xffffffff | |
707c4602 MD |
682 | }; |
683 | ||
684 | enum phy_port_state { | |
685 | MLX5_AAA_111 | |
686 | }; | |
687 | ||
688 | struct mlx5_hca_vport_context { | |
689 | u32 field_select; | |
690 | bool sm_virt_aware; | |
691 | bool has_smi; | |
692 | bool has_raw; | |
693 | enum port_state_policy policy; | |
694 | enum phy_port_state phys_state; | |
695 | enum ib_port_state vport_state; | |
696 | u8 port_physical_state; | |
697 | u64 sys_image_guid; | |
698 | u64 port_guid; | |
699 | u64 node_guid; | |
700 | u32 cap_mask1; | |
701 | u32 cap_mask1_perm; | |
702 | u32 cap_mask2; | |
703 | u32 cap_mask2_perm; | |
704 | u16 lid; | |
705 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
706 | u8 lmc; | |
707 | u8 subnet_timeout; | |
708 | u16 sm_lid; | |
709 | u8 sm_sl; | |
710 | u16 qkey_violation_counter; | |
711 | u16 pkey_violation_counter; | |
712 | bool grh_required; | |
713 | }; | |
714 | ||
e126ba97 EC |
715 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
716 | { | |
e126ba97 | 717 | return buf->direct.buf + offset; |
e126ba97 EC |
718 | } |
719 | ||
720 | extern struct workqueue_struct *mlx5_core_wq; | |
721 | ||
722 | #define STRUCT_FIELD(header, field) \ | |
723 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
724 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
725 | ||
e126ba97 EC |
726 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
727 | { | |
728 | return pci_get_drvdata(pdev); | |
729 | } | |
730 | ||
731 | extern struct dentry *mlx5_debugfs_root; | |
732 | ||
733 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
734 | { | |
735 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
736 | } | |
737 | ||
738 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
739 | { | |
740 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
741 | } | |
742 | ||
743 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
744 | { | |
745 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
746 | } | |
747 | ||
748 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
749 | { | |
750 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
751 | } | |
752 | ||
753 | static inline void *mlx5_vzalloc(unsigned long size) | |
754 | { | |
755 | void *rtn; | |
756 | ||
757 | rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); | |
758 | if (!rtn) | |
759 | rtn = vzalloc(size); | |
760 | return rtn; | |
761 | } | |
762 | ||
3bcdb17a SG |
763 | static inline u32 mlx5_base_mkey(const u32 key) |
764 | { | |
765 | return key & 0xffffff00u; | |
766 | } | |
767 | ||
e126ba97 EC |
768 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
769 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
770 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
771 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 772 | |
e126ba97 EC |
773 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
774 | int out_size); | |
746b5583 EC |
775 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
776 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
777 | void *context); | |
c4f287c4 SM |
778 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
779 | ||
780 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
781 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
782 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
783 | int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
784 | int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
0ba42241 ML |
785 | int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar, |
786 | bool map_wc); | |
e281682b | 787 | void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); |
ac6ea6e8 EC |
788 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
789 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
790 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
791 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
311c7c71 SM |
792 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
793 | struct mlx5_buf *buf, int node); | |
64ffaa21 | 794 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 EC |
795 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
796 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
797 | gfp_t flags, int npages); | |
798 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
799 | struct mlx5_cmd_mailbox *head); | |
800 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 801 | struct mlx5_srq_attr *in); |
e126ba97 EC |
802 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
803 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 804 | struct mlx5_srq_attr *out); |
e126ba97 EC |
805 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
806 | u16 lwm, int is_srq); | |
a606b0f6 MB |
807 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
808 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
809 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
810 | struct mlx5_core_mkey *mkey, | |
811 | u32 *in, int inlen, | |
812 | u32 *out, int outlen, | |
813 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
814 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
815 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 816 | u32 *in, int inlen); |
a606b0f6 MB |
817 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
818 | struct mlx5_core_mkey *mkey); | |
819 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 820 | u32 *out, int outlen); |
a606b0f6 | 821 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, |
e126ba97 EC |
822 | u32 *mkey); |
823 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
824 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 825 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 826 | u16 opmod, u8 port); |
e126ba97 EC |
827 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
828 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
829 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
830 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
fc50db98 EC |
831 | int mlx5_sriov_init(struct mlx5_core_dev *dev); |
832 | int mlx5_sriov_cleanup(struct mlx5_core_dev *dev); | |
e126ba97 | 833 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, |
0a324f31 | 834 | s32 npages); |
cd23b14b | 835 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
836 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
837 | void mlx5_register_debugfs(void); | |
838 | void mlx5_unregister_debugfs(void); | |
839 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
840 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
841 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
842 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); | |
5903325a | 843 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e420f0c0 HE |
844 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
845 | void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); | |
846 | #endif | |
e126ba97 EC |
847 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
848 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
020446e0 | 849 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); |
e126ba97 EC |
850 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
851 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
852 | int nent, u64 mask, const char *name, struct mlx5_uar *uar); | |
853 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
854 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
855 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
0b6e26ce DT |
856 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
857 | unsigned int *irqn); | |
e126ba97 EC |
858 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
859 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
860 | ||
861 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
862 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
863 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
864 | int size_in, void *data_out, int size_out, | |
865 | u16 reg_num, int arg, int write); | |
adb0c954 | 866 | |
e126ba97 EC |
867 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
868 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
869 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
73b626c1 | 870 | u32 *out, int outlen); |
e126ba97 EC |
871 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); |
872 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
873 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
874 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
875 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
311c7c71 SM |
876 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
877 | int node); | |
e126ba97 EC |
878 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
879 | ||
e126ba97 EC |
880 | const char *mlx5_command_str(int command); |
881 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
882 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
883 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
884 | int npsvs, u32 *sig_index); | |
885 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 886 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
887 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
888 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
889 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
890 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 891 | |
1466cc5b YP |
892 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
893 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
894 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); | |
895 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); | |
896 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); | |
897 | ||
e3297246 EC |
898 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
899 | { | |
900 | return ioread32be(&dev->iseg->initializing) >> 31; | |
901 | } | |
902 | ||
e126ba97 EC |
903 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
904 | { | |
905 | return mkey >> 8; | |
906 | } | |
907 | ||
908 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
909 | { | |
910 | return mkey_idx << 8; | |
911 | } | |
912 | ||
746b5583 EC |
913 | static inline u8 mlx5_mkey_variant(u32 mkey) |
914 | { | |
915 | return mkey & 0xff; | |
916 | } | |
917 | ||
e126ba97 EC |
918 | enum { |
919 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 920 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
921 | }; |
922 | ||
923 | enum { | |
924 | MAX_MR_CACHE_ENTRIES = 16, | |
925 | }; | |
926 | ||
64613d94 SM |
927 | enum { |
928 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
929 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
930 | }; | |
931 | ||
9603b61d JM |
932 | struct mlx5_interface { |
933 | void * (*add)(struct mlx5_core_dev *dev); | |
934 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
935 | void (*event)(struct mlx5_core_dev *dev, void *context, | |
4d2f9bbb | 936 | enum mlx5_dev_event event, unsigned long param); |
64613d94 SM |
937 | void * (*get_dev)(void *context); |
938 | int protocol; | |
9603b61d JM |
939 | struct list_head list; |
940 | }; | |
941 | ||
64613d94 | 942 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
943 | int mlx5_register_interface(struct mlx5_interface *intf); |
944 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 945 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 946 | |
7907f23a AH |
947 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
948 | ||
e126ba97 EC |
949 | struct mlx5_profile { |
950 | u64 mask; | |
f241e749 | 951 | u8 log_max_qp; |
e126ba97 EC |
952 | struct { |
953 | int size; | |
954 | int limit; | |
955 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
956 | }; | |
957 | ||
fc50db98 EC |
958 | enum { |
959 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
960 | }; | |
961 | ||
962 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
963 | { | |
964 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
965 | } | |
966 | ||
707c4602 MD |
967 | static inline int mlx5_get_gid_table_len(u16 param) |
968 | { | |
969 | if (param > 4) { | |
970 | pr_warn("gid table length is zero\n"); | |
971 | return 0; | |
972 | } | |
973 | ||
974 | return 8 * (1 << param); | |
975 | } | |
976 | ||
1466cc5b YP |
977 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
978 | { | |
979 | return !!(dev->priv.rl_table.max_size); | |
980 | } | |
981 | ||
020446e0 EC |
982 | enum { |
983 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
984 | }; | |
985 | ||
e126ba97 | 986 | #endif /* MLX5_DRIVER_H */ |