Commit | Line | Data |
---|---|---|
e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 EC |
43 | #include <linux/vmalloc.h> |
44 | #include <linux/radix-tree.h> | |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
6ecde51d | 49 | |
e126ba97 EC |
50 | #include <linux/mlx5/device.h> |
51 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 52 | #include <linux/mlx5/srq.h> |
7c39afb3 FD |
53 | #include <linux/timecounter.h> |
54 | #include <linux/ptp_clock_kernel.h> | |
e126ba97 EC |
55 | |
56 | enum { | |
57 | MLX5_BOARD_ID_LEN = 64, | |
58 | MLX5_MAX_NAME_LEN = 16, | |
59 | }; | |
60 | ||
61 | enum { | |
62 | /* one minute for the sake of bringup. Generally, commands must always | |
63 | * complete and we may need to increase this timeout value | |
64 | */ | |
6b6c07bd | 65 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
66 | MLX5_CMD_WQ_MAX_NAME = 32, |
67 | }; | |
68 | ||
69 | enum { | |
70 | CMD_OWNER_SW = 0x0, | |
71 | CMD_OWNER_HW = 0x1, | |
72 | CMD_STATUS_SUCCESS = 0, | |
73 | }; | |
74 | ||
75 | enum mlx5_sqp_t { | |
76 | MLX5_SQP_SMI = 0, | |
77 | MLX5_SQP_GSI = 1, | |
78 | MLX5_SQP_IEEE_1588 = 2, | |
79 | MLX5_SQP_SNIFFER = 3, | |
80 | MLX5_SQP_SYNC_UMR = 4, | |
81 | }; | |
82 | ||
83 | enum { | |
84 | MLX5_MAX_PORTS = 2, | |
85 | }; | |
86 | ||
87 | enum { | |
88 | MLX5_EQ_VEC_PAGES = 0, | |
89 | MLX5_EQ_VEC_CMD = 1, | |
90 | MLX5_EQ_VEC_ASYNC = 2, | |
d9aaed83 | 91 | MLX5_EQ_VEC_PFAULT = 3, |
e126ba97 EC |
92 | MLX5_EQ_VEC_COMP_BASE, |
93 | }; | |
94 | ||
95 | enum { | |
db058a18 | 96 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
97 | }; |
98 | ||
99 | enum { | |
100 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
101 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
102 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
103 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
104 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
105 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
106 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
107 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
108 | }; | |
109 | ||
e126ba97 | 110 | enum { |
415a64aa | 111 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
112 | MLX5_REG_QETCR = 0x4005, |
113 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 114 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 115 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
116 | MLX5_REG_DCBX_PARAM = 0x4020, |
117 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
118 | MLX5_REG_FPGA_CAP = 0x4022, |
119 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 120 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
e126ba97 EC |
121 | MLX5_REG_PCAP = 0x5001, |
122 | MLX5_REG_PMTU = 0x5003, | |
123 | MLX5_REG_PTYS = 0x5004, | |
124 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 125 | MLX5_REG_PFCC = 0x5007, |
efea389d | 126 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
127 | MLX5_REG_PPTB = 0x500b, |
128 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
129 | MLX5_REG_PMAOS = 0x5012, |
130 | MLX5_REG_PUDE = 0x5009, | |
131 | MLX5_REG_PMPE = 0x5010, | |
132 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 133 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 134 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 135 | MLX5_REG_PMLP = 0x5002, |
cfdcbcea | 136 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
137 | MLX5_REG_NODE_DESC = 0x6001, |
138 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 139 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 140 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
141 | MLX5_REG_MTRC_CAP = 0x9040, |
142 | MLX5_REG_MTRC_CONF = 0x9041, | |
143 | MLX5_REG_MTRC_STDB = 0x9042, | |
144 | MLX5_REG_MTRC_CTRL = 0x9043, | |
8ed1a630 | 145 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
146 | MLX5_REG_MTPPS = 0x9053, |
147 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 148 | MLX5_REG_MPEGC = 0x9056, |
47176289 OG |
149 | MLX5_REG_MCQI = 0x9061, |
150 | MLX5_REG_MCC = 0x9062, | |
151 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 152 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
153 | }; |
154 | ||
415a64aa HN |
155 | enum mlx5_qpts_trust_state { |
156 | MLX5_QPTS_TRUST_PCP = 1, | |
157 | MLX5_QPTS_TRUST_DSCP = 2, | |
158 | }; | |
159 | ||
341c5ee2 HN |
160 | enum mlx5_dcbx_oper_mode { |
161 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
162 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
163 | }; | |
164 | ||
57cda166 | 165 | enum mlx5_dct_atomic_mode { |
aa7e80b2 | 166 | MLX5_ATOMIC_MODE_DCT_CX = 2, |
57cda166 MS |
167 | }; |
168 | ||
da7525d2 EBE |
169 | enum { |
170 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
171 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
172 | }; | |
173 | ||
e420f0c0 HE |
174 | enum mlx5_page_fault_resume_flags { |
175 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
176 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
177 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
178 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
179 | }; | |
180 | ||
e126ba97 EC |
181 | enum dbg_rsc_type { |
182 | MLX5_DBG_RSC_QP, | |
183 | MLX5_DBG_RSC_EQ, | |
184 | MLX5_DBG_RSC_CQ, | |
185 | }; | |
186 | ||
7ecf6d8f BW |
187 | enum port_state_policy { |
188 | MLX5_POLICY_DOWN = 0, | |
189 | MLX5_POLICY_UP = 1, | |
190 | MLX5_POLICY_FOLLOW = 2, | |
191 | MLX5_POLICY_INVALID = 0xffffffff | |
192 | }; | |
193 | ||
e126ba97 EC |
194 | struct mlx5_field_desc { |
195 | struct dentry *dent; | |
196 | int i; | |
197 | }; | |
198 | ||
199 | struct mlx5_rsc_debug { | |
200 | struct mlx5_core_dev *dev; | |
201 | void *object; | |
202 | enum dbg_rsc_type type; | |
203 | struct dentry *root; | |
204 | struct mlx5_field_desc fields[0]; | |
205 | }; | |
206 | ||
207 | enum mlx5_dev_event { | |
208 | MLX5_DEV_EVENT_SYS_ERROR, | |
209 | MLX5_DEV_EVENT_PORT_UP, | |
210 | MLX5_DEV_EVENT_PORT_DOWN, | |
211 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
212 | MLX5_DEV_EVENT_LID_CHANGE, | |
213 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
214 | MLX5_DEV_EVENT_GUID_CHANGE, | |
215 | MLX5_DEV_EVENT_CLIENT_REREG, | |
f9a1ef72 | 216 | MLX5_DEV_EVENT_PPS, |
246ac981 | 217 | MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, |
e126ba97 EC |
218 | }; |
219 | ||
4c916a79 | 220 | enum mlx5_port_status { |
6fa1bcab AS |
221 | MLX5_PORT_UP = 1, |
222 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
223 | }; |
224 | ||
d9aaed83 AK |
225 | enum mlx5_eq_type { |
226 | MLX5_EQ_TYPE_COMP, | |
227 | MLX5_EQ_TYPE_ASYNC, | |
228 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
229 | MLX5_EQ_TYPE_PF, | |
230 | #endif | |
231 | }; | |
232 | ||
2f5ff264 | 233 | struct mlx5_bfreg_info { |
b037c29a | 234 | u32 *sys_pages; |
2f5ff264 | 235 | int num_low_latency_bfregs; |
e126ba97 | 236 | unsigned int *count; |
e126ba97 EC |
237 | |
238 | /* | |
2f5ff264 | 239 | * protect bfreg allocation data structs |
e126ba97 EC |
240 | */ |
241 | struct mutex lock; | |
78c0f98c | 242 | u32 ver; |
b037c29a EC |
243 | bool lib_uar_4k; |
244 | u32 num_sys_pages; | |
31a78a5a YH |
245 | u32 num_static_sys_pages; |
246 | u32 total_num_bfregs; | |
247 | u32 num_dyn_bfregs; | |
e126ba97 EC |
248 | }; |
249 | ||
250 | struct mlx5_cmd_first { | |
251 | __be32 data[4]; | |
252 | }; | |
253 | ||
254 | struct mlx5_cmd_msg { | |
255 | struct list_head list; | |
0ac3ea70 | 256 | struct cmd_msg_cache *parent; |
e126ba97 EC |
257 | u32 len; |
258 | struct mlx5_cmd_first first; | |
259 | struct mlx5_cmd_mailbox *next; | |
260 | }; | |
261 | ||
262 | struct mlx5_cmd_debug { | |
263 | struct dentry *dbg_root; | |
264 | struct dentry *dbg_in; | |
265 | struct dentry *dbg_out; | |
266 | struct dentry *dbg_outlen; | |
267 | struct dentry *dbg_status; | |
268 | struct dentry *dbg_run; | |
269 | void *in_msg; | |
270 | void *out_msg; | |
271 | u8 status; | |
272 | u16 inlen; | |
273 | u16 outlen; | |
274 | }; | |
275 | ||
0ac3ea70 | 276 | struct cmd_msg_cache { |
e126ba97 EC |
277 | /* protect block chain allocations |
278 | */ | |
279 | spinlock_t lock; | |
280 | struct list_head head; | |
0ac3ea70 MHY |
281 | unsigned int max_inbox_size; |
282 | unsigned int num_ent; | |
e126ba97 EC |
283 | }; |
284 | ||
0ac3ea70 MHY |
285 | enum { |
286 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
287 | }; |
288 | ||
289 | struct mlx5_cmd_stats { | |
290 | u64 sum; | |
291 | u64 n; | |
292 | struct dentry *root; | |
293 | struct dentry *avg; | |
294 | struct dentry *count; | |
295 | /* protect command average calculations */ | |
296 | spinlock_t lock; | |
297 | }; | |
298 | ||
299 | struct mlx5_cmd { | |
64599cca EC |
300 | void *cmd_alloc_buf; |
301 | dma_addr_t alloc_dma; | |
302 | int alloc_size; | |
e126ba97 EC |
303 | void *cmd_buf; |
304 | dma_addr_t dma; | |
305 | u16 cmdif_rev; | |
306 | u8 log_sz; | |
307 | u8 log_stride; | |
308 | int max_reg_cmds; | |
309 | int events; | |
310 | u32 __iomem *vector; | |
311 | ||
312 | /* protect command queue allocations | |
313 | */ | |
314 | spinlock_t alloc_lock; | |
315 | ||
316 | /* protect token allocations | |
317 | */ | |
318 | spinlock_t token_lock; | |
319 | u8 token; | |
320 | unsigned long bitmask; | |
321 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
322 | struct workqueue_struct *wq; | |
323 | struct semaphore sem; | |
324 | struct semaphore pages_sem; | |
325 | int mode; | |
326 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 327 | struct dma_pool *pool; |
e126ba97 | 328 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 329 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
330 | int checksum_disabled; |
331 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
332 | }; | |
333 | ||
334 | struct mlx5_port_caps { | |
335 | int gid_table_len; | |
336 | int pkey_table_len; | |
938fe83c | 337 | u8 ext_port_cap; |
c43f1112 | 338 | bool has_smi; |
e126ba97 EC |
339 | }; |
340 | ||
341 | struct mlx5_cmd_mailbox { | |
342 | void *buf; | |
343 | dma_addr_t dma; | |
344 | struct mlx5_cmd_mailbox *next; | |
345 | }; | |
346 | ||
347 | struct mlx5_buf_list { | |
348 | void *buf; | |
349 | dma_addr_t map; | |
350 | }; | |
351 | ||
1c1b5228 TT |
352 | struct mlx5_frag_buf { |
353 | struct mlx5_buf_list *frags; | |
354 | int npages; | |
355 | int size; | |
356 | u8 page_shift; | |
357 | }; | |
358 | ||
388ca8be YC |
359 | struct mlx5_frag_buf_ctrl { |
360 | struct mlx5_frag_buf frag_buf; | |
361 | u32 sz_m1; | |
362 | u32 frag_sz_m1; | |
d7037ad7 | 363 | u32 strides_offset; |
388ca8be YC |
364 | u8 log_sz; |
365 | u8 log_stride; | |
366 | u8 log_frag_strides; | |
367 | }; | |
368 | ||
94c6825e MB |
369 | struct mlx5_eq_tasklet { |
370 | struct list_head list; | |
371 | struct list_head process_list; | |
372 | struct tasklet_struct task; | |
373 | /* lock on completion tasklet list */ | |
374 | spinlock_t lock; | |
375 | }; | |
376 | ||
d9aaed83 AK |
377 | struct mlx5_eq_pagefault { |
378 | struct work_struct work; | |
379 | /* Pagefaults lock */ | |
380 | spinlock_t lock; | |
381 | struct workqueue_struct *wq; | |
382 | mempool_t *pool; | |
383 | }; | |
384 | ||
02d92f79 SM |
385 | struct mlx5_cq_table { |
386 | /* protect radix tree */ | |
387 | spinlock_t lock; | |
388 | struct radix_tree_root tree; | |
389 | }; | |
390 | ||
e126ba97 EC |
391 | struct mlx5_eq { |
392 | struct mlx5_core_dev *dev; | |
02d92f79 | 393 | struct mlx5_cq_table cq_table; |
e126ba97 EC |
394 | __be32 __iomem *doorbell; |
395 | u32 cons_index; | |
388ca8be | 396 | struct mlx5_frag_buf buf; |
e126ba97 | 397 | int size; |
0b6e26ce | 398 | unsigned int irqn; |
e126ba97 EC |
399 | u8 eqn; |
400 | int nent; | |
401 | u64 mask; | |
e126ba97 EC |
402 | struct list_head list; |
403 | int index; | |
404 | struct mlx5_rsc_debug *dbg; | |
d9aaed83 AK |
405 | enum mlx5_eq_type type; |
406 | union { | |
407 | struct mlx5_eq_tasklet tasklet_ctx; | |
408 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
409 | struct mlx5_eq_pagefault pf_ctx; | |
410 | #endif | |
411 | }; | |
e126ba97 EC |
412 | }; |
413 | ||
3121e3c4 SG |
414 | struct mlx5_core_psv { |
415 | u32 psv_idx; | |
416 | struct psv_layout { | |
417 | u32 pd; | |
418 | u16 syndrome; | |
419 | u16 reserved; | |
420 | u16 bg; | |
421 | u16 app_tag; | |
422 | u32 ref_tag; | |
423 | } psv; | |
424 | }; | |
425 | ||
426 | struct mlx5_core_sig_ctx { | |
427 | struct mlx5_core_psv psv_memory; | |
428 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
429 | struct ib_sig_err err_item; |
430 | bool sig_status_checked; | |
431 | bool sig_err_exists; | |
432 | u32 sigerr_count; | |
3121e3c4 | 433 | }; |
e126ba97 | 434 | |
aa8e08d2 AK |
435 | enum { |
436 | MLX5_MKEY_MR = 1, | |
437 | MLX5_MKEY_MW, | |
438 | }; | |
439 | ||
a606b0f6 | 440 | struct mlx5_core_mkey { |
e126ba97 EC |
441 | u64 iova; |
442 | u64 size; | |
443 | u32 key; | |
444 | u32 pd; | |
aa8e08d2 | 445 | u32 type; |
e126ba97 EC |
446 | }; |
447 | ||
d9aaed83 AK |
448 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
449 | ||
5903325a | 450 | enum mlx5_res_type { |
e2013b21 | 451 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
452 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
453 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
454 | MLX5_RES_SRQ = 3, | |
455 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 456 | MLX5_RES_XRQ = 5, |
57cda166 | 457 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
458 | }; |
459 | ||
460 | struct mlx5_core_rsc_common { | |
461 | enum mlx5_res_type res; | |
462 | atomic_t refcount; | |
463 | struct completion free; | |
464 | }; | |
465 | ||
e126ba97 | 466 | struct mlx5_core_srq { |
01949d01 | 467 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
468 | u32 srqn; |
469 | int max; | |
c2b37f76 BP |
470 | size_t max_gs; |
471 | size_t max_avail_gather; | |
e126ba97 EC |
472 | int wqe_shift; |
473 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
474 | ||
475 | atomic_t refcount; | |
476 | struct completion free; | |
a0d8c054 | 477 | u16 uid; |
e126ba97 EC |
478 | }; |
479 | ||
480 | struct mlx5_eq_table { | |
481 | void __iomem *update_ci; | |
482 | void __iomem *update_arm_ci; | |
233d05d2 | 483 | struct list_head comp_eqs_list; |
e126ba97 EC |
484 | struct mlx5_eq pages_eq; |
485 | struct mlx5_eq async_eq; | |
486 | struct mlx5_eq cmd_eq; | |
d9aaed83 AK |
487 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
488 | struct mlx5_eq pfault_eq; | |
489 | #endif | |
e126ba97 EC |
490 | int num_comp_vectors; |
491 | /* protect EQs list | |
492 | */ | |
493 | spinlock_t lock; | |
494 | }; | |
495 | ||
a6d51b68 | 496 | struct mlx5_uars_page { |
e126ba97 | 497 | void __iomem *map; |
a6d51b68 EC |
498 | bool wc; |
499 | u32 index; | |
500 | struct list_head list; | |
501 | unsigned int bfregs; | |
502 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
503 | unsigned long *fp_bitmap; | |
504 | unsigned int reg_avail; | |
505 | unsigned int fp_avail; | |
506 | struct kref ref_count; | |
507 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
508 | }; |
509 | ||
a6d51b68 EC |
510 | struct mlx5_bfreg_head { |
511 | /* protect blue flame registers allocations */ | |
512 | struct mutex lock; | |
513 | struct list_head list; | |
514 | }; | |
515 | ||
516 | struct mlx5_bfreg_data { | |
517 | struct mlx5_bfreg_head reg_head; | |
518 | struct mlx5_bfreg_head wc_head; | |
519 | }; | |
520 | ||
521 | struct mlx5_sq_bfreg { | |
522 | void __iomem *map; | |
523 | struct mlx5_uars_page *up; | |
524 | bool wc; | |
525 | u32 index; | |
526 | unsigned int offset; | |
527 | }; | |
e126ba97 EC |
528 | |
529 | struct mlx5_core_health { | |
530 | struct health_buffer __iomem *health; | |
531 | __be32 __iomem *health_counter; | |
532 | struct timer_list timer; | |
e126ba97 EC |
533 | u32 prev; |
534 | int miss_counter; | |
fd76ee4d | 535 | bool sick; |
05ac2c0b MHY |
536 | /* wq spinlock to synchronize draining */ |
537 | spinlock_t wq_lock; | |
ac6ea6e8 | 538 | struct workqueue_struct *wq; |
05ac2c0b | 539 | unsigned long flags; |
ac6ea6e8 | 540 | struct work_struct work; |
04c0c1ab | 541 | struct delayed_work recover_work; |
e126ba97 EC |
542 | }; |
543 | ||
e126ba97 EC |
544 | struct mlx5_qp_table { |
545 | /* protect radix tree | |
546 | */ | |
547 | spinlock_t lock; | |
548 | struct radix_tree_root tree; | |
549 | }; | |
550 | ||
551 | struct mlx5_srq_table { | |
552 | /* protect radix tree | |
553 | */ | |
554 | spinlock_t lock; | |
555 | struct radix_tree_root tree; | |
556 | }; | |
557 | ||
a606b0f6 | 558 | struct mlx5_mkey_table { |
3bcdb17a SG |
559 | /* protect radix tree |
560 | */ | |
561 | rwlock_t lock; | |
562 | struct radix_tree_root tree; | |
563 | }; | |
564 | ||
fc50db98 EC |
565 | struct mlx5_vf_context { |
566 | int enabled; | |
7ecf6d8f BW |
567 | u64 port_guid; |
568 | u64 node_guid; | |
569 | enum port_state_policy policy; | |
fc50db98 EC |
570 | }; |
571 | ||
572 | struct mlx5_core_sriov { | |
573 | struct mlx5_vf_context *vfs_ctx; | |
574 | int num_vfs; | |
575 | int enabled_vfs; | |
576 | }; | |
577 | ||
db058a18 | 578 | struct mlx5_irq_info { |
231243c8 | 579 | cpumask_var_t mask; |
db058a18 SM |
580 | char name[MLX5_MAX_IRQ_NAME]; |
581 | }; | |
582 | ||
43a335e0 | 583 | struct mlx5_fc_stats { |
29cc6679 | 584 | struct rb_root counters; |
43a335e0 AV |
585 | struct list_head addlist; |
586 | /* protect addlist add/splice operations */ | |
587 | spinlock_t addlist_lock; | |
588 | ||
589 | struct workqueue_struct *wq; | |
590 | struct delayed_work work; | |
591 | unsigned long next_query; | |
f6dfb4c3 | 592 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
593 | }; |
594 | ||
eeb66cdb | 595 | struct mlx5_mpfs; |
073bb189 | 596 | struct mlx5_eswitch; |
7907f23a | 597 | struct mlx5_lag; |
d9aaed83 | 598 | struct mlx5_pagefault; |
073bb189 | 599 | |
05d3ac97 BW |
600 | struct mlx5_rate_limit { |
601 | u32 rate; | |
602 | u32 max_burst_sz; | |
603 | u16 typical_pkt_sz; | |
604 | }; | |
605 | ||
1466cc5b | 606 | struct mlx5_rl_entry { |
05d3ac97 | 607 | struct mlx5_rate_limit rl; |
1466cc5b YP |
608 | u16 index; |
609 | u16 refcount; | |
610 | }; | |
611 | ||
612 | struct mlx5_rl_table { | |
613 | /* protect rate limit table */ | |
614 | struct mutex rl_lock; | |
615 | u16 max_size; | |
616 | u32 max_rate; | |
617 | u32 min_rate; | |
618 | struct mlx5_rl_entry *rl_entry; | |
619 | }; | |
620 | ||
d4eb4cd7 HN |
621 | enum port_module_event_status_type { |
622 | MLX5_MODULE_STATUS_PLUGGED = 0x1, | |
623 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, | |
624 | MLX5_MODULE_STATUS_ERROR = 0x3, | |
625 | MLX5_MODULE_STATUS_NUM = 0x3, | |
626 | }; | |
627 | ||
628 | enum port_module_event_error_type { | |
629 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, | |
630 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, | |
631 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, | |
632 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, | |
633 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, | |
634 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, | |
635 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, | |
636 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, | |
637 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, | |
638 | MLX5_MODULE_EVENT_ERROR_NUM, | |
639 | }; | |
640 | ||
641 | struct mlx5_port_module_event_stats { | |
642 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; | |
643 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; | |
644 | }; | |
645 | ||
e126ba97 EC |
646 | struct mlx5_priv { |
647 | char name[MLX5_MAX_NAME_LEN]; | |
648 | struct mlx5_eq_table eq_table; | |
db058a18 | 649 | struct mlx5_irq_info *irq_info; |
e126ba97 EC |
650 | |
651 | /* pages stuff */ | |
652 | struct workqueue_struct *pg_wq; | |
653 | struct rb_root page_root; | |
654 | int fw_pages; | |
6aec21f6 | 655 | atomic_t reg_pages; |
bf0bf77f | 656 | struct list_head free_list; |
fc50db98 | 657 | int vfs_pages; |
e126ba97 EC |
658 | |
659 | struct mlx5_core_health health; | |
660 | ||
661 | struct mlx5_srq_table srq_table; | |
662 | ||
663 | /* start: qp staff */ | |
664 | struct mlx5_qp_table qp_table; | |
665 | struct dentry *qp_debugfs; | |
666 | struct dentry *eq_debugfs; | |
667 | struct dentry *cq_debugfs; | |
668 | struct dentry *cmdif_debugfs; | |
669 | /* end: qp staff */ | |
670 | ||
a606b0f6 MB |
671 | /* start: mkey staff */ |
672 | struct mlx5_mkey_table mkey_table; | |
673 | /* end: mkey staff */ | |
3bcdb17a | 674 | |
e126ba97 | 675 | /* start: alloc staff */ |
311c7c71 SM |
676 | /* protect buffer alocation according to numa node */ |
677 | struct mutex alloc_mutex; | |
678 | int numa_node; | |
679 | ||
e126ba97 EC |
680 | struct mutex pgdir_mutex; |
681 | struct list_head pgdir_list; | |
682 | /* end: alloc staff */ | |
683 | struct dentry *dbg_root; | |
684 | ||
685 | /* protect mkey key part */ | |
686 | spinlock_t mkey_lock; | |
687 | u8 mkey_key; | |
9603b61d JM |
688 | |
689 | struct list_head dev_list; | |
690 | struct list_head ctx_list; | |
691 | spinlock_t ctx_lock; | |
073bb189 | 692 | |
97834eba ES |
693 | struct list_head waiting_events_list; |
694 | bool is_accum_events; | |
695 | ||
fba53f7b | 696 | struct mlx5_flow_steering *steering; |
eeb66cdb | 697 | struct mlx5_mpfs *mpfs; |
073bb189 | 698 | struct mlx5_eswitch *eswitch; |
fc50db98 | 699 | struct mlx5_core_sriov sriov; |
7907f23a | 700 | struct mlx5_lag *lag; |
fc50db98 | 701 | unsigned long pci_dev_data; |
43a335e0 | 702 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 703 | struct mlx5_rl_table rl_table; |
d4eb4cd7 HN |
704 | |
705 | struct mlx5_port_module_event_stats pme_stats; | |
d9aaed83 AK |
706 | |
707 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
708 | void (*pfault)(struct mlx5_core_dev *dev, | |
709 | void *context, | |
710 | struct mlx5_pagefault *pfault); | |
711 | void *pfault_ctx; | |
712 | struct srcu_struct pfault_srcu; | |
713 | #endif | |
a6d51b68 | 714 | struct mlx5_bfreg_data bfregs; |
01187175 | 715 | struct mlx5_uars_page *uar; |
e126ba97 EC |
716 | }; |
717 | ||
89d44f0a MD |
718 | enum mlx5_device_state { |
719 | MLX5_DEVICE_STATE_UP, | |
720 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
721 | }; | |
722 | ||
723 | enum mlx5_interface_state { | |
b3cb5388 | 724 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
725 | }; |
726 | ||
727 | enum mlx5_pci_status { | |
728 | MLX5_PCI_STATUS_DISABLED, | |
729 | MLX5_PCI_STATUS_ENABLED, | |
730 | }; | |
731 | ||
d9aaed83 AK |
732 | enum mlx5_pagefault_type_flags { |
733 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
734 | MLX5_PFAULT_WRITE = 1 << 1, | |
735 | MLX5_PFAULT_RDMA = 1 << 2, | |
736 | }; | |
737 | ||
738 | /* Contains the details of a pagefault. */ | |
739 | struct mlx5_pagefault { | |
740 | u32 bytes_committed; | |
741 | u32 token; | |
742 | u8 event_subtype; | |
743 | u8 type; | |
744 | union { | |
745 | /* Initiator or send message responder pagefault details. */ | |
746 | struct { | |
747 | /* Received packet size, only valid for responders. */ | |
748 | u32 packet_size; | |
749 | /* | |
750 | * Number of resource holding WQE, depends on type. | |
751 | */ | |
752 | u32 wq_num; | |
753 | /* | |
754 | * WQE index. Refers to either the send queue or | |
755 | * receive queue, according to event_subtype. | |
756 | */ | |
757 | u16 wqe_index; | |
758 | } wqe; | |
759 | /* RDMA responder pagefault details */ | |
760 | struct { | |
761 | u32 r_key; | |
762 | /* | |
763 | * Received packet size, minimal size page fault | |
764 | * resolution required for forward progress. | |
765 | */ | |
766 | u32 packet_size; | |
767 | u32 rdma_op_len; | |
768 | u64 rdma_va; | |
769 | } rdma; | |
770 | }; | |
771 | ||
772 | struct mlx5_eq *eq; | |
773 | struct work_struct work; | |
774 | }; | |
775 | ||
b50d292b HHZ |
776 | struct mlx5_td { |
777 | struct list_head tirs_list; | |
778 | u32 tdn; | |
779 | }; | |
780 | ||
781 | struct mlx5e_resources { | |
b50d292b HHZ |
782 | u32 pdn; |
783 | struct mlx5_td td; | |
784 | struct mlx5_core_mkey mkey; | |
aff26157 | 785 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
786 | }; |
787 | ||
52ec462e IT |
788 | #define MLX5_MAX_RESERVED_GIDS 8 |
789 | ||
790 | struct mlx5_rsvd_gids { | |
791 | unsigned int start; | |
792 | unsigned int count; | |
793 | struct ida ida; | |
794 | }; | |
795 | ||
7c39afb3 FD |
796 | #define MAX_PIN_NUM 8 |
797 | struct mlx5_pps { | |
798 | u8 pin_caps[MAX_PIN_NUM]; | |
799 | struct work_struct out_work; | |
800 | u64 start[MAX_PIN_NUM]; | |
801 | u8 enabled; | |
802 | }; | |
803 | ||
804 | struct mlx5_clock { | |
805 | rwlock_t lock; | |
806 | struct cyclecounter cycles; | |
807 | struct timecounter tc; | |
808 | struct hwtstamp_config hwtstamp_config; | |
809 | u32 nominal_c_mult; | |
810 | unsigned long overflow_period; | |
811 | struct delayed_work overflow_work; | |
24d33d2c | 812 | struct mlx5_core_dev *mdev; |
7c39afb3 FD |
813 | struct ptp_clock *ptp; |
814 | struct ptp_clock_info ptp_info; | |
815 | struct mlx5_pps pps_info; | |
816 | }; | |
817 | ||
f53aaa31 | 818 | struct mlx5_fw_tracer; |
358aa5ce | 819 | struct mlx5_vxlan; |
f53aaa31 | 820 | |
e126ba97 EC |
821 | struct mlx5_core_dev { |
822 | struct pci_dev *pdev; | |
89d44f0a MD |
823 | /* sync pci state */ |
824 | struct mutex pci_status_mutex; | |
825 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
826 | u8 rev_id; |
827 | char board_id[MLX5_BOARD_ID_LEN]; | |
828 | struct mlx5_cmd cmd; | |
938fe83c | 829 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 830 | struct { |
701052c5 GP |
831 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
832 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
833 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
834 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 835 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 836 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
71862561 | 837 | } caps; |
e126ba97 EC |
838 | phys_addr_t iseg_base; |
839 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
840 | enum mlx5_device_state state; |
841 | /* sync interface state */ | |
842 | struct mutex intf_state_mutex; | |
5fc7197d | 843 | unsigned long intf_state; |
e126ba97 EC |
844 | void (*event) (struct mlx5_core_dev *dev, |
845 | enum mlx5_dev_event event, | |
4d2f9bbb | 846 | unsigned long param); |
e126ba97 EC |
847 | struct mlx5_priv priv; |
848 | struct mlx5_profile *profile; | |
849 | atomic_t num_qps; | |
f62b8bb8 | 850 | u32 issi; |
b50d292b | 851 | struct mlx5e_resources mlx5e_res; |
358aa5ce | 852 | struct mlx5_vxlan *vxlan; |
52ec462e IT |
853 | struct { |
854 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 855 | u32 roce_en; |
52ec462e | 856 | } roce; |
e29341fb IT |
857 | #ifdef CONFIG_MLX5_FPGA |
858 | struct mlx5_fpga_device *fpga; | |
859 | #endif | |
5a7b27eb MG |
860 | #ifdef CONFIG_RFS_ACCEL |
861 | struct cpu_rmap *rmap; | |
862 | #endif | |
7c39afb3 | 863 | struct mlx5_clock clock; |
24d33d2c FD |
864 | struct mlx5_ib_clock_info *clock_info; |
865 | struct page *clock_info_page; | |
f53aaa31 | 866 | struct mlx5_fw_tracer *tracer; |
e126ba97 EC |
867 | }; |
868 | ||
869 | struct mlx5_db { | |
870 | __be32 *db; | |
871 | union { | |
872 | struct mlx5_db_pgdir *pgdir; | |
873 | struct mlx5_ib_user_db_page *user_page; | |
874 | } u; | |
875 | dma_addr_t dma; | |
876 | int index; | |
877 | }; | |
878 | ||
e126ba97 EC |
879 | enum { |
880 | MLX5_COMP_EQ_SIZE = 1024, | |
881 | }; | |
882 | ||
adb0c954 SM |
883 | enum { |
884 | MLX5_PTYS_IB = 1 << 0, | |
885 | MLX5_PTYS_EN = 1 << 2, | |
886 | }; | |
887 | ||
e126ba97 EC |
888 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
889 | ||
73dd3a48 MHY |
890 | enum { |
891 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
892 | }; | |
893 | ||
e126ba97 | 894 | struct mlx5_cmd_work_ent { |
73dd3a48 | 895 | unsigned long state; |
e126ba97 EC |
896 | struct mlx5_cmd_msg *in; |
897 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
898 | void *uout; |
899 | int uout_size; | |
e126ba97 | 900 | mlx5_cmd_cbk_t callback; |
65ee6708 | 901 | struct delayed_work cb_timeout_work; |
e126ba97 | 902 | void *context; |
746b5583 | 903 | int idx; |
e126ba97 EC |
904 | struct completion done; |
905 | struct mlx5_cmd *cmd; | |
906 | struct work_struct work; | |
907 | struct mlx5_cmd_layout *lay; | |
908 | int ret; | |
909 | int page_queue; | |
910 | u8 status; | |
911 | u8 token; | |
14a70046 TG |
912 | u64 ts1; |
913 | u64 ts2; | |
746b5583 | 914 | u16 op; |
4525abea | 915 | bool polling; |
e126ba97 EC |
916 | }; |
917 | ||
918 | struct mlx5_pas { | |
919 | u64 pa; | |
920 | u8 log_sz; | |
921 | }; | |
922 | ||
707c4602 MD |
923 | enum phy_port_state { |
924 | MLX5_AAA_111 | |
925 | }; | |
926 | ||
927 | struct mlx5_hca_vport_context { | |
928 | u32 field_select; | |
929 | bool sm_virt_aware; | |
930 | bool has_smi; | |
931 | bool has_raw; | |
932 | enum port_state_policy policy; | |
933 | enum phy_port_state phys_state; | |
934 | enum ib_port_state vport_state; | |
935 | u8 port_physical_state; | |
936 | u64 sys_image_guid; | |
937 | u64 port_guid; | |
938 | u64 node_guid; | |
939 | u32 cap_mask1; | |
940 | u32 cap_mask1_perm; | |
941 | u32 cap_mask2; | |
942 | u32 cap_mask2_perm; | |
943 | u16 lid; | |
944 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
945 | u8 lmc; | |
946 | u8 subnet_timeout; | |
947 | u16 sm_lid; | |
948 | u8 sm_sl; | |
949 | u16 qkey_violation_counter; | |
950 | u16 pkey_violation_counter; | |
951 | bool grh_required; | |
952 | }; | |
953 | ||
388ca8be | 954 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 955 | { |
388ca8be | 956 | return buf->frags->buf + offset; |
e126ba97 EC |
957 | } |
958 | ||
e126ba97 EC |
959 | #define STRUCT_FIELD(header, field) \ |
960 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
961 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
962 | ||
e126ba97 EC |
963 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
964 | { | |
965 | return pci_get_drvdata(pdev); | |
966 | } | |
967 | ||
968 | extern struct dentry *mlx5_debugfs_root; | |
969 | ||
970 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
971 | { | |
972 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
973 | } | |
974 | ||
975 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
976 | { | |
977 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
978 | } | |
979 | ||
980 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
981 | { | |
982 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
983 | } | |
984 | ||
985 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
986 | { | |
987 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
988 | } | |
989 | ||
3bcdb17a SG |
990 | static inline u32 mlx5_base_mkey(const u32 key) |
991 | { | |
992 | return key & 0xffffff00u; | |
993 | } | |
994 | ||
d7037ad7 TT |
995 | static inline void mlx5_fill_fbc_offset(u8 log_stride, u8 log_sz, |
996 | u32 strides_offset, | |
997 | struct mlx5_frag_buf_ctrl *fbc) | |
388ca8be | 998 | { |
3a2f7033 TT |
999 | fbc->log_stride = log_stride; |
1000 | fbc->log_sz = log_sz; | |
388ca8be YC |
1001 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
1002 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
1003 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
1004 | fbc->strides_offset = strides_offset; |
1005 | } | |
1006 | ||
1007 | static inline void mlx5_fill_fbc(u8 log_stride, u8 log_sz, | |
1008 | struct mlx5_frag_buf_ctrl *fbc) | |
1009 | { | |
1010 | mlx5_fill_fbc_offset(log_stride, log_sz, 0, fbc); | |
388ca8be YC |
1011 | } |
1012 | ||
3a2f7033 TT |
1013 | static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc, |
1014 | void *cqc) | |
1015 | { | |
1016 | mlx5_fill_fbc(6 + MLX5_GET(cqc, cqc, cqe_sz), | |
1017 | MLX5_GET(cqc, cqc, log_cq_size), | |
1018 | fbc); | |
1019 | } | |
1020 | ||
388ca8be YC |
1021 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
1022 | u32 ix) | |
1023 | { | |
d7037ad7 TT |
1024 | unsigned int frag; |
1025 | ||
1026 | ix += fbc->strides_offset; | |
1027 | frag = ix >> fbc->log_frag_strides; | |
388ca8be YC |
1028 | |
1029 | return fbc->frag_buf.frags[frag].buf + | |
1030 | ((fbc->frag_sz_m1 & ix) << fbc->log_stride); | |
1031 | } | |
1032 | ||
e126ba97 EC |
1033 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
1034 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
1035 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
1036 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 1037 | |
e126ba97 EC |
1038 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
1039 | int out_size); | |
746b5583 EC |
1040 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
1041 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
1042 | void *context); | |
4525abea MD |
1043 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
1044 | void *out, int out_size); | |
c4f287c4 SM |
1045 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
1046 | ||
1047 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
1048 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
1049 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
1050 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
1051 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
1052 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
1053 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
05ac2c0b | 1054 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 1055 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
2a0165a0 | 1056 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
311c7c71 | 1057 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
388ca8be YC |
1058 | struct mlx5_frag_buf *buf, int node); |
1059 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, | |
1060 | int size, struct mlx5_frag_buf *buf); | |
1061 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
1062 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
1063 | struct mlx5_frag_buf *buf, int node); | |
1064 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
1065 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
1066 | gfp_t flags, int npages); | |
1067 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
1068 | struct mlx5_cmd_mailbox *head); | |
1069 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 1070 | struct mlx5_srq_attr *in); |
e126ba97 EC |
1071 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
1072 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 1073 | struct mlx5_srq_attr *out); |
e126ba97 EC |
1074 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
1075 | u16 lwm, int is_srq); | |
a606b0f6 MB |
1076 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
1077 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
1078 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
1079 | struct mlx5_core_mkey *mkey, | |
1080 | u32 *in, int inlen, | |
1081 | u32 *out, int outlen, | |
1082 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
1083 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
1084 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1085 | u32 *in, int inlen); |
a606b0f6 MB |
1086 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
1087 | struct mlx5_core_mkey *mkey); | |
1088 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1089 | u32 *out, int outlen); |
e126ba97 EC |
1090 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
1091 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 1092 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 1093 | u16 opmod, u8 port); |
e126ba97 EC |
1094 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
1095 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
1096 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
1097 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
1098 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 1099 | s32 npages); |
cd23b14b | 1100 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
1101 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
1102 | void mlx5_register_debugfs(void); | |
1103 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
1104 | |
1105 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 1106 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
5903325a | 1107 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e126ba97 EC |
1108 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
1109 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
0b6e26ce DT |
1110 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
1111 | unsigned int *irqn); | |
e126ba97 EC |
1112 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
1113 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
1114 | ||
1115 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
1116 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
1117 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
1118 | int size_in, void *data_out, int size_out, | |
1119 | u16 reg_num, int arg, int write); | |
adb0c954 | 1120 | |
e126ba97 | 1121 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
1122 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
1123 | int node); | |
e126ba97 EC |
1124 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
1125 | ||
e126ba97 EC |
1126 | const char *mlx5_command_str(int command); |
1127 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
1128 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
1129 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
1130 | int npsvs, u32 *sig_index); | |
1131 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1132 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1133 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1134 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1135 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1136 | u8 port_num, void *out, size_t sz); | |
d9aaed83 AK |
1137 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1138 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, | |
1139 | u32 wq_num, u8 type, int error); | |
1140 | #endif | |
e126ba97 | 1141 | |
1466cc5b YP |
1142 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1143 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
1144 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
1145 | struct mlx5_rate_limit *rl); | |
1146 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 1147 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
05d3ac97 BW |
1148 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
1149 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
1150 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1151 | bool map_wc, bool fast_path); | |
1152 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1153 | |
52ec462e IT |
1154 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1155 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1156 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1157 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1158 | |
e3297246 EC |
1159 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1160 | { | |
1161 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1162 | } | |
1163 | ||
e126ba97 EC |
1164 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1165 | { | |
1166 | return mkey >> 8; | |
1167 | } | |
1168 | ||
1169 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1170 | { | |
1171 | return mkey_idx << 8; | |
1172 | } | |
1173 | ||
746b5583 EC |
1174 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1175 | { | |
1176 | return mkey & 0xff; | |
1177 | } | |
1178 | ||
e126ba97 EC |
1179 | enum { |
1180 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1181 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1182 | }; |
1183 | ||
1184 | enum { | |
8b7ff7f3 | 1185 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1186 | MLX5_IMR_MTT_CACHE_ENTRY, |
1187 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1188 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1189 | }; |
1190 | ||
64613d94 SM |
1191 | enum { |
1192 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1193 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1194 | }; | |
1195 | ||
9603b61d JM |
1196 | struct mlx5_interface { |
1197 | void * (*add)(struct mlx5_core_dev *dev); | |
1198 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1199 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1200 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 1201 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1202 | enum mlx5_dev_event event, unsigned long param); |
d9aaed83 AK |
1203 | void (*pfault)(struct mlx5_core_dev *dev, |
1204 | void *context, | |
1205 | struct mlx5_pagefault *pfault); | |
64613d94 SM |
1206 | void * (*get_dev)(void *context); |
1207 | int protocol; | |
9603b61d JM |
1208 | struct list_head list; |
1209 | }; | |
1210 | ||
64613d94 | 1211 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
1212 | int mlx5_register_interface(struct mlx5_interface *intf); |
1213 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 1214 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1215 | |
3bc34f3b AH |
1216 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1217 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 1218 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1219 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1220 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1221 | u64 *values, | |
1222 | int num_counters, | |
1223 | size_t *offsets); | |
01187175 EC |
1224 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1225 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1226 | |
693dfd5a ES |
1227 | #ifndef CONFIG_MLX5_CORE_IPOIB |
1228 | static inline | |
1229 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1230 | struct ib_device *ibdev, | |
1231 | const char *name, | |
1232 | void (*setup)(struct net_device *)) | |
1233 | { | |
1234 | return ERR_PTR(-EOPNOTSUPP); | |
1235 | } | |
693dfd5a ES |
1236 | #else |
1237 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, | |
1238 | struct ib_device *ibdev, | |
1239 | const char *name, | |
1240 | void (*setup)(struct net_device *)); | |
693dfd5a ES |
1241 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
1242 | ||
e126ba97 EC |
1243 | struct mlx5_profile { |
1244 | u64 mask; | |
f241e749 | 1245 | u8 log_max_qp; |
e126ba97 EC |
1246 | struct { |
1247 | int size; | |
1248 | int limit; | |
1249 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1250 | }; | |
1251 | ||
fc50db98 EC |
1252 | enum { |
1253 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1254 | }; | |
1255 | ||
1256 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1257 | { | |
1258 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1259 | } | |
1260 | ||
57cbd893 MB |
1261 | #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) |
1262 | #define MLX5_VPORT_MANAGER(mdev) \ | |
1263 | (MLX5_CAP_GEN(mdev, vport_group_manager) && \ | |
1264 | (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ | |
1265 | mlx5_core_is_pf(mdev)) | |
1266 | ||
707c4602 MD |
1267 | static inline int mlx5_get_gid_table_len(u16 param) |
1268 | { | |
1269 | if (param > 4) { | |
1270 | pr_warn("gid table length is zero\n"); | |
1271 | return 0; | |
1272 | } | |
1273 | ||
1274 | return 8 * (1 << param); | |
1275 | } | |
1276 | ||
1466cc5b YP |
1277 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1278 | { | |
1279 | return !!(dev->priv.rl_table.max_size); | |
1280 | } | |
1281 | ||
32f69e4b DJ |
1282 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1283 | { | |
1284 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1285 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1286 | } | |
1287 | ||
1288 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1289 | { | |
1290 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1291 | } | |
1292 | ||
1293 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1294 | { | |
1295 | return mlx5_core_is_mp_slave(dev) || | |
1296 | mlx5_core_is_mp_master(dev); | |
1297 | } | |
1298 | ||
7fd8aefb DJ |
1299 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1300 | { | |
32f69e4b DJ |
1301 | if (!mlx5_core_mp_enabled(dev)) |
1302 | return 1; | |
1303 | ||
1304 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1305 | } |
1306 | ||
020446e0 EC |
1307 | enum { |
1308 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1309 | }; | |
1310 | ||
a435393a | 1311 | static inline const struct cpumask * |
6082d9c9 | 1312 | mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector) |
a435393a | 1313 | { |
e3ca3488 | 1314 | return dev->priv.irq_info[vector].mask; |
a435393a SG |
1315 | } |
1316 | ||
e126ba97 | 1317 | #endif /* MLX5_DRIVER_H */ |