net/mlx5: Query and cache PCAM, MCAM registers on initialization
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
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3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
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42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
43a335e0 44#include <linux/workqueue.h>
d9aaed83 45#include <linux/mempool.h>
94c6825e 46#include <linux/interrupt.h>
6ecde51d 47
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48#include <linux/mlx5/device.h>
49#include <linux/mlx5/doorbell.h>
af1ba291 50#include <linux/mlx5/srq.h>
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51
52enum {
53 MLX5_BOARD_ID_LEN = 64,
54 MLX5_MAX_NAME_LEN = 16,
55};
56
57enum {
58 /* one minute for the sake of bringup. Generally, commands must always
59 * complete and we may need to increase this timeout value
60 */
6b6c07bd 61 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
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EC
62 MLX5_CMD_WQ_MAX_NAME = 32,
63};
64
65enum {
66 CMD_OWNER_SW = 0x0,
67 CMD_OWNER_HW = 0x1,
68 CMD_STATUS_SUCCESS = 0,
69};
70
71enum mlx5_sqp_t {
72 MLX5_SQP_SMI = 0,
73 MLX5_SQP_GSI = 1,
74 MLX5_SQP_IEEE_1588 = 2,
75 MLX5_SQP_SNIFFER = 3,
76 MLX5_SQP_SYNC_UMR = 4,
77};
78
79enum {
80 MLX5_MAX_PORTS = 2,
81};
82
83enum {
84 MLX5_EQ_VEC_PAGES = 0,
85 MLX5_EQ_VEC_CMD = 1,
86 MLX5_EQ_VEC_ASYNC = 2,
d9aaed83 87 MLX5_EQ_VEC_PFAULT = 3,
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88 MLX5_EQ_VEC_COMP_BASE,
89};
90
91enum {
db058a18 92 MLX5_MAX_IRQ_NAME = 32
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93};
94
95enum {
96 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
97 MLX5_ATOMIC_MODE_CX = 2 << 16,
98 MLX5_ATOMIC_MODE_8B = 3 << 16,
99 MLX5_ATOMIC_MODE_16B = 4 << 16,
100 MLX5_ATOMIC_MODE_32B = 5 << 16,
101 MLX5_ATOMIC_MODE_64B = 6 << 16,
102 MLX5_ATOMIC_MODE_128B = 7 << 16,
103 MLX5_ATOMIC_MODE_256B = 8 << 16,
104};
105
e126ba97 106enum {
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SM
107 MLX5_REG_QETCR = 0x4005,
108 MLX5_REG_QTCT = 0x400a,
341c5ee2
HN
109 MLX5_REG_DCBX_PARAM = 0x4020,
110 MLX5_REG_DCBX_APP = 0x4021,
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111 MLX5_REG_PCAP = 0x5001,
112 MLX5_REG_PMTU = 0x5003,
113 MLX5_REG_PTYS = 0x5004,
114 MLX5_REG_PAOS = 0x5006,
3c2d18ef 115 MLX5_REG_PFCC = 0x5007,
efea389d 116 MLX5_REG_PPCNT = 0x5008,
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117 MLX5_REG_PMAOS = 0x5012,
118 MLX5_REG_PUDE = 0x5009,
119 MLX5_REG_PMPE = 0x5010,
120 MLX5_REG_PELC = 0x500e,
a124d13e 121 MLX5_REG_PVLC = 0x500f,
94cb1ebb 122 MLX5_REG_PCMR = 0x5041,
bb64143e 123 MLX5_REG_PMLP = 0x5002,
cfdcbcea 124 MLX5_REG_PCAM = 0x507f,
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125 MLX5_REG_NODE_DESC = 0x6001,
126 MLX5_REG_HOST_ENDIANNESS = 0x7004,
bb64143e 127 MLX5_REG_MCIA = 0x9014,
da54d24e 128 MLX5_REG_MLCR = 0x902b,
f9a1ef72
EE
129 MLX5_REG_MTPPS = 0x9053,
130 MLX5_REG_MTPPSE = 0x9054,
cfdcbcea 131 MLX5_REG_MCAM = 0x907f,
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132};
133
341c5ee2
HN
134enum mlx5_dcbx_oper_mode {
135 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
136 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
137};
138
da7525d2
EBE
139enum {
140 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
141 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
142};
143
e420f0c0
HE
144enum mlx5_page_fault_resume_flags {
145 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
146 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
147 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
148 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
149};
150
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EC
151enum dbg_rsc_type {
152 MLX5_DBG_RSC_QP,
153 MLX5_DBG_RSC_EQ,
154 MLX5_DBG_RSC_CQ,
155};
156
157struct mlx5_field_desc {
158 struct dentry *dent;
159 int i;
160};
161
162struct mlx5_rsc_debug {
163 struct mlx5_core_dev *dev;
164 void *object;
165 enum dbg_rsc_type type;
166 struct dentry *root;
167 struct mlx5_field_desc fields[0];
168};
169
170enum mlx5_dev_event {
171 MLX5_DEV_EVENT_SYS_ERROR,
172 MLX5_DEV_EVENT_PORT_UP,
173 MLX5_DEV_EVENT_PORT_DOWN,
174 MLX5_DEV_EVENT_PORT_INITIALIZED,
175 MLX5_DEV_EVENT_LID_CHANGE,
176 MLX5_DEV_EVENT_PKEY_CHANGE,
177 MLX5_DEV_EVENT_GUID_CHANGE,
178 MLX5_DEV_EVENT_CLIENT_REREG,
f9a1ef72 179 MLX5_DEV_EVENT_PPS,
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180};
181
4c916a79 182enum mlx5_port_status {
6fa1bcab
AS
183 MLX5_PORT_UP = 1,
184 MLX5_PORT_DOWN = 2,
4c916a79
RS
185};
186
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187enum mlx5_eq_type {
188 MLX5_EQ_TYPE_COMP,
189 MLX5_EQ_TYPE_ASYNC,
190#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
191 MLX5_EQ_TYPE_PF,
192#endif
193};
194
2f5ff264 195struct mlx5_bfreg_info {
b037c29a 196 u32 *sys_pages;
2f5ff264 197 int num_low_latency_bfregs;
e126ba97 198 unsigned int *count;
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199
200 /*
2f5ff264 201 * protect bfreg allocation data structs
e126ba97
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202 */
203 struct mutex lock;
78c0f98c 204 u32 ver;
b037c29a
EC
205 bool lib_uar_4k;
206 u32 num_sys_pages;
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207};
208
209struct mlx5_cmd_first {
210 __be32 data[4];
211};
212
213struct mlx5_cmd_msg {
214 struct list_head list;
0ac3ea70 215 struct cmd_msg_cache *parent;
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216 u32 len;
217 struct mlx5_cmd_first first;
218 struct mlx5_cmd_mailbox *next;
219};
220
221struct mlx5_cmd_debug {
222 struct dentry *dbg_root;
223 struct dentry *dbg_in;
224 struct dentry *dbg_out;
225 struct dentry *dbg_outlen;
226 struct dentry *dbg_status;
227 struct dentry *dbg_run;
228 void *in_msg;
229 void *out_msg;
230 u8 status;
231 u16 inlen;
232 u16 outlen;
233};
234
0ac3ea70 235struct cmd_msg_cache {
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236 /* protect block chain allocations
237 */
238 spinlock_t lock;
239 struct list_head head;
0ac3ea70
MHY
240 unsigned int max_inbox_size;
241 unsigned int num_ent;
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242};
243
0ac3ea70
MHY
244enum {
245 MLX5_NUM_COMMAND_CACHES = 5,
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246};
247
248struct mlx5_cmd_stats {
249 u64 sum;
250 u64 n;
251 struct dentry *root;
252 struct dentry *avg;
253 struct dentry *count;
254 /* protect command average calculations */
255 spinlock_t lock;
256};
257
258struct mlx5_cmd {
64599cca
EC
259 void *cmd_alloc_buf;
260 dma_addr_t alloc_dma;
261 int alloc_size;
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262 void *cmd_buf;
263 dma_addr_t dma;
264 u16 cmdif_rev;
265 u8 log_sz;
266 u8 log_stride;
267 int max_reg_cmds;
268 int events;
269 u32 __iomem *vector;
270
271 /* protect command queue allocations
272 */
273 spinlock_t alloc_lock;
274
275 /* protect token allocations
276 */
277 spinlock_t token_lock;
278 u8 token;
279 unsigned long bitmask;
280 char wq_name[MLX5_CMD_WQ_MAX_NAME];
281 struct workqueue_struct *wq;
282 struct semaphore sem;
283 struct semaphore pages_sem;
284 int mode;
285 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
286 struct pci_pool *pool;
287 struct mlx5_cmd_debug dbg;
0ac3ea70 288 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
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289 int checksum_disabled;
290 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
291};
292
293struct mlx5_port_caps {
294 int gid_table_len;
295 int pkey_table_len;
938fe83c 296 u8 ext_port_cap;
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EC
297};
298
299struct mlx5_cmd_mailbox {
300 void *buf;
301 dma_addr_t dma;
302 struct mlx5_cmd_mailbox *next;
303};
304
305struct mlx5_buf_list {
306 void *buf;
307 dma_addr_t map;
308};
309
310struct mlx5_buf {
311 struct mlx5_buf_list direct;
e126ba97 312 int npages;
e126ba97 313 int size;
f241e749 314 u8 page_shift;
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315};
316
1c1b5228
TT
317struct mlx5_frag_buf {
318 struct mlx5_buf_list *frags;
319 int npages;
320 int size;
321 u8 page_shift;
322};
323
94c6825e
MB
324struct mlx5_eq_tasklet {
325 struct list_head list;
326 struct list_head process_list;
327 struct tasklet_struct task;
328 /* lock on completion tasklet list */
329 spinlock_t lock;
330};
331
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332struct mlx5_eq_pagefault {
333 struct work_struct work;
334 /* Pagefaults lock */
335 spinlock_t lock;
336 struct workqueue_struct *wq;
337 mempool_t *pool;
338};
339
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EC
340struct mlx5_eq {
341 struct mlx5_core_dev *dev;
342 __be32 __iomem *doorbell;
343 u32 cons_index;
344 struct mlx5_buf buf;
345 int size;
0b6e26ce 346 unsigned int irqn;
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347 u8 eqn;
348 int nent;
349 u64 mask;
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350 struct list_head list;
351 int index;
352 struct mlx5_rsc_debug *dbg;
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353 enum mlx5_eq_type type;
354 union {
355 struct mlx5_eq_tasklet tasklet_ctx;
356#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
357 struct mlx5_eq_pagefault pf_ctx;
358#endif
359 };
e126ba97
EC
360};
361
3121e3c4
SG
362struct mlx5_core_psv {
363 u32 psv_idx;
364 struct psv_layout {
365 u32 pd;
366 u16 syndrome;
367 u16 reserved;
368 u16 bg;
369 u16 app_tag;
370 u32 ref_tag;
371 } psv;
372};
373
374struct mlx5_core_sig_ctx {
375 struct mlx5_core_psv psv_memory;
376 struct mlx5_core_psv psv_wire;
d5436ba0
SG
377 struct ib_sig_err err_item;
378 bool sig_status_checked;
379 bool sig_err_exists;
380 u32 sigerr_count;
3121e3c4 381};
e126ba97 382
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AK
383enum {
384 MLX5_MKEY_MR = 1,
385 MLX5_MKEY_MW,
386};
387
a606b0f6 388struct mlx5_core_mkey {
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389 u64 iova;
390 u64 size;
391 u32 key;
392 u32 pd;
aa8e08d2 393 u32 type;
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394};
395
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396#define MLX5_24BIT_MASK ((1 << 24) - 1)
397
5903325a 398enum mlx5_res_type {
e2013b21 399 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
400 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
401 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
402 MLX5_RES_SRQ = 3,
403 MLX5_RES_XSRQ = 4,
5903325a
EC
404};
405
406struct mlx5_core_rsc_common {
407 enum mlx5_res_type res;
408 atomic_t refcount;
409 struct completion free;
410};
411
e126ba97 412struct mlx5_core_srq {
01949d01 413 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC
414 u32 srqn;
415 int max;
416 int max_gs;
417 int max_avail_gather;
418 int wqe_shift;
419 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
420
421 atomic_t refcount;
422 struct completion free;
423};
424
425struct mlx5_eq_table {
426 void __iomem *update_ci;
427 void __iomem *update_arm_ci;
233d05d2 428 struct list_head comp_eqs_list;
e126ba97
EC
429 struct mlx5_eq pages_eq;
430 struct mlx5_eq async_eq;
431 struct mlx5_eq cmd_eq;
d9aaed83
AK
432#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
433 struct mlx5_eq pfault_eq;
434#endif
e126ba97
EC
435 int num_comp_vectors;
436 /* protect EQs list
437 */
438 spinlock_t lock;
439};
440
a6d51b68 441struct mlx5_uars_page {
e126ba97 442 void __iomem *map;
a6d51b68
EC
443 bool wc;
444 u32 index;
445 struct list_head list;
446 unsigned int bfregs;
447 unsigned long *reg_bitmap; /* for non fast path bf regs */
448 unsigned long *fp_bitmap;
449 unsigned int reg_avail;
450 unsigned int fp_avail;
451 struct kref ref_count;
452 struct mlx5_core_dev *mdev;
e126ba97
EC
453};
454
a6d51b68
EC
455struct mlx5_bfreg_head {
456 /* protect blue flame registers allocations */
457 struct mutex lock;
458 struct list_head list;
459};
460
461struct mlx5_bfreg_data {
462 struct mlx5_bfreg_head reg_head;
463 struct mlx5_bfreg_head wc_head;
464};
465
466struct mlx5_sq_bfreg {
467 void __iomem *map;
468 struct mlx5_uars_page *up;
469 bool wc;
470 u32 index;
471 unsigned int offset;
472};
e126ba97
EC
473
474struct mlx5_core_health {
475 struct health_buffer __iomem *health;
476 __be32 __iomem *health_counter;
477 struct timer_list timer;
e126ba97
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478 u32 prev;
479 int miss_counter;
fd76ee4d 480 bool sick;
05ac2c0b
MHY
481 /* wq spinlock to synchronize draining */
482 spinlock_t wq_lock;
ac6ea6e8 483 struct workqueue_struct *wq;
05ac2c0b 484 unsigned long flags;
ac6ea6e8 485 struct work_struct work;
04c0c1ab 486 struct delayed_work recover_work;
e126ba97
EC
487};
488
489struct mlx5_cq_table {
490 /* protect radix tree
491 */
492 spinlock_t lock;
493 struct radix_tree_root tree;
494};
495
496struct mlx5_qp_table {
497 /* protect radix tree
498 */
499 spinlock_t lock;
500 struct radix_tree_root tree;
501};
502
503struct mlx5_srq_table {
504 /* protect radix tree
505 */
506 spinlock_t lock;
507 struct radix_tree_root tree;
508};
509
a606b0f6 510struct mlx5_mkey_table {
3bcdb17a
SG
511 /* protect radix tree
512 */
513 rwlock_t lock;
514 struct radix_tree_root tree;
515};
516
fc50db98
EC
517struct mlx5_vf_context {
518 int enabled;
519};
520
521struct mlx5_core_sriov {
522 struct mlx5_vf_context *vfs_ctx;
523 int num_vfs;
524 int enabled_vfs;
525};
526
db058a18
SM
527struct mlx5_irq_info {
528 cpumask_var_t mask;
529 char name[MLX5_MAX_IRQ_NAME];
530};
531
43a335e0 532struct mlx5_fc_stats {
29cc6679 533 struct rb_root counters;
43a335e0
AV
534 struct list_head addlist;
535 /* protect addlist add/splice operations */
536 spinlock_t addlist_lock;
537
538 struct workqueue_struct *wq;
539 struct delayed_work work;
540 unsigned long next_query;
541};
542
073bb189 543struct mlx5_eswitch;
7907f23a 544struct mlx5_lag;
d9aaed83 545struct mlx5_pagefault;
073bb189 546
1466cc5b
YP
547struct mlx5_rl_entry {
548 u32 rate;
549 u16 index;
550 u16 refcount;
551};
552
553struct mlx5_rl_table {
554 /* protect rate limit table */
555 struct mutex rl_lock;
556 u16 max_size;
557 u32 max_rate;
558 u32 min_rate;
559 struct mlx5_rl_entry *rl_entry;
560};
561
d4eb4cd7
HN
562enum port_module_event_status_type {
563 MLX5_MODULE_STATUS_PLUGGED = 0x1,
564 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
565 MLX5_MODULE_STATUS_ERROR = 0x3,
566 MLX5_MODULE_STATUS_NUM = 0x3,
567};
568
569enum port_module_event_error_type {
570 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
571 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
572 MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
573 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
574 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
575 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
576 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
577 MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
578 MLX5_MODULE_EVENT_ERROR_UNKNOWN,
579 MLX5_MODULE_EVENT_ERROR_NUM,
580};
581
582struct mlx5_port_module_event_stats {
583 u64 status_counters[MLX5_MODULE_STATUS_NUM];
584 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
585};
586
e126ba97
EC
587struct mlx5_priv {
588 char name[MLX5_MAX_NAME_LEN];
589 struct mlx5_eq_table eq_table;
db058a18
SM
590 struct msix_entry *msix_arr;
591 struct mlx5_irq_info *irq_info;
e126ba97
EC
592
593 /* pages stuff */
594 struct workqueue_struct *pg_wq;
595 struct rb_root page_root;
596 int fw_pages;
6aec21f6 597 atomic_t reg_pages;
bf0bf77f 598 struct list_head free_list;
fc50db98 599 int vfs_pages;
e126ba97
EC
600
601 struct mlx5_core_health health;
602
603 struct mlx5_srq_table srq_table;
604
605 /* start: qp staff */
606 struct mlx5_qp_table qp_table;
607 struct dentry *qp_debugfs;
608 struct dentry *eq_debugfs;
609 struct dentry *cq_debugfs;
610 struct dentry *cmdif_debugfs;
611 /* end: qp staff */
612
613 /* start: cq staff */
614 struct mlx5_cq_table cq_table;
615 /* end: cq staff */
616
a606b0f6
MB
617 /* start: mkey staff */
618 struct mlx5_mkey_table mkey_table;
619 /* end: mkey staff */
3bcdb17a 620
e126ba97 621 /* start: alloc staff */
311c7c71
SM
622 /* protect buffer alocation according to numa node */
623 struct mutex alloc_mutex;
624 int numa_node;
625
e126ba97
EC
626 struct mutex pgdir_mutex;
627 struct list_head pgdir_list;
628 /* end: alloc staff */
629 struct dentry *dbg_root;
630
631 /* protect mkey key part */
632 spinlock_t mkey_lock;
633 u8 mkey_key;
9603b61d
JM
634
635 struct list_head dev_list;
636 struct list_head ctx_list;
637 spinlock_t ctx_lock;
073bb189 638
fba53f7b 639 struct mlx5_flow_steering *steering;
073bb189 640 struct mlx5_eswitch *eswitch;
fc50db98 641 struct mlx5_core_sriov sriov;
7907f23a 642 struct mlx5_lag *lag;
fc50db98 643 unsigned long pci_dev_data;
43a335e0 644 struct mlx5_fc_stats fc_stats;
1466cc5b 645 struct mlx5_rl_table rl_table;
d4eb4cd7
HN
646
647 struct mlx5_port_module_event_stats pme_stats;
d9aaed83
AK
648
649#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
650 void (*pfault)(struct mlx5_core_dev *dev,
651 void *context,
652 struct mlx5_pagefault *pfault);
653 void *pfault_ctx;
654 struct srcu_struct pfault_srcu;
655#endif
a6d51b68 656 struct mlx5_bfreg_data bfregs;
01187175 657 struct mlx5_uars_page *uar;
e126ba97
EC
658};
659
89d44f0a
MD
660enum mlx5_device_state {
661 MLX5_DEVICE_STATE_UP,
662 MLX5_DEVICE_STATE_INTERNAL_ERROR,
663};
664
665enum mlx5_interface_state {
5fc7197d
MD
666 MLX5_INTERFACE_STATE_DOWN = BIT(0),
667 MLX5_INTERFACE_STATE_UP = BIT(1),
668 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
89d44f0a
MD
669};
670
671enum mlx5_pci_status {
672 MLX5_PCI_STATUS_DISABLED,
673 MLX5_PCI_STATUS_ENABLED,
674};
675
d9aaed83
AK
676enum mlx5_pagefault_type_flags {
677 MLX5_PFAULT_REQUESTOR = 1 << 0,
678 MLX5_PFAULT_WRITE = 1 << 1,
679 MLX5_PFAULT_RDMA = 1 << 2,
680};
681
682/* Contains the details of a pagefault. */
683struct mlx5_pagefault {
684 u32 bytes_committed;
685 u32 token;
686 u8 event_subtype;
687 u8 type;
688 union {
689 /* Initiator or send message responder pagefault details. */
690 struct {
691 /* Received packet size, only valid for responders. */
692 u32 packet_size;
693 /*
694 * Number of resource holding WQE, depends on type.
695 */
696 u32 wq_num;
697 /*
698 * WQE index. Refers to either the send queue or
699 * receive queue, according to event_subtype.
700 */
701 u16 wqe_index;
702 } wqe;
703 /* RDMA responder pagefault details */
704 struct {
705 u32 r_key;
706 /*
707 * Received packet size, minimal size page fault
708 * resolution required for forward progress.
709 */
710 u32 packet_size;
711 u32 rdma_op_len;
712 u64 rdma_va;
713 } rdma;
714 };
715
716 struct mlx5_eq *eq;
717 struct work_struct work;
718};
719
b50d292b
HHZ
720struct mlx5_td {
721 struct list_head tirs_list;
722 u32 tdn;
723};
724
725struct mlx5e_resources {
b50d292b
HHZ
726 u32 pdn;
727 struct mlx5_td td;
728 struct mlx5_core_mkey mkey;
729};
730
e126ba97
EC
731struct mlx5_core_dev {
732 struct pci_dev *pdev;
89d44f0a
MD
733 /* sync pci state */
734 struct mutex pci_status_mutex;
735 enum mlx5_pci_status pci_status;
e126ba97
EC
736 u8 rev_id;
737 char board_id[MLX5_BOARD_ID_LEN];
738 struct mlx5_cmd cmd;
938fe83c
SM
739 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
740 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
741 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
71862561
GP
742 struct {
743 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
744 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
745 } caps;
e126ba97
EC
746 phys_addr_t iseg_base;
747 struct mlx5_init_seg __iomem *iseg;
89d44f0a
MD
748 enum mlx5_device_state state;
749 /* sync interface state */
750 struct mutex intf_state_mutex;
5fc7197d 751 unsigned long intf_state;
e126ba97
EC
752 void (*event) (struct mlx5_core_dev *dev,
753 enum mlx5_dev_event event,
4d2f9bbb 754 unsigned long param);
e126ba97
EC
755 struct mlx5_priv priv;
756 struct mlx5_profile *profile;
757 atomic_t num_qps;
f62b8bb8 758 u32 issi;
b50d292b 759 struct mlx5e_resources mlx5e_res;
5a7b27eb
MG
760#ifdef CONFIG_RFS_ACCEL
761 struct cpu_rmap *rmap;
762#endif
e126ba97
EC
763};
764
765struct mlx5_db {
766 __be32 *db;
767 union {
768 struct mlx5_db_pgdir *pgdir;
769 struct mlx5_ib_user_db_page *user_page;
770 } u;
771 dma_addr_t dma;
772 int index;
773};
774
e126ba97
EC
775enum {
776 MLX5_COMP_EQ_SIZE = 1024,
777};
778
adb0c954
SM
779enum {
780 MLX5_PTYS_IB = 1 << 0,
781 MLX5_PTYS_EN = 1 << 2,
782};
783
e126ba97
EC
784typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
785
786struct mlx5_cmd_work_ent {
787 struct mlx5_cmd_msg *in;
788 struct mlx5_cmd_msg *out;
746b5583
EC
789 void *uout;
790 int uout_size;
e126ba97 791 mlx5_cmd_cbk_t callback;
65ee6708 792 struct delayed_work cb_timeout_work;
e126ba97 793 void *context;
746b5583 794 int idx;
e126ba97
EC
795 struct completion done;
796 struct mlx5_cmd *cmd;
797 struct work_struct work;
798 struct mlx5_cmd_layout *lay;
799 int ret;
800 int page_queue;
801 u8 status;
802 u8 token;
14a70046
TG
803 u64 ts1;
804 u64 ts2;
746b5583 805 u16 op;
e126ba97
EC
806};
807
808struct mlx5_pas {
809 u64 pa;
810 u8 log_sz;
811};
812
707c4602 813enum port_state_policy {
eff901d3
EC
814 MLX5_POLICY_DOWN = 0,
815 MLX5_POLICY_UP = 1,
816 MLX5_POLICY_FOLLOW = 2,
817 MLX5_POLICY_INVALID = 0xffffffff
707c4602
MD
818};
819
820enum phy_port_state {
821 MLX5_AAA_111
822};
823
824struct mlx5_hca_vport_context {
825 u32 field_select;
826 bool sm_virt_aware;
827 bool has_smi;
828 bool has_raw;
829 enum port_state_policy policy;
830 enum phy_port_state phys_state;
831 enum ib_port_state vport_state;
832 u8 port_physical_state;
833 u64 sys_image_guid;
834 u64 port_guid;
835 u64 node_guid;
836 u32 cap_mask1;
837 u32 cap_mask1_perm;
838 u32 cap_mask2;
839 u32 cap_mask2_perm;
840 u16 lid;
841 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
842 u8 lmc;
843 u8 subnet_timeout;
844 u16 sm_lid;
845 u8 sm_sl;
846 u16 qkey_violation_counter;
847 u16 pkey_violation_counter;
848 bool grh_required;
849};
850
e126ba97
EC
851static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
852{
e126ba97 853 return buf->direct.buf + offset;
e126ba97
EC
854}
855
856extern struct workqueue_struct *mlx5_core_wq;
857
858#define STRUCT_FIELD(header, field) \
859 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
860 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
861
e126ba97
EC
862static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
863{
864 return pci_get_drvdata(pdev);
865}
866
867extern struct dentry *mlx5_debugfs_root;
868
869static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
870{
871 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
872}
873
874static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
875{
876 return ioread32be(&dev->iseg->fw_rev) >> 16;
877}
878
879static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
880{
881 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
882}
883
884static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
885{
886 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
887}
888
889static inline void *mlx5_vzalloc(unsigned long size)
890{
891 void *rtn;
892
893 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
894 if (!rtn)
895 rtn = vzalloc(size);
896 return rtn;
897}
898
3bcdb17a
SG
899static inline u32 mlx5_base_mkey(const u32 key)
900{
901 return key & 0xffffff00u;
902}
903
e126ba97
EC
904int mlx5_cmd_init(struct mlx5_core_dev *dev);
905void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
906void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
907void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
c4f287c4 908
e126ba97
EC
909int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
910 int out_size);
746b5583
EC
911int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
912 void *out, int out_size, mlx5_cmd_cbk_t callback,
913 void *context);
c4f287c4
SM
914void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
915
916int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
e126ba97
EC
917int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
918int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
ac6ea6e8
EC
919void mlx5_health_cleanup(struct mlx5_core_dev *dev);
920int mlx5_health_init(struct mlx5_core_dev *dev);
e126ba97
EC
921void mlx5_start_health_poll(struct mlx5_core_dev *dev);
922void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
05ac2c0b 923void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
311c7c71
SM
924int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
925 struct mlx5_buf *buf, int node);
64ffaa21 926int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97 927void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
1c1b5228
TT
928int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
929 struct mlx5_frag_buf *buf, int node);
930void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
e126ba97
EC
931struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
932 gfp_t flags, int npages);
933void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
934 struct mlx5_cmd_mailbox *head);
935int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
af1ba291 936 struct mlx5_srq_attr *in);
e126ba97
EC
937int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
938int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
af1ba291 939 struct mlx5_srq_attr *out);
e126ba97
EC
940int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
941 u16 lwm, int is_srq);
a606b0f6
MB
942void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
943void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
ec22eb53
SM
944int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
945 struct mlx5_core_mkey *mkey,
946 u32 *in, int inlen,
947 u32 *out, int outlen,
948 mlx5_cmd_cbk_t callback, void *context);
a606b0f6
MB
949int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
950 struct mlx5_core_mkey *mkey,
ec22eb53 951 u32 *in, int inlen);
a606b0f6
MB
952int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
953 struct mlx5_core_mkey *mkey);
954int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
ec22eb53 955 u32 *out, int outlen);
a606b0f6 956int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
e126ba97
EC
957 u32 *mkey);
958int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
959int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
a97e2d86 960int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
f241e749 961 u16 opmod, u8 port);
e126ba97
EC
962void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
963void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
964int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
965void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
966void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 967 s32 npages);
cd23b14b 968int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC
969int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
970void mlx5_register_debugfs(void);
971void mlx5_unregister_debugfs(void);
972int mlx5_eq_init(struct mlx5_core_dev *dev);
973void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
974void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1c1b5228 975void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
e126ba97 976void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 977void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e126ba97
EC
978void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
979struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
020446e0 980void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
e126ba97
EC
981void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
982int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
d9aaed83 983 int nent, u64 mask, const char *name,
01187175 984 enum mlx5_eq_type type);
e126ba97
EC
985int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
986int mlx5_start_eqs(struct mlx5_core_dev *dev);
987int mlx5_stop_eqs(struct mlx5_core_dev *dev);
0b6e26ce
DT
988int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
989 unsigned int *irqn);
e126ba97
EC
990int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
991int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
992
993int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
994void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
995int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
996 int size_in, void *data_out, int size_out,
997 u16 reg_num, int arg, int write);
adb0c954 998
e126ba97
EC
999int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1000void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1001int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
73b626c1 1002 u32 *out, int outlen);
e126ba97
EC
1003int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1004void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1005int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1006void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1007int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
311c7c71
SM
1008int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1009 int node);
e126ba97
EC
1010void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1011
e126ba97
EC
1012const char *mlx5_command_str(int command);
1013int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1014void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG
1015int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1016 int npsvs, u32 *sig_index);
1017int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 1018void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE
1019int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1020 struct mlx5_odp_caps *odp_caps);
1c64bf6f
MY
1021int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1022 u8 port_num, void *out, size_t sz);
d9aaed83
AK
1023#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1024int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1025 u32 wq_num, u8 type, int error);
1026#endif
e126ba97 1027
1466cc5b
YP
1028int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1029void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1030int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1031void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1032bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
a6d51b68
EC
1033int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1034 bool map_wc, bool fast_path);
1035void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1466cc5b 1036
e3297246
EC
1037static inline int fw_initializing(struct mlx5_core_dev *dev)
1038{
1039 return ioread32be(&dev->iseg->initializing) >> 31;
1040}
1041
e126ba97
EC
1042static inline u32 mlx5_mkey_to_idx(u32 mkey)
1043{
1044 return mkey >> 8;
1045}
1046
1047static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1048{
1049 return mkey_idx << 8;
1050}
1051
746b5583
EC
1052static inline u8 mlx5_mkey_variant(u32 mkey)
1053{
1054 return mkey & 0xff;
1055}
1056
e126ba97
EC
1057enum {
1058 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 1059 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC
1060};
1061
1062enum {
7d0cc6ed 1063 MAX_MR_CACHE_ENTRIES = 21,
e126ba97
EC
1064};
1065
64613d94
SM
1066enum {
1067 MLX5_INTERFACE_PROTOCOL_IB = 0,
1068 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1069};
1070
9603b61d
JM
1071struct mlx5_interface {
1072 void * (*add)(struct mlx5_core_dev *dev);
1073 void (*remove)(struct mlx5_core_dev *dev, void *context);
737a234b
MHY
1074 int (*attach)(struct mlx5_core_dev *dev, void *context);
1075 void (*detach)(struct mlx5_core_dev *dev, void *context);
9603b61d 1076 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1077 enum mlx5_dev_event event, unsigned long param);
d9aaed83
AK
1078 void (*pfault)(struct mlx5_core_dev *dev,
1079 void *context,
1080 struct mlx5_pagefault *pfault);
64613d94
SM
1081 void * (*get_dev)(void *context);
1082 int protocol;
9603b61d
JM
1083 struct list_head list;
1084};
1085
64613d94 1086void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM
1087int mlx5_register_interface(struct mlx5_interface *intf);
1088void mlx5_unregister_interface(struct mlx5_interface *intf);
211e6c80 1089int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
9603b61d 1090
3bc34f3b
AH
1091int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1092int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
7907f23a 1093bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
6a32047a 1094struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
01187175
EC
1095struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1096void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
7907f23a 1097
e126ba97
EC
1098struct mlx5_profile {
1099 u64 mask;
f241e749 1100 u8 log_max_qp;
e126ba97
EC
1101 struct {
1102 int size;
1103 int limit;
1104 } mr_cache[MAX_MR_CACHE_ENTRIES];
1105};
1106
fc50db98
EC
1107enum {
1108 MLX5_PCI_DEV_IS_VF = 1 << 0,
1109};
1110
1111static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1112{
1113 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1114}
1115
707c4602
MD
1116static inline int mlx5_get_gid_table_len(u16 param)
1117{
1118 if (param > 4) {
1119 pr_warn("gid table length is zero\n");
1120 return 0;
1121 }
1122
1123 return 8 * (1 << param);
1124}
1125
1466cc5b
YP
1126static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1127{
1128 return !!(dev->priv.rl_table.max_size);
1129}
1130
020446e0
EC
1131enum {
1132 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1133};
1134
e126ba97 1135#endif /* MLX5_DRIVER_H */