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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 | 43 | #include <linux/vmalloc.h> |
792c4e9d | 44 | #include <linux/xarray.h> |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
20902be4 | 49 | #include <linux/notifier.h> |
94f3e14e | 50 | #include <linux/refcount.h> |
a925b5e3 | 51 | #include <linux/auxiliary_bus.h> |
6ecde51d | 52 | |
e126ba97 EC |
53 | #include <linux/mlx5/device.h> |
54 | #include <linux/mlx5/doorbell.h> | |
41069256 | 55 | #include <linux/mlx5/eq.h> |
7c39afb3 FD |
56 | #include <linux/timecounter.h> |
57 | #include <linux/ptp_clock_kernel.h> | |
1e34f3ef | 58 | #include <net/devlink.h> |
e126ba97 | 59 | |
17a7612b LR |
60 | #define MLX5_ADEV_NAME "mlx5_core" |
61 | ||
e126ba97 EC |
62 | enum { |
63 | MLX5_BOARD_ID_LEN = 64, | |
e126ba97 EC |
64 | }; |
65 | ||
66 | enum { | |
67 | /* one minute for the sake of bringup. Generally, commands must always | |
68 | * complete and we may need to increase this timeout value | |
69 | */ | |
6b6c07bd | 70 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
71 | MLX5_CMD_WQ_MAX_NAME = 32, |
72 | }; | |
73 | ||
74 | enum { | |
75 | CMD_OWNER_SW = 0x0, | |
76 | CMD_OWNER_HW = 0x1, | |
77 | CMD_STATUS_SUCCESS = 0, | |
78 | }; | |
79 | ||
80 | enum mlx5_sqp_t { | |
81 | MLX5_SQP_SMI = 0, | |
82 | MLX5_SQP_GSI = 1, | |
83 | MLX5_SQP_IEEE_1588 = 2, | |
84 | MLX5_SQP_SNIFFER = 3, | |
85 | MLX5_SQP_SYNC_UMR = 4, | |
86 | }; | |
87 | ||
88 | enum { | |
89 | MLX5_MAX_PORTS = 2, | |
90 | }; | |
91 | ||
e126ba97 | 92 | enum { |
a60109dc YC |
93 | MLX5_ATOMIC_MODE_OFFSET = 16, |
94 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
95 | MLX5_ATOMIC_MODE_CX = 2, | |
96 | MLX5_ATOMIC_MODE_8B = 3, | |
97 | MLX5_ATOMIC_MODE_16B = 4, | |
98 | MLX5_ATOMIC_MODE_32B = 5, | |
99 | MLX5_ATOMIC_MODE_64B = 6, | |
100 | MLX5_ATOMIC_MODE_128B = 7, | |
101 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
102 | }; |
103 | ||
e126ba97 | 104 | enum { |
415a64aa | 105 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
106 | MLX5_REG_QETCR = 0x4005, |
107 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 108 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 109 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
110 | MLX5_REG_DCBX_PARAM = 0x4020, |
111 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
112 | MLX5_REG_FPGA_CAP = 0x4022, |
113 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 114 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
0b9055a1 | 115 | MLX5_REG_CORE_DUMP = 0x402e, |
e126ba97 EC |
116 | MLX5_REG_PCAP = 0x5001, |
117 | MLX5_REG_PMTU = 0x5003, | |
118 | MLX5_REG_PTYS = 0x5004, | |
119 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 120 | MLX5_REG_PFCC = 0x5007, |
efea389d | 121 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
122 | MLX5_REG_PPTB = 0x500b, |
123 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
124 | MLX5_REG_PMAOS = 0x5012, |
125 | MLX5_REG_PUDE = 0x5009, | |
126 | MLX5_REG_PMPE = 0x5010, | |
127 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 128 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 129 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 130 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 131 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 132 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
133 | MLX5_REG_NODE_DESC = 0x6001, |
134 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 135 | MLX5_REG_MCIA = 0x9014, |
06939536 | 136 | MLX5_REG_MFRL = 0x9028, |
da54d24e | 137 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
138 | MLX5_REG_MTRC_CAP = 0x9040, |
139 | MLX5_REG_MTRC_CONF = 0x9041, | |
140 | MLX5_REG_MTRC_STDB = 0x9042, | |
141 | MLX5_REG_MTRC_CTRL = 0x9043, | |
4039049b | 142 | MLX5_REG_MPEIN = 0x9050, |
8ed1a630 | 143 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
144 | MLX5_REG_MTPPS = 0x9053, |
145 | MLX5_REG_MTPPSE = 0x9054, | |
ae02d415 | 146 | MLX5_REG_MTUTC = 0x9055, |
5e022dd3 | 147 | MLX5_REG_MPEGC = 0x9056, |
a82e0b5b | 148 | MLX5_REG_MCQS = 0x9060, |
47176289 OG |
149 | MLX5_REG_MCQI = 0x9061, |
150 | MLX5_REG_MCC = 0x9062, | |
151 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 152 | MLX5_REG_MCAM = 0x907f, |
bab58ba1 | 153 | MLX5_REG_MIRC = 0x9162, |
88b3d5c9 | 154 | MLX5_REG_SBCAM = 0xB01F, |
609b8272 | 155 | MLX5_REG_RESOURCE_DUMP = 0xC000, |
e126ba97 EC |
156 | }; |
157 | ||
415a64aa HN |
158 | enum mlx5_qpts_trust_state { |
159 | MLX5_QPTS_TRUST_PCP = 1, | |
160 | MLX5_QPTS_TRUST_DSCP = 2, | |
161 | }; | |
162 | ||
341c5ee2 HN |
163 | enum mlx5_dcbx_oper_mode { |
164 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
165 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
166 | }; | |
167 | ||
da7525d2 EBE |
168 | enum { |
169 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
170 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
171 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
172 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
173 | }; |
174 | ||
e420f0c0 HE |
175 | enum mlx5_page_fault_resume_flags { |
176 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
177 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
178 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
179 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
180 | }; | |
181 | ||
e126ba97 EC |
182 | enum dbg_rsc_type { |
183 | MLX5_DBG_RSC_QP, | |
184 | MLX5_DBG_RSC_EQ, | |
185 | MLX5_DBG_RSC_CQ, | |
186 | }; | |
187 | ||
7ecf6d8f BW |
188 | enum port_state_policy { |
189 | MLX5_POLICY_DOWN = 0, | |
190 | MLX5_POLICY_UP = 1, | |
191 | MLX5_POLICY_FOLLOW = 2, | |
192 | MLX5_POLICY_INVALID = 0xffffffff | |
193 | }; | |
194 | ||
386e75af HN |
195 | enum mlx5_coredev_type { |
196 | MLX5_COREDEV_PF, | |
1958fc2f PP |
197 | MLX5_COREDEV_VF, |
198 | MLX5_COREDEV_SF, | |
386e75af HN |
199 | }; |
200 | ||
e126ba97 | 201 | struct mlx5_field_desc { |
e126ba97 EC |
202 | int i; |
203 | }; | |
204 | ||
205 | struct mlx5_rsc_debug { | |
206 | struct mlx5_core_dev *dev; | |
207 | void *object; | |
208 | enum dbg_rsc_type type; | |
209 | struct dentry *root; | |
b6ca09cb | 210 | struct mlx5_field_desc fields[]; |
e126ba97 EC |
211 | }; |
212 | ||
213 | enum mlx5_dev_event { | |
58d180b3 | 214 | MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ |
6997b1c9 | 215 | MLX5_DEV_EVENT_PORT_AFFINITY = 129, |
e126ba97 EC |
216 | }; |
217 | ||
4c916a79 | 218 | enum mlx5_port_status { |
6fa1bcab AS |
219 | MLX5_PORT_UP = 1, |
220 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
221 | }; |
222 | ||
f7936ddd EBE |
223 | enum mlx5_cmdif_state { |
224 | MLX5_CMDIF_STATE_UNINITIALIZED, | |
225 | MLX5_CMDIF_STATE_UP, | |
226 | MLX5_CMDIF_STATE_DOWN, | |
227 | }; | |
228 | ||
e126ba97 EC |
229 | struct mlx5_cmd_first { |
230 | __be32 data[4]; | |
231 | }; | |
232 | ||
233 | struct mlx5_cmd_msg { | |
234 | struct list_head list; | |
0ac3ea70 | 235 | struct cmd_msg_cache *parent; |
e126ba97 EC |
236 | u32 len; |
237 | struct mlx5_cmd_first first; | |
238 | struct mlx5_cmd_mailbox *next; | |
239 | }; | |
240 | ||
241 | struct mlx5_cmd_debug { | |
242 | struct dentry *dbg_root; | |
e126ba97 EC |
243 | void *in_msg; |
244 | void *out_msg; | |
245 | u8 status; | |
246 | u16 inlen; | |
247 | u16 outlen; | |
248 | }; | |
249 | ||
0ac3ea70 | 250 | struct cmd_msg_cache { |
e126ba97 EC |
251 | /* protect block chain allocations |
252 | */ | |
253 | spinlock_t lock; | |
254 | struct list_head head; | |
0ac3ea70 MHY |
255 | unsigned int max_inbox_size; |
256 | unsigned int num_ent; | |
e126ba97 EC |
257 | }; |
258 | ||
0ac3ea70 MHY |
259 | enum { |
260 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
261 | }; |
262 | ||
263 | struct mlx5_cmd_stats { | |
264 | u64 sum; | |
265 | u64 n; | |
266 | struct dentry *root; | |
e126ba97 EC |
267 | /* protect command average calculations */ |
268 | spinlock_t lock; | |
269 | }; | |
270 | ||
271 | struct mlx5_cmd { | |
71edc69c SM |
272 | struct mlx5_nb nb; |
273 | ||
f7936ddd | 274 | enum mlx5_cmdif_state state; |
64599cca EC |
275 | void *cmd_alloc_buf; |
276 | dma_addr_t alloc_dma; | |
277 | int alloc_size; | |
e126ba97 EC |
278 | void *cmd_buf; |
279 | dma_addr_t dma; | |
280 | u16 cmdif_rev; | |
281 | u8 log_sz; | |
282 | u8 log_stride; | |
283 | int max_reg_cmds; | |
284 | int events; | |
285 | u32 __iomem *vector; | |
286 | ||
287 | /* protect command queue allocations | |
288 | */ | |
289 | spinlock_t alloc_lock; | |
290 | ||
291 | /* protect token allocations | |
292 | */ | |
293 | spinlock_t token_lock; | |
294 | u8 token; | |
295 | unsigned long bitmask; | |
296 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
297 | struct workqueue_struct *wq; | |
298 | struct semaphore sem; | |
299 | struct semaphore pages_sem; | |
300 | int mode; | |
d43b7007 | 301 | u16 allowed_opcode; |
e126ba97 | 302 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; |
18c90df9 | 303 | struct dma_pool *pool; |
e126ba97 | 304 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 305 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 | 306 | int checksum_disabled; |
2553f421 | 307 | struct mlx5_cmd_stats *stats; |
e126ba97 EC |
308 | }; |
309 | ||
e126ba97 EC |
310 | struct mlx5_cmd_mailbox { |
311 | void *buf; | |
312 | dma_addr_t dma; | |
313 | struct mlx5_cmd_mailbox *next; | |
314 | }; | |
315 | ||
316 | struct mlx5_buf_list { | |
317 | void *buf; | |
318 | dma_addr_t map; | |
319 | }; | |
320 | ||
1c1b5228 TT |
321 | struct mlx5_frag_buf { |
322 | struct mlx5_buf_list *frags; | |
323 | int npages; | |
324 | int size; | |
325 | u8 page_shift; | |
326 | }; | |
327 | ||
388ca8be | 328 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 329 | struct mlx5_buf_list *frags; |
388ca8be | 330 | u32 sz_m1; |
8d71e818 | 331 | u16 frag_sz_m1; |
a0903622 | 332 | u16 strides_offset; |
388ca8be YC |
333 | u8 log_sz; |
334 | u8 log_stride; | |
335 | u8 log_frag_strides; | |
336 | }; | |
337 | ||
3121e3c4 SG |
338 | struct mlx5_core_psv { |
339 | u32 psv_idx; | |
340 | struct psv_layout { | |
341 | u32 pd; | |
342 | u16 syndrome; | |
343 | u16 reserved; | |
344 | u16 bg; | |
345 | u16 app_tag; | |
346 | u32 ref_tag; | |
347 | } psv; | |
348 | }; | |
349 | ||
350 | struct mlx5_core_sig_ctx { | |
351 | struct mlx5_core_psv psv_memory; | |
352 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
353 | struct ib_sig_err err_item; |
354 | bool sig_status_checked; | |
355 | bool sig_err_exists; | |
356 | u32 sigerr_count; | |
3121e3c4 | 357 | }; |
e126ba97 | 358 | |
aa8e08d2 AK |
359 | enum { |
360 | MLX5_MKEY_MR = 1, | |
361 | MLX5_MKEY_MW, | |
534fd7aa | 362 | MLX5_MKEY_INDIRECT_DEVX, |
aa8e08d2 AK |
363 | }; |
364 | ||
a606b0f6 | 365 | struct mlx5_core_mkey { |
e126ba97 EC |
366 | u64 iova; |
367 | u64 size; | |
368 | u32 key; | |
369 | u32 pd; | |
aa8e08d2 | 370 | u32 type; |
db72438c YH |
371 | struct wait_queue_head wait; |
372 | refcount_t usecount; | |
e126ba97 EC |
373 | }; |
374 | ||
d9aaed83 AK |
375 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
376 | ||
5903325a | 377 | enum mlx5_res_type { |
e2013b21 | 378 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
379 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
380 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
381 | MLX5_RES_SRQ = 3, | |
382 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 383 | MLX5_RES_XRQ = 5, |
57cda166 | 384 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
385 | }; |
386 | ||
387 | struct mlx5_core_rsc_common { | |
388 | enum mlx5_res_type res; | |
94f3e14e | 389 | refcount_t refcount; |
5903325a EC |
390 | struct completion free; |
391 | }; | |
392 | ||
a6d51b68 | 393 | struct mlx5_uars_page { |
e126ba97 | 394 | void __iomem *map; |
a6d51b68 EC |
395 | bool wc; |
396 | u32 index; | |
397 | struct list_head list; | |
398 | unsigned int bfregs; | |
399 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
400 | unsigned long *fp_bitmap; | |
401 | unsigned int reg_avail; | |
402 | unsigned int fp_avail; | |
403 | struct kref ref_count; | |
404 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
405 | }; |
406 | ||
a6d51b68 EC |
407 | struct mlx5_bfreg_head { |
408 | /* protect blue flame registers allocations */ | |
409 | struct mutex lock; | |
410 | struct list_head list; | |
411 | }; | |
412 | ||
413 | struct mlx5_bfreg_data { | |
414 | struct mlx5_bfreg_head reg_head; | |
415 | struct mlx5_bfreg_head wc_head; | |
416 | }; | |
417 | ||
418 | struct mlx5_sq_bfreg { | |
419 | void __iomem *map; | |
420 | struct mlx5_uars_page *up; | |
421 | bool wc; | |
422 | u32 index; | |
423 | unsigned int offset; | |
424 | }; | |
e126ba97 EC |
425 | |
426 | struct mlx5_core_health { | |
427 | struct health_buffer __iomem *health; | |
428 | __be32 __iomem *health_counter; | |
429 | struct timer_list timer; | |
e126ba97 EC |
430 | u32 prev; |
431 | int miss_counter; | |
d1bf0e2c | 432 | u8 synd; |
63cbc552 | 433 | u32 fatal_error; |
8b9d8baa | 434 | u32 crdump_size; |
05ac2c0b MHY |
435 | /* wq spinlock to synchronize draining */ |
436 | spinlock_t wq_lock; | |
ac6ea6e8 | 437 | struct workqueue_struct *wq; |
05ac2c0b | 438 | unsigned long flags; |
b3bd076f | 439 | struct work_struct fatal_report_work; |
d1bf0e2c | 440 | struct work_struct report_work; |
1e34f3ef | 441 | struct devlink_health_reporter *fw_reporter; |
96c82cdf | 442 | struct devlink_health_reporter *fw_fatal_reporter; |
e126ba97 EC |
443 | }; |
444 | ||
e126ba97 | 445 | struct mlx5_qp_table { |
451be51c | 446 | struct notifier_block nb; |
221c14f3 | 447 | |
e126ba97 EC |
448 | /* protect radix tree |
449 | */ | |
450 | spinlock_t lock; | |
451 | struct radix_tree_root tree; | |
452 | }; | |
453 | ||
fc50db98 EC |
454 | struct mlx5_vf_context { |
455 | int enabled; | |
7ecf6d8f BW |
456 | u64 port_guid; |
457 | u64 node_guid; | |
4bbd4923 DG |
458 | /* Valid bits are used to validate administrative guid only. |
459 | * Enabled after ndo_set_vf_guid | |
460 | */ | |
461 | u8 port_guid_valid:1; | |
462 | u8 node_guid_valid:1; | |
7ecf6d8f | 463 | enum port_state_policy policy; |
fc50db98 EC |
464 | }; |
465 | ||
466 | struct mlx5_core_sriov { | |
467 | struct mlx5_vf_context *vfs_ctx; | |
468 | int num_vfs; | |
86eec50b | 469 | u16 max_vfs; |
fc50db98 EC |
470 | }; |
471 | ||
558101f1 GT |
472 | struct mlx5_fc_pool { |
473 | struct mlx5_core_dev *dev; | |
474 | struct mutex pool_lock; /* protects pool lists */ | |
475 | struct list_head fully_used; | |
476 | struct list_head partially_used; | |
477 | struct list_head unused; | |
478 | int available_fcs; | |
479 | int used_fcs; | |
480 | int threshold; | |
481 | }; | |
482 | ||
43a335e0 | 483 | struct mlx5_fc_stats { |
12d6066c VB |
484 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
485 | struct idr counters_idr; | |
9aff93d7 | 486 | struct list_head counters; |
83033688 | 487 | struct llist_head addlist; |
6e5e2283 | 488 | struct llist_head dellist; |
43a335e0 AV |
489 | |
490 | struct workqueue_struct *wq; | |
491 | struct delayed_work work; | |
492 | unsigned long next_query; | |
f6dfb4c3 | 493 | unsigned long sampling_interval; /* jiffies */ |
6f06e04b | 494 | u32 *bulk_query_out; |
558101f1 | 495 | struct mlx5_fc_pool fc_pool; |
43a335e0 AV |
496 | }; |
497 | ||
69c1280b | 498 | struct mlx5_events; |
eeb66cdb | 499 | struct mlx5_mpfs; |
073bb189 | 500 | struct mlx5_eswitch; |
7907f23a | 501 | struct mlx5_lag; |
fadd59fc | 502 | struct mlx5_devcom; |
38b9f903 | 503 | struct mlx5_fw_reset; |
f2f3df55 | 504 | struct mlx5_eq_table; |
561aa15a | 505 | struct mlx5_irq_table; |
f3196bb0 | 506 | struct mlx5_vhca_state_notifier; |
90d010b8 | 507 | struct mlx5_sf_dev_table; |
8f010541 PP |
508 | struct mlx5_sf_hw_table; |
509 | struct mlx5_sf_table; | |
073bb189 | 510 | |
05d3ac97 BW |
511 | struct mlx5_rate_limit { |
512 | u32 rate; | |
513 | u32 max_burst_sz; | |
514 | u16 typical_pkt_sz; | |
515 | }; | |
516 | ||
1466cc5b | 517 | struct mlx5_rl_entry { |
1326034b | 518 | u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)]; |
1326034b | 519 | u64 refcount; |
4c4c0a89 | 520 | u16 index; |
1326034b YH |
521 | u16 uid; |
522 | u8 dedicated : 1; | |
1466cc5b YP |
523 | }; |
524 | ||
525 | struct mlx5_rl_table { | |
526 | /* protect rate limit table */ | |
527 | struct mutex rl_lock; | |
528 | u16 max_size; | |
529 | u32 max_rate; | |
530 | u32 min_rate; | |
531 | struct mlx5_rl_entry *rl_entry; | |
6b30b6d4 | 532 | u64 refcount; |
1466cc5b YP |
533 | }; |
534 | ||
80f09dfc MG |
535 | struct mlx5_core_roce { |
536 | struct mlx5_flow_table *ft; | |
537 | struct mlx5_flow_group *fg; | |
538 | struct mlx5_flow_handle *allow_rule; | |
539 | }; | |
540 | ||
a925b5e3 LR |
541 | enum { |
542 | MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0, | |
543 | MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1, | |
544 | }; | |
545 | ||
546 | struct mlx5_adev { | |
547 | struct auxiliary_device adev; | |
548 | struct mlx5_core_dev *mdev; | |
549 | int idx; | |
550 | }; | |
551 | ||
e126ba97 | 552 | struct mlx5_priv { |
561aa15a YA |
553 | /* IRQ table valid only for real pci devices PF or VF */ |
554 | struct mlx5_irq_table *irq_table; | |
f2f3df55 | 555 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
556 | |
557 | /* pages stuff */ | |
0cf53c12 | 558 | struct mlx5_nb pg_nb; |
e126ba97 | 559 | struct workqueue_struct *pg_wq; |
d6945242 | 560 | struct xarray page_root_xa; |
e126ba97 | 561 | int fw_pages; |
6aec21f6 | 562 | atomic_t reg_pages; |
bf0bf77f | 563 | struct list_head free_list; |
fc50db98 | 564 | int vfs_pages; |
8a90f2fc | 565 | int host_pf_pages; |
e126ba97 EC |
566 | |
567 | struct mlx5_core_health health; | |
3d347b1b | 568 | struct list_head traps; |
e126ba97 | 569 | |
e126ba97 | 570 | /* start: qp staff */ |
e126ba97 EC |
571 | struct dentry *qp_debugfs; |
572 | struct dentry *eq_debugfs; | |
573 | struct dentry *cq_debugfs; | |
574 | struct dentry *cmdif_debugfs; | |
575 | /* end: qp staff */ | |
576 | ||
e126ba97 | 577 | /* start: alloc staff */ |
311c7c71 SM |
578 | /* protect buffer alocation according to numa node */ |
579 | struct mutex alloc_mutex; | |
580 | int numa_node; | |
581 | ||
e126ba97 EC |
582 | struct mutex pgdir_mutex; |
583 | struct list_head pgdir_list; | |
584 | /* end: alloc staff */ | |
585 | struct dentry *dbg_root; | |
586 | ||
9603b61d JM |
587 | struct list_head ctx_list; |
588 | spinlock_t ctx_lock; | |
a925b5e3 LR |
589 | struct mlx5_adev **adev; |
590 | int adev_idx; | |
02039fb6 | 591 | struct mlx5_events *events; |
97834eba | 592 | |
fba53f7b | 593 | struct mlx5_flow_steering *steering; |
eeb66cdb | 594 | struct mlx5_mpfs *mpfs; |
073bb189 | 595 | struct mlx5_eswitch *eswitch; |
fc50db98 | 596 | struct mlx5_core_sriov sriov; |
7907f23a | 597 | struct mlx5_lag *lag; |
a925b5e3 | 598 | u32 flags; |
fadd59fc | 599 | struct mlx5_devcom *devcom; |
38b9f903 | 600 | struct mlx5_fw_reset *fw_reset; |
80f09dfc | 601 | struct mlx5_core_roce roce; |
43a335e0 | 602 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 603 | struct mlx5_rl_table rl_table; |
d4eb4cd7 | 604 | |
a6d51b68 | 605 | struct mlx5_bfreg_data bfregs; |
01187175 | 606 | struct mlx5_uars_page *uar; |
f3196bb0 PP |
607 | #ifdef CONFIG_MLX5_SF |
608 | struct mlx5_vhca_state_notifier *vhca_state_notifier; | |
90d010b8 | 609 | struct mlx5_sf_dev_table *sf_dev_table; |
1958fc2f | 610 | struct mlx5_core_dev *parent_mdev; |
f3196bb0 | 611 | #endif |
8f010541 PP |
612 | #ifdef CONFIG_MLX5_SF_MANAGER |
613 | struct mlx5_sf_hw_table *sf_hw_table; | |
614 | struct mlx5_sf_table *sf_table; | |
615 | #endif | |
e126ba97 EC |
616 | }; |
617 | ||
89d44f0a | 618 | enum mlx5_device_state { |
3e5b72ac | 619 | MLX5_DEVICE_STATE_UNINITIALIZED, |
89d44f0a MD |
620 | MLX5_DEVICE_STATE_UP, |
621 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
622 | }; | |
623 | ||
624 | enum mlx5_interface_state { | |
b3cb5388 | 625 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
626 | }; |
627 | ||
628 | enum mlx5_pci_status { | |
629 | MLX5_PCI_STATUS_DISABLED, | |
630 | MLX5_PCI_STATUS_ENABLED, | |
631 | }; | |
632 | ||
d9aaed83 AK |
633 | enum mlx5_pagefault_type_flags { |
634 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
635 | MLX5_PFAULT_WRITE = 1 << 1, | |
636 | MLX5_PFAULT_RDMA = 1 << 2, | |
637 | }; | |
638 | ||
b50d292b | 639 | struct mlx5_td { |
80a2a902 YA |
640 | /* protects tirs list changes while tirs refresh */ |
641 | struct mutex list_lock; | |
b50d292b HHZ |
642 | struct list_head tirs_list; |
643 | u32 tdn; | |
644 | }; | |
645 | ||
646 | struct mlx5e_resources { | |
c276aae8 RD |
647 | struct mlx5e_hw_objs { |
648 | u32 pdn; | |
649 | struct mlx5_td td; | |
650 | struct mlx5_core_mkey mkey; | |
651 | struct mlx5_sq_bfreg bfreg; | |
652 | } hw_objs; | |
c27971d0 | 653 | struct devlink_port dl_port; |
7a9fb35e | 654 | struct net_device *uplink_netdev; |
b50d292b HHZ |
655 | }; |
656 | ||
c9b9dcb4 AL |
657 | enum mlx5_sw_icm_type { |
658 | MLX5_SW_ICM_TYPE_STEERING, | |
659 | MLX5_SW_ICM_TYPE_HEADER_MODIFY, | |
660 | }; | |
661 | ||
52ec462e IT |
662 | #define MLX5_MAX_RESERVED_GIDS 8 |
663 | ||
664 | struct mlx5_rsvd_gids { | |
665 | unsigned int start; | |
666 | unsigned int count; | |
667 | struct ida ida; | |
668 | }; | |
669 | ||
7c39afb3 FD |
670 | #define MAX_PIN_NUM 8 |
671 | struct mlx5_pps { | |
672 | u8 pin_caps[MAX_PIN_NUM]; | |
673 | struct work_struct out_work; | |
674 | u64 start[MAX_PIN_NUM]; | |
675 | u8 enabled; | |
676 | }; | |
677 | ||
d6f3dc8f | 678 | struct mlx5_timer { |
7c39afb3 FD |
679 | struct cyclecounter cycles; |
680 | struct timecounter tc; | |
7c39afb3 FD |
681 | u32 nominal_c_mult; |
682 | unsigned long overflow_period; | |
683 | struct delayed_work overflow_work; | |
d6f3dc8f EBE |
684 | }; |
685 | ||
686 | struct mlx5_clock { | |
687 | struct mlx5_nb pps_nb; | |
688 | seqlock_t lock; | |
689 | struct hwtstamp_config hwtstamp_config; | |
7c39afb3 FD |
690 | struct ptp_clock *ptp; |
691 | struct ptp_clock_info ptp_info; | |
692 | struct mlx5_pps pps_info; | |
d6f3dc8f | 693 | struct mlx5_timer timer; |
7c39afb3 FD |
694 | }; |
695 | ||
c9b9dcb4 | 696 | struct mlx5_dm; |
f53aaa31 | 697 | struct mlx5_fw_tracer; |
358aa5ce | 698 | struct mlx5_vxlan; |
0ccc171e | 699 | struct mlx5_geneve; |
87175120 | 700 | struct mlx5_hv_vhca; |
f53aaa31 | 701 | |
c9b9dcb4 AL |
702 | #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) |
703 | #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) | |
704 | ||
e126ba97 | 705 | struct mlx5_core_dev { |
27b942fb | 706 | struct device *device; |
386e75af | 707 | enum mlx5_coredev_type coredev_type; |
e126ba97 | 708 | struct pci_dev *pdev; |
89d44f0a MD |
709 | /* sync pci state */ |
710 | struct mutex pci_status_mutex; | |
711 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
712 | u8 rev_id; |
713 | char board_id[MLX5_BOARD_ID_LEN]; | |
714 | struct mlx5_cmd cmd; | |
71862561 | 715 | struct { |
701052c5 GP |
716 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
717 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 | 718 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
932ef155 | 719 | u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; |
99d3cd27 | 720 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 721 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
591905ba | 722 | u8 embedded_cpu; |
71862561 | 723 | } caps; |
59c9d35e | 724 | u64 sys_image_guid; |
e126ba97 EC |
725 | phys_addr_t iseg_base; |
726 | struct mlx5_init_seg __iomem *iseg; | |
aa8106f1 | 727 | phys_addr_t bar_addr; |
89d44f0a MD |
728 | enum mlx5_device_state state; |
729 | /* sync interface state */ | |
730 | struct mutex intf_state_mutex; | |
5fc7197d | 731 | unsigned long intf_state; |
e126ba97 EC |
732 | struct mlx5_priv priv; |
733 | struct mlx5_profile *profile; | |
f62b8bb8 | 734 | u32 issi; |
b50d292b | 735 | struct mlx5e_resources mlx5e_res; |
c9b9dcb4 | 736 | struct mlx5_dm *dm; |
358aa5ce | 737 | struct mlx5_vxlan *vxlan; |
0ccc171e | 738 | struct mlx5_geneve *geneve; |
52ec462e IT |
739 | struct { |
740 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 741 | u32 roce_en; |
52ec462e | 742 | } roce; |
e29341fb IT |
743 | #ifdef CONFIG_MLX5_FPGA |
744 | struct mlx5_fpga_device *fpga; | |
9a6ad1ad RS |
745 | #endif |
746 | #ifdef CONFIG_MLX5_ACCEL | |
747 | const struct mlx5_accel_ipsec_ops *ipsec_ops; | |
5a7b27eb | 748 | #endif |
7c39afb3 | 749 | struct mlx5_clock clock; |
24d33d2c | 750 | struct mlx5_ib_clock_info *clock_info; |
f53aaa31 | 751 | struct mlx5_fw_tracer *tracer; |
12206b17 | 752 | struct mlx5_rsc_dump *rsc_dump; |
b25bbc2f | 753 | u32 vsc_addr; |
87175120 | 754 | struct mlx5_hv_vhca *hv_vhca; |
e126ba97 EC |
755 | }; |
756 | ||
757 | struct mlx5_db { | |
758 | __be32 *db; | |
759 | union { | |
760 | struct mlx5_db_pgdir *pgdir; | |
761 | struct mlx5_ib_user_db_page *user_page; | |
762 | } u; | |
763 | dma_addr_t dma; | |
764 | int index; | |
765 | }; | |
766 | ||
e126ba97 EC |
767 | enum { |
768 | MLX5_COMP_EQ_SIZE = 1024, | |
769 | }; | |
770 | ||
adb0c954 SM |
771 | enum { |
772 | MLX5_PTYS_IB = 1 << 0, | |
773 | MLX5_PTYS_EN = 1 << 2, | |
774 | }; | |
775 | ||
e126ba97 EC |
776 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
777 | ||
73dd3a48 MHY |
778 | enum { |
779 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
780 | }; | |
781 | ||
e126ba97 | 782 | struct mlx5_cmd_work_ent { |
73dd3a48 | 783 | unsigned long state; |
e126ba97 EC |
784 | struct mlx5_cmd_msg *in; |
785 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
786 | void *uout; |
787 | int uout_size; | |
e126ba97 | 788 | mlx5_cmd_cbk_t callback; |
65ee6708 | 789 | struct delayed_work cb_timeout_work; |
e126ba97 | 790 | void *context; |
746b5583 | 791 | int idx; |
17d00e83 | 792 | struct completion handling; |
e126ba97 EC |
793 | struct completion done; |
794 | struct mlx5_cmd *cmd; | |
795 | struct work_struct work; | |
796 | struct mlx5_cmd_layout *lay; | |
797 | int ret; | |
798 | int page_queue; | |
799 | u8 status; | |
800 | u8 token; | |
14a70046 TG |
801 | u64 ts1; |
802 | u64 ts2; | |
746b5583 | 803 | u16 op; |
4525abea | 804 | bool polling; |
50b2412b EBE |
805 | /* Track the max comp handlers */ |
806 | refcount_t refcnt; | |
e126ba97 EC |
807 | }; |
808 | ||
809 | struct mlx5_pas { | |
810 | u64 pa; | |
811 | u8 log_sz; | |
812 | }; | |
813 | ||
707c4602 MD |
814 | enum phy_port_state { |
815 | MLX5_AAA_111 | |
816 | }; | |
817 | ||
818 | struct mlx5_hca_vport_context { | |
819 | u32 field_select; | |
820 | bool sm_virt_aware; | |
821 | bool has_smi; | |
822 | bool has_raw; | |
823 | enum port_state_policy policy; | |
824 | enum phy_port_state phys_state; | |
825 | enum ib_port_state vport_state; | |
826 | u8 port_physical_state; | |
827 | u64 sys_image_guid; | |
828 | u64 port_guid; | |
829 | u64 node_guid; | |
830 | u32 cap_mask1; | |
831 | u32 cap_mask1_perm; | |
4106a758 MG |
832 | u16 cap_mask2; |
833 | u16 cap_mask2_perm; | |
707c4602 MD |
834 | u16 lid; |
835 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
836 | u8 lmc; | |
837 | u8 subnet_timeout; | |
838 | u16 sm_lid; | |
839 | u8 sm_sl; | |
840 | u16 qkey_violation_counter; | |
841 | u16 pkey_violation_counter; | |
842 | bool grh_required; | |
843 | }; | |
844 | ||
388ca8be | 845 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 846 | { |
388ca8be | 847 | return buf->frags->buf + offset; |
e126ba97 EC |
848 | } |
849 | ||
e126ba97 EC |
850 | #define STRUCT_FIELD(header, field) \ |
851 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
852 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
853 | ||
e126ba97 EC |
854 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
855 | { | |
856 | return pci_get_drvdata(pdev); | |
857 | } | |
858 | ||
859 | extern struct dentry *mlx5_debugfs_root; | |
860 | ||
861 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
862 | { | |
863 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
864 | } | |
865 | ||
866 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
867 | { | |
868 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
869 | } | |
870 | ||
871 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
872 | { | |
873 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
874 | } | |
875 | ||
3bcdb17a SG |
876 | static inline u32 mlx5_base_mkey(const u32 key) |
877 | { | |
878 | return key & 0xffffff00u; | |
879 | } | |
880 | ||
26bf3090 TT |
881 | static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride) |
882 | { | |
883 | return ((u32)1 << log_sz) << log_stride; | |
884 | } | |
885 | ||
4972e6fa TT |
886 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
887 | u8 log_stride, u8 log_sz, | |
a0903622 | 888 | u16 strides_offset, |
d7037ad7 | 889 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 890 | { |
4972e6fa | 891 | fbc->frags = frags; |
3a2f7033 TT |
892 | fbc->log_stride = log_stride; |
893 | fbc->log_sz = log_sz; | |
388ca8be YC |
894 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
895 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
896 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
897 | fbc->strides_offset = strides_offset; |
898 | } | |
899 | ||
4972e6fa TT |
900 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
901 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
902 | struct mlx5_frag_buf_ctrl *fbc) |
903 | { | |
4972e6fa | 904 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
905 | } |
906 | ||
388ca8be YC |
907 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
908 | u32 ix) | |
909 | { | |
d7037ad7 TT |
910 | unsigned int frag; |
911 | ||
912 | ix += fbc->strides_offset; | |
913 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 914 | |
4972e6fa | 915 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
916 | } |
917 | ||
37fdffb2 TT |
918 | static inline u32 |
919 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
920 | { | |
921 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
922 | ||
923 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
924 | } | |
925 | ||
d43b7007 EBE |
926 | enum { |
927 | CMD_ALLOWED_OPCODE_ALL, | |
928 | }; | |
929 | ||
e126ba97 EC |
930 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); |
931 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
d43b7007 | 932 | void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode); |
c4f287c4 | 933 | |
e355477e JG |
934 | struct mlx5_async_ctx { |
935 | struct mlx5_core_dev *dev; | |
936 | atomic_t num_inflight; | |
937 | struct wait_queue_head wait; | |
938 | }; | |
939 | ||
940 | struct mlx5_async_work; | |
941 | ||
942 | typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); | |
943 | ||
944 | struct mlx5_async_work { | |
945 | struct mlx5_async_ctx *ctx; | |
946 | mlx5_async_cbk_t user_callback; | |
947 | }; | |
948 | ||
949 | void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, | |
950 | struct mlx5_async_ctx *ctx); | |
951 | void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); | |
952 | int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, | |
953 | void *out, int out_size, mlx5_async_cbk_t callback, | |
954 | struct mlx5_async_work *work); | |
955 | ||
e126ba97 EC |
956 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
957 | int out_size); | |
bb7fc863 LR |
958 | |
959 | #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \ | |
960 | ({ \ | |
961 | mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \ | |
962 | MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \ | |
963 | }) | |
964 | ||
965 | #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \ | |
966 | ({ \ | |
967 | u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \ | |
968 | mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \ | |
969 | }) | |
970 | ||
4525abea MD |
971 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
972 | void *out, int out_size); | |
c4f287c4 | 973 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
b898ce7b | 974 | bool mlx5_cmd_is_down(struct mlx5_core_dev *dev); |
c4f287c4 SM |
975 | |
976 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
977 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
978 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
52c368dc | 979 | void mlx5_health_flush(struct mlx5_core_dev *dev); |
ac6ea6e8 EC |
980 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
981 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 982 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 983 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 984 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 985 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
388ca8be YC |
986 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, |
987 | int size, struct mlx5_frag_buf *buf); | |
988 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
989 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
990 | struct mlx5_frag_buf *buf, int node); | |
991 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
992 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
993 | gfp_t flags, int npages); | |
994 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
995 | struct mlx5_cmd_mailbox *head); | |
a606b0f6 MB |
996 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
997 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 998 | u32 *in, int inlen); |
a606b0f6 MB |
999 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
1000 | struct mlx5_core_mkey *mkey); | |
1001 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1002 | u32 *out, int outlen); |
e126ba97 EC |
1003 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
1004 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
0cf53c12 | 1005 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
e126ba97 | 1006 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
0cf53c12 | 1007 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
e126ba97 EC |
1008 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
1009 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
591905ba | 1010 | s32 npages, bool ec_function); |
cd23b14b | 1011 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
1012 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
1013 | void mlx5_register_debugfs(void); | |
1014 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
1015 | |
1016 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1dcb6c36 | 1017 | void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm); |
1c1b5228 | 1018 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
0b6e26ce DT |
1019 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
1020 | unsigned int *irqn); | |
e126ba97 EC |
1021 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
1022 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
1023 | ||
9f818c8a | 1024 | void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 EC |
1025 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); |
1026 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
1027 | int size_in, void *data_out, int size_out, | |
1028 | u16 reg_num, int arg, int write); | |
adb0c954 | 1029 | |
e126ba97 | 1030 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
1031 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
1032 | int node); | |
e126ba97 EC |
1033 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
1034 | ||
e126ba97 | 1035 | const char *mlx5_command_str(int command); |
9f818c8a | 1036 | void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 | 1037 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); |
3121e3c4 SG |
1038 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
1039 | int npsvs, u32 *sig_index); | |
1040 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1041 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1042 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1043 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1044 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1045 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 1046 | |
1466cc5b YP |
1047 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1048 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
1049 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
1050 | struct mlx5_rate_limit *rl); | |
1051 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 1052 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
1326034b YH |
1053 | int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid, |
1054 | bool dedicated_entry, u16 *index); | |
1055 | void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index); | |
05d3ac97 BW |
1056 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
1057 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
1058 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1059 | bool map_wc, bool fast_path); | |
1060 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1061 | |
f2f3df55 SM |
1062 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
1063 | struct cpumask * | |
1064 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
1065 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1066 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1067 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1068 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1069 | |
e126ba97 EC |
1070 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1071 | { | |
1072 | return mkey >> 8; | |
1073 | } | |
1074 | ||
1075 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1076 | { | |
1077 | return mkey_idx << 8; | |
1078 | } | |
1079 | ||
746b5583 EC |
1080 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1081 | { | |
1082 | return mkey & 0xff; | |
1083 | } | |
1084 | ||
e126ba97 EC |
1085 | enum { |
1086 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1087 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1088 | }; |
1089 | ||
1090 | enum { | |
8b7ff7f3 | 1091 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1092 | MLX5_IMR_MTT_CACHE_ENTRY, |
1093 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1094 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1095 | }; |
1096 | ||
241dc159 AL |
1097 | /* Async-atomic event notifier used by mlx5 core to forward FW |
1098 | * evetns recived from event queue to mlx5 consumers. | |
1099 | * Optimise event queue dipatching. | |
1100 | */ | |
20902be4 SM |
1101 | int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
1102 | int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
241dc159 AL |
1103 | |
1104 | /* Async-atomic event notifier used for forwarding | |
1105 | * evetns from the event queue into the to mlx5 events dispatcher, | |
1106 | * eswitch, clock and others. | |
1107 | */ | |
c0670781 YH |
1108 | int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); |
1109 | int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); | |
20902be4 | 1110 | |
241dc159 AL |
1111 | /* Blocking event notifier used to forward SW events, used for slow path */ |
1112 | int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
1113 | int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
1114 | int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event, | |
1115 | void *data); | |
1116 | ||
211e6c80 | 1117 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1118 | |
3bc34f3b AH |
1119 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1120 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7c34ec19 AH |
1121 | bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); |
1122 | bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); | |
724b509c | 1123 | bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); |
7907f23a | 1124 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1125 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
c6bc6041 MG |
1126 | u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev, |
1127 | struct net_device *slave); | |
71a0ff65 MD |
1128 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1129 | u64 *values, | |
1130 | int num_counters, | |
1131 | size_t *offsets); | |
01187175 EC |
1132 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1133 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
c9b9dcb4 | 1134 | int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
dff8e2d1 ES |
1135 | u64 length, u32 log_alignment, u16 uid, |
1136 | phys_addr_t *addr, u32 *obj_id); | |
c9b9dcb4 AL |
1137 | int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
1138 | u64 length, u16 uid, phys_addr_t addr, u32 obj_id); | |
7907f23a | 1139 | |
f6a8a19b | 1140 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1141 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1142 | struct ib_device *ibdev, | |
1143 | const char *name, | |
1144 | void (*setup)(struct net_device *)); | |
693dfd5a | 1145 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1146 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1147 | struct ib_device *device, | |
1148 | struct rdma_netdev_alloc_params *params); | |
693dfd5a | 1149 | |
e126ba97 EC |
1150 | struct mlx5_profile { |
1151 | u64 mask; | |
f241e749 | 1152 | u8 log_max_qp; |
e126ba97 EC |
1153 | struct { |
1154 | int size; | |
1155 | int limit; | |
1156 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1157 | }; | |
1158 | ||
fc50db98 EC |
1159 | enum { |
1160 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1161 | }; | |
1162 | ||
2752b823 | 1163 | static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) |
fc50db98 | 1164 | { |
386e75af | 1165 | return dev->coredev_type == MLX5_COREDEV_PF; |
fc50db98 EC |
1166 | } |
1167 | ||
e53a9d26 PP |
1168 | static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev) |
1169 | { | |
1170 | return dev->coredev_type == MLX5_COREDEV_VF; | |
1171 | } | |
1172 | ||
3b1e58aa | 1173 | static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev) |
591905ba BW |
1174 | { |
1175 | return dev->caps.embedded_cpu; | |
1176 | } | |
1177 | ||
2752b823 PP |
1178 | static inline bool |
1179 | mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) | |
7f0d11c7 BW |
1180 | { |
1181 | return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); | |
1182 | } | |
1183 | ||
2752b823 | 1184 | static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) |
81cd229c BW |
1185 | { |
1186 | return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); | |
1187 | } | |
1188 | ||
2752b823 | 1189 | static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) |
feb39369 | 1190 | { |
86eec50b | 1191 | return dev->priv.sriov.max_vfs; |
feb39369 BW |
1192 | } |
1193 | ||
707c4602 MD |
1194 | static inline int mlx5_get_gid_table_len(u16 param) |
1195 | { | |
1196 | if (param > 4) { | |
1197 | pr_warn("gid table length is zero\n"); | |
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | return 8 * (1 << param); | |
1202 | } | |
1203 | ||
1466cc5b YP |
1204 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1205 | { | |
1206 | return !!(dev->priv.rl_table.max_size); | |
1207 | } | |
1208 | ||
32f69e4b DJ |
1209 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1210 | { | |
1211 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1212 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1213 | } | |
1214 | ||
1215 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1216 | { | |
1217 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1218 | } | |
1219 | ||
1220 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1221 | { | |
1222 | return mlx5_core_is_mp_slave(dev) || | |
1223 | mlx5_core_is_mp_master(dev); | |
1224 | } | |
1225 | ||
7fd8aefb DJ |
1226 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1227 | { | |
32f69e4b DJ |
1228 | if (!mlx5_core_mp_enabled(dev)) |
1229 | return 1; | |
1230 | ||
1231 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1232 | } |
1233 | ||
020446e0 EC |
1234 | enum { |
1235 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1236 | }; | |
1237 | ||
cc9defcb MG |
1238 | static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev) |
1239 | { | |
1240 | struct devlink *devlink = priv_to_devlink(dev); | |
1241 | union devlink_param_value val; | |
1242 | ||
1243 | devlink_param_driverinit_value_get(devlink, | |
1244 | DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, | |
1245 | &val); | |
1246 | return val.vbool; | |
1247 | } | |
1248 | ||
e126ba97 | 1249 | #endif /* MLX5_DRIVER_H */ |