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net/mlx5: Initializing CPU reverse mapping
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
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e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
36350114
GP		 48enum {
49 MLX5_RQ_BITMASK_VSD = 1 << 1,
50};
51
e126ba97
EC		 52enum {
53 MLX5_BOARD_ID_LEN = 64,
54 MLX5_MAX_NAME_LEN = 16,
55};
56
57enum {
58 /* one minute for the sake of bringup. Generally, commands must always
59 * complete and we may need to increase this timeout value
60 */
6b6c07bd 61 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
e126ba97
EC		 62 MLX5_CMD_WQ_MAX_NAME = 32,
63};
64
65enum {
66 CMD_OWNER_SW = 0x0,
67 CMD_OWNER_HW = 0x1,
68 CMD_STATUS_SUCCESS = 0,
69};
70
71enum mlx5_sqp_t {
72 MLX5_SQP_SMI = 0,
73 MLX5_SQP_GSI = 1,
74 MLX5_SQP_IEEE_1588 = 2,
75 MLX5_SQP_SNIFFER = 3,
76 MLX5_SQP_SYNC_UMR = 4,
77};
78
79enum {
80 MLX5_MAX_PORTS = 2,
81};
82
83enum {
84 MLX5_EQ_VEC_PAGES = 0,
85 MLX5_EQ_VEC_CMD = 1,
86 MLX5_EQ_VEC_ASYNC = 2,
87 MLX5_EQ_VEC_COMP_BASE,
88};
89
90enum {
db058a18 91 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 92};
93
94enum {
95 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
96 MLX5_ATOMIC_MODE_CX = 2 << 16,
97 MLX5_ATOMIC_MODE_8B = 3 << 16,
98 MLX5_ATOMIC_MODE_16B = 4 << 16,
99 MLX5_ATOMIC_MODE_32B = 5 << 16,
100 MLX5_ATOMIC_MODE_64B = 6 << 16,
101 MLX5_ATOMIC_MODE_128B = 7 << 16,
102 MLX5_ATOMIC_MODE_256B = 8 << 16,
103};
104
e126ba97 105enum {
4f3961ee
SM		 106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
e126ba97
EC		 108 MLX5_REG_PCAP = 0x5001,
109 MLX5_REG_PMTU = 0x5003,
110 MLX5_REG_PTYS = 0x5004,
111 MLX5_REG_PAOS = 0x5006,
3c2d18ef 112 MLX5_REG_PFCC = 0x5007,
efea389d 113 MLX5_REG_PPCNT = 0x5008,
e126ba97
EC		 114 MLX5_REG_PMAOS = 0x5012,
115 MLX5_REG_PUDE = 0x5009,
116 MLX5_REG_PMPE = 0x5010,
117 MLX5_REG_PELC = 0x500e,
a124d13e 118 MLX5_REG_PVLC = 0x500f,
94cb1ebb 119 MLX5_REG_PCMR = 0x5041,
bb64143e 120 MLX5_REG_PMLP = 0x5002,
e126ba97
EC		 121 MLX5_REG_NODE_DESC = 0x6001,
122 MLX5_REG_HOST_ENDIANNESS = 0x7004,
bb64143e 123 MLX5_REG_MCIA = 0x9014,
da54d24e 124 MLX5_REG_MLCR = 0x902b,
e126ba97
EC		 125};
126
da7525d2
EBE		 127enum {
128 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
129 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
130};
131
e420f0c0
HE		 132enum mlx5_page_fault_resume_flags {
133 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
134 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
135 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
136 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
137};
138
e126ba97
EC		 139enum dbg_rsc_type {
140 MLX5_DBG_RSC_QP,
141 MLX5_DBG_RSC_EQ,
142 MLX5_DBG_RSC_CQ,
143};
144
145struct mlx5_field_desc {
146 struct dentry *dent;
147 int i;
148};
149
150struct mlx5_rsc_debug {
151 struct mlx5_core_dev *dev;
152 void *object;
153 enum dbg_rsc_type type;
154 struct dentry *root;
155 struct mlx5_field_desc fields[0];
156};
157
158enum mlx5_dev_event {
159 MLX5_DEV_EVENT_SYS_ERROR,
160 MLX5_DEV_EVENT_PORT_UP,
161 MLX5_DEV_EVENT_PORT_DOWN,
162 MLX5_DEV_EVENT_PORT_INITIALIZED,
163 MLX5_DEV_EVENT_LID_CHANGE,
164 MLX5_DEV_EVENT_PKEY_CHANGE,
165 MLX5_DEV_EVENT_GUID_CHANGE,
166 MLX5_DEV_EVENT_CLIENT_REREG,
167};
168
4c916a79 169enum mlx5_port_status {
6fa1bcab
AS		 170 MLX5_PORT_UP = 1,
171 MLX5_PORT_DOWN = 2,
4c916a79
RS		 172};
173
e126ba97
EC		 174struct mlx5_uuar_info {
175 struct mlx5_uar *uars;
176 int num_uars;
177 int num_low_latency_uuars;
178 unsigned long *bitmap;
179 unsigned int *count;
180 struct mlx5_bf *bfs;
181
182 /*
183 * protect uuar allocation data structs
184 */
185 struct mutex lock;
78c0f98c 186 u32 ver;
e126ba97
EC		 187};
188
189struct mlx5_bf {
190 void __iomem *reg;
191 void __iomem *regreg;
192 int buf_size;
193 struct mlx5_uar *uar;
194 unsigned long offset;
195 int need_lock;
196 /* protect blue flame buffer selection when needed
197 */
198 spinlock_t lock;
199
200 /* serialize 64 bit writes when done as two 32 bit accesses
201 */
202 spinlock_t lock32;
203 int uuarn;
204};
205
206struct mlx5_cmd_first {
207 __be32 data[4];
208};
209
210struct mlx5_cmd_msg {
211 struct list_head list;
212 struct cache_ent *cache;
213 u32 len;
214 struct mlx5_cmd_first first;
215 struct mlx5_cmd_mailbox *next;
216};
217
218struct mlx5_cmd_debug {
219 struct dentry *dbg_root;
220 struct dentry *dbg_in;
221 struct dentry *dbg_out;
222 struct dentry *dbg_outlen;
223 struct dentry *dbg_status;
224 struct dentry *dbg_run;
225 void *in_msg;
226 void *out_msg;
227 u8 status;
228 u16 inlen;
229 u16 outlen;
230};
231
232struct cache_ent {
233 /* protect block chain allocations
234 */
235 spinlock_t lock;
236 struct list_head head;
237};
238
239struct cmd_msg_cache {
240 struct cache_ent large;
241 struct cache_ent med;
242
243};
244
245struct mlx5_cmd_stats {
246 u64 sum;
247 u64 n;
248 struct dentry *root;
249 struct dentry *avg;
250 struct dentry *count;
251 /* protect command average calculations */
252 spinlock_t lock;
253};
254
255struct mlx5_cmd {
64599cca
EC		 256 void *cmd_alloc_buf;
257 dma_addr_t alloc_dma;
258 int alloc_size;
e126ba97
EC		 259 void *cmd_buf;
260 dma_addr_t dma;
261 u16 cmdif_rev;
262 u8 log_sz;
263 u8 log_stride;
264 int max_reg_cmds;
265 int events;
266 u32 __iomem *vector;
267
268 /* protect command queue allocations
269 */
270 spinlock_t alloc_lock;
271
272 /* protect token allocations
273 */
274 spinlock_t token_lock;
275 u8 token;
276 unsigned long bitmask;
277 char wq_name[MLX5_CMD_WQ_MAX_NAME];
278 struct workqueue_struct *wq;
279 struct semaphore sem;
280 struct semaphore pages_sem;
281 int mode;
282 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
283 struct pci_pool *pool;
284 struct mlx5_cmd_debug dbg;
285 struct cmd_msg_cache cache;
286 int checksum_disabled;
287 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
288};
289
290struct mlx5_port_caps {
291 int gid_table_len;
292 int pkey_table_len;
938fe83c 293 u8 ext_port_cap;
e126ba97
EC		 294};
295
296struct mlx5_cmd_mailbox {
297 void *buf;
298 dma_addr_t dma;
299 struct mlx5_cmd_mailbox *next;
300};
301
302struct mlx5_buf_list {
303 void *buf;
304 dma_addr_t map;
305};
306
307struct mlx5_buf {
308 struct mlx5_buf_list direct;
e126ba97 309 int npages;
e126ba97 310 int size;
f241e749 311 u8 page_shift;
e126ba97
EC		 312};
313
314struct mlx5_eq {
315 struct mlx5_core_dev *dev;
316 __be32 __iomem *doorbell;
317 u32 cons_index;
318 struct mlx5_buf buf;
319 int size;
0b6e26ce 320 unsigned int irqn;
e126ba97
EC		 321 u8 eqn;
322 int nent;
323 u64 mask;
e126ba97
EC		 324 struct list_head list;
325 int index;
326 struct mlx5_rsc_debug *dbg;
327};
328
3121e3c4
SG		 329struct mlx5_core_psv {
330 u32 psv_idx;
331 struct psv_layout {
332 u32 pd;
333 u16 syndrome;
334 u16 reserved;
335 u16 bg;
336 u16 app_tag;
337 u32 ref_tag;
338 } psv;
339};
340
341struct mlx5_core_sig_ctx {
342 struct mlx5_core_psv psv_memory;
343 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 344 struct ib_sig_err err_item;
345 bool sig_status_checked;
346 bool sig_err_exists;
347 u32 sigerr_count;
3121e3c4 348};
e126ba97 349
a606b0f6 350struct mlx5_core_mkey {
e126ba97
EC		 351 u64 iova;
352 u64 size;
353 u32 key;
354 u32 pd;
e126ba97
EC		 355};
356
5903325a 357enum mlx5_res_type {
e2013b21 358 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
359 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
360 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
361 MLX5_RES_SRQ = 3,
362 MLX5_RES_XSRQ = 4,
5903325a
EC		 363};
364
365struct mlx5_core_rsc_common {
366 enum mlx5_res_type res;
367 atomic_t refcount;
368 struct completion free;
369};
370
e126ba97 371struct mlx5_core_srq {
01949d01 372 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC		 373 u32 srqn;
374 int max;
375 int max_gs;
376 int max_avail_gather;
377 int wqe_shift;
378 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
379
380 atomic_t refcount;
381 struct completion free;
382};
383
384struct mlx5_eq_table {
385 void __iomem *update_ci;
386 void __iomem *update_arm_ci;
233d05d2 387 struct list_head comp_eqs_list;
e126ba97
EC		 388 struct mlx5_eq pages_eq;
389 struct mlx5_eq async_eq;
390 struct mlx5_eq cmd_eq;
e126ba97
EC		 391 int num_comp_vectors;
392 /* protect EQs list
393 */
394 spinlock_t lock;
395};
396
397struct mlx5_uar {
398 u32 index;
399 struct list_head bf_list;
400 unsigned free_bf_bmap;
88a85f99 401 void __iomem *bf_map;
e126ba97
EC		 402 void __iomem *map;
403};
404
405
406struct mlx5_core_health {
407 struct health_buffer __iomem *health;
408 __be32 __iomem *health_counter;
409 struct timer_list timer;
e126ba97
EC		 410 u32 prev;
411 int miss_counter;
fd76ee4d 412 bool sick;
ac6ea6e8
EC		 413 struct workqueue_struct *wq;
414 struct work_struct work;
e126ba97
EC		 415};
416
417struct mlx5_cq_table {
418 /* protect radix tree
419 */
420 spinlock_t lock;
421 struct radix_tree_root tree;
422};
423
424struct mlx5_qp_table {
425 /* protect radix tree
426 */
427 spinlock_t lock;
428 struct radix_tree_root tree;
429};
430
431struct mlx5_srq_table {
432 /* protect radix tree
433 */
434 spinlock_t lock;
435 struct radix_tree_root tree;
436};
437
a606b0f6 438struct mlx5_mkey_table {
3bcdb17a
SG		 439 /* protect radix tree
440 */
441 rwlock_t lock;
442 struct radix_tree_root tree;
443};
444
fc50db98
EC		 445struct mlx5_vf_context {
446 int enabled;
447};
448
449struct mlx5_core_sriov {
450 struct mlx5_vf_context *vfs_ctx;
451 int num_vfs;
452 int enabled_vfs;
453};
454
db058a18
SM		 455struct mlx5_irq_info {
456 cpumask_var_t mask;
457 char name[MLX5_MAX_IRQ_NAME];
458};
459
073bb189
SM		 460struct mlx5_eswitch;
461
e126ba97
EC		 462struct mlx5_priv {
463 char name[MLX5_MAX_NAME_LEN];
464 struct mlx5_eq_table eq_table;
db058a18
SM		 465 struct msix_entry *msix_arr;
466 struct mlx5_irq_info *irq_info;
e126ba97
EC		 467 struct mlx5_uuar_info uuari;
468 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
469
470 /* pages stuff */
471 struct workqueue_struct *pg_wq;
472 struct rb_root page_root;
473 int fw_pages;
6aec21f6 474 atomic_t reg_pages;
bf0bf77f 475 struct list_head free_list;
fc50db98 476 int vfs_pages;
e126ba97
EC		 477
478 struct mlx5_core_health health;
479
480 struct mlx5_srq_table srq_table;
481
482 /* start: qp staff */
483 struct mlx5_qp_table qp_table;
484 struct dentry *qp_debugfs;
485 struct dentry *eq_debugfs;
486 struct dentry *cq_debugfs;
487 struct dentry *cmdif_debugfs;
488 /* end: qp staff */
489
490 /* start: cq staff */
491 struct mlx5_cq_table cq_table;
492 /* end: cq staff */
493
a606b0f6
MB		 494 /* start: mkey staff */
495 struct mlx5_mkey_table mkey_table;
496 /* end: mkey staff */
3bcdb17a 497
e126ba97 498 /* start: alloc staff */
311c7c71
SM		 499 /* protect buffer alocation according to numa node */
500 struct mutex alloc_mutex;
501 int numa_node;
502
e126ba97
EC		 503 struct mutex pgdir_mutex;
504 struct list_head pgdir_list;
505 /* end: alloc staff */
506 struct dentry *dbg_root;
507
508 /* protect mkey key part */
509 spinlock_t mkey_lock;
510 u8 mkey_key;
9603b61d
JM		 511
512 struct list_head dev_list;
513 struct list_head ctx_list;
514 spinlock_t ctx_lock;
073bb189
SM		 515
516 struct mlx5_eswitch *eswitch;
fc50db98
EC		 517 struct mlx5_core_sriov sriov;
518 unsigned long pci_dev_data;
25302363
MG		 519 struct mlx5_flow_root_namespace *root_ns;
520 struct mlx5_flow_root_namespace *fdb_root_ns;
e126ba97
EC		 521};
522
89d44f0a
MD		 523enum mlx5_device_state {
524 MLX5_DEVICE_STATE_UP,
525 MLX5_DEVICE_STATE_INTERNAL_ERROR,
526};
527
528enum mlx5_interface_state {
5fc7197d
MD		 529 MLX5_INTERFACE_STATE_DOWN = BIT(0),
530 MLX5_INTERFACE_STATE_UP = BIT(1),
531 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
89d44f0a
MD		 532};
533
534enum mlx5_pci_status {
535 MLX5_PCI_STATUS_DISABLED,
536 MLX5_PCI_STATUS_ENABLED,
537};
538
e126ba97
EC		 539struct mlx5_core_dev {
540 struct pci_dev *pdev;
89d44f0a
MD		 541 /* sync pci state */
542 struct mutex pci_status_mutex;
543 enum mlx5_pci_status pci_status;
e126ba97
EC		 544 u8 rev_id;
545 char board_id[MLX5_BOARD_ID_LEN];
546 struct mlx5_cmd cmd;
938fe83c
SM		 547 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
548 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
549 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 550 phys_addr_t iseg_base;
551 struct mlx5_init_seg __iomem *iseg;
89d44f0a
MD		 552 enum mlx5_device_state state;
553 /* sync interface state */
554 struct mutex intf_state_mutex;
5fc7197d 555 unsigned long intf_state;
e126ba97
EC		 556 void (*event) (struct mlx5_core_dev *dev,
557 enum mlx5_dev_event event,
4d2f9bbb 558 unsigned long param);
e126ba97
EC		 559 struct mlx5_priv priv;
560 struct mlx5_profile *profile;
561 atomic_t num_qps;
f62b8bb8 562 u32 issi;
5a7b27eb
MG		 563#ifdef CONFIG_RFS_ACCEL
564 struct cpu_rmap *rmap;
565#endif
e126ba97
EC		 566};
567
568struct mlx5_db {
569 __be32 *db;
570 union {
571 struct mlx5_db_pgdir *pgdir;
572 struct mlx5_ib_user_db_page *user_page;
573 } u;
574 dma_addr_t dma;
575 int index;
576};
577
578enum {
579 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
580};
581
582enum {
583 MLX5_COMP_EQ_SIZE = 1024,
584};
585
adb0c954
SM		 586enum {
587 MLX5_PTYS_IB = 1 << 0,
588 MLX5_PTYS_EN = 1 << 2,
589};
590
e126ba97
EC		 591struct mlx5_db_pgdir {
592 struct list_head list;
593 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
594 __be32 *db_page;
595 dma_addr_t db_dma;
596};
597
598typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
599
600struct mlx5_cmd_work_ent {
601 struct mlx5_cmd_msg *in;
602 struct mlx5_cmd_msg *out;
746b5583
EC		 603 void *uout;
604 int uout_size;
e126ba97
EC		 605 mlx5_cmd_cbk_t callback;
606 void *context;
746b5583 607 int idx;
e126ba97
EC		 608 struct completion done;
609 struct mlx5_cmd *cmd;
610 struct work_struct work;
611 struct mlx5_cmd_layout *lay;
612 int ret;
613 int page_queue;
614 u8 status;
615 u8 token;
14a70046
TG		 616 u64 ts1;
617 u64 ts2;
746b5583 618 u16 op;
e126ba97
EC		 619};
620
621struct mlx5_pas {
622 u64 pa;
623 u8 log_sz;
624};
625
707c4602 626enum port_state_policy {
eff901d3
EC		 627 MLX5_POLICY_DOWN = 0,
628 MLX5_POLICY_UP = 1,
629 MLX5_POLICY_FOLLOW = 2,
630 MLX5_POLICY_INVALID = 0xffffffff
707c4602
MD		 631};
632
633enum phy_port_state {
634 MLX5_AAA_111
635};
636
637struct mlx5_hca_vport_context {
638 u32 field_select;
639 bool sm_virt_aware;
640 bool has_smi;
641 bool has_raw;
642 enum port_state_policy policy;
643 enum phy_port_state phys_state;
644 enum ib_port_state vport_state;
645 u8 port_physical_state;
646 u64 sys_image_guid;
647 u64 port_guid;
648 u64 node_guid;
649 u32 cap_mask1;
650 u32 cap_mask1_perm;
651 u32 cap_mask2;
652 u32 cap_mask2_perm;
653 u16 lid;
654 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
655 u8 lmc;
656 u8 subnet_timeout;
657 u16 sm_lid;
658 u8 sm_sl;
659 u16 qkey_violation_counter;
660 u16 pkey_violation_counter;
661 bool grh_required;
662};
663
e126ba97
EC		 664static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
665{
e126ba97 666 return buf->direct.buf + offset;
e126ba97
EC		 667}
668
669extern struct workqueue_struct *mlx5_core_wq;
670
671#define STRUCT_FIELD(header, field) \
672 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
673 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
674
e126ba97
EC		 675static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
676{
677 return pci_get_drvdata(pdev);
678}
679
680extern struct dentry *mlx5_debugfs_root;
681
682static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
683{
684 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
685}
686
687static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
688{
689 return ioread32be(&dev->iseg->fw_rev) >> 16;
690}
691
692static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
693{
694 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
695}
696
697static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
698{
699 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
700}
701
702static inline void *mlx5_vzalloc(unsigned long size)
703{
704 void *rtn;
705
706 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
707 if (!rtn)
708 rtn = vzalloc(size);
709 return rtn;
710}
711
3bcdb17a
SG		 712static inline u32 mlx5_base_mkey(const u32 key)
713{
714 return key & 0xffffff00u;
715}
716
e126ba97
EC		 717int mlx5_cmd_init(struct mlx5_core_dev *dev);
718void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
719void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
720void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
721int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 722int mlx5_cmd_status_to_err_v2(void *ptr);
b06e7de8 723int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
e126ba97
EC		 724int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
725 int out_size);
746b5583
EC		 726int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
727 void *out, int out_size, mlx5_cmd_cbk_t callback,
728 void *context);
e126ba97
EC		 729int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
730int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
731int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
732int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
0ba42241
ML		 733int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
734 bool map_wc);
e281682b 735void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
ac6ea6e8
EC		 736void mlx5_health_cleanup(struct mlx5_core_dev *dev);
737int mlx5_health_init(struct mlx5_core_dev *dev);
e126ba97
EC		 738void mlx5_start_health_poll(struct mlx5_core_dev *dev);
739void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
311c7c71
SM		 740int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
741 struct mlx5_buf *buf, int node);
64ffaa21 742int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 743void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
744struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
745 gfp_t flags, int npages);
746void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
747 struct mlx5_cmd_mailbox *head);
748int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
01949d01
HA		 749 struct mlx5_create_srq_mbox_in *in, int inlen,
750 int is_xrc);
e126ba97
EC		 751int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
752int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
753 struct mlx5_query_srq_mbox_out *out);
754int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
755 u16 lwm, int is_srq);
a606b0f6
MB		 756void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
757void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
758int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
759 struct mlx5_core_mkey *mkey,
746b5583
EC		 760 struct mlx5_create_mkey_mbox_in *in, int inlen,
761 mlx5_cmd_cbk_t callback, void *context,
762 struct mlx5_create_mkey_mbox_out *out);
a606b0f6
MB		 763int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
764 struct mlx5_core_mkey *mkey);
765int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
e126ba97 766 struct mlx5_query_mkey_mbox_out *out, int outlen);
a606b0f6 767int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
e126ba97
EC		 768 u32 *mkey);
769int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
770int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
a97e2d86 771int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
f241e749 772 u16 opmod, u8 port);
e126ba97
EC		 773void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
774void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
775int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
776void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
fc50db98
EC		 777int mlx5_sriov_init(struct mlx5_core_dev *dev);
778int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
e126ba97 779void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 780 s32 npages);
cd23b14b 781int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC		 782int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
783void mlx5_register_debugfs(void);
784void mlx5_unregister_debugfs(void);
785int mlx5_eq_init(struct mlx5_core_dev *dev);
786void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
787void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
788void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 789void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e420f0c0
HE		 790#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
791void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
792#endif
e126ba97
EC		 793void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
794struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
020446e0 795void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
e126ba97
EC		 796void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
797int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
798 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
799int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
800int mlx5_start_eqs(struct mlx5_core_dev *dev);
801int mlx5_stop_eqs(struct mlx5_core_dev *dev);
0b6e26ce
DT		 802int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
803 unsigned int *irqn);
e126ba97
EC		 804int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
805int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
806
807int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
808void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
809int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
810 int size_in, void *data_out, int size_out,
811 u16 reg_num, int arg, int write);
adb0c954 812
e126ba97
EC		 813int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
814void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
815int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
816 struct mlx5_query_eq_mbox_out *out, int outlen);
817int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
818void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
819int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
820void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
821int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
311c7c71
SM		 822int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
823 int node);
e126ba97
EC		 824void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
825
e126ba97
EC		 826const char *mlx5_command_str(int command);
827int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
828void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 829int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
830 int npsvs, u32 *sig_index);
831int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 832void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE		 833int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
834 struct mlx5_odp_caps *odp_caps);
1c64bf6f
MY		 835int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
836 u8 port_num, void *out, size_t sz);
e126ba97 837
e3297246
EC		 838static inline int fw_initializing(struct mlx5_core_dev *dev)
839{
840 return ioread32be(&dev->iseg->initializing) >> 31;
841}
842
e126ba97
EC		 843static inline u32 mlx5_mkey_to_idx(u32 mkey)
844{
845 return mkey >> 8;
846}
847
848static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
849{
850 return mkey_idx << 8;
851}
852
746b5583
EC		 853static inline u8 mlx5_mkey_variant(u32 mkey)
854{
855 return mkey & 0xff;
856}
857
e126ba97
EC		 858enum {
859 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 860 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC		 861};
862
863enum {
864 MAX_MR_CACHE_ENTRIES = 16,
865};
866
64613d94
SM		 867enum {
868 MLX5_INTERFACE_PROTOCOL_IB = 0,
869 MLX5_INTERFACE_PROTOCOL_ETH = 1,
870};
871
9603b61d
JM		 872struct mlx5_interface {
873 void * (*add)(struct mlx5_core_dev *dev);
874 void (*remove)(struct mlx5_core_dev *dev, void *context);
875 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 876 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 877 void * (*get_dev)(void *context);
878 int protocol;
9603b61d
JM		 879 struct list_head list;
880};
881
64613d94 882void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM		 883int mlx5_register_interface(struct mlx5_interface *intf);
884void mlx5_unregister_interface(struct mlx5_interface *intf);
211e6c80 885int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
9603b61d 886
e126ba97
EC		 887struct mlx5_profile {
888 u64 mask;
f241e749 889 u8 log_max_qp;
e126ba97
EC		 890 struct {
891 int size;
892 int limit;
893 } mr_cache[MAX_MR_CACHE_ENTRIES];
894};
895
fc50db98
EC		 896enum {
897 MLX5_PCI_DEV_IS_VF = 1 << 0,
898};
899
900static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
901{
902 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
903}
904
707c4602
MD		 905static inline int mlx5_get_gid_table_len(u16 param)
906{
907 if (param > 4) {
908 pr_warn("gid table length is zero\n");
909 return 0;
910 }
911
912 return 8 * (1 << param);
913}
914
020446e0
EC		 915enum {
916 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
917};
918
e126ba97 919#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)