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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 | 43 | #include <linux/vmalloc.h> |
792c4e9d | 44 | #include <linux/xarray.h> |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
20902be4 | 49 | #include <linux/notifier.h> |
94f3e14e | 50 | #include <linux/refcount.h> |
6ecde51d | 51 | |
e126ba97 EC |
52 | #include <linux/mlx5/device.h> |
53 | #include <linux/mlx5/doorbell.h> | |
41069256 | 54 | #include <linux/mlx5/eq.h> |
7c39afb3 FD |
55 | #include <linux/timecounter.h> |
56 | #include <linux/ptp_clock_kernel.h> | |
1e34f3ef | 57 | #include <net/devlink.h> |
e126ba97 EC |
58 | |
59 | enum { | |
60 | MLX5_BOARD_ID_LEN = 64, | |
e126ba97 EC |
61 | }; |
62 | ||
63 | enum { | |
64 | /* one minute for the sake of bringup. Generally, commands must always | |
65 | * complete and we may need to increase this timeout value | |
66 | */ | |
6b6c07bd | 67 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
68 | MLX5_CMD_WQ_MAX_NAME = 32, |
69 | }; | |
70 | ||
71 | enum { | |
72 | CMD_OWNER_SW = 0x0, | |
73 | CMD_OWNER_HW = 0x1, | |
74 | CMD_STATUS_SUCCESS = 0, | |
75 | }; | |
76 | ||
77 | enum mlx5_sqp_t { | |
78 | MLX5_SQP_SMI = 0, | |
79 | MLX5_SQP_GSI = 1, | |
80 | MLX5_SQP_IEEE_1588 = 2, | |
81 | MLX5_SQP_SNIFFER = 3, | |
82 | MLX5_SQP_SYNC_UMR = 4, | |
83 | }; | |
84 | ||
85 | enum { | |
86 | MLX5_MAX_PORTS = 2, | |
87 | }; | |
88 | ||
e126ba97 | 89 | enum { |
a60109dc YC |
90 | MLX5_ATOMIC_MODE_OFFSET = 16, |
91 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
92 | MLX5_ATOMIC_MODE_CX = 2, | |
93 | MLX5_ATOMIC_MODE_8B = 3, | |
94 | MLX5_ATOMIC_MODE_16B = 4, | |
95 | MLX5_ATOMIC_MODE_32B = 5, | |
96 | MLX5_ATOMIC_MODE_64B = 6, | |
97 | MLX5_ATOMIC_MODE_128B = 7, | |
98 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
99 | }; |
100 | ||
e126ba97 | 101 | enum { |
415a64aa | 102 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
103 | MLX5_REG_QETCR = 0x4005, |
104 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 105 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 106 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
107 | MLX5_REG_DCBX_PARAM = 0x4020, |
108 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
109 | MLX5_REG_FPGA_CAP = 0x4022, |
110 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 111 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
0b9055a1 | 112 | MLX5_REG_CORE_DUMP = 0x402e, |
e126ba97 EC |
113 | MLX5_REG_PCAP = 0x5001, |
114 | MLX5_REG_PMTU = 0x5003, | |
115 | MLX5_REG_PTYS = 0x5004, | |
116 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 117 | MLX5_REG_PFCC = 0x5007, |
efea389d | 118 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
119 | MLX5_REG_PPTB = 0x500b, |
120 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
121 | MLX5_REG_PMAOS = 0x5012, |
122 | MLX5_REG_PUDE = 0x5009, | |
123 | MLX5_REG_PMPE = 0x5010, | |
124 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 125 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 126 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 127 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 128 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 129 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
130 | MLX5_REG_NODE_DESC = 0x6001, |
131 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 132 | MLX5_REG_MCIA = 0x9014, |
06939536 | 133 | MLX5_REG_MFRL = 0x9028, |
da54d24e | 134 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
135 | MLX5_REG_MTRC_CAP = 0x9040, |
136 | MLX5_REG_MTRC_CONF = 0x9041, | |
137 | MLX5_REG_MTRC_STDB = 0x9042, | |
138 | MLX5_REG_MTRC_CTRL = 0x9043, | |
4039049b | 139 | MLX5_REG_MPEIN = 0x9050, |
8ed1a630 | 140 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
141 | MLX5_REG_MTPPS = 0x9053, |
142 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 143 | MLX5_REG_MPEGC = 0x9056, |
a82e0b5b | 144 | MLX5_REG_MCQS = 0x9060, |
47176289 OG |
145 | MLX5_REG_MCQI = 0x9061, |
146 | MLX5_REG_MCC = 0x9062, | |
147 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 148 | MLX5_REG_MCAM = 0x907f, |
bab58ba1 | 149 | MLX5_REG_MIRC = 0x9162, |
609b8272 | 150 | MLX5_REG_RESOURCE_DUMP = 0xC000, |
e126ba97 EC |
151 | }; |
152 | ||
415a64aa HN |
153 | enum mlx5_qpts_trust_state { |
154 | MLX5_QPTS_TRUST_PCP = 1, | |
155 | MLX5_QPTS_TRUST_DSCP = 2, | |
156 | }; | |
157 | ||
341c5ee2 HN |
158 | enum mlx5_dcbx_oper_mode { |
159 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
160 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
161 | }; | |
162 | ||
da7525d2 EBE |
163 | enum { |
164 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
165 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
166 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
167 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
168 | }; |
169 | ||
e420f0c0 HE |
170 | enum mlx5_page_fault_resume_flags { |
171 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
172 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
173 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
174 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
175 | }; | |
176 | ||
e126ba97 EC |
177 | enum dbg_rsc_type { |
178 | MLX5_DBG_RSC_QP, | |
179 | MLX5_DBG_RSC_EQ, | |
180 | MLX5_DBG_RSC_CQ, | |
181 | }; | |
182 | ||
7ecf6d8f BW |
183 | enum port_state_policy { |
184 | MLX5_POLICY_DOWN = 0, | |
185 | MLX5_POLICY_UP = 1, | |
186 | MLX5_POLICY_FOLLOW = 2, | |
187 | MLX5_POLICY_INVALID = 0xffffffff | |
188 | }; | |
189 | ||
386e75af HN |
190 | enum mlx5_coredev_type { |
191 | MLX5_COREDEV_PF, | |
192 | MLX5_COREDEV_VF | |
193 | }; | |
194 | ||
e126ba97 | 195 | struct mlx5_field_desc { |
e126ba97 EC |
196 | int i; |
197 | }; | |
198 | ||
199 | struct mlx5_rsc_debug { | |
200 | struct mlx5_core_dev *dev; | |
201 | void *object; | |
202 | enum dbg_rsc_type type; | |
203 | struct dentry *root; | |
b6ca09cb | 204 | struct mlx5_field_desc fields[]; |
e126ba97 EC |
205 | }; |
206 | ||
207 | enum mlx5_dev_event { | |
58d180b3 | 208 | MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ |
6997b1c9 | 209 | MLX5_DEV_EVENT_PORT_AFFINITY = 129, |
e126ba97 EC |
210 | }; |
211 | ||
4c916a79 | 212 | enum mlx5_port_status { |
6fa1bcab AS |
213 | MLX5_PORT_UP = 1, |
214 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
215 | }; |
216 | ||
f7936ddd EBE |
217 | enum mlx5_cmdif_state { |
218 | MLX5_CMDIF_STATE_UNINITIALIZED, | |
219 | MLX5_CMDIF_STATE_UP, | |
220 | MLX5_CMDIF_STATE_DOWN, | |
221 | }; | |
222 | ||
e126ba97 EC |
223 | struct mlx5_cmd_first { |
224 | __be32 data[4]; | |
225 | }; | |
226 | ||
227 | struct mlx5_cmd_msg { | |
228 | struct list_head list; | |
0ac3ea70 | 229 | struct cmd_msg_cache *parent; |
e126ba97 EC |
230 | u32 len; |
231 | struct mlx5_cmd_first first; | |
232 | struct mlx5_cmd_mailbox *next; | |
233 | }; | |
234 | ||
235 | struct mlx5_cmd_debug { | |
236 | struct dentry *dbg_root; | |
e126ba97 EC |
237 | void *in_msg; |
238 | void *out_msg; | |
239 | u8 status; | |
240 | u16 inlen; | |
241 | u16 outlen; | |
242 | }; | |
243 | ||
0ac3ea70 | 244 | struct cmd_msg_cache { |
e126ba97 EC |
245 | /* protect block chain allocations |
246 | */ | |
247 | spinlock_t lock; | |
248 | struct list_head head; | |
0ac3ea70 MHY |
249 | unsigned int max_inbox_size; |
250 | unsigned int num_ent; | |
e126ba97 EC |
251 | }; |
252 | ||
0ac3ea70 MHY |
253 | enum { |
254 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
255 | }; |
256 | ||
257 | struct mlx5_cmd_stats { | |
258 | u64 sum; | |
259 | u64 n; | |
260 | struct dentry *root; | |
e126ba97 EC |
261 | /* protect command average calculations */ |
262 | spinlock_t lock; | |
263 | }; | |
264 | ||
265 | struct mlx5_cmd { | |
71edc69c SM |
266 | struct mlx5_nb nb; |
267 | ||
f7936ddd | 268 | enum mlx5_cmdif_state state; |
64599cca EC |
269 | void *cmd_alloc_buf; |
270 | dma_addr_t alloc_dma; | |
271 | int alloc_size; | |
e126ba97 EC |
272 | void *cmd_buf; |
273 | dma_addr_t dma; | |
274 | u16 cmdif_rev; | |
275 | u8 log_sz; | |
276 | u8 log_stride; | |
277 | int max_reg_cmds; | |
278 | int events; | |
279 | u32 __iomem *vector; | |
280 | ||
281 | /* protect command queue allocations | |
282 | */ | |
283 | spinlock_t alloc_lock; | |
284 | ||
285 | /* protect token allocations | |
286 | */ | |
287 | spinlock_t token_lock; | |
288 | u8 token; | |
289 | unsigned long bitmask; | |
290 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
291 | struct workqueue_struct *wq; | |
292 | struct semaphore sem; | |
293 | struct semaphore pages_sem; | |
294 | int mode; | |
d43b7007 | 295 | u16 allowed_opcode; |
e126ba97 | 296 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; |
18c90df9 | 297 | struct dma_pool *pool; |
e126ba97 | 298 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 299 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 | 300 | int checksum_disabled; |
2553f421 | 301 | struct mlx5_cmd_stats *stats; |
e126ba97 EC |
302 | }; |
303 | ||
304 | struct mlx5_port_caps { | |
305 | int gid_table_len; | |
306 | int pkey_table_len; | |
938fe83c | 307 | u8 ext_port_cap; |
c43f1112 | 308 | bool has_smi; |
e126ba97 EC |
309 | }; |
310 | ||
311 | struct mlx5_cmd_mailbox { | |
312 | void *buf; | |
313 | dma_addr_t dma; | |
314 | struct mlx5_cmd_mailbox *next; | |
315 | }; | |
316 | ||
317 | struct mlx5_buf_list { | |
318 | void *buf; | |
319 | dma_addr_t map; | |
320 | }; | |
321 | ||
1c1b5228 TT |
322 | struct mlx5_frag_buf { |
323 | struct mlx5_buf_list *frags; | |
324 | int npages; | |
325 | int size; | |
326 | u8 page_shift; | |
327 | }; | |
328 | ||
388ca8be | 329 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 330 | struct mlx5_buf_list *frags; |
388ca8be | 331 | u32 sz_m1; |
8d71e818 | 332 | u16 frag_sz_m1; |
a0903622 | 333 | u16 strides_offset; |
388ca8be YC |
334 | u8 log_sz; |
335 | u8 log_stride; | |
336 | u8 log_frag_strides; | |
337 | }; | |
338 | ||
3121e3c4 SG |
339 | struct mlx5_core_psv { |
340 | u32 psv_idx; | |
341 | struct psv_layout { | |
342 | u32 pd; | |
343 | u16 syndrome; | |
344 | u16 reserved; | |
345 | u16 bg; | |
346 | u16 app_tag; | |
347 | u32 ref_tag; | |
348 | } psv; | |
349 | }; | |
350 | ||
351 | struct mlx5_core_sig_ctx { | |
352 | struct mlx5_core_psv psv_memory; | |
353 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
354 | struct ib_sig_err err_item; |
355 | bool sig_status_checked; | |
356 | bool sig_err_exists; | |
357 | u32 sigerr_count; | |
3121e3c4 | 358 | }; |
e126ba97 | 359 | |
aa8e08d2 AK |
360 | enum { |
361 | MLX5_MKEY_MR = 1, | |
362 | MLX5_MKEY_MW, | |
534fd7aa | 363 | MLX5_MKEY_INDIRECT_DEVX, |
aa8e08d2 AK |
364 | }; |
365 | ||
a606b0f6 | 366 | struct mlx5_core_mkey { |
e126ba97 EC |
367 | u64 iova; |
368 | u64 size; | |
369 | u32 key; | |
370 | u32 pd; | |
aa8e08d2 | 371 | u32 type; |
e126ba97 EC |
372 | }; |
373 | ||
d9aaed83 AK |
374 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
375 | ||
5903325a | 376 | enum mlx5_res_type { |
e2013b21 | 377 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
378 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
379 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
380 | MLX5_RES_SRQ = 3, | |
381 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 382 | MLX5_RES_XRQ = 5, |
57cda166 | 383 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
384 | }; |
385 | ||
386 | struct mlx5_core_rsc_common { | |
387 | enum mlx5_res_type res; | |
94f3e14e | 388 | refcount_t refcount; |
5903325a EC |
389 | struct completion free; |
390 | }; | |
391 | ||
a6d51b68 | 392 | struct mlx5_uars_page { |
e126ba97 | 393 | void __iomem *map; |
a6d51b68 EC |
394 | bool wc; |
395 | u32 index; | |
396 | struct list_head list; | |
397 | unsigned int bfregs; | |
398 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
399 | unsigned long *fp_bitmap; | |
400 | unsigned int reg_avail; | |
401 | unsigned int fp_avail; | |
402 | struct kref ref_count; | |
403 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
404 | }; |
405 | ||
a6d51b68 EC |
406 | struct mlx5_bfreg_head { |
407 | /* protect blue flame registers allocations */ | |
408 | struct mutex lock; | |
409 | struct list_head list; | |
410 | }; | |
411 | ||
412 | struct mlx5_bfreg_data { | |
413 | struct mlx5_bfreg_head reg_head; | |
414 | struct mlx5_bfreg_head wc_head; | |
415 | }; | |
416 | ||
417 | struct mlx5_sq_bfreg { | |
418 | void __iomem *map; | |
419 | struct mlx5_uars_page *up; | |
420 | bool wc; | |
421 | u32 index; | |
422 | unsigned int offset; | |
423 | }; | |
e126ba97 EC |
424 | |
425 | struct mlx5_core_health { | |
426 | struct health_buffer __iomem *health; | |
427 | __be32 __iomem *health_counter; | |
428 | struct timer_list timer; | |
e126ba97 EC |
429 | u32 prev; |
430 | int miss_counter; | |
d1bf0e2c | 431 | u8 synd; |
63cbc552 | 432 | u32 fatal_error; |
8b9d8baa | 433 | u32 crdump_size; |
05ac2c0b MHY |
434 | /* wq spinlock to synchronize draining */ |
435 | spinlock_t wq_lock; | |
ac6ea6e8 | 436 | struct workqueue_struct *wq; |
05ac2c0b | 437 | unsigned long flags; |
b3bd076f | 438 | struct work_struct fatal_report_work; |
d1bf0e2c | 439 | struct work_struct report_work; |
04c0c1ab | 440 | struct delayed_work recover_work; |
1e34f3ef | 441 | struct devlink_health_reporter *fw_reporter; |
96c82cdf | 442 | struct devlink_health_reporter *fw_fatal_reporter; |
e126ba97 EC |
443 | }; |
444 | ||
e126ba97 | 445 | struct mlx5_qp_table { |
451be51c | 446 | struct notifier_block nb; |
221c14f3 | 447 | |
e126ba97 EC |
448 | /* protect radix tree |
449 | */ | |
450 | spinlock_t lock; | |
451 | struct radix_tree_root tree; | |
452 | }; | |
453 | ||
fc50db98 EC |
454 | struct mlx5_vf_context { |
455 | int enabled; | |
7ecf6d8f BW |
456 | u64 port_guid; |
457 | u64 node_guid; | |
4bbd4923 DG |
458 | /* Valid bits are used to validate administrative guid only. |
459 | * Enabled after ndo_set_vf_guid | |
460 | */ | |
461 | u8 port_guid_valid:1; | |
462 | u8 node_guid_valid:1; | |
7ecf6d8f | 463 | enum port_state_policy policy; |
fc50db98 EC |
464 | }; |
465 | ||
466 | struct mlx5_core_sriov { | |
467 | struct mlx5_vf_context *vfs_ctx; | |
468 | int num_vfs; | |
86eec50b | 469 | u16 max_vfs; |
fc50db98 EC |
470 | }; |
471 | ||
558101f1 GT |
472 | struct mlx5_fc_pool { |
473 | struct mlx5_core_dev *dev; | |
474 | struct mutex pool_lock; /* protects pool lists */ | |
475 | struct list_head fully_used; | |
476 | struct list_head partially_used; | |
477 | struct list_head unused; | |
478 | int available_fcs; | |
479 | int used_fcs; | |
480 | int threshold; | |
481 | }; | |
482 | ||
43a335e0 | 483 | struct mlx5_fc_stats { |
12d6066c VB |
484 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
485 | struct idr counters_idr; | |
9aff93d7 | 486 | struct list_head counters; |
83033688 | 487 | struct llist_head addlist; |
6e5e2283 | 488 | struct llist_head dellist; |
43a335e0 AV |
489 | |
490 | struct workqueue_struct *wq; | |
491 | struct delayed_work work; | |
492 | unsigned long next_query; | |
f6dfb4c3 | 493 | unsigned long sampling_interval; /* jiffies */ |
6f06e04b | 494 | u32 *bulk_query_out; |
558101f1 | 495 | struct mlx5_fc_pool fc_pool; |
43a335e0 AV |
496 | }; |
497 | ||
69c1280b | 498 | struct mlx5_events; |
eeb66cdb | 499 | struct mlx5_mpfs; |
073bb189 | 500 | struct mlx5_eswitch; |
7907f23a | 501 | struct mlx5_lag; |
fadd59fc | 502 | struct mlx5_devcom; |
f2f3df55 | 503 | struct mlx5_eq_table; |
561aa15a | 504 | struct mlx5_irq_table; |
073bb189 | 505 | |
05d3ac97 BW |
506 | struct mlx5_rate_limit { |
507 | u32 rate; | |
508 | u32 max_burst_sz; | |
509 | u16 typical_pkt_sz; | |
510 | }; | |
511 | ||
1466cc5b | 512 | struct mlx5_rl_entry { |
1326034b YH |
513 | u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)]; |
514 | u16 index; | |
515 | u64 refcount; | |
516 | u16 uid; | |
517 | u8 dedicated : 1; | |
1466cc5b YP |
518 | }; |
519 | ||
520 | struct mlx5_rl_table { | |
521 | /* protect rate limit table */ | |
522 | struct mutex rl_lock; | |
523 | u16 max_size; | |
524 | u32 max_rate; | |
525 | u32 min_rate; | |
526 | struct mlx5_rl_entry *rl_entry; | |
527 | }; | |
528 | ||
80f09dfc MG |
529 | struct mlx5_core_roce { |
530 | struct mlx5_flow_table *ft; | |
531 | struct mlx5_flow_group *fg; | |
532 | struct mlx5_flow_handle *allow_rule; | |
533 | }; | |
534 | ||
e126ba97 | 535 | struct mlx5_priv { |
561aa15a YA |
536 | /* IRQ table valid only for real pci devices PF or VF */ |
537 | struct mlx5_irq_table *irq_table; | |
f2f3df55 | 538 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
539 | |
540 | /* pages stuff */ | |
0cf53c12 | 541 | struct mlx5_nb pg_nb; |
e126ba97 EC |
542 | struct workqueue_struct *pg_wq; |
543 | struct rb_root page_root; | |
544 | int fw_pages; | |
6aec21f6 | 545 | atomic_t reg_pages; |
bf0bf77f | 546 | struct list_head free_list; |
fc50db98 | 547 | int vfs_pages; |
591905ba | 548 | int peer_pf_pages; |
e126ba97 EC |
549 | |
550 | struct mlx5_core_health health; | |
551 | ||
e126ba97 | 552 | /* start: qp staff */ |
e126ba97 EC |
553 | struct dentry *qp_debugfs; |
554 | struct dentry *eq_debugfs; | |
555 | struct dentry *cq_debugfs; | |
556 | struct dentry *cmdif_debugfs; | |
557 | /* end: qp staff */ | |
558 | ||
e126ba97 | 559 | /* start: alloc staff */ |
311c7c71 SM |
560 | /* protect buffer alocation according to numa node */ |
561 | struct mutex alloc_mutex; | |
562 | int numa_node; | |
563 | ||
e126ba97 EC |
564 | struct mutex pgdir_mutex; |
565 | struct list_head pgdir_list; | |
566 | /* end: alloc staff */ | |
567 | struct dentry *dbg_root; | |
568 | ||
9603b61d JM |
569 | struct list_head dev_list; |
570 | struct list_head ctx_list; | |
571 | spinlock_t ctx_lock; | |
02039fb6 | 572 | struct mlx5_events *events; |
97834eba | 573 | |
fba53f7b | 574 | struct mlx5_flow_steering *steering; |
eeb66cdb | 575 | struct mlx5_mpfs *mpfs; |
073bb189 | 576 | struct mlx5_eswitch *eswitch; |
fc50db98 | 577 | struct mlx5_core_sriov sriov; |
7907f23a | 578 | struct mlx5_lag *lag; |
fadd59fc | 579 | struct mlx5_devcom *devcom; |
80f09dfc | 580 | struct mlx5_core_roce roce; |
43a335e0 | 581 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 582 | struct mlx5_rl_table rl_table; |
d4eb4cd7 | 583 | |
a6d51b68 | 584 | struct mlx5_bfreg_data bfregs; |
01187175 | 585 | struct mlx5_uars_page *uar; |
e126ba97 EC |
586 | }; |
587 | ||
89d44f0a | 588 | enum mlx5_device_state { |
3e5b72ac | 589 | MLX5_DEVICE_STATE_UNINITIALIZED, |
89d44f0a MD |
590 | MLX5_DEVICE_STATE_UP, |
591 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
592 | }; | |
593 | ||
594 | enum mlx5_interface_state { | |
b3cb5388 | 595 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
596 | }; |
597 | ||
598 | enum mlx5_pci_status { | |
599 | MLX5_PCI_STATUS_DISABLED, | |
600 | MLX5_PCI_STATUS_ENABLED, | |
601 | }; | |
602 | ||
d9aaed83 AK |
603 | enum mlx5_pagefault_type_flags { |
604 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
605 | MLX5_PFAULT_WRITE = 1 << 1, | |
606 | MLX5_PFAULT_RDMA = 1 << 2, | |
607 | }; | |
608 | ||
b50d292b | 609 | struct mlx5_td { |
80a2a902 YA |
610 | /* protects tirs list changes while tirs refresh */ |
611 | struct mutex list_lock; | |
b50d292b HHZ |
612 | struct list_head tirs_list; |
613 | u32 tdn; | |
614 | }; | |
615 | ||
616 | struct mlx5e_resources { | |
b50d292b HHZ |
617 | u32 pdn; |
618 | struct mlx5_td td; | |
619 | struct mlx5_core_mkey mkey; | |
aff26157 | 620 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
621 | }; |
622 | ||
c9b9dcb4 AL |
623 | enum mlx5_sw_icm_type { |
624 | MLX5_SW_ICM_TYPE_STEERING, | |
625 | MLX5_SW_ICM_TYPE_HEADER_MODIFY, | |
626 | }; | |
627 | ||
52ec462e IT |
628 | #define MLX5_MAX_RESERVED_GIDS 8 |
629 | ||
630 | struct mlx5_rsvd_gids { | |
631 | unsigned int start; | |
632 | unsigned int count; | |
633 | struct ida ida; | |
634 | }; | |
635 | ||
7c39afb3 FD |
636 | #define MAX_PIN_NUM 8 |
637 | struct mlx5_pps { | |
638 | u8 pin_caps[MAX_PIN_NUM]; | |
639 | struct work_struct out_work; | |
640 | u64 start[MAX_PIN_NUM]; | |
641 | u8 enabled; | |
642 | }; | |
643 | ||
644 | struct mlx5_clock { | |
41069256 SM |
645 | struct mlx5_core_dev *mdev; |
646 | struct mlx5_nb pps_nb; | |
64109f1d | 647 | seqlock_t lock; |
7c39afb3 FD |
648 | struct cyclecounter cycles; |
649 | struct timecounter tc; | |
650 | struct hwtstamp_config hwtstamp_config; | |
651 | u32 nominal_c_mult; | |
652 | unsigned long overflow_period; | |
653 | struct delayed_work overflow_work; | |
654 | struct ptp_clock *ptp; | |
655 | struct ptp_clock_info ptp_info; | |
656 | struct mlx5_pps pps_info; | |
657 | }; | |
658 | ||
c9b9dcb4 | 659 | struct mlx5_dm; |
f53aaa31 | 660 | struct mlx5_fw_tracer; |
358aa5ce | 661 | struct mlx5_vxlan; |
0ccc171e | 662 | struct mlx5_geneve; |
87175120 | 663 | struct mlx5_hv_vhca; |
f53aaa31 | 664 | |
c9b9dcb4 AL |
665 | #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) |
666 | #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) | |
667 | ||
e126ba97 | 668 | struct mlx5_core_dev { |
27b942fb | 669 | struct device *device; |
386e75af | 670 | enum mlx5_coredev_type coredev_type; |
e126ba97 | 671 | struct pci_dev *pdev; |
89d44f0a MD |
672 | /* sync pci state */ |
673 | struct mutex pci_status_mutex; | |
674 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
675 | u8 rev_id; |
676 | char board_id[MLX5_BOARD_ID_LEN]; | |
677 | struct mlx5_cmd cmd; | |
938fe83c | 678 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 679 | struct { |
701052c5 GP |
680 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
681 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 | 682 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
932ef155 | 683 | u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; |
99d3cd27 | 684 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 685 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
591905ba | 686 | u8 embedded_cpu; |
71862561 | 687 | } caps; |
59c9d35e | 688 | u64 sys_image_guid; |
e126ba97 EC |
689 | phys_addr_t iseg_base; |
690 | struct mlx5_init_seg __iomem *iseg; | |
aa8106f1 | 691 | phys_addr_t bar_addr; |
89d44f0a MD |
692 | enum mlx5_device_state state; |
693 | /* sync interface state */ | |
694 | struct mutex intf_state_mutex; | |
5fc7197d | 695 | unsigned long intf_state; |
e126ba97 EC |
696 | struct mlx5_priv priv; |
697 | struct mlx5_profile *profile; | |
f62b8bb8 | 698 | u32 issi; |
b50d292b | 699 | struct mlx5e_resources mlx5e_res; |
c9b9dcb4 | 700 | struct mlx5_dm *dm; |
358aa5ce | 701 | struct mlx5_vxlan *vxlan; |
0ccc171e | 702 | struct mlx5_geneve *geneve; |
52ec462e IT |
703 | struct { |
704 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 705 | u32 roce_en; |
52ec462e | 706 | } roce; |
e29341fb IT |
707 | #ifdef CONFIG_MLX5_FPGA |
708 | struct mlx5_fpga_device *fpga; | |
5a7b27eb | 709 | #endif |
7c39afb3 | 710 | struct mlx5_clock clock; |
24d33d2c | 711 | struct mlx5_ib_clock_info *clock_info; |
f53aaa31 | 712 | struct mlx5_fw_tracer *tracer; |
12206b17 | 713 | struct mlx5_rsc_dump *rsc_dump; |
b25bbc2f | 714 | u32 vsc_addr; |
87175120 | 715 | struct mlx5_hv_vhca *hv_vhca; |
e126ba97 EC |
716 | }; |
717 | ||
718 | struct mlx5_db { | |
719 | __be32 *db; | |
720 | union { | |
721 | struct mlx5_db_pgdir *pgdir; | |
722 | struct mlx5_ib_user_db_page *user_page; | |
723 | } u; | |
724 | dma_addr_t dma; | |
725 | int index; | |
726 | }; | |
727 | ||
e126ba97 EC |
728 | enum { |
729 | MLX5_COMP_EQ_SIZE = 1024, | |
730 | }; | |
731 | ||
adb0c954 SM |
732 | enum { |
733 | MLX5_PTYS_IB = 1 << 0, | |
734 | MLX5_PTYS_EN = 1 << 2, | |
735 | }; | |
736 | ||
e126ba97 EC |
737 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
738 | ||
73dd3a48 MHY |
739 | enum { |
740 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
741 | }; | |
742 | ||
e126ba97 | 743 | struct mlx5_cmd_work_ent { |
73dd3a48 | 744 | unsigned long state; |
e126ba97 EC |
745 | struct mlx5_cmd_msg *in; |
746 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
747 | void *uout; |
748 | int uout_size; | |
e126ba97 | 749 | mlx5_cmd_cbk_t callback; |
65ee6708 | 750 | struct delayed_work cb_timeout_work; |
e126ba97 | 751 | void *context; |
746b5583 | 752 | int idx; |
17d00e83 | 753 | struct completion handling; |
e126ba97 EC |
754 | struct completion done; |
755 | struct mlx5_cmd *cmd; | |
756 | struct work_struct work; | |
757 | struct mlx5_cmd_layout *lay; | |
758 | int ret; | |
759 | int page_queue; | |
760 | u8 status; | |
761 | u8 token; | |
14a70046 TG |
762 | u64 ts1; |
763 | u64 ts2; | |
746b5583 | 764 | u16 op; |
4525abea | 765 | bool polling; |
e126ba97 EC |
766 | }; |
767 | ||
768 | struct mlx5_pas { | |
769 | u64 pa; | |
770 | u8 log_sz; | |
771 | }; | |
772 | ||
707c4602 MD |
773 | enum phy_port_state { |
774 | MLX5_AAA_111 | |
775 | }; | |
776 | ||
777 | struct mlx5_hca_vport_context { | |
778 | u32 field_select; | |
779 | bool sm_virt_aware; | |
780 | bool has_smi; | |
781 | bool has_raw; | |
782 | enum port_state_policy policy; | |
783 | enum phy_port_state phys_state; | |
784 | enum ib_port_state vport_state; | |
785 | u8 port_physical_state; | |
786 | u64 sys_image_guid; | |
787 | u64 port_guid; | |
788 | u64 node_guid; | |
789 | u32 cap_mask1; | |
790 | u32 cap_mask1_perm; | |
4106a758 MG |
791 | u16 cap_mask2; |
792 | u16 cap_mask2_perm; | |
707c4602 MD |
793 | u16 lid; |
794 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
795 | u8 lmc; | |
796 | u8 subnet_timeout; | |
797 | u16 sm_lid; | |
798 | u8 sm_sl; | |
799 | u16 qkey_violation_counter; | |
800 | u16 pkey_violation_counter; | |
801 | bool grh_required; | |
802 | }; | |
803 | ||
388ca8be | 804 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 805 | { |
388ca8be | 806 | return buf->frags->buf + offset; |
e126ba97 EC |
807 | } |
808 | ||
e126ba97 EC |
809 | #define STRUCT_FIELD(header, field) \ |
810 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
811 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
812 | ||
e126ba97 EC |
813 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
814 | { | |
815 | return pci_get_drvdata(pdev); | |
816 | } | |
817 | ||
818 | extern struct dentry *mlx5_debugfs_root; | |
819 | ||
820 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
821 | { | |
822 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
823 | } | |
824 | ||
825 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
826 | { | |
827 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
828 | } | |
829 | ||
830 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
831 | { | |
832 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
833 | } | |
834 | ||
3bcdb17a SG |
835 | static inline u32 mlx5_base_mkey(const u32 key) |
836 | { | |
837 | return key & 0xffffff00u; | |
838 | } | |
839 | ||
4972e6fa TT |
840 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
841 | u8 log_stride, u8 log_sz, | |
a0903622 | 842 | u16 strides_offset, |
d7037ad7 | 843 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 844 | { |
4972e6fa | 845 | fbc->frags = frags; |
3a2f7033 TT |
846 | fbc->log_stride = log_stride; |
847 | fbc->log_sz = log_sz; | |
388ca8be YC |
848 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
849 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
850 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
851 | fbc->strides_offset = strides_offset; |
852 | } | |
853 | ||
4972e6fa TT |
854 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
855 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
856 | struct mlx5_frag_buf_ctrl *fbc) |
857 | { | |
4972e6fa | 858 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
859 | } |
860 | ||
388ca8be YC |
861 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
862 | u32 ix) | |
863 | { | |
d7037ad7 TT |
864 | unsigned int frag; |
865 | ||
866 | ix += fbc->strides_offset; | |
867 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 868 | |
4972e6fa | 869 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
870 | } |
871 | ||
37fdffb2 TT |
872 | static inline u32 |
873 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
874 | { | |
875 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
876 | ||
877 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
878 | } | |
879 | ||
d43b7007 EBE |
880 | enum { |
881 | CMD_ALLOWED_OPCODE_ALL, | |
882 | }; | |
883 | ||
e126ba97 EC |
884 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
885 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
f7936ddd EBE |
886 | void mlx5_cmd_set_state(struct mlx5_core_dev *dev, |
887 | enum mlx5_cmdif_state cmdif_state); | |
e126ba97 EC |
888 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); |
889 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
d43b7007 | 890 | void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode); |
c4f287c4 | 891 | |
e355477e JG |
892 | struct mlx5_async_ctx { |
893 | struct mlx5_core_dev *dev; | |
894 | atomic_t num_inflight; | |
895 | struct wait_queue_head wait; | |
896 | }; | |
897 | ||
898 | struct mlx5_async_work; | |
899 | ||
900 | typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); | |
901 | ||
902 | struct mlx5_async_work { | |
903 | struct mlx5_async_ctx *ctx; | |
904 | mlx5_async_cbk_t user_callback; | |
905 | }; | |
906 | ||
907 | void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, | |
908 | struct mlx5_async_ctx *ctx); | |
909 | void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); | |
910 | int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, | |
911 | void *out, int out_size, mlx5_async_cbk_t callback, | |
912 | struct mlx5_async_work *work); | |
913 | ||
e126ba97 EC |
914 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
915 | int out_size); | |
bb7fc863 LR |
916 | |
917 | #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \ | |
918 | ({ \ | |
919 | mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \ | |
920 | MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \ | |
921 | }) | |
922 | ||
923 | #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \ | |
924 | ({ \ | |
925 | u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \ | |
926 | mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \ | |
927 | }) | |
928 | ||
4525abea MD |
929 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
930 | void *out, int out_size); | |
c4f287c4 SM |
931 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
932 | ||
933 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
934 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
935 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
52c368dc | 936 | void mlx5_health_flush(struct mlx5_core_dev *dev); |
ac6ea6e8 EC |
937 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
938 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 939 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 940 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 941 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 942 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
388ca8be YC |
943 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, |
944 | int size, struct mlx5_frag_buf *buf); | |
945 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
946 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
947 | struct mlx5_frag_buf *buf, int node); | |
948 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
949 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
950 | gfp_t flags, int npages); | |
951 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
952 | struct mlx5_cmd_mailbox *head); | |
a606b0f6 MB |
953 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
954 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 955 | u32 *in, int inlen); |
a606b0f6 MB |
956 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
957 | struct mlx5_core_mkey *mkey); | |
958 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 959 | u32 *out, int outlen); |
e126ba97 EC |
960 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
961 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
0cf53c12 | 962 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
e126ba97 | 963 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
0cf53c12 | 964 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
e126ba97 EC |
965 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
966 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
591905ba | 967 | s32 npages, bool ec_function); |
cd23b14b | 968 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
969 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
970 | void mlx5_register_debugfs(void); | |
971 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
972 | |
973 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 974 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
0b6e26ce DT |
975 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
976 | unsigned int *irqn); | |
e126ba97 EC |
977 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
978 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
979 | ||
9f818c8a | 980 | void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 EC |
981 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); |
982 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
983 | int size_in, void *data_out, int size_out, | |
984 | u16 reg_num, int arg, int write); | |
adb0c954 | 985 | |
e126ba97 | 986 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
987 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
988 | int node); | |
e126ba97 EC |
989 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
990 | ||
e126ba97 | 991 | const char *mlx5_command_str(int command); |
9f818c8a | 992 | void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 | 993 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); |
3121e3c4 SG |
994 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
995 | int npsvs, u32 *sig_index); | |
996 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 997 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
998 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
999 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1000 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1001 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 1002 | |
1466cc5b YP |
1003 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1004 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
1005 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
1006 | struct mlx5_rate_limit *rl); | |
1007 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 1008 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
1326034b YH |
1009 | int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid, |
1010 | bool dedicated_entry, u16 *index); | |
1011 | void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index); | |
05d3ac97 BW |
1012 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
1013 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
1014 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1015 | bool map_wc, bool fast_path); | |
1016 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1017 | |
f2f3df55 SM |
1018 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
1019 | struct cpumask * | |
1020 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
1021 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1022 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1023 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1024 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1025 | |
e126ba97 EC |
1026 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1027 | { | |
1028 | return mkey >> 8; | |
1029 | } | |
1030 | ||
1031 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1032 | { | |
1033 | return mkey_idx << 8; | |
1034 | } | |
1035 | ||
746b5583 EC |
1036 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1037 | { | |
1038 | return mkey & 0xff; | |
1039 | } | |
1040 | ||
e126ba97 EC |
1041 | enum { |
1042 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1043 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1044 | }; |
1045 | ||
1046 | enum { | |
8b7ff7f3 | 1047 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1048 | MLX5_IMR_MTT_CACHE_ENTRY, |
1049 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1050 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1051 | }; |
1052 | ||
64613d94 SM |
1053 | enum { |
1054 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1055 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1056 | }; | |
1057 | ||
9603b61d JM |
1058 | struct mlx5_interface { |
1059 | void * (*add)(struct mlx5_core_dev *dev); | |
1060 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1061 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1062 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
64613d94 | 1063 | int protocol; |
9603b61d JM |
1064 | struct list_head list; |
1065 | }; | |
1066 | ||
1067 | int mlx5_register_interface(struct mlx5_interface *intf); | |
1068 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
20902be4 SM |
1069 | int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
1070 | int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
c0670781 YH |
1071 | int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); |
1072 | int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); | |
20902be4 | 1073 | |
211e6c80 | 1074 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1075 | |
3bc34f3b AH |
1076 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1077 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7c34ec19 AH |
1078 | bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); |
1079 | bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); | |
724b509c | 1080 | bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); |
7907f23a | 1081 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1082 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
c6bc6041 MG |
1083 | u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev, |
1084 | struct net_device *slave); | |
71a0ff65 MD |
1085 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1086 | u64 *values, | |
1087 | int num_counters, | |
1088 | size_t *offsets); | |
01187175 EC |
1089 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1090 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
c9b9dcb4 | 1091 | int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
dff8e2d1 ES |
1092 | u64 length, u32 log_alignment, u16 uid, |
1093 | phys_addr_t *addr, u32 *obj_id); | |
c9b9dcb4 AL |
1094 | int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
1095 | u64 length, u16 uid, phys_addr_t addr, u32 obj_id); | |
7907f23a | 1096 | |
f6a8a19b | 1097 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1098 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1099 | struct ib_device *ibdev, | |
1100 | const char *name, | |
1101 | void (*setup)(struct net_device *)); | |
693dfd5a | 1102 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1103 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1104 | struct ib_device *device, | |
1105 | struct rdma_netdev_alloc_params *params); | |
693dfd5a | 1106 | |
e126ba97 EC |
1107 | struct mlx5_profile { |
1108 | u64 mask; | |
f241e749 | 1109 | u8 log_max_qp; |
e126ba97 EC |
1110 | struct { |
1111 | int size; | |
1112 | int limit; | |
1113 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1114 | }; | |
1115 | ||
fc50db98 EC |
1116 | enum { |
1117 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1118 | }; | |
1119 | ||
2752b823 | 1120 | static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) |
fc50db98 | 1121 | { |
386e75af | 1122 | return dev->coredev_type == MLX5_COREDEV_PF; |
fc50db98 EC |
1123 | } |
1124 | ||
e53a9d26 PP |
1125 | static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev) |
1126 | { | |
1127 | return dev->coredev_type == MLX5_COREDEV_VF; | |
1128 | } | |
1129 | ||
591905ba BW |
1130 | static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) |
1131 | { | |
1132 | return dev->caps.embedded_cpu; | |
1133 | } | |
1134 | ||
2752b823 PP |
1135 | static inline bool |
1136 | mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) | |
7f0d11c7 BW |
1137 | { |
1138 | return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); | |
1139 | } | |
1140 | ||
2752b823 | 1141 | static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) |
81cd229c BW |
1142 | { |
1143 | return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); | |
1144 | } | |
1145 | ||
2752b823 | 1146 | static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) |
feb39369 | 1147 | { |
86eec50b | 1148 | return dev->priv.sriov.max_vfs; |
feb39369 BW |
1149 | } |
1150 | ||
707c4602 MD |
1151 | static inline int mlx5_get_gid_table_len(u16 param) |
1152 | { | |
1153 | if (param > 4) { | |
1154 | pr_warn("gid table length is zero\n"); | |
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | return 8 * (1 << param); | |
1159 | } | |
1160 | ||
1466cc5b YP |
1161 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1162 | { | |
1163 | return !!(dev->priv.rl_table.max_size); | |
1164 | } | |
1165 | ||
32f69e4b DJ |
1166 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1167 | { | |
1168 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1169 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1170 | } | |
1171 | ||
1172 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1173 | { | |
1174 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1175 | } | |
1176 | ||
1177 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1178 | { | |
1179 | return mlx5_core_is_mp_slave(dev) || | |
1180 | mlx5_core_is_mp_master(dev); | |
1181 | } | |
1182 | ||
7fd8aefb DJ |
1183 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1184 | { | |
32f69e4b DJ |
1185 | if (!mlx5_core_mp_enabled(dev)) |
1186 | return 1; | |
1187 | ||
1188 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1189 | } |
1190 | ||
020446e0 EC |
1191 | enum { |
1192 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1193 | }; | |
1194 | ||
cc9defcb MG |
1195 | static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev) |
1196 | { | |
1197 | struct devlink *devlink = priv_to_devlink(dev); | |
1198 | union devlink_param_value val; | |
1199 | ||
1200 | devlink_param_driverinit_value_get(devlink, | |
1201 | DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, | |
1202 | &val); | |
1203 | return val.vbool; | |
1204 | } | |
1205 | ||
e126ba97 | 1206 | #endif /* MLX5_DRIVER_H */ |