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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 | 43 | #include <linux/vmalloc.h> |
792c4e9d | 44 | #include <linux/xarray.h> |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
20902be4 | 49 | #include <linux/notifier.h> |
94f3e14e | 50 | #include <linux/refcount.h> |
a925b5e3 | 51 | #include <linux/auxiliary_bus.h> |
6ecde51d | 52 | |
e126ba97 EC |
53 | #include <linux/mlx5/device.h> |
54 | #include <linux/mlx5/doorbell.h> | |
41069256 | 55 | #include <linux/mlx5/eq.h> |
7c39afb3 FD |
56 | #include <linux/timecounter.h> |
57 | #include <linux/ptp_clock_kernel.h> | |
1e34f3ef | 58 | #include <net/devlink.h> |
e126ba97 | 59 | |
17a7612b LR |
60 | #define MLX5_ADEV_NAME "mlx5_core" |
61 | ||
3663ad34 SD |
62 | #define MLX5_IRQ_EQ_CTRL (U8_MAX) |
63 | ||
e126ba97 EC |
64 | enum { |
65 | MLX5_BOARD_ID_LEN = 64, | |
e126ba97 EC |
66 | }; |
67 | ||
68 | enum { | |
e126ba97 EC |
69 | MLX5_CMD_WQ_MAX_NAME = 32, |
70 | }; | |
71 | ||
72 | enum { | |
73 | CMD_OWNER_SW = 0x0, | |
74 | CMD_OWNER_HW = 0x1, | |
75 | CMD_STATUS_SUCCESS = 0, | |
76 | }; | |
77 | ||
78 | enum mlx5_sqp_t { | |
79 | MLX5_SQP_SMI = 0, | |
80 | MLX5_SQP_GSI = 1, | |
81 | MLX5_SQP_IEEE_1588 = 2, | |
82 | MLX5_SQP_SNIFFER = 3, | |
83 | MLX5_SQP_SYNC_UMR = 4, | |
84 | }; | |
85 | ||
86 | enum { | |
87 | MLX5_MAX_PORTS = 2, | |
88 | }; | |
89 | ||
e126ba97 | 90 | enum { |
a60109dc YC |
91 | MLX5_ATOMIC_MODE_OFFSET = 16, |
92 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
93 | MLX5_ATOMIC_MODE_CX = 2, | |
94 | MLX5_ATOMIC_MODE_8B = 3, | |
95 | MLX5_ATOMIC_MODE_16B = 4, | |
96 | MLX5_ATOMIC_MODE_32B = 5, | |
97 | MLX5_ATOMIC_MODE_64B = 6, | |
98 | MLX5_ATOMIC_MODE_128B = 7, | |
99 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
100 | }; |
101 | ||
e126ba97 | 102 | enum { |
415a64aa | 103 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
104 | MLX5_REG_QETCR = 0x4005, |
105 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 106 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 107 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
108 | MLX5_REG_DCBX_PARAM = 0x4020, |
109 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
110 | MLX5_REG_FPGA_CAP = 0x4022, |
111 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 112 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
0b9055a1 | 113 | MLX5_REG_CORE_DUMP = 0x402e, |
e126ba97 EC |
114 | MLX5_REG_PCAP = 0x5001, |
115 | MLX5_REG_PMTU = 0x5003, | |
116 | MLX5_REG_PTYS = 0x5004, | |
117 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 118 | MLX5_REG_PFCC = 0x5007, |
efea389d | 119 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
120 | MLX5_REG_PPTB = 0x500b, |
121 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
122 | MLX5_REG_PMAOS = 0x5012, |
123 | MLX5_REG_PUDE = 0x5009, | |
124 | MLX5_REG_PMPE = 0x5010, | |
125 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 126 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 127 | MLX5_REG_PCMR = 0x5041, |
36830159 | 128 | MLX5_REG_PDDR = 0x5031, |
bb64143e | 129 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 130 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 131 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
132 | MLX5_REG_NODE_DESC = 0x6001, |
133 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 134 | MLX5_REG_MCIA = 0x9014, |
06939536 | 135 | MLX5_REG_MFRL = 0x9028, |
da54d24e | 136 | MLX5_REG_MLCR = 0x902b, |
5a1023de | 137 | MLX5_REG_MRTC = 0x902d, |
eff8ea8f FD |
138 | MLX5_REG_MTRC_CAP = 0x9040, |
139 | MLX5_REG_MTRC_CONF = 0x9041, | |
140 | MLX5_REG_MTRC_STDB = 0x9042, | |
141 | MLX5_REG_MTRC_CTRL = 0x9043, | |
4039049b | 142 | MLX5_REG_MPEIN = 0x9050, |
8ed1a630 | 143 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
144 | MLX5_REG_MTPPS = 0x9053, |
145 | MLX5_REG_MTPPSE = 0x9054, | |
ae02d415 | 146 | MLX5_REG_MTUTC = 0x9055, |
5e022dd3 | 147 | MLX5_REG_MPEGC = 0x9056, |
a82e0b5b | 148 | MLX5_REG_MCQS = 0x9060, |
47176289 OG |
149 | MLX5_REG_MCQI = 0x9061, |
150 | MLX5_REG_MCC = 0x9062, | |
151 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 152 | MLX5_REG_MCAM = 0x907f, |
bab58ba1 | 153 | MLX5_REG_MIRC = 0x9162, |
88b3d5c9 | 154 | MLX5_REG_SBCAM = 0xB01F, |
609b8272 | 155 | MLX5_REG_RESOURCE_DUMP = 0xC000, |
4b2c5fa9 | 156 | MLX5_REG_DTOR = 0xC00E, |
e126ba97 EC |
157 | }; |
158 | ||
415a64aa HN |
159 | enum mlx5_qpts_trust_state { |
160 | MLX5_QPTS_TRUST_PCP = 1, | |
161 | MLX5_QPTS_TRUST_DSCP = 2, | |
162 | }; | |
163 | ||
341c5ee2 HN |
164 | enum mlx5_dcbx_oper_mode { |
165 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
166 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
167 | }; | |
168 | ||
da7525d2 EBE |
169 | enum { |
170 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
171 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
172 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
173 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
174 | }; |
175 | ||
e420f0c0 HE |
176 | enum mlx5_page_fault_resume_flags { |
177 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
178 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
179 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
180 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
181 | }; | |
182 | ||
e126ba97 EC |
183 | enum dbg_rsc_type { |
184 | MLX5_DBG_RSC_QP, | |
185 | MLX5_DBG_RSC_EQ, | |
186 | MLX5_DBG_RSC_CQ, | |
187 | }; | |
188 | ||
7ecf6d8f BW |
189 | enum port_state_policy { |
190 | MLX5_POLICY_DOWN = 0, | |
191 | MLX5_POLICY_UP = 1, | |
192 | MLX5_POLICY_FOLLOW = 2, | |
193 | MLX5_POLICY_INVALID = 0xffffffff | |
194 | }; | |
195 | ||
386e75af HN |
196 | enum mlx5_coredev_type { |
197 | MLX5_COREDEV_PF, | |
1958fc2f PP |
198 | MLX5_COREDEV_VF, |
199 | MLX5_COREDEV_SF, | |
386e75af HN |
200 | }; |
201 | ||
e126ba97 | 202 | struct mlx5_field_desc { |
e126ba97 EC |
203 | int i; |
204 | }; | |
205 | ||
206 | struct mlx5_rsc_debug { | |
207 | struct mlx5_core_dev *dev; | |
208 | void *object; | |
209 | enum dbg_rsc_type type; | |
210 | struct dentry *root; | |
b6ca09cb | 211 | struct mlx5_field_desc fields[]; |
e126ba97 EC |
212 | }; |
213 | ||
214 | enum mlx5_dev_event { | |
58d180b3 | 215 | MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ |
6997b1c9 | 216 | MLX5_DEV_EVENT_PORT_AFFINITY = 129, |
e126ba97 EC |
217 | }; |
218 | ||
4c916a79 | 219 | enum mlx5_port_status { |
6fa1bcab AS |
220 | MLX5_PORT_UP = 1, |
221 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
222 | }; |
223 | ||
f7936ddd EBE |
224 | enum mlx5_cmdif_state { |
225 | MLX5_CMDIF_STATE_UNINITIALIZED, | |
226 | MLX5_CMDIF_STATE_UP, | |
227 | MLX5_CMDIF_STATE_DOWN, | |
228 | }; | |
229 | ||
e126ba97 EC |
230 | struct mlx5_cmd_first { |
231 | __be32 data[4]; | |
232 | }; | |
233 | ||
234 | struct mlx5_cmd_msg { | |
235 | struct list_head list; | |
0ac3ea70 | 236 | struct cmd_msg_cache *parent; |
e126ba97 EC |
237 | u32 len; |
238 | struct mlx5_cmd_first first; | |
239 | struct mlx5_cmd_mailbox *next; | |
240 | }; | |
241 | ||
242 | struct mlx5_cmd_debug { | |
243 | struct dentry *dbg_root; | |
e126ba97 EC |
244 | void *in_msg; |
245 | void *out_msg; | |
246 | u8 status; | |
247 | u16 inlen; | |
248 | u16 outlen; | |
249 | }; | |
250 | ||
0ac3ea70 | 251 | struct cmd_msg_cache { |
e126ba97 EC |
252 | /* protect block chain allocations |
253 | */ | |
254 | spinlock_t lock; | |
255 | struct list_head head; | |
0ac3ea70 MHY |
256 | unsigned int max_inbox_size; |
257 | unsigned int num_ent; | |
e126ba97 EC |
258 | }; |
259 | ||
0ac3ea70 MHY |
260 | enum { |
261 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
262 | }; |
263 | ||
264 | struct mlx5_cmd_stats { | |
265 | u64 sum; | |
266 | u64 n; | |
267 | struct dentry *root; | |
e126ba97 EC |
268 | /* protect command average calculations */ |
269 | spinlock_t lock; | |
270 | }; | |
271 | ||
272 | struct mlx5_cmd { | |
71edc69c SM |
273 | struct mlx5_nb nb; |
274 | ||
f7936ddd | 275 | enum mlx5_cmdif_state state; |
64599cca EC |
276 | void *cmd_alloc_buf; |
277 | dma_addr_t alloc_dma; | |
278 | int alloc_size; | |
e126ba97 EC |
279 | void *cmd_buf; |
280 | dma_addr_t dma; | |
281 | u16 cmdif_rev; | |
282 | u8 log_sz; | |
283 | u8 log_stride; | |
284 | int max_reg_cmds; | |
285 | int events; | |
286 | u32 __iomem *vector; | |
287 | ||
288 | /* protect command queue allocations | |
289 | */ | |
290 | spinlock_t alloc_lock; | |
291 | ||
292 | /* protect token allocations | |
293 | */ | |
294 | spinlock_t token_lock; | |
295 | u8 token; | |
296 | unsigned long bitmask; | |
297 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
298 | struct workqueue_struct *wq; | |
299 | struct semaphore sem; | |
300 | struct semaphore pages_sem; | |
301 | int mode; | |
d43b7007 | 302 | u16 allowed_opcode; |
e126ba97 | 303 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; |
18c90df9 | 304 | struct dma_pool *pool; |
e126ba97 | 305 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 306 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 | 307 | int checksum_disabled; |
2553f421 | 308 | struct mlx5_cmd_stats *stats; |
e126ba97 EC |
309 | }; |
310 | ||
e126ba97 EC |
311 | struct mlx5_cmd_mailbox { |
312 | void *buf; | |
313 | dma_addr_t dma; | |
314 | struct mlx5_cmd_mailbox *next; | |
315 | }; | |
316 | ||
317 | struct mlx5_buf_list { | |
318 | void *buf; | |
319 | dma_addr_t map; | |
320 | }; | |
321 | ||
1c1b5228 TT |
322 | struct mlx5_frag_buf { |
323 | struct mlx5_buf_list *frags; | |
324 | int npages; | |
325 | int size; | |
326 | u8 page_shift; | |
327 | }; | |
328 | ||
388ca8be | 329 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 330 | struct mlx5_buf_list *frags; |
388ca8be | 331 | u32 sz_m1; |
8d71e818 | 332 | u16 frag_sz_m1; |
a0903622 | 333 | u16 strides_offset; |
388ca8be YC |
334 | u8 log_sz; |
335 | u8 log_stride; | |
336 | u8 log_frag_strides; | |
337 | }; | |
338 | ||
3121e3c4 SG |
339 | struct mlx5_core_psv { |
340 | u32 psv_idx; | |
341 | struct psv_layout { | |
342 | u32 pd; | |
343 | u16 syndrome; | |
344 | u16 reserved; | |
345 | u16 bg; | |
346 | u16 app_tag; | |
347 | u32 ref_tag; | |
348 | } psv; | |
349 | }; | |
350 | ||
351 | struct mlx5_core_sig_ctx { | |
352 | struct mlx5_core_psv psv_memory; | |
353 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
354 | struct ib_sig_err err_item; |
355 | bool sig_status_checked; | |
356 | bool sig_err_exists; | |
357 | u32 sigerr_count; | |
3121e3c4 | 358 | }; |
e126ba97 | 359 | |
aa8e08d2 AK |
360 | enum { |
361 | MLX5_MKEY_MR = 1, | |
362 | MLX5_MKEY_MW, | |
534fd7aa | 363 | MLX5_MKEY_INDIRECT_DEVX, |
aa8e08d2 AK |
364 | }; |
365 | ||
a606b0f6 | 366 | struct mlx5_core_mkey { |
e126ba97 EC |
367 | u64 iova; |
368 | u64 size; | |
369 | u32 key; | |
370 | u32 pd; | |
aa8e08d2 | 371 | u32 type; |
db72438c YH |
372 | struct wait_queue_head wait; |
373 | refcount_t usecount; | |
e126ba97 EC |
374 | }; |
375 | ||
d9aaed83 AK |
376 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
377 | ||
5903325a | 378 | enum mlx5_res_type { |
e2013b21 | 379 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
380 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
381 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
382 | MLX5_RES_SRQ = 3, | |
383 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 384 | MLX5_RES_XRQ = 5, |
57cda166 | 385 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
386 | }; |
387 | ||
388 | struct mlx5_core_rsc_common { | |
389 | enum mlx5_res_type res; | |
94f3e14e | 390 | refcount_t refcount; |
5903325a EC |
391 | struct completion free; |
392 | }; | |
393 | ||
a6d51b68 | 394 | struct mlx5_uars_page { |
e126ba97 | 395 | void __iomem *map; |
a6d51b68 EC |
396 | bool wc; |
397 | u32 index; | |
398 | struct list_head list; | |
399 | unsigned int bfregs; | |
400 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
401 | unsigned long *fp_bitmap; | |
402 | unsigned int reg_avail; | |
403 | unsigned int fp_avail; | |
404 | struct kref ref_count; | |
405 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
406 | }; |
407 | ||
a6d51b68 EC |
408 | struct mlx5_bfreg_head { |
409 | /* protect blue flame registers allocations */ | |
410 | struct mutex lock; | |
411 | struct list_head list; | |
412 | }; | |
413 | ||
414 | struct mlx5_bfreg_data { | |
415 | struct mlx5_bfreg_head reg_head; | |
416 | struct mlx5_bfreg_head wc_head; | |
417 | }; | |
418 | ||
419 | struct mlx5_sq_bfreg { | |
420 | void __iomem *map; | |
421 | struct mlx5_uars_page *up; | |
422 | bool wc; | |
423 | u32 index; | |
424 | unsigned int offset; | |
425 | }; | |
e126ba97 EC |
426 | |
427 | struct mlx5_core_health { | |
428 | struct health_buffer __iomem *health; | |
429 | __be32 __iomem *health_counter; | |
430 | struct timer_list timer; | |
e126ba97 EC |
431 | u32 prev; |
432 | int miss_counter; | |
d1bf0e2c | 433 | u8 synd; |
63cbc552 | 434 | u32 fatal_error; |
8b9d8baa | 435 | u32 crdump_size; |
05ac2c0b MHY |
436 | /* wq spinlock to synchronize draining */ |
437 | spinlock_t wq_lock; | |
ac6ea6e8 | 438 | struct workqueue_struct *wq; |
05ac2c0b | 439 | unsigned long flags; |
b3bd076f | 440 | struct work_struct fatal_report_work; |
d1bf0e2c | 441 | struct work_struct report_work; |
1e34f3ef | 442 | struct devlink_health_reporter *fw_reporter; |
96c82cdf | 443 | struct devlink_health_reporter *fw_fatal_reporter; |
5a1023de | 444 | struct delayed_work update_fw_log_ts_work; |
e126ba97 EC |
445 | }; |
446 | ||
e126ba97 | 447 | struct mlx5_qp_table { |
451be51c | 448 | struct notifier_block nb; |
221c14f3 | 449 | |
e126ba97 EC |
450 | /* protect radix tree |
451 | */ | |
452 | spinlock_t lock; | |
453 | struct radix_tree_root tree; | |
454 | }; | |
455 | ||
fc50db98 EC |
456 | struct mlx5_vf_context { |
457 | int enabled; | |
7ecf6d8f BW |
458 | u64 port_guid; |
459 | u64 node_guid; | |
4bbd4923 DG |
460 | /* Valid bits are used to validate administrative guid only. |
461 | * Enabled after ndo_set_vf_guid | |
462 | */ | |
463 | u8 port_guid_valid:1; | |
464 | u8 node_guid_valid:1; | |
7ecf6d8f | 465 | enum port_state_policy policy; |
fc50db98 EC |
466 | }; |
467 | ||
468 | struct mlx5_core_sriov { | |
469 | struct mlx5_vf_context *vfs_ctx; | |
470 | int num_vfs; | |
86eec50b | 471 | u16 max_vfs; |
fc50db98 EC |
472 | }; |
473 | ||
558101f1 GT |
474 | struct mlx5_fc_pool { |
475 | struct mlx5_core_dev *dev; | |
476 | struct mutex pool_lock; /* protects pool lists */ | |
477 | struct list_head fully_used; | |
478 | struct list_head partially_used; | |
479 | struct list_head unused; | |
480 | int available_fcs; | |
481 | int used_fcs; | |
482 | int threshold; | |
483 | }; | |
484 | ||
43a335e0 | 485 | struct mlx5_fc_stats { |
12d6066c VB |
486 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
487 | struct idr counters_idr; | |
9aff93d7 | 488 | struct list_head counters; |
83033688 | 489 | struct llist_head addlist; |
6e5e2283 | 490 | struct llist_head dellist; |
43a335e0 AV |
491 | |
492 | struct workqueue_struct *wq; | |
493 | struct delayed_work work; | |
494 | unsigned long next_query; | |
f6dfb4c3 | 495 | unsigned long sampling_interval; /* jiffies */ |
6f06e04b | 496 | u32 *bulk_query_out; |
558101f1 | 497 | struct mlx5_fc_pool fc_pool; |
43a335e0 AV |
498 | }; |
499 | ||
69c1280b | 500 | struct mlx5_events; |
eeb66cdb | 501 | struct mlx5_mpfs; |
073bb189 | 502 | struct mlx5_eswitch; |
7907f23a | 503 | struct mlx5_lag; |
fadd59fc | 504 | struct mlx5_devcom; |
38b9f903 | 505 | struct mlx5_fw_reset; |
f2f3df55 | 506 | struct mlx5_eq_table; |
561aa15a | 507 | struct mlx5_irq_table; |
f3196bb0 | 508 | struct mlx5_vhca_state_notifier; |
90d010b8 | 509 | struct mlx5_sf_dev_table; |
8f010541 PP |
510 | struct mlx5_sf_hw_table; |
511 | struct mlx5_sf_table; | |
073bb189 | 512 | |
05d3ac97 BW |
513 | struct mlx5_rate_limit { |
514 | u32 rate; | |
515 | u32 max_burst_sz; | |
516 | u16 typical_pkt_sz; | |
517 | }; | |
518 | ||
1466cc5b | 519 | struct mlx5_rl_entry { |
1326034b | 520 | u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)]; |
1326034b | 521 | u64 refcount; |
4c4c0a89 | 522 | u16 index; |
1326034b YH |
523 | u16 uid; |
524 | u8 dedicated : 1; | |
1466cc5b YP |
525 | }; |
526 | ||
527 | struct mlx5_rl_table { | |
528 | /* protect rate limit table */ | |
529 | struct mutex rl_lock; | |
530 | u16 max_size; | |
531 | u32 max_rate; | |
532 | u32 min_rate; | |
533 | struct mlx5_rl_entry *rl_entry; | |
6b30b6d4 | 534 | u64 refcount; |
1466cc5b YP |
535 | }; |
536 | ||
80f09dfc MG |
537 | struct mlx5_core_roce { |
538 | struct mlx5_flow_table *ft; | |
539 | struct mlx5_flow_group *fg; | |
540 | struct mlx5_flow_handle *allow_rule; | |
541 | }; | |
542 | ||
a925b5e3 LR |
543 | enum { |
544 | MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0, | |
545 | MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1, | |
a5ae8fc9 DL |
546 | /* Set during device detach to block any further devices |
547 | * creation/deletion on drivers rescan. Unset during device attach. | |
548 | */ | |
549 | MLX5_PRIV_FLAGS_DETACH = 1 << 2, | |
a925b5e3 LR |
550 | }; |
551 | ||
552 | struct mlx5_adev { | |
553 | struct auxiliary_device adev; | |
554 | struct mlx5_core_dev *mdev; | |
555 | int idx; | |
556 | }; | |
557 | ||
4a98544d | 558 | struct mlx5_ft_pool; |
e126ba97 | 559 | struct mlx5_priv { |
561aa15a YA |
560 | /* IRQ table valid only for real pci devices PF or VF */ |
561 | struct mlx5_irq_table *irq_table; | |
f2f3df55 | 562 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
563 | |
564 | /* pages stuff */ | |
0cf53c12 | 565 | struct mlx5_nb pg_nb; |
e126ba97 | 566 | struct workqueue_struct *pg_wq; |
d6945242 | 567 | struct xarray page_root_xa; |
e126ba97 | 568 | int fw_pages; |
6aec21f6 | 569 | atomic_t reg_pages; |
bf0bf77f | 570 | struct list_head free_list; |
fc50db98 | 571 | int vfs_pages; |
8a90f2fc | 572 | int host_pf_pages; |
e126ba97 EC |
573 | |
574 | struct mlx5_core_health health; | |
3d347b1b | 575 | struct list_head traps; |
e126ba97 | 576 | |
e126ba97 | 577 | /* start: qp staff */ |
e126ba97 EC |
578 | struct dentry *qp_debugfs; |
579 | struct dentry *eq_debugfs; | |
580 | struct dentry *cq_debugfs; | |
581 | struct dentry *cmdif_debugfs; | |
582 | /* end: qp staff */ | |
583 | ||
e126ba97 | 584 | /* start: alloc staff */ |
39c538d6 | 585 | /* protect buffer allocation according to numa node */ |
311c7c71 SM |
586 | struct mutex alloc_mutex; |
587 | int numa_node; | |
588 | ||
e126ba97 EC |
589 | struct mutex pgdir_mutex; |
590 | struct list_head pgdir_list; | |
591 | /* end: alloc staff */ | |
592 | struct dentry *dbg_root; | |
593 | ||
9603b61d JM |
594 | struct list_head ctx_list; |
595 | spinlock_t ctx_lock; | |
a925b5e3 LR |
596 | struct mlx5_adev **adev; |
597 | int adev_idx; | |
02039fb6 | 598 | struct mlx5_events *events; |
97834eba | 599 | |
fba53f7b | 600 | struct mlx5_flow_steering *steering; |
eeb66cdb | 601 | struct mlx5_mpfs *mpfs; |
073bb189 | 602 | struct mlx5_eswitch *eswitch; |
fc50db98 | 603 | struct mlx5_core_sriov sriov; |
7907f23a | 604 | struct mlx5_lag *lag; |
a925b5e3 | 605 | u32 flags; |
fadd59fc | 606 | struct mlx5_devcom *devcom; |
38b9f903 | 607 | struct mlx5_fw_reset *fw_reset; |
80f09dfc | 608 | struct mlx5_core_roce roce; |
43a335e0 | 609 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 610 | struct mlx5_rl_table rl_table; |
4a98544d | 611 | struct mlx5_ft_pool *ft_pool; |
d4eb4cd7 | 612 | |
a6d51b68 | 613 | struct mlx5_bfreg_data bfregs; |
01187175 | 614 | struct mlx5_uars_page *uar; |
f3196bb0 PP |
615 | #ifdef CONFIG_MLX5_SF |
616 | struct mlx5_vhca_state_notifier *vhca_state_notifier; | |
90d010b8 | 617 | struct mlx5_sf_dev_table *sf_dev_table; |
1958fc2f | 618 | struct mlx5_core_dev *parent_mdev; |
f3196bb0 | 619 | #endif |
8f010541 PP |
620 | #ifdef CONFIG_MLX5_SF_MANAGER |
621 | struct mlx5_sf_hw_table *sf_hw_table; | |
622 | struct mlx5_sf_table *sf_table; | |
623 | #endif | |
e126ba97 EC |
624 | }; |
625 | ||
89d44f0a | 626 | enum mlx5_device_state { |
8e792700 | 627 | MLX5_DEVICE_STATE_UP = 1, |
89d44f0a MD |
628 | MLX5_DEVICE_STATE_INTERNAL_ERROR, |
629 | }; | |
630 | ||
631 | enum mlx5_interface_state { | |
b3cb5388 | 632 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
633 | }; |
634 | ||
635 | enum mlx5_pci_status { | |
636 | MLX5_PCI_STATUS_DISABLED, | |
637 | MLX5_PCI_STATUS_ENABLED, | |
638 | }; | |
639 | ||
d9aaed83 AK |
640 | enum mlx5_pagefault_type_flags { |
641 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
642 | MLX5_PFAULT_WRITE = 1 << 1, | |
643 | MLX5_PFAULT_RDMA = 1 << 2, | |
644 | }; | |
645 | ||
b50d292b | 646 | struct mlx5_td { |
80a2a902 YA |
647 | /* protects tirs list changes while tirs refresh */ |
648 | struct mutex list_lock; | |
b50d292b HHZ |
649 | struct list_head tirs_list; |
650 | u32 tdn; | |
651 | }; | |
652 | ||
653 | struct mlx5e_resources { | |
c276aae8 RD |
654 | struct mlx5e_hw_objs { |
655 | u32 pdn; | |
656 | struct mlx5_td td; | |
657 | struct mlx5_core_mkey mkey; | |
658 | struct mlx5_sq_bfreg bfreg; | |
659 | } hw_objs; | |
c27971d0 | 660 | struct devlink_port dl_port; |
7a9fb35e | 661 | struct net_device *uplink_netdev; |
b50d292b HHZ |
662 | }; |
663 | ||
c9b9dcb4 AL |
664 | enum mlx5_sw_icm_type { |
665 | MLX5_SW_ICM_TYPE_STEERING, | |
666 | MLX5_SW_ICM_TYPE_HEADER_MODIFY, | |
667 | }; | |
668 | ||
52ec462e IT |
669 | #define MLX5_MAX_RESERVED_GIDS 8 |
670 | ||
671 | struct mlx5_rsvd_gids { | |
672 | unsigned int start; | |
673 | unsigned int count; | |
674 | struct ida ida; | |
675 | }; | |
676 | ||
7c39afb3 FD |
677 | #define MAX_PIN_NUM 8 |
678 | struct mlx5_pps { | |
679 | u8 pin_caps[MAX_PIN_NUM]; | |
680 | struct work_struct out_work; | |
681 | u64 start[MAX_PIN_NUM]; | |
682 | u8 enabled; | |
683 | }; | |
684 | ||
d6f3dc8f | 685 | struct mlx5_timer { |
7c39afb3 FD |
686 | struct cyclecounter cycles; |
687 | struct timecounter tc; | |
7c39afb3 FD |
688 | u32 nominal_c_mult; |
689 | unsigned long overflow_period; | |
690 | struct delayed_work overflow_work; | |
d6f3dc8f EBE |
691 | }; |
692 | ||
693 | struct mlx5_clock { | |
694 | struct mlx5_nb pps_nb; | |
695 | seqlock_t lock; | |
696 | struct hwtstamp_config hwtstamp_config; | |
7c39afb3 FD |
697 | struct ptp_clock *ptp; |
698 | struct ptp_clock_info ptp_info; | |
699 | struct mlx5_pps pps_info; | |
d6f3dc8f | 700 | struct mlx5_timer timer; |
7c39afb3 FD |
701 | }; |
702 | ||
c9b9dcb4 | 703 | struct mlx5_dm; |
f53aaa31 | 704 | struct mlx5_fw_tracer; |
358aa5ce | 705 | struct mlx5_vxlan; |
0ccc171e | 706 | struct mlx5_geneve; |
87175120 | 707 | struct mlx5_hv_vhca; |
f53aaa31 | 708 | |
c9b9dcb4 AL |
709 | #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) |
710 | #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) | |
711 | ||
3410fbcd MG |
712 | enum { |
713 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
714 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, | |
715 | }; | |
716 | ||
717 | enum { | |
718 | MR_CACHE_LAST_STD_ENTRY = 20, | |
719 | MLX5_IMR_MTT_CACHE_ENTRY, | |
720 | MLX5_IMR_KSM_CACHE_ENTRY, | |
721 | MAX_MR_CACHE_ENTRIES | |
722 | }; | |
723 | ||
724 | struct mlx5_profile { | |
725 | u64 mask; | |
726 | u8 log_max_qp; | |
727 | struct { | |
728 | int size; | |
729 | int limit; | |
730 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
731 | }; | |
732 | ||
5958a6fa PP |
733 | struct mlx5_hca_cap { |
734 | u32 cur[MLX5_UN_SZ_DW(hca_cap_union)]; | |
735 | u32 max[MLX5_UN_SZ_DW(hca_cap_union)]; | |
736 | }; | |
737 | ||
e126ba97 | 738 | struct mlx5_core_dev { |
27b942fb | 739 | struct device *device; |
386e75af | 740 | enum mlx5_coredev_type coredev_type; |
e126ba97 | 741 | struct pci_dev *pdev; |
89d44f0a MD |
742 | /* sync pci state */ |
743 | struct mutex pci_status_mutex; | |
744 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
745 | u8 rev_id; |
746 | char board_id[MLX5_BOARD_ID_LEN]; | |
747 | struct mlx5_cmd cmd; | |
71862561 | 748 | struct { |
48f02eef | 749 | struct mlx5_hca_cap *hca[MLX5_CAP_NUM]; |
71862561 | 750 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
932ef155 | 751 | u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; |
99d3cd27 | 752 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 753 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
591905ba | 754 | u8 embedded_cpu; |
71862561 | 755 | } caps; |
5945e1ad | 756 | struct mlx5_timeouts *timeouts; |
59c9d35e | 757 | u64 sys_image_guid; |
e126ba97 EC |
758 | phys_addr_t iseg_base; |
759 | struct mlx5_init_seg __iomem *iseg; | |
aa8106f1 | 760 | phys_addr_t bar_addr; |
89d44f0a MD |
761 | enum mlx5_device_state state; |
762 | /* sync interface state */ | |
763 | struct mutex intf_state_mutex; | |
5fc7197d | 764 | unsigned long intf_state; |
e126ba97 | 765 | struct mlx5_priv priv; |
3410fbcd | 766 | struct mlx5_profile profile; |
f62b8bb8 | 767 | u32 issi; |
b50d292b | 768 | struct mlx5e_resources mlx5e_res; |
c9b9dcb4 | 769 | struct mlx5_dm *dm; |
358aa5ce | 770 | struct mlx5_vxlan *vxlan; |
0ccc171e | 771 | struct mlx5_geneve *geneve; |
52ec462e IT |
772 | struct { |
773 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 774 | u32 roce_en; |
52ec462e | 775 | } roce; |
e29341fb IT |
776 | #ifdef CONFIG_MLX5_FPGA |
777 | struct mlx5_fpga_device *fpga; | |
9a6ad1ad RS |
778 | #endif |
779 | #ifdef CONFIG_MLX5_ACCEL | |
780 | const struct mlx5_accel_ipsec_ops *ipsec_ops; | |
5a7b27eb | 781 | #endif |
7c39afb3 | 782 | struct mlx5_clock clock; |
24d33d2c | 783 | struct mlx5_ib_clock_info *clock_info; |
f53aaa31 | 784 | struct mlx5_fw_tracer *tracer; |
12206b17 | 785 | struct mlx5_rsc_dump *rsc_dump; |
b25bbc2f | 786 | u32 vsc_addr; |
87175120 | 787 | struct mlx5_hv_vhca *hv_vhca; |
e126ba97 EC |
788 | }; |
789 | ||
790 | struct mlx5_db { | |
791 | __be32 *db; | |
792 | union { | |
793 | struct mlx5_db_pgdir *pgdir; | |
794 | struct mlx5_ib_user_db_page *user_page; | |
795 | } u; | |
796 | dma_addr_t dma; | |
797 | int index; | |
798 | }; | |
799 | ||
adb0c954 SM |
800 | enum { |
801 | MLX5_PTYS_IB = 1 << 0, | |
802 | MLX5_PTYS_EN = 1 << 2, | |
803 | }; | |
804 | ||
e126ba97 EC |
805 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
806 | ||
73dd3a48 MHY |
807 | enum { |
808 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
809 | }; | |
810 | ||
e126ba97 | 811 | struct mlx5_cmd_work_ent { |
73dd3a48 | 812 | unsigned long state; |
e126ba97 EC |
813 | struct mlx5_cmd_msg *in; |
814 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
815 | void *uout; |
816 | int uout_size; | |
e126ba97 | 817 | mlx5_cmd_cbk_t callback; |
65ee6708 | 818 | struct delayed_work cb_timeout_work; |
e126ba97 | 819 | void *context; |
746b5583 | 820 | int idx; |
17d00e83 | 821 | struct completion handling; |
e126ba97 EC |
822 | struct completion done; |
823 | struct mlx5_cmd *cmd; | |
824 | struct work_struct work; | |
825 | struct mlx5_cmd_layout *lay; | |
826 | int ret; | |
827 | int page_queue; | |
828 | u8 status; | |
829 | u8 token; | |
14a70046 TG |
830 | u64 ts1; |
831 | u64 ts2; | |
746b5583 | 832 | u16 op; |
4525abea | 833 | bool polling; |
50b2412b EBE |
834 | /* Track the max comp handlers */ |
835 | refcount_t refcnt; | |
e126ba97 EC |
836 | }; |
837 | ||
838 | struct mlx5_pas { | |
839 | u64 pa; | |
840 | u8 log_sz; | |
841 | }; | |
842 | ||
707c4602 MD |
843 | enum phy_port_state { |
844 | MLX5_AAA_111 | |
845 | }; | |
846 | ||
847 | struct mlx5_hca_vport_context { | |
848 | u32 field_select; | |
849 | bool sm_virt_aware; | |
850 | bool has_smi; | |
851 | bool has_raw; | |
852 | enum port_state_policy policy; | |
853 | enum phy_port_state phys_state; | |
854 | enum ib_port_state vport_state; | |
855 | u8 port_physical_state; | |
856 | u64 sys_image_guid; | |
857 | u64 port_guid; | |
858 | u64 node_guid; | |
859 | u32 cap_mask1; | |
860 | u32 cap_mask1_perm; | |
4106a758 MG |
861 | u16 cap_mask2; |
862 | u16 cap_mask2_perm; | |
707c4602 MD |
863 | u16 lid; |
864 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
865 | u8 lmc; | |
866 | u8 subnet_timeout; | |
867 | u16 sm_lid; | |
868 | u8 sm_sl; | |
869 | u16 qkey_violation_counter; | |
870 | u16 pkey_violation_counter; | |
871 | bool grh_required; | |
872 | }; | |
873 | ||
388ca8be | 874 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 875 | { |
388ca8be | 876 | return buf->frags->buf + offset; |
e126ba97 EC |
877 | } |
878 | ||
e126ba97 EC |
879 | #define STRUCT_FIELD(header, field) \ |
880 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
881 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
882 | ||
e126ba97 EC |
883 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
884 | { | |
885 | return pci_get_drvdata(pdev); | |
886 | } | |
887 | ||
888 | extern struct dentry *mlx5_debugfs_root; | |
889 | ||
890 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
891 | { | |
892 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
893 | } | |
894 | ||
895 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
896 | { | |
897 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
898 | } | |
899 | ||
900 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
901 | { | |
902 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
903 | } | |
904 | ||
3bcdb17a SG |
905 | static inline u32 mlx5_base_mkey(const u32 key) |
906 | { | |
907 | return key & 0xffffff00u; | |
908 | } | |
909 | ||
26bf3090 TT |
910 | static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride) |
911 | { | |
912 | return ((u32)1 << log_sz) << log_stride; | |
913 | } | |
914 | ||
4972e6fa TT |
915 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
916 | u8 log_stride, u8 log_sz, | |
a0903622 | 917 | u16 strides_offset, |
d7037ad7 | 918 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 919 | { |
4972e6fa | 920 | fbc->frags = frags; |
3a2f7033 TT |
921 | fbc->log_stride = log_stride; |
922 | fbc->log_sz = log_sz; | |
388ca8be YC |
923 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
924 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
925 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
926 | fbc->strides_offset = strides_offset; |
927 | } | |
928 | ||
4972e6fa TT |
929 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
930 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
931 | struct mlx5_frag_buf_ctrl *fbc) |
932 | { | |
4972e6fa | 933 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
934 | } |
935 | ||
388ca8be YC |
936 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
937 | u32 ix) | |
938 | { | |
d7037ad7 TT |
939 | unsigned int frag; |
940 | ||
941 | ix += fbc->strides_offset; | |
942 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 943 | |
4972e6fa | 944 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
945 | } |
946 | ||
37fdffb2 TT |
947 | static inline u32 |
948 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
949 | { | |
950 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
951 | ||
952 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
953 | } | |
954 | ||
d43b7007 EBE |
955 | enum { |
956 | CMD_ALLOWED_OPCODE_ALL, | |
957 | }; | |
958 | ||
e126ba97 EC |
959 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); |
960 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
d43b7007 | 961 | void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode); |
c4f287c4 | 962 | |
e355477e JG |
963 | struct mlx5_async_ctx { |
964 | struct mlx5_core_dev *dev; | |
965 | atomic_t num_inflight; | |
966 | struct wait_queue_head wait; | |
967 | }; | |
968 | ||
969 | struct mlx5_async_work; | |
970 | ||
971 | typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); | |
972 | ||
973 | struct mlx5_async_work { | |
974 | struct mlx5_async_ctx *ctx; | |
975 | mlx5_async_cbk_t user_callback; | |
976 | }; | |
977 | ||
978 | void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, | |
979 | struct mlx5_async_ctx *ctx); | |
980 | void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); | |
981 | int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, | |
982 | void *out, int out_size, mlx5_async_cbk_t callback, | |
983 | struct mlx5_async_work *work); | |
984 | ||
e126ba97 EC |
985 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
986 | int out_size); | |
bb7fc863 LR |
987 | |
988 | #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \ | |
989 | ({ \ | |
990 | mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \ | |
991 | MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \ | |
992 | }) | |
993 | ||
994 | #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \ | |
995 | ({ \ | |
996 | u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \ | |
997 | mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \ | |
998 | }) | |
999 | ||
4525abea MD |
1000 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
1001 | void *out, int out_size); | |
c4f287c4 | 1002 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
b898ce7b | 1003 | bool mlx5_cmd_is_down(struct mlx5_core_dev *dev); |
c4f287c4 SM |
1004 | |
1005 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
1006 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
1007 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
52c368dc | 1008 | void mlx5_health_flush(struct mlx5_core_dev *dev); |
ac6ea6e8 EC |
1009 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
1010 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 1011 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 1012 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 1013 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 1014 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
388ca8be YC |
1015 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, |
1016 | int size, struct mlx5_frag_buf *buf); | |
1017 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
1018 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
1019 | struct mlx5_frag_buf *buf, int node); | |
1020 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
1021 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
1022 | gfp_t flags, int npages); | |
1023 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
1024 | struct mlx5_cmd_mailbox *head); | |
a606b0f6 MB |
1025 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
1026 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1027 | u32 *in, int inlen); |
a606b0f6 MB |
1028 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
1029 | struct mlx5_core_mkey *mkey); | |
1030 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 1031 | u32 *out, int outlen); |
e126ba97 EC |
1032 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
1033 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
0cf53c12 | 1034 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
e126ba97 | 1035 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
0cf53c12 | 1036 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
e126ba97 EC |
1037 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
1038 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
591905ba | 1039 | s32 npages, bool ec_function); |
cd23b14b | 1040 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
1041 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
1042 | void mlx5_register_debugfs(void); | |
1043 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
1044 | |
1045 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1dcb6c36 | 1046 | void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm); |
1c1b5228 | 1047 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
563476ae | 1048 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn); |
e126ba97 EC |
1049 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
1050 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
1051 | ||
9f818c8a | 1052 | void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 EC |
1053 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); |
1054 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
1055 | int size_in, void *data_out, int size_out, | |
1056 | u16 reg_num, int arg, int write); | |
adb0c954 | 1057 | |
e126ba97 | 1058 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
1059 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
1060 | int node); | |
e126ba97 EC |
1061 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
1062 | ||
e126ba97 | 1063 | const char *mlx5_command_str(int command); |
9f818c8a | 1064 | void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 | 1065 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); |
3121e3c4 SG |
1066 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
1067 | int npsvs, u32 *sig_index); | |
1068 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 1069 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
1070 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1071 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1072 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1073 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 1074 | |
1466cc5b YP |
1075 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1076 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
1077 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
1078 | struct mlx5_rate_limit *rl); | |
1079 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 1080 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
1326034b YH |
1081 | int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid, |
1082 | bool dedicated_entry, u16 *index); | |
1083 | void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index); | |
05d3ac97 BW |
1084 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
1085 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
1086 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1087 | bool map_wc, bool fast_path); | |
1088 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1089 | |
f2f3df55 SM |
1090 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
1091 | struct cpumask * | |
1092 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
1093 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1094 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1095 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1096 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1097 | |
e126ba97 EC |
1098 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1099 | { | |
1100 | return mkey >> 8; | |
1101 | } | |
1102 | ||
1103 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1104 | { | |
1105 | return mkey_idx << 8; | |
1106 | } | |
1107 | ||
746b5583 EC |
1108 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1109 | { | |
1110 | return mkey & 0xff; | |
1111 | } | |
1112 | ||
241dc159 | 1113 | /* Async-atomic event notifier used by mlx5 core to forward FW |
39c538d6 | 1114 | * evetns received from event queue to mlx5 consumers. |
241dc159 AL |
1115 | * Optimise event queue dipatching. |
1116 | */ | |
20902be4 SM |
1117 | int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
1118 | int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
241dc159 AL |
1119 | |
1120 | /* Async-atomic event notifier used for forwarding | |
1121 | * evetns from the event queue into the to mlx5 events dispatcher, | |
1122 | * eswitch, clock and others. | |
1123 | */ | |
c0670781 YH |
1124 | int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); |
1125 | int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); | |
20902be4 | 1126 | |
241dc159 AL |
1127 | /* Blocking event notifier used to forward SW events, used for slow path */ |
1128 | int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
1129 | int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
1130 | int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event, | |
1131 | void *data); | |
1132 | ||
211e6c80 | 1133 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1134 | |
3bc34f3b AH |
1135 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1136 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7c34ec19 AH |
1137 | bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); |
1138 | bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); | |
7907f23a | 1139 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
af8c0e25 MB |
1140 | bool mlx5_lag_is_master(struct mlx5_core_dev *dev); |
1141 | bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev); | |
6a32047a | 1142 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
c6bc6041 MG |
1143 | u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev, |
1144 | struct net_device *slave); | |
71a0ff65 MD |
1145 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1146 | u64 *values, | |
1147 | int num_counters, | |
1148 | size_t *offsets); | |
af8c0e25 | 1149 | struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev); |
01187175 EC |
1150 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1151 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
c9b9dcb4 | 1152 | int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
dff8e2d1 ES |
1153 | u64 length, u32 log_alignment, u16 uid, |
1154 | phys_addr_t *addr, u32 *obj_id); | |
c9b9dcb4 AL |
1155 | int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
1156 | u64 length, u16 uid, phys_addr_t addr, u32 obj_id); | |
7907f23a | 1157 | |
f6a8a19b | 1158 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1159 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1160 | struct ib_device *ibdev, | |
1161 | const char *name, | |
1162 | void (*setup)(struct net_device *)); | |
693dfd5a | 1163 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1164 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1165 | struct ib_device *device, | |
1166 | struct rdma_netdev_alloc_params *params); | |
e126ba97 | 1167 | |
fc50db98 EC |
1168 | enum { |
1169 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1170 | }; | |
1171 | ||
2752b823 | 1172 | static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) |
fc50db98 | 1173 | { |
386e75af | 1174 | return dev->coredev_type == MLX5_COREDEV_PF; |
fc50db98 EC |
1175 | } |
1176 | ||
e53a9d26 PP |
1177 | static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev) |
1178 | { | |
1179 | return dev->coredev_type == MLX5_COREDEV_VF; | |
1180 | } | |
1181 | ||
3b1e58aa | 1182 | static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev) |
591905ba BW |
1183 | { |
1184 | return dev->caps.embedded_cpu; | |
1185 | } | |
1186 | ||
2752b823 PP |
1187 | static inline bool |
1188 | mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) | |
7f0d11c7 BW |
1189 | { |
1190 | return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); | |
1191 | } | |
1192 | ||
2752b823 | 1193 | static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) |
81cd229c BW |
1194 | { |
1195 | return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); | |
1196 | } | |
1197 | ||
2752b823 | 1198 | static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) |
feb39369 | 1199 | { |
86eec50b | 1200 | return dev->priv.sriov.max_vfs; |
feb39369 BW |
1201 | } |
1202 | ||
707c4602 MD |
1203 | static inline int mlx5_get_gid_table_len(u16 param) |
1204 | { | |
1205 | if (param > 4) { | |
1206 | pr_warn("gid table length is zero\n"); | |
1207 | return 0; | |
1208 | } | |
1209 | ||
1210 | return 8 * (1 << param); | |
1211 | } | |
1212 | ||
1466cc5b YP |
1213 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1214 | { | |
1215 | return !!(dev->priv.rl_table.max_size); | |
1216 | } | |
1217 | ||
32f69e4b DJ |
1218 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1219 | { | |
1220 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1221 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1222 | } | |
1223 | ||
1224 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1225 | { | |
1226 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1227 | } | |
1228 | ||
1229 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1230 | { | |
1231 | return mlx5_core_is_mp_slave(dev) || | |
1232 | mlx5_core_is_mp_master(dev); | |
1233 | } | |
1234 | ||
7fd8aefb DJ |
1235 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1236 | { | |
32f69e4b DJ |
1237 | if (!mlx5_core_mp_enabled(dev)) |
1238 | return 1; | |
1239 | ||
1240 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1241 | } |
1242 | ||
2ec16ddd RL |
1243 | static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev) |
1244 | { | |
1021d064 RL |
1245 | int idx = MLX5_CAP_GEN(dev, native_port_num); |
1246 | ||
1247 | if (idx >= 1 && idx <= MLX5_MAX_PORTS) | |
1248 | return idx - 1; | |
1249 | else | |
1250 | return PCI_FUNC(dev->pdev->devfn); | |
2ec16ddd RL |
1251 | } |
1252 | ||
020446e0 EC |
1253 | enum { |
1254 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1255 | }; | |
1256 | ||
7852546f | 1257 | static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev) |
cc9defcb MG |
1258 | { |
1259 | struct devlink *devlink = priv_to_devlink(dev); | |
1260 | union devlink_param_value val; | |
fbfa97b4 | 1261 | int err; |
cc9defcb | 1262 | |
fbfa97b4 SD |
1263 | err = devlink_param_driverinit_value_get(devlink, |
1264 | DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, | |
1265 | &val); | |
1266 | return err ? MLX5_CAP_GEN(dev, roce) : val.vbool; | |
cc9defcb MG |
1267 | } |
1268 | ||
e126ba97 | 1269 | #endif /* MLX5_DRIVER_H */ |