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net/mlx5_core: Flow counters infrastructure
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
43a335e0 44#include <linux/workqueue.h>
6ecde51d 45
e126ba97
EC		 46#include <linux/mlx5/device.h>
47#include <linux/mlx5/doorbell.h>
48
36350114
GP		 49enum {
50 MLX5_RQ_BITMASK_VSD = 1 << 1,
51};
52
e126ba97
EC		 53enum {
54 MLX5_BOARD_ID_LEN = 64,
55 MLX5_MAX_NAME_LEN = 16,
56};
57
58enum {
59 /* one minute for the sake of bringup. Generally, commands must always
60 * complete and we may need to increase this timeout value
61 */
6b6c07bd 62 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
e126ba97
EC		 63 MLX5_CMD_WQ_MAX_NAME = 32,
64};
65
66enum {
67 CMD_OWNER_SW = 0x0,
68 CMD_OWNER_HW = 0x1,
69 CMD_STATUS_SUCCESS = 0,
70};
71
72enum mlx5_sqp_t {
73 MLX5_SQP_SMI = 0,
74 MLX5_SQP_GSI = 1,
75 MLX5_SQP_IEEE_1588 = 2,
76 MLX5_SQP_SNIFFER = 3,
77 MLX5_SQP_SYNC_UMR = 4,
78};
79
80enum {
81 MLX5_MAX_PORTS = 2,
82};
83
84enum {
85 MLX5_EQ_VEC_PAGES = 0,
86 MLX5_EQ_VEC_CMD = 1,
87 MLX5_EQ_VEC_ASYNC = 2,
88 MLX5_EQ_VEC_COMP_BASE,
89};
90
91enum {
db058a18 92 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 93};
94
95enum {
96 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
97 MLX5_ATOMIC_MODE_CX = 2 << 16,
98 MLX5_ATOMIC_MODE_8B = 3 << 16,
99 MLX5_ATOMIC_MODE_16B = 4 << 16,
100 MLX5_ATOMIC_MODE_32B = 5 << 16,
101 MLX5_ATOMIC_MODE_64B = 6 << 16,
102 MLX5_ATOMIC_MODE_128B = 7 << 16,
103 MLX5_ATOMIC_MODE_256B = 8 << 16,
104};
105
e126ba97 106enum {
4f3961ee
SM		 107 MLX5_REG_QETCR = 0x4005,
108 MLX5_REG_QTCT = 0x400a,
e126ba97
EC		 109 MLX5_REG_PCAP = 0x5001,
110 MLX5_REG_PMTU = 0x5003,
111 MLX5_REG_PTYS = 0x5004,
112 MLX5_REG_PAOS = 0x5006,
3c2d18ef 113 MLX5_REG_PFCC = 0x5007,
efea389d 114 MLX5_REG_PPCNT = 0x5008,
e126ba97
EC		 115 MLX5_REG_PMAOS = 0x5012,
116 MLX5_REG_PUDE = 0x5009,
117 MLX5_REG_PMPE = 0x5010,
118 MLX5_REG_PELC = 0x500e,
a124d13e 119 MLX5_REG_PVLC = 0x500f,
94cb1ebb 120 MLX5_REG_PCMR = 0x5041,
bb64143e 121 MLX5_REG_PMLP = 0x5002,
e126ba97
EC		 122 MLX5_REG_NODE_DESC = 0x6001,
123 MLX5_REG_HOST_ENDIANNESS = 0x7004,
bb64143e 124 MLX5_REG_MCIA = 0x9014,
da54d24e 125 MLX5_REG_MLCR = 0x902b,
e126ba97
EC		 126};
127
da7525d2
EBE		 128enum {
129 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
130 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
131};
132
e420f0c0
HE		 133enum mlx5_page_fault_resume_flags {
134 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
135 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
136 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
137 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
138};
139
e126ba97
EC		 140enum dbg_rsc_type {
141 MLX5_DBG_RSC_QP,
142 MLX5_DBG_RSC_EQ,
143 MLX5_DBG_RSC_CQ,
144};
145
146struct mlx5_field_desc {
147 struct dentry *dent;
148 int i;
149};
150
151struct mlx5_rsc_debug {
152 struct mlx5_core_dev *dev;
153 void *object;
154 enum dbg_rsc_type type;
155 struct dentry *root;
156 struct mlx5_field_desc fields[0];
157};
158
159enum mlx5_dev_event {
160 MLX5_DEV_EVENT_SYS_ERROR,
161 MLX5_DEV_EVENT_PORT_UP,
162 MLX5_DEV_EVENT_PORT_DOWN,
163 MLX5_DEV_EVENT_PORT_INITIALIZED,
164 MLX5_DEV_EVENT_LID_CHANGE,
165 MLX5_DEV_EVENT_PKEY_CHANGE,
166 MLX5_DEV_EVENT_GUID_CHANGE,
167 MLX5_DEV_EVENT_CLIENT_REREG,
168};
169
4c916a79 170enum mlx5_port_status {
6fa1bcab
AS		 171 MLX5_PORT_UP = 1,
172 MLX5_PORT_DOWN = 2,
4c916a79
RS		 173};
174
e126ba97
EC		 175struct mlx5_uuar_info {
176 struct mlx5_uar *uars;
177 int num_uars;
178 int num_low_latency_uuars;
179 unsigned long *bitmap;
180 unsigned int *count;
181 struct mlx5_bf *bfs;
182
183 /*
184 * protect uuar allocation data structs
185 */
186 struct mutex lock;
78c0f98c 187 u32 ver;
e126ba97
EC		 188};
189
190struct mlx5_bf {
191 void __iomem *reg;
192 void __iomem *regreg;
193 int buf_size;
194 struct mlx5_uar *uar;
195 unsigned long offset;
196 int need_lock;
197 /* protect blue flame buffer selection when needed
198 */
199 spinlock_t lock;
200
201 /* serialize 64 bit writes when done as two 32 bit accesses
202 */
203 spinlock_t lock32;
204 int uuarn;
205};
206
207struct mlx5_cmd_first {
208 __be32 data[4];
209};
210
211struct mlx5_cmd_msg {
212 struct list_head list;
213 struct cache_ent *cache;
214 u32 len;
215 struct mlx5_cmd_first first;
216 struct mlx5_cmd_mailbox *next;
217};
218
219struct mlx5_cmd_debug {
220 struct dentry *dbg_root;
221 struct dentry *dbg_in;
222 struct dentry *dbg_out;
223 struct dentry *dbg_outlen;
224 struct dentry *dbg_status;
225 struct dentry *dbg_run;
226 void *in_msg;
227 void *out_msg;
228 u8 status;
229 u16 inlen;
230 u16 outlen;
231};
232
233struct cache_ent {
234 /* protect block chain allocations
235 */
236 spinlock_t lock;
237 struct list_head head;
238};
239
240struct cmd_msg_cache {
241 struct cache_ent large;
242 struct cache_ent med;
243
244};
245
246struct mlx5_cmd_stats {
247 u64 sum;
248 u64 n;
249 struct dentry *root;
250 struct dentry *avg;
251 struct dentry *count;
252 /* protect command average calculations */
253 spinlock_t lock;
254};
255
256struct mlx5_cmd {
64599cca
EC		 257 void *cmd_alloc_buf;
258 dma_addr_t alloc_dma;
259 int alloc_size;
e126ba97
EC		 260 void *cmd_buf;
261 dma_addr_t dma;
262 u16 cmdif_rev;
263 u8 log_sz;
264 u8 log_stride;
265 int max_reg_cmds;
266 int events;
267 u32 __iomem *vector;
268
269 /* protect command queue allocations
270 */
271 spinlock_t alloc_lock;
272
273 /* protect token allocations
274 */
275 spinlock_t token_lock;
276 u8 token;
277 unsigned long bitmask;
278 char wq_name[MLX5_CMD_WQ_MAX_NAME];
279 struct workqueue_struct *wq;
280 struct semaphore sem;
281 struct semaphore pages_sem;
282 int mode;
283 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
284 struct pci_pool *pool;
285 struct mlx5_cmd_debug dbg;
286 struct cmd_msg_cache cache;
287 int checksum_disabled;
288 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
289};
290
291struct mlx5_port_caps {
292 int gid_table_len;
293 int pkey_table_len;
938fe83c 294 u8 ext_port_cap;
e126ba97
EC		 295};
296
297struct mlx5_cmd_mailbox {
298 void *buf;
299 dma_addr_t dma;
300 struct mlx5_cmd_mailbox *next;
301};
302
303struct mlx5_buf_list {
304 void *buf;
305 dma_addr_t map;
306};
307
308struct mlx5_buf {
309 struct mlx5_buf_list direct;
e126ba97 310 int npages;
e126ba97 311 int size;
f241e749 312 u8 page_shift;
e126ba97
EC		 313};
314
315struct mlx5_eq {
316 struct mlx5_core_dev *dev;
317 __be32 __iomem *doorbell;
318 u32 cons_index;
319 struct mlx5_buf buf;
320 int size;
0b6e26ce 321 unsigned int irqn;
e126ba97
EC		 322 u8 eqn;
323 int nent;
324 u64 mask;
e126ba97
EC		 325 struct list_head list;
326 int index;
327 struct mlx5_rsc_debug *dbg;
328};
329
3121e3c4
SG		 330struct mlx5_core_psv {
331 u32 psv_idx;
332 struct psv_layout {
333 u32 pd;
334 u16 syndrome;
335 u16 reserved;
336 u16 bg;
337 u16 app_tag;
338 u32 ref_tag;
339 } psv;
340};
341
342struct mlx5_core_sig_ctx {
343 struct mlx5_core_psv psv_memory;
344 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 345 struct ib_sig_err err_item;
346 bool sig_status_checked;
347 bool sig_err_exists;
348 u32 sigerr_count;
3121e3c4 349};
e126ba97 350
a606b0f6 351struct mlx5_core_mkey {
e126ba97
EC		 352 u64 iova;
353 u64 size;
354 u32 key;
355 u32 pd;
e126ba97
EC		 356};
357
5903325a 358enum mlx5_res_type {
e2013b21 359 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
360 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
361 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
362 MLX5_RES_SRQ = 3,
363 MLX5_RES_XSRQ = 4,
5903325a
EC		 364};
365
366struct mlx5_core_rsc_common {
367 enum mlx5_res_type res;
368 atomic_t refcount;
369 struct completion free;
370};
371
e126ba97 372struct mlx5_core_srq {
01949d01 373 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC		 374 u32 srqn;
375 int max;
376 int max_gs;
377 int max_avail_gather;
378 int wqe_shift;
379 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
380
381 atomic_t refcount;
382 struct completion free;
383};
384
385struct mlx5_eq_table {
386 void __iomem *update_ci;
387 void __iomem *update_arm_ci;
233d05d2 388 struct list_head comp_eqs_list;
e126ba97
EC		 389 struct mlx5_eq pages_eq;
390 struct mlx5_eq async_eq;
391 struct mlx5_eq cmd_eq;
e126ba97
EC		 392 int num_comp_vectors;
393 /* protect EQs list
394 */
395 spinlock_t lock;
396};
397
398struct mlx5_uar {
399 u32 index;
400 struct list_head bf_list;
401 unsigned free_bf_bmap;
88a85f99 402 void __iomem *bf_map;
e126ba97
EC		 403 void __iomem *map;
404};
405
406
407struct mlx5_core_health {
408 struct health_buffer __iomem *health;
409 __be32 __iomem *health_counter;
410 struct timer_list timer;
e126ba97
EC		 411 u32 prev;
412 int miss_counter;
fd76ee4d 413 bool sick;
ac6ea6e8
EC		 414 struct workqueue_struct *wq;
415 struct work_struct work;
e126ba97
EC		 416};
417
418struct mlx5_cq_table {
419 /* protect radix tree
420 */
421 spinlock_t lock;
422 struct radix_tree_root tree;
423};
424
425struct mlx5_qp_table {
426 /* protect radix tree
427 */
428 spinlock_t lock;
429 struct radix_tree_root tree;
430};
431
432struct mlx5_srq_table {
433 /* protect radix tree
434 */
435 spinlock_t lock;
436 struct radix_tree_root tree;
437};
438
a606b0f6 439struct mlx5_mkey_table {
3bcdb17a
SG		 440 /* protect radix tree
441 */
442 rwlock_t lock;
443 struct radix_tree_root tree;
444};
445
fc50db98
EC		 446struct mlx5_vf_context {
447 int enabled;
448};
449
450struct mlx5_core_sriov {
451 struct mlx5_vf_context *vfs_ctx;
452 int num_vfs;
453 int enabled_vfs;
454};
455
db058a18
SM		 456struct mlx5_irq_info {
457 cpumask_var_t mask;
458 char name[MLX5_MAX_IRQ_NAME];
459};
460
43a335e0
AV		 461struct mlx5_fc_stats {
462 struct list_head list;
463 struct list_head addlist;
464 /* protect addlist add/splice operations */
465 spinlock_t addlist_lock;
466
467 struct workqueue_struct *wq;
468 struct delayed_work work;
469 unsigned long next_query;
470};
471
073bb189
SM		 472struct mlx5_eswitch;
473
e126ba97
EC		 474struct mlx5_priv {
475 char name[MLX5_MAX_NAME_LEN];
476 struct mlx5_eq_table eq_table;
db058a18
SM		 477 struct msix_entry *msix_arr;
478 struct mlx5_irq_info *irq_info;
e126ba97
EC		 479 struct mlx5_uuar_info uuari;
480 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
481
482 /* pages stuff */
483 struct workqueue_struct *pg_wq;
484 struct rb_root page_root;
485 int fw_pages;
6aec21f6 486 atomic_t reg_pages;
bf0bf77f 487 struct list_head free_list;
fc50db98 488 int vfs_pages;
e126ba97
EC		 489
490 struct mlx5_core_health health;
491
492 struct mlx5_srq_table srq_table;
493
494 /* start: qp staff */
495 struct mlx5_qp_table qp_table;
496 struct dentry *qp_debugfs;
497 struct dentry *eq_debugfs;
498 struct dentry *cq_debugfs;
499 struct dentry *cmdif_debugfs;
500 /* end: qp staff */
501
502 /* start: cq staff */
503 struct mlx5_cq_table cq_table;
504 /* end: cq staff */
505
a606b0f6
MB		 506 /* start: mkey staff */
507 struct mlx5_mkey_table mkey_table;
508 /* end: mkey staff */
3bcdb17a 509
e126ba97 510 /* start: alloc staff */
311c7c71
SM		 511 /* protect buffer alocation according to numa node */
512 struct mutex alloc_mutex;
513 int numa_node;
514
e126ba97
EC		 515 struct mutex pgdir_mutex;
516 struct list_head pgdir_list;
517 /* end: alloc staff */
518 struct dentry *dbg_root;
519
520 /* protect mkey key part */
521 spinlock_t mkey_lock;
522 u8 mkey_key;
9603b61d
JM		 523
524 struct list_head dev_list;
525 struct list_head ctx_list;
526 spinlock_t ctx_lock;
073bb189
SM		 527
528 struct mlx5_eswitch *eswitch;
fc50db98
EC		 529 struct mlx5_core_sriov sriov;
530 unsigned long pci_dev_data;
25302363
MG		 531 struct mlx5_flow_root_namespace *root_ns;
532 struct mlx5_flow_root_namespace *fdb_root_ns;
efdc810b
MHY		 533 struct mlx5_flow_root_namespace *esw_egress_root_ns;
534 struct mlx5_flow_root_namespace *esw_ingress_root_ns;
43a335e0
AV		 535
536 struct mlx5_fc_stats fc_stats;
e126ba97
EC		 537};
538
89d44f0a
MD		 539enum mlx5_device_state {
540 MLX5_DEVICE_STATE_UP,
541 MLX5_DEVICE_STATE_INTERNAL_ERROR,
542};
543
544enum mlx5_interface_state {
5fc7197d
MD		 545 MLX5_INTERFACE_STATE_DOWN = BIT(0),
546 MLX5_INTERFACE_STATE_UP = BIT(1),
547 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
89d44f0a
MD		 548};
549
550enum mlx5_pci_status {
551 MLX5_PCI_STATUS_DISABLED,
552 MLX5_PCI_STATUS_ENABLED,
553};
554
e126ba97
EC		 555struct mlx5_core_dev {
556 struct pci_dev *pdev;
89d44f0a
MD		 557 /* sync pci state */
558 struct mutex pci_status_mutex;
559 enum mlx5_pci_status pci_status;
e126ba97
EC		 560 u8 rev_id;
561 char board_id[MLX5_BOARD_ID_LEN];
562 struct mlx5_cmd cmd;
938fe83c
SM		 563 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
564 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
565 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 566 phys_addr_t iseg_base;
567 struct mlx5_init_seg __iomem *iseg;
89d44f0a
MD		 568 enum mlx5_device_state state;
569 /* sync interface state */
570 struct mutex intf_state_mutex;
5fc7197d 571 unsigned long intf_state;
e126ba97
EC		 572 void (*event) (struct mlx5_core_dev *dev,
573 enum mlx5_dev_event event,
4d2f9bbb 574 unsigned long param);
e126ba97
EC		 575 struct mlx5_priv priv;
576 struct mlx5_profile *profile;
577 atomic_t num_qps;
f62b8bb8 578 u32 issi;
5a7b27eb
MG		 579#ifdef CONFIG_RFS_ACCEL
580 struct cpu_rmap *rmap;
581#endif
e126ba97
EC		 582};
583
584struct mlx5_db {
585 __be32 *db;
586 union {
587 struct mlx5_db_pgdir *pgdir;
588 struct mlx5_ib_user_db_page *user_page;
589 } u;
590 dma_addr_t dma;
591 int index;
592};
593
594enum {
595 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
596};
597
598enum {
599 MLX5_COMP_EQ_SIZE = 1024,
600};
601
adb0c954
SM		 602enum {
603 MLX5_PTYS_IB = 1 << 0,
604 MLX5_PTYS_EN = 1 << 2,
605};
606
e126ba97
EC		 607struct mlx5_db_pgdir {
608 struct list_head list;
609 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
610 __be32 *db_page;
611 dma_addr_t db_dma;
612};
613
614typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
615
616struct mlx5_cmd_work_ent {
617 struct mlx5_cmd_msg *in;
618 struct mlx5_cmd_msg *out;
746b5583
EC		 619 void *uout;
620 int uout_size;
e126ba97
EC		 621 mlx5_cmd_cbk_t callback;
622 void *context;
746b5583 623 int idx;
e126ba97
EC		 624 struct completion done;
625 struct mlx5_cmd *cmd;
626 struct work_struct work;
627 struct mlx5_cmd_layout *lay;
628 int ret;
629 int page_queue;
630 u8 status;
631 u8 token;
14a70046
TG		 632 u64 ts1;
633 u64 ts2;
746b5583 634 u16 op;
e126ba97
EC		 635};
636
637struct mlx5_pas {
638 u64 pa;
639 u8 log_sz;
640};
641
707c4602 642enum port_state_policy {
eff901d3
EC		 643 MLX5_POLICY_DOWN = 0,
644 MLX5_POLICY_UP = 1,
645 MLX5_POLICY_FOLLOW = 2,
646 MLX5_POLICY_INVALID = 0xffffffff
707c4602
MD		 647};
648
649enum phy_port_state {
650 MLX5_AAA_111
651};
652
653struct mlx5_hca_vport_context {
654 u32 field_select;
655 bool sm_virt_aware;
656 bool has_smi;
657 bool has_raw;
658 enum port_state_policy policy;
659 enum phy_port_state phys_state;
660 enum ib_port_state vport_state;
661 u8 port_physical_state;
662 u64 sys_image_guid;
663 u64 port_guid;
664 u64 node_guid;
665 u32 cap_mask1;
666 u32 cap_mask1_perm;
667 u32 cap_mask2;
668 u32 cap_mask2_perm;
669 u16 lid;
670 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
671 u8 lmc;
672 u8 subnet_timeout;
673 u16 sm_lid;
674 u8 sm_sl;
675 u16 qkey_violation_counter;
676 u16 pkey_violation_counter;
677 bool grh_required;
678};
679
e126ba97
EC		 680static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
681{
e126ba97 682 return buf->direct.buf + offset;
e126ba97
EC		 683}
684
685extern struct workqueue_struct *mlx5_core_wq;
686
687#define STRUCT_FIELD(header, field) \
688 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
689 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
690
e126ba97
EC		 691static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
692{
693 return pci_get_drvdata(pdev);
694}
695
696extern struct dentry *mlx5_debugfs_root;
697
698static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
699{
700 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
701}
702
703static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
704{
705 return ioread32be(&dev->iseg->fw_rev) >> 16;
706}
707
708static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
709{
710 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
711}
712
713static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
714{
715 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
716}
717
718static inline void *mlx5_vzalloc(unsigned long size)
719{
720 void *rtn;
721
722 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
723 if (!rtn)
724 rtn = vzalloc(size);
725 return rtn;
726}
727
3bcdb17a
SG		 728static inline u32 mlx5_base_mkey(const u32 key)
729{
730 return key & 0xffffff00u;
731}
732
e126ba97
EC		 733int mlx5_cmd_init(struct mlx5_core_dev *dev);
734void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
735void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
736void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
737int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 738int mlx5_cmd_status_to_err_v2(void *ptr);
b06e7de8 739int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
e126ba97
EC		 740int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
741 int out_size);
746b5583
EC		 742int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
743 void *out, int out_size, mlx5_cmd_cbk_t callback,
744 void *context);
e126ba97
EC		 745int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
746int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
747int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
748int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
0ba42241
ML		 749int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
750 bool map_wc);
e281682b 751void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
ac6ea6e8
EC		 752void mlx5_health_cleanup(struct mlx5_core_dev *dev);
753int mlx5_health_init(struct mlx5_core_dev *dev);
e126ba97
EC		 754void mlx5_start_health_poll(struct mlx5_core_dev *dev);
755void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
311c7c71
SM		 756int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
757 struct mlx5_buf *buf, int node);
64ffaa21 758int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 759void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
760struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
761 gfp_t flags, int npages);
762void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
763 struct mlx5_cmd_mailbox *head);
764int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
01949d01
HA		 765 struct mlx5_create_srq_mbox_in *in, int inlen,
766 int is_xrc);
e126ba97
EC		 767int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
768int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
769 struct mlx5_query_srq_mbox_out *out);
770int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
771 u16 lwm, int is_srq);
a606b0f6
MB		 772void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
773void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
774int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
775 struct mlx5_core_mkey *mkey,
746b5583
EC		 776 struct mlx5_create_mkey_mbox_in *in, int inlen,
777 mlx5_cmd_cbk_t callback, void *context,
778 struct mlx5_create_mkey_mbox_out *out);
a606b0f6
MB		 779int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
780 struct mlx5_core_mkey *mkey);
781int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
e126ba97 782 struct mlx5_query_mkey_mbox_out *out, int outlen);
a606b0f6 783int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
e126ba97
EC		 784 u32 *mkey);
785int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
786int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
a97e2d86 787int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
f241e749 788 u16 opmod, u8 port);
e126ba97
EC		 789void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
790void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
791int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
792void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
fc50db98
EC		 793int mlx5_sriov_init(struct mlx5_core_dev *dev);
794int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
e126ba97 795void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 796 s32 npages);
cd23b14b 797int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC		 798int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
799void mlx5_register_debugfs(void);
800void mlx5_unregister_debugfs(void);
801int mlx5_eq_init(struct mlx5_core_dev *dev);
802void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
803void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
804void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 805void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e420f0c0
HE		 806#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
807void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
808#endif
e126ba97
EC		 809void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
810struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
020446e0 811void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
e126ba97
EC		 812void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
813int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
814 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
815int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
816int mlx5_start_eqs(struct mlx5_core_dev *dev);
817int mlx5_stop_eqs(struct mlx5_core_dev *dev);
0b6e26ce
DT		 818int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
819 unsigned int *irqn);
e126ba97
EC		 820int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
821int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
822
823int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
824void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
825int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
826 int size_in, void *data_out, int size_out,
827 u16 reg_num, int arg, int write);
adb0c954 828
e126ba97
EC		 829int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
830void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
831int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
832 struct mlx5_query_eq_mbox_out *out, int outlen);
833int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
834void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
835int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
836void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
837int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
311c7c71
SM		 838int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
839 int node);
e126ba97
EC		 840void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
841
e126ba97
EC		 842const char *mlx5_command_str(int command);
843int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
844void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 845int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
846 int npsvs, u32 *sig_index);
847int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 848void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE		 849int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
850 struct mlx5_odp_caps *odp_caps);
1c64bf6f
MY		 851int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
852 u8 port_num, void *out, size_t sz);
e126ba97 853
e3297246
EC		 854static inline int fw_initializing(struct mlx5_core_dev *dev)
855{
856 return ioread32be(&dev->iseg->initializing) >> 31;
857}
858
e126ba97
EC		 859static inline u32 mlx5_mkey_to_idx(u32 mkey)
860{
861 return mkey >> 8;
862}
863
864static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
865{
866 return mkey_idx << 8;
867}
868
746b5583
EC		 869static inline u8 mlx5_mkey_variant(u32 mkey)
870{
871 return mkey & 0xff;
872}
873
e126ba97
EC		 874enum {
875 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 876 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC		 877};
878
879enum {
880 MAX_MR_CACHE_ENTRIES = 16,
881};
882
64613d94
SM		 883enum {
884 MLX5_INTERFACE_PROTOCOL_IB = 0,
885 MLX5_INTERFACE_PROTOCOL_ETH = 1,
886};
887
9603b61d
JM		 888struct mlx5_interface {
889 void * (*add)(struct mlx5_core_dev *dev);
890 void (*remove)(struct mlx5_core_dev *dev, void *context);
891 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 892 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 893 void * (*get_dev)(void *context);
894 int protocol;
9603b61d
JM		 895 struct list_head list;
896};
897
64613d94 898void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM		 899int mlx5_register_interface(struct mlx5_interface *intf);
900void mlx5_unregister_interface(struct mlx5_interface *intf);
211e6c80 901int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
9603b61d 902
e126ba97
EC		 903struct mlx5_profile {
904 u64 mask;
f241e749 905 u8 log_max_qp;
e126ba97
EC		 906 struct {
907 int size;
908 int limit;
909 } mr_cache[MAX_MR_CACHE_ENTRIES];
910};
911
fc50db98
EC		 912enum {
913 MLX5_PCI_DEV_IS_VF = 1 << 0,
914};
915
916static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
917{
918 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
919}
920
707c4602
MD		 921static inline int mlx5_get_gid_table_len(u16 param)
922{
923 if (param > 4) {
924 pr_warn("gid table length is zero\n");
925 return 0;
926 }
927
928 return 8 * (1 << param);
929}
930
020446e0
EC		 931enum {
932 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
933};
934
e126ba97 935#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)