Commit | Line | Data |
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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
43a335e0 | 44 | #include <linux/workqueue.h> |
94c6825e | 45 | #include <linux/interrupt.h> |
6ecde51d | 46 | |
e126ba97 EC |
47 | #include <linux/mlx5/device.h> |
48 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 49 | #include <linux/mlx5/srq.h> |
e126ba97 EC |
50 | |
51 | enum { | |
52 | MLX5_BOARD_ID_LEN = 64, | |
53 | MLX5_MAX_NAME_LEN = 16, | |
54 | }; | |
55 | ||
56 | enum { | |
57 | /* one minute for the sake of bringup. Generally, commands must always | |
58 | * complete and we may need to increase this timeout value | |
59 | */ | |
6b6c07bd | 60 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
61 | MLX5_CMD_WQ_MAX_NAME = 32, |
62 | }; | |
63 | ||
64 | enum { | |
65 | CMD_OWNER_SW = 0x0, | |
66 | CMD_OWNER_HW = 0x1, | |
67 | CMD_STATUS_SUCCESS = 0, | |
68 | }; | |
69 | ||
70 | enum mlx5_sqp_t { | |
71 | MLX5_SQP_SMI = 0, | |
72 | MLX5_SQP_GSI = 1, | |
73 | MLX5_SQP_IEEE_1588 = 2, | |
74 | MLX5_SQP_SNIFFER = 3, | |
75 | MLX5_SQP_SYNC_UMR = 4, | |
76 | }; | |
77 | ||
78 | enum { | |
79 | MLX5_MAX_PORTS = 2, | |
80 | }; | |
81 | ||
82 | enum { | |
83 | MLX5_EQ_VEC_PAGES = 0, | |
84 | MLX5_EQ_VEC_CMD = 1, | |
85 | MLX5_EQ_VEC_ASYNC = 2, | |
86 | MLX5_EQ_VEC_COMP_BASE, | |
87 | }; | |
88 | ||
89 | enum { | |
db058a18 | 90 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
91 | }; |
92 | ||
93 | enum { | |
94 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
95 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
96 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
97 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
98 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
99 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
100 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
101 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
102 | }; | |
103 | ||
e126ba97 | 104 | enum { |
4f3961ee SM |
105 | MLX5_REG_QETCR = 0x4005, |
106 | MLX5_REG_QTCT = 0x400a, | |
341c5ee2 HN |
107 | MLX5_REG_DCBX_PARAM = 0x4020, |
108 | MLX5_REG_DCBX_APP = 0x4021, | |
e126ba97 EC |
109 | MLX5_REG_PCAP = 0x5001, |
110 | MLX5_REG_PMTU = 0x5003, | |
111 | MLX5_REG_PTYS = 0x5004, | |
112 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 113 | MLX5_REG_PFCC = 0x5007, |
efea389d | 114 | MLX5_REG_PPCNT = 0x5008, |
e126ba97 EC |
115 | MLX5_REG_PMAOS = 0x5012, |
116 | MLX5_REG_PUDE = 0x5009, | |
117 | MLX5_REG_PMPE = 0x5010, | |
118 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 119 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 120 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 121 | MLX5_REG_PMLP = 0x5002, |
e126ba97 EC |
122 | MLX5_REG_NODE_DESC = 0x6001, |
123 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 124 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 125 | MLX5_REG_MLCR = 0x902b, |
7f503169 | 126 | MLX5_REG_MPCNT = 0x9051, |
e126ba97 EC |
127 | }; |
128 | ||
341c5ee2 HN |
129 | enum mlx5_dcbx_oper_mode { |
130 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
131 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
132 | }; | |
133 | ||
da7525d2 EBE |
134 | enum { |
135 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
136 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
137 | }; | |
138 | ||
e420f0c0 HE |
139 | enum mlx5_page_fault_resume_flags { |
140 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
141 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
142 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
143 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
144 | }; | |
145 | ||
e126ba97 EC |
146 | enum dbg_rsc_type { |
147 | MLX5_DBG_RSC_QP, | |
148 | MLX5_DBG_RSC_EQ, | |
149 | MLX5_DBG_RSC_CQ, | |
150 | }; | |
151 | ||
152 | struct mlx5_field_desc { | |
153 | struct dentry *dent; | |
154 | int i; | |
155 | }; | |
156 | ||
157 | struct mlx5_rsc_debug { | |
158 | struct mlx5_core_dev *dev; | |
159 | void *object; | |
160 | enum dbg_rsc_type type; | |
161 | struct dentry *root; | |
162 | struct mlx5_field_desc fields[0]; | |
163 | }; | |
164 | ||
165 | enum mlx5_dev_event { | |
166 | MLX5_DEV_EVENT_SYS_ERROR, | |
167 | MLX5_DEV_EVENT_PORT_UP, | |
168 | MLX5_DEV_EVENT_PORT_DOWN, | |
169 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
170 | MLX5_DEV_EVENT_LID_CHANGE, | |
171 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
172 | MLX5_DEV_EVENT_GUID_CHANGE, | |
173 | MLX5_DEV_EVENT_CLIENT_REREG, | |
174 | }; | |
175 | ||
4c916a79 | 176 | enum mlx5_port_status { |
6fa1bcab AS |
177 | MLX5_PORT_UP = 1, |
178 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
179 | }; |
180 | ||
e126ba97 EC |
181 | struct mlx5_uuar_info { |
182 | struct mlx5_uar *uars; | |
183 | int num_uars; | |
184 | int num_low_latency_uuars; | |
185 | unsigned long *bitmap; | |
186 | unsigned int *count; | |
187 | struct mlx5_bf *bfs; | |
188 | ||
189 | /* | |
190 | * protect uuar allocation data structs | |
191 | */ | |
192 | struct mutex lock; | |
78c0f98c | 193 | u32 ver; |
e126ba97 EC |
194 | }; |
195 | ||
196 | struct mlx5_bf { | |
197 | void __iomem *reg; | |
198 | void __iomem *regreg; | |
199 | int buf_size; | |
200 | struct mlx5_uar *uar; | |
201 | unsigned long offset; | |
202 | int need_lock; | |
203 | /* protect blue flame buffer selection when needed | |
204 | */ | |
205 | spinlock_t lock; | |
206 | ||
207 | /* serialize 64 bit writes when done as two 32 bit accesses | |
208 | */ | |
209 | spinlock_t lock32; | |
210 | int uuarn; | |
211 | }; | |
212 | ||
213 | struct mlx5_cmd_first { | |
214 | __be32 data[4]; | |
215 | }; | |
216 | ||
217 | struct mlx5_cmd_msg { | |
218 | struct list_head list; | |
0ac3ea70 | 219 | struct cmd_msg_cache *parent; |
e126ba97 EC |
220 | u32 len; |
221 | struct mlx5_cmd_first first; | |
222 | struct mlx5_cmd_mailbox *next; | |
223 | }; | |
224 | ||
225 | struct mlx5_cmd_debug { | |
226 | struct dentry *dbg_root; | |
227 | struct dentry *dbg_in; | |
228 | struct dentry *dbg_out; | |
229 | struct dentry *dbg_outlen; | |
230 | struct dentry *dbg_status; | |
231 | struct dentry *dbg_run; | |
232 | void *in_msg; | |
233 | void *out_msg; | |
234 | u8 status; | |
235 | u16 inlen; | |
236 | u16 outlen; | |
237 | }; | |
238 | ||
0ac3ea70 | 239 | struct cmd_msg_cache { |
e126ba97 EC |
240 | /* protect block chain allocations |
241 | */ | |
242 | spinlock_t lock; | |
243 | struct list_head head; | |
0ac3ea70 MHY |
244 | unsigned int max_inbox_size; |
245 | unsigned int num_ent; | |
e126ba97 EC |
246 | }; |
247 | ||
0ac3ea70 MHY |
248 | enum { |
249 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
250 | }; |
251 | ||
252 | struct mlx5_cmd_stats { | |
253 | u64 sum; | |
254 | u64 n; | |
255 | struct dentry *root; | |
256 | struct dentry *avg; | |
257 | struct dentry *count; | |
258 | /* protect command average calculations */ | |
259 | spinlock_t lock; | |
260 | }; | |
261 | ||
262 | struct mlx5_cmd { | |
64599cca EC |
263 | void *cmd_alloc_buf; |
264 | dma_addr_t alloc_dma; | |
265 | int alloc_size; | |
e126ba97 EC |
266 | void *cmd_buf; |
267 | dma_addr_t dma; | |
268 | u16 cmdif_rev; | |
269 | u8 log_sz; | |
270 | u8 log_stride; | |
271 | int max_reg_cmds; | |
272 | int events; | |
273 | u32 __iomem *vector; | |
274 | ||
275 | /* protect command queue allocations | |
276 | */ | |
277 | spinlock_t alloc_lock; | |
278 | ||
279 | /* protect token allocations | |
280 | */ | |
281 | spinlock_t token_lock; | |
282 | u8 token; | |
283 | unsigned long bitmask; | |
284 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
285 | struct workqueue_struct *wq; | |
286 | struct semaphore sem; | |
287 | struct semaphore pages_sem; | |
288 | int mode; | |
289 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
290 | struct pci_pool *pool; | |
291 | struct mlx5_cmd_debug dbg; | |
0ac3ea70 | 292 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
293 | int checksum_disabled; |
294 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
295 | }; | |
296 | ||
297 | struct mlx5_port_caps { | |
298 | int gid_table_len; | |
299 | int pkey_table_len; | |
938fe83c | 300 | u8 ext_port_cap; |
e126ba97 EC |
301 | }; |
302 | ||
303 | struct mlx5_cmd_mailbox { | |
304 | void *buf; | |
305 | dma_addr_t dma; | |
306 | struct mlx5_cmd_mailbox *next; | |
307 | }; | |
308 | ||
309 | struct mlx5_buf_list { | |
310 | void *buf; | |
311 | dma_addr_t map; | |
312 | }; | |
313 | ||
314 | struct mlx5_buf { | |
315 | struct mlx5_buf_list direct; | |
e126ba97 | 316 | int npages; |
e126ba97 | 317 | int size; |
f241e749 | 318 | u8 page_shift; |
e126ba97 EC |
319 | }; |
320 | ||
94c6825e MB |
321 | struct mlx5_eq_tasklet { |
322 | struct list_head list; | |
323 | struct list_head process_list; | |
324 | struct tasklet_struct task; | |
325 | /* lock on completion tasklet list */ | |
326 | spinlock_t lock; | |
327 | }; | |
328 | ||
e126ba97 EC |
329 | struct mlx5_eq { |
330 | struct mlx5_core_dev *dev; | |
331 | __be32 __iomem *doorbell; | |
332 | u32 cons_index; | |
333 | struct mlx5_buf buf; | |
334 | int size; | |
0b6e26ce | 335 | unsigned int irqn; |
e126ba97 EC |
336 | u8 eqn; |
337 | int nent; | |
338 | u64 mask; | |
e126ba97 EC |
339 | struct list_head list; |
340 | int index; | |
341 | struct mlx5_rsc_debug *dbg; | |
94c6825e | 342 | struct mlx5_eq_tasklet tasklet_ctx; |
e126ba97 EC |
343 | }; |
344 | ||
3121e3c4 SG |
345 | struct mlx5_core_psv { |
346 | u32 psv_idx; | |
347 | struct psv_layout { | |
348 | u32 pd; | |
349 | u16 syndrome; | |
350 | u16 reserved; | |
351 | u16 bg; | |
352 | u16 app_tag; | |
353 | u32 ref_tag; | |
354 | } psv; | |
355 | }; | |
356 | ||
357 | struct mlx5_core_sig_ctx { | |
358 | struct mlx5_core_psv psv_memory; | |
359 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
360 | struct ib_sig_err err_item; |
361 | bool sig_status_checked; | |
362 | bool sig_err_exists; | |
363 | u32 sigerr_count; | |
3121e3c4 | 364 | }; |
e126ba97 | 365 | |
a606b0f6 | 366 | struct mlx5_core_mkey { |
e126ba97 EC |
367 | u64 iova; |
368 | u64 size; | |
369 | u32 key; | |
370 | u32 pd; | |
e126ba97 EC |
371 | }; |
372 | ||
5903325a | 373 | enum mlx5_res_type { |
e2013b21 | 374 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
375 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
376 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
377 | MLX5_RES_SRQ = 3, | |
378 | MLX5_RES_XSRQ = 4, | |
5903325a EC |
379 | }; |
380 | ||
381 | struct mlx5_core_rsc_common { | |
382 | enum mlx5_res_type res; | |
383 | atomic_t refcount; | |
384 | struct completion free; | |
385 | }; | |
386 | ||
e126ba97 | 387 | struct mlx5_core_srq { |
01949d01 | 388 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
389 | u32 srqn; |
390 | int max; | |
391 | int max_gs; | |
392 | int max_avail_gather; | |
393 | int wqe_shift; | |
394 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
395 | ||
396 | atomic_t refcount; | |
397 | struct completion free; | |
398 | }; | |
399 | ||
400 | struct mlx5_eq_table { | |
401 | void __iomem *update_ci; | |
402 | void __iomem *update_arm_ci; | |
233d05d2 | 403 | struct list_head comp_eqs_list; |
e126ba97 EC |
404 | struct mlx5_eq pages_eq; |
405 | struct mlx5_eq async_eq; | |
406 | struct mlx5_eq cmd_eq; | |
e126ba97 EC |
407 | int num_comp_vectors; |
408 | /* protect EQs list | |
409 | */ | |
410 | spinlock_t lock; | |
411 | }; | |
412 | ||
413 | struct mlx5_uar { | |
414 | u32 index; | |
415 | struct list_head bf_list; | |
416 | unsigned free_bf_bmap; | |
88a85f99 | 417 | void __iomem *bf_map; |
e126ba97 EC |
418 | void __iomem *map; |
419 | }; | |
420 | ||
421 | ||
422 | struct mlx5_core_health { | |
423 | struct health_buffer __iomem *health; | |
424 | __be32 __iomem *health_counter; | |
425 | struct timer_list timer; | |
e126ba97 EC |
426 | u32 prev; |
427 | int miss_counter; | |
fd76ee4d | 428 | bool sick; |
05ac2c0b MHY |
429 | /* wq spinlock to synchronize draining */ |
430 | spinlock_t wq_lock; | |
ac6ea6e8 | 431 | struct workqueue_struct *wq; |
05ac2c0b | 432 | unsigned long flags; |
ac6ea6e8 | 433 | struct work_struct work; |
04c0c1ab | 434 | struct delayed_work recover_work; |
e126ba97 EC |
435 | }; |
436 | ||
437 | struct mlx5_cq_table { | |
438 | /* protect radix tree | |
439 | */ | |
440 | spinlock_t lock; | |
441 | struct radix_tree_root tree; | |
442 | }; | |
443 | ||
444 | struct mlx5_qp_table { | |
445 | /* protect radix tree | |
446 | */ | |
447 | spinlock_t lock; | |
448 | struct radix_tree_root tree; | |
449 | }; | |
450 | ||
451 | struct mlx5_srq_table { | |
452 | /* protect radix tree | |
453 | */ | |
454 | spinlock_t lock; | |
455 | struct radix_tree_root tree; | |
456 | }; | |
457 | ||
a606b0f6 | 458 | struct mlx5_mkey_table { |
3bcdb17a SG |
459 | /* protect radix tree |
460 | */ | |
461 | rwlock_t lock; | |
462 | struct radix_tree_root tree; | |
463 | }; | |
464 | ||
fc50db98 EC |
465 | struct mlx5_vf_context { |
466 | int enabled; | |
467 | }; | |
468 | ||
469 | struct mlx5_core_sriov { | |
470 | struct mlx5_vf_context *vfs_ctx; | |
471 | int num_vfs; | |
472 | int enabled_vfs; | |
473 | }; | |
474 | ||
db058a18 SM |
475 | struct mlx5_irq_info { |
476 | cpumask_var_t mask; | |
477 | char name[MLX5_MAX_IRQ_NAME]; | |
478 | }; | |
479 | ||
43a335e0 | 480 | struct mlx5_fc_stats { |
29cc6679 | 481 | struct rb_root counters; |
43a335e0 AV |
482 | struct list_head addlist; |
483 | /* protect addlist add/splice operations */ | |
484 | spinlock_t addlist_lock; | |
485 | ||
486 | struct workqueue_struct *wq; | |
487 | struct delayed_work work; | |
488 | unsigned long next_query; | |
489 | }; | |
490 | ||
073bb189 | 491 | struct mlx5_eswitch; |
7907f23a | 492 | struct mlx5_lag; |
073bb189 | 493 | |
1466cc5b YP |
494 | struct mlx5_rl_entry { |
495 | u32 rate; | |
496 | u16 index; | |
497 | u16 refcount; | |
498 | }; | |
499 | ||
500 | struct mlx5_rl_table { | |
501 | /* protect rate limit table */ | |
502 | struct mutex rl_lock; | |
503 | u16 max_size; | |
504 | u32 max_rate; | |
505 | u32 min_rate; | |
506 | struct mlx5_rl_entry *rl_entry; | |
507 | }; | |
508 | ||
d4eb4cd7 HN |
509 | enum port_module_event_status_type { |
510 | MLX5_MODULE_STATUS_PLUGGED = 0x1, | |
511 | MLX5_MODULE_STATUS_UNPLUGGED = 0x2, | |
512 | MLX5_MODULE_STATUS_ERROR = 0x3, | |
513 | MLX5_MODULE_STATUS_NUM = 0x3, | |
514 | }; | |
515 | ||
516 | enum port_module_event_error_type { | |
517 | MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, | |
518 | MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, | |
519 | MLX5_MODULE_EVENT_ERROR_BUS_STUCK, | |
520 | MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, | |
521 | MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, | |
522 | MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, | |
523 | MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, | |
524 | MLX5_MODULE_EVENT_ERROR_BAD_CABLE, | |
525 | MLX5_MODULE_EVENT_ERROR_UNKNOWN, | |
526 | MLX5_MODULE_EVENT_ERROR_NUM, | |
527 | }; | |
528 | ||
529 | struct mlx5_port_module_event_stats { | |
530 | u64 status_counters[MLX5_MODULE_STATUS_NUM]; | |
531 | u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; | |
532 | }; | |
533 | ||
e126ba97 EC |
534 | struct mlx5_priv { |
535 | char name[MLX5_MAX_NAME_LEN]; | |
536 | struct mlx5_eq_table eq_table; | |
db058a18 SM |
537 | struct msix_entry *msix_arr; |
538 | struct mlx5_irq_info *irq_info; | |
e126ba97 EC |
539 | struct mlx5_uuar_info uuari; |
540 | MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); | |
541 | ||
542 | /* pages stuff */ | |
543 | struct workqueue_struct *pg_wq; | |
544 | struct rb_root page_root; | |
545 | int fw_pages; | |
6aec21f6 | 546 | atomic_t reg_pages; |
bf0bf77f | 547 | struct list_head free_list; |
fc50db98 | 548 | int vfs_pages; |
e126ba97 EC |
549 | |
550 | struct mlx5_core_health health; | |
551 | ||
552 | struct mlx5_srq_table srq_table; | |
553 | ||
554 | /* start: qp staff */ | |
555 | struct mlx5_qp_table qp_table; | |
556 | struct dentry *qp_debugfs; | |
557 | struct dentry *eq_debugfs; | |
558 | struct dentry *cq_debugfs; | |
559 | struct dentry *cmdif_debugfs; | |
560 | /* end: qp staff */ | |
561 | ||
562 | /* start: cq staff */ | |
563 | struct mlx5_cq_table cq_table; | |
564 | /* end: cq staff */ | |
565 | ||
a606b0f6 MB |
566 | /* start: mkey staff */ |
567 | struct mlx5_mkey_table mkey_table; | |
568 | /* end: mkey staff */ | |
3bcdb17a | 569 | |
e126ba97 | 570 | /* start: alloc staff */ |
311c7c71 SM |
571 | /* protect buffer alocation according to numa node */ |
572 | struct mutex alloc_mutex; | |
573 | int numa_node; | |
574 | ||
e126ba97 EC |
575 | struct mutex pgdir_mutex; |
576 | struct list_head pgdir_list; | |
577 | /* end: alloc staff */ | |
578 | struct dentry *dbg_root; | |
579 | ||
580 | /* protect mkey key part */ | |
581 | spinlock_t mkey_lock; | |
582 | u8 mkey_key; | |
9603b61d JM |
583 | |
584 | struct list_head dev_list; | |
585 | struct list_head ctx_list; | |
586 | spinlock_t ctx_lock; | |
073bb189 | 587 | |
fba53f7b | 588 | struct mlx5_flow_steering *steering; |
073bb189 | 589 | struct mlx5_eswitch *eswitch; |
fc50db98 | 590 | struct mlx5_core_sriov sriov; |
7907f23a | 591 | struct mlx5_lag *lag; |
fc50db98 | 592 | unsigned long pci_dev_data; |
43a335e0 | 593 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 594 | struct mlx5_rl_table rl_table; |
d4eb4cd7 HN |
595 | |
596 | struct mlx5_port_module_event_stats pme_stats; | |
e126ba97 EC |
597 | }; |
598 | ||
89d44f0a MD |
599 | enum mlx5_device_state { |
600 | MLX5_DEVICE_STATE_UP, | |
601 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
602 | }; | |
603 | ||
604 | enum mlx5_interface_state { | |
5fc7197d MD |
605 | MLX5_INTERFACE_STATE_DOWN = BIT(0), |
606 | MLX5_INTERFACE_STATE_UP = BIT(1), | |
607 | MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), | |
89d44f0a MD |
608 | }; |
609 | ||
610 | enum mlx5_pci_status { | |
611 | MLX5_PCI_STATUS_DISABLED, | |
612 | MLX5_PCI_STATUS_ENABLED, | |
613 | }; | |
614 | ||
b50d292b HHZ |
615 | struct mlx5_td { |
616 | struct list_head tirs_list; | |
617 | u32 tdn; | |
618 | }; | |
619 | ||
620 | struct mlx5e_resources { | |
621 | struct mlx5_uar cq_uar; | |
622 | u32 pdn; | |
623 | struct mlx5_td td; | |
624 | struct mlx5_core_mkey mkey; | |
625 | }; | |
626 | ||
e126ba97 EC |
627 | struct mlx5_core_dev { |
628 | struct pci_dev *pdev; | |
89d44f0a MD |
629 | /* sync pci state */ |
630 | struct mutex pci_status_mutex; | |
631 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
632 | u8 rev_id; |
633 | char board_id[MLX5_BOARD_ID_LEN]; | |
634 | struct mlx5_cmd cmd; | |
938fe83c SM |
635 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
636 | u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
637 | u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
e126ba97 EC |
638 | phys_addr_t iseg_base; |
639 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
640 | enum mlx5_device_state state; |
641 | /* sync interface state */ | |
642 | struct mutex intf_state_mutex; | |
5fc7197d | 643 | unsigned long intf_state; |
e126ba97 EC |
644 | void (*event) (struct mlx5_core_dev *dev, |
645 | enum mlx5_dev_event event, | |
4d2f9bbb | 646 | unsigned long param); |
e126ba97 EC |
647 | struct mlx5_priv priv; |
648 | struct mlx5_profile *profile; | |
649 | atomic_t num_qps; | |
f62b8bb8 | 650 | u32 issi; |
b50d292b | 651 | struct mlx5e_resources mlx5e_res; |
5a7b27eb MG |
652 | #ifdef CONFIG_RFS_ACCEL |
653 | struct cpu_rmap *rmap; | |
654 | #endif | |
e126ba97 EC |
655 | }; |
656 | ||
657 | struct mlx5_db { | |
658 | __be32 *db; | |
659 | union { | |
660 | struct mlx5_db_pgdir *pgdir; | |
661 | struct mlx5_ib_user_db_page *user_page; | |
662 | } u; | |
663 | dma_addr_t dma; | |
664 | int index; | |
665 | }; | |
666 | ||
e126ba97 EC |
667 | enum { |
668 | MLX5_COMP_EQ_SIZE = 1024, | |
669 | }; | |
670 | ||
adb0c954 SM |
671 | enum { |
672 | MLX5_PTYS_IB = 1 << 0, | |
673 | MLX5_PTYS_EN = 1 << 2, | |
674 | }; | |
675 | ||
e126ba97 EC |
676 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
677 | ||
678 | struct mlx5_cmd_work_ent { | |
679 | struct mlx5_cmd_msg *in; | |
680 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
681 | void *uout; |
682 | int uout_size; | |
e126ba97 | 683 | mlx5_cmd_cbk_t callback; |
65ee6708 | 684 | struct delayed_work cb_timeout_work; |
e126ba97 | 685 | void *context; |
746b5583 | 686 | int idx; |
e126ba97 EC |
687 | struct completion done; |
688 | struct mlx5_cmd *cmd; | |
689 | struct work_struct work; | |
690 | struct mlx5_cmd_layout *lay; | |
691 | int ret; | |
692 | int page_queue; | |
693 | u8 status; | |
694 | u8 token; | |
14a70046 TG |
695 | u64 ts1; |
696 | u64 ts2; | |
746b5583 | 697 | u16 op; |
e126ba97 EC |
698 | }; |
699 | ||
700 | struct mlx5_pas { | |
701 | u64 pa; | |
702 | u8 log_sz; | |
703 | }; | |
704 | ||
707c4602 | 705 | enum port_state_policy { |
eff901d3 EC |
706 | MLX5_POLICY_DOWN = 0, |
707 | MLX5_POLICY_UP = 1, | |
708 | MLX5_POLICY_FOLLOW = 2, | |
709 | MLX5_POLICY_INVALID = 0xffffffff | |
707c4602 MD |
710 | }; |
711 | ||
712 | enum phy_port_state { | |
713 | MLX5_AAA_111 | |
714 | }; | |
715 | ||
716 | struct mlx5_hca_vport_context { | |
717 | u32 field_select; | |
718 | bool sm_virt_aware; | |
719 | bool has_smi; | |
720 | bool has_raw; | |
721 | enum port_state_policy policy; | |
722 | enum phy_port_state phys_state; | |
723 | enum ib_port_state vport_state; | |
724 | u8 port_physical_state; | |
725 | u64 sys_image_guid; | |
726 | u64 port_guid; | |
727 | u64 node_guid; | |
728 | u32 cap_mask1; | |
729 | u32 cap_mask1_perm; | |
730 | u32 cap_mask2; | |
731 | u32 cap_mask2_perm; | |
732 | u16 lid; | |
733 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
734 | u8 lmc; | |
735 | u8 subnet_timeout; | |
736 | u16 sm_lid; | |
737 | u8 sm_sl; | |
738 | u16 qkey_violation_counter; | |
739 | u16 pkey_violation_counter; | |
740 | bool grh_required; | |
741 | }; | |
742 | ||
e126ba97 EC |
743 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
744 | { | |
e126ba97 | 745 | return buf->direct.buf + offset; |
e126ba97 EC |
746 | } |
747 | ||
748 | extern struct workqueue_struct *mlx5_core_wq; | |
749 | ||
750 | #define STRUCT_FIELD(header, field) \ | |
751 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
752 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
753 | ||
e126ba97 EC |
754 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
755 | { | |
756 | return pci_get_drvdata(pdev); | |
757 | } | |
758 | ||
759 | extern struct dentry *mlx5_debugfs_root; | |
760 | ||
761 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
762 | { | |
763 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
764 | } | |
765 | ||
766 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
767 | { | |
768 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
769 | } | |
770 | ||
771 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
772 | { | |
773 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
774 | } | |
775 | ||
776 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
777 | { | |
778 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
779 | } | |
780 | ||
781 | static inline void *mlx5_vzalloc(unsigned long size) | |
782 | { | |
783 | void *rtn; | |
784 | ||
785 | rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); | |
786 | if (!rtn) | |
787 | rtn = vzalloc(size); | |
788 | return rtn; | |
789 | } | |
790 | ||
3bcdb17a SG |
791 | static inline u32 mlx5_base_mkey(const u32 key) |
792 | { | |
793 | return key & 0xffffff00u; | |
794 | } | |
795 | ||
e126ba97 EC |
796 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
797 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
798 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
799 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 800 | |
e126ba97 EC |
801 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
802 | int out_size); | |
746b5583 EC |
803 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
804 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
805 | void *context); | |
c4f287c4 SM |
806 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
807 | ||
808 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
809 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
810 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
811 | int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
812 | int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
0ba42241 ML |
813 | int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar, |
814 | bool map_wc); | |
e281682b | 815 | void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); |
ac6ea6e8 EC |
816 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
817 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
818 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
819 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
05ac2c0b | 820 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
311c7c71 SM |
821 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
822 | struct mlx5_buf *buf, int node); | |
64ffaa21 | 823 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 EC |
824 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
825 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
826 | gfp_t flags, int npages); | |
827 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
828 | struct mlx5_cmd_mailbox *head); | |
829 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 830 | struct mlx5_srq_attr *in); |
e126ba97 EC |
831 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
832 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 833 | struct mlx5_srq_attr *out); |
e126ba97 EC |
834 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
835 | u16 lwm, int is_srq); | |
a606b0f6 MB |
836 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
837 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
838 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
839 | struct mlx5_core_mkey *mkey, | |
840 | u32 *in, int inlen, | |
841 | u32 *out, int outlen, | |
842 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
843 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
844 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 845 | u32 *in, int inlen); |
a606b0f6 MB |
846 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
847 | struct mlx5_core_mkey *mkey); | |
848 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 849 | u32 *out, int outlen); |
a606b0f6 | 850 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, |
e126ba97 EC |
851 | u32 *mkey); |
852 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
853 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 854 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 855 | u16 opmod, u8 port); |
e126ba97 EC |
856 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
857 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
858 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
859 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
860 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 861 | s32 npages); |
cd23b14b | 862 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
863 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
864 | void mlx5_register_debugfs(void); | |
865 | void mlx5_unregister_debugfs(void); | |
866 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
867 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
868 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
869 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); | |
5903325a | 870 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e420f0c0 HE |
871 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
872 | void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); | |
873 | #endif | |
e126ba97 EC |
874 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
875 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
020446e0 | 876 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); |
e126ba97 EC |
877 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
878 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
879 | int nent, u64 mask, const char *name, struct mlx5_uar *uar); | |
880 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
881 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
882 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
0b6e26ce DT |
883 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
884 | unsigned int *irqn); | |
e126ba97 EC |
885 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
886 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
887 | ||
888 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
889 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
890 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
891 | int size_in, void *data_out, int size_out, | |
892 | u16 reg_num, int arg, int write); | |
adb0c954 | 893 | |
e126ba97 EC |
894 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
895 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
896 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
73b626c1 | 897 | u32 *out, int outlen); |
e126ba97 EC |
898 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); |
899 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
900 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
901 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
902 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
311c7c71 SM |
903 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
904 | int node); | |
e126ba97 EC |
905 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
906 | ||
e126ba97 EC |
907 | const char *mlx5_command_str(int command); |
908 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
909 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
910 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
911 | int npsvs, u32 *sig_index); | |
912 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 913 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
914 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
915 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
916 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
917 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 918 | |
1466cc5b YP |
919 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
920 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
921 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); | |
922 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); | |
923 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); | |
924 | ||
e3297246 EC |
925 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
926 | { | |
927 | return ioread32be(&dev->iseg->initializing) >> 31; | |
928 | } | |
929 | ||
e126ba97 EC |
930 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
931 | { | |
932 | return mkey >> 8; | |
933 | } | |
934 | ||
935 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
936 | { | |
937 | return mkey_idx << 8; | |
938 | } | |
939 | ||
746b5583 EC |
940 | static inline u8 mlx5_mkey_variant(u32 mkey) |
941 | { | |
942 | return mkey & 0xff; | |
943 | } | |
944 | ||
e126ba97 EC |
945 | enum { |
946 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 947 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
948 | }; |
949 | ||
950 | enum { | |
951 | MAX_MR_CACHE_ENTRIES = 16, | |
952 | }; | |
953 | ||
64613d94 SM |
954 | enum { |
955 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
956 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
957 | }; | |
958 | ||
9603b61d JM |
959 | struct mlx5_interface { |
960 | void * (*add)(struct mlx5_core_dev *dev); | |
961 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
962 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
963 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 964 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 965 | enum mlx5_dev_event event, unsigned long param); |
64613d94 SM |
966 | void * (*get_dev)(void *context); |
967 | int protocol; | |
9603b61d JM |
968 | struct list_head list; |
969 | }; | |
970 | ||
64613d94 | 971 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
972 | int mlx5_register_interface(struct mlx5_interface *intf); |
973 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 974 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 975 | |
3bc34f3b AH |
976 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
977 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 978 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 979 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
7907f23a | 980 | |
e126ba97 EC |
981 | struct mlx5_profile { |
982 | u64 mask; | |
f241e749 | 983 | u8 log_max_qp; |
e126ba97 EC |
984 | struct { |
985 | int size; | |
986 | int limit; | |
987 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
988 | }; | |
989 | ||
fc50db98 EC |
990 | enum { |
991 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
992 | }; | |
993 | ||
994 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
995 | { | |
996 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
997 | } | |
998 | ||
707c4602 MD |
999 | static inline int mlx5_get_gid_table_len(u16 param) |
1000 | { | |
1001 | if (param > 4) { | |
1002 | pr_warn("gid table length is zero\n"); | |
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | return 8 * (1 << param); | |
1007 | } | |
1008 | ||
1466cc5b YP |
1009 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1010 | { | |
1011 | return !!(dev->priv.rl_table.max_size); | |
1012 | } | |
1013 | ||
020446e0 EC |
1014 | enum { |
1015 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1016 | }; | |
1017 | ||
e126ba97 | 1018 | #endif /* MLX5_DRIVER_H */ |