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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
6ecde51d | 44 | |
e126ba97 EC |
45 | #include <linux/mlx5/device.h> |
46 | #include <linux/mlx5/doorbell.h> | |
47 | ||
48 | enum { | |
49 | MLX5_BOARD_ID_LEN = 64, | |
50 | MLX5_MAX_NAME_LEN = 16, | |
51 | }; | |
52 | ||
53 | enum { | |
54 | /* one minute for the sake of bringup. Generally, commands must always | |
55 | * complete and we may need to increase this timeout value | |
56 | */ | |
57 | MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, | |
58 | MLX5_CMD_WQ_MAX_NAME = 32, | |
59 | }; | |
60 | ||
61 | enum { | |
62 | CMD_OWNER_SW = 0x0, | |
63 | CMD_OWNER_HW = 0x1, | |
64 | CMD_STATUS_SUCCESS = 0, | |
65 | }; | |
66 | ||
67 | enum mlx5_sqp_t { | |
68 | MLX5_SQP_SMI = 0, | |
69 | MLX5_SQP_GSI = 1, | |
70 | MLX5_SQP_IEEE_1588 = 2, | |
71 | MLX5_SQP_SNIFFER = 3, | |
72 | MLX5_SQP_SYNC_UMR = 4, | |
73 | }; | |
74 | ||
75 | enum { | |
76 | MLX5_MAX_PORTS = 2, | |
77 | }; | |
78 | ||
79 | enum { | |
80 | MLX5_EQ_VEC_PAGES = 0, | |
81 | MLX5_EQ_VEC_CMD = 1, | |
82 | MLX5_EQ_VEC_ASYNC = 2, | |
83 | MLX5_EQ_VEC_COMP_BASE, | |
84 | }; | |
85 | ||
86 | enum { | |
db058a18 | 87 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
88 | }; |
89 | ||
90 | enum { | |
91 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
92 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
93 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
94 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
95 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
96 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
97 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
98 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
99 | }; | |
100 | ||
e126ba97 | 101 | enum { |
4f3961ee SM |
102 | MLX5_REG_QETCR = 0x4005, |
103 | MLX5_REG_QTCT = 0x400a, | |
e126ba97 EC |
104 | MLX5_REG_PCAP = 0x5001, |
105 | MLX5_REG_PMTU = 0x5003, | |
106 | MLX5_REG_PTYS = 0x5004, | |
107 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 108 | MLX5_REG_PFCC = 0x5007, |
efea389d | 109 | MLX5_REG_PPCNT = 0x5008, |
e126ba97 EC |
110 | MLX5_REG_PMAOS = 0x5012, |
111 | MLX5_REG_PUDE = 0x5009, | |
112 | MLX5_REG_PMPE = 0x5010, | |
113 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 114 | MLX5_REG_PVLC = 0x500f, |
e126ba97 EC |
115 | MLX5_REG_PMLP = 0, /* TBD */ |
116 | MLX5_REG_NODE_DESC = 0x6001, | |
117 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
118 | }; | |
119 | ||
da7525d2 EBE |
120 | enum { |
121 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
122 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
123 | }; | |
124 | ||
e420f0c0 HE |
125 | enum mlx5_page_fault_resume_flags { |
126 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
127 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
128 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
129 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
130 | }; | |
131 | ||
e126ba97 EC |
132 | enum dbg_rsc_type { |
133 | MLX5_DBG_RSC_QP, | |
134 | MLX5_DBG_RSC_EQ, | |
135 | MLX5_DBG_RSC_CQ, | |
136 | }; | |
137 | ||
138 | struct mlx5_field_desc { | |
139 | struct dentry *dent; | |
140 | int i; | |
141 | }; | |
142 | ||
143 | struct mlx5_rsc_debug { | |
144 | struct mlx5_core_dev *dev; | |
145 | void *object; | |
146 | enum dbg_rsc_type type; | |
147 | struct dentry *root; | |
148 | struct mlx5_field_desc fields[0]; | |
149 | }; | |
150 | ||
151 | enum mlx5_dev_event { | |
152 | MLX5_DEV_EVENT_SYS_ERROR, | |
153 | MLX5_DEV_EVENT_PORT_UP, | |
154 | MLX5_DEV_EVENT_PORT_DOWN, | |
155 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
156 | MLX5_DEV_EVENT_LID_CHANGE, | |
157 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
158 | MLX5_DEV_EVENT_GUID_CHANGE, | |
159 | MLX5_DEV_EVENT_CLIENT_REREG, | |
160 | }; | |
161 | ||
4c916a79 | 162 | enum mlx5_port_status { |
6fa1bcab AS |
163 | MLX5_PORT_UP = 1, |
164 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
165 | }; |
166 | ||
e126ba97 EC |
167 | struct mlx5_uuar_info { |
168 | struct mlx5_uar *uars; | |
169 | int num_uars; | |
170 | int num_low_latency_uuars; | |
171 | unsigned long *bitmap; | |
172 | unsigned int *count; | |
173 | struct mlx5_bf *bfs; | |
174 | ||
175 | /* | |
176 | * protect uuar allocation data structs | |
177 | */ | |
178 | struct mutex lock; | |
78c0f98c | 179 | u32 ver; |
e126ba97 EC |
180 | }; |
181 | ||
182 | struct mlx5_bf { | |
183 | void __iomem *reg; | |
184 | void __iomem *regreg; | |
185 | int buf_size; | |
186 | struct mlx5_uar *uar; | |
187 | unsigned long offset; | |
188 | int need_lock; | |
189 | /* protect blue flame buffer selection when needed | |
190 | */ | |
191 | spinlock_t lock; | |
192 | ||
193 | /* serialize 64 bit writes when done as two 32 bit accesses | |
194 | */ | |
195 | spinlock_t lock32; | |
196 | int uuarn; | |
197 | }; | |
198 | ||
199 | struct mlx5_cmd_first { | |
200 | __be32 data[4]; | |
201 | }; | |
202 | ||
203 | struct mlx5_cmd_msg { | |
204 | struct list_head list; | |
205 | struct cache_ent *cache; | |
206 | u32 len; | |
207 | struct mlx5_cmd_first first; | |
208 | struct mlx5_cmd_mailbox *next; | |
209 | }; | |
210 | ||
211 | struct mlx5_cmd_debug { | |
212 | struct dentry *dbg_root; | |
213 | struct dentry *dbg_in; | |
214 | struct dentry *dbg_out; | |
215 | struct dentry *dbg_outlen; | |
216 | struct dentry *dbg_status; | |
217 | struct dentry *dbg_run; | |
218 | void *in_msg; | |
219 | void *out_msg; | |
220 | u8 status; | |
221 | u16 inlen; | |
222 | u16 outlen; | |
223 | }; | |
224 | ||
225 | struct cache_ent { | |
226 | /* protect block chain allocations | |
227 | */ | |
228 | spinlock_t lock; | |
229 | struct list_head head; | |
230 | }; | |
231 | ||
232 | struct cmd_msg_cache { | |
233 | struct cache_ent large; | |
234 | struct cache_ent med; | |
235 | ||
236 | }; | |
237 | ||
238 | struct mlx5_cmd_stats { | |
239 | u64 sum; | |
240 | u64 n; | |
241 | struct dentry *root; | |
242 | struct dentry *avg; | |
243 | struct dentry *count; | |
244 | /* protect command average calculations */ | |
245 | spinlock_t lock; | |
246 | }; | |
247 | ||
248 | struct mlx5_cmd { | |
64599cca EC |
249 | void *cmd_alloc_buf; |
250 | dma_addr_t alloc_dma; | |
251 | int alloc_size; | |
e126ba97 EC |
252 | void *cmd_buf; |
253 | dma_addr_t dma; | |
254 | u16 cmdif_rev; | |
255 | u8 log_sz; | |
256 | u8 log_stride; | |
257 | int max_reg_cmds; | |
258 | int events; | |
259 | u32 __iomem *vector; | |
260 | ||
261 | /* protect command queue allocations | |
262 | */ | |
263 | spinlock_t alloc_lock; | |
264 | ||
265 | /* protect token allocations | |
266 | */ | |
267 | spinlock_t token_lock; | |
268 | u8 token; | |
269 | unsigned long bitmask; | |
270 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
271 | struct workqueue_struct *wq; | |
272 | struct semaphore sem; | |
273 | struct semaphore pages_sem; | |
274 | int mode; | |
275 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
276 | struct pci_pool *pool; | |
277 | struct mlx5_cmd_debug dbg; | |
278 | struct cmd_msg_cache cache; | |
279 | int checksum_disabled; | |
280 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
281 | }; | |
282 | ||
283 | struct mlx5_port_caps { | |
284 | int gid_table_len; | |
285 | int pkey_table_len; | |
938fe83c | 286 | u8 ext_port_cap; |
e126ba97 EC |
287 | }; |
288 | ||
289 | struct mlx5_cmd_mailbox { | |
290 | void *buf; | |
291 | dma_addr_t dma; | |
292 | struct mlx5_cmd_mailbox *next; | |
293 | }; | |
294 | ||
295 | struct mlx5_buf_list { | |
296 | void *buf; | |
297 | dma_addr_t map; | |
298 | }; | |
299 | ||
300 | struct mlx5_buf { | |
301 | struct mlx5_buf_list direct; | |
e126ba97 | 302 | int npages; |
e126ba97 | 303 | int size; |
f241e749 | 304 | u8 page_shift; |
e126ba97 EC |
305 | }; |
306 | ||
307 | struct mlx5_eq { | |
308 | struct mlx5_core_dev *dev; | |
309 | __be32 __iomem *doorbell; | |
310 | u32 cons_index; | |
311 | struct mlx5_buf buf; | |
312 | int size; | |
0b6e26ce | 313 | unsigned int irqn; |
e126ba97 EC |
314 | u8 eqn; |
315 | int nent; | |
316 | u64 mask; | |
e126ba97 EC |
317 | struct list_head list; |
318 | int index; | |
319 | struct mlx5_rsc_debug *dbg; | |
320 | }; | |
321 | ||
3121e3c4 SG |
322 | struct mlx5_core_psv { |
323 | u32 psv_idx; | |
324 | struct psv_layout { | |
325 | u32 pd; | |
326 | u16 syndrome; | |
327 | u16 reserved; | |
328 | u16 bg; | |
329 | u16 app_tag; | |
330 | u32 ref_tag; | |
331 | } psv; | |
332 | }; | |
333 | ||
334 | struct mlx5_core_sig_ctx { | |
335 | struct mlx5_core_psv psv_memory; | |
336 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
337 | struct ib_sig_err err_item; |
338 | bool sig_status_checked; | |
339 | bool sig_err_exists; | |
340 | u32 sigerr_count; | |
3121e3c4 | 341 | }; |
e126ba97 EC |
342 | |
343 | struct mlx5_core_mr { | |
344 | u64 iova; | |
345 | u64 size; | |
346 | u32 key; | |
347 | u32 pd; | |
e126ba97 EC |
348 | }; |
349 | ||
5903325a | 350 | enum mlx5_res_type { |
e2013b21 | 351 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
352 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
353 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
354 | MLX5_RES_SRQ = 3, | |
355 | MLX5_RES_XSRQ = 4, | |
5903325a EC |
356 | }; |
357 | ||
358 | struct mlx5_core_rsc_common { | |
359 | enum mlx5_res_type res; | |
360 | atomic_t refcount; | |
361 | struct completion free; | |
362 | }; | |
363 | ||
e126ba97 | 364 | struct mlx5_core_srq { |
01949d01 | 365 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
366 | u32 srqn; |
367 | int max; | |
368 | int max_gs; | |
369 | int max_avail_gather; | |
370 | int wqe_shift; | |
371 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
372 | ||
373 | atomic_t refcount; | |
374 | struct completion free; | |
375 | }; | |
376 | ||
377 | struct mlx5_eq_table { | |
378 | void __iomem *update_ci; | |
379 | void __iomem *update_arm_ci; | |
233d05d2 | 380 | struct list_head comp_eqs_list; |
e126ba97 EC |
381 | struct mlx5_eq pages_eq; |
382 | struct mlx5_eq async_eq; | |
383 | struct mlx5_eq cmd_eq; | |
e126ba97 EC |
384 | int num_comp_vectors; |
385 | /* protect EQs list | |
386 | */ | |
387 | spinlock_t lock; | |
388 | }; | |
389 | ||
390 | struct mlx5_uar { | |
391 | u32 index; | |
392 | struct list_head bf_list; | |
393 | unsigned free_bf_bmap; | |
88a85f99 | 394 | void __iomem *bf_map; |
e126ba97 EC |
395 | void __iomem *map; |
396 | }; | |
397 | ||
398 | ||
399 | struct mlx5_core_health { | |
400 | struct health_buffer __iomem *health; | |
401 | __be32 __iomem *health_counter; | |
402 | struct timer_list timer; | |
e126ba97 EC |
403 | u32 prev; |
404 | int miss_counter; | |
fd76ee4d | 405 | bool sick; |
ac6ea6e8 EC |
406 | struct workqueue_struct *wq; |
407 | struct work_struct work; | |
e126ba97 EC |
408 | }; |
409 | ||
410 | struct mlx5_cq_table { | |
411 | /* protect radix tree | |
412 | */ | |
413 | spinlock_t lock; | |
414 | struct radix_tree_root tree; | |
415 | }; | |
416 | ||
417 | struct mlx5_qp_table { | |
418 | /* protect radix tree | |
419 | */ | |
420 | spinlock_t lock; | |
421 | struct radix_tree_root tree; | |
422 | }; | |
423 | ||
424 | struct mlx5_srq_table { | |
425 | /* protect radix tree | |
426 | */ | |
427 | spinlock_t lock; | |
428 | struct radix_tree_root tree; | |
429 | }; | |
430 | ||
3bcdb17a SG |
431 | struct mlx5_mr_table { |
432 | /* protect radix tree | |
433 | */ | |
434 | rwlock_t lock; | |
435 | struct radix_tree_root tree; | |
436 | }; | |
437 | ||
fc50db98 EC |
438 | struct mlx5_vf_context { |
439 | int enabled; | |
440 | }; | |
441 | ||
442 | struct mlx5_core_sriov { | |
443 | struct mlx5_vf_context *vfs_ctx; | |
444 | int num_vfs; | |
445 | int enabled_vfs; | |
446 | }; | |
447 | ||
db058a18 SM |
448 | struct mlx5_irq_info { |
449 | cpumask_var_t mask; | |
450 | char name[MLX5_MAX_IRQ_NAME]; | |
451 | }; | |
452 | ||
073bb189 SM |
453 | struct mlx5_eswitch; |
454 | ||
e126ba97 EC |
455 | struct mlx5_priv { |
456 | char name[MLX5_MAX_NAME_LEN]; | |
457 | struct mlx5_eq_table eq_table; | |
db058a18 SM |
458 | struct msix_entry *msix_arr; |
459 | struct mlx5_irq_info *irq_info; | |
e126ba97 EC |
460 | struct mlx5_uuar_info uuari; |
461 | MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); | |
462 | ||
88a85f99 AS |
463 | struct io_mapping *bf_mapping; |
464 | ||
e126ba97 EC |
465 | /* pages stuff */ |
466 | struct workqueue_struct *pg_wq; | |
467 | struct rb_root page_root; | |
468 | int fw_pages; | |
6aec21f6 | 469 | atomic_t reg_pages; |
bf0bf77f | 470 | struct list_head free_list; |
fc50db98 | 471 | int vfs_pages; |
e126ba97 EC |
472 | |
473 | struct mlx5_core_health health; | |
474 | ||
475 | struct mlx5_srq_table srq_table; | |
476 | ||
477 | /* start: qp staff */ | |
478 | struct mlx5_qp_table qp_table; | |
479 | struct dentry *qp_debugfs; | |
480 | struct dentry *eq_debugfs; | |
481 | struct dentry *cq_debugfs; | |
482 | struct dentry *cmdif_debugfs; | |
483 | /* end: qp staff */ | |
484 | ||
485 | /* start: cq staff */ | |
486 | struct mlx5_cq_table cq_table; | |
487 | /* end: cq staff */ | |
488 | ||
3bcdb17a SG |
489 | /* start: mr staff */ |
490 | struct mlx5_mr_table mr_table; | |
491 | /* end: mr staff */ | |
492 | ||
e126ba97 | 493 | /* start: alloc staff */ |
311c7c71 SM |
494 | /* protect buffer alocation according to numa node */ |
495 | struct mutex alloc_mutex; | |
496 | int numa_node; | |
497 | ||
e126ba97 EC |
498 | struct mutex pgdir_mutex; |
499 | struct list_head pgdir_list; | |
500 | /* end: alloc staff */ | |
501 | struct dentry *dbg_root; | |
502 | ||
503 | /* protect mkey key part */ | |
504 | spinlock_t mkey_lock; | |
505 | u8 mkey_key; | |
9603b61d JM |
506 | |
507 | struct list_head dev_list; | |
508 | struct list_head ctx_list; | |
509 | spinlock_t ctx_lock; | |
073bb189 SM |
510 | |
511 | struct mlx5_eswitch *eswitch; | |
fc50db98 EC |
512 | struct mlx5_core_sriov sriov; |
513 | unsigned long pci_dev_data; | |
25302363 MG |
514 | struct mlx5_flow_root_namespace *root_ns; |
515 | struct mlx5_flow_root_namespace *fdb_root_ns; | |
e126ba97 EC |
516 | }; |
517 | ||
89d44f0a MD |
518 | enum mlx5_device_state { |
519 | MLX5_DEVICE_STATE_UP, | |
520 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
521 | }; | |
522 | ||
523 | enum mlx5_interface_state { | |
524 | MLX5_INTERFACE_STATE_DOWN, | |
525 | MLX5_INTERFACE_STATE_UP, | |
526 | }; | |
527 | ||
528 | enum mlx5_pci_status { | |
529 | MLX5_PCI_STATUS_DISABLED, | |
530 | MLX5_PCI_STATUS_ENABLED, | |
531 | }; | |
532 | ||
e126ba97 EC |
533 | struct mlx5_core_dev { |
534 | struct pci_dev *pdev; | |
89d44f0a MD |
535 | /* sync pci state */ |
536 | struct mutex pci_status_mutex; | |
537 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
538 | u8 rev_id; |
539 | char board_id[MLX5_BOARD_ID_LEN]; | |
540 | struct mlx5_cmd cmd; | |
938fe83c SM |
541 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
542 | u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
543 | u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
e126ba97 EC |
544 | phys_addr_t iseg_base; |
545 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
546 | enum mlx5_device_state state; |
547 | /* sync interface state */ | |
548 | struct mutex intf_state_mutex; | |
549 | enum mlx5_interface_state interface_state; | |
e126ba97 EC |
550 | void (*event) (struct mlx5_core_dev *dev, |
551 | enum mlx5_dev_event event, | |
4d2f9bbb | 552 | unsigned long param); |
e126ba97 EC |
553 | struct mlx5_priv priv; |
554 | struct mlx5_profile *profile; | |
555 | atomic_t num_qps; | |
f62b8bb8 | 556 | u32 issi; |
e126ba97 EC |
557 | }; |
558 | ||
559 | struct mlx5_db { | |
560 | __be32 *db; | |
561 | union { | |
562 | struct mlx5_db_pgdir *pgdir; | |
563 | struct mlx5_ib_user_db_page *user_page; | |
564 | } u; | |
565 | dma_addr_t dma; | |
566 | int index; | |
567 | }; | |
568 | ||
569 | enum { | |
570 | MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, | |
571 | }; | |
572 | ||
573 | enum { | |
574 | MLX5_COMP_EQ_SIZE = 1024, | |
575 | }; | |
576 | ||
adb0c954 SM |
577 | enum { |
578 | MLX5_PTYS_IB = 1 << 0, | |
579 | MLX5_PTYS_EN = 1 << 2, | |
580 | }; | |
581 | ||
e126ba97 EC |
582 | struct mlx5_db_pgdir { |
583 | struct list_head list; | |
584 | DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); | |
585 | __be32 *db_page; | |
586 | dma_addr_t db_dma; | |
587 | }; | |
588 | ||
589 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); | |
590 | ||
591 | struct mlx5_cmd_work_ent { | |
592 | struct mlx5_cmd_msg *in; | |
593 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
594 | void *uout; |
595 | int uout_size; | |
e126ba97 EC |
596 | mlx5_cmd_cbk_t callback; |
597 | void *context; | |
746b5583 | 598 | int idx; |
e126ba97 EC |
599 | struct completion done; |
600 | struct mlx5_cmd *cmd; | |
601 | struct work_struct work; | |
602 | struct mlx5_cmd_layout *lay; | |
603 | int ret; | |
604 | int page_queue; | |
605 | u8 status; | |
606 | u8 token; | |
14a70046 TG |
607 | u64 ts1; |
608 | u64 ts2; | |
746b5583 | 609 | u16 op; |
e126ba97 EC |
610 | }; |
611 | ||
612 | struct mlx5_pas { | |
613 | u64 pa; | |
614 | u8 log_sz; | |
615 | }; | |
616 | ||
707c4602 MD |
617 | enum port_state_policy { |
618 | MLX5_AAA_000 | |
619 | }; | |
620 | ||
621 | enum phy_port_state { | |
622 | MLX5_AAA_111 | |
623 | }; | |
624 | ||
625 | struct mlx5_hca_vport_context { | |
626 | u32 field_select; | |
627 | bool sm_virt_aware; | |
628 | bool has_smi; | |
629 | bool has_raw; | |
630 | enum port_state_policy policy; | |
631 | enum phy_port_state phys_state; | |
632 | enum ib_port_state vport_state; | |
633 | u8 port_physical_state; | |
634 | u64 sys_image_guid; | |
635 | u64 port_guid; | |
636 | u64 node_guid; | |
637 | u32 cap_mask1; | |
638 | u32 cap_mask1_perm; | |
639 | u32 cap_mask2; | |
640 | u32 cap_mask2_perm; | |
641 | u16 lid; | |
642 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
643 | u8 lmc; | |
644 | u8 subnet_timeout; | |
645 | u16 sm_lid; | |
646 | u8 sm_sl; | |
647 | u16 qkey_violation_counter; | |
648 | u16 pkey_violation_counter; | |
649 | bool grh_required; | |
650 | }; | |
651 | ||
e126ba97 EC |
652 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
653 | { | |
e126ba97 | 654 | return buf->direct.buf + offset; |
e126ba97 EC |
655 | } |
656 | ||
657 | extern struct workqueue_struct *mlx5_core_wq; | |
658 | ||
659 | #define STRUCT_FIELD(header, field) \ | |
660 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
661 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
662 | ||
e126ba97 EC |
663 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
664 | { | |
665 | return pci_get_drvdata(pdev); | |
666 | } | |
667 | ||
668 | extern struct dentry *mlx5_debugfs_root; | |
669 | ||
670 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
671 | { | |
672 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
673 | } | |
674 | ||
675 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
676 | { | |
677 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
678 | } | |
679 | ||
680 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
681 | { | |
682 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
683 | } | |
684 | ||
685 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
686 | { | |
687 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
688 | } | |
689 | ||
690 | static inline void *mlx5_vzalloc(unsigned long size) | |
691 | { | |
692 | void *rtn; | |
693 | ||
694 | rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); | |
695 | if (!rtn) | |
696 | rtn = vzalloc(size); | |
697 | return rtn; | |
698 | } | |
699 | ||
3bcdb17a SG |
700 | static inline u32 mlx5_base_mkey(const u32 key) |
701 | { | |
702 | return key & 0xffffff00u; | |
703 | } | |
704 | ||
e126ba97 EC |
705 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
706 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
707 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
708 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
709 | int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); | |
b775516b | 710 | int mlx5_cmd_status_to_err_v2(void *ptr); |
938fe83c SM |
711 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, |
712 | enum mlx5_cap_mode cap_mode); | |
e126ba97 EC |
713 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
714 | int out_size); | |
746b5583 EC |
715 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
716 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
717 | void *context); | |
e126ba97 EC |
718 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
719 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
720 | int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
721 | int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
e281682b SM |
722 | int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); |
723 | void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); | |
ac6ea6e8 EC |
724 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
725 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
726 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
727 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
311c7c71 SM |
728 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
729 | struct mlx5_buf *buf, int node); | |
64ffaa21 | 730 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 EC |
731 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
732 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
733 | gfp_t flags, int npages); | |
734 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
735 | struct mlx5_cmd_mailbox *head); | |
736 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
01949d01 HA |
737 | struct mlx5_create_srq_mbox_in *in, int inlen, |
738 | int is_xrc); | |
e126ba97 EC |
739 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
740 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
741 | struct mlx5_query_srq_mbox_out *out); | |
742 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
743 | u16 lwm, int is_srq); | |
3bcdb17a SG |
744 | void mlx5_init_mr_table(struct mlx5_core_dev *dev); |
745 | void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); | |
e126ba97 | 746 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, |
746b5583 EC |
747 | struct mlx5_create_mkey_mbox_in *in, int inlen, |
748 | mlx5_cmd_cbk_t callback, void *context, | |
749 | struct mlx5_create_mkey_mbox_out *out); | |
e126ba97 EC |
750 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); |
751 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
752 | struct mlx5_query_mkey_mbox_out *out, int outlen); | |
753 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
754 | u32 *mkey); | |
755 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
756 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 757 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 758 | u16 opmod, u8 port); |
e126ba97 EC |
759 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
760 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
761 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
762 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
fc50db98 EC |
763 | int mlx5_sriov_init(struct mlx5_core_dev *dev); |
764 | int mlx5_sriov_cleanup(struct mlx5_core_dev *dev); | |
e126ba97 | 765 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, |
0a324f31 | 766 | s32 npages); |
cd23b14b | 767 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
768 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
769 | void mlx5_register_debugfs(void); | |
770 | void mlx5_unregister_debugfs(void); | |
771 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
772 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
773 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
774 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); | |
5903325a | 775 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e420f0c0 HE |
776 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
777 | void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); | |
778 | #endif | |
e126ba97 EC |
779 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
780 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
020446e0 | 781 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); |
e126ba97 EC |
782 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
783 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
784 | int nent, u64 mask, const char *name, struct mlx5_uar *uar); | |
785 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
786 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
787 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
0b6e26ce DT |
788 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
789 | unsigned int *irqn); | |
e126ba97 EC |
790 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
791 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
792 | ||
793 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
794 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
795 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
796 | int size_in, void *data_out, int size_out, | |
797 | u16 reg_num, int arg, int write); | |
adb0c954 | 798 | |
e126ba97 EC |
799 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
800 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
801 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
802 | struct mlx5_query_eq_mbox_out *out, int outlen); | |
803 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); | |
804 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
805 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
806 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
807 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
311c7c71 SM |
808 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
809 | int node); | |
e126ba97 EC |
810 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
811 | ||
e126ba97 EC |
812 | const char *mlx5_command_str(int command); |
813 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
814 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
815 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
816 | int npsvs, u32 *sig_index); | |
817 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 818 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
819 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
820 | struct mlx5_odp_caps *odp_caps); | |
e126ba97 | 821 | |
e3297246 EC |
822 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
823 | { | |
824 | return ioread32be(&dev->iseg->initializing) >> 31; | |
825 | } | |
826 | ||
e126ba97 EC |
827 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
828 | { | |
829 | return mkey >> 8; | |
830 | } | |
831 | ||
832 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
833 | { | |
834 | return mkey_idx << 8; | |
835 | } | |
836 | ||
746b5583 EC |
837 | static inline u8 mlx5_mkey_variant(u32 mkey) |
838 | { | |
839 | return mkey & 0xff; | |
840 | } | |
841 | ||
e126ba97 EC |
842 | enum { |
843 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 844 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
845 | }; |
846 | ||
847 | enum { | |
848 | MAX_MR_CACHE_ENTRIES = 16, | |
849 | }; | |
850 | ||
64613d94 SM |
851 | enum { |
852 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
853 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
854 | }; | |
855 | ||
9603b61d JM |
856 | struct mlx5_interface { |
857 | void * (*add)(struct mlx5_core_dev *dev); | |
858 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
859 | void (*event)(struct mlx5_core_dev *dev, void *context, | |
4d2f9bbb | 860 | enum mlx5_dev_event event, unsigned long param); |
64613d94 SM |
861 | void * (*get_dev)(void *context); |
862 | int protocol; | |
9603b61d JM |
863 | struct list_head list; |
864 | }; | |
865 | ||
64613d94 | 866 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
867 | int mlx5_register_interface(struct mlx5_interface *intf); |
868 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 869 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 870 | |
e126ba97 EC |
871 | struct mlx5_profile { |
872 | u64 mask; | |
f241e749 | 873 | u8 log_max_qp; |
e126ba97 EC |
874 | struct { |
875 | int size; | |
876 | int limit; | |
877 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
878 | }; | |
879 | ||
fc50db98 EC |
880 | enum { |
881 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
882 | }; | |
883 | ||
884 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
885 | { | |
886 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
887 | } | |
888 | ||
707c4602 MD |
889 | static inline int mlx5_get_gid_table_len(u16 param) |
890 | { | |
891 | if (param > 4) { | |
892 | pr_warn("gid table length is zero\n"); | |
893 | return 0; | |
894 | } | |
895 | ||
896 | return 8 * (1 << param); | |
897 | } | |
898 | ||
020446e0 EC |
899 | enum { |
900 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
901 | }; | |
902 | ||
e126ba97 | 903 | #endif /* MLX5_DRIVER_H */ |