Commit | Line | Data |
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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 EC |
43 | #include <linux/vmalloc.h> |
44 | #include <linux/radix-tree.h> | |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
6ecde51d | 49 | |
e126ba97 EC |
50 | #include <linux/mlx5/device.h> |
51 | #include <linux/mlx5/doorbell.h> | |
af1ba291 | 52 | #include <linux/mlx5/srq.h> |
41069256 | 53 | #include <linux/mlx5/eq.h> |
7c39afb3 FD |
54 | #include <linux/timecounter.h> |
55 | #include <linux/ptp_clock_kernel.h> | |
e126ba97 EC |
56 | |
57 | enum { | |
58 | MLX5_BOARD_ID_LEN = 64, | |
59 | MLX5_MAX_NAME_LEN = 16, | |
60 | }; | |
61 | ||
62 | enum { | |
63 | /* one minute for the sake of bringup. Generally, commands must always | |
64 | * complete and we may need to increase this timeout value | |
65 | */ | |
6b6c07bd | 66 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
67 | MLX5_CMD_WQ_MAX_NAME = 32, |
68 | }; | |
69 | ||
70 | enum { | |
71 | CMD_OWNER_SW = 0x0, | |
72 | CMD_OWNER_HW = 0x1, | |
73 | CMD_STATUS_SUCCESS = 0, | |
74 | }; | |
75 | ||
76 | enum mlx5_sqp_t { | |
77 | MLX5_SQP_SMI = 0, | |
78 | MLX5_SQP_GSI = 1, | |
79 | MLX5_SQP_IEEE_1588 = 2, | |
80 | MLX5_SQP_SNIFFER = 3, | |
81 | MLX5_SQP_SYNC_UMR = 4, | |
82 | }; | |
83 | ||
84 | enum { | |
85 | MLX5_MAX_PORTS = 2, | |
86 | }; | |
87 | ||
e126ba97 | 88 | enum { |
a60109dc YC |
89 | MLX5_ATOMIC_MODE_OFFSET = 16, |
90 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
91 | MLX5_ATOMIC_MODE_CX = 2, | |
92 | MLX5_ATOMIC_MODE_8B = 3, | |
93 | MLX5_ATOMIC_MODE_16B = 4, | |
94 | MLX5_ATOMIC_MODE_32B = 5, | |
95 | MLX5_ATOMIC_MODE_64B = 6, | |
96 | MLX5_ATOMIC_MODE_128B = 7, | |
97 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
98 | }; |
99 | ||
e126ba97 | 100 | enum { |
415a64aa | 101 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
102 | MLX5_REG_QETCR = 0x4005, |
103 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 104 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 105 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
106 | MLX5_REG_DCBX_PARAM = 0x4020, |
107 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
108 | MLX5_REG_FPGA_CAP = 0x4022, |
109 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 110 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
e126ba97 EC |
111 | MLX5_REG_PCAP = 0x5001, |
112 | MLX5_REG_PMTU = 0x5003, | |
113 | MLX5_REG_PTYS = 0x5004, | |
114 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 115 | MLX5_REG_PFCC = 0x5007, |
efea389d | 116 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
117 | MLX5_REG_PPTB = 0x500b, |
118 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
119 | MLX5_REG_PMAOS = 0x5012, |
120 | MLX5_REG_PUDE = 0x5009, | |
121 | MLX5_REG_PMPE = 0x5010, | |
122 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 123 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 124 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 125 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 126 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 127 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
128 | MLX5_REG_NODE_DESC = 0x6001, |
129 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 130 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 131 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
132 | MLX5_REG_MTRC_CAP = 0x9040, |
133 | MLX5_REG_MTRC_CONF = 0x9041, | |
134 | MLX5_REG_MTRC_STDB = 0x9042, | |
135 | MLX5_REG_MTRC_CTRL = 0x9043, | |
8ed1a630 | 136 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
137 | MLX5_REG_MTPPS = 0x9053, |
138 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 139 | MLX5_REG_MPEGC = 0x9056, |
47176289 OG |
140 | MLX5_REG_MCQI = 0x9061, |
141 | MLX5_REG_MCC = 0x9062, | |
142 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 143 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
144 | }; |
145 | ||
415a64aa HN |
146 | enum mlx5_qpts_trust_state { |
147 | MLX5_QPTS_TRUST_PCP = 1, | |
148 | MLX5_QPTS_TRUST_DSCP = 2, | |
149 | }; | |
150 | ||
341c5ee2 HN |
151 | enum mlx5_dcbx_oper_mode { |
152 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
153 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
154 | }; | |
155 | ||
da7525d2 EBE |
156 | enum { |
157 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
158 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
159 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
160 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
161 | }; |
162 | ||
e420f0c0 HE |
163 | enum mlx5_page_fault_resume_flags { |
164 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
165 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
166 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
167 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
168 | }; | |
169 | ||
e126ba97 EC |
170 | enum dbg_rsc_type { |
171 | MLX5_DBG_RSC_QP, | |
172 | MLX5_DBG_RSC_EQ, | |
173 | MLX5_DBG_RSC_CQ, | |
174 | }; | |
175 | ||
7ecf6d8f BW |
176 | enum port_state_policy { |
177 | MLX5_POLICY_DOWN = 0, | |
178 | MLX5_POLICY_UP = 1, | |
179 | MLX5_POLICY_FOLLOW = 2, | |
180 | MLX5_POLICY_INVALID = 0xffffffff | |
181 | }; | |
182 | ||
e126ba97 EC |
183 | struct mlx5_field_desc { |
184 | struct dentry *dent; | |
185 | int i; | |
186 | }; | |
187 | ||
188 | struct mlx5_rsc_debug { | |
189 | struct mlx5_core_dev *dev; | |
190 | void *object; | |
191 | enum dbg_rsc_type type; | |
192 | struct dentry *root; | |
193 | struct mlx5_field_desc fields[0]; | |
194 | }; | |
195 | ||
196 | enum mlx5_dev_event { | |
197 | MLX5_DEV_EVENT_SYS_ERROR, | |
198 | MLX5_DEV_EVENT_PORT_UP, | |
199 | MLX5_DEV_EVENT_PORT_DOWN, | |
200 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
201 | MLX5_DEV_EVENT_LID_CHANGE, | |
202 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
203 | MLX5_DEV_EVENT_GUID_CHANGE, | |
204 | MLX5_DEV_EVENT_CLIENT_REREG, | |
f9a1ef72 | 205 | MLX5_DEV_EVENT_PPS, |
246ac981 | 206 | MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, |
e126ba97 EC |
207 | }; |
208 | ||
4c916a79 | 209 | enum mlx5_port_status { |
6fa1bcab AS |
210 | MLX5_PORT_UP = 1, |
211 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
212 | }; |
213 | ||
2f5ff264 | 214 | struct mlx5_bfreg_info { |
b037c29a | 215 | u32 *sys_pages; |
2f5ff264 | 216 | int num_low_latency_bfregs; |
e126ba97 | 217 | unsigned int *count; |
e126ba97 EC |
218 | |
219 | /* | |
2f5ff264 | 220 | * protect bfreg allocation data structs |
e126ba97 EC |
221 | */ |
222 | struct mutex lock; | |
78c0f98c | 223 | u32 ver; |
b037c29a EC |
224 | bool lib_uar_4k; |
225 | u32 num_sys_pages; | |
31a78a5a YH |
226 | u32 num_static_sys_pages; |
227 | u32 total_num_bfregs; | |
228 | u32 num_dyn_bfregs; | |
e126ba97 EC |
229 | }; |
230 | ||
231 | struct mlx5_cmd_first { | |
232 | __be32 data[4]; | |
233 | }; | |
234 | ||
235 | struct mlx5_cmd_msg { | |
236 | struct list_head list; | |
0ac3ea70 | 237 | struct cmd_msg_cache *parent; |
e126ba97 EC |
238 | u32 len; |
239 | struct mlx5_cmd_first first; | |
240 | struct mlx5_cmd_mailbox *next; | |
241 | }; | |
242 | ||
243 | struct mlx5_cmd_debug { | |
244 | struct dentry *dbg_root; | |
245 | struct dentry *dbg_in; | |
246 | struct dentry *dbg_out; | |
247 | struct dentry *dbg_outlen; | |
248 | struct dentry *dbg_status; | |
249 | struct dentry *dbg_run; | |
250 | void *in_msg; | |
251 | void *out_msg; | |
252 | u8 status; | |
253 | u16 inlen; | |
254 | u16 outlen; | |
255 | }; | |
256 | ||
0ac3ea70 | 257 | struct cmd_msg_cache { |
e126ba97 EC |
258 | /* protect block chain allocations |
259 | */ | |
260 | spinlock_t lock; | |
261 | struct list_head head; | |
0ac3ea70 MHY |
262 | unsigned int max_inbox_size; |
263 | unsigned int num_ent; | |
e126ba97 EC |
264 | }; |
265 | ||
0ac3ea70 MHY |
266 | enum { |
267 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
268 | }; |
269 | ||
270 | struct mlx5_cmd_stats { | |
271 | u64 sum; | |
272 | u64 n; | |
273 | struct dentry *root; | |
274 | struct dentry *avg; | |
275 | struct dentry *count; | |
276 | /* protect command average calculations */ | |
277 | spinlock_t lock; | |
278 | }; | |
279 | ||
280 | struct mlx5_cmd { | |
71edc69c SM |
281 | struct mlx5_nb nb; |
282 | ||
64599cca EC |
283 | void *cmd_alloc_buf; |
284 | dma_addr_t alloc_dma; | |
285 | int alloc_size; | |
e126ba97 EC |
286 | void *cmd_buf; |
287 | dma_addr_t dma; | |
288 | u16 cmdif_rev; | |
289 | u8 log_sz; | |
290 | u8 log_stride; | |
291 | int max_reg_cmds; | |
292 | int events; | |
293 | u32 __iomem *vector; | |
294 | ||
295 | /* protect command queue allocations | |
296 | */ | |
297 | spinlock_t alloc_lock; | |
298 | ||
299 | /* protect token allocations | |
300 | */ | |
301 | spinlock_t token_lock; | |
302 | u8 token; | |
303 | unsigned long bitmask; | |
304 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
305 | struct workqueue_struct *wq; | |
306 | struct semaphore sem; | |
307 | struct semaphore pages_sem; | |
308 | int mode; | |
309 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 310 | struct dma_pool *pool; |
e126ba97 | 311 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 312 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
313 | int checksum_disabled; |
314 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
315 | }; | |
316 | ||
317 | struct mlx5_port_caps { | |
318 | int gid_table_len; | |
319 | int pkey_table_len; | |
938fe83c | 320 | u8 ext_port_cap; |
c43f1112 | 321 | bool has_smi; |
e126ba97 EC |
322 | }; |
323 | ||
324 | struct mlx5_cmd_mailbox { | |
325 | void *buf; | |
326 | dma_addr_t dma; | |
327 | struct mlx5_cmd_mailbox *next; | |
328 | }; | |
329 | ||
330 | struct mlx5_buf_list { | |
331 | void *buf; | |
332 | dma_addr_t map; | |
333 | }; | |
334 | ||
1c1b5228 TT |
335 | struct mlx5_frag_buf { |
336 | struct mlx5_buf_list *frags; | |
337 | int npages; | |
338 | int size; | |
339 | u8 page_shift; | |
340 | }; | |
341 | ||
388ca8be | 342 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 343 | struct mlx5_buf_list *frags; |
388ca8be | 344 | u32 sz_m1; |
8d71e818 | 345 | u16 frag_sz_m1; |
a0903622 | 346 | u16 strides_offset; |
388ca8be YC |
347 | u8 log_sz; |
348 | u8 log_stride; | |
349 | u8 log_frag_strides; | |
350 | }; | |
351 | ||
3121e3c4 SG |
352 | struct mlx5_core_psv { |
353 | u32 psv_idx; | |
354 | struct psv_layout { | |
355 | u32 pd; | |
356 | u16 syndrome; | |
357 | u16 reserved; | |
358 | u16 bg; | |
359 | u16 app_tag; | |
360 | u32 ref_tag; | |
361 | } psv; | |
362 | }; | |
363 | ||
364 | struct mlx5_core_sig_ctx { | |
365 | struct mlx5_core_psv psv_memory; | |
366 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
367 | struct ib_sig_err err_item; |
368 | bool sig_status_checked; | |
369 | bool sig_err_exists; | |
370 | u32 sigerr_count; | |
3121e3c4 | 371 | }; |
e126ba97 | 372 | |
aa8e08d2 AK |
373 | enum { |
374 | MLX5_MKEY_MR = 1, | |
375 | MLX5_MKEY_MW, | |
376 | }; | |
377 | ||
a606b0f6 | 378 | struct mlx5_core_mkey { |
e126ba97 EC |
379 | u64 iova; |
380 | u64 size; | |
381 | u32 key; | |
382 | u32 pd; | |
aa8e08d2 | 383 | u32 type; |
e126ba97 EC |
384 | }; |
385 | ||
d9aaed83 AK |
386 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
387 | ||
5903325a | 388 | enum mlx5_res_type { |
e2013b21 | 389 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
390 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
391 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
392 | MLX5_RES_SRQ = 3, | |
393 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 394 | MLX5_RES_XRQ = 5, |
57cda166 | 395 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
396 | }; |
397 | ||
398 | struct mlx5_core_rsc_common { | |
399 | enum mlx5_res_type res; | |
400 | atomic_t refcount; | |
401 | struct completion free; | |
402 | }; | |
403 | ||
e126ba97 | 404 | struct mlx5_core_srq { |
01949d01 | 405 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
406 | u32 srqn; |
407 | int max; | |
c2b37f76 BP |
408 | size_t max_gs; |
409 | size_t max_avail_gather; | |
e126ba97 EC |
410 | int wqe_shift; |
411 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
412 | ||
413 | atomic_t refcount; | |
414 | struct completion free; | |
a0d8c054 | 415 | u16 uid; |
e126ba97 EC |
416 | }; |
417 | ||
a6d51b68 | 418 | struct mlx5_uars_page { |
e126ba97 | 419 | void __iomem *map; |
a6d51b68 EC |
420 | bool wc; |
421 | u32 index; | |
422 | struct list_head list; | |
423 | unsigned int bfregs; | |
424 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
425 | unsigned long *fp_bitmap; | |
426 | unsigned int reg_avail; | |
427 | unsigned int fp_avail; | |
428 | struct kref ref_count; | |
429 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
430 | }; |
431 | ||
a6d51b68 EC |
432 | struct mlx5_bfreg_head { |
433 | /* protect blue flame registers allocations */ | |
434 | struct mutex lock; | |
435 | struct list_head list; | |
436 | }; | |
437 | ||
438 | struct mlx5_bfreg_data { | |
439 | struct mlx5_bfreg_head reg_head; | |
440 | struct mlx5_bfreg_head wc_head; | |
441 | }; | |
442 | ||
443 | struct mlx5_sq_bfreg { | |
444 | void __iomem *map; | |
445 | struct mlx5_uars_page *up; | |
446 | bool wc; | |
447 | u32 index; | |
448 | unsigned int offset; | |
449 | }; | |
e126ba97 EC |
450 | |
451 | struct mlx5_core_health { | |
452 | struct health_buffer __iomem *health; | |
453 | __be32 __iomem *health_counter; | |
454 | struct timer_list timer; | |
e126ba97 EC |
455 | u32 prev; |
456 | int miss_counter; | |
fd76ee4d | 457 | bool sick; |
05ac2c0b MHY |
458 | /* wq spinlock to synchronize draining */ |
459 | spinlock_t wq_lock; | |
ac6ea6e8 | 460 | struct workqueue_struct *wq; |
05ac2c0b | 461 | unsigned long flags; |
ac6ea6e8 | 462 | struct work_struct work; |
04c0c1ab | 463 | struct delayed_work recover_work; |
e126ba97 EC |
464 | }; |
465 | ||
e126ba97 | 466 | struct mlx5_qp_table { |
221c14f3 SM |
467 | struct mlx5_nb nb; |
468 | ||
e126ba97 EC |
469 | /* protect radix tree |
470 | */ | |
471 | spinlock_t lock; | |
472 | struct radix_tree_root tree; | |
473 | }; | |
474 | ||
475 | struct mlx5_srq_table { | |
221c14f3 SM |
476 | struct mlx5_nb catas_err_nb; |
477 | struct mlx5_nb rq_limit_nb; | |
e126ba97 EC |
478 | /* protect radix tree |
479 | */ | |
480 | spinlock_t lock; | |
481 | struct radix_tree_root tree; | |
482 | }; | |
483 | ||
a606b0f6 | 484 | struct mlx5_mkey_table { |
3bcdb17a SG |
485 | /* protect radix tree |
486 | */ | |
487 | rwlock_t lock; | |
488 | struct radix_tree_root tree; | |
489 | }; | |
490 | ||
fc50db98 EC |
491 | struct mlx5_vf_context { |
492 | int enabled; | |
7ecf6d8f BW |
493 | u64 port_guid; |
494 | u64 node_guid; | |
495 | enum port_state_policy policy; | |
fc50db98 EC |
496 | }; |
497 | ||
498 | struct mlx5_core_sriov { | |
499 | struct mlx5_vf_context *vfs_ctx; | |
500 | int num_vfs; | |
501 | int enabled_vfs; | |
502 | }; | |
503 | ||
43a335e0 | 504 | struct mlx5_fc_stats { |
12d6066c VB |
505 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
506 | struct idr counters_idr; | |
9aff93d7 | 507 | struct list_head counters; |
83033688 | 508 | struct llist_head addlist; |
6e5e2283 | 509 | struct llist_head dellist; |
43a335e0 AV |
510 | |
511 | struct workqueue_struct *wq; | |
512 | struct delayed_work work; | |
513 | unsigned long next_query; | |
f6dfb4c3 | 514 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
515 | }; |
516 | ||
69c1280b | 517 | struct mlx5_events; |
eeb66cdb | 518 | struct mlx5_mpfs; |
073bb189 | 519 | struct mlx5_eswitch; |
7907f23a | 520 | struct mlx5_lag; |
f2f3df55 | 521 | struct mlx5_eq_table; |
073bb189 | 522 | |
05d3ac97 BW |
523 | struct mlx5_rate_limit { |
524 | u32 rate; | |
525 | u32 max_burst_sz; | |
526 | u16 typical_pkt_sz; | |
527 | }; | |
528 | ||
1466cc5b | 529 | struct mlx5_rl_entry { |
05d3ac97 | 530 | struct mlx5_rate_limit rl; |
1466cc5b YP |
531 | u16 index; |
532 | u16 refcount; | |
533 | }; | |
534 | ||
535 | struct mlx5_rl_table { | |
536 | /* protect rate limit table */ | |
537 | struct mutex rl_lock; | |
538 | u16 max_size; | |
539 | u32 max_rate; | |
540 | u32 min_rate; | |
541 | struct mlx5_rl_entry *rl_entry; | |
542 | }; | |
543 | ||
e126ba97 EC |
544 | struct mlx5_priv { |
545 | char name[MLX5_MAX_NAME_LEN]; | |
f2f3df55 | 546 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
547 | |
548 | /* pages stuff */ | |
0cf53c12 | 549 | struct mlx5_nb pg_nb; |
e126ba97 EC |
550 | struct workqueue_struct *pg_wq; |
551 | struct rb_root page_root; | |
552 | int fw_pages; | |
6aec21f6 | 553 | atomic_t reg_pages; |
bf0bf77f | 554 | struct list_head free_list; |
fc50db98 | 555 | int vfs_pages; |
e126ba97 EC |
556 | |
557 | struct mlx5_core_health health; | |
558 | ||
559 | struct mlx5_srq_table srq_table; | |
560 | ||
561 | /* start: qp staff */ | |
562 | struct mlx5_qp_table qp_table; | |
563 | struct dentry *qp_debugfs; | |
564 | struct dentry *eq_debugfs; | |
565 | struct dentry *cq_debugfs; | |
566 | struct dentry *cmdif_debugfs; | |
567 | /* end: qp staff */ | |
568 | ||
a606b0f6 MB |
569 | /* start: mkey staff */ |
570 | struct mlx5_mkey_table mkey_table; | |
571 | /* end: mkey staff */ | |
3bcdb17a | 572 | |
e126ba97 | 573 | /* start: alloc staff */ |
311c7c71 SM |
574 | /* protect buffer alocation according to numa node */ |
575 | struct mutex alloc_mutex; | |
576 | int numa_node; | |
577 | ||
e126ba97 EC |
578 | struct mutex pgdir_mutex; |
579 | struct list_head pgdir_list; | |
580 | /* end: alloc staff */ | |
581 | struct dentry *dbg_root; | |
582 | ||
583 | /* protect mkey key part */ | |
584 | spinlock_t mkey_lock; | |
585 | u8 mkey_key; | |
9603b61d JM |
586 | |
587 | struct list_head dev_list; | |
588 | struct list_head ctx_list; | |
589 | spinlock_t ctx_lock; | |
073bb189 | 590 | |
97834eba ES |
591 | struct list_head waiting_events_list; |
592 | bool is_accum_events; | |
69c1280b | 593 | struct mlx5_events *events; |
97834eba | 594 | |
fba53f7b | 595 | struct mlx5_flow_steering *steering; |
eeb66cdb | 596 | struct mlx5_mpfs *mpfs; |
073bb189 | 597 | struct mlx5_eswitch *eswitch; |
fc50db98 | 598 | struct mlx5_core_sriov sriov; |
7907f23a | 599 | struct mlx5_lag *lag; |
fc50db98 | 600 | unsigned long pci_dev_data; |
43a335e0 | 601 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 602 | struct mlx5_rl_table rl_table; |
d4eb4cd7 | 603 | |
a6d51b68 | 604 | struct mlx5_bfreg_data bfregs; |
01187175 | 605 | struct mlx5_uars_page *uar; |
e126ba97 EC |
606 | }; |
607 | ||
89d44f0a MD |
608 | enum mlx5_device_state { |
609 | MLX5_DEVICE_STATE_UP, | |
610 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
611 | }; | |
612 | ||
613 | enum mlx5_interface_state { | |
b3cb5388 | 614 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
615 | }; |
616 | ||
617 | enum mlx5_pci_status { | |
618 | MLX5_PCI_STATUS_DISABLED, | |
619 | MLX5_PCI_STATUS_ENABLED, | |
620 | }; | |
621 | ||
d9aaed83 AK |
622 | enum mlx5_pagefault_type_flags { |
623 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
624 | MLX5_PFAULT_WRITE = 1 << 1, | |
625 | MLX5_PFAULT_RDMA = 1 << 2, | |
626 | }; | |
627 | ||
b50d292b HHZ |
628 | struct mlx5_td { |
629 | struct list_head tirs_list; | |
630 | u32 tdn; | |
631 | }; | |
632 | ||
633 | struct mlx5e_resources { | |
b50d292b HHZ |
634 | u32 pdn; |
635 | struct mlx5_td td; | |
636 | struct mlx5_core_mkey mkey; | |
aff26157 | 637 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
638 | }; |
639 | ||
52ec462e IT |
640 | #define MLX5_MAX_RESERVED_GIDS 8 |
641 | ||
642 | struct mlx5_rsvd_gids { | |
643 | unsigned int start; | |
644 | unsigned int count; | |
645 | struct ida ida; | |
646 | }; | |
647 | ||
7c39afb3 FD |
648 | #define MAX_PIN_NUM 8 |
649 | struct mlx5_pps { | |
650 | u8 pin_caps[MAX_PIN_NUM]; | |
651 | struct work_struct out_work; | |
652 | u64 start[MAX_PIN_NUM]; | |
653 | u8 enabled; | |
654 | }; | |
655 | ||
656 | struct mlx5_clock { | |
41069256 SM |
657 | struct mlx5_core_dev *mdev; |
658 | struct mlx5_nb pps_nb; | |
64109f1d | 659 | seqlock_t lock; |
7c39afb3 FD |
660 | struct cyclecounter cycles; |
661 | struct timecounter tc; | |
662 | struct hwtstamp_config hwtstamp_config; | |
663 | u32 nominal_c_mult; | |
664 | unsigned long overflow_period; | |
665 | struct delayed_work overflow_work; | |
666 | struct ptp_clock *ptp; | |
667 | struct ptp_clock_info ptp_info; | |
668 | struct mlx5_pps pps_info; | |
669 | }; | |
670 | ||
f53aaa31 | 671 | struct mlx5_fw_tracer; |
358aa5ce | 672 | struct mlx5_vxlan; |
f53aaa31 | 673 | |
e126ba97 EC |
674 | struct mlx5_core_dev { |
675 | struct pci_dev *pdev; | |
89d44f0a MD |
676 | /* sync pci state */ |
677 | struct mutex pci_status_mutex; | |
678 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
679 | u8 rev_id; |
680 | char board_id[MLX5_BOARD_ID_LEN]; | |
681 | struct mlx5_cmd cmd; | |
938fe83c | 682 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 683 | struct { |
701052c5 GP |
684 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
685 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
686 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
687 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 688 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 689 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
71862561 | 690 | } caps; |
59c9d35e | 691 | u64 sys_image_guid; |
e126ba97 EC |
692 | phys_addr_t iseg_base; |
693 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
694 | enum mlx5_device_state state; |
695 | /* sync interface state */ | |
696 | struct mutex intf_state_mutex; | |
5fc7197d | 697 | unsigned long intf_state; |
e126ba97 EC |
698 | void (*event) (struct mlx5_core_dev *dev, |
699 | enum mlx5_dev_event event, | |
4d2f9bbb | 700 | unsigned long param); |
e126ba97 EC |
701 | struct mlx5_priv priv; |
702 | struct mlx5_profile *profile; | |
703 | atomic_t num_qps; | |
f62b8bb8 | 704 | u32 issi; |
b50d292b | 705 | struct mlx5e_resources mlx5e_res; |
358aa5ce | 706 | struct mlx5_vxlan *vxlan; |
52ec462e IT |
707 | struct { |
708 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 709 | u32 roce_en; |
52ec462e | 710 | } roce; |
e29341fb IT |
711 | #ifdef CONFIG_MLX5_FPGA |
712 | struct mlx5_fpga_device *fpga; | |
5a7b27eb | 713 | #endif |
7c39afb3 | 714 | struct mlx5_clock clock; |
24d33d2c FD |
715 | struct mlx5_ib_clock_info *clock_info; |
716 | struct page *clock_info_page; | |
f53aaa31 | 717 | struct mlx5_fw_tracer *tracer; |
e126ba97 EC |
718 | }; |
719 | ||
720 | struct mlx5_db { | |
721 | __be32 *db; | |
722 | union { | |
723 | struct mlx5_db_pgdir *pgdir; | |
724 | struct mlx5_ib_user_db_page *user_page; | |
725 | } u; | |
726 | dma_addr_t dma; | |
727 | int index; | |
728 | }; | |
729 | ||
e126ba97 EC |
730 | enum { |
731 | MLX5_COMP_EQ_SIZE = 1024, | |
732 | }; | |
733 | ||
adb0c954 SM |
734 | enum { |
735 | MLX5_PTYS_IB = 1 << 0, | |
736 | MLX5_PTYS_EN = 1 << 2, | |
737 | }; | |
738 | ||
e126ba97 EC |
739 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
740 | ||
73dd3a48 MHY |
741 | enum { |
742 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
743 | }; | |
744 | ||
e126ba97 | 745 | struct mlx5_cmd_work_ent { |
73dd3a48 | 746 | unsigned long state; |
e126ba97 EC |
747 | struct mlx5_cmd_msg *in; |
748 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
749 | void *uout; |
750 | int uout_size; | |
e126ba97 | 751 | mlx5_cmd_cbk_t callback; |
65ee6708 | 752 | struct delayed_work cb_timeout_work; |
e126ba97 | 753 | void *context; |
746b5583 | 754 | int idx; |
e126ba97 EC |
755 | struct completion done; |
756 | struct mlx5_cmd *cmd; | |
757 | struct work_struct work; | |
758 | struct mlx5_cmd_layout *lay; | |
759 | int ret; | |
760 | int page_queue; | |
761 | u8 status; | |
762 | u8 token; | |
14a70046 TG |
763 | u64 ts1; |
764 | u64 ts2; | |
746b5583 | 765 | u16 op; |
4525abea | 766 | bool polling; |
e126ba97 EC |
767 | }; |
768 | ||
769 | struct mlx5_pas { | |
770 | u64 pa; | |
771 | u8 log_sz; | |
772 | }; | |
773 | ||
707c4602 MD |
774 | enum phy_port_state { |
775 | MLX5_AAA_111 | |
776 | }; | |
777 | ||
778 | struct mlx5_hca_vport_context { | |
779 | u32 field_select; | |
780 | bool sm_virt_aware; | |
781 | bool has_smi; | |
782 | bool has_raw; | |
783 | enum port_state_policy policy; | |
784 | enum phy_port_state phys_state; | |
785 | enum ib_port_state vport_state; | |
786 | u8 port_physical_state; | |
787 | u64 sys_image_guid; | |
788 | u64 port_guid; | |
789 | u64 node_guid; | |
790 | u32 cap_mask1; | |
791 | u32 cap_mask1_perm; | |
792 | u32 cap_mask2; | |
793 | u32 cap_mask2_perm; | |
794 | u16 lid; | |
795 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
796 | u8 lmc; | |
797 | u8 subnet_timeout; | |
798 | u16 sm_lid; | |
799 | u8 sm_sl; | |
800 | u16 qkey_violation_counter; | |
801 | u16 pkey_violation_counter; | |
802 | bool grh_required; | |
803 | }; | |
804 | ||
388ca8be | 805 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 806 | { |
388ca8be | 807 | return buf->frags->buf + offset; |
e126ba97 EC |
808 | } |
809 | ||
e126ba97 EC |
810 | #define STRUCT_FIELD(header, field) \ |
811 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
812 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
813 | ||
e126ba97 EC |
814 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
815 | { | |
816 | return pci_get_drvdata(pdev); | |
817 | } | |
818 | ||
819 | extern struct dentry *mlx5_debugfs_root; | |
820 | ||
821 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
822 | { | |
823 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
824 | } | |
825 | ||
826 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
827 | { | |
828 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
829 | } | |
830 | ||
831 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
832 | { | |
833 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
834 | } | |
835 | ||
836 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
837 | { | |
838 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
839 | } | |
840 | ||
3bcdb17a SG |
841 | static inline u32 mlx5_base_mkey(const u32 key) |
842 | { | |
843 | return key & 0xffffff00u; | |
844 | } | |
845 | ||
4972e6fa TT |
846 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
847 | u8 log_stride, u8 log_sz, | |
a0903622 | 848 | u16 strides_offset, |
d7037ad7 | 849 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 850 | { |
4972e6fa | 851 | fbc->frags = frags; |
3a2f7033 TT |
852 | fbc->log_stride = log_stride; |
853 | fbc->log_sz = log_sz; | |
388ca8be YC |
854 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
855 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
856 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
857 | fbc->strides_offset = strides_offset; |
858 | } | |
859 | ||
4972e6fa TT |
860 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
861 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
862 | struct mlx5_frag_buf_ctrl *fbc) |
863 | { | |
4972e6fa | 864 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
865 | } |
866 | ||
388ca8be YC |
867 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
868 | u32 ix) | |
869 | { | |
d7037ad7 TT |
870 | unsigned int frag; |
871 | ||
872 | ix += fbc->strides_offset; | |
873 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 874 | |
4972e6fa | 875 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
876 | } |
877 | ||
37fdffb2 TT |
878 | static inline u32 |
879 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
880 | { | |
881 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
882 | ||
883 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
884 | } | |
885 | ||
e126ba97 EC |
886 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
887 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
888 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
889 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 890 | |
e126ba97 EC |
891 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
892 | int out_size); | |
746b5583 EC |
893 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
894 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
895 | void *context); | |
4525abea MD |
896 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
897 | void *out, int out_size); | |
c4f287c4 SM |
898 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
899 | ||
900 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
901 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
902 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
903 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
904 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 905 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 906 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 907 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 908 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
2a0165a0 | 909 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
311c7c71 | 910 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
388ca8be YC |
911 | struct mlx5_frag_buf *buf, int node); |
912 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, | |
913 | int size, struct mlx5_frag_buf *buf); | |
914 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
915 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
916 | struct mlx5_frag_buf *buf, int node); | |
917 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
918 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
919 | gfp_t flags, int npages); | |
920 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
921 | struct mlx5_cmd_mailbox *head); | |
922 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 923 | struct mlx5_srq_attr *in); |
e126ba97 EC |
924 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
925 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
af1ba291 | 926 | struct mlx5_srq_attr *out); |
e126ba97 EC |
927 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
928 | u16 lwm, int is_srq); | |
a606b0f6 MB |
929 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
930 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
931 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
932 | struct mlx5_core_mkey *mkey, | |
933 | u32 *in, int inlen, | |
934 | u32 *out, int outlen, | |
935 | mlx5_cmd_cbk_t callback, void *context); | |
a606b0f6 MB |
936 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
937 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 938 | u32 *in, int inlen); |
a606b0f6 MB |
939 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
940 | struct mlx5_core_mkey *mkey); | |
941 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 942 | u32 *out, int outlen); |
e126ba97 EC |
943 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
944 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 945 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 946 | u16 opmod, u8 port); |
0cf53c12 | 947 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
e126ba97 | 948 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
0cf53c12 | 949 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
e126ba97 EC |
950 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
951 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 952 | s32 npages); |
cd23b14b | 953 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
954 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
955 | void mlx5_register_debugfs(void); | |
956 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
957 | |
958 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 959 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
e126ba97 | 960 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); |
0b6e26ce DT |
961 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
962 | unsigned int *irqn); | |
e126ba97 EC |
963 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
964 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
965 | ||
966 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
967 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
968 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
969 | int size_in, void *data_out, int size_out, | |
970 | u16 reg_num, int arg, int write); | |
adb0c954 | 971 | |
e126ba97 | 972 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
973 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
974 | int node); | |
e126ba97 EC |
975 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
976 | ||
e126ba97 EC |
977 | const char *mlx5_command_str(int command); |
978 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
979 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
980 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
981 | int npsvs, u32 *sig_index); | |
982 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 983 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
984 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
985 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
986 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
987 | u8 port_num, void *out, size_t sz); | |
d9aaed83 AK |
988 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
989 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, | |
990 | u32 wq_num, u8 type, int error); | |
991 | #endif | |
e126ba97 | 992 | |
1466cc5b YP |
993 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
994 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
995 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
996 | struct mlx5_rate_limit *rl); | |
997 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 998 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
05d3ac97 BW |
999 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
1000 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
1001 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1002 | bool map_wc, bool fast_path); | |
1003 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1004 | |
f2f3df55 SM |
1005 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
1006 | struct cpumask * | |
1007 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
1008 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1009 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1010 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1011 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1012 | |
e3297246 EC |
1013 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1014 | { | |
1015 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1016 | } | |
1017 | ||
e126ba97 EC |
1018 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1019 | { | |
1020 | return mkey >> 8; | |
1021 | } | |
1022 | ||
1023 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1024 | { | |
1025 | return mkey_idx << 8; | |
1026 | } | |
1027 | ||
746b5583 EC |
1028 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1029 | { | |
1030 | return mkey & 0xff; | |
1031 | } | |
1032 | ||
e126ba97 EC |
1033 | enum { |
1034 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1035 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1036 | }; |
1037 | ||
1038 | enum { | |
8b7ff7f3 | 1039 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1040 | MLX5_IMR_MTT_CACHE_ENTRY, |
1041 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1042 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1043 | }; |
1044 | ||
64613d94 SM |
1045 | enum { |
1046 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1047 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1048 | }; | |
1049 | ||
9603b61d JM |
1050 | struct mlx5_interface { |
1051 | void * (*add)(struct mlx5_core_dev *dev); | |
1052 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1053 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1054 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
9603b61d | 1055 | void (*event)(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1056 | enum mlx5_dev_event event, unsigned long param); |
64613d94 SM |
1057 | void * (*get_dev)(void *context); |
1058 | int protocol; | |
9603b61d JM |
1059 | struct list_head list; |
1060 | }; | |
1061 | ||
64613d94 | 1062 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
1063 | int mlx5_register_interface(struct mlx5_interface *intf); |
1064 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 1065 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1066 | |
3bc34f3b AH |
1067 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1068 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7907f23a | 1069 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1070 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1071 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1072 | u64 *values, | |
1073 | int num_counters, | |
1074 | size_t *offsets); | |
01187175 EC |
1075 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1076 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1077 | |
f6a8a19b | 1078 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1079 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1080 | struct ib_device *ibdev, | |
1081 | const char *name, | |
1082 | void (*setup)(struct net_device *)); | |
693dfd5a | 1083 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1084 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1085 | struct ib_device *device, | |
1086 | struct rdma_netdev_alloc_params *params); | |
693dfd5a | 1087 | |
e126ba97 EC |
1088 | struct mlx5_profile { |
1089 | u64 mask; | |
f241e749 | 1090 | u8 log_max_qp; |
e126ba97 EC |
1091 | struct { |
1092 | int size; | |
1093 | int limit; | |
1094 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1095 | }; | |
1096 | ||
fc50db98 EC |
1097 | enum { |
1098 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1099 | }; | |
1100 | ||
1101 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1102 | { | |
1103 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1104 | } | |
1105 | ||
57cbd893 MB |
1106 | #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) |
1107 | #define MLX5_VPORT_MANAGER(mdev) \ | |
1108 | (MLX5_CAP_GEN(mdev, vport_group_manager) && \ | |
1109 | (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ | |
1110 | mlx5_core_is_pf(mdev)) | |
1111 | ||
707c4602 MD |
1112 | static inline int mlx5_get_gid_table_len(u16 param) |
1113 | { | |
1114 | if (param > 4) { | |
1115 | pr_warn("gid table length is zero\n"); | |
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | return 8 * (1 << param); | |
1120 | } | |
1121 | ||
1466cc5b YP |
1122 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1123 | { | |
1124 | return !!(dev->priv.rl_table.max_size); | |
1125 | } | |
1126 | ||
32f69e4b DJ |
1127 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1128 | { | |
1129 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1130 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1131 | } | |
1132 | ||
1133 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1134 | { | |
1135 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1136 | } | |
1137 | ||
1138 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1139 | { | |
1140 | return mlx5_core_is_mp_slave(dev) || | |
1141 | mlx5_core_is_mp_master(dev); | |
1142 | } | |
1143 | ||
7fd8aefb DJ |
1144 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1145 | { | |
32f69e4b DJ |
1146 | if (!mlx5_core_mp_enabled(dev)) |
1147 | return 1; | |
1148 | ||
1149 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1150 | } |
1151 | ||
020446e0 EC |
1152 | enum { |
1153 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1154 | }; | |
1155 | ||
e126ba97 | 1156 | #endif /* MLX5_DRIVER_H */ |