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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 EC |
43 | #include <linux/vmalloc.h> |
44 | #include <linux/radix-tree.h> | |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
20902be4 | 49 | #include <linux/notifier.h> |
6ecde51d | 50 | |
e126ba97 EC |
51 | #include <linux/mlx5/device.h> |
52 | #include <linux/mlx5/doorbell.h> | |
41069256 | 53 | #include <linux/mlx5/eq.h> |
7c39afb3 FD |
54 | #include <linux/timecounter.h> |
55 | #include <linux/ptp_clock_kernel.h> | |
e126ba97 EC |
56 | |
57 | enum { | |
58 | MLX5_BOARD_ID_LEN = 64, | |
59 | MLX5_MAX_NAME_LEN = 16, | |
60 | }; | |
61 | ||
62 | enum { | |
63 | /* one minute for the sake of bringup. Generally, commands must always | |
64 | * complete and we may need to increase this timeout value | |
65 | */ | |
6b6c07bd | 66 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
67 | MLX5_CMD_WQ_MAX_NAME = 32, |
68 | }; | |
69 | ||
70 | enum { | |
71 | CMD_OWNER_SW = 0x0, | |
72 | CMD_OWNER_HW = 0x1, | |
73 | CMD_STATUS_SUCCESS = 0, | |
74 | }; | |
75 | ||
76 | enum mlx5_sqp_t { | |
77 | MLX5_SQP_SMI = 0, | |
78 | MLX5_SQP_GSI = 1, | |
79 | MLX5_SQP_IEEE_1588 = 2, | |
80 | MLX5_SQP_SNIFFER = 3, | |
81 | MLX5_SQP_SYNC_UMR = 4, | |
82 | }; | |
83 | ||
84 | enum { | |
85 | MLX5_MAX_PORTS = 2, | |
86 | }; | |
87 | ||
e126ba97 | 88 | enum { |
a60109dc YC |
89 | MLX5_ATOMIC_MODE_OFFSET = 16, |
90 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
91 | MLX5_ATOMIC_MODE_CX = 2, | |
92 | MLX5_ATOMIC_MODE_8B = 3, | |
93 | MLX5_ATOMIC_MODE_16B = 4, | |
94 | MLX5_ATOMIC_MODE_32B = 5, | |
95 | MLX5_ATOMIC_MODE_64B = 6, | |
96 | MLX5_ATOMIC_MODE_128B = 7, | |
97 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
98 | }; |
99 | ||
e126ba97 | 100 | enum { |
415a64aa | 101 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
102 | MLX5_REG_QETCR = 0x4005, |
103 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 104 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 105 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
106 | MLX5_REG_DCBX_PARAM = 0x4020, |
107 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
108 | MLX5_REG_FPGA_CAP = 0x4022, |
109 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 110 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
e126ba97 EC |
111 | MLX5_REG_PCAP = 0x5001, |
112 | MLX5_REG_PMTU = 0x5003, | |
113 | MLX5_REG_PTYS = 0x5004, | |
114 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 115 | MLX5_REG_PFCC = 0x5007, |
efea389d | 116 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
117 | MLX5_REG_PPTB = 0x500b, |
118 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
119 | MLX5_REG_PMAOS = 0x5012, |
120 | MLX5_REG_PUDE = 0x5009, | |
121 | MLX5_REG_PMPE = 0x5010, | |
122 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 123 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 124 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 125 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 126 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 127 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
128 | MLX5_REG_NODE_DESC = 0x6001, |
129 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 130 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 131 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
132 | MLX5_REG_MTRC_CAP = 0x9040, |
133 | MLX5_REG_MTRC_CONF = 0x9041, | |
134 | MLX5_REG_MTRC_STDB = 0x9042, | |
135 | MLX5_REG_MTRC_CTRL = 0x9043, | |
8ed1a630 | 136 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
137 | MLX5_REG_MTPPS = 0x9053, |
138 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 139 | MLX5_REG_MPEGC = 0x9056, |
47176289 OG |
140 | MLX5_REG_MCQI = 0x9061, |
141 | MLX5_REG_MCC = 0x9062, | |
142 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 143 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
144 | }; |
145 | ||
415a64aa HN |
146 | enum mlx5_qpts_trust_state { |
147 | MLX5_QPTS_TRUST_PCP = 1, | |
148 | MLX5_QPTS_TRUST_DSCP = 2, | |
149 | }; | |
150 | ||
341c5ee2 HN |
151 | enum mlx5_dcbx_oper_mode { |
152 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
153 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
154 | }; | |
155 | ||
da7525d2 EBE |
156 | enum { |
157 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
158 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
159 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
160 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
161 | }; |
162 | ||
e420f0c0 HE |
163 | enum mlx5_page_fault_resume_flags { |
164 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
165 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
166 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
167 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
168 | }; | |
169 | ||
e126ba97 EC |
170 | enum dbg_rsc_type { |
171 | MLX5_DBG_RSC_QP, | |
172 | MLX5_DBG_RSC_EQ, | |
173 | MLX5_DBG_RSC_CQ, | |
174 | }; | |
175 | ||
7ecf6d8f BW |
176 | enum port_state_policy { |
177 | MLX5_POLICY_DOWN = 0, | |
178 | MLX5_POLICY_UP = 1, | |
179 | MLX5_POLICY_FOLLOW = 2, | |
180 | MLX5_POLICY_INVALID = 0xffffffff | |
181 | }; | |
182 | ||
e126ba97 EC |
183 | struct mlx5_field_desc { |
184 | struct dentry *dent; | |
185 | int i; | |
186 | }; | |
187 | ||
188 | struct mlx5_rsc_debug { | |
189 | struct mlx5_core_dev *dev; | |
190 | void *object; | |
191 | enum dbg_rsc_type type; | |
192 | struct dentry *root; | |
193 | struct mlx5_field_desc fields[0]; | |
194 | }; | |
195 | ||
196 | enum mlx5_dev_event { | |
58d180b3 | 197 | MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ |
6997b1c9 | 198 | MLX5_DEV_EVENT_PORT_AFFINITY = 129, |
e126ba97 EC |
199 | }; |
200 | ||
4c916a79 | 201 | enum mlx5_port_status { |
6fa1bcab AS |
202 | MLX5_PORT_UP = 1, |
203 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
204 | }; |
205 | ||
2f5ff264 | 206 | struct mlx5_bfreg_info { |
b037c29a | 207 | u32 *sys_pages; |
2f5ff264 | 208 | int num_low_latency_bfregs; |
e126ba97 | 209 | unsigned int *count; |
e126ba97 EC |
210 | |
211 | /* | |
2f5ff264 | 212 | * protect bfreg allocation data structs |
e126ba97 EC |
213 | */ |
214 | struct mutex lock; | |
78c0f98c | 215 | u32 ver; |
b037c29a EC |
216 | bool lib_uar_4k; |
217 | u32 num_sys_pages; | |
31a78a5a YH |
218 | u32 num_static_sys_pages; |
219 | u32 total_num_bfregs; | |
220 | u32 num_dyn_bfregs; | |
e126ba97 EC |
221 | }; |
222 | ||
223 | struct mlx5_cmd_first { | |
224 | __be32 data[4]; | |
225 | }; | |
226 | ||
227 | struct mlx5_cmd_msg { | |
228 | struct list_head list; | |
0ac3ea70 | 229 | struct cmd_msg_cache *parent; |
e126ba97 EC |
230 | u32 len; |
231 | struct mlx5_cmd_first first; | |
232 | struct mlx5_cmd_mailbox *next; | |
233 | }; | |
234 | ||
235 | struct mlx5_cmd_debug { | |
236 | struct dentry *dbg_root; | |
237 | struct dentry *dbg_in; | |
238 | struct dentry *dbg_out; | |
239 | struct dentry *dbg_outlen; | |
240 | struct dentry *dbg_status; | |
241 | struct dentry *dbg_run; | |
242 | void *in_msg; | |
243 | void *out_msg; | |
244 | u8 status; | |
245 | u16 inlen; | |
246 | u16 outlen; | |
247 | }; | |
248 | ||
0ac3ea70 | 249 | struct cmd_msg_cache { |
e126ba97 EC |
250 | /* protect block chain allocations |
251 | */ | |
252 | spinlock_t lock; | |
253 | struct list_head head; | |
0ac3ea70 MHY |
254 | unsigned int max_inbox_size; |
255 | unsigned int num_ent; | |
e126ba97 EC |
256 | }; |
257 | ||
0ac3ea70 MHY |
258 | enum { |
259 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
260 | }; |
261 | ||
262 | struct mlx5_cmd_stats { | |
263 | u64 sum; | |
264 | u64 n; | |
265 | struct dentry *root; | |
266 | struct dentry *avg; | |
267 | struct dentry *count; | |
268 | /* protect command average calculations */ | |
269 | spinlock_t lock; | |
270 | }; | |
271 | ||
272 | struct mlx5_cmd { | |
71edc69c SM |
273 | struct mlx5_nb nb; |
274 | ||
64599cca EC |
275 | void *cmd_alloc_buf; |
276 | dma_addr_t alloc_dma; | |
277 | int alloc_size; | |
e126ba97 EC |
278 | void *cmd_buf; |
279 | dma_addr_t dma; | |
280 | u16 cmdif_rev; | |
281 | u8 log_sz; | |
282 | u8 log_stride; | |
283 | int max_reg_cmds; | |
284 | int events; | |
285 | u32 __iomem *vector; | |
286 | ||
287 | /* protect command queue allocations | |
288 | */ | |
289 | spinlock_t alloc_lock; | |
290 | ||
291 | /* protect token allocations | |
292 | */ | |
293 | spinlock_t token_lock; | |
294 | u8 token; | |
295 | unsigned long bitmask; | |
296 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
297 | struct workqueue_struct *wq; | |
298 | struct semaphore sem; | |
299 | struct semaphore pages_sem; | |
300 | int mode; | |
301 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 302 | struct dma_pool *pool; |
e126ba97 | 303 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 304 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
305 | int checksum_disabled; |
306 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
307 | }; | |
308 | ||
309 | struct mlx5_port_caps { | |
310 | int gid_table_len; | |
311 | int pkey_table_len; | |
938fe83c | 312 | u8 ext_port_cap; |
c43f1112 | 313 | bool has_smi; |
e126ba97 EC |
314 | }; |
315 | ||
316 | struct mlx5_cmd_mailbox { | |
317 | void *buf; | |
318 | dma_addr_t dma; | |
319 | struct mlx5_cmd_mailbox *next; | |
320 | }; | |
321 | ||
322 | struct mlx5_buf_list { | |
323 | void *buf; | |
324 | dma_addr_t map; | |
325 | }; | |
326 | ||
1c1b5228 TT |
327 | struct mlx5_frag_buf { |
328 | struct mlx5_buf_list *frags; | |
329 | int npages; | |
330 | int size; | |
331 | u8 page_shift; | |
332 | }; | |
333 | ||
388ca8be | 334 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 335 | struct mlx5_buf_list *frags; |
388ca8be | 336 | u32 sz_m1; |
8d71e818 | 337 | u16 frag_sz_m1; |
a0903622 | 338 | u16 strides_offset; |
388ca8be YC |
339 | u8 log_sz; |
340 | u8 log_stride; | |
341 | u8 log_frag_strides; | |
342 | }; | |
343 | ||
3121e3c4 SG |
344 | struct mlx5_core_psv { |
345 | u32 psv_idx; | |
346 | struct psv_layout { | |
347 | u32 pd; | |
348 | u16 syndrome; | |
349 | u16 reserved; | |
350 | u16 bg; | |
351 | u16 app_tag; | |
352 | u32 ref_tag; | |
353 | } psv; | |
354 | }; | |
355 | ||
356 | struct mlx5_core_sig_ctx { | |
357 | struct mlx5_core_psv psv_memory; | |
358 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
359 | struct ib_sig_err err_item; |
360 | bool sig_status_checked; | |
361 | bool sig_err_exists; | |
362 | u32 sigerr_count; | |
3121e3c4 | 363 | }; |
e126ba97 | 364 | |
aa8e08d2 AK |
365 | enum { |
366 | MLX5_MKEY_MR = 1, | |
367 | MLX5_MKEY_MW, | |
534fd7aa | 368 | MLX5_MKEY_INDIRECT_DEVX, |
aa8e08d2 AK |
369 | }; |
370 | ||
a606b0f6 | 371 | struct mlx5_core_mkey { |
e126ba97 EC |
372 | u64 iova; |
373 | u64 size; | |
374 | u32 key; | |
375 | u32 pd; | |
aa8e08d2 | 376 | u32 type; |
e126ba97 EC |
377 | }; |
378 | ||
d9aaed83 AK |
379 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
380 | ||
5903325a | 381 | enum mlx5_res_type { |
e2013b21 | 382 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
383 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
384 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
385 | MLX5_RES_SRQ = 3, | |
386 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 387 | MLX5_RES_XRQ = 5, |
57cda166 | 388 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
389 | }; |
390 | ||
391 | struct mlx5_core_rsc_common { | |
392 | enum mlx5_res_type res; | |
393 | atomic_t refcount; | |
394 | struct completion free; | |
395 | }; | |
396 | ||
a6d51b68 | 397 | struct mlx5_uars_page { |
e126ba97 | 398 | void __iomem *map; |
a6d51b68 EC |
399 | bool wc; |
400 | u32 index; | |
401 | struct list_head list; | |
402 | unsigned int bfregs; | |
403 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
404 | unsigned long *fp_bitmap; | |
405 | unsigned int reg_avail; | |
406 | unsigned int fp_avail; | |
407 | struct kref ref_count; | |
408 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
409 | }; |
410 | ||
a6d51b68 EC |
411 | struct mlx5_bfreg_head { |
412 | /* protect blue flame registers allocations */ | |
413 | struct mutex lock; | |
414 | struct list_head list; | |
415 | }; | |
416 | ||
417 | struct mlx5_bfreg_data { | |
418 | struct mlx5_bfreg_head reg_head; | |
419 | struct mlx5_bfreg_head wc_head; | |
420 | }; | |
421 | ||
422 | struct mlx5_sq_bfreg { | |
423 | void __iomem *map; | |
424 | struct mlx5_uars_page *up; | |
425 | bool wc; | |
426 | u32 index; | |
427 | unsigned int offset; | |
428 | }; | |
e126ba97 EC |
429 | |
430 | struct mlx5_core_health { | |
431 | struct health_buffer __iomem *health; | |
432 | __be32 __iomem *health_counter; | |
433 | struct timer_list timer; | |
e126ba97 EC |
434 | u32 prev; |
435 | int miss_counter; | |
fd76ee4d | 436 | bool sick; |
05ac2c0b MHY |
437 | /* wq spinlock to synchronize draining */ |
438 | spinlock_t wq_lock; | |
ac6ea6e8 | 439 | struct workqueue_struct *wq; |
05ac2c0b | 440 | unsigned long flags; |
ac6ea6e8 | 441 | struct work_struct work; |
04c0c1ab | 442 | struct delayed_work recover_work; |
e126ba97 EC |
443 | }; |
444 | ||
e126ba97 | 445 | struct mlx5_qp_table { |
451be51c | 446 | struct notifier_block nb; |
221c14f3 | 447 | |
e126ba97 EC |
448 | /* protect radix tree |
449 | */ | |
450 | spinlock_t lock; | |
451 | struct radix_tree_root tree; | |
452 | }; | |
453 | ||
a606b0f6 | 454 | struct mlx5_mkey_table { |
3bcdb17a SG |
455 | /* protect radix tree |
456 | */ | |
457 | rwlock_t lock; | |
458 | struct radix_tree_root tree; | |
459 | }; | |
460 | ||
fc50db98 EC |
461 | struct mlx5_vf_context { |
462 | int enabled; | |
7ecf6d8f BW |
463 | u64 port_guid; |
464 | u64 node_guid; | |
465 | enum port_state_policy policy; | |
fc50db98 EC |
466 | }; |
467 | ||
468 | struct mlx5_core_sriov { | |
469 | struct mlx5_vf_context *vfs_ctx; | |
470 | int num_vfs; | |
471 | int enabled_vfs; | |
472 | }; | |
473 | ||
43a335e0 | 474 | struct mlx5_fc_stats { |
12d6066c VB |
475 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
476 | struct idr counters_idr; | |
9aff93d7 | 477 | struct list_head counters; |
83033688 | 478 | struct llist_head addlist; |
6e5e2283 | 479 | struct llist_head dellist; |
43a335e0 AV |
480 | |
481 | struct workqueue_struct *wq; | |
482 | struct delayed_work work; | |
483 | unsigned long next_query; | |
f6dfb4c3 | 484 | unsigned long sampling_interval; /* jiffies */ |
43a335e0 AV |
485 | }; |
486 | ||
69c1280b | 487 | struct mlx5_events; |
eeb66cdb | 488 | struct mlx5_mpfs; |
073bb189 | 489 | struct mlx5_eswitch; |
7907f23a | 490 | struct mlx5_lag; |
fadd59fc | 491 | struct mlx5_devcom; |
f2f3df55 | 492 | struct mlx5_eq_table; |
073bb189 | 493 | |
05d3ac97 BW |
494 | struct mlx5_rate_limit { |
495 | u32 rate; | |
496 | u32 max_burst_sz; | |
497 | u16 typical_pkt_sz; | |
498 | }; | |
499 | ||
1466cc5b | 500 | struct mlx5_rl_entry { |
05d3ac97 | 501 | struct mlx5_rate_limit rl; |
1466cc5b YP |
502 | u16 index; |
503 | u16 refcount; | |
504 | }; | |
505 | ||
506 | struct mlx5_rl_table { | |
507 | /* protect rate limit table */ | |
508 | struct mutex rl_lock; | |
509 | u16 max_size; | |
510 | u32 max_rate; | |
511 | u32 min_rate; | |
512 | struct mlx5_rl_entry *rl_entry; | |
513 | }; | |
514 | ||
e126ba97 EC |
515 | struct mlx5_priv { |
516 | char name[MLX5_MAX_NAME_LEN]; | |
f2f3df55 | 517 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
518 | |
519 | /* pages stuff */ | |
0cf53c12 | 520 | struct mlx5_nb pg_nb; |
e126ba97 EC |
521 | struct workqueue_struct *pg_wq; |
522 | struct rb_root page_root; | |
523 | int fw_pages; | |
6aec21f6 | 524 | atomic_t reg_pages; |
bf0bf77f | 525 | struct list_head free_list; |
fc50db98 | 526 | int vfs_pages; |
591905ba | 527 | int peer_pf_pages; |
e126ba97 EC |
528 | |
529 | struct mlx5_core_health health; | |
530 | ||
e126ba97 EC |
531 | /* start: qp staff */ |
532 | struct mlx5_qp_table qp_table; | |
533 | struct dentry *qp_debugfs; | |
534 | struct dentry *eq_debugfs; | |
535 | struct dentry *cq_debugfs; | |
536 | struct dentry *cmdif_debugfs; | |
537 | /* end: qp staff */ | |
538 | ||
a606b0f6 MB |
539 | /* start: mkey staff */ |
540 | struct mlx5_mkey_table mkey_table; | |
541 | /* end: mkey staff */ | |
3bcdb17a | 542 | |
e126ba97 | 543 | /* start: alloc staff */ |
311c7c71 SM |
544 | /* protect buffer alocation according to numa node */ |
545 | struct mutex alloc_mutex; | |
546 | int numa_node; | |
547 | ||
e126ba97 EC |
548 | struct mutex pgdir_mutex; |
549 | struct list_head pgdir_list; | |
550 | /* end: alloc staff */ | |
551 | struct dentry *dbg_root; | |
552 | ||
553 | /* protect mkey key part */ | |
554 | spinlock_t mkey_lock; | |
555 | u8 mkey_key; | |
9603b61d JM |
556 | |
557 | struct list_head dev_list; | |
558 | struct list_head ctx_list; | |
559 | spinlock_t ctx_lock; | |
02039fb6 | 560 | struct mlx5_events *events; |
97834eba | 561 | |
fba53f7b | 562 | struct mlx5_flow_steering *steering; |
eeb66cdb | 563 | struct mlx5_mpfs *mpfs; |
073bb189 | 564 | struct mlx5_eswitch *eswitch; |
fc50db98 | 565 | struct mlx5_core_sriov sriov; |
7907f23a | 566 | struct mlx5_lag *lag; |
fadd59fc | 567 | struct mlx5_devcom *devcom; |
fc50db98 | 568 | unsigned long pci_dev_data; |
43a335e0 | 569 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 570 | struct mlx5_rl_table rl_table; |
d4eb4cd7 | 571 | |
a6d51b68 | 572 | struct mlx5_bfreg_data bfregs; |
01187175 | 573 | struct mlx5_uars_page *uar; |
e126ba97 EC |
574 | }; |
575 | ||
89d44f0a MD |
576 | enum mlx5_device_state { |
577 | MLX5_DEVICE_STATE_UP, | |
578 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
579 | }; | |
580 | ||
581 | enum mlx5_interface_state { | |
b3cb5388 | 582 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
583 | }; |
584 | ||
585 | enum mlx5_pci_status { | |
586 | MLX5_PCI_STATUS_DISABLED, | |
587 | MLX5_PCI_STATUS_ENABLED, | |
588 | }; | |
589 | ||
d9aaed83 AK |
590 | enum mlx5_pagefault_type_flags { |
591 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
592 | MLX5_PFAULT_WRITE = 1 << 1, | |
593 | MLX5_PFAULT_RDMA = 1 << 2, | |
594 | }; | |
595 | ||
b50d292b HHZ |
596 | struct mlx5_td { |
597 | struct list_head tirs_list; | |
598 | u32 tdn; | |
599 | }; | |
600 | ||
601 | struct mlx5e_resources { | |
b50d292b HHZ |
602 | u32 pdn; |
603 | struct mlx5_td td; | |
604 | struct mlx5_core_mkey mkey; | |
aff26157 | 605 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
606 | }; |
607 | ||
52ec462e IT |
608 | #define MLX5_MAX_RESERVED_GIDS 8 |
609 | ||
610 | struct mlx5_rsvd_gids { | |
611 | unsigned int start; | |
612 | unsigned int count; | |
613 | struct ida ida; | |
614 | }; | |
615 | ||
7c39afb3 FD |
616 | #define MAX_PIN_NUM 8 |
617 | struct mlx5_pps { | |
618 | u8 pin_caps[MAX_PIN_NUM]; | |
619 | struct work_struct out_work; | |
620 | u64 start[MAX_PIN_NUM]; | |
621 | u8 enabled; | |
622 | }; | |
623 | ||
624 | struct mlx5_clock { | |
41069256 SM |
625 | struct mlx5_core_dev *mdev; |
626 | struct mlx5_nb pps_nb; | |
64109f1d | 627 | seqlock_t lock; |
7c39afb3 FD |
628 | struct cyclecounter cycles; |
629 | struct timecounter tc; | |
630 | struct hwtstamp_config hwtstamp_config; | |
631 | u32 nominal_c_mult; | |
632 | unsigned long overflow_period; | |
633 | struct delayed_work overflow_work; | |
634 | struct ptp_clock *ptp; | |
635 | struct ptp_clock_info ptp_info; | |
636 | struct mlx5_pps pps_info; | |
637 | }; | |
638 | ||
f53aaa31 | 639 | struct mlx5_fw_tracer; |
358aa5ce | 640 | struct mlx5_vxlan; |
f53aaa31 | 641 | |
e126ba97 EC |
642 | struct mlx5_core_dev { |
643 | struct pci_dev *pdev; | |
89d44f0a MD |
644 | /* sync pci state */ |
645 | struct mutex pci_status_mutex; | |
646 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
647 | u8 rev_id; |
648 | char board_id[MLX5_BOARD_ID_LEN]; | |
649 | struct mlx5_cmd cmd; | |
938fe83c | 650 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 651 | struct { |
701052c5 GP |
652 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
653 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
654 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
655 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 656 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 657 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
591905ba | 658 | u8 embedded_cpu; |
71862561 | 659 | } caps; |
59c9d35e | 660 | u64 sys_image_guid; |
e126ba97 EC |
661 | phys_addr_t iseg_base; |
662 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
663 | enum mlx5_device_state state; |
664 | /* sync interface state */ | |
665 | struct mutex intf_state_mutex; | |
5fc7197d | 666 | unsigned long intf_state; |
e126ba97 EC |
667 | struct mlx5_priv priv; |
668 | struct mlx5_profile *profile; | |
669 | atomic_t num_qps; | |
f62b8bb8 | 670 | u32 issi; |
b50d292b | 671 | struct mlx5e_resources mlx5e_res; |
358aa5ce | 672 | struct mlx5_vxlan *vxlan; |
52ec462e IT |
673 | struct { |
674 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 675 | u32 roce_en; |
52ec462e | 676 | } roce; |
e29341fb IT |
677 | #ifdef CONFIG_MLX5_FPGA |
678 | struct mlx5_fpga_device *fpga; | |
5a7b27eb | 679 | #endif |
7c39afb3 | 680 | struct mlx5_clock clock; |
24d33d2c FD |
681 | struct mlx5_ib_clock_info *clock_info; |
682 | struct page *clock_info_page; | |
f53aaa31 | 683 | struct mlx5_fw_tracer *tracer; |
e126ba97 EC |
684 | }; |
685 | ||
686 | struct mlx5_db { | |
687 | __be32 *db; | |
688 | union { | |
689 | struct mlx5_db_pgdir *pgdir; | |
690 | struct mlx5_ib_user_db_page *user_page; | |
691 | } u; | |
692 | dma_addr_t dma; | |
693 | int index; | |
694 | }; | |
695 | ||
e126ba97 EC |
696 | enum { |
697 | MLX5_COMP_EQ_SIZE = 1024, | |
698 | }; | |
699 | ||
adb0c954 SM |
700 | enum { |
701 | MLX5_PTYS_IB = 1 << 0, | |
702 | MLX5_PTYS_EN = 1 << 2, | |
703 | }; | |
704 | ||
e126ba97 EC |
705 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
706 | ||
73dd3a48 MHY |
707 | enum { |
708 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
709 | }; | |
710 | ||
e126ba97 | 711 | struct mlx5_cmd_work_ent { |
73dd3a48 | 712 | unsigned long state; |
e126ba97 EC |
713 | struct mlx5_cmd_msg *in; |
714 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
715 | void *uout; |
716 | int uout_size; | |
e126ba97 | 717 | mlx5_cmd_cbk_t callback; |
65ee6708 | 718 | struct delayed_work cb_timeout_work; |
e126ba97 | 719 | void *context; |
746b5583 | 720 | int idx; |
e126ba97 EC |
721 | struct completion done; |
722 | struct mlx5_cmd *cmd; | |
723 | struct work_struct work; | |
724 | struct mlx5_cmd_layout *lay; | |
725 | int ret; | |
726 | int page_queue; | |
727 | u8 status; | |
728 | u8 token; | |
14a70046 TG |
729 | u64 ts1; |
730 | u64 ts2; | |
746b5583 | 731 | u16 op; |
4525abea | 732 | bool polling; |
e126ba97 EC |
733 | }; |
734 | ||
735 | struct mlx5_pas { | |
736 | u64 pa; | |
737 | u8 log_sz; | |
738 | }; | |
739 | ||
707c4602 MD |
740 | enum phy_port_state { |
741 | MLX5_AAA_111 | |
742 | }; | |
743 | ||
744 | struct mlx5_hca_vport_context { | |
745 | u32 field_select; | |
746 | bool sm_virt_aware; | |
747 | bool has_smi; | |
748 | bool has_raw; | |
749 | enum port_state_policy policy; | |
750 | enum phy_port_state phys_state; | |
751 | enum ib_port_state vport_state; | |
752 | u8 port_physical_state; | |
753 | u64 sys_image_guid; | |
754 | u64 port_guid; | |
755 | u64 node_guid; | |
756 | u32 cap_mask1; | |
757 | u32 cap_mask1_perm; | |
4106a758 MG |
758 | u16 cap_mask2; |
759 | u16 cap_mask2_perm; | |
707c4602 MD |
760 | u16 lid; |
761 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
762 | u8 lmc; | |
763 | u8 subnet_timeout; | |
764 | u16 sm_lid; | |
765 | u8 sm_sl; | |
766 | u16 qkey_violation_counter; | |
767 | u16 pkey_violation_counter; | |
768 | bool grh_required; | |
769 | }; | |
770 | ||
388ca8be | 771 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 772 | { |
388ca8be | 773 | return buf->frags->buf + offset; |
e126ba97 EC |
774 | } |
775 | ||
e126ba97 EC |
776 | #define STRUCT_FIELD(header, field) \ |
777 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
778 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
779 | ||
e126ba97 EC |
780 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
781 | { | |
782 | return pci_get_drvdata(pdev); | |
783 | } | |
784 | ||
785 | extern struct dentry *mlx5_debugfs_root; | |
786 | ||
787 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
788 | { | |
789 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
790 | } | |
791 | ||
792 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
793 | { | |
794 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
795 | } | |
796 | ||
797 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
798 | { | |
799 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
800 | } | |
801 | ||
802 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
803 | { | |
804 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
805 | } | |
806 | ||
3bcdb17a SG |
807 | static inline u32 mlx5_base_mkey(const u32 key) |
808 | { | |
809 | return key & 0xffffff00u; | |
810 | } | |
811 | ||
4972e6fa TT |
812 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
813 | u8 log_stride, u8 log_sz, | |
a0903622 | 814 | u16 strides_offset, |
d7037ad7 | 815 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 816 | { |
4972e6fa | 817 | fbc->frags = frags; |
3a2f7033 TT |
818 | fbc->log_stride = log_stride; |
819 | fbc->log_sz = log_sz; | |
388ca8be YC |
820 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
821 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
822 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
823 | fbc->strides_offset = strides_offset; |
824 | } | |
825 | ||
4972e6fa TT |
826 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
827 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
828 | struct mlx5_frag_buf_ctrl *fbc) |
829 | { | |
4972e6fa | 830 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
831 | } |
832 | ||
388ca8be YC |
833 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
834 | u32 ix) | |
835 | { | |
d7037ad7 TT |
836 | unsigned int frag; |
837 | ||
838 | ix += fbc->strides_offset; | |
839 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 840 | |
4972e6fa | 841 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
842 | } |
843 | ||
37fdffb2 TT |
844 | static inline u32 |
845 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
846 | { | |
847 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
848 | ||
849 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
850 | } | |
851 | ||
e126ba97 EC |
852 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
853 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
854 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
855 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 856 | |
e355477e JG |
857 | struct mlx5_async_ctx { |
858 | struct mlx5_core_dev *dev; | |
859 | atomic_t num_inflight; | |
860 | struct wait_queue_head wait; | |
861 | }; | |
862 | ||
863 | struct mlx5_async_work; | |
864 | ||
865 | typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); | |
866 | ||
867 | struct mlx5_async_work { | |
868 | struct mlx5_async_ctx *ctx; | |
869 | mlx5_async_cbk_t user_callback; | |
870 | }; | |
871 | ||
872 | void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, | |
873 | struct mlx5_async_ctx *ctx); | |
874 | void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); | |
875 | int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, | |
876 | void *out, int out_size, mlx5_async_cbk_t callback, | |
877 | struct mlx5_async_work *work); | |
878 | ||
e126ba97 EC |
879 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
880 | int out_size); | |
4525abea MD |
881 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
882 | void *out, int out_size); | |
c4f287c4 SM |
883 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
884 | ||
885 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
886 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
887 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
ac6ea6e8 EC |
888 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
889 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 890 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 891 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 892 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 893 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
2a0165a0 | 894 | void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); |
311c7c71 | 895 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
388ca8be YC |
896 | struct mlx5_frag_buf *buf, int node); |
897 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, | |
898 | int size, struct mlx5_frag_buf *buf); | |
899 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
900 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
901 | struct mlx5_frag_buf *buf, int node); | |
902 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
903 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
904 | gfp_t flags, int npages); | |
905 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
906 | struct mlx5_cmd_mailbox *head); | |
a606b0f6 MB |
907 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
908 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
909 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
910 | struct mlx5_core_mkey *mkey, | |
e355477e JG |
911 | struct mlx5_async_ctx *async_ctx, u32 *in, |
912 | int inlen, u32 *out, int outlen, | |
913 | mlx5_async_cbk_t callback, | |
914 | struct mlx5_async_work *context); | |
a606b0f6 MB |
915 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
916 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 917 | u32 *in, int inlen); |
a606b0f6 MB |
918 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
919 | struct mlx5_core_mkey *mkey); | |
920 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 921 | u32 *out, int outlen); |
e126ba97 EC |
922 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
923 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
0cf53c12 | 924 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
e126ba97 | 925 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
0cf53c12 | 926 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
e126ba97 EC |
927 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
928 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
591905ba | 929 | s32 npages, bool ec_function); |
cd23b14b | 930 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
931 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
932 | void mlx5_register_debugfs(void); | |
933 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
934 | |
935 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 936 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
0b6e26ce DT |
937 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
938 | unsigned int *irqn); | |
e126ba97 EC |
939 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
940 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
941 | ||
942 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
943 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
944 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
945 | int size_in, void *data_out, int size_out, | |
946 | u16 reg_num, int arg, int write); | |
adb0c954 | 947 | |
e126ba97 | 948 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
949 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
950 | int node); | |
e126ba97 EC |
951 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
952 | ||
e126ba97 EC |
953 | const char *mlx5_command_str(int command); |
954 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
955 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
956 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
957 | int npsvs, u32 *sig_index); | |
958 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 959 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
960 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
961 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
962 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
963 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 964 | |
1466cc5b YP |
965 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
966 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
967 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
968 | struct mlx5_rate_limit *rl); | |
969 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 970 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
05d3ac97 BW |
971 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
972 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
973 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
974 | bool map_wc, bool fast_path); | |
975 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 976 | |
f2f3df55 SM |
977 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
978 | struct cpumask * | |
979 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
980 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
981 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
982 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 983 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 984 | |
e3297246 EC |
985 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
986 | { | |
987 | return ioread32be(&dev->iseg->initializing) >> 31; | |
988 | } | |
989 | ||
e126ba97 EC |
990 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
991 | { | |
992 | return mkey >> 8; | |
993 | } | |
994 | ||
995 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
996 | { | |
997 | return mkey_idx << 8; | |
998 | } | |
999 | ||
746b5583 EC |
1000 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1001 | { | |
1002 | return mkey & 0xff; | |
1003 | } | |
1004 | ||
e126ba97 EC |
1005 | enum { |
1006 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1007 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1008 | }; |
1009 | ||
1010 | enum { | |
8b7ff7f3 | 1011 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1012 | MLX5_IMR_MTT_CACHE_ENTRY, |
1013 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1014 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1015 | }; |
1016 | ||
64613d94 SM |
1017 | enum { |
1018 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1019 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1020 | }; | |
1021 | ||
9603b61d JM |
1022 | struct mlx5_interface { |
1023 | void * (*add)(struct mlx5_core_dev *dev); | |
1024 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1025 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1026 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
64613d94 | 1027 | int protocol; |
9603b61d JM |
1028 | struct list_head list; |
1029 | }; | |
1030 | ||
1031 | int mlx5_register_interface(struct mlx5_interface *intf); | |
1032 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
20902be4 SM |
1033 | int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
1034 | int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
1035 | ||
211e6c80 | 1036 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1037 | |
3bc34f3b AH |
1038 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1039 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7c34ec19 AH |
1040 | bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); |
1041 | bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); | |
724b509c | 1042 | bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); |
7907f23a | 1043 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1044 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1045 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1046 | u64 *values, | |
1047 | int num_counters, | |
1048 | size_t *offsets); | |
01187175 EC |
1049 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1050 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
7907f23a | 1051 | |
f6a8a19b | 1052 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1053 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1054 | struct ib_device *ibdev, | |
1055 | const char *name, | |
1056 | void (*setup)(struct net_device *)); | |
693dfd5a | 1057 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1058 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1059 | struct ib_device *device, | |
1060 | struct rdma_netdev_alloc_params *params); | |
693dfd5a | 1061 | |
e126ba97 EC |
1062 | struct mlx5_profile { |
1063 | u64 mask; | |
f241e749 | 1064 | u8 log_max_qp; |
e126ba97 EC |
1065 | struct { |
1066 | int size; | |
1067 | int limit; | |
1068 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1069 | }; | |
1070 | ||
fc50db98 EC |
1071 | enum { |
1072 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1073 | }; | |
1074 | ||
1075 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
1076 | { | |
1077 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
1078 | } | |
1079 | ||
591905ba BW |
1080 | static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) |
1081 | { | |
1082 | return dev->caps.embedded_cpu; | |
1083 | } | |
1084 | ||
7f0d11c7 BW |
1085 | static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev) |
1086 | { | |
1087 | return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); | |
1088 | } | |
1089 | ||
81cd229c BW |
1090 | static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev) |
1091 | { | |
1092 | return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); | |
1093 | } | |
1094 | ||
feb39369 BW |
1095 | #define MLX5_HOST_PF_MAX_VFS (127u) |
1096 | static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev) | |
1097 | { | |
1098 | if (mlx5_core_is_ecpf_esw_manager(dev)) | |
1099 | return MLX5_HOST_PF_MAX_VFS; | |
1100 | else | |
1101 | return pci_sriov_get_totalvfs(dev->pdev); | |
1102 | } | |
1103 | ||
707c4602 MD |
1104 | static inline int mlx5_get_gid_table_len(u16 param) |
1105 | { | |
1106 | if (param > 4) { | |
1107 | pr_warn("gid table length is zero\n"); | |
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | return 8 * (1 << param); | |
1112 | } | |
1113 | ||
1466cc5b YP |
1114 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1115 | { | |
1116 | return !!(dev->priv.rl_table.max_size); | |
1117 | } | |
1118 | ||
32f69e4b DJ |
1119 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1120 | { | |
1121 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1122 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1123 | } | |
1124 | ||
1125 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1126 | { | |
1127 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1128 | } | |
1129 | ||
1130 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1131 | { | |
1132 | return mlx5_core_is_mp_slave(dev) || | |
1133 | mlx5_core_is_mp_master(dev); | |
1134 | } | |
1135 | ||
7fd8aefb DJ |
1136 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1137 | { | |
32f69e4b DJ |
1138 | if (!mlx5_core_mp_enabled(dev)) |
1139 | return 1; | |
1140 | ||
1141 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1142 | } |
1143 | ||
020446e0 EC |
1144 | enum { |
1145 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1146 | }; | |
1147 | ||
e126ba97 | 1148 | #endif /* MLX5_DRIVER_H */ |