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net/mlx5: Introduce blue flame register allocator
[linux-2.6-block.git] / include / linux / mlx5 / device.h
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e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
9218b44d 62#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
938fe83c
SM		 63#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 65#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67
68/* insert a value to a struct */
69#define MLX5_SET(typ, p, fld, v) do { \
70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
74 << __mlx5_dw_bit_off(typ, fld))); \
75} while (0)
76
e281682b
SM		 77#define MLX5_SET_TO_ONES(typ, p, fld) do { \
78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
83} while (0)
84
d29b796a
EC		 85#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87__mlx5_mask(typ, fld))
88
89#define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
92 ___t; \
93})
94
b8a4ddb2 95#define __MLX5_SET64(typ, p, fld, v) do { \
d29b796a 96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
d29b796a
EC		 97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
b8a4ddb2
TH		 100#define MLX5_SET64(typ, p, fld, v) do { \
101 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
102 __MLX5_SET64(typ, p, fld, v); \
103} while (0)
104
105#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
107 __MLX5_SET64(typ, p, fld[idx], v); \
108} while (0)
109
d29b796a
EC		 110#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
111
707c4602
MD		 112#define MLX5_GET64_PR(typ, p, fld) ({ \
113 u64 ___t = MLX5_GET64(typ, p, fld); \
114 pr_debug(#fld " = 0x%llx\n", ___t); \
115 ___t; \
116})
117
3efd9a11
MY		 118/* Big endian getters */
119#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
120 __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
123 type_t tmp; \
124 switch (sizeof(tmp)) { \
125 case sizeof(u8): \
126 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
127 break; \
128 case sizeof(u16): \
129 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
130 break; \
131 case sizeof(u32): \
132 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
133 break; \
134 case sizeof(u64): \
135 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
136 break; \
137 } \
138 tmp; \
139 })
140
ae76715d
HHZ		 141enum mlx5_inline_modes {
142 MLX5_INLINE_MODE_NONE,
143 MLX5_INLINE_MODE_L2,
144 MLX5_INLINE_MODE_IP,
145 MLX5_INLINE_MODE_TCP_UDP,
146};
147
e126ba97
EC		 148enum {
149 MLX5_MAX_COMMANDS = 32,
150 MLX5_CMD_DATA_BLOCK_SIZE = 512,
151 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 152 MLX5_MKEY_BSF_OCTO_SIZE = 4,
153 MLX5_MAX_PSVS = 4,
e126ba97
EC		 154};
155
156enum {
157 MLX5_EXTENDED_UD_AV = 0x80000000,
158};
159
160enum {
161 MLX5_CQ_STATE_ARMED = 9,
162 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
163 MLX5_CQ_STATE_FIRED = 0xa,
164};
165
166enum {
167 MLX5_STAT_RATE_OFFSET = 5,
168};
169
170enum {
171 MLX5_INLINE_SEG = 0x80000000,
172};
173
fc11fbf9
SM		 174enum {
175 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
176};
177
c7a08ac7
EC		 178enum {
179 MLX5_MIN_PKEY_TABLE_SIZE = 128,
180 MLX5_MAX_LOG_PKEY_TABLE = 5,
181};
182
e420f0c0
HE		 183enum {
184 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
185};
186
187enum {
188 MLX5_PFAULT_SUBTYPE_WQE = 0,
189 MLX5_PFAULT_SUBTYPE_RDMA = 1,
190};
191
e126ba97
EC		 192enum {
193 MLX5_PERM_LOCAL_READ = 1 << 2,
194 MLX5_PERM_LOCAL_WRITE = 1 << 3,
195 MLX5_PERM_REMOTE_READ = 1 << 4,
196 MLX5_PERM_REMOTE_WRITE = 1 << 5,
197 MLX5_PERM_ATOMIC = 1 << 6,
198 MLX5_PERM_UMR_EN = 1 << 7,
199};
200
201enum {
202 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
203 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
204 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
205 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
206 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
207};
208
e126ba97
EC		 209enum {
210 MLX5_EN_RD = (u64)1,
211 MLX5_EN_WR = (u64)2
212};
213
214enum {
2f5ff264
EC		 215 MLX5_BFREGS_PER_UAR = 4,
216 MLX5_MAX_UARS = 1 << 8,
217 MLX5_NON_FP_BFREGS_PER_UAR = 2,
a6d51b68
EC		 218 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
219 MLX5_NON_FP_BFREGS_PER_UAR,
2f5ff264
EC		 220 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
221 MLX5_NON_FP_BFREGS_PER_UAR,
e126ba97
EC		 222};
223
224enum {
225 MLX5_MKEY_MASK_LEN = 1ull << 0,
226 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
227 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
228 MLX5_MKEY_MASK_PD = 1ull << 7,
229 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 230 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 231 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
232 MLX5_MKEY_MASK_KEY = 1ull << 13,
233 MLX5_MKEY_MASK_QPN = 1ull << 14,
234 MLX5_MKEY_MASK_LR = 1ull << 17,
235 MLX5_MKEY_MASK_LW = 1ull << 18,
236 MLX5_MKEY_MASK_RR = 1ull << 19,
237 MLX5_MKEY_MASK_RW = 1ull << 20,
238 MLX5_MKEY_MASK_A = 1ull << 21,
239 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
240 MLX5_MKEY_MASK_FREE = 1ull << 29,
241};
242
968e78dd
HE		 243enum {
244 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
245
246 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
247 MLX5_UMR_CHECK_FREE = (2 << 5),
248
249 MLX5_UMR_INLINE = (1 << 7),
250};
251
cc149f75
HE		 252#define MLX5_UMR_MTT_ALIGNMENT 0x40
253#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 254#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 255
e2013b21 256#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
257
258enum {
259 MLX5_EVENT_QUEUE_TYPE_QP = 0,
260 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
261 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
262};
263
e126ba97
EC		 264enum mlx5_event {
265 MLX5_EVENT_TYPE_COMP = 0x0,
266
267 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
268 MLX5_EVENT_TYPE_COMM_EST = 0x02,
269 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
270 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
271 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
272
273 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
274 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
275 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
276 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
277 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
278 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
279
280 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
281 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
282 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
4ce3bf2f 283 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
e126ba97
EC		 284 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
285
286 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
287 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
288
289 MLX5_EVENT_TYPE_CMD = 0x0a,
290 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 291
292 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
073bb189 293 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
e126ba97
EC		 294};
295
296enum {
297 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
298 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
299 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
300 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
301 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
302 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
303 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
304};
305
306enum {
e126ba97 307 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 308 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
309 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
310 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
311 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 312 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 313 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 314 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 315 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 316 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 317 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 318 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 319};
320
3cca2606
AS		 321enum {
322 MLX5_ROCE_VERSION_1 = 0,
323 MLX5_ROCE_VERSION_2 = 2,
324};
325
326enum {
327 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
328 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
329};
330
331enum {
332 MLX5_ROCE_L3_TYPE_IPV4 = 0,
333 MLX5_ROCE_L3_TYPE_IPV6 = 1,
334};
335
336enum {
337 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
338 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
339};
340
e126ba97
EC		 341enum {
342 MLX5_OPCODE_NOP = 0x00,
343 MLX5_OPCODE_SEND_INVAL = 0x01,
344 MLX5_OPCODE_RDMA_WRITE = 0x08,
345 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
346 MLX5_OPCODE_SEND = 0x0a,
347 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 348 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 349 MLX5_OPCODE_RDMA_READ = 0x10,
350 MLX5_OPCODE_ATOMIC_CS = 0x11,
351 MLX5_OPCODE_ATOMIC_FA = 0x12,
352 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
353 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
354 MLX5_OPCODE_BIND_MW = 0x18,
355 MLX5_OPCODE_CONFIG_CMD = 0x1f,
356
357 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
358 MLX5_RECV_OPCODE_SEND = 0x01,
359 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
360 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
361
362 MLX5_CQE_OPCODE_ERROR = 0x1e,
363 MLX5_CQE_OPCODE_RESIZE = 0x16,
364
365 MLX5_OPCODE_SET_PSV = 0x20,
366 MLX5_OPCODE_GET_PSV = 0x21,
367 MLX5_OPCODE_CHECK_PSV = 0x22,
368 MLX5_OPCODE_RGET_PSV = 0x26,
369 MLX5_OPCODE_RCHECK_PSV = 0x27,
370
371 MLX5_OPCODE_UMR = 0x25,
372
373};
374
375enum {
376 MLX5_SET_PORT_RESET_QKEY = 0,
377 MLX5_SET_PORT_GUID0 = 16,
378 MLX5_SET_PORT_NODE_GUID = 17,
379 MLX5_SET_PORT_SYS_GUID = 18,
380 MLX5_SET_PORT_GID_TABLE = 19,
381 MLX5_SET_PORT_PKEY_TABLE = 20,
382};
383
d8880795
TT		 384enum {
385 MLX5_BW_NO_LIMIT = 0,
386 MLX5_100_MBPS_UNIT = 3,
387 MLX5_GBPS_UNIT = 4,
388};
389
e126ba97
EC		 390enum {
391 MLX5_MAX_PAGE_SHIFT = 31
392};
393
1b77d2bd 394enum {
05bdb2ab
EC		 395 MLX5_ADAPTER_PAGE_SHIFT = 12,
396 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 397};
398
87b8de49 399enum {
87b8de49
EC		 400 MLX5_CAP_OFF_CMDIF_CSUM = 46,
401};
402
986ef95e
SG		 403enum {
404 /*
405 * Max wqe size for rdma read is 512 bytes, so this
406 * limits our max_sge_rd as the wqe needs to fit:
407 * - ctrl segment (16 bytes)
408 * - rdma segment (16 bytes)
409 * - scatter elements (16 bytes each)
410 */
411 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
412};
413
e420f0c0
HE		 414enum mlx5_odp_transport_cap_bits {
415 MLX5_ODP_SUPPORT_SEND = 1 << 31,
416 MLX5_ODP_SUPPORT_RECV = 1 << 30,
417 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
418 MLX5_ODP_SUPPORT_READ = 1 << 28,
419};
420
421struct mlx5_odp_caps {
422 char reserved[0x10];
423 struct {
424 __be32 rc_odp_caps;
425 __be32 uc_odp_caps;
426 __be32 ud_odp_caps;
427 } per_transport_caps;
428 char reserved2[0xe4];
429};
430
e126ba97
EC		 431struct mlx5_cmd_layout {
432 u8 type;
433 u8 rsvd0[3];
434 __be32 inlen;
435 __be64 in_ptr;
436 __be32 in[4];
437 __be32 out[4];
438 __be64 out_ptr;
439 __be32 outlen;
440 u8 token;
441 u8 sig;
442 u8 rsvd1;
443 u8 status_own;
444};
445
e126ba97
EC		 446struct health_buffer {
447 __be32 assert_var[5];
448 __be32 rsvd0[3];
449 __be32 assert_exit_ptr;
450 __be32 assert_callra;
451 __be32 rsvd1[2];
452 __be32 fw_ver;
453 __be32 hw_id;
454 __be32 rsvd2;
455 u8 irisc_index;
456 u8 synd;
78ccb258 457 __be16 ext_synd;
e126ba97
EC		 458};
459
460struct mlx5_init_seg {
461 __be32 fw_rev;
462 __be32 cmdif_rev_fw_sub;
463 __be32 rsvd0[2];
464 __be32 cmdq_addr_h;
465 __be32 cmdq_addr_l_sz;
466 __be32 cmd_dbell;
e3297246
EC		 467 __be32 rsvd1[120];
468 __be32 initializing;
e126ba97 469 struct health_buffer health;
b0844444
EBE		 470 __be32 rsvd2[880];
471 __be32 internal_timer_h;
472 __be32 internal_timer_l;
b368d7cb 473 __be32 rsvd3[2];
e126ba97 474 __be32 health_counter;
b0844444 475 __be32 rsvd4[1019];
e126ba97
EC		 476 __be64 ieee1588_clk;
477 __be32 ieee1588_clk_type;
478 __be32 clr_intx;
479};
480
481struct mlx5_eqe_comp {
482 __be32 reserved[6];
483 __be32 cqn;
484};
485
486struct mlx5_eqe_qp_srq {
e2013b21 487 __be32 reserved1[5];
488 u8 type;
489 u8 reserved2[3];
e126ba97
EC		 490 __be32 qp_srq_n;
491};
492
493struct mlx5_eqe_cq_err {
494 __be32 cqn;
495 u8 reserved1[7];
496 u8 syndrome;
497};
498
e126ba97
EC		 499struct mlx5_eqe_port_state {
500 u8 reserved0[8];
501 u8 port;
502};
503
504struct mlx5_eqe_gpio {
505 __be32 reserved0[2];
506 __be64 gpio_event;
507};
508
509struct mlx5_eqe_congestion {
510 u8 type;
511 u8 rsvd0;
512 u8 congestion_level;
513};
514
515struct mlx5_eqe_stall_vl {
516 u8 rsvd0[3];
517 u8 port_vl;
518};
519
520struct mlx5_eqe_cmd {
521 __be32 vector;
522 __be32 rsvd[6];
523};
524
525struct mlx5_eqe_page_req {
526 u8 rsvd0[2];
527 __be16 func_id;
0a324f31
ML		 528 __be32 num_pages;
529 __be32 rsvd1[5];
e126ba97
EC		 530};
531
e420f0c0
HE		 532struct mlx5_eqe_page_fault {
533 __be32 bytes_committed;
534 union {
535 struct {
536 u16 reserved1;
537 __be16 wqe_index;
538 u16 reserved2;
539 __be16 packet_length;
d9aaed83
AK		 540 __be32 token;
541 u8 reserved4[8];
542 __be32 pftype_wq;
e420f0c0
HE		 543 } __packed wqe;
544 struct {
545 __be32 r_key;
546 u16 reserved1;
547 __be16 packet_length;
548 __be32 rdma_op_len;
549 __be64 rdma_va;
d9aaed83 550 __be32 pftype_token;
e420f0c0
HE		 551 } __packed rdma;
552 } __packed;
e420f0c0
HE		 553} __packed;
554
073bb189
SM		 555struct mlx5_eqe_vport_change {
556 u8 rsvd0[2];
557 __be16 vport_num;
558 __be32 rsvd1[6];
559} __packed;
560
4ce3bf2f
HN		 561struct mlx5_eqe_port_module {
562 u8 reserved_at_0[1];
563 u8 module;
564 u8 reserved_at_2[1];
565 u8 module_status;
566 u8 reserved_at_4[2];
567 u8 error_type;
568} __packed;
569
e126ba97
EC		 570union ev_data {
571 __be32 raw[7];
572 struct mlx5_eqe_cmd cmd;
573 struct mlx5_eqe_comp comp;
574 struct mlx5_eqe_qp_srq qp_srq;
575 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 576 struct mlx5_eqe_port_state port;
577 struct mlx5_eqe_gpio gpio;
578 struct mlx5_eqe_congestion cong;
579 struct mlx5_eqe_stall_vl stall_vl;
580 struct mlx5_eqe_page_req req_pages;
e420f0c0 581 struct mlx5_eqe_page_fault page_fault;
073bb189 582 struct mlx5_eqe_vport_change vport_change;
4ce3bf2f 583 struct mlx5_eqe_port_module port_module;
e126ba97
EC		 584} __packed;
585
586struct mlx5_eqe {
587 u8 rsvd0;
588 u8 type;
589 u8 rsvd1;
590 u8 sub_type;
591 __be32 rsvd2[7];
592 union ev_data data;
593 __be16 rsvd3;
594 u8 signature;
595 u8 owner;
596} __packed;
597
598struct mlx5_cmd_prot_block {
599 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
600 u8 rsvd0[48];
601 __be64 next;
602 __be32 block_num;
603 u8 rsvd1;
604 u8 token;
605 u8 ctrl_sig;
606 u8 sig;
607};
608
e281682b
SM		 609enum {
610 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
611};
612
e126ba97
EC		 613struct mlx5_err_cqe {
614 u8 rsvd0[32];
615 __be32 srqn;
616 u8 rsvd1[18];
617 u8 vendor_err_synd;
618 u8 syndrome;
619 __be32 s_wqe_opcode_qpn;
620 __be16 wqe_counter;
621 u8 signature;
622 u8 op_own;
623};
624
625struct mlx5_cqe64 {
1b223dd3
SM		 626 u8 outer_l3_tunneled;
627 u8 rsvd0;
628 __be16 wqe_id;
e281682b
SM		 629 u8 lro_tcppsh_abort_dupack;
630 u8 lro_min_ttl;
631 __be16 lro_tcp_win;
632 __be32 lro_ack_seq_num;
633 __be32 rss_hash_result;
634 u8 rss_hash_type;
e126ba97 635 u8 ml_path;
e281682b
SM		 636 u8 rsvd20[2];
637 __be16 check_sum;
e126ba97
EC		 638 __be16 slid;
639 __be32 flags_rqpn;
e281682b 640 u8 hds_ip_ext;
1b223dd3 641 u8 l4_l3_hdr_type;
e281682b
SM		 642 __be16 vlan_info;
643 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 644 __be32 imm_inval_pkey;
645 u8 rsvd40[4];
646 __be32 byte_cnt;
b0844444
EBE		 647 __be32 timestamp_h;
648 __be32 timestamp_l;
e126ba97
EC		 649 __be32 sop_drop_qpn;
650 __be16 wqe_counter;
651 u8 signature;
652 u8 op_own;
653};
654
7219ab34
TT		 655struct mlx5_mini_cqe8 {
656 union {
657 __be32 rx_hash_result;
658 struct {
659 __be16 checksum;
660 __be16 rsvd;
661 };
662 struct {
663 __be16 wqe_counter;
664 u8 s_wqe_opcode;
665 u8 reserved;
666 } s_wqe_info;
667 };
668 __be32 byte_cnt;
669};
670
671enum {
672 MLX5_NO_INLINE_DATA,
673 MLX5_INLINE_DATA32_SEG,
674 MLX5_INLINE_DATA64_SEG,
675 MLX5_COMPRESSED,
676};
677
678enum {
679 MLX5_CQE_FORMAT_CSUM = 0x1,
680};
681
682#define MLX5_MINI_CQE_ARRAY_SIZE 8
683
684static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
685{
686 return (cqe->op_own >> 2) & 0x3;
687}
688
e281682b
SM		 689static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
690{
691 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
692}
693
694static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
695{
1b223dd3
SM		 696 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
697}
698
699static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
700{
701 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
702}
703
704static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
705{
706 return cqe->outer_l3_tunneled & 0x1;
e281682b
SM		 707}
708
709static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
710{
1b223dd3 711 return !!(cqe->l4_l3_hdr_type & 0x1);
e281682b
SM		 712}
713
b0844444
EBE		 714static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
715{
716 u32 hi, lo;
717
718 hi = be32_to_cpu(cqe->timestamp_h);
719 lo = be32_to_cpu(cqe->timestamp_l);
720
721 return (u64)lo | ((u64)hi << 32);
722}
723
461017cb
TT		 724struct mpwrq_cqe_bc {
725 __be16 filler_consumed_strides;
726 __be16 byte_cnt;
727};
728
729static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
730{
731 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
732
733 return be16_to_cpu(bc->byte_cnt);
734}
735
736static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
737{
738 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
739}
740
741static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
742{
743 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
744
745 return mpwrq_get_cqe_bc_consumed_strides(bc);
746}
747
748static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
749{
750 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
751
752 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
753}
754
755static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
756{
757 return be16_to_cpu(cqe->wqe_counter);
758}
759
e281682b
SM		 760enum {
761 CQE_L4_HDR_TYPE_NONE = 0x0,
762 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
763 CQE_L4_HDR_TYPE_UDP = 0x2,
764 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
765 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
766};
767
768enum {
769 CQE_RSS_HTYPE_IP = 0x3 << 6,
770 CQE_RSS_HTYPE_L4 = 0x3 << 2,
771};
772
cb34be6d
AS		 773enum {
774 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
775 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
776 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
777};
778
e281682b
SM		 779enum {
780 CQE_L2_OK = 1 << 0,
781 CQE_L3_OK = 1 << 1,
782 CQE_L4_OK = 1 << 2,
783};
784
d5436ba0
SG		 785struct mlx5_sig_err_cqe {
786 u8 rsvd0[16];
787 __be32 expected_trans_sig;
788 __be32 actual_trans_sig;
789 __be32 expected_reftag;
790 __be32 actual_reftag;
791 __be16 syndrome;
792 u8 rsvd22[2];
793 __be32 mkey;
794 __be64 err_offset;
795 u8 rsvd30[8];
796 __be32 qpn;
797 u8 rsvd38[2];
798 u8 signature;
799 u8 op_own;
800};
801
e126ba97
EC		 802struct mlx5_wqe_srq_next_seg {
803 u8 rsvd0[2];
804 __be16 next_wqe_index;
805 u8 signature;
806 u8 rsvd1[11];
807};
808
809union mlx5_ext_cqe {
810 struct ib_grh grh;
811 u8 inl[64];
812};
813
814struct mlx5_cqe128 {
815 union mlx5_ext_cqe inl_grh;
816 struct mlx5_cqe64 cqe64;
817};
818
968e78dd
HE		 819enum {
820 MLX5_MKEY_STATUS_FREE = 1 << 6,
821};
822
ec22eb53
SM		 823enum {
824 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
825 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
826 MLX5_MKEY_BSF_EN = 1 << 30,
827 MLX5_MKEY_LEN64 = 1 << 31,
828};
829
e126ba97
EC		 830struct mlx5_mkey_seg {
831 /* This is a two bit field occupying bits 31-30.
832 * bit 31 is always 0,
833 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
834 */
835 u8 status;
836 u8 pcie_control;
837 u8 flags;
838 u8 version;
839 __be32 qpn_mkey7_0;
840 u8 rsvd1[4];
841 __be32 flags_pd;
842 __be64 start_addr;
843 __be64 len;
844 __be32 bsfs_octo_size;
845 u8 rsvd2[16];
846 __be32 xlt_oct_size;
847 u8 rsvd3[3];
848 u8 log2_page_size;
849 u8 rsvd4[4];
850};
851
e126ba97
EC		 852#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
853
854enum {
855 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
856};
857
e281682b
SM		 858enum {
859 VPORT_STATE_DOWN = 0x0,
860 VPORT_STATE_UP = 0x1,
861};
862
81848731
SM		 863enum {
864 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
865 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
866 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
867};
868
e281682b
SM		 869enum {
870 MLX5_L3_PROT_TYPE_IPV4 = 0,
871 MLX5_L3_PROT_TYPE_IPV6 = 1,
872};
873
874enum {
875 MLX5_L4_PROT_TYPE_TCP = 0,
876 MLX5_L4_PROT_TYPE_UDP = 1,
877};
878
879enum {
880 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
881 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
882 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
883 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
884 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
885};
886
887enum {
888 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
889 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
890 MLX5_MATCH_INNER_HEADERS = 1 << 2,
891
892};
893
894enum {
895 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
896 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
897};
898
899enum {
900 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
901 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
902 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
903};
904
e16aea27
SM		 905enum mlx5_list_type {
906 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
907 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
908 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
909};
910
e281682b
SM		 911enum {
912 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
913 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
914};
915
928cfe87
TT		 916enum mlx5_wol_mode {
917 MLX5_WOL_DISABLE = 0,
918 MLX5_WOL_SECURED_MAGIC = 1 << 1,
919 MLX5_WOL_MAGIC = 1 << 2,
920 MLX5_WOL_ARP = 1 << 3,
921 MLX5_WOL_BROADCAST = 1 << 4,
922 MLX5_WOL_MULTICAST = 1 << 5,
923 MLX5_WOL_UNICAST = 1 << 6,
924 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
925};
926
938fe83c
SM		 927/* MLX5 DEV CAPs */
928
929/* TODO: EAT.ME */
930enum mlx5_cap_mode {
931 HCA_CAP_OPMOD_GET_MAX = 0,
932 HCA_CAP_OPMOD_GET_CUR = 1,
933};
934
935enum mlx5_cap_type {
936 MLX5_CAP_GENERAL = 0,
937 MLX5_CAP_ETHERNET_OFFLOADS,
938 MLX5_CAP_ODP,
939 MLX5_CAP_ATOMIC,
940 MLX5_CAP_ROCE,
941 MLX5_CAP_IPOIB_OFFLOADS,
942 MLX5_CAP_EOIB_OFFLOADS,
943 MLX5_CAP_FLOW_TABLE,
495716b1 944 MLX5_CAP_ESWITCH_FLOW_TABLE,
d6666753 945 MLX5_CAP_ESWITCH,
3f0393a5
SG		 946 MLX5_CAP_RESERVED,
947 MLX5_CAP_VECTOR_CALC,
1466cc5b 948 MLX5_CAP_QOS,
938fe83c
SM		 949 /* NUM OF CAP Types */
950 MLX5_CAP_NUM
951};
952
953/* GET Dev Caps macros */
954#define MLX5_CAP_GEN(mdev, cap) \
955 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
956
957#define MLX5_CAP_GEN_MAX(mdev, cap) \
958 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
959
960#define MLX5_CAP_ETH(mdev, cap) \
961 MLX5_GET(per_protocol_networking_offload_caps,\
962 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
963
964#define MLX5_CAP_ETH_MAX(mdev, cap) \
965 MLX5_GET(per_protocol_networking_offload_caps,\
966 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
967
968#define MLX5_CAP_ROCE(mdev, cap) \
969 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
970
971#define MLX5_CAP_ROCE_MAX(mdev, cap) \
972 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
973
974#define MLX5_CAP_ATOMIC(mdev, cap) \
975 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
976
977#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
978 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
979
980#define MLX5_CAP_FLOWTABLE(mdev, cap) \
981 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
982
983#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
984 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
985
876d634d
MG		 986#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
987 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
988
989#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
990 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
991
cea824d4
MG		 992#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
993 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
994
995#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
996 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
997
998#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
999 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1000
1001#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1002 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1003
495716b1
SM		 1004#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1005 MLX5_GET(flow_table_eswitch_cap, \
1006 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1007
1008#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1009 MLX5_GET(flow_table_eswitch_cap, \
1010 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1011
1012#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1013 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1014
1015#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1016 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1017
efdc810b
MHY		 1018#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1019 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1020
1021#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1022 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1023
1024#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1025 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1026
1027#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1028 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1029
d6666753
SM		 1030#define MLX5_CAP_ESW(mdev, cap) \
1031 MLX5_GET(e_switch_cap, \
1032 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1033
1034#define MLX5_CAP_ESW_MAX(mdev, cap) \
1035 MLX5_GET(e_switch_cap, \
1036 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1037
938fe83c
SM		 1038#define MLX5_CAP_ODP(mdev, cap)\
1039 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1040
3f0393a5
SG		 1041#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1042 MLX5_GET(vector_calc_cap, \
1043 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1044
1466cc5b
YP		 1045#define MLX5_CAP_QOS(mdev, cap)\
1046 MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1047
f62b8bb8
AV		 1048enum {
1049 MLX5_CMD_STAT_OK = 0x0,
1050 MLX5_CMD_STAT_INT_ERR = 0x1,
1051 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1052 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1053 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1054 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1055 MLX5_CMD_STAT_RES_BUSY = 0x6,
1056 MLX5_CMD_STAT_LIM_ERR = 0x8,
1057 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1058 MLX5_CMD_STAT_IX_ERR = 0xa,
1059 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1060 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1061 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1062 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1063 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1064 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1065};
1066
efea389d
GP		 1067enum {
1068 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1069 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1070 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1071 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1072 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1073 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1c64bf6f 1074 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
121fcdc8 1075 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1c64bf6f 1076 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
efea389d
GP		 1077};
1078
7f503169
GP		 1079enum {
1080 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1081 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1082};
1083
707c4602
MD		 1084static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1085{
1086 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1087 return 0;
1088 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1089}
1090
35d19011
MG		 1091#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1092#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1093#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1094#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1095 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1096 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
4cbdd30e 1097
e126ba97 1098#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)