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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DEVICE_H | |
34 | #define MLX5_DEVICE_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <rdma/ib_verbs.h> | |
e281682b | 38 | #include <linux/mlx5/mlx5_ifc.h> |
e126ba97 EC |
39 | |
40 | #if defined(__LITTLE_ENDIAN) | |
41 | #define MLX5_SET_HOST_ENDIANNESS 0 | |
42 | #elif defined(__BIG_ENDIAN) | |
43 | #define MLX5_SET_HOST_ENDIANNESS 0x80 | |
44 | #else | |
45 | #error Host endianness not defined | |
46 | #endif | |
47 | ||
d29b796a EC |
48 | /* helper macros */ |
49 | #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) | |
50 | #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) | |
667cb65a | 51 | #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) |
d29b796a EC |
52 | #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) |
53 | #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) | |
54 | #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) | |
55 | #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) | |
56 | #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) | |
57 | #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) | |
58 | ||
59 | #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) | |
60 | #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) | |
61 | #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) | |
9218b44d | 62 | #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) |
938fe83c SM |
63 | #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) |
64 | #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) | |
d29b796a EC |
65 | #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) |
66 | #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) | |
67 | ||
68 | /* insert a value to a struct */ | |
69 | #define MLX5_SET(typ, p, fld, v) do { \ | |
a61d5ce9 | 70 | u32 _v = v; \ |
d29b796a EC |
71 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ |
72 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ | |
73 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ | |
a61d5ce9 | 74 | (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ |
d29b796a EC |
75 | << __mlx5_dw_bit_off(typ, fld))); \ |
76 | } while (0) | |
77 | ||
e281682b SM |
78 | #define MLX5_SET_TO_ONES(typ, p, fld) do { \ |
79 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ | |
80 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ | |
81 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ | |
82 | (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ | |
83 | << __mlx5_dw_bit_off(typ, fld))); \ | |
84 | } while (0) | |
85 | ||
d29b796a EC |
86 | #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ |
87 | __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ | |
88 | __mlx5_mask(typ, fld)) | |
89 | ||
90 | #define MLX5_GET_PR(typ, p, fld) ({ \ | |
91 | u32 ___t = MLX5_GET(typ, p, fld); \ | |
92 | pr_debug(#fld " = 0x%x\n", ___t); \ | |
93 | ___t; \ | |
94 | }) | |
95 | ||
b8a4ddb2 | 96 | #define __MLX5_SET64(typ, p, fld, v) do { \ |
d29b796a | 97 | BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ |
d29b796a EC |
98 | *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ |
99 | } while (0) | |
100 | ||
b8a4ddb2 TH |
101 | #define MLX5_SET64(typ, p, fld, v) do { \ |
102 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ | |
103 | __MLX5_SET64(typ, p, fld, v); \ | |
104 | } while (0) | |
105 | ||
106 | #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ | |
107 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ | |
108 | __MLX5_SET64(typ, p, fld[idx], v); \ | |
109 | } while (0) | |
110 | ||
d29b796a EC |
111 | #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) |
112 | ||
707c4602 MD |
113 | #define MLX5_GET64_PR(typ, p, fld) ({ \ |
114 | u64 ___t = MLX5_GET64(typ, p, fld); \ | |
115 | pr_debug(#fld " = 0x%llx\n", ___t); \ | |
116 | ___t; \ | |
117 | }) | |
118 | ||
3efd9a11 MY |
119 | /* Big endian getters */ |
120 | #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ | |
121 | __mlx5_64_off(typ, fld))) | |
122 | ||
123 | #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ | |
124 | type_t tmp; \ | |
125 | switch (sizeof(tmp)) { \ | |
126 | case sizeof(u8): \ | |
127 | tmp = (__force type_t)MLX5_GET(typ, p, fld); \ | |
128 | break; \ | |
129 | case sizeof(u16): \ | |
130 | tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ | |
131 | break; \ | |
132 | case sizeof(u32): \ | |
133 | tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ | |
134 | break; \ | |
135 | case sizeof(u64): \ | |
136 | tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ | |
137 | break; \ | |
138 | } \ | |
139 | tmp; \ | |
140 | }) | |
141 | ||
ae76715d HHZ |
142 | enum mlx5_inline_modes { |
143 | MLX5_INLINE_MODE_NONE, | |
144 | MLX5_INLINE_MODE_L2, | |
145 | MLX5_INLINE_MODE_IP, | |
146 | MLX5_INLINE_MODE_TCP_UDP, | |
147 | }; | |
148 | ||
e126ba97 EC |
149 | enum { |
150 | MLX5_MAX_COMMANDS = 32, | |
151 | MLX5_CMD_DATA_BLOCK_SIZE = 512, | |
152 | MLX5_PCI_CMD_XPORT = 7, | |
3121e3c4 SG |
153 | MLX5_MKEY_BSF_OCTO_SIZE = 4, |
154 | MLX5_MAX_PSVS = 4, | |
e126ba97 EC |
155 | }; |
156 | ||
157 | enum { | |
158 | MLX5_EXTENDED_UD_AV = 0x80000000, | |
159 | }; | |
160 | ||
161 | enum { | |
162 | MLX5_CQ_STATE_ARMED = 9, | |
163 | MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, | |
164 | MLX5_CQ_STATE_FIRED = 0xa, | |
165 | }; | |
166 | ||
167 | enum { | |
168 | MLX5_STAT_RATE_OFFSET = 5, | |
169 | }; | |
170 | ||
171 | enum { | |
172 | MLX5_INLINE_SEG = 0x80000000, | |
173 | }; | |
174 | ||
fc11fbf9 SM |
175 | enum { |
176 | MLX5_HW_START_PADDING = MLX5_INLINE_SEG, | |
177 | }; | |
178 | ||
c7a08ac7 EC |
179 | enum { |
180 | MLX5_MIN_PKEY_TABLE_SIZE = 128, | |
181 | MLX5_MAX_LOG_PKEY_TABLE = 5, | |
182 | }; | |
183 | ||
e420f0c0 HE |
184 | enum { |
185 | MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 | |
186 | }; | |
187 | ||
188 | enum { | |
189 | MLX5_PFAULT_SUBTYPE_WQE = 0, | |
190 | MLX5_PFAULT_SUBTYPE_RDMA = 1, | |
191 | }; | |
192 | ||
e126ba97 EC |
193 | enum { |
194 | MLX5_PERM_LOCAL_READ = 1 << 2, | |
195 | MLX5_PERM_LOCAL_WRITE = 1 << 3, | |
196 | MLX5_PERM_REMOTE_READ = 1 << 4, | |
197 | MLX5_PERM_REMOTE_WRITE = 1 << 5, | |
198 | MLX5_PERM_ATOMIC = 1 << 6, | |
199 | MLX5_PERM_UMR_EN = 1 << 7, | |
200 | }; | |
201 | ||
202 | enum { | |
203 | MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, | |
204 | MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, | |
205 | MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, | |
206 | MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, | |
207 | MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, | |
208 | }; | |
209 | ||
e126ba97 EC |
210 | enum { |
211 | MLX5_EN_RD = (u64)1, | |
212 | MLX5_EN_WR = (u64)2 | |
213 | }; | |
214 | ||
215 | enum { | |
b037c29a EC |
216 | MLX5_ADAPTER_PAGE_SHIFT = 12, |
217 | MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, | |
218 | }; | |
219 | ||
e126ba97 | 220 | enum { |
2f5ff264 EC |
221 | MLX5_BFREGS_PER_UAR = 4, |
222 | MLX5_MAX_UARS = 1 << 8, | |
223 | MLX5_NON_FP_BFREGS_PER_UAR = 2, | |
a6d51b68 EC |
224 | MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - |
225 | MLX5_NON_FP_BFREGS_PER_UAR, | |
2f5ff264 EC |
226 | MLX5_MAX_BFREGS = MLX5_MAX_UARS * |
227 | MLX5_NON_FP_BFREGS_PER_UAR, | |
b037c29a EC |
228 | MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, |
229 | MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, | |
e126ba97 EC |
230 | }; |
231 | ||
232 | enum { | |
233 | MLX5_MKEY_MASK_LEN = 1ull << 0, | |
234 | MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, | |
235 | MLX5_MKEY_MASK_START_ADDR = 1ull << 6, | |
236 | MLX5_MKEY_MASK_PD = 1ull << 7, | |
237 | MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, | |
d5436ba0 | 238 | MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, |
e126ba97 EC |
239 | MLX5_MKEY_MASK_BSF_EN = 1ull << 12, |
240 | MLX5_MKEY_MASK_KEY = 1ull << 13, | |
241 | MLX5_MKEY_MASK_QPN = 1ull << 14, | |
242 | MLX5_MKEY_MASK_LR = 1ull << 17, | |
243 | MLX5_MKEY_MASK_LW = 1ull << 18, | |
244 | MLX5_MKEY_MASK_RR = 1ull << 19, | |
245 | MLX5_MKEY_MASK_RW = 1ull << 20, | |
246 | MLX5_MKEY_MASK_A = 1ull << 21, | |
247 | MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, | |
248 | MLX5_MKEY_MASK_FREE = 1ull << 29, | |
249 | }; | |
250 | ||
968e78dd HE |
251 | enum { |
252 | MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), | |
253 | ||
254 | MLX5_UMR_CHECK_NOT_FREE = (1 << 5), | |
255 | MLX5_UMR_CHECK_FREE = (2 << 5), | |
256 | ||
257 | MLX5_UMR_INLINE = (1 << 7), | |
258 | }; | |
259 | ||
cc149f75 HE |
260 | #define MLX5_UMR_MTT_ALIGNMENT 0x40 |
261 | #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) | |
832a6b06 | 262 | #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT |
cc149f75 | 263 | |
e2013b21 | 264 | #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) |
265 | ||
266 | enum { | |
267 | MLX5_EVENT_QUEUE_TYPE_QP = 0, | |
268 | MLX5_EVENT_QUEUE_TYPE_RQ = 1, | |
269 | MLX5_EVENT_QUEUE_TYPE_SQ = 2, | |
270 | }; | |
271 | ||
e126ba97 EC |
272 | enum mlx5_event { |
273 | MLX5_EVENT_TYPE_COMP = 0x0, | |
274 | ||
275 | MLX5_EVENT_TYPE_PATH_MIG = 0x01, | |
276 | MLX5_EVENT_TYPE_COMM_EST = 0x02, | |
277 | MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, | |
278 | MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | |
279 | MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, | |
280 | ||
281 | MLX5_EVENT_TYPE_CQ_ERROR = 0x04, | |
282 | MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
283 | MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
284 | MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
285 | MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
286 | MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
287 | ||
288 | MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, | |
289 | MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, | |
290 | MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, | |
4ce3bf2f | 291 | MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, |
e126ba97 | 292 | MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, |
246ac981 | 293 | MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22, |
f9a1ef72 | 294 | MLX5_EVENT_TYPE_PPS_EVENT = 0x25, |
e126ba97 EC |
295 | |
296 | MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, | |
297 | MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, | |
298 | ||
299 | MLX5_EVENT_TYPE_CMD = 0x0a, | |
300 | MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, | |
e420f0c0 HE |
301 | |
302 | MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, | |
073bb189 | 303 | MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, |
e29341fb IT |
304 | |
305 | MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, | |
e126ba97 EC |
306 | }; |
307 | ||
246ac981 MG |
308 | enum { |
309 | MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, | |
310 | }; | |
311 | ||
e126ba97 EC |
312 | enum { |
313 | MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
314 | MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, | |
315 | MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, | |
316 | MLX5_PORT_CHANGE_SUBTYPE_LID = 6, | |
317 | MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, | |
318 | MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, | |
319 | MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, | |
320 | }; | |
321 | ||
322 | enum { | |
e126ba97 | 323 | MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, |
e126ba97 EC |
324 | MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, |
325 | MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
326 | MLX5_DEV_CAP_FLAG_APM = 1LL << 17, | |
327 | MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
f360d88a | 328 | MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, |
6cb7ff3d | 329 | MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, |
3bdb31f6 | 330 | MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, |
bde51583 | 331 | MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, |
c7a08ac7 | 332 | MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, |
e126ba97 | 333 | MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, |
c1868b82 | 334 | MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, |
e126ba97 EC |
335 | }; |
336 | ||
3cca2606 AS |
337 | enum { |
338 | MLX5_ROCE_VERSION_1 = 0, | |
339 | MLX5_ROCE_VERSION_2 = 2, | |
340 | }; | |
341 | ||
342 | enum { | |
343 | MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, | |
344 | MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, | |
345 | }; | |
346 | ||
347 | enum { | |
348 | MLX5_ROCE_L3_TYPE_IPV4 = 0, | |
349 | MLX5_ROCE_L3_TYPE_IPV6 = 1, | |
350 | }; | |
351 | ||
352 | enum { | |
353 | MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, | |
354 | MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, | |
355 | }; | |
356 | ||
e126ba97 EC |
357 | enum { |
358 | MLX5_OPCODE_NOP = 0x00, | |
359 | MLX5_OPCODE_SEND_INVAL = 0x01, | |
360 | MLX5_OPCODE_RDMA_WRITE = 0x08, | |
361 | MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, | |
362 | MLX5_OPCODE_SEND = 0x0a, | |
363 | MLX5_OPCODE_SEND_IMM = 0x0b, | |
e281682b | 364 | MLX5_OPCODE_LSO = 0x0e, |
e126ba97 EC |
365 | MLX5_OPCODE_RDMA_READ = 0x10, |
366 | MLX5_OPCODE_ATOMIC_CS = 0x11, | |
367 | MLX5_OPCODE_ATOMIC_FA = 0x12, | |
368 | MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, | |
369 | MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, | |
370 | MLX5_OPCODE_BIND_MW = 0x18, | |
371 | MLX5_OPCODE_CONFIG_CMD = 0x1f, | |
372 | ||
373 | MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
374 | MLX5_RECV_OPCODE_SEND = 0x01, | |
375 | MLX5_RECV_OPCODE_SEND_IMM = 0x02, | |
376 | MLX5_RECV_OPCODE_SEND_INVAL = 0x03, | |
377 | ||
378 | MLX5_CQE_OPCODE_ERROR = 0x1e, | |
379 | MLX5_CQE_OPCODE_RESIZE = 0x16, | |
380 | ||
381 | MLX5_OPCODE_SET_PSV = 0x20, | |
382 | MLX5_OPCODE_GET_PSV = 0x21, | |
383 | MLX5_OPCODE_CHECK_PSV = 0x22, | |
384 | MLX5_OPCODE_RGET_PSV = 0x26, | |
385 | MLX5_OPCODE_RCHECK_PSV = 0x27, | |
386 | ||
387 | MLX5_OPCODE_UMR = 0x25, | |
388 | ||
389 | }; | |
390 | ||
391 | enum { | |
392 | MLX5_SET_PORT_RESET_QKEY = 0, | |
393 | MLX5_SET_PORT_GUID0 = 16, | |
394 | MLX5_SET_PORT_NODE_GUID = 17, | |
395 | MLX5_SET_PORT_SYS_GUID = 18, | |
396 | MLX5_SET_PORT_GID_TABLE = 19, | |
397 | MLX5_SET_PORT_PKEY_TABLE = 20, | |
398 | }; | |
399 | ||
d8880795 TT |
400 | enum { |
401 | MLX5_BW_NO_LIMIT = 0, | |
402 | MLX5_100_MBPS_UNIT = 3, | |
403 | MLX5_GBPS_UNIT = 4, | |
404 | }; | |
405 | ||
e126ba97 EC |
406 | enum { |
407 | MLX5_MAX_PAGE_SHIFT = 31 | |
408 | }; | |
409 | ||
87b8de49 | 410 | enum { |
87b8de49 EC |
411 | MLX5_CAP_OFF_CMDIF_CSUM = 46, |
412 | }; | |
413 | ||
986ef95e SG |
414 | enum { |
415 | /* | |
416 | * Max wqe size for rdma read is 512 bytes, so this | |
417 | * limits our max_sge_rd as the wqe needs to fit: | |
418 | * - ctrl segment (16 bytes) | |
419 | * - rdma segment (16 bytes) | |
420 | * - scatter elements (16 bytes each) | |
421 | */ | |
422 | MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 | |
423 | }; | |
424 | ||
e420f0c0 HE |
425 | enum mlx5_odp_transport_cap_bits { |
426 | MLX5_ODP_SUPPORT_SEND = 1 << 31, | |
427 | MLX5_ODP_SUPPORT_RECV = 1 << 30, | |
428 | MLX5_ODP_SUPPORT_WRITE = 1 << 29, | |
429 | MLX5_ODP_SUPPORT_READ = 1 << 28, | |
430 | }; | |
431 | ||
432 | struct mlx5_odp_caps { | |
433 | char reserved[0x10]; | |
434 | struct { | |
435 | __be32 rc_odp_caps; | |
436 | __be32 uc_odp_caps; | |
437 | __be32 ud_odp_caps; | |
438 | } per_transport_caps; | |
439 | char reserved2[0xe4]; | |
440 | }; | |
441 | ||
e126ba97 EC |
442 | struct mlx5_cmd_layout { |
443 | u8 type; | |
444 | u8 rsvd0[3]; | |
445 | __be32 inlen; | |
446 | __be64 in_ptr; | |
447 | __be32 in[4]; | |
448 | __be32 out[4]; | |
449 | __be64 out_ptr; | |
450 | __be32 outlen; | |
451 | u8 token; | |
452 | u8 sig; | |
453 | u8 rsvd1; | |
454 | u8 status_own; | |
455 | }; | |
456 | ||
e126ba97 EC |
457 | struct health_buffer { |
458 | __be32 assert_var[5]; | |
459 | __be32 rsvd0[3]; | |
460 | __be32 assert_exit_ptr; | |
461 | __be32 assert_callra; | |
462 | __be32 rsvd1[2]; | |
463 | __be32 fw_ver; | |
464 | __be32 hw_id; | |
465 | __be32 rsvd2; | |
466 | u8 irisc_index; | |
467 | u8 synd; | |
78ccb258 | 468 | __be16 ext_synd; |
e126ba97 EC |
469 | }; |
470 | ||
471 | struct mlx5_init_seg { | |
472 | __be32 fw_rev; | |
473 | __be32 cmdif_rev_fw_sub; | |
474 | __be32 rsvd0[2]; | |
475 | __be32 cmdq_addr_h; | |
476 | __be32 cmdq_addr_l_sz; | |
477 | __be32 cmd_dbell; | |
e3297246 EC |
478 | __be32 rsvd1[120]; |
479 | __be32 initializing; | |
e126ba97 | 480 | struct health_buffer health; |
b0844444 EBE |
481 | __be32 rsvd2[880]; |
482 | __be32 internal_timer_h; | |
483 | __be32 internal_timer_l; | |
b368d7cb | 484 | __be32 rsvd3[2]; |
e126ba97 | 485 | __be32 health_counter; |
b0844444 | 486 | __be32 rsvd4[1019]; |
e126ba97 EC |
487 | __be64 ieee1588_clk; |
488 | __be32 ieee1588_clk_type; | |
489 | __be32 clr_intx; | |
490 | }; | |
491 | ||
492 | struct mlx5_eqe_comp { | |
493 | __be32 reserved[6]; | |
494 | __be32 cqn; | |
495 | }; | |
496 | ||
497 | struct mlx5_eqe_qp_srq { | |
e2013b21 | 498 | __be32 reserved1[5]; |
499 | u8 type; | |
500 | u8 reserved2[3]; | |
e126ba97 EC |
501 | __be32 qp_srq_n; |
502 | }; | |
503 | ||
504 | struct mlx5_eqe_cq_err { | |
505 | __be32 cqn; | |
506 | u8 reserved1[7]; | |
507 | u8 syndrome; | |
508 | }; | |
509 | ||
e126ba97 EC |
510 | struct mlx5_eqe_port_state { |
511 | u8 reserved0[8]; | |
512 | u8 port; | |
513 | }; | |
514 | ||
515 | struct mlx5_eqe_gpio { | |
516 | __be32 reserved0[2]; | |
517 | __be64 gpio_event; | |
518 | }; | |
519 | ||
520 | struct mlx5_eqe_congestion { | |
521 | u8 type; | |
522 | u8 rsvd0; | |
523 | u8 congestion_level; | |
524 | }; | |
525 | ||
526 | struct mlx5_eqe_stall_vl { | |
527 | u8 rsvd0[3]; | |
528 | u8 port_vl; | |
529 | }; | |
530 | ||
531 | struct mlx5_eqe_cmd { | |
532 | __be32 vector; | |
533 | __be32 rsvd[6]; | |
534 | }; | |
535 | ||
536 | struct mlx5_eqe_page_req { | |
537 | u8 rsvd0[2]; | |
538 | __be16 func_id; | |
0a324f31 ML |
539 | __be32 num_pages; |
540 | __be32 rsvd1[5]; | |
e126ba97 EC |
541 | }; |
542 | ||
e420f0c0 HE |
543 | struct mlx5_eqe_page_fault { |
544 | __be32 bytes_committed; | |
545 | union { | |
546 | struct { | |
547 | u16 reserved1; | |
548 | __be16 wqe_index; | |
549 | u16 reserved2; | |
550 | __be16 packet_length; | |
d9aaed83 AK |
551 | __be32 token; |
552 | u8 reserved4[8]; | |
553 | __be32 pftype_wq; | |
e420f0c0 HE |
554 | } __packed wqe; |
555 | struct { | |
556 | __be32 r_key; | |
557 | u16 reserved1; | |
558 | __be16 packet_length; | |
559 | __be32 rdma_op_len; | |
560 | __be64 rdma_va; | |
d9aaed83 | 561 | __be32 pftype_token; |
e420f0c0 HE |
562 | } __packed rdma; |
563 | } __packed; | |
e420f0c0 HE |
564 | } __packed; |
565 | ||
073bb189 SM |
566 | struct mlx5_eqe_vport_change { |
567 | u8 rsvd0[2]; | |
568 | __be16 vport_num; | |
569 | __be32 rsvd1[6]; | |
570 | } __packed; | |
571 | ||
4ce3bf2f HN |
572 | struct mlx5_eqe_port_module { |
573 | u8 reserved_at_0[1]; | |
574 | u8 module; | |
575 | u8 reserved_at_2[1]; | |
576 | u8 module_status; | |
577 | u8 reserved_at_4[2]; | |
578 | u8 error_type; | |
579 | } __packed; | |
580 | ||
f9a1ef72 EE |
581 | struct mlx5_eqe_pps { |
582 | u8 rsvd0[3]; | |
583 | u8 pin; | |
584 | u8 rsvd1[4]; | |
585 | union { | |
586 | struct { | |
587 | __be32 time_sec; | |
588 | __be32 time_nsec; | |
589 | }; | |
590 | struct { | |
591 | __be64 time_stamp; | |
592 | }; | |
593 | }; | |
594 | u8 rsvd2[12]; | |
595 | } __packed; | |
596 | ||
e126ba97 EC |
597 | union ev_data { |
598 | __be32 raw[7]; | |
599 | struct mlx5_eqe_cmd cmd; | |
600 | struct mlx5_eqe_comp comp; | |
601 | struct mlx5_eqe_qp_srq qp_srq; | |
602 | struct mlx5_eqe_cq_err cq_err; | |
e126ba97 EC |
603 | struct mlx5_eqe_port_state port; |
604 | struct mlx5_eqe_gpio gpio; | |
605 | struct mlx5_eqe_congestion cong; | |
606 | struct mlx5_eqe_stall_vl stall_vl; | |
607 | struct mlx5_eqe_page_req req_pages; | |
e420f0c0 | 608 | struct mlx5_eqe_page_fault page_fault; |
073bb189 | 609 | struct mlx5_eqe_vport_change vport_change; |
4ce3bf2f | 610 | struct mlx5_eqe_port_module port_module; |
f9a1ef72 | 611 | struct mlx5_eqe_pps pps; |
e126ba97 EC |
612 | } __packed; |
613 | ||
614 | struct mlx5_eqe { | |
615 | u8 rsvd0; | |
616 | u8 type; | |
617 | u8 rsvd1; | |
618 | u8 sub_type; | |
619 | __be32 rsvd2[7]; | |
620 | union ev_data data; | |
621 | __be16 rsvd3; | |
622 | u8 signature; | |
623 | u8 owner; | |
624 | } __packed; | |
625 | ||
626 | struct mlx5_cmd_prot_block { | |
627 | u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; | |
628 | u8 rsvd0[48]; | |
629 | __be64 next; | |
630 | __be32 block_num; | |
631 | u8 rsvd1; | |
632 | u8 token; | |
633 | u8 ctrl_sig; | |
634 | u8 sig; | |
635 | }; | |
636 | ||
e281682b SM |
637 | enum { |
638 | MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, | |
639 | }; | |
640 | ||
e126ba97 EC |
641 | struct mlx5_err_cqe { |
642 | u8 rsvd0[32]; | |
643 | __be32 srqn; | |
644 | u8 rsvd1[18]; | |
645 | u8 vendor_err_synd; | |
646 | u8 syndrome; | |
647 | __be32 s_wqe_opcode_qpn; | |
648 | __be16 wqe_counter; | |
649 | u8 signature; | |
650 | u8 op_own; | |
651 | }; | |
652 | ||
653 | struct mlx5_cqe64 { | |
1b223dd3 SM |
654 | u8 outer_l3_tunneled; |
655 | u8 rsvd0; | |
656 | __be16 wqe_id; | |
e281682b SM |
657 | u8 lro_tcppsh_abort_dupack; |
658 | u8 lro_min_ttl; | |
659 | __be16 lro_tcp_win; | |
660 | __be32 lro_ack_seq_num; | |
661 | __be32 rss_hash_result; | |
662 | u8 rss_hash_type; | |
e126ba97 | 663 | u8 ml_path; |
e281682b SM |
664 | u8 rsvd20[2]; |
665 | __be16 check_sum; | |
e126ba97 EC |
666 | __be16 slid; |
667 | __be32 flags_rqpn; | |
e281682b | 668 | u8 hds_ip_ext; |
1b223dd3 | 669 | u8 l4_l3_hdr_type; |
e281682b SM |
670 | __be16 vlan_info; |
671 | __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ | |
e126ba97 EC |
672 | __be32 imm_inval_pkey; |
673 | u8 rsvd40[4]; | |
674 | __be32 byte_cnt; | |
b0844444 EBE |
675 | __be32 timestamp_h; |
676 | __be32 timestamp_l; | |
e126ba97 EC |
677 | __be32 sop_drop_qpn; |
678 | __be16 wqe_counter; | |
679 | u8 signature; | |
680 | u8 op_own; | |
681 | }; | |
682 | ||
7219ab34 TT |
683 | struct mlx5_mini_cqe8 { |
684 | union { | |
685 | __be32 rx_hash_result; | |
686 | struct { | |
687 | __be16 checksum; | |
688 | __be16 rsvd; | |
689 | }; | |
690 | struct { | |
691 | __be16 wqe_counter; | |
692 | u8 s_wqe_opcode; | |
693 | u8 reserved; | |
694 | } s_wqe_info; | |
695 | }; | |
696 | __be32 byte_cnt; | |
697 | }; | |
698 | ||
699 | enum { | |
700 | MLX5_NO_INLINE_DATA, | |
701 | MLX5_INLINE_DATA32_SEG, | |
702 | MLX5_INLINE_DATA64_SEG, | |
703 | MLX5_COMPRESSED, | |
704 | }; | |
705 | ||
706 | enum { | |
707 | MLX5_CQE_FORMAT_CSUM = 0x1, | |
708 | }; | |
709 | ||
710 | #define MLX5_MINI_CQE_ARRAY_SIZE 8 | |
711 | ||
712 | static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) | |
713 | { | |
714 | return (cqe->op_own >> 2) & 0x3; | |
715 | } | |
716 | ||
604acb19 | 717 | static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) |
e281682b SM |
718 | { |
719 | return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; | |
720 | } | |
721 | ||
722 | static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) | |
723 | { | |
1b223dd3 SM |
724 | return (cqe->l4_l3_hdr_type >> 4) & 0x7; |
725 | } | |
726 | ||
727 | static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) | |
728 | { | |
729 | return (cqe->l4_l3_hdr_type >> 2) & 0x3; | |
730 | } | |
731 | ||
732 | static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe) | |
733 | { | |
734 | return cqe->outer_l3_tunneled & 0x1; | |
e281682b SM |
735 | } |
736 | ||
737 | static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe) | |
738 | { | |
1b223dd3 | 739 | return !!(cqe->l4_l3_hdr_type & 0x1); |
e281682b SM |
740 | } |
741 | ||
b0844444 EBE |
742 | static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) |
743 | { | |
744 | u32 hi, lo; | |
745 | ||
746 | hi = be32_to_cpu(cqe->timestamp_h); | |
747 | lo = be32_to_cpu(cqe->timestamp_l); | |
748 | ||
749 | return (u64)lo | ((u64)hi << 32); | |
750 | } | |
751 | ||
461017cb TT |
752 | struct mpwrq_cqe_bc { |
753 | __be16 filler_consumed_strides; | |
754 | __be16 byte_cnt; | |
755 | }; | |
756 | ||
757 | static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) | |
758 | { | |
759 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; | |
760 | ||
761 | return be16_to_cpu(bc->byte_cnt); | |
762 | } | |
763 | ||
764 | static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) | |
765 | { | |
766 | return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); | |
767 | } | |
768 | ||
769 | static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) | |
770 | { | |
771 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; | |
772 | ||
773 | return mpwrq_get_cqe_bc_consumed_strides(bc); | |
774 | } | |
775 | ||
776 | static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) | |
777 | { | |
778 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; | |
779 | ||
780 | return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); | |
781 | } | |
782 | ||
783 | static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) | |
784 | { | |
785 | return be16_to_cpu(cqe->wqe_counter); | |
786 | } | |
787 | ||
e281682b SM |
788 | enum { |
789 | CQE_L4_HDR_TYPE_NONE = 0x0, | |
790 | CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, | |
791 | CQE_L4_HDR_TYPE_UDP = 0x2, | |
792 | CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, | |
793 | CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, | |
794 | }; | |
795 | ||
796 | enum { | |
12e8b570 JDB |
797 | CQE_RSS_HTYPE_IP = 0x3 << 2, |
798 | /* cqe->rss_hash_type[3:2] - IP destination selected for hash | |
799 | * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) | |
800 | */ | |
801 | CQE_RSS_HTYPE_L4 = 0x3 << 6, | |
802 | /* cqe->rss_hash_type[7:6] - L4 destination selected for hash | |
803 | * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI | |
804 | */ | |
e281682b SM |
805 | }; |
806 | ||
cb34be6d AS |
807 | enum { |
808 | MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, | |
809 | MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, | |
810 | MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, | |
811 | }; | |
812 | ||
e281682b SM |
813 | enum { |
814 | CQE_L2_OK = 1 << 0, | |
815 | CQE_L3_OK = 1 << 1, | |
816 | CQE_L4_OK = 1 << 2, | |
817 | }; | |
818 | ||
d5436ba0 SG |
819 | struct mlx5_sig_err_cqe { |
820 | u8 rsvd0[16]; | |
821 | __be32 expected_trans_sig; | |
822 | __be32 actual_trans_sig; | |
823 | __be32 expected_reftag; | |
824 | __be32 actual_reftag; | |
825 | __be16 syndrome; | |
826 | u8 rsvd22[2]; | |
827 | __be32 mkey; | |
828 | __be64 err_offset; | |
829 | u8 rsvd30[8]; | |
830 | __be32 qpn; | |
831 | u8 rsvd38[2]; | |
832 | u8 signature; | |
833 | u8 op_own; | |
834 | }; | |
835 | ||
e126ba97 EC |
836 | struct mlx5_wqe_srq_next_seg { |
837 | u8 rsvd0[2]; | |
838 | __be16 next_wqe_index; | |
839 | u8 signature; | |
840 | u8 rsvd1[11]; | |
841 | }; | |
842 | ||
843 | union mlx5_ext_cqe { | |
844 | struct ib_grh grh; | |
845 | u8 inl[64]; | |
846 | }; | |
847 | ||
848 | struct mlx5_cqe128 { | |
849 | union mlx5_ext_cqe inl_grh; | |
850 | struct mlx5_cqe64 cqe64; | |
851 | }; | |
852 | ||
968e78dd HE |
853 | enum { |
854 | MLX5_MKEY_STATUS_FREE = 1 << 6, | |
855 | }; | |
856 | ||
ec22eb53 SM |
857 | enum { |
858 | MLX5_MKEY_REMOTE_INVAL = 1 << 24, | |
859 | MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, | |
860 | MLX5_MKEY_BSF_EN = 1 << 30, | |
861 | MLX5_MKEY_LEN64 = 1 << 31, | |
862 | }; | |
863 | ||
e126ba97 EC |
864 | struct mlx5_mkey_seg { |
865 | /* This is a two bit field occupying bits 31-30. | |
866 | * bit 31 is always 0, | |
867 | * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation | |
868 | */ | |
869 | u8 status; | |
870 | u8 pcie_control; | |
871 | u8 flags; | |
872 | u8 version; | |
873 | __be32 qpn_mkey7_0; | |
874 | u8 rsvd1[4]; | |
875 | __be32 flags_pd; | |
876 | __be64 start_addr; | |
877 | __be64 len; | |
878 | __be32 bsfs_octo_size; | |
879 | u8 rsvd2[16]; | |
880 | __be32 xlt_oct_size; | |
881 | u8 rsvd3[3]; | |
882 | u8 log2_page_size; | |
883 | u8 rsvd4[4]; | |
884 | }; | |
885 | ||
e126ba97 EC |
886 | #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
887 | ||
888 | enum { | |
889 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 | |
890 | }; | |
891 | ||
e281682b SM |
892 | enum { |
893 | VPORT_STATE_DOWN = 0x0, | |
894 | VPORT_STATE_UP = 0x1, | |
895 | }; | |
896 | ||
81848731 SM |
897 | enum { |
898 | MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, | |
899 | MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, | |
900 | MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, | |
901 | }; | |
902 | ||
e281682b SM |
903 | enum { |
904 | MLX5_L3_PROT_TYPE_IPV4 = 0, | |
905 | MLX5_L3_PROT_TYPE_IPV6 = 1, | |
906 | }; | |
907 | ||
908 | enum { | |
909 | MLX5_L4_PROT_TYPE_TCP = 0, | |
910 | MLX5_L4_PROT_TYPE_UDP = 1, | |
911 | }; | |
912 | ||
913 | enum { | |
914 | MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, | |
915 | MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, | |
916 | MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, | |
917 | MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, | |
918 | MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, | |
919 | }; | |
920 | ||
921 | enum { | |
922 | MLX5_MATCH_OUTER_HEADERS = 1 << 0, | |
923 | MLX5_MATCH_MISC_PARAMETERS = 1 << 1, | |
924 | MLX5_MATCH_INNER_HEADERS = 1 << 2, | |
925 | ||
926 | }; | |
927 | ||
928 | enum { | |
929 | MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, | |
930 | MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, | |
931 | }; | |
932 | ||
933 | enum { | |
934 | MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, | |
935 | MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, | |
936 | MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, | |
937 | }; | |
938 | ||
e16aea27 SM |
939 | enum mlx5_list_type { |
940 | MLX5_NVPRT_LIST_TYPE_UC = 0x0, | |
941 | MLX5_NVPRT_LIST_TYPE_MC = 0x1, | |
942 | MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, | |
943 | }; | |
944 | ||
e281682b SM |
945 | enum { |
946 | MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, | |
947 | MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, | |
948 | }; | |
949 | ||
928cfe87 TT |
950 | enum mlx5_wol_mode { |
951 | MLX5_WOL_DISABLE = 0, | |
952 | MLX5_WOL_SECURED_MAGIC = 1 << 1, | |
953 | MLX5_WOL_MAGIC = 1 << 2, | |
954 | MLX5_WOL_ARP = 1 << 3, | |
955 | MLX5_WOL_BROADCAST = 1 << 4, | |
956 | MLX5_WOL_MULTICAST = 1 << 5, | |
957 | MLX5_WOL_UNICAST = 1 << 6, | |
958 | MLX5_WOL_PHY_ACTIVITY = 1 << 7, | |
959 | }; | |
960 | ||
938fe83c SM |
961 | /* MLX5 DEV CAPs */ |
962 | ||
963 | /* TODO: EAT.ME */ | |
964 | enum mlx5_cap_mode { | |
965 | HCA_CAP_OPMOD_GET_MAX = 0, | |
966 | HCA_CAP_OPMOD_GET_CUR = 1, | |
967 | }; | |
968 | ||
969 | enum mlx5_cap_type { | |
970 | MLX5_CAP_GENERAL = 0, | |
971 | MLX5_CAP_ETHERNET_OFFLOADS, | |
972 | MLX5_CAP_ODP, | |
973 | MLX5_CAP_ATOMIC, | |
974 | MLX5_CAP_ROCE, | |
975 | MLX5_CAP_IPOIB_OFFLOADS, | |
4ce749bd | 976 | MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, |
938fe83c | 977 | MLX5_CAP_FLOW_TABLE, |
495716b1 | 978 | MLX5_CAP_ESWITCH_FLOW_TABLE, |
d6666753 | 979 | MLX5_CAP_ESWITCH, |
3f0393a5 SG |
980 | MLX5_CAP_RESERVED, |
981 | MLX5_CAP_VECTOR_CALC, | |
1466cc5b | 982 | MLX5_CAP_QOS, |
938fe83c SM |
983 | /* NUM OF CAP Types */ |
984 | MLX5_CAP_NUM | |
985 | }; | |
986 | ||
cfdcbcea GP |
987 | enum mlx5_pcam_reg_groups { |
988 | MLX5_PCAM_REGS_5000_TO_507F = 0x0, | |
989 | }; | |
990 | ||
991 | enum mlx5_pcam_feature_groups { | |
992 | MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, | |
993 | }; | |
994 | ||
995 | enum mlx5_mcam_reg_groups { | |
996 | MLX5_MCAM_REGS_FIRST_128 = 0x0, | |
997 | }; | |
998 | ||
999 | enum mlx5_mcam_feature_groups { | |
1000 | MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, | |
1001 | }; | |
1002 | ||
938fe83c SM |
1003 | /* GET Dev Caps macros */ |
1004 | #define MLX5_CAP_GEN(mdev, cap) \ | |
701052c5 | 1005 | MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) |
938fe83c SM |
1006 | |
1007 | #define MLX5_CAP_GEN_MAX(mdev, cap) \ | |
701052c5 | 1008 | MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap) |
938fe83c SM |
1009 | |
1010 | #define MLX5_CAP_ETH(mdev, cap) \ | |
1011 | MLX5_GET(per_protocol_networking_offload_caps,\ | |
701052c5 | 1012 | mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) |
938fe83c SM |
1013 | |
1014 | #define MLX5_CAP_ETH_MAX(mdev, cap) \ | |
1015 | MLX5_GET(per_protocol_networking_offload_caps,\ | |
701052c5 | 1016 | mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) |
938fe83c | 1017 | |
4ce749bd YH |
1018 | #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ |
1019 | MLX5_GET(per_protocol_networking_offload_caps,\ | |
1020 | mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap) | |
1021 | ||
938fe83c | 1022 | #define MLX5_CAP_ROCE(mdev, cap) \ |
701052c5 | 1023 | MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap) |
938fe83c SM |
1024 | |
1025 | #define MLX5_CAP_ROCE_MAX(mdev, cap) \ | |
701052c5 | 1026 | MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap) |
938fe83c SM |
1027 | |
1028 | #define MLX5_CAP_ATOMIC(mdev, cap) \ | |
701052c5 | 1029 | MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap) |
938fe83c SM |
1030 | |
1031 | #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ | |
701052c5 | 1032 | MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap) |
938fe83c SM |
1033 | |
1034 | #define MLX5_CAP_FLOWTABLE(mdev, cap) \ | |
701052c5 | 1035 | MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap) |
938fe83c SM |
1036 | |
1037 | #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ | |
701052c5 | 1038 | MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap) |
938fe83c | 1039 | |
876d634d MG |
1040 | #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ |
1041 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) | |
1042 | ||
1043 | #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ | |
1044 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) | |
1045 | ||
cea824d4 MG |
1046 | #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ |
1047 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) | |
1048 | ||
1049 | #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ | |
1050 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) | |
1051 | ||
1052 | #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ | |
1053 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) | |
1054 | ||
1055 | #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ | |
1056 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) | |
1057 | ||
495716b1 SM |
1058 | #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ |
1059 | MLX5_GET(flow_table_eswitch_cap, \ | |
701052c5 | 1060 | mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) |
495716b1 SM |
1061 | |
1062 | #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ | |
1063 | MLX5_GET(flow_table_eswitch_cap, \ | |
701052c5 | 1064 | mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) |
495716b1 SM |
1065 | |
1066 | #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ | |
1067 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) | |
1068 | ||
1069 | #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ | |
1070 | MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) | |
1071 | ||
efdc810b MHY |
1072 | #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ |
1073 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) | |
1074 | ||
1075 | #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ | |
1076 | MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) | |
1077 | ||
1078 | #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ | |
1079 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) | |
1080 | ||
1081 | #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ | |
1082 | MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) | |
1083 | ||
d6666753 SM |
1084 | #define MLX5_CAP_ESW(mdev, cap) \ |
1085 | MLX5_GET(e_switch_cap, \ | |
701052c5 | 1086 | mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap) |
d6666753 SM |
1087 | |
1088 | #define MLX5_CAP_ESW_MAX(mdev, cap) \ | |
1089 | MLX5_GET(e_switch_cap, \ | |
701052c5 | 1090 | mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap) |
d6666753 | 1091 | |
938fe83c | 1092 | #define MLX5_CAP_ODP(mdev, cap)\ |
701052c5 | 1093 | MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap) |
938fe83c | 1094 | |
3f0393a5 SG |
1095 | #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ |
1096 | MLX5_GET(vector_calc_cap, \ | |
701052c5 | 1097 | mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap) |
3f0393a5 | 1098 | |
1466cc5b | 1099 | #define MLX5_CAP_QOS(mdev, cap)\ |
701052c5 | 1100 | MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap) |
1466cc5b | 1101 | |
71862561 GP |
1102 | #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ |
1103 | MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) | |
1104 | ||
0ab87743 OG |
1105 | #define MLX5_CAP_MCAM_REG(mdev, reg) \ |
1106 | MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) | |
1107 | ||
71862561 GP |
1108 | #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ |
1109 | MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) | |
1110 | ||
e29341fb | 1111 | #define MLX5_CAP_FPGA(mdev, cap) \ |
99d3cd27 | 1112 | MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) |
e29341fb | 1113 | |
a9956d35 | 1114 | #define MLX5_CAP64_FPGA(mdev, cap) \ |
99d3cd27 | 1115 | MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) |
a9956d35 | 1116 | |
f62b8bb8 AV |
1117 | enum { |
1118 | MLX5_CMD_STAT_OK = 0x0, | |
1119 | MLX5_CMD_STAT_INT_ERR = 0x1, | |
1120 | MLX5_CMD_STAT_BAD_OP_ERR = 0x2, | |
1121 | MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, | |
1122 | MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, | |
1123 | MLX5_CMD_STAT_BAD_RES_ERR = 0x5, | |
1124 | MLX5_CMD_STAT_RES_BUSY = 0x6, | |
1125 | MLX5_CMD_STAT_LIM_ERR = 0x8, | |
1126 | MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, | |
1127 | MLX5_CMD_STAT_IX_ERR = 0xa, | |
1128 | MLX5_CMD_STAT_NO_RES_ERR = 0xf, | |
1129 | MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, | |
1130 | MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, | |
1131 | MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, | |
1132 | MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, | |
1133 | MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, | |
1134 | }; | |
1135 | ||
efea389d GP |
1136 | enum { |
1137 | MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, | |
1138 | MLX5_RFC_2863_COUNTERS_GROUP = 0x1, | |
1139 | MLX5_RFC_2819_COUNTERS_GROUP = 0x2, | |
1140 | MLX5_RFC_3635_COUNTERS_GROUP = 0x3, | |
1141 | MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, | |
1142 | MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, | |
1c64bf6f | 1143 | MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, |
121fcdc8 | 1144 | MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, |
d8dc0508 | 1145 | MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, |
1c64bf6f | 1146 | MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, |
efea389d GP |
1147 | }; |
1148 | ||
8ed1a630 GP |
1149 | enum { |
1150 | MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, | |
1151 | }; | |
1152 | ||
707c4602 MD |
1153 | static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) |
1154 | { | |
1155 | if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) | |
1156 | return 0; | |
1157 | return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; | |
1158 | } | |
1159 | ||
35d19011 MG |
1160 | #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 |
1161 | #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 | |
1162 | #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 | |
1163 | #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ | |
1164 | MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ | |
1165 | MLX5_BY_PASS_NUM_MULTICAST_PRIOS) | |
4cbdd30e | 1166 | |
e126ba97 | 1167 | #endif /* MLX5_DEVICE_H */ |