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net/mlx5: Fix race for multiple RoCE enable
[linux-block.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
667cb65a 51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
71c70eb2 52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
d29b796a
EC		 53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
71c70eb2 55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
d29b796a
EC		 56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
71c70eb2
HN		 59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
d29b796a
EC		 61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
9218b44d 66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
938fe83c
SM		 67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72/* insert a value to a struct */
73#define MLX5_SET(typ, p, fld, v) do { \
a61d5ce9 74 u32 _v = v; \
d29b796a
EC		 75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
a61d5ce9 78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
d29b796a
EC		 79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
e281682b
SM		 82#define MLX5_SET_TO_ONES(typ, p, fld) do { \
83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
84 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
85 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
86 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
87 << __mlx5_dw_bit_off(typ, fld))); \
88} while (0)
89
d29b796a
EC		 90#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
91__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
92__mlx5_mask(typ, fld))
93
94#define MLX5_GET_PR(typ, p, fld) ({ \
95 u32 ___t = MLX5_GET(typ, p, fld); \
96 pr_debug(#fld " = 0x%x\n", ___t); \
97 ___t; \
98})
99
b8a4ddb2 100#define __MLX5_SET64(typ, p, fld, v) do { \
d29b796a 101 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
d29b796a
EC		 102 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
103} while (0)
104
b8a4ddb2
TH		 105#define MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
107 __MLX5_SET64(typ, p, fld, v); \
108} while (0)
109
110#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld[idx], v); \
113} while (0)
114
d29b796a
EC		 115#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
116
707c4602
MD		 117#define MLX5_GET64_PR(typ, p, fld) ({ \
118 u64 ___t = MLX5_GET64(typ, p, fld); \
119 pr_debug(#fld " = 0x%llx\n", ___t); \
120 ___t; \
121})
122
71c70eb2
HN		 123#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
124__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
125__mlx5_mask16(typ, fld))
126
127#define MLX5_SET16(typ, p, fld, v) do { \
128 u16 _v = v; \
129 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
130 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
131 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
132 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
133 << __mlx5_16_bit_off(typ, fld))); \
134} while (0)
135
3efd9a11
MY		 136/* Big endian getters */
137#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
138 __mlx5_64_off(typ, fld)))
139
140#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
141 type_t tmp; \
142 switch (sizeof(tmp)) { \
143 case sizeof(u8): \
144 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
145 break; \
146 case sizeof(u16): \
147 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
148 break; \
149 case sizeof(u32): \
150 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
151 break; \
152 case sizeof(u64): \
153 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
154 break; \
155 } \
156 tmp; \
157 })
158
ae76715d
HHZ		 159enum mlx5_inline_modes {
160 MLX5_INLINE_MODE_NONE,
161 MLX5_INLINE_MODE_L2,
162 MLX5_INLINE_MODE_IP,
163 MLX5_INLINE_MODE_TCP_UDP,
164};
165
e126ba97
EC		 166enum {
167 MLX5_MAX_COMMANDS = 32,
168 MLX5_CMD_DATA_BLOCK_SIZE = 512,
169 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 170 MLX5_MKEY_BSF_OCTO_SIZE = 4,
171 MLX5_MAX_PSVS = 4,
e126ba97
EC		 172};
173
174enum {
175 MLX5_EXTENDED_UD_AV = 0x80000000,
176};
177
178enum {
179 MLX5_CQ_STATE_ARMED = 9,
180 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
181 MLX5_CQ_STATE_FIRED = 0xa,
182};
183
184enum {
185 MLX5_STAT_RATE_OFFSET = 5,
186};
187
188enum {
189 MLX5_INLINE_SEG = 0x80000000,
190};
191
fc11fbf9
SM		 192enum {
193 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
194};
195
c7a08ac7
EC		 196enum {
197 MLX5_MIN_PKEY_TABLE_SIZE = 128,
198 MLX5_MAX_LOG_PKEY_TABLE = 5,
199};
200
e420f0c0
HE		 201enum {
202 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
203};
204
205enum {
206 MLX5_PFAULT_SUBTYPE_WQE = 0,
207 MLX5_PFAULT_SUBTYPE_RDMA = 1,
208};
209
e126ba97
EC		 210enum {
211 MLX5_PERM_LOCAL_READ = 1 << 2,
212 MLX5_PERM_LOCAL_WRITE = 1 << 3,
213 MLX5_PERM_REMOTE_READ = 1 << 4,
214 MLX5_PERM_REMOTE_WRITE = 1 << 5,
215 MLX5_PERM_ATOMIC = 1 << 6,
216 MLX5_PERM_UMR_EN = 1 << 7,
217};
218
219enum {
220 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
221 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
222 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
223 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
224 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
225};
226
e126ba97
EC		 227enum {
228 MLX5_EN_RD = (u64)1,
229 MLX5_EN_WR = (u64)2
230};
231
232enum {
b037c29a
EC		 233 MLX5_ADAPTER_PAGE_SHIFT = 12,
234 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
235};
236
e126ba97 237enum {
2f5ff264
EC		 238 MLX5_BFREGS_PER_UAR = 4,
239 MLX5_MAX_UARS = 1 << 8,
240 MLX5_NON_FP_BFREGS_PER_UAR = 2,
a6d51b68
EC		 241 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
242 MLX5_NON_FP_BFREGS_PER_UAR,
2f5ff264
EC		 243 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
244 MLX5_NON_FP_BFREGS_PER_UAR,
b037c29a
EC		 245 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
246 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
31a78a5a
YH		 247 MLX5_MIN_DYN_BFREGS = 512,
248 MLX5_MAX_DYN_BFREGS = 1024,
e126ba97
EC		 249};
250
251enum {
252 MLX5_MKEY_MASK_LEN = 1ull << 0,
253 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
254 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
255 MLX5_MKEY_MASK_PD = 1ull << 7,
256 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 257 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 258 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
259 MLX5_MKEY_MASK_KEY = 1ull << 13,
260 MLX5_MKEY_MASK_QPN = 1ull << 14,
261 MLX5_MKEY_MASK_LR = 1ull << 17,
262 MLX5_MKEY_MASK_LW = 1ull << 18,
263 MLX5_MKEY_MASK_RR = 1ull << 19,
264 MLX5_MKEY_MASK_RW = 1ull << 20,
265 MLX5_MKEY_MASK_A = 1ull << 21,
266 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
267 MLX5_MKEY_MASK_FREE = 1ull << 29,
268};
269
968e78dd
HE		 270enum {
271 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
272
273 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
274 MLX5_UMR_CHECK_FREE = (2 << 5),
275
276 MLX5_UMR_INLINE = (1 << 7),
277};
278
cc149f75
HE		 279#define MLX5_UMR_MTT_ALIGNMENT 0x40
280#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 281#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 282
e2013b21 283#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
284
285enum {
286 MLX5_EVENT_QUEUE_TYPE_QP = 0,
287 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
288 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
57cda166 289 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
e2013b21 290};
291
e126ba97
EC		 292enum mlx5_event {
293 MLX5_EVENT_TYPE_COMP = 0x0,
294
295 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
296 MLX5_EVENT_TYPE_COMM_EST = 0x02,
297 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
298 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
299 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
300
301 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
302 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
303 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
304 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
305 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
306 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
307
308 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
309 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
310 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
4ce3bf2f 311 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
e126ba97 312 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
246ac981 313 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
f9a1ef72 314 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
e126ba97
EC		 315
316 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
317 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
318
319 MLX5_EVENT_TYPE_CMD = 0x0a,
320 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 321
322 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
073bb189 323 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
e29341fb 324
57cda166
MS		 325 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
326
e29341fb 327 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
e126ba97
EC		 328};
329
246ac981
MG		 330enum {
331 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
332};
333
e126ba97
EC		 334enum {
335 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
336 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
337 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
338 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
339 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
340 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
341 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
342};
343
344enum {
e126ba97 345 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 346 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
347 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
348 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
349 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 350 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 351 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 352 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 353 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 354 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 355 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 356 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 357};
358
3cca2606
AS		 359enum {
360 MLX5_ROCE_VERSION_1 = 0,
361 MLX5_ROCE_VERSION_2 = 2,
362};
363
364enum {
365 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
366 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
367};
368
369enum {
370 MLX5_ROCE_L3_TYPE_IPV4 = 0,
371 MLX5_ROCE_L3_TYPE_IPV6 = 1,
372};
373
374enum {
375 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
376 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
377};
378
e126ba97
EC		 379enum {
380 MLX5_OPCODE_NOP = 0x00,
381 MLX5_OPCODE_SEND_INVAL = 0x01,
382 MLX5_OPCODE_RDMA_WRITE = 0x08,
383 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
384 MLX5_OPCODE_SEND = 0x0a,
385 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 386 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 387 MLX5_OPCODE_RDMA_READ = 0x10,
388 MLX5_OPCODE_ATOMIC_CS = 0x11,
389 MLX5_OPCODE_ATOMIC_FA = 0x12,
390 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
391 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
392 MLX5_OPCODE_BIND_MW = 0x18,
393 MLX5_OPCODE_CONFIG_CMD = 0x1f,
394
395 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
396 MLX5_RECV_OPCODE_SEND = 0x01,
397 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
398 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
399
400 MLX5_CQE_OPCODE_ERROR = 0x1e,
401 MLX5_CQE_OPCODE_RESIZE = 0x16,
402
403 MLX5_OPCODE_SET_PSV = 0x20,
404 MLX5_OPCODE_GET_PSV = 0x21,
405 MLX5_OPCODE_CHECK_PSV = 0x22,
406 MLX5_OPCODE_RGET_PSV = 0x26,
407 MLX5_OPCODE_RCHECK_PSV = 0x27,
408
409 MLX5_OPCODE_UMR = 0x25,
410
411};
412
413enum {
414 MLX5_SET_PORT_RESET_QKEY = 0,
415 MLX5_SET_PORT_GUID0 = 16,
416 MLX5_SET_PORT_NODE_GUID = 17,
417 MLX5_SET_PORT_SYS_GUID = 18,
418 MLX5_SET_PORT_GID_TABLE = 19,
419 MLX5_SET_PORT_PKEY_TABLE = 20,
420};
421
d8880795
TT		 422enum {
423 MLX5_BW_NO_LIMIT = 0,
424 MLX5_100_MBPS_UNIT = 3,
425 MLX5_GBPS_UNIT = 4,
426};
427
e126ba97
EC		 428enum {
429 MLX5_MAX_PAGE_SHIFT = 31
430};
431
87b8de49 432enum {
87b8de49
EC		 433 MLX5_CAP_OFF_CMDIF_CSUM = 46,
434};
435
986ef95e
SG		 436enum {
437 /*
438 * Max wqe size for rdma read is 512 bytes, so this
439 * limits our max_sge_rd as the wqe needs to fit:
440 * - ctrl segment (16 bytes)
441 * - rdma segment (16 bytes)
442 * - scatter elements (16 bytes each)
443 */
444 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
445};
446
e420f0c0
HE		 447enum mlx5_odp_transport_cap_bits {
448 MLX5_ODP_SUPPORT_SEND = 1 << 31,
449 MLX5_ODP_SUPPORT_RECV = 1 << 30,
450 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
451 MLX5_ODP_SUPPORT_READ = 1 << 28,
452};
453
454struct mlx5_odp_caps {
455 char reserved[0x10];
456 struct {
457 __be32 rc_odp_caps;
458 __be32 uc_odp_caps;
459 __be32 ud_odp_caps;
460 } per_transport_caps;
461 char reserved2[0xe4];
462};
463
e126ba97
EC		 464struct mlx5_cmd_layout {
465 u8 type;
466 u8 rsvd0[3];
467 __be32 inlen;
468 __be64 in_ptr;
469 __be32 in[4];
470 __be32 out[4];
471 __be64 out_ptr;
472 __be32 outlen;
473 u8 token;
474 u8 sig;
475 u8 rsvd1;
476 u8 status_own;
477};
478
e126ba97
EC		 479struct health_buffer {
480 __be32 assert_var[5];
481 __be32 rsvd0[3];
482 __be32 assert_exit_ptr;
483 __be32 assert_callra;
484 __be32 rsvd1[2];
485 __be32 fw_ver;
486 __be32 hw_id;
487 __be32 rsvd2;
488 u8 irisc_index;
489 u8 synd;
78ccb258 490 __be16 ext_synd;
e126ba97
EC		 491};
492
493struct mlx5_init_seg {
494 __be32 fw_rev;
495 __be32 cmdif_rev_fw_sub;
496 __be32 rsvd0[2];
497 __be32 cmdq_addr_h;
498 __be32 cmdq_addr_l_sz;
499 __be32 cmd_dbell;
e3297246
EC		 500 __be32 rsvd1[120];
501 __be32 initializing;
e126ba97 502 struct health_buffer health;
b0844444
EBE		 503 __be32 rsvd2[880];
504 __be32 internal_timer_h;
505 __be32 internal_timer_l;
b368d7cb 506 __be32 rsvd3[2];
e126ba97 507 __be32 health_counter;
b0844444 508 __be32 rsvd4[1019];
e126ba97
EC		 509 __be64 ieee1588_clk;
510 __be32 ieee1588_clk_type;
511 __be32 clr_intx;
512};
513
514struct mlx5_eqe_comp {
515 __be32 reserved[6];
516 __be32 cqn;
517};
518
519struct mlx5_eqe_qp_srq {
e2013b21 520 __be32 reserved1[5];
521 u8 type;
522 u8 reserved2[3];
e126ba97
EC		 523 __be32 qp_srq_n;
524};
525
526struct mlx5_eqe_cq_err {
527 __be32 cqn;
528 u8 reserved1[7];
529 u8 syndrome;
530};
531
e126ba97
EC		 532struct mlx5_eqe_port_state {
533 u8 reserved0[8];
534 u8 port;
535};
536
537struct mlx5_eqe_gpio {
538 __be32 reserved0[2];
539 __be64 gpio_event;
540};
541
542struct mlx5_eqe_congestion {
543 u8 type;
544 u8 rsvd0;
545 u8 congestion_level;
546};
547
548struct mlx5_eqe_stall_vl {
549 u8 rsvd0[3];
550 u8 port_vl;
551};
552
553struct mlx5_eqe_cmd {
554 __be32 vector;
555 __be32 rsvd[6];
556};
557
558struct mlx5_eqe_page_req {
559 u8 rsvd0[2];
560 __be16 func_id;
0a324f31
ML		 561 __be32 num_pages;
562 __be32 rsvd1[5];
e126ba97
EC		 563};
564
e420f0c0
HE		 565struct mlx5_eqe_page_fault {
566 __be32 bytes_committed;
567 union {
568 struct {
569 u16 reserved1;
570 __be16 wqe_index;
571 u16 reserved2;
572 __be16 packet_length;
d9aaed83
AK		 573 __be32 token;
574 u8 reserved4[8];
575 __be32 pftype_wq;
e420f0c0
HE		 576 } __packed wqe;
577 struct {
578 __be32 r_key;
579 u16 reserved1;
580 __be16 packet_length;
581 __be32 rdma_op_len;
582 __be64 rdma_va;
d9aaed83 583 __be32 pftype_token;
e420f0c0
HE		 584 } __packed rdma;
585 } __packed;
e420f0c0
HE		 586} __packed;
587
073bb189
SM		 588struct mlx5_eqe_vport_change {
589 u8 rsvd0[2];
590 __be16 vport_num;
591 __be32 rsvd1[6];
592} __packed;
593
4ce3bf2f
HN		 594struct mlx5_eqe_port_module {
595 u8 reserved_at_0[1];
596 u8 module;
597 u8 reserved_at_2[1];
598 u8 module_status;
599 u8 reserved_at_4[2];
600 u8 error_type;
601} __packed;
602
f9a1ef72
EE		 603struct mlx5_eqe_pps {
604 u8 rsvd0[3];
605 u8 pin;
606 u8 rsvd1[4];
607 union {
608 struct {
609 __be32 time_sec;
610 __be32 time_nsec;
611 };
612 struct {
613 __be64 time_stamp;
614 };
615 };
616 u8 rsvd2[12];
617} __packed;
618
57cda166
MS		 619struct mlx5_eqe_dct {
620 __be32 reserved[6];
621 __be32 dctn;
622};
623
e126ba97
EC		 624union ev_data {
625 __be32 raw[7];
626 struct mlx5_eqe_cmd cmd;
627 struct mlx5_eqe_comp comp;
628 struct mlx5_eqe_qp_srq qp_srq;
629 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 630 struct mlx5_eqe_port_state port;
631 struct mlx5_eqe_gpio gpio;
632 struct mlx5_eqe_congestion cong;
633 struct mlx5_eqe_stall_vl stall_vl;
634 struct mlx5_eqe_page_req req_pages;
e420f0c0 635 struct mlx5_eqe_page_fault page_fault;
073bb189 636 struct mlx5_eqe_vport_change vport_change;
4ce3bf2f 637 struct mlx5_eqe_port_module port_module;
f9a1ef72 638 struct mlx5_eqe_pps pps;
57cda166 639 struct mlx5_eqe_dct dct;
e126ba97
EC		 640} __packed;
641
642struct mlx5_eqe {
643 u8 rsvd0;
644 u8 type;
645 u8 rsvd1;
646 u8 sub_type;
647 __be32 rsvd2[7];
648 union ev_data data;
649 __be16 rsvd3;
650 u8 signature;
651 u8 owner;
652} __packed;
653
654struct mlx5_cmd_prot_block {
655 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
656 u8 rsvd0[48];
657 __be64 next;
658 __be32 block_num;
659 u8 rsvd1;
660 u8 token;
661 u8 ctrl_sig;
662 u8 sig;
663};
664
e281682b
SM		 665enum {
666 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
667};
668
e126ba97
EC		 669struct mlx5_err_cqe {
670 u8 rsvd0[32];
671 __be32 srqn;
672 u8 rsvd1[18];
673 u8 vendor_err_synd;
674 u8 syndrome;
675 __be32 s_wqe_opcode_qpn;
676 __be16 wqe_counter;
677 u8 signature;
678 u8 op_own;
679};
680
681struct mlx5_cqe64 {
1b223dd3
SM		 682 u8 outer_l3_tunneled;
683 u8 rsvd0;
684 __be16 wqe_id;
e281682b
SM		 685 u8 lro_tcppsh_abort_dupack;
686 u8 lro_min_ttl;
687 __be16 lro_tcp_win;
688 __be32 lro_ack_seq_num;
689 __be32 rss_hash_result;
690 u8 rss_hash_type;
e126ba97 691 u8 ml_path;
e281682b
SM		 692 u8 rsvd20[2];
693 __be16 check_sum;
e126ba97
EC		 694 __be16 slid;
695 __be32 flags_rqpn;
e281682b 696 u8 hds_ip_ext;
1b223dd3 697 u8 l4_l3_hdr_type;
e281682b
SM		 698 __be16 vlan_info;
699 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 700 __be32 imm_inval_pkey;
701 u8 rsvd40[4];
702 __be32 byte_cnt;
b0844444
EBE		 703 __be32 timestamp_h;
704 __be32 timestamp_l;
e126ba97
EC		 705 __be32 sop_drop_qpn;
706 __be16 wqe_counter;
707 u8 signature;
708 u8 op_own;
709};
710
7219ab34
TT		 711struct mlx5_mini_cqe8 {
712 union {
713 __be32 rx_hash_result;
714 struct {
715 __be16 checksum;
716 __be16 rsvd;
717 };
718 struct {
719 __be16 wqe_counter;
720 u8 s_wqe_opcode;
721 u8 reserved;
722 } s_wqe_info;
723 };
724 __be32 byte_cnt;
725};
726
727enum {
728 MLX5_NO_INLINE_DATA,
729 MLX5_INLINE_DATA32_SEG,
730 MLX5_INLINE_DATA64_SEG,
731 MLX5_COMPRESSED,
732};
733
734enum {
735 MLX5_CQE_FORMAT_CSUM = 0x1,
736};
737
738#define MLX5_MINI_CQE_ARRAY_SIZE 8
739
740static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
741{
742 return (cqe->op_own >> 2) & 0x3;
743}
744
604acb19 745static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
e281682b
SM		 746{
747 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
748}
749
750static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
751{
1b223dd3
SM		 752 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
753}
754
755static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
756{
757 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
758}
759
760static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
761{
762 return cqe->outer_l3_tunneled & 0x1;
e281682b
SM		 763}
764
765static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
766{
1b223dd3 767 return !!(cqe->l4_l3_hdr_type & 0x1);
e281682b
SM		 768}
769
b0844444
EBE		 770static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
771{
772 u32 hi, lo;
773
774 hi = be32_to_cpu(cqe->timestamp_h);
775 lo = be32_to_cpu(cqe->timestamp_l);
776
777 return (u64)lo | ((u64)hi << 32);
778}
779
461017cb
TT		 780struct mpwrq_cqe_bc {
781 __be16 filler_consumed_strides;
782 __be16 byte_cnt;
783};
784
785static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
786{
787 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
788
789 return be16_to_cpu(bc->byte_cnt);
790}
791
792static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
793{
794 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
795}
796
797static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
798{
799 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
800
801 return mpwrq_get_cqe_bc_consumed_strides(bc);
802}
803
804static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
805{
806 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
807
808 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
809}
810
811static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
812{
813 return be16_to_cpu(cqe->wqe_counter);
814}
815
e281682b
SM		 816enum {
817 CQE_L4_HDR_TYPE_NONE = 0x0,
818 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
819 CQE_L4_HDR_TYPE_UDP = 0x2,
820 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
821 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
822};
823
824enum {
12e8b570
JDB		 825 CQE_RSS_HTYPE_IP = 0x3 << 2,
826 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
827 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
828 */
829 CQE_RSS_HTYPE_L4 = 0x3 << 6,
830 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
831 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
832 */
e281682b
SM		 833};
834
cb34be6d
AS		 835enum {
836 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
837 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
838 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
839};
840
e281682b
SM		 841enum {
842 CQE_L2_OK = 1 << 0,
843 CQE_L3_OK = 1 << 1,
844 CQE_L4_OK = 1 << 2,
845};
846
d5436ba0
SG		 847struct mlx5_sig_err_cqe {
848 u8 rsvd0[16];
849 __be32 expected_trans_sig;
850 __be32 actual_trans_sig;
851 __be32 expected_reftag;
852 __be32 actual_reftag;
853 __be16 syndrome;
854 u8 rsvd22[2];
855 __be32 mkey;
856 __be64 err_offset;
857 u8 rsvd30[8];
858 __be32 qpn;
859 u8 rsvd38[2];
860 u8 signature;
861 u8 op_own;
862};
863
e126ba97
EC		 864struct mlx5_wqe_srq_next_seg {
865 u8 rsvd0[2];
866 __be16 next_wqe_index;
867 u8 signature;
868 u8 rsvd1[11];
869};
870
871union mlx5_ext_cqe {
872 struct ib_grh grh;
873 u8 inl[64];
874};
875
876struct mlx5_cqe128 {
877 union mlx5_ext_cqe inl_grh;
878 struct mlx5_cqe64 cqe64;
879};
880
968e78dd
HE		 881enum {
882 MLX5_MKEY_STATUS_FREE = 1 << 6,
883};
884
ec22eb53
SM		 885enum {
886 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
887 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
888 MLX5_MKEY_BSF_EN = 1 << 30,
889 MLX5_MKEY_LEN64 = 1 << 31,
890};
891
e126ba97
EC		 892struct mlx5_mkey_seg {
893 /* This is a two bit field occupying bits 31-30.
894 * bit 31 is always 0,
895 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
896 */
897 u8 status;
898 u8 pcie_control;
899 u8 flags;
900 u8 version;
901 __be32 qpn_mkey7_0;
902 u8 rsvd1[4];
903 __be32 flags_pd;
904 __be64 start_addr;
905 __be64 len;
906 __be32 bsfs_octo_size;
907 u8 rsvd2[16];
908 __be32 xlt_oct_size;
909 u8 rsvd3[3];
910 u8 log2_page_size;
911 u8 rsvd4[4];
912};
913
e126ba97
EC		 914#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
915
916enum {
917 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
918};
919
e281682b
SM		 920enum {
921 VPORT_STATE_DOWN = 0x0,
922 VPORT_STATE_UP = 0x1,
923};
924
81848731
SM		 925enum {
926 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
927 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
928 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
929};
930
e281682b
SM		 931enum {
932 MLX5_L3_PROT_TYPE_IPV4 = 0,
933 MLX5_L3_PROT_TYPE_IPV6 = 1,
934};
935
936enum {
937 MLX5_L4_PROT_TYPE_TCP = 0,
938 MLX5_L4_PROT_TYPE_UDP = 1,
939};
940
941enum {
942 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
943 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
944 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
945 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
946 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
947};
948
949enum {
950 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
951 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
952 MLX5_MATCH_INNER_HEADERS = 1 << 2,
953
954};
955
956enum {
957 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
958 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
959};
960
961enum {
962 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
963 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
964 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
965};
966
e16aea27
SM		 967enum mlx5_list_type {
968 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
969 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
970 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
971};
972
e281682b
SM		 973enum {
974 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
975 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
976};
977
928cfe87
TT		 978enum mlx5_wol_mode {
979 MLX5_WOL_DISABLE = 0,
980 MLX5_WOL_SECURED_MAGIC = 1 << 1,
981 MLX5_WOL_MAGIC = 1 << 2,
982 MLX5_WOL_ARP = 1 << 3,
983 MLX5_WOL_BROADCAST = 1 << 4,
984 MLX5_WOL_MULTICAST = 1 << 5,
985 MLX5_WOL_UNICAST = 1 << 6,
986 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
987};
988
938fe83c
SM		 989/* MLX5 DEV CAPs */
990
991/* TODO: EAT.ME */
992enum mlx5_cap_mode {
993 HCA_CAP_OPMOD_GET_MAX = 0,
994 HCA_CAP_OPMOD_GET_CUR = 1,
995};
996
997enum mlx5_cap_type {
998 MLX5_CAP_GENERAL = 0,
999 MLX5_CAP_ETHERNET_OFFLOADS,
1000 MLX5_CAP_ODP,
1001 MLX5_CAP_ATOMIC,
1002 MLX5_CAP_ROCE,
1003 MLX5_CAP_IPOIB_OFFLOADS,
4ce749bd 1004 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
938fe83c 1005 MLX5_CAP_FLOW_TABLE,
495716b1 1006 MLX5_CAP_ESWITCH_FLOW_TABLE,
d6666753 1007 MLX5_CAP_ESWITCH,
3f0393a5
SG		 1008 MLX5_CAP_RESERVED,
1009 MLX5_CAP_VECTOR_CALC,
1466cc5b 1010 MLX5_CAP_QOS,
938fe83c
SM		 1011 /* NUM OF CAP Types */
1012 MLX5_CAP_NUM
1013};
1014
cfdcbcea
GP		 1015enum mlx5_pcam_reg_groups {
1016 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1017};
1018
1019enum mlx5_pcam_feature_groups {
1020 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1021};
1022
1023enum mlx5_mcam_reg_groups {
1024 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1025};
1026
1027enum mlx5_mcam_feature_groups {
1028 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1029};
1030
c02762eb
HN		 1031enum mlx5_qcam_reg_groups {
1032 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1033};
1034
1035enum mlx5_qcam_feature_groups {
1036 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1037};
1038
938fe83c
SM		 1039/* GET Dev Caps macros */
1040#define MLX5_CAP_GEN(mdev, cap) \
701052c5 1041 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
938fe83c
SM		 1042
1043#define MLX5_CAP_GEN_MAX(mdev, cap) \
701052c5 1044 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
938fe83c
SM		 1045
1046#define MLX5_CAP_ETH(mdev, cap) \
1047 MLX5_GET(per_protocol_networking_offload_caps,\
701052c5 1048 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
938fe83c
SM		 1049
1050#define MLX5_CAP_ETH_MAX(mdev, cap) \
1051 MLX5_GET(per_protocol_networking_offload_caps,\
701052c5 1052 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
938fe83c 1053
4ce749bd
YH		 1054#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1055 MLX5_GET(per_protocol_networking_offload_caps,\
1056 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1057
938fe83c 1058#define MLX5_CAP_ROCE(mdev, cap) \
701052c5 1059 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
938fe83c
SM		 1060
1061#define MLX5_CAP_ROCE_MAX(mdev, cap) \
701052c5 1062 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
938fe83c
SM		 1063
1064#define MLX5_CAP_ATOMIC(mdev, cap) \
701052c5 1065 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
938fe83c
SM		 1066
1067#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
701052c5 1068 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
938fe83c
SM		 1069
1070#define MLX5_CAP_FLOWTABLE(mdev, cap) \
701052c5 1071 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
938fe83c
SM		 1072
1073#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
701052c5 1074 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
938fe83c 1075
876d634d
MG		 1076#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1077 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1078
1079#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1080 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1081
cea824d4
MG		 1082#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1083 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1084
1085#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1086 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1087
1088#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1089 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1090
1091#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1092 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1093
495716b1
SM		 1094#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1095 MLX5_GET(flow_table_eswitch_cap, \
701052c5 1096 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
495716b1
SM		 1097
1098#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1099 MLX5_GET(flow_table_eswitch_cap, \
701052c5 1100 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
495716b1
SM		 1101
1102#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1103 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1104
1105#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1106 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1107
efdc810b
MHY		 1108#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1109 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1110
1111#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1112 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1113
1114#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1115 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1116
1117#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1118 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1119
d6666753
SM		 1120#define MLX5_CAP_ESW(mdev, cap) \
1121 MLX5_GET(e_switch_cap, \
701052c5 1122 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
d6666753
SM		 1123
1124#define MLX5_CAP_ESW_MAX(mdev, cap) \
1125 MLX5_GET(e_switch_cap, \
701052c5 1126 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
d6666753 1127
938fe83c 1128#define MLX5_CAP_ODP(mdev, cap)\
701052c5 1129 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
938fe83c 1130
3f0393a5
SG		 1131#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1132 MLX5_GET(vector_calc_cap, \
701052c5 1133 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
3f0393a5 1134
1466cc5b 1135#define MLX5_CAP_QOS(mdev, cap)\
701052c5 1136 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1466cc5b 1137
71862561
GP		 1138#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1139 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1140
0ab87743
OG		 1141#define MLX5_CAP_MCAM_REG(mdev, reg) \
1142 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1143
71862561
GP		 1144#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1145 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1146
c02762eb
HN		 1147#define MLX5_CAP_QCAM_REG(mdev, fld) \
1148 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1149
1150#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1151 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1152
e29341fb 1153#define MLX5_CAP_FPGA(mdev, cap) \
99d3cd27 1154 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
e29341fb 1155
a9956d35 1156#define MLX5_CAP64_FPGA(mdev, cap) \
99d3cd27 1157 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
a9956d35 1158
f62b8bb8
AV		 1159enum {
1160 MLX5_CMD_STAT_OK = 0x0,
1161 MLX5_CMD_STAT_INT_ERR = 0x1,
1162 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1163 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1164 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1165 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1166 MLX5_CMD_STAT_RES_BUSY = 0x6,
1167 MLX5_CMD_STAT_LIM_ERR = 0x8,
1168 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1169 MLX5_CMD_STAT_IX_ERR = 0xa,
1170 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1171 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1172 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1173 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1174 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1175 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1176};
1177
efea389d
GP		 1178enum {
1179 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1180 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1181 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1182 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1183 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1184 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1c64bf6f 1185 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
121fcdc8 1186 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
d8dc0508 1187 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1c64bf6f 1188 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
efea389d
GP		 1189};
1190
8ed1a630
GP		 1191enum {
1192 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1193};
1194
707c4602
MD		 1195static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1196{
1197 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1198 return 0;
1199 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1200}
1201
35d19011
MG		 1202#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1203#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1204#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1205#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1206 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1207 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
4cbdd30e 1208
e126ba97 1209#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)