Commit | Line | Data |
---|---|---|
e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DEVICE_H | |
34 | #define MLX5_DEVICE_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <rdma/ib_verbs.h> | |
e281682b | 38 | #include <linux/mlx5/mlx5_ifc.h> |
e126ba97 EC |
39 | |
40 | #if defined(__LITTLE_ENDIAN) | |
41 | #define MLX5_SET_HOST_ENDIANNESS 0 | |
42 | #elif defined(__BIG_ENDIAN) | |
43 | #define MLX5_SET_HOST_ENDIANNESS 0x80 | |
44 | #else | |
45 | #error Host endianness not defined | |
46 | #endif | |
47 | ||
d29b796a EC |
48 | /* helper macros */ |
49 | #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) | |
50 | #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) | |
667cb65a | 51 | #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) |
71c70eb2 | 52 | #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) |
d29b796a EC |
53 | #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) |
54 | #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) | |
71c70eb2 | 55 | #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) |
d29b796a EC |
56 | #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) |
57 | #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) | |
58 | #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) | |
71c70eb2 HN |
59 | #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) |
60 | #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) | |
d29b796a EC |
61 | #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) |
62 | ||
63 | #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) | |
64 | #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) | |
65 | #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) | |
9218b44d | 66 | #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) |
938fe83c SM |
67 | #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) |
68 | #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) | |
d29b796a | 69 | #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) |
20bbf22a | 70 | #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld))) |
d29b796a EC |
71 | |
72 | /* insert a value to a struct */ | |
73 | #define MLX5_SET(typ, p, fld, v) do { \ | |
a61d5ce9 | 74 | u32 _v = v; \ |
d29b796a EC |
75 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ |
76 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ | |
77 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ | |
a61d5ce9 | 78 | (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ |
d29b796a EC |
79 | << __mlx5_dw_bit_off(typ, fld))); \ |
80 | } while (0) | |
81 | ||
8737f818 DJ |
82 | #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \ |
83 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \ | |
84 | MLX5_SET(typ, p, fld[idx], v); \ | |
85 | } while (0) | |
86 | ||
e281682b SM |
87 | #define MLX5_SET_TO_ONES(typ, p, fld) do { \ |
88 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ | |
89 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ | |
90 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ | |
91 | (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ | |
92 | << __mlx5_dw_bit_off(typ, fld))); \ | |
93 | } while (0) | |
94 | ||
d29b796a EC |
95 | #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ |
96 | __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ | |
97 | __mlx5_mask(typ, fld)) | |
98 | ||
99 | #define MLX5_GET_PR(typ, p, fld) ({ \ | |
100 | u32 ___t = MLX5_GET(typ, p, fld); \ | |
101 | pr_debug(#fld " = 0x%x\n", ___t); \ | |
102 | ___t; \ | |
103 | }) | |
104 | ||
b8a4ddb2 | 105 | #define __MLX5_SET64(typ, p, fld, v) do { \ |
d29b796a | 106 | BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ |
d29b796a EC |
107 | *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ |
108 | } while (0) | |
109 | ||
b8a4ddb2 TH |
110 | #define MLX5_SET64(typ, p, fld, v) do { \ |
111 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ | |
112 | __MLX5_SET64(typ, p, fld, v); \ | |
113 | } while (0) | |
114 | ||
115 | #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ | |
116 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ | |
117 | __MLX5_SET64(typ, p, fld[idx], v); \ | |
118 | } while (0) | |
119 | ||
d29b796a EC |
120 | #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) |
121 | ||
707c4602 MD |
122 | #define MLX5_GET64_PR(typ, p, fld) ({ \ |
123 | u64 ___t = MLX5_GET64(typ, p, fld); \ | |
124 | pr_debug(#fld " = 0x%llx\n", ___t); \ | |
125 | ___t; \ | |
126 | }) | |
127 | ||
71c70eb2 HN |
128 | #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ |
129 | __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ | |
130 | __mlx5_mask16(typ, fld)) | |
131 | ||
132 | #define MLX5_SET16(typ, p, fld, v) do { \ | |
133 | u16 _v = v; \ | |
134 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ | |
135 | *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ | |
136 | cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ | |
137 | (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ | |
138 | << __mlx5_16_bit_off(typ, fld))); \ | |
139 | } while (0) | |
140 | ||
3efd9a11 MY |
141 | /* Big endian getters */ |
142 | #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ | |
143 | __mlx5_64_off(typ, fld))) | |
144 | ||
145 | #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ | |
146 | type_t tmp; \ | |
147 | switch (sizeof(tmp)) { \ | |
148 | case sizeof(u8): \ | |
149 | tmp = (__force type_t)MLX5_GET(typ, p, fld); \ | |
150 | break; \ | |
151 | case sizeof(u16): \ | |
152 | tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ | |
153 | break; \ | |
154 | case sizeof(u32): \ | |
155 | tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ | |
156 | break; \ | |
157 | case sizeof(u64): \ | |
158 | tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ | |
159 | break; \ | |
160 | } \ | |
161 | tmp; \ | |
162 | }) | |
163 | ||
ae76715d HHZ |
164 | enum mlx5_inline_modes { |
165 | MLX5_INLINE_MODE_NONE, | |
166 | MLX5_INLINE_MODE_L2, | |
167 | MLX5_INLINE_MODE_IP, | |
168 | MLX5_INLINE_MODE_TCP_UDP, | |
169 | }; | |
170 | ||
e126ba97 EC |
171 | enum { |
172 | MLX5_MAX_COMMANDS = 32, | |
173 | MLX5_CMD_DATA_BLOCK_SIZE = 512, | |
174 | MLX5_PCI_CMD_XPORT = 7, | |
3121e3c4 SG |
175 | MLX5_MKEY_BSF_OCTO_SIZE = 4, |
176 | MLX5_MAX_PSVS = 4, | |
e126ba97 EC |
177 | }; |
178 | ||
179 | enum { | |
180 | MLX5_EXTENDED_UD_AV = 0x80000000, | |
181 | }; | |
182 | ||
183 | enum { | |
184 | MLX5_CQ_STATE_ARMED = 9, | |
185 | MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, | |
186 | MLX5_CQ_STATE_FIRED = 0xa, | |
187 | }; | |
188 | ||
189 | enum { | |
190 | MLX5_STAT_RATE_OFFSET = 5, | |
191 | }; | |
192 | ||
193 | enum { | |
194 | MLX5_INLINE_SEG = 0x80000000, | |
195 | }; | |
196 | ||
fc11fbf9 SM |
197 | enum { |
198 | MLX5_HW_START_PADDING = MLX5_INLINE_SEG, | |
199 | }; | |
200 | ||
c7a08ac7 EC |
201 | enum { |
202 | MLX5_MIN_PKEY_TABLE_SIZE = 128, | |
203 | MLX5_MAX_LOG_PKEY_TABLE = 5, | |
204 | }; | |
205 | ||
e420f0c0 HE |
206 | enum { |
207 | MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 | |
208 | }; | |
209 | ||
210 | enum { | |
211 | MLX5_PFAULT_SUBTYPE_WQE = 0, | |
212 | MLX5_PFAULT_SUBTYPE_RDMA = 1, | |
213 | }; | |
214 | ||
c99fefea MS |
215 | enum wqe_page_fault_type { |
216 | MLX5_WQE_PF_TYPE_RMP = 0, | |
217 | MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1, | |
218 | MLX5_WQE_PF_TYPE_RESP = 2, | |
219 | MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3, | |
220 | }; | |
221 | ||
e126ba97 EC |
222 | enum { |
223 | MLX5_PERM_LOCAL_READ = 1 << 2, | |
224 | MLX5_PERM_LOCAL_WRITE = 1 << 3, | |
225 | MLX5_PERM_REMOTE_READ = 1 << 4, | |
226 | MLX5_PERM_REMOTE_WRITE = 1 << 5, | |
227 | MLX5_PERM_ATOMIC = 1 << 6, | |
228 | MLX5_PERM_UMR_EN = 1 << 7, | |
229 | }; | |
230 | ||
231 | enum { | |
232 | MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, | |
233 | MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, | |
234 | MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, | |
235 | MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, | |
236 | MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, | |
237 | }; | |
238 | ||
e126ba97 EC |
239 | enum { |
240 | MLX5_EN_RD = (u64)1, | |
241 | MLX5_EN_WR = (u64)2 | |
242 | }; | |
243 | ||
244 | enum { | |
b037c29a EC |
245 | MLX5_ADAPTER_PAGE_SHIFT = 12, |
246 | MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, | |
247 | }; | |
248 | ||
e126ba97 | 249 | enum { |
2f5ff264 EC |
250 | MLX5_BFREGS_PER_UAR = 4, |
251 | MLX5_MAX_UARS = 1 << 8, | |
252 | MLX5_NON_FP_BFREGS_PER_UAR = 2, | |
a6d51b68 EC |
253 | MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - |
254 | MLX5_NON_FP_BFREGS_PER_UAR, | |
2f5ff264 EC |
255 | MLX5_MAX_BFREGS = MLX5_MAX_UARS * |
256 | MLX5_NON_FP_BFREGS_PER_UAR, | |
b037c29a EC |
257 | MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, |
258 | MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, | |
31a78a5a YH |
259 | MLX5_MIN_DYN_BFREGS = 512, |
260 | MLX5_MAX_DYN_BFREGS = 1024, | |
e126ba97 EC |
261 | }; |
262 | ||
263 | enum { | |
264 | MLX5_MKEY_MASK_LEN = 1ull << 0, | |
265 | MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, | |
266 | MLX5_MKEY_MASK_START_ADDR = 1ull << 6, | |
267 | MLX5_MKEY_MASK_PD = 1ull << 7, | |
268 | MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, | |
d5436ba0 | 269 | MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, |
e126ba97 EC |
270 | MLX5_MKEY_MASK_BSF_EN = 1ull << 12, |
271 | MLX5_MKEY_MASK_KEY = 1ull << 13, | |
272 | MLX5_MKEY_MASK_QPN = 1ull << 14, | |
273 | MLX5_MKEY_MASK_LR = 1ull << 17, | |
274 | MLX5_MKEY_MASK_LW = 1ull << 18, | |
275 | MLX5_MKEY_MASK_RR = 1ull << 19, | |
276 | MLX5_MKEY_MASK_RW = 1ull << 20, | |
277 | MLX5_MKEY_MASK_A = 1ull << 21, | |
278 | MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, | |
896ec973 ML |
279 | MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25, |
280 | MLX5_MKEY_MASK_FREE = 1ull << 29, | |
281 | MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47, | |
e126ba97 EC |
282 | }; |
283 | ||
968e78dd HE |
284 | enum { |
285 | MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), | |
286 | ||
287 | MLX5_UMR_CHECK_NOT_FREE = (1 << 5), | |
288 | MLX5_UMR_CHECK_FREE = (2 << 5), | |
289 | ||
290 | MLX5_UMR_INLINE = (1 << 7), | |
291 | }; | |
292 | ||
cc149f75 HE |
293 | #define MLX5_UMR_MTT_ALIGNMENT 0x40 |
294 | #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) | |
832a6b06 | 295 | #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT |
cc149f75 | 296 | |
e2013b21 | 297 | #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) |
298 | ||
299 | enum { | |
300 | MLX5_EVENT_QUEUE_TYPE_QP = 0, | |
301 | MLX5_EVENT_QUEUE_TYPE_RQ = 1, | |
302 | MLX5_EVENT_QUEUE_TYPE_SQ = 2, | |
57cda166 | 303 | MLX5_EVENT_QUEUE_TYPE_DCT = 6, |
e2013b21 | 304 | }; |
305 | ||
0f597ed4 SM |
306 | /* mlx5 components can subscribe to any one of these events via |
307 | * mlx5_eq_notifier_register API. | |
308 | */ | |
e126ba97 | 309 | enum mlx5_event { |
0f597ed4 SM |
310 | /* Special value to subscribe to any event */ |
311 | MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, | |
312 | /* HW events enum start: comp events are not subscribable */ | |
e126ba97 | 313 | MLX5_EVENT_TYPE_COMP = 0x0, |
0f597ed4 | 314 | /* HW Async events enum start: subscribable events */ |
e126ba97 EC |
315 | MLX5_EVENT_TYPE_PATH_MIG = 0x01, |
316 | MLX5_EVENT_TYPE_COMM_EST = 0x02, | |
317 | MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, | |
318 | MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | |
319 | MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, | |
320 | ||
321 | MLX5_EVENT_TYPE_CQ_ERROR = 0x04, | |
322 | MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
323 | MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
324 | MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
325 | MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
326 | MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
327 | ||
328 | MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, | |
329 | MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, | |
330 | MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, | |
4ce3bf2f | 331 | MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, |
1865ea9a | 332 | MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, |
972d7560 | 333 | MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, |
e126ba97 | 334 | MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, |
246ac981 | 335 | MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22, |
fd4572b3 | 336 | MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24, |
f9a1ef72 | 337 | MLX5_EVENT_TYPE_PPS_EVENT = 0x25, |
e126ba97 EC |
338 | |
339 | MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, | |
340 | MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, | |
341 | ||
342 | MLX5_EVENT_TYPE_CMD = 0x0a, | |
343 | MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, | |
e420f0c0 HE |
344 | |
345 | MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, | |
073bb189 | 346 | MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, |
e29341fb | 347 | |
cd56f929 | 348 | MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe, |
349125ba | 349 | MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf, |
7f0d11c7 | 350 | |
57cda166 | 351 | MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, |
972d7560 | 352 | MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, |
57cda166 | 353 | |
e29341fb | 354 | MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, |
1f0cf89b | 355 | MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, |
c71ad41c FD |
356 | |
357 | MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26, | |
0f597ed4 | 358 | |
b9a7ba55 | 359 | MLX5_EVENT_TYPE_MAX = 0x100, |
c71ad41c FD |
360 | }; |
361 | ||
241dc159 AL |
362 | enum mlx5_driver_event { |
363 | MLX5_DRIVER_EVENT_TYPE_TRAP = 0, | |
364 | }; | |
365 | ||
c71ad41c FD |
366 | enum { |
367 | MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0, | |
368 | MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1, | |
e126ba97 EC |
369 | }; |
370 | ||
246ac981 MG |
371 | enum { |
372 | MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, | |
5d3c537f | 373 | MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, |
2d693567 | 374 | MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7, |
3df01077 | 375 | MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8, |
246ac981 MG |
376 | }; |
377 | ||
e126ba97 EC |
378 | enum { |
379 | MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
380 | MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, | |
381 | MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, | |
382 | MLX5_PORT_CHANGE_SUBTYPE_LID = 6, | |
383 | MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, | |
384 | MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, | |
385 | MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, | |
386 | }; | |
387 | ||
388 | enum { | |
e126ba97 | 389 | MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, |
e126ba97 EC |
390 | MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, |
391 | MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
392 | MLX5_DEV_CAP_FLAG_APM = 1LL << 17, | |
393 | MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
f360d88a | 394 | MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, |
6cb7ff3d | 395 | MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, |
3bdb31f6 | 396 | MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, |
bde51583 | 397 | MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, |
c7a08ac7 | 398 | MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, |
e126ba97 | 399 | MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, |
c1868b82 | 400 | MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, |
e126ba97 EC |
401 | }; |
402 | ||
3cca2606 AS |
403 | enum { |
404 | MLX5_ROCE_VERSION_1 = 0, | |
405 | MLX5_ROCE_VERSION_2 = 2, | |
406 | }; | |
407 | ||
408 | enum { | |
409 | MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, | |
410 | MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, | |
411 | }; | |
412 | ||
413 | enum { | |
414 | MLX5_ROCE_L3_TYPE_IPV4 = 0, | |
415 | MLX5_ROCE_L3_TYPE_IPV6 = 1, | |
416 | }; | |
417 | ||
418 | enum { | |
419 | MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, | |
420 | MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, | |
421 | }; | |
422 | ||
e126ba97 EC |
423 | enum { |
424 | MLX5_OPCODE_NOP = 0x00, | |
425 | MLX5_OPCODE_SEND_INVAL = 0x01, | |
426 | MLX5_OPCODE_RDMA_WRITE = 0x08, | |
427 | MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, | |
428 | MLX5_OPCODE_SEND = 0x0a, | |
429 | MLX5_OPCODE_SEND_IMM = 0x0b, | |
e281682b | 430 | MLX5_OPCODE_LSO = 0x0e, |
e126ba97 EC |
431 | MLX5_OPCODE_RDMA_READ = 0x10, |
432 | MLX5_OPCODE_ATOMIC_CS = 0x11, | |
433 | MLX5_OPCODE_ATOMIC_FA = 0x12, | |
434 | MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, | |
435 | MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, | |
436 | MLX5_OPCODE_BIND_MW = 0x18, | |
437 | MLX5_OPCODE_CONFIG_CMD = 0x1f, | |
5e0d2eef | 438 | MLX5_OPCODE_ENHANCED_MPSW = 0x29, |
e126ba97 EC |
439 | |
440 | MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
441 | MLX5_RECV_OPCODE_SEND = 0x01, | |
442 | MLX5_RECV_OPCODE_SEND_IMM = 0x02, | |
443 | MLX5_RECV_OPCODE_SEND_INVAL = 0x03, | |
444 | ||
445 | MLX5_CQE_OPCODE_ERROR = 0x1e, | |
446 | MLX5_CQE_OPCODE_RESIZE = 0x16, | |
447 | ||
448 | MLX5_OPCODE_SET_PSV = 0x20, | |
449 | MLX5_OPCODE_GET_PSV = 0x21, | |
450 | MLX5_OPCODE_CHECK_PSV = 0x22, | |
a12ff35e | 451 | MLX5_OPCODE_DUMP = 0x23, |
e126ba97 EC |
452 | MLX5_OPCODE_RGET_PSV = 0x26, |
453 | MLX5_OPCODE_RCHECK_PSV = 0x27, | |
454 | ||
455 | MLX5_OPCODE_UMR = 0x25, | |
456 | ||
457 | }; | |
458 | ||
a12ff35e | 459 | enum { |
26149e3e | 460 | MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, |
ee5cdf7a | 461 | MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2, |
a12ff35e EBE |
462 | }; |
463 | ||
464 | enum { | |
26149e3e | 465 | MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, |
ee5cdf7a | 466 | MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2, |
a12ff35e EBE |
467 | }; |
468 | ||
2d1b69ed TT |
469 | struct mlx5_wqe_tls_static_params_seg { |
470 | u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)]; | |
471 | }; | |
472 | ||
473 | struct mlx5_wqe_tls_progress_params_seg { | |
474 | __be32 tis_tir_num; | |
475 | u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)]; | |
476 | }; | |
477 | ||
e126ba97 EC |
478 | enum { |
479 | MLX5_SET_PORT_RESET_QKEY = 0, | |
480 | MLX5_SET_PORT_GUID0 = 16, | |
481 | MLX5_SET_PORT_NODE_GUID = 17, | |
482 | MLX5_SET_PORT_SYS_GUID = 18, | |
483 | MLX5_SET_PORT_GID_TABLE = 19, | |
484 | MLX5_SET_PORT_PKEY_TABLE = 20, | |
485 | }; | |
486 | ||
d8880795 TT |
487 | enum { |
488 | MLX5_BW_NO_LIMIT = 0, | |
489 | MLX5_100_MBPS_UNIT = 3, | |
490 | MLX5_GBPS_UNIT = 4, | |
491 | }; | |
492 | ||
e126ba97 EC |
493 | enum { |
494 | MLX5_MAX_PAGE_SHIFT = 31 | |
495 | }; | |
496 | ||
87b8de49 | 497 | enum { |
87b8de49 EC |
498 | MLX5_CAP_OFF_CMDIF_CSUM = 46, |
499 | }; | |
500 | ||
986ef95e SG |
501 | enum { |
502 | /* | |
503 | * Max wqe size for rdma read is 512 bytes, so this | |
504 | * limits our max_sge_rd as the wqe needs to fit: | |
505 | * - ctrl segment (16 bytes) | |
506 | * - rdma segment (16 bytes) | |
507 | * - scatter elements (16 bytes each) | |
508 | */ | |
509 | MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 | |
510 | }; | |
511 | ||
e420f0c0 HE |
512 | enum mlx5_odp_transport_cap_bits { |
513 | MLX5_ODP_SUPPORT_SEND = 1 << 31, | |
514 | MLX5_ODP_SUPPORT_RECV = 1 << 30, | |
515 | MLX5_ODP_SUPPORT_WRITE = 1 << 29, | |
516 | MLX5_ODP_SUPPORT_READ = 1 << 28, | |
517 | }; | |
518 | ||
519 | struct mlx5_odp_caps { | |
520 | char reserved[0x10]; | |
521 | struct { | |
522 | __be32 rc_odp_caps; | |
523 | __be32 uc_odp_caps; | |
524 | __be32 ud_odp_caps; | |
525 | } per_transport_caps; | |
526 | char reserved2[0xe4]; | |
527 | }; | |
528 | ||
e126ba97 EC |
529 | struct mlx5_cmd_layout { |
530 | u8 type; | |
531 | u8 rsvd0[3]; | |
532 | __be32 inlen; | |
533 | __be64 in_ptr; | |
534 | __be32 in[4]; | |
535 | __be32 out[4]; | |
536 | __be64 out_ptr; | |
537 | __be32 outlen; | |
538 | u8 token; | |
539 | u8 sig; | |
540 | u8 rsvd1; | |
541 | u8 status_own; | |
542 | }; | |
543 | ||
3e5b72ac FD |
544 | enum mlx5_fatal_assert_bit_offsets { |
545 | MLX5_RFR_OFFSET = 31, | |
546 | }; | |
547 | ||
e126ba97 EC |
548 | struct health_buffer { |
549 | __be32 assert_var[5]; | |
550 | __be32 rsvd0[3]; | |
551 | __be32 assert_exit_ptr; | |
552 | __be32 assert_callra; | |
553 | __be32 rsvd1[2]; | |
554 | __be32 fw_ver; | |
555 | __be32 hw_id; | |
3e5b72ac | 556 | __be32 rfr; |
e126ba97 EC |
557 | u8 irisc_index; |
558 | u8 synd; | |
78ccb258 | 559 | __be16 ext_synd; |
e126ba97 EC |
560 | }; |
561 | ||
3e5b72ac FD |
562 | enum mlx5_initializing_bit_offsets { |
563 | MLX5_FW_RESET_SUPPORTED_OFFSET = 30, | |
564 | }; | |
565 | ||
fcd29ad1 FD |
566 | enum mlx5_cmd_addr_l_sz_offset { |
567 | MLX5_NIC_IFC_OFFSET = 8, | |
568 | }; | |
569 | ||
e126ba97 EC |
570 | struct mlx5_init_seg { |
571 | __be32 fw_rev; | |
572 | __be32 cmdif_rev_fw_sub; | |
573 | __be32 rsvd0[2]; | |
574 | __be32 cmdq_addr_h; | |
575 | __be32 cmdq_addr_l_sz; | |
576 | __be32 cmd_dbell; | |
e3297246 EC |
577 | __be32 rsvd1[120]; |
578 | __be32 initializing; | |
e126ba97 | 579 | struct health_buffer health; |
4b2c5fa9 AT |
580 | __be32 rsvd2[878]; |
581 | __be32 cmd_exec_to; | |
582 | __be32 cmd_q_init_to; | |
b0844444 EBE |
583 | __be32 internal_timer_h; |
584 | __be32 internal_timer_l; | |
b368d7cb | 585 | __be32 rsvd3[2]; |
e126ba97 | 586 | __be32 health_counter; |
ae02d415 EBE |
587 | __be32 rsvd4[11]; |
588 | __be32 real_time_h; | |
589 | __be32 real_time_l; | |
590 | __be32 rsvd5[1006]; | |
e126ba97 EC |
591 | __be64 ieee1588_clk; |
592 | __be32 ieee1588_clk_type; | |
593 | __be32 clr_intx; | |
594 | }; | |
595 | ||
596 | struct mlx5_eqe_comp { | |
597 | __be32 reserved[6]; | |
598 | __be32 cqn; | |
599 | }; | |
600 | ||
601 | struct mlx5_eqe_qp_srq { | |
e2013b21 | 602 | __be32 reserved1[5]; |
603 | u8 type; | |
604 | u8 reserved2[3]; | |
e126ba97 EC |
605 | __be32 qp_srq_n; |
606 | }; | |
607 | ||
608 | struct mlx5_eqe_cq_err { | |
609 | __be32 cqn; | |
610 | u8 reserved1[7]; | |
611 | u8 syndrome; | |
612 | }; | |
613 | ||
972d7560 YH |
614 | struct mlx5_eqe_xrq_err { |
615 | __be32 reserved1[5]; | |
616 | __be32 type_xrqn; | |
617 | __be32 reserved2; | |
618 | }; | |
619 | ||
e126ba97 EC |
620 | struct mlx5_eqe_port_state { |
621 | u8 reserved0[8]; | |
622 | u8 port; | |
623 | }; | |
624 | ||
625 | struct mlx5_eqe_gpio { | |
626 | __be32 reserved0[2]; | |
627 | __be64 gpio_event; | |
628 | }; | |
629 | ||
630 | struct mlx5_eqe_congestion { | |
631 | u8 type; | |
632 | u8 rsvd0; | |
633 | u8 congestion_level; | |
634 | }; | |
635 | ||
636 | struct mlx5_eqe_stall_vl { | |
637 | u8 rsvd0[3]; | |
638 | u8 port_vl; | |
639 | }; | |
640 | ||
641 | struct mlx5_eqe_cmd { | |
642 | __be32 vector; | |
643 | __be32 rsvd[6]; | |
644 | }; | |
645 | ||
646 | struct mlx5_eqe_page_req { | |
591905ba | 647 | __be16 ec_function; |
e126ba97 | 648 | __be16 func_id; |
0a324f31 ML |
649 | __be32 num_pages; |
650 | __be32 rsvd1[5]; | |
e126ba97 EC |
651 | }; |
652 | ||
e420f0c0 HE |
653 | struct mlx5_eqe_page_fault { |
654 | __be32 bytes_committed; | |
655 | union { | |
656 | struct { | |
657 | u16 reserved1; | |
658 | __be16 wqe_index; | |
659 | u16 reserved2; | |
660 | __be16 packet_length; | |
d9aaed83 AK |
661 | __be32 token; |
662 | u8 reserved4[8]; | |
663 | __be32 pftype_wq; | |
e420f0c0 HE |
664 | } __packed wqe; |
665 | struct { | |
666 | __be32 r_key; | |
667 | u16 reserved1; | |
668 | __be16 packet_length; | |
669 | __be32 rdma_op_len; | |
670 | __be64 rdma_va; | |
d9aaed83 | 671 | __be32 pftype_token; |
e420f0c0 HE |
672 | } __packed rdma; |
673 | } __packed; | |
e420f0c0 HE |
674 | } __packed; |
675 | ||
073bb189 SM |
676 | struct mlx5_eqe_vport_change { |
677 | u8 rsvd0[2]; | |
678 | __be16 vport_num; | |
679 | __be32 rsvd1[6]; | |
680 | } __packed; | |
681 | ||
4ce3bf2f HN |
682 | struct mlx5_eqe_port_module { |
683 | u8 reserved_at_0[1]; | |
684 | u8 module; | |
685 | u8 reserved_at_2[1]; | |
686 | u8 module_status; | |
687 | u8 reserved_at_4[2]; | |
688 | u8 error_type; | |
689 | } __packed; | |
690 | ||
f9a1ef72 EE |
691 | struct mlx5_eqe_pps { |
692 | u8 rsvd0[3]; | |
693 | u8 pin; | |
694 | u8 rsvd1[4]; | |
695 | union { | |
696 | struct { | |
697 | __be32 time_sec; | |
698 | __be32 time_nsec; | |
699 | }; | |
700 | struct { | |
701 | __be64 time_stamp; | |
702 | }; | |
703 | }; | |
704 | u8 rsvd2[12]; | |
705 | } __packed; | |
706 | ||
57cda166 MS |
707 | struct mlx5_eqe_dct { |
708 | __be32 reserved[6]; | |
709 | __be32 dctn; | |
710 | }; | |
711 | ||
1865ea9a IT |
712 | struct mlx5_eqe_temp_warning { |
713 | __be64 sensor_warning_msb; | |
714 | __be64 sensor_warning_lsb; | |
715 | } __packed; | |
716 | ||
3df01077 MS |
717 | #define SYNC_RST_STATE_MASK 0xf |
718 | ||
719 | enum sync_rst_state_type { | |
720 | MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0, | |
721 | MLX5_SYNC_RST_STATE_RESET_NOW = 0x1, | |
722 | MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2, | |
723 | }; | |
724 | ||
725 | struct mlx5_eqe_sync_fw_update { | |
726 | u8 reserved_at_0[3]; | |
727 | u8 sync_rst_state; | |
728 | }; | |
729 | ||
349125ba PP |
730 | struct mlx5_eqe_vhca_state { |
731 | __be16 ec_function; | |
732 | __be16 function_id; | |
733 | } __packed; | |
734 | ||
e126ba97 EC |
735 | union ev_data { |
736 | __be32 raw[7]; | |
737 | struct mlx5_eqe_cmd cmd; | |
738 | struct mlx5_eqe_comp comp; | |
739 | struct mlx5_eqe_qp_srq qp_srq; | |
740 | struct mlx5_eqe_cq_err cq_err; | |
e126ba97 EC |
741 | struct mlx5_eqe_port_state port; |
742 | struct mlx5_eqe_gpio gpio; | |
743 | struct mlx5_eqe_congestion cong; | |
744 | struct mlx5_eqe_stall_vl stall_vl; | |
745 | struct mlx5_eqe_page_req req_pages; | |
e420f0c0 | 746 | struct mlx5_eqe_page_fault page_fault; |
073bb189 | 747 | struct mlx5_eqe_vport_change vport_change; |
4ce3bf2f | 748 | struct mlx5_eqe_port_module port_module; |
f9a1ef72 | 749 | struct mlx5_eqe_pps pps; |
57cda166 | 750 | struct mlx5_eqe_dct dct; |
1865ea9a | 751 | struct mlx5_eqe_temp_warning temp_warning; |
972d7560 | 752 | struct mlx5_eqe_xrq_err xrq_err; |
3df01077 | 753 | struct mlx5_eqe_sync_fw_update sync_fw_update; |
349125ba | 754 | struct mlx5_eqe_vhca_state vhca_state; |
e126ba97 EC |
755 | } __packed; |
756 | ||
757 | struct mlx5_eqe { | |
758 | u8 rsvd0; | |
759 | u8 type; | |
760 | u8 rsvd1; | |
761 | u8 sub_type; | |
762 | __be32 rsvd2[7]; | |
763 | union ev_data data; | |
764 | __be16 rsvd3; | |
765 | u8 signature; | |
766 | u8 owner; | |
767 | } __packed; | |
768 | ||
769 | struct mlx5_cmd_prot_block { | |
770 | u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; | |
771 | u8 rsvd0[48]; | |
772 | __be64 next; | |
773 | __be32 block_num; | |
774 | u8 rsvd1; | |
775 | u8 token; | |
776 | u8 ctrl_sig; | |
777 | u8 sig; | |
778 | }; | |
779 | ||
e281682b SM |
780 | enum { |
781 | MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, | |
782 | }; | |
783 | ||
e126ba97 EC |
784 | struct mlx5_err_cqe { |
785 | u8 rsvd0[32]; | |
786 | __be32 srqn; | |
787 | u8 rsvd1[18]; | |
788 | u8 vendor_err_synd; | |
789 | u8 syndrome; | |
790 | __be32 s_wqe_opcode_qpn; | |
791 | __be16 wqe_counter; | |
792 | u8 signature; | |
793 | u8 op_own; | |
794 | }; | |
795 | ||
796 | struct mlx5_cqe64 { | |
ee5cdf7a | 797 | u8 tls_outer_l3_tunneled; |
1b223dd3 SM |
798 | u8 rsvd0; |
799 | __be16 wqe_id; | |
e281682b SM |
800 | u8 lro_tcppsh_abort_dupack; |
801 | u8 lro_min_ttl; | |
802 | __be16 lro_tcp_win; | |
803 | __be32 lro_ack_seq_num; | |
804 | __be32 rss_hash_result; | |
805 | u8 rss_hash_type; | |
e126ba97 | 806 | u8 ml_path; |
e281682b SM |
807 | u8 rsvd20[2]; |
808 | __be16 check_sum; | |
e126ba97 EC |
809 | __be16 slid; |
810 | __be32 flags_rqpn; | |
e281682b | 811 | u8 hds_ip_ext; |
1b223dd3 | 812 | u8 l4_l3_hdr_type; |
e281682b SM |
813 | __be16 vlan_info; |
814 | __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ | |
244faedf RS |
815 | union { |
816 | __be32 immediate; | |
817 | __be32 inval_rkey; | |
818 | __be32 pkey; | |
819 | __be32 ft_metadata; | |
820 | }; | |
e126ba97 EC |
821 | u8 rsvd40[4]; |
822 | __be32 byte_cnt; | |
b0844444 EBE |
823 | __be32 timestamp_h; |
824 | __be32 timestamp_l; | |
e126ba97 EC |
825 | __be32 sop_drop_qpn; |
826 | __be16 wqe_counter; | |
827 | u8 signature; | |
828 | u8 op_own; | |
829 | }; | |
830 | ||
7219ab34 TT |
831 | struct mlx5_mini_cqe8 { |
832 | union { | |
833 | __be32 rx_hash_result; | |
834 | struct { | |
835 | __be16 checksum; | |
b7cf0806 | 836 | __be16 stridx; |
7219ab34 TT |
837 | }; |
838 | struct { | |
839 | __be16 wqe_counter; | |
840 | u8 s_wqe_opcode; | |
841 | u8 reserved; | |
842 | } s_wqe_info; | |
843 | }; | |
844 | __be32 byte_cnt; | |
845 | }; | |
846 | ||
847 | enum { | |
848 | MLX5_NO_INLINE_DATA, | |
849 | MLX5_INLINE_DATA32_SEG, | |
850 | MLX5_INLINE_DATA64_SEG, | |
851 | MLX5_COMPRESSED, | |
852 | }; | |
853 | ||
854 | enum { | |
855 | MLX5_CQE_FORMAT_CSUM = 0x1, | |
b7cf0806 | 856 | MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3, |
7219ab34 TT |
857 | }; |
858 | ||
859 | #define MLX5_MINI_CQE_ARRAY_SIZE 8 | |
860 | ||
e2abdcf1 | 861 | static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) |
7219ab34 TT |
862 | { |
863 | return (cqe->op_own >> 2) & 0x3; | |
864 | } | |
865 | ||
6254adeb TT |
866 | static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) |
867 | { | |
868 | return cqe->op_own >> 4; | |
869 | } | |
870 | ||
604acb19 | 871 | static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) |
e281682b SM |
872 | { |
873 | return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; | |
874 | } | |
875 | ||
876 | static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) | |
877 | { | |
1b223dd3 SM |
878 | return (cqe->l4_l3_hdr_type >> 4) & 0x7; |
879 | } | |
880 | ||
881 | static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) | |
882 | { | |
883 | return (cqe->l4_l3_hdr_type >> 2) & 0x3; | |
884 | } | |
885 | ||
e2abdcf1 | 886 | static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) |
1b223dd3 | 887 | { |
ee5cdf7a TT |
888 | return cqe->tls_outer_l3_tunneled & 0x1; |
889 | } | |
890 | ||
891 | static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) | |
892 | { | |
893 | return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; | |
e281682b SM |
894 | } |
895 | ||
e2abdcf1 | 896 | static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) |
e281682b | 897 | { |
e2abdcf1 | 898 | return cqe->l4_l3_hdr_type & 0x1; |
e281682b SM |
899 | } |
900 | ||
b0844444 EBE |
901 | static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) |
902 | { | |
903 | u32 hi, lo; | |
904 | ||
905 | hi = be32_to_cpu(cqe->timestamp_h); | |
906 | lo = be32_to_cpu(cqe->timestamp_l); | |
907 | ||
908 | return (u64)lo | ((u64)hi << 32); | |
909 | } | |
910 | ||
5543e989 AL |
911 | static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe) |
912 | { | |
913 | return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF; | |
914 | } | |
915 | ||
6980ffa0 TT |
916 | #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3 |
917 | #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9 | |
918 | #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16 | |
919 | #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6 | |
920 | #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13 | |
619a8f2a | 921 | |
461017cb TT |
922 | struct mpwrq_cqe_bc { |
923 | __be16 filler_consumed_strides; | |
924 | __be16 byte_cnt; | |
925 | }; | |
926 | ||
927 | static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) | |
928 | { | |
929 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; | |
930 | ||
931 | return be16_to_cpu(bc->byte_cnt); | |
932 | } | |
933 | ||
934 | static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) | |
935 | { | |
936 | return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); | |
937 | } | |
938 | ||
939 | static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) | |
940 | { | |
941 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; | |
942 | ||
943 | return mpwrq_get_cqe_bc_consumed_strides(bc); | |
944 | } | |
945 | ||
946 | static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) | |
947 | { | |
948 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; | |
949 | ||
950 | return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); | |
951 | } | |
952 | ||
953 | static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) | |
954 | { | |
955 | return be16_to_cpu(cqe->wqe_counter); | |
956 | } | |
957 | ||
e281682b SM |
958 | enum { |
959 | CQE_L4_HDR_TYPE_NONE = 0x0, | |
960 | CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, | |
961 | CQE_L4_HDR_TYPE_UDP = 0x2, | |
962 | CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, | |
963 | CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, | |
964 | }; | |
965 | ||
966 | enum { | |
12e8b570 JDB |
967 | CQE_RSS_HTYPE_IP = 0x3 << 2, |
968 | /* cqe->rss_hash_type[3:2] - IP destination selected for hash | |
969 | * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) | |
970 | */ | |
971 | CQE_RSS_HTYPE_L4 = 0x3 << 6, | |
972 | /* cqe->rss_hash_type[7:6] - L4 destination selected for hash | |
973 | * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI | |
974 | */ | |
e281682b SM |
975 | }; |
976 | ||
cb34be6d AS |
977 | enum { |
978 | MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, | |
979 | MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, | |
980 | MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, | |
981 | }; | |
982 | ||
e281682b SM |
983 | enum { |
984 | CQE_L2_OK = 1 << 0, | |
985 | CQE_L3_OK = 1 << 1, | |
986 | CQE_L4_OK = 1 << 2, | |
987 | }; | |
988 | ||
ee5cdf7a TT |
989 | enum { |
990 | CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, | |
991 | CQE_TLS_OFFLOAD_DECRYPTED = 0x1, | |
992 | CQE_TLS_OFFLOAD_RESYNC = 0x2, | |
993 | CQE_TLS_OFFLOAD_ERROR = 0x3, | |
994 | }; | |
995 | ||
d5436ba0 SG |
996 | struct mlx5_sig_err_cqe { |
997 | u8 rsvd0[16]; | |
998 | __be32 expected_trans_sig; | |
999 | __be32 actual_trans_sig; | |
1000 | __be32 expected_reftag; | |
1001 | __be32 actual_reftag; | |
1002 | __be16 syndrome; | |
1003 | u8 rsvd22[2]; | |
1004 | __be32 mkey; | |
1005 | __be64 err_offset; | |
1006 | u8 rsvd30[8]; | |
1007 | __be32 qpn; | |
1008 | u8 rsvd38[2]; | |
1009 | u8 signature; | |
1010 | u8 op_own; | |
1011 | }; | |
1012 | ||
e126ba97 EC |
1013 | struct mlx5_wqe_srq_next_seg { |
1014 | u8 rsvd0[2]; | |
1015 | __be16 next_wqe_index; | |
1016 | u8 signature; | |
1017 | u8 rsvd1[11]; | |
1018 | }; | |
1019 | ||
1020 | union mlx5_ext_cqe { | |
1021 | struct ib_grh grh; | |
1022 | u8 inl[64]; | |
1023 | }; | |
1024 | ||
1025 | struct mlx5_cqe128 { | |
1026 | union mlx5_ext_cqe inl_grh; | |
1027 | struct mlx5_cqe64 cqe64; | |
1028 | }; | |
1029 | ||
968e78dd HE |
1030 | enum { |
1031 | MLX5_MKEY_STATUS_FREE = 1 << 6, | |
1032 | }; | |
1033 | ||
ec22eb53 SM |
1034 | enum { |
1035 | MLX5_MKEY_REMOTE_INVAL = 1 << 24, | |
1036 | MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, | |
1037 | MLX5_MKEY_BSF_EN = 1 << 30, | |
ec22eb53 SM |
1038 | }; |
1039 | ||
e126ba97 EC |
1040 | struct mlx5_mkey_seg { |
1041 | /* This is a two bit field occupying bits 31-30. | |
1042 | * bit 31 is always 0, | |
39c538d6 | 1043 | * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation |
e126ba97 EC |
1044 | */ |
1045 | u8 status; | |
1046 | u8 pcie_control; | |
1047 | u8 flags; | |
1048 | u8 version; | |
1049 | __be32 qpn_mkey7_0; | |
1050 | u8 rsvd1[4]; | |
1051 | __be32 flags_pd; | |
1052 | __be64 start_addr; | |
1053 | __be64 len; | |
1054 | __be32 bsfs_octo_size; | |
1055 | u8 rsvd2[16]; | |
1056 | __be32 xlt_oct_size; | |
1057 | u8 rsvd3[3]; | |
1058 | u8 log2_page_size; | |
1059 | u8 rsvd4[4]; | |
1060 | }; | |
1061 | ||
e126ba97 EC |
1062 | #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
1063 | ||
1064 | enum { | |
1065 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 | |
1066 | }; | |
1067 | ||
e281682b SM |
1068 | enum { |
1069 | VPORT_STATE_DOWN = 0x0, | |
1070 | VPORT_STATE_UP = 0x1, | |
1071 | }; | |
1072 | ||
81848731 | 1073 | enum { |
cc9c82a8 EBE |
1074 | MLX5_VPORT_ADMIN_STATE_DOWN = 0x0, |
1075 | MLX5_VPORT_ADMIN_STATE_UP = 0x1, | |
1076 | MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, | |
81848731 SM |
1077 | }; |
1078 | ||
e281682b SM |
1079 | enum { |
1080 | MLX5_L3_PROT_TYPE_IPV4 = 0, | |
1081 | MLX5_L3_PROT_TYPE_IPV6 = 1, | |
1082 | }; | |
1083 | ||
1084 | enum { | |
1085 | MLX5_L4_PROT_TYPE_TCP = 0, | |
1086 | MLX5_L4_PROT_TYPE_UDP = 1, | |
1087 | }; | |
1088 | ||
1089 | enum { | |
1090 | MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, | |
1091 | MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, | |
1092 | MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, | |
1093 | MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, | |
1094 | MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, | |
1095 | }; | |
1096 | ||
1097 | enum { | |
1098 | MLX5_MATCH_OUTER_HEADERS = 1 << 0, | |
1099 | MLX5_MATCH_MISC_PARAMETERS = 1 << 1, | |
1100 | MLX5_MATCH_INNER_HEADERS = 1 << 2, | |
b169e64a YK |
1101 | MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, |
1102 | MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, | |
7da3ad6c | 1103 | MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5, |
e281682b SM |
1104 | }; |
1105 | ||
1106 | enum { | |
1107 | MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, | |
1108 | MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, | |
1109 | }; | |
1110 | ||
1111 | enum { | |
1112 | MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, | |
1113 | MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, | |
1114 | MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, | |
1115 | }; | |
1116 | ||
e16aea27 SM |
1117 | enum mlx5_list_type { |
1118 | MLX5_NVPRT_LIST_TYPE_UC = 0x0, | |
1119 | MLX5_NVPRT_LIST_TYPE_MC = 0x1, | |
1120 | MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, | |
1121 | }; | |
1122 | ||
e281682b SM |
1123 | enum { |
1124 | MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, | |
1125 | MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, | |
1126 | }; | |
1127 | ||
928cfe87 TT |
1128 | enum mlx5_wol_mode { |
1129 | MLX5_WOL_DISABLE = 0, | |
1130 | MLX5_WOL_SECURED_MAGIC = 1 << 1, | |
1131 | MLX5_WOL_MAGIC = 1 << 2, | |
1132 | MLX5_WOL_ARP = 1 << 3, | |
1133 | MLX5_WOL_BROADCAST = 1 << 4, | |
1134 | MLX5_WOL_MULTICAST = 1 << 5, | |
1135 | MLX5_WOL_UNICAST = 1 << 6, | |
1136 | MLX5_WOL_PHY_ACTIVITY = 1 << 7, | |
1137 | }; | |
1138 | ||
71c6e863 AL |
1139 | enum mlx5_mpls_supported_fields { |
1140 | MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0, | |
1141 | MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1, | |
1142 | MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2, | |
1143 | MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3 | |
1144 | }; | |
1145 | ||
e818e255 | 1146 | enum mlx5_flex_parser_protos { |
b169e64a | 1147 | MLX5_FLEX_PROTO_GENEVE = 1 << 3, |
e818e255 AL |
1148 | MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4, |
1149 | MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5, | |
a3222a2d MD |
1150 | MLX5_FLEX_PROTO_ICMP = 1 << 8, |
1151 | MLX5_FLEX_PROTO_ICMPV6 = 1 << 9, | |
e818e255 AL |
1152 | }; |
1153 | ||
938fe83c SM |
1154 | /* MLX5 DEV CAPs */ |
1155 | ||
1156 | /* TODO: EAT.ME */ | |
1157 | enum mlx5_cap_mode { | |
1158 | HCA_CAP_OPMOD_GET_MAX = 0, | |
1159 | HCA_CAP_OPMOD_GET_CUR = 1, | |
1160 | }; | |
1161 | ||
48f02eef PP |
1162 | /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate |
1163 | * capability memory. | |
1164 | */ | |
938fe83c SM |
1165 | enum mlx5_cap_type { |
1166 | MLX5_CAP_GENERAL = 0, | |
1167 | MLX5_CAP_ETHERNET_OFFLOADS, | |
1168 | MLX5_CAP_ODP, | |
1169 | MLX5_CAP_ATOMIC, | |
1170 | MLX5_CAP_ROCE, | |
1171 | MLX5_CAP_IPOIB_OFFLOADS, | |
4ce749bd | 1172 | MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, |
938fe83c | 1173 | MLX5_CAP_FLOW_TABLE, |
495716b1 | 1174 | MLX5_CAP_ESWITCH_FLOW_TABLE, |
d6666753 | 1175 | MLX5_CAP_ESWITCH, |
3f0393a5 SG |
1176 | MLX5_CAP_RESERVED, |
1177 | MLX5_CAP_VECTOR_CALC, | |
1466cc5b | 1178 | MLX5_CAP_QOS, |
2fcb12df | 1179 | MLX5_CAP_DEBUG, |
e72bd817 AL |
1180 | MLX5_CAP_RESERVED_14, |
1181 | MLX5_CAP_DEV_MEM, | |
a12ff35e EBE |
1182 | MLX5_CAP_RESERVED_16, |
1183 | MLX5_CAP_TLS, | |
ca1992c6 | 1184 | MLX5_CAP_VDPA_EMULATION = 0x13, |
b9a7ba55 | 1185 | MLX5_CAP_DEV_EVENT = 0x14, |
2b58f6d9 | 1186 | MLX5_CAP_IPSEC, |
67133eaa | 1187 | MLX5_CAP_GENERAL_2 = 0x20, |
938fe83c SM |
1188 | /* NUM OF CAP Types */ |
1189 | MLX5_CAP_NUM | |
1190 | }; | |
1191 | ||
cfdcbcea GP |
1192 | enum mlx5_pcam_reg_groups { |
1193 | MLX5_PCAM_REGS_5000_TO_507F = 0x0, | |
1194 | }; | |
1195 | ||
1196 | enum mlx5_pcam_feature_groups { | |
1197 | MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, | |
1198 | }; | |
1199 | ||
1200 | enum mlx5_mcam_reg_groups { | |
1201 | MLX5_MCAM_REGS_FIRST_128 = 0x0, | |
932ef155 EBE |
1202 | MLX5_MCAM_REGS_0x9080_0x90FF = 0x1, |
1203 | MLX5_MCAM_REGS_0x9100_0x917F = 0x2, | |
1204 | MLX5_MCAM_REGS_NUM = 0x3, | |
cfdcbcea GP |
1205 | }; |
1206 | ||
1207 | enum mlx5_mcam_feature_groups { | |
1208 | MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, | |
1209 | }; | |
1210 | ||
c02762eb HN |
1211 | enum mlx5_qcam_reg_groups { |
1212 | MLX5_QCAM_REGS_FIRST_128 = 0x0, | |
1213 | }; | |
1214 | ||
1215 | enum mlx5_qcam_feature_groups { | |
1216 | MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, | |
1217 | }; | |
1218 | ||
938fe83c SM |
1219 | /* GET Dev Caps macros */ |
1220 | #define MLX5_CAP_GEN(mdev, cap) \ | |
48f02eef | 1221 | MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) |
938fe83c | 1222 | |
38b7ca92 | 1223 | #define MLX5_CAP_GEN_64(mdev, cap) \ |
48f02eef | 1224 | MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) |
38b7ca92 | 1225 | |
938fe83c | 1226 | #define MLX5_CAP_GEN_MAX(mdev, cap) \ |
48f02eef | 1227 | MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap) |
938fe83c | 1228 | |
67133eaa | 1229 | #define MLX5_CAP_GEN_2(mdev, cap) \ |
48f02eef | 1230 | MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) |
67133eaa YK |
1231 | |
1232 | #define MLX5_CAP_GEN_2_64(mdev, cap) \ | |
48f02eef | 1233 | MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) |
67133eaa YK |
1234 | |
1235 | #define MLX5_CAP_GEN_2_MAX(mdev, cap) \ | |
48f02eef | 1236 | MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap) |
67133eaa | 1237 | |
938fe83c SM |
1238 | #define MLX5_CAP_ETH(mdev, cap) \ |
1239 | MLX5_GET(per_protocol_networking_offload_caps,\ | |
48f02eef | 1240 | mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap) |
938fe83c SM |
1241 | |
1242 | #define MLX5_CAP_ETH_MAX(mdev, cap) \ | |
1243 | MLX5_GET(per_protocol_networking_offload_caps,\ | |
48f02eef | 1244 | mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->max, cap) |
938fe83c | 1245 | |
4ce749bd YH |
1246 | #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ |
1247 | MLX5_GET(per_protocol_networking_offload_caps,\ | |
48f02eef | 1248 | mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap) |
4ce749bd | 1249 | |
938fe83c | 1250 | #define MLX5_CAP_ROCE(mdev, cap) \ |
48f02eef | 1251 | MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap) |
938fe83c SM |
1252 | |
1253 | #define MLX5_CAP_ROCE_MAX(mdev, cap) \ | |
48f02eef | 1254 | MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap) |
938fe83c SM |
1255 | |
1256 | #define MLX5_CAP_ATOMIC(mdev, cap) \ | |
48f02eef | 1257 | MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap) |
938fe83c SM |
1258 | |
1259 | #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ | |
48f02eef | 1260 | MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap) |
938fe83c SM |
1261 | |
1262 | #define MLX5_CAP_FLOWTABLE(mdev, cap) \ | |
48f02eef | 1263 | MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) |
938fe83c | 1264 | |
97b5484e | 1265 | #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ |
48f02eef | 1266 | MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) |
97b5484e | 1267 | |
938fe83c | 1268 | #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ |
48f02eef | 1269 | MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->max, cap) |
938fe83c | 1270 | |
876d634d MG |
1271 | #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ |
1272 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) | |
1273 | ||
1274 | #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ | |
1275 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) | |
1276 | ||
8ce78257 MB |
1277 | #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ |
1278 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) | |
1279 | ||
1280 | #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \ | |
1281 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap) | |
1282 | ||
cea824d4 MG |
1283 | #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ |
1284 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) | |
1285 | ||
1286 | #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ | |
1287 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) | |
1288 | ||
1289 | #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ | |
1290 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) | |
1291 | ||
1292 | #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ | |
1293 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) | |
1294 | ||
d83eb50e MG |
1295 | #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ |
1296 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) | |
1297 | ||
1298 | #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \ | |
1299 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap) | |
1300 | ||
24670b1a MG |
1301 | #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ |
1302 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap) | |
1303 | ||
1304 | #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \ | |
1305 | MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap) | |
1306 | ||
495716b1 SM |
1307 | #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ |
1308 | MLX5_GET(flow_table_eswitch_cap, \ | |
48f02eef | 1309 | mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) |
495716b1 SM |
1310 | |
1311 | #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ | |
1312 | MLX5_GET(flow_table_eswitch_cap, \ | |
48f02eef | 1313 | mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->max, cap) |
495716b1 SM |
1314 | |
1315 | #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ | |
1316 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) | |
1317 | ||
1318 | #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ | |
1319 | MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) | |
1320 | ||
efdc810b MHY |
1321 | #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ |
1322 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) | |
1323 | ||
1324 | #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ | |
1325 | MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) | |
1326 | ||
1327 | #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ | |
1328 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) | |
1329 | ||
1330 | #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ | |
1331 | MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) | |
1332 | ||
d6666753 SM |
1333 | #define MLX5_CAP_ESW(mdev, cap) \ |
1334 | MLX5_GET(e_switch_cap, \ | |
48f02eef | 1335 | mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap) |
d6666753 | 1336 | |
97b5484e AV |
1337 | #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ |
1338 | MLX5_GET64(flow_table_eswitch_cap, \ | |
48f02eef | 1339 | (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) |
97b5484e | 1340 | |
d6666753 SM |
1341 | #define MLX5_CAP_ESW_MAX(mdev, cap) \ |
1342 | MLX5_GET(e_switch_cap, \ | |
48f02eef | 1343 | mdev->caps.hca[MLX5_CAP_ESWITCH]->max, cap) |
d6666753 | 1344 | |
938fe83c | 1345 | #define MLX5_CAP_ODP(mdev, cap)\ |
48f02eef | 1346 | MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap) |
938fe83c | 1347 | |
46861e3e | 1348 | #define MLX5_CAP_ODP_MAX(mdev, cap)\ |
48f02eef | 1349 | MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap) |
46861e3e | 1350 | |
3f0393a5 SG |
1351 | #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ |
1352 | MLX5_GET(vector_calc_cap, \ | |
48f02eef | 1353 | mdev->caps.hca[MLX5_CAP_VECTOR_CALC]->cur, cap) |
3f0393a5 | 1354 | |
1466cc5b | 1355 | #define MLX5_CAP_QOS(mdev, cap)\ |
48f02eef | 1356 | MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap) |
1466cc5b | 1357 | |
2fcb12df | 1358 | #define MLX5_CAP_DEBUG(mdev, cap)\ |
48f02eef | 1359 | MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap) |
2fcb12df | 1360 | |
71862561 GP |
1361 | #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ |
1362 | MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) | |
1363 | ||
df5f1361 HN |
1364 | #define MLX5_CAP_PCAM_REG(mdev, reg) \ |
1365 | MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) | |
1366 | ||
0ab87743 | 1367 | #define MLX5_CAP_MCAM_REG(mdev, reg) \ |
932ef155 EBE |
1368 | MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \ |
1369 | mng_access_reg_cap_mask.access_regs.reg) | |
1370 | ||
1371 | #define MLX5_CAP_MCAM_REG1(mdev, reg) \ | |
1372 | MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \ | |
1373 | mng_access_reg_cap_mask.access_regs1.reg) | |
1374 | ||
1375 | #define MLX5_CAP_MCAM_REG2(mdev, reg) \ | |
1376 | MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ | |
1377 | mng_access_reg_cap_mask.access_regs2.reg) | |
0ab87743 | 1378 | |
71862561 GP |
1379 | #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ |
1380 | MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) | |
1381 | ||
c02762eb HN |
1382 | #define MLX5_CAP_QCAM_REG(mdev, fld) \ |
1383 | MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) | |
1384 | ||
1385 | #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ | |
1386 | MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) | |
1387 | ||
e29341fb | 1388 | #define MLX5_CAP_FPGA(mdev, cap) \ |
99d3cd27 | 1389 | MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) |
e29341fb | 1390 | |
a9956d35 | 1391 | #define MLX5_CAP64_FPGA(mdev, cap) \ |
99d3cd27 | 1392 | MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) |
a9956d35 | 1393 | |
e72bd817 | 1394 | #define MLX5_CAP_DEV_MEM(mdev, cap)\ |
48f02eef | 1395 | MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) |
e72bd817 AL |
1396 | |
1397 | #define MLX5_CAP64_DEV_MEM(mdev, cap)\ | |
48f02eef | 1398 | MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) |
e72bd817 | 1399 | |
a12ff35e | 1400 | #define MLX5_CAP_TLS(mdev, cap) \ |
48f02eef | 1401 | MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap) |
a12ff35e | 1402 | |
b9a7ba55 | 1403 | #define MLX5_CAP_DEV_EVENT(mdev, cap)\ |
48f02eef | 1404 | MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap) |
b9a7ba55 | 1405 | |
ca1992c6 | 1406 | #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\ |
8a06a79b | 1407 | MLX5_GET(virtio_emulation_cap, \ |
48f02eef | 1408 | (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) |
ca1992c6 YH |
1409 | |
1410 | #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\ | |
8a06a79b | 1411 | MLX5_GET64(virtio_emulation_cap, \ |
48f02eef | 1412 | (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) |
ca1992c6 | 1413 | |
2b58f6d9 | 1414 | #define MLX5_CAP_IPSEC(mdev, cap)\ |
48f02eef | 1415 | MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap) |
2b58f6d9 | 1416 | |
f62b8bb8 AV |
1417 | enum { |
1418 | MLX5_CMD_STAT_OK = 0x0, | |
1419 | MLX5_CMD_STAT_INT_ERR = 0x1, | |
1420 | MLX5_CMD_STAT_BAD_OP_ERR = 0x2, | |
1421 | MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, | |
1422 | MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, | |
1423 | MLX5_CMD_STAT_BAD_RES_ERR = 0x5, | |
1424 | MLX5_CMD_STAT_RES_BUSY = 0x6, | |
1425 | MLX5_CMD_STAT_LIM_ERR = 0x8, | |
1426 | MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, | |
1427 | MLX5_CMD_STAT_IX_ERR = 0xa, | |
1428 | MLX5_CMD_STAT_NO_RES_ERR = 0xf, | |
1429 | MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, | |
1430 | MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, | |
1431 | MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, | |
1432 | MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, | |
1433 | MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, | |
1434 | }; | |
1435 | ||
efea389d GP |
1436 | enum { |
1437 | MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, | |
1438 | MLX5_RFC_2863_COUNTERS_GROUP = 0x1, | |
1439 | MLX5_RFC_2819_COUNTERS_GROUP = 0x2, | |
1440 | MLX5_RFC_3635_COUNTERS_GROUP = 0x3, | |
1441 | MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, | |
1442 | MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, | |
1c64bf6f | 1443 | MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, |
121fcdc8 | 1444 | MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, |
948d3f90 | 1445 | MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13, |
d8dc0508 | 1446 | MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, |
1c64bf6f | 1447 | MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, |
efea389d GP |
1448 | }; |
1449 | ||
8ed1a630 GP |
1450 | enum { |
1451 | MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, | |
1452 | }; | |
1453 | ||
707c4602 MD |
1454 | static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) |
1455 | { | |
1456 | if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) | |
1457 | return 0; | |
1458 | return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; | |
1459 | } | |
1460 | ||
72f7cc09 MB |
1461 | #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 |
1462 | #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 | |
35d19011 MG |
1463 | #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 |
1464 | #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ | |
1465 | MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ | |
1466 | MLX5_BY_PASS_NUM_MULTICAST_PRIOS) | |
4cbdd30e | 1467 | |
e126ba97 | 1468 | #endif /* MLX5_DEVICE_H */ |