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IB/mlx5: Extend UAR stuff to support dynamic allocation
[linux-2.6-block.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
667cb65a 51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
71c70eb2 52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
d29b796a
EC		 53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
71c70eb2 55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
d29b796a
EC		 56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
71c70eb2
HN		 59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
d29b796a
EC		 61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
9218b44d 66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
938fe83c
SM		 67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72/* insert a value to a struct */
73#define MLX5_SET(typ, p, fld, v) do { \
a61d5ce9 74 u32 _v = v; \
d29b796a
EC		 75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
a61d5ce9 78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
d29b796a
EC		 79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
e281682b
SM		 82#define MLX5_SET_TO_ONES(typ, p, fld) do { \
83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
84 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
85 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
86 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
87 << __mlx5_dw_bit_off(typ, fld))); \
88} while (0)
89
d29b796a
EC		 90#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
91__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
92__mlx5_mask(typ, fld))
93
94#define MLX5_GET_PR(typ, p, fld) ({ \
95 u32 ___t = MLX5_GET(typ, p, fld); \
96 pr_debug(#fld " = 0x%x\n", ___t); \
97 ___t; \
98})
99
b8a4ddb2 100#define __MLX5_SET64(typ, p, fld, v) do { \
d29b796a 101 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
d29b796a
EC		 102 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
103} while (0)
104
b8a4ddb2
TH		 105#define MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
107 __MLX5_SET64(typ, p, fld, v); \
108} while (0)
109
110#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld[idx], v); \
113} while (0)
114
d29b796a
EC		 115#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
116
707c4602
MD		 117#define MLX5_GET64_PR(typ, p, fld) ({ \
118 u64 ___t = MLX5_GET64(typ, p, fld); \
119 pr_debug(#fld " = 0x%llx\n", ___t); \
120 ___t; \
121})
122
71c70eb2
HN		 123#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
124__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
125__mlx5_mask16(typ, fld))
126
127#define MLX5_SET16(typ, p, fld, v) do { \
128 u16 _v = v; \
129 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
130 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
131 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
132 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
133 << __mlx5_16_bit_off(typ, fld))); \
134} while (0)
135
3efd9a11
MY		 136/* Big endian getters */
137#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
138 __mlx5_64_off(typ, fld)))
139
140#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
141 type_t tmp; \
142 switch (sizeof(tmp)) { \
143 case sizeof(u8): \
144 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
145 break; \
146 case sizeof(u16): \
147 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
148 break; \
149 case sizeof(u32): \
150 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
151 break; \
152 case sizeof(u64): \
153 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
154 break; \
155 } \
156 tmp; \
157 })
158
ae76715d
HHZ		 159enum mlx5_inline_modes {
160 MLX5_INLINE_MODE_NONE,
161 MLX5_INLINE_MODE_L2,
162 MLX5_INLINE_MODE_IP,
163 MLX5_INLINE_MODE_TCP_UDP,
164};
165
e126ba97
EC		 166enum {
167 MLX5_MAX_COMMANDS = 32,
168 MLX5_CMD_DATA_BLOCK_SIZE = 512,
169 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 170 MLX5_MKEY_BSF_OCTO_SIZE = 4,
171 MLX5_MAX_PSVS = 4,
e126ba97
EC		 172};
173
174enum {
175 MLX5_EXTENDED_UD_AV = 0x80000000,
176};
177
178enum {
179 MLX5_CQ_STATE_ARMED = 9,
180 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
181 MLX5_CQ_STATE_FIRED = 0xa,
182};
183
184enum {
185 MLX5_STAT_RATE_OFFSET = 5,
186};
187
188enum {
189 MLX5_INLINE_SEG = 0x80000000,
190};
191
fc11fbf9
SM		 192enum {
193 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
194};
195
c7a08ac7
EC		 196enum {
197 MLX5_MIN_PKEY_TABLE_SIZE = 128,
198 MLX5_MAX_LOG_PKEY_TABLE = 5,
199};
200
e420f0c0
HE		 201enum {
202 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
203};
204
205enum {
206 MLX5_PFAULT_SUBTYPE_WQE = 0,
207 MLX5_PFAULT_SUBTYPE_RDMA = 1,
208};
209
e126ba97
EC		 210enum {
211 MLX5_PERM_LOCAL_READ = 1 << 2,
212 MLX5_PERM_LOCAL_WRITE = 1 << 3,
213 MLX5_PERM_REMOTE_READ = 1 << 4,
214 MLX5_PERM_REMOTE_WRITE = 1 << 5,
215 MLX5_PERM_ATOMIC = 1 << 6,
216 MLX5_PERM_UMR_EN = 1 << 7,
217};
218
219enum {
220 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
221 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
222 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
223 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
224 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
225};
226
e126ba97
EC		 227enum {
228 MLX5_EN_RD = (u64)1,
229 MLX5_EN_WR = (u64)2
230};
231
232enum {
b037c29a
EC		 233 MLX5_ADAPTER_PAGE_SHIFT = 12,
234 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
235};
236
e126ba97 237enum {
2f5ff264
EC		 238 MLX5_BFREGS_PER_UAR = 4,
239 MLX5_MAX_UARS = 1 << 8,
240 MLX5_NON_FP_BFREGS_PER_UAR = 2,
a6d51b68
EC		 241 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
242 MLX5_NON_FP_BFREGS_PER_UAR,
2f5ff264
EC		 243 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
244 MLX5_NON_FP_BFREGS_PER_UAR,
b037c29a
EC		 245 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
246 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
31a78a5a
YH		 247 MLX5_MIN_DYN_BFREGS = 512,
248 MLX5_MAX_DYN_BFREGS = 1024,
e126ba97
EC		 249};
250
251enum {
252 MLX5_MKEY_MASK_LEN = 1ull << 0,
253 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
254 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
255 MLX5_MKEY_MASK_PD = 1ull << 7,
256 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 257 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 258 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
259 MLX5_MKEY_MASK_KEY = 1ull << 13,
260 MLX5_MKEY_MASK_QPN = 1ull << 14,
261 MLX5_MKEY_MASK_LR = 1ull << 17,
262 MLX5_MKEY_MASK_LW = 1ull << 18,
263 MLX5_MKEY_MASK_RR = 1ull << 19,
264 MLX5_MKEY_MASK_RW = 1ull << 20,
265 MLX5_MKEY_MASK_A = 1ull << 21,
266 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
267 MLX5_MKEY_MASK_FREE = 1ull << 29,
268};
269
968e78dd
HE		 270enum {
271 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
272
273 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
274 MLX5_UMR_CHECK_FREE = (2 << 5),
275
276 MLX5_UMR_INLINE = (1 << 7),
277};
278
cc149f75
HE		 279#define MLX5_UMR_MTT_ALIGNMENT 0x40
280#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 281#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 282
e2013b21 283#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
284
285enum {
286 MLX5_EVENT_QUEUE_TYPE_QP = 0,
287 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
288 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
289};
290
e126ba97
EC		 291enum mlx5_event {
292 MLX5_EVENT_TYPE_COMP = 0x0,
293
294 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
295 MLX5_EVENT_TYPE_COMM_EST = 0x02,
296 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
297 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
298 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
299
300 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
301 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
302 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
303 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
304 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
305 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
306
307 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
308 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
309 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
4ce3bf2f 310 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
e126ba97 311 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
246ac981 312 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
f9a1ef72 313 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
e126ba97
EC		 314
315 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
316 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
317
318 MLX5_EVENT_TYPE_CMD = 0x0a,
319 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 320
321 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
073bb189 322 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
e29341fb
IT		 323
324 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
e126ba97
EC		 325};
326
246ac981
MG		 327enum {
328 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
329};
330
e126ba97
EC		 331enum {
332 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
333 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
334 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
335 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
336 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
337 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
338 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
339};
340
341enum {
e126ba97 342 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 343 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
344 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
345 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
346 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 347 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 348 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 349 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 350 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 351 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 352 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 353 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 354};
355
3cca2606
AS		 356enum {
357 MLX5_ROCE_VERSION_1 = 0,
358 MLX5_ROCE_VERSION_2 = 2,
359};
360
361enum {
362 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
363 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
364};
365
366enum {
367 MLX5_ROCE_L3_TYPE_IPV4 = 0,
368 MLX5_ROCE_L3_TYPE_IPV6 = 1,
369};
370
371enum {
372 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
373 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
374};
375
e126ba97
EC		 376enum {
377 MLX5_OPCODE_NOP = 0x00,
378 MLX5_OPCODE_SEND_INVAL = 0x01,
379 MLX5_OPCODE_RDMA_WRITE = 0x08,
380 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
381 MLX5_OPCODE_SEND = 0x0a,
382 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 383 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 384 MLX5_OPCODE_RDMA_READ = 0x10,
385 MLX5_OPCODE_ATOMIC_CS = 0x11,
386 MLX5_OPCODE_ATOMIC_FA = 0x12,
387 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
388 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
389 MLX5_OPCODE_BIND_MW = 0x18,
390 MLX5_OPCODE_CONFIG_CMD = 0x1f,
391
392 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
393 MLX5_RECV_OPCODE_SEND = 0x01,
394 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
395 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
396
397 MLX5_CQE_OPCODE_ERROR = 0x1e,
398 MLX5_CQE_OPCODE_RESIZE = 0x16,
399
400 MLX5_OPCODE_SET_PSV = 0x20,
401 MLX5_OPCODE_GET_PSV = 0x21,
402 MLX5_OPCODE_CHECK_PSV = 0x22,
403 MLX5_OPCODE_RGET_PSV = 0x26,
404 MLX5_OPCODE_RCHECK_PSV = 0x27,
405
406 MLX5_OPCODE_UMR = 0x25,
407
408};
409
410enum {
411 MLX5_SET_PORT_RESET_QKEY = 0,
412 MLX5_SET_PORT_GUID0 = 16,
413 MLX5_SET_PORT_NODE_GUID = 17,
414 MLX5_SET_PORT_SYS_GUID = 18,
415 MLX5_SET_PORT_GID_TABLE = 19,
416 MLX5_SET_PORT_PKEY_TABLE = 20,
417};
418
d8880795
TT		 419enum {
420 MLX5_BW_NO_LIMIT = 0,
421 MLX5_100_MBPS_UNIT = 3,
422 MLX5_GBPS_UNIT = 4,
423};
424
e126ba97
EC		 425enum {
426 MLX5_MAX_PAGE_SHIFT = 31
427};
428
87b8de49 429enum {
87b8de49
EC		 430 MLX5_CAP_OFF_CMDIF_CSUM = 46,
431};
432
986ef95e
SG		 433enum {
434 /*
435 * Max wqe size for rdma read is 512 bytes, so this
436 * limits our max_sge_rd as the wqe needs to fit:
437 * - ctrl segment (16 bytes)
438 * - rdma segment (16 bytes)
439 * - scatter elements (16 bytes each)
440 */
441 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
442};
443
e420f0c0
HE		 444enum mlx5_odp_transport_cap_bits {
445 MLX5_ODP_SUPPORT_SEND = 1 << 31,
446 MLX5_ODP_SUPPORT_RECV = 1 << 30,
447 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
448 MLX5_ODP_SUPPORT_READ = 1 << 28,
449};
450
451struct mlx5_odp_caps {
452 char reserved[0x10];
453 struct {
454 __be32 rc_odp_caps;
455 __be32 uc_odp_caps;
456 __be32 ud_odp_caps;
457 } per_transport_caps;
458 char reserved2[0xe4];
459};
460
e126ba97
EC		 461struct mlx5_cmd_layout {
462 u8 type;
463 u8 rsvd0[3];
464 __be32 inlen;
465 __be64 in_ptr;
466 __be32 in[4];
467 __be32 out[4];
468 __be64 out_ptr;
469 __be32 outlen;
470 u8 token;
471 u8 sig;
472 u8 rsvd1;
473 u8 status_own;
474};
475
e126ba97
EC		 476struct health_buffer {
477 __be32 assert_var[5];
478 __be32 rsvd0[3];
479 __be32 assert_exit_ptr;
480 __be32 assert_callra;
481 __be32 rsvd1[2];
482 __be32 fw_ver;
483 __be32 hw_id;
484 __be32 rsvd2;
485 u8 irisc_index;
486 u8 synd;
78ccb258 487 __be16 ext_synd;
e126ba97
EC		 488};
489
490struct mlx5_init_seg {
491 __be32 fw_rev;
492 __be32 cmdif_rev_fw_sub;
493 __be32 rsvd0[2];
494 __be32 cmdq_addr_h;
495 __be32 cmdq_addr_l_sz;
496 __be32 cmd_dbell;
e3297246
EC		 497 __be32 rsvd1[120];
498 __be32 initializing;
e126ba97 499 struct health_buffer health;
b0844444
EBE		 500 __be32 rsvd2[880];
501 __be32 internal_timer_h;
502 __be32 internal_timer_l;
b368d7cb 503 __be32 rsvd3[2];
e126ba97 504 __be32 health_counter;
b0844444 505 __be32 rsvd4[1019];
e126ba97
EC		 506 __be64 ieee1588_clk;
507 __be32 ieee1588_clk_type;
508 __be32 clr_intx;
509};
510
511struct mlx5_eqe_comp {
512 __be32 reserved[6];
513 __be32 cqn;
514};
515
516struct mlx5_eqe_qp_srq {
e2013b21 517 __be32 reserved1[5];
518 u8 type;
519 u8 reserved2[3];
e126ba97
EC		 520 __be32 qp_srq_n;
521};
522
523struct mlx5_eqe_cq_err {
524 __be32 cqn;
525 u8 reserved1[7];
526 u8 syndrome;
527};
528
e126ba97
EC		 529struct mlx5_eqe_port_state {
530 u8 reserved0[8];
531 u8 port;
532};
533
534struct mlx5_eqe_gpio {
535 __be32 reserved0[2];
536 __be64 gpio_event;
537};
538
539struct mlx5_eqe_congestion {
540 u8 type;
541 u8 rsvd0;
542 u8 congestion_level;
543};
544
545struct mlx5_eqe_stall_vl {
546 u8 rsvd0[3];
547 u8 port_vl;
548};
549
550struct mlx5_eqe_cmd {
551 __be32 vector;
552 __be32 rsvd[6];
553};
554
555struct mlx5_eqe_page_req {
556 u8 rsvd0[2];
557 __be16 func_id;
0a324f31
ML		 558 __be32 num_pages;
559 __be32 rsvd1[5];
e126ba97
EC		 560};
561
e420f0c0
HE		 562struct mlx5_eqe_page_fault {
563 __be32 bytes_committed;
564 union {
565 struct {
566 u16 reserved1;
567 __be16 wqe_index;
568 u16 reserved2;
569 __be16 packet_length;
d9aaed83
AK		 570 __be32 token;
571 u8 reserved4[8];
572 __be32 pftype_wq;
e420f0c0
HE		 573 } __packed wqe;
574 struct {
575 __be32 r_key;
576 u16 reserved1;
577 __be16 packet_length;
578 __be32 rdma_op_len;
579 __be64 rdma_va;
d9aaed83 580 __be32 pftype_token;
e420f0c0
HE		 581 } __packed rdma;
582 } __packed;
e420f0c0
HE		 583} __packed;
584
073bb189
SM		 585struct mlx5_eqe_vport_change {
586 u8 rsvd0[2];
587 __be16 vport_num;
588 __be32 rsvd1[6];
589} __packed;
590
4ce3bf2f
HN		 591struct mlx5_eqe_port_module {
592 u8 reserved_at_0[1];
593 u8 module;
594 u8 reserved_at_2[1];
595 u8 module_status;
596 u8 reserved_at_4[2];
597 u8 error_type;
598} __packed;
599
f9a1ef72
EE		 600struct mlx5_eqe_pps {
601 u8 rsvd0[3];
602 u8 pin;
603 u8 rsvd1[4];
604 union {
605 struct {
606 __be32 time_sec;
607 __be32 time_nsec;
608 };
609 struct {
610 __be64 time_stamp;
611 };
612 };
613 u8 rsvd2[12];
614} __packed;
615
e126ba97
EC		 616union ev_data {
617 __be32 raw[7];
618 struct mlx5_eqe_cmd cmd;
619 struct mlx5_eqe_comp comp;
620 struct mlx5_eqe_qp_srq qp_srq;
621 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 622 struct mlx5_eqe_port_state port;
623 struct mlx5_eqe_gpio gpio;
624 struct mlx5_eqe_congestion cong;
625 struct mlx5_eqe_stall_vl stall_vl;
626 struct mlx5_eqe_page_req req_pages;
e420f0c0 627 struct mlx5_eqe_page_fault page_fault;
073bb189 628 struct mlx5_eqe_vport_change vport_change;
4ce3bf2f 629 struct mlx5_eqe_port_module port_module;
f9a1ef72 630 struct mlx5_eqe_pps pps;
e126ba97
EC		 631} __packed;
632
633struct mlx5_eqe {
634 u8 rsvd0;
635 u8 type;
636 u8 rsvd1;
637 u8 sub_type;
638 __be32 rsvd2[7];
639 union ev_data data;
640 __be16 rsvd3;
641 u8 signature;
642 u8 owner;
643} __packed;
644
645struct mlx5_cmd_prot_block {
646 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
647 u8 rsvd0[48];
648 __be64 next;
649 __be32 block_num;
650 u8 rsvd1;
651 u8 token;
652 u8 ctrl_sig;
653 u8 sig;
654};
655
e281682b
SM		 656enum {
657 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
658};
659
e126ba97
EC		 660struct mlx5_err_cqe {
661 u8 rsvd0[32];
662 __be32 srqn;
663 u8 rsvd1[18];
664 u8 vendor_err_synd;
665 u8 syndrome;
666 __be32 s_wqe_opcode_qpn;
667 __be16 wqe_counter;
668 u8 signature;
669 u8 op_own;
670};
671
672struct mlx5_cqe64 {
1b223dd3
SM		 673 u8 outer_l3_tunneled;
674 u8 rsvd0;
675 __be16 wqe_id;
e281682b
SM		 676 u8 lro_tcppsh_abort_dupack;
677 u8 lro_min_ttl;
678 __be16 lro_tcp_win;
679 __be32 lro_ack_seq_num;
680 __be32 rss_hash_result;
681 u8 rss_hash_type;
e126ba97 682 u8 ml_path;
e281682b
SM		 683 u8 rsvd20[2];
684 __be16 check_sum;
e126ba97
EC		 685 __be16 slid;
686 __be32 flags_rqpn;
e281682b 687 u8 hds_ip_ext;
1b223dd3 688 u8 l4_l3_hdr_type;
e281682b
SM		 689 __be16 vlan_info;
690 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 691 __be32 imm_inval_pkey;
692 u8 rsvd40[4];
693 __be32 byte_cnt;
b0844444
EBE		 694 __be32 timestamp_h;
695 __be32 timestamp_l;
e126ba97
EC		 696 __be32 sop_drop_qpn;
697 __be16 wqe_counter;
698 u8 signature;
699 u8 op_own;
700};
701
7219ab34
TT		 702struct mlx5_mini_cqe8 {
703 union {
704 __be32 rx_hash_result;
705 struct {
706 __be16 checksum;
707 __be16 rsvd;
708 };
709 struct {
710 __be16 wqe_counter;
711 u8 s_wqe_opcode;
712 u8 reserved;
713 } s_wqe_info;
714 };
715 __be32 byte_cnt;
716};
717
718enum {
719 MLX5_NO_INLINE_DATA,
720 MLX5_INLINE_DATA32_SEG,
721 MLX5_INLINE_DATA64_SEG,
722 MLX5_COMPRESSED,
723};
724
725enum {
726 MLX5_CQE_FORMAT_CSUM = 0x1,
727};
728
729#define MLX5_MINI_CQE_ARRAY_SIZE 8
730
731static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
732{
733 return (cqe->op_own >> 2) & 0x3;
734}
735
604acb19 736static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
e281682b
SM		 737{
738 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
739}
740
741static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
742{
1b223dd3
SM		 743 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
744}
745
746static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
747{
748 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
749}
750
751static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
752{
753 return cqe->outer_l3_tunneled & 0x1;
e281682b
SM		 754}
755
756static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
757{
1b223dd3 758 return !!(cqe->l4_l3_hdr_type & 0x1);
e281682b
SM		 759}
760
b0844444
EBE		 761static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
762{
763 u32 hi, lo;
764
765 hi = be32_to_cpu(cqe->timestamp_h);
766 lo = be32_to_cpu(cqe->timestamp_l);
767
768 return (u64)lo | ((u64)hi << 32);
769}
770
461017cb
TT		 771struct mpwrq_cqe_bc {
772 __be16 filler_consumed_strides;
773 __be16 byte_cnt;
774};
775
776static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
777{
778 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
779
780 return be16_to_cpu(bc->byte_cnt);
781}
782
783static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
784{
785 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
786}
787
788static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
789{
790 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
791
792 return mpwrq_get_cqe_bc_consumed_strides(bc);
793}
794
795static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
796{
797 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
798
799 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
800}
801
802static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
803{
804 return be16_to_cpu(cqe->wqe_counter);
805}
806
e281682b
SM		 807enum {
808 CQE_L4_HDR_TYPE_NONE = 0x0,
809 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
810 CQE_L4_HDR_TYPE_UDP = 0x2,
811 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
812 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
813};
814
815enum {
12e8b570
JDB		 816 CQE_RSS_HTYPE_IP = 0x3 << 2,
817 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
818 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
819 */
820 CQE_RSS_HTYPE_L4 = 0x3 << 6,
821 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
822 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
823 */
e281682b
SM		 824};
825
cb34be6d
AS		 826enum {
827 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
828 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
829 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
830};
831
e281682b
SM		 832enum {
833 CQE_L2_OK = 1 << 0,
834 CQE_L3_OK = 1 << 1,
835 CQE_L4_OK = 1 << 2,
836};
837
d5436ba0
SG		 838struct mlx5_sig_err_cqe {
839 u8 rsvd0[16];
840 __be32 expected_trans_sig;
841 __be32 actual_trans_sig;
842 __be32 expected_reftag;
843 __be32 actual_reftag;
844 __be16 syndrome;
845 u8 rsvd22[2];
846 __be32 mkey;
847 __be64 err_offset;
848 u8 rsvd30[8];
849 __be32 qpn;
850 u8 rsvd38[2];
851 u8 signature;
852 u8 op_own;
853};
854
e126ba97
EC		 855struct mlx5_wqe_srq_next_seg {
856 u8 rsvd0[2];
857 __be16 next_wqe_index;
858 u8 signature;
859 u8 rsvd1[11];
860};
861
862union mlx5_ext_cqe {
863 struct ib_grh grh;
864 u8 inl[64];
865};
866
867struct mlx5_cqe128 {
868 union mlx5_ext_cqe inl_grh;
869 struct mlx5_cqe64 cqe64;
870};
871
968e78dd
HE		 872enum {
873 MLX5_MKEY_STATUS_FREE = 1 << 6,
874};
875
ec22eb53
SM		 876enum {
877 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
878 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
879 MLX5_MKEY_BSF_EN = 1 << 30,
880 MLX5_MKEY_LEN64 = 1 << 31,
881};
882
e126ba97
EC		 883struct mlx5_mkey_seg {
884 /* This is a two bit field occupying bits 31-30.
885 * bit 31 is always 0,
886 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
887 */
888 u8 status;
889 u8 pcie_control;
890 u8 flags;
891 u8 version;
892 __be32 qpn_mkey7_0;
893 u8 rsvd1[4];
894 __be32 flags_pd;
895 __be64 start_addr;
896 __be64 len;
897 __be32 bsfs_octo_size;
898 u8 rsvd2[16];
899 __be32 xlt_oct_size;
900 u8 rsvd3[3];
901 u8 log2_page_size;
902 u8 rsvd4[4];
903};
904
e126ba97
EC		 905#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
906
907enum {
908 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
909};
910
e281682b
SM		 911enum {
912 VPORT_STATE_DOWN = 0x0,
913 VPORT_STATE_UP = 0x1,
914};
915
81848731
SM		 916enum {
917 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
918 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
919 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
920};
921
e281682b
SM		 922enum {
923 MLX5_L3_PROT_TYPE_IPV4 = 0,
924 MLX5_L3_PROT_TYPE_IPV6 = 1,
925};
926
927enum {
928 MLX5_L4_PROT_TYPE_TCP = 0,
929 MLX5_L4_PROT_TYPE_UDP = 1,
930};
931
932enum {
933 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
934 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
935 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
936 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
937 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
938};
939
940enum {
941 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
942 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
943 MLX5_MATCH_INNER_HEADERS = 1 << 2,
944
945};
946
947enum {
948 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
949 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
950};
951
952enum {
953 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
954 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
955 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
956};
957
e16aea27
SM		 958enum mlx5_list_type {
959 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
960 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
961 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
962};
963
e281682b
SM		 964enum {
965 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
966 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
967};
968
928cfe87
TT		 969enum mlx5_wol_mode {
970 MLX5_WOL_DISABLE = 0,
971 MLX5_WOL_SECURED_MAGIC = 1 << 1,
972 MLX5_WOL_MAGIC = 1 << 2,
973 MLX5_WOL_ARP = 1 << 3,
974 MLX5_WOL_BROADCAST = 1 << 4,
975 MLX5_WOL_MULTICAST = 1 << 5,
976 MLX5_WOL_UNICAST = 1 << 6,
977 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
978};
979
938fe83c
SM		 980/* MLX5 DEV CAPs */
981
982/* TODO: EAT.ME */
983enum mlx5_cap_mode {
984 HCA_CAP_OPMOD_GET_MAX = 0,
985 HCA_CAP_OPMOD_GET_CUR = 1,
986};
987
988enum mlx5_cap_type {
989 MLX5_CAP_GENERAL = 0,
990 MLX5_CAP_ETHERNET_OFFLOADS,
991 MLX5_CAP_ODP,
992 MLX5_CAP_ATOMIC,
993 MLX5_CAP_ROCE,
994 MLX5_CAP_IPOIB_OFFLOADS,
4ce749bd 995 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
938fe83c 996 MLX5_CAP_FLOW_TABLE,
495716b1 997 MLX5_CAP_ESWITCH_FLOW_TABLE,
d6666753 998 MLX5_CAP_ESWITCH,
3f0393a5
SG		 999 MLX5_CAP_RESERVED,
1000 MLX5_CAP_VECTOR_CALC,
1466cc5b 1001 MLX5_CAP_QOS,
938fe83c
SM		 1002 /* NUM OF CAP Types */
1003 MLX5_CAP_NUM
1004};
1005
cfdcbcea
GP		 1006enum mlx5_pcam_reg_groups {
1007 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1008};
1009
1010enum mlx5_pcam_feature_groups {
1011 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1012};
1013
1014enum mlx5_mcam_reg_groups {
1015 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1016};
1017
1018enum mlx5_mcam_feature_groups {
1019 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1020};
1021
c02762eb
HN		 1022enum mlx5_qcam_reg_groups {
1023 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1024};
1025
1026enum mlx5_qcam_feature_groups {
1027 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1028};
1029
938fe83c
SM		 1030/* GET Dev Caps macros */
1031#define MLX5_CAP_GEN(mdev, cap) \
701052c5 1032 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
938fe83c
SM		 1033
1034#define MLX5_CAP_GEN_MAX(mdev, cap) \
701052c5 1035 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
938fe83c
SM		 1036
1037#define MLX5_CAP_ETH(mdev, cap) \
1038 MLX5_GET(per_protocol_networking_offload_caps,\
701052c5 1039 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
938fe83c
SM		 1040
1041#define MLX5_CAP_ETH_MAX(mdev, cap) \
1042 MLX5_GET(per_protocol_networking_offload_caps,\
701052c5 1043 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
938fe83c 1044
4ce749bd
YH		 1045#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1046 MLX5_GET(per_protocol_networking_offload_caps,\
1047 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1048
938fe83c 1049#define MLX5_CAP_ROCE(mdev, cap) \
701052c5 1050 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
938fe83c
SM		 1051
1052#define MLX5_CAP_ROCE_MAX(mdev, cap) \
701052c5 1053 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
938fe83c
SM		 1054
1055#define MLX5_CAP_ATOMIC(mdev, cap) \
701052c5 1056 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
938fe83c
SM		 1057
1058#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
701052c5 1059 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
938fe83c
SM		 1060
1061#define MLX5_CAP_FLOWTABLE(mdev, cap) \
701052c5 1062 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
938fe83c
SM		 1063
1064#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
701052c5 1065 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
938fe83c 1066
876d634d
MG		 1067#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1068 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1069
1070#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1071 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1072
cea824d4
MG		 1073#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1074 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1075
1076#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1077 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1078
1079#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1080 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1081
1082#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1083 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1084
495716b1
SM		 1085#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1086 MLX5_GET(flow_table_eswitch_cap, \
701052c5 1087 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
495716b1
SM		 1088
1089#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1090 MLX5_GET(flow_table_eswitch_cap, \
701052c5 1091 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
495716b1
SM		 1092
1093#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1094 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1095
1096#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1097 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1098
efdc810b
MHY		 1099#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1100 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1101
1102#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1103 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1104
1105#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1106 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1107
1108#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1109 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1110
d6666753
SM		 1111#define MLX5_CAP_ESW(mdev, cap) \
1112 MLX5_GET(e_switch_cap, \
701052c5 1113 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
d6666753
SM		 1114
1115#define MLX5_CAP_ESW_MAX(mdev, cap) \
1116 MLX5_GET(e_switch_cap, \
701052c5 1117 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
d6666753 1118
938fe83c 1119#define MLX5_CAP_ODP(mdev, cap)\
701052c5 1120 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
938fe83c 1121
3f0393a5
SG		 1122#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1123 MLX5_GET(vector_calc_cap, \
701052c5 1124 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
3f0393a5 1125
1466cc5b 1126#define MLX5_CAP_QOS(mdev, cap)\
701052c5 1127 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1466cc5b 1128
71862561
GP		 1129#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1130 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1131
0ab87743
OG		 1132#define MLX5_CAP_MCAM_REG(mdev, reg) \
1133 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1134
71862561
GP		 1135#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1136 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1137
c02762eb
HN		 1138#define MLX5_CAP_QCAM_REG(mdev, fld) \
1139 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1140
1141#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1142 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1143
e29341fb 1144#define MLX5_CAP_FPGA(mdev, cap) \
99d3cd27 1145 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
e29341fb 1146
a9956d35 1147#define MLX5_CAP64_FPGA(mdev, cap) \
99d3cd27 1148 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
a9956d35 1149
f62b8bb8
AV		 1150enum {
1151 MLX5_CMD_STAT_OK = 0x0,
1152 MLX5_CMD_STAT_INT_ERR = 0x1,
1153 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1154 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1155 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1156 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1157 MLX5_CMD_STAT_RES_BUSY = 0x6,
1158 MLX5_CMD_STAT_LIM_ERR = 0x8,
1159 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1160 MLX5_CMD_STAT_IX_ERR = 0xa,
1161 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1162 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1163 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1164 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1165 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1166 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1167};
1168
efea389d
GP		 1169enum {
1170 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1171 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1172 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1173 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1174 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1175 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1c64bf6f 1176 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
121fcdc8 1177 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
d8dc0508 1178 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1c64bf6f 1179 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
efea389d
GP		 1180};
1181
8ed1a630
GP		 1182enum {
1183 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1184};
1185
707c4602
MD		 1186static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1187{
1188 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1189 return 0;
1190 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1191}
1192
35d19011
MG		 1193#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1194#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1195#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1196#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1197 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1198 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
4cbdd30e 1199
e126ba97 1200#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)