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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
8c2d2b87 | 36 | #include <linux/auxiliary_bus.h> |
574e2af7 | 37 | #include <linux/if_ether.h> |
225c7b1f RD |
38 | #include <linux/pci.h> |
39 | #include <linux/completion.h> | |
40 | #include <linux/radix-tree.h> | |
d9236c3f | 41 | #include <linux/cpu_rmap.h> |
48ea526a | 42 | #include <linux/crash_dump.h> |
225c7b1f | 43 | |
ff61b5e3 | 44 | #include <linux/refcount.h> |
225c7b1f | 45 | |
74d23cc7 | 46 | #include <linux/timecounter.h> |
ec693d47 | 47 | |
85743f1e HN |
48 | #define DEFAULT_UAR_PAGE_SHIFT 12 |
49 | ||
a442c2c3 | 50 | #define MAX_MSIX 128 |
0b7ca5a9 | 51 | #define MIN_MSIX_P_PORT 5 |
c66fa19c MB |
52 | #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ |
53 | (dev_cap).num_ports * MIN_MSIX_P_PORT) | |
0b7ca5a9 | 54 | |
523ece88 EE |
55 | #define MLX4_MAX_100M_UNITS_VAL 255 /* |
56 | * work around: can't set values | |
57 | * greater then this value when | |
58 | * using 100 Mbps units. | |
59 | */ | |
60 | #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ | |
61 | #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ | |
62 | #define MLX4_RATELIMIT_DEFAULT 0x00ff | |
63 | ||
6ee51a4e | 64 | #define MLX4_ROCE_MAX_GIDS 128 |
b6ffaeff | 65 | #define MLX4_ROCE_PF_GIDS 16 |
6ee51a4e | 66 | |
225c7b1f RD |
67 | enum { |
68 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 69 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
70 | MLX4_FLAG_MASTER = 1 << 2, |
71 | MLX4_FLAG_SLAVE = 1 << 3, | |
72 | MLX4_FLAG_SRIOV = 1 << 4, | |
acddd5dd | 73 | MLX4_FLAG_OLD_REG_MAC = 1 << 6, |
fd10ed8e JM |
74 | MLX4_FLAG_BONDED = 1 << 7, |
75 | MLX4_FLAG_SECURE_HOST = 1 << 8, | |
225c7b1f RD |
76 | }; |
77 | ||
efcd235d JM |
78 | enum { |
79 | MLX4_PORT_CAP_IS_SM = 1 << 1, | |
80 | MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, | |
81 | }; | |
82 | ||
225c7b1f | 83 | enum { |
fc06573d | 84 | MLX4_MAX_PORTS = 2, |
e26be1bf MS |
85 | MLX4_MAX_PORT_PKEYS = 128, |
86 | MLX4_MAX_PORT_GIDS = 128 | |
225c7b1f RD |
87 | }; |
88 | ||
396f2feb JM |
89 | /* base qkey for use in sriov tunnel-qp/proxy-qp communication. |
90 | * These qkeys must not be allowed for general use. This is a 64k range, | |
91 | * and to test for violation, we use the mask (protect against future chg). | |
92 | */ | |
93 | #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) | |
94 | #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) | |
95 | ||
cd9281d8 JM |
96 | enum { |
97 | MLX4_BOARD_ID_LEN = 64 | |
98 | }; | |
99 | ||
623ed84b JM |
100 | enum { |
101 | MLX4_MAX_NUM_PF = 16, | |
de966c59 | 102 | MLX4_MAX_NUM_VF = 126, |
1ab95d37 | 103 | MLX4_MAX_NUM_VF_P_PORT = 64, |
5a2e87b1 | 104 | MLX4_MFUNC_MAX = 128, |
3fc929e2 | 105 | MLX4_MAX_EQ_NUM = 1024, |
623ed84b JM |
106 | MLX4_MFUNC_EQ_NUM = 4, |
107 | MLX4_MFUNC_MAX_EQES = 8, | |
108 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
109 | }; | |
110 | ||
8ac1ed79 | 111 | /* Driver supports 3 different device methods to manage traffic steering: |
0ff1fb65 HHZ |
112 | * -device managed - High level API for ib and eth flow steering. FW is |
113 | * managing flow steering tables. | |
c96d97f4 HHZ |
114 | * - B0 steering mode - Common low level API for ib and (if supported) eth. |
115 | * - A0 steering mode - Limited low level API for eth. In case of IB, | |
116 | * B0 mode is in use. | |
117 | */ | |
118 | enum { | |
119 | MLX4_STEERING_MODE_A0, | |
0ff1fb65 HHZ |
120 | MLX4_STEERING_MODE_B0, |
121 | MLX4_STEERING_MODE_DEVICE_MANAGED | |
c96d97f4 HHZ |
122 | }; |
123 | ||
7d077cd3 MB |
124 | enum { |
125 | MLX4_STEERING_DMFS_A0_DEFAULT, | |
126 | MLX4_STEERING_DMFS_A0_DYNAMIC, | |
127 | MLX4_STEERING_DMFS_A0_STATIC, | |
128 | MLX4_STEERING_DMFS_A0_DISABLE, | |
129 | MLX4_STEERING_DMFS_A0_NOT_SUPPORTED | |
130 | }; | |
131 | ||
c96d97f4 HHZ |
132 | static inline const char *mlx4_steering_mode_str(int steering_mode) |
133 | { | |
134 | switch (steering_mode) { | |
135 | case MLX4_STEERING_MODE_A0: | |
136 | return "A0 steering"; | |
137 | ||
138 | case MLX4_STEERING_MODE_B0: | |
139 | return "B0 steering"; | |
0ff1fb65 HHZ |
140 | |
141 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
142 | return "Device managed flow steering"; | |
143 | ||
c96d97f4 HHZ |
144 | default: |
145 | return "Unrecognize steering mode"; | |
146 | } | |
147 | } | |
148 | ||
7ffdf726 OG |
149 | enum { |
150 | MLX4_TUNNEL_OFFLOAD_MODE_NONE, | |
151 | MLX4_TUNNEL_OFFLOAD_MODE_VXLAN | |
152 | }; | |
153 | ||
225c7b1f | 154 | enum { |
52eafc68 OG |
155 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
156 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
157 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 158 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
159 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
160 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
161 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
162 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
163 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
164 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
165 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
166 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
167 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
168 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
169 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
170 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
171 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
172 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 173 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
174 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
175 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
176 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
177 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 178 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 | 179 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
802f42a8 | 180 | MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, |
540b3a39 | 181 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
00f5ce99 JM |
182 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
183 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | |
08ff3235 OG |
184 | MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, |
185 | MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 | |
225c7b1f RD |
186 | }; |
187 | ||
b3416f44 SP |
188 | enum { |
189 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, | |
190 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, | |
0ff1fb65 | 191 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, |
955154fa | 192 | MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, |
5930e8d0 | 193 | MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, |
3f7fb021 | 194 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
e6b6a231 | 195 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
b01978ca | 196 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
4de65803 | 197 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, |
4ba9920e LT |
198 | MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, |
199 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, | |
114840c3 | 200 | MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, |
77507aa2 | 201 | MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, |
adbc7ac5 | 202 | MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, |
a53e3e8c | 203 | MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, |
d475c95b | 204 | MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, |
7ae0e400 | 205 | MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, |
de966c59 | 206 | MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, |
7d077cd3 | 207 | MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, |
be6a6b43 | 208 | MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, |
59e14e32 | 209 | MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, |
d237baa1 SM |
210 | MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, |
211 | MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, | |
0b131561 | 212 | MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, |
d019fcb2 IS |
213 | MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, |
214 | MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, | |
3742cc65 | 215 | MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, |
51af33cf | 216 | MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, |
78500b8c | 217 | MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, |
77fc29c4 HHZ |
218 | MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, |
219 | MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, | |
9a892835 MG |
220 | MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, |
221 | MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, | |
d8ae9141 | 222 | MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33, |
0e451e88 | 223 | MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34, |
c7c122ed | 224 | MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35, |
7c3d21c8 | 225 | MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36, |
b9044ac8 | 226 | MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37, |
be599603 | 227 | MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38, |
e5c9a705 | 228 | MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1ULL << 39, |
e4567897 | 229 | MLX4_DEV_CAP_FLAG2_SW_CQ_INIT = 1ULL << 40, |
b3416f44 SP |
230 | }; |
231 | ||
ddae0349 | 232 | enum { |
d57febe1 MB |
233 | MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, |
234 | MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 | |
ddae0349 EE |
235 | }; |
236 | ||
55ad3592 YH |
237 | enum { |
238 | MLX4_VF_CAP_FLAG_RESET = 1 << 0 | |
239 | }; | |
240 | ||
ddae0349 EE |
241 | /* bit enums for an 8-bit flags field indicating special use |
242 | * QPs which require special handling in qp_reserve_range. | |
243 | * Currently, this only includes QPs used by the ETH interface, | |
244 | * where we expect to use blueflame. These QPs must not have | |
245 | * bits 6 and 7 set in their qp number. | |
246 | * | |
247 | * This enum may use only bits 0..7. | |
248 | */ | |
249 | enum { | |
d57febe1 | 250 | MLX4_RESERVE_A0_QP = 1 << 6, |
ddae0349 EE |
251 | MLX4_RESERVE_ETH_BF_QP = 1 << 7, |
252 | }; | |
253 | ||
08ff3235 OG |
254 | enum { |
255 | MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, | |
77507aa2 IS |
256 | MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, |
257 | MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, | |
258 | MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 | |
08ff3235 OG |
259 | }; |
260 | ||
08ff3235 | 261 | enum { |
77507aa2 | 262 | MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, |
7d077cd3 MB |
263 | MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, |
264 | MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 | |
08ff3235 OG |
265 | }; |
266 | ||
267 | ||
97285b78 MA |
268 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
269 | ||
95d04f07 | 270 | enum { |
804d6a89 | 271 | MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, |
95d04f07 RD |
272 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, |
273 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
274 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
275 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
276 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
d8ae9141 | 277 | MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19, |
59e14e32 | 278 | MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, |
09e05c3f | 279 | MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, |
95d04f07 RD |
280 | }; |
281 | ||
59e14e32 | 282 | enum { |
d8ae9141 MS |
283 | MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP, |
284 | MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2 | |
59e14e32 MS |
285 | }; |
286 | ||
225c7b1f RD |
287 | enum mlx4_event { |
288 | MLX4_EVENT_TYPE_COMP = 0x00, | |
289 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
290 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
291 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
292 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
293 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
294 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
295 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
296 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
297 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
298 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
299 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
300 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
301 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
302 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
303 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
304 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
305 | MLX4_EVENT_TYPE_CMD = 0x0a, |
306 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
307 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
fe6f700d | 308 | MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, |
5984be90 | 309 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
623ed84b | 310 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
00f5ce99 | 311 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
be6a6b43 | 312 | MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, |
623ed84b | 313 | MLX4_EVENT_TYPE_NONE = 0xff, |
225c7b1f RD |
314 | }; |
315 | ||
316 | enum { | |
317 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
318 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
319 | }; | |
320 | ||
be6a6b43 JM |
321 | enum { |
322 | MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, | |
323 | MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, | |
324 | }; | |
325 | ||
5984be90 JM |
326 | enum { |
327 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, | |
328 | }; | |
329 | ||
993c401e JM |
330 | enum slave_port_state { |
331 | SLAVE_PORT_DOWN = 0, | |
332 | SLAVE_PENDING_UP, | |
333 | SLAVE_PORT_UP, | |
334 | }; | |
335 | ||
336 | enum slave_port_gen_event { | |
337 | SLAVE_PORT_GEN_EVENT_DOWN = 0, | |
338 | SLAVE_PORT_GEN_EVENT_UP, | |
339 | SLAVE_PORT_GEN_EVENT_NONE, | |
340 | }; | |
341 | ||
342 | enum slave_port_state_event { | |
343 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
344 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP, | |
345 | MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, | |
346 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID, | |
347 | }; | |
348 | ||
225c7b1f RD |
349 | enum { |
350 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
351 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
352 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
353 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
804d6a89 SM |
354 | MLX4_PERM_ATOMIC = 1 << 14, |
355 | MLX4_PERM_BIND_MW = 1 << 15, | |
e630664c | 356 | MLX4_PERM_MASK = 0xFC00 |
225c7b1f RD |
357 | }; |
358 | ||
359 | enum { | |
360 | MLX4_OPCODE_NOP = 0x00, | |
361 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
362 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
363 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
364 | MLX4_OPCODE_SEND = 0x0a, | |
365 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
366 | MLX4_OPCODE_LSO = 0x0e, | |
367 | MLX4_OPCODE_RDMA_READ = 0x10, | |
368 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
369 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
370 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
371 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
372 | MLX4_OPCODE_BIND_MW = 0x18, |
373 | MLX4_OPCODE_FMR = 0x19, | |
374 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
375 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
376 | ||
377 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
378 | MLX4_RECV_OPCODE_SEND = 0x01, | |
379 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
380 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
381 | ||
382 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
383 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
384 | }; | |
385 | ||
386 | enum { | |
387 | MLX4_STAT_RATE_OFFSET = 5 | |
388 | }; | |
389 | ||
da995a8a | 390 | enum mlx4_protocol { |
0345584e YP |
391 | MLX4_PROT_IB_IPV6 = 0, |
392 | MLX4_PROT_ETH, | |
393 | MLX4_PROT_IB_IPV4, | |
394 | MLX4_PROT_FCOE | |
da995a8a AS |
395 | }; |
396 | ||
29bdc883 VS |
397 | enum { |
398 | MLX4_MTT_FLAG_PRESENT = 1 | |
399 | }; | |
400 | ||
93fc9e1b YP |
401 | enum mlx4_qp_region { |
402 | MLX4_QP_REGION_FW = 0, | |
d57febe1 MB |
403 | MLX4_QP_REGION_RSS_RAW_ETH, |
404 | MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, | |
93fc9e1b YP |
405 | MLX4_QP_REGION_ETH_ADDR, |
406 | MLX4_QP_REGION_FC_ADDR, | |
407 | MLX4_QP_REGION_FC_EXCH, | |
408 | MLX4_NUM_QP_REGION | |
409 | }; | |
410 | ||
7ff93f8b | 411 | enum mlx4_port_type { |
623ed84b | 412 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
413 | MLX4_PORT_TYPE_IB = 1, |
414 | MLX4_PORT_TYPE_ETH = 2, | |
415 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
416 | }; |
417 | ||
2a2336f8 YP |
418 | enum mlx4_special_vlan_idx { |
419 | MLX4_NO_VLAN_IDX = 0, | |
420 | MLX4_VLAN_MISS_IDX, | |
421 | MLX4_VLAN_REGULAR | |
422 | }; | |
423 | ||
0345584e YP |
424 | enum mlx4_steer_type { |
425 | MLX4_MC_STEER = 0, | |
426 | MLX4_UC_STEER, | |
427 | MLX4_NUM_STEERS | |
428 | }; | |
429 | ||
f3301870 MS |
430 | enum mlx4_resource_usage { |
431 | MLX4_RES_USAGE_NONE, | |
432 | MLX4_RES_USAGE_DRIVER, | |
433 | MLX4_RES_USAGE_USER_VERBS, | |
434 | }; | |
435 | ||
93fc9e1b YP |
436 | enum { |
437 | MLX4_NUM_FEXCH = 64 * 1024, | |
438 | }; | |
439 | ||
5a0fd094 EC |
440 | enum { |
441 | MLX4_MAX_FAST_REG_PAGES = 511, | |
442 | }; | |
443 | ||
a5e14ba3 SG |
444 | enum { |
445 | /* | |
446 | * Max wqe size for rdma read is 512 bytes, so this | |
447 | * limits our max_sge_rd as the wqe needs to fit: | |
448 | * - ctrl segment (16 bytes) | |
449 | * - rdma segment (16 bytes) | |
450 | * - scatter elements (16 bytes each) | |
451 | */ | |
452 | MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 | |
453 | }; | |
454 | ||
00f5ce99 JM |
455 | enum { |
456 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, | |
457 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, | |
458 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, | |
fd10ed8e | 459 | MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17, |
00f5ce99 JM |
460 | }; |
461 | ||
462 | /* Port mgmt change event handling */ | |
463 | enum { | |
464 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, | |
465 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, | |
466 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, | |
467 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, | |
468 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, | |
469 | }; | |
470 | ||
fd10ed8e JM |
471 | union sl2vl_tbl_to_u64 { |
472 | u8 sl8[8]; | |
473 | u64 sl64; | |
474 | }; | |
475 | ||
f6bc11e4 YH |
476 | enum { |
477 | MLX4_DEVICE_STATE_UP = 1 << 0, | |
478 | MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, | |
479 | }; | |
480 | ||
c69453e2 YH |
481 | enum { |
482 | MLX4_INTERFACE_STATE_UP = 1 << 0, | |
483 | MLX4_INTERFACE_STATE_DELETION = 1 << 1, | |
4cbe4dac | 484 | MLX4_INTERFACE_STATE_NOWAIT = 1 << 2, |
c69453e2 YH |
485 | }; |
486 | ||
00f5ce99 JM |
487 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ |
488 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) | |
489 | ||
32a173c7 SM |
490 | enum mlx4_module_id { |
491 | MLX4_MODULE_ID_SFP = 0x3, | |
492 | MLX4_MODULE_ID_QSFP = 0xC, | |
493 | MLX4_MODULE_ID_QSFP_PLUS = 0xD, | |
494 | MLX4_MODULE_ID_QSFP28 = 0x11, | |
495 | }; | |
496 | ||
fc31e256 OG |
497 | enum { /* rl */ |
498 | MLX4_QP_RATE_LIMIT_NONE = 0, | |
499 | MLX4_QP_RATE_LIMIT_KBS = 1, | |
500 | MLX4_QP_RATE_LIMIT_MBS = 2, | |
501 | MLX4_QP_RATE_LIMIT_GBS = 3 | |
502 | }; | |
503 | ||
504 | struct mlx4_rate_limit_caps { | |
505 | u16 num_rates; /* Number of different rates */ | |
506 | u8 min_unit; | |
507 | u16 min_val; | |
508 | u8 max_unit; | |
509 | u16 max_val; | |
510 | }; | |
511 | ||
ea54b10c JM |
512 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
513 | { | |
514 | return (major << 32) | (minor << 16) | subminor; | |
515 | } | |
516 | ||
3fc929e2 | 517 | struct mlx4_phys_caps { |
6634961c JM |
518 | u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; |
519 | u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; | |
3fc929e2 | 520 | u32 num_phys_eqs; |
47605df9 JM |
521 | u32 base_sqpn; |
522 | u32 base_proxy_sqpn; | |
523 | u32 base_tunnel_sqpn; | |
3fc929e2 MA |
524 | }; |
525 | ||
c73c8b1e EBE |
526 | struct mlx4_spec_qps { |
527 | u32 qp0_qkey; | |
528 | u32 qp0_proxy; | |
529 | u32 qp0_tunnel; | |
530 | u32 qp1_proxy; | |
531 | u32 qp1_tunnel; | |
532 | }; | |
533 | ||
225c7b1f RD |
534 | struct mlx4_caps { |
535 | u64 fw_ver; | |
623ed84b | 536 | u32 function; |
225c7b1f | 537 | int num_ports; |
5ae2a7a8 | 538 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 539 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 540 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
541 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
542 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
543 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
544 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
545 | int trans_type[MLX4_MAX_PORTS + 1]; |
546 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
547 | int wavelength[MLX4_MAX_PORTS + 1]; | |
548 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
549 | int local_ca_ack_delay; |
550 | int num_uars; | |
f5311ac1 | 551 | u32 uar_page_size; |
225c7b1f RD |
552 | int bf_reg_size; |
553 | int bf_regs_per_page; | |
554 | int max_sq_sg; | |
555 | int max_rq_sg; | |
556 | int num_qps; | |
557 | int max_wqes; | |
558 | int max_sq_desc_sz; | |
559 | int max_rq_desc_sz; | |
560 | int max_qp_init_rdma; | |
561 | int max_qp_dest_rdma; | |
af7d5185 | 562 | int max_tc_eth; |
c73c8b1e | 563 | struct mlx4_spec_qps *spec_qps; |
225c7b1f RD |
564 | int num_srqs; |
565 | int max_srq_wqes; | |
566 | int max_srq_sge; | |
567 | int reserved_srqs; | |
568 | int num_cqs; | |
569 | int max_cqes; | |
570 | int reserved_cqs; | |
7ae0e400 | 571 | int num_sys_eqs; |
225c7b1f RD |
572 | int num_eqs; |
573 | int reserved_eqs; | |
b8dd786f | 574 | int num_comp_vectors; |
225c7b1f | 575 | int num_mpts; |
2b8fb286 | 576 | int num_mtts; |
225c7b1f RD |
577 | int fmr_reserved_mtts; |
578 | int reserved_mtts; | |
579 | int reserved_mrws; | |
580 | int reserved_uars; | |
581 | int num_mgms; | |
582 | int num_amgms; | |
583 | int reserved_mcgs; | |
584 | int num_qp_per_mgm; | |
c96d97f4 | 585 | int steering_mode; |
7d077cd3 | 586 | int dmfs_high_steer_mode; |
0ff1fb65 | 587 | int fs_log_max_ucast_qp_range_size; |
225c7b1f RD |
588 | int num_pds; |
589 | int reserved_pds; | |
012a8ff5 SH |
590 | int max_xrcds; |
591 | int reserved_xrcds; | |
225c7b1f | 592 | int mtt_entry_sz; |
149983af | 593 | u32 max_msg_sz; |
225c7b1f | 594 | u32 page_size_cap; |
52eafc68 | 595 | u64 flags; |
b3416f44 | 596 | u64 flags2; |
95d04f07 RD |
597 | u32 bmme_flags; |
598 | u32 reserved_lkey; | |
225c7b1f | 599 | u16 stat_rate_support; |
5ae2a7a8 | 600 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 601 | int max_gso_sz; |
b3416f44 | 602 | int max_rss_tbl_sz; |
93fc9e1b YP |
603 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
604 | int reserved_qps; | |
605 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
606 | int log_num_macs; | |
607 | int log_num_vlans; | |
7ff93f8b YP |
608 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
609 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
610 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
611 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 612 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 613 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 614 | u32 max_counters; |
096335b3 | 615 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
1ffeb2eb | 616 | u16 sqp_demux; |
08ff3235 OG |
617 | u32 eqe_size; |
618 | u32 cqe_size; | |
619 | u8 eqe_factor; | |
620 | u32 userspace_caps; /* userspace must be aware of these */ | |
621 | u32 function_caps; /* VFs must be aware of these */ | |
ddd8a6c1 | 622 | u16 hca_core_clock; |
8e1a28e8 | 623 | u64 phys_port_id[MLX4_MAX_PORTS + 1]; |
7ffdf726 | 624 | int tunnel_offload_mode; |
f8c6455b | 625 | u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; |
77fc29c4 | 626 | u8 phv_bit[MLX4_MAX_PORTS + 1]; |
ddae0349 | 627 | u8 alloc_res_qp_mask; |
7d077cd3 MB |
628 | u32 dmfs_high_rate_qpn_base; |
629 | u32 dmfs_high_rate_qpn_range; | |
55ad3592 | 630 | u32 vf_caps; |
c994f778 | 631 | bool wol_port[MLX4_MAX_PORTS + 1]; |
fc31e256 | 632 | struct mlx4_rate_limit_caps rl_caps; |
523f9eb1 | 633 | u32 health_buffer_addrs; |
404e5a12 | 634 | bool map_clock_to_user; |
225c7b1f RD |
635 | }; |
636 | ||
637 | struct mlx4_buf_list { | |
638 | void *buf; | |
639 | dma_addr_t map; | |
640 | }; | |
641 | ||
642 | struct mlx4_buf { | |
b57aacfa RD |
643 | struct mlx4_buf_list direct; |
644 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
645 | int nbufs; |
646 | int npages; | |
647 | int page_shift; | |
648 | }; | |
649 | ||
650 | struct mlx4_mtt { | |
2b8fb286 | 651 | u32 offset; |
225c7b1f RD |
652 | int order; |
653 | int page_shift; | |
654 | }; | |
655 | ||
6296883c YP |
656 | enum { |
657 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
658 | }; | |
659 | ||
660 | struct mlx4_db_pgdir { | |
661 | struct list_head list; | |
662 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
663 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
664 | unsigned long *bits[2]; | |
665 | __be32 *db_page; | |
666 | dma_addr_t db_dma; | |
667 | }; | |
668 | ||
669 | struct mlx4_ib_user_db_page; | |
670 | ||
671 | struct mlx4_db { | |
672 | __be32 *db; | |
673 | union { | |
674 | struct mlx4_db_pgdir *pgdir; | |
675 | struct mlx4_ib_user_db_page *user_page; | |
676 | } u; | |
677 | dma_addr_t dma; | |
678 | int index; | |
679 | int order; | |
680 | }; | |
681 | ||
38ae6a53 YP |
682 | struct mlx4_hwq_resources { |
683 | struct mlx4_db db; | |
684 | struct mlx4_mtt mtt; | |
685 | struct mlx4_buf buf; | |
686 | }; | |
687 | ||
225c7b1f RD |
688 | struct mlx4_mr { |
689 | struct mlx4_mtt mtt; | |
690 | u64 iova; | |
691 | u64 size; | |
692 | u32 key; | |
693 | u32 pd; | |
694 | u32 access; | |
695 | int enabled; | |
696 | }; | |
697 | ||
804d6a89 SM |
698 | enum mlx4_mw_type { |
699 | MLX4_MW_TYPE_1 = 1, | |
700 | MLX4_MW_TYPE_2 = 2, | |
701 | }; | |
702 | ||
703 | struct mlx4_mw { | |
704 | u32 key; | |
705 | u32 pd; | |
706 | enum mlx4_mw_type type; | |
707 | int enabled; | |
708 | }; | |
709 | ||
225c7b1f RD |
710 | struct mlx4_uar { |
711 | unsigned long pfn; | |
712 | int index; | |
c1b43dca EC |
713 | struct list_head bf_list; |
714 | unsigned free_bf_bmap; | |
715 | void __iomem *map; | |
716 | void __iomem *bf_map; | |
717 | }; | |
718 | ||
719 | struct mlx4_bf { | |
7dfa4b41 | 720 | unsigned int offset; |
c1b43dca EC |
721 | int buf_size; |
722 | struct mlx4_uar *uar; | |
723 | void __iomem *reg; | |
225c7b1f RD |
724 | }; |
725 | ||
726 | struct mlx4_cq { | |
727 | void (*comp) (struct mlx4_cq *); | |
728 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
729 | ||
730 | struct mlx4_uar *uar; | |
731 | ||
732 | u32 cons_index; | |
733 | ||
2eacc23c | 734 | u16 irq; |
225c7b1f RD |
735 | __be32 *set_ci_db; |
736 | __be32 *arm_db; | |
737 | int arm_sn; | |
738 | ||
739 | int cqn; | |
b8dd786f | 740 | unsigned vector; |
225c7b1f | 741 | |
ff61b5e3 | 742 | refcount_t refcount; |
225c7b1f | 743 | struct completion free; |
3dca0f42 MB |
744 | struct { |
745 | struct list_head list; | |
746 | void (*comp)(struct mlx4_cq *); | |
747 | void *priv; | |
748 | } tasklet_ctx; | |
35f05dab YH |
749 | int reset_notify_added; |
750 | struct list_head reset_notify; | |
f3301870 | 751 | u8 usage; |
225c7b1f RD |
752 | }; |
753 | ||
754 | struct mlx4_qp { | |
755 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
756 | ||
757 | int qpn; | |
758 | ||
0068895f | 759 | refcount_t refcount; |
225c7b1f | 760 | struct completion free; |
f3301870 | 761 | u8 usage; |
225c7b1f RD |
762 | }; |
763 | ||
764 | struct mlx4_srq { | |
765 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
766 | ||
767 | int srqn; | |
768 | int max; | |
769 | int max_gs; | |
770 | int wqe_shift; | |
771 | ||
17ac99b2 | 772 | refcount_t refcount; |
225c7b1f RD |
773 | struct completion free; |
774 | }; | |
775 | ||
776 | struct mlx4_av { | |
777 | __be32 port_pd; | |
778 | u8 reserved1; | |
779 | u8 g_slid; | |
780 | __be16 dlid; | |
781 | u8 reserved2; | |
782 | u8 gid_index; | |
783 | u8 stat_rate; | |
784 | u8 hop_limit; | |
785 | __be32 sl_tclass_flowlabel; | |
786 | u8 dgid[16]; | |
787 | }; | |
788 | ||
fa417f7b EC |
789 | struct mlx4_eth_av { |
790 | __be32 port_pd; | |
791 | u8 reserved1; | |
792 | u8 smac_idx; | |
793 | u16 reserved2; | |
794 | u8 reserved3; | |
795 | u8 gid_index; | |
796 | u8 stat_rate; | |
797 | u8 hop_limit; | |
798 | __be32 sl_tclass_flowlabel; | |
799 | u8 dgid[16]; | |
5ea8bbfc JM |
800 | u8 s_mac[6]; |
801 | u8 reserved4[2]; | |
fa417f7b | 802 | __be16 vlan; |
574e2af7 | 803 | u8 mac[ETH_ALEN]; |
fa417f7b EC |
804 | }; |
805 | ||
806 | union mlx4_ext_av { | |
807 | struct mlx4_av ib; | |
808 | struct mlx4_eth_av eth; | |
809 | }; | |
810 | ||
9616982f EBE |
811 | /* Counters should be saturate once they reach their maximum value */ |
812 | #define ASSIGN_32BIT_COUNTER(counter, value) do { \ | |
813 | if ((value) > U32_MAX) \ | |
814 | counter = cpu_to_be32(U32_MAX); \ | |
815 | else \ | |
816 | counter = cpu_to_be32(value); \ | |
817 | } while (0) | |
818 | ||
f2a3f6a3 OG |
819 | struct mlx4_counter { |
820 | u8 reserved1[3]; | |
821 | u8 counter_mode; | |
822 | __be32 num_ifc; | |
823 | u32 reserved2[2]; | |
824 | __be64 rx_frames; | |
825 | __be64 rx_bytes; | |
826 | __be64 tx_frames; | |
827 | __be64 tx_bytes; | |
828 | }; | |
829 | ||
5a0d0a61 JM |
830 | struct mlx4_quotas { |
831 | int qp; | |
832 | int cq; | |
833 | int srq; | |
834 | int mpt; | |
835 | int mtt; | |
836 | int counter; | |
837 | int xrcd; | |
838 | }; | |
839 | ||
1ab95d37 MB |
840 | struct mlx4_vf_dev { |
841 | u8 min_port; | |
842 | u8 n_ports; | |
843 | }; | |
844 | ||
bedc989b | 845 | struct mlx4_fw_crdump { |
3c641ba4 | 846 | bool snapshot_enable; |
bedc989b AV |
847 | struct devlink_region *region_crspace; |
848 | struct devlink_region *region_fw_health; | |
849 | }; | |
850 | ||
4bfd2e6e DJ |
851 | enum mlx4_pci_status { |
852 | MLX4_PCI_STATUS_DISABLED, | |
853 | MLX4_PCI_STATUS_ENABLED, | |
854 | }; | |
855 | ||
872bf2fb | 856 | struct mlx4_dev_persistent { |
225c7b1f | 857 | struct pci_dev *pdev; |
872bf2fb YH |
858 | struct mlx4_dev *dev; |
859 | int nvfs[MLX4_MAX_PORTS + 1]; | |
860 | int num_vfs; | |
dd0eefe3 YH |
861 | enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; |
862 | enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; | |
ad9a0bf0 YH |
863 | struct work_struct catas_work; |
864 | struct workqueue_struct *catas_wq; | |
f6bc11e4 YH |
865 | struct mutex device_state_mutex; /* protect HW state */ |
866 | u8 state; | |
c69453e2 YH |
867 | struct mutex interface_state_mutex; /* protect SW state */ |
868 | u8 interface_state; | |
4bfd2e6e DJ |
869 | struct mutex pci_status_mutex; /* sync pci state */ |
870 | enum mlx4_pci_status pci_status; | |
bedc989b | 871 | struct mlx4_fw_crdump crdump; |
872bf2fb YH |
872 | }; |
873 | ||
874 | struct mlx4_dev { | |
875 | struct mlx4_dev_persistent *persist; | |
225c7b1f | 876 | unsigned long flags; |
623ed84b | 877 | unsigned long num_slaves; |
225c7b1f | 878 | struct mlx4_caps caps; |
3fc929e2 | 879 | struct mlx4_phys_caps phys_caps; |
5a0d0a61 | 880 | struct mlx4_quotas quotas; |
225c7b1f | 881 | struct radix_tree_root qp_table_tree; |
725c8999 | 882 | u8 rev_id; |
2b3ddf27 | 883 | u8 port_random_macs; |
cd9281d8 | 884 | char board_id[MLX4_BOARD_ID_LEN]; |
6e7136ed | 885 | int numa_node; |
3c439b55 | 886 | int oper_log_mgm_entry_size; |
592e49dd HHZ |
887 | u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; |
888 | u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; | |
1ab95d37 | 889 | struct mlx4_vf_dev *dev_vfs; |
85743f1e | 890 | u8 uar_page_shift; |
225c7b1f RD |
891 | }; |
892 | ||
8c2d2b87 PP |
893 | struct mlx4_adev { |
894 | struct auxiliary_device adev; | |
895 | struct mlx4_dev *mdev; | |
896 | int idx; | |
897 | }; | |
898 | ||
52033cfb MB |
899 | struct mlx4_clock_params { |
900 | u64 offset; | |
901 | u8 bar; | |
902 | u8 size; | |
903 | }; | |
904 | ||
00f5ce99 JM |
905 | struct mlx4_eqe { |
906 | u8 reserved1; | |
907 | u8 type; | |
908 | u8 reserved2; | |
909 | u8 subtype; | |
910 | union { | |
911 | u32 raw[6]; | |
912 | struct { | |
913 | __be32 cqn; | |
914 | } __packed comp; | |
915 | struct { | |
916 | u16 reserved1; | |
917 | __be16 token; | |
918 | u32 reserved2; | |
919 | u8 reserved3[3]; | |
920 | u8 status; | |
921 | __be64 out_param; | |
922 | } __packed cmd; | |
923 | struct { | |
924 | __be32 qpn; | |
925 | } __packed qp; | |
926 | struct { | |
927 | __be32 srqn; | |
928 | } __packed srq; | |
929 | struct { | |
930 | __be32 cqn; | |
931 | u32 reserved1; | |
932 | u8 reserved2[3]; | |
933 | u8 syndrome; | |
934 | } __packed cq_err; | |
935 | struct { | |
936 | u32 reserved1[2]; | |
937 | __be32 port; | |
938 | } __packed port_change; | |
939 | struct { | |
940 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 | |
941 | u32 reserved; | |
942 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; | |
943 | } __packed comm_channel_arm; | |
944 | struct { | |
945 | u8 port; | |
946 | u8 reserved[3]; | |
947 | __be64 mac; | |
948 | } __packed mac_update; | |
949 | struct { | |
950 | __be32 slave_id; | |
951 | } __packed flr_event; | |
952 | struct { | |
953 | __be16 current_temperature; | |
954 | __be16 warning_threshold; | |
955 | } __packed warming; | |
956 | struct { | |
957 | u8 reserved[3]; | |
958 | u8 port; | |
959 | union { | |
960 | struct { | |
961 | __be16 mstr_sm_lid; | |
962 | __be16 port_lid; | |
963 | __be32 changed_attr; | |
964 | u8 reserved[3]; | |
965 | u8 mstr_sm_sl; | |
966 | __be64 gid_prefix; | |
967 | } __packed port_info; | |
968 | struct { | |
969 | __be32 block_ptr; | |
970 | __be32 tbl_entries_mask; | |
971 | } __packed tbl_change_info; | |
fd10ed8e JM |
972 | struct { |
973 | u8 sl2vl_table[8]; | |
974 | } __packed sl2vl_tbl_change_info; | |
00f5ce99 JM |
975 | } params; |
976 | } __packed port_mgmt_change; | |
be6a6b43 JM |
977 | struct { |
978 | u8 reserved[3]; | |
979 | u8 port; | |
980 | u32 reserved1[5]; | |
981 | } __packed bad_cable; | |
00f5ce99 JM |
982 | } event; |
983 | u8 slave_id; | |
984 | u8 reserved3[2]; | |
985 | u8 owner; | |
986 | } __packed; | |
987 | ||
225c7b1f RD |
988 | struct mlx4_init_port_param { |
989 | int set_guid0; | |
990 | int set_node_guid; | |
991 | int set_si_guid; | |
992 | u16 mtu; | |
993 | int port_width_cap; | |
994 | u16 vl_cap; | |
995 | u16 max_gid; | |
996 | u16 max_pkey; | |
997 | u64 guid0; | |
998 | u64 node_guid; | |
999 | u64 si_guid; | |
1000 | }; | |
1001 | ||
32a173c7 SM |
1002 | #define MAD_IFC_DATA_SZ 192 |
1003 | /* MAD IFC Mailbox */ | |
1004 | struct mlx4_mad_ifc { | |
1005 | u8 base_version; | |
1006 | u8 mgmt_class; | |
1007 | u8 class_version; | |
1008 | u8 method; | |
1009 | __be16 status; | |
1010 | __be16 class_specific; | |
1011 | __be64 tid; | |
1012 | __be16 attr_id; | |
1013 | __be16 resv; | |
1014 | __be32 attr_mod; | |
1015 | __be64 mkey; | |
1016 | __be16 dr_slid; | |
1017 | __be16 dr_dlid; | |
1018 | u8 reserved[28]; | |
1019 | u8 data[MAD_IFC_DATA_SZ]; | |
1020 | } __packed; | |
1021 | ||
7ff93f8b YP |
1022 | #define mlx4_foreach_port(port, dev, type) \ |
1023 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 1024 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 1025 | |
65dab25d | 1026 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
d8ae9141 | 1027 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ |
65dab25d | 1028 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ |
dd77abf8 | 1029 | ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH)) |
623ed84b | 1030 | |
752a50ca | 1031 | #define MLX4_INVALID_SLAVE_ID 0xFF |
47d8417f | 1032 | #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) |
752a50ca | 1033 | |
00f5ce99 JM |
1034 | void handle_port_mgmt_change_event(struct work_struct *work); |
1035 | ||
2aca1172 JM |
1036 | static inline int mlx4_master_func_num(struct mlx4_dev *dev) |
1037 | { | |
1038 | return dev->caps.function; | |
1039 | } | |
1040 | ||
623ed84b JM |
1041 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
1042 | { | |
1043 | return dev->flags & MLX4_FLAG_MASTER; | |
1044 | } | |
1045 | ||
5a0d0a61 JM |
1046 | static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) |
1047 | { | |
1048 | return dev->phys_caps.base_sqpn + 8 + | |
1049 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); | |
1050 | } | |
1051 | ||
623ed84b JM |
1052 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) |
1053 | { | |
47605df9 | 1054 | return (qpn < dev->phys_caps.base_sqpn + 8 + |
d57febe1 MB |
1055 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && |
1056 | qpn >= dev->phys_caps.base_sqpn) || | |
1057 | (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); | |
e2c76824 JM |
1058 | } |
1059 | ||
1060 | static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) | |
1061 | { | |
47605df9 | 1062 | int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; |
e2c76824 | 1063 | |
47605df9 | 1064 | if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) |
e2c76824 JM |
1065 | return 1; |
1066 | ||
1067 | return 0; | |
623ed84b | 1068 | } |
fa417f7b | 1069 | |
623ed84b JM |
1070 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
1071 | { | |
1072 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
1073 | } | |
1074 | ||
1075 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
1076 | { | |
1077 | return dev->flags & MLX4_FLAG_SLAVE; | |
1078 | } | |
fa417f7b | 1079 | |
fccea643 IS |
1080 | static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) |
1081 | { | |
1082 | return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; | |
1083 | } | |
1084 | ||
225c7b1f | 1085 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
8900b894 | 1086 | struct mlx4_buf *buf); |
225c7b1f | 1087 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); |
1c69fc2a RD |
1088 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
1089 | { | |
73898db0 | 1090 | if (buf->nbufs == 1) |
b57aacfa | 1091 | return buf->direct.buf + offset; |
1c69fc2a | 1092 | else |
b57aacfa | 1093 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
1094 | (offset & (PAGE_SIZE - 1)); |
1095 | } | |
225c7b1f | 1096 | |
e2fb47d4 PP |
1097 | static inline int mlx4_is_bonded(struct mlx4_dev *dev) |
1098 | { | |
1099 | return !!(dev->flags & MLX4_FLAG_BONDED); | |
1100 | } | |
1101 | ||
1102 | static inline int mlx4_is_mf_bonded(struct mlx4_dev *dev) | |
1103 | { | |
1104 | return (mlx4_is_bonded(dev) && mlx4_is_mfunc(dev)); | |
1105 | } | |
1106 | ||
1107 | int mlx4_queue_bond_work(struct mlx4_dev *dev, int is_bonded, u8 v2p_p1, | |
1108 | u8 v2p_p2); | |
1109 | ||
225c7b1f RD |
1110 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); |
1111 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
1112 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
1113 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
1114 | |
1115 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
1116 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
163561a4 | 1117 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); |
c1b43dca | 1118 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); |
225c7b1f RD |
1119 | |
1120 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
1121 | struct mlx4_mtt *mtt); | |
1122 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
1123 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
1124 | ||
1125 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
1126 | int npages, int page_shift, struct mlx4_mr *mr); | |
61083720 | 1127 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); |
225c7b1f | 1128 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); |
804d6a89 SM |
1129 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
1130 | struct mlx4_mw *mw); | |
1131 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
1132 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
225c7b1f RD |
1133 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
1134 | int start_index, int npages, u64 *page_list); | |
1135 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
8900b894 | 1136 | struct mlx4_buf *buf); |
225c7b1f | 1137 | |
8900b894 | 1138 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
6296883c YP |
1139 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); |
1140 | ||
38ae6a53 | 1141 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
73898db0 | 1142 | int size); |
38ae6a53 YP |
1143 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, |
1144 | int size); | |
1145 | ||
225c7b1f | 1146 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 1147 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
e4567897 DJ |
1148 | unsigned int vector, int collapsed, int timestamp_en, |
1149 | void *buf_addr, bool user_cq); | |
225c7b1f | 1150 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
ddae0349 | 1151 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, |
f3301870 | 1152 | int *base, u8 flags, u8 usage); |
a3cdcbfa YP |
1153 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); |
1154 | ||
8900b894 | 1155 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); |
225c7b1f RD |
1156 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
1157 | ||
18abd5ea SH |
1158 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
1159 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
1160 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
1161 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 1162 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 1163 | |
5ae2a7a8 | 1164 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
1165 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
1166 | ||
ffe455ad EE |
1167 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
1168 | int block_mcast_loopback, enum mlx4_protocol prot); | |
1169 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
1170 | enum mlx4_protocol prot); | |
521e575b | 1171 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
1172 | u8 port, int block_mcast_loopback, |
1173 | enum mlx4_protocol protocol, u64 *reg_id); | |
da995a8a | 1174 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
1175 | enum mlx4_protocol protocol, u64 reg_id); |
1176 | ||
1177 | enum { | |
1178 | MLX4_DOMAIN_UVERBS = 0x1000, | |
1179 | MLX4_DOMAIN_ETHTOOL = 0x2000, | |
1180 | MLX4_DOMAIN_RFS = 0x3000, | |
1181 | MLX4_DOMAIN_NIC = 0x5000, | |
1182 | }; | |
1183 | ||
1184 | enum mlx4_net_trans_rule_id { | |
1185 | MLX4_NET_TRANS_RULE_ID_ETH = 0, | |
1186 | MLX4_NET_TRANS_RULE_ID_IB, | |
1187 | MLX4_NET_TRANS_RULE_ID_IPV6, | |
1188 | MLX4_NET_TRANS_RULE_ID_IPV4, | |
1189 | MLX4_NET_TRANS_RULE_ID_TCP, | |
1190 | MLX4_NET_TRANS_RULE_ID_UDP, | |
7ffdf726 | 1191 | MLX4_NET_TRANS_RULE_ID_VXLAN, |
0ff1fb65 HHZ |
1192 | MLX4_NET_TRANS_RULE_NUM, /* should be last */ |
1193 | }; | |
1194 | ||
a8edc3bf HHZ |
1195 | extern const u16 __sw_id_hw[]; |
1196 | ||
7fb40f87 HHZ |
1197 | static inline int map_hw_to_sw_id(u16 header_id) |
1198 | { | |
1199 | ||
1200 | int i; | |
1201 | for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { | |
1202 | if (header_id == __sw_id_hw[i]) | |
1203 | return i; | |
1204 | } | |
1205 | return -EINVAL; | |
1206 | } | |
1207 | ||
0ff1fb65 | 1208 | enum mlx4_net_trans_promisc_mode { |
f9162539 HHZ |
1209 | MLX4_FS_REGULAR = 1, |
1210 | MLX4_FS_ALL_DEFAULT, | |
1211 | MLX4_FS_MC_DEFAULT, | |
0e451e88 MV |
1212 | MLX4_FS_MIRROR_RX_PORT, |
1213 | MLX4_FS_MIRROR_SX_PORT, | |
f9162539 HHZ |
1214 | MLX4_FS_UC_SNIFFER, |
1215 | MLX4_FS_MC_SNIFFER, | |
c2c19dc3 | 1216 | MLX4_FS_MODE_NUM, /* should be last */ |
0ff1fb65 HHZ |
1217 | }; |
1218 | ||
1219 | struct mlx4_spec_eth { | |
574e2af7 JP |
1220 | u8 dst_mac[ETH_ALEN]; |
1221 | u8 dst_mac_msk[ETH_ALEN]; | |
1222 | u8 src_mac[ETH_ALEN]; | |
1223 | u8 src_mac_msk[ETH_ALEN]; | |
0ff1fb65 HHZ |
1224 | u8 ether_type_enable; |
1225 | __be16 ether_type; | |
1226 | __be16 vlan_id_msk; | |
1227 | __be16 vlan_id; | |
1228 | }; | |
1229 | ||
1230 | struct mlx4_spec_tcp_udp { | |
1231 | __be16 dst_port; | |
1232 | __be16 dst_port_msk; | |
1233 | __be16 src_port; | |
1234 | __be16 src_port_msk; | |
1235 | }; | |
1236 | ||
1237 | struct mlx4_spec_ipv4 { | |
1238 | __be32 dst_ip; | |
1239 | __be32 dst_ip_msk; | |
1240 | __be32 src_ip; | |
1241 | __be32 src_ip_msk; | |
1242 | }; | |
1243 | ||
1244 | struct mlx4_spec_ib { | |
ba60a356 | 1245 | __be32 l3_qpn; |
0ff1fb65 HHZ |
1246 | __be32 qpn_msk; |
1247 | u8 dst_gid[16]; | |
1248 | u8 dst_gid_msk[16]; | |
1249 | }; | |
1250 | ||
7ffdf726 OG |
1251 | struct mlx4_spec_vxlan { |
1252 | __be32 vni; | |
1253 | __be32 vni_mask; | |
1254 | ||
1255 | }; | |
1256 | ||
0ff1fb65 HHZ |
1257 | struct mlx4_spec_list { |
1258 | struct list_head list; | |
1259 | enum mlx4_net_trans_rule_id id; | |
1260 | union { | |
1261 | struct mlx4_spec_eth eth; | |
1262 | struct mlx4_spec_ib ib; | |
1263 | struct mlx4_spec_ipv4 ipv4; | |
1264 | struct mlx4_spec_tcp_udp tcp_udp; | |
7ffdf726 | 1265 | struct mlx4_spec_vxlan vxlan; |
0ff1fb65 HHZ |
1266 | }; |
1267 | }; | |
1268 | ||
1269 | enum mlx4_net_trans_hw_rule_queue { | |
1270 | MLX4_NET_TRANS_Q_FIFO, | |
1271 | MLX4_NET_TRANS_Q_LIFO, | |
1272 | }; | |
1273 | ||
1274 | struct mlx4_net_trans_rule { | |
1275 | struct list_head list; | |
1276 | enum mlx4_net_trans_hw_rule_queue queue_mode; | |
1277 | bool exclusive; | |
1278 | bool allow_loopback; | |
1279 | enum mlx4_net_trans_promisc_mode promisc_mode; | |
1280 | u8 port; | |
1281 | u16 priority; | |
1282 | u32 qpn; | |
1283 | }; | |
1284 | ||
3cd0e178 | 1285 | struct mlx4_net_trans_rule_hw_ctrl { |
bcf37297 HHZ |
1286 | __be16 prio; |
1287 | u8 type; | |
1288 | u8 flags; | |
3cd0e178 HHZ |
1289 | u8 rsvd1; |
1290 | u8 funcid; | |
1291 | u8 vep; | |
1292 | u8 port; | |
1293 | __be32 qpn; | |
1294 | __be32 rsvd2; | |
1295 | }; | |
1296 | ||
1297 | struct mlx4_net_trans_rule_hw_ib { | |
1298 | u8 size; | |
1299 | u8 rsvd1; | |
1300 | __be16 id; | |
1301 | u32 rsvd2; | |
ba60a356 | 1302 | __be32 l3_qpn; |
3cd0e178 HHZ |
1303 | __be32 qpn_mask; |
1304 | u8 dst_gid[16]; | |
1305 | u8 dst_gid_msk[16]; | |
1306 | } __packed; | |
1307 | ||
1308 | struct mlx4_net_trans_rule_hw_eth { | |
1309 | u8 size; | |
1310 | u8 rsvd; | |
1311 | __be16 id; | |
1312 | u8 rsvd1[6]; | |
1313 | u8 dst_mac[6]; | |
1314 | u16 rsvd2; | |
1315 | u8 dst_mac_msk[6]; | |
1316 | u16 rsvd3; | |
1317 | u8 src_mac[6]; | |
1318 | u16 rsvd4; | |
1319 | u8 src_mac_msk[6]; | |
1320 | u8 rsvd5; | |
1321 | u8 ether_type_enable; | |
1322 | __be16 ether_type; | |
ba60a356 HHZ |
1323 | __be16 vlan_tag_msk; |
1324 | __be16 vlan_tag; | |
3cd0e178 HHZ |
1325 | } __packed; |
1326 | ||
1327 | struct mlx4_net_trans_rule_hw_tcp_udp { | |
1328 | u8 size; | |
1329 | u8 rsvd; | |
1330 | __be16 id; | |
1331 | __be16 rsvd1[3]; | |
1332 | __be16 dst_port; | |
1333 | __be16 rsvd2; | |
1334 | __be16 dst_port_msk; | |
1335 | __be16 rsvd3; | |
1336 | __be16 src_port; | |
1337 | __be16 rsvd4; | |
1338 | __be16 src_port_msk; | |
1339 | } __packed; | |
1340 | ||
1341 | struct mlx4_net_trans_rule_hw_ipv4 { | |
1342 | u8 size; | |
1343 | u8 rsvd; | |
1344 | __be16 id; | |
1345 | __be32 rsvd1; | |
1346 | __be32 dst_ip; | |
1347 | __be32 dst_ip_msk; | |
1348 | __be32 src_ip; | |
1349 | __be32 src_ip_msk; | |
1350 | } __packed; | |
1351 | ||
7ffdf726 OG |
1352 | struct mlx4_net_trans_rule_hw_vxlan { |
1353 | u8 size; | |
1354 | u8 rsvd; | |
1355 | __be16 id; | |
1356 | __be32 rsvd1; | |
1357 | __be32 vni; | |
1358 | __be32 vni_mask; | |
1359 | } __packed; | |
1360 | ||
3cd0e178 HHZ |
1361 | struct _rule_hw { |
1362 | union { | |
1363 | struct { | |
1364 | u8 size; | |
1365 | u8 rsvd; | |
1366 | __be16 id; | |
1367 | }; | |
1368 | struct mlx4_net_trans_rule_hw_eth eth; | |
1369 | struct mlx4_net_trans_rule_hw_ib ib; | |
1370 | struct mlx4_net_trans_rule_hw_ipv4 ipv4; | |
1371 | struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; | |
7ffdf726 | 1372 | struct mlx4_net_trans_rule_hw_vxlan vxlan; |
3cd0e178 HHZ |
1373 | }; |
1374 | }; | |
1375 | ||
7ffdf726 OG |
1376 | enum { |
1377 | VXLAN_STEER_BY_OUTER_MAC = 1 << 0, | |
1378 | VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, | |
1379 | VXLAN_STEER_BY_VSID_VNI = 1 << 2, | |
1380 | VXLAN_STEER_BY_INNER_MAC = 1 << 3, | |
1381 | VXLAN_STEER_BY_INNER_VLAN = 1 << 4, | |
1382 | }; | |
1383 | ||
3f85f2aa MB |
1384 | enum { |
1385 | MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2, | |
1386 | }; | |
7ffdf726 | 1387 | |
592e49dd HHZ |
1388 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, |
1389 | enum mlx4_net_trans_promisc_mode mode); | |
1390 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, | |
1391 | enum mlx4_net_trans_promisc_mode mode); | |
1679200f YP |
1392 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
1393 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1394 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1395 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1396 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
1397 | ||
ffe455ad EE |
1398 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
1399 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
16a10ffd YB |
1400 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
1401 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
9a9a232a YP |
1402 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
1403 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | |
be599603 | 1404 | int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac); |
40fb4fc1 | 1405 | int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu); |
9a9a232a YP |
1406 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, |
1407 | u8 promisc); | |
51af33cf | 1408 | int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); |
78500b8c MM |
1409 | int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, |
1410 | u8 ignore_fcs_value); | |
1b136de1 | 1411 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); |
77fc29c4 HHZ |
1412 | int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); |
1413 | int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); | |
7c3d21c8 MS |
1414 | int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, |
1415 | bool *vlan_offload_disabled); | |
10b1c04e JM |
1416 | void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, |
1417 | struct _rule_hw *eth_header); | |
dd5f03be | 1418 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); |
4c3eb3ca | 1419 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 | 1420 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2009d005 | 1421 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
2a2336f8 | 1422 | |
8ad11fb6 | 1423 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); |
6f2e0d2c EE |
1424 | int mlx4_test_interrupt(struct mlx4_dev *dev, int vector); |
1425 | int mlx4_test_async(struct mlx4_dev *dev); | |
bfaf3168 MB |
1426 | int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, |
1427 | const u32 offset[], u32 value[], | |
1428 | size_t array_len, u8 port); | |
c66fa19c MB |
1429 | u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); |
1430 | bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); | |
1431 | struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); | |
1432 | int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); | |
0b7ca5a9 | 1433 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); |
8ad11fb6 | 1434 | |
c66fa19c | 1435 | int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); |
35f6f453 AV |
1436 | int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); |
1437 | ||
8e1a28e8 | 1438 | int mlx4_get_phys_port_id(struct mlx4_dev *dev); |
14c07b13 YP |
1439 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
1440 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
1441 | ||
f3301870 | 1442 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage); |
f2a3f6a3 | 1443 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); |
6de5f7f6 | 1444 | int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); |
f2a3f6a3 | 1445 | |
773af94e YH |
1446 | void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, |
1447 | int port); | |
1448 | __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); | |
fb517a4f | 1449 | void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); |
0ff1fb65 HHZ |
1450 | int mlx4_flow_attach(struct mlx4_dev *dev, |
1451 | struct mlx4_net_trans_rule *rule, u64 *reg_id); | |
1452 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); | |
c2c19dc3 HHZ |
1453 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, |
1454 | enum mlx4_net_trans_promisc_mode flow_type); | |
1455 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, | |
1456 | enum mlx4_net_trans_rule_id id); | |
1457 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); | |
0ff1fb65 | 1458 | |
ebb1fdb5 | 1459 | int mlx4_tunnel_steer_add(struct mlx4_dev *dev, const unsigned char *addr, |
b95089d0 OG |
1460 | int port, int qpn, u16 prio, u64 *reg_id); |
1461 | ||
54679e14 JM |
1462 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, |
1463 | int i, int val); | |
1464 | ||
396f2feb JM |
1465 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); |
1466 | ||
993c401e JM |
1467 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); |
1468 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1469 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1470 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); | |
1471 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); | |
1472 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); | |
1473 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); | |
1474 | ||
afa8fd1d JM |
1475 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
1476 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); | |
9cd59352 JM |
1477 | |
1478 | int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, | |
1479 | int *slave_id); | |
1480 | int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, | |
1481 | u8 *gid); | |
993c401e | 1482 | |
4de65803 MB |
1483 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, |
1484 | u32 max_range_qpn); | |
1485 | ||
a5a1d1c2 | 1486 | u64 mlx4_read_clock(struct mlx4_dev *dev); |
ec693d47 | 1487 | |
f74462ac MB |
1488 | struct mlx4_active_ports { |
1489 | DECLARE_BITMAP(ports, MLX4_MAX_PORTS); | |
1490 | }; | |
1491 | /* Returns a bitmap of the physical ports which are assigned to slave */ | |
1492 | struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); | |
1493 | ||
1494 | /* Returns the physical port that represents the virtual port of the slave, */ | |
1495 | /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ | |
1496 | /* mapping is returned. */ | |
1497 | int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); | |
1498 | ||
1499 | struct mlx4_slaves_pport { | |
1500 | DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); | |
1501 | }; | |
1502 | /* Returns a bitmap of all slaves that are assigned to port. */ | |
1503 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, | |
1504 | int port); | |
1505 | ||
1506 | /* Returns a bitmap of all slaves that are assigned exactly to all the */ | |
1507 | /* the ports that are set in crit_ports. */ | |
1508 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( | |
1509 | struct mlx4_dev *dev, | |
1510 | const struct mlx4_active_ports *crit_ports); | |
1511 | ||
1512 | /* Returns the slave's virtual port that represents the physical port. */ | |
1513 | int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); | |
1514 | ||
449fc488 | 1515 | int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); |
d18f141a OG |
1516 | |
1517 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); | |
59e14e32 | 1518 | int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); |
fca83006 | 1519 | int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port); |
59e14e32 | 1520 | int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); |
97982f5a | 1521 | int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); |
65fed8a8 JM |
1522 | int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); |
1523 | int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, | |
1524 | int enable); | |
1f55b7ab MG |
1525 | |
1526 | struct mlx4_mpt_entry; | |
e630664c MB |
1527 | int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, |
1528 | struct mlx4_mpt_entry ***mpt_entry); | |
1529 | int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, | |
1530 | struct mlx4_mpt_entry **mpt_entry); | |
1531 | int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, | |
1532 | u32 pdn); | |
1533 | int mlx4_mr_hw_change_access(struct mlx4_dev *dev, | |
1534 | struct mlx4_mpt_entry *mpt_entry, | |
1535 | u32 access); | |
1536 | void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, | |
1537 | struct mlx4_mpt_entry **mpt_entry); | |
1538 | void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
1539 | int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, | |
1540 | u64 iova, u64 size, int npages, | |
1541 | int page_shift, struct mlx4_mpt_entry *mpt_entry); | |
2599d858 | 1542 | |
32a173c7 SM |
1543 | int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, |
1544 | u16 offset, u16 size, u8 *data); | |
af7d5185 | 1545 | int mlx4_max_tc(struct mlx4_dev *dev); |
32a173c7 | 1546 | |
2599d858 AV |
1547 | /* Returns true if running in low memory profile (kdump kernel) */ |
1548 | static inline bool mlx4_low_memory_profile(void) | |
1549 | { | |
48ea526a | 1550 | return is_kdump_kernel(); |
2599d858 AV |
1551 | } |
1552 | ||
adbc7ac5 SM |
1553 | /* ACCESS REG commands */ |
1554 | enum mlx4_access_reg_method { | |
1555 | MLX4_ACCESS_REG_QUERY = 0x1, | |
1556 | MLX4_ACCESS_REG_WRITE = 0x2, | |
1557 | }; | |
1558 | ||
1559 | /* ACCESS PTYS Reg command */ | |
1560 | enum mlx4_ptys_proto { | |
1561 | MLX4_PTYS_IB = 1<<0, | |
1562 | MLX4_PTYS_EN = 1<<2, | |
1563 | }; | |
1564 | ||
297e1cf2 AL |
1565 | enum mlx4_ptys_flags { |
1566 | MLX4_PTYS_AN_DISABLE_CAP = 1 << 5, | |
1567 | MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6, | |
1568 | }; | |
1569 | ||
adbc7ac5 | 1570 | struct mlx4_ptys_reg { |
297e1cf2 | 1571 | u8 flags; |
adbc7ac5 SM |
1572 | u8 local_port; |
1573 | u8 resrvd2; | |
1574 | u8 proto_mask; | |
1575 | __be32 resrvd3[2]; | |
1576 | __be32 eth_proto_cap; | |
1577 | __be16 ib_width_cap; | |
1578 | __be16 ib_speed_cap; | |
1579 | __be32 resrvd4; | |
1580 | __be32 eth_proto_admin; | |
1581 | __be16 ib_width_admin; | |
1582 | __be16 ib_speed_admin; | |
1583 | __be32 resrvd5; | |
1584 | __be32 eth_proto_oper; | |
1585 | __be16 ib_width_oper; | |
1586 | __be16 ib_speed_oper; | |
1587 | __be32 resrvd6; | |
1588 | __be32 eth_proto_lp_adv; | |
1589 | } __packed; | |
1590 | ||
1591 | int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, | |
1592 | enum mlx4_access_reg_method method, | |
1593 | struct mlx4_ptys_reg *ptys_reg); | |
1594 | ||
52033cfb MB |
1595 | int mlx4_get_internal_clock_params(struct mlx4_dev *dev, |
1596 | struct mlx4_clock_params *params); | |
1597 | ||
85743f1e HN |
1598 | static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index) |
1599 | { | |
1600 | return (index << (PAGE_SHIFT - dev->uar_page_shift)); | |
1601 | } | |
1602 | ||
1603 | static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev) | |
1604 | { | |
1605 | /* The first 128 UARs are used for EQ doorbells */ | |
1606 | return (128 >> (PAGE_SHIFT - dev->uar_page_shift)); | |
1607 | } | |
225c7b1f | 1608 | #endif /* MLX4_DEVICE_H */ |