Commit | Line | Data |
---|---|---|
225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
36 | #include <linux/pci.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/radix-tree.h> | |
39 | ||
60063497 | 40 | #include <linux/atomic.h> |
225c7b1f | 41 | |
0b7ca5a9 YP |
42 | #define MAX_MSIX_P_PORT 17 |
43 | #define MAX_MSIX 64 | |
44 | #define MSIX_LEGACY_SZ 4 | |
45 | #define MIN_MSIX_P_PORT 5 | |
46 | ||
225c7b1f RD |
47 | enum { |
48 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 49 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
225c7b1f RD |
50 | }; |
51 | ||
52 | enum { | |
53 | MLX4_MAX_PORTS = 2 | |
54 | }; | |
55 | ||
cd9281d8 JM |
56 | enum { |
57 | MLX4_BOARD_ID_LEN = 64 | |
58 | }; | |
59 | ||
225c7b1f | 60 | enum { |
52eafc68 OG |
61 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
62 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
63 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 64 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
65 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
66 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
67 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
68 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
69 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
70 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
71 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
72 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
73 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
74 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
75 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
76 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
77 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
78 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 79 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
ccf86321 OG |
80 | MLX4_DEV_CAP_FLAG_WOL = 1LL << 38, |
81 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, | |
82 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 OG |
83 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
84 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48 | |
225c7b1f RD |
85 | }; |
86 | ||
97285b78 MA |
87 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
88 | ||
89 | enum { | |
90 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 | |
91 | }; | |
92 | ||
95d04f07 RD |
93 | enum { |
94 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, | |
95 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
96 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
97 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
98 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
99 | }; | |
100 | ||
225c7b1f RD |
101 | enum mlx4_event { |
102 | MLX4_EVENT_TYPE_COMP = 0x00, | |
103 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
104 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
105 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
106 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
107 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
108 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
109 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
110 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
111 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
112 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
113 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
114 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
115 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
116 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
117 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
118 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
119 | MLX4_EVENT_TYPE_CMD = 0x0a | |
120 | }; | |
121 | ||
122 | enum { | |
123 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
124 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
125 | }; | |
126 | ||
127 | enum { | |
128 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
129 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
130 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
131 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
132 | MLX4_PERM_ATOMIC = 1 << 14 | |
133 | }; | |
134 | ||
135 | enum { | |
136 | MLX4_OPCODE_NOP = 0x00, | |
137 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
138 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
139 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
140 | MLX4_OPCODE_SEND = 0x0a, | |
141 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
142 | MLX4_OPCODE_LSO = 0x0e, | |
143 | MLX4_OPCODE_RDMA_READ = 0x10, | |
144 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
145 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
146 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
147 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
148 | MLX4_OPCODE_BIND_MW = 0x18, |
149 | MLX4_OPCODE_FMR = 0x19, | |
150 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
151 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
152 | ||
153 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
154 | MLX4_RECV_OPCODE_SEND = 0x01, | |
155 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
156 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
157 | ||
158 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
159 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
160 | }; | |
161 | ||
162 | enum { | |
163 | MLX4_STAT_RATE_OFFSET = 5 | |
164 | }; | |
165 | ||
da995a8a | 166 | enum mlx4_protocol { |
0345584e YP |
167 | MLX4_PROT_IB_IPV6 = 0, |
168 | MLX4_PROT_ETH, | |
169 | MLX4_PROT_IB_IPV4, | |
170 | MLX4_PROT_FCOE | |
da995a8a AS |
171 | }; |
172 | ||
29bdc883 VS |
173 | enum { |
174 | MLX4_MTT_FLAG_PRESENT = 1 | |
175 | }; | |
176 | ||
93fc9e1b YP |
177 | enum mlx4_qp_region { |
178 | MLX4_QP_REGION_FW = 0, | |
179 | MLX4_QP_REGION_ETH_ADDR, | |
180 | MLX4_QP_REGION_FC_ADDR, | |
181 | MLX4_QP_REGION_FC_EXCH, | |
182 | MLX4_NUM_QP_REGION | |
183 | }; | |
184 | ||
7ff93f8b | 185 | enum mlx4_port_type { |
27bf91d6 YP |
186 | MLX4_PORT_TYPE_IB = 1, |
187 | MLX4_PORT_TYPE_ETH = 2, | |
188 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
189 | }; |
190 | ||
2a2336f8 YP |
191 | enum mlx4_special_vlan_idx { |
192 | MLX4_NO_VLAN_IDX = 0, | |
193 | MLX4_VLAN_MISS_IDX, | |
194 | MLX4_VLAN_REGULAR | |
195 | }; | |
196 | ||
0345584e YP |
197 | enum mlx4_steer_type { |
198 | MLX4_MC_STEER = 0, | |
199 | MLX4_UC_STEER, | |
200 | MLX4_NUM_STEERS | |
201 | }; | |
202 | ||
93fc9e1b YP |
203 | enum { |
204 | MLX4_NUM_FEXCH = 64 * 1024, | |
205 | }; | |
206 | ||
5a0fd094 EC |
207 | enum { |
208 | MLX4_MAX_FAST_REG_PAGES = 511, | |
209 | }; | |
210 | ||
ea54b10c JM |
211 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
212 | { | |
213 | return (major << 32) | (minor << 16) | subminor; | |
214 | } | |
215 | ||
225c7b1f RD |
216 | struct mlx4_caps { |
217 | u64 fw_ver; | |
218 | int num_ports; | |
5ae2a7a8 | 219 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 220 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 221 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
222 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
223 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
224 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
225 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
226 | int trans_type[MLX4_MAX_PORTS + 1]; |
227 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
228 | int wavelength[MLX4_MAX_PORTS + 1]; | |
229 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
230 | int local_ca_ack_delay; |
231 | int num_uars; | |
232 | int bf_reg_size; | |
233 | int bf_regs_per_page; | |
234 | int max_sq_sg; | |
235 | int max_rq_sg; | |
236 | int num_qps; | |
237 | int max_wqes; | |
238 | int max_sq_desc_sz; | |
239 | int max_rq_desc_sz; | |
240 | int max_qp_init_rdma; | |
241 | int max_qp_dest_rdma; | |
225c7b1f RD |
242 | int sqp_start; |
243 | int num_srqs; | |
244 | int max_srq_wqes; | |
245 | int max_srq_sge; | |
246 | int reserved_srqs; | |
247 | int num_cqs; | |
248 | int max_cqes; | |
249 | int reserved_cqs; | |
250 | int num_eqs; | |
251 | int reserved_eqs; | |
b8dd786f | 252 | int num_comp_vectors; |
0b7ca5a9 | 253 | int comp_pool; |
225c7b1f RD |
254 | int num_mpts; |
255 | int num_mtt_segs; | |
ab6bf42e | 256 | int mtts_per_seg; |
225c7b1f RD |
257 | int fmr_reserved_mtts; |
258 | int reserved_mtts; | |
259 | int reserved_mrws; | |
260 | int reserved_uars; | |
261 | int num_mgms; | |
262 | int num_amgms; | |
263 | int reserved_mcgs; | |
264 | int num_qp_per_mgm; | |
265 | int num_pds; | |
266 | int reserved_pds; | |
012a8ff5 SH |
267 | int max_xrcds; |
268 | int reserved_xrcds; | |
225c7b1f | 269 | int mtt_entry_sz; |
149983af | 270 | u32 max_msg_sz; |
225c7b1f | 271 | u32 page_size_cap; |
52eafc68 | 272 | u64 flags; |
95d04f07 RD |
273 | u32 bmme_flags; |
274 | u32 reserved_lkey; | |
225c7b1f | 275 | u16 stat_rate_support; |
5ae2a7a8 | 276 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 277 | int max_gso_sz; |
93fc9e1b YP |
278 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
279 | int reserved_qps; | |
280 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
281 | int log_num_macs; | |
282 | int log_num_vlans; | |
283 | int log_num_prios; | |
7ff93f8b YP |
284 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
285 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
286 | u32 port_mask; | |
27bf91d6 | 287 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 288 | u32 max_counters; |
97285b78 | 289 | u8 ext_port_cap[MLX4_MAX_PORTS + 1]; |
225c7b1f RD |
290 | }; |
291 | ||
292 | struct mlx4_buf_list { | |
293 | void *buf; | |
294 | dma_addr_t map; | |
295 | }; | |
296 | ||
297 | struct mlx4_buf { | |
b57aacfa RD |
298 | struct mlx4_buf_list direct; |
299 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
300 | int nbufs; |
301 | int npages; | |
302 | int page_shift; | |
303 | }; | |
304 | ||
305 | struct mlx4_mtt { | |
306 | u32 first_seg; | |
307 | int order; | |
308 | int page_shift; | |
309 | }; | |
310 | ||
6296883c YP |
311 | enum { |
312 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
313 | }; | |
314 | ||
315 | struct mlx4_db_pgdir { | |
316 | struct list_head list; | |
317 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
318 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
319 | unsigned long *bits[2]; | |
320 | __be32 *db_page; | |
321 | dma_addr_t db_dma; | |
322 | }; | |
323 | ||
324 | struct mlx4_ib_user_db_page; | |
325 | ||
326 | struct mlx4_db { | |
327 | __be32 *db; | |
328 | union { | |
329 | struct mlx4_db_pgdir *pgdir; | |
330 | struct mlx4_ib_user_db_page *user_page; | |
331 | } u; | |
332 | dma_addr_t dma; | |
333 | int index; | |
334 | int order; | |
335 | }; | |
336 | ||
38ae6a53 YP |
337 | struct mlx4_hwq_resources { |
338 | struct mlx4_db db; | |
339 | struct mlx4_mtt mtt; | |
340 | struct mlx4_buf buf; | |
341 | }; | |
342 | ||
225c7b1f RD |
343 | struct mlx4_mr { |
344 | struct mlx4_mtt mtt; | |
345 | u64 iova; | |
346 | u64 size; | |
347 | u32 key; | |
348 | u32 pd; | |
349 | u32 access; | |
350 | int enabled; | |
351 | }; | |
352 | ||
8ad11fb6 JM |
353 | struct mlx4_fmr { |
354 | struct mlx4_mr mr; | |
355 | struct mlx4_mpt_entry *mpt; | |
356 | __be64 *mtts; | |
357 | dma_addr_t dma_handle; | |
358 | int max_pages; | |
359 | int max_maps; | |
360 | int maps; | |
361 | u8 page_shift; | |
362 | }; | |
363 | ||
225c7b1f RD |
364 | struct mlx4_uar { |
365 | unsigned long pfn; | |
366 | int index; | |
c1b43dca EC |
367 | struct list_head bf_list; |
368 | unsigned free_bf_bmap; | |
369 | void __iomem *map; | |
370 | void __iomem *bf_map; | |
371 | }; | |
372 | ||
373 | struct mlx4_bf { | |
374 | unsigned long offset; | |
375 | int buf_size; | |
376 | struct mlx4_uar *uar; | |
377 | void __iomem *reg; | |
225c7b1f RD |
378 | }; |
379 | ||
380 | struct mlx4_cq { | |
381 | void (*comp) (struct mlx4_cq *); | |
382 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
383 | ||
384 | struct mlx4_uar *uar; | |
385 | ||
386 | u32 cons_index; | |
387 | ||
388 | __be32 *set_ci_db; | |
389 | __be32 *arm_db; | |
390 | int arm_sn; | |
391 | ||
392 | int cqn; | |
b8dd786f | 393 | unsigned vector; |
225c7b1f RD |
394 | |
395 | atomic_t refcount; | |
396 | struct completion free; | |
397 | }; | |
398 | ||
399 | struct mlx4_qp { | |
400 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
401 | ||
402 | int qpn; | |
403 | ||
404 | atomic_t refcount; | |
405 | struct completion free; | |
406 | }; | |
407 | ||
408 | struct mlx4_srq { | |
409 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
410 | ||
411 | int srqn; | |
412 | int max; | |
413 | int max_gs; | |
414 | int wqe_shift; | |
415 | ||
416 | atomic_t refcount; | |
417 | struct completion free; | |
418 | }; | |
419 | ||
420 | struct mlx4_av { | |
421 | __be32 port_pd; | |
422 | u8 reserved1; | |
423 | u8 g_slid; | |
424 | __be16 dlid; | |
425 | u8 reserved2; | |
426 | u8 gid_index; | |
427 | u8 stat_rate; | |
428 | u8 hop_limit; | |
429 | __be32 sl_tclass_flowlabel; | |
430 | u8 dgid[16]; | |
431 | }; | |
432 | ||
fa417f7b EC |
433 | struct mlx4_eth_av { |
434 | __be32 port_pd; | |
435 | u8 reserved1; | |
436 | u8 smac_idx; | |
437 | u16 reserved2; | |
438 | u8 reserved3; | |
439 | u8 gid_index; | |
440 | u8 stat_rate; | |
441 | u8 hop_limit; | |
442 | __be32 sl_tclass_flowlabel; | |
443 | u8 dgid[16]; | |
444 | u32 reserved4[2]; | |
445 | __be16 vlan; | |
446 | u8 mac[6]; | |
447 | }; | |
448 | ||
449 | union mlx4_ext_av { | |
450 | struct mlx4_av ib; | |
451 | struct mlx4_eth_av eth; | |
452 | }; | |
453 | ||
f2a3f6a3 OG |
454 | struct mlx4_counter { |
455 | u8 reserved1[3]; | |
456 | u8 counter_mode; | |
457 | __be32 num_ifc; | |
458 | u32 reserved2[2]; | |
459 | __be64 rx_frames; | |
460 | __be64 rx_bytes; | |
461 | __be64 tx_frames; | |
462 | __be64 tx_bytes; | |
463 | }; | |
464 | ||
225c7b1f RD |
465 | struct mlx4_dev { |
466 | struct pci_dev *pdev; | |
467 | unsigned long flags; | |
468 | struct mlx4_caps caps; | |
469 | struct radix_tree_root qp_table_tree; | |
725c8999 | 470 | u8 rev_id; |
cd9281d8 | 471 | char board_id[MLX4_BOARD_ID_LEN]; |
225c7b1f RD |
472 | }; |
473 | ||
474 | struct mlx4_init_port_param { | |
475 | int set_guid0; | |
476 | int set_node_guid; | |
477 | int set_si_guid; | |
478 | u16 mtu; | |
479 | int port_width_cap; | |
480 | u16 vl_cap; | |
481 | u16 max_gid; | |
482 | u16 max_pkey; | |
483 | u64 guid0; | |
484 | u64 node_guid; | |
485 | u64 si_guid; | |
486 | }; | |
487 | ||
7ff93f8b YP |
488 | #define mlx4_foreach_port(port, dev, type) \ |
489 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
490 | if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \ | |
491 | ~(dev)->caps.port_mask) & 1 << ((port) - 1)) | |
492 | ||
fa417f7b EC |
493 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
494 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
495 | if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \ | |
496 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
497 | ||
498 | ||
225c7b1f RD |
499 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
500 | struct mlx4_buf *buf); | |
501 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | |
1c69fc2a RD |
502 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
503 | { | |
313abe55 | 504 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 505 | return buf->direct.buf + offset; |
1c69fc2a | 506 | else |
b57aacfa | 507 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
508 | (offset & (PAGE_SIZE - 1)); |
509 | } | |
225c7b1f RD |
510 | |
511 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
512 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
513 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
514 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
515 | |
516 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
517 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
c1b43dca EC |
518 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); |
519 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); | |
225c7b1f RD |
520 | |
521 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
522 | struct mlx4_mtt *mtt); | |
523 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
524 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
525 | ||
526 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
527 | int npages, int page_shift, struct mlx4_mr *mr); | |
528 | void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
529 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
530 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
531 | int start_index, int npages, u64 *page_list); | |
532 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
533 | struct mlx4_buf *buf); | |
534 | ||
6296883c YP |
535 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
536 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); | |
537 | ||
38ae6a53 YP |
538 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
539 | int size, int max_direct); | |
540 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
541 | int size); | |
542 | ||
225c7b1f | 543 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 544 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
b8dd786f | 545 | unsigned vector, int collapsed); |
225c7b1f RD |
546 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
547 | ||
a3cdcbfa YP |
548 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
549 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
550 | ||
551 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); | |
225c7b1f RD |
552 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
553 | ||
18abd5ea SH |
554 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
555 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
556 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
557 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 558 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 559 | |
5ae2a7a8 | 560 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
561 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
562 | ||
521e575b | 563 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
da995a8a AS |
564 | int block_mcast_loopback, enum mlx4_protocol protocol); |
565 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
566 | enum mlx4_protocol protocol); | |
1679200f YP |
567 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
568 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
569 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
570 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
571 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
572 | ||
573 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap); | |
574 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn); | |
575 | int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap); | |
2a2336f8 | 576 | |
4c3eb3ca | 577 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 YP |
578 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
579 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); | |
580 | ||
8ad11fb6 JM |
581 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
582 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
583 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
584 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
585 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
586 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
587 | u32 *lkey, u32 *rkey); | |
588 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
589 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 590 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
0b7ca5a9 YP |
591 | int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector); |
592 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); | |
8ad11fb6 | 593 | |
14c07b13 YP |
594 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
595 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
596 | ||
f2a3f6a3 OG |
597 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
598 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
599 | ||
225c7b1f | 600 | #endif /* MLX4_DEVICE_H */ |