Commit | Line | Data |
---|---|---|
225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
574e2af7 | 36 | #include <linux/if_ether.h> |
225c7b1f RD |
37 | #include <linux/pci.h> |
38 | #include <linux/completion.h> | |
39 | #include <linux/radix-tree.h> | |
d9236c3f | 40 | #include <linux/cpu_rmap.h> |
48ea526a | 41 | #include <linux/crash_dump.h> |
225c7b1f | 42 | |
60063497 | 43 | #include <linux/atomic.h> |
225c7b1f | 44 | |
74d23cc7 | 45 | #include <linux/timecounter.h> |
ec693d47 | 46 | |
0b7ca5a9 YP |
47 | #define MAX_MSIX_P_PORT 17 |
48 | #define MAX_MSIX 64 | |
49 | #define MSIX_LEGACY_SZ 4 | |
50 | #define MIN_MSIX_P_PORT 5 | |
51 | ||
523ece88 EE |
52 | #define MLX4_NUM_UP 8 |
53 | #define MLX4_NUM_TC 8 | |
54 | #define MLX4_MAX_100M_UNITS_VAL 255 /* | |
55 | * work around: can't set values | |
56 | * greater then this value when | |
57 | * using 100 Mbps units. | |
58 | */ | |
59 | #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ | |
60 | #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ | |
61 | #define MLX4_RATELIMIT_DEFAULT 0x00ff | |
62 | ||
6ee51a4e | 63 | #define MLX4_ROCE_MAX_GIDS 128 |
b6ffaeff | 64 | #define MLX4_ROCE_PF_GIDS 16 |
6ee51a4e | 65 | |
225c7b1f RD |
66 | enum { |
67 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 68 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
69 | MLX4_FLAG_MASTER = 1 << 2, |
70 | MLX4_FLAG_SLAVE = 1 << 3, | |
71 | MLX4_FLAG_SRIOV = 1 << 4, | |
acddd5dd | 72 | MLX4_FLAG_OLD_REG_MAC = 1 << 6, |
225c7b1f RD |
73 | }; |
74 | ||
efcd235d JM |
75 | enum { |
76 | MLX4_PORT_CAP_IS_SM = 1 << 1, | |
77 | MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, | |
78 | }; | |
79 | ||
225c7b1f | 80 | enum { |
fc06573d JM |
81 | MLX4_MAX_PORTS = 2, |
82 | MLX4_MAX_PORT_PKEYS = 128 | |
225c7b1f RD |
83 | }; |
84 | ||
396f2feb JM |
85 | /* base qkey for use in sriov tunnel-qp/proxy-qp communication. |
86 | * These qkeys must not be allowed for general use. This is a 64k range, | |
87 | * and to test for violation, we use the mask (protect against future chg). | |
88 | */ | |
89 | #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) | |
90 | #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) | |
91 | ||
cd9281d8 JM |
92 | enum { |
93 | MLX4_BOARD_ID_LEN = 64 | |
94 | }; | |
95 | ||
623ed84b JM |
96 | enum { |
97 | MLX4_MAX_NUM_PF = 16, | |
de966c59 | 98 | MLX4_MAX_NUM_VF = 126, |
1ab95d37 | 99 | MLX4_MAX_NUM_VF_P_PORT = 64, |
623ed84b | 100 | MLX4_MFUNC_MAX = 80, |
3fc929e2 | 101 | MLX4_MAX_EQ_NUM = 1024, |
623ed84b JM |
102 | MLX4_MFUNC_EQ_NUM = 4, |
103 | MLX4_MFUNC_MAX_EQES = 8, | |
104 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
105 | }; | |
106 | ||
0ff1fb65 HHZ |
107 | /* Driver supports 3 diffrent device methods to manage traffic steering: |
108 | * -device managed - High level API for ib and eth flow steering. FW is | |
109 | * managing flow steering tables. | |
c96d97f4 HHZ |
110 | * - B0 steering mode - Common low level API for ib and (if supported) eth. |
111 | * - A0 steering mode - Limited low level API for eth. In case of IB, | |
112 | * B0 mode is in use. | |
113 | */ | |
114 | enum { | |
115 | MLX4_STEERING_MODE_A0, | |
0ff1fb65 HHZ |
116 | MLX4_STEERING_MODE_B0, |
117 | MLX4_STEERING_MODE_DEVICE_MANAGED | |
c96d97f4 HHZ |
118 | }; |
119 | ||
7d077cd3 MB |
120 | enum { |
121 | MLX4_STEERING_DMFS_A0_DEFAULT, | |
122 | MLX4_STEERING_DMFS_A0_DYNAMIC, | |
123 | MLX4_STEERING_DMFS_A0_STATIC, | |
124 | MLX4_STEERING_DMFS_A0_DISABLE, | |
125 | MLX4_STEERING_DMFS_A0_NOT_SUPPORTED | |
126 | }; | |
127 | ||
c96d97f4 HHZ |
128 | static inline const char *mlx4_steering_mode_str(int steering_mode) |
129 | { | |
130 | switch (steering_mode) { | |
131 | case MLX4_STEERING_MODE_A0: | |
132 | return "A0 steering"; | |
133 | ||
134 | case MLX4_STEERING_MODE_B0: | |
135 | return "B0 steering"; | |
0ff1fb65 HHZ |
136 | |
137 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
138 | return "Device managed flow steering"; | |
139 | ||
c96d97f4 HHZ |
140 | default: |
141 | return "Unrecognize steering mode"; | |
142 | } | |
143 | } | |
144 | ||
7ffdf726 OG |
145 | enum { |
146 | MLX4_TUNNEL_OFFLOAD_MODE_NONE, | |
147 | MLX4_TUNNEL_OFFLOAD_MODE_VXLAN | |
148 | }; | |
149 | ||
225c7b1f | 150 | enum { |
52eafc68 OG |
151 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
152 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
153 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 154 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
155 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
156 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
157 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
158 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
159 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
160 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
161 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
162 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
163 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
164 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
165 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
166 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
167 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
168 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 169 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
170 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
171 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
172 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
173 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 174 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 | 175 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
540b3a39 | 176 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
00f5ce99 JM |
177 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
178 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | |
08ff3235 OG |
179 | MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, |
180 | MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 | |
225c7b1f RD |
181 | }; |
182 | ||
b3416f44 SP |
183 | enum { |
184 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, | |
185 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, | |
0ff1fb65 | 186 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, |
955154fa | 187 | MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, |
5930e8d0 | 188 | MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, |
3f7fb021 | 189 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
e6b6a231 | 190 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
b01978ca | 191 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
4de65803 | 192 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, |
4ba9920e LT |
193 | MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, |
194 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, | |
114840c3 | 195 | MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, |
77507aa2 | 196 | MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, |
adbc7ac5 | 197 | MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, |
a53e3e8c | 198 | MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, |
d475c95b | 199 | MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, |
7ae0e400 | 200 | MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, |
de966c59 | 201 | MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, |
7d077cd3 MB |
202 | MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, |
203 | MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19 | |
b3416f44 SP |
204 | }; |
205 | ||
ddae0349 | 206 | enum { |
d57febe1 MB |
207 | MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, |
208 | MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 | |
ddae0349 EE |
209 | }; |
210 | ||
211 | /* bit enums for an 8-bit flags field indicating special use | |
212 | * QPs which require special handling in qp_reserve_range. | |
213 | * Currently, this only includes QPs used by the ETH interface, | |
214 | * where we expect to use blueflame. These QPs must not have | |
215 | * bits 6 and 7 set in their qp number. | |
216 | * | |
217 | * This enum may use only bits 0..7. | |
218 | */ | |
219 | enum { | |
d57febe1 | 220 | MLX4_RESERVE_A0_QP = 1 << 6, |
ddae0349 EE |
221 | MLX4_RESERVE_ETH_BF_QP = 1 << 7, |
222 | }; | |
223 | ||
08ff3235 OG |
224 | enum { |
225 | MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, | |
77507aa2 IS |
226 | MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, |
227 | MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, | |
228 | MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 | |
08ff3235 OG |
229 | }; |
230 | ||
231 | enum { | |
77507aa2 | 232 | MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 |
08ff3235 OG |
233 | }; |
234 | ||
235 | enum { | |
77507aa2 | 236 | MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, |
7d077cd3 MB |
237 | MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, |
238 | MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 | |
08ff3235 OG |
239 | }; |
240 | ||
241 | ||
97285b78 MA |
242 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
243 | ||
95d04f07 | 244 | enum { |
804d6a89 | 245 | MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, |
95d04f07 RD |
246 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, |
247 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
248 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
249 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
250 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
09e05c3f | 251 | MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, |
95d04f07 RD |
252 | }; |
253 | ||
225c7b1f RD |
254 | enum mlx4_event { |
255 | MLX4_EVENT_TYPE_COMP = 0x00, | |
256 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
257 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
258 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
259 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
260 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
261 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
262 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
263 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
264 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
265 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
266 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
267 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
268 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
269 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
270 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
271 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
272 | MLX4_EVENT_TYPE_CMD = 0x0a, |
273 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
274 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
fe6f700d | 275 | MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, |
5984be90 | 276 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
623ed84b | 277 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
00f5ce99 | 278 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
623ed84b | 279 | MLX4_EVENT_TYPE_NONE = 0xff, |
225c7b1f RD |
280 | }; |
281 | ||
282 | enum { | |
283 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
284 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
285 | }; | |
286 | ||
5984be90 JM |
287 | enum { |
288 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, | |
289 | }; | |
290 | ||
993c401e JM |
291 | enum slave_port_state { |
292 | SLAVE_PORT_DOWN = 0, | |
293 | SLAVE_PENDING_UP, | |
294 | SLAVE_PORT_UP, | |
295 | }; | |
296 | ||
297 | enum slave_port_gen_event { | |
298 | SLAVE_PORT_GEN_EVENT_DOWN = 0, | |
299 | SLAVE_PORT_GEN_EVENT_UP, | |
300 | SLAVE_PORT_GEN_EVENT_NONE, | |
301 | }; | |
302 | ||
303 | enum slave_port_state_event { | |
304 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
305 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP, | |
306 | MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, | |
307 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID, | |
308 | }; | |
309 | ||
225c7b1f RD |
310 | enum { |
311 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
312 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
313 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
314 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
804d6a89 SM |
315 | MLX4_PERM_ATOMIC = 1 << 14, |
316 | MLX4_PERM_BIND_MW = 1 << 15, | |
e630664c | 317 | MLX4_PERM_MASK = 0xFC00 |
225c7b1f RD |
318 | }; |
319 | ||
320 | enum { | |
321 | MLX4_OPCODE_NOP = 0x00, | |
322 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
323 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
324 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
325 | MLX4_OPCODE_SEND = 0x0a, | |
326 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
327 | MLX4_OPCODE_LSO = 0x0e, | |
328 | MLX4_OPCODE_RDMA_READ = 0x10, | |
329 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
330 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
331 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
332 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
333 | MLX4_OPCODE_BIND_MW = 0x18, |
334 | MLX4_OPCODE_FMR = 0x19, | |
335 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
336 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
337 | ||
338 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
339 | MLX4_RECV_OPCODE_SEND = 0x01, | |
340 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
341 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
342 | ||
343 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
344 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
345 | }; | |
346 | ||
347 | enum { | |
348 | MLX4_STAT_RATE_OFFSET = 5 | |
349 | }; | |
350 | ||
da995a8a | 351 | enum mlx4_protocol { |
0345584e YP |
352 | MLX4_PROT_IB_IPV6 = 0, |
353 | MLX4_PROT_ETH, | |
354 | MLX4_PROT_IB_IPV4, | |
355 | MLX4_PROT_FCOE | |
da995a8a AS |
356 | }; |
357 | ||
29bdc883 VS |
358 | enum { |
359 | MLX4_MTT_FLAG_PRESENT = 1 | |
360 | }; | |
361 | ||
93fc9e1b YP |
362 | enum mlx4_qp_region { |
363 | MLX4_QP_REGION_FW = 0, | |
d57febe1 MB |
364 | MLX4_QP_REGION_RSS_RAW_ETH, |
365 | MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, | |
93fc9e1b YP |
366 | MLX4_QP_REGION_ETH_ADDR, |
367 | MLX4_QP_REGION_FC_ADDR, | |
368 | MLX4_QP_REGION_FC_EXCH, | |
369 | MLX4_NUM_QP_REGION | |
370 | }; | |
371 | ||
7ff93f8b | 372 | enum mlx4_port_type { |
623ed84b | 373 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
374 | MLX4_PORT_TYPE_IB = 1, |
375 | MLX4_PORT_TYPE_ETH = 2, | |
376 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
377 | }; |
378 | ||
2a2336f8 YP |
379 | enum mlx4_special_vlan_idx { |
380 | MLX4_NO_VLAN_IDX = 0, | |
381 | MLX4_VLAN_MISS_IDX, | |
382 | MLX4_VLAN_REGULAR | |
383 | }; | |
384 | ||
0345584e YP |
385 | enum mlx4_steer_type { |
386 | MLX4_MC_STEER = 0, | |
387 | MLX4_UC_STEER, | |
388 | MLX4_NUM_STEERS | |
389 | }; | |
390 | ||
93fc9e1b YP |
391 | enum { |
392 | MLX4_NUM_FEXCH = 64 * 1024, | |
393 | }; | |
394 | ||
5a0fd094 EC |
395 | enum { |
396 | MLX4_MAX_FAST_REG_PAGES = 511, | |
397 | }; | |
398 | ||
00f5ce99 JM |
399 | enum { |
400 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, | |
401 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, | |
402 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, | |
403 | }; | |
404 | ||
405 | /* Port mgmt change event handling */ | |
406 | enum { | |
407 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, | |
408 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, | |
409 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, | |
410 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, | |
411 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, | |
412 | }; | |
413 | ||
f6bc11e4 YH |
414 | enum { |
415 | MLX4_DEVICE_STATE_UP = 1 << 0, | |
416 | MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, | |
417 | }; | |
418 | ||
c69453e2 YH |
419 | enum { |
420 | MLX4_INTERFACE_STATE_UP = 1 << 0, | |
421 | MLX4_INTERFACE_STATE_DELETION = 1 << 1, | |
422 | }; | |
423 | ||
00f5ce99 JM |
424 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ |
425 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) | |
426 | ||
32a173c7 SM |
427 | enum mlx4_module_id { |
428 | MLX4_MODULE_ID_SFP = 0x3, | |
429 | MLX4_MODULE_ID_QSFP = 0xC, | |
430 | MLX4_MODULE_ID_QSFP_PLUS = 0xD, | |
431 | MLX4_MODULE_ID_QSFP28 = 0x11, | |
432 | }; | |
433 | ||
ea54b10c JM |
434 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
435 | { | |
436 | return (major << 32) | (minor << 16) | subminor; | |
437 | } | |
438 | ||
3fc929e2 | 439 | struct mlx4_phys_caps { |
6634961c JM |
440 | u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; |
441 | u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; | |
3fc929e2 | 442 | u32 num_phys_eqs; |
47605df9 JM |
443 | u32 base_sqpn; |
444 | u32 base_proxy_sqpn; | |
445 | u32 base_tunnel_sqpn; | |
3fc929e2 MA |
446 | }; |
447 | ||
225c7b1f RD |
448 | struct mlx4_caps { |
449 | u64 fw_ver; | |
623ed84b | 450 | u32 function; |
225c7b1f | 451 | int num_ports; |
5ae2a7a8 | 452 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 453 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 454 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
455 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
456 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
457 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
458 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
459 | int trans_type[MLX4_MAX_PORTS + 1]; |
460 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
461 | int wavelength[MLX4_MAX_PORTS + 1]; | |
462 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
463 | int local_ca_ack_delay; |
464 | int num_uars; | |
f5311ac1 | 465 | u32 uar_page_size; |
225c7b1f RD |
466 | int bf_reg_size; |
467 | int bf_regs_per_page; | |
468 | int max_sq_sg; | |
469 | int max_rq_sg; | |
470 | int num_qps; | |
471 | int max_wqes; | |
472 | int max_sq_desc_sz; | |
473 | int max_rq_desc_sz; | |
474 | int max_qp_init_rdma; | |
475 | int max_qp_dest_rdma; | |
99ec41d0 | 476 | u32 *qp0_qkey; |
47605df9 JM |
477 | u32 *qp0_proxy; |
478 | u32 *qp1_proxy; | |
479 | u32 *qp0_tunnel; | |
480 | u32 *qp1_tunnel; | |
225c7b1f RD |
481 | int num_srqs; |
482 | int max_srq_wqes; | |
483 | int max_srq_sge; | |
484 | int reserved_srqs; | |
485 | int num_cqs; | |
486 | int max_cqes; | |
487 | int reserved_cqs; | |
7ae0e400 | 488 | int num_sys_eqs; |
225c7b1f RD |
489 | int num_eqs; |
490 | int reserved_eqs; | |
b8dd786f | 491 | int num_comp_vectors; |
0b7ca5a9 | 492 | int comp_pool; |
225c7b1f | 493 | int num_mpts; |
a5bbe892 | 494 | int max_fmr_maps; |
2b8fb286 | 495 | int num_mtts; |
225c7b1f RD |
496 | int fmr_reserved_mtts; |
497 | int reserved_mtts; | |
498 | int reserved_mrws; | |
499 | int reserved_uars; | |
500 | int num_mgms; | |
501 | int num_amgms; | |
502 | int reserved_mcgs; | |
503 | int num_qp_per_mgm; | |
c96d97f4 | 504 | int steering_mode; |
7d077cd3 | 505 | int dmfs_high_steer_mode; |
0ff1fb65 | 506 | int fs_log_max_ucast_qp_range_size; |
225c7b1f RD |
507 | int num_pds; |
508 | int reserved_pds; | |
012a8ff5 SH |
509 | int max_xrcds; |
510 | int reserved_xrcds; | |
225c7b1f | 511 | int mtt_entry_sz; |
149983af | 512 | u32 max_msg_sz; |
225c7b1f | 513 | u32 page_size_cap; |
52eafc68 | 514 | u64 flags; |
b3416f44 | 515 | u64 flags2; |
95d04f07 RD |
516 | u32 bmme_flags; |
517 | u32 reserved_lkey; | |
225c7b1f | 518 | u16 stat_rate_support; |
5ae2a7a8 | 519 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 520 | int max_gso_sz; |
b3416f44 | 521 | int max_rss_tbl_sz; |
93fc9e1b YP |
522 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
523 | int reserved_qps; | |
524 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
525 | int log_num_macs; | |
526 | int log_num_vlans; | |
7ff93f8b YP |
527 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
528 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
529 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
530 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 531 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 532 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 533 | u32 max_counters; |
096335b3 | 534 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
1ffeb2eb | 535 | u16 sqp_demux; |
08ff3235 OG |
536 | u32 eqe_size; |
537 | u32 cqe_size; | |
538 | u8 eqe_factor; | |
539 | u32 userspace_caps; /* userspace must be aware of these */ | |
540 | u32 function_caps; /* VFs must be aware of these */ | |
ddd8a6c1 | 541 | u16 hca_core_clock; |
8e1a28e8 | 542 | u64 phys_port_id[MLX4_MAX_PORTS + 1]; |
7ffdf726 | 543 | int tunnel_offload_mode; |
f8c6455b | 544 | u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; |
ddae0349 | 545 | u8 alloc_res_qp_mask; |
7d077cd3 MB |
546 | u32 dmfs_high_rate_qpn_base; |
547 | u32 dmfs_high_rate_qpn_range; | |
225c7b1f RD |
548 | }; |
549 | ||
550 | struct mlx4_buf_list { | |
551 | void *buf; | |
552 | dma_addr_t map; | |
553 | }; | |
554 | ||
555 | struct mlx4_buf { | |
b57aacfa RD |
556 | struct mlx4_buf_list direct; |
557 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
558 | int nbufs; |
559 | int npages; | |
560 | int page_shift; | |
561 | }; | |
562 | ||
563 | struct mlx4_mtt { | |
2b8fb286 | 564 | u32 offset; |
225c7b1f RD |
565 | int order; |
566 | int page_shift; | |
567 | }; | |
568 | ||
6296883c YP |
569 | enum { |
570 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
571 | }; | |
572 | ||
573 | struct mlx4_db_pgdir { | |
574 | struct list_head list; | |
575 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
576 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
577 | unsigned long *bits[2]; | |
578 | __be32 *db_page; | |
579 | dma_addr_t db_dma; | |
580 | }; | |
581 | ||
582 | struct mlx4_ib_user_db_page; | |
583 | ||
584 | struct mlx4_db { | |
585 | __be32 *db; | |
586 | union { | |
587 | struct mlx4_db_pgdir *pgdir; | |
588 | struct mlx4_ib_user_db_page *user_page; | |
589 | } u; | |
590 | dma_addr_t dma; | |
591 | int index; | |
592 | int order; | |
593 | }; | |
594 | ||
38ae6a53 YP |
595 | struct mlx4_hwq_resources { |
596 | struct mlx4_db db; | |
597 | struct mlx4_mtt mtt; | |
598 | struct mlx4_buf buf; | |
599 | }; | |
600 | ||
225c7b1f RD |
601 | struct mlx4_mr { |
602 | struct mlx4_mtt mtt; | |
603 | u64 iova; | |
604 | u64 size; | |
605 | u32 key; | |
606 | u32 pd; | |
607 | u32 access; | |
608 | int enabled; | |
609 | }; | |
610 | ||
804d6a89 SM |
611 | enum mlx4_mw_type { |
612 | MLX4_MW_TYPE_1 = 1, | |
613 | MLX4_MW_TYPE_2 = 2, | |
614 | }; | |
615 | ||
616 | struct mlx4_mw { | |
617 | u32 key; | |
618 | u32 pd; | |
619 | enum mlx4_mw_type type; | |
620 | int enabled; | |
621 | }; | |
622 | ||
8ad11fb6 JM |
623 | struct mlx4_fmr { |
624 | struct mlx4_mr mr; | |
625 | struct mlx4_mpt_entry *mpt; | |
626 | __be64 *mtts; | |
627 | dma_addr_t dma_handle; | |
628 | int max_pages; | |
629 | int max_maps; | |
630 | int maps; | |
631 | u8 page_shift; | |
632 | }; | |
633 | ||
225c7b1f RD |
634 | struct mlx4_uar { |
635 | unsigned long pfn; | |
636 | int index; | |
c1b43dca EC |
637 | struct list_head bf_list; |
638 | unsigned free_bf_bmap; | |
639 | void __iomem *map; | |
640 | void __iomem *bf_map; | |
641 | }; | |
642 | ||
643 | struct mlx4_bf { | |
7dfa4b41 | 644 | unsigned int offset; |
c1b43dca EC |
645 | int buf_size; |
646 | struct mlx4_uar *uar; | |
647 | void __iomem *reg; | |
225c7b1f RD |
648 | }; |
649 | ||
650 | struct mlx4_cq { | |
651 | void (*comp) (struct mlx4_cq *); | |
652 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
653 | ||
654 | struct mlx4_uar *uar; | |
655 | ||
656 | u32 cons_index; | |
657 | ||
2eacc23c | 658 | u16 irq; |
225c7b1f RD |
659 | __be32 *set_ci_db; |
660 | __be32 *arm_db; | |
661 | int arm_sn; | |
662 | ||
663 | int cqn; | |
b8dd786f | 664 | unsigned vector; |
225c7b1f RD |
665 | |
666 | atomic_t refcount; | |
667 | struct completion free; | |
3dca0f42 MB |
668 | struct { |
669 | struct list_head list; | |
670 | void (*comp)(struct mlx4_cq *); | |
671 | void *priv; | |
672 | } tasklet_ctx; | |
225c7b1f RD |
673 | }; |
674 | ||
675 | struct mlx4_qp { | |
676 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
677 | ||
678 | int qpn; | |
679 | ||
680 | atomic_t refcount; | |
681 | struct completion free; | |
682 | }; | |
683 | ||
684 | struct mlx4_srq { | |
685 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
686 | ||
687 | int srqn; | |
688 | int max; | |
689 | int max_gs; | |
690 | int wqe_shift; | |
691 | ||
692 | atomic_t refcount; | |
693 | struct completion free; | |
694 | }; | |
695 | ||
696 | struct mlx4_av { | |
697 | __be32 port_pd; | |
698 | u8 reserved1; | |
699 | u8 g_slid; | |
700 | __be16 dlid; | |
701 | u8 reserved2; | |
702 | u8 gid_index; | |
703 | u8 stat_rate; | |
704 | u8 hop_limit; | |
705 | __be32 sl_tclass_flowlabel; | |
706 | u8 dgid[16]; | |
707 | }; | |
708 | ||
fa417f7b EC |
709 | struct mlx4_eth_av { |
710 | __be32 port_pd; | |
711 | u8 reserved1; | |
712 | u8 smac_idx; | |
713 | u16 reserved2; | |
714 | u8 reserved3; | |
715 | u8 gid_index; | |
716 | u8 stat_rate; | |
717 | u8 hop_limit; | |
718 | __be32 sl_tclass_flowlabel; | |
719 | u8 dgid[16]; | |
5ea8bbfc JM |
720 | u8 s_mac[6]; |
721 | u8 reserved4[2]; | |
fa417f7b | 722 | __be16 vlan; |
574e2af7 | 723 | u8 mac[ETH_ALEN]; |
fa417f7b EC |
724 | }; |
725 | ||
726 | union mlx4_ext_av { | |
727 | struct mlx4_av ib; | |
728 | struct mlx4_eth_av eth; | |
729 | }; | |
730 | ||
f2a3f6a3 OG |
731 | struct mlx4_counter { |
732 | u8 reserved1[3]; | |
733 | u8 counter_mode; | |
734 | __be32 num_ifc; | |
735 | u32 reserved2[2]; | |
736 | __be64 rx_frames; | |
737 | __be64 rx_bytes; | |
738 | __be64 tx_frames; | |
739 | __be64 tx_bytes; | |
740 | }; | |
741 | ||
5a0d0a61 JM |
742 | struct mlx4_quotas { |
743 | int qp; | |
744 | int cq; | |
745 | int srq; | |
746 | int mpt; | |
747 | int mtt; | |
748 | int counter; | |
749 | int xrcd; | |
750 | }; | |
751 | ||
1ab95d37 MB |
752 | struct mlx4_vf_dev { |
753 | u8 min_port; | |
754 | u8 n_ports; | |
755 | }; | |
756 | ||
872bf2fb | 757 | struct mlx4_dev_persistent { |
225c7b1f | 758 | struct pci_dev *pdev; |
872bf2fb YH |
759 | struct mlx4_dev *dev; |
760 | int nvfs[MLX4_MAX_PORTS + 1]; | |
761 | int num_vfs; | |
dd0eefe3 YH |
762 | enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; |
763 | enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; | |
ad9a0bf0 YH |
764 | struct work_struct catas_work; |
765 | struct workqueue_struct *catas_wq; | |
f6bc11e4 YH |
766 | struct mutex device_state_mutex; /* protect HW state */ |
767 | u8 state; | |
c69453e2 YH |
768 | struct mutex interface_state_mutex; /* protect SW state */ |
769 | u8 interface_state; | |
872bf2fb YH |
770 | }; |
771 | ||
772 | struct mlx4_dev { | |
773 | struct mlx4_dev_persistent *persist; | |
225c7b1f | 774 | unsigned long flags; |
623ed84b | 775 | unsigned long num_slaves; |
225c7b1f | 776 | struct mlx4_caps caps; |
3fc929e2 | 777 | struct mlx4_phys_caps phys_caps; |
5a0d0a61 | 778 | struct mlx4_quotas quotas; |
225c7b1f | 779 | struct radix_tree_root qp_table_tree; |
725c8999 | 780 | u8 rev_id; |
cd9281d8 | 781 | char board_id[MLX4_BOARD_ID_LEN]; |
6e7136ed | 782 | int numa_node; |
3c439b55 | 783 | int oper_log_mgm_entry_size; |
592e49dd HHZ |
784 | u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; |
785 | u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; | |
1ab95d37 | 786 | struct mlx4_vf_dev *dev_vfs; |
225c7b1f RD |
787 | }; |
788 | ||
00f5ce99 JM |
789 | struct mlx4_eqe { |
790 | u8 reserved1; | |
791 | u8 type; | |
792 | u8 reserved2; | |
793 | u8 subtype; | |
794 | union { | |
795 | u32 raw[6]; | |
796 | struct { | |
797 | __be32 cqn; | |
798 | } __packed comp; | |
799 | struct { | |
800 | u16 reserved1; | |
801 | __be16 token; | |
802 | u32 reserved2; | |
803 | u8 reserved3[3]; | |
804 | u8 status; | |
805 | __be64 out_param; | |
806 | } __packed cmd; | |
807 | struct { | |
808 | __be32 qpn; | |
809 | } __packed qp; | |
810 | struct { | |
811 | __be32 srqn; | |
812 | } __packed srq; | |
813 | struct { | |
814 | __be32 cqn; | |
815 | u32 reserved1; | |
816 | u8 reserved2[3]; | |
817 | u8 syndrome; | |
818 | } __packed cq_err; | |
819 | struct { | |
820 | u32 reserved1[2]; | |
821 | __be32 port; | |
822 | } __packed port_change; | |
823 | struct { | |
824 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 | |
825 | u32 reserved; | |
826 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; | |
827 | } __packed comm_channel_arm; | |
828 | struct { | |
829 | u8 port; | |
830 | u8 reserved[3]; | |
831 | __be64 mac; | |
832 | } __packed mac_update; | |
833 | struct { | |
834 | __be32 slave_id; | |
835 | } __packed flr_event; | |
836 | struct { | |
837 | __be16 current_temperature; | |
838 | __be16 warning_threshold; | |
839 | } __packed warming; | |
840 | struct { | |
841 | u8 reserved[3]; | |
842 | u8 port; | |
843 | union { | |
844 | struct { | |
845 | __be16 mstr_sm_lid; | |
846 | __be16 port_lid; | |
847 | __be32 changed_attr; | |
848 | u8 reserved[3]; | |
849 | u8 mstr_sm_sl; | |
850 | __be64 gid_prefix; | |
851 | } __packed port_info; | |
852 | struct { | |
853 | __be32 block_ptr; | |
854 | __be32 tbl_entries_mask; | |
855 | } __packed tbl_change_info; | |
856 | } params; | |
857 | } __packed port_mgmt_change; | |
858 | } event; | |
859 | u8 slave_id; | |
860 | u8 reserved3[2]; | |
861 | u8 owner; | |
862 | } __packed; | |
863 | ||
225c7b1f RD |
864 | struct mlx4_init_port_param { |
865 | int set_guid0; | |
866 | int set_node_guid; | |
867 | int set_si_guid; | |
868 | u16 mtu; | |
869 | int port_width_cap; | |
870 | u16 vl_cap; | |
871 | u16 max_gid; | |
872 | u16 max_pkey; | |
873 | u64 guid0; | |
874 | u64 node_guid; | |
875 | u64 si_guid; | |
876 | }; | |
877 | ||
32a173c7 SM |
878 | #define MAD_IFC_DATA_SZ 192 |
879 | /* MAD IFC Mailbox */ | |
880 | struct mlx4_mad_ifc { | |
881 | u8 base_version; | |
882 | u8 mgmt_class; | |
883 | u8 class_version; | |
884 | u8 method; | |
885 | __be16 status; | |
886 | __be16 class_specific; | |
887 | __be64 tid; | |
888 | __be16 attr_id; | |
889 | __be16 resv; | |
890 | __be32 attr_mod; | |
891 | __be64 mkey; | |
892 | __be16 dr_slid; | |
893 | __be16 dr_dlid; | |
894 | u8 reserved[28]; | |
895 | u8 data[MAD_IFC_DATA_SZ]; | |
896 | } __packed; | |
897 | ||
7ff93f8b YP |
898 | #define mlx4_foreach_port(port, dev, type) \ |
899 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 900 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 901 | |
026149cb JM |
902 | #define mlx4_foreach_non_ib_transport_port(port, dev) \ |
903 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
904 | if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) | |
905 | ||
65dab25d JM |
906 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
907 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
908 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ | |
909 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
623ed84b | 910 | |
752a50ca JM |
911 | #define MLX4_INVALID_SLAVE_ID 0xFF |
912 | ||
00f5ce99 JM |
913 | void handle_port_mgmt_change_event(struct work_struct *work); |
914 | ||
2aca1172 JM |
915 | static inline int mlx4_master_func_num(struct mlx4_dev *dev) |
916 | { | |
917 | return dev->caps.function; | |
918 | } | |
919 | ||
623ed84b JM |
920 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
921 | { | |
922 | return dev->flags & MLX4_FLAG_MASTER; | |
923 | } | |
924 | ||
5a0d0a61 JM |
925 | static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) |
926 | { | |
927 | return dev->phys_caps.base_sqpn + 8 + | |
928 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); | |
929 | } | |
930 | ||
623ed84b JM |
931 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) |
932 | { | |
47605df9 | 933 | return (qpn < dev->phys_caps.base_sqpn + 8 + |
d57febe1 MB |
934 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && |
935 | qpn >= dev->phys_caps.base_sqpn) || | |
936 | (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); | |
e2c76824 JM |
937 | } |
938 | ||
939 | static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) | |
940 | { | |
47605df9 | 941 | int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; |
e2c76824 | 942 | |
47605df9 | 943 | if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) |
e2c76824 JM |
944 | return 1; |
945 | ||
946 | return 0; | |
623ed84b | 947 | } |
fa417f7b | 948 | |
623ed84b JM |
949 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
950 | { | |
951 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
952 | } | |
953 | ||
954 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
955 | { | |
956 | return dev->flags & MLX4_FLAG_SLAVE; | |
957 | } | |
fa417f7b | 958 | |
225c7b1f | 959 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
40f2287b | 960 | struct mlx4_buf *buf, gfp_t gfp); |
225c7b1f | 961 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); |
1c69fc2a RD |
962 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
963 | { | |
313abe55 | 964 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 965 | return buf->direct.buf + offset; |
1c69fc2a | 966 | else |
b57aacfa | 967 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
968 | (offset & (PAGE_SIZE - 1)); |
969 | } | |
225c7b1f RD |
970 | |
971 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
972 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
973 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
974 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
975 | |
976 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
977 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
163561a4 | 978 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); |
c1b43dca | 979 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); |
225c7b1f RD |
980 | |
981 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
982 | struct mlx4_mtt *mtt); | |
983 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
984 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
985 | ||
986 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
987 | int npages, int page_shift, struct mlx4_mr *mr); | |
61083720 | 988 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); |
225c7b1f | 989 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); |
804d6a89 SM |
990 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
991 | struct mlx4_mw *mw); | |
992 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
993 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
225c7b1f RD |
994 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
995 | int start_index, int npages, u64 *page_list); | |
996 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
40f2287b | 997 | struct mlx4_buf *buf, gfp_t gfp); |
225c7b1f | 998 | |
40f2287b JK |
999 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, |
1000 | gfp_t gfp); | |
6296883c YP |
1001 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); |
1002 | ||
38ae6a53 YP |
1003 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
1004 | int size, int max_direct); | |
1005 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
1006 | int size); | |
1007 | ||
225c7b1f | 1008 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 1009 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
ec693d47 | 1010 | unsigned vector, int collapsed, int timestamp_en); |
225c7b1f | 1011 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
ddae0349 EE |
1012 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, |
1013 | int *base, u8 flags); | |
a3cdcbfa YP |
1014 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); |
1015 | ||
40f2287b JK |
1016 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, |
1017 | gfp_t gfp); | |
225c7b1f RD |
1018 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
1019 | ||
18abd5ea SH |
1020 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
1021 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
1022 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
1023 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 1024 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 1025 | |
5ae2a7a8 | 1026 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
1027 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
1028 | ||
ffe455ad EE |
1029 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
1030 | int block_mcast_loopback, enum mlx4_protocol prot); | |
1031 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
1032 | enum mlx4_protocol prot); | |
521e575b | 1033 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
1034 | u8 port, int block_mcast_loopback, |
1035 | enum mlx4_protocol protocol, u64 *reg_id); | |
da995a8a | 1036 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
1037 | enum mlx4_protocol protocol, u64 reg_id); |
1038 | ||
1039 | enum { | |
1040 | MLX4_DOMAIN_UVERBS = 0x1000, | |
1041 | MLX4_DOMAIN_ETHTOOL = 0x2000, | |
1042 | MLX4_DOMAIN_RFS = 0x3000, | |
1043 | MLX4_DOMAIN_NIC = 0x5000, | |
1044 | }; | |
1045 | ||
1046 | enum mlx4_net_trans_rule_id { | |
1047 | MLX4_NET_TRANS_RULE_ID_ETH = 0, | |
1048 | MLX4_NET_TRANS_RULE_ID_IB, | |
1049 | MLX4_NET_TRANS_RULE_ID_IPV6, | |
1050 | MLX4_NET_TRANS_RULE_ID_IPV4, | |
1051 | MLX4_NET_TRANS_RULE_ID_TCP, | |
1052 | MLX4_NET_TRANS_RULE_ID_UDP, | |
7ffdf726 | 1053 | MLX4_NET_TRANS_RULE_ID_VXLAN, |
0ff1fb65 HHZ |
1054 | MLX4_NET_TRANS_RULE_NUM, /* should be last */ |
1055 | }; | |
1056 | ||
a8edc3bf HHZ |
1057 | extern const u16 __sw_id_hw[]; |
1058 | ||
7fb40f87 HHZ |
1059 | static inline int map_hw_to_sw_id(u16 header_id) |
1060 | { | |
1061 | ||
1062 | int i; | |
1063 | for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { | |
1064 | if (header_id == __sw_id_hw[i]) | |
1065 | return i; | |
1066 | } | |
1067 | return -EINVAL; | |
1068 | } | |
1069 | ||
0ff1fb65 | 1070 | enum mlx4_net_trans_promisc_mode { |
f9162539 HHZ |
1071 | MLX4_FS_REGULAR = 1, |
1072 | MLX4_FS_ALL_DEFAULT, | |
1073 | MLX4_FS_MC_DEFAULT, | |
1074 | MLX4_FS_UC_SNIFFER, | |
1075 | MLX4_FS_MC_SNIFFER, | |
c2c19dc3 | 1076 | MLX4_FS_MODE_NUM, /* should be last */ |
0ff1fb65 HHZ |
1077 | }; |
1078 | ||
1079 | struct mlx4_spec_eth { | |
574e2af7 JP |
1080 | u8 dst_mac[ETH_ALEN]; |
1081 | u8 dst_mac_msk[ETH_ALEN]; | |
1082 | u8 src_mac[ETH_ALEN]; | |
1083 | u8 src_mac_msk[ETH_ALEN]; | |
0ff1fb65 HHZ |
1084 | u8 ether_type_enable; |
1085 | __be16 ether_type; | |
1086 | __be16 vlan_id_msk; | |
1087 | __be16 vlan_id; | |
1088 | }; | |
1089 | ||
1090 | struct mlx4_spec_tcp_udp { | |
1091 | __be16 dst_port; | |
1092 | __be16 dst_port_msk; | |
1093 | __be16 src_port; | |
1094 | __be16 src_port_msk; | |
1095 | }; | |
1096 | ||
1097 | struct mlx4_spec_ipv4 { | |
1098 | __be32 dst_ip; | |
1099 | __be32 dst_ip_msk; | |
1100 | __be32 src_ip; | |
1101 | __be32 src_ip_msk; | |
1102 | }; | |
1103 | ||
1104 | struct mlx4_spec_ib { | |
ba60a356 | 1105 | __be32 l3_qpn; |
0ff1fb65 HHZ |
1106 | __be32 qpn_msk; |
1107 | u8 dst_gid[16]; | |
1108 | u8 dst_gid_msk[16]; | |
1109 | }; | |
1110 | ||
7ffdf726 OG |
1111 | struct mlx4_spec_vxlan { |
1112 | __be32 vni; | |
1113 | __be32 vni_mask; | |
1114 | ||
1115 | }; | |
1116 | ||
0ff1fb65 HHZ |
1117 | struct mlx4_spec_list { |
1118 | struct list_head list; | |
1119 | enum mlx4_net_trans_rule_id id; | |
1120 | union { | |
1121 | struct mlx4_spec_eth eth; | |
1122 | struct mlx4_spec_ib ib; | |
1123 | struct mlx4_spec_ipv4 ipv4; | |
1124 | struct mlx4_spec_tcp_udp tcp_udp; | |
7ffdf726 | 1125 | struct mlx4_spec_vxlan vxlan; |
0ff1fb65 HHZ |
1126 | }; |
1127 | }; | |
1128 | ||
1129 | enum mlx4_net_trans_hw_rule_queue { | |
1130 | MLX4_NET_TRANS_Q_FIFO, | |
1131 | MLX4_NET_TRANS_Q_LIFO, | |
1132 | }; | |
1133 | ||
1134 | struct mlx4_net_trans_rule { | |
1135 | struct list_head list; | |
1136 | enum mlx4_net_trans_hw_rule_queue queue_mode; | |
1137 | bool exclusive; | |
1138 | bool allow_loopback; | |
1139 | enum mlx4_net_trans_promisc_mode promisc_mode; | |
1140 | u8 port; | |
1141 | u16 priority; | |
1142 | u32 qpn; | |
1143 | }; | |
1144 | ||
3cd0e178 | 1145 | struct mlx4_net_trans_rule_hw_ctrl { |
bcf37297 HHZ |
1146 | __be16 prio; |
1147 | u8 type; | |
1148 | u8 flags; | |
3cd0e178 HHZ |
1149 | u8 rsvd1; |
1150 | u8 funcid; | |
1151 | u8 vep; | |
1152 | u8 port; | |
1153 | __be32 qpn; | |
1154 | __be32 rsvd2; | |
1155 | }; | |
1156 | ||
1157 | struct mlx4_net_trans_rule_hw_ib { | |
1158 | u8 size; | |
1159 | u8 rsvd1; | |
1160 | __be16 id; | |
1161 | u32 rsvd2; | |
ba60a356 | 1162 | __be32 l3_qpn; |
3cd0e178 HHZ |
1163 | __be32 qpn_mask; |
1164 | u8 dst_gid[16]; | |
1165 | u8 dst_gid_msk[16]; | |
1166 | } __packed; | |
1167 | ||
1168 | struct mlx4_net_trans_rule_hw_eth { | |
1169 | u8 size; | |
1170 | u8 rsvd; | |
1171 | __be16 id; | |
1172 | u8 rsvd1[6]; | |
1173 | u8 dst_mac[6]; | |
1174 | u16 rsvd2; | |
1175 | u8 dst_mac_msk[6]; | |
1176 | u16 rsvd3; | |
1177 | u8 src_mac[6]; | |
1178 | u16 rsvd4; | |
1179 | u8 src_mac_msk[6]; | |
1180 | u8 rsvd5; | |
1181 | u8 ether_type_enable; | |
1182 | __be16 ether_type; | |
ba60a356 HHZ |
1183 | __be16 vlan_tag_msk; |
1184 | __be16 vlan_tag; | |
3cd0e178 HHZ |
1185 | } __packed; |
1186 | ||
1187 | struct mlx4_net_trans_rule_hw_tcp_udp { | |
1188 | u8 size; | |
1189 | u8 rsvd; | |
1190 | __be16 id; | |
1191 | __be16 rsvd1[3]; | |
1192 | __be16 dst_port; | |
1193 | __be16 rsvd2; | |
1194 | __be16 dst_port_msk; | |
1195 | __be16 rsvd3; | |
1196 | __be16 src_port; | |
1197 | __be16 rsvd4; | |
1198 | __be16 src_port_msk; | |
1199 | } __packed; | |
1200 | ||
1201 | struct mlx4_net_trans_rule_hw_ipv4 { | |
1202 | u8 size; | |
1203 | u8 rsvd; | |
1204 | __be16 id; | |
1205 | __be32 rsvd1; | |
1206 | __be32 dst_ip; | |
1207 | __be32 dst_ip_msk; | |
1208 | __be32 src_ip; | |
1209 | __be32 src_ip_msk; | |
1210 | } __packed; | |
1211 | ||
7ffdf726 OG |
1212 | struct mlx4_net_trans_rule_hw_vxlan { |
1213 | u8 size; | |
1214 | u8 rsvd; | |
1215 | __be16 id; | |
1216 | __be32 rsvd1; | |
1217 | __be32 vni; | |
1218 | __be32 vni_mask; | |
1219 | } __packed; | |
1220 | ||
3cd0e178 HHZ |
1221 | struct _rule_hw { |
1222 | union { | |
1223 | struct { | |
1224 | u8 size; | |
1225 | u8 rsvd; | |
1226 | __be16 id; | |
1227 | }; | |
1228 | struct mlx4_net_trans_rule_hw_eth eth; | |
1229 | struct mlx4_net_trans_rule_hw_ib ib; | |
1230 | struct mlx4_net_trans_rule_hw_ipv4 ipv4; | |
1231 | struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; | |
7ffdf726 | 1232 | struct mlx4_net_trans_rule_hw_vxlan vxlan; |
3cd0e178 HHZ |
1233 | }; |
1234 | }; | |
1235 | ||
7ffdf726 OG |
1236 | enum { |
1237 | VXLAN_STEER_BY_OUTER_MAC = 1 << 0, | |
1238 | VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, | |
1239 | VXLAN_STEER_BY_VSID_VNI = 1 << 2, | |
1240 | VXLAN_STEER_BY_INNER_MAC = 1 << 3, | |
1241 | VXLAN_STEER_BY_INNER_VLAN = 1 << 4, | |
1242 | }; | |
1243 | ||
1244 | ||
592e49dd HHZ |
1245 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, |
1246 | enum mlx4_net_trans_promisc_mode mode); | |
1247 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, | |
1248 | enum mlx4_net_trans_promisc_mode mode); | |
1679200f YP |
1249 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
1250 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1251 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1252 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1253 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
1254 | ||
ffe455ad EE |
1255 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
1256 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
16a10ffd YB |
1257 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
1258 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
93ece0c1 | 1259 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); |
9a9a232a YP |
1260 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
1261 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | |
1262 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | |
1263 | u8 promisc); | |
e5395e92 AV |
1264 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); |
1265 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
1266 | u8 *pg, u16 *ratelimit); | |
1b136de1 | 1267 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); |
dd5f03be | 1268 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); |
4c3eb3ca | 1269 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 | 1270 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2009d005 | 1271 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
2a2336f8 | 1272 | |
8ad11fb6 JM |
1273 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
1274 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
1275 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1276 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
1277 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1278 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1279 | u32 *lkey, u32 *rkey); | |
1280 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1281 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 1282 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
d9236c3f AV |
1283 | int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, |
1284 | int *vector); | |
0b7ca5a9 | 1285 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); |
8ad11fb6 | 1286 | |
35f6f453 AV |
1287 | int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); |
1288 | ||
8e1a28e8 | 1289 | int mlx4_get_phys_port_id(struct mlx4_dev *dev); |
14c07b13 YP |
1290 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
1291 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
1292 | ||
f2a3f6a3 OG |
1293 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
1294 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
1295 | ||
0ff1fb65 HHZ |
1296 | int mlx4_flow_attach(struct mlx4_dev *dev, |
1297 | struct mlx4_net_trans_rule *rule, u64 *reg_id); | |
1298 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); | |
c2c19dc3 HHZ |
1299 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, |
1300 | enum mlx4_net_trans_promisc_mode flow_type); | |
1301 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, | |
1302 | enum mlx4_net_trans_rule_id id); | |
1303 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); | |
0ff1fb65 | 1304 | |
b95089d0 OG |
1305 | int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, |
1306 | int port, int qpn, u16 prio, u64 *reg_id); | |
1307 | ||
54679e14 JM |
1308 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, |
1309 | int i, int val); | |
1310 | ||
396f2feb JM |
1311 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); |
1312 | ||
993c401e JM |
1313 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); |
1314 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1315 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1316 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); | |
1317 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); | |
1318 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); | |
1319 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); | |
1320 | ||
afa8fd1d JM |
1321 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
1322 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); | |
9cd59352 JM |
1323 | |
1324 | int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, | |
1325 | int *slave_id); | |
1326 | int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, | |
1327 | u8 *gid); | |
993c401e | 1328 | |
4de65803 MB |
1329 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, |
1330 | u32 max_range_qpn); | |
1331 | ||
ec693d47 AV |
1332 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); |
1333 | ||
f74462ac MB |
1334 | struct mlx4_active_ports { |
1335 | DECLARE_BITMAP(ports, MLX4_MAX_PORTS); | |
1336 | }; | |
1337 | /* Returns a bitmap of the physical ports which are assigned to slave */ | |
1338 | struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); | |
1339 | ||
1340 | /* Returns the physical port that represents the virtual port of the slave, */ | |
1341 | /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ | |
1342 | /* mapping is returned. */ | |
1343 | int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); | |
1344 | ||
1345 | struct mlx4_slaves_pport { | |
1346 | DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); | |
1347 | }; | |
1348 | /* Returns a bitmap of all slaves that are assigned to port. */ | |
1349 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, | |
1350 | int port); | |
1351 | ||
1352 | /* Returns a bitmap of all slaves that are assigned exactly to all the */ | |
1353 | /* the ports that are set in crit_ports. */ | |
1354 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( | |
1355 | struct mlx4_dev *dev, | |
1356 | const struct mlx4_active_ports *crit_ports); | |
1357 | ||
1358 | /* Returns the slave's virtual port that represents the physical port. */ | |
1359 | int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); | |
1360 | ||
449fc488 | 1361 | int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); |
d18f141a OG |
1362 | |
1363 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); | |
97982f5a | 1364 | int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); |
65fed8a8 JM |
1365 | int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); |
1366 | int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, | |
1367 | int enable); | |
e630664c MB |
1368 | int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, |
1369 | struct mlx4_mpt_entry ***mpt_entry); | |
1370 | int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, | |
1371 | struct mlx4_mpt_entry **mpt_entry); | |
1372 | int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, | |
1373 | u32 pdn); | |
1374 | int mlx4_mr_hw_change_access(struct mlx4_dev *dev, | |
1375 | struct mlx4_mpt_entry *mpt_entry, | |
1376 | u32 access); | |
1377 | void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, | |
1378 | struct mlx4_mpt_entry **mpt_entry); | |
1379 | void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
1380 | int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, | |
1381 | u64 iova, u64 size, int npages, | |
1382 | int page_shift, struct mlx4_mpt_entry *mpt_entry); | |
2599d858 | 1383 | |
32a173c7 SM |
1384 | int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, |
1385 | u16 offset, u16 size, u8 *data); | |
1386 | ||
2599d858 AV |
1387 | /* Returns true if running in low memory profile (kdump kernel) */ |
1388 | static inline bool mlx4_low_memory_profile(void) | |
1389 | { | |
48ea526a | 1390 | return is_kdump_kernel(); |
2599d858 AV |
1391 | } |
1392 | ||
adbc7ac5 SM |
1393 | /* ACCESS REG commands */ |
1394 | enum mlx4_access_reg_method { | |
1395 | MLX4_ACCESS_REG_QUERY = 0x1, | |
1396 | MLX4_ACCESS_REG_WRITE = 0x2, | |
1397 | }; | |
1398 | ||
1399 | /* ACCESS PTYS Reg command */ | |
1400 | enum mlx4_ptys_proto { | |
1401 | MLX4_PTYS_IB = 1<<0, | |
1402 | MLX4_PTYS_EN = 1<<2, | |
1403 | }; | |
1404 | ||
1405 | struct mlx4_ptys_reg { | |
1406 | u8 resrvd1; | |
1407 | u8 local_port; | |
1408 | u8 resrvd2; | |
1409 | u8 proto_mask; | |
1410 | __be32 resrvd3[2]; | |
1411 | __be32 eth_proto_cap; | |
1412 | __be16 ib_width_cap; | |
1413 | __be16 ib_speed_cap; | |
1414 | __be32 resrvd4; | |
1415 | __be32 eth_proto_admin; | |
1416 | __be16 ib_width_admin; | |
1417 | __be16 ib_speed_admin; | |
1418 | __be32 resrvd5; | |
1419 | __be32 eth_proto_oper; | |
1420 | __be16 ib_width_oper; | |
1421 | __be16 ib_speed_oper; | |
1422 | __be32 resrvd6; | |
1423 | __be32 eth_proto_lp_adv; | |
1424 | } __packed; | |
1425 | ||
1426 | int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, | |
1427 | enum mlx4_access_reg_method method, | |
1428 | struct mlx4_ptys_reg *ptys_reg); | |
1429 | ||
225c7b1f | 1430 | #endif /* MLX4_DEVICE_H */ |