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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
36 | #include <linux/pci.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/radix-tree.h> | |
39 | ||
40 | #include <asm/atomic.h> | |
41 | ||
42 | enum { | |
43 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 44 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
225c7b1f RD |
45 | }; |
46 | ||
47 | enum { | |
48 | MLX4_MAX_PORTS = 2 | |
49 | }; | |
50 | ||
cd9281d8 JM |
51 | enum { |
52 | MLX4_BOARD_ID_LEN = 64 | |
53 | }; | |
54 | ||
225c7b1f RD |
55 | enum { |
56 | MLX4_DEV_CAP_FLAG_RC = 1 << 0, | |
57 | MLX4_DEV_CAP_FLAG_UC = 1 << 1, | |
58 | MLX4_DEV_CAP_FLAG_UD = 1 << 2, | |
59 | MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, | |
60 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, | |
61 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, | |
62 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, | |
7ff93f8b | 63 | MLX4_DEV_CAP_FLAG_DPDP = 1 << 12, |
417608c2 | 64 | MLX4_DEV_CAP_FLAG_BLH = 1 << 15, |
225c7b1f RD |
65 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, |
66 | MLX4_DEV_CAP_FLAG_APM = 1 << 17, | |
67 | MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, | |
68 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19, | |
69 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20, | |
96dfa684 EC |
70 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21, |
71 | MLX4_DEV_CAP_FLAG_IBOE = 1 << 30 | |
225c7b1f RD |
72 | }; |
73 | ||
95d04f07 RD |
74 | enum { |
75 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, | |
76 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
77 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
78 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
79 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
80 | }; | |
81 | ||
225c7b1f RD |
82 | enum mlx4_event { |
83 | MLX4_EVENT_TYPE_COMP = 0x00, | |
84 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
85 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
86 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
87 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
88 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
89 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
90 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
91 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
92 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
93 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
94 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
95 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
96 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
97 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
98 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
99 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
100 | MLX4_EVENT_TYPE_CMD = 0x0a | |
101 | }; | |
102 | ||
103 | enum { | |
104 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
105 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
106 | }; | |
107 | ||
108 | enum { | |
109 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
110 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
111 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
112 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
113 | MLX4_PERM_ATOMIC = 1 << 14 | |
114 | }; | |
115 | ||
116 | enum { | |
117 | MLX4_OPCODE_NOP = 0x00, | |
118 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
119 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
120 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
121 | MLX4_OPCODE_SEND = 0x0a, | |
122 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
123 | MLX4_OPCODE_LSO = 0x0e, | |
124 | MLX4_OPCODE_RDMA_READ = 0x10, | |
125 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
126 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
127 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
128 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
129 | MLX4_OPCODE_BIND_MW = 0x18, |
130 | MLX4_OPCODE_FMR = 0x19, | |
131 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
132 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
133 | ||
134 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
135 | MLX4_RECV_OPCODE_SEND = 0x01, | |
136 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
137 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
138 | ||
139 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
140 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
141 | }; | |
142 | ||
143 | enum { | |
144 | MLX4_STAT_RATE_OFFSET = 5 | |
145 | }; | |
146 | ||
29bdc883 VS |
147 | enum { |
148 | MLX4_MTT_FLAG_PRESENT = 1 | |
149 | }; | |
150 | ||
93fc9e1b YP |
151 | enum mlx4_qp_region { |
152 | MLX4_QP_REGION_FW = 0, | |
153 | MLX4_QP_REGION_ETH_ADDR, | |
154 | MLX4_QP_REGION_FC_ADDR, | |
155 | MLX4_QP_REGION_FC_EXCH, | |
156 | MLX4_NUM_QP_REGION | |
157 | }; | |
158 | ||
7ff93f8b | 159 | enum mlx4_port_type { |
27bf91d6 YP |
160 | MLX4_PORT_TYPE_IB = 1, |
161 | MLX4_PORT_TYPE_ETH = 2, | |
162 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
163 | }; |
164 | ||
2a2336f8 YP |
165 | enum mlx4_special_vlan_idx { |
166 | MLX4_NO_VLAN_IDX = 0, | |
167 | MLX4_VLAN_MISS_IDX, | |
168 | MLX4_VLAN_REGULAR | |
169 | }; | |
170 | ||
93fc9e1b YP |
171 | enum { |
172 | MLX4_NUM_FEXCH = 64 * 1024, | |
173 | }; | |
174 | ||
ea54b10c JM |
175 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
176 | { | |
177 | return (major << 32) | (minor << 16) | subminor; | |
178 | } | |
179 | ||
225c7b1f RD |
180 | struct mlx4_caps { |
181 | u64 fw_ver; | |
182 | int num_ports; | |
5ae2a7a8 | 183 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 184 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 185 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
186 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
187 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
188 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
189 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
190 | int local_ca_ack_delay; |
191 | int num_uars; | |
192 | int bf_reg_size; | |
193 | int bf_regs_per_page; | |
194 | int max_sq_sg; | |
195 | int max_rq_sg; | |
196 | int num_qps; | |
197 | int max_wqes; | |
198 | int max_sq_desc_sz; | |
199 | int max_rq_desc_sz; | |
200 | int max_qp_init_rdma; | |
201 | int max_qp_dest_rdma; | |
225c7b1f RD |
202 | int sqp_start; |
203 | int num_srqs; | |
204 | int max_srq_wqes; | |
205 | int max_srq_sge; | |
206 | int reserved_srqs; | |
207 | int num_cqs; | |
208 | int max_cqes; | |
209 | int reserved_cqs; | |
210 | int num_eqs; | |
211 | int reserved_eqs; | |
b8dd786f | 212 | int num_comp_vectors; |
225c7b1f RD |
213 | int num_mpts; |
214 | int num_mtt_segs; | |
ab6bf42e | 215 | int mtts_per_seg; |
225c7b1f RD |
216 | int fmr_reserved_mtts; |
217 | int reserved_mtts; | |
218 | int reserved_mrws; | |
219 | int reserved_uars; | |
220 | int num_mgms; | |
221 | int num_amgms; | |
222 | int reserved_mcgs; | |
223 | int num_qp_per_mgm; | |
224 | int num_pds; | |
225 | int reserved_pds; | |
226 | int mtt_entry_sz; | |
149983af | 227 | u32 max_msg_sz; |
225c7b1f RD |
228 | u32 page_size_cap; |
229 | u32 flags; | |
95d04f07 RD |
230 | u32 bmme_flags; |
231 | u32 reserved_lkey; | |
225c7b1f | 232 | u16 stat_rate_support; |
5ae2a7a8 | 233 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 234 | int max_gso_sz; |
93fc9e1b YP |
235 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
236 | int reserved_qps; | |
237 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
238 | int log_num_macs; | |
239 | int log_num_vlans; | |
240 | int log_num_prios; | |
7ff93f8b YP |
241 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
242 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
243 | u32 port_mask; | |
27bf91d6 | 244 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
225c7b1f RD |
245 | }; |
246 | ||
247 | struct mlx4_buf_list { | |
248 | void *buf; | |
249 | dma_addr_t map; | |
250 | }; | |
251 | ||
252 | struct mlx4_buf { | |
b57aacfa RD |
253 | struct mlx4_buf_list direct; |
254 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
255 | int nbufs; |
256 | int npages; | |
257 | int page_shift; | |
258 | }; | |
259 | ||
260 | struct mlx4_mtt { | |
261 | u32 first_seg; | |
262 | int order; | |
263 | int page_shift; | |
264 | }; | |
265 | ||
6296883c YP |
266 | enum { |
267 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
268 | }; | |
269 | ||
270 | struct mlx4_db_pgdir { | |
271 | struct list_head list; | |
272 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
273 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
274 | unsigned long *bits[2]; | |
275 | __be32 *db_page; | |
276 | dma_addr_t db_dma; | |
277 | }; | |
278 | ||
279 | struct mlx4_ib_user_db_page; | |
280 | ||
281 | struct mlx4_db { | |
282 | __be32 *db; | |
283 | union { | |
284 | struct mlx4_db_pgdir *pgdir; | |
285 | struct mlx4_ib_user_db_page *user_page; | |
286 | } u; | |
287 | dma_addr_t dma; | |
288 | int index; | |
289 | int order; | |
290 | }; | |
291 | ||
38ae6a53 YP |
292 | struct mlx4_hwq_resources { |
293 | struct mlx4_db db; | |
294 | struct mlx4_mtt mtt; | |
295 | struct mlx4_buf buf; | |
296 | }; | |
297 | ||
225c7b1f RD |
298 | struct mlx4_mr { |
299 | struct mlx4_mtt mtt; | |
300 | u64 iova; | |
301 | u64 size; | |
302 | u32 key; | |
303 | u32 pd; | |
304 | u32 access; | |
305 | int enabled; | |
306 | }; | |
307 | ||
8ad11fb6 JM |
308 | struct mlx4_fmr { |
309 | struct mlx4_mr mr; | |
310 | struct mlx4_mpt_entry *mpt; | |
311 | __be64 *mtts; | |
312 | dma_addr_t dma_handle; | |
313 | int max_pages; | |
314 | int max_maps; | |
315 | int maps; | |
316 | u8 page_shift; | |
317 | }; | |
318 | ||
225c7b1f RD |
319 | struct mlx4_uar { |
320 | unsigned long pfn; | |
321 | int index; | |
322 | }; | |
323 | ||
324 | struct mlx4_cq { | |
325 | void (*comp) (struct mlx4_cq *); | |
326 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
327 | ||
328 | struct mlx4_uar *uar; | |
329 | ||
330 | u32 cons_index; | |
331 | ||
332 | __be32 *set_ci_db; | |
333 | __be32 *arm_db; | |
334 | int arm_sn; | |
335 | ||
336 | int cqn; | |
b8dd786f | 337 | unsigned vector; |
225c7b1f RD |
338 | |
339 | atomic_t refcount; | |
340 | struct completion free; | |
341 | }; | |
342 | ||
343 | struct mlx4_qp { | |
344 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
345 | ||
346 | int qpn; | |
347 | ||
348 | atomic_t refcount; | |
349 | struct completion free; | |
350 | }; | |
351 | ||
352 | struct mlx4_srq { | |
353 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
354 | ||
355 | int srqn; | |
356 | int max; | |
357 | int max_gs; | |
358 | int wqe_shift; | |
359 | ||
360 | atomic_t refcount; | |
361 | struct completion free; | |
362 | }; | |
363 | ||
364 | struct mlx4_av { | |
365 | __be32 port_pd; | |
366 | u8 reserved1; | |
367 | u8 g_slid; | |
368 | __be16 dlid; | |
369 | u8 reserved2; | |
370 | u8 gid_index; | |
371 | u8 stat_rate; | |
372 | u8 hop_limit; | |
373 | __be32 sl_tclass_flowlabel; | |
374 | u8 dgid[16]; | |
375 | }; | |
376 | ||
fa417f7b EC |
377 | struct mlx4_eth_av { |
378 | __be32 port_pd; | |
379 | u8 reserved1; | |
380 | u8 smac_idx; | |
381 | u16 reserved2; | |
382 | u8 reserved3; | |
383 | u8 gid_index; | |
384 | u8 stat_rate; | |
385 | u8 hop_limit; | |
386 | __be32 sl_tclass_flowlabel; | |
387 | u8 dgid[16]; | |
388 | u32 reserved4[2]; | |
389 | __be16 vlan; | |
390 | u8 mac[6]; | |
391 | }; | |
392 | ||
393 | union mlx4_ext_av { | |
394 | struct mlx4_av ib; | |
395 | struct mlx4_eth_av eth; | |
396 | }; | |
397 | ||
225c7b1f RD |
398 | struct mlx4_dev { |
399 | struct pci_dev *pdev; | |
400 | unsigned long flags; | |
401 | struct mlx4_caps caps; | |
402 | struct radix_tree_root qp_table_tree; | |
cd9281d8 JM |
403 | u32 rev_id; |
404 | char board_id[MLX4_BOARD_ID_LEN]; | |
225c7b1f RD |
405 | }; |
406 | ||
407 | struct mlx4_init_port_param { | |
408 | int set_guid0; | |
409 | int set_node_guid; | |
410 | int set_si_guid; | |
411 | u16 mtu; | |
412 | int port_width_cap; | |
413 | u16 vl_cap; | |
414 | u16 max_gid; | |
415 | u16 max_pkey; | |
416 | u64 guid0; | |
417 | u64 node_guid; | |
418 | u64 si_guid; | |
419 | }; | |
420 | ||
7ff93f8b YP |
421 | #define mlx4_foreach_port(port, dev, type) \ |
422 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
423 | if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \ | |
424 | ~(dev)->caps.port_mask) & 1 << ((port) - 1)) | |
425 | ||
fa417f7b EC |
426 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
427 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
428 | if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \ | |
429 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
430 | ||
431 | ||
225c7b1f RD |
432 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
433 | struct mlx4_buf *buf); | |
434 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | |
1c69fc2a RD |
435 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
436 | { | |
313abe55 | 437 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 438 | return buf->direct.buf + offset; |
1c69fc2a | 439 | else |
b57aacfa | 440 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
441 | (offset & (PAGE_SIZE - 1)); |
442 | } | |
225c7b1f RD |
443 | |
444 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
445 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
446 | ||
447 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
448 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
449 | ||
450 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
451 | struct mlx4_mtt *mtt); | |
452 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
453 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
454 | ||
455 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
456 | int npages, int page_shift, struct mlx4_mr *mr); | |
457 | void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
458 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
459 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
460 | int start_index, int npages, u64 *page_list); | |
461 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
462 | struct mlx4_buf *buf); | |
463 | ||
6296883c YP |
464 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
465 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); | |
466 | ||
38ae6a53 YP |
467 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
468 | int size, int max_direct); | |
469 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
470 | int size); | |
471 | ||
225c7b1f | 472 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 473 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
b8dd786f | 474 | unsigned vector, int collapsed); |
225c7b1f RD |
475 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
476 | ||
a3cdcbfa YP |
477 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
478 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
479 | ||
480 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); | |
225c7b1f RD |
481 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
482 | ||
483 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, | |
484 | u64 db_rec, struct mlx4_srq *srq); | |
485 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); | |
486 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 487 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 488 | |
5ae2a7a8 | 489 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
490 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
491 | ||
521e575b RL |
492 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
493 | int block_mcast_loopback); | |
225c7b1f RD |
494 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); |
495 | ||
2a2336f8 YP |
496 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index); |
497 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index); | |
498 | ||
499 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); | |
500 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); | |
501 | ||
8ad11fb6 JM |
502 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
503 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
504 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
505 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
506 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
507 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
508 | u32 *lkey, u32 *rkey); | |
509 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
510 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
511 | ||
225c7b1f | 512 | #endif /* MLX4_DEVICE_H */ |