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IB/mlx4: Fix info returned when querying IBoE ports
[linux-2.6-block.git] / include / linux / mlx4 / device.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
60063497 40#include <linux/atomic.h>
225c7b1f 41
0b7ca5a9
YP		 42#define MAX_MSIX_P_PORT 17
43#define MAX_MSIX 64
44#define MSIX_LEGACY_SZ 4
45#define MIN_MSIX_P_PORT 5
46
225c7b1f
RD		 47enum {
48 MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8 49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
623ed84b
JM		 50 MLX4_FLAG_MASTER = 1 << 2,
51 MLX4_FLAG_SLAVE = 1 << 3,
52 MLX4_FLAG_SRIOV = 1 << 4,
225c7b1f
RD		 53};
54
55enum {
56 MLX4_MAX_PORTS = 2
57};
58
cd9281d8
JM		 59enum {
60 MLX4_BOARD_ID_LEN = 64
61};
62
623ed84b
JM		 63enum {
64 MLX4_MAX_NUM_PF = 16,
65 MLX4_MAX_NUM_VF = 64,
66 MLX4_MFUNC_MAX = 80,
67 MLX4_MFUNC_EQ_NUM = 4,
68 MLX4_MFUNC_MAX_EQES = 8,
69 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
70};
71
225c7b1f 72enum {
52eafc68
OG		 73 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
74 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
75 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
012a8ff5 76 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
52eafc68
OG		 77 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
78 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
79 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
80 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
81 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
82 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
83 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
84 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
85 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
86 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
87 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
88 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
ccf86321
OG		 89 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
90 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
f3a9d1f2 91 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
559a9f1d
OD		 92 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
93 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
ccf86321
OG		 94 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
95 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
f2a3f6a3 96 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
58a60168
YP		 97 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
98 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55
225c7b1f
RD		 99};
100
97285b78
MA		 101#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
102
103enum {
104 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
105};
106
95d04f07
RD		 107enum {
108 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
109 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
110 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
111 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
112 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
113};
114
225c7b1f
RD		 115enum mlx4_event {
116 MLX4_EVENT_TYPE_COMP = 0x00,
117 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
118 MLX4_EVENT_TYPE_COMM_EST = 0x02,
119 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
120 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
121 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
122 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
123 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
124 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
125 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
126 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
127 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
128 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
129 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
130 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
131 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
132 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
623ed84b
JM		 133 MLX4_EVENT_TYPE_CMD = 0x0a,
134 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
135 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
5984be90 136 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
623ed84b
JM		 137 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
138 MLX4_EVENT_TYPE_NONE = 0xff,
225c7b1f
RD		 139};
140
141enum {
142 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
143 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
144};
145
5984be90
JM		 146enum {
147 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
148};
149
225c7b1f
RD		 150enum {
151 MLX4_PERM_LOCAL_READ = 1 << 10,
152 MLX4_PERM_LOCAL_WRITE = 1 << 11,
153 MLX4_PERM_REMOTE_READ = 1 << 12,
154 MLX4_PERM_REMOTE_WRITE = 1 << 13,
155 MLX4_PERM_ATOMIC = 1 << 14
156};
157
158enum {
159 MLX4_OPCODE_NOP = 0x00,
160 MLX4_OPCODE_SEND_INVAL = 0x01,
161 MLX4_OPCODE_RDMA_WRITE = 0x08,
162 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
163 MLX4_OPCODE_SEND = 0x0a,
164 MLX4_OPCODE_SEND_IMM = 0x0b,
165 MLX4_OPCODE_LSO = 0x0e,
166 MLX4_OPCODE_RDMA_READ = 0x10,
167 MLX4_OPCODE_ATOMIC_CS = 0x11,
168 MLX4_OPCODE_ATOMIC_FA = 0x12,
6fa8f719
VS		 169 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
170 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
225c7b1f
RD		 171 MLX4_OPCODE_BIND_MW = 0x18,
172 MLX4_OPCODE_FMR = 0x19,
173 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
174 MLX4_OPCODE_CONFIG_CMD = 0x1f,
175
176 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
177 MLX4_RECV_OPCODE_SEND = 0x01,
178 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
179 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
180
181 MLX4_CQE_OPCODE_ERROR = 0x1e,
182 MLX4_CQE_OPCODE_RESIZE = 0x16,
183};
184
185enum {
186 MLX4_STAT_RATE_OFFSET = 5
187};
188
da995a8a 189enum mlx4_protocol {
0345584e
YP		 190 MLX4_PROT_IB_IPV6 = 0,
191 MLX4_PROT_ETH,
192 MLX4_PROT_IB_IPV4,
193 MLX4_PROT_FCOE
da995a8a
AS		 194};
195
29bdc883
VS		 196enum {
197 MLX4_MTT_FLAG_PRESENT = 1
198};
199
93fc9e1b
YP		 200enum mlx4_qp_region {
201 MLX4_QP_REGION_FW = 0,
202 MLX4_QP_REGION_ETH_ADDR,
203 MLX4_QP_REGION_FC_ADDR,
204 MLX4_QP_REGION_FC_EXCH,
205 MLX4_NUM_QP_REGION
206};
207
7ff93f8b 208enum mlx4_port_type {
623ed84b 209 MLX4_PORT_TYPE_NONE = 0,
27bf91d6
YP		 210 MLX4_PORT_TYPE_IB = 1,
211 MLX4_PORT_TYPE_ETH = 2,
212 MLX4_PORT_TYPE_AUTO = 3
7ff93f8b
YP		 213};
214
2a2336f8
YP		 215enum mlx4_special_vlan_idx {
216 MLX4_NO_VLAN_IDX = 0,
217 MLX4_VLAN_MISS_IDX,
218 MLX4_VLAN_REGULAR
219};
220
0345584e
YP		 221enum mlx4_steer_type {
222 MLX4_MC_STEER = 0,
223 MLX4_UC_STEER,
224 MLX4_NUM_STEERS
225};
226
93fc9e1b
YP		 227enum {
228 MLX4_NUM_FEXCH = 64 * 1024,
229};
230
5a0fd094
EC		 231enum {
232 MLX4_MAX_FAST_REG_PAGES = 511,
233};
234
ea54b10c
JM		 235static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
236{
237 return (major << 32) | (minor << 16) | subminor;
238}
239
225c7b1f
RD		 240struct mlx4_caps {
241 u64 fw_ver;
623ed84b 242 u32 function;
225c7b1f 243 int num_ports;
5ae2a7a8 244 int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49 245 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
9a5aa622 246 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
b79acb49
YP		 247 u64 def_mac[MLX4_MAX_PORTS + 1];
248 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8
RD		 249 int gid_table_len[MLX4_MAX_PORTS + 1];
250 int pkey_table_len[MLX4_MAX_PORTS + 1];
7699517d
YP		 251 int trans_type[MLX4_MAX_PORTS + 1];
252 int vendor_oui[MLX4_MAX_PORTS + 1];
253 int wavelength[MLX4_MAX_PORTS + 1];
254 u64 trans_code[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 255 int local_ca_ack_delay;
256 int num_uars;
f5311ac1 257 u32 uar_page_size;
225c7b1f
RD		 258 int bf_reg_size;
259 int bf_regs_per_page;
260 int max_sq_sg;
261 int max_rq_sg;
262 int num_qps;
263 int max_wqes;
264 int max_sq_desc_sz;
265 int max_rq_desc_sz;
266 int max_qp_init_rdma;
267 int max_qp_dest_rdma;
225c7b1f
RD		 268 int sqp_start;
269 int num_srqs;
270 int max_srq_wqes;
271 int max_srq_sge;
272 int reserved_srqs;
273 int num_cqs;
274 int max_cqes;
275 int reserved_cqs;
276 int num_eqs;
277 int reserved_eqs;
b8dd786f 278 int num_comp_vectors;
0b7ca5a9 279 int comp_pool;
225c7b1f 280 int num_mpts;
a5bbe892 281 int max_fmr_maps;
2b8fb286 282 int num_mtts;
225c7b1f
RD		 283 int fmr_reserved_mtts;
284 int reserved_mtts;
285 int reserved_mrws;
286 int reserved_uars;
287 int num_mgms;
288 int num_amgms;
289 int reserved_mcgs;
290 int num_qp_per_mgm;
291 int num_pds;
292 int reserved_pds;
012a8ff5
SH		 293 int max_xrcds;
294 int reserved_xrcds;
225c7b1f 295 int mtt_entry_sz;
149983af 296 u32 max_msg_sz;
225c7b1f 297 u32 page_size_cap;
52eafc68 298 u64 flags;
95d04f07
RD		 299 u32 bmme_flags;
300 u32 reserved_lkey;
225c7b1f 301 u16 stat_rate_support;
5ae2a7a8 302 u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e 303 int max_gso_sz;
93fc9e1b
YP		 304 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
305 int reserved_qps;
306 int reserved_qps_base[MLX4_NUM_QP_REGION];
307 int log_num_macs;
308 int log_num_vlans;
309 int log_num_prios;
7ff93f8b
YP		 310 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
311 u8 supported_type[MLX4_MAX_PORTS + 1];
8d0fc7b6
YP		 312 u8 suggested_type[MLX4_MAX_PORTS + 1];
313 u8 default_sense[MLX4_MAX_PORTS + 1];
65dab25d 314 u32 port_mask[MLX4_MAX_PORTS + 1];
27bf91d6 315 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
f2a3f6a3 316 u32 max_counters;
97285b78 317 u8 ext_port_cap[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 318};
319
320struct mlx4_buf_list {
321 void *buf;
322 dma_addr_t map;
323};
324
325struct mlx4_buf {
b57aacfa
RD		 326 struct mlx4_buf_list direct;
327 struct mlx4_buf_list *page_list;
225c7b1f
RD		 328 int nbufs;
329 int npages;
330 int page_shift;
331};
332
333struct mlx4_mtt {
2b8fb286 334 u32 offset;
225c7b1f
RD		 335 int order;
336 int page_shift;
337};
338
6296883c
YP		 339enum {
340 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
341};
342
343struct mlx4_db_pgdir {
344 struct list_head list;
345 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
346 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
347 unsigned long *bits[2];
348 __be32 *db_page;
349 dma_addr_t db_dma;
350};
351
352struct mlx4_ib_user_db_page;
353
354struct mlx4_db {
355 __be32 *db;
356 union {
357 struct mlx4_db_pgdir *pgdir;
358 struct mlx4_ib_user_db_page *user_page;
359 } u;
360 dma_addr_t dma;
361 int index;
362 int order;
363};
364
38ae6a53
YP		 365struct mlx4_hwq_resources {
366 struct mlx4_db db;
367 struct mlx4_mtt mtt;
368 struct mlx4_buf buf;
369};
370
225c7b1f
RD		 371struct mlx4_mr {
372 struct mlx4_mtt mtt;
373 u64 iova;
374 u64 size;
375 u32 key;
376 u32 pd;
377 u32 access;
378 int enabled;
379};
380
8ad11fb6
JM		 381struct mlx4_fmr {
382 struct mlx4_mr mr;
383 struct mlx4_mpt_entry *mpt;
384 __be64 *mtts;
385 dma_addr_t dma_handle;
386 int max_pages;
387 int max_maps;
388 int maps;
389 u8 page_shift;
390};
391
225c7b1f
RD		 392struct mlx4_uar {
393 unsigned long pfn;
394 int index;
c1b43dca
EC		 395 struct list_head bf_list;
396 unsigned free_bf_bmap;
397 void __iomem *map;
398 void __iomem *bf_map;
399};
400
401struct mlx4_bf {
402 unsigned long offset;
403 int buf_size;
404 struct mlx4_uar *uar;
405 void __iomem *reg;
225c7b1f
RD		 406};
407
408struct mlx4_cq {
409 void (*comp) (struct mlx4_cq *);
410 void (*event) (struct mlx4_cq *, enum mlx4_event);
411
412 struct mlx4_uar *uar;
413
414 u32 cons_index;
415
416 __be32 *set_ci_db;
417 __be32 *arm_db;
418 int arm_sn;
419
420 int cqn;
b8dd786f 421 unsigned vector;
225c7b1f
RD		 422
423 atomic_t refcount;
424 struct completion free;
425};
426
427struct mlx4_qp {
428 void (*event) (struct mlx4_qp *, enum mlx4_event);
429
430 int qpn;
431
432 atomic_t refcount;
433 struct completion free;
434};
435
436struct mlx4_srq {
437 void (*event) (struct mlx4_srq *, enum mlx4_event);
438
439 int srqn;
440 int max;
441 int max_gs;
442 int wqe_shift;
443
444 atomic_t refcount;
445 struct completion free;
446};
447
448struct mlx4_av {
449 __be32 port_pd;
450 u8 reserved1;
451 u8 g_slid;
452 __be16 dlid;
453 u8 reserved2;
454 u8 gid_index;
455 u8 stat_rate;
456 u8 hop_limit;
457 __be32 sl_tclass_flowlabel;
458 u8 dgid[16];
459};
460
fa417f7b
EC		 461struct mlx4_eth_av {
462 __be32 port_pd;
463 u8 reserved1;
464 u8 smac_idx;
465 u16 reserved2;
466 u8 reserved3;
467 u8 gid_index;
468 u8 stat_rate;
469 u8 hop_limit;
470 __be32 sl_tclass_flowlabel;
471 u8 dgid[16];
472 u32 reserved4[2];
473 __be16 vlan;
474 u8 mac[6];
475};
476
477union mlx4_ext_av {
478 struct mlx4_av ib;
479 struct mlx4_eth_av eth;
480};
481
f2a3f6a3
OG		 482struct mlx4_counter {
483 u8 reserved1[3];
484 u8 counter_mode;
485 __be32 num_ifc;
486 u32 reserved2[2];
487 __be64 rx_frames;
488 __be64 rx_bytes;
489 __be64 tx_frames;
490 __be64 tx_bytes;
491};
492
225c7b1f
RD		 493struct mlx4_dev {
494 struct pci_dev *pdev;
495 unsigned long flags;
623ed84b 496 unsigned long num_slaves;
225c7b1f
RD		 497 struct mlx4_caps caps;
498 struct radix_tree_root qp_table_tree;
725c8999 499 u8 rev_id;
cd9281d8 500 char board_id[MLX4_BOARD_ID_LEN];
ab9c17a0 501 int num_vfs;
225c7b1f
RD		 502};
503
504struct mlx4_init_port_param {
505 int set_guid0;
506 int set_node_guid;
507 int set_si_guid;
508 u16 mtu;
509 int port_width_cap;
510 u16 vl_cap;
511 u16 max_gid;
512 u16 max_pkey;
513 u64 guid0;
514 u64 node_guid;
515 u64 si_guid;
516};
517
7ff93f8b
YP		 518#define mlx4_foreach_port(port, dev, type) \
519 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
65dab25d 520 if ((type) == (dev)->caps.port_mask[(port)])
7ff93f8b 521
65dab25d
JM		 522#define mlx4_foreach_ib_transport_port(port, dev) \
523 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
524 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
525 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
623ed84b
JM		 526
527static inline int mlx4_is_master(struct mlx4_dev *dev)
528{
529 return dev->flags & MLX4_FLAG_MASTER;
530}
531
532static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
533{
534 return (qpn < dev->caps.sqp_start + 8);
535}
fa417f7b 536
623ed84b
JM		 537static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
538{
539 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
540}
541
542static inline int mlx4_is_slave(struct mlx4_dev *dev)
543{
544 return dev->flags & MLX4_FLAG_SLAVE;
545}
fa417f7b 546
225c7b1f
RD		 547int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
548 struct mlx4_buf *buf);
549void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1c69fc2a
RD		 550static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
551{
313abe55 552 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
b57aacfa 553 return buf->direct.buf + offset;
1c69fc2a 554 else
b57aacfa 555 return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a
RD		 556 (offset & (PAGE_SIZE - 1));
557}
225c7b1f
RD		 558
559int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
560void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
012a8ff5
SH		 561int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
562void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
225c7b1f
RD		 563
564int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
565void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
c1b43dca
EC		 566int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
567void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
225c7b1f
RD		 568
569int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
570 struct mlx4_mtt *mtt);
571void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
572u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
573
574int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
575 int npages, int page_shift, struct mlx4_mr *mr);
576void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
577int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
578int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
579 int start_index, int npages, u64 *page_list);
580int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
581 struct mlx4_buf *buf);
582
6296883c
YP		 583int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
584void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
585
38ae6a53
YP		 586int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
587 int size, int max_direct);
588void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
589 int size);
590
225c7b1f 591int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
e463c7b1 592 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
b8dd786f 593 unsigned vector, int collapsed);
225c7b1f
RD		 594void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
595
a3cdcbfa
YP		 596int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
597void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
598
599int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
225c7b1f
RD		 600void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
601
18abd5ea
SH		 602int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
603 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
225c7b1f
RD		 604void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
605int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
65541cb7 606int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
225c7b1f 607
5ae2a7a8 608int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f
RD		 609int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
610
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EE		 611int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
612 int block_mcast_loopback, enum mlx4_protocol prot);
613int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
614 enum mlx4_protocol prot);
521e575b 615int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
da995a8a
AS		 616 int block_mcast_loopback, enum mlx4_protocol protocol);
617int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
618 enum mlx4_protocol protocol);
1679200f
YP		 619int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
620int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
621int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
622int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
623int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
624
ffe455ad
EE		 625int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
626void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
627int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
628int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
629void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
93ece0c1 630void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
2a2336f8 631
4c3eb3ca 632int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
2a2336f8
YP		 633int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
634void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
635
8ad11fb6
JM		 636int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
637 int npages, u64 iova, u32 *lkey, u32 *rkey);
638int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
639 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
640int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
641void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
642 u32 *lkey, u32 *rkey);
643int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
644int mlx4_SYNC_TPT(struct mlx4_dev *dev);
e7c1c2c4 645int mlx4_test_interrupts(struct mlx4_dev *dev);
0b7ca5a9
YP		 646int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
647void mlx4_release_eq(struct mlx4_dev *dev, int vec);
8ad11fb6 648
14c07b13
YP		 649int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
650int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
651
f2a3f6a3
OG		 652int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
653void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
654
225c7b1f 655#endif /* MLX4_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)