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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
574e2af7 | 36 | #include <linux/if_ether.h> |
225c7b1f RD |
37 | #include <linux/pci.h> |
38 | #include <linux/completion.h> | |
39 | #include <linux/radix-tree.h> | |
d9236c3f | 40 | #include <linux/cpu_rmap.h> |
225c7b1f | 41 | |
60063497 | 42 | #include <linux/atomic.h> |
225c7b1f | 43 | |
ec693d47 AV |
44 | #include <linux/clocksource.h> |
45 | ||
0b7ca5a9 YP |
46 | #define MAX_MSIX_P_PORT 17 |
47 | #define MAX_MSIX 64 | |
48 | #define MSIX_LEGACY_SZ 4 | |
49 | #define MIN_MSIX_P_PORT 5 | |
50 | ||
6ee51a4e JM |
51 | #define MLX4_ROCE_MAX_GIDS 128 |
52 | ||
225c7b1f RD |
53 | enum { |
54 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 55 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
56 | MLX4_FLAG_MASTER = 1 << 2, |
57 | MLX4_FLAG_SLAVE = 1 << 3, | |
58 | MLX4_FLAG_SRIOV = 1 << 4, | |
acddd5dd | 59 | MLX4_FLAG_OLD_REG_MAC = 1 << 6, |
225c7b1f RD |
60 | }; |
61 | ||
efcd235d JM |
62 | enum { |
63 | MLX4_PORT_CAP_IS_SM = 1 << 1, | |
64 | MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, | |
65 | }; | |
66 | ||
225c7b1f | 67 | enum { |
fc06573d JM |
68 | MLX4_MAX_PORTS = 2, |
69 | MLX4_MAX_PORT_PKEYS = 128 | |
225c7b1f RD |
70 | }; |
71 | ||
396f2feb JM |
72 | /* base qkey for use in sriov tunnel-qp/proxy-qp communication. |
73 | * These qkeys must not be allowed for general use. This is a 64k range, | |
74 | * and to test for violation, we use the mask (protect against future chg). | |
75 | */ | |
76 | #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) | |
77 | #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) | |
78 | ||
cd9281d8 JM |
79 | enum { |
80 | MLX4_BOARD_ID_LEN = 64 | |
81 | }; | |
82 | ||
623ed84b JM |
83 | enum { |
84 | MLX4_MAX_NUM_PF = 16, | |
85 | MLX4_MAX_NUM_VF = 64, | |
86 | MLX4_MFUNC_MAX = 80, | |
3fc929e2 | 87 | MLX4_MAX_EQ_NUM = 1024, |
623ed84b JM |
88 | MLX4_MFUNC_EQ_NUM = 4, |
89 | MLX4_MFUNC_MAX_EQES = 8, | |
90 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
91 | }; | |
92 | ||
0ff1fb65 HHZ |
93 | /* Driver supports 3 diffrent device methods to manage traffic steering: |
94 | * -device managed - High level API for ib and eth flow steering. FW is | |
95 | * managing flow steering tables. | |
c96d97f4 HHZ |
96 | * - B0 steering mode - Common low level API for ib and (if supported) eth. |
97 | * - A0 steering mode - Limited low level API for eth. In case of IB, | |
98 | * B0 mode is in use. | |
99 | */ | |
100 | enum { | |
101 | MLX4_STEERING_MODE_A0, | |
0ff1fb65 HHZ |
102 | MLX4_STEERING_MODE_B0, |
103 | MLX4_STEERING_MODE_DEVICE_MANAGED | |
c96d97f4 HHZ |
104 | }; |
105 | ||
106 | static inline const char *mlx4_steering_mode_str(int steering_mode) | |
107 | { | |
108 | switch (steering_mode) { | |
109 | case MLX4_STEERING_MODE_A0: | |
110 | return "A0 steering"; | |
111 | ||
112 | case MLX4_STEERING_MODE_B0: | |
113 | return "B0 steering"; | |
0ff1fb65 HHZ |
114 | |
115 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
116 | return "Device managed flow steering"; | |
117 | ||
c96d97f4 HHZ |
118 | default: |
119 | return "Unrecognize steering mode"; | |
120 | } | |
121 | } | |
122 | ||
7ffdf726 OG |
123 | enum { |
124 | MLX4_TUNNEL_OFFLOAD_MODE_NONE, | |
125 | MLX4_TUNNEL_OFFLOAD_MODE_VXLAN | |
126 | }; | |
127 | ||
225c7b1f | 128 | enum { |
52eafc68 OG |
129 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
130 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
131 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 132 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
133 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
134 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
135 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
136 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
137 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
138 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
139 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
140 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
141 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
142 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
143 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
144 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
145 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
146 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 147 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
148 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
149 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
150 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
151 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 152 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 | 153 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
540b3a39 | 154 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
00f5ce99 JM |
155 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
156 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | |
08ff3235 OG |
157 | MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, |
158 | MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 | |
225c7b1f RD |
159 | }; |
160 | ||
b3416f44 SP |
161 | enum { |
162 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, | |
163 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, | |
0ff1fb65 | 164 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, |
955154fa | 165 | MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, |
5930e8d0 | 166 | MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, |
3f7fb021 | 167 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
e6b6a231 | 168 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
b01978ca | 169 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
4de65803 | 170 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, |
4ba9920e LT |
171 | MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, |
172 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, | |
b3416f44 SP |
173 | }; |
174 | ||
08ff3235 OG |
175 | enum { |
176 | MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, | |
177 | MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 | |
178 | }; | |
179 | ||
180 | enum { | |
181 | MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 | |
182 | }; | |
183 | ||
184 | enum { | |
185 | MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 | |
186 | }; | |
187 | ||
188 | ||
97285b78 MA |
189 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
190 | ||
95d04f07 | 191 | enum { |
804d6a89 | 192 | MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, |
95d04f07 RD |
193 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, |
194 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
195 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
196 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
197 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
198 | }; | |
199 | ||
225c7b1f RD |
200 | enum mlx4_event { |
201 | MLX4_EVENT_TYPE_COMP = 0x00, | |
202 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
203 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
204 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
205 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
206 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
207 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
208 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
209 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
210 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
211 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
212 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
213 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
214 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
215 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
216 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
217 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
218 | MLX4_EVENT_TYPE_CMD = 0x0a, |
219 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
220 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
fe6f700d | 221 | MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, |
5984be90 | 222 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
623ed84b | 223 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
00f5ce99 | 224 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
623ed84b | 225 | MLX4_EVENT_TYPE_NONE = 0xff, |
225c7b1f RD |
226 | }; |
227 | ||
228 | enum { | |
229 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
230 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
231 | }; | |
232 | ||
5984be90 JM |
233 | enum { |
234 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, | |
235 | }; | |
236 | ||
993c401e JM |
237 | enum slave_port_state { |
238 | SLAVE_PORT_DOWN = 0, | |
239 | SLAVE_PENDING_UP, | |
240 | SLAVE_PORT_UP, | |
241 | }; | |
242 | ||
243 | enum slave_port_gen_event { | |
244 | SLAVE_PORT_GEN_EVENT_DOWN = 0, | |
245 | SLAVE_PORT_GEN_EVENT_UP, | |
246 | SLAVE_PORT_GEN_EVENT_NONE, | |
247 | }; | |
248 | ||
249 | enum slave_port_state_event { | |
250 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
251 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP, | |
252 | MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, | |
253 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID, | |
254 | }; | |
255 | ||
225c7b1f RD |
256 | enum { |
257 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
258 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
259 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
260 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
804d6a89 SM |
261 | MLX4_PERM_ATOMIC = 1 << 14, |
262 | MLX4_PERM_BIND_MW = 1 << 15, | |
225c7b1f RD |
263 | }; |
264 | ||
265 | enum { | |
266 | MLX4_OPCODE_NOP = 0x00, | |
267 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
268 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
269 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
270 | MLX4_OPCODE_SEND = 0x0a, | |
271 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
272 | MLX4_OPCODE_LSO = 0x0e, | |
273 | MLX4_OPCODE_RDMA_READ = 0x10, | |
274 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
275 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
276 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
277 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
278 | MLX4_OPCODE_BIND_MW = 0x18, |
279 | MLX4_OPCODE_FMR = 0x19, | |
280 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
281 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
282 | ||
283 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
284 | MLX4_RECV_OPCODE_SEND = 0x01, | |
285 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
286 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
287 | ||
288 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
289 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
290 | }; | |
291 | ||
292 | enum { | |
293 | MLX4_STAT_RATE_OFFSET = 5 | |
294 | }; | |
295 | ||
da995a8a | 296 | enum mlx4_protocol { |
0345584e YP |
297 | MLX4_PROT_IB_IPV6 = 0, |
298 | MLX4_PROT_ETH, | |
299 | MLX4_PROT_IB_IPV4, | |
300 | MLX4_PROT_FCOE | |
da995a8a AS |
301 | }; |
302 | ||
29bdc883 VS |
303 | enum { |
304 | MLX4_MTT_FLAG_PRESENT = 1 | |
305 | }; | |
306 | ||
93fc9e1b YP |
307 | enum mlx4_qp_region { |
308 | MLX4_QP_REGION_FW = 0, | |
309 | MLX4_QP_REGION_ETH_ADDR, | |
310 | MLX4_QP_REGION_FC_ADDR, | |
311 | MLX4_QP_REGION_FC_EXCH, | |
312 | MLX4_NUM_QP_REGION | |
313 | }; | |
314 | ||
7ff93f8b | 315 | enum mlx4_port_type { |
623ed84b | 316 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
317 | MLX4_PORT_TYPE_IB = 1, |
318 | MLX4_PORT_TYPE_ETH = 2, | |
319 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
320 | }; |
321 | ||
2a2336f8 YP |
322 | enum mlx4_special_vlan_idx { |
323 | MLX4_NO_VLAN_IDX = 0, | |
324 | MLX4_VLAN_MISS_IDX, | |
325 | MLX4_VLAN_REGULAR | |
326 | }; | |
327 | ||
0345584e YP |
328 | enum mlx4_steer_type { |
329 | MLX4_MC_STEER = 0, | |
330 | MLX4_UC_STEER, | |
331 | MLX4_NUM_STEERS | |
332 | }; | |
333 | ||
93fc9e1b YP |
334 | enum { |
335 | MLX4_NUM_FEXCH = 64 * 1024, | |
336 | }; | |
337 | ||
5a0fd094 EC |
338 | enum { |
339 | MLX4_MAX_FAST_REG_PAGES = 511, | |
340 | }; | |
341 | ||
00f5ce99 JM |
342 | enum { |
343 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, | |
344 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, | |
345 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, | |
346 | }; | |
347 | ||
348 | /* Port mgmt change event handling */ | |
349 | enum { | |
350 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, | |
351 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, | |
352 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, | |
353 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, | |
354 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, | |
355 | }; | |
356 | ||
357 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ | |
358 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) | |
359 | ||
ea54b10c JM |
360 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
361 | { | |
362 | return (major << 32) | (minor << 16) | subminor; | |
363 | } | |
364 | ||
3fc929e2 | 365 | struct mlx4_phys_caps { |
6634961c JM |
366 | u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; |
367 | u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; | |
3fc929e2 | 368 | u32 num_phys_eqs; |
47605df9 JM |
369 | u32 base_sqpn; |
370 | u32 base_proxy_sqpn; | |
371 | u32 base_tunnel_sqpn; | |
3fc929e2 MA |
372 | }; |
373 | ||
225c7b1f RD |
374 | struct mlx4_caps { |
375 | u64 fw_ver; | |
623ed84b | 376 | u32 function; |
225c7b1f | 377 | int num_ports; |
5ae2a7a8 | 378 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 379 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 380 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
381 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
382 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
383 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
384 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
385 | int trans_type[MLX4_MAX_PORTS + 1]; |
386 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
387 | int wavelength[MLX4_MAX_PORTS + 1]; | |
388 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
389 | int local_ca_ack_delay; |
390 | int num_uars; | |
f5311ac1 | 391 | u32 uar_page_size; |
225c7b1f RD |
392 | int bf_reg_size; |
393 | int bf_regs_per_page; | |
394 | int max_sq_sg; | |
395 | int max_rq_sg; | |
396 | int num_qps; | |
397 | int max_wqes; | |
398 | int max_sq_desc_sz; | |
399 | int max_rq_desc_sz; | |
400 | int max_qp_init_rdma; | |
401 | int max_qp_dest_rdma; | |
47605df9 JM |
402 | u32 *qp0_proxy; |
403 | u32 *qp1_proxy; | |
404 | u32 *qp0_tunnel; | |
405 | u32 *qp1_tunnel; | |
225c7b1f RD |
406 | int num_srqs; |
407 | int max_srq_wqes; | |
408 | int max_srq_sge; | |
409 | int reserved_srqs; | |
410 | int num_cqs; | |
411 | int max_cqes; | |
412 | int reserved_cqs; | |
413 | int num_eqs; | |
414 | int reserved_eqs; | |
b8dd786f | 415 | int num_comp_vectors; |
0b7ca5a9 | 416 | int comp_pool; |
225c7b1f | 417 | int num_mpts; |
a5bbe892 | 418 | int max_fmr_maps; |
2b8fb286 | 419 | int num_mtts; |
225c7b1f RD |
420 | int fmr_reserved_mtts; |
421 | int reserved_mtts; | |
422 | int reserved_mrws; | |
423 | int reserved_uars; | |
424 | int num_mgms; | |
425 | int num_amgms; | |
426 | int reserved_mcgs; | |
427 | int num_qp_per_mgm; | |
c96d97f4 | 428 | int steering_mode; |
0ff1fb65 | 429 | int fs_log_max_ucast_qp_range_size; |
225c7b1f RD |
430 | int num_pds; |
431 | int reserved_pds; | |
012a8ff5 SH |
432 | int max_xrcds; |
433 | int reserved_xrcds; | |
225c7b1f | 434 | int mtt_entry_sz; |
149983af | 435 | u32 max_msg_sz; |
225c7b1f | 436 | u32 page_size_cap; |
52eafc68 | 437 | u64 flags; |
b3416f44 | 438 | u64 flags2; |
95d04f07 RD |
439 | u32 bmme_flags; |
440 | u32 reserved_lkey; | |
225c7b1f | 441 | u16 stat_rate_support; |
5ae2a7a8 | 442 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 443 | int max_gso_sz; |
b3416f44 | 444 | int max_rss_tbl_sz; |
93fc9e1b YP |
445 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
446 | int reserved_qps; | |
447 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
448 | int log_num_macs; | |
449 | int log_num_vlans; | |
450 | int log_num_prios; | |
7ff93f8b YP |
451 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
452 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
453 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
454 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 455 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 456 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 457 | u32 max_counters; |
096335b3 | 458 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
1ffeb2eb | 459 | u16 sqp_demux; |
08ff3235 OG |
460 | u32 eqe_size; |
461 | u32 cqe_size; | |
462 | u8 eqe_factor; | |
463 | u32 userspace_caps; /* userspace must be aware of these */ | |
464 | u32 function_caps; /* VFs must be aware of these */ | |
ddd8a6c1 | 465 | u16 hca_core_clock; |
8e1a28e8 | 466 | u64 phys_port_id[MLX4_MAX_PORTS + 1]; |
7ffdf726 | 467 | int tunnel_offload_mode; |
225c7b1f RD |
468 | }; |
469 | ||
470 | struct mlx4_buf_list { | |
471 | void *buf; | |
472 | dma_addr_t map; | |
473 | }; | |
474 | ||
475 | struct mlx4_buf { | |
b57aacfa RD |
476 | struct mlx4_buf_list direct; |
477 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
478 | int nbufs; |
479 | int npages; | |
480 | int page_shift; | |
481 | }; | |
482 | ||
483 | struct mlx4_mtt { | |
2b8fb286 | 484 | u32 offset; |
225c7b1f RD |
485 | int order; |
486 | int page_shift; | |
487 | }; | |
488 | ||
6296883c YP |
489 | enum { |
490 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
491 | }; | |
492 | ||
493 | struct mlx4_db_pgdir { | |
494 | struct list_head list; | |
495 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
496 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
497 | unsigned long *bits[2]; | |
498 | __be32 *db_page; | |
499 | dma_addr_t db_dma; | |
500 | }; | |
501 | ||
502 | struct mlx4_ib_user_db_page; | |
503 | ||
504 | struct mlx4_db { | |
505 | __be32 *db; | |
506 | union { | |
507 | struct mlx4_db_pgdir *pgdir; | |
508 | struct mlx4_ib_user_db_page *user_page; | |
509 | } u; | |
510 | dma_addr_t dma; | |
511 | int index; | |
512 | int order; | |
513 | }; | |
514 | ||
38ae6a53 YP |
515 | struct mlx4_hwq_resources { |
516 | struct mlx4_db db; | |
517 | struct mlx4_mtt mtt; | |
518 | struct mlx4_buf buf; | |
519 | }; | |
520 | ||
225c7b1f RD |
521 | struct mlx4_mr { |
522 | struct mlx4_mtt mtt; | |
523 | u64 iova; | |
524 | u64 size; | |
525 | u32 key; | |
526 | u32 pd; | |
527 | u32 access; | |
528 | int enabled; | |
529 | }; | |
530 | ||
804d6a89 SM |
531 | enum mlx4_mw_type { |
532 | MLX4_MW_TYPE_1 = 1, | |
533 | MLX4_MW_TYPE_2 = 2, | |
534 | }; | |
535 | ||
536 | struct mlx4_mw { | |
537 | u32 key; | |
538 | u32 pd; | |
539 | enum mlx4_mw_type type; | |
540 | int enabled; | |
541 | }; | |
542 | ||
8ad11fb6 JM |
543 | struct mlx4_fmr { |
544 | struct mlx4_mr mr; | |
545 | struct mlx4_mpt_entry *mpt; | |
546 | __be64 *mtts; | |
547 | dma_addr_t dma_handle; | |
548 | int max_pages; | |
549 | int max_maps; | |
550 | int maps; | |
551 | u8 page_shift; | |
552 | }; | |
553 | ||
225c7b1f RD |
554 | struct mlx4_uar { |
555 | unsigned long pfn; | |
556 | int index; | |
c1b43dca EC |
557 | struct list_head bf_list; |
558 | unsigned free_bf_bmap; | |
559 | void __iomem *map; | |
560 | void __iomem *bf_map; | |
561 | }; | |
562 | ||
563 | struct mlx4_bf { | |
564 | unsigned long offset; | |
565 | int buf_size; | |
566 | struct mlx4_uar *uar; | |
567 | void __iomem *reg; | |
225c7b1f RD |
568 | }; |
569 | ||
570 | struct mlx4_cq { | |
571 | void (*comp) (struct mlx4_cq *); | |
572 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
573 | ||
574 | struct mlx4_uar *uar; | |
575 | ||
576 | u32 cons_index; | |
577 | ||
578 | __be32 *set_ci_db; | |
579 | __be32 *arm_db; | |
580 | int arm_sn; | |
581 | ||
582 | int cqn; | |
b8dd786f | 583 | unsigned vector; |
225c7b1f RD |
584 | |
585 | atomic_t refcount; | |
586 | struct completion free; | |
587 | }; | |
588 | ||
589 | struct mlx4_qp { | |
590 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
591 | ||
592 | int qpn; | |
593 | ||
594 | atomic_t refcount; | |
595 | struct completion free; | |
596 | }; | |
597 | ||
598 | struct mlx4_srq { | |
599 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
600 | ||
601 | int srqn; | |
602 | int max; | |
603 | int max_gs; | |
604 | int wqe_shift; | |
605 | ||
606 | atomic_t refcount; | |
607 | struct completion free; | |
608 | }; | |
609 | ||
610 | struct mlx4_av { | |
611 | __be32 port_pd; | |
612 | u8 reserved1; | |
613 | u8 g_slid; | |
614 | __be16 dlid; | |
615 | u8 reserved2; | |
616 | u8 gid_index; | |
617 | u8 stat_rate; | |
618 | u8 hop_limit; | |
619 | __be32 sl_tclass_flowlabel; | |
620 | u8 dgid[16]; | |
621 | }; | |
622 | ||
fa417f7b EC |
623 | struct mlx4_eth_av { |
624 | __be32 port_pd; | |
625 | u8 reserved1; | |
626 | u8 smac_idx; | |
627 | u16 reserved2; | |
628 | u8 reserved3; | |
629 | u8 gid_index; | |
630 | u8 stat_rate; | |
631 | u8 hop_limit; | |
632 | __be32 sl_tclass_flowlabel; | |
633 | u8 dgid[16]; | |
634 | u32 reserved4[2]; | |
635 | __be16 vlan; | |
574e2af7 | 636 | u8 mac[ETH_ALEN]; |
fa417f7b EC |
637 | }; |
638 | ||
639 | union mlx4_ext_av { | |
640 | struct mlx4_av ib; | |
641 | struct mlx4_eth_av eth; | |
642 | }; | |
643 | ||
f2a3f6a3 OG |
644 | struct mlx4_counter { |
645 | u8 reserved1[3]; | |
646 | u8 counter_mode; | |
647 | __be32 num_ifc; | |
648 | u32 reserved2[2]; | |
649 | __be64 rx_frames; | |
650 | __be64 rx_bytes; | |
651 | __be64 tx_frames; | |
652 | __be64 tx_bytes; | |
653 | }; | |
654 | ||
5a0d0a61 JM |
655 | struct mlx4_quotas { |
656 | int qp; | |
657 | int cq; | |
658 | int srq; | |
659 | int mpt; | |
660 | int mtt; | |
661 | int counter; | |
662 | int xrcd; | |
663 | }; | |
664 | ||
225c7b1f RD |
665 | struct mlx4_dev { |
666 | struct pci_dev *pdev; | |
667 | unsigned long flags; | |
623ed84b | 668 | unsigned long num_slaves; |
225c7b1f | 669 | struct mlx4_caps caps; |
3fc929e2 | 670 | struct mlx4_phys_caps phys_caps; |
5a0d0a61 | 671 | struct mlx4_quotas quotas; |
225c7b1f | 672 | struct radix_tree_root qp_table_tree; |
725c8999 | 673 | u8 rev_id; |
cd9281d8 | 674 | char board_id[MLX4_BOARD_ID_LEN]; |
ab9c17a0 | 675 | int num_vfs; |
6e7136ed | 676 | int numa_node; |
3c439b55 | 677 | int oper_log_mgm_entry_size; |
592e49dd HHZ |
678 | u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; |
679 | u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
680 | }; |
681 | ||
00f5ce99 JM |
682 | struct mlx4_eqe { |
683 | u8 reserved1; | |
684 | u8 type; | |
685 | u8 reserved2; | |
686 | u8 subtype; | |
687 | union { | |
688 | u32 raw[6]; | |
689 | struct { | |
690 | __be32 cqn; | |
691 | } __packed comp; | |
692 | struct { | |
693 | u16 reserved1; | |
694 | __be16 token; | |
695 | u32 reserved2; | |
696 | u8 reserved3[3]; | |
697 | u8 status; | |
698 | __be64 out_param; | |
699 | } __packed cmd; | |
700 | struct { | |
701 | __be32 qpn; | |
702 | } __packed qp; | |
703 | struct { | |
704 | __be32 srqn; | |
705 | } __packed srq; | |
706 | struct { | |
707 | __be32 cqn; | |
708 | u32 reserved1; | |
709 | u8 reserved2[3]; | |
710 | u8 syndrome; | |
711 | } __packed cq_err; | |
712 | struct { | |
713 | u32 reserved1[2]; | |
714 | __be32 port; | |
715 | } __packed port_change; | |
716 | struct { | |
717 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 | |
718 | u32 reserved; | |
719 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; | |
720 | } __packed comm_channel_arm; | |
721 | struct { | |
722 | u8 port; | |
723 | u8 reserved[3]; | |
724 | __be64 mac; | |
725 | } __packed mac_update; | |
726 | struct { | |
727 | __be32 slave_id; | |
728 | } __packed flr_event; | |
729 | struct { | |
730 | __be16 current_temperature; | |
731 | __be16 warning_threshold; | |
732 | } __packed warming; | |
733 | struct { | |
734 | u8 reserved[3]; | |
735 | u8 port; | |
736 | union { | |
737 | struct { | |
738 | __be16 mstr_sm_lid; | |
739 | __be16 port_lid; | |
740 | __be32 changed_attr; | |
741 | u8 reserved[3]; | |
742 | u8 mstr_sm_sl; | |
743 | __be64 gid_prefix; | |
744 | } __packed port_info; | |
745 | struct { | |
746 | __be32 block_ptr; | |
747 | __be32 tbl_entries_mask; | |
748 | } __packed tbl_change_info; | |
749 | } params; | |
750 | } __packed port_mgmt_change; | |
751 | } event; | |
752 | u8 slave_id; | |
753 | u8 reserved3[2]; | |
754 | u8 owner; | |
755 | } __packed; | |
756 | ||
225c7b1f RD |
757 | struct mlx4_init_port_param { |
758 | int set_guid0; | |
759 | int set_node_guid; | |
760 | int set_si_guid; | |
761 | u16 mtu; | |
762 | int port_width_cap; | |
763 | u16 vl_cap; | |
764 | u16 max_gid; | |
765 | u16 max_pkey; | |
766 | u64 guid0; | |
767 | u64 node_guid; | |
768 | u64 si_guid; | |
769 | }; | |
770 | ||
7ff93f8b YP |
771 | #define mlx4_foreach_port(port, dev, type) \ |
772 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 773 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 774 | |
026149cb JM |
775 | #define mlx4_foreach_non_ib_transport_port(port, dev) \ |
776 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
777 | if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) | |
778 | ||
65dab25d JM |
779 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
780 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
781 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ | |
782 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
623ed84b | 783 | |
752a50ca JM |
784 | #define MLX4_INVALID_SLAVE_ID 0xFF |
785 | ||
00f5ce99 JM |
786 | void handle_port_mgmt_change_event(struct work_struct *work); |
787 | ||
2aca1172 JM |
788 | static inline int mlx4_master_func_num(struct mlx4_dev *dev) |
789 | { | |
790 | return dev->caps.function; | |
791 | } | |
792 | ||
623ed84b JM |
793 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
794 | { | |
795 | return dev->flags & MLX4_FLAG_MASTER; | |
796 | } | |
797 | ||
5a0d0a61 JM |
798 | static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) |
799 | { | |
800 | return dev->phys_caps.base_sqpn + 8 + | |
801 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); | |
802 | } | |
803 | ||
623ed84b JM |
804 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) |
805 | { | |
47605df9 | 806 | return (qpn < dev->phys_caps.base_sqpn + 8 + |
e2c76824 JM |
807 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); |
808 | } | |
809 | ||
810 | static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) | |
811 | { | |
47605df9 | 812 | int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; |
e2c76824 | 813 | |
47605df9 | 814 | if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) |
e2c76824 JM |
815 | return 1; |
816 | ||
817 | return 0; | |
623ed84b | 818 | } |
fa417f7b | 819 | |
623ed84b JM |
820 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
821 | { | |
822 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
823 | } | |
824 | ||
825 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
826 | { | |
827 | return dev->flags & MLX4_FLAG_SLAVE; | |
828 | } | |
fa417f7b | 829 | |
225c7b1f RD |
830 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
831 | struct mlx4_buf *buf); | |
832 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | |
1c69fc2a RD |
833 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
834 | { | |
313abe55 | 835 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 836 | return buf->direct.buf + offset; |
1c69fc2a | 837 | else |
b57aacfa | 838 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
839 | (offset & (PAGE_SIZE - 1)); |
840 | } | |
225c7b1f RD |
841 | |
842 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
843 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
844 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
845 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
846 | |
847 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
848 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
163561a4 | 849 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); |
c1b43dca | 850 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); |
225c7b1f RD |
851 | |
852 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
853 | struct mlx4_mtt *mtt); | |
854 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
855 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
856 | ||
857 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
858 | int npages, int page_shift, struct mlx4_mr *mr); | |
61083720 | 859 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); |
225c7b1f | 860 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); |
804d6a89 SM |
861 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
862 | struct mlx4_mw *mw); | |
863 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
864 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
225c7b1f RD |
865 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
866 | int start_index, int npages, u64 *page_list); | |
867 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
868 | struct mlx4_buf *buf); | |
869 | ||
6296883c YP |
870 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
871 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); | |
872 | ||
38ae6a53 YP |
873 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
874 | int size, int max_direct); | |
875 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
876 | int size); | |
877 | ||
225c7b1f | 878 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 879 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
ec693d47 | 880 | unsigned vector, int collapsed, int timestamp_en); |
225c7b1f RD |
881 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
882 | ||
a3cdcbfa YP |
883 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
884 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
885 | ||
886 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); | |
225c7b1f RD |
887 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
888 | ||
18abd5ea SH |
889 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
890 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
891 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
892 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 893 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 894 | |
5ae2a7a8 | 895 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
896 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
897 | ||
ffe455ad EE |
898 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
899 | int block_mcast_loopback, enum mlx4_protocol prot); | |
900 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
901 | enum mlx4_protocol prot); | |
521e575b | 902 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
903 | u8 port, int block_mcast_loopback, |
904 | enum mlx4_protocol protocol, u64 *reg_id); | |
da995a8a | 905 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
906 | enum mlx4_protocol protocol, u64 reg_id); |
907 | ||
908 | enum { | |
909 | MLX4_DOMAIN_UVERBS = 0x1000, | |
910 | MLX4_DOMAIN_ETHTOOL = 0x2000, | |
911 | MLX4_DOMAIN_RFS = 0x3000, | |
912 | MLX4_DOMAIN_NIC = 0x5000, | |
913 | }; | |
914 | ||
915 | enum mlx4_net_trans_rule_id { | |
916 | MLX4_NET_TRANS_RULE_ID_ETH = 0, | |
917 | MLX4_NET_TRANS_RULE_ID_IB, | |
918 | MLX4_NET_TRANS_RULE_ID_IPV6, | |
919 | MLX4_NET_TRANS_RULE_ID_IPV4, | |
920 | MLX4_NET_TRANS_RULE_ID_TCP, | |
921 | MLX4_NET_TRANS_RULE_ID_UDP, | |
7ffdf726 | 922 | MLX4_NET_TRANS_RULE_ID_VXLAN, |
0ff1fb65 HHZ |
923 | MLX4_NET_TRANS_RULE_NUM, /* should be last */ |
924 | }; | |
925 | ||
a8edc3bf HHZ |
926 | extern const u16 __sw_id_hw[]; |
927 | ||
7fb40f87 HHZ |
928 | static inline int map_hw_to_sw_id(u16 header_id) |
929 | { | |
930 | ||
931 | int i; | |
932 | for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { | |
933 | if (header_id == __sw_id_hw[i]) | |
934 | return i; | |
935 | } | |
936 | return -EINVAL; | |
937 | } | |
938 | ||
0ff1fb65 | 939 | enum mlx4_net_trans_promisc_mode { |
f9162539 HHZ |
940 | MLX4_FS_REGULAR = 1, |
941 | MLX4_FS_ALL_DEFAULT, | |
942 | MLX4_FS_MC_DEFAULT, | |
943 | MLX4_FS_UC_SNIFFER, | |
944 | MLX4_FS_MC_SNIFFER, | |
c2c19dc3 | 945 | MLX4_FS_MODE_NUM, /* should be last */ |
0ff1fb65 HHZ |
946 | }; |
947 | ||
948 | struct mlx4_spec_eth { | |
574e2af7 JP |
949 | u8 dst_mac[ETH_ALEN]; |
950 | u8 dst_mac_msk[ETH_ALEN]; | |
951 | u8 src_mac[ETH_ALEN]; | |
952 | u8 src_mac_msk[ETH_ALEN]; | |
0ff1fb65 HHZ |
953 | u8 ether_type_enable; |
954 | __be16 ether_type; | |
955 | __be16 vlan_id_msk; | |
956 | __be16 vlan_id; | |
957 | }; | |
958 | ||
959 | struct mlx4_spec_tcp_udp { | |
960 | __be16 dst_port; | |
961 | __be16 dst_port_msk; | |
962 | __be16 src_port; | |
963 | __be16 src_port_msk; | |
964 | }; | |
965 | ||
966 | struct mlx4_spec_ipv4 { | |
967 | __be32 dst_ip; | |
968 | __be32 dst_ip_msk; | |
969 | __be32 src_ip; | |
970 | __be32 src_ip_msk; | |
971 | }; | |
972 | ||
973 | struct mlx4_spec_ib { | |
ba60a356 | 974 | __be32 l3_qpn; |
0ff1fb65 HHZ |
975 | __be32 qpn_msk; |
976 | u8 dst_gid[16]; | |
977 | u8 dst_gid_msk[16]; | |
978 | }; | |
979 | ||
7ffdf726 OG |
980 | struct mlx4_spec_vxlan { |
981 | __be32 vni; | |
982 | __be32 vni_mask; | |
983 | ||
984 | }; | |
985 | ||
0ff1fb65 HHZ |
986 | struct mlx4_spec_list { |
987 | struct list_head list; | |
988 | enum mlx4_net_trans_rule_id id; | |
989 | union { | |
990 | struct mlx4_spec_eth eth; | |
991 | struct mlx4_spec_ib ib; | |
992 | struct mlx4_spec_ipv4 ipv4; | |
993 | struct mlx4_spec_tcp_udp tcp_udp; | |
7ffdf726 | 994 | struct mlx4_spec_vxlan vxlan; |
0ff1fb65 HHZ |
995 | }; |
996 | }; | |
997 | ||
998 | enum mlx4_net_trans_hw_rule_queue { | |
999 | MLX4_NET_TRANS_Q_FIFO, | |
1000 | MLX4_NET_TRANS_Q_LIFO, | |
1001 | }; | |
1002 | ||
1003 | struct mlx4_net_trans_rule { | |
1004 | struct list_head list; | |
1005 | enum mlx4_net_trans_hw_rule_queue queue_mode; | |
1006 | bool exclusive; | |
1007 | bool allow_loopback; | |
1008 | enum mlx4_net_trans_promisc_mode promisc_mode; | |
1009 | u8 port; | |
1010 | u16 priority; | |
1011 | u32 qpn; | |
1012 | }; | |
1013 | ||
3cd0e178 | 1014 | struct mlx4_net_trans_rule_hw_ctrl { |
bcf37297 HHZ |
1015 | __be16 prio; |
1016 | u8 type; | |
1017 | u8 flags; | |
3cd0e178 HHZ |
1018 | u8 rsvd1; |
1019 | u8 funcid; | |
1020 | u8 vep; | |
1021 | u8 port; | |
1022 | __be32 qpn; | |
1023 | __be32 rsvd2; | |
1024 | }; | |
1025 | ||
1026 | struct mlx4_net_trans_rule_hw_ib { | |
1027 | u8 size; | |
1028 | u8 rsvd1; | |
1029 | __be16 id; | |
1030 | u32 rsvd2; | |
ba60a356 | 1031 | __be32 l3_qpn; |
3cd0e178 HHZ |
1032 | __be32 qpn_mask; |
1033 | u8 dst_gid[16]; | |
1034 | u8 dst_gid_msk[16]; | |
1035 | } __packed; | |
1036 | ||
1037 | struct mlx4_net_trans_rule_hw_eth { | |
1038 | u8 size; | |
1039 | u8 rsvd; | |
1040 | __be16 id; | |
1041 | u8 rsvd1[6]; | |
1042 | u8 dst_mac[6]; | |
1043 | u16 rsvd2; | |
1044 | u8 dst_mac_msk[6]; | |
1045 | u16 rsvd3; | |
1046 | u8 src_mac[6]; | |
1047 | u16 rsvd4; | |
1048 | u8 src_mac_msk[6]; | |
1049 | u8 rsvd5; | |
1050 | u8 ether_type_enable; | |
1051 | __be16 ether_type; | |
ba60a356 HHZ |
1052 | __be16 vlan_tag_msk; |
1053 | __be16 vlan_tag; | |
3cd0e178 HHZ |
1054 | } __packed; |
1055 | ||
1056 | struct mlx4_net_trans_rule_hw_tcp_udp { | |
1057 | u8 size; | |
1058 | u8 rsvd; | |
1059 | __be16 id; | |
1060 | __be16 rsvd1[3]; | |
1061 | __be16 dst_port; | |
1062 | __be16 rsvd2; | |
1063 | __be16 dst_port_msk; | |
1064 | __be16 rsvd3; | |
1065 | __be16 src_port; | |
1066 | __be16 rsvd4; | |
1067 | __be16 src_port_msk; | |
1068 | } __packed; | |
1069 | ||
1070 | struct mlx4_net_trans_rule_hw_ipv4 { | |
1071 | u8 size; | |
1072 | u8 rsvd; | |
1073 | __be16 id; | |
1074 | __be32 rsvd1; | |
1075 | __be32 dst_ip; | |
1076 | __be32 dst_ip_msk; | |
1077 | __be32 src_ip; | |
1078 | __be32 src_ip_msk; | |
1079 | } __packed; | |
1080 | ||
7ffdf726 OG |
1081 | struct mlx4_net_trans_rule_hw_vxlan { |
1082 | u8 size; | |
1083 | u8 rsvd; | |
1084 | __be16 id; | |
1085 | __be32 rsvd1; | |
1086 | __be32 vni; | |
1087 | __be32 vni_mask; | |
1088 | } __packed; | |
1089 | ||
3cd0e178 HHZ |
1090 | struct _rule_hw { |
1091 | union { | |
1092 | struct { | |
1093 | u8 size; | |
1094 | u8 rsvd; | |
1095 | __be16 id; | |
1096 | }; | |
1097 | struct mlx4_net_trans_rule_hw_eth eth; | |
1098 | struct mlx4_net_trans_rule_hw_ib ib; | |
1099 | struct mlx4_net_trans_rule_hw_ipv4 ipv4; | |
1100 | struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; | |
7ffdf726 | 1101 | struct mlx4_net_trans_rule_hw_vxlan vxlan; |
3cd0e178 HHZ |
1102 | }; |
1103 | }; | |
1104 | ||
7ffdf726 OG |
1105 | enum { |
1106 | VXLAN_STEER_BY_OUTER_MAC = 1 << 0, | |
1107 | VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, | |
1108 | VXLAN_STEER_BY_VSID_VNI = 1 << 2, | |
1109 | VXLAN_STEER_BY_INNER_MAC = 1 << 3, | |
1110 | VXLAN_STEER_BY_INNER_VLAN = 1 << 4, | |
1111 | }; | |
1112 | ||
1113 | ||
592e49dd HHZ |
1114 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, |
1115 | enum mlx4_net_trans_promisc_mode mode); | |
1116 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, | |
1117 | enum mlx4_net_trans_promisc_mode mode); | |
1679200f YP |
1118 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
1119 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1120 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1121 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1122 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
1123 | ||
ffe455ad EE |
1124 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
1125 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
16a10ffd YB |
1126 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
1127 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
93ece0c1 | 1128 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); |
9a9a232a YP |
1129 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
1130 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | |
1131 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | |
1132 | u8 promisc); | |
e5395e92 AV |
1133 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); |
1134 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
1135 | u8 *pg, u16 *ratelimit); | |
7ffdf726 | 1136 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering); |
dd5f03be | 1137 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); |
4c3eb3ca | 1138 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 | 1139 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2009d005 | 1140 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
2a2336f8 | 1141 | |
8ad11fb6 JM |
1142 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
1143 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
1144 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1145 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
1146 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1147 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1148 | u32 *lkey, u32 *rkey); | |
1149 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1150 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 1151 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
d9236c3f AV |
1152 | int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, |
1153 | int *vector); | |
0b7ca5a9 | 1154 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); |
8ad11fb6 | 1155 | |
8e1a28e8 | 1156 | int mlx4_get_phys_port_id(struct mlx4_dev *dev); |
14c07b13 YP |
1157 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
1158 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
1159 | ||
f2a3f6a3 OG |
1160 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
1161 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
1162 | ||
0ff1fb65 HHZ |
1163 | int mlx4_flow_attach(struct mlx4_dev *dev, |
1164 | struct mlx4_net_trans_rule *rule, u64 *reg_id); | |
1165 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); | |
c2c19dc3 HHZ |
1166 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, |
1167 | enum mlx4_net_trans_promisc_mode flow_type); | |
1168 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, | |
1169 | enum mlx4_net_trans_rule_id id); | |
1170 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); | |
0ff1fb65 | 1171 | |
54679e14 JM |
1172 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, |
1173 | int i, int val); | |
1174 | ||
396f2feb JM |
1175 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); |
1176 | ||
993c401e JM |
1177 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); |
1178 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1179 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1180 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); | |
1181 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); | |
1182 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); | |
1183 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); | |
1184 | ||
afa8fd1d JM |
1185 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
1186 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); | |
6ee51a4e JM |
1187 | int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id); |
1188 | int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid); | |
993c401e | 1189 | |
4de65803 MB |
1190 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, |
1191 | u32 max_range_qpn); | |
1192 | ||
ec693d47 AV |
1193 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); |
1194 | ||
225c7b1f | 1195 | #endif /* MLX4_DEVICE_H */ |