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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
574e2af7 | 36 | #include <linux/if_ether.h> |
225c7b1f RD |
37 | #include <linux/pci.h> |
38 | #include <linux/completion.h> | |
39 | #include <linux/radix-tree.h> | |
d9236c3f | 40 | #include <linux/cpu_rmap.h> |
225c7b1f | 41 | |
60063497 | 42 | #include <linux/atomic.h> |
225c7b1f | 43 | |
ec693d47 AV |
44 | #include <linux/clocksource.h> |
45 | ||
0b7ca5a9 YP |
46 | #define MAX_MSIX_P_PORT 17 |
47 | #define MAX_MSIX 64 | |
48 | #define MSIX_LEGACY_SZ 4 | |
49 | #define MIN_MSIX_P_PORT 5 | |
50 | ||
523ece88 EE |
51 | #define MLX4_NUM_UP 8 |
52 | #define MLX4_NUM_TC 8 | |
53 | #define MLX4_MAX_100M_UNITS_VAL 255 /* | |
54 | * work around: can't set values | |
55 | * greater then this value when | |
56 | * using 100 Mbps units. | |
57 | */ | |
58 | #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ | |
59 | #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ | |
60 | #define MLX4_RATELIMIT_DEFAULT 0x00ff | |
61 | ||
6ee51a4e | 62 | #define MLX4_ROCE_MAX_GIDS 128 |
b6ffaeff | 63 | #define MLX4_ROCE_PF_GIDS 16 |
6ee51a4e | 64 | |
225c7b1f RD |
65 | enum { |
66 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 67 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
68 | MLX4_FLAG_MASTER = 1 << 2, |
69 | MLX4_FLAG_SLAVE = 1 << 3, | |
70 | MLX4_FLAG_SRIOV = 1 << 4, | |
acddd5dd | 71 | MLX4_FLAG_OLD_REG_MAC = 1 << 6, |
225c7b1f RD |
72 | }; |
73 | ||
efcd235d JM |
74 | enum { |
75 | MLX4_PORT_CAP_IS_SM = 1 << 1, | |
76 | MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, | |
77 | }; | |
78 | ||
225c7b1f | 79 | enum { |
fc06573d JM |
80 | MLX4_MAX_PORTS = 2, |
81 | MLX4_MAX_PORT_PKEYS = 128 | |
225c7b1f RD |
82 | }; |
83 | ||
396f2feb JM |
84 | /* base qkey for use in sriov tunnel-qp/proxy-qp communication. |
85 | * These qkeys must not be allowed for general use. This is a 64k range, | |
86 | * and to test for violation, we use the mask (protect against future chg). | |
87 | */ | |
88 | #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) | |
89 | #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) | |
90 | ||
cd9281d8 JM |
91 | enum { |
92 | MLX4_BOARD_ID_LEN = 64 | |
93 | }; | |
94 | ||
623ed84b JM |
95 | enum { |
96 | MLX4_MAX_NUM_PF = 16, | |
97 | MLX4_MAX_NUM_VF = 64, | |
1ab95d37 | 98 | MLX4_MAX_NUM_VF_P_PORT = 64, |
623ed84b | 99 | MLX4_MFUNC_MAX = 80, |
3fc929e2 | 100 | MLX4_MAX_EQ_NUM = 1024, |
623ed84b JM |
101 | MLX4_MFUNC_EQ_NUM = 4, |
102 | MLX4_MFUNC_MAX_EQES = 8, | |
103 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
104 | }; | |
105 | ||
0ff1fb65 HHZ |
106 | /* Driver supports 3 diffrent device methods to manage traffic steering: |
107 | * -device managed - High level API for ib and eth flow steering. FW is | |
108 | * managing flow steering tables. | |
c96d97f4 HHZ |
109 | * - B0 steering mode - Common low level API for ib and (if supported) eth. |
110 | * - A0 steering mode - Limited low level API for eth. In case of IB, | |
111 | * B0 mode is in use. | |
112 | */ | |
113 | enum { | |
114 | MLX4_STEERING_MODE_A0, | |
0ff1fb65 HHZ |
115 | MLX4_STEERING_MODE_B0, |
116 | MLX4_STEERING_MODE_DEVICE_MANAGED | |
c96d97f4 HHZ |
117 | }; |
118 | ||
119 | static inline const char *mlx4_steering_mode_str(int steering_mode) | |
120 | { | |
121 | switch (steering_mode) { | |
122 | case MLX4_STEERING_MODE_A0: | |
123 | return "A0 steering"; | |
124 | ||
125 | case MLX4_STEERING_MODE_B0: | |
126 | return "B0 steering"; | |
0ff1fb65 HHZ |
127 | |
128 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
129 | return "Device managed flow steering"; | |
130 | ||
c96d97f4 HHZ |
131 | default: |
132 | return "Unrecognize steering mode"; | |
133 | } | |
134 | } | |
135 | ||
7ffdf726 OG |
136 | enum { |
137 | MLX4_TUNNEL_OFFLOAD_MODE_NONE, | |
138 | MLX4_TUNNEL_OFFLOAD_MODE_VXLAN | |
139 | }; | |
140 | ||
225c7b1f | 141 | enum { |
52eafc68 OG |
142 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
143 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
144 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 145 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
146 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
147 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
148 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
149 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
150 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
151 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
152 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
153 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
154 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
155 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
156 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
157 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
158 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
159 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 160 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
161 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
162 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
163 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
164 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 165 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 | 166 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
540b3a39 | 167 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
00f5ce99 JM |
168 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
169 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | |
08ff3235 OG |
170 | MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, |
171 | MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 | |
225c7b1f RD |
172 | }; |
173 | ||
b3416f44 SP |
174 | enum { |
175 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, | |
176 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, | |
0ff1fb65 | 177 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, |
955154fa | 178 | MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, |
5930e8d0 | 179 | MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, |
3f7fb021 | 180 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
e6b6a231 | 181 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
b01978ca | 182 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
4de65803 | 183 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, |
4ba9920e LT |
184 | MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, |
185 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, | |
b3416f44 SP |
186 | }; |
187 | ||
08ff3235 OG |
188 | enum { |
189 | MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, | |
190 | MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 | |
191 | }; | |
192 | ||
193 | enum { | |
194 | MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 | |
195 | }; | |
196 | ||
197 | enum { | |
198 | MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 | |
199 | }; | |
200 | ||
201 | ||
97285b78 MA |
202 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
203 | ||
95d04f07 | 204 | enum { |
804d6a89 | 205 | MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, |
95d04f07 RD |
206 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, |
207 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
208 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
209 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
210 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
211 | }; | |
212 | ||
225c7b1f RD |
213 | enum mlx4_event { |
214 | MLX4_EVENT_TYPE_COMP = 0x00, | |
215 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
216 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
217 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
218 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
219 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
220 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
221 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
222 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
223 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
224 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
225 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
226 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
227 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
228 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
229 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
230 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
231 | MLX4_EVENT_TYPE_CMD = 0x0a, |
232 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
233 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
fe6f700d | 234 | MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, |
5984be90 | 235 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
623ed84b | 236 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
00f5ce99 | 237 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
623ed84b | 238 | MLX4_EVENT_TYPE_NONE = 0xff, |
225c7b1f RD |
239 | }; |
240 | ||
241 | enum { | |
242 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
243 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
244 | }; | |
245 | ||
5984be90 JM |
246 | enum { |
247 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, | |
248 | }; | |
249 | ||
993c401e JM |
250 | enum slave_port_state { |
251 | SLAVE_PORT_DOWN = 0, | |
252 | SLAVE_PENDING_UP, | |
253 | SLAVE_PORT_UP, | |
254 | }; | |
255 | ||
256 | enum slave_port_gen_event { | |
257 | SLAVE_PORT_GEN_EVENT_DOWN = 0, | |
258 | SLAVE_PORT_GEN_EVENT_UP, | |
259 | SLAVE_PORT_GEN_EVENT_NONE, | |
260 | }; | |
261 | ||
262 | enum slave_port_state_event { | |
263 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
264 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP, | |
265 | MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, | |
266 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID, | |
267 | }; | |
268 | ||
225c7b1f RD |
269 | enum { |
270 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
271 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
272 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
273 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
804d6a89 SM |
274 | MLX4_PERM_ATOMIC = 1 << 14, |
275 | MLX4_PERM_BIND_MW = 1 << 15, | |
225c7b1f RD |
276 | }; |
277 | ||
278 | enum { | |
279 | MLX4_OPCODE_NOP = 0x00, | |
280 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
281 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
282 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
283 | MLX4_OPCODE_SEND = 0x0a, | |
284 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
285 | MLX4_OPCODE_LSO = 0x0e, | |
286 | MLX4_OPCODE_RDMA_READ = 0x10, | |
287 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
288 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
289 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
290 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
291 | MLX4_OPCODE_BIND_MW = 0x18, |
292 | MLX4_OPCODE_FMR = 0x19, | |
293 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
294 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
295 | ||
296 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
297 | MLX4_RECV_OPCODE_SEND = 0x01, | |
298 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
299 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
300 | ||
301 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
302 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
303 | }; | |
304 | ||
305 | enum { | |
306 | MLX4_STAT_RATE_OFFSET = 5 | |
307 | }; | |
308 | ||
da995a8a | 309 | enum mlx4_protocol { |
0345584e YP |
310 | MLX4_PROT_IB_IPV6 = 0, |
311 | MLX4_PROT_ETH, | |
312 | MLX4_PROT_IB_IPV4, | |
313 | MLX4_PROT_FCOE | |
da995a8a AS |
314 | }; |
315 | ||
29bdc883 VS |
316 | enum { |
317 | MLX4_MTT_FLAG_PRESENT = 1 | |
318 | }; | |
319 | ||
93fc9e1b YP |
320 | enum mlx4_qp_region { |
321 | MLX4_QP_REGION_FW = 0, | |
322 | MLX4_QP_REGION_ETH_ADDR, | |
323 | MLX4_QP_REGION_FC_ADDR, | |
324 | MLX4_QP_REGION_FC_EXCH, | |
325 | MLX4_NUM_QP_REGION | |
326 | }; | |
327 | ||
7ff93f8b | 328 | enum mlx4_port_type { |
623ed84b | 329 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
330 | MLX4_PORT_TYPE_IB = 1, |
331 | MLX4_PORT_TYPE_ETH = 2, | |
332 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
333 | }; |
334 | ||
2a2336f8 YP |
335 | enum mlx4_special_vlan_idx { |
336 | MLX4_NO_VLAN_IDX = 0, | |
337 | MLX4_VLAN_MISS_IDX, | |
338 | MLX4_VLAN_REGULAR | |
339 | }; | |
340 | ||
0345584e YP |
341 | enum mlx4_steer_type { |
342 | MLX4_MC_STEER = 0, | |
343 | MLX4_UC_STEER, | |
344 | MLX4_NUM_STEERS | |
345 | }; | |
346 | ||
93fc9e1b YP |
347 | enum { |
348 | MLX4_NUM_FEXCH = 64 * 1024, | |
349 | }; | |
350 | ||
5a0fd094 EC |
351 | enum { |
352 | MLX4_MAX_FAST_REG_PAGES = 511, | |
353 | }; | |
354 | ||
00f5ce99 JM |
355 | enum { |
356 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, | |
357 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, | |
358 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, | |
359 | }; | |
360 | ||
361 | /* Port mgmt change event handling */ | |
362 | enum { | |
363 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, | |
364 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, | |
365 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, | |
366 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, | |
367 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, | |
368 | }; | |
369 | ||
370 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ | |
371 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) | |
372 | ||
ea54b10c JM |
373 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
374 | { | |
375 | return (major << 32) | (minor << 16) | subminor; | |
376 | } | |
377 | ||
3fc929e2 | 378 | struct mlx4_phys_caps { |
6634961c JM |
379 | u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; |
380 | u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; | |
3fc929e2 | 381 | u32 num_phys_eqs; |
47605df9 JM |
382 | u32 base_sqpn; |
383 | u32 base_proxy_sqpn; | |
384 | u32 base_tunnel_sqpn; | |
3fc929e2 MA |
385 | }; |
386 | ||
225c7b1f RD |
387 | struct mlx4_caps { |
388 | u64 fw_ver; | |
623ed84b | 389 | u32 function; |
225c7b1f | 390 | int num_ports; |
5ae2a7a8 | 391 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 392 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 393 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
394 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
395 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
396 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
397 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
398 | int trans_type[MLX4_MAX_PORTS + 1]; |
399 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
400 | int wavelength[MLX4_MAX_PORTS + 1]; | |
401 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
402 | int local_ca_ack_delay; |
403 | int num_uars; | |
f5311ac1 | 404 | u32 uar_page_size; |
225c7b1f RD |
405 | int bf_reg_size; |
406 | int bf_regs_per_page; | |
407 | int max_sq_sg; | |
408 | int max_rq_sg; | |
409 | int num_qps; | |
410 | int max_wqes; | |
411 | int max_sq_desc_sz; | |
412 | int max_rq_desc_sz; | |
413 | int max_qp_init_rdma; | |
414 | int max_qp_dest_rdma; | |
99ec41d0 | 415 | u32 *qp0_qkey; |
47605df9 JM |
416 | u32 *qp0_proxy; |
417 | u32 *qp1_proxy; | |
418 | u32 *qp0_tunnel; | |
419 | u32 *qp1_tunnel; | |
225c7b1f RD |
420 | int num_srqs; |
421 | int max_srq_wqes; | |
422 | int max_srq_sge; | |
423 | int reserved_srqs; | |
424 | int num_cqs; | |
425 | int max_cqes; | |
426 | int reserved_cqs; | |
427 | int num_eqs; | |
428 | int reserved_eqs; | |
b8dd786f | 429 | int num_comp_vectors; |
0b7ca5a9 | 430 | int comp_pool; |
225c7b1f | 431 | int num_mpts; |
a5bbe892 | 432 | int max_fmr_maps; |
2b8fb286 | 433 | int num_mtts; |
225c7b1f RD |
434 | int fmr_reserved_mtts; |
435 | int reserved_mtts; | |
436 | int reserved_mrws; | |
437 | int reserved_uars; | |
438 | int num_mgms; | |
439 | int num_amgms; | |
440 | int reserved_mcgs; | |
441 | int num_qp_per_mgm; | |
c96d97f4 | 442 | int steering_mode; |
0ff1fb65 | 443 | int fs_log_max_ucast_qp_range_size; |
225c7b1f RD |
444 | int num_pds; |
445 | int reserved_pds; | |
012a8ff5 SH |
446 | int max_xrcds; |
447 | int reserved_xrcds; | |
225c7b1f | 448 | int mtt_entry_sz; |
149983af | 449 | u32 max_msg_sz; |
225c7b1f | 450 | u32 page_size_cap; |
52eafc68 | 451 | u64 flags; |
b3416f44 | 452 | u64 flags2; |
95d04f07 RD |
453 | u32 bmme_flags; |
454 | u32 reserved_lkey; | |
225c7b1f | 455 | u16 stat_rate_support; |
5ae2a7a8 | 456 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 457 | int max_gso_sz; |
b3416f44 | 458 | int max_rss_tbl_sz; |
93fc9e1b YP |
459 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
460 | int reserved_qps; | |
461 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
462 | int log_num_macs; | |
463 | int log_num_vlans; | |
7ff93f8b YP |
464 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
465 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
466 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
467 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 468 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 469 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 470 | u32 max_counters; |
096335b3 | 471 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
1ffeb2eb | 472 | u16 sqp_demux; |
08ff3235 OG |
473 | u32 eqe_size; |
474 | u32 cqe_size; | |
475 | u8 eqe_factor; | |
476 | u32 userspace_caps; /* userspace must be aware of these */ | |
477 | u32 function_caps; /* VFs must be aware of these */ | |
ddd8a6c1 | 478 | u16 hca_core_clock; |
8e1a28e8 | 479 | u64 phys_port_id[MLX4_MAX_PORTS + 1]; |
7ffdf726 | 480 | int tunnel_offload_mode; |
225c7b1f RD |
481 | }; |
482 | ||
483 | struct mlx4_buf_list { | |
484 | void *buf; | |
485 | dma_addr_t map; | |
486 | }; | |
487 | ||
488 | struct mlx4_buf { | |
b57aacfa RD |
489 | struct mlx4_buf_list direct; |
490 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
491 | int nbufs; |
492 | int npages; | |
493 | int page_shift; | |
494 | }; | |
495 | ||
496 | struct mlx4_mtt { | |
2b8fb286 | 497 | u32 offset; |
225c7b1f RD |
498 | int order; |
499 | int page_shift; | |
500 | }; | |
501 | ||
6296883c YP |
502 | enum { |
503 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
504 | }; | |
505 | ||
506 | struct mlx4_db_pgdir { | |
507 | struct list_head list; | |
508 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
509 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
510 | unsigned long *bits[2]; | |
511 | __be32 *db_page; | |
512 | dma_addr_t db_dma; | |
513 | }; | |
514 | ||
515 | struct mlx4_ib_user_db_page; | |
516 | ||
517 | struct mlx4_db { | |
518 | __be32 *db; | |
519 | union { | |
520 | struct mlx4_db_pgdir *pgdir; | |
521 | struct mlx4_ib_user_db_page *user_page; | |
522 | } u; | |
523 | dma_addr_t dma; | |
524 | int index; | |
525 | int order; | |
526 | }; | |
527 | ||
38ae6a53 YP |
528 | struct mlx4_hwq_resources { |
529 | struct mlx4_db db; | |
530 | struct mlx4_mtt mtt; | |
531 | struct mlx4_buf buf; | |
532 | }; | |
533 | ||
225c7b1f RD |
534 | struct mlx4_mr { |
535 | struct mlx4_mtt mtt; | |
536 | u64 iova; | |
537 | u64 size; | |
538 | u32 key; | |
539 | u32 pd; | |
540 | u32 access; | |
541 | int enabled; | |
542 | }; | |
543 | ||
804d6a89 SM |
544 | enum mlx4_mw_type { |
545 | MLX4_MW_TYPE_1 = 1, | |
546 | MLX4_MW_TYPE_2 = 2, | |
547 | }; | |
548 | ||
549 | struct mlx4_mw { | |
550 | u32 key; | |
551 | u32 pd; | |
552 | enum mlx4_mw_type type; | |
553 | int enabled; | |
554 | }; | |
555 | ||
8ad11fb6 JM |
556 | struct mlx4_fmr { |
557 | struct mlx4_mr mr; | |
558 | struct mlx4_mpt_entry *mpt; | |
559 | __be64 *mtts; | |
560 | dma_addr_t dma_handle; | |
561 | int max_pages; | |
562 | int max_maps; | |
563 | int maps; | |
564 | u8 page_shift; | |
565 | }; | |
566 | ||
225c7b1f RD |
567 | struct mlx4_uar { |
568 | unsigned long pfn; | |
569 | int index; | |
c1b43dca EC |
570 | struct list_head bf_list; |
571 | unsigned free_bf_bmap; | |
572 | void __iomem *map; | |
573 | void __iomem *bf_map; | |
574 | }; | |
575 | ||
576 | struct mlx4_bf { | |
577 | unsigned long offset; | |
578 | int buf_size; | |
579 | struct mlx4_uar *uar; | |
580 | void __iomem *reg; | |
225c7b1f RD |
581 | }; |
582 | ||
583 | struct mlx4_cq { | |
584 | void (*comp) (struct mlx4_cq *); | |
585 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
586 | ||
587 | struct mlx4_uar *uar; | |
588 | ||
589 | u32 cons_index; | |
590 | ||
2eacc23c | 591 | u16 irq; |
225c7b1f RD |
592 | __be32 *set_ci_db; |
593 | __be32 *arm_db; | |
594 | int arm_sn; | |
595 | ||
596 | int cqn; | |
b8dd786f | 597 | unsigned vector; |
225c7b1f RD |
598 | |
599 | atomic_t refcount; | |
600 | struct completion free; | |
601 | }; | |
602 | ||
603 | struct mlx4_qp { | |
604 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
605 | ||
606 | int qpn; | |
607 | ||
608 | atomic_t refcount; | |
609 | struct completion free; | |
610 | }; | |
611 | ||
612 | struct mlx4_srq { | |
613 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
614 | ||
615 | int srqn; | |
616 | int max; | |
617 | int max_gs; | |
618 | int wqe_shift; | |
619 | ||
620 | atomic_t refcount; | |
621 | struct completion free; | |
622 | }; | |
623 | ||
624 | struct mlx4_av { | |
625 | __be32 port_pd; | |
626 | u8 reserved1; | |
627 | u8 g_slid; | |
628 | __be16 dlid; | |
629 | u8 reserved2; | |
630 | u8 gid_index; | |
631 | u8 stat_rate; | |
632 | u8 hop_limit; | |
633 | __be32 sl_tclass_flowlabel; | |
634 | u8 dgid[16]; | |
635 | }; | |
636 | ||
fa417f7b EC |
637 | struct mlx4_eth_av { |
638 | __be32 port_pd; | |
639 | u8 reserved1; | |
640 | u8 smac_idx; | |
641 | u16 reserved2; | |
642 | u8 reserved3; | |
643 | u8 gid_index; | |
644 | u8 stat_rate; | |
645 | u8 hop_limit; | |
646 | __be32 sl_tclass_flowlabel; | |
647 | u8 dgid[16]; | |
5ea8bbfc JM |
648 | u8 s_mac[6]; |
649 | u8 reserved4[2]; | |
fa417f7b | 650 | __be16 vlan; |
574e2af7 | 651 | u8 mac[ETH_ALEN]; |
fa417f7b EC |
652 | }; |
653 | ||
654 | union mlx4_ext_av { | |
655 | struct mlx4_av ib; | |
656 | struct mlx4_eth_av eth; | |
657 | }; | |
658 | ||
f2a3f6a3 OG |
659 | struct mlx4_counter { |
660 | u8 reserved1[3]; | |
661 | u8 counter_mode; | |
662 | __be32 num_ifc; | |
663 | u32 reserved2[2]; | |
664 | __be64 rx_frames; | |
665 | __be64 rx_bytes; | |
666 | __be64 tx_frames; | |
667 | __be64 tx_bytes; | |
668 | }; | |
669 | ||
5a0d0a61 JM |
670 | struct mlx4_quotas { |
671 | int qp; | |
672 | int cq; | |
673 | int srq; | |
674 | int mpt; | |
675 | int mtt; | |
676 | int counter; | |
677 | int xrcd; | |
678 | }; | |
679 | ||
1ab95d37 MB |
680 | struct mlx4_vf_dev { |
681 | u8 min_port; | |
682 | u8 n_ports; | |
683 | }; | |
684 | ||
225c7b1f RD |
685 | struct mlx4_dev { |
686 | struct pci_dev *pdev; | |
687 | unsigned long flags; | |
623ed84b | 688 | unsigned long num_slaves; |
225c7b1f | 689 | struct mlx4_caps caps; |
3fc929e2 | 690 | struct mlx4_phys_caps phys_caps; |
5a0d0a61 | 691 | struct mlx4_quotas quotas; |
225c7b1f | 692 | struct radix_tree_root qp_table_tree; |
725c8999 | 693 | u8 rev_id; |
cd9281d8 | 694 | char board_id[MLX4_BOARD_ID_LEN]; |
ab9c17a0 | 695 | int num_vfs; |
6e7136ed | 696 | int numa_node; |
3c439b55 | 697 | int oper_log_mgm_entry_size; |
592e49dd HHZ |
698 | u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; |
699 | u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; | |
1ab95d37 | 700 | struct mlx4_vf_dev *dev_vfs; |
225c7b1f RD |
701 | }; |
702 | ||
00f5ce99 JM |
703 | struct mlx4_eqe { |
704 | u8 reserved1; | |
705 | u8 type; | |
706 | u8 reserved2; | |
707 | u8 subtype; | |
708 | union { | |
709 | u32 raw[6]; | |
710 | struct { | |
711 | __be32 cqn; | |
712 | } __packed comp; | |
713 | struct { | |
714 | u16 reserved1; | |
715 | __be16 token; | |
716 | u32 reserved2; | |
717 | u8 reserved3[3]; | |
718 | u8 status; | |
719 | __be64 out_param; | |
720 | } __packed cmd; | |
721 | struct { | |
722 | __be32 qpn; | |
723 | } __packed qp; | |
724 | struct { | |
725 | __be32 srqn; | |
726 | } __packed srq; | |
727 | struct { | |
728 | __be32 cqn; | |
729 | u32 reserved1; | |
730 | u8 reserved2[3]; | |
731 | u8 syndrome; | |
732 | } __packed cq_err; | |
733 | struct { | |
734 | u32 reserved1[2]; | |
735 | __be32 port; | |
736 | } __packed port_change; | |
737 | struct { | |
738 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 | |
739 | u32 reserved; | |
740 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; | |
741 | } __packed comm_channel_arm; | |
742 | struct { | |
743 | u8 port; | |
744 | u8 reserved[3]; | |
745 | __be64 mac; | |
746 | } __packed mac_update; | |
747 | struct { | |
748 | __be32 slave_id; | |
749 | } __packed flr_event; | |
750 | struct { | |
751 | __be16 current_temperature; | |
752 | __be16 warning_threshold; | |
753 | } __packed warming; | |
754 | struct { | |
755 | u8 reserved[3]; | |
756 | u8 port; | |
757 | union { | |
758 | struct { | |
759 | __be16 mstr_sm_lid; | |
760 | __be16 port_lid; | |
761 | __be32 changed_attr; | |
762 | u8 reserved[3]; | |
763 | u8 mstr_sm_sl; | |
764 | __be64 gid_prefix; | |
765 | } __packed port_info; | |
766 | struct { | |
767 | __be32 block_ptr; | |
768 | __be32 tbl_entries_mask; | |
769 | } __packed tbl_change_info; | |
770 | } params; | |
771 | } __packed port_mgmt_change; | |
772 | } event; | |
773 | u8 slave_id; | |
774 | u8 reserved3[2]; | |
775 | u8 owner; | |
776 | } __packed; | |
777 | ||
225c7b1f RD |
778 | struct mlx4_init_port_param { |
779 | int set_guid0; | |
780 | int set_node_guid; | |
781 | int set_si_guid; | |
782 | u16 mtu; | |
783 | int port_width_cap; | |
784 | u16 vl_cap; | |
785 | u16 max_gid; | |
786 | u16 max_pkey; | |
787 | u64 guid0; | |
788 | u64 node_guid; | |
789 | u64 si_guid; | |
790 | }; | |
791 | ||
7ff93f8b YP |
792 | #define mlx4_foreach_port(port, dev, type) \ |
793 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 794 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 795 | |
026149cb JM |
796 | #define mlx4_foreach_non_ib_transport_port(port, dev) \ |
797 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
798 | if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) | |
799 | ||
65dab25d JM |
800 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
801 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
802 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ | |
803 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
623ed84b | 804 | |
752a50ca JM |
805 | #define MLX4_INVALID_SLAVE_ID 0xFF |
806 | ||
00f5ce99 JM |
807 | void handle_port_mgmt_change_event(struct work_struct *work); |
808 | ||
2aca1172 JM |
809 | static inline int mlx4_master_func_num(struct mlx4_dev *dev) |
810 | { | |
811 | return dev->caps.function; | |
812 | } | |
813 | ||
623ed84b JM |
814 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
815 | { | |
816 | return dev->flags & MLX4_FLAG_MASTER; | |
817 | } | |
818 | ||
5a0d0a61 JM |
819 | static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) |
820 | { | |
821 | return dev->phys_caps.base_sqpn + 8 + | |
822 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); | |
823 | } | |
824 | ||
623ed84b JM |
825 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) |
826 | { | |
47605df9 | 827 | return (qpn < dev->phys_caps.base_sqpn + 8 + |
e2c76824 JM |
828 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); |
829 | } | |
830 | ||
831 | static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) | |
832 | { | |
47605df9 | 833 | int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; |
e2c76824 | 834 | |
47605df9 | 835 | if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) |
e2c76824 JM |
836 | return 1; |
837 | ||
838 | return 0; | |
623ed84b | 839 | } |
fa417f7b | 840 | |
623ed84b JM |
841 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
842 | { | |
843 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
844 | } | |
845 | ||
846 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
847 | { | |
848 | return dev->flags & MLX4_FLAG_SLAVE; | |
849 | } | |
fa417f7b | 850 | |
225c7b1f | 851 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
40f2287b | 852 | struct mlx4_buf *buf, gfp_t gfp); |
225c7b1f | 853 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); |
1c69fc2a RD |
854 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
855 | { | |
313abe55 | 856 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 857 | return buf->direct.buf + offset; |
1c69fc2a | 858 | else |
b57aacfa | 859 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
860 | (offset & (PAGE_SIZE - 1)); |
861 | } | |
225c7b1f RD |
862 | |
863 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
864 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
865 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
866 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
867 | |
868 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
869 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
163561a4 | 870 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); |
c1b43dca | 871 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); |
225c7b1f RD |
872 | |
873 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
874 | struct mlx4_mtt *mtt); | |
875 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
876 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
877 | ||
878 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
879 | int npages, int page_shift, struct mlx4_mr *mr); | |
61083720 | 880 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); |
225c7b1f | 881 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); |
804d6a89 SM |
882 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
883 | struct mlx4_mw *mw); | |
884 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
885 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
225c7b1f RD |
886 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
887 | int start_index, int npages, u64 *page_list); | |
888 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
40f2287b | 889 | struct mlx4_buf *buf, gfp_t gfp); |
225c7b1f | 890 | |
40f2287b JK |
891 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, |
892 | gfp_t gfp); | |
6296883c YP |
893 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); |
894 | ||
38ae6a53 YP |
895 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
896 | int size, int max_direct); | |
897 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
898 | int size); | |
899 | ||
225c7b1f | 900 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 901 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
ec693d47 | 902 | unsigned vector, int collapsed, int timestamp_en); |
225c7b1f RD |
903 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
904 | ||
a3cdcbfa YP |
905 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
906 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
907 | ||
40f2287b JK |
908 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, |
909 | gfp_t gfp); | |
225c7b1f RD |
910 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
911 | ||
18abd5ea SH |
912 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
913 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
914 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
915 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 916 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 917 | |
5ae2a7a8 | 918 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
919 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
920 | ||
ffe455ad EE |
921 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
922 | int block_mcast_loopback, enum mlx4_protocol prot); | |
923 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
924 | enum mlx4_protocol prot); | |
521e575b | 925 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
926 | u8 port, int block_mcast_loopback, |
927 | enum mlx4_protocol protocol, u64 *reg_id); | |
da995a8a | 928 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
929 | enum mlx4_protocol protocol, u64 reg_id); |
930 | ||
931 | enum { | |
932 | MLX4_DOMAIN_UVERBS = 0x1000, | |
933 | MLX4_DOMAIN_ETHTOOL = 0x2000, | |
934 | MLX4_DOMAIN_RFS = 0x3000, | |
935 | MLX4_DOMAIN_NIC = 0x5000, | |
936 | }; | |
937 | ||
938 | enum mlx4_net_trans_rule_id { | |
939 | MLX4_NET_TRANS_RULE_ID_ETH = 0, | |
940 | MLX4_NET_TRANS_RULE_ID_IB, | |
941 | MLX4_NET_TRANS_RULE_ID_IPV6, | |
942 | MLX4_NET_TRANS_RULE_ID_IPV4, | |
943 | MLX4_NET_TRANS_RULE_ID_TCP, | |
944 | MLX4_NET_TRANS_RULE_ID_UDP, | |
7ffdf726 | 945 | MLX4_NET_TRANS_RULE_ID_VXLAN, |
0ff1fb65 HHZ |
946 | MLX4_NET_TRANS_RULE_NUM, /* should be last */ |
947 | }; | |
948 | ||
a8edc3bf HHZ |
949 | extern const u16 __sw_id_hw[]; |
950 | ||
7fb40f87 HHZ |
951 | static inline int map_hw_to_sw_id(u16 header_id) |
952 | { | |
953 | ||
954 | int i; | |
955 | for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { | |
956 | if (header_id == __sw_id_hw[i]) | |
957 | return i; | |
958 | } | |
959 | return -EINVAL; | |
960 | } | |
961 | ||
0ff1fb65 | 962 | enum mlx4_net_trans_promisc_mode { |
f9162539 HHZ |
963 | MLX4_FS_REGULAR = 1, |
964 | MLX4_FS_ALL_DEFAULT, | |
965 | MLX4_FS_MC_DEFAULT, | |
966 | MLX4_FS_UC_SNIFFER, | |
967 | MLX4_FS_MC_SNIFFER, | |
c2c19dc3 | 968 | MLX4_FS_MODE_NUM, /* should be last */ |
0ff1fb65 HHZ |
969 | }; |
970 | ||
971 | struct mlx4_spec_eth { | |
574e2af7 JP |
972 | u8 dst_mac[ETH_ALEN]; |
973 | u8 dst_mac_msk[ETH_ALEN]; | |
974 | u8 src_mac[ETH_ALEN]; | |
975 | u8 src_mac_msk[ETH_ALEN]; | |
0ff1fb65 HHZ |
976 | u8 ether_type_enable; |
977 | __be16 ether_type; | |
978 | __be16 vlan_id_msk; | |
979 | __be16 vlan_id; | |
980 | }; | |
981 | ||
982 | struct mlx4_spec_tcp_udp { | |
983 | __be16 dst_port; | |
984 | __be16 dst_port_msk; | |
985 | __be16 src_port; | |
986 | __be16 src_port_msk; | |
987 | }; | |
988 | ||
989 | struct mlx4_spec_ipv4 { | |
990 | __be32 dst_ip; | |
991 | __be32 dst_ip_msk; | |
992 | __be32 src_ip; | |
993 | __be32 src_ip_msk; | |
994 | }; | |
995 | ||
996 | struct mlx4_spec_ib { | |
ba60a356 | 997 | __be32 l3_qpn; |
0ff1fb65 HHZ |
998 | __be32 qpn_msk; |
999 | u8 dst_gid[16]; | |
1000 | u8 dst_gid_msk[16]; | |
1001 | }; | |
1002 | ||
7ffdf726 OG |
1003 | struct mlx4_spec_vxlan { |
1004 | __be32 vni; | |
1005 | __be32 vni_mask; | |
1006 | ||
1007 | }; | |
1008 | ||
0ff1fb65 HHZ |
1009 | struct mlx4_spec_list { |
1010 | struct list_head list; | |
1011 | enum mlx4_net_trans_rule_id id; | |
1012 | union { | |
1013 | struct mlx4_spec_eth eth; | |
1014 | struct mlx4_spec_ib ib; | |
1015 | struct mlx4_spec_ipv4 ipv4; | |
1016 | struct mlx4_spec_tcp_udp tcp_udp; | |
7ffdf726 | 1017 | struct mlx4_spec_vxlan vxlan; |
0ff1fb65 HHZ |
1018 | }; |
1019 | }; | |
1020 | ||
1021 | enum mlx4_net_trans_hw_rule_queue { | |
1022 | MLX4_NET_TRANS_Q_FIFO, | |
1023 | MLX4_NET_TRANS_Q_LIFO, | |
1024 | }; | |
1025 | ||
1026 | struct mlx4_net_trans_rule { | |
1027 | struct list_head list; | |
1028 | enum mlx4_net_trans_hw_rule_queue queue_mode; | |
1029 | bool exclusive; | |
1030 | bool allow_loopback; | |
1031 | enum mlx4_net_trans_promisc_mode promisc_mode; | |
1032 | u8 port; | |
1033 | u16 priority; | |
1034 | u32 qpn; | |
1035 | }; | |
1036 | ||
3cd0e178 | 1037 | struct mlx4_net_trans_rule_hw_ctrl { |
bcf37297 HHZ |
1038 | __be16 prio; |
1039 | u8 type; | |
1040 | u8 flags; | |
3cd0e178 HHZ |
1041 | u8 rsvd1; |
1042 | u8 funcid; | |
1043 | u8 vep; | |
1044 | u8 port; | |
1045 | __be32 qpn; | |
1046 | __be32 rsvd2; | |
1047 | }; | |
1048 | ||
1049 | struct mlx4_net_trans_rule_hw_ib { | |
1050 | u8 size; | |
1051 | u8 rsvd1; | |
1052 | __be16 id; | |
1053 | u32 rsvd2; | |
ba60a356 | 1054 | __be32 l3_qpn; |
3cd0e178 HHZ |
1055 | __be32 qpn_mask; |
1056 | u8 dst_gid[16]; | |
1057 | u8 dst_gid_msk[16]; | |
1058 | } __packed; | |
1059 | ||
1060 | struct mlx4_net_trans_rule_hw_eth { | |
1061 | u8 size; | |
1062 | u8 rsvd; | |
1063 | __be16 id; | |
1064 | u8 rsvd1[6]; | |
1065 | u8 dst_mac[6]; | |
1066 | u16 rsvd2; | |
1067 | u8 dst_mac_msk[6]; | |
1068 | u16 rsvd3; | |
1069 | u8 src_mac[6]; | |
1070 | u16 rsvd4; | |
1071 | u8 src_mac_msk[6]; | |
1072 | u8 rsvd5; | |
1073 | u8 ether_type_enable; | |
1074 | __be16 ether_type; | |
ba60a356 HHZ |
1075 | __be16 vlan_tag_msk; |
1076 | __be16 vlan_tag; | |
3cd0e178 HHZ |
1077 | } __packed; |
1078 | ||
1079 | struct mlx4_net_trans_rule_hw_tcp_udp { | |
1080 | u8 size; | |
1081 | u8 rsvd; | |
1082 | __be16 id; | |
1083 | __be16 rsvd1[3]; | |
1084 | __be16 dst_port; | |
1085 | __be16 rsvd2; | |
1086 | __be16 dst_port_msk; | |
1087 | __be16 rsvd3; | |
1088 | __be16 src_port; | |
1089 | __be16 rsvd4; | |
1090 | __be16 src_port_msk; | |
1091 | } __packed; | |
1092 | ||
1093 | struct mlx4_net_trans_rule_hw_ipv4 { | |
1094 | u8 size; | |
1095 | u8 rsvd; | |
1096 | __be16 id; | |
1097 | __be32 rsvd1; | |
1098 | __be32 dst_ip; | |
1099 | __be32 dst_ip_msk; | |
1100 | __be32 src_ip; | |
1101 | __be32 src_ip_msk; | |
1102 | } __packed; | |
1103 | ||
7ffdf726 OG |
1104 | struct mlx4_net_trans_rule_hw_vxlan { |
1105 | u8 size; | |
1106 | u8 rsvd; | |
1107 | __be16 id; | |
1108 | __be32 rsvd1; | |
1109 | __be32 vni; | |
1110 | __be32 vni_mask; | |
1111 | } __packed; | |
1112 | ||
3cd0e178 HHZ |
1113 | struct _rule_hw { |
1114 | union { | |
1115 | struct { | |
1116 | u8 size; | |
1117 | u8 rsvd; | |
1118 | __be16 id; | |
1119 | }; | |
1120 | struct mlx4_net_trans_rule_hw_eth eth; | |
1121 | struct mlx4_net_trans_rule_hw_ib ib; | |
1122 | struct mlx4_net_trans_rule_hw_ipv4 ipv4; | |
1123 | struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; | |
7ffdf726 | 1124 | struct mlx4_net_trans_rule_hw_vxlan vxlan; |
3cd0e178 HHZ |
1125 | }; |
1126 | }; | |
1127 | ||
7ffdf726 OG |
1128 | enum { |
1129 | VXLAN_STEER_BY_OUTER_MAC = 1 << 0, | |
1130 | VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, | |
1131 | VXLAN_STEER_BY_VSID_VNI = 1 << 2, | |
1132 | VXLAN_STEER_BY_INNER_MAC = 1 << 3, | |
1133 | VXLAN_STEER_BY_INNER_VLAN = 1 << 4, | |
1134 | }; | |
1135 | ||
1136 | ||
592e49dd HHZ |
1137 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, |
1138 | enum mlx4_net_trans_promisc_mode mode); | |
1139 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, | |
1140 | enum mlx4_net_trans_promisc_mode mode); | |
1679200f YP |
1141 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
1142 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1143 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1144 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1145 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
1146 | ||
ffe455ad EE |
1147 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
1148 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
16a10ffd YB |
1149 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
1150 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
93ece0c1 | 1151 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); |
9a9a232a YP |
1152 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
1153 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | |
1154 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | |
1155 | u8 promisc); | |
e5395e92 AV |
1156 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); |
1157 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
1158 | u8 *pg, u16 *ratelimit); | |
1b136de1 | 1159 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); |
dd5f03be | 1160 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); |
4c3eb3ca | 1161 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 | 1162 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2009d005 | 1163 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
2a2336f8 | 1164 | |
8ad11fb6 JM |
1165 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
1166 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
1167 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1168 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
1169 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1170 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1171 | u32 *lkey, u32 *rkey); | |
1172 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1173 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 1174 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
d9236c3f AV |
1175 | int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, |
1176 | int *vector); | |
0b7ca5a9 | 1177 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); |
8ad11fb6 | 1178 | |
35f6f453 AV |
1179 | int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); |
1180 | ||
8e1a28e8 | 1181 | int mlx4_get_phys_port_id(struct mlx4_dev *dev); |
14c07b13 YP |
1182 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
1183 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
1184 | ||
f2a3f6a3 OG |
1185 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
1186 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
1187 | ||
0ff1fb65 HHZ |
1188 | int mlx4_flow_attach(struct mlx4_dev *dev, |
1189 | struct mlx4_net_trans_rule *rule, u64 *reg_id); | |
1190 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); | |
c2c19dc3 HHZ |
1191 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, |
1192 | enum mlx4_net_trans_promisc_mode flow_type); | |
1193 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, | |
1194 | enum mlx4_net_trans_rule_id id); | |
1195 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); | |
0ff1fb65 | 1196 | |
54679e14 JM |
1197 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, |
1198 | int i, int val); | |
1199 | ||
396f2feb JM |
1200 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); |
1201 | ||
993c401e JM |
1202 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); |
1203 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1204 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1205 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); | |
1206 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); | |
1207 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); | |
1208 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); | |
1209 | ||
afa8fd1d JM |
1210 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
1211 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); | |
9cd59352 JM |
1212 | |
1213 | int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, | |
1214 | int *slave_id); | |
1215 | int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, | |
1216 | u8 *gid); | |
993c401e | 1217 | |
4de65803 MB |
1218 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, |
1219 | u32 max_range_qpn); | |
1220 | ||
ec693d47 AV |
1221 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); |
1222 | ||
f74462ac MB |
1223 | struct mlx4_active_ports { |
1224 | DECLARE_BITMAP(ports, MLX4_MAX_PORTS); | |
1225 | }; | |
1226 | /* Returns a bitmap of the physical ports which are assigned to slave */ | |
1227 | struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); | |
1228 | ||
1229 | /* Returns the physical port that represents the virtual port of the slave, */ | |
1230 | /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ | |
1231 | /* mapping is returned. */ | |
1232 | int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); | |
1233 | ||
1234 | struct mlx4_slaves_pport { | |
1235 | DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); | |
1236 | }; | |
1237 | /* Returns a bitmap of all slaves that are assigned to port. */ | |
1238 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, | |
1239 | int port); | |
1240 | ||
1241 | /* Returns a bitmap of all slaves that are assigned exactly to all the */ | |
1242 | /* the ports that are set in crit_ports. */ | |
1243 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( | |
1244 | struct mlx4_dev *dev, | |
1245 | const struct mlx4_active_ports *crit_ports); | |
1246 | ||
1247 | /* Returns the slave's virtual port that represents the physical port. */ | |
1248 | int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); | |
1249 | ||
449fc488 | 1250 | int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); |
d18f141a OG |
1251 | |
1252 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); | |
97982f5a | 1253 | int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); |
65fed8a8 JM |
1254 | int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); |
1255 | int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, | |
1256 | int enable); | |
2599d858 AV |
1257 | |
1258 | /* Returns true if running in low memory profile (kdump kernel) */ | |
1259 | static inline bool mlx4_low_memory_profile(void) | |
1260 | { | |
1261 | return reset_devices; | |
1262 | } | |
1263 | ||
225c7b1f | 1264 | #endif /* MLX4_DEVICE_H */ |